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1 | /* GNU/Linux on ARM native support. | |
2 | Copyright (C) 1999-2015 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
18 | ||
19 | #include "defs.h" | |
20 | #include "inferior.h" | |
21 | #include "gdbcore.h" | |
22 | #include "regcache.h" | |
23 | #include "target.h" | |
24 | #include "linux-nat.h" | |
25 | #include "target-descriptions.h" | |
26 | #include "auxv.h" | |
27 | #include "observer.h" | |
28 | #include "gdbthread.h" | |
29 | ||
30 | #include "arm-tdep.h" | |
31 | #include "arm-linux-tdep.h" | |
32 | #include "aarch32-linux-nat.h" | |
33 | ||
34 | #include <elf/common.h> | |
35 | #include <sys/user.h> | |
36 | #include "nat/gdb_ptrace.h" | |
37 | #include <sys/utsname.h> | |
38 | #include <sys/procfs.h> | |
39 | ||
40 | #include "nat/linux-ptrace.h" | |
41 | ||
42 | /* Prototypes for supply_gregset etc. */ | |
43 | #include "gregset.h" | |
44 | ||
45 | /* Defines ps_err_e, struct ps_prochandle. */ | |
46 | #include "gdb_proc_service.h" | |
47 | ||
48 | #ifndef PTRACE_GET_THREAD_AREA | |
49 | #define PTRACE_GET_THREAD_AREA 22 | |
50 | #endif | |
51 | ||
52 | #ifndef PTRACE_GETWMMXREGS | |
53 | #define PTRACE_GETWMMXREGS 18 | |
54 | #define PTRACE_SETWMMXREGS 19 | |
55 | #endif | |
56 | ||
57 | #ifndef PTRACE_GETVFPREGS | |
58 | #define PTRACE_GETVFPREGS 27 | |
59 | #define PTRACE_SETVFPREGS 28 | |
60 | #endif | |
61 | ||
62 | #ifndef PTRACE_GETHBPREGS | |
63 | #define PTRACE_GETHBPREGS 29 | |
64 | #define PTRACE_SETHBPREGS 30 | |
65 | #endif | |
66 | ||
67 | extern int arm_apcs_32; | |
68 | ||
69 | /* On GNU/Linux, threads are implemented as pseudo-processes, in which | |
70 | case we may be tracing more than one process at a time. In that | |
71 | case, inferior_ptid will contain the main process ID and the | |
72 | individual thread (process) ID. get_thread_id () is used to get | |
73 | the thread id if it's available, and the process id otherwise. */ | |
74 | ||
75 | static int | |
76 | get_thread_id (ptid_t ptid) | |
77 | { | |
78 | int tid = ptid_get_lwp (ptid); | |
79 | if (0 == tid) | |
80 | tid = ptid_get_pid (ptid); | |
81 | return tid; | |
82 | } | |
83 | ||
84 | #define GET_THREAD_ID(PTID) get_thread_id (PTID) | |
85 | ||
86 | /* Get the whole floating point state of the process and store it | |
87 | into regcache. */ | |
88 | ||
89 | static void | |
90 | fetch_fpregs (struct regcache *regcache) | |
91 | { | |
92 | int ret, regno, tid; | |
93 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; | |
94 | ||
95 | /* Get the thread id for the ptrace call. */ | |
96 | tid = GET_THREAD_ID (inferior_ptid); | |
97 | ||
98 | /* Read the floating point state. */ | |
99 | if (have_ptrace_getregset == TRIBOOL_TRUE) | |
100 | { | |
101 | struct iovec iov; | |
102 | ||
103 | iov.iov_base = &fp; | |
104 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
105 | ||
106 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
107 | } | |
108 | else | |
109 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
110 | ||
111 | if (ret < 0) | |
112 | { | |
113 | warning (_("Unable to fetch the floating point registers.")); | |
114 | return; | |
115 | } | |
116 | ||
117 | /* Fetch fpsr. */ | |
118 | regcache_raw_supply (regcache, ARM_FPS_REGNUM, | |
119 | fp + NWFPE_FPSR_OFFSET); | |
120 | ||
121 | /* Fetch the floating point registers. */ | |
122 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) | |
123 | supply_nwfpe_register (regcache, regno, fp); | |
124 | } | |
125 | ||
126 | /* Save the whole floating point state of the process using | |
127 | the contents from regcache. */ | |
128 | ||
129 | static void | |
130 | store_fpregs (const struct regcache *regcache) | |
131 | { | |
132 | int ret, regno, tid; | |
133 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; | |
134 | ||
135 | /* Get the thread id for the ptrace call. */ | |
136 | tid = GET_THREAD_ID (inferior_ptid); | |
137 | ||
138 | /* Read the floating point state. */ | |
139 | if (have_ptrace_getregset == TRIBOOL_TRUE) | |
140 | { | |
141 | elf_fpregset_t fpregs; | |
142 | struct iovec iov; | |
143 | ||
144 | iov.iov_base = &fpregs; | |
145 | iov.iov_len = sizeof (fpregs); | |
146 | ||
147 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
148 | } | |
149 | else | |
150 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
151 | ||
152 | if (ret < 0) | |
153 | { | |
154 | warning (_("Unable to fetch the floating point registers.")); | |
155 | return; | |
156 | } | |
157 | ||
158 | /* Store fpsr. */ | |
159 | if (REG_VALID == regcache_register_status (regcache, ARM_FPS_REGNUM)) | |
160 | regcache_raw_collect (regcache, ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); | |
161 | ||
162 | /* Store the floating point registers. */ | |
163 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) | |
164 | if (REG_VALID == regcache_register_status (regcache, regno)) | |
165 | collect_nwfpe_register (regcache, regno, fp); | |
166 | ||
167 | if (have_ptrace_getregset == TRIBOOL_TRUE) | |
168 | { | |
169 | struct iovec iov; | |
170 | ||
171 | iov.iov_base = &fp; | |
172 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
173 | ||
174 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov); | |
175 | } | |
176 | else | |
177 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); | |
178 | ||
179 | if (ret < 0) | |
180 | { | |
181 | warning (_("Unable to store floating point registers.")); | |
182 | return; | |
183 | } | |
184 | } | |
185 | ||
186 | /* Fetch all general registers of the process and store into | |
187 | regcache. */ | |
188 | ||
189 | static void | |
190 | fetch_regs (struct regcache *regcache) | |
191 | { | |
192 | int ret, regno, tid; | |
193 | elf_gregset_t regs; | |
194 | ||
195 | /* Get the thread id for the ptrace call. */ | |
196 | tid = GET_THREAD_ID (inferior_ptid); | |
197 | ||
198 | if (have_ptrace_getregset == TRIBOOL_TRUE) | |
199 | { | |
200 | struct iovec iov; | |
201 | ||
202 | iov.iov_base = ®s; | |
203 | iov.iov_len = sizeof (regs); | |
204 | ||
205 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
206 | } | |
207 | else | |
208 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
209 | ||
210 | if (ret < 0) | |
211 | { | |
212 | warning (_("Unable to fetch general registers.")); | |
213 | return; | |
214 | } | |
215 | ||
216 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, arm_apcs_32); | |
217 | } | |
218 | ||
219 | static void | |
220 | store_regs (const struct regcache *regcache) | |
221 | { | |
222 | int ret, regno, tid; | |
223 | elf_gregset_t regs; | |
224 | ||
225 | /* Get the thread id for the ptrace call. */ | |
226 | tid = GET_THREAD_ID (inferior_ptid); | |
227 | ||
228 | /* Fetch the general registers. */ | |
229 | if (have_ptrace_getregset == TRIBOOL_TRUE) | |
230 | { | |
231 | struct iovec iov; | |
232 | ||
233 | iov.iov_base = ®s; | |
234 | iov.iov_len = sizeof (regs); | |
235 | ||
236 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
237 | } | |
238 | else | |
239 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
240 | ||
241 | if (ret < 0) | |
242 | { | |
243 | warning (_("Unable to fetch general registers.")); | |
244 | return; | |
245 | } | |
246 | ||
247 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, arm_apcs_32); | |
248 | ||
249 | if (have_ptrace_getregset == TRIBOOL_TRUE) | |
250 | { | |
251 | struct iovec iov; | |
252 | ||
253 | iov.iov_base = ®s; | |
254 | iov.iov_len = sizeof (regs); | |
255 | ||
256 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); | |
257 | } | |
258 | else | |
259 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
260 | ||
261 | if (ret < 0) | |
262 | { | |
263 | warning (_("Unable to store general registers.")); | |
264 | return; | |
265 | } | |
266 | } | |
267 | ||
268 | /* Fetch all WMMX registers of the process and store into | |
269 | regcache. */ | |
270 | ||
271 | #define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4) | |
272 | ||
273 | static void | |
274 | fetch_wmmx_regs (struct regcache *regcache) | |
275 | { | |
276 | char regbuf[IWMMXT_REGS_SIZE]; | |
277 | int ret, regno, tid; | |
278 | ||
279 | /* Get the thread id for the ptrace call. */ | |
280 | tid = GET_THREAD_ID (inferior_ptid); | |
281 | ||
282 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
283 | if (ret < 0) | |
284 | { | |
285 | warning (_("Unable to fetch WMMX registers.")); | |
286 | return; | |
287 | } | |
288 | ||
289 | for (regno = 0; regno < 16; regno++) | |
290 | regcache_raw_supply (regcache, regno + ARM_WR0_REGNUM, | |
291 | ®buf[regno * 8]); | |
292 | ||
293 | for (regno = 0; regno < 2; regno++) | |
294 | regcache_raw_supply (regcache, regno + ARM_WCSSF_REGNUM, | |
295 | ®buf[16 * 8 + regno * 4]); | |
296 | ||
297 | for (regno = 0; regno < 4; regno++) | |
298 | regcache_raw_supply (regcache, regno + ARM_WCGR0_REGNUM, | |
299 | ®buf[16 * 8 + 2 * 4 + regno * 4]); | |
300 | } | |
301 | ||
302 | static void | |
303 | store_wmmx_regs (const struct regcache *regcache) | |
304 | { | |
305 | char regbuf[IWMMXT_REGS_SIZE]; | |
306 | int ret, regno, tid; | |
307 | ||
308 | /* Get the thread id for the ptrace call. */ | |
309 | tid = GET_THREAD_ID (inferior_ptid); | |
310 | ||
311 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
312 | if (ret < 0) | |
313 | { | |
314 | warning (_("Unable to fetch WMMX registers.")); | |
315 | return; | |
316 | } | |
317 | ||
318 | for (regno = 0; regno < 16; regno++) | |
319 | if (REG_VALID == regcache_register_status (regcache, | |
320 | regno + ARM_WR0_REGNUM)) | |
321 | regcache_raw_collect (regcache, regno + ARM_WR0_REGNUM, | |
322 | ®buf[regno * 8]); | |
323 | ||
324 | for (regno = 0; regno < 2; regno++) | |
325 | if (REG_VALID == regcache_register_status (regcache, | |
326 | regno + ARM_WCSSF_REGNUM)) | |
327 | regcache_raw_collect (regcache, regno + ARM_WCSSF_REGNUM, | |
328 | ®buf[16 * 8 + regno * 4]); | |
329 | ||
330 | for (regno = 0; regno < 4; regno++) | |
331 | if (REG_VALID == regcache_register_status (regcache, | |
332 | regno + ARM_WCGR0_REGNUM)) | |
333 | regcache_raw_collect (regcache, regno + ARM_WCGR0_REGNUM, | |
334 | ®buf[16 * 8 + 2 * 4 + regno * 4]); | |
335 | ||
336 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); | |
337 | ||
338 | if (ret < 0) | |
339 | { | |
340 | warning (_("Unable to store WMMX registers.")); | |
341 | return; | |
342 | } | |
343 | } | |
344 | ||
345 | static void | |
346 | fetch_vfp_regs (struct regcache *regcache) | |
347 | { | |
348 | gdb_byte regbuf[VFP_REGS_SIZE]; | |
349 | int ret, regno, tid; | |
350 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
351 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
352 | ||
353 | /* Get the thread id for the ptrace call. */ | |
354 | tid = GET_THREAD_ID (inferior_ptid); | |
355 | ||
356 | if (have_ptrace_getregset == TRIBOOL_TRUE) | |
357 | { | |
358 | struct iovec iov; | |
359 | ||
360 | iov.iov_base = regbuf; | |
361 | iov.iov_len = VFP_REGS_SIZE; | |
362 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); | |
363 | } | |
364 | else | |
365 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
366 | ||
367 | if (ret < 0) | |
368 | { | |
369 | warning (_("Unable to fetch VFP registers.")); | |
370 | return; | |
371 | } | |
372 | ||
373 | aarch32_vfp_regcache_supply (regcache, regbuf, | |
374 | tdep->vfp_register_count); | |
375 | } | |
376 | ||
377 | static void | |
378 | store_vfp_regs (const struct regcache *regcache) | |
379 | { | |
380 | gdb_byte regbuf[VFP_REGS_SIZE]; | |
381 | int ret, regno, tid; | |
382 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
383 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
384 | ||
385 | /* Get the thread id for the ptrace call. */ | |
386 | tid = GET_THREAD_ID (inferior_ptid); | |
387 | ||
388 | if (have_ptrace_getregset == TRIBOOL_TRUE) | |
389 | { | |
390 | struct iovec iov; | |
391 | ||
392 | iov.iov_base = regbuf; | |
393 | iov.iov_len = VFP_REGS_SIZE; | |
394 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); | |
395 | } | |
396 | else | |
397 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
398 | ||
399 | if (ret < 0) | |
400 | { | |
401 | warning (_("Unable to fetch VFP registers (for update).")); | |
402 | return; | |
403 | } | |
404 | ||
405 | aarch32_vfp_regcache_collect (regcache, regbuf, | |
406 | tdep->vfp_register_count); | |
407 | ||
408 | if (have_ptrace_getregset == TRIBOOL_TRUE) | |
409 | { | |
410 | struct iovec iov; | |
411 | ||
412 | iov.iov_base = regbuf; | |
413 | iov.iov_len = VFP_REGS_SIZE; | |
414 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov); | |
415 | } | |
416 | else | |
417 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); | |
418 | ||
419 | if (ret < 0) | |
420 | { | |
421 | warning (_("Unable to store VFP registers.")); | |
422 | return; | |
423 | } | |
424 | } | |
425 | ||
426 | /* Fetch registers from the child process. Fetch all registers if | |
427 | regno == -1, otherwise fetch all general registers or all floating | |
428 | point registers depending upon the value of regno. */ | |
429 | ||
430 | static void | |
431 | arm_linux_fetch_inferior_registers (struct target_ops *ops, | |
432 | struct regcache *regcache, int regno) | |
433 | { | |
434 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
435 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
436 | ||
437 | if (-1 == regno) | |
438 | { | |
439 | fetch_regs (regcache); | |
440 | fetch_fpregs (regcache); | |
441 | if (tdep->have_wmmx_registers) | |
442 | fetch_wmmx_regs (regcache); | |
443 | if (tdep->vfp_register_count > 0) | |
444 | fetch_vfp_regs (regcache); | |
445 | } | |
446 | else | |
447 | { | |
448 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) | |
449 | fetch_regs (regcache); | |
450 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) | |
451 | fetch_fpregs (regcache); | |
452 | else if (tdep->have_wmmx_registers | |
453 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) | |
454 | fetch_wmmx_regs (regcache); | |
455 | else if (tdep->vfp_register_count > 0 | |
456 | && regno >= ARM_D0_REGNUM | |
457 | && regno <= ARM_D0_REGNUM + tdep->vfp_register_count) | |
458 | fetch_vfp_regs (regcache); | |
459 | } | |
460 | } | |
461 | ||
462 | /* Store registers back into the inferior. Store all registers if | |
463 | regno == -1, otherwise store all general registers or all floating | |
464 | point registers depending upon the value of regno. */ | |
465 | ||
466 | static void | |
467 | arm_linux_store_inferior_registers (struct target_ops *ops, | |
468 | struct regcache *regcache, int regno) | |
469 | { | |
470 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
471 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
472 | ||
473 | if (-1 == regno) | |
474 | { | |
475 | store_regs (regcache); | |
476 | store_fpregs (regcache); | |
477 | if (tdep->have_wmmx_registers) | |
478 | store_wmmx_regs (regcache); | |
479 | if (tdep->vfp_register_count > 0) | |
480 | store_vfp_regs (regcache); | |
481 | } | |
482 | else | |
483 | { | |
484 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) | |
485 | store_regs (regcache); | |
486 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) | |
487 | store_fpregs (regcache); | |
488 | else if (tdep->have_wmmx_registers | |
489 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) | |
490 | store_wmmx_regs (regcache); | |
491 | else if (tdep->vfp_register_count > 0 | |
492 | && regno >= ARM_D0_REGNUM | |
493 | && regno <= ARM_D0_REGNUM + tdep->vfp_register_count) | |
494 | store_vfp_regs (regcache); | |
495 | } | |
496 | } | |
497 | ||
498 | /* Wrapper functions for the standard regset handling, used by | |
499 | thread debugging. */ | |
500 | ||
501 | void | |
502 | fill_gregset (const struct regcache *regcache, | |
503 | gdb_gregset_t *gregsetp, int regno) | |
504 | { | |
505 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); | |
506 | } | |
507 | ||
508 | void | |
509 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) | |
510 | { | |
511 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); | |
512 | } | |
513 | ||
514 | void | |
515 | fill_fpregset (const struct regcache *regcache, | |
516 | gdb_fpregset_t *fpregsetp, int regno) | |
517 | { | |
518 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); | |
519 | } | |
520 | ||
521 | /* Fill GDB's register array with the floating-point register values | |
522 | in *fpregsetp. */ | |
523 | ||
524 | void | |
525 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) | |
526 | { | |
527 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); | |
528 | } | |
529 | ||
530 | /* Fetch the thread-local storage pointer for libthread_db. */ | |
531 | ||
532 | ps_err_e | |
533 | ps_get_thread_area (const struct ps_prochandle *ph, | |
534 | lwpid_t lwpid, int idx, void **base) | |
535 | { | |
536 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
537 | return PS_ERR; | |
538 | ||
539 | /* IDX is the bias from the thread pointer to the beginning of the | |
540 | thread descriptor. It has to be subtracted due to implementation | |
541 | quirks in libthread_db. */ | |
542 | *base = (void *) ((char *)*base - idx); | |
543 | ||
544 | return PS_OK; | |
545 | } | |
546 | ||
547 | static const struct target_desc * | |
548 | arm_linux_read_description (struct target_ops *ops) | |
549 | { | |
550 | CORE_ADDR arm_hwcap = 0; | |
551 | ||
552 | if (have_ptrace_getregset == TRIBOOL_UNKNOWN) | |
553 | { | |
554 | elf_gregset_t gpregs; | |
555 | struct iovec iov; | |
556 | int tid = GET_THREAD_ID (inferior_ptid); | |
557 | ||
558 | iov.iov_base = &gpregs; | |
559 | iov.iov_len = sizeof (gpregs); | |
560 | ||
561 | /* Check if PTRACE_GETREGSET works. */ | |
562 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) < 0) | |
563 | have_ptrace_getregset = TRIBOOL_FALSE; | |
564 | else | |
565 | have_ptrace_getregset = TRIBOOL_TRUE; | |
566 | } | |
567 | ||
568 | if (target_auxv_search (ops, AT_HWCAP, &arm_hwcap) != 1) | |
569 | { | |
570 | return ops->beneath->to_read_description (ops->beneath); | |
571 | } | |
572 | ||
573 | if (arm_hwcap & HWCAP_IWMMXT) | |
574 | return tdesc_arm_with_iwmmxt; | |
575 | ||
576 | if (arm_hwcap & HWCAP_VFP) | |
577 | { | |
578 | int pid; | |
579 | char *buf; | |
580 | const struct target_desc * result = NULL; | |
581 | ||
582 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support | |
583 | Neon with VFPv3-D32. */ | |
584 | if (arm_hwcap & HWCAP_NEON) | |
585 | result = tdesc_arm_with_neon; | |
586 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) | |
587 | result = tdesc_arm_with_vfpv3; | |
588 | else | |
589 | result = tdesc_arm_with_vfpv2; | |
590 | ||
591 | /* Now make sure that the kernel supports reading these | |
592 | registers. Support was added in 2.6.30. */ | |
593 | pid = ptid_get_lwp (inferior_ptid); | |
594 | errno = 0; | |
595 | buf = alloca (VFP_REGS_SIZE); | |
596 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 | |
597 | && errno == EIO) | |
598 | result = NULL; | |
599 | ||
600 | return result; | |
601 | } | |
602 | ||
603 | return ops->beneath->to_read_description (ops->beneath); | |
604 | } | |
605 | ||
606 | /* Information describing the hardware breakpoint capabilities. */ | |
607 | struct arm_linux_hwbp_cap | |
608 | { | |
609 | gdb_byte arch; | |
610 | gdb_byte max_wp_length; | |
611 | gdb_byte wp_count; | |
612 | gdb_byte bp_count; | |
613 | }; | |
614 | ||
615 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, | |
616 | assume a maximum number of supported break-/watchpoints. */ | |
617 | #define MAX_BPTS 16 | |
618 | #define MAX_WPTS 16 | |
619 | ||
620 | /* Get hold of the Hardware Breakpoint information for the target we are | |
621 | attached to. Returns NULL if the kernel doesn't support Hardware | |
622 | breakpoints at all, or a pointer to the information structure. */ | |
623 | static const struct arm_linux_hwbp_cap * | |
624 | arm_linux_get_hwbp_cap (void) | |
625 | { | |
626 | /* The info structure we return. */ | |
627 | static struct arm_linux_hwbp_cap info; | |
628 | ||
629 | /* Is INFO in a good state? -1 means that no attempt has been made to | |
630 | initialize INFO; 0 means an attempt has been made, but it failed; 1 | |
631 | means INFO is in an initialized state. */ | |
632 | static int available = -1; | |
633 | ||
634 | if (available == -1) | |
635 | { | |
636 | int tid; | |
637 | unsigned int val; | |
638 | ||
639 | tid = GET_THREAD_ID (inferior_ptid); | |
640 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) | |
641 | available = 0; | |
642 | else | |
643 | { | |
644 | info.arch = (gdb_byte)((val >> 24) & 0xff); | |
645 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); | |
646 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); | |
647 | info.bp_count = (gdb_byte)(val & 0xff); | |
648 | ||
649 | if (info.wp_count > MAX_WPTS) | |
650 | { | |
651 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ | |
652 | supports %d"), MAX_WPTS, info.wp_count); | |
653 | info.wp_count = MAX_WPTS; | |
654 | } | |
655 | ||
656 | if (info.bp_count > MAX_BPTS) | |
657 | { | |
658 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ | |
659 | supports %d"), MAX_BPTS, info.bp_count); | |
660 | info.bp_count = MAX_BPTS; | |
661 | } | |
662 | available = (info.arch != 0); | |
663 | } | |
664 | } | |
665 | ||
666 | return available == 1 ? &info : NULL; | |
667 | } | |
668 | ||
669 | /* How many hardware breakpoints are available? */ | |
670 | static int | |
671 | arm_linux_get_hw_breakpoint_count (void) | |
672 | { | |
673 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
674 | return cap != NULL ? cap->bp_count : 0; | |
675 | } | |
676 | ||
677 | /* How many hardware watchpoints are available? */ | |
678 | static int | |
679 | arm_linux_get_hw_watchpoint_count (void) | |
680 | { | |
681 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
682 | return cap != NULL ? cap->wp_count : 0; | |
683 | } | |
684 | ||
685 | /* Have we got a free break-/watch-point available for use? Returns -1 if | |
686 | there is not an appropriate resource available, otherwise returns 1. */ | |
687 | static int | |
688 | arm_linux_can_use_hw_breakpoint (struct target_ops *self, | |
689 | enum bptype type, | |
690 | int cnt, int ot) | |
691 | { | |
692 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint | |
693 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
694 | { | |
695 | int count = arm_linux_get_hw_watchpoint_count (); | |
696 | ||
697 | if (count == 0) | |
698 | return 0; | |
699 | else if (cnt + ot > count) | |
700 | return -1; | |
701 | } | |
702 | else if (type == bp_hardware_breakpoint) | |
703 | { | |
704 | int count = arm_linux_get_hw_breakpoint_count (); | |
705 | ||
706 | if (count == 0) | |
707 | return 0; | |
708 | else if (cnt > count) | |
709 | return -1; | |
710 | } | |
711 | else | |
712 | gdb_assert (FALSE); | |
713 | ||
714 | return 1; | |
715 | } | |
716 | ||
717 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
718 | typedef enum | |
719 | { | |
720 | arm_hwbp_break = 0, | |
721 | arm_hwbp_load = 1, | |
722 | arm_hwbp_store = 2, | |
723 | arm_hwbp_access = 3 | |
724 | } arm_hwbp_type; | |
725 | ||
726 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
727 | typedef unsigned int arm_hwbp_control_t; | |
728 | ||
729 | /* Structure used to keep track of hardware break-/watch-points. */ | |
730 | struct arm_linux_hw_breakpoint | |
731 | { | |
732 | /* Address to break on, or being watched. */ | |
733 | unsigned int address; | |
734 | /* Control register for break-/watch- point. */ | |
735 | arm_hwbp_control_t control; | |
736 | }; | |
737 | ||
738 | /* Structure containing arrays of per process hardware break-/watchpoints | |
739 | for caching address and control information. | |
740 | ||
741 | The Linux ptrace interface to hardware break-/watch-points presents the | |
742 | values in a vector centred around 0 (which is used fo generic information). | |
743 | Positive indicies refer to breakpoint addresses/control registers, negative | |
744 | indices to watchpoint addresses/control registers. | |
745 | ||
746 | The Linux vector is indexed as follows: | |
747 | -((i << 1) + 2): Control register for watchpoint i. | |
748 | -((i << 1) + 1): Address register for watchpoint i. | |
749 | 0: Information register. | |
750 | ((i << 1) + 1): Address register for breakpoint i. | |
751 | ((i << 1) + 2): Control register for breakpoint i. | |
752 | ||
753 | This structure is used as a per-thread cache of the state stored by the | |
754 | kernel, so that we don't need to keep calling into the kernel to find a | |
755 | free breakpoint. | |
756 | ||
757 | We treat break-/watch-points with their enable bit clear as being deleted. | |
758 | */ | |
759 | struct arm_linux_debug_reg_state | |
760 | { | |
761 | /* Hardware breakpoints for this process. */ | |
762 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
763 | /* Hardware watchpoints for this process. */ | |
764 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
765 | }; | |
766 | ||
767 | /* Per-process arch-specific data we want to keep. */ | |
768 | struct arm_linux_process_info | |
769 | { | |
770 | /* Linked list. */ | |
771 | struct arm_linux_process_info *next; | |
772 | /* The process identifier. */ | |
773 | pid_t pid; | |
774 | /* Hardware break-/watchpoints state information. */ | |
775 | struct arm_linux_debug_reg_state state; | |
776 | ||
777 | }; | |
778 | ||
779 | /* Per-thread arch-specific data we want to keep. */ | |
780 | struct arch_lwp_info | |
781 | { | |
782 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
783 | char bpts_changed[MAX_BPTS]; | |
784 | char wpts_changed[MAX_WPTS]; | |
785 | }; | |
786 | ||
787 | static struct arm_linux_process_info *arm_linux_process_list = NULL; | |
788 | ||
789 | /* Find process data for process PID. */ | |
790 | ||
791 | static struct arm_linux_process_info * | |
792 | arm_linux_find_process_pid (pid_t pid) | |
793 | { | |
794 | struct arm_linux_process_info *proc; | |
795 | ||
796 | for (proc = arm_linux_process_list; proc; proc = proc->next) | |
797 | if (proc->pid == pid) | |
798 | return proc; | |
799 | ||
800 | return NULL; | |
801 | } | |
802 | ||
803 | /* Add process data for process PID. Returns newly allocated info | |
804 | object. */ | |
805 | ||
806 | static struct arm_linux_process_info * | |
807 | arm_linux_add_process (pid_t pid) | |
808 | { | |
809 | struct arm_linux_process_info *proc; | |
810 | ||
811 | proc = xcalloc (1, sizeof (*proc)); | |
812 | proc->pid = pid; | |
813 | ||
814 | proc->next = arm_linux_process_list; | |
815 | arm_linux_process_list = proc; | |
816 | ||
817 | return proc; | |
818 | } | |
819 | ||
820 | /* Get data specific info for process PID, creating it if necessary. | |
821 | Never returns NULL. */ | |
822 | ||
823 | static struct arm_linux_process_info * | |
824 | arm_linux_process_info_get (pid_t pid) | |
825 | { | |
826 | struct arm_linux_process_info *proc; | |
827 | ||
828 | proc = arm_linux_find_process_pid (pid); | |
829 | if (proc == NULL) | |
830 | proc = arm_linux_add_process (pid); | |
831 | ||
832 | return proc; | |
833 | } | |
834 | ||
835 | /* Called whenever GDB is no longer debugging process PID. It deletes | |
836 | data structures that keep track of debug register state. */ | |
837 | ||
838 | static void | |
839 | arm_linux_forget_process (pid_t pid) | |
840 | { | |
841 | struct arm_linux_process_info *proc, **proc_link; | |
842 | ||
843 | proc = arm_linux_process_list; | |
844 | proc_link = &arm_linux_process_list; | |
845 | ||
846 | while (proc != NULL) | |
847 | { | |
848 | if (proc->pid == pid) | |
849 | { | |
850 | *proc_link = proc->next; | |
851 | ||
852 | xfree (proc); | |
853 | return; | |
854 | } | |
855 | ||
856 | proc_link = &proc->next; | |
857 | proc = *proc_link; | |
858 | } | |
859 | } | |
860 | ||
861 | /* Get hardware break-/watchpoint state for process PID. */ | |
862 | ||
863 | static struct arm_linux_debug_reg_state * | |
864 | arm_linux_get_debug_reg_state (pid_t pid) | |
865 | { | |
866 | return &arm_linux_process_info_get (pid)->state; | |
867 | } | |
868 | ||
869 | /* Initialize an ARM hardware break-/watch-point control register value. | |
870 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
871 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
872 | */ | |
873 | static arm_hwbp_control_t | |
874 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
875 | arm_hwbp_type hwbp_type, | |
876 | int enable) | |
877 | { | |
878 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
879 | gdb_assert (hwbp_type != arm_hwbp_break | |
880 | || ((byte_address_select & 0xfU) != 0)); | |
881 | ||
882 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
883 | } | |
884 | ||
885 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
886 | static int | |
887 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
888 | { | |
889 | return control & 0x1; | |
890 | } | |
891 | ||
892 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
893 | static arm_hwbp_control_t | |
894 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
895 | { | |
896 | return control & ~0x1; | |
897 | } | |
898 | ||
899 | /* Initialise the hardware breakpoint structure P. The breakpoint will be | |
900 | enabled, and will point to the placed address of BP_TGT. */ | |
901 | static void | |
902 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, | |
903 | struct bp_target_info *bp_tgt, | |
904 | struct arm_linux_hw_breakpoint *p) | |
905 | { | |
906 | unsigned mask; | |
907 | CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address; | |
908 | ||
909 | /* We have to create a mask for the control register which says which bits | |
910 | of the word pointed to by address to break on. */ | |
911 | if (arm_pc_is_thumb (gdbarch, address)) | |
912 | { | |
913 | mask = 0x3; | |
914 | address &= ~1; | |
915 | } | |
916 | else | |
917 | { | |
918 | mask = 0xf; | |
919 | address &= ~3; | |
920 | } | |
921 | ||
922 | p->address = (unsigned int) address; | |
923 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); | |
924 | } | |
925 | ||
926 | /* Get the ARM hardware breakpoint type from the type value we're | |
927 | given when asked to set a watchpoint. */ | |
928 | static arm_hwbp_type | |
929 | arm_linux_get_hwbp_type (enum target_hw_bp_type type) | |
930 | { | |
931 | if (rw == hw_read) | |
932 | return arm_hwbp_load; | |
933 | else if (rw == hw_write) | |
934 | return arm_hwbp_store; | |
935 | else | |
936 | return arm_hwbp_access; | |
937 | } | |
938 | ||
939 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR | |
940 | to LEN. The type of watchpoint is given in RW. */ | |
941 | static void | |
942 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, | |
943 | enum target_hw_bp_type type, | |
944 | struct arm_linux_hw_breakpoint *p) | |
945 | { | |
946 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
947 | unsigned mask; | |
948 | ||
949 | gdb_assert (cap != NULL); | |
950 | gdb_assert (cap->max_wp_length != 0); | |
951 | ||
952 | mask = (1 << len) - 1; | |
953 | ||
954 | p->address = (unsigned int) addr; | |
955 | p->control = arm_hwbp_control_initialize (mask, | |
956 | arm_linux_get_hwbp_type (type), 1); | |
957 | } | |
958 | ||
959 | /* Are two break-/watch-points equal? */ | |
960 | static int | |
961 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
962 | const struct arm_linux_hw_breakpoint *p2) | |
963 | { | |
964 | return p1->address == p2->address && p1->control == p2->control; | |
965 | } | |
966 | ||
967 | /* Callback to mark a watch-/breakpoint to be updated in all threads of | |
968 | the current process. */ | |
969 | ||
970 | struct update_registers_data | |
971 | { | |
972 | int watch; | |
973 | int index; | |
974 | }; | |
975 | ||
976 | static int | |
977 | update_registers_callback (struct lwp_info *lwp, void *arg) | |
978 | { | |
979 | struct update_registers_data *data = (struct update_registers_data *) arg; | |
980 | ||
981 | if (lwp->arch_private == NULL) | |
982 | lwp->arch_private = XCNEW (struct arch_lwp_info); | |
983 | ||
984 | /* The actual update is done later just before resuming the lwp, | |
985 | we just mark that the registers need updating. */ | |
986 | if (data->watch) | |
987 | lwp->arch_private->wpts_changed[data->index] = 1; | |
988 | else | |
989 | lwp->arch_private->bpts_changed[data->index] = 1; | |
990 | ||
991 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
992 | we can update its breakpoint registers. */ | |
993 | if (!lwp->stopped) | |
994 | linux_stop_lwp (lwp); | |
995 | ||
996 | return 0; | |
997 | } | |
998 | ||
999 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT | |
1000 | =1) BPT for thread TID. */ | |
1001 | static void | |
1002 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, | |
1003 | int watchpoint) | |
1004 | { | |
1005 | int pid; | |
1006 | ptid_t pid_ptid; | |
1007 | gdb_byte count, i; | |
1008 | struct arm_linux_hw_breakpoint* bpts; | |
1009 | struct update_registers_data data; | |
1010 | ||
1011 | pid = ptid_get_pid (inferior_ptid); | |
1012 | pid_ptid = pid_to_ptid (pid); | |
1013 | ||
1014 | if (watchpoint) | |
1015 | { | |
1016 | count = arm_linux_get_hw_watchpoint_count (); | |
1017 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; | |
1018 | } | |
1019 | else | |
1020 | { | |
1021 | count = arm_linux_get_hw_breakpoint_count (); | |
1022 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; | |
1023 | } | |
1024 | ||
1025 | for (i = 0; i < count; ++i) | |
1026 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) | |
1027 | { | |
1028 | data.watch = watchpoint; | |
1029 | data.index = i; | |
1030 | bpts[i] = *bpt; | |
1031 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1032 | break; | |
1033 | } | |
1034 | ||
1035 | gdb_assert (i != count); | |
1036 | } | |
1037 | ||
1038 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint | |
1039 | (WATCHPOINT = 1) BPT for thread TID. */ | |
1040 | static void | |
1041 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, | |
1042 | int watchpoint) | |
1043 | { | |
1044 | int pid; | |
1045 | gdb_byte count, i; | |
1046 | ptid_t pid_ptid; | |
1047 | struct arm_linux_hw_breakpoint* bpts; | |
1048 | struct update_registers_data data; | |
1049 | ||
1050 | pid = ptid_get_pid (inferior_ptid); | |
1051 | pid_ptid = pid_to_ptid (pid); | |
1052 | ||
1053 | if (watchpoint) | |
1054 | { | |
1055 | count = arm_linux_get_hw_watchpoint_count (); | |
1056 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; | |
1057 | } | |
1058 | else | |
1059 | { | |
1060 | count = arm_linux_get_hw_breakpoint_count (); | |
1061 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; | |
1062 | } | |
1063 | ||
1064 | for (i = 0; i < count; ++i) | |
1065 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) | |
1066 | { | |
1067 | data.watch = watchpoint; | |
1068 | data.index = i; | |
1069 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); | |
1070 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1071 | break; | |
1072 | } | |
1073 | ||
1074 | gdb_assert (i != count); | |
1075 | } | |
1076 | ||
1077 | /* Insert a Hardware breakpoint. */ | |
1078 | static int | |
1079 | arm_linux_insert_hw_breakpoint (struct target_ops *self, | |
1080 | struct gdbarch *gdbarch, | |
1081 | struct bp_target_info *bp_tgt) | |
1082 | { | |
1083 | struct lwp_info *lp; | |
1084 | struct arm_linux_hw_breakpoint p; | |
1085 | ||
1086 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1087 | return -1; | |
1088 | ||
1089 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
1090 | ||
1091 | arm_linux_insert_hw_breakpoint1 (&p, 0); | |
1092 | ||
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | /* Remove a hardware breakpoint. */ | |
1097 | static int | |
1098 | arm_linux_remove_hw_breakpoint (struct target_ops *self, | |
1099 | struct gdbarch *gdbarch, | |
1100 | struct bp_target_info *bp_tgt) | |
1101 | { | |
1102 | struct lwp_info *lp; | |
1103 | struct arm_linux_hw_breakpoint p; | |
1104 | ||
1105 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1106 | return -1; | |
1107 | ||
1108 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
1109 | ||
1110 | arm_linux_remove_hw_breakpoint1 (&p, 0); | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at | |
1116 | ADDR? */ | |
1117 | static int | |
1118 | arm_linux_region_ok_for_hw_watchpoint (struct target_ops *self, | |
1119 | CORE_ADDR addr, int len) | |
1120 | { | |
1121 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1122 | CORE_ADDR max_wp_length, aligned_addr; | |
1123 | ||
1124 | /* Can not set watchpoints for zero or negative lengths. */ | |
1125 | if (len <= 0) | |
1126 | return 0; | |
1127 | ||
1128 | /* Need to be able to use the ptrace interface. */ | |
1129 | if (cap == NULL || cap->wp_count == 0) | |
1130 | return 0; | |
1131 | ||
1132 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
1133 | range covered by a watchpoint. */ | |
1134 | max_wp_length = (CORE_ADDR)cap->max_wp_length; | |
1135 | aligned_addr = addr & ~(max_wp_length - 1); | |
1136 | ||
1137 | if (aligned_addr + max_wp_length < addr + len) | |
1138 | return 0; | |
1139 | ||
1140 | /* The current ptrace interface can only handle watchpoints that are a | |
1141 | power of 2. */ | |
1142 | if ((len & (len - 1)) != 0) | |
1143 | return 0; | |
1144 | ||
1145 | /* All tests passed so we must be able to set a watchpoint. */ | |
1146 | return 1; | |
1147 | } | |
1148 | ||
1149 | /* Insert a Hardware breakpoint. */ | |
1150 | static int | |
1151 | arm_linux_insert_watchpoint (struct target_ops *self, | |
1152 | CORE_ADDR addr, int len, | |
1153 | enum target_hw_bp_type rw, | |
1154 | struct expression *cond) | |
1155 | { | |
1156 | struct lwp_info *lp; | |
1157 | struct arm_linux_hw_breakpoint p; | |
1158 | ||
1159 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1160 | return -1; | |
1161 | ||
1162 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
1163 | ||
1164 | arm_linux_insert_hw_breakpoint1 (&p, 1); | |
1165 | ||
1166 | return 0; | |
1167 | } | |
1168 | ||
1169 | /* Remove a hardware breakpoint. */ | |
1170 | static int | |
1171 | arm_linux_remove_watchpoint (struct target_ops *self, | |
1172 | CORE_ADDR addr, int len, int rw, | |
1173 | struct expression *cond) | |
1174 | { | |
1175 | struct lwp_info *lp; | |
1176 | struct arm_linux_hw_breakpoint p; | |
1177 | ||
1178 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1179 | return -1; | |
1180 | ||
1181 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
1182 | ||
1183 | arm_linux_remove_hw_breakpoint1 (&p, 1); | |
1184 | ||
1185 | return 0; | |
1186 | } | |
1187 | ||
1188 | /* What was the data address the target was stopped on accessing. */ | |
1189 | static int | |
1190 | arm_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) | |
1191 | { | |
1192 | siginfo_t siginfo; | |
1193 | int slot; | |
1194 | ||
1195 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
1196 | return 0; | |
1197 | ||
1198 | /* This must be a hardware breakpoint. */ | |
1199 | if (siginfo.si_signo != SIGTRAP | |
1200 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
1201 | return 0; | |
1202 | ||
1203 | /* We must be able to set hardware watchpoints. */ | |
1204 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1205 | return 0; | |
1206 | ||
1207 | slot = siginfo.si_errno; | |
1208 | ||
1209 | /* If we are in a positive slot then we're looking at a breakpoint and not | |
1210 | a watchpoint. */ | |
1211 | if (slot >= 0) | |
1212 | return 0; | |
1213 | ||
1214 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; | |
1215 | return 1; | |
1216 | } | |
1217 | ||
1218 | /* Has the target been stopped by hitting a watchpoint? */ | |
1219 | static int | |
1220 | arm_linux_stopped_by_watchpoint (struct target_ops *ops) | |
1221 | { | |
1222 | CORE_ADDR addr; | |
1223 | return arm_linux_stopped_data_address (ops, &addr); | |
1224 | } | |
1225 | ||
1226 | static int | |
1227 | arm_linux_watchpoint_addr_within_range (struct target_ops *target, | |
1228 | CORE_ADDR addr, | |
1229 | CORE_ADDR start, int length) | |
1230 | { | |
1231 | return start <= addr && start + length - 1 >= addr; | |
1232 | } | |
1233 | ||
1234 | /* Handle thread creation. We need to copy the breakpoints and watchpoints | |
1235 | in the parent thread to the child thread. */ | |
1236 | static void | |
1237 | arm_linux_new_thread (struct lwp_info *lp) | |
1238 | { | |
1239 | int i; | |
1240 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
1241 | ||
1242 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1243 | for this thread need to be initialized. */ | |
1244 | ||
1245 | for (i = 0; i < MAX_BPTS; i++) | |
1246 | { | |
1247 | info->bpts_changed[i] = 1; | |
1248 | info->wpts_changed[i] = 1; | |
1249 | } | |
1250 | ||
1251 | lp->arch_private = info; | |
1252 | } | |
1253 | ||
1254 | /* Called when resuming a thread. | |
1255 | The hardware debug registers are updated when there is any change. */ | |
1256 | ||
1257 | static void | |
1258 | arm_linux_prepare_to_resume (struct lwp_info *lwp) | |
1259 | { | |
1260 | int pid, i; | |
1261 | struct arm_linux_hw_breakpoint *bpts, *wpts; | |
1262 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; | |
1263 | ||
1264 | pid = ptid_get_lwp (lwp->ptid); | |
1265 | bpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->bpts; | |
1266 | wpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->wpts; | |
1267 | ||
1268 | /* NULL means this is the main thread still going through the shell, | |
1269 | or, no watchpoint has been set yet. In that case, there's | |
1270 | nothing to do. */ | |
1271 | if (arm_lwp_info == NULL) | |
1272 | return; | |
1273 | ||
1274 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) | |
1275 | if (arm_lwp_info->bpts_changed[i]) | |
1276 | { | |
1277 | errno = 0; | |
1278 | if (arm_hwbp_control_is_enabled (bpts[i].control)) | |
1279 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1280 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) | |
1281 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1282 | ||
1283 | if (bpts[i].control != 0) | |
1284 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1285 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) | |
1286 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1287 | ||
1288 | arm_lwp_info->bpts_changed[i] = 0; | |
1289 | } | |
1290 | ||
1291 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) | |
1292 | if (arm_lwp_info->wpts_changed[i]) | |
1293 | { | |
1294 | errno = 0; | |
1295 | if (arm_hwbp_control_is_enabled (wpts[i].control)) | |
1296 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1297 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) | |
1298 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1299 | ||
1300 | if (wpts[i].control != 0) | |
1301 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1302 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) | |
1303 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1304 | ||
1305 | arm_lwp_info->wpts_changed[i] = 0; | |
1306 | } | |
1307 | } | |
1308 | ||
1309 | /* linux_nat_new_fork hook. */ | |
1310 | ||
1311 | static void | |
1312 | arm_linux_new_fork (struct lwp_info *parent, pid_t child_pid) | |
1313 | { | |
1314 | pid_t parent_pid; | |
1315 | struct arm_linux_debug_reg_state *parent_state; | |
1316 | struct arm_linux_debug_reg_state *child_state; | |
1317 | ||
1318 | /* NULL means no watchpoint has ever been set in the parent. In | |
1319 | that case, there's nothing to do. */ | |
1320 | if (parent->arch_private == NULL) | |
1321 | return; | |
1322 | ||
1323 | /* GDB core assumes the child inherits the watchpoints/hw | |
1324 | breakpoints of the parent, and will remove them all from the | |
1325 | forked off process. Copy the debug registers mirrors into the | |
1326 | new process so that all breakpoints and watchpoints can be | |
1327 | removed together. */ | |
1328 | ||
1329 | parent_pid = ptid_get_pid (parent->ptid); | |
1330 | parent_state = arm_linux_get_debug_reg_state (parent_pid); | |
1331 | child_state = arm_linux_get_debug_reg_state (child_pid); | |
1332 | *child_state = *parent_state; | |
1333 | } | |
1334 | ||
1335 | void _initialize_arm_linux_nat (void); | |
1336 | ||
1337 | void | |
1338 | _initialize_arm_linux_nat (void) | |
1339 | { | |
1340 | struct target_ops *t; | |
1341 | ||
1342 | /* Fill in the generic GNU/Linux methods. */ | |
1343 | t = linux_target (); | |
1344 | ||
1345 | /* Add our register access methods. */ | |
1346 | t->to_fetch_registers = arm_linux_fetch_inferior_registers; | |
1347 | t->to_store_registers = arm_linux_store_inferior_registers; | |
1348 | ||
1349 | /* Add our hardware breakpoint and watchpoint implementation. */ | |
1350 | t->to_can_use_hw_breakpoint = arm_linux_can_use_hw_breakpoint; | |
1351 | t->to_insert_hw_breakpoint = arm_linux_insert_hw_breakpoint; | |
1352 | t->to_remove_hw_breakpoint = arm_linux_remove_hw_breakpoint; | |
1353 | t->to_region_ok_for_hw_watchpoint = arm_linux_region_ok_for_hw_watchpoint; | |
1354 | t->to_insert_watchpoint = arm_linux_insert_watchpoint; | |
1355 | t->to_remove_watchpoint = arm_linux_remove_watchpoint; | |
1356 | t->to_stopped_by_watchpoint = arm_linux_stopped_by_watchpoint; | |
1357 | t->to_stopped_data_address = arm_linux_stopped_data_address; | |
1358 | t->to_watchpoint_addr_within_range = arm_linux_watchpoint_addr_within_range; | |
1359 | ||
1360 | t->to_read_description = arm_linux_read_description; | |
1361 | ||
1362 | /* Register the target. */ | |
1363 | linux_nat_add_target (t); | |
1364 | ||
1365 | /* Handle thread creation and exit. */ | |
1366 | linux_nat_set_new_thread (t, arm_linux_new_thread); | |
1367 | linux_nat_set_prepare_to_resume (t, arm_linux_prepare_to_resume); | |
1368 | ||
1369 | /* Handle process creation and exit. */ | |
1370 | linux_nat_set_new_fork (t, arm_linux_new_fork); | |
1371 | linux_nat_set_forget_process (t, arm_linux_forget_process); | |
1372 | } |