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1 | /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger. | |
2 | ||
3 | Copyright (C) 2002-2019 Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "inferior.h" | |
22 | #include "gdbcore.h" | |
23 | #include "arch-utils.h" | |
24 | #include "regcache.h" | |
25 | #include "frame.h" | |
26 | #include "frame-unwind.h" | |
27 | #include "frame-base.h" | |
28 | #include "trad-frame.h" | |
29 | #include "dis-asm.h" | |
30 | #include "sim-regno.h" | |
31 | #include "gdb/sim-frv.h" | |
32 | #include "../opcodes/frv-desc.h" /* for the H_SPR_... enums */ | |
33 | #include "symtab.h" | |
34 | #include "elf-bfd.h" | |
35 | #include "elf/frv.h" | |
36 | #include "osabi.h" | |
37 | #include "infcall.h" | |
38 | #include "solib.h" | |
39 | #include "frv-tdep.h" | |
40 | #include "objfiles.h" | |
41 | ||
42 | struct frv_unwind_cache /* was struct frame_extra_info */ | |
43 | { | |
44 | /* The previous frame's inner-most stack address. Used as this | |
45 | frame ID's stack_addr. */ | |
46 | CORE_ADDR prev_sp; | |
47 | ||
48 | /* The frame's base, optionally used by the high-level debug info. */ | |
49 | CORE_ADDR base; | |
50 | ||
51 | /* Table indicating the location of each and every register. */ | |
52 | struct trad_frame_saved_reg *saved_regs; | |
53 | }; | |
54 | ||
55 | /* A structure describing a particular variant of the FRV. | |
56 | We allocate and initialize one of these structures when we create | |
57 | the gdbarch object for a variant. | |
58 | ||
59 | At the moment, all the FR variants we support differ only in which | |
60 | registers are present; the portable code of GDB knows that | |
61 | registers whose names are the empty string don't exist, so the | |
62 | `register_names' array captures all the per-variant information we | |
63 | need. | |
64 | ||
65 | in the future, if we need to have per-variant maps for raw size, | |
66 | virtual type, etc., we should replace register_names with an array | |
67 | of structures, each of which gives all the necessary info for one | |
68 | register. Don't stick parallel arrays in here --- that's so | |
69 | Fortran. */ | |
70 | struct gdbarch_tdep | |
71 | { | |
72 | /* Which ABI is in use? */ | |
73 | enum frv_abi frv_abi; | |
74 | ||
75 | /* How many general-purpose registers does this variant have? */ | |
76 | int num_gprs; | |
77 | ||
78 | /* How many floating-point registers does this variant have? */ | |
79 | int num_fprs; | |
80 | ||
81 | /* How many hardware watchpoints can it support? */ | |
82 | int num_hw_watchpoints; | |
83 | ||
84 | /* How many hardware breakpoints can it support? */ | |
85 | int num_hw_breakpoints; | |
86 | ||
87 | /* Register names. */ | |
88 | const char **register_names; | |
89 | }; | |
90 | ||
91 | /* Return the FR-V ABI associated with GDBARCH. */ | |
92 | enum frv_abi | |
93 | frv_abi (struct gdbarch *gdbarch) | |
94 | { | |
95 | return gdbarch_tdep (gdbarch)->frv_abi; | |
96 | } | |
97 | ||
98 | /* Fetch the interpreter and executable loadmap addresses (for shared | |
99 | library support) for the FDPIC ABI. Return 0 if successful, -1 if | |
100 | not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */ | |
101 | int | |
102 | frv_fdpic_loadmap_addresses (struct gdbarch *gdbarch, CORE_ADDR *interp_addr, | |
103 | CORE_ADDR *exec_addr) | |
104 | { | |
105 | if (frv_abi (gdbarch) != FRV_ABI_FDPIC) | |
106 | return -1; | |
107 | else | |
108 | { | |
109 | struct regcache *regcache = get_current_regcache (); | |
110 | ||
111 | if (interp_addr != NULL) | |
112 | { | |
113 | ULONGEST val; | |
114 | regcache_cooked_read_unsigned (regcache, | |
115 | fdpic_loadmap_interp_regnum, &val); | |
116 | *interp_addr = val; | |
117 | } | |
118 | if (exec_addr != NULL) | |
119 | { | |
120 | ULONGEST val; | |
121 | regcache_cooked_read_unsigned (regcache, | |
122 | fdpic_loadmap_exec_regnum, &val); | |
123 | *exec_addr = val; | |
124 | } | |
125 | return 0; | |
126 | } | |
127 | } | |
128 | ||
129 | /* Allocate a new variant structure, and set up default values for all | |
130 | the fields. */ | |
131 | static struct gdbarch_tdep * | |
132 | new_variant (void) | |
133 | { | |
134 | struct gdbarch_tdep *var; | |
135 | int r; | |
136 | ||
137 | var = XCNEW (struct gdbarch_tdep); | |
138 | ||
139 | var->frv_abi = FRV_ABI_EABI; | |
140 | var->num_gprs = 64; | |
141 | var->num_fprs = 64; | |
142 | var->num_hw_watchpoints = 0; | |
143 | var->num_hw_breakpoints = 0; | |
144 | ||
145 | /* By default, don't supply any general-purpose or floating-point | |
146 | register names. */ | |
147 | var->register_names | |
148 | = (const char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs) | |
149 | * sizeof (const char *)); | |
150 | for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++) | |
151 | var->register_names[r] = ""; | |
152 | ||
153 | /* Do, however, supply default names for the known special-purpose | |
154 | registers. */ | |
155 | ||
156 | var->register_names[pc_regnum] = "pc"; | |
157 | var->register_names[lr_regnum] = "lr"; | |
158 | var->register_names[lcr_regnum] = "lcr"; | |
159 | ||
160 | var->register_names[psr_regnum] = "psr"; | |
161 | var->register_names[ccr_regnum] = "ccr"; | |
162 | var->register_names[cccr_regnum] = "cccr"; | |
163 | var->register_names[tbr_regnum] = "tbr"; | |
164 | ||
165 | /* Debug registers. */ | |
166 | var->register_names[brr_regnum] = "brr"; | |
167 | var->register_names[dbar0_regnum] = "dbar0"; | |
168 | var->register_names[dbar1_regnum] = "dbar1"; | |
169 | var->register_names[dbar2_regnum] = "dbar2"; | |
170 | var->register_names[dbar3_regnum] = "dbar3"; | |
171 | ||
172 | /* iacc0 (Only found on MB93405.) */ | |
173 | var->register_names[iacc0h_regnum] = "iacc0h"; | |
174 | var->register_names[iacc0l_regnum] = "iacc0l"; | |
175 | var->register_names[iacc0_regnum] = "iacc0"; | |
176 | ||
177 | /* fsr0 (Found on FR555 and FR501.) */ | |
178 | var->register_names[fsr0_regnum] = "fsr0"; | |
179 | ||
180 | /* acc0 - acc7. The architecture provides for the possibility of many | |
181 | more (up to 64 total), but we don't want to make that big of a hole | |
182 | in the G packet. If we need more in the future, we'll add them | |
183 | elsewhere. */ | |
184 | for (r = acc0_regnum; r <= acc7_regnum; r++) | |
185 | { | |
186 | char *buf; | |
187 | buf = xstrprintf ("acc%d", r - acc0_regnum); | |
188 | var->register_names[r] = buf; | |
189 | } | |
190 | ||
191 | /* accg0 - accg7: These are one byte registers. The remote protocol | |
192 | provides the raw values packed four into a slot. accg0123 and | |
193 | accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively. | |
194 | We don't provide names for accg0123 and accg4567 since the user will | |
195 | likely not want to see these raw values. */ | |
196 | ||
197 | for (r = accg0_regnum; r <= accg7_regnum; r++) | |
198 | { | |
199 | char *buf; | |
200 | buf = xstrprintf ("accg%d", r - accg0_regnum); | |
201 | var->register_names[r] = buf; | |
202 | } | |
203 | ||
204 | /* msr0 and msr1. */ | |
205 | ||
206 | var->register_names[msr0_regnum] = "msr0"; | |
207 | var->register_names[msr1_regnum] = "msr1"; | |
208 | ||
209 | /* gner and fner registers. */ | |
210 | var->register_names[gner0_regnum] = "gner0"; | |
211 | var->register_names[gner1_regnum] = "gner1"; | |
212 | var->register_names[fner0_regnum] = "fner0"; | |
213 | var->register_names[fner1_regnum] = "fner1"; | |
214 | ||
215 | return var; | |
216 | } | |
217 | ||
218 | ||
219 | /* Indicate that the variant VAR has NUM_GPRS general-purpose | |
220 | registers, and fill in the names array appropriately. */ | |
221 | static void | |
222 | set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs) | |
223 | { | |
224 | int r; | |
225 | ||
226 | var->num_gprs = num_gprs; | |
227 | ||
228 | for (r = 0; r < num_gprs; ++r) | |
229 | { | |
230 | char buf[20]; | |
231 | ||
232 | xsnprintf (buf, sizeof (buf), "gr%d", r); | |
233 | var->register_names[first_gpr_regnum + r] = xstrdup (buf); | |
234 | } | |
235 | } | |
236 | ||
237 | ||
238 | /* Indicate that the variant VAR has NUM_FPRS floating-point | |
239 | registers, and fill in the names array appropriately. */ | |
240 | static void | |
241 | set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs) | |
242 | { | |
243 | int r; | |
244 | ||
245 | var->num_fprs = num_fprs; | |
246 | ||
247 | for (r = 0; r < num_fprs; ++r) | |
248 | { | |
249 | char buf[20]; | |
250 | ||
251 | xsnprintf (buf, sizeof (buf), "fr%d", r); | |
252 | var->register_names[first_fpr_regnum + r] = xstrdup (buf); | |
253 | } | |
254 | } | |
255 | ||
256 | static void | |
257 | set_variant_abi_fdpic (struct gdbarch_tdep *var) | |
258 | { | |
259 | var->frv_abi = FRV_ABI_FDPIC; | |
260 | var->register_names[fdpic_loadmap_exec_regnum] = xstrdup ("loadmap_exec"); | |
261 | var->register_names[fdpic_loadmap_interp_regnum] | |
262 | = xstrdup ("loadmap_interp"); | |
263 | } | |
264 | ||
265 | static void | |
266 | set_variant_scratch_registers (struct gdbarch_tdep *var) | |
267 | { | |
268 | var->register_names[scr0_regnum] = xstrdup ("scr0"); | |
269 | var->register_names[scr1_regnum] = xstrdup ("scr1"); | |
270 | var->register_names[scr2_regnum] = xstrdup ("scr2"); | |
271 | var->register_names[scr3_regnum] = xstrdup ("scr3"); | |
272 | } | |
273 | ||
274 | static const char * | |
275 | frv_register_name (struct gdbarch *gdbarch, int reg) | |
276 | { | |
277 | if (reg < 0) | |
278 | return "?toosmall?"; | |
279 | if (reg >= frv_num_regs + frv_num_pseudo_regs) | |
280 | return "?toolarge?"; | |
281 | ||
282 | return gdbarch_tdep (gdbarch)->register_names[reg]; | |
283 | } | |
284 | ||
285 | ||
286 | static struct type * | |
287 | frv_register_type (struct gdbarch *gdbarch, int reg) | |
288 | { | |
289 | if (reg >= first_fpr_regnum && reg <= last_fpr_regnum) | |
290 | return builtin_type (gdbarch)->builtin_float; | |
291 | else if (reg == iacc0_regnum) | |
292 | return builtin_type (gdbarch)->builtin_int64; | |
293 | else | |
294 | return builtin_type (gdbarch)->builtin_int32; | |
295 | } | |
296 | ||
297 | static enum register_status | |
298 | frv_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, | |
299 | int reg, gdb_byte *buffer) | |
300 | { | |
301 | enum register_status status; | |
302 | ||
303 | if (reg == iacc0_regnum) | |
304 | { | |
305 | status = regcache->raw_read (iacc0h_regnum, buffer); | |
306 | if (status == REG_VALID) | |
307 | status = regcache->raw_read (iacc0l_regnum, (bfd_byte *) buffer + 4); | |
308 | } | |
309 | else if (accg0_regnum <= reg && reg <= accg7_regnum) | |
310 | { | |
311 | /* The accg raw registers have four values in each slot with the | |
312 | lowest register number occupying the first byte. */ | |
313 | ||
314 | int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4; | |
315 | int byte_num = (reg - accg0_regnum) % 4; | |
316 | gdb_byte buf[4]; | |
317 | ||
318 | status = regcache->raw_read (raw_regnum, buf); | |
319 | if (status == REG_VALID) | |
320 | { | |
321 | memset (buffer, 0, 4); | |
322 | /* FR-V is big endian, so put the requested byte in the | |
323 | first byte of the buffer allocated to hold the | |
324 | pseudo-register. */ | |
325 | buffer[0] = buf[byte_num]; | |
326 | } | |
327 | } | |
328 | else | |
329 | gdb_assert_not_reached ("invalid pseudo register number"); | |
330 | ||
331 | return status; | |
332 | } | |
333 | ||
334 | static void | |
335 | frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
336 | int reg, const gdb_byte *buffer) | |
337 | { | |
338 | if (reg == iacc0_regnum) | |
339 | { | |
340 | regcache->raw_write (iacc0h_regnum, buffer); | |
341 | regcache->raw_write (iacc0l_regnum, (bfd_byte *) buffer + 4); | |
342 | } | |
343 | else if (accg0_regnum <= reg && reg <= accg7_regnum) | |
344 | { | |
345 | /* The accg raw registers have four values in each slot with the | |
346 | lowest register number occupying the first byte. */ | |
347 | ||
348 | int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4; | |
349 | int byte_num = (reg - accg0_regnum) % 4; | |
350 | gdb_byte buf[4]; | |
351 | ||
352 | regcache->raw_read (raw_regnum, buf); | |
353 | buf[byte_num] = ((bfd_byte *) buffer)[0]; | |
354 | regcache->raw_write (raw_regnum, buf); | |
355 | } | |
356 | } | |
357 | ||
358 | static int | |
359 | frv_register_sim_regno (struct gdbarch *gdbarch, int reg) | |
360 | { | |
361 | static const int spr_map[] = | |
362 | { | |
363 | H_SPR_PSR, /* psr_regnum */ | |
364 | H_SPR_CCR, /* ccr_regnum */ | |
365 | H_SPR_CCCR, /* cccr_regnum */ | |
366 | -1, /* fdpic_loadmap_exec_regnum */ | |
367 | -1, /* fdpic_loadmap_interp_regnum */ | |
368 | -1, /* 134 */ | |
369 | H_SPR_TBR, /* tbr_regnum */ | |
370 | H_SPR_BRR, /* brr_regnum */ | |
371 | H_SPR_DBAR0, /* dbar0_regnum */ | |
372 | H_SPR_DBAR1, /* dbar1_regnum */ | |
373 | H_SPR_DBAR2, /* dbar2_regnum */ | |
374 | H_SPR_DBAR3, /* dbar3_regnum */ | |
375 | H_SPR_SCR0, /* scr0_regnum */ | |
376 | H_SPR_SCR1, /* scr1_regnum */ | |
377 | H_SPR_SCR2, /* scr2_regnum */ | |
378 | H_SPR_SCR3, /* scr3_regnum */ | |
379 | H_SPR_LR, /* lr_regnum */ | |
380 | H_SPR_LCR, /* lcr_regnum */ | |
381 | H_SPR_IACC0H, /* iacc0h_regnum */ | |
382 | H_SPR_IACC0L, /* iacc0l_regnum */ | |
383 | H_SPR_FSR0, /* fsr0_regnum */ | |
384 | /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */ | |
385 | -1, /* acc0_regnum */ | |
386 | -1, /* acc1_regnum */ | |
387 | -1, /* acc2_regnum */ | |
388 | -1, /* acc3_regnum */ | |
389 | -1, /* acc4_regnum */ | |
390 | -1, /* acc5_regnum */ | |
391 | -1, /* acc6_regnum */ | |
392 | -1, /* acc7_regnum */ | |
393 | -1, /* acc0123_regnum */ | |
394 | -1, /* acc4567_regnum */ | |
395 | H_SPR_MSR0, /* msr0_regnum */ | |
396 | H_SPR_MSR1, /* msr1_regnum */ | |
397 | H_SPR_GNER0, /* gner0_regnum */ | |
398 | H_SPR_GNER1, /* gner1_regnum */ | |
399 | H_SPR_FNER0, /* fner0_regnum */ | |
400 | H_SPR_FNER1, /* fner1_regnum */ | |
401 | }; | |
402 | ||
403 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); | |
404 | ||
405 | if (first_gpr_regnum <= reg && reg <= last_gpr_regnum) | |
406 | return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM; | |
407 | else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum) | |
408 | return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM; | |
409 | else if (pc_regnum == reg) | |
410 | return SIM_FRV_PC_REGNUM; | |
411 | else if (reg >= first_spr_regnum | |
412 | && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0])) | |
413 | { | |
414 | int spr_reg_offset = spr_map[reg - first_spr_regnum]; | |
415 | ||
416 | if (spr_reg_offset < 0) | |
417 | return SIM_REGNO_DOES_NOT_EXIST; | |
418 | else | |
419 | return SIM_FRV_SPR0_REGNUM + spr_reg_offset; | |
420 | } | |
421 | ||
422 | internal_error (__FILE__, __LINE__, _("Bad register number %d"), reg); | |
423 | } | |
424 | ||
425 | constexpr gdb_byte frv_break_insn[] = {0xc0, 0x70, 0x00, 0x01}; | |
426 | ||
427 | typedef BP_MANIPULATION (frv_break_insn) frv_breakpoint; | |
428 | ||
429 | /* Define the maximum number of instructions which may be packed into a | |
430 | bundle (VLIW instruction). */ | |
431 | static const int max_instrs_per_bundle = 8; | |
432 | ||
433 | /* Define the size (in bytes) of an FR-V instruction. */ | |
434 | static const int frv_instr_size = 4; | |
435 | ||
436 | /* Adjust a breakpoint's address to account for the FR-V architecture's | |
437 | constraint that a break instruction must not appear as any but the | |
438 | first instruction in the bundle. */ | |
439 | static CORE_ADDR | |
440 | frv_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
441 | { | |
442 | int count = max_instrs_per_bundle; | |
443 | CORE_ADDR addr = bpaddr - frv_instr_size; | |
444 | CORE_ADDR func_start = get_pc_function_start (bpaddr); | |
445 | ||
446 | /* Find the end of the previous packing sequence. This will be indicated | |
447 | by either attempting to access some inaccessible memory or by finding | |
448 | an instruction word whose packing bit is set to one. */ | |
449 | while (count-- > 0 && addr >= func_start) | |
450 | { | |
451 | gdb_byte instr[frv_instr_size]; | |
452 | int status; | |
453 | ||
454 | status = target_read_memory (addr, instr, sizeof instr); | |
455 | ||
456 | if (status != 0) | |
457 | break; | |
458 | ||
459 | /* This is a big endian architecture, so byte zero will have most | |
460 | significant byte. The most significant bit of this byte is the | |
461 | packing bit. */ | |
462 | if (instr[0] & 0x80) | |
463 | break; | |
464 | ||
465 | addr -= frv_instr_size; | |
466 | } | |
467 | ||
468 | if (count > 0) | |
469 | bpaddr = addr + frv_instr_size; | |
470 | ||
471 | return bpaddr; | |
472 | } | |
473 | ||
474 | ||
475 | /* Return true if REG is a caller-saves ("scratch") register, | |
476 | false otherwise. */ | |
477 | static int | |
478 | is_caller_saves_reg (int reg) | |
479 | { | |
480 | return ((4 <= reg && reg <= 7) | |
481 | || (14 <= reg && reg <= 15) | |
482 | || (32 <= reg && reg <= 47)); | |
483 | } | |
484 | ||
485 | ||
486 | /* Return true if REG is a callee-saves register, false otherwise. */ | |
487 | static int | |
488 | is_callee_saves_reg (int reg) | |
489 | { | |
490 | return ((16 <= reg && reg <= 31) | |
491 | || (48 <= reg && reg <= 63)); | |
492 | } | |
493 | ||
494 | ||
495 | /* Return true if REG is an argument register, false otherwise. */ | |
496 | static int | |
497 | is_argument_reg (int reg) | |
498 | { | |
499 | return (8 <= reg && reg <= 13); | |
500 | } | |
501 | ||
502 | /* Scan an FR-V prologue, starting at PC, until frame->PC. | |
503 | If FRAME is non-zero, fill in its saved_regs with appropriate addresses. | |
504 | We assume FRAME's saved_regs array has already been allocated and cleared. | |
505 | Return the first PC value after the prologue. | |
506 | ||
507 | Note that, for unoptimized code, we almost don't need this function | |
508 | at all; all arguments and locals live on the stack, so we just need | |
509 | the FP to find everything. The catch: structures passed by value | |
510 | have their addresses living in registers; they're never spilled to | |
511 | the stack. So if you ever want to be able to get to these | |
512 | arguments in any frame but the top, you'll need to do this serious | |
513 | prologue analysis. */ | |
514 | static CORE_ADDR | |
515 | frv_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, | |
516 | struct frame_info *this_frame, | |
517 | struct frv_unwind_cache *info) | |
518 | { | |
519 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
520 | ||
521 | /* When writing out instruction bitpatterns, we use the following | |
522 | letters to label instruction fields: | |
523 | P - The parallel bit. We don't use this. | |
524 | J - The register number of GRj in the instruction description. | |
525 | K - The register number of GRk in the instruction description. | |
526 | I - The register number of GRi. | |
527 | S - a signed imediate offset. | |
528 | U - an unsigned immediate offset. | |
529 | ||
530 | The dots below the numbers indicate where hex digit boundaries | |
531 | fall, to make it easier to check the numbers. */ | |
532 | ||
533 | /* Non-zero iff we've seen the instruction that initializes the | |
534 | frame pointer for this function's frame. */ | |
535 | int fp_set = 0; | |
536 | ||
537 | /* If fp_set is non_zero, then this is the distance from | |
538 | the stack pointer to frame pointer: fp = sp + fp_offset. */ | |
539 | int fp_offset = 0; | |
540 | ||
541 | /* Total size of frame prior to any alloca operations. */ | |
542 | int framesize = 0; | |
543 | ||
544 | /* Flag indicating if lr has been saved on the stack. */ | |
545 | int lr_saved_on_stack = 0; | |
546 | ||
547 | /* The number of the general-purpose register we saved the return | |
548 | address ("link register") in, or -1 if we haven't moved it yet. */ | |
549 | int lr_save_reg = -1; | |
550 | ||
551 | /* Offset (from sp) at which lr has been saved on the stack. */ | |
552 | ||
553 | int lr_sp_offset = 0; | |
554 | ||
555 | /* If gr_saved[i] is non-zero, then we've noticed that general | |
556 | register i has been saved at gr_sp_offset[i] from the stack | |
557 | pointer. */ | |
558 | char gr_saved[64]; | |
559 | int gr_sp_offset[64]; | |
560 | ||
561 | /* The address of the most recently scanned prologue instruction. */ | |
562 | CORE_ADDR last_prologue_pc; | |
563 | ||
564 | /* The address of the next instruction. */ | |
565 | CORE_ADDR next_pc; | |
566 | ||
567 | /* The upper bound to of the pc values to scan. */ | |
568 | CORE_ADDR lim_pc; | |
569 | ||
570 | memset (gr_saved, 0, sizeof (gr_saved)); | |
571 | ||
572 | last_prologue_pc = pc; | |
573 | ||
574 | /* Try to compute an upper limit (on how far to scan) based on the | |
575 | line number info. */ | |
576 | lim_pc = skip_prologue_using_sal (gdbarch, pc); | |
577 | /* If there's no line number info, lim_pc will be 0. In that case, | |
578 | set the limit to be 100 instructions away from pc. Hopefully, this | |
579 | will be far enough away to account for the entire prologue. Don't | |
580 | worry about overshooting the end of the function. The scan loop | |
581 | below contains some checks to avoid scanning unreasonably far. */ | |
582 | if (lim_pc == 0) | |
583 | lim_pc = pc + 400; | |
584 | ||
585 | /* If we have a frame, we don't want to scan past the frame's pc. This | |
586 | will catch those cases where the pc is in the prologue. */ | |
587 | if (this_frame) | |
588 | { | |
589 | CORE_ADDR frame_pc = get_frame_pc (this_frame); | |
590 | if (frame_pc < lim_pc) | |
591 | lim_pc = frame_pc; | |
592 | } | |
593 | ||
594 | /* Scan the prologue. */ | |
595 | while (pc < lim_pc) | |
596 | { | |
597 | gdb_byte buf[frv_instr_size]; | |
598 | LONGEST op; | |
599 | ||
600 | if (target_read_memory (pc, buf, sizeof buf) != 0) | |
601 | break; | |
602 | op = extract_signed_integer (buf, sizeof buf, byte_order); | |
603 | ||
604 | next_pc = pc + 4; | |
605 | ||
606 | /* The tests in this chain of ifs should be in order of | |
607 | decreasing selectivity, so that more particular patterns get | |
608 | to fire before less particular patterns. */ | |
609 | ||
610 | /* Some sort of control transfer instruction: stop scanning prologue. | |
611 | Integer Conditional Branch: | |
612 | X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX | |
613 | Floating-point / media Conditional Branch: | |
614 | X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX | |
615 | LCR Conditional Branch to LR | |
616 | X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX | |
617 | Integer conditional Branches to LR | |
618 | X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX | |
619 | X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX | |
620 | Floating-point/Media Branches to LR | |
621 | X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX | |
622 | X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX | |
623 | Jump and Link | |
624 | X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX | |
625 | X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX | |
626 | Call | |
627 | X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX | |
628 | Return from Trap | |
629 | X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX | |
630 | Integer Conditional Trap | |
631 | X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX | |
632 | X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX | |
633 | Floating-point /media Conditional Trap | |
634 | X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX | |
635 | X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX | |
636 | Break | |
637 | X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX | |
638 | Media Trap | |
639 | X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */ | |
640 | if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */ | |
641 | || (op & 0x01f80000) == 0x00300000 /* Jump and Link */ | |
642 | || (op & 0x01f80000) == 0x00100000 /* Return from Trap, Trap */ | |
643 | || (op & 0x01f80000) == 0x00700000) /* Trap immediate */ | |
644 | { | |
645 | /* Stop scanning; not in prologue any longer. */ | |
646 | break; | |
647 | } | |
648 | ||
649 | /* Loading something from memory into fp probably means that | |
650 | we're in the epilogue. Stop scanning the prologue. | |
651 | ld @(GRi, GRk), fp | |
652 | X 000010 0000010 XXXXXX 000100 XXXXXX | |
653 | ldi @(GRi, d12), fp | |
654 | X 000010 0110010 XXXXXX XXXXXXXXXXXX */ | |
655 | else if ((op & 0x7ffc0fc0) == 0x04080100 | |
656 | || (op & 0x7ffc0000) == 0x04c80000) | |
657 | { | |
658 | break; | |
659 | } | |
660 | ||
661 | /* Setting the FP from the SP: | |
662 | ori sp, 0, fp | |
663 | P 000010 0100010 000001 000000000000 = 0x04881000 | |
664 | 0 111111 1111111 111111 111111111111 = 0x7fffffff | |
665 | . . . . . . . . | |
666 | We treat this as part of the prologue. */ | |
667 | else if ((op & 0x7fffffff) == 0x04881000) | |
668 | { | |
669 | fp_set = 1; | |
670 | fp_offset = 0; | |
671 | last_prologue_pc = next_pc; | |
672 | } | |
673 | ||
674 | /* Move the link register to the scratch register grJ, before saving: | |
675 | movsg lr, grJ | |
676 | P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0 | |
677 | 0 111111 1111111 111111 111111 000000 = 0x7fffffc0 | |
678 | . . . . . . . . | |
679 | We treat this as part of the prologue. */ | |
680 | else if ((op & 0x7fffffc0) == 0x080d01c0) | |
681 | { | |
682 | int gr_j = op & 0x3f; | |
683 | ||
684 | /* If we're moving it to a scratch register, that's fine. */ | |
685 | if (is_caller_saves_reg (gr_j)) | |
686 | { | |
687 | lr_save_reg = gr_j; | |
688 | last_prologue_pc = next_pc; | |
689 | } | |
690 | } | |
691 | ||
692 | /* To save multiple callee-saves registers on the stack, at | |
693 | offset zero: | |
694 | ||
695 | std grK,@(sp,gr0) | |
696 | P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0 | |
697 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff | |
698 | ||
699 | stq grK,@(sp,gr0) | |
700 | P KKKKKK 0000011 000001 000100 000000 = 0x000c1100 | |
701 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff | |
702 | . . . . . . . . | |
703 | We treat this as part of the prologue, and record the register's | |
704 | saved address in the frame structure. */ | |
705 | else if ((op & 0x01ffffff) == 0x000c10c0 | |
706 | || (op & 0x01ffffff) == 0x000c1100) | |
707 | { | |
708 | int gr_k = ((op >> 25) & 0x3f); | |
709 | int ope = ((op >> 6) & 0x3f); | |
710 | int count; | |
711 | int i; | |
712 | ||
713 | /* Is it an std or an stq? */ | |
714 | if (ope == 0x03) | |
715 | count = 2; | |
716 | else | |
717 | count = 4; | |
718 | ||
719 | /* Is it really a callee-saves register? */ | |
720 | if (is_callee_saves_reg (gr_k)) | |
721 | { | |
722 | for (i = 0; i < count; i++) | |
723 | { | |
724 | gr_saved[gr_k + i] = 1; | |
725 | gr_sp_offset[gr_k + i] = 4 * i; | |
726 | } | |
727 | last_prologue_pc = next_pc; | |
728 | } | |
729 | } | |
730 | ||
731 | /* Adjusting the stack pointer. (The stack pointer is GR1.) | |
732 | addi sp, S, sp | |
733 | P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000 | |
734 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 | |
735 | . . . . . . . . | |
736 | We treat this as part of the prologue. */ | |
737 | else if ((op & 0x7ffff000) == 0x02401000) | |
738 | { | |
739 | if (framesize == 0) | |
740 | { | |
741 | /* Sign-extend the twelve-bit field. | |
742 | (Isn't there a better way to do this?) */ | |
743 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
744 | ||
745 | framesize -= s; | |
746 | last_prologue_pc = pc; | |
747 | } | |
748 | else | |
749 | { | |
750 | /* If the prologue is being adjusted again, we've | |
751 | likely gone too far; i.e. we're probably in the | |
752 | epilogue. */ | |
753 | break; | |
754 | } | |
755 | } | |
756 | ||
757 | /* Setting the FP to a constant distance from the SP: | |
758 | addi sp, S, fp | |
759 | P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000 | |
760 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 | |
761 | . . . . . . . . | |
762 | We treat this as part of the prologue. */ | |
763 | else if ((op & 0x7ffff000) == 0x04401000) | |
764 | { | |
765 | /* Sign-extend the twelve-bit field. | |
766 | (Isn't there a better way to do this?) */ | |
767 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
768 | fp_set = 1; | |
769 | fp_offset = s; | |
770 | last_prologue_pc = pc; | |
771 | } | |
772 | ||
773 | /* To spill an argument register to a scratch register: | |
774 | ori GRi, 0, GRk | |
775 | P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000 | |
776 | 0 000000 1111111 000000 111111111111 = 0x01fc0fff | |
777 | . . . . . . . . | |
778 | For the time being, we treat this as a prologue instruction, | |
779 | assuming that GRi is an argument register. This one's kind | |
780 | of suspicious, because it seems like it could be part of a | |
781 | legitimate body instruction. But we only come here when the | |
782 | source info wasn't helpful, so we have to do the best we can. | |
783 | Hopefully once GCC and GDB agree on how to emit line number | |
784 | info for prologues, then this code will never come into play. */ | |
785 | else if ((op & 0x01fc0fff) == 0x00880000) | |
786 | { | |
787 | int gr_i = ((op >> 12) & 0x3f); | |
788 | ||
789 | /* Make sure that the source is an arg register; if it is, we'll | |
790 | treat it as a prologue instruction. */ | |
791 | if (is_argument_reg (gr_i)) | |
792 | last_prologue_pc = next_pc; | |
793 | } | |
794 | ||
795 | /* To spill 16-bit values to the stack: | |
796 | sthi GRk, @(fp, s) | |
797 | P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000 | |
798 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
799 | . . . . . . . . | |
800 | And for 8-bit values, we use STB instructions. | |
801 | stbi GRk, @(fp, s) | |
802 | P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000 | |
803 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
804 | . . . . . . . . | |
805 | We check that GRk is really an argument register, and treat | |
806 | all such as part of the prologue. */ | |
807 | else if ( (op & 0x01fff000) == 0x01442000 | |
808 | || (op & 0x01fff000) == 0x01402000) | |
809 | { | |
810 | int gr_k = ((op >> 25) & 0x3f); | |
811 | ||
812 | /* Make sure that GRk is really an argument register; treat | |
813 | it as a prologue instruction if so. */ | |
814 | if (is_argument_reg (gr_k)) | |
815 | last_prologue_pc = next_pc; | |
816 | } | |
817 | ||
818 | /* To save multiple callee-saves register on the stack, at a | |
819 | non-zero offset: | |
820 | ||
821 | stdi GRk, @(sp, s) | |
822 | P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000 | |
823 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
824 | . . . . . . . . | |
825 | stqi GRk, @(sp, s) | |
826 | P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000 | |
827 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
828 | . . . . . . . . | |
829 | We treat this as part of the prologue, and record the register's | |
830 | saved address in the frame structure. */ | |
831 | else if ((op & 0x01fff000) == 0x014c1000 | |
832 | || (op & 0x01fff000) == 0x01501000) | |
833 | { | |
834 | int gr_k = ((op >> 25) & 0x3f); | |
835 | int count; | |
836 | int i; | |
837 | ||
838 | /* Is it a stdi or a stqi? */ | |
839 | if ((op & 0x01fff000) == 0x014c1000) | |
840 | count = 2; | |
841 | else | |
842 | count = 4; | |
843 | ||
844 | /* Is it really a callee-saves register? */ | |
845 | if (is_callee_saves_reg (gr_k)) | |
846 | { | |
847 | /* Sign-extend the twelve-bit field. | |
848 | (Isn't there a better way to do this?) */ | |
849 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
850 | ||
851 | for (i = 0; i < count; i++) | |
852 | { | |
853 | gr_saved[gr_k + i] = 1; | |
854 | gr_sp_offset[gr_k + i] = s + (4 * i); | |
855 | } | |
856 | last_prologue_pc = next_pc; | |
857 | } | |
858 | } | |
859 | ||
860 | /* Storing any kind of integer register at any constant offset | |
861 | from any other register. | |
862 | ||
863 | st GRk, @(GRi, gr0) | |
864 | P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080 | |
865 | 0 000000 1111111 000000 111111 111111 = 0x01fc0fff | |
866 | . . . . . . . . | |
867 | sti GRk, @(GRi, d12) | |
868 | P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000 | |
869 | 0 000000 1111111 000000 000000000000 = 0x01fc0000 | |
870 | . . . . . . . . | |
871 | These could be almost anything, but a lot of prologue | |
872 | instructions fall into this pattern, so let's decode the | |
873 | instruction once, and then work at a higher level. */ | |
874 | else if (((op & 0x01fc0fff) == 0x000c0080) | |
875 | || ((op & 0x01fc0000) == 0x01480000)) | |
876 | { | |
877 | int gr_k = ((op >> 25) & 0x3f); | |
878 | int gr_i = ((op >> 12) & 0x3f); | |
879 | int offset; | |
880 | ||
881 | /* Are we storing with gr0 as an offset, or using an | |
882 | immediate value? */ | |
883 | if ((op & 0x01fc0fff) == 0x000c0080) | |
884 | offset = 0; | |
885 | else | |
886 | offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
887 | ||
888 | /* If the address isn't relative to the SP or FP, it's not a | |
889 | prologue instruction. */ | |
890 | if (gr_i != sp_regnum && gr_i != fp_regnum) | |
891 | { | |
892 | /* Do nothing; not a prologue instruction. */ | |
893 | } | |
894 | ||
895 | /* Saving the old FP in the new frame (relative to the SP). */ | |
896 | else if (gr_k == fp_regnum && gr_i == sp_regnum) | |
897 | { | |
898 | gr_saved[fp_regnum] = 1; | |
899 | gr_sp_offset[fp_regnum] = offset; | |
900 | last_prologue_pc = next_pc; | |
901 | } | |
902 | ||
903 | /* Saving callee-saves register(s) on the stack, relative to | |
904 | the SP. */ | |
905 | else if (gr_i == sp_regnum | |
906 | && is_callee_saves_reg (gr_k)) | |
907 | { | |
908 | gr_saved[gr_k] = 1; | |
909 | if (gr_i == sp_regnum) | |
910 | gr_sp_offset[gr_k] = offset; | |
911 | else | |
912 | gr_sp_offset[gr_k] = offset + fp_offset; | |
913 | last_prologue_pc = next_pc; | |
914 | } | |
915 | ||
916 | /* Saving the scratch register holding the return address. */ | |
917 | else if (lr_save_reg != -1 | |
918 | && gr_k == lr_save_reg) | |
919 | { | |
920 | lr_saved_on_stack = 1; | |
921 | if (gr_i == sp_regnum) | |
922 | lr_sp_offset = offset; | |
923 | else | |
924 | lr_sp_offset = offset + fp_offset; | |
925 | last_prologue_pc = next_pc; | |
926 | } | |
927 | ||
928 | /* Spilling int-sized arguments to the stack. */ | |
929 | else if (is_argument_reg (gr_k)) | |
930 | last_prologue_pc = next_pc; | |
931 | } | |
932 | pc = next_pc; | |
933 | } | |
934 | ||
935 | if (this_frame && info) | |
936 | { | |
937 | int i; | |
938 | ULONGEST this_base; | |
939 | ||
940 | /* If we know the relationship between the stack and frame | |
941 | pointers, record the addresses of the registers we noticed. | |
942 | Note that we have to do this as a separate step at the end, | |
943 | because instructions may save relative to the SP, but we need | |
944 | their addresses relative to the FP. */ | |
945 | if (fp_set) | |
946 | this_base = get_frame_register_unsigned (this_frame, fp_regnum); | |
947 | else | |
948 | this_base = get_frame_register_unsigned (this_frame, sp_regnum); | |
949 | ||
950 | for (i = 0; i < 64; i++) | |
951 | if (gr_saved[i]) | |
952 | info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i]; | |
953 | ||
954 | info->prev_sp = this_base - fp_offset + framesize; | |
955 | info->base = this_base; | |
956 | ||
957 | /* If LR was saved on the stack, record its location. */ | |
958 | if (lr_saved_on_stack) | |
959 | info->saved_regs[lr_regnum].addr | |
960 | = this_base - fp_offset + lr_sp_offset; | |
961 | ||
962 | /* The call instruction moves the caller's PC in the callee's LR. | |
963 | Since this is an unwind, do the reverse. Copy the location of LR | |
964 | into PC (the address / regnum) so that a request for PC will be | |
965 | converted into a request for the LR. */ | |
966 | info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum]; | |
967 | ||
968 | /* Save the previous frame's computed SP value. */ | |
969 | trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp); | |
970 | } | |
971 | ||
972 | return last_prologue_pc; | |
973 | } | |
974 | ||
975 | ||
976 | static CORE_ADDR | |
977 | frv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
978 | { | |
979 | CORE_ADDR func_addr, func_end, new_pc; | |
980 | ||
981 | new_pc = pc; | |
982 | ||
983 | /* If the line table has entry for a line *within* the function | |
984 | (i.e., not in the prologue, and not past the end), then that's | |
985 | our location. */ | |
986 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
987 | { | |
988 | struct symtab_and_line sal; | |
989 | ||
990 | sal = find_pc_line (func_addr, 0); | |
991 | ||
992 | if (sal.line != 0 && sal.end < func_end) | |
993 | { | |
994 | new_pc = sal.end; | |
995 | } | |
996 | } | |
997 | ||
998 | /* The FR-V prologue is at least five instructions long (twenty bytes). | |
999 | If we didn't find a real source location past that, then | |
1000 | do a full analysis of the prologue. */ | |
1001 | if (new_pc < pc + 20) | |
1002 | new_pc = frv_analyze_prologue (gdbarch, pc, 0, 0); | |
1003 | ||
1004 | return new_pc; | |
1005 | } | |
1006 | ||
1007 | ||
1008 | /* Examine the instruction pointed to by PC. If it corresponds to | |
1009 | a call to __main, return the address of the next instruction. | |
1010 | Otherwise, return PC. */ | |
1011 | ||
1012 | static CORE_ADDR | |
1013 | frv_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1014 | { | |
1015 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1016 | gdb_byte buf[4]; | |
1017 | unsigned long op; | |
1018 | CORE_ADDR orig_pc = pc; | |
1019 | ||
1020 | if (target_read_memory (pc, buf, 4)) | |
1021 | return pc; | |
1022 | op = extract_unsigned_integer (buf, 4, byte_order); | |
1023 | ||
1024 | /* In PIC code, GR15 may be loaded from some offset off of FP prior | |
1025 | to the call instruction. | |
1026 | ||
1027 | Skip over this instruction if present. It won't be present in | |
1028 | non-PIC code, and even in PIC code, it might not be present. | |
1029 | (This is due to the fact that GR15, the FDPIC register, already | |
1030 | contains the correct value.) | |
1031 | ||
1032 | The general form of the LDI is given first, followed by the | |
1033 | specific instruction with the GRi and GRk filled in as FP and | |
1034 | GR15. | |
1035 | ||
1036 | ldi @(GRi, d12), GRk | |
1037 | P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x00c80000 | |
1038 | 0 000000 1111111 000000 000000000000 = 0x01fc0000 | |
1039 | . . . . . . . . | |
1040 | ldi @(FP, d12), GR15 | |
1041 | P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x1ec82000 | |
1042 | 0 001111 1111111 000010 000000000000 = 0x7ffff000 | |
1043 | . . . . . . . . */ | |
1044 | ||
1045 | if ((op & 0x7ffff000) == 0x1ec82000) | |
1046 | { | |
1047 | pc += 4; | |
1048 | if (target_read_memory (pc, buf, 4)) | |
1049 | return orig_pc; | |
1050 | op = extract_unsigned_integer (buf, 4, byte_order); | |
1051 | } | |
1052 | ||
1053 | /* The format of an FRV CALL instruction is as follows: | |
1054 | ||
1055 | call label24 | |
1056 | P HHHHHH 0001111 LLLLLLLLLLLLLLLLLL = 0x003c0000 | |
1057 | 0 000000 1111111 000000000000000000 = 0x01fc0000 | |
1058 | . . . . . . . . | |
1059 | ||
1060 | where label24 is constructed by concatenating the H bits with the | |
1061 | L bits. The call target is PC + (4 * sign_ext(label24)). */ | |
1062 | ||
1063 | if ((op & 0x01fc0000) == 0x003c0000) | |
1064 | { | |
1065 | LONGEST displ; | |
1066 | CORE_ADDR call_dest; | |
1067 | struct bound_minimal_symbol s; | |
1068 | ||
1069 | displ = ((op & 0xfe000000) >> 7) | (op & 0x0003ffff); | |
1070 | if ((displ & 0x00800000) != 0) | |
1071 | displ |= ~((LONGEST) 0x00ffffff); | |
1072 | ||
1073 | call_dest = pc + 4 * displ; | |
1074 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1075 | ||
1076 | if (s.minsym != NULL | |
1077 | && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL | |
1078 | && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0) | |
1079 | { | |
1080 | pc += 4; | |
1081 | return pc; | |
1082 | } | |
1083 | } | |
1084 | return orig_pc; | |
1085 | } | |
1086 | ||
1087 | ||
1088 | static struct frv_unwind_cache * | |
1089 | frv_frame_unwind_cache (struct frame_info *this_frame, | |
1090 | void **this_prologue_cache) | |
1091 | { | |
1092 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1093 | struct frv_unwind_cache *info; | |
1094 | ||
1095 | if ((*this_prologue_cache)) | |
1096 | return (struct frv_unwind_cache *) (*this_prologue_cache); | |
1097 | ||
1098 | info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache); | |
1099 | (*this_prologue_cache) = info; | |
1100 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
1101 | ||
1102 | /* Prologue analysis does the rest... */ | |
1103 | frv_analyze_prologue (gdbarch, | |
1104 | get_frame_func (this_frame), this_frame, info); | |
1105 | ||
1106 | return info; | |
1107 | } | |
1108 | ||
1109 | static void | |
1110 | frv_extract_return_value (struct type *type, struct regcache *regcache, | |
1111 | gdb_byte *valbuf) | |
1112 | { | |
1113 | struct gdbarch *gdbarch = regcache->arch (); | |
1114 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1115 | int len = TYPE_LENGTH (type); | |
1116 | ||
1117 | if (len <= 4) | |
1118 | { | |
1119 | ULONGEST gpr8_val; | |
1120 | regcache_cooked_read_unsigned (regcache, 8, &gpr8_val); | |
1121 | store_unsigned_integer (valbuf, len, byte_order, gpr8_val); | |
1122 | } | |
1123 | else if (len == 8) | |
1124 | { | |
1125 | ULONGEST regval; | |
1126 | ||
1127 | regcache_cooked_read_unsigned (regcache, 8, ®val); | |
1128 | store_unsigned_integer (valbuf, 4, byte_order, regval); | |
1129 | regcache_cooked_read_unsigned (regcache, 9, ®val); | |
1130 | store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, byte_order, regval); | |
1131 | } | |
1132 | else | |
1133 | internal_error (__FILE__, __LINE__, | |
1134 | _("Illegal return value length: %d"), len); | |
1135 | } | |
1136 | ||
1137 | static CORE_ADDR | |
1138 | frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1139 | { | |
1140 | /* Require dword alignment. */ | |
1141 | return align_down (sp, 8); | |
1142 | } | |
1143 | ||
1144 | static CORE_ADDR | |
1145 | find_func_descr (struct gdbarch *gdbarch, CORE_ADDR entry_point) | |
1146 | { | |
1147 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1148 | CORE_ADDR descr; | |
1149 | gdb_byte valbuf[4]; | |
1150 | CORE_ADDR start_addr; | |
1151 | ||
1152 | /* If we can't find the function in the symbol table, then we assume | |
1153 | that the function address is already in descriptor form. */ | |
1154 | if (!find_pc_partial_function (entry_point, NULL, &start_addr, NULL) | |
1155 | || entry_point != start_addr) | |
1156 | return entry_point; | |
1157 | ||
1158 | descr = frv_fdpic_find_canonical_descriptor (entry_point); | |
1159 | ||
1160 | if (descr != 0) | |
1161 | return descr; | |
1162 | ||
1163 | /* Construct a non-canonical descriptor from space allocated on | |
1164 | the stack. */ | |
1165 | ||
1166 | descr = value_as_long (value_allocate_space_in_inferior (8)); | |
1167 | store_unsigned_integer (valbuf, 4, byte_order, entry_point); | |
1168 | write_memory (descr, valbuf, 4); | |
1169 | store_unsigned_integer (valbuf, 4, byte_order, | |
1170 | frv_fdpic_find_global_pointer (entry_point)); | |
1171 | write_memory (descr + 4, valbuf, 4); | |
1172 | return descr; | |
1173 | } | |
1174 | ||
1175 | static CORE_ADDR | |
1176 | frv_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr, | |
1177 | struct target_ops *targ) | |
1178 | { | |
1179 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1180 | CORE_ADDR entry_point; | |
1181 | CORE_ADDR got_address; | |
1182 | ||
1183 | entry_point = get_target_memory_unsigned (targ, addr, 4, byte_order); | |
1184 | got_address = get_target_memory_unsigned (targ, addr + 4, 4, byte_order); | |
1185 | ||
1186 | if (got_address == frv_fdpic_find_global_pointer (entry_point)) | |
1187 | return entry_point; | |
1188 | else | |
1189 | return addr; | |
1190 | } | |
1191 | ||
1192 | static CORE_ADDR | |
1193 | frv_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
1194 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1195 | int nargs, struct value **args, CORE_ADDR sp, | |
1196 | function_call_return_method return_method, | |
1197 | CORE_ADDR struct_addr) | |
1198 | { | |
1199 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1200 | int argreg; | |
1201 | int argnum; | |
1202 | const gdb_byte *val; | |
1203 | gdb_byte valbuf[4]; | |
1204 | struct value *arg; | |
1205 | struct type *arg_type; | |
1206 | int len; | |
1207 | enum type_code typecode; | |
1208 | CORE_ADDR regval; | |
1209 | int stack_space; | |
1210 | int stack_offset; | |
1211 | enum frv_abi abi = frv_abi (gdbarch); | |
1212 | CORE_ADDR func_addr = find_function_addr (function, NULL); | |
1213 | ||
1214 | #if 0 | |
1215 | printf("Push %d args at sp = %x, struct_return=%d (%x)\n", | |
1216 | nargs, (int) sp, struct_return, struct_addr); | |
1217 | #endif | |
1218 | ||
1219 | stack_space = 0; | |
1220 | for (argnum = 0; argnum < nargs; ++argnum) | |
1221 | stack_space += align_up (TYPE_LENGTH (value_type (args[argnum])), 4); | |
1222 | ||
1223 | stack_space -= (6 * 4); | |
1224 | if (stack_space > 0) | |
1225 | sp -= stack_space; | |
1226 | ||
1227 | /* Make sure stack is dword aligned. */ | |
1228 | sp = align_down (sp, 8); | |
1229 | ||
1230 | stack_offset = 0; | |
1231 | ||
1232 | argreg = 8; | |
1233 | ||
1234 | if (return_method == return_method_struct) | |
1235 | regcache_cooked_write_unsigned (regcache, struct_return_regnum, | |
1236 | struct_addr); | |
1237 | ||
1238 | for (argnum = 0; argnum < nargs; ++argnum) | |
1239 | { | |
1240 | arg = args[argnum]; | |
1241 | arg_type = check_typedef (value_type (arg)); | |
1242 | len = TYPE_LENGTH (arg_type); | |
1243 | typecode = TYPE_CODE (arg_type); | |
1244 | ||
1245 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
1246 | { | |
1247 | store_unsigned_integer (valbuf, 4, byte_order, | |
1248 | value_address (arg)); | |
1249 | typecode = TYPE_CODE_PTR; | |
1250 | len = 4; | |
1251 | val = valbuf; | |
1252 | } | |
1253 | else if (abi == FRV_ABI_FDPIC | |
1254 | && len == 4 | |
1255 | && typecode == TYPE_CODE_PTR | |
1256 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
1257 | { | |
1258 | /* The FDPIC ABI requires function descriptors to be passed instead | |
1259 | of entry points. */ | |
1260 | CORE_ADDR addr = extract_unsigned_integer | |
1261 | (value_contents (arg), 4, byte_order); | |
1262 | addr = find_func_descr (gdbarch, addr); | |
1263 | store_unsigned_integer (valbuf, 4, byte_order, addr); | |
1264 | typecode = TYPE_CODE_PTR; | |
1265 | len = 4; | |
1266 | val = valbuf; | |
1267 | } | |
1268 | else | |
1269 | { | |
1270 | val = value_contents (arg); | |
1271 | } | |
1272 | ||
1273 | while (len > 0) | |
1274 | { | |
1275 | int partial_len = (len < 4 ? len : 4); | |
1276 | ||
1277 | if (argreg < 14) | |
1278 | { | |
1279 | regval = extract_unsigned_integer (val, partial_len, byte_order); | |
1280 | #if 0 | |
1281 | printf(" Argnum %d data %x -> reg %d\n", | |
1282 | argnum, (int) regval, argreg); | |
1283 | #endif | |
1284 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
1285 | ++argreg; | |
1286 | } | |
1287 | else | |
1288 | { | |
1289 | #if 0 | |
1290 | printf(" Argnum %d data %x -> offset %d (%x)\n", | |
1291 | argnum, *((int *)val), stack_offset, | |
1292 | (int) (sp + stack_offset)); | |
1293 | #endif | |
1294 | write_memory (sp + stack_offset, val, partial_len); | |
1295 | stack_offset += align_up (partial_len, 4); | |
1296 | } | |
1297 | len -= partial_len; | |
1298 | val += partial_len; | |
1299 | } | |
1300 | } | |
1301 | ||
1302 | /* Set the return address. For the frv, the return breakpoint is | |
1303 | always at BP_ADDR. */ | |
1304 | regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr); | |
1305 | ||
1306 | if (abi == FRV_ABI_FDPIC) | |
1307 | { | |
1308 | /* Set the GOT register for the FDPIC ABI. */ | |
1309 | regcache_cooked_write_unsigned | |
1310 | (regcache, first_gpr_regnum + 15, | |
1311 | frv_fdpic_find_global_pointer (func_addr)); | |
1312 | } | |
1313 | ||
1314 | /* Finally, update the SP register. */ | |
1315 | regcache_cooked_write_unsigned (regcache, sp_regnum, sp); | |
1316 | ||
1317 | return sp; | |
1318 | } | |
1319 | ||
1320 | static void | |
1321 | frv_store_return_value (struct type *type, struct regcache *regcache, | |
1322 | const gdb_byte *valbuf) | |
1323 | { | |
1324 | int len = TYPE_LENGTH (type); | |
1325 | ||
1326 | if (len <= 4) | |
1327 | { | |
1328 | bfd_byte val[4]; | |
1329 | memset (val, 0, sizeof (val)); | |
1330 | memcpy (val + (4 - len), valbuf, len); | |
1331 | regcache->cooked_write (8, val); | |
1332 | } | |
1333 | else if (len == 8) | |
1334 | { | |
1335 | regcache->cooked_write (8, valbuf); | |
1336 | regcache->cooked_write (9, (bfd_byte *) valbuf + 4); | |
1337 | } | |
1338 | else | |
1339 | internal_error (__FILE__, __LINE__, | |
1340 | _("Don't know how to return a %d-byte value."), len); | |
1341 | } | |
1342 | ||
1343 | static enum return_value_convention | |
1344 | frv_return_value (struct gdbarch *gdbarch, struct value *function, | |
1345 | struct type *valtype, struct regcache *regcache, | |
1346 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
1347 | { | |
1348 | int struct_return = TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
1349 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
1350 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY; | |
1351 | ||
1352 | if (writebuf != NULL) | |
1353 | { | |
1354 | gdb_assert (!struct_return); | |
1355 | frv_store_return_value (valtype, regcache, writebuf); | |
1356 | } | |
1357 | ||
1358 | if (readbuf != NULL) | |
1359 | { | |
1360 | gdb_assert (!struct_return); | |
1361 | frv_extract_return_value (valtype, regcache, readbuf); | |
1362 | } | |
1363 | ||
1364 | if (struct_return) | |
1365 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1366 | else | |
1367 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1368 | } | |
1369 | ||
1370 | /* Given a GDB frame, determine the address of the calling function's | |
1371 | frame. This will be used to create a new GDB frame struct. */ | |
1372 | ||
1373 | static void | |
1374 | frv_frame_this_id (struct frame_info *this_frame, | |
1375 | void **this_prologue_cache, struct frame_id *this_id) | |
1376 | { | |
1377 | struct frv_unwind_cache *info | |
1378 | = frv_frame_unwind_cache (this_frame, this_prologue_cache); | |
1379 | CORE_ADDR base; | |
1380 | CORE_ADDR func; | |
1381 | struct bound_minimal_symbol msym_stack; | |
1382 | struct frame_id id; | |
1383 | ||
1384 | /* The FUNC is easy. */ | |
1385 | func = get_frame_func (this_frame); | |
1386 | ||
1387 | /* Check if the stack is empty. */ | |
1388 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
1389 | if (msym_stack.minsym && info->base == BMSYMBOL_VALUE_ADDRESS (msym_stack)) | |
1390 | return; | |
1391 | ||
1392 | /* Hopefully the prologue analysis either correctly determined the | |
1393 | frame's base (which is the SP from the previous frame), or set | |
1394 | that base to "NULL". */ | |
1395 | base = info->prev_sp; | |
1396 | if (base == 0) | |
1397 | return; | |
1398 | ||
1399 | id = frame_id_build (base, func); | |
1400 | (*this_id) = id; | |
1401 | } | |
1402 | ||
1403 | static struct value * | |
1404 | frv_frame_prev_register (struct frame_info *this_frame, | |
1405 | void **this_prologue_cache, int regnum) | |
1406 | { | |
1407 | struct frv_unwind_cache *info | |
1408 | = frv_frame_unwind_cache (this_frame, this_prologue_cache); | |
1409 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
1410 | } | |
1411 | ||
1412 | static const struct frame_unwind frv_frame_unwind = { | |
1413 | NORMAL_FRAME, | |
1414 | default_frame_unwind_stop_reason, | |
1415 | frv_frame_this_id, | |
1416 | frv_frame_prev_register, | |
1417 | NULL, | |
1418 | default_frame_sniffer | |
1419 | }; | |
1420 | ||
1421 | static CORE_ADDR | |
1422 | frv_frame_base_address (struct frame_info *this_frame, void **this_cache) | |
1423 | { | |
1424 | struct frv_unwind_cache *info | |
1425 | = frv_frame_unwind_cache (this_frame, this_cache); | |
1426 | return info->base; | |
1427 | } | |
1428 | ||
1429 | static const struct frame_base frv_frame_base = { | |
1430 | &frv_frame_unwind, | |
1431 | frv_frame_base_address, | |
1432 | frv_frame_base_address, | |
1433 | frv_frame_base_address | |
1434 | }; | |
1435 | ||
1436 | static struct gdbarch * | |
1437 | frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1438 | { | |
1439 | struct gdbarch *gdbarch; | |
1440 | struct gdbarch_tdep *var; | |
1441 | int elf_flags = 0; | |
1442 | ||
1443 | /* Check to see if we've already built an appropriate architecture | |
1444 | object for this executable. */ | |
1445 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1446 | if (arches) | |
1447 | return arches->gdbarch; | |
1448 | ||
1449 | /* Select the right tdep structure for this variant. */ | |
1450 | var = new_variant (); | |
1451 | switch (info.bfd_arch_info->mach) | |
1452 | { | |
1453 | case bfd_mach_frv: | |
1454 | case bfd_mach_frvsimple: | |
1455 | case bfd_mach_fr300: | |
1456 | case bfd_mach_fr500: | |
1457 | case bfd_mach_frvtomcat: | |
1458 | case bfd_mach_fr550: | |
1459 | set_variant_num_gprs (var, 64); | |
1460 | set_variant_num_fprs (var, 64); | |
1461 | break; | |
1462 | ||
1463 | case bfd_mach_fr400: | |
1464 | case bfd_mach_fr450: | |
1465 | set_variant_num_gprs (var, 32); | |
1466 | set_variant_num_fprs (var, 32); | |
1467 | break; | |
1468 | ||
1469 | default: | |
1470 | /* Never heard of this variant. */ | |
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | /* Extract the ELF flags, if available. */ | |
1475 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
1476 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
1477 | ||
1478 | if (elf_flags & EF_FRV_FDPIC) | |
1479 | set_variant_abi_fdpic (var); | |
1480 | ||
1481 | if (elf_flags & EF_FRV_CPU_FR450) | |
1482 | set_variant_scratch_registers (var); | |
1483 | ||
1484 | gdbarch = gdbarch_alloc (&info, var); | |
1485 | ||
1486 | set_gdbarch_short_bit (gdbarch, 16); | |
1487 | set_gdbarch_int_bit (gdbarch, 32); | |
1488 | set_gdbarch_long_bit (gdbarch, 32); | |
1489 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1490 | set_gdbarch_float_bit (gdbarch, 32); | |
1491 | set_gdbarch_double_bit (gdbarch, 64); | |
1492 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1493 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1494 | ||
1495 | set_gdbarch_num_regs (gdbarch, frv_num_regs); | |
1496 | set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs); | |
1497 | ||
1498 | set_gdbarch_sp_regnum (gdbarch, sp_regnum); | |
1499 | set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum); | |
1500 | set_gdbarch_pc_regnum (gdbarch, pc_regnum); | |
1501 | ||
1502 | set_gdbarch_register_name (gdbarch, frv_register_name); | |
1503 | set_gdbarch_register_type (gdbarch, frv_register_type); | |
1504 | set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno); | |
1505 | ||
1506 | set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read); | |
1507 | set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write); | |
1508 | ||
1509 | set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue); | |
1510 | set_gdbarch_skip_main_prologue (gdbarch, frv_skip_main_prologue); | |
1511 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, frv_breakpoint::kind_from_pc); | |
1512 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, frv_breakpoint::bp_from_kind); | |
1513 | set_gdbarch_adjust_breakpoint_address | |
1514 | (gdbarch, frv_adjust_breakpoint_address); | |
1515 | ||
1516 | set_gdbarch_return_value (gdbarch, frv_return_value); | |
1517 | ||
1518 | /* Frame stuff. */ | |
1519 | set_gdbarch_frame_align (gdbarch, frv_frame_align); | |
1520 | frame_base_set_default (gdbarch, &frv_frame_base); | |
1521 | /* We set the sniffer lower down after the OSABI hooks have been | |
1522 | established. */ | |
1523 | ||
1524 | /* Settings for calling functions in the inferior. */ | |
1525 | set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call); | |
1526 | ||
1527 | /* Settings that should be unnecessary. */ | |
1528 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1529 | ||
1530 | /* Hardware watchpoint / breakpoint support. */ | |
1531 | switch (info.bfd_arch_info->mach) | |
1532 | { | |
1533 | case bfd_mach_frv: | |
1534 | case bfd_mach_frvsimple: | |
1535 | case bfd_mach_fr300: | |
1536 | case bfd_mach_fr500: | |
1537 | case bfd_mach_frvtomcat: | |
1538 | /* fr500-style hardware debugging support. */ | |
1539 | var->num_hw_watchpoints = 4; | |
1540 | var->num_hw_breakpoints = 4; | |
1541 | break; | |
1542 | ||
1543 | case bfd_mach_fr400: | |
1544 | case bfd_mach_fr450: | |
1545 | /* fr400-style hardware debugging support. */ | |
1546 | var->num_hw_watchpoints = 2; | |
1547 | var->num_hw_breakpoints = 4; | |
1548 | break; | |
1549 | ||
1550 | default: | |
1551 | /* Otherwise, assume we don't have hardware debugging support. */ | |
1552 | var->num_hw_watchpoints = 0; | |
1553 | var->num_hw_breakpoints = 0; | |
1554 | break; | |
1555 | } | |
1556 | ||
1557 | if (frv_abi (gdbarch) == FRV_ABI_FDPIC) | |
1558 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, | |
1559 | frv_convert_from_func_ptr_addr); | |
1560 | ||
1561 | set_solib_ops (gdbarch, &frv_so_ops); | |
1562 | ||
1563 | /* Hook in ABI-specific overrides, if they have been registered. */ | |
1564 | gdbarch_init_osabi (info, gdbarch); | |
1565 | ||
1566 | /* Set the fallback (prologue based) frame sniffer. */ | |
1567 | frame_unwind_append_unwinder (gdbarch, &frv_frame_unwind); | |
1568 | ||
1569 | /* Enable TLS support. */ | |
1570 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
1571 | frv_fetch_objfile_link_map); | |
1572 | ||
1573 | return gdbarch; | |
1574 | } | |
1575 | ||
1576 | void | |
1577 | _initialize_frv_tdep (void) | |
1578 | { | |
1579 | register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init); | |
1580 | } |