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1/* Intel 387 floating point stuff.
2
3 Copyright (C) 1988-2025 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "extract-store-integer.h"
21#include "frame.h"
22#include "gdbcore.h"
23#include "inferior.h"
24#include "language.h"
25#include "regcache.h"
26#include "target-float.h"
27#include "value.h"
28
29#include "i386-tdep.h"
30#include "i387-tdep.h"
31#include "gdbsupport/x86-xstate.h"
32
33/* Print the floating point number specified by RAW. */
34
35static void
36print_i387_value (struct gdbarch *gdbarch,
37 const gdb_byte *raw, struct ui_file *file)
38{
39 /* We try to print 19 digits. The last digit may or may not contain
40 garbage, but we'd better print one too many. We need enough room
41 to print the value, 1 position for the sign, 1 for the decimal
42 point, 19 for the digits and 6 for the exponent adds up to 27. */
43 const struct type *type = i387_ext_type (gdbarch);
44 std::string str = target_float_to_string (raw, type, " %-+27.19g");
45 gdb_printf (file, "%s", str.c_str ());
46}
47
48/* Print the classification for the register contents RAW. */
49
50static void
51print_i387_ext (struct gdbarch *gdbarch,
52 const gdb_byte *raw, struct ui_file *file)
53{
54 int sign;
55 int integer;
56 unsigned int exponent;
57 unsigned long fraction[2];
58
59 sign = raw[9] & 0x80;
60 integer = raw[7] & 0x80;
61 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
62 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
63 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
64 | (raw[5] << 8) | raw[4]);
65
66 if (exponent == 0x7fff && integer)
67 {
68 if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000)
69 /* Infinity. */
70 gdb_printf (file, " %cInf", (sign ? '-' : '+'));
71 else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000)
72 /* Real Indefinite (QNaN). */
73 gdb_puts (" Real Indefinite (QNaN)", file);
74 else if (fraction[1] & 0x40000000)
75 /* QNaN. */
76 gdb_puts (" QNaN", file);
77 else
78 /* SNaN. */
79 gdb_puts (" SNaN", file);
80 }
81 else if (exponent < 0x7fff && exponent > 0x0000 && integer)
82 /* Normal. */
83 print_i387_value (gdbarch, raw, file);
84 else if (exponent == 0x0000)
85 {
86 /* Denormal or zero. */
87 print_i387_value (gdbarch, raw, file);
88
89 if (integer)
90 /* Pseudo-denormal. */
91 gdb_puts (" Pseudo-denormal", file);
92 else if (fraction[0] || fraction[1])
93 /* Denormal. */
94 gdb_puts (" Denormal", file);
95 }
96 else
97 /* Unsupported. */
98 gdb_puts (" Unsupported", file);
99}
100
101/* Print the status word STATUS. If STATUS_P is false, then STATUS
102 was unavailable. */
103
104static void
105print_i387_status_word (int status_p,
106 unsigned int status, struct ui_file *file)
107{
108 gdb_printf (file, "Status Word: ");
109 if (!status_p)
110 {
111 gdb_printf (file, "%s\n", _("<unavailable>"));
112 return;
113 }
114
115 gdb_printf (file, "%s", hex_string_custom (status, 4));
116 gdb_puts (" ", file);
117 gdb_printf (file, " %s", (status & 0x0001) ? "IE" : " ");
118 gdb_printf (file, " %s", (status & 0x0002) ? "DE" : " ");
119 gdb_printf (file, " %s", (status & 0x0004) ? "ZE" : " ");
120 gdb_printf (file, " %s", (status & 0x0008) ? "OE" : " ");
121 gdb_printf (file, " %s", (status & 0x0010) ? "UE" : " ");
122 gdb_printf (file, " %s", (status & 0x0020) ? "PE" : " ");
123 gdb_puts (" ", file);
124 gdb_printf (file, " %s", (status & 0x0080) ? "ES" : " ");
125 gdb_puts (" ", file);
126 gdb_printf (file, " %s", (status & 0x0040) ? "SF" : " ");
127 gdb_puts (" ", file);
128 gdb_printf (file, " %s", (status & 0x0100) ? "C0" : " ");
129 gdb_printf (file, " %s", (status & 0x0200) ? "C1" : " ");
130 gdb_printf (file, " %s", (status & 0x0400) ? "C2" : " ");
131 gdb_printf (file, " %s", (status & 0x4000) ? "C3" : " ");
132
133 gdb_puts ("\n", file);
134
135 gdb_printf (file,
136 " TOP: %d\n", ((status >> 11) & 7));
137}
138
139/* Print the control word CONTROL. If CONTROL_P is false, then
140 CONTROL was unavailable. */
141
142static void
143print_i387_control_word (int control_p,
144 unsigned int control, struct ui_file *file)
145{
146 gdb_printf (file, "Control Word: ");
147 if (!control_p)
148 {
149 gdb_printf (file, "%s\n", _("<unavailable>"));
150 return;
151 }
152
153 gdb_printf (file, "%s", hex_string_custom (control, 4));
154 gdb_puts (" ", file);
155 gdb_printf (file, " %s", (control & 0x0001) ? "IM" : " ");
156 gdb_printf (file, " %s", (control & 0x0002) ? "DM" : " ");
157 gdb_printf (file, " %s", (control & 0x0004) ? "ZM" : " ");
158 gdb_printf (file, " %s", (control & 0x0008) ? "OM" : " ");
159 gdb_printf (file, " %s", (control & 0x0010) ? "UM" : " ");
160 gdb_printf (file, " %s", (control & 0x0020) ? "PM" : " ");
161
162 gdb_puts ("\n", file);
163
164 gdb_puts (" PC: ", file);
165 switch ((control >> 8) & 3)
166 {
167 case 0:
168 gdb_puts ("Single Precision (24-bits)\n", file);
169 break;
170 case 1:
171 gdb_puts ("Reserved\n", file);
172 break;
173 case 2:
174 gdb_puts ("Double Precision (53-bits)\n", file);
175 break;
176 case 3:
177 gdb_puts ("Extended Precision (64-bits)\n", file);
178 break;
179 }
180
181 gdb_puts (" RC: ", file);
182 switch ((control >> 10) & 3)
183 {
184 case 0:
185 gdb_puts ("Round to nearest\n", file);
186 break;
187 case 1:
188 gdb_puts ("Round down\n", file);
189 break;
190 case 2:
191 gdb_puts ("Round up\n", file);
192 break;
193 case 3:
194 gdb_puts ("Round toward zero\n", file);
195 break;
196 }
197}
198
199/* Print out the i387 floating point state. Note that we ignore FRAME
200 in the code below. That's OK since floating-point registers are
201 never saved on the stack. */
202
203void
204i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
205 const frame_info_ptr &frame, const char *args)
206{
207 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
208 ULONGEST fctrl;
209 int fctrl_p;
210 ULONGEST fstat;
211 int fstat_p;
212 ULONGEST ftag;
213 int ftag_p;
214 ULONGEST fiseg;
215 int fiseg_p;
216 ULONGEST fioff;
217 int fioff_p;
218 ULONGEST foseg;
219 int foseg_p;
220 ULONGEST fooff;
221 int fooff_p;
222 ULONGEST fop;
223 int fop_p;
224 int fpreg;
225 int top;
226
227 gdb_assert (gdbarch == get_frame_arch (frame));
228
229 fctrl_p = read_frame_register_unsigned (frame,
230 I387_FCTRL_REGNUM (tdep), &fctrl);
231 fstat_p = read_frame_register_unsigned (frame,
232 I387_FSTAT_REGNUM (tdep), &fstat);
233 ftag_p = read_frame_register_unsigned (frame,
234 I387_FTAG_REGNUM (tdep), &ftag);
235 fiseg_p = read_frame_register_unsigned (frame,
236 I387_FISEG_REGNUM (tdep), &fiseg);
237 fioff_p = read_frame_register_unsigned (frame,
238 I387_FIOFF_REGNUM (tdep), &fioff);
239 foseg_p = read_frame_register_unsigned (frame,
240 I387_FOSEG_REGNUM (tdep), &foseg);
241 fooff_p = read_frame_register_unsigned (frame,
242 I387_FOOFF_REGNUM (tdep), &fooff);
243 fop_p = read_frame_register_unsigned (frame,
244 I387_FOP_REGNUM (tdep), &fop);
245
246 if (fstat_p)
247 {
248 top = ((fstat >> 11) & 7);
249
250 for (fpreg = 7; fpreg >= 0; fpreg--)
251 {
252 struct value *regval;
253 int regnum;
254 int i;
255 int tag = -1;
256
257 gdb_printf (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
258
259 if (ftag_p)
260 {
261 tag = (ftag >> (fpreg * 2)) & 3;
262
263 switch (tag)
264 {
265 case 0:
266 gdb_puts ("Valid ", file);
267 break;
268 case 1:
269 gdb_puts ("Zero ", file);
270 break;
271 case 2:
272 gdb_puts ("Special ", file);
273 break;
274 case 3:
275 gdb_puts ("Empty ", file);
276 break;
277 }
278 }
279 else
280 gdb_puts ("Unknown ", file);
281
282 regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep);
283 regval = get_frame_register_value (frame, regnum);
284
285 if (regval->entirely_available ())
286 {
287 const gdb_byte *raw = regval->contents ().data ();
288
289 gdb_puts ("0x", file);
290 for (i = 9; i >= 0; i--)
291 gdb_printf (file, "%02x", raw[i]);
292
293 if (tag != -1 && tag != 3)
294 print_i387_ext (gdbarch, raw, file);
295 }
296 else
297 gdb_printf (file, "%s", _("<unavailable>"));
298
299 gdb_puts ("\n", file);
300 }
301 }
302
303 gdb_puts ("\n", file);
304 print_i387_status_word (fstat_p, fstat, file);
305 print_i387_control_word (fctrl_p, fctrl, file);
306 gdb_printf (file, "Tag Word: %s\n",
307 ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>"));
308 gdb_printf (file, "Instruction Pointer: %s:",
309 fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>"));
310 gdb_printf (file, "%s\n",
311 fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>"));
312 gdb_printf (file, "Operand Pointer: %s:",
313 foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>"));
314 gdb_printf (file, "%s\n",
315 fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>"));
316 gdb_printf (file, "Opcode: %s\n",
317 fop_p
318 ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4))
319 : _("<unavailable>"));
320}
321\f
322
323/* Return nonzero if a value of type TYPE stored in register REGNUM
324 needs any special handling. */
325
326int
327i387_convert_register_p (struct gdbarch *gdbarch, int regnum,
328 struct type *type)
329{
330 if (i386_fp_regnum_p (gdbarch, regnum))
331 {
332 /* Floating point registers must be converted unless we are
333 accessing them in their hardware type or TYPE is not float. */
334 if (type == i387_ext_type (gdbarch)
335 || type->code () != TYPE_CODE_FLT)
336 return 0;
337 else
338 return 1;
339 }
340
341 return 0;
342}
343
344/* Read a value of type TYPE from register REGNUM in frame FRAME, and
345 return its contents in TO. */
346
347int
348i387_register_to_value (const frame_info_ptr &frame, int regnum,
349 struct type *type, gdb_byte *to,
350 int *optimizedp, int *unavailablep)
351{
352 struct gdbarch *gdbarch = get_frame_arch (frame);
353 gdb_byte from[I386_MAX_REGISTER_SIZE];
354
355 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
356
357 /* We only support floating-point values. */
358 if (type->code () != TYPE_CODE_FLT)
359 {
360 warning (_("Cannot convert floating-point register value "
361 "to non-floating-point type."));
362 *optimizedp = *unavailablep = 0;
363 return 0;
364 }
365
366 /* Convert to TYPE. */
367 auto from_view
368 = gdb::make_array_view (from, register_size (gdbarch, regnum));
369 frame_info_ptr next_frame = get_next_frame_sentinel_okay (frame);
370 if (!get_frame_register_bytes (next_frame, regnum, 0, from_view, optimizedp,
371 unavailablep))
372 return 0;
373
374 target_float_convert (from, i387_ext_type (gdbarch), to, type);
375 *optimizedp = *unavailablep = 0;
376 return 1;
377}
378
379/* Write the contents FROM of a value of type TYPE into register
380 REGNUM in frame FRAME. */
381
382void
383i387_value_to_register (const frame_info_ptr &frame, int regnum,
384 struct type *type, const gdb_byte *from)
385{
386 struct gdbarch *gdbarch = get_frame_arch (frame);
387 gdb_byte to[I386_MAX_REGISTER_SIZE];
388
389 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
390
391 /* We only support floating-point values. */
392 if (type->code () != TYPE_CODE_FLT)
393 {
394 warning (_("Cannot convert non-floating-point type "
395 "to floating-point register value."));
396 return;
397 }
398
399 /* Convert from TYPE. */
400 struct type *to_type = i387_ext_type (gdbarch);
401 target_float_convert (from, type, to, to_type);
402 auto to_view = gdb::make_array_view (to, to_type->length ());
403 put_frame_register (get_next_frame_sentinel_okay (frame), regnum, to_view);
404}
405\f
406
407/* Handle FSAVE and FXSAVE formats. */
408
409/* At fsave_offset[REGNUM] you'll find the offset to the location in
410 the data structure used by the "fsave" instruction where GDB
411 register REGNUM is stored. */
412
413static int fsave_offset[] =
414{
415 28 + 0 * 10, /* %st(0) ... */
416 28 + 1 * 10,
417 28 + 2 * 10,
418 28 + 3 * 10,
419 28 + 4 * 10,
420 28 + 5 * 10,
421 28 + 6 * 10,
422 28 + 7 * 10, /* ... %st(7). */
423 0, /* `fctrl' (16 bits). */
424 4, /* `fstat' (16 bits). */
425 8, /* `ftag' (16 bits). */
426 16, /* `fiseg' (16 bits). */
427 12, /* `fioff'. */
428 24, /* `foseg' (16 bits). */
429 20, /* `fooff'. */
430 18 /* `fop' (bottom 11 bits). */
431};
432
433#define FSAVE_ADDR(tdep, fsave, regnum) \
434 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
435\f
436
437/* Fill register REGNUM in REGCACHE with the appropriate value from
438 *FSAVE. This function masks off any of the reserved bits in
439 *FSAVE. */
440
441void
442i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave)
443{
444 struct gdbarch *gdbarch = regcache->arch ();
445 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
446 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
447 const gdb_byte *regs = (const gdb_byte *) fsave;
448 int i;
449
450 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
451
452 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
453 if (regnum == -1 || regnum == i)
454 {
455 if (fsave == NULL)
456 {
457 regcache->raw_supply (i, NULL);
458 continue;
459 }
460
461 /* Most of the FPU control registers occupy only 16 bits in the
462 fsave area. Give those a special treatment. */
463 if (i >= I387_FCTRL_REGNUM (tdep)
464 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
465 {
466 gdb_byte val[4];
467
468 memcpy (val, FSAVE_ADDR (tdep, regs, i), 2);
469 val[2] = val[3] = 0;
470 if (i == I387_FOP_REGNUM (tdep))
471 val[1] &= ((1 << 3) - 1);
472 regcache->raw_supply (i, val);
473 }
474 else
475 regcache->raw_supply (i, FSAVE_ADDR (tdep, regs, i));
476 }
477
478 /* Provide dummy values for the SSE registers. */
479 for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
480 if (regnum == -1 || regnum == i)
481 regcache->raw_supply (i, NULL);
482 if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep))
483 {
484 gdb_byte buf[4];
485
486 store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL);
487 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf);
488 }
489}
490
491/* Fill register REGNUM (if it is a floating-point register) in *FSAVE
492 with the value from REGCACHE. If REGNUM is -1, do this for all
493 registers. This function doesn't touch any of the reserved bits in
494 *FSAVE. */
495
496void
497i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave)
498{
499 gdbarch *arch = regcache->arch ();
500 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
501 gdb_byte *regs = (gdb_byte *) fsave;
502 int i;
503
504 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
505
506 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
507 if (regnum == -1 || regnum == i)
508 {
509 /* Most of the FPU control registers occupy only 16 bits in
510 the fsave area. Give those a special treatment. */
511 if (i >= I387_FCTRL_REGNUM (tdep)
512 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
513 {
514 gdb_byte buf[4];
515
516 regcache->raw_collect (i, buf);
517
518 if (i == I387_FOP_REGNUM (tdep))
519 {
520 /* The opcode occupies only 11 bits. Make sure we
521 don't touch the other bits. */
522 buf[1] &= ((1 << 3) - 1);
523 buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
524 }
525 memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2);
526 }
527 else
528 regcache->raw_collect (i, FSAVE_ADDR (tdep, regs, i));
529 }
530}
531\f
532
533/* At fxsave_offset[REGNUM] you'll find the offset to the location in
534 the data structure used by the "fxsave" instruction where GDB
535 register REGNUM is stored. */
536
537static int fxsave_offset[] =
538{
539 32, /* %st(0) through ... */
540 48,
541 64,
542 80,
543 96,
544 112,
545 128,
546 144, /* ... %st(7) (80 bits each). */
547 0, /* `fctrl' (16 bits). */
548 2, /* `fstat' (16 bits). */
549 4, /* `ftag' (16 bits). */
550 12, /* `fiseg' (16 bits). */
551 8, /* `fioff'. */
552 20, /* `foseg' (16 bits). */
553 16, /* `fooff'. */
554 6, /* `fop' (bottom 11 bits). */
555 160 + 0 * 16, /* %xmm0 through ... */
556 160 + 1 * 16,
557 160 + 2 * 16,
558 160 + 3 * 16,
559 160 + 4 * 16,
560 160 + 5 * 16,
561 160 + 6 * 16,
562 160 + 7 * 16,
563 160 + 8 * 16,
564 160 + 9 * 16,
565 160 + 10 * 16,
566 160 + 11 * 16,
567 160 + 12 * 16,
568 160 + 13 * 16,
569 160 + 14 * 16,
570 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
571};
572
573#define FXSAVE_ADDR(tdep, fxsave, regnum) \
574 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
575
576/* We made an unfortunate choice in putting %mxcsr after the SSE
577 registers %xmm0-%xmm7 instead of before, since it makes supporting
578 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
579 don't include the offset for %mxcsr here above. */
580
581#define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
582
583static int i387_tag (const gdb_byte *raw);
584\f
585
586/* Fill register REGNUM in REGCACHE with the appropriate
587 floating-point or SSE register value from *FXSAVE. This function
588 masks off any of the reserved bits in *FXSAVE. */
589
590void
591i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave)
592{
593 gdbarch *arch = regcache->arch ();
594 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
595 const gdb_byte *regs = (const gdb_byte *) fxsave;
596 int i;
597
598 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
599 gdb_assert (tdep->num_xmm_regs > 0);
600
601 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
602 if (regnum == -1 || regnum == i)
603 {
604 if (regs == NULL)
605 {
606 regcache->raw_supply (i, NULL);
607 continue;
608 }
609
610 /* Most of the FPU control registers occupy only 16 bits in
611 the fxsave area. Give those a special treatment. */
612 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
613 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
614 {
615 gdb_byte val[4];
616
617 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
618 val[2] = val[3] = 0;
619 if (i == I387_FOP_REGNUM (tdep))
620 val[1] &= ((1 << 3) - 1);
621 else if (i== I387_FTAG_REGNUM (tdep))
622 {
623 /* The fxsave area contains a simplified version of
624 the tag word. We have to look at the actual 80-bit
625 FP data to recreate the traditional i387 tag word. */
626
627 unsigned long ftag = 0;
628 int fpreg;
629 int top;
630
631 top = ((FXSAVE_ADDR (tdep, regs,
632 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
633 top &= 0x7;
634
635 for (fpreg = 7; fpreg >= 0; fpreg--)
636 {
637 int tag;
638
639 if (val[0] & (1 << fpreg))
640 {
641 int thisreg = (fpreg + 8 - top) % 8
642 + I387_ST0_REGNUM (tdep);
643 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
644 }
645 else
646 tag = 3; /* Empty */
647
648 ftag |= tag << (2 * fpreg);
649 }
650 val[0] = ftag & 0xff;
651 val[1] = (ftag >> 8) & 0xff;
652 }
653 regcache->raw_supply (i, val);
654 }
655 else
656 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
657 }
658
659 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
660 {
661 if (regs == NULL)
662 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), NULL);
663 else
664 regcache->raw_supply (I387_MXCSR_REGNUM (tdep),
665 FXSAVE_MXCSR_ADDR (regs));
666 }
667}
668
669/* Fill register REGNUM (if it is a floating-point or SSE register) in
670 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
671 all registers. This function doesn't touch any of the reserved
672 bits in *FXSAVE. */
673
674void
675i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave)
676{
677 gdbarch *arch = regcache->arch ();
678 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
679 gdb_byte *regs = (gdb_byte *) fxsave;
680 int i;
681
682 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
683 gdb_assert (tdep->num_xmm_regs > 0);
684
685 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
686 if (regnum == -1 || regnum == i)
687 {
688 /* Most of the FPU control registers occupy only 16 bits in
689 the fxsave area. Give those a special treatment. */
690 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
691 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
692 {
693 gdb_byte buf[4];
694
695 regcache->raw_collect (i, buf);
696
697 if (i == I387_FOP_REGNUM (tdep))
698 {
699 /* The opcode occupies only 11 bits. Make sure we
700 don't touch the other bits. */
701 buf[1] &= ((1 << 3) - 1);
702 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
703 }
704 else if (i == I387_FTAG_REGNUM (tdep))
705 {
706 /* Converting back is much easier. */
707
708 unsigned short ftag;
709 int fpreg;
710
711 ftag = (buf[1] << 8) | buf[0];
712 buf[0] = 0;
713 buf[1] = 0;
714
715 for (fpreg = 7; fpreg >= 0; fpreg--)
716 {
717 int tag = (ftag >> (fpreg * 2)) & 3;
718
719 if (tag != 3)
720 buf[0] |= (1 << fpreg);
721 }
722 }
723 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
724 }
725 else
726 regcache->raw_collect (i, FXSAVE_ADDR (tdep, regs, i));
727 }
728
729 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
730 regcache->raw_collect (I387_MXCSR_REGNUM (tdep),
731 FXSAVE_MXCSR_ADDR (regs));
732}
733
734/* `xstate_bv' is at byte offset 512. */
735#define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
736
737/* At xsave_avxh_offset[REGNUM] you'll find the relative offset within
738 the AVX region of the XSAVE extended state where the upper 128bits
739 of GDB register YMM0 + REGNUM is stored. */
740
741static int xsave_avxh_offset[] =
742{
743 0 * 16, /* Upper 128bit of %ymm0 through ... */
744 1 * 16,
745 2 * 16,
746 3 * 16,
747 4 * 16,
748 5 * 16,
749 6 * 16,
750 7 * 16,
751 8 * 16,
752 9 * 16,
753 10 * 16,
754 11 * 16,
755 12 * 16,
756 13 * 16,
757 14 * 16,
758 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
759};
760
761#define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
762 (xsave + (tdep)->xsave_layout.avx_offset \
763 + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
764
765/* At xsave_ymm_h_avx512_offset[REGNUM] you'll find the relative offset
766 within the ZMM region of the XSAVE extended state where the second
767 128bits of GDB register YMM16 + REGNUM is stored. */
768
769static int xsave_ymm_h_avx512_offset[] =
770{
771 16 + 0 * 64, /* %ymm16 through... */
772 16 + 1 * 64,
773 16 + 2 * 64,
774 16 + 3 * 64,
775 16 + 4 * 64,
776 16 + 5 * 64,
777 16 + 6 * 64,
778 16 + 7 * 64,
779 16 + 8 * 64,
780 16 + 9 * 64,
781 16 + 10 * 64,
782 16 + 11 * 64,
783 16 + 12 * 64,
784 16 + 13 * 64,
785 16 + 14 * 64,
786 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
787};
788
789#define XSAVE_YMM_H_AVX512_ADDR(tdep, xsave, regnum) \
790 (xsave + (tdep)->xsave_layout.zmm_offset \
791 + xsave_ymm_h_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
792
793/* At xsave_xmm_avx512_offset[REGNUM] you'll find the relative offset
794 within the ZMM region of the XSAVE extended state where the first
795 128bits of GDB register XMM16 + REGNUM is stored. */
796
797static int xsave_xmm_avx512_offset[] =
798{
799 0 * 64, /* %xmm16 through... */
800 1 * 64,
801 2 * 64,
802 3 * 64,
803 4 * 64,
804 5 * 64,
805 6 * 64,
806 7 * 64,
807 8 * 64,
808 9 * 64,
809 10 * 64,
810 11 * 64,
811 12 * 64,
812 13 * 64,
813 14 * 64,
814 15 * 64 /* ... %xmm31 (128 bits each). */
815};
816
817#define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \
818 (xsave + (tdep)->xsave_layout.zmm_offset \
819 + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)])
820
821/* At xsave_avx512_k_offset[REGNUM] you'll find the relative offset
822 within the K region of the XSAVE extended state where the AVX512
823 opmask register K0 + REGNUM is stored. */
824
825static int xsave_avx512_k_offset[] =
826{
827 0 * 8, /* %k0 through... */
828 1 * 8,
829 2 * 8,
830 3 * 8,
831 4 * 8,
832 5 * 8,
833 6 * 8,
834 7 * 8 /* %k7 (64 bits each). */
835};
836
837#define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \
838 (xsave + (tdep)->xsave_layout.k_offset \
839 + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)])
840
841
842/* At xsave_avx512_zmm0_h_offset[REGNUM] you find the relative offset
843 within the ZMM_H region of the XSAVE extended state where the upper
844 256bits of the GDB register ZMM0 + REGNUM is stored. */
845
846static int xsave_avx512_zmm0_h_offset[] =
847{
848 0 * 32, /* Upper 256bit of %zmmh0 through... */
849 1 * 32,
850 2 * 32,
851 3 * 32,
852 4 * 32,
853 5 * 32,
854 6 * 32,
855 7 * 32,
856 8 * 32,
857 9 * 32,
858 10 * 32,
859 11 * 32,
860 12 * 32,
861 13 * 32,
862 14 * 32,
863 15 * 32 /* Upper 256bit of... %zmmh15 (256 bits each). */
864};
865
866#define XSAVE_AVX512_ZMM0_H_ADDR(tdep, xsave, regnum) \
867 (xsave + (tdep)->xsave_layout.zmm_h_offset \
868 + xsave_avx512_zmm0_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)])
869
870/* At xsave_avx512_zmm16_h_offset[REGNUM] you find the relative offset
871 within the ZMM_H region of the XSAVE extended state where the upper
872 256bits of the GDB register ZMM16 + REGNUM is stored. */
873
874static int xsave_avx512_zmm16_h_offset[] =
875{
876 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */
877 32 + 1 * 64,
878 32 + 2 * 64,
879 32 + 3 * 64,
880 32 + 4 * 64,
881 32 + 5 * 64,
882 32 + 6 * 64,
883 32 + 7 * 64,
884 32 + 8 * 64,
885 32 + 9 * 64,
886 32 + 10 * 64,
887 32 + 11 * 64,
888 32 + 12 * 64,
889 32 + 13 * 64,
890 32 + 14 * 64,
891 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */
892};
893
894#define XSAVE_AVX512_ZMM16_H_ADDR(tdep, xsave, regnum) \
895 (xsave + (tdep)->xsave_layout.zmm_offset \
896 + xsave_avx512_zmm16_h_offset[regnum - I387_ZMM16H_REGNUM (tdep)])
897
898/* At xsave_pkeys_offset[REGNUM] you'll find the relative offset
899 within the PKEYS region of the XSAVE extended state where the PKRU
900 register is stored. */
901
902static int xsave_pkeys_offset[] =
903{
904 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by
905 instructions and applications). */
906};
907
908#define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \
909 (xsave + (tdep)->xsave_layout.pkru_offset \
910 + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)])
911
912
913/* See i387-tdep.h. */
914
915bool
916i387_guess_xsave_layout (uint64_t xcr0, size_t xsave_size,
917 x86_xsave_layout &layout)
918{
919 if (HAS_PKRU (xcr0) && xsave_size == 2696)
920 {
921 /* Intel CPUs supporting PKRU. */
922 layout.avx_offset = 576;
923 layout.k_offset = 1088;
924 layout.zmm_h_offset = 1152;
925 layout.zmm_offset = 1664;
926 layout.pkru_offset = 2688;
927 }
928 else if (HAS_PKRU (xcr0) && xsave_size == 2440)
929 {
930 /* AMD CPUs supporting PKRU. */
931 layout.avx_offset = 576;
932 layout.k_offset = 832;
933 layout.zmm_h_offset = 896;
934 layout.zmm_offset = 1408;
935 layout.pkru_offset = 2432;
936 }
937 else if (HAS_AVX512 (xcr0) && xsave_size == 2688)
938 {
939 /* Intel CPUs supporting AVX512. */
940 layout.avx_offset = 576;
941 layout.k_offset = 1088;
942 layout.zmm_h_offset = 1152;
943 layout.zmm_offset = 1664;
944 }
945 /* As MPX has been removed, we need the additional check
946 (xsave_size == 1088) to allow reading AVX registers from corefiles
947 on CPUs with MPX as the highest supported feature. */
948 else if (HAS_AVX (xcr0) && (xsave_size == 832 || xsave_size == 1088))
949 {
950 /* Intel and AMD CPUs supporting AVX. */
951 layout.avx_offset = 576;
952 }
953 else
954 return false;
955
956 layout.sizeof_xsave = xsave_size;
957 return true;
958}
959
960/* See i387-tdep.h. */
961
962x86_xsave_layout
963i387_fallback_xsave_layout (uint64_t xcr0)
964{
965 x86_xsave_layout layout;
966
967 if (HAS_PKRU (xcr0))
968 {
969 /* Intel CPUs supporting PKRU. */
970 layout.avx_offset = 576;
971 layout.k_offset = 1088;
972 layout.zmm_h_offset = 1152;
973 layout.zmm_offset = 1664;
974 layout.pkru_offset = 2688;
975 layout.sizeof_xsave = 2696;
976 }
977 else if (HAS_AVX512 (xcr0))
978 {
979 /* Intel CPUs supporting AVX512. */
980 layout.avx_offset = 576;
981 layout.k_offset = 1088;
982 layout.zmm_h_offset = 1152;
983 layout.zmm_offset = 1664;
984 layout.sizeof_xsave = 2688;
985 }
986 else if (HAS_AVX (xcr0))
987 {
988 /* Intel and AMD CPUs supporting AVX. */
989 layout.avx_offset = 576;
990 layout.sizeof_xsave = 832;
991 }
992
993 return layout;
994}
995
996/* Extract from XSAVE a bitset of the features that are available on the
997 target, but which have not yet been enabled. */
998
999ULONGEST
1000i387_xsave_get_clear_bv (struct gdbarch *gdbarch, const void *xsave)
1001{
1002 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1003 const gdb_byte *regs = (const gdb_byte *) xsave;
1004 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
1005
1006 /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */
1007 ULONGEST xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1008 8, byte_order);
1009
1010 /* Clear part in vector registers if its bit in xstat_bv is zero. */
1011 ULONGEST clear_bv = (~(xstate_bv)) & tdep->xcr0;
1012
1013 return clear_bv;
1014}
1015
1016/* Similar to i387_supply_fxsave, but use XSAVE extended state. */
1017
1018void
1019i387_supply_xsave (struct regcache *regcache, int regnum,
1020 const void *xsave)
1021{
1022 struct gdbarch *gdbarch = regcache->arch ();
1023 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1024 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
1025 const gdb_byte *regs = (const gdb_byte *) xsave;
1026 int i;
1027 /* In 64-bit mode the split between "low" and "high" ZMM registers is at
1028 ZMM16. Outside of 64-bit mode there are no "high" ZMM registers at all.
1029 Precalculate the number to be used for the split point, with the all
1030 registers in the "low" portion outside of 64-bit mode. */
1031 unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep)
1032 + std::min (tdep->num_zmm_regs, 16);
1033 ULONGEST clear_bv;
1034 enum
1035 {
1036 none = 0x0,
1037 x87 = 0x1,
1038 sse = 0x2,
1039 avxh = 0x4,
1040 avx512_k = 0x8,
1041 avx512_zmm0_h = 0x10,
1042 avx512_zmm16_h = 0x20,
1043 avx512_ymmh_avx512 = 0x40,
1044 avx512_xmm_avx512 = 0x80,
1045 pkeys = 0x100,
1046 all = x87 | sse | avxh | avx512_k | avx512_zmm0_h | avx512_zmm16_h
1047 | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
1048 } regclass;
1049
1050 gdb_assert (regs != NULL);
1051 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
1052 gdb_assert (tdep->num_xmm_regs > 0);
1053
1054 if (regnum == -1)
1055 regclass = all;
1056 else if (regnum >= I387_PKRU_REGNUM (tdep)
1057 && regnum < I387_PKEYSEND_REGNUM (tdep))
1058 regclass = pkeys;
1059 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
1060 && regnum < I387_ZMM16H_REGNUM (tdep))
1061 regclass = avx512_zmm0_h;
1062 else if (regnum >= I387_ZMM16H_REGNUM (tdep)
1063 && regnum < I387_ZMMENDH_REGNUM (tdep))
1064 regclass = avx512_zmm16_h;
1065 else if (regnum >= I387_K0_REGNUM (tdep)
1066 && regnum < I387_KEND_REGNUM (tdep))
1067 regclass = avx512_k;
1068 else if (regnum >= I387_YMM16H_REGNUM (tdep)
1069 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
1070 regclass = avx512_ymmh_avx512;
1071 else if (regnum >= I387_XMM16_REGNUM (tdep)
1072 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
1073 regclass = avx512_xmm_avx512;
1074 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1075 && regnum < I387_YMMENDH_REGNUM (tdep))
1076 regclass = avxh;
1077 else if (regnum >= I387_XMM0_REGNUM (tdep)
1078 && regnum < I387_MXCSR_REGNUM (tdep))
1079 regclass = sse;
1080 else if (regnum >= I387_ST0_REGNUM (tdep)
1081 && regnum < I387_FCTRL_REGNUM (tdep))
1082 regclass = x87;
1083 else
1084 regclass = none;
1085
1086 clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave);
1087
1088 /* With the delayed xsave mechanism, in between the program
1089 starting, and the program accessing the vector registers for the
1090 first time, the register's values are invalid. The kernel
1091 initializes register states to zero when they are set the first
1092 time in a program. This means that from the user-space programs'
1093 perspective, it's the same as if the registers have always been
1094 zero from the start of the program. Therefore, the debugger
1095 should provide the same illusion to the user. */
1096
1097 switch (regclass)
1098 {
1099 case none:
1100 break;
1101
1102 case pkeys:
1103 if ((clear_bv & X86_XSTATE_PKRU))
1104 regcache->raw_supply_zeroed (regnum);
1105 else
1106 regcache->raw_supply (regnum, XSAVE_PKEYS_ADDR (tdep, regs, regnum));
1107 return;
1108
1109 case avx512_zmm0_h:
1110 if ((clear_bv & X86_XSTATE_ZMM_H))
1111 regcache->raw_supply_zeroed (regnum);
1112 else
1113 regcache->raw_supply (regnum,
1114 XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, regnum));
1115 return;
1116
1117 case avx512_zmm16_h:
1118 if ((clear_bv & X86_XSTATE_ZMM))
1119 regcache->raw_supply_zeroed (regnum);
1120 else
1121 regcache->raw_supply (regnum,
1122 XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, regnum));
1123 return;
1124
1125 case avx512_k:
1126 if ((clear_bv & X86_XSTATE_K))
1127 regcache->raw_supply_zeroed (regnum);
1128 else
1129 regcache->raw_supply (regnum, XSAVE_AVX512_K_ADDR (tdep, regs, regnum));
1130 return;
1131
1132 case avx512_ymmh_avx512:
1133 if ((clear_bv & X86_XSTATE_ZMM))
1134 regcache->raw_supply_zeroed (regnum);
1135 else
1136 regcache->raw_supply (regnum,
1137 XSAVE_YMM_H_AVX512_ADDR (tdep, regs, regnum));
1138 return;
1139
1140 case avx512_xmm_avx512:
1141 if ((clear_bv & X86_XSTATE_ZMM))
1142 regcache->raw_supply_zeroed (regnum);
1143 else
1144 regcache->raw_supply (regnum,
1145 XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum));
1146 return;
1147
1148 case avxh:
1149 if ((clear_bv & X86_XSTATE_AVX))
1150 regcache->raw_supply_zeroed (regnum);
1151 else
1152 regcache->raw_supply (regnum, XSAVE_AVXH_ADDR (tdep, regs, regnum));
1153 return;
1154
1155 case sse:
1156 if ((clear_bv & X86_XSTATE_SSE))
1157 regcache->raw_supply_zeroed (regnum);
1158 else
1159 regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum));
1160 return;
1161
1162 case x87:
1163 if ((clear_bv & X86_XSTATE_X87))
1164 regcache->raw_supply_zeroed (regnum);
1165 else
1166 regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum));
1167 return;
1168
1169 case all:
1170 /* Handle PKEYS registers. */
1171 if ((tdep->xcr0 & X86_XSTATE_PKRU))
1172 {
1173 if ((clear_bv & X86_XSTATE_PKRU))
1174 {
1175 for (i = I387_PKRU_REGNUM (tdep);
1176 i < I387_PKEYSEND_REGNUM (tdep);
1177 i++)
1178 regcache->raw_supply_zeroed (i);
1179 }
1180 else
1181 {
1182 for (i = I387_PKRU_REGNUM (tdep);
1183 i < I387_PKEYSEND_REGNUM (tdep);
1184 i++)
1185 regcache->raw_supply (i, XSAVE_PKEYS_ADDR (tdep, regs, i));
1186 }
1187 }
1188
1189 /* Handle the upper halves of the low 8/16 ZMM registers. */
1190 if ((tdep->xcr0 & X86_XSTATE_ZMM_H))
1191 {
1192 if ((clear_bv & X86_XSTATE_ZMM_H))
1193 {
1194 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1195 regcache->raw_supply_zeroed (i);
1196 }
1197 else
1198 {
1199 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1200 regcache->raw_supply (i,
1201 XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i));
1202 }
1203 }
1204
1205 /* Handle AVX512 OpMask registers. */
1206 if ((tdep->xcr0 & X86_XSTATE_K))
1207 {
1208 if ((clear_bv & X86_XSTATE_K))
1209 {
1210 for (i = I387_K0_REGNUM (tdep);
1211 i < I387_KEND_REGNUM (tdep);
1212 i++)
1213 regcache->raw_supply_zeroed (i);
1214 }
1215 else
1216 {
1217 for (i = I387_K0_REGNUM (tdep);
1218 i < I387_KEND_REGNUM (tdep);
1219 i++)
1220 regcache->raw_supply (i, XSAVE_AVX512_K_ADDR (tdep, regs, i));
1221 }
1222 }
1223
1224 /* Handle the upper 16 ZMM/YMM/XMM registers (if any). */
1225 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1226 {
1227 if ((clear_bv & X86_XSTATE_ZMM))
1228 {
1229 for (i = I387_ZMM16H_REGNUM (tdep);
1230 i < I387_ZMMENDH_REGNUM (tdep); i++)
1231 regcache->raw_supply_zeroed (i);
1232 for (i = I387_YMM16H_REGNUM (tdep);
1233 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1234 i++)
1235 regcache->raw_supply_zeroed (i);
1236 for (i = I387_XMM16_REGNUM (tdep);
1237 i < I387_XMM_AVX512_END_REGNUM (tdep);
1238 i++)
1239 regcache->raw_supply_zeroed (i);
1240 }
1241 else
1242 {
1243 for (i = I387_ZMM16H_REGNUM (tdep);
1244 i < I387_ZMMENDH_REGNUM (tdep); i++)
1245 regcache->raw_supply (i,
1246 XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i));
1247 for (i = I387_YMM16H_REGNUM (tdep);
1248 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1249 i++)
1250 regcache->raw_supply (i,
1251 XSAVE_YMM_H_AVX512_ADDR (tdep, regs, i));
1252 for (i = I387_XMM16_REGNUM (tdep);
1253 i < I387_XMM_AVX512_END_REGNUM (tdep);
1254 i++)
1255 regcache->raw_supply (i, XSAVE_XMM_AVX512_ADDR (tdep, regs, i));
1256 }
1257 }
1258 /* Handle the upper YMM registers. */
1259 if ((tdep->xcr0 & X86_XSTATE_AVX))
1260 {
1261 if ((clear_bv & X86_XSTATE_AVX))
1262 {
1263 for (i = I387_YMM0H_REGNUM (tdep);
1264 i < I387_YMMENDH_REGNUM (tdep);
1265 i++)
1266 regcache->raw_supply_zeroed (i);
1267 }
1268 else
1269 {
1270 for (i = I387_YMM0H_REGNUM (tdep);
1271 i < I387_YMMENDH_REGNUM (tdep);
1272 i++)
1273 regcache->raw_supply (i, XSAVE_AVXH_ADDR (tdep, regs, i));
1274 }
1275 }
1276
1277 /* Handle the XMM registers. */
1278 if ((tdep->xcr0 & X86_XSTATE_SSE))
1279 {
1280 if ((clear_bv & X86_XSTATE_SSE))
1281 {
1282 for (i = I387_XMM0_REGNUM (tdep);
1283 i < I387_MXCSR_REGNUM (tdep);
1284 i++)
1285 regcache->raw_supply_zeroed (i);
1286 }
1287 else
1288 {
1289 for (i = I387_XMM0_REGNUM (tdep);
1290 i < I387_MXCSR_REGNUM (tdep); i++)
1291 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
1292 }
1293 }
1294
1295 /* Handle the x87 registers. */
1296 if ((tdep->xcr0 & X86_XSTATE_X87))
1297 {
1298 if ((clear_bv & X86_XSTATE_X87))
1299 {
1300 for (i = I387_ST0_REGNUM (tdep);
1301 i < I387_FCTRL_REGNUM (tdep);
1302 i++)
1303 regcache->raw_supply_zeroed (i);
1304 }
1305 else
1306 {
1307 for (i = I387_ST0_REGNUM (tdep);
1308 i < I387_FCTRL_REGNUM (tdep);
1309 i++)
1310 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
1311 }
1312 }
1313 break;
1314 }
1315
1316 /* Only handle x87 control registers. */
1317 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1318 if (regnum == -1 || regnum == i)
1319 {
1320 if (clear_bv & X86_XSTATE_X87)
1321 {
1322 if (i == I387_FCTRL_REGNUM (tdep))
1323 {
1324 gdb_byte buf[4];
1325
1326 store_unsigned_integer (buf, 4, byte_order,
1327 I387_FCTRL_INIT_VAL);
1328 regcache->raw_supply (i, buf);
1329 }
1330 else if (i == I387_FTAG_REGNUM (tdep))
1331 {
1332 gdb_byte buf[4];
1333
1334 store_unsigned_integer (buf, 4, byte_order, 0xffff);
1335 regcache->raw_supply (i, buf);
1336 }
1337 else
1338 regcache->raw_supply_zeroed (i);
1339 }
1340 /* Most of the FPU control registers occupy only 16 bits in
1341 the xsave extended state. Give those a special treatment. */
1342 else if (i != I387_FIOFF_REGNUM (tdep)
1343 && i != I387_FOOFF_REGNUM (tdep))
1344 {
1345 gdb_byte val[4];
1346
1347 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
1348 val[2] = val[3] = 0;
1349 if (i == I387_FOP_REGNUM (tdep))
1350 val[1] &= ((1 << 3) - 1);
1351 else if (i == I387_FTAG_REGNUM (tdep))
1352 {
1353 /* The fxsave area contains a simplified version of
1354 the tag word. We have to look at the actual 80-bit
1355 FP data to recreate the traditional i387 tag word. */
1356
1357 unsigned long ftag = 0;
1358 int fpreg;
1359 int top;
1360
1361 top = ((FXSAVE_ADDR (tdep, regs,
1362 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
1363 top &= 0x7;
1364
1365 for (fpreg = 7; fpreg >= 0; fpreg--)
1366 {
1367 int tag;
1368
1369 if (val[0] & (1 << fpreg))
1370 {
1371 int thisreg = (fpreg + 8 - top) % 8
1372 + I387_ST0_REGNUM (tdep);
1373 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
1374 }
1375 else
1376 tag = 3; /* Empty */
1377
1378 ftag |= tag << (2 * fpreg);
1379 }
1380 val[0] = ftag & 0xff;
1381 val[1] = (ftag >> 8) & 0xff;
1382 }
1383 regcache->raw_supply (i, val);
1384 }
1385 else
1386 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
1387 }
1388
1389 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1390 {
1391 /* The MXCSR register is placed into the xsave buffer if either the
1392 AVX or SSE features are enabled. */
1393 if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE))
1394 == (X86_XSTATE_AVX | X86_XSTATE_SSE))
1395 {
1396 gdb_byte buf[4];
1397
1398 store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL);
1399 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf);
1400 }
1401 else
1402 regcache->raw_supply (I387_MXCSR_REGNUM (tdep),
1403 FXSAVE_MXCSR_ADDR (regs));
1404 }
1405}
1406
1407/* Similar to i387_collect_fxsave, but use XSAVE extended state. */
1408
1409void
1410i387_collect_xsave (const struct regcache *regcache, int regnum,
1411 void *xsave, int gcore)
1412{
1413 struct gdbarch *gdbarch = regcache->arch ();
1414 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1415 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
1416 gdb_byte *p, *regs = (gdb_byte *) xsave;
1417 gdb_byte raw[I386_MAX_REGISTER_SIZE];
1418 ULONGEST initial_xstate_bv, clear_bv, xstate_bv = 0;
1419 unsigned int i;
1420 /* See the comment in i387_supply_xsave(). */
1421 unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep)
1422 + std::min (tdep->num_zmm_regs, 16);
1423 enum
1424 {
1425 x87_ctrl_or_mxcsr = 0x1,
1426 x87 = 0x2,
1427 sse = 0x4,
1428 avxh = 0x8,
1429 avx512_k = 0x10,
1430 avx512_zmm0_h = 0x20,
1431 avx512_zmm16_h = 0x40,
1432 avx512_ymmh_avx512 = 0x80,
1433 avx512_xmm_avx512 = 0x100,
1434 pkeys = 0x200,
1435 all = x87 | sse | avxh | avx512_k | avx512_zmm0_h | avx512_zmm16_h
1436 | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
1437 } regclass;
1438
1439 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
1440 gdb_assert (tdep->num_xmm_regs > 0);
1441
1442 if (regnum == -1)
1443 regclass = all;
1444 else if (regnum >= I387_PKRU_REGNUM (tdep)
1445 && regnum < I387_PKEYSEND_REGNUM (tdep))
1446 regclass = pkeys;
1447 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
1448 && regnum < I387_ZMM16H_REGNUM (tdep))
1449 regclass = avx512_zmm0_h;
1450 else if (regnum >= I387_ZMM16H_REGNUM (tdep)
1451 && regnum < I387_ZMMENDH_REGNUM (tdep))
1452 regclass = avx512_zmm16_h;
1453 else if (regnum >= I387_K0_REGNUM (tdep)
1454 && regnum < I387_KEND_REGNUM (tdep))
1455 regclass = avx512_k;
1456 else if (regnum >= I387_YMM16H_REGNUM (tdep)
1457 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
1458 regclass = avx512_ymmh_avx512;
1459 else if (regnum >= I387_XMM16_REGNUM (tdep)
1460 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
1461 regclass = avx512_xmm_avx512;
1462 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1463 && regnum < I387_YMMENDH_REGNUM (tdep))
1464 regclass = avxh;
1465 else if (regnum >= I387_XMM0_REGNUM (tdep)
1466 && regnum < I387_MXCSR_REGNUM (tdep))
1467 regclass = sse;
1468 else if (regnum >= I387_ST0_REGNUM (tdep)
1469 && regnum < I387_FCTRL_REGNUM (tdep))
1470 regclass = x87;
1471 else if ((regnum >= I387_FCTRL_REGNUM (tdep)
1472 && regnum < I387_XMM0_REGNUM (tdep))
1473 || regnum == I387_MXCSR_REGNUM (tdep))
1474 regclass = x87_ctrl_or_mxcsr;
1475 else
1476 internal_error (_("invalid i387 regnum %d"), regnum);
1477
1478 if (gcore)
1479 {
1480 /* Clear XSAVE extended state. */
1481 memset (regs, 0, tdep->xsave_layout.sizeof_xsave);
1482
1483 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1484 if (tdep->xsave_xcr0_offset != -1)
1485 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
1486 memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
1487 }
1488
1489 /* The supported bits in `xstat_bv' are 8 bytes. */
1490 initial_xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1491 8, byte_order);
1492 clear_bv = (~(initial_xstate_bv)) & tdep->xcr0;
1493
1494 /* The XSAVE buffer was filled lazily by the kernel. Only those
1495 features that are enabled were written into the buffer, disabled
1496 features left the buffer uninitialised. In order to identify if any
1497 registers have changed we will be comparing the register cache
1498 version to the version in the XSAVE buffer, it is important then that
1499 at this point we initialise to the default values any features in
1500 XSAVE that are not yet initialised.
1501
1502 This could be made more efficient, we know which features (from
1503 REGNUM) we will be potentially updating, and could limit ourselves to
1504 only clearing that feature. However, the extra complexity does not
1505 seem justified at this point. */
1506 if (clear_bv)
1507 {
1508 if ((clear_bv & X86_XSTATE_PKRU))
1509 for (i = I387_PKRU_REGNUM (tdep);
1510 i < I387_PKEYSEND_REGNUM (tdep); i++)
1511 memset (XSAVE_PKEYS_ADDR (tdep, regs, i), 0, 4);
1512
1513 if ((clear_bv & X86_XSTATE_ZMM_H))
1514 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1515 memset (XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i), 0, 32);
1516
1517 if ((clear_bv & X86_XSTATE_K))
1518 for (i = I387_K0_REGNUM (tdep);
1519 i < I387_KEND_REGNUM (tdep); i++)
1520 memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8);
1521
1522 if ((clear_bv & X86_XSTATE_ZMM))
1523 {
1524 for (i = I387_ZMM16H_REGNUM (tdep); i < I387_ZMMENDH_REGNUM (tdep);
1525 i++)
1526 memset (XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i), 0, 32);
1527 for (i = I387_YMM16H_REGNUM (tdep);
1528 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1529 memset (XSAVE_YMM_H_AVX512_ADDR (tdep, regs, i), 0, 16);
1530 for (i = I387_XMM16_REGNUM (tdep);
1531 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1532 memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1533 }
1534
1535 if ((clear_bv & X86_XSTATE_AVX))
1536 for (i = I387_YMM0H_REGNUM (tdep);
1537 i < I387_YMMENDH_REGNUM (tdep); i++)
1538 memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16);
1539
1540 if ((clear_bv & X86_XSTATE_SSE))
1541 for (i = I387_XMM0_REGNUM (tdep);
1542 i < I387_MXCSR_REGNUM (tdep); i++)
1543 memset (FXSAVE_ADDR (tdep, regs, i), 0, 16);
1544
1545 /* The mxcsr register is written into the xsave buffer if either AVX
1546 or SSE is enabled, so only clear it if both of those features
1547 require clearing. */
1548 if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE))
1549 == (X86_XSTATE_AVX | X86_XSTATE_SSE))
1550 store_unsigned_integer (FXSAVE_MXCSR_ADDR (regs), 2, byte_order,
1551 I387_MXCSR_INIT_VAL);
1552
1553 if ((clear_bv & X86_XSTATE_X87))
1554 {
1555 for (i = I387_ST0_REGNUM (tdep);
1556 i < I387_FCTRL_REGNUM (tdep); i++)
1557 memset (FXSAVE_ADDR (tdep, regs, i), 0, 10);
1558
1559 for (i = I387_FCTRL_REGNUM (tdep);
1560 i < I387_XMM0_REGNUM (tdep); i++)
1561 {
1562 if (i == I387_FCTRL_REGNUM (tdep))
1563 store_unsigned_integer (FXSAVE_ADDR (tdep, regs, i), 2,
1564 byte_order, I387_FCTRL_INIT_VAL);
1565 else
1566 memset (FXSAVE_ADDR (tdep, regs, i), 0,
1567 regcache->register_size (i));
1568 }
1569 }
1570 }
1571
1572 if (regclass == all)
1573 {
1574 /* Check if any PKEYS registers are changed. */
1575 if ((tdep->xcr0 & X86_XSTATE_PKRU))
1576 for (i = I387_PKRU_REGNUM (tdep);
1577 i < I387_PKEYSEND_REGNUM (tdep); i++)
1578 {
1579 regcache->raw_collect (i, raw);
1580 p = XSAVE_PKEYS_ADDR (tdep, regs, i);
1581 if (memcmp (raw, p, 4) != 0)
1582 {
1583 xstate_bv |= X86_XSTATE_PKRU;
1584 memcpy (p, raw, 4);
1585 }
1586 }
1587
1588 /* Check if any ZMMH registers are changed. */
1589 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1590 for (i = I387_ZMM16H_REGNUM (tdep);
1591 i < I387_ZMMENDH_REGNUM (tdep); i++)
1592 {
1593 regcache->raw_collect (i, raw);
1594 p = XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i);
1595 if (memcmp (raw, p, 32) != 0)
1596 {
1597 xstate_bv |= X86_XSTATE_ZMM;
1598 memcpy (p, raw, 32);
1599 }
1600 }
1601
1602 if ((tdep->xcr0 & X86_XSTATE_ZMM_H))
1603 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1604 {
1605 regcache->raw_collect (i, raw);
1606 p = XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i);
1607 if (memcmp (raw, p, 32) != 0)
1608 {
1609 xstate_bv |= X86_XSTATE_ZMM_H;
1610 memcpy (p, raw, 32);
1611 }
1612 }
1613
1614 /* Check if any K registers are changed. */
1615 if ((tdep->xcr0 & X86_XSTATE_K))
1616 for (i = I387_K0_REGNUM (tdep);
1617 i < I387_KEND_REGNUM (tdep); i++)
1618 {
1619 regcache->raw_collect (i, raw);
1620 p = XSAVE_AVX512_K_ADDR (tdep, regs, i);
1621 if (memcmp (raw, p, 8) != 0)
1622 {
1623 xstate_bv |= X86_XSTATE_K;
1624 memcpy (p, raw, 8);
1625 }
1626 }
1627
1628 /* Check if any XMM or upper YMM registers are changed. */
1629 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1630 {
1631 for (i = I387_YMM16H_REGNUM (tdep);
1632 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1633 {
1634 regcache->raw_collect (i, raw);
1635 p = XSAVE_YMM_H_AVX512_ADDR (tdep, regs, i);
1636 if (memcmp (raw, p, 16) != 0)
1637 {
1638 xstate_bv |= X86_XSTATE_ZMM;
1639 memcpy (p, raw, 16);
1640 }
1641 }
1642 for (i = I387_XMM16_REGNUM (tdep);
1643 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1644 {
1645 regcache->raw_collect (i, raw);
1646 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i);
1647 if (memcmp (raw, p, 16) != 0)
1648 {
1649 xstate_bv |= X86_XSTATE_ZMM;
1650 memcpy (p, raw, 16);
1651 }
1652 }
1653 }
1654
1655 /* Check if any upper YMM registers are changed. */
1656 if ((tdep->xcr0 & X86_XSTATE_AVX))
1657 for (i = I387_YMM0H_REGNUM (tdep);
1658 i < I387_YMMENDH_REGNUM (tdep); i++)
1659 {
1660 regcache->raw_collect (i, raw);
1661 p = XSAVE_AVXH_ADDR (tdep, regs, i);
1662 if (memcmp (raw, p, 16))
1663 {
1664 xstate_bv |= X86_XSTATE_AVX;
1665 memcpy (p, raw, 16);
1666 }
1667 }
1668
1669 /* Check if any SSE registers are changed. */
1670 if ((tdep->xcr0 & X86_XSTATE_SSE))
1671 for (i = I387_XMM0_REGNUM (tdep);
1672 i < I387_MXCSR_REGNUM (tdep); i++)
1673 {
1674 regcache->raw_collect (i, raw);
1675 p = FXSAVE_ADDR (tdep, regs, i);
1676 if (memcmp (raw, p, 16))
1677 {
1678 xstate_bv |= X86_XSTATE_SSE;
1679 memcpy (p, raw, 16);
1680 }
1681 }
1682
1683 if ((tdep->xcr0 & X86_XSTATE_AVX) || (tdep->xcr0 & X86_XSTATE_SSE))
1684 {
1685 i = I387_MXCSR_REGNUM (tdep);
1686 regcache->raw_collect (i, raw);
1687 p = FXSAVE_MXCSR_ADDR (regs);
1688 if (memcmp (raw, p, 4))
1689 {
1690 /* Now, we need to mark one of either SSE of AVX as enabled.
1691 We could pick either. What we do is check to see if one
1692 of the features is already enabled, if it is then we leave
1693 it at that, otherwise we pick SSE. */
1694 if ((xstate_bv & (X86_XSTATE_SSE | X86_XSTATE_AVX)) == 0)
1695 xstate_bv |= X86_XSTATE_SSE;
1696 memcpy (p, raw, 4);
1697 }
1698 }
1699
1700 /* Check if any X87 registers are changed. Only the non-control
1701 registers are handled here, the control registers are all handled
1702 later on in this function. */
1703 if ((tdep->xcr0 & X86_XSTATE_X87))
1704 for (i = I387_ST0_REGNUM (tdep);
1705 i < I387_FCTRL_REGNUM (tdep); i++)
1706 {
1707 regcache->raw_collect (i, raw);
1708 p = FXSAVE_ADDR (tdep, regs, i);
1709 if (memcmp (raw, p, 10))
1710 {
1711 xstate_bv |= X86_XSTATE_X87;
1712 memcpy (p, raw, 10);
1713 }
1714 }
1715 }
1716 else
1717 {
1718 /* Check if REGNUM is changed. */
1719 regcache->raw_collect (regnum, raw);
1720
1721 switch (regclass)
1722 {
1723 default:
1724 internal_error (_("invalid i387 regclass"));
1725
1726 case pkeys:
1727 /* This is a PKEYS register. */
1728 p = XSAVE_PKEYS_ADDR (tdep, regs, regnum);
1729 if (memcmp (raw, p, 4) != 0)
1730 {
1731 xstate_bv |= X86_XSTATE_PKRU;
1732 memcpy (p, raw, 4);
1733 }
1734 break;
1735
1736 case avx512_zmm16_h:
1737 /* This is a ZMM16-31 register. */
1738 p = XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, regnum);
1739 if (memcmp (raw, p, 32) != 0)
1740 {
1741 xstate_bv |= X86_XSTATE_ZMM;
1742 memcpy (p, raw, 32);
1743 }
1744 break;
1745
1746 case avx512_zmm0_h:
1747 /* This is a ZMM0-15 register. */
1748 p = XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, regnum);
1749 if (memcmp (raw, p, 32) != 0)
1750 {
1751 xstate_bv |= X86_XSTATE_ZMM_H;
1752 memcpy (p, raw, 32);
1753 }
1754 break;
1755
1756 case avx512_k:
1757 /* This is a AVX512 mask register. */
1758 p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum);
1759 if (memcmp (raw, p, 8) != 0)
1760 {
1761 xstate_bv |= X86_XSTATE_K;
1762 memcpy (p, raw, 8);
1763 }
1764 break;
1765
1766 case avx512_ymmh_avx512:
1767 /* This is an upper YMM16-31 register. */
1768 p = XSAVE_YMM_H_AVX512_ADDR (tdep, regs, regnum);
1769 if (memcmp (raw, p, 16) != 0)
1770 {
1771 xstate_bv |= X86_XSTATE_ZMM;
1772 memcpy (p, raw, 16);
1773 }
1774 break;
1775
1776 case avx512_xmm_avx512:
1777 /* This is an upper XMM16-31 register. */
1778 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum);
1779 if (memcmp (raw, p, 16) != 0)
1780 {
1781 xstate_bv |= X86_XSTATE_ZMM;
1782 memcpy (p, raw, 16);
1783 }
1784 break;
1785
1786 case avxh:
1787 /* This is an upper YMM register. */
1788 p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
1789 if (memcmp (raw, p, 16))
1790 {
1791 xstate_bv |= X86_XSTATE_AVX;
1792 memcpy (p, raw, 16);
1793 }
1794 break;
1795
1796 case sse:
1797 /* This is an SSE register. */
1798 p = FXSAVE_ADDR (tdep, regs, regnum);
1799 if (memcmp (raw, p, 16))
1800 {
1801 xstate_bv |= X86_XSTATE_SSE;
1802 memcpy (p, raw, 16);
1803 }
1804 break;
1805
1806 case x87:
1807 /* This is an x87 register. */
1808 p = FXSAVE_ADDR (tdep, regs, regnum);
1809 if (memcmp (raw, p, 10))
1810 {
1811 xstate_bv |= X86_XSTATE_X87;
1812 memcpy (p, raw, 10);
1813 }
1814 break;
1815
1816 case x87_ctrl_or_mxcsr:
1817 /* We only handle MXCSR here. All other x87 control registers
1818 are handled separately below. */
1819 if (regnum == I387_MXCSR_REGNUM (tdep))
1820 {
1821 p = FXSAVE_MXCSR_ADDR (regs);
1822 if (memcmp (raw, p, 2))
1823 {
1824 /* We're only setting MXCSR, so check the initial state
1825 to see if either of AVX or SSE are already enabled.
1826 If they are then we'll attribute this changed MXCSR to
1827 that feature. If neither feature is enabled, then
1828 we'll attribute this change to the SSE feature. */
1829 xstate_bv |= (initial_xstate_bv
1830 & (X86_XSTATE_AVX | X86_XSTATE_SSE));
1831 if ((xstate_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) == 0)
1832 xstate_bv |= X86_XSTATE_SSE;
1833 memcpy (p, raw, 2);
1834 }
1835 }
1836 }
1837 }
1838
1839 /* Only handle x87 control registers. */
1840 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1841 if (regnum == -1 || regnum == i)
1842 {
1843 /* Most of the FPU control registers occupy only 16 bits in
1844 the xsave extended state. Give those a special treatment. */
1845 if (i != I387_FIOFF_REGNUM (tdep)
1846 && i != I387_FOOFF_REGNUM (tdep))
1847 {
1848 gdb_byte buf[4];
1849
1850 regcache->raw_collect (i, buf);
1851
1852 if (i == I387_FOP_REGNUM (tdep))
1853 {
1854 /* The opcode occupies only 11 bits. Make sure we
1855 don't touch the other bits. */
1856 buf[1] &= ((1 << 3) - 1);
1857 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
1858 }
1859 else if (i == I387_FTAG_REGNUM (tdep))
1860 {
1861 /* Converting back is much easier. */
1862
1863 unsigned short ftag;
1864 int fpreg;
1865
1866 ftag = (buf[1] << 8) | buf[0];
1867 buf[0] = 0;
1868 buf[1] = 0;
1869
1870 for (fpreg = 7; fpreg >= 0; fpreg--)
1871 {
1872 int tag = (ftag >> (fpreg * 2)) & 3;
1873
1874 if (tag != 3)
1875 buf[0] |= (1 << fpreg);
1876 }
1877 }
1878 p = FXSAVE_ADDR (tdep, regs, i);
1879 if (memcmp (p, buf, 2))
1880 {
1881 xstate_bv |= X86_XSTATE_X87;
1882 memcpy (p, buf, 2);
1883 }
1884 }
1885 else
1886 {
1887 int regsize;
1888
1889 regcache->raw_collect (i, raw);
1890 regsize = regcache->register_size (i);
1891 p = FXSAVE_ADDR (tdep, regs, i);
1892 if (memcmp (raw, p, regsize))
1893 {
1894 xstate_bv |= X86_XSTATE_X87;
1895 memcpy (p, raw, regsize);
1896 }
1897 }
1898 }
1899
1900 /* Update the corresponding bits in `xstate_bv' if any
1901 registers are changed. */
1902 if (xstate_bv)
1903 {
1904 /* The supported bits in `xstat_bv' are 8 bytes. */
1905 initial_xstate_bv |= xstate_bv;
1906 store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1907 8, byte_order,
1908 initial_xstate_bv);
1909 }
1910}
1911
1912/* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
1913 *RAW. */
1914
1915static int
1916i387_tag (const gdb_byte *raw)
1917{
1918 int integer;
1919 unsigned int exponent;
1920 unsigned long fraction[2];
1921
1922 integer = raw[7] & 0x80;
1923 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
1924 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
1925 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
1926 | (raw[5] << 8) | raw[4]);
1927
1928 if (exponent == 0x7fff)
1929 {
1930 /* Special. */
1931 return (2);
1932 }
1933 else if (exponent == 0x0000)
1934 {
1935 if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer)
1936 {
1937 /* Zero. */
1938 return (1);
1939 }
1940 else
1941 {
1942 /* Special. */
1943 return (2);
1944 }
1945 }
1946 else
1947 {
1948 if (integer)
1949 {
1950 /* Valid. */
1951 return (0);
1952 }
1953 else
1954 {
1955 /* Special. */
1956 return (2);
1957 }
1958 }
1959}
1960
1961/* Prepare the FPU stack in REGCACHE for a function return. */
1962
1963void
1964i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache)
1965{
1966 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
1967 ULONGEST fstat;
1968
1969 /* Set the top of the floating-point register stack to 7. The
1970 actual value doesn't really matter, but 7 is what a normal
1971 function return would end up with if the program started out with
1972 a freshly initialized FPU. */
1973 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
1974 fstat |= (7 << 11);
1975 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
1976
1977 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
1978 floating-point register stack to 7, the appropriate value for the
1979 tag word is 0x3fff. */
1980 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
1981
1982}
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