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1/* Functions specific to running gdb native on IA-64 running
2 GNU/Linux.
3
4 Copyright (C) 1999-2025 Free Software Foundation, Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "inferior.h"
22#include "target.h"
23#include "gdbarch.h"
24#include "gdbcore.h"
25#include "regcache.h"
26#include "ia64-tdep.h"
27#include "linux-nat.h"
28
29#include <signal.h>
30#include "nat/gdb_ptrace.h"
31#include "gdbsupport/gdb_wait.h"
32#ifdef HAVE_SYS_REG_H
33#include <sys/reg.h>
34#endif
35#include <sys/syscall.h>
36#include <sys/user.h>
37
38#include <asm/ptrace_offsets.h>
39#include <sys/procfs.h>
40
41/* Prototypes for supply_gregset etc. */
42#include "gregset.h"
43
44#include "inf-ptrace.h"
45
46class ia64_linux_nat_target final : public linux_nat_target
47{
48public:
49 /* Add our register access methods. */
50 void fetch_registers (struct regcache *, int) override;
51 void store_registers (struct regcache *, int) override;
52
53 enum target_xfer_status xfer_partial (enum target_object object,
54 const char *annex,
55 gdb_byte *readbuf,
56 const gdb_byte *writebuf,
57 ULONGEST offset, ULONGEST len,
58 ULONGEST *xfered_len) override;
59
60 /* Override watchpoint routines. */
61
62 /* The IA-64 architecture can step over a watch point (without
63 triggering it again) if the "dd" (data debug fault disable) bit
64 in the processor status word is set.
65
66 This PSR bit is set in
67 ia64_linux_nat_target::stopped_by_watchpoint when the code there
68 has determined that a hardware watchpoint has indeed been hit.
69 The CPU will then be able to execute one instruction without
70 triggering a watchpoint. */
71 bool have_steppable_watchpoint () override { return true; }
72
73 int can_use_hw_breakpoint (enum bptype, int, int) override;
74 bool stopped_by_watchpoint () override;
75 bool stopped_data_address (CORE_ADDR *) override;
76 int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
77 struct expression *) override;
78 int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
79 struct expression *) override;
80 /* Override linux_nat_target low methods. */
81 void low_new_thread (struct lwp_info *lp) override;
82 bool low_status_is_event (int status) override;
83
84 void enable_watchpoints_in_psr (ptid_t ptid);
85};
86
87static ia64_linux_nat_target the_ia64_linux_nat_target;
88
89/* These must match the order of the register names.
90
91 Some sort of lookup table is needed because the offsets associated
92 with the registers are all over the board. */
93
94static int u_offsets[] =
95 {
96 /* general registers */
97 -1, /* gr0 not available; i.e, it's always zero. */
98 PT_R1,
99 PT_R2,
100 PT_R3,
101 PT_R4,
102 PT_R5,
103 PT_R6,
104 PT_R7,
105 PT_R8,
106 PT_R9,
107 PT_R10,
108 PT_R11,
109 PT_R12,
110 PT_R13,
111 PT_R14,
112 PT_R15,
113 PT_R16,
114 PT_R17,
115 PT_R18,
116 PT_R19,
117 PT_R20,
118 PT_R21,
119 PT_R22,
120 PT_R23,
121 PT_R24,
122 PT_R25,
123 PT_R26,
124 PT_R27,
125 PT_R28,
126 PT_R29,
127 PT_R30,
128 PT_R31,
129 /* gr32 through gr127 not directly available via the ptrace interface. */
130 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
131 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
132 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
133 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
134 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
135 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
136 /* Floating point registers */
137 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0). */
138 PT_F2,
139 PT_F3,
140 PT_F4,
141 PT_F5,
142 PT_F6,
143 PT_F7,
144 PT_F8,
145 PT_F9,
146 PT_F10,
147 PT_F11,
148 PT_F12,
149 PT_F13,
150 PT_F14,
151 PT_F15,
152 PT_F16,
153 PT_F17,
154 PT_F18,
155 PT_F19,
156 PT_F20,
157 PT_F21,
158 PT_F22,
159 PT_F23,
160 PT_F24,
161 PT_F25,
162 PT_F26,
163 PT_F27,
164 PT_F28,
165 PT_F29,
166 PT_F30,
167 PT_F31,
168 PT_F32,
169 PT_F33,
170 PT_F34,
171 PT_F35,
172 PT_F36,
173 PT_F37,
174 PT_F38,
175 PT_F39,
176 PT_F40,
177 PT_F41,
178 PT_F42,
179 PT_F43,
180 PT_F44,
181 PT_F45,
182 PT_F46,
183 PT_F47,
184 PT_F48,
185 PT_F49,
186 PT_F50,
187 PT_F51,
188 PT_F52,
189 PT_F53,
190 PT_F54,
191 PT_F55,
192 PT_F56,
193 PT_F57,
194 PT_F58,
195 PT_F59,
196 PT_F60,
197 PT_F61,
198 PT_F62,
199 PT_F63,
200 PT_F64,
201 PT_F65,
202 PT_F66,
203 PT_F67,
204 PT_F68,
205 PT_F69,
206 PT_F70,
207 PT_F71,
208 PT_F72,
209 PT_F73,
210 PT_F74,
211 PT_F75,
212 PT_F76,
213 PT_F77,
214 PT_F78,
215 PT_F79,
216 PT_F80,
217 PT_F81,
218 PT_F82,
219 PT_F83,
220 PT_F84,
221 PT_F85,
222 PT_F86,
223 PT_F87,
224 PT_F88,
225 PT_F89,
226 PT_F90,
227 PT_F91,
228 PT_F92,
229 PT_F93,
230 PT_F94,
231 PT_F95,
232 PT_F96,
233 PT_F97,
234 PT_F98,
235 PT_F99,
236 PT_F100,
237 PT_F101,
238 PT_F102,
239 PT_F103,
240 PT_F104,
241 PT_F105,
242 PT_F106,
243 PT_F107,
244 PT_F108,
245 PT_F109,
246 PT_F110,
247 PT_F111,
248 PT_F112,
249 PT_F113,
250 PT_F114,
251 PT_F115,
252 PT_F116,
253 PT_F117,
254 PT_F118,
255 PT_F119,
256 PT_F120,
257 PT_F121,
258 PT_F122,
259 PT_F123,
260 PT_F124,
261 PT_F125,
262 PT_F126,
263 PT_F127,
264 /* Predicate registers - we don't fetch these individually. */
265 -1, -1, -1, -1, -1, -1, -1, -1,
266 -1, -1, -1, -1, -1, -1, -1, -1,
267 -1, -1, -1, -1, -1, -1, -1, -1,
268 -1, -1, -1, -1, -1, -1, -1, -1,
269 -1, -1, -1, -1, -1, -1, -1, -1,
270 -1, -1, -1, -1, -1, -1, -1, -1,
271 -1, -1, -1, -1, -1, -1, -1, -1,
272 -1, -1, -1, -1, -1, -1, -1, -1,
273 /* branch registers */
274 PT_B0,
275 PT_B1,
276 PT_B2,
277 PT_B3,
278 PT_B4,
279 PT_B5,
280 PT_B6,
281 PT_B7,
282 /* Virtual frame pointer and virtual return address pointer. */
283 -1, -1,
284 /* other registers */
285 PT_PR,
286 PT_CR_IIP, /* ip */
287 PT_CR_IPSR, /* psr */
288 PT_CFM, /* cfm */
289 /* kernel registers not visible via ptrace interface (?) */
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 /* hole */
292 -1, -1, -1, -1, -1, -1, -1, -1,
293 PT_AR_RSC,
294 PT_AR_BSP,
295 PT_AR_BSPSTORE,
296 PT_AR_RNAT,
297 -1,
298 -1, /* Not available: FCR, IA32 floating control register. */
299 -1, -1,
300 -1, /* Not available: EFLAG */
301 -1, /* Not available: CSD */
302 -1, /* Not available: SSD */
303 -1, /* Not available: CFLG */
304 -1, /* Not available: FSR */
305 -1, /* Not available: FIR */
306 -1, /* Not available: FDR */
307 -1,
308 PT_AR_CCV,
309 -1, -1, -1,
310 PT_AR_UNAT,
311 -1, -1, -1,
312 PT_AR_FPSR,
313 -1, -1, -1,
314 -1, /* Not available: ITC */
315 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
316 -1, -1, -1, -1, -1, -1, -1, -1, -1,
317 PT_AR_PFS,
318 PT_AR_LC,
319 PT_AR_EC,
320 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
321 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
322 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
323 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
324 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
325 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
326 -1,
327 /* nat bits - not fetched directly; instead we obtain these bits from
328 either rnat or unat or from memory. */
329 -1, -1, -1, -1, -1, -1, -1, -1,
330 -1, -1, -1, -1, -1, -1, -1, -1,
331 -1, -1, -1, -1, -1, -1, -1, -1,
332 -1, -1, -1, -1, -1, -1, -1, -1,
333 -1, -1, -1, -1, -1, -1, -1, -1,
334 -1, -1, -1, -1, -1, -1, -1, -1,
335 -1, -1, -1, -1, -1, -1, -1, -1,
336 -1, -1, -1, -1, -1, -1, -1, -1,
337 -1, -1, -1, -1, -1, -1, -1, -1,
338 -1, -1, -1, -1, -1, -1, -1, -1,
339 -1, -1, -1, -1, -1, -1, -1, -1,
340 -1, -1, -1, -1, -1, -1, -1, -1,
341 -1, -1, -1, -1, -1, -1, -1, -1,
342 -1, -1, -1, -1, -1, -1, -1, -1,
343 -1, -1, -1, -1, -1, -1, -1, -1,
344 -1, -1, -1, -1, -1, -1, -1, -1,
345 };
346
347static CORE_ADDR
348ia64_register_addr (struct gdbarch *gdbarch, int regno)
349{
350 CORE_ADDR addr;
351
352 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
353 error (_("Invalid register number %d."), regno);
354
355 if (u_offsets[regno] == -1)
356 addr = 0;
357 else
358 addr = (CORE_ADDR) u_offsets[regno];
359
360 return addr;
361}
362
363static int
364ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
365{
366 return regno < 0
367 || regno >= gdbarch_num_regs (gdbarch)
368 || u_offsets[regno] == -1;
369}
370
371static int
372ia64_cannot_store_register (struct gdbarch *gdbarch, int regno)
373{
374 /* Rationale behind not permitting stores to bspstore...
375
376 The IA-64 architecture provides bspstore and bsp which refer
377 memory locations in the RSE's backing store. bspstore is the
378 next location which will be written when the RSE needs to write
379 to memory. bsp is the address at which r32 in the current frame
380 would be found if it were written to the backing store.
381
382 The IA-64 architecture provides read-only access to bsp and
383 read/write access to bspstore (but only when the RSE is in
384 the enforced lazy mode). It should be noted that stores
385 to bspstore also affect the value of bsp. Changing bspstore
386 does not affect the number of dirty entries between bspstore
387 and bsp, so changing bspstore by N words will also cause bsp
388 to be changed by (roughly) N as well. (It could be N-1 or N+1
389 depending upon where the NaT collection bits fall.)
390
391 OTOH, the Linux kernel provides read/write access to bsp (and
392 currently read/write access to bspstore as well). But it
393 is definitely the case that if you change one, the other
394 will change at the same time. It is more useful to gdb to
395 be able to change bsp. So in order to prevent strange and
396 undesirable things from happening when a dummy stack frame
397 is popped (after calling an inferior function), we allow
398 bspstore to be read, but not written. (Note that popping
399 a (generic) dummy stack frame causes all registers that
400 were previously read from the inferior process to be written
401 back.) */
402
403 return regno < 0
404 || regno >= gdbarch_num_regs (gdbarch)
405 || u_offsets[regno] == -1
406 || regno == IA64_BSPSTORE_REGNUM;
407}
408
409void
410supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
411{
412 int regi;
413 const greg_t *regp = (const greg_t *) gregsetp;
414
415 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
416 {
417 regcache->raw_supply (regi, regp + (regi - IA64_GR0_REGNUM));
418 }
419
420 /* FIXME: NAT collection bits are at index 32; gotta deal with these
421 somehow... */
422
423 regcache->raw_supply (IA64_PR_REGNUM, regp + 33);
424
425 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
426 {
427 regcache->raw_supply (regi, regp + 34 + (regi - IA64_BR0_REGNUM));
428 }
429
430 regcache->raw_supply (IA64_IP_REGNUM, regp + 42);
431 regcache->raw_supply (IA64_CFM_REGNUM, regp + 43);
432 regcache->raw_supply (IA64_PSR_REGNUM, regp + 44);
433 regcache->raw_supply (IA64_RSC_REGNUM, regp + 45);
434 regcache->raw_supply (IA64_BSP_REGNUM, regp + 46);
435 regcache->raw_supply (IA64_BSPSTORE_REGNUM, regp + 47);
436 regcache->raw_supply (IA64_RNAT_REGNUM, regp + 48);
437 regcache->raw_supply (IA64_CCV_REGNUM, regp + 49);
438 regcache->raw_supply (IA64_UNAT_REGNUM, regp + 50);
439 regcache->raw_supply (IA64_FPSR_REGNUM, regp + 51);
440 regcache->raw_supply (IA64_PFS_REGNUM, regp + 52);
441 regcache->raw_supply (IA64_LC_REGNUM, regp + 53);
442 regcache->raw_supply (IA64_EC_REGNUM, regp + 54);
443}
444
445void
446fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
447{
448 int regi;
449 greg_t *regp = (greg_t *) gregsetp;
450
451#define COPY_REG(_idx_,_regi_) \
452 if ((regno == -1) || regno == _regi_) \
453 regcache->raw_collect (_regi_, regp + _idx_)
454
455 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
456 {
457 COPY_REG (regi - IA64_GR0_REGNUM, regi);
458 }
459
460 /* FIXME: NAT collection bits at index 32? */
461
462 COPY_REG (33, IA64_PR_REGNUM);
463
464 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
465 {
466 COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
467 }
468
469 COPY_REG (42, IA64_IP_REGNUM);
470 COPY_REG (43, IA64_CFM_REGNUM);
471 COPY_REG (44, IA64_PSR_REGNUM);
472 COPY_REG (45, IA64_RSC_REGNUM);
473 COPY_REG (46, IA64_BSP_REGNUM);
474 COPY_REG (47, IA64_BSPSTORE_REGNUM);
475 COPY_REG (48, IA64_RNAT_REGNUM);
476 COPY_REG (49, IA64_CCV_REGNUM);
477 COPY_REG (50, IA64_UNAT_REGNUM);
478 COPY_REG (51, IA64_FPSR_REGNUM);
479 COPY_REG (52, IA64_PFS_REGNUM);
480 COPY_REG (53, IA64_LC_REGNUM);
481 COPY_REG (54, IA64_EC_REGNUM);
482}
483
484/* Given a pointer to a floating point register set in /proc format
485 (fpregset_t *), unpack the register contents and supply them as gdb's
486 idea of the current floating point register values. */
487
488void
489supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
490{
491 int regi;
492 const char *from;
493 const gdb_byte f_one[16] =
494 { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
495
496 /* Kernel generated cores have fr1==0 instead of 1.0. Older GDBs
497 did the same. So ignore whatever might be recorded in fpregset_t
498 for fr0/fr1 and always supply their expected values. */
499
500 /* fr0 is always read as zero. */
501 regcache->raw_supply_zeroed (IA64_FR0_REGNUM);
502 /* fr1 is always read as one (1.0). */
503 regcache->raw_supply (IA64_FR1_REGNUM, f_one);
504
505 for (regi = IA64_FR2_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
506 {
507 from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
508 regcache->raw_supply (regi, from);
509 }
510}
511
512/* Given a pointer to a floating point register set in /proc format
513 (fpregset_t *), update the register specified by REGNO from gdb's idea
514 of the current floating point register set. If REGNO is -1, update
515 them all. */
516
517void
518fill_fpregset (const struct regcache *regcache,
519 fpregset_t *fpregsetp, int regno)
520{
521 int regi;
522
523 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
524 {
525 if ((regno == -1) || (regno == regi))
526 regcache->raw_collect (regi, &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
527 }
528}
529
530#define IA64_PSR_DB (1UL << 24)
531#define IA64_PSR_DD (1UL << 39)
532
533void
534ia64_linux_nat_target::enable_watchpoints_in_psr (ptid_t ptid)
535{
536 struct regcache *regcache = get_thread_regcache (this, ptid);
537 ULONGEST psr;
538
539 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
540 if (!(psr & IA64_PSR_DB))
541 {
542 psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware
543 watchpoints and breakpoints. */
544 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
545 }
546}
547
548static long debug_registers[8];
549
550static void
551store_debug_register (ptid_t ptid, int idx, long val)
552{
553 int tid;
554
555 tid = ptid.lwp ();
556 if (tid == 0)
557 tid = ptid.pid ();
558
559 (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
560}
561
562static void
563store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr,
564 long *dbr_mask)
565{
566 if (dbr_addr)
567 store_debug_register (ptid, 2 * idx, *dbr_addr);
568 if (dbr_mask)
569 store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
570}
571
572static int
573is_power_of_2 (int val)
574{
575 int i, onecount;
576
577 onecount = 0;
578 for (i = 0; i < 8 * sizeof (val); i++)
579 if (val & (1 << i))
580 onecount++;
581
582 return onecount <= 1;
583}
584
585int
586ia64_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len,
587 enum target_hw_bp_type type,
588 struct expression *cond)
589{
590 int idx;
591 long dbr_addr, dbr_mask;
592 int max_watchpoints = 4;
593
594 if (len <= 0 || !is_power_of_2 (len))
595 return -1;
596
597 for (idx = 0; idx < max_watchpoints; idx++)
598 {
599 dbr_mask = debug_registers[idx * 2 + 1];
600 if ((dbr_mask & (0x3UL << 62)) == 0)
601 {
602 /* Exit loop if both r and w bits clear. */
603 break;
604 }
605 }
606
607 if (idx == max_watchpoints)
608 return -1;
609
610 dbr_addr = (long) addr;
611 dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */
612 dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */
613 switch (type)
614 {
615 case hw_write:
616 dbr_mask |= (1L << 62); /* Set w bit */
617 break;
618 case hw_read:
619 dbr_mask |= (1L << 63); /* Set r bit */
620 break;
621 case hw_access:
622 dbr_mask |= (3L << 62); /* Set both r and w bits */
623 break;
624 default:
625 return -1;
626 }
627
628 debug_registers[2 * idx] = dbr_addr;
629 debug_registers[2 * idx + 1] = dbr_mask;
630
631 for (const lwp_info *lp : all_lwps ())
632 {
633 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
634 enable_watchpoints_in_psr (lp->ptid);
635 }
636
637 return 0;
638}
639
640int
641ia64_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len,
642 enum target_hw_bp_type type,
643 struct expression *cond)
644{
645 int idx;
646 long dbr_addr, dbr_mask;
647 int max_watchpoints = 4;
648
649 if (len <= 0 || !is_power_of_2 (len))
650 return -1;
651
652 for (idx = 0; idx < max_watchpoints; idx++)
653 {
654 dbr_addr = debug_registers[2 * idx];
655 dbr_mask = debug_registers[2 * idx + 1];
656 if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
657 {
658 debug_registers[2 * idx] = 0;
659 debug_registers[2 * idx + 1] = 0;
660 dbr_addr = 0;
661 dbr_mask = 0;
662
663 for (const lwp_info *lp : all_lwps ())
664 store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
665
666 return 0;
667 }
668 }
669 return -1;
670}
671
672void
673ia64_linux_nat_target::low_new_thread (struct lwp_info *lp)
674{
675 int i, any;
676
677 any = 0;
678 for (i = 0; i < 8; i++)
679 {
680 if (debug_registers[i] != 0)
681 any = 1;
682 store_debug_register (lp->ptid, i, debug_registers[i]);
683 }
684
685 if (any)
686 enable_watchpoints_in_psr (lp->ptid);
687}
688
689bool
690ia64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
691{
692 CORE_ADDR psr;
693 siginfo_t siginfo;
694 regcache *regcache = get_thread_regcache (inferior_thread ());
695
696 if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
697 return false;
698
699 if (siginfo.si_signo != SIGTRAP
700 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
701 return false;
702
703 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
704 psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint
705 for the next instruction. */
706 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
707
708 *addr_p = (CORE_ADDR) siginfo.si_addr;
709 return true;
710}
711
712bool
713ia64_linux_nat_target::stopped_by_watchpoint ()
714{
715 CORE_ADDR addr;
716 return stopped_data_address (&addr);
717}
718
719int
720ia64_linux_nat_target::can_use_hw_breakpoint (enum bptype type,
721 int cnt, int othertype)
722{
723 return 1;
724}
725
726
727/* Fetch register REGNUM from the inferior. */
728
729static void
730ia64_linux_fetch_register (struct regcache *regcache, int regnum)
731{
732 struct gdbarch *gdbarch = regcache->arch ();
733 CORE_ADDR addr;
734 size_t size;
735 PTRACE_TYPE_RET *buf;
736 pid_t pid;
737 int i;
738
739 /* r0 cannot be fetched but is always zero. */
740 if (regnum == IA64_GR0_REGNUM)
741 {
742 regcache->raw_supply_zeroed (regnum);
743 return;
744 }
745
746 /* fr0 cannot be fetched but is always zero. */
747 if (regnum == IA64_FR0_REGNUM)
748 {
749 regcache->raw_supply_zeroed (regnum);
750 return;
751 }
752
753 /* fr1 cannot be fetched but is always one (1.0). */
754 if (regnum == IA64_FR1_REGNUM)
755 {
756 const gdb_byte f_one[16] =
757 { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
758
759 gdb_assert (sizeof (f_one) == register_size (gdbarch, regnum));
760 regcache->raw_supply (regnum, f_one);
761 return;
762 }
763
764 if (ia64_cannot_fetch_register (gdbarch, regnum))
765 {
766 regcache->raw_supply (regnum, NULL);
767 return;
768 }
769
770 pid = get_ptrace_pid (regcache->ptid ());
771
772 /* This isn't really an address, but ptrace thinks of it as one. */
773 addr = ia64_register_addr (gdbarch, regnum);
774 size = register_size (gdbarch, regnum);
775
776 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
777 buf = (PTRACE_TYPE_RET *) alloca (size);
778
779 /* Read the register contents from the inferior a chunk at a time. */
780 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
781 {
782 errno = 0;
783 buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
784 if (errno != 0)
785 error (_("Couldn't read register %s (#%d): %s."),
786 gdbarch_register_name (gdbarch, regnum),
787 regnum, safe_strerror (errno));
788
789 addr += sizeof (PTRACE_TYPE_RET);
790 }
791 regcache->raw_supply (regnum, buf);
792}
793
794/* Fetch register REGNUM from the inferior. If REGNUM is -1, do this
795 for all registers. */
796
797void
798ia64_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
799{
800 if (regnum == -1)
801 for (regnum = 0;
802 regnum < gdbarch_num_regs (regcache->arch ());
803 regnum++)
804 ia64_linux_fetch_register (regcache, regnum);
805 else
806 ia64_linux_fetch_register (regcache, regnum);
807}
808
809/* Store register REGNUM into the inferior. */
810
811static void
812ia64_linux_store_register (const struct regcache *regcache, int regnum)
813{
814 struct gdbarch *gdbarch = regcache->arch ();
815 CORE_ADDR addr;
816 size_t size;
817 PTRACE_TYPE_RET *buf;
818 pid_t pid;
819 int i;
820
821 if (ia64_cannot_store_register (gdbarch, regnum))
822 return;
823
824 pid = get_ptrace_pid (regcache->ptid ());
825
826 /* This isn't really an address, but ptrace thinks of it as one. */
827 addr = ia64_register_addr (gdbarch, regnum);
828 size = register_size (gdbarch, regnum);
829
830 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
831 buf = (PTRACE_TYPE_RET *) alloca (size);
832
833 /* Write the register contents into the inferior a chunk at a time. */
834 regcache->raw_collect (regnum, buf);
835 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
836 {
837 errno = 0;
838 ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
839 if (errno != 0)
840 error (_("Couldn't write register %s (#%d): %s."),
841 gdbarch_register_name (gdbarch, regnum),
842 regnum, safe_strerror (errno));
843
844 addr += sizeof (PTRACE_TYPE_RET);
845 }
846}
847
848/* Store register REGNUM back into the inferior. If REGNUM is -1, do
849 this for all registers. */
850
851void
852ia64_linux_nat_target::store_registers (struct regcache *regcache, int regnum)
853{
854 if (regnum == -1)
855 for (regnum = 0;
856 regnum < gdbarch_num_regs (regcache->arch ());
857 regnum++)
858 ia64_linux_store_register (regcache, regnum);
859 else
860 ia64_linux_store_register (regcache, regnum);
861}
862
863/* Implement the xfer_partial target_ops method. */
864
865enum target_xfer_status
866ia64_linux_nat_target::xfer_partial (enum target_object object,
867 const char *annex,
868 gdb_byte *readbuf, const gdb_byte *writebuf,
869 ULONGEST offset, ULONGEST len,
870 ULONGEST *xfered_len)
871{
872 if (object == TARGET_OBJECT_UNWIND_TABLE && readbuf != NULL)
873 {
874 static long gate_table_size;
875 gdb_byte *tmp_buf;
876 long res;
877
878 /* Probe for the table size once. */
879 if (gate_table_size == 0)
880 gate_table_size = syscall (__NR_getunwind, NULL, 0);
881 if (gate_table_size < 0)
882 return TARGET_XFER_E_IO;
883
884 if (offset >= gate_table_size)
885 return TARGET_XFER_EOF;
886
887 tmp_buf = (gdb_byte *) alloca (gate_table_size);
888 res = syscall (__NR_getunwind, tmp_buf, gate_table_size);
889 if (res < 0)
890 return TARGET_XFER_E_IO;
891 gdb_assert (res == gate_table_size);
892
893 if (offset + len > gate_table_size)
894 len = gate_table_size - offset;
895
896 memcpy (readbuf, tmp_buf + offset, len);
897 *xfered_len = len;
898 return TARGET_XFER_OK;
899 }
900
901 return linux_nat_target::xfer_partial (object, annex, readbuf, writebuf,
902 offset, len, xfered_len);
903}
904
905/* For break.b instruction ia64 CPU forgets the immediate value and generates
906 SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
907 ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
908 difference for the signals here. */
909
910bool
911ia64_linux_nat_target::low_status_is_event (int status)
912{
913 return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP
914 || WSTOPSIG (status) == SIGILL);
915}
916
917INIT_GDB_FILE (ia64_linux_nat)
918{
919 /* Register the target. */
920 linux_target = &the_ia64_linux_nat_target;
921 add_inf_child_target (&the_ia64_linux_nat_target);
922}
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