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1 | /* Debug register code for the i386. | |
2 | ||
3 | Copyright (C) 2001-2014 Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #ifdef GDBSERVER | |
21 | #include "server.h" | |
22 | #else | |
23 | #include "defs.h" | |
24 | #include "inferior.h" | |
25 | #endif | |
26 | #include "i386-dregs.h" | |
27 | ||
28 | /* Support for hardware watchpoints and breakpoints using the i386 | |
29 | debug registers. | |
30 | ||
31 | This provides several functions for inserting and removing | |
32 | hardware-assisted breakpoints and watchpoints, testing if one or | |
33 | more of the watchpoints triggered and at what address, checking | |
34 | whether a given region can be watched, etc. | |
35 | ||
36 | The functions below implement debug registers sharing by reference | |
37 | counts, and allow to watch regions up to 16 bytes long. */ | |
38 | ||
39 | /* Accessor macros for low-level function vector. */ | |
40 | ||
41 | /* Can we update the inferior's debug registers? */ | |
42 | #define i386_dr_low_can_set_addr() (i386_dr_low.set_addr != NULL) | |
43 | ||
44 | /* Update the inferior's debug register REGNUM from STATE. */ | |
45 | #define i386_dr_low_set_addr(new_state, i) \ | |
46 | (i386_dr_low.set_addr ((i), (new_state)->dr_mirror[(i)])) | |
47 | ||
48 | /* Return the inferior's debug register REGNUM. */ | |
49 | #define i386_dr_low_get_addr(i) (i386_dr_low.get_addr ((i))) | |
50 | ||
51 | /* Can we update the inferior's DR7 control register? */ | |
52 | #define i386_dr_low_can_set_control() (i386_dr_low.set_control != NULL) | |
53 | ||
54 | /* Update the inferior's DR7 debug control register from STATE. */ | |
55 | #define i386_dr_low_set_control(new_state) \ | |
56 | (i386_dr_low.set_control ((new_state)->dr_control_mirror)) | |
57 | ||
58 | /* Return the value of the inferior's DR7 debug control register. */ | |
59 | #define i386_dr_low_get_control() (i386_dr_low.get_control ()) | |
60 | ||
61 | /* Return the value of the inferior's DR6 debug status register. */ | |
62 | #define i386_dr_low_get_status() (i386_dr_low.get_status ()) | |
63 | ||
64 | /* Return the debug register size, in bytes. */ | |
65 | #define i386_get_debug_register_length() \ | |
66 | (i386_dr_low.debug_register_length) | |
67 | ||
68 | /* Support for 8-byte wide hw watchpoints. */ | |
69 | #define TARGET_HAS_DR_LEN_8 (i386_get_debug_register_length () == 8) | |
70 | ||
71 | /* DR7 Debug Control register fields. */ | |
72 | ||
73 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
74 | #define DR_CONTROL_SHIFT 16 | |
75 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
76 | #define DR_CONTROL_SIZE 4 | |
77 | ||
78 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
79 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ | |
80 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
81 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
82 | ||
83 | /* This is here for completeness. No platform supports this | |
84 | functionality yet (as of March 2001). Note that the DE flag in the | |
85 | CR4 register needs to be set to support this. */ | |
86 | #ifndef DR_RW_IORW | |
87 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ | |
88 | #endif | |
89 | ||
90 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
91 | is so we could OR this with the read/write field defined above. */ | |
92 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ | |
93 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
94 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
95 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
96 | ||
97 | /* Local and Global Enable flags in DR7. | |
98 | ||
99 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
100 | enabled only for the current task; the processor automatically | |
101 | clears this flag on every task switch. When the Global Enable flag | |
102 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
103 | processor never clears this flag. | |
104 | ||
105 | Currently, all watchpoint are locally enabled. If you need to | |
106 | enable them globally, read the comment which pertains to this in | |
107 | i386_insert_aligned_watchpoint below. */ | |
108 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ | |
109 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
110 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
111 | ||
112 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
113 | flags). These are only required on i386, to allow detection of the | |
114 | exact instruction which caused a watchpoint to break; i486 and | |
115 | later processors do that automatically. We set these flags for | |
116 | backwards compatibility. */ | |
117 | #define DR_LOCAL_SLOWDOWN (0x100) | |
118 | #define DR_GLOBAL_SLOWDOWN (0x200) | |
119 | ||
120 | /* Fields reserved by Intel. This includes the GD (General Detect | |
121 | Enable) flag, which causes a debug exception to be generated when a | |
122 | MOV instruction accesses one of the debug registers. | |
123 | ||
124 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
125 | #define DR_CONTROL_RESERVED (0xFC00) | |
126 | ||
127 | /* Auxiliary helper macros. */ | |
128 | ||
129 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
130 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) | |
131 | ||
132 | /* The I'th debug register is vacant if its Local and Global Enable | |
133 | bits are reset in the Debug Control register. */ | |
134 | #define I386_DR_VACANT(state, i) \ | |
135 | (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) | |
136 | ||
137 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
138 | #define I386_DR_LOCAL_ENABLE(state, i) \ | |
139 | do { \ | |
140 | (state)->dr_control_mirror |= \ | |
141 | (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
142 | } while (0) | |
143 | ||
144 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
145 | #define I386_DR_GLOBAL_ENABLE(state, i) \ | |
146 | do { \ | |
147 | (state)->dr_control_mirror |= \ | |
148 | (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
149 | } while (0) | |
150 | ||
151 | /* Disable the break/watchpoint in the I'th debug register. */ | |
152 | #define I386_DR_DISABLE(state, i) \ | |
153 | do { \ | |
154 | (state)->dr_control_mirror &= \ | |
155 | ~(3 << (DR_ENABLE_SIZE * (i))); \ | |
156 | } while (0) | |
157 | ||
158 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
159 | #define I386_DR_SET_RW_LEN(state, i, rwlen) \ | |
160 | do { \ | |
161 | (state)->dr_control_mirror &= \ | |
162 | ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
163 | (state)->dr_control_mirror |= \ | |
164 | ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
165 | } while (0) | |
166 | ||
167 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
168 | #define I386_DR_GET_RW_LEN(dr7, i) \ | |
169 | (((dr7) \ | |
170 | >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) | |
171 | ||
172 | /* Did the watchpoint whose address is in the I'th register break? */ | |
173 | #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) | |
174 | ||
175 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ | |
176 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; | |
177 | ||
178 | #ifndef GDBSERVER | |
179 | /* Whether or not to print the mirrored debug registers. */ | |
180 | extern int debug_hw_points; | |
181 | ||
182 | /* Print debugging messages. */ | |
183 | #define debug_printf(fmt, args...) \ | |
184 | fprintf_unfiltered (gdb_stdlog, fmt, ##args); | |
185 | #endif | |
186 | ||
187 | /* Print the values of the mirrored debug registers. */ | |
188 | ||
189 | static void | |
190 | i386_show_dr (struct i386_debug_reg_state *state, | |
191 | const char *func, CORE_ADDR addr, | |
192 | int len, enum target_hw_bp_type type) | |
193 | { | |
194 | int i; | |
195 | ||
196 | debug_printf ("%s", func); | |
197 | if (addr || len) | |
198 | debug_printf (" (addr=%s, len=%d, type=%s)", | |
199 | phex (addr, 8), len, | |
200 | type == hw_write ? "data-write" | |
201 | : (type == hw_read ? "data-read" | |
202 | : (type == hw_access ? "data-read/write" | |
203 | : (type == hw_execute ? "instruction-execute" | |
204 | /* FIXME: if/when I/O read/write | |
205 | watchpoints are supported, add them | |
206 | here. */ | |
207 | : "??unknown??")))); | |
208 | debug_printf (":\n"); | |
209 | debug_printf ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", | |
210 | phex (state->dr_control_mirror, 8), | |
211 | phex (state->dr_status_mirror, 8)); | |
212 | ALL_DEBUG_REGISTERS (i) | |
213 | { | |
214 | debug_printf ("\ | |
215 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", | |
216 | i, phex (state->dr_mirror[i], | |
217 | i386_get_debug_register_length ()), | |
218 | state->dr_ref_count[i], | |
219 | i + 1, phex (state->dr_mirror[i + 1], | |
220 | i386_get_debug_register_length ()), | |
221 | state->dr_ref_count[i + 1]); | |
222 | i++; | |
223 | } | |
224 | } | |
225 | ||
226 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
227 | region of LEN bytes for accesses of type TYPE. LEN is assumed to | |
228 | have the value of 1, 2, or 4. */ | |
229 | ||
230 | static unsigned | |
231 | i386_length_and_rw_bits (int len, enum target_hw_bp_type type) | |
232 | { | |
233 | unsigned rw; | |
234 | ||
235 | switch (type) | |
236 | { | |
237 | case hw_execute: | |
238 | rw = DR_RW_EXECUTE; | |
239 | break; | |
240 | case hw_write: | |
241 | rw = DR_RW_WRITE; | |
242 | break; | |
243 | case hw_read: | |
244 | internal_error (__FILE__, __LINE__, | |
245 | _("The i386 doesn't support " | |
246 | "data-read watchpoints.\n")); | |
247 | case hw_access: | |
248 | rw = DR_RW_READ; | |
249 | break; | |
250 | #if 0 | |
251 | /* Not yet supported. */ | |
252 | case hw_io_access: | |
253 | rw = DR_RW_IORW; | |
254 | break; | |
255 | #endif | |
256 | default: | |
257 | internal_error (__FILE__, __LINE__, _("\ | |
258 | Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), | |
259 | (int) type); | |
260 | } | |
261 | ||
262 | switch (len) | |
263 | { | |
264 | case 1: | |
265 | return (DR_LEN_1 | rw); | |
266 | case 2: | |
267 | return (DR_LEN_2 | rw); | |
268 | case 4: | |
269 | return (DR_LEN_4 | rw); | |
270 | case 8: | |
271 | if (TARGET_HAS_DR_LEN_8) | |
272 | return (DR_LEN_8 | rw); | |
273 | /* ELSE FALL THROUGH */ | |
274 | default: | |
275 | internal_error (__FILE__, __LINE__, _("\ | |
276 | Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); | |
277 | } | |
278 | } | |
279 | ||
280 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
281 | according to the length of the region to watch. LEN_RW_BITS is the | |
282 | value of the bits from DR7 which describes the length and access | |
283 | type of the region to be watched by this watchpoint. Return 0 on | |
284 | success, -1 on failure. */ | |
285 | ||
286 | static int | |
287 | i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, | |
288 | CORE_ADDR addr, unsigned len_rw_bits) | |
289 | { | |
290 | int i; | |
291 | ||
292 | if (!i386_dr_low_can_set_addr () || !i386_dr_low_can_set_control ()) | |
293 | return -1; | |
294 | ||
295 | /* First, look for an occupied debug register with the same address | |
296 | and the same RW and LEN definitions. If we find one, we can | |
297 | reuse it for this watchpoint as well (and save a register). */ | |
298 | ALL_DEBUG_REGISTERS (i) | |
299 | { | |
300 | if (!I386_DR_VACANT (state, i) | |
301 | && state->dr_mirror[i] == addr | |
302 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
303 | { | |
304 | state->dr_ref_count[i]++; | |
305 | return 0; | |
306 | } | |
307 | } | |
308 | ||
309 | /* Next, look for a vacant debug register. */ | |
310 | ALL_DEBUG_REGISTERS (i) | |
311 | { | |
312 | if (I386_DR_VACANT (state, i)) | |
313 | break; | |
314 | } | |
315 | ||
316 | /* No more debug registers! */ | |
317 | if (i >= DR_NADDR) | |
318 | return -1; | |
319 | ||
320 | /* Now set up the register I to watch our region. */ | |
321 | ||
322 | /* Record the info in our local mirrored array. */ | |
323 | state->dr_mirror[i] = addr; | |
324 | state->dr_ref_count[i] = 1; | |
325 | I386_DR_SET_RW_LEN (state, i, len_rw_bits); | |
326 | /* Note: we only enable the watchpoint locally, i.e. in the current | |
327 | task. Currently, no i386 target allows or supports global | |
328 | watchpoints; however, if any target would want that in the | |
329 | future, GDB should probably provide a command to control whether | |
330 | to enable watchpoints globally or locally, and the code below | |
331 | should use global or local enable and slow-down flags as | |
332 | appropriate. */ | |
333 | I386_DR_LOCAL_ENABLE (state, i); | |
334 | state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; | |
335 | state->dr_control_mirror &= I386_DR_CONTROL_MASK; | |
336 | ||
337 | return 0; | |
338 | } | |
339 | ||
340 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
341 | according to the length of the region to watch. LEN_RW_BITS is the | |
342 | value of the bits from DR7 which describes the length and access | |
343 | type of the region watched by this watchpoint. Return 0 on | |
344 | success, -1 on failure. */ | |
345 | ||
346 | static int | |
347 | i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, | |
348 | CORE_ADDR addr, unsigned len_rw_bits) | |
349 | { | |
350 | int i, retval = -1; | |
351 | ||
352 | ALL_DEBUG_REGISTERS (i) | |
353 | { | |
354 | if (!I386_DR_VACANT (state, i) | |
355 | && state->dr_mirror[i] == addr | |
356 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
357 | { | |
358 | if (--state->dr_ref_count[i] == 0) /* No longer in use? */ | |
359 | { | |
360 | /* Reset our mirror. */ | |
361 | state->dr_mirror[i] = 0; | |
362 | I386_DR_DISABLE (state, i); | |
363 | } | |
364 | retval = 0; | |
365 | } | |
366 | } | |
367 | ||
368 | return retval; | |
369 | } | |
370 | ||
371 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
372 | number of debug registers required to watch a region at address | |
373 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
374 | successful insertion or removal, a positive number when queried | |
375 | about the number of registers, or -1 on failure. If WHAT is not a | |
376 | valid value, bombs through internal_error. */ | |
377 | ||
378 | static int | |
379 | i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, | |
380 | i386_wp_op_t what, CORE_ADDR addr, int len, | |
381 | enum target_hw_bp_type type) | |
382 | { | |
383 | int retval = 0; | |
384 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; | |
385 | ||
386 | static const int size_try_array[8][8] = | |
387 | { | |
388 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ | |
389 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
390 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
391 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
392 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
393 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
394 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
395 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
396 | }; | |
397 | ||
398 | while (len > 0) | |
399 | { | |
400 | int align = addr % max_wp_len; | |
401 | /* Four (eight on AMD64) is the maximum length a debug register | |
402 | can watch. */ | |
403 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); | |
404 | int size = size_try_array[try][align]; | |
405 | ||
406 | if (what == WP_COUNT) | |
407 | { | |
408 | /* size_try_array[] is defined such that each iteration | |
409 | through the loop is guaranteed to produce an address and a | |
410 | size that can be watched with a single debug register. | |
411 | Thus, for counting the registers required to watch a | |
412 | region, we simply need to increment the count on each | |
413 | iteration. */ | |
414 | retval++; | |
415 | } | |
416 | else | |
417 | { | |
418 | unsigned len_rw = i386_length_and_rw_bits (size, type); | |
419 | ||
420 | if (what == WP_INSERT) | |
421 | retval = i386_insert_aligned_watchpoint (state, addr, len_rw); | |
422 | else if (what == WP_REMOVE) | |
423 | retval = i386_remove_aligned_watchpoint (state, addr, len_rw); | |
424 | else | |
425 | internal_error (__FILE__, __LINE__, _("\ | |
426 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), | |
427 | (int) what); | |
428 | if (retval) | |
429 | break; | |
430 | } | |
431 | ||
432 | addr += size; | |
433 | len -= size; | |
434 | } | |
435 | ||
436 | return retval; | |
437 | } | |
438 | ||
439 | /* Update the inferior debug registers state, in STATE, with the | |
440 | new debug registers state, in NEW_STATE. */ | |
441 | ||
442 | static void | |
443 | i386_update_inferior_debug_regs (struct i386_debug_reg_state *state, | |
444 | struct i386_debug_reg_state *new_state) | |
445 | { | |
446 | int i; | |
447 | ||
448 | ALL_DEBUG_REGISTERS (i) | |
449 | { | |
450 | if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (state, i)) | |
451 | i386_dr_low_set_addr (new_state, i); | |
452 | else | |
453 | gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]); | |
454 | } | |
455 | ||
456 | if (new_state->dr_control_mirror != state->dr_control_mirror) | |
457 | i386_dr_low_set_control (new_state); | |
458 | ||
459 | *state = *new_state; | |
460 | } | |
461 | ||
462 | /* Insert a watchpoint to watch a memory region which starts at | |
463 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
464 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
465 | ||
466 | int | |
467 | i386_dr_insert_watchpoint (struct i386_debug_reg_state *state, | |
468 | enum target_hw_bp_type type, | |
469 | CORE_ADDR addr, int len) | |
470 | { | |
471 | int retval; | |
472 | /* Work on a local copy of the debug registers, and on success, | |
473 | commit the change back to the inferior. */ | |
474 | struct i386_debug_reg_state local_state = *state; | |
475 | ||
476 | if (type == hw_read) | |
477 | return 1; /* unsupported */ | |
478 | ||
479 | if (((len != 1 && len != 2 && len != 4) | |
480 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
481 | || addr % len != 0) | |
482 | { | |
483 | retval = i386_handle_nonaligned_watchpoint (&local_state, | |
484 | WP_INSERT, | |
485 | addr, len, type); | |
486 | } | |
487 | else | |
488 | { | |
489 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
490 | ||
491 | retval = i386_insert_aligned_watchpoint (&local_state, | |
492 | addr, len_rw); | |
493 | } | |
494 | ||
495 | if (retval == 0) | |
496 | i386_update_inferior_debug_regs (state, &local_state); | |
497 | ||
498 | if (debug_hw_points) | |
499 | i386_show_dr (state, "insert_watchpoint", addr, len, type); | |
500 | ||
501 | return retval; | |
502 | } | |
503 | ||
504 | /* Remove a watchpoint that watched the memory region which starts at | |
505 | address ADDR, whose length is LEN bytes, and for accesses of the | |
506 | type TYPE. Return 0 on success, -1 on failure. */ | |
507 | ||
508 | int | |
509 | i386_dr_remove_watchpoint (struct i386_debug_reg_state *state, | |
510 | enum target_hw_bp_type type, | |
511 | CORE_ADDR addr, int len) | |
512 | { | |
513 | int retval; | |
514 | /* Work on a local copy of the debug registers, and on success, | |
515 | commit the change back to the inferior. */ | |
516 | struct i386_debug_reg_state local_state = *state; | |
517 | ||
518 | if (((len != 1 && len != 2 && len != 4) | |
519 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
520 | || addr % len != 0) | |
521 | { | |
522 | retval = i386_handle_nonaligned_watchpoint (&local_state, | |
523 | WP_REMOVE, | |
524 | addr, len, type); | |
525 | } | |
526 | else | |
527 | { | |
528 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
529 | ||
530 | retval = i386_remove_aligned_watchpoint (&local_state, | |
531 | addr, len_rw); | |
532 | } | |
533 | ||
534 | if (retval == 0) | |
535 | i386_update_inferior_debug_regs (state, &local_state); | |
536 | ||
537 | if (debug_hw_points) | |
538 | i386_show_dr (state, "remove_watchpoint", addr, len, type); | |
539 | ||
540 | return retval; | |
541 | } | |
542 | ||
543 | /* Return non-zero if we can watch a memory region that starts at | |
544 | address ADDR and whose length is LEN bytes. */ | |
545 | ||
546 | int | |
547 | i386_dr_region_ok_for_watchpoint (struct i386_debug_reg_state *state, | |
548 | CORE_ADDR addr, int len) | |
549 | { | |
550 | int nregs; | |
551 | ||
552 | /* Compute how many aligned watchpoints we would need to cover this | |
553 | region. */ | |
554 | nregs = i386_handle_nonaligned_watchpoint (state, WP_COUNT, | |
555 | addr, len, hw_write); | |
556 | return nregs <= DR_NADDR ? 1 : 0; | |
557 | } | |
558 | ||
559 | /* If the inferior has some break/watchpoint that triggered, set the | |
560 | address associated with that break/watchpoint and return non-zero. | |
561 | Otherwise, return zero. */ | |
562 | ||
563 | int | |
564 | i386_dr_stopped_data_address (struct i386_debug_reg_state *state, | |
565 | CORE_ADDR *addr_p) | |
566 | { | |
567 | CORE_ADDR addr = 0; | |
568 | int i; | |
569 | int rc = 0; | |
570 | /* The current thread's DR_STATUS. We always need to read this to | |
571 | check whether some watchpoint caused the trap. */ | |
572 | unsigned status; | |
573 | /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a | |
574 | data breakpoint trap. Only fetch it when necessary, to avoid an | |
575 | unnecessary extra syscall when no watchpoint triggered. */ | |
576 | int control_p = 0; | |
577 | unsigned control = 0; | |
578 | ||
579 | /* In non-stop/async, threads can be running while we change the | |
580 | global dr_mirror (and friends). Say, we set a watchpoint, and | |
581 | let threads resume. Now, say you delete the watchpoint, or | |
582 | add/remove watchpoints such that dr_mirror changes while threads | |
583 | are running. On targets that support non-stop, | |
584 | inserting/deleting watchpoints updates the global dr_mirror only. | |
585 | It does not update the real thread's debug registers; that's only | |
586 | done prior to resume. Instead, if threads are running when the | |
587 | mirror changes, a temporary and transparent stop on all threads | |
588 | is forced so they can get their copy of the debug registers | |
589 | updated on re-resume. Now, say, a thread hit a watchpoint before | |
590 | having been updated with the new dr_mirror contents, and we | |
591 | haven't yet handled the corresponding SIGTRAP. If we trusted | |
592 | dr_mirror below, we'd mistake the real trapped address (from the | |
593 | last time we had updated debug registers in the thread) with | |
594 | whatever was currently in dr_mirror. So to fix this, dr_mirror | |
595 | always represents intention, what we _want_ threads to have in | |
596 | debug registers. To get at the address and cause of the trap, we | |
597 | need to read the state the thread still has in its debug | |
598 | registers. | |
599 | ||
600 | In sum, always get the current debug register values the current | |
601 | thread has, instead of trusting the global mirror. If the thread | |
602 | was running when we last changed watchpoints, the mirror no | |
603 | longer represents what was set in this thread's debug | |
604 | registers. */ | |
605 | status = i386_dr_low_get_status (); | |
606 | ||
607 | ALL_DEBUG_REGISTERS (i) | |
608 | { | |
609 | if (!I386_DR_WATCH_HIT (status, i)) | |
610 | continue; | |
611 | ||
612 | if (!control_p) | |
613 | { | |
614 | control = i386_dr_low_get_control (); | |
615 | control_p = 1; | |
616 | } | |
617 | ||
618 | /* This second condition makes sure DRi is set up for a data | |
619 | watchpoint, not a hardware breakpoint. The reason is that | |
620 | GDB doesn't call the target_stopped_data_address method | |
621 | except for data watchpoints. In other words, I'm being | |
622 | paranoiac. */ | |
623 | if (I386_DR_GET_RW_LEN (control, i) != 0) | |
624 | { | |
625 | addr = i386_dr_low_get_addr (i); | |
626 | rc = 1; | |
627 | if (debug_hw_points) | |
628 | i386_show_dr (state, "watchpoint_hit", addr, -1, hw_write); | |
629 | } | |
630 | } | |
631 | ||
632 | if (debug_hw_points && addr == 0) | |
633 | i386_show_dr (state, "stopped_data_addr", 0, 0, hw_write); | |
634 | ||
635 | if (rc) | |
636 | *addr_p = addr; | |
637 | return rc; | |
638 | } | |
639 | ||
640 | /* Return non-zero if the inferior has some watchpoint that triggered. | |
641 | Otherwise return zero. */ | |
642 | ||
643 | int | |
644 | i386_dr_stopped_by_watchpoint (struct i386_debug_reg_state *state) | |
645 | { | |
646 | CORE_ADDR addr = 0; | |
647 | return i386_dr_stopped_data_address (state, &addr); | |
648 | } |