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1 | /* AArch64 assembler/disassembler support. | |
2 | ||
3 | Copyright (C) 2009-2016 Free Software Foundation, Inc. | |
4 | Contributed by ARM Ltd. | |
5 | ||
6 | This file is part of GNU Binutils. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the license, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; see the file COPYING3. If not, | |
20 | see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #ifndef OPCODE_AARCH64_H | |
23 | #define OPCODE_AARCH64_H | |
24 | ||
25 | #include "bfd.h" | |
26 | #include "bfd_stdint.h" | |
27 | #include <assert.h> | |
28 | #include <stdlib.h> | |
29 | ||
30 | #ifdef __cplusplus | |
31 | extern "C" { | |
32 | #endif | |
33 | ||
34 | /* The offset for pc-relative addressing is currently defined to be 0. */ | |
35 | #define AARCH64_PCREL_OFFSET 0 | |
36 | ||
37 | typedef uint32_t aarch64_insn; | |
38 | ||
39 | /* The following bitmasks control CPU features. */ | |
40 | #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ | |
41 | #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ | |
42 | #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ | |
43 | #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ | |
44 | #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ | |
45 | #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ | |
46 | #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ | |
47 | #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */ | |
48 | #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */ | |
49 | #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */ | |
50 | #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */ | |
51 | #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */ | |
52 | #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */ | |
53 | #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */ | |
54 | ||
55 | /* Architectures are the sum of the base and extensions. */ | |
56 | #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ | |
57 | AARCH64_FEATURE_FP \ | |
58 | | AARCH64_FEATURE_SIMD) | |
59 | #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ | |
60 | AARCH64_FEATURE_FP \ | |
61 | | AARCH64_FEATURE_SIMD \ | |
62 | | AARCH64_FEATURE_CRC \ | |
63 | | AARCH64_FEATURE_V8_1 \ | |
64 | | AARCH64_FEATURE_LSE \ | |
65 | | AARCH64_FEATURE_PAN \ | |
66 | | AARCH64_FEATURE_LOR \ | |
67 | | AARCH64_FEATURE_RDMA) | |
68 | #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ | |
69 | AARCH64_FEATURE_V8_2 \ | |
70 | | AARCH64_FEATURE_F16 \ | |
71 | | AARCH64_FEATURE_RAS \ | |
72 | | AARCH64_FEATURE_FP \ | |
73 | | AARCH64_FEATURE_SIMD \ | |
74 | | AARCH64_FEATURE_CRC \ | |
75 | | AARCH64_FEATURE_V8_1 \ | |
76 | | AARCH64_FEATURE_LSE \ | |
77 | | AARCH64_FEATURE_PAN \ | |
78 | | AARCH64_FEATURE_LOR \ | |
79 | | AARCH64_FEATURE_RDMA) | |
80 | ||
81 | #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) | |
82 | #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ | |
83 | ||
84 | /* CPU-specific features. */ | |
85 | typedef unsigned long aarch64_feature_set; | |
86 | ||
87 | #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ | |
88 | ((~(CPU) & (FEAT)) == 0) | |
89 | ||
90 | #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ | |
91 | (((CPU) & (FEAT)) != 0) | |
92 | ||
93 | #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ | |
94 | AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT) | |
95 | ||
96 | #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ | |
97 | do \ | |
98 | { \ | |
99 | (TARG) = (F1) | (F2); \ | |
100 | } \ | |
101 | while (0) | |
102 | ||
103 | #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ | |
104 | do \ | |
105 | { \ | |
106 | (TARG) = (F1) &~ (F2); \ | |
107 | } \ | |
108 | while (0) | |
109 | ||
110 | #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) | |
111 | ||
112 | enum aarch64_operand_class | |
113 | { | |
114 | AARCH64_OPND_CLASS_NIL, | |
115 | AARCH64_OPND_CLASS_INT_REG, | |
116 | AARCH64_OPND_CLASS_MODIFIED_REG, | |
117 | AARCH64_OPND_CLASS_FP_REG, | |
118 | AARCH64_OPND_CLASS_SIMD_REG, | |
119 | AARCH64_OPND_CLASS_SIMD_ELEMENT, | |
120 | AARCH64_OPND_CLASS_SISD_REG, | |
121 | AARCH64_OPND_CLASS_SIMD_REGLIST, | |
122 | AARCH64_OPND_CLASS_CP_REG, | |
123 | AARCH64_OPND_CLASS_SVE_REG, | |
124 | AARCH64_OPND_CLASS_PRED_REG, | |
125 | AARCH64_OPND_CLASS_ADDRESS, | |
126 | AARCH64_OPND_CLASS_IMMEDIATE, | |
127 | AARCH64_OPND_CLASS_SYSTEM, | |
128 | AARCH64_OPND_CLASS_COND, | |
129 | }; | |
130 | ||
131 | /* Operand code that helps both parsing and coding. | |
132 | Keep AARCH64_OPERANDS synced. */ | |
133 | ||
134 | enum aarch64_opnd | |
135 | { | |
136 | AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ | |
137 | ||
138 | AARCH64_OPND_Rd, /* Integer register as destination. */ | |
139 | AARCH64_OPND_Rn, /* Integer register as source. */ | |
140 | AARCH64_OPND_Rm, /* Integer register as source. */ | |
141 | AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ | |
142 | AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ | |
143 | AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ | |
144 | AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ | |
145 | AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ | |
146 | ||
147 | AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ | |
148 | AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ | |
149 | AARCH64_OPND_PAIRREG, /* Paired register operand. */ | |
150 | AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ | |
151 | AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ | |
152 | ||
153 | AARCH64_OPND_Fd, /* Floating-point Fd. */ | |
154 | AARCH64_OPND_Fn, /* Floating-point Fn. */ | |
155 | AARCH64_OPND_Fm, /* Floating-point Fm. */ | |
156 | AARCH64_OPND_Fa, /* Floating-point Fa. */ | |
157 | AARCH64_OPND_Ft, /* Floating-point Ft. */ | |
158 | AARCH64_OPND_Ft2, /* Floating-point Ft2. */ | |
159 | ||
160 | AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ | |
161 | AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ | |
162 | AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ | |
163 | ||
164 | AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ | |
165 | AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ | |
166 | AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ | |
167 | AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ | |
168 | AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ | |
169 | AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ | |
170 | AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ | |
171 | AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ | |
172 | AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ | |
173 | AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ | |
174 | AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single | |
175 | structure to all lanes. */ | |
176 | AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ | |
177 | ||
178 | AARCH64_OPND_Cn, /* Co-processor register in CRn field. */ | |
179 | AARCH64_OPND_Cm, /* Co-processor register in CRm field. */ | |
180 | ||
181 | AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ | |
182 | AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ | |
183 | AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ | |
184 | AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ | |
185 | AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ | |
186 | AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ | |
187 | AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction | |
188 | (no encoding). */ | |
189 | AARCH64_OPND_IMM0, /* Immediate for #0. */ | |
190 | AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ | |
191 | AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ | |
192 | AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ | |
193 | AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ | |
194 | AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ | |
195 | AARCH64_OPND_IMM, /* Immediate. */ | |
196 | AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ | |
197 | AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ | |
198 | AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ | |
199 | AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ | |
200 | AARCH64_OPND_BIT_NUM, /* Immediate. */ | |
201 | AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ | |
202 | AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ | |
203 | AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for | |
204 | each condition flag. */ | |
205 | ||
206 | AARCH64_OPND_LIMM, /* Logical Immediate. */ | |
207 | AARCH64_OPND_AIMM, /* Arithmetic immediate. */ | |
208 | AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ | |
209 | AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ | |
210 | AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ | |
211 | ||
212 | AARCH64_OPND_COND, /* Standard condition as the last operand. */ | |
213 | AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ | |
214 | ||
215 | AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ | |
216 | AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ | |
217 | AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ | |
218 | AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ | |
219 | AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ | |
220 | ||
221 | AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ | |
222 | AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ | |
223 | AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ | |
224 | AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ | |
225 | AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is | |
226 | negative or unaligned and there is | |
227 | no writeback allowed. This operand code | |
228 | is only used to support the programmer- | |
229 | friendly feature of using LDR/STR as the | |
230 | the mnemonic name for LDUR/STUR instructions | |
231 | wherever there is no ambiguity. */ | |
232 | AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ | |
233 | AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ | |
234 | AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ | |
235 | ||
236 | AARCH64_OPND_SYSREG, /* System register operand. */ | |
237 | AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ | |
238 | AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ | |
239 | AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ | |
240 | AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ | |
241 | AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ | |
242 | AARCH64_OPND_BARRIER, /* Barrier operand. */ | |
243 | AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ | |
244 | AARCH64_OPND_PRFOP, /* Prefetch operation. */ | |
245 | AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ | |
246 | ||
247 | AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */ | |
248 | AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */ | |
249 | AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */ | |
250 | AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */ | |
251 | AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */ | |
252 | AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */ | |
253 | AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */ | |
254 | AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ | |
255 | AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ | |
256 | AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ | |
257 | AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ | |
258 | AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ | |
259 | AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ | |
260 | AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ | |
261 | AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ | |
262 | AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ | |
263 | AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ | |
264 | AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */ | |
265 | AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */ | |
266 | AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */ | |
267 | AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */ | |
268 | AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */ | |
269 | AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. | |
270 | Bit 14 controls S/U choice. */ | |
271 | AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. | |
272 | Bit 22 controls S/U choice. */ | |
273 | AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. | |
274 | Bit 14 controls S/U choice. */ | |
275 | AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. | |
276 | Bit 22 controls S/U choice. */ | |
277 | AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. | |
278 | Bit 14 controls S/U choice. */ | |
279 | AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. | |
280 | Bit 22 controls S/U choice. */ | |
281 | AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. | |
282 | Bit 14 controls S/U choice. */ | |
283 | AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. | |
284 | Bit 22 controls S/U choice. */ | |
285 | AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */ | |
286 | AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */ | |
287 | AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */ | |
288 | AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */ | |
289 | AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */ | |
290 | AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */ | |
291 | AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */ | |
292 | AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */ | |
293 | AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */ | |
294 | AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */ | |
295 | AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */ | |
296 | AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */ | |
297 | AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */ | |
298 | AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */ | |
299 | AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */ | |
300 | AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */ | |
301 | AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */ | |
302 | AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */ | |
303 | AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ | |
304 | AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ | |
305 | AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ | |
306 | AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */ | |
307 | AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */ | |
308 | AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ | |
309 | AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ | |
310 | AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ | |
311 | AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ | |
312 | AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ | |
313 | }; | |
314 | ||
315 | /* Qualifier constrains an operand. It either specifies a variant of an | |
316 | operand type or limits values available to an operand type. | |
317 | ||
318 | N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ | |
319 | ||
320 | enum aarch64_opnd_qualifier | |
321 | { | |
322 | /* Indicating no further qualification on an operand. */ | |
323 | AARCH64_OPND_QLF_NIL, | |
324 | ||
325 | /* Qualifying an operand which is a general purpose (integer) register; | |
326 | indicating the operand data size or a specific register. */ | |
327 | AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ | |
328 | AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ | |
329 | AARCH64_OPND_QLF_WSP, /* WSP. */ | |
330 | AARCH64_OPND_QLF_SP, /* SP. */ | |
331 | ||
332 | /* Qualifying an operand which is a floating-point register, a SIMD | |
333 | vector element or a SIMD vector element list; indicating operand data | |
334 | size or the size of each SIMD vector element in the case of a SIMD | |
335 | vector element list. | |
336 | These qualifiers are also used to qualify an address operand to | |
337 | indicate the size of data element a load/store instruction is | |
338 | accessing. | |
339 | They are also used for the immediate shift operand in e.g. SSHR. Such | |
340 | a use is only for the ease of operand encoding/decoding and qualifier | |
341 | sequence matching; such a use should not be applied widely; use the value | |
342 | constraint qualifiers for immediate operands wherever possible. */ | |
343 | AARCH64_OPND_QLF_S_B, | |
344 | AARCH64_OPND_QLF_S_H, | |
345 | AARCH64_OPND_QLF_S_S, | |
346 | AARCH64_OPND_QLF_S_D, | |
347 | AARCH64_OPND_QLF_S_Q, | |
348 | ||
349 | /* Qualifying an operand which is a SIMD vector register or a SIMD vector | |
350 | register list; indicating register shape. | |
351 | They are also used for the immediate shift operand in e.g. SSHR. Such | |
352 | a use is only for the ease of operand encoding/decoding and qualifier | |
353 | sequence matching; such a use should not be applied widely; use the value | |
354 | constraint qualifiers for immediate operands wherever possible. */ | |
355 | AARCH64_OPND_QLF_V_8B, | |
356 | AARCH64_OPND_QLF_V_16B, | |
357 | AARCH64_OPND_QLF_V_2H, | |
358 | AARCH64_OPND_QLF_V_4H, | |
359 | AARCH64_OPND_QLF_V_8H, | |
360 | AARCH64_OPND_QLF_V_2S, | |
361 | AARCH64_OPND_QLF_V_4S, | |
362 | AARCH64_OPND_QLF_V_1D, | |
363 | AARCH64_OPND_QLF_V_2D, | |
364 | AARCH64_OPND_QLF_V_1Q, | |
365 | ||
366 | AARCH64_OPND_QLF_P_Z, | |
367 | AARCH64_OPND_QLF_P_M, | |
368 | ||
369 | /* Constraint on value. */ | |
370 | AARCH64_OPND_QLF_imm_0_7, | |
371 | AARCH64_OPND_QLF_imm_0_15, | |
372 | AARCH64_OPND_QLF_imm_0_31, | |
373 | AARCH64_OPND_QLF_imm_0_63, | |
374 | AARCH64_OPND_QLF_imm_1_32, | |
375 | AARCH64_OPND_QLF_imm_1_64, | |
376 | ||
377 | /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros | |
378 | or shift-ones. */ | |
379 | AARCH64_OPND_QLF_LSL, | |
380 | AARCH64_OPND_QLF_MSL, | |
381 | ||
382 | /* Special qualifier helping retrieve qualifier information during the | |
383 | decoding time (currently not in use). */ | |
384 | AARCH64_OPND_QLF_RETRIEVE, | |
385 | }; | |
386 | \f | |
387 | /* Instruction class. */ | |
388 | ||
389 | enum aarch64_insn_class | |
390 | { | |
391 | addsub_carry, | |
392 | addsub_ext, | |
393 | addsub_imm, | |
394 | addsub_shift, | |
395 | asimdall, | |
396 | asimddiff, | |
397 | asimdelem, | |
398 | asimdext, | |
399 | asimdimm, | |
400 | asimdins, | |
401 | asimdmisc, | |
402 | asimdperm, | |
403 | asimdsame, | |
404 | asimdshf, | |
405 | asimdtbl, | |
406 | asisddiff, | |
407 | asisdelem, | |
408 | asisdlse, | |
409 | asisdlsep, | |
410 | asisdlso, | |
411 | asisdlsop, | |
412 | asisdmisc, | |
413 | asisdone, | |
414 | asisdpair, | |
415 | asisdsame, | |
416 | asisdshf, | |
417 | bitfield, | |
418 | branch_imm, | |
419 | branch_reg, | |
420 | compbranch, | |
421 | condbranch, | |
422 | condcmp_imm, | |
423 | condcmp_reg, | |
424 | condsel, | |
425 | cryptoaes, | |
426 | cryptosha2, | |
427 | cryptosha3, | |
428 | dp_1src, | |
429 | dp_2src, | |
430 | dp_3src, | |
431 | exception, | |
432 | extract, | |
433 | float2fix, | |
434 | float2int, | |
435 | floatccmp, | |
436 | floatcmp, | |
437 | floatdp1, | |
438 | floatdp2, | |
439 | floatdp3, | |
440 | floatimm, | |
441 | floatsel, | |
442 | ldst_immpost, | |
443 | ldst_immpre, | |
444 | ldst_imm9, /* immpost or immpre */ | |
445 | ldst_pos, | |
446 | ldst_regoff, | |
447 | ldst_unpriv, | |
448 | ldst_unscaled, | |
449 | ldstexcl, | |
450 | ldstnapair_offs, | |
451 | ldstpair_off, | |
452 | ldstpair_indexed, | |
453 | loadlit, | |
454 | log_imm, | |
455 | log_shift, | |
456 | lse_atomic, | |
457 | movewide, | |
458 | pcreladdr, | |
459 | ic_system, | |
460 | testbranch, | |
461 | }; | |
462 | ||
463 | /* Opcode enumerators. */ | |
464 | ||
465 | enum aarch64_op | |
466 | { | |
467 | OP_NIL, | |
468 | OP_STRB_POS, | |
469 | OP_LDRB_POS, | |
470 | OP_LDRSB_POS, | |
471 | OP_STRH_POS, | |
472 | OP_LDRH_POS, | |
473 | OP_LDRSH_POS, | |
474 | OP_STR_POS, | |
475 | OP_LDR_POS, | |
476 | OP_STRF_POS, | |
477 | OP_LDRF_POS, | |
478 | OP_LDRSW_POS, | |
479 | OP_PRFM_POS, | |
480 | ||
481 | OP_STURB, | |
482 | OP_LDURB, | |
483 | OP_LDURSB, | |
484 | OP_STURH, | |
485 | OP_LDURH, | |
486 | OP_LDURSH, | |
487 | OP_STUR, | |
488 | OP_LDUR, | |
489 | OP_STURV, | |
490 | OP_LDURV, | |
491 | OP_LDURSW, | |
492 | OP_PRFUM, | |
493 | ||
494 | OP_LDR_LIT, | |
495 | OP_LDRV_LIT, | |
496 | OP_LDRSW_LIT, | |
497 | OP_PRFM_LIT, | |
498 | ||
499 | OP_ADD, | |
500 | OP_B, | |
501 | OP_BL, | |
502 | ||
503 | OP_MOVN, | |
504 | OP_MOVZ, | |
505 | OP_MOVK, | |
506 | ||
507 | OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ | |
508 | OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ | |
509 | OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ | |
510 | ||
511 | OP_MOV_V, /* MOV alias for moving vector register. */ | |
512 | ||
513 | OP_ASR_IMM, | |
514 | OP_LSR_IMM, | |
515 | OP_LSL_IMM, | |
516 | ||
517 | OP_BIC, | |
518 | ||
519 | OP_UBFX, | |
520 | OP_BFXIL, | |
521 | OP_SBFX, | |
522 | OP_SBFIZ, | |
523 | OP_BFI, | |
524 | OP_BFC, /* ARMv8.2. */ | |
525 | OP_UBFIZ, | |
526 | OP_UXTB, | |
527 | OP_UXTH, | |
528 | OP_UXTW, | |
529 | ||
530 | OP_CINC, | |
531 | OP_CINV, | |
532 | OP_CNEG, | |
533 | OP_CSET, | |
534 | OP_CSETM, | |
535 | ||
536 | OP_FCVT, | |
537 | OP_FCVTN, | |
538 | OP_FCVTN2, | |
539 | OP_FCVTL, | |
540 | OP_FCVTL2, | |
541 | OP_FCVTXN_S, /* Scalar version. */ | |
542 | ||
543 | OP_ROR_IMM, | |
544 | ||
545 | OP_SXTL, | |
546 | OP_SXTL2, | |
547 | OP_UXTL, | |
548 | OP_UXTL2, | |
549 | ||
550 | OP_TOTAL_NUM, /* Pseudo. */ | |
551 | }; | |
552 | ||
553 | /* Maximum number of operands an instruction can have. */ | |
554 | #define AARCH64_MAX_OPND_NUM 6 | |
555 | /* Maximum number of qualifier sequences an instruction can have. */ | |
556 | #define AARCH64_MAX_QLF_SEQ_NUM 10 | |
557 | /* Operand qualifier typedef; optimized for the size. */ | |
558 | typedef unsigned char aarch64_opnd_qualifier_t; | |
559 | /* Operand qualifier sequence typedef. */ | |
560 | typedef aarch64_opnd_qualifier_t \ | |
561 | aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; | |
562 | ||
563 | /* FIXME: improve the efficiency. */ | |
564 | static inline bfd_boolean | |
565 | empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) | |
566 | { | |
567 | int i; | |
568 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
569 | if (qualifiers[i] != AARCH64_OPND_QLF_NIL) | |
570 | return FALSE; | |
571 | return TRUE; | |
572 | } | |
573 | ||
574 | /* This structure holds information for a particular opcode. */ | |
575 | ||
576 | struct aarch64_opcode | |
577 | { | |
578 | /* The name of the mnemonic. */ | |
579 | const char *name; | |
580 | ||
581 | /* The opcode itself. Those bits which will be filled in with | |
582 | operands are zeroes. */ | |
583 | aarch64_insn opcode; | |
584 | ||
585 | /* The opcode mask. This is used by the disassembler. This is a | |
586 | mask containing ones indicating those bits which must match the | |
587 | opcode field, and zeroes indicating those bits which need not | |
588 | match (and are presumably filled in by operands). */ | |
589 | aarch64_insn mask; | |
590 | ||
591 | /* Instruction class. */ | |
592 | enum aarch64_insn_class iclass; | |
593 | ||
594 | /* Enumerator identifier. */ | |
595 | enum aarch64_op op; | |
596 | ||
597 | /* Which architecture variant provides this instruction. */ | |
598 | const aarch64_feature_set *avariant; | |
599 | ||
600 | /* An array of operand codes. Each code is an index into the | |
601 | operand table. They appear in the order which the operands must | |
602 | appear in assembly code, and are terminated by a zero. */ | |
603 | enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; | |
604 | ||
605 | /* A list of operand qualifier code sequence. Each operand qualifier | |
606 | code qualifies the corresponding operand code. Each operand | |
607 | qualifier sequence specifies a valid opcode variant and related | |
608 | constraint on operands. */ | |
609 | aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; | |
610 | ||
611 | /* Flags providing information about this instruction */ | |
612 | uint32_t flags; | |
613 | ||
614 | /* If nonzero, this operand and operand 0 are both registers and | |
615 | are required to have the same register number. */ | |
616 | unsigned char tied_operand; | |
617 | ||
618 | /* If non-NULL, a function to verify that a given instruction is valid. */ | |
619 | bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn); | |
620 | }; | |
621 | ||
622 | typedef struct aarch64_opcode aarch64_opcode; | |
623 | ||
624 | /* Table describing all the AArch64 opcodes. */ | |
625 | extern aarch64_opcode aarch64_opcode_table[]; | |
626 | ||
627 | /* Opcode flags. */ | |
628 | #define F_ALIAS (1 << 0) | |
629 | #define F_HAS_ALIAS (1 << 1) | |
630 | /* Disassembly preference priority 1-3 (the larger the higher). If nothing | |
631 | is specified, it is the priority 0 by default, i.e. the lowest priority. */ | |
632 | #define F_P1 (1 << 2) | |
633 | #define F_P2 (2 << 2) | |
634 | #define F_P3 (3 << 2) | |
635 | /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ | |
636 | #define F_COND (1 << 4) | |
637 | /* Instruction has the field of 'sf'. */ | |
638 | #define F_SF (1 << 5) | |
639 | /* Instruction has the field of 'size:Q'. */ | |
640 | #define F_SIZEQ (1 << 6) | |
641 | /* Floating-point instruction has the field of 'type'. */ | |
642 | #define F_FPTYPE (1 << 7) | |
643 | /* AdvSIMD scalar instruction has the field of 'size'. */ | |
644 | #define F_SSIZE (1 << 8) | |
645 | /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ | |
646 | #define F_T (1 << 9) | |
647 | /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ | |
648 | #define F_GPRSIZE_IN_Q (1 << 10) | |
649 | /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ | |
650 | #define F_LDS_SIZE (1 << 11) | |
651 | /* Optional operand; assume maximum of 1 operand can be optional. */ | |
652 | #define F_OPD0_OPT (1 << 12) | |
653 | #define F_OPD1_OPT (2 << 12) | |
654 | #define F_OPD2_OPT (3 << 12) | |
655 | #define F_OPD3_OPT (4 << 12) | |
656 | #define F_OPD4_OPT (5 << 12) | |
657 | /* Default value for the optional operand when omitted from the assembly. */ | |
658 | #define F_DEFAULT(X) (((X) & 0x1f) << 15) | |
659 | /* Instruction that is an alias of another instruction needs to be | |
660 | encoded/decoded by converting it to/from the real form, followed by | |
661 | the encoding/decoding according to the rules of the real opcode. | |
662 | This compares to the direct coding using the alias's information. | |
663 | N.B. this flag requires F_ALIAS to be used together. */ | |
664 | #define F_CONV (1 << 20) | |
665 | /* Use together with F_ALIAS to indicate an alias opcode is a programmer | |
666 | friendly pseudo instruction available only in the assembly code (thus will | |
667 | not show up in the disassembly). */ | |
668 | #define F_PSEUDO (1 << 21) | |
669 | /* Instruction has miscellaneous encoding/decoding rules. */ | |
670 | #define F_MISC (1 << 22) | |
671 | /* Instruction has the field of 'N'; used in conjunction with F_SF. */ | |
672 | #define F_N (1 << 23) | |
673 | /* Opcode dependent field. */ | |
674 | #define F_OD(X) (((X) & 0x7) << 24) | |
675 | /* Instruction has the field of 'sz'. */ | |
676 | #define F_LSE_SZ (1 << 27) | |
677 | /* Require an exact qualifier match, even for NIL qualifiers. */ | |
678 | #define F_STRICT (1ULL << 28) | |
679 | /* Next bit is 29. */ | |
680 | ||
681 | static inline bfd_boolean | |
682 | alias_opcode_p (const aarch64_opcode *opcode) | |
683 | { | |
684 | return (opcode->flags & F_ALIAS) ? TRUE : FALSE; | |
685 | } | |
686 | ||
687 | static inline bfd_boolean | |
688 | opcode_has_alias (const aarch64_opcode *opcode) | |
689 | { | |
690 | return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; | |
691 | } | |
692 | ||
693 | /* Priority for disassembling preference. */ | |
694 | static inline int | |
695 | opcode_priority (const aarch64_opcode *opcode) | |
696 | { | |
697 | return (opcode->flags >> 2) & 0x3; | |
698 | } | |
699 | ||
700 | static inline bfd_boolean | |
701 | pseudo_opcode_p (const aarch64_opcode *opcode) | |
702 | { | |
703 | return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; | |
704 | } | |
705 | ||
706 | static inline bfd_boolean | |
707 | optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) | |
708 | { | |
709 | return (((opcode->flags >> 12) & 0x7) == idx + 1) | |
710 | ? TRUE : FALSE; | |
711 | } | |
712 | ||
713 | static inline aarch64_insn | |
714 | get_optional_operand_default_value (const aarch64_opcode *opcode) | |
715 | { | |
716 | return (opcode->flags >> 15) & 0x1f; | |
717 | } | |
718 | ||
719 | static inline unsigned int | |
720 | get_opcode_dependent_value (const aarch64_opcode *opcode) | |
721 | { | |
722 | return (opcode->flags >> 24) & 0x7; | |
723 | } | |
724 | ||
725 | static inline bfd_boolean | |
726 | opcode_has_special_coder (const aarch64_opcode *opcode) | |
727 | { | |
728 | return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T | |
729 | | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE | |
730 | : FALSE; | |
731 | } | |
732 | \f | |
733 | struct aarch64_name_value_pair | |
734 | { | |
735 | const char * name; | |
736 | aarch64_insn value; | |
737 | }; | |
738 | ||
739 | extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; | |
740 | extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; | |
741 | extern const struct aarch64_name_value_pair aarch64_prfops [32]; | |
742 | extern const struct aarch64_name_value_pair aarch64_hint_options []; | |
743 | ||
744 | typedef struct | |
745 | { | |
746 | const char * name; | |
747 | aarch64_insn value; | |
748 | uint32_t flags; | |
749 | } aarch64_sys_reg; | |
750 | ||
751 | extern const aarch64_sys_reg aarch64_sys_regs []; | |
752 | extern const aarch64_sys_reg aarch64_pstatefields []; | |
753 | extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); | |
754 | extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set, | |
755 | const aarch64_sys_reg *); | |
756 | extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set, | |
757 | const aarch64_sys_reg *); | |
758 | ||
759 | typedef struct | |
760 | { | |
761 | const char *name; | |
762 | uint32_t value; | |
763 | uint32_t flags ; | |
764 | } aarch64_sys_ins_reg; | |
765 | ||
766 | extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); | |
767 | extern bfd_boolean | |
768 | aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, | |
769 | const aarch64_sys_ins_reg *); | |
770 | ||
771 | extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; | |
772 | extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; | |
773 | extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; | |
774 | extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; | |
775 | ||
776 | /* Shift/extending operator kinds. | |
777 | N.B. order is important; keep aarch64_operand_modifiers synced. */ | |
778 | enum aarch64_modifier_kind | |
779 | { | |
780 | AARCH64_MOD_NONE, | |
781 | AARCH64_MOD_MSL, | |
782 | AARCH64_MOD_ROR, | |
783 | AARCH64_MOD_ASR, | |
784 | AARCH64_MOD_LSR, | |
785 | AARCH64_MOD_LSL, | |
786 | AARCH64_MOD_UXTB, | |
787 | AARCH64_MOD_UXTH, | |
788 | AARCH64_MOD_UXTW, | |
789 | AARCH64_MOD_UXTX, | |
790 | AARCH64_MOD_SXTB, | |
791 | AARCH64_MOD_SXTH, | |
792 | AARCH64_MOD_SXTW, | |
793 | AARCH64_MOD_SXTX, | |
794 | AARCH64_MOD_MUL, | |
795 | AARCH64_MOD_MUL_VL, | |
796 | }; | |
797 | ||
798 | bfd_boolean | |
799 | aarch64_extend_operator_p (enum aarch64_modifier_kind); | |
800 | ||
801 | enum aarch64_modifier_kind | |
802 | aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); | |
803 | /* Condition. */ | |
804 | ||
805 | typedef struct | |
806 | { | |
807 | /* A list of names with the first one as the disassembly preference; | |
808 | terminated by NULL if fewer than 3. */ | |
809 | const char *names[3]; | |
810 | aarch64_insn value; | |
811 | } aarch64_cond; | |
812 | ||
813 | extern const aarch64_cond aarch64_conds[16]; | |
814 | ||
815 | const aarch64_cond* get_cond_from_value (aarch64_insn value); | |
816 | const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); | |
817 | \f | |
818 | /* Structure representing an operand. */ | |
819 | ||
820 | struct aarch64_opnd_info | |
821 | { | |
822 | enum aarch64_opnd type; | |
823 | aarch64_opnd_qualifier_t qualifier; | |
824 | int idx; | |
825 | ||
826 | union | |
827 | { | |
828 | struct | |
829 | { | |
830 | unsigned regno; | |
831 | } reg; | |
832 | struct | |
833 | { | |
834 | unsigned int regno; | |
835 | int64_t index; | |
836 | } reglane; | |
837 | /* e.g. LVn. */ | |
838 | struct | |
839 | { | |
840 | unsigned first_regno : 5; | |
841 | unsigned num_regs : 3; | |
842 | /* 1 if it is a list of reg element. */ | |
843 | unsigned has_index : 1; | |
844 | /* Lane index; valid only when has_index is 1. */ | |
845 | int64_t index; | |
846 | } reglist; | |
847 | /* e.g. immediate or pc relative address offset. */ | |
848 | struct | |
849 | { | |
850 | int64_t value; | |
851 | unsigned is_fp : 1; | |
852 | } imm; | |
853 | /* e.g. address in STR (register offset). */ | |
854 | struct | |
855 | { | |
856 | unsigned base_regno; | |
857 | struct | |
858 | { | |
859 | union | |
860 | { | |
861 | int imm; | |
862 | unsigned regno; | |
863 | }; | |
864 | unsigned is_reg; | |
865 | } offset; | |
866 | unsigned pcrel : 1; /* PC-relative. */ | |
867 | unsigned writeback : 1; | |
868 | unsigned preind : 1; /* Pre-indexed. */ | |
869 | unsigned postind : 1; /* Post-indexed. */ | |
870 | } addr; | |
871 | const aarch64_cond *cond; | |
872 | /* The encoding of the system register. */ | |
873 | aarch64_insn sysreg; | |
874 | /* The encoding of the PSTATE field. */ | |
875 | aarch64_insn pstatefield; | |
876 | const aarch64_sys_ins_reg *sysins_op; | |
877 | const struct aarch64_name_value_pair *barrier; | |
878 | const struct aarch64_name_value_pair *hint_option; | |
879 | const struct aarch64_name_value_pair *prfop; | |
880 | }; | |
881 | ||
882 | /* Operand shifter; in use when the operand is a register offset address, | |
883 | add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ | |
884 | struct | |
885 | { | |
886 | enum aarch64_modifier_kind kind; | |
887 | unsigned operator_present: 1; /* Only valid during encoding. */ | |
888 | /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ | |
889 | unsigned amount_present: 1; | |
890 | int64_t amount; | |
891 | } shifter; | |
892 | ||
893 | unsigned skip:1; /* Operand is not completed if there is a fixup needed | |
894 | to be done on it. In some (but not all) of these | |
895 | cases, we need to tell libopcodes to skip the | |
896 | constraint checking and the encoding for this | |
897 | operand, so that the libopcodes can pick up the | |
898 | right opcode before the operand is fixed-up. This | |
899 | flag should only be used during the | |
900 | assembling/encoding. */ | |
901 | unsigned present:1; /* Whether this operand is present in the assembly | |
902 | line; not used during the disassembly. */ | |
903 | }; | |
904 | ||
905 | typedef struct aarch64_opnd_info aarch64_opnd_info; | |
906 | ||
907 | /* Structure representing an instruction. | |
908 | ||
909 | It is used during both the assembling and disassembling. The assembler | |
910 | fills an aarch64_inst after a successful parsing and then passes it to the | |
911 | encoding routine to do the encoding. During the disassembling, the | |
912 | disassembler calls the decoding routine to decode a binary instruction; on a | |
913 | successful return, such a structure will be filled with information of the | |
914 | instruction; then the disassembler uses the information to print out the | |
915 | instruction. */ | |
916 | ||
917 | struct aarch64_inst | |
918 | { | |
919 | /* The value of the binary instruction. */ | |
920 | aarch64_insn value; | |
921 | ||
922 | /* Corresponding opcode entry. */ | |
923 | const aarch64_opcode *opcode; | |
924 | ||
925 | /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ | |
926 | const aarch64_cond *cond; | |
927 | ||
928 | /* Operands information. */ | |
929 | aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; | |
930 | }; | |
931 | ||
932 | typedef struct aarch64_inst aarch64_inst; | |
933 | \f | |
934 | /* Diagnosis related declaration and interface. */ | |
935 | ||
936 | /* Operand error kind enumerators. | |
937 | ||
938 | AARCH64_OPDE_RECOVERABLE | |
939 | Less severe error found during the parsing, very possibly because that | |
940 | GAS has picked up a wrong instruction template for the parsing. | |
941 | ||
942 | AARCH64_OPDE_SYNTAX_ERROR | |
943 | General syntax error; it can be either a user error, or simply because | |
944 | that GAS is trying a wrong instruction template. | |
945 | ||
946 | AARCH64_OPDE_FATAL_SYNTAX_ERROR | |
947 | Definitely a user syntax error. | |
948 | ||
949 | AARCH64_OPDE_INVALID_VARIANT | |
950 | No syntax error, but the operands are not a valid combination, e.g. | |
951 | FMOV D0,S0 | |
952 | ||
953 | AARCH64_OPDE_UNTIED_OPERAND | |
954 | The asm failed to use the same register for a destination operand | |
955 | and a tied source operand. | |
956 | ||
957 | AARCH64_OPDE_OUT_OF_RANGE | |
958 | Error about some immediate value out of a valid range. | |
959 | ||
960 | AARCH64_OPDE_UNALIGNED | |
961 | Error about some immediate value not properly aligned (i.e. not being a | |
962 | multiple times of a certain value). | |
963 | ||
964 | AARCH64_OPDE_REG_LIST | |
965 | Error about the register list operand having unexpected number of | |
966 | registers. | |
967 | ||
968 | AARCH64_OPDE_OTHER_ERROR | |
969 | Error of the highest severity and used for any severe issue that does not | |
970 | fall into any of the above categories. | |
971 | ||
972 | The enumerators are only interesting to GAS. They are declared here (in | |
973 | libopcodes) because that some errors are detected (and then notified to GAS) | |
974 | by libopcodes (rather than by GAS solely). | |
975 | ||
976 | The first three errors are only deteced by GAS while the | |
977 | AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as | |
978 | only libopcodes has the information about the valid variants of each | |
979 | instruction. | |
980 | ||
981 | The enumerators have an increasing severity. This is helpful when there are | |
982 | multiple instruction templates available for a given mnemonic name (e.g. | |
983 | FMOV); this mechanism will help choose the most suitable template from which | |
984 | the generated diagnostics can most closely describe the issues, if any. */ | |
985 | ||
986 | enum aarch64_operand_error_kind | |
987 | { | |
988 | AARCH64_OPDE_NIL, | |
989 | AARCH64_OPDE_RECOVERABLE, | |
990 | AARCH64_OPDE_SYNTAX_ERROR, | |
991 | AARCH64_OPDE_FATAL_SYNTAX_ERROR, | |
992 | AARCH64_OPDE_INVALID_VARIANT, | |
993 | AARCH64_OPDE_UNTIED_OPERAND, | |
994 | AARCH64_OPDE_OUT_OF_RANGE, | |
995 | AARCH64_OPDE_UNALIGNED, | |
996 | AARCH64_OPDE_REG_LIST, | |
997 | AARCH64_OPDE_OTHER_ERROR | |
998 | }; | |
999 | ||
1000 | /* N.B. GAS assumes that this structure work well with shallow copy. */ | |
1001 | struct aarch64_operand_error | |
1002 | { | |
1003 | enum aarch64_operand_error_kind kind; | |
1004 | int index; | |
1005 | const char *error; | |
1006 | int data[3]; /* Some data for extra information. */ | |
1007 | }; | |
1008 | ||
1009 | typedef struct aarch64_operand_error aarch64_operand_error; | |
1010 | ||
1011 | /* Encoding entrypoint. */ | |
1012 | ||
1013 | extern int | |
1014 | aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, | |
1015 | aarch64_insn *, aarch64_opnd_qualifier_t *, | |
1016 | aarch64_operand_error *); | |
1017 | ||
1018 | extern const aarch64_opcode * | |
1019 | aarch64_replace_opcode (struct aarch64_inst *, | |
1020 | const aarch64_opcode *); | |
1021 | ||
1022 | /* Given the opcode enumerator OP, return the pointer to the corresponding | |
1023 | opcode entry. */ | |
1024 | ||
1025 | extern const aarch64_opcode * | |
1026 | aarch64_get_opcode (enum aarch64_op); | |
1027 | ||
1028 | /* Generate the string representation of an operand. */ | |
1029 | extern void | |
1030 | aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, | |
1031 | const aarch64_opnd_info *, int, int *, bfd_vma *); | |
1032 | ||
1033 | /* Miscellaneous interface. */ | |
1034 | ||
1035 | extern int | |
1036 | aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); | |
1037 | ||
1038 | extern aarch64_opnd_qualifier_t | |
1039 | aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, | |
1040 | const aarch64_opnd_qualifier_t, int); | |
1041 | ||
1042 | extern int | |
1043 | aarch64_num_of_operands (const aarch64_opcode *); | |
1044 | ||
1045 | extern int | |
1046 | aarch64_stack_pointer_p (const aarch64_opnd_info *); | |
1047 | ||
1048 | extern int | |
1049 | aarch64_zero_register_p (const aarch64_opnd_info *); | |
1050 | ||
1051 | extern int | |
1052 | aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean); | |
1053 | ||
1054 | /* Given an operand qualifier, return the expected data element size | |
1055 | of a qualified operand. */ | |
1056 | extern unsigned char | |
1057 | aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); | |
1058 | ||
1059 | extern enum aarch64_operand_class | |
1060 | aarch64_get_operand_class (enum aarch64_opnd); | |
1061 | ||
1062 | extern const char * | |
1063 | aarch64_get_operand_name (enum aarch64_opnd); | |
1064 | ||
1065 | extern const char * | |
1066 | aarch64_get_operand_desc (enum aarch64_opnd); | |
1067 | ||
1068 | #ifdef DEBUG_AARCH64 | |
1069 | extern int debug_dump; | |
1070 | ||
1071 | extern void | |
1072 | aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); | |
1073 | ||
1074 | #define DEBUG_TRACE(M, ...) \ | |
1075 | { \ | |
1076 | if (debug_dump) \ | |
1077 | aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ | |
1078 | } | |
1079 | ||
1080 | #define DEBUG_TRACE_IF(C, M, ...) \ | |
1081 | { \ | |
1082 | if (debug_dump && (C)) \ | |
1083 | aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ | |
1084 | } | |
1085 | #else /* !DEBUG_AARCH64 */ | |
1086 | #define DEBUG_TRACE(M, ...) ; | |
1087 | #define DEBUG_TRACE_IF(C, M, ...) ; | |
1088 | #endif /* DEBUG_AARCH64 */ | |
1089 | ||
1090 | extern const char *const aarch64_sve_pattern_array[32]; | |
1091 | extern const char *const aarch64_sve_prfop_array[16]; | |
1092 | ||
1093 | #ifdef __cplusplus | |
1094 | } | |
1095 | #endif | |
1096 | ||
1097 | #endif /* OPCODE_AARCH64_H */ |