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1/* riscv.h. RISC-V opcode list for GDB, the GNU debugger.
2 Copyright (C) 2011-2025 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 3, or (at your option) any later version.
11
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21#ifndef _RISCV_H_
22#define _RISCV_H_
23
24#include "riscv-opc.h"
25#include <stdlib.h>
26#include <stdint.h>
27
28typedef uint64_t insn_t;
29
30static inline unsigned int riscv_insn_length (insn_t insn)
31{
32 if ((insn & 0x3) != 0x3) /* RVC instructions. */
33 return 2;
34 if ((insn & 0x1f) != 0x1f) /* 32-bit instructions. */
35 return 4;
36 if ((insn & 0x3f) == 0x1f) /* 48-bit instructions. */
37 return 6;
38 if ((insn & 0x7f) == 0x3f) /* 64-bit instructions. */
39 return 8;
40 /* 80- ... 176-bit instructions. */
41 if ((insn & 0x7f) == 0x7f && (insn & 0x7000) != 0x7000)
42 return 10 + ((insn >> 11) & 0xe);
43 /* Maximum value returned by this function. */
44#define RISCV_MAX_INSN_LEN 22
45 /* Longer instructions not supported at the moment. */
46 return 2;
47}
48
49#define RVC_JUMP_BITS 11
50#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
51
52#define RVC_BRANCH_BITS 8
53#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
54
55#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
56#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
57#define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n)))
58#define RV_IMM_SIGN_N(x, s, n) (-(((x) >> ((s) + (n) - 1)) & 1))
59
60#define EXTRACT_ITYPE_IMM(x) \
61 (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
62#define EXTRACT_STYPE_IMM(x) \
63 (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
64#define EXTRACT_BTYPE_IMM(x) \
65 ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
66#define EXTRACT_UTYPE_IMM(x) \
67 ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
68#define EXTRACT_JTYPE_IMM(x) \
69 ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
70#define EXTRACT_CITYPE_IMM(x) \
71 (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
72#define EXTRACT_CITYPE_LUI_IMM(x) \
73 (EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS)
74#define EXTRACT_CITYPE_ADDI16SP_IMM(x) \
75 ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
76#define EXTRACT_CITYPE_LWSP_IMM(x) \
77 ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
78#define EXTRACT_CITYPE_LDSP_IMM(x) \
79 ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
80#define EXTRACT_CSSTYPE_IMM(x) \
81 (RV_X(x, 7, 6) << 0)
82#define EXTRACT_CSSTYPE_SWSP_IMM(x) \
83 ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
84#define EXTRACT_CSSTYPE_SDSP_IMM(x) \
85 ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
86#define EXTRACT_CIWTYPE_IMM(x) \
87 (RV_X(x, 5, 8))
88#define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \
89 ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
90#define EXTRACT_CLTYPE_IMM(x) \
91 ((RV_X(x, 5, 2) << 0) | (RV_X(x, 10, 3) << 2))
92#define EXTRACT_CLTYPE_LW_IMM(x) \
93 ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
94#define EXTRACT_CLTYPE_LD_IMM(x) \
95 ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
96#define EXTRACT_CBTYPE_IMM(x) \
97 ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
98#define EXTRACT_CJTYPE_IMM(x) \
99 ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
100#define EXTRACT_RVV_VI_IMM(x) \
101 (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
102#define EXTRACT_RVV_VI_UIMM(x) \
103 (RV_X(x, 15, 5))
104#define EXTRACT_RVV_VI_UIMM6(x) \
105 (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5))
106#define EXTRACT_RVV_OFFSET(x) \
107 (RV_X(x, 29, 3))
108#define EXTRACT_RVV_VB_IMM(x) \
109 (RV_X(x, 20, 10))
110#define EXTRACT_RVV_VC_IMM(x) \
111 (RV_X(x, 20, 11))
112#define EXTRACT_ZCB_BYTE_UIMM(x) \
113 (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1))
114#define EXTRACT_ZCB_HALFWORD_UIMM(x) \
115 (RV_X(x, 5, 1) << 1)
116#define EXTRACT_ZCMP_SPIMM(x) \
117 (RV_X(x, 2, 2) << 4)
118#define EXTRACT_ZCMT_INDEX(x) \
119 (RV_X(x, 2, 8))
120/* Vendor-specific (CORE-V) extract macros. */
121#define EXTRACT_CV_IS2_UIMM5(x) \
122 (RV_X(x, 20, 5))
123#define EXTRACT_CV_IS3_UIMM5(x) \
124 (RV_X(x, 25, 5))
125#define EXTRACT_CV_BI_IMM5(x) \
126 (RV_X(x, 20, 5) | (RV_IMM_SIGN_N(x, 20, 5) << 5))
127#define EXTRACT_CV_BITMANIP_UIMM5(x) \
128 (RV_X(x, 25, 5))
129#define EXTRACT_CV_BITMANIP_UIMM2(x) \
130 (RV_X(x, 25, 2))
131#define EXTRACT_CV_SIMD_IMM6(x) \
132 ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1) | (RV_IMM_SIGN_N(x, 20, 5) << 5))
133#define EXTRACT_CV_SIMD_UIMM6(x) \
134 ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1))
135/* Vendor-specific (MIPS) extract macros. */
136#define EXTRACT_MIPS_LWP_IMM(x) \
137 (RV_X(x, 22, 5) << 2)
138#define EXTRACT_MIPS_LDP_IMM(x) \
139 (RV_X(x, 23, 4) << 3)
140#define EXTRACT_MIPS_SWP_IMM(x) \
141 ((RV_X(x, 25, 2) << 5) | (RV_X(x, 9, 3) << 2))
142#define EXTRACT_MIPS_SDP_IMM(x) \
143 ((RV_X(x, 25, 2) << 5) | (RV_X(x, 10, 2) << 3))
144
145#define ENCODE_ITYPE_IMM(x) \
146 (RV_X(x, 0, 12) << 20)
147#define ENCODE_STYPE_IMM(x) \
148 ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
149#define ENCODE_BTYPE_IMM(x) \
150 ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
151#define ENCODE_UTYPE_IMM(x) \
152 (RV_X(x, 12, 20) << 12)
153#define ENCODE_JTYPE_IMM(x) \
154 ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
155#define ENCODE_CITYPE_IMM(x) \
156 ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
157#define ENCODE_CITYPE_LUI_IMM(x) \
158 ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS)
159#define ENCODE_CITYPE_ADDI16SP_IMM(x) \
160 ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
161#define ENCODE_CITYPE_LWSP_IMM(x) \
162 ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
163#define ENCODE_CITYPE_LDSP_IMM(x) \
164 ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
165#define ENCODE_CSSTYPE_IMM(x) \
166 (RV_X(x, 0, 6) << 7)
167#define ENCODE_CSSTYPE_SWSP_IMM(x) \
168 ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
169#define ENCODE_CSSTYPE_SDSP_IMM(x) \
170 ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
171#define ENCODE_CIWTYPE_IMM(x) \
172 (RV_X(x, 0, 8) << 5)
173#define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \
174 ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
175#define ENCODE_CLTYPE_IMM(x) \
176 ((RV_X(x, 0, 2) << 5) | (RV_X(x, 2, 3) << 10))
177#define ENCODE_CLTYPE_LW_IMM(x) \
178 ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
179#define ENCODE_CLTYPE_LD_IMM(x) \
180 ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
181#define ENCODE_CBTYPE_IMM(x) \
182 ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
183#define ENCODE_CJTYPE_IMM(x) \
184 ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
185#define ENCODE_RVV_VB_IMM(x) \
186 (RV_X(x, 0, 10) << 20)
187#define ENCODE_RVV_VC_IMM(x) \
188 (RV_X(x, 0, 11) << 20)
189#define ENCODE_RVV_VI_UIMM6(x) \
190 (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26)
191#define ENCODE_ZCB_BYTE_UIMM(x) \
192 ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5))
193#define ENCODE_ZCB_HALFWORD_UIMM(x) \
194 (RV_X(x, 1, 1) << 5)
195#define ENCODE_ZCMP_SPIMM(x) \
196 (RV_X(x, 4, 2) << 2)
197#define ENCODE_ZCMT_INDEX(x) \
198 (RV_X(x, 0, 8) << 2)
199/* Vendor-specific (CORE-V) encode macros. */
200#define ENCODE_CV_IS2_UIMM5(x) \
201 (RV_X(x, 0, 5) << 20)
202#define ENCODE_CV_IS3_UIMM5(x) \
203 (RV_X(x, 0, 5) << 25)
204#define ENCODE_CV_BITMANIP_UIMM5(x) \
205 (RV_X(x, 0, 5) << 25)
206#define ENCODE_CV_BITMANIP_UIMM2(x) \
207 (RV_X(x, 0, 2) << 25)
208#define ENCODE_CV_SIMD_IMM6(x) \
209 ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20))
210#define ENCODE_CV_SIMD_UIMM6(x) \
211 ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20))
212/* Vendor-specific (MIPS) encode macros. */
213#define ENCODE_MIPS_LWP_IMM(x) \
214 (RV_X(x, 2, 5) << 22)
215#define ENCODE_MIPS_LDP_IMM(x) \
216 (RV_X(x, 3, 4) << 23)
217#define ENCODE_MIPS_SWP_IMM(x) \
218 ((RV_X(x, 5, 2) << 25) | (RV_X(x, 2, 3) << 9))
219#define ENCODE_MIPS_SDP_IMM(x) \
220 ((RV_X(x, 5, 2) << 25) | (RV_X(x, 3, 2) << 10))
221
222#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
223#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
224#define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x))
225#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
226#define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x))
227#define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x))
228#define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \
229 && EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x))
230#define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \
231 && EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x))
232#define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x))
233#define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x))
234#define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x))
235#define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x))
236#define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x))
237#define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x))
238#define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x))
239#define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x))
240#define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x))
241#define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x))
242#define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x))
243#define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))
244#define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x))
245#define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
246#define VALID_ZCB_BYTE_UIMM(x) (EXTRACT_ZCB_BYTE_UIMM(ENCODE_ZCB_BYTE_UIMM(x)) == (x))
247#define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_HALFWORD_UIMM(x)) == (x))
248#define VALID_ZCMP_SPIMM(x) (EXTRACT_ZCMP_SPIMM(ENCODE_ZCMP_SPIMM(x)) == (x))
249
250#define RISCV_RTYPE(insn, rd, rs1, rs2) \
251 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
252#define RISCV_ITYPE(insn, rd, rs1, imm) \
253 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
254#define RISCV_STYPE(insn, rs1, rs2, imm) \
255 ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
256#define RISCV_BTYPE(insn, rs1, rs2, target) \
257 ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_BTYPE_IMM(target))
258#define RISCV_UTYPE(insn, rd, bigimm) \
259 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
260#define RISCV_JTYPE(insn, rd, target) \
261 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_JTYPE_IMM(target))
262
263#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
264#define RVC_NOP MATCH_C_ADDI
265
266#define RISCV_CONST_HIGH_PART(VALUE) \
267 (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
268#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
269#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
270#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
271
272#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
273#define RISCV_JUMP_ALIGN_BITS 1
274#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
275#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
276
277#define RISCV_IMM_BITS 12
278#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
279#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
280#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
281#define RISCV_RVC_IMM_REACH (1LL << 6)
282#define RISCV_BRANCH_BITS RISCV_IMM_BITS
283#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
284#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
285#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
286
287/* RV fields. */
288
289#define OP_MASK_OP 0x7f
290#define OP_SH_OP 0
291#define OP_MASK_RS2 0x1f
292#define OP_SH_RS2 20
293#define OP_MASK_RS1 0x1f
294#define OP_SH_RS1 15
295#define OP_MASK_RS3 0x1fU
296#define OP_SH_RS3 27
297#define OP_MASK_RD 0x1f
298#define OP_SH_RD 7
299#define OP_MASK_SHAMT 0x3f
300#define OP_SH_SHAMT 20
301#define OP_MASK_SHAMTW 0x1f
302#define OP_SH_SHAMTW 20
303#define OP_MASK_RM 0x7
304#define OP_SH_RM 12
305#define OP_MASK_PRED 0xf
306#define OP_SH_PRED 24
307#define OP_MASK_SUCC 0xf
308#define OP_SH_SUCC 20
309#define OP_MASK_AQ 0x1
310#define OP_SH_AQ 26
311#define OP_MASK_RL 0x1
312#define OP_SH_RL 25
313
314#define OP_MASK_CSR 0xfffU
315#define OP_SH_CSR 20
316
317#define OP_MASK_FUNCT3 0x7
318#define OP_SH_FUNCT3 12
319#define OP_MASK_FUNCT7 0x7fU
320#define OP_SH_FUNCT7 25
321#define OP_MASK_FUNCT2 0x3
322#define OP_SH_FUNCT2 25
323
324/* RVC fields. */
325
326#define OP_MASK_OP2 0x3
327#define OP_SH_OP2 0
328
329#define OP_MASK_CRS2 0x1f
330#define OP_SH_CRS2 2
331#define OP_MASK_CRS1S 0x7
332#define OP_SH_CRS1S 7
333#define OP_MASK_CRS2S 0x7
334#define OP_SH_CRS2S 2
335
336#define OP_MASK_CFUNCT6 0x3f
337#define OP_SH_CFUNCT6 10
338#define OP_MASK_CFUNCT4 0xf
339#define OP_SH_CFUNCT4 12
340#define OP_MASK_CFUNCT3 0x7
341#define OP_SH_CFUNCT3 13
342#define OP_MASK_CFUNCT2 0x3
343#define OP_SH_CFUNCT2 5
344
345/* Scalar crypto fields. */
346
347#define OP_SH_BS 30
348#define OP_MASK_BS 3
349#define OP_SH_RNUM 20
350#define OP_MASK_RNUM 0xf
351
352/* RVV fields. */
353
354#define OP_MASK_VD 0x1f
355#define OP_SH_VD 7
356#define OP_MASK_VS1 0x1f
357#define OP_SH_VS1 15
358#define OP_MASK_VS2 0x1f
359#define OP_SH_VS2 20
360#define OP_MASK_VIMM 0x1f
361#define OP_SH_VIMM 15
362#define OP_MASK_VMASK 0x1
363#define OP_SH_VMASK 25
364#define OP_MASK_VFUNCT6 0x3f
365#define OP_SH_VFUNCT6 26
366#define OP_MASK_VLMUL 0x7
367#define OP_SH_VLMUL 0
368#define OP_MASK_VSEW 0x7
369#define OP_SH_VSEW 3
370#define OP_MASK_VTA 0x1
371#define OP_SH_VTA 6
372#define OP_MASK_VMA 0x1
373#define OP_SH_VMA 7
374#define OP_MASK_VWD 0x1
375#define OP_SH_VWD 26
376
377#define OP_MASK_XTHEADVLMUL 0x3
378#define OP_SH_XTHEADVLMUL 0
379#define OP_MASK_XTHEADVSEW 0x7
380#define OP_SH_XTHEADVSEW 2
381#define OP_MASK_XTHEADVEDIV 0x3
382#define OP_SH_XTHEADVEDIV 5
383#define OP_MASK_XTHEADVTYPE_RES 0xf
384#define OP_SH_XTHEADVTYPE_RES 7
385
386/* Zc fields. */
387#define OP_MASK_REG_LIST 0xf
388#define OP_SH_REG_LIST 4
389#define ZCMP_SP_ALIGNMENT 16
390#define OP_MASK_SREG1 0x7
391#define OP_SH_SREG1 7
392#define OP_MASK_SREG2 0x7
393#define OP_SH_SREG2 2
394
395#define NVECR 32
396#define NVECM 1
397
398/* SiFive fields. */
399#define OP_MASK_XSO2 0x3
400#define OP_SH_XSO2 26
401#define OP_MASK_XSO1 0x1
402#define OP_SH_XSO1 26
403
404/* MIPS fields. */
405#define OP_MASK_MIPS_IMM9 0x1ff
406#define OP_SH_MIPS_IMM9 20
407#define OP_MASK_MIPS_HINT 0x1f
408#define OP_SH_MIPS_HINT 7
409#define OP_MASK_MIPS_LWP_OFFSET 0x1f
410#define OP_SH_MIPS_LWP_OFFSET 22
411#define OP_MASK_MIPS_LDP_OFFSET 0xf
412#define OP_SH_MIPS_LDP_OFFSET 23
413#define OP_MASK_MIPS_SWP_OFFSET9 0x7
414#define OP_SH_MIPS_SWP_OFFSET9 9
415#define OP_MASK_MIPS_SWP_OFFSET25 0x3
416#define OP_SH_MIPS_SWP_OFFSET25 25
417#define OP_MASK_MIPS_SDP_OFFSET10 0x3
418#define OP_SH_MIPS_SDP_OFFSET10 10
419#define OP_MASK_MIPS_SDP_OFFSET25 0x3
420#define OP_SH_MIPS_SDP_OFFSET25 25
421
422/* ABI names for selected x-registers. */
423
424#define X_ZERO 0
425#define X_RA 1
426#define X_SP 2
427#define X_GP 3
428#define X_TP 4
429#define X_T0 5
430#define X_T1 6
431#define X_T2 7
432#define X_S0 8
433#define X_S1 9
434#define X_A0 10
435#define X_A1 11
436#define X_S2 18
437#define X_S7 23
438#define X_S10 26
439#define X_S11 27
440#define X_T3 28
441
442#define NGPR 32
443#define NFPR 32
444
445/* These fake label defines are use by both the assembler, and
446 libopcodes. The assembler uses this when it needs to generate a fake
447 label, and libopcodes uses it to hide the fake labels in its output. */
448#define RISCV_FAKE_LABEL_NAME ".L0 "
449#define RISCV_FAKE_LABEL_CHAR ' '
450
451/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
452 VALUE << SHIFT. VALUE is evaluated exactly once. */
453#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
454 (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
455 | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
456
457/* Extract bits MASK << SHIFT from STRUCT and shift them right
458 SHIFT places. */
459#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
460 (((STRUCT) >> (SHIFT)) & (MASK))
461
462/* Extract the operand given by FIELD from integer INSN. */
463#define EXTRACT_OPERAND(FIELD, INSN) \
464 ((unsigned int) EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD))
465
466/* Extract an unsigned immediate operand on position s with n bits. */
467#define EXTRACT_U_IMM(n, s, l) \
468 RV_X (l, s, n)
469
470/* Extract an signed immediate operand on position s with n bits. */
471#define EXTRACT_S_IMM(n, s, l) \
472 RV_X_SIGNED (l, s, n)
473
474/* Validate that unsigned n-bit immediate is within bounds. */
475#define VALIDATE_U_IMM(v, n) \
476 ((unsigned long) v < (1UL << n))
477
478/* Validate that signed n-bit immediate is within bounds. */
479#define VALIDATE_S_IMM(v, n) \
480 (v < (long) (1UL << (n-1)) && v >= -(offsetT) (1UL << (n-1)))
481
482/* The maximal number of subset can be required. */
483#define MAX_SUBSET_NUM 4
484
485/* The range of sregs. */
486#define RISCV_SREG_0_7(REGNO) \
487 ((REGNO == X_S0 || REGNO == X_S1) \
488 || (REGNO >= X_S2 && REGNO <= X_S7))
489
490/* All RISC-V instructions belong to at least one of these classes. */
491enum riscv_insn_class
492{
493 INSN_CLASS_NONE,
494
495 INSN_CLASS_I,
496 INSN_CLASS_C,
497 INSN_CLASS_M,
498 INSN_CLASS_F,
499 INSN_CLASS_D,
500 INSN_CLASS_Q,
501 INSN_CLASS_F_AND_C,
502 INSN_CLASS_D_AND_C,
503 INSN_CLASS_ZICOND,
504 INSN_CLASS_ZICSR,
505 INSN_CLASS_ZIFENCEI,
506 INSN_CLASS_ZIHINTNTL,
507 INSN_CLASS_ZIHINTNTL_AND_C,
508 INSN_CLASS_ZIHINTPAUSE,
509 INSN_CLASS_ZIMOP,
510 INSN_CLASS_ZMMUL,
511 INSN_CLASS_ZAAMO,
512 INSN_CLASS_ZALRSC,
513 INSN_CLASS_ZAWRS,
514 INSN_CLASS_F_INX,
515 INSN_CLASS_D_INX,
516 INSN_CLASS_Q_INX,
517 INSN_CLASS_ZFH_INX,
518 INSN_CLASS_ZFHMIN,
519 INSN_CLASS_ZFHMIN_INX,
520 INSN_CLASS_ZFHMIN_AND_D_INX,
521 INSN_CLASS_ZFHMIN_AND_Q_INX,
522 INSN_CLASS_ZFBFMIN,
523 INSN_CLASS_ZFA,
524 INSN_CLASS_D_AND_ZFA,
525 INSN_CLASS_Q_AND_ZFA,
526 INSN_CLASS_ZFH_AND_ZFA,
527 INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA,
528 INSN_CLASS_ZBA,
529 INSN_CLASS_ZBB,
530 INSN_CLASS_ZBC,
531 INSN_CLASS_ZBS,
532 INSN_CLASS_ZBKB,
533 INSN_CLASS_ZBKC,
534 INSN_CLASS_ZBKX,
535 INSN_CLASS_ZKND,
536 INSN_CLASS_ZKNE,
537 INSN_CLASS_ZKNH,
538 INSN_CLASS_ZKSED,
539 INSN_CLASS_ZKSH,
540 INSN_CLASS_ZBB_OR_ZBKB,
541 INSN_CLASS_ZBC_OR_ZBKC,
542 INSN_CLASS_ZKND_OR_ZKNE,
543 INSN_CLASS_V,
544 INSN_CLASS_ZVEF,
545 INSN_CLASS_ZVBB,
546 INSN_CLASS_ZVBC,
547 INSN_CLASS_ZVFBFMIN,
548 INSN_CLASS_ZVFBFWMA,
549 INSN_CLASS_ZVKB,
550 INSN_CLASS_ZVKG,
551 INSN_CLASS_ZVKNED,
552 INSN_CLASS_ZVKNHA_OR_ZVKNHB,
553 INSN_CLASS_ZVKSED,
554 INSN_CLASS_ZVKSH,
555 INSN_CLASS_ZICFISS,
556 INSN_CLASS_ZICFISS_AND_ZCMOP,
557 INSN_CLASS_ZICFILP,
558 INSN_CLASS_ZCB,
559 INSN_CLASS_ZCB_AND_ZBA,
560 INSN_CLASS_ZCB_AND_ZBB,
561 INSN_CLASS_ZCB_AND_ZMMUL,
562 INSN_CLASS_ZCMOP,
563 INSN_CLASS_ZCMP,
564 INSN_CLASS_ZCMT,
565 INSN_CLASS_SMCTR_OR_SSCTR,
566 INSN_CLASS_ZILSD,
567 INSN_CLASS_ZCLSD,
568 INSN_CLASS_SMRNMI,
569 INSN_CLASS_SVINVAL,
570 INSN_CLASS_ZICBOM,
571 INSN_CLASS_ZICBOP,
572 INSN_CLASS_ZICBOZ,
573 INSN_CLASS_ZABHA,
574 INSN_CLASS_ZACAS,
575 INSN_CLASS_ZABHA_AND_ZACAS,
576 INSN_CLASS_H,
577 INSN_CLASS_XCVALU,
578 INSN_CLASS_XCVBI,
579 INSN_CLASS_XCVBITMANIP,
580 INSN_CLASS_XCVELW,
581 INSN_CLASS_XCVMAC,
582 INSN_CLASS_XCVMEM,
583 INSN_CLASS_XCVSIMD,
584 INSN_CLASS_XTHEADBA,
585 INSN_CLASS_XTHEADBB,
586 INSN_CLASS_XTHEADBS,
587 INSN_CLASS_XTHEADCMO,
588 INSN_CLASS_XTHEADCONDMOV,
589 INSN_CLASS_XTHEADFMEMIDX,
590 INSN_CLASS_XTHEADFMV,
591 INSN_CLASS_XTHEADINT,
592 INSN_CLASS_XTHEADMAC,
593 INSN_CLASS_XTHEADMEMIDX,
594 INSN_CLASS_XTHEADMEMPAIR,
595 INSN_CLASS_XTHEADSYNC,
596 INSN_CLASS_XTHEADVECTOR,
597 INSN_CLASS_XTHEADVDOT,
598 INSN_CLASS_XTHEADZVAMO,
599 INSN_CLASS_XVENTANACONDOPS,
600 INSN_CLASS_XSFVCP,
601 INSN_CLASS_XSFCEASE,
602 INSN_CLASS_XSFVQMACCQOQ,
603 INSN_CLASS_XSFVQMACCDOD,
604 INSN_CLASS_XSFVFNRCLIPXFQF,
605 INSN_CLASS_XMIPSCBOP,
606 INSN_CLASS_XMIPSCMOV,
607 INSN_CLASS_XMIPSEXECTL,
608 INSN_CLASS_XMIPSLSP,
609};
610
611/* This structure holds information for a particular instruction. */
612struct riscv_opcode
613{
614 /* The name of the instruction. */
615 const char *name;
616
617 /* The requirement of xlen for the instruction, 0 if no requirement. */
618 unsigned xlen_requirement;
619
620 /* Class to which this instruction belongs. Used to decide whether or
621 not this instruction is legal in the current -march context. */
622 enum riscv_insn_class insn_class;
623
624 /* A string describing the arguments for this instruction. */
625 const char *args;
626
627 /* The basic opcode for the instruction. When assembling, this
628 opcode is modified by the arguments to produce the actual opcode
629 that is used. If pinfo is INSN_MACRO, then this is 0. */
630 insn_t match;
631
632 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
633 relevant portions of the opcode when disassembling. If the
634 actual opcode anded with the match field equals the opcode field,
635 then we have found the correct instruction. If pinfo is
636 INSN_MACRO, then this field is the macro identifier. */
637 insn_t mask;
638
639 /* A function to determine if a word corresponds to this instruction.
640 Usually, this computes ((word & mask) == match). */
641 int (*match_func) (const struct riscv_opcode *op, insn_t word);
642
643 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
644 of bits describing the instruction, notably any relevant hazard
645 information. */
646 unsigned long pinfo;
647};
648
649/* Instruction is a simple alias (e.g. "mv" for "addi"). */
650#define INSN_ALIAS 0x00000001
651
652/* These are for setting insn_info fields.
653
654 Nonbranch is the default. Noninsn is used only if there is no match.
655 There are no condjsr or dref2 instructions. So that leaves condbranch,
656 branch, jsr, and dref that we need to handle here, encoded in 3 bits. */
657#define INSN_TYPE 0x0000000e
658
659/* Instruction is an unconditional branch. */
660#define INSN_BRANCH 0x00000002
661/* Instruction is a conditional branch. */
662#define INSN_CONDBRANCH 0x00000004
663/* Instruction is a jump to subroutine. */
664#define INSN_JSR 0x00000006
665/* Instruction is a data reference. */
666#define INSN_DREF 0x00000008
667/* Instruction is allowed when eew >= 64. */
668#define INSN_V_EEW64 0x10000000
669
670/* We have 5 data reference sizes, which we can encode in 3 bits. */
671#define INSN_DATA_SIZE 0x00000070
672#define INSN_DATA_SIZE_SHIFT 4
673#define INSN_1_BYTE 0x00000010
674#define INSN_2_BYTE 0x00000020
675#define INSN_4_BYTE 0x00000030
676#define INSN_8_BYTE 0x00000040
677#define INSN_16_BYTE 0x00000050
678
679/* Instruction is actually a macro. It should be ignored by the
680 disassembler, and requires special treatment by the assembler. */
681#define INSN_MACRO 0xffffffff
682
683/* This is a list of macro expanded instructions. */
684enum
685{
686 M_LA,
687 M_LLA,
688 M_LGA,
689 M_LA_TLS_GD,
690 M_LA_TLS_IE,
691 M_Lx,
692 M_FLx,
693 M_Sx_FSx,
694 M_CALL,
695 M_LI,
696 M_EXTH,
697 M_ZEXTW,
698 M_SEXTB,
699 M_VMSGE,
700 M_NUM_MACROS
701};
702
703/* The mapping symbol states. */
704enum riscv_seg_mstate
705{
706 MAP_NONE = 0, /* Must be zero, for seginfo in new sections. */
707 MAP_DATA, /* Data. */
708 MAP_INSN, /* Instructions. */
709};
710
711#define NRC (4 + 1) /* Max characters in register names, incl nul. */
712
713extern const char riscv_gpr_names_numeric[NGPR][NRC];
714extern const char riscv_gpr_names_abi[NGPR][NRC];
715extern const char riscv_fpr_names_numeric[NFPR][NRC];
716extern const char riscv_fpr_names_abi[NFPR][NRC];
717extern const char * const riscv_rm[8];
718extern const char * const riscv_pred_succ[16];
719extern const char riscv_vecr_names_numeric[NVECR][NRC];
720extern const char riscv_vecm_names_numeric[NVECM][NRC];
721extern const char * const riscv_vsew[8];
722extern const char * const riscv_vlmul[8];
723extern const char * const riscv_vta[2];
724extern const char * const riscv_vma[2];
725extern const char * const riscv_th_vlen[4];
726extern const char * const riscv_th_vediv[4];
727extern const char * const riscv_fli_symval[32];
728extern const float riscv_fli_numval[32];
729
730extern const struct riscv_opcode riscv_opcodes[];
731extern const struct riscv_opcode riscv_insn_types[];
732
733extern unsigned int riscv_get_sp_base (insn_t, unsigned int);
734
735#endif /* _RISCV_H_ */
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