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1/* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5
6 This file is part of the GNU opcodes library.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23
24/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
25 July 1988
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
29
30/* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
36
37#include "sysdep.h"
38#include "dis-asm.h"
39#include "opintl.h"
40#include "opcode/i386.h"
41#include "libiberty.h"
42
43#include <setjmp.h>
44
45static int print_insn (bfd_vma, disassemble_info *);
46static void dofloat (int);
47static void OP_ST (int, int);
48static void OP_STi (int, int);
49static int putop (const char *, int);
50static void oappend (const char *);
51static void append_seg (void);
52static void OP_indirE (int, int);
53static void print_operand_value (char *, int, bfd_vma);
54static void OP_E_register (int, int);
55static void OP_E_memory (int, int);
56static void print_displacement (char *, bfd_vma);
57static void OP_E (int, int);
58static void OP_G (int, int);
59static bfd_vma get64 (void);
60static bfd_signed_vma get32 (void);
61static bfd_signed_vma get32s (void);
62static int get16 (void);
63static void set_op (bfd_vma, int);
64static void OP_Skip_MODRM (int, int);
65static void OP_REG (int, int);
66static void OP_IMREG (int, int);
67static void OP_I (int, int);
68static void OP_I64 (int, int);
69static void OP_sI (int, int);
70static void OP_J (int, int);
71static void OP_SEG (int, int);
72static void OP_DIR (int, int);
73static void OP_OFF (int, int);
74static void OP_OFF64 (int, int);
75static void ptr_reg (int, int);
76static void OP_ESreg (int, int);
77static void OP_DSreg (int, int);
78static void OP_C (int, int);
79static void OP_D (int, int);
80static void OP_T (int, int);
81static void OP_R (int, int);
82static void OP_MMX (int, int);
83static void OP_XMM (int, int);
84static void OP_EM (int, int);
85static void OP_EX (int, int);
86static void OP_EMC (int,int);
87static void OP_MXC (int,int);
88static void OP_MS (int, int);
89static void OP_XS (int, int);
90static void OP_M (int, int);
91static void OP_VEX (int, int);
92static void OP_EX_Vex (int, int);
93static void OP_EX_VexW (int, int);
94static void OP_EX_VexImmW (int, int);
95static void OP_XMM_Vex (int, int);
96static void OP_XMM_VexW (int, int);
97static void OP_REG_VexI4 (int, int);
98static void PCLMUL_Fixup (int, int);
99static void VEXI4_Fixup (int, int);
100static void VZERO_Fixup (int, int);
101static void VCMP_Fixup (int, int);
102static void OP_0f07 (int, int);
103static void OP_Monitor (int, int);
104static void OP_Mwait (int, int);
105static void NOP_Fixup1 (int, int);
106static void NOP_Fixup2 (int, int);
107static void OP_3DNowSuffix (int, int);
108static void CMP_Fixup (int, int);
109static void BadOp (void);
110static void REP_Fixup (int, int);
111static void CMPXCHG8B_Fixup (int, int);
112static void XMM_Fixup (int, int);
113static void CRC32_Fixup (int, int);
114static void FXSAVE_Fixup (int, int);
115static void OP_LWPCB_E (int, int);
116static void OP_LWP_E (int, int);
117static void OP_Vex_2src_1 (int, int);
118static void OP_Vex_2src_2 (int, int);
119
120static void MOVBE_Fixup (int, int);
121
122struct dis_private {
123 /* Points to first byte not fetched. */
124 bfd_byte *max_fetched;
125 bfd_byte the_buffer[MAX_MNEM_SIZE];
126 bfd_vma insn_start;
127 int orig_sizeflag;
128 jmp_buf bailout;
129};
130
131enum address_mode
132{
133 mode_16bit,
134 mode_32bit,
135 mode_64bit
136};
137
138enum address_mode address_mode;
139
140/* Flags for the prefixes for the current instruction. See below. */
141static int prefixes;
142
143/* REX prefix the current instruction. See below. */
144static int rex;
145/* Bits of REX we've already used. */
146static int rex_used;
147/* REX bits in original REX prefix ignored. */
148static int rex_ignored;
149/* Mark parts used in the REX prefix. When we are testing for
150 empty prefix (for 8bit register REX extension), just mask it
151 out. Otherwise test for REX bit is excuse for existence of REX
152 only in case value is nonzero. */
153#define USED_REX(value) \
154 { \
155 if (value) \
156 { \
157 if ((rex & value)) \
158 rex_used |= (value) | REX_OPCODE; \
159 } \
160 else \
161 rex_used |= REX_OPCODE; \
162 }
163
164/* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166static int used_prefixes;
167
168/* Flags stored in PREFIXES. */
169#define PREFIX_REPZ 1
170#define PREFIX_REPNZ 2
171#define PREFIX_LOCK 4
172#define PREFIX_CS 8
173#define PREFIX_SS 0x10
174#define PREFIX_DS 0x20
175#define PREFIX_ES 0x40
176#define PREFIX_FS 0x80
177#define PREFIX_GS 0x100
178#define PREFIX_DATA 0x200
179#define PREFIX_ADDR 0x400
180#define PREFIX_FWAIT 0x800
181
182/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
184 on error. */
185#define FETCH_DATA(info, addr) \
186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
187 ? 1 : fetch_data ((info), (addr)))
188
189static int
190fetch_data (struct disassemble_info *info, bfd_byte *addr)
191{
192 int status;
193 struct dis_private *priv = (struct dis_private *) info->private_data;
194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
195
196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
197 status = (*info->read_memory_func) (start,
198 priv->max_fetched,
199 addr - priv->max_fetched,
200 info);
201 else
202 status = -1;
203 if (status != 0)
204 {
205 /* If we did manage to read at least one byte, then
206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
208 STATUS. */
209 if (priv->max_fetched == priv->the_buffer)
210 (*info->memory_error_func) (status, start, info);
211 longjmp (priv->bailout, 1);
212 }
213 else
214 priv->max_fetched = addr;
215 return 1;
216}
217
218#define XX { NULL, 0 }
219#define Bad_Opcode NULL, { { NULL, 0 } }
220
221#define Eb { OP_E, b_mode }
222#define EbS { OP_E, b_swap_mode }
223#define Ev { OP_E, v_mode }
224#define EvS { OP_E, v_swap_mode }
225#define Ed { OP_E, d_mode }
226#define Edq { OP_E, dq_mode }
227#define Edqw { OP_E, dqw_mode }
228#define Edqb { OP_E, dqb_mode }
229#define Edqd { OP_E, dqd_mode }
230#define Eq { OP_E, q_mode }
231#define indirEv { OP_indirE, stack_v_mode }
232#define indirEp { OP_indirE, f_mode }
233#define stackEv { OP_E, stack_v_mode }
234#define Em { OP_E, m_mode }
235#define Ew { OP_E, w_mode }
236#define M { OP_M, 0 } /* lea, lgdt, etc. */
237#define Ma { OP_M, a_mode }
238#define Mb { OP_M, b_mode }
239#define Md { OP_M, d_mode }
240#define Mo { OP_M, o_mode }
241#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
242#define Mq { OP_M, q_mode }
243#define Mx { OP_M, x_mode }
244#define Mxmm { OP_M, xmm_mode }
245#define Gb { OP_G, b_mode }
246#define Gv { OP_G, v_mode }
247#define Gd { OP_G, d_mode }
248#define Gdq { OP_G, dq_mode }
249#define Gm { OP_G, m_mode }
250#define Gw { OP_G, w_mode }
251#define Rd { OP_R, d_mode }
252#define Rm { OP_R, m_mode }
253#define Ib { OP_I, b_mode }
254#define sIb { OP_sI, b_mode } /* sign extened byte */
255#define Iv { OP_I, v_mode }
256#define Iq { OP_I, q_mode }
257#define Iv64 { OP_I64, v_mode }
258#define Iw { OP_I, w_mode }
259#define I1 { OP_I, const_1_mode }
260#define Jb { OP_J, b_mode }
261#define Jv { OP_J, v_mode }
262#define Cm { OP_C, m_mode }
263#define Dm { OP_D, m_mode }
264#define Td { OP_T, d_mode }
265#define Skip_MODRM { OP_Skip_MODRM, 0 }
266
267#define RMeAX { OP_REG, eAX_reg }
268#define RMeBX { OP_REG, eBX_reg }
269#define RMeCX { OP_REG, eCX_reg }
270#define RMeDX { OP_REG, eDX_reg }
271#define RMeSP { OP_REG, eSP_reg }
272#define RMeBP { OP_REG, eBP_reg }
273#define RMeSI { OP_REG, eSI_reg }
274#define RMeDI { OP_REG, eDI_reg }
275#define RMrAX { OP_REG, rAX_reg }
276#define RMrBX { OP_REG, rBX_reg }
277#define RMrCX { OP_REG, rCX_reg }
278#define RMrDX { OP_REG, rDX_reg }
279#define RMrSP { OP_REG, rSP_reg }
280#define RMrBP { OP_REG, rBP_reg }
281#define RMrSI { OP_REG, rSI_reg }
282#define RMrDI { OP_REG, rDI_reg }
283#define RMAL { OP_REG, al_reg }
284#define RMAL { OP_REG, al_reg }
285#define RMCL { OP_REG, cl_reg }
286#define RMDL { OP_REG, dl_reg }
287#define RMBL { OP_REG, bl_reg }
288#define RMAH { OP_REG, ah_reg }
289#define RMCH { OP_REG, ch_reg }
290#define RMDH { OP_REG, dh_reg }
291#define RMBH { OP_REG, bh_reg }
292#define RMAX { OP_REG, ax_reg }
293#define RMDX { OP_REG, dx_reg }
294
295#define eAX { OP_IMREG, eAX_reg }
296#define eBX { OP_IMREG, eBX_reg }
297#define eCX { OP_IMREG, eCX_reg }
298#define eDX { OP_IMREG, eDX_reg }
299#define eSP { OP_IMREG, eSP_reg }
300#define eBP { OP_IMREG, eBP_reg }
301#define eSI { OP_IMREG, eSI_reg }
302#define eDI { OP_IMREG, eDI_reg }
303#define AL { OP_IMREG, al_reg }
304#define CL { OP_IMREG, cl_reg }
305#define DL { OP_IMREG, dl_reg }
306#define BL { OP_IMREG, bl_reg }
307#define AH { OP_IMREG, ah_reg }
308#define CH { OP_IMREG, ch_reg }
309#define DH { OP_IMREG, dh_reg }
310#define BH { OP_IMREG, bh_reg }
311#define AX { OP_IMREG, ax_reg }
312#define DX { OP_IMREG, dx_reg }
313#define zAX { OP_IMREG, z_mode_ax_reg }
314#define indirDX { OP_IMREG, indir_dx_reg }
315
316#define Sw { OP_SEG, w_mode }
317#define Sv { OP_SEG, v_mode }
318#define Ap { OP_DIR, 0 }
319#define Ob { OP_OFF64, b_mode }
320#define Ov { OP_OFF64, v_mode }
321#define Xb { OP_DSreg, eSI_reg }
322#define Xv { OP_DSreg, eSI_reg }
323#define Xz { OP_DSreg, eSI_reg }
324#define Yb { OP_ESreg, eDI_reg }
325#define Yv { OP_ESreg, eDI_reg }
326#define DSBX { OP_DSreg, eBX_reg }
327
328#define es { OP_REG, es_reg }
329#define ss { OP_REG, ss_reg }
330#define cs { OP_REG, cs_reg }
331#define ds { OP_REG, ds_reg }
332#define fs { OP_REG, fs_reg }
333#define gs { OP_REG, gs_reg }
334
335#define MX { OP_MMX, 0 }
336#define XM { OP_XMM, 0 }
337#define XMScalar { OP_XMM, scalar_mode }
338#define XMM { OP_XMM, xmm_mode }
339#define EM { OP_EM, v_mode }
340#define EMS { OP_EM, v_swap_mode }
341#define EMd { OP_EM, d_mode }
342#define EMx { OP_EM, x_mode }
343#define EXw { OP_EX, w_mode }
344#define EXd { OP_EX, d_mode }
345#define EXdScalar { OP_EX, d_scalar_mode }
346#define EXdS { OP_EX, d_swap_mode }
347#define EXq { OP_EX, q_mode }
348#define EXqScalar { OP_EX, q_scalar_mode }
349#define EXqScalarS { OP_EX, q_scalar_swap_mode }
350#define EXqS { OP_EX, q_swap_mode }
351#define EXx { OP_EX, x_mode }
352#define EXxS { OP_EX, x_swap_mode }
353#define EXxmm { OP_EX, xmm_mode }
354#define EXxmmq { OP_EX, xmmq_mode }
355#define EXymmq { OP_EX, ymmq_mode }
356#define EXVexWdq { OP_EX, vex_w_dq_mode }
357#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
358#define MS { OP_MS, v_mode }
359#define XS { OP_XS, v_mode }
360#define EMCq { OP_EMC, q_mode }
361#define MXC { OP_MXC, 0 }
362#define OPSUF { OP_3DNowSuffix, 0 }
363#define CMP { CMP_Fixup, 0 }
364#define XMM0 { XMM_Fixup, 0 }
365#define FXSAVE { FXSAVE_Fixup, 0 }
366#define Vex_2src_1 { OP_Vex_2src_1, 0 }
367#define Vex_2src_2 { OP_Vex_2src_2, 0 }
368
369#define Vex { OP_VEX, vex_mode }
370#define VexScalar { OP_VEX, vex_scalar_mode }
371#define Vex128 { OP_VEX, vex128_mode }
372#define Vex256 { OP_VEX, vex256_mode }
373#define VexI4 { VEXI4_Fixup, 0}
374#define EXdVex { OP_EX_Vex, d_mode }
375#define EXdVexS { OP_EX_Vex, d_swap_mode }
376#define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
377#define EXqVex { OP_EX_Vex, q_mode }
378#define EXqVexS { OP_EX_Vex, q_swap_mode }
379#define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
380#define EXVexW { OP_EX_VexW, x_mode }
381#define EXdVexW { OP_EX_VexW, d_mode }
382#define EXqVexW { OP_EX_VexW, q_mode }
383#define EXVexImmW { OP_EX_VexImmW, x_mode }
384#define XMVex { OP_XMM_Vex, 0 }
385#define XMVexScalar { OP_XMM_Vex, scalar_mode }
386#define XMVexW { OP_XMM_VexW, 0 }
387#define XMVexI4 { OP_REG_VexI4, x_mode }
388#define PCLMUL { PCLMUL_Fixup, 0 }
389#define VZERO { VZERO_Fixup, 0 }
390#define VCMP { VCMP_Fixup, 0 }
391
392/* Used handle "rep" prefix for string instructions. */
393#define Xbr { REP_Fixup, eSI_reg }
394#define Xvr { REP_Fixup, eSI_reg }
395#define Ybr { REP_Fixup, eDI_reg }
396#define Yvr { REP_Fixup, eDI_reg }
397#define Yzr { REP_Fixup, eDI_reg }
398#define indirDXr { REP_Fixup, indir_dx_reg }
399#define ALr { REP_Fixup, al_reg }
400#define eAXr { REP_Fixup, eAX_reg }
401
402#define cond_jump_flag { NULL, cond_jump_mode }
403#define loop_jcxz_flag { NULL, loop_jcxz_mode }
404
405/* bits in sizeflag */
406#define SUFFIX_ALWAYS 4
407#define AFLAG 2
408#define DFLAG 1
409
410enum
411{
412 /* byte operand */
413 b_mode = 1,
414 /* byte operand with operand swapped */
415 b_swap_mode,
416 /* operand size depends on prefixes */
417 v_mode,
418 /* operand size depends on prefixes with operand swapped */
419 v_swap_mode,
420 /* word operand */
421 w_mode,
422 /* double word operand */
423 d_mode,
424 /* double word operand with operand swapped */
425 d_swap_mode,
426 /* quad word operand */
427 q_mode,
428 /* quad word operand with operand swapped */
429 q_swap_mode,
430 /* ten-byte operand */
431 t_mode,
432 /* 16-byte XMM or 32-byte YMM operand */
433 x_mode,
434 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
435 x_swap_mode,
436 /* 16-byte XMM operand */
437 xmm_mode,
438 /* 16-byte XMM or quad word operand */
439 xmmq_mode,
440 /* 32-byte YMM or quad word operand */
441 ymmq_mode,
442 /* d_mode in 32bit, q_mode in 64bit mode. */
443 m_mode,
444 /* pair of v_mode operands */
445 a_mode,
446 cond_jump_mode,
447 loop_jcxz_mode,
448 /* operand size depends on REX prefixes. */
449 dq_mode,
450 /* registers like dq_mode, memory like w_mode. */
451 dqw_mode,
452 /* 4- or 6-byte pointer operand */
453 f_mode,
454 const_1_mode,
455 /* v_mode for stack-related opcodes. */
456 stack_v_mode,
457 /* non-quad operand size depends on prefixes */
458 z_mode,
459 /* 16-byte operand */
460 o_mode,
461 /* registers like dq_mode, memory like b_mode. */
462 dqb_mode,
463 /* registers like dq_mode, memory like d_mode. */
464 dqd_mode,
465 /* normal vex mode */
466 vex_mode,
467 /* 128bit vex mode */
468 vex128_mode,
469 /* 256bit vex mode */
470 vex256_mode,
471 /* operand size depends on the VEX.W bit. */
472 vex_w_dq_mode,
473
474 /* scalar, ignore vector length. */
475 scalar_mode,
476 /* like d_mode, ignore vector length. */
477 d_scalar_mode,
478 /* like d_swap_mode, ignore vector length. */
479 d_scalar_swap_mode,
480 /* like q_mode, ignore vector length. */
481 q_scalar_mode,
482 /* like q_swap_mode, ignore vector length. */
483 q_scalar_swap_mode,
484 /* like vex_mode, ignore vector length. */
485 vex_scalar_mode,
486 /* like vex_w_dq_mode, ignore vector length. */
487 vex_scalar_w_dq_mode,
488
489 es_reg,
490 cs_reg,
491 ss_reg,
492 ds_reg,
493 fs_reg,
494 gs_reg,
495
496 eAX_reg,
497 eCX_reg,
498 eDX_reg,
499 eBX_reg,
500 eSP_reg,
501 eBP_reg,
502 eSI_reg,
503 eDI_reg,
504
505 al_reg,
506 cl_reg,
507 dl_reg,
508 bl_reg,
509 ah_reg,
510 ch_reg,
511 dh_reg,
512 bh_reg,
513
514 ax_reg,
515 cx_reg,
516 dx_reg,
517 bx_reg,
518 sp_reg,
519 bp_reg,
520 si_reg,
521 di_reg,
522
523 rAX_reg,
524 rCX_reg,
525 rDX_reg,
526 rBX_reg,
527 rSP_reg,
528 rBP_reg,
529 rSI_reg,
530 rDI_reg,
531
532 z_mode_ax_reg,
533 indir_dx_reg
534};
535
536enum
537{
538 FLOATCODE = 1,
539 USE_REG_TABLE,
540 USE_MOD_TABLE,
541 USE_RM_TABLE,
542 USE_PREFIX_TABLE,
543 USE_X86_64_TABLE,
544 USE_3BYTE_TABLE,
545 USE_XOP_8F_TABLE,
546 USE_VEX_C4_TABLE,
547 USE_VEX_C5_TABLE,
548 USE_VEX_LEN_TABLE,
549 USE_VEX_W_TABLE
550};
551
552#define FLOAT NULL, { { NULL, FLOATCODE } }
553
554#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
555#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
556#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
557#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
558#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
559#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
560#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
561#define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
562#define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
563#define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
564#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
565#define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
566
567enum
568{
569 REG_80 = 0,
570 REG_81,
571 REG_82,
572 REG_8F,
573 REG_C0,
574 REG_C1,
575 REG_C6,
576 REG_C7,
577 REG_D0,
578 REG_D1,
579 REG_D2,
580 REG_D3,
581 REG_F6,
582 REG_F7,
583 REG_FE,
584 REG_FF,
585 REG_0F00,
586 REG_0F01,
587 REG_0F0D,
588 REG_0F18,
589 REG_0F71,
590 REG_0F72,
591 REG_0F73,
592 REG_0FA6,
593 REG_0FA7,
594 REG_0FAE,
595 REG_0FBA,
596 REG_0FC7,
597 REG_VEX_71,
598 REG_VEX_72,
599 REG_VEX_73,
600 REG_VEX_AE,
601 REG_XOP_LWPCB,
602 REG_XOP_LWP
603};
604
605enum
606{
607 MOD_8D = 0,
608 MOD_0F01_REG_0,
609 MOD_0F01_REG_1,
610 MOD_0F01_REG_2,
611 MOD_0F01_REG_3,
612 MOD_0F01_REG_7,
613 MOD_0F12_PREFIX_0,
614 MOD_0F13,
615 MOD_0F16_PREFIX_0,
616 MOD_0F17,
617 MOD_0F18_REG_0,
618 MOD_0F18_REG_1,
619 MOD_0F18_REG_2,
620 MOD_0F18_REG_3,
621 MOD_0F20,
622 MOD_0F21,
623 MOD_0F22,
624 MOD_0F23,
625 MOD_0F24,
626 MOD_0F26,
627 MOD_0F2B_PREFIX_0,
628 MOD_0F2B_PREFIX_1,
629 MOD_0F2B_PREFIX_2,
630 MOD_0F2B_PREFIX_3,
631 MOD_0F51,
632 MOD_0F71_REG_2,
633 MOD_0F71_REG_4,
634 MOD_0F71_REG_6,
635 MOD_0F72_REG_2,
636 MOD_0F72_REG_4,
637 MOD_0F72_REG_6,
638 MOD_0F73_REG_2,
639 MOD_0F73_REG_3,
640 MOD_0F73_REG_6,
641 MOD_0F73_REG_7,
642 MOD_0FAE_REG_0,
643 MOD_0FAE_REG_1,
644 MOD_0FAE_REG_2,
645 MOD_0FAE_REG_3,
646 MOD_0FAE_REG_4,
647 MOD_0FAE_REG_5,
648 MOD_0FAE_REG_6,
649 MOD_0FAE_REG_7,
650 MOD_0FB2,
651 MOD_0FB4,
652 MOD_0FB5,
653 MOD_0FC7_REG_6,
654 MOD_0FC7_REG_7,
655 MOD_0FD7,
656 MOD_0FE7_PREFIX_2,
657 MOD_0FF0_PREFIX_3,
658 MOD_0F382A_PREFIX_2,
659 MOD_62_32BIT,
660 MOD_C4_32BIT,
661 MOD_C5_32BIT,
662 MOD_VEX_12_PREFIX_0,
663 MOD_VEX_13,
664 MOD_VEX_16_PREFIX_0,
665 MOD_VEX_17,
666 MOD_VEX_2B,
667 MOD_VEX_50,
668 MOD_VEX_71_REG_2,
669 MOD_VEX_71_REG_4,
670 MOD_VEX_71_REG_6,
671 MOD_VEX_72_REG_2,
672 MOD_VEX_72_REG_4,
673 MOD_VEX_72_REG_6,
674 MOD_VEX_73_REG_2,
675 MOD_VEX_73_REG_3,
676 MOD_VEX_73_REG_6,
677 MOD_VEX_73_REG_7,
678 MOD_VEX_AE_REG_2,
679 MOD_VEX_AE_REG_3,
680 MOD_VEX_D7_PREFIX_2,
681 MOD_VEX_E7_PREFIX_2,
682 MOD_VEX_F0_PREFIX_3,
683 MOD_VEX_3818_PREFIX_2,
684 MOD_VEX_3819_PREFIX_2,
685 MOD_VEX_381A_PREFIX_2,
686 MOD_VEX_382A_PREFIX_2,
687 MOD_VEX_382C_PREFIX_2,
688 MOD_VEX_382D_PREFIX_2,
689 MOD_VEX_382E_PREFIX_2,
690 MOD_VEX_382F_PREFIX_2
691};
692
693enum
694{
695 RM_0F01_REG_0 = 0,
696 RM_0F01_REG_1,
697 RM_0F01_REG_2,
698 RM_0F01_REG_3,
699 RM_0F01_REG_7,
700 RM_0FAE_REG_5,
701 RM_0FAE_REG_6,
702 RM_0FAE_REG_7
703};
704
705enum
706{
707 PREFIX_90 = 0,
708 PREFIX_0F10,
709 PREFIX_0F11,
710 PREFIX_0F12,
711 PREFIX_0F16,
712 PREFIX_0F2A,
713 PREFIX_0F2B,
714 PREFIX_0F2C,
715 PREFIX_0F2D,
716 PREFIX_0F2E,
717 PREFIX_0F2F,
718 PREFIX_0F51,
719 PREFIX_0F52,
720 PREFIX_0F53,
721 PREFIX_0F58,
722 PREFIX_0F59,
723 PREFIX_0F5A,
724 PREFIX_0F5B,
725 PREFIX_0F5C,
726 PREFIX_0F5D,
727 PREFIX_0F5E,
728 PREFIX_0F5F,
729 PREFIX_0F60,
730 PREFIX_0F61,
731 PREFIX_0F62,
732 PREFIX_0F6C,
733 PREFIX_0F6D,
734 PREFIX_0F6F,
735 PREFIX_0F70,
736 PREFIX_0F73_REG_3,
737 PREFIX_0F73_REG_7,
738 PREFIX_0F78,
739 PREFIX_0F79,
740 PREFIX_0F7C,
741 PREFIX_0F7D,
742 PREFIX_0F7E,
743 PREFIX_0F7F,
744 PREFIX_0FAE_REG_0,
745 PREFIX_0FAE_REG_1,
746 PREFIX_0FAE_REG_2,
747 PREFIX_0FAE_REG_3,
748 PREFIX_0FB8,
749 PREFIX_0FBD,
750 PREFIX_0FC2,
751 PREFIX_0FC3,
752 PREFIX_0FC7_REG_6,
753 PREFIX_0FD0,
754 PREFIX_0FD6,
755 PREFIX_0FE6,
756 PREFIX_0FE7,
757 PREFIX_0FF0,
758 PREFIX_0FF7,
759 PREFIX_0F3810,
760 PREFIX_0F3814,
761 PREFIX_0F3815,
762 PREFIX_0F3817,
763 PREFIX_0F3820,
764 PREFIX_0F3821,
765 PREFIX_0F3822,
766 PREFIX_0F3823,
767 PREFIX_0F3824,
768 PREFIX_0F3825,
769 PREFIX_0F3828,
770 PREFIX_0F3829,
771 PREFIX_0F382A,
772 PREFIX_0F382B,
773 PREFIX_0F3830,
774 PREFIX_0F3831,
775 PREFIX_0F3832,
776 PREFIX_0F3833,
777 PREFIX_0F3834,
778 PREFIX_0F3835,
779 PREFIX_0F3837,
780 PREFIX_0F3838,
781 PREFIX_0F3839,
782 PREFIX_0F383A,
783 PREFIX_0F383B,
784 PREFIX_0F383C,
785 PREFIX_0F383D,
786 PREFIX_0F383E,
787 PREFIX_0F383F,
788 PREFIX_0F3840,
789 PREFIX_0F3841,
790 PREFIX_0F3880,
791 PREFIX_0F3881,
792 PREFIX_0F38DB,
793 PREFIX_0F38DC,
794 PREFIX_0F38DD,
795 PREFIX_0F38DE,
796 PREFIX_0F38DF,
797 PREFIX_0F38F0,
798 PREFIX_0F38F1,
799 PREFIX_0F3A08,
800 PREFIX_0F3A09,
801 PREFIX_0F3A0A,
802 PREFIX_0F3A0B,
803 PREFIX_0F3A0C,
804 PREFIX_0F3A0D,
805 PREFIX_0F3A0E,
806 PREFIX_0F3A14,
807 PREFIX_0F3A15,
808 PREFIX_0F3A16,
809 PREFIX_0F3A17,
810 PREFIX_0F3A20,
811 PREFIX_0F3A21,
812 PREFIX_0F3A22,
813 PREFIX_0F3A40,
814 PREFIX_0F3A41,
815 PREFIX_0F3A42,
816 PREFIX_0F3A44,
817 PREFIX_0F3A60,
818 PREFIX_0F3A61,
819 PREFIX_0F3A62,
820 PREFIX_0F3A63,
821 PREFIX_0F3ADF,
822 PREFIX_VEX_10,
823 PREFIX_VEX_11,
824 PREFIX_VEX_12,
825 PREFIX_VEX_16,
826 PREFIX_VEX_2A,
827 PREFIX_VEX_2C,
828 PREFIX_VEX_2D,
829 PREFIX_VEX_2E,
830 PREFIX_VEX_2F,
831 PREFIX_VEX_51,
832 PREFIX_VEX_52,
833 PREFIX_VEX_53,
834 PREFIX_VEX_58,
835 PREFIX_VEX_59,
836 PREFIX_VEX_5A,
837 PREFIX_VEX_5B,
838 PREFIX_VEX_5C,
839 PREFIX_VEX_5D,
840 PREFIX_VEX_5E,
841 PREFIX_VEX_5F,
842 PREFIX_VEX_60,
843 PREFIX_VEX_61,
844 PREFIX_VEX_62,
845 PREFIX_VEX_63,
846 PREFIX_VEX_64,
847 PREFIX_VEX_65,
848 PREFIX_VEX_66,
849 PREFIX_VEX_67,
850 PREFIX_VEX_68,
851 PREFIX_VEX_69,
852 PREFIX_VEX_6A,
853 PREFIX_VEX_6B,
854 PREFIX_VEX_6C,
855 PREFIX_VEX_6D,
856 PREFIX_VEX_6E,
857 PREFIX_VEX_6F,
858 PREFIX_VEX_70,
859 PREFIX_VEX_71_REG_2,
860 PREFIX_VEX_71_REG_4,
861 PREFIX_VEX_71_REG_6,
862 PREFIX_VEX_72_REG_2,
863 PREFIX_VEX_72_REG_4,
864 PREFIX_VEX_72_REG_6,
865 PREFIX_VEX_73_REG_2,
866 PREFIX_VEX_73_REG_3,
867 PREFIX_VEX_73_REG_6,
868 PREFIX_VEX_73_REG_7,
869 PREFIX_VEX_74,
870 PREFIX_VEX_75,
871 PREFIX_VEX_76,
872 PREFIX_VEX_77,
873 PREFIX_VEX_7C,
874 PREFIX_VEX_7D,
875 PREFIX_VEX_7E,
876 PREFIX_VEX_7F,
877 PREFIX_VEX_C2,
878 PREFIX_VEX_C4,
879 PREFIX_VEX_C5,
880 PREFIX_VEX_D0,
881 PREFIX_VEX_D1,
882 PREFIX_VEX_D2,
883 PREFIX_VEX_D3,
884 PREFIX_VEX_D4,
885 PREFIX_VEX_D5,
886 PREFIX_VEX_D6,
887 PREFIX_VEX_D7,
888 PREFIX_VEX_D8,
889 PREFIX_VEX_D9,
890 PREFIX_VEX_DA,
891 PREFIX_VEX_DB,
892 PREFIX_VEX_DC,
893 PREFIX_VEX_DD,
894 PREFIX_VEX_DE,
895 PREFIX_VEX_DF,
896 PREFIX_VEX_E0,
897 PREFIX_VEX_E1,
898 PREFIX_VEX_E2,
899 PREFIX_VEX_E3,
900 PREFIX_VEX_E4,
901 PREFIX_VEX_E5,
902 PREFIX_VEX_E6,
903 PREFIX_VEX_E7,
904 PREFIX_VEX_E8,
905 PREFIX_VEX_E9,
906 PREFIX_VEX_EA,
907 PREFIX_VEX_EB,
908 PREFIX_VEX_EC,
909 PREFIX_VEX_ED,
910 PREFIX_VEX_EE,
911 PREFIX_VEX_EF,
912 PREFIX_VEX_F0,
913 PREFIX_VEX_F1,
914 PREFIX_VEX_F2,
915 PREFIX_VEX_F3,
916 PREFIX_VEX_F4,
917 PREFIX_VEX_F5,
918 PREFIX_VEX_F6,
919 PREFIX_VEX_F7,
920 PREFIX_VEX_F8,
921 PREFIX_VEX_F9,
922 PREFIX_VEX_FA,
923 PREFIX_VEX_FB,
924 PREFIX_VEX_FC,
925 PREFIX_VEX_FD,
926 PREFIX_VEX_FE,
927 PREFIX_VEX_3800,
928 PREFIX_VEX_3801,
929 PREFIX_VEX_3802,
930 PREFIX_VEX_3803,
931 PREFIX_VEX_3804,
932 PREFIX_VEX_3805,
933 PREFIX_VEX_3806,
934 PREFIX_VEX_3807,
935 PREFIX_VEX_3808,
936 PREFIX_VEX_3809,
937 PREFIX_VEX_380A,
938 PREFIX_VEX_380B,
939 PREFIX_VEX_380C,
940 PREFIX_VEX_380D,
941 PREFIX_VEX_380E,
942 PREFIX_VEX_380F,
943 PREFIX_VEX_3813,
944 PREFIX_VEX_3817,
945 PREFIX_VEX_3818,
946 PREFIX_VEX_3819,
947 PREFIX_VEX_381A,
948 PREFIX_VEX_381C,
949 PREFIX_VEX_381D,
950 PREFIX_VEX_381E,
951 PREFIX_VEX_3820,
952 PREFIX_VEX_3821,
953 PREFIX_VEX_3822,
954 PREFIX_VEX_3823,
955 PREFIX_VEX_3824,
956 PREFIX_VEX_3825,
957 PREFIX_VEX_3828,
958 PREFIX_VEX_3829,
959 PREFIX_VEX_382A,
960 PREFIX_VEX_382B,
961 PREFIX_VEX_382C,
962 PREFIX_VEX_382D,
963 PREFIX_VEX_382E,
964 PREFIX_VEX_382F,
965 PREFIX_VEX_3830,
966 PREFIX_VEX_3831,
967 PREFIX_VEX_3832,
968 PREFIX_VEX_3833,
969 PREFIX_VEX_3834,
970 PREFIX_VEX_3835,
971 PREFIX_VEX_3837,
972 PREFIX_VEX_3838,
973 PREFIX_VEX_3839,
974 PREFIX_VEX_383A,
975 PREFIX_VEX_383B,
976 PREFIX_VEX_383C,
977 PREFIX_VEX_383D,
978 PREFIX_VEX_383E,
979 PREFIX_VEX_383F,
980 PREFIX_VEX_3840,
981 PREFIX_VEX_3841,
982 PREFIX_VEX_3896,
983 PREFIX_VEX_3897,
984 PREFIX_VEX_3898,
985 PREFIX_VEX_3899,
986 PREFIX_VEX_389A,
987 PREFIX_VEX_389B,
988 PREFIX_VEX_389C,
989 PREFIX_VEX_389D,
990 PREFIX_VEX_389E,
991 PREFIX_VEX_389F,
992 PREFIX_VEX_38A6,
993 PREFIX_VEX_38A7,
994 PREFIX_VEX_38A8,
995 PREFIX_VEX_38A9,
996 PREFIX_VEX_38AA,
997 PREFIX_VEX_38AB,
998 PREFIX_VEX_38AC,
999 PREFIX_VEX_38AD,
1000 PREFIX_VEX_38AE,
1001 PREFIX_VEX_38AF,
1002 PREFIX_VEX_38B6,
1003 PREFIX_VEX_38B7,
1004 PREFIX_VEX_38B8,
1005 PREFIX_VEX_38B9,
1006 PREFIX_VEX_38BA,
1007 PREFIX_VEX_38BB,
1008 PREFIX_VEX_38BC,
1009 PREFIX_VEX_38BD,
1010 PREFIX_VEX_38BE,
1011 PREFIX_VEX_38BF,
1012 PREFIX_VEX_38DB,
1013 PREFIX_VEX_38DC,
1014 PREFIX_VEX_38DD,
1015 PREFIX_VEX_38DE,
1016 PREFIX_VEX_38DF,
1017 PREFIX_VEX_3A04,
1018 PREFIX_VEX_3A05,
1019 PREFIX_VEX_3A06,
1020 PREFIX_VEX_3A08,
1021 PREFIX_VEX_3A09,
1022 PREFIX_VEX_3A0A,
1023 PREFIX_VEX_3A0B,
1024 PREFIX_VEX_3A0C,
1025 PREFIX_VEX_3A0D,
1026 PREFIX_VEX_3A0E,
1027 PREFIX_VEX_3A0F,
1028 PREFIX_VEX_3A14,
1029 PREFIX_VEX_3A15,
1030 PREFIX_VEX_3A16,
1031 PREFIX_VEX_3A17,
1032 PREFIX_VEX_3A18,
1033 PREFIX_VEX_3A19,
1034 PREFIX_VEX_3A1D,
1035 PREFIX_VEX_3A20,
1036 PREFIX_VEX_3A21,
1037 PREFIX_VEX_3A22,
1038 PREFIX_VEX_3A40,
1039 PREFIX_VEX_3A41,
1040 PREFIX_VEX_3A42,
1041 PREFIX_VEX_3A44,
1042 PREFIX_VEX_3A48,
1043 PREFIX_VEX_3A49,
1044 PREFIX_VEX_3A4A,
1045 PREFIX_VEX_3A4B,
1046 PREFIX_VEX_3A4C,
1047 PREFIX_VEX_3A5C,
1048 PREFIX_VEX_3A5D,
1049 PREFIX_VEX_3A5E,
1050 PREFIX_VEX_3A5F,
1051 PREFIX_VEX_3A60,
1052 PREFIX_VEX_3A61,
1053 PREFIX_VEX_3A62,
1054 PREFIX_VEX_3A63,
1055 PREFIX_VEX_3A68,
1056 PREFIX_VEX_3A69,
1057 PREFIX_VEX_3A6A,
1058 PREFIX_VEX_3A6B,
1059 PREFIX_VEX_3A6C,
1060 PREFIX_VEX_3A6D,
1061 PREFIX_VEX_3A6E,
1062 PREFIX_VEX_3A6F,
1063 PREFIX_VEX_3A78,
1064 PREFIX_VEX_3A79,
1065 PREFIX_VEX_3A7A,
1066 PREFIX_VEX_3A7B,
1067 PREFIX_VEX_3A7C,
1068 PREFIX_VEX_3A7D,
1069 PREFIX_VEX_3A7E,
1070 PREFIX_VEX_3A7F,
1071 PREFIX_VEX_3ADF
1072};
1073
1074enum
1075{
1076 X86_64_06 = 0,
1077 X86_64_07,
1078 X86_64_0D,
1079 X86_64_16,
1080 X86_64_17,
1081 X86_64_1E,
1082 X86_64_1F,
1083 X86_64_27,
1084 X86_64_2F,
1085 X86_64_37,
1086 X86_64_3F,
1087 X86_64_60,
1088 X86_64_61,
1089 X86_64_62,
1090 X86_64_63,
1091 X86_64_6D,
1092 X86_64_6F,
1093 X86_64_9A,
1094 X86_64_C4,
1095 X86_64_C5,
1096 X86_64_CE,
1097 X86_64_D4,
1098 X86_64_D5,
1099 X86_64_EA,
1100 X86_64_0F01_REG_0,
1101 X86_64_0F01_REG_1,
1102 X86_64_0F01_REG_2,
1103 X86_64_0F01_REG_3
1104};
1105
1106enum
1107{
1108 THREE_BYTE_0F38 = 0,
1109 THREE_BYTE_0F3A,
1110 THREE_BYTE_0F7A
1111};
1112
1113enum
1114{
1115 XOP_08 = 0,
1116 XOP_09,
1117 XOP_0A
1118};
1119
1120enum
1121{
1122 VEX_0F = 0,
1123 VEX_0F38,
1124 VEX_0F3A
1125};
1126
1127enum
1128{
1129 VEX_LEN_10_P_1 = 0,
1130 VEX_LEN_10_P_3,
1131 VEX_LEN_11_P_1,
1132 VEX_LEN_11_P_3,
1133 VEX_LEN_12_P_0_M_0,
1134 VEX_LEN_12_P_0_M_1,
1135 VEX_LEN_12_P_2,
1136 VEX_LEN_13_M_0,
1137 VEX_LEN_16_P_0_M_0,
1138 VEX_LEN_16_P_0_M_1,
1139 VEX_LEN_16_P_2,
1140 VEX_LEN_17_M_0,
1141 VEX_LEN_2A_P_1,
1142 VEX_LEN_2A_P_3,
1143 VEX_LEN_2C_P_1,
1144 VEX_LEN_2C_P_3,
1145 VEX_LEN_2D_P_1,
1146 VEX_LEN_2D_P_3,
1147 VEX_LEN_2E_P_0,
1148 VEX_LEN_2E_P_2,
1149 VEX_LEN_2F_P_0,
1150 VEX_LEN_2F_P_2,
1151 VEX_LEN_51_P_1,
1152 VEX_LEN_51_P_3,
1153 VEX_LEN_52_P_1,
1154 VEX_LEN_53_P_1,
1155 VEX_LEN_58_P_1,
1156 VEX_LEN_58_P_3,
1157 VEX_LEN_59_P_1,
1158 VEX_LEN_59_P_3,
1159 VEX_LEN_5A_P_1,
1160 VEX_LEN_5A_P_3,
1161 VEX_LEN_5C_P_1,
1162 VEX_LEN_5C_P_3,
1163 VEX_LEN_5D_P_1,
1164 VEX_LEN_5D_P_3,
1165 VEX_LEN_5E_P_1,
1166 VEX_LEN_5E_P_3,
1167 VEX_LEN_5F_P_1,
1168 VEX_LEN_5F_P_3,
1169 VEX_LEN_60_P_2,
1170 VEX_LEN_61_P_2,
1171 VEX_LEN_62_P_2,
1172 VEX_LEN_63_P_2,
1173 VEX_LEN_64_P_2,
1174 VEX_LEN_65_P_2,
1175 VEX_LEN_66_P_2,
1176 VEX_LEN_67_P_2,
1177 VEX_LEN_68_P_2,
1178 VEX_LEN_69_P_2,
1179 VEX_LEN_6A_P_2,
1180 VEX_LEN_6B_P_2,
1181 VEX_LEN_6C_P_2,
1182 VEX_LEN_6D_P_2,
1183 VEX_LEN_6E_P_2,
1184 VEX_LEN_70_P_1,
1185 VEX_LEN_70_P_2,
1186 VEX_LEN_70_P_3,
1187 VEX_LEN_71_R_2_P_2,
1188 VEX_LEN_71_R_4_P_2,
1189 VEX_LEN_71_R_6_P_2,
1190 VEX_LEN_72_R_2_P_2,
1191 VEX_LEN_72_R_4_P_2,
1192 VEX_LEN_72_R_6_P_2,
1193 VEX_LEN_73_R_2_P_2,
1194 VEX_LEN_73_R_3_P_2,
1195 VEX_LEN_73_R_6_P_2,
1196 VEX_LEN_73_R_7_P_2,
1197 VEX_LEN_74_P_2,
1198 VEX_LEN_75_P_2,
1199 VEX_LEN_76_P_2,
1200 VEX_LEN_7E_P_1,
1201 VEX_LEN_7E_P_2,
1202 VEX_LEN_AE_R_2_M_0,
1203 VEX_LEN_AE_R_3_M_0,
1204 VEX_LEN_C2_P_1,
1205 VEX_LEN_C2_P_3,
1206 VEX_LEN_C4_P_2,
1207 VEX_LEN_C5_P_2,
1208 VEX_LEN_D1_P_2,
1209 VEX_LEN_D2_P_2,
1210 VEX_LEN_D3_P_2,
1211 VEX_LEN_D4_P_2,
1212 VEX_LEN_D5_P_2,
1213 VEX_LEN_D6_P_2,
1214 VEX_LEN_D7_P_2_M_1,
1215 VEX_LEN_D8_P_2,
1216 VEX_LEN_D9_P_2,
1217 VEX_LEN_DA_P_2,
1218 VEX_LEN_DB_P_2,
1219 VEX_LEN_DC_P_2,
1220 VEX_LEN_DD_P_2,
1221 VEX_LEN_DE_P_2,
1222 VEX_LEN_DF_P_2,
1223 VEX_LEN_E0_P_2,
1224 VEX_LEN_E1_P_2,
1225 VEX_LEN_E2_P_2,
1226 VEX_LEN_E3_P_2,
1227 VEX_LEN_E4_P_2,
1228 VEX_LEN_E5_P_2,
1229 VEX_LEN_E8_P_2,
1230 VEX_LEN_E9_P_2,
1231 VEX_LEN_EA_P_2,
1232 VEX_LEN_EB_P_2,
1233 VEX_LEN_EC_P_2,
1234 VEX_LEN_ED_P_2,
1235 VEX_LEN_EE_P_2,
1236 VEX_LEN_EF_P_2,
1237 VEX_LEN_F1_P_2,
1238 VEX_LEN_F2_P_2,
1239 VEX_LEN_F3_P_2,
1240 VEX_LEN_F4_P_2,
1241 VEX_LEN_F5_P_2,
1242 VEX_LEN_F6_P_2,
1243 VEX_LEN_F7_P_2,
1244 VEX_LEN_F8_P_2,
1245 VEX_LEN_F9_P_2,
1246 VEX_LEN_FA_P_2,
1247 VEX_LEN_FB_P_2,
1248 VEX_LEN_FC_P_2,
1249 VEX_LEN_FD_P_2,
1250 VEX_LEN_FE_P_2,
1251 VEX_LEN_3800_P_2,
1252 VEX_LEN_3801_P_2,
1253 VEX_LEN_3802_P_2,
1254 VEX_LEN_3803_P_2,
1255 VEX_LEN_3804_P_2,
1256 VEX_LEN_3805_P_2,
1257 VEX_LEN_3806_P_2,
1258 VEX_LEN_3807_P_2,
1259 VEX_LEN_3808_P_2,
1260 VEX_LEN_3809_P_2,
1261 VEX_LEN_380A_P_2,
1262 VEX_LEN_380B_P_2,
1263 VEX_LEN_3819_P_2_M_0,
1264 VEX_LEN_381A_P_2_M_0,
1265 VEX_LEN_381C_P_2,
1266 VEX_LEN_381D_P_2,
1267 VEX_LEN_381E_P_2,
1268 VEX_LEN_3820_P_2,
1269 VEX_LEN_3821_P_2,
1270 VEX_LEN_3822_P_2,
1271 VEX_LEN_3823_P_2,
1272 VEX_LEN_3824_P_2,
1273 VEX_LEN_3825_P_2,
1274 VEX_LEN_3828_P_2,
1275 VEX_LEN_3829_P_2,
1276 VEX_LEN_382A_P_2_M_0,
1277 VEX_LEN_382B_P_2,
1278 VEX_LEN_3830_P_2,
1279 VEX_LEN_3831_P_2,
1280 VEX_LEN_3832_P_2,
1281 VEX_LEN_3833_P_2,
1282 VEX_LEN_3834_P_2,
1283 VEX_LEN_3835_P_2,
1284 VEX_LEN_3837_P_2,
1285 VEX_LEN_3838_P_2,
1286 VEX_LEN_3839_P_2,
1287 VEX_LEN_383A_P_2,
1288 VEX_LEN_383B_P_2,
1289 VEX_LEN_383C_P_2,
1290 VEX_LEN_383D_P_2,
1291 VEX_LEN_383E_P_2,
1292 VEX_LEN_383F_P_2,
1293 VEX_LEN_3840_P_2,
1294 VEX_LEN_3841_P_2,
1295 VEX_LEN_38DB_P_2,
1296 VEX_LEN_38DC_P_2,
1297 VEX_LEN_38DD_P_2,
1298 VEX_LEN_38DE_P_2,
1299 VEX_LEN_38DF_P_2,
1300 VEX_LEN_3A06_P_2,
1301 VEX_LEN_3A0A_P_2,
1302 VEX_LEN_3A0B_P_2,
1303 VEX_LEN_3A0E_P_2,
1304 VEX_LEN_3A0F_P_2,
1305 VEX_LEN_3A14_P_2,
1306 VEX_LEN_3A15_P_2,
1307 VEX_LEN_3A16_P_2,
1308 VEX_LEN_3A17_P_2,
1309 VEX_LEN_3A18_P_2,
1310 VEX_LEN_3A19_P_2,
1311 VEX_LEN_3A20_P_2,
1312 VEX_LEN_3A21_P_2,
1313 VEX_LEN_3A22_P_2,
1314 VEX_LEN_3A41_P_2,
1315 VEX_LEN_3A42_P_2,
1316 VEX_LEN_3A44_P_2,
1317 VEX_LEN_3A4C_P_2,
1318 VEX_LEN_3A60_P_2,
1319 VEX_LEN_3A61_P_2,
1320 VEX_LEN_3A62_P_2,
1321 VEX_LEN_3A63_P_2,
1322 VEX_LEN_3A6A_P_2,
1323 VEX_LEN_3A6B_P_2,
1324 VEX_LEN_3A6E_P_2,
1325 VEX_LEN_3A6F_P_2,
1326 VEX_LEN_3A7A_P_2,
1327 VEX_LEN_3A7B_P_2,
1328 VEX_LEN_3A7E_P_2,
1329 VEX_LEN_3A7F_P_2,
1330 VEX_LEN_3ADF_P_2,
1331 VEX_LEN_XOP_09_80,
1332 VEX_LEN_XOP_09_81
1333};
1334
1335enum
1336{
1337 VEX_W_10_P_0 = 0,
1338 VEX_W_10_P_1,
1339 VEX_W_10_P_2,
1340 VEX_W_10_P_3,
1341 VEX_W_11_P_0,
1342 VEX_W_11_P_1,
1343 VEX_W_11_P_2,
1344 VEX_W_11_P_3,
1345 VEX_W_12_P_0_M_0,
1346 VEX_W_12_P_0_M_1,
1347 VEX_W_12_P_1,
1348 VEX_W_12_P_2,
1349 VEX_W_12_P_3,
1350 VEX_W_13_M_0,
1351 VEX_W_14,
1352 VEX_W_15,
1353 VEX_W_16_P_0_M_0,
1354 VEX_W_16_P_0_M_1,
1355 VEX_W_16_P_1,
1356 VEX_W_16_P_2,
1357 VEX_W_17_M_0,
1358 VEX_W_28,
1359 VEX_W_29,
1360 VEX_W_2B_M_0,
1361 VEX_W_2E_P_0,
1362 VEX_W_2E_P_2,
1363 VEX_W_2F_P_0,
1364 VEX_W_2F_P_2,
1365 VEX_W_50_M_0,
1366 VEX_W_51_P_0,
1367 VEX_W_51_P_1,
1368 VEX_W_51_P_2,
1369 VEX_W_51_P_3,
1370 VEX_W_52_P_0,
1371 VEX_W_52_P_1,
1372 VEX_W_53_P_0,
1373 VEX_W_53_P_1,
1374 VEX_W_58_P_0,
1375 VEX_W_58_P_1,
1376 VEX_W_58_P_2,
1377 VEX_W_58_P_3,
1378 VEX_W_59_P_0,
1379 VEX_W_59_P_1,
1380 VEX_W_59_P_2,
1381 VEX_W_59_P_3,
1382 VEX_W_5A_P_0,
1383 VEX_W_5A_P_1,
1384 VEX_W_5A_P_3,
1385 VEX_W_5B_P_0,
1386 VEX_W_5B_P_1,
1387 VEX_W_5B_P_2,
1388 VEX_W_5C_P_0,
1389 VEX_W_5C_P_1,
1390 VEX_W_5C_P_2,
1391 VEX_W_5C_P_3,
1392 VEX_W_5D_P_0,
1393 VEX_W_5D_P_1,
1394 VEX_W_5D_P_2,
1395 VEX_W_5D_P_3,
1396 VEX_W_5E_P_0,
1397 VEX_W_5E_P_1,
1398 VEX_W_5E_P_2,
1399 VEX_W_5E_P_3,
1400 VEX_W_5F_P_0,
1401 VEX_W_5F_P_1,
1402 VEX_W_5F_P_2,
1403 VEX_W_5F_P_3,
1404 VEX_W_60_P_2,
1405 VEX_W_61_P_2,
1406 VEX_W_62_P_2,
1407 VEX_W_63_P_2,
1408 VEX_W_64_P_2,
1409 VEX_W_65_P_2,
1410 VEX_W_66_P_2,
1411 VEX_W_67_P_2,
1412 VEX_W_68_P_2,
1413 VEX_W_69_P_2,
1414 VEX_W_6A_P_2,
1415 VEX_W_6B_P_2,
1416 VEX_W_6C_P_2,
1417 VEX_W_6D_P_2,
1418 VEX_W_6F_P_1,
1419 VEX_W_6F_P_2,
1420 VEX_W_70_P_1,
1421 VEX_W_70_P_2,
1422 VEX_W_70_P_3,
1423 VEX_W_71_R_2_P_2,
1424 VEX_W_71_R_4_P_2,
1425 VEX_W_71_R_6_P_2,
1426 VEX_W_72_R_2_P_2,
1427 VEX_W_72_R_4_P_2,
1428 VEX_W_72_R_6_P_2,
1429 VEX_W_73_R_2_P_2,
1430 VEX_W_73_R_3_P_2,
1431 VEX_W_73_R_6_P_2,
1432 VEX_W_73_R_7_P_2,
1433 VEX_W_74_P_2,
1434 VEX_W_75_P_2,
1435 VEX_W_76_P_2,
1436 VEX_W_77_P_0,
1437 VEX_W_7C_P_2,
1438 VEX_W_7C_P_3,
1439 VEX_W_7D_P_2,
1440 VEX_W_7D_P_3,
1441 VEX_W_7E_P_1,
1442 VEX_W_7F_P_1,
1443 VEX_W_7F_P_2,
1444 VEX_W_AE_R_2_M_0,
1445 VEX_W_AE_R_3_M_0,
1446 VEX_W_C2_P_0,
1447 VEX_W_C2_P_1,
1448 VEX_W_C2_P_2,
1449 VEX_W_C2_P_3,
1450 VEX_W_C4_P_2,
1451 VEX_W_C5_P_2,
1452 VEX_W_D0_P_2,
1453 VEX_W_D0_P_3,
1454 VEX_W_D1_P_2,
1455 VEX_W_D2_P_2,
1456 VEX_W_D3_P_2,
1457 VEX_W_D4_P_2,
1458 VEX_W_D5_P_2,
1459 VEX_W_D6_P_2,
1460 VEX_W_D7_P_2_M_1,
1461 VEX_W_D8_P_2,
1462 VEX_W_D9_P_2,
1463 VEX_W_DA_P_2,
1464 VEX_W_DB_P_2,
1465 VEX_W_DC_P_2,
1466 VEX_W_DD_P_2,
1467 VEX_W_DE_P_2,
1468 VEX_W_DF_P_2,
1469 VEX_W_E0_P_2,
1470 VEX_W_E1_P_2,
1471 VEX_W_E2_P_2,
1472 VEX_W_E3_P_2,
1473 VEX_W_E4_P_2,
1474 VEX_W_E5_P_2,
1475 VEX_W_E6_P_1,
1476 VEX_W_E6_P_2,
1477 VEX_W_E6_P_3,
1478 VEX_W_E7_P_2_M_0,
1479 VEX_W_E8_P_2,
1480 VEX_W_E9_P_2,
1481 VEX_W_EA_P_2,
1482 VEX_W_EB_P_2,
1483 VEX_W_EC_P_2,
1484 VEX_W_ED_P_2,
1485 VEX_W_EE_P_2,
1486 VEX_W_EF_P_2,
1487 VEX_W_F0_P_3_M_0,
1488 VEX_W_F1_P_2,
1489 VEX_W_F2_P_2,
1490 VEX_W_F3_P_2,
1491 VEX_W_F4_P_2,
1492 VEX_W_F5_P_2,
1493 VEX_W_F6_P_2,
1494 VEX_W_F7_P_2,
1495 VEX_W_F8_P_2,
1496 VEX_W_F9_P_2,
1497 VEX_W_FA_P_2,
1498 VEX_W_FB_P_2,
1499 VEX_W_FC_P_2,
1500 VEX_W_FD_P_2,
1501 VEX_W_FE_P_2,
1502 VEX_W_3800_P_2,
1503 VEX_W_3801_P_2,
1504 VEX_W_3802_P_2,
1505 VEX_W_3803_P_2,
1506 VEX_W_3804_P_2,
1507 VEX_W_3805_P_2,
1508 VEX_W_3806_P_2,
1509 VEX_W_3807_P_2,
1510 VEX_W_3808_P_2,
1511 VEX_W_3809_P_2,
1512 VEX_W_380A_P_2,
1513 VEX_W_380B_P_2,
1514 VEX_W_380C_P_2,
1515 VEX_W_380D_P_2,
1516 VEX_W_380E_P_2,
1517 VEX_W_380F_P_2,
1518 VEX_W_3817_P_2,
1519 VEX_W_3818_P_2_M_0,
1520 VEX_W_3819_P_2_M_0,
1521 VEX_W_381A_P_2_M_0,
1522 VEX_W_381C_P_2,
1523 VEX_W_381D_P_2,
1524 VEX_W_381E_P_2,
1525 VEX_W_3820_P_2,
1526 VEX_W_3821_P_2,
1527 VEX_W_3822_P_2,
1528 VEX_W_3823_P_2,
1529 VEX_W_3824_P_2,
1530 VEX_W_3825_P_2,
1531 VEX_W_3828_P_2,
1532 VEX_W_3829_P_2,
1533 VEX_W_382A_P_2_M_0,
1534 VEX_W_382B_P_2,
1535 VEX_W_382C_P_2_M_0,
1536 VEX_W_382D_P_2_M_0,
1537 VEX_W_382E_P_2_M_0,
1538 VEX_W_382F_P_2_M_0,
1539 VEX_W_3830_P_2,
1540 VEX_W_3831_P_2,
1541 VEX_W_3832_P_2,
1542 VEX_W_3833_P_2,
1543 VEX_W_3834_P_2,
1544 VEX_W_3835_P_2,
1545 VEX_W_3837_P_2,
1546 VEX_W_3838_P_2,
1547 VEX_W_3839_P_2,
1548 VEX_W_383A_P_2,
1549 VEX_W_383B_P_2,
1550 VEX_W_383C_P_2,
1551 VEX_W_383D_P_2,
1552 VEX_W_383E_P_2,
1553 VEX_W_383F_P_2,
1554 VEX_W_3840_P_2,
1555 VEX_W_3841_P_2,
1556 VEX_W_38DB_P_2,
1557 VEX_W_38DC_P_2,
1558 VEX_W_38DD_P_2,
1559 VEX_W_38DE_P_2,
1560 VEX_W_38DF_P_2,
1561 VEX_W_3A04_P_2,
1562 VEX_W_3A05_P_2,
1563 VEX_W_3A06_P_2,
1564 VEX_W_3A08_P_2,
1565 VEX_W_3A09_P_2,
1566 VEX_W_3A0A_P_2,
1567 VEX_W_3A0B_P_2,
1568 VEX_W_3A0C_P_2,
1569 VEX_W_3A0D_P_2,
1570 VEX_W_3A0E_P_2,
1571 VEX_W_3A0F_P_2,
1572 VEX_W_3A14_P_2,
1573 VEX_W_3A15_P_2,
1574 VEX_W_3A18_P_2,
1575 VEX_W_3A19_P_2,
1576 VEX_W_3A20_P_2,
1577 VEX_W_3A21_P_2,
1578 VEX_W_3A40_P_2,
1579 VEX_W_3A41_P_2,
1580 VEX_W_3A42_P_2,
1581 VEX_W_3A44_P_2,
1582 VEX_W_3A48_P_2,
1583 VEX_W_3A49_P_2,
1584 VEX_W_3A4A_P_2,
1585 VEX_W_3A4B_P_2,
1586 VEX_W_3A4C_P_2,
1587 VEX_W_3A60_P_2,
1588 VEX_W_3A61_P_2,
1589 VEX_W_3A62_P_2,
1590 VEX_W_3A63_P_2,
1591 VEX_W_3ADF_P_2
1592};
1593
1594typedef void (*op_rtn) (int bytemode, int sizeflag);
1595
1596struct dis386 {
1597 const char *name;
1598 struct
1599 {
1600 op_rtn rtn;
1601 int bytemode;
1602 } op[MAX_OPERANDS];
1603};
1604
1605/* Upper case letters in the instruction names here are macros.
1606 'A' => print 'b' if no register operands or suffix_always is true
1607 'B' => print 'b' if suffix_always is true
1608 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1609 size prefix
1610 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1611 suffix_always is true
1612 'E' => print 'e' if 32-bit form of jcxz
1613 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1614 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1615 'H' => print ",pt" or ",pn" branch hint
1616 'I' => honor following macro letter even in Intel mode (implemented only
1617 for some of the macro letters)
1618 'J' => print 'l'
1619 'K' => print 'd' or 'q' if rex prefix is present.
1620 'L' => print 'l' if suffix_always is true
1621 'M' => print 'r' if intel_mnemonic is false.
1622 'N' => print 'n' if instruction has no wait "prefix"
1623 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1624 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1625 or suffix_always is true. print 'q' if rex prefix is present.
1626 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1627 is true
1628 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1629 'S' => print 'w', 'l' or 'q' if suffix_always is true
1630 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1631 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1632 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1633 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1634 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1635 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1636 suffix_always is true.
1637 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1638 '!' => change condition from true to false or from false to true.
1639 '%' => add 1 upper case letter to the macro.
1640
1641 2 upper case letter macros:
1642 "XY" => print 'x' or 'y' if no register operands or suffix_always
1643 is true.
1644 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1645 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1646 or suffix_always is true
1647 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1648 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1649 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1650
1651 Many of the above letters print nothing in Intel mode. See "putop"
1652 for the details.
1653
1654 Braces '{' and '}', and vertical bars '|', indicate alternative
1655 mnemonic strings for AT&T and Intel. */
1656
1657static const struct dis386 dis386[] = {
1658 /* 00 */
1659 { "addB", { Eb, Gb } },
1660 { "addS", { Ev, Gv } },
1661 { "addB", { Gb, EbS } },
1662 { "addS", { Gv, EvS } },
1663 { "addB", { AL, Ib } },
1664 { "addS", { eAX, Iv } },
1665 { X86_64_TABLE (X86_64_06) },
1666 { X86_64_TABLE (X86_64_07) },
1667 /* 08 */
1668 { "orB", { Eb, Gb } },
1669 { "orS", { Ev, Gv } },
1670 { "orB", { Gb, EbS } },
1671 { "orS", { Gv, EvS } },
1672 { "orB", { AL, Ib } },
1673 { "orS", { eAX, Iv } },
1674 { X86_64_TABLE (X86_64_0D) },
1675 { Bad_Opcode }, /* 0x0f extended opcode escape */
1676 /* 10 */
1677 { "adcB", { Eb, Gb } },
1678 { "adcS", { Ev, Gv } },
1679 { "adcB", { Gb, EbS } },
1680 { "adcS", { Gv, EvS } },
1681 { "adcB", { AL, Ib } },
1682 { "adcS", { eAX, Iv } },
1683 { X86_64_TABLE (X86_64_16) },
1684 { X86_64_TABLE (X86_64_17) },
1685 /* 18 */
1686 { "sbbB", { Eb, Gb } },
1687 { "sbbS", { Ev, Gv } },
1688 { "sbbB", { Gb, EbS } },
1689 { "sbbS", { Gv, EvS } },
1690 { "sbbB", { AL, Ib } },
1691 { "sbbS", { eAX, Iv } },
1692 { X86_64_TABLE (X86_64_1E) },
1693 { X86_64_TABLE (X86_64_1F) },
1694 /* 20 */
1695 { "andB", { Eb, Gb } },
1696 { "andS", { Ev, Gv } },
1697 { "andB", { Gb, EbS } },
1698 { "andS", { Gv, EvS } },
1699 { "andB", { AL, Ib } },
1700 { "andS", { eAX, Iv } },
1701 { Bad_Opcode }, /* SEG ES prefix */
1702 { X86_64_TABLE (X86_64_27) },
1703 /* 28 */
1704 { "subB", { Eb, Gb } },
1705 { "subS", { Ev, Gv } },
1706 { "subB", { Gb, EbS } },
1707 { "subS", { Gv, EvS } },
1708 { "subB", { AL, Ib } },
1709 { "subS", { eAX, Iv } },
1710 { Bad_Opcode }, /* SEG CS prefix */
1711 { X86_64_TABLE (X86_64_2F) },
1712 /* 30 */
1713 { "xorB", { Eb, Gb } },
1714 { "xorS", { Ev, Gv } },
1715 { "xorB", { Gb, EbS } },
1716 { "xorS", { Gv, EvS } },
1717 { "xorB", { AL, Ib } },
1718 { "xorS", { eAX, Iv } },
1719 { Bad_Opcode }, /* SEG SS prefix */
1720 { X86_64_TABLE (X86_64_37) },
1721 /* 38 */
1722 { "cmpB", { Eb, Gb } },
1723 { "cmpS", { Ev, Gv } },
1724 { "cmpB", { Gb, EbS } },
1725 { "cmpS", { Gv, EvS } },
1726 { "cmpB", { AL, Ib } },
1727 { "cmpS", { eAX, Iv } },
1728 { Bad_Opcode }, /* SEG DS prefix */
1729 { X86_64_TABLE (X86_64_3F) },
1730 /* 40 */
1731 { "inc{S|}", { RMeAX } },
1732 { "inc{S|}", { RMeCX } },
1733 { "inc{S|}", { RMeDX } },
1734 { "inc{S|}", { RMeBX } },
1735 { "inc{S|}", { RMeSP } },
1736 { "inc{S|}", { RMeBP } },
1737 { "inc{S|}", { RMeSI } },
1738 { "inc{S|}", { RMeDI } },
1739 /* 48 */
1740 { "dec{S|}", { RMeAX } },
1741 { "dec{S|}", { RMeCX } },
1742 { "dec{S|}", { RMeDX } },
1743 { "dec{S|}", { RMeBX } },
1744 { "dec{S|}", { RMeSP } },
1745 { "dec{S|}", { RMeBP } },
1746 { "dec{S|}", { RMeSI } },
1747 { "dec{S|}", { RMeDI } },
1748 /* 50 */
1749 { "pushV", { RMrAX } },
1750 { "pushV", { RMrCX } },
1751 { "pushV", { RMrDX } },
1752 { "pushV", { RMrBX } },
1753 { "pushV", { RMrSP } },
1754 { "pushV", { RMrBP } },
1755 { "pushV", { RMrSI } },
1756 { "pushV", { RMrDI } },
1757 /* 58 */
1758 { "popV", { RMrAX } },
1759 { "popV", { RMrCX } },
1760 { "popV", { RMrDX } },
1761 { "popV", { RMrBX } },
1762 { "popV", { RMrSP } },
1763 { "popV", { RMrBP } },
1764 { "popV", { RMrSI } },
1765 { "popV", { RMrDI } },
1766 /* 60 */
1767 { X86_64_TABLE (X86_64_60) },
1768 { X86_64_TABLE (X86_64_61) },
1769 { X86_64_TABLE (X86_64_62) },
1770 { X86_64_TABLE (X86_64_63) },
1771 { Bad_Opcode }, /* seg fs */
1772 { Bad_Opcode }, /* seg gs */
1773 { Bad_Opcode }, /* op size prefix */
1774 { Bad_Opcode }, /* adr size prefix */
1775 /* 68 */
1776 { "pushT", { Iq } },
1777 { "imulS", { Gv, Ev, Iv } },
1778 { "pushT", { sIb } },
1779 { "imulS", { Gv, Ev, sIb } },
1780 { "ins{b|}", { Ybr, indirDX } },
1781 { X86_64_TABLE (X86_64_6D) },
1782 { "outs{b|}", { indirDXr, Xb } },
1783 { X86_64_TABLE (X86_64_6F) },
1784 /* 70 */
1785 { "joH", { Jb, XX, cond_jump_flag } },
1786 { "jnoH", { Jb, XX, cond_jump_flag } },
1787 { "jbH", { Jb, XX, cond_jump_flag } },
1788 { "jaeH", { Jb, XX, cond_jump_flag } },
1789 { "jeH", { Jb, XX, cond_jump_flag } },
1790 { "jneH", { Jb, XX, cond_jump_flag } },
1791 { "jbeH", { Jb, XX, cond_jump_flag } },
1792 { "jaH", { Jb, XX, cond_jump_flag } },
1793 /* 78 */
1794 { "jsH", { Jb, XX, cond_jump_flag } },
1795 { "jnsH", { Jb, XX, cond_jump_flag } },
1796 { "jpH", { Jb, XX, cond_jump_flag } },
1797 { "jnpH", { Jb, XX, cond_jump_flag } },
1798 { "jlH", { Jb, XX, cond_jump_flag } },
1799 { "jgeH", { Jb, XX, cond_jump_flag } },
1800 { "jleH", { Jb, XX, cond_jump_flag } },
1801 { "jgH", { Jb, XX, cond_jump_flag } },
1802 /* 80 */
1803 { REG_TABLE (REG_80) },
1804 { REG_TABLE (REG_81) },
1805 { Bad_Opcode },
1806 { REG_TABLE (REG_82) },
1807 { "testB", { Eb, Gb } },
1808 { "testS", { Ev, Gv } },
1809 { "xchgB", { Eb, Gb } },
1810 { "xchgS", { Ev, Gv } },
1811 /* 88 */
1812 { "movB", { Eb, Gb } },
1813 { "movS", { Ev, Gv } },
1814 { "movB", { Gb, EbS } },
1815 { "movS", { Gv, EvS } },
1816 { "movD", { Sv, Sw } },
1817 { MOD_TABLE (MOD_8D) },
1818 { "movD", { Sw, Sv } },
1819 { REG_TABLE (REG_8F) },
1820 /* 90 */
1821 { PREFIX_TABLE (PREFIX_90) },
1822 { "xchgS", { RMeCX, eAX } },
1823 { "xchgS", { RMeDX, eAX } },
1824 { "xchgS", { RMeBX, eAX } },
1825 { "xchgS", { RMeSP, eAX } },
1826 { "xchgS", { RMeBP, eAX } },
1827 { "xchgS", { RMeSI, eAX } },
1828 { "xchgS", { RMeDI, eAX } },
1829 /* 98 */
1830 { "cW{t|}R", { XX } },
1831 { "cR{t|}O", { XX } },
1832 { X86_64_TABLE (X86_64_9A) },
1833 { Bad_Opcode }, /* fwait */
1834 { "pushfT", { XX } },
1835 { "popfT", { XX } },
1836 { "sahf", { XX } },
1837 { "lahf", { XX } },
1838 /* a0 */
1839 { "mov%LB", { AL, Ob } },
1840 { "mov%LS", { eAX, Ov } },
1841 { "mov%LB", { Ob, AL } },
1842 { "mov%LS", { Ov, eAX } },
1843 { "movs{b|}", { Ybr, Xb } },
1844 { "movs{R|}", { Yvr, Xv } },
1845 { "cmps{b|}", { Xb, Yb } },
1846 { "cmps{R|}", { Xv, Yv } },
1847 /* a8 */
1848 { "testB", { AL, Ib } },
1849 { "testS", { eAX, Iv } },
1850 { "stosB", { Ybr, AL } },
1851 { "stosS", { Yvr, eAX } },
1852 { "lodsB", { ALr, Xb } },
1853 { "lodsS", { eAXr, Xv } },
1854 { "scasB", { AL, Yb } },
1855 { "scasS", { eAX, Yv } },
1856 /* b0 */
1857 { "movB", { RMAL, Ib } },
1858 { "movB", { RMCL, Ib } },
1859 { "movB", { RMDL, Ib } },
1860 { "movB", { RMBL, Ib } },
1861 { "movB", { RMAH, Ib } },
1862 { "movB", { RMCH, Ib } },
1863 { "movB", { RMDH, Ib } },
1864 { "movB", { RMBH, Ib } },
1865 /* b8 */
1866 { "mov%LV", { RMeAX, Iv64 } },
1867 { "mov%LV", { RMeCX, Iv64 } },
1868 { "mov%LV", { RMeDX, Iv64 } },
1869 { "mov%LV", { RMeBX, Iv64 } },
1870 { "mov%LV", { RMeSP, Iv64 } },
1871 { "mov%LV", { RMeBP, Iv64 } },
1872 { "mov%LV", { RMeSI, Iv64 } },
1873 { "mov%LV", { RMeDI, Iv64 } },
1874 /* c0 */
1875 { REG_TABLE (REG_C0) },
1876 { REG_TABLE (REG_C1) },
1877 { "retT", { Iw } },
1878 { "retT", { XX } },
1879 { X86_64_TABLE (X86_64_C4) },
1880 { X86_64_TABLE (X86_64_C5) },
1881 { REG_TABLE (REG_C6) },
1882 { REG_TABLE (REG_C7) },
1883 /* c8 */
1884 { "enterT", { Iw, Ib } },
1885 { "leaveT", { XX } },
1886 { "Jret{|f}P", { Iw } },
1887 { "Jret{|f}P", { XX } },
1888 { "int3", { XX } },
1889 { "int", { Ib } },
1890 { X86_64_TABLE (X86_64_CE) },
1891 { "iretP", { XX } },
1892 /* d0 */
1893 { REG_TABLE (REG_D0) },
1894 { REG_TABLE (REG_D1) },
1895 { REG_TABLE (REG_D2) },
1896 { REG_TABLE (REG_D3) },
1897 { X86_64_TABLE (X86_64_D4) },
1898 { X86_64_TABLE (X86_64_D5) },
1899 { Bad_Opcode },
1900 { "xlat", { DSBX } },
1901 /* d8 */
1902 { FLOAT },
1903 { FLOAT },
1904 { FLOAT },
1905 { FLOAT },
1906 { FLOAT },
1907 { FLOAT },
1908 { FLOAT },
1909 { FLOAT },
1910 /* e0 */
1911 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1912 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1913 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1914 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1915 { "inB", { AL, Ib } },
1916 { "inG", { zAX, Ib } },
1917 { "outB", { Ib, AL } },
1918 { "outG", { Ib, zAX } },
1919 /* e8 */
1920 { "callT", { Jv } },
1921 { "jmpT", { Jv } },
1922 { X86_64_TABLE (X86_64_EA) },
1923 { "jmp", { Jb } },
1924 { "inB", { AL, indirDX } },
1925 { "inG", { zAX, indirDX } },
1926 { "outB", { indirDX, AL } },
1927 { "outG", { indirDX, zAX } },
1928 /* f0 */
1929 { Bad_Opcode }, /* lock prefix */
1930 { "icebp", { XX } },
1931 { Bad_Opcode }, /* repne */
1932 { Bad_Opcode }, /* repz */
1933 { "hlt", { XX } },
1934 { "cmc", { XX } },
1935 { REG_TABLE (REG_F6) },
1936 { REG_TABLE (REG_F7) },
1937 /* f8 */
1938 { "clc", { XX } },
1939 { "stc", { XX } },
1940 { "cli", { XX } },
1941 { "sti", { XX } },
1942 { "cld", { XX } },
1943 { "std", { XX } },
1944 { REG_TABLE (REG_FE) },
1945 { REG_TABLE (REG_FF) },
1946};
1947
1948static const struct dis386 dis386_twobyte[] = {
1949 /* 00 */
1950 { REG_TABLE (REG_0F00 ) },
1951 { REG_TABLE (REG_0F01 ) },
1952 { "larS", { Gv, Ew } },
1953 { "lslS", { Gv, Ew } },
1954 { Bad_Opcode },
1955 { "syscall", { XX } },
1956 { "clts", { XX } },
1957 { "sysretP", { XX } },
1958 /* 08 */
1959 { "invd", { XX } },
1960 { "wbinvd", { XX } },
1961 { Bad_Opcode },
1962 { "ud2a", { XX } },
1963 { Bad_Opcode },
1964 { REG_TABLE (REG_0F0D) },
1965 { "femms", { XX } },
1966 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1967 /* 10 */
1968 { PREFIX_TABLE (PREFIX_0F10) },
1969 { PREFIX_TABLE (PREFIX_0F11) },
1970 { PREFIX_TABLE (PREFIX_0F12) },
1971 { MOD_TABLE (MOD_0F13) },
1972 { "unpcklpX", { XM, EXx } },
1973 { "unpckhpX", { XM, EXx } },
1974 { PREFIX_TABLE (PREFIX_0F16) },
1975 { MOD_TABLE (MOD_0F17) },
1976 /* 18 */
1977 { REG_TABLE (REG_0F18) },
1978 { "nopQ", { Ev } },
1979 { "nopQ", { Ev } },
1980 { "nopQ", { Ev } },
1981 { "nopQ", { Ev } },
1982 { "nopQ", { Ev } },
1983 { "nopQ", { Ev } },
1984 { "nopQ", { Ev } },
1985 /* 20 */
1986 { MOD_TABLE (MOD_0F20) },
1987 { MOD_TABLE (MOD_0F21) },
1988 { MOD_TABLE (MOD_0F22) },
1989 { MOD_TABLE (MOD_0F23) },
1990 { MOD_TABLE (MOD_0F24) },
1991 { Bad_Opcode },
1992 { MOD_TABLE (MOD_0F26) },
1993 { Bad_Opcode },
1994 /* 28 */
1995 { "movapX", { XM, EXx } },
1996 { "movapX", { EXxS, XM } },
1997 { PREFIX_TABLE (PREFIX_0F2A) },
1998 { PREFIX_TABLE (PREFIX_0F2B) },
1999 { PREFIX_TABLE (PREFIX_0F2C) },
2000 { PREFIX_TABLE (PREFIX_0F2D) },
2001 { PREFIX_TABLE (PREFIX_0F2E) },
2002 { PREFIX_TABLE (PREFIX_0F2F) },
2003 /* 30 */
2004 { "wrmsr", { XX } },
2005 { "rdtsc", { XX } },
2006 { "rdmsr", { XX } },
2007 { "rdpmc", { XX } },
2008 { "sysenter", { XX } },
2009 { "sysexit", { XX } },
2010 { Bad_Opcode },
2011 { "getsec", { XX } },
2012 /* 38 */
2013 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2014 { Bad_Opcode },
2015 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2016 { Bad_Opcode },
2017 { Bad_Opcode },
2018 { Bad_Opcode },
2019 { Bad_Opcode },
2020 { Bad_Opcode },
2021 /* 40 */
2022 { "cmovoS", { Gv, Ev } },
2023 { "cmovnoS", { Gv, Ev } },
2024 { "cmovbS", { Gv, Ev } },
2025 { "cmovaeS", { Gv, Ev } },
2026 { "cmoveS", { Gv, Ev } },
2027 { "cmovneS", { Gv, Ev } },
2028 { "cmovbeS", { Gv, Ev } },
2029 { "cmovaS", { Gv, Ev } },
2030 /* 48 */
2031 { "cmovsS", { Gv, Ev } },
2032 { "cmovnsS", { Gv, Ev } },
2033 { "cmovpS", { Gv, Ev } },
2034 { "cmovnpS", { Gv, Ev } },
2035 { "cmovlS", { Gv, Ev } },
2036 { "cmovgeS", { Gv, Ev } },
2037 { "cmovleS", { Gv, Ev } },
2038 { "cmovgS", { Gv, Ev } },
2039 /* 50 */
2040 { MOD_TABLE (MOD_0F51) },
2041 { PREFIX_TABLE (PREFIX_0F51) },
2042 { PREFIX_TABLE (PREFIX_0F52) },
2043 { PREFIX_TABLE (PREFIX_0F53) },
2044 { "andpX", { XM, EXx } },
2045 { "andnpX", { XM, EXx } },
2046 { "orpX", { XM, EXx } },
2047 { "xorpX", { XM, EXx } },
2048 /* 58 */
2049 { PREFIX_TABLE (PREFIX_0F58) },
2050 { PREFIX_TABLE (PREFIX_0F59) },
2051 { PREFIX_TABLE (PREFIX_0F5A) },
2052 { PREFIX_TABLE (PREFIX_0F5B) },
2053 { PREFIX_TABLE (PREFIX_0F5C) },
2054 { PREFIX_TABLE (PREFIX_0F5D) },
2055 { PREFIX_TABLE (PREFIX_0F5E) },
2056 { PREFIX_TABLE (PREFIX_0F5F) },
2057 /* 60 */
2058 { PREFIX_TABLE (PREFIX_0F60) },
2059 { PREFIX_TABLE (PREFIX_0F61) },
2060 { PREFIX_TABLE (PREFIX_0F62) },
2061 { "packsswb", { MX, EM } },
2062 { "pcmpgtb", { MX, EM } },
2063 { "pcmpgtw", { MX, EM } },
2064 { "pcmpgtd", { MX, EM } },
2065 { "packuswb", { MX, EM } },
2066 /* 68 */
2067 { "punpckhbw", { MX, EM } },
2068 { "punpckhwd", { MX, EM } },
2069 { "punpckhdq", { MX, EM } },
2070 { "packssdw", { MX, EM } },
2071 { PREFIX_TABLE (PREFIX_0F6C) },
2072 { PREFIX_TABLE (PREFIX_0F6D) },
2073 { "movK", { MX, Edq } },
2074 { PREFIX_TABLE (PREFIX_0F6F) },
2075 /* 70 */
2076 { PREFIX_TABLE (PREFIX_0F70) },
2077 { REG_TABLE (REG_0F71) },
2078 { REG_TABLE (REG_0F72) },
2079 { REG_TABLE (REG_0F73) },
2080 { "pcmpeqb", { MX, EM } },
2081 { "pcmpeqw", { MX, EM } },
2082 { "pcmpeqd", { MX, EM } },
2083 { "emms", { XX } },
2084 /* 78 */
2085 { PREFIX_TABLE (PREFIX_0F78) },
2086 { PREFIX_TABLE (PREFIX_0F79) },
2087 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2088 { Bad_Opcode },
2089 { PREFIX_TABLE (PREFIX_0F7C) },
2090 { PREFIX_TABLE (PREFIX_0F7D) },
2091 { PREFIX_TABLE (PREFIX_0F7E) },
2092 { PREFIX_TABLE (PREFIX_0F7F) },
2093 /* 80 */
2094 { "joH", { Jv, XX, cond_jump_flag } },
2095 { "jnoH", { Jv, XX, cond_jump_flag } },
2096 { "jbH", { Jv, XX, cond_jump_flag } },
2097 { "jaeH", { Jv, XX, cond_jump_flag } },
2098 { "jeH", { Jv, XX, cond_jump_flag } },
2099 { "jneH", { Jv, XX, cond_jump_flag } },
2100 { "jbeH", { Jv, XX, cond_jump_flag } },
2101 { "jaH", { Jv, XX, cond_jump_flag } },
2102 /* 88 */
2103 { "jsH", { Jv, XX, cond_jump_flag } },
2104 { "jnsH", { Jv, XX, cond_jump_flag } },
2105 { "jpH", { Jv, XX, cond_jump_flag } },
2106 { "jnpH", { Jv, XX, cond_jump_flag } },
2107 { "jlH", { Jv, XX, cond_jump_flag } },
2108 { "jgeH", { Jv, XX, cond_jump_flag } },
2109 { "jleH", { Jv, XX, cond_jump_flag } },
2110 { "jgH", { Jv, XX, cond_jump_flag } },
2111 /* 90 */
2112 { "seto", { Eb } },
2113 { "setno", { Eb } },
2114 { "setb", { Eb } },
2115 { "setae", { Eb } },
2116 { "sete", { Eb } },
2117 { "setne", { Eb } },
2118 { "setbe", { Eb } },
2119 { "seta", { Eb } },
2120 /* 98 */
2121 { "sets", { Eb } },
2122 { "setns", { Eb } },
2123 { "setp", { Eb } },
2124 { "setnp", { Eb } },
2125 { "setl", { Eb } },
2126 { "setge", { Eb } },
2127 { "setle", { Eb } },
2128 { "setg", { Eb } },
2129 /* a0 */
2130 { "pushT", { fs } },
2131 { "popT", { fs } },
2132 { "cpuid", { XX } },
2133 { "btS", { Ev, Gv } },
2134 { "shldS", { Ev, Gv, Ib } },
2135 { "shldS", { Ev, Gv, CL } },
2136 { REG_TABLE (REG_0FA6) },
2137 { REG_TABLE (REG_0FA7) },
2138 /* a8 */
2139 { "pushT", { gs } },
2140 { "popT", { gs } },
2141 { "rsm", { XX } },
2142 { "btsS", { Ev, Gv } },
2143 { "shrdS", { Ev, Gv, Ib } },
2144 { "shrdS", { Ev, Gv, CL } },
2145 { REG_TABLE (REG_0FAE) },
2146 { "imulS", { Gv, Ev } },
2147 /* b0 */
2148 { "cmpxchgB", { Eb, Gb } },
2149 { "cmpxchgS", { Ev, Gv } },
2150 { MOD_TABLE (MOD_0FB2) },
2151 { "btrS", { Ev, Gv } },
2152 { MOD_TABLE (MOD_0FB4) },
2153 { MOD_TABLE (MOD_0FB5) },
2154 { "movz{bR|x}", { Gv, Eb } },
2155 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
2156 /* b8 */
2157 { PREFIX_TABLE (PREFIX_0FB8) },
2158 { "ud2b", { XX } },
2159 { REG_TABLE (REG_0FBA) },
2160 { "btcS", { Ev, Gv } },
2161 { "bsfS", { Gv, Ev } },
2162 { PREFIX_TABLE (PREFIX_0FBD) },
2163 { "movs{bR|x}", { Gv, Eb } },
2164 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
2165 /* c0 */
2166 { "xaddB", { Eb, Gb } },
2167 { "xaddS", { Ev, Gv } },
2168 { PREFIX_TABLE (PREFIX_0FC2) },
2169 { PREFIX_TABLE (PREFIX_0FC3) },
2170 { "pinsrw", { MX, Edqw, Ib } },
2171 { "pextrw", { Gdq, MS, Ib } },
2172 { "shufpX", { XM, EXx, Ib } },
2173 { REG_TABLE (REG_0FC7) },
2174 /* c8 */
2175 { "bswap", { RMeAX } },
2176 { "bswap", { RMeCX } },
2177 { "bswap", { RMeDX } },
2178 { "bswap", { RMeBX } },
2179 { "bswap", { RMeSP } },
2180 { "bswap", { RMeBP } },
2181 { "bswap", { RMeSI } },
2182 { "bswap", { RMeDI } },
2183 /* d0 */
2184 { PREFIX_TABLE (PREFIX_0FD0) },
2185 { "psrlw", { MX, EM } },
2186 { "psrld", { MX, EM } },
2187 { "psrlq", { MX, EM } },
2188 { "paddq", { MX, EM } },
2189 { "pmullw", { MX, EM } },
2190 { PREFIX_TABLE (PREFIX_0FD6) },
2191 { MOD_TABLE (MOD_0FD7) },
2192 /* d8 */
2193 { "psubusb", { MX, EM } },
2194 { "psubusw", { MX, EM } },
2195 { "pminub", { MX, EM } },
2196 { "pand", { MX, EM } },
2197 { "paddusb", { MX, EM } },
2198 { "paddusw", { MX, EM } },
2199 { "pmaxub", { MX, EM } },
2200 { "pandn", { MX, EM } },
2201 /* e0 */
2202 { "pavgb", { MX, EM } },
2203 { "psraw", { MX, EM } },
2204 { "psrad", { MX, EM } },
2205 { "pavgw", { MX, EM } },
2206 { "pmulhuw", { MX, EM } },
2207 { "pmulhw", { MX, EM } },
2208 { PREFIX_TABLE (PREFIX_0FE6) },
2209 { PREFIX_TABLE (PREFIX_0FE7) },
2210 /* e8 */
2211 { "psubsb", { MX, EM } },
2212 { "psubsw", { MX, EM } },
2213 { "pminsw", { MX, EM } },
2214 { "por", { MX, EM } },
2215 { "paddsb", { MX, EM } },
2216 { "paddsw", { MX, EM } },
2217 { "pmaxsw", { MX, EM } },
2218 { "pxor", { MX, EM } },
2219 /* f0 */
2220 { PREFIX_TABLE (PREFIX_0FF0) },
2221 { "psllw", { MX, EM } },
2222 { "pslld", { MX, EM } },
2223 { "psllq", { MX, EM } },
2224 { "pmuludq", { MX, EM } },
2225 { "pmaddwd", { MX, EM } },
2226 { "psadbw", { MX, EM } },
2227 { PREFIX_TABLE (PREFIX_0FF7) },
2228 /* f8 */
2229 { "psubb", { MX, EM } },
2230 { "psubw", { MX, EM } },
2231 { "psubd", { MX, EM } },
2232 { "psubq", { MX, EM } },
2233 { "paddb", { MX, EM } },
2234 { "paddw", { MX, EM } },
2235 { "paddd", { MX, EM } },
2236 { Bad_Opcode },
2237};
2238
2239static const unsigned char onebyte_has_modrm[256] = {
2240 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2241 /* ------------------------------- */
2242 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2243 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2244 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2245 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2246 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2247 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2248 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2249 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2250 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2251 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2252 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2253 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2254 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2255 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2256 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2257 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2258 /* ------------------------------- */
2259 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2260};
2261
2262static const unsigned char twobyte_has_modrm[256] = {
2263 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2264 /* ------------------------------- */
2265 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2266 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2267 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2268 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2269 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2270 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2271 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2272 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2273 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2274 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2275 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2276 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2277 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2278 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2279 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2280 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2281 /* ------------------------------- */
2282 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2283};
2284
2285static char obuf[100];
2286static char *obufp;
2287static char *mnemonicendp;
2288static char scratchbuf[100];
2289static unsigned char *start_codep;
2290static unsigned char *insn_codep;
2291static unsigned char *codep;
2292static int last_lock_prefix;
2293static int last_repz_prefix;
2294static int last_repnz_prefix;
2295static int last_data_prefix;
2296static int last_addr_prefix;
2297static int last_rex_prefix;
2298static int last_seg_prefix;
2299#define MAX_CODE_LENGTH 15
2300/* We can up to 14 prefixes since the maximum instruction length is
2301 15bytes. */
2302static int all_prefixes[MAX_CODE_LENGTH - 1];
2303static disassemble_info *the_info;
2304static struct
2305 {
2306 int mod;
2307 int reg;
2308 int rm;
2309 }
2310modrm;
2311static unsigned char need_modrm;
2312static struct
2313 {
2314 int scale;
2315 int index;
2316 int base;
2317 }
2318sib;
2319static struct
2320 {
2321 int register_specifier;
2322 int length;
2323 int prefix;
2324 int w;
2325 }
2326vex;
2327static unsigned char need_vex;
2328static unsigned char need_vex_reg;
2329static unsigned char vex_w_done;
2330
2331struct op
2332 {
2333 const char *name;
2334 unsigned int len;
2335 };
2336
2337/* If we are accessing mod/rm/reg without need_modrm set, then the
2338 values are stale. Hitting this abort likely indicates that you
2339 need to update onebyte_has_modrm or twobyte_has_modrm. */
2340#define MODRM_CHECK if (!need_modrm) abort ()
2341
2342static const char **names64;
2343static const char **names32;
2344static const char **names16;
2345static const char **names8;
2346static const char **names8rex;
2347static const char **names_seg;
2348static const char *index64;
2349static const char *index32;
2350static const char **index16;
2351
2352static const char *intel_names64[] = {
2353 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2354 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2355};
2356static const char *intel_names32[] = {
2357 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2358 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2359};
2360static const char *intel_names16[] = {
2361 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2362 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2363};
2364static const char *intel_names8[] = {
2365 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2366};
2367static const char *intel_names8rex[] = {
2368 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2369 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2370};
2371static const char *intel_names_seg[] = {
2372 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2373};
2374static const char *intel_index64 = "riz";
2375static const char *intel_index32 = "eiz";
2376static const char *intel_index16[] = {
2377 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2378};
2379
2380static const char *att_names64[] = {
2381 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2382 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2383};
2384static const char *att_names32[] = {
2385 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2386 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2387};
2388static const char *att_names16[] = {
2389 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2390 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2391};
2392static const char *att_names8[] = {
2393 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2394};
2395static const char *att_names8rex[] = {
2396 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2397 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2398};
2399static const char *att_names_seg[] = {
2400 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2401};
2402static const char *att_index64 = "%riz";
2403static const char *att_index32 = "%eiz";
2404static const char *att_index16[] = {
2405 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2406};
2407
2408static const char **names_mm;
2409static const char *intel_names_mm[] = {
2410 "mm0", "mm1", "mm2", "mm3",
2411 "mm4", "mm5", "mm6", "mm7"
2412};
2413static const char *att_names_mm[] = {
2414 "%mm0", "%mm1", "%mm2", "%mm3",
2415 "%mm4", "%mm5", "%mm6", "%mm7"
2416};
2417
2418static const char **names_xmm;
2419static const char *intel_names_xmm[] = {
2420 "xmm0", "xmm1", "xmm2", "xmm3",
2421 "xmm4", "xmm5", "xmm6", "xmm7",
2422 "xmm8", "xmm9", "xmm10", "xmm11",
2423 "xmm12", "xmm13", "xmm14", "xmm15"
2424};
2425static const char *att_names_xmm[] = {
2426 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2427 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2428 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2429 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2430};
2431
2432static const char **names_ymm;
2433static const char *intel_names_ymm[] = {
2434 "ymm0", "ymm1", "ymm2", "ymm3",
2435 "ymm4", "ymm5", "ymm6", "ymm7",
2436 "ymm8", "ymm9", "ymm10", "ymm11",
2437 "ymm12", "ymm13", "ymm14", "ymm15"
2438};
2439static const char *att_names_ymm[] = {
2440 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2441 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2442 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2443 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2444};
2445
2446static const struct dis386 reg_table[][8] = {
2447 /* REG_80 */
2448 {
2449 { "addA", { Eb, Ib } },
2450 { "orA", { Eb, Ib } },
2451 { "adcA", { Eb, Ib } },
2452 { "sbbA", { Eb, Ib } },
2453 { "andA", { Eb, Ib } },
2454 { "subA", { Eb, Ib } },
2455 { "xorA", { Eb, Ib } },
2456 { "cmpA", { Eb, Ib } },
2457 },
2458 /* REG_81 */
2459 {
2460 { "addQ", { Ev, Iv } },
2461 { "orQ", { Ev, Iv } },
2462 { "adcQ", { Ev, Iv } },
2463 { "sbbQ", { Ev, Iv } },
2464 { "andQ", { Ev, Iv } },
2465 { "subQ", { Ev, Iv } },
2466 { "xorQ", { Ev, Iv } },
2467 { "cmpQ", { Ev, Iv } },
2468 },
2469 /* REG_82 */
2470 {
2471 { "addQ", { Ev, sIb } },
2472 { "orQ", { Ev, sIb } },
2473 { "adcQ", { Ev, sIb } },
2474 { "sbbQ", { Ev, sIb } },
2475 { "andQ", { Ev, sIb } },
2476 { "subQ", { Ev, sIb } },
2477 { "xorQ", { Ev, sIb } },
2478 { "cmpQ", { Ev, sIb } },
2479 },
2480 /* REG_8F */
2481 {
2482 { "popU", { stackEv } },
2483 { XOP_8F_TABLE (XOP_09) },
2484 { Bad_Opcode },
2485 { Bad_Opcode },
2486 { Bad_Opcode },
2487 { XOP_8F_TABLE (XOP_09) },
2488 },
2489 /* REG_C0 */
2490 {
2491 { "rolA", { Eb, Ib } },
2492 { "rorA", { Eb, Ib } },
2493 { "rclA", { Eb, Ib } },
2494 { "rcrA", { Eb, Ib } },
2495 { "shlA", { Eb, Ib } },
2496 { "shrA", { Eb, Ib } },
2497 { Bad_Opcode },
2498 { "sarA", { Eb, Ib } },
2499 },
2500 /* REG_C1 */
2501 {
2502 { "rolQ", { Ev, Ib } },
2503 { "rorQ", { Ev, Ib } },
2504 { "rclQ", { Ev, Ib } },
2505 { "rcrQ", { Ev, Ib } },
2506 { "shlQ", { Ev, Ib } },
2507 { "shrQ", { Ev, Ib } },
2508 { Bad_Opcode },
2509 { "sarQ", { Ev, Ib } },
2510 },
2511 /* REG_C6 */
2512 {
2513 { "movA", { Eb, Ib } },
2514 },
2515 /* REG_C7 */
2516 {
2517 { "movQ", { Ev, Iv } },
2518 },
2519 /* REG_D0 */
2520 {
2521 { "rolA", { Eb, I1 } },
2522 { "rorA", { Eb, I1 } },
2523 { "rclA", { Eb, I1 } },
2524 { "rcrA", { Eb, I1 } },
2525 { "shlA", { Eb, I1 } },
2526 { "shrA", { Eb, I1 } },
2527 { Bad_Opcode },
2528 { "sarA", { Eb, I1 } },
2529 },
2530 /* REG_D1 */
2531 {
2532 { "rolQ", { Ev, I1 } },
2533 { "rorQ", { Ev, I1 } },
2534 { "rclQ", { Ev, I1 } },
2535 { "rcrQ", { Ev, I1 } },
2536 { "shlQ", { Ev, I1 } },
2537 { "shrQ", { Ev, I1 } },
2538 { Bad_Opcode },
2539 { "sarQ", { Ev, I1 } },
2540 },
2541 /* REG_D2 */
2542 {
2543 { "rolA", { Eb, CL } },
2544 { "rorA", { Eb, CL } },
2545 { "rclA", { Eb, CL } },
2546 { "rcrA", { Eb, CL } },
2547 { "shlA", { Eb, CL } },
2548 { "shrA", { Eb, CL } },
2549 { Bad_Opcode },
2550 { "sarA", { Eb, CL } },
2551 },
2552 /* REG_D3 */
2553 {
2554 { "rolQ", { Ev, CL } },
2555 { "rorQ", { Ev, CL } },
2556 { "rclQ", { Ev, CL } },
2557 { "rcrQ", { Ev, CL } },
2558 { "shlQ", { Ev, CL } },
2559 { "shrQ", { Ev, CL } },
2560 { Bad_Opcode },
2561 { "sarQ", { Ev, CL } },
2562 },
2563 /* REG_F6 */
2564 {
2565 { "testA", { Eb, Ib } },
2566 { Bad_Opcode },
2567 { "notA", { Eb } },
2568 { "negA", { Eb } },
2569 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2570 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2571 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2572 { "idivA", { Eb } }, /* and idiv for consistency. */
2573 },
2574 /* REG_F7 */
2575 {
2576 { "testQ", { Ev, Iv } },
2577 { Bad_Opcode },
2578 { "notQ", { Ev } },
2579 { "negQ", { Ev } },
2580 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2581 { "imulQ", { Ev } },
2582 { "divQ", { Ev } },
2583 { "idivQ", { Ev } },
2584 },
2585 /* REG_FE */
2586 {
2587 { "incA", { Eb } },
2588 { "decA", { Eb } },
2589 },
2590 /* REG_FF */
2591 {
2592 { "incQ", { Ev } },
2593 { "decQ", { Ev } },
2594 { "callT", { indirEv } },
2595 { "JcallT", { indirEp } },
2596 { "jmpT", { indirEv } },
2597 { "JjmpT", { indirEp } },
2598 { "pushU", { stackEv } },
2599 { Bad_Opcode },
2600 },
2601 /* REG_0F00 */
2602 {
2603 { "sldtD", { Sv } },
2604 { "strD", { Sv } },
2605 { "lldt", { Ew } },
2606 { "ltr", { Ew } },
2607 { "verr", { Ew } },
2608 { "verw", { Ew } },
2609 { Bad_Opcode },
2610 { Bad_Opcode },
2611 },
2612 /* REG_0F01 */
2613 {
2614 { MOD_TABLE (MOD_0F01_REG_0) },
2615 { MOD_TABLE (MOD_0F01_REG_1) },
2616 { MOD_TABLE (MOD_0F01_REG_2) },
2617 { MOD_TABLE (MOD_0F01_REG_3) },
2618 { "smswD", { Sv } },
2619 { Bad_Opcode },
2620 { "lmsw", { Ew } },
2621 { MOD_TABLE (MOD_0F01_REG_7) },
2622 },
2623 /* REG_0F0D */
2624 {
2625 { "prefetch", { Eb } },
2626 { "prefetchw", { Eb } },
2627 },
2628 /* REG_0F18 */
2629 {
2630 { MOD_TABLE (MOD_0F18_REG_0) },
2631 { MOD_TABLE (MOD_0F18_REG_1) },
2632 { MOD_TABLE (MOD_0F18_REG_2) },
2633 { MOD_TABLE (MOD_0F18_REG_3) },
2634 },
2635 /* REG_0F71 */
2636 {
2637 { Bad_Opcode },
2638 { Bad_Opcode },
2639 { MOD_TABLE (MOD_0F71_REG_2) },
2640 { Bad_Opcode },
2641 { MOD_TABLE (MOD_0F71_REG_4) },
2642 { Bad_Opcode },
2643 { MOD_TABLE (MOD_0F71_REG_6) },
2644 },
2645 /* REG_0F72 */
2646 {
2647 { Bad_Opcode },
2648 { Bad_Opcode },
2649 { MOD_TABLE (MOD_0F72_REG_2) },
2650 { Bad_Opcode },
2651 { MOD_TABLE (MOD_0F72_REG_4) },
2652 { Bad_Opcode },
2653 { MOD_TABLE (MOD_0F72_REG_6) },
2654 },
2655 /* REG_0F73 */
2656 {
2657 { Bad_Opcode },
2658 { Bad_Opcode },
2659 { MOD_TABLE (MOD_0F73_REG_2) },
2660 { MOD_TABLE (MOD_0F73_REG_3) },
2661 { Bad_Opcode },
2662 { Bad_Opcode },
2663 { MOD_TABLE (MOD_0F73_REG_6) },
2664 { MOD_TABLE (MOD_0F73_REG_7) },
2665 },
2666 /* REG_0FA6 */
2667 {
2668 { "montmul", { { OP_0f07, 0 } } },
2669 { "xsha1", { { OP_0f07, 0 } } },
2670 { "xsha256", { { OP_0f07, 0 } } },
2671 },
2672 /* REG_0FA7 */
2673 {
2674 { "xstore-rng", { { OP_0f07, 0 } } },
2675 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2676 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2677 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2678 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2679 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2680 },
2681 /* REG_0FAE */
2682 {
2683 { MOD_TABLE (MOD_0FAE_REG_0) },
2684 { MOD_TABLE (MOD_0FAE_REG_1) },
2685 { MOD_TABLE (MOD_0FAE_REG_2) },
2686 { MOD_TABLE (MOD_0FAE_REG_3) },
2687 { MOD_TABLE (MOD_0FAE_REG_4) },
2688 { MOD_TABLE (MOD_0FAE_REG_5) },
2689 { MOD_TABLE (MOD_0FAE_REG_6) },
2690 { MOD_TABLE (MOD_0FAE_REG_7) },
2691 },
2692 /* REG_0FBA */
2693 {
2694 { Bad_Opcode },
2695 { Bad_Opcode },
2696 { Bad_Opcode },
2697 { Bad_Opcode },
2698 { "btQ", { Ev, Ib } },
2699 { "btsQ", { Ev, Ib } },
2700 { "btrQ", { Ev, Ib } },
2701 { "btcQ", { Ev, Ib } },
2702 },
2703 /* REG_0FC7 */
2704 {
2705 { Bad_Opcode },
2706 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2707 { Bad_Opcode },
2708 { Bad_Opcode },
2709 { Bad_Opcode },
2710 { Bad_Opcode },
2711 { MOD_TABLE (MOD_0FC7_REG_6) },
2712 { MOD_TABLE (MOD_0FC7_REG_7) },
2713 },
2714 /* REG_VEX_71 */
2715 {
2716 { Bad_Opcode },
2717 { Bad_Opcode },
2718 { MOD_TABLE (MOD_VEX_71_REG_2) },
2719 { Bad_Opcode },
2720 { MOD_TABLE (MOD_VEX_71_REG_4) },
2721 { Bad_Opcode },
2722 { MOD_TABLE (MOD_VEX_71_REG_6) },
2723 },
2724 /* REG_VEX_72 */
2725 {
2726 { Bad_Opcode },
2727 { Bad_Opcode },
2728 { MOD_TABLE (MOD_VEX_72_REG_2) },
2729 { Bad_Opcode },
2730 { MOD_TABLE (MOD_VEX_72_REG_4) },
2731 { Bad_Opcode },
2732 { MOD_TABLE (MOD_VEX_72_REG_6) },
2733 },
2734 /* REG_VEX_73 */
2735 {
2736 { Bad_Opcode },
2737 { Bad_Opcode },
2738 { MOD_TABLE (MOD_VEX_73_REG_2) },
2739 { MOD_TABLE (MOD_VEX_73_REG_3) },
2740 { Bad_Opcode },
2741 { Bad_Opcode },
2742 { MOD_TABLE (MOD_VEX_73_REG_6) },
2743 { MOD_TABLE (MOD_VEX_73_REG_7) },
2744 },
2745 /* REG_VEX_AE */
2746 {
2747 { Bad_Opcode },
2748 { Bad_Opcode },
2749 { MOD_TABLE (MOD_VEX_AE_REG_2) },
2750 { MOD_TABLE (MOD_VEX_AE_REG_3) },
2751 },
2752 /* REG_XOP_LWPCB */
2753 {
2754 { "llwpcb", { { OP_LWPCB_E, 0 } } },
2755 { "slwpcb", { { OP_LWPCB_E, 0 } } },
2756 },
2757 /* REG_XOP_LWP */
2758 {
2759 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2760 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2761 },
2762};
2763
2764static const struct dis386 prefix_table[][4] = {
2765 /* PREFIX_90 */
2766 {
2767 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2768 { "pause", { XX } },
2769 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2770 },
2771
2772 /* PREFIX_0F10 */
2773 {
2774 { "movups", { XM, EXx } },
2775 { "movss", { XM, EXd } },
2776 { "movupd", { XM, EXx } },
2777 { "movsd", { XM, EXq } },
2778 },
2779
2780 /* PREFIX_0F11 */
2781 {
2782 { "movups", { EXxS, XM } },
2783 { "movss", { EXdS, XM } },
2784 { "movupd", { EXxS, XM } },
2785 { "movsd", { EXqS, XM } },
2786 },
2787
2788 /* PREFIX_0F12 */
2789 {
2790 { MOD_TABLE (MOD_0F12_PREFIX_0) },
2791 { "movsldup", { XM, EXx } },
2792 { "movlpd", { XM, EXq } },
2793 { "movddup", { XM, EXq } },
2794 },
2795
2796 /* PREFIX_0F16 */
2797 {
2798 { MOD_TABLE (MOD_0F16_PREFIX_0) },
2799 { "movshdup", { XM, EXx } },
2800 { "movhpd", { XM, EXq } },
2801 },
2802
2803 /* PREFIX_0F2A */
2804 {
2805 { "cvtpi2ps", { XM, EMCq } },
2806 { "cvtsi2ss%LQ", { XM, Ev } },
2807 { "cvtpi2pd", { XM, EMCq } },
2808 { "cvtsi2sd%LQ", { XM, Ev } },
2809 },
2810
2811 /* PREFIX_0F2B */
2812 {
2813 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2814 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2815 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2816 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2817 },
2818
2819 /* PREFIX_0F2C */
2820 {
2821 { "cvttps2pi", { MXC, EXq } },
2822 { "cvttss2siY", { Gv, EXd } },
2823 { "cvttpd2pi", { MXC, EXx } },
2824 { "cvttsd2siY", { Gv, EXq } },
2825 },
2826
2827 /* PREFIX_0F2D */
2828 {
2829 { "cvtps2pi", { MXC, EXq } },
2830 { "cvtss2siY", { Gv, EXd } },
2831 { "cvtpd2pi", { MXC, EXx } },
2832 { "cvtsd2siY", { Gv, EXq } },
2833 },
2834
2835 /* PREFIX_0F2E */
2836 {
2837 { "ucomiss",{ XM, EXd } },
2838 { Bad_Opcode },
2839 { "ucomisd",{ XM, EXq } },
2840 },
2841
2842 /* PREFIX_0F2F */
2843 {
2844 { "comiss", { XM, EXd } },
2845 { Bad_Opcode },
2846 { "comisd", { XM, EXq } },
2847 },
2848
2849 /* PREFIX_0F51 */
2850 {
2851 { "sqrtps", { XM, EXx } },
2852 { "sqrtss", { XM, EXd } },
2853 { "sqrtpd", { XM, EXx } },
2854 { "sqrtsd", { XM, EXq } },
2855 },
2856
2857 /* PREFIX_0F52 */
2858 {
2859 { "rsqrtps",{ XM, EXx } },
2860 { "rsqrtss",{ XM, EXd } },
2861 },
2862
2863 /* PREFIX_0F53 */
2864 {
2865 { "rcpps", { XM, EXx } },
2866 { "rcpss", { XM, EXd } },
2867 },
2868
2869 /* PREFIX_0F58 */
2870 {
2871 { "addps", { XM, EXx } },
2872 { "addss", { XM, EXd } },
2873 { "addpd", { XM, EXx } },
2874 { "addsd", { XM, EXq } },
2875 },
2876
2877 /* PREFIX_0F59 */
2878 {
2879 { "mulps", { XM, EXx } },
2880 { "mulss", { XM, EXd } },
2881 { "mulpd", { XM, EXx } },
2882 { "mulsd", { XM, EXq } },
2883 },
2884
2885 /* PREFIX_0F5A */
2886 {
2887 { "cvtps2pd", { XM, EXq } },
2888 { "cvtss2sd", { XM, EXd } },
2889 { "cvtpd2ps", { XM, EXx } },
2890 { "cvtsd2ss", { XM, EXq } },
2891 },
2892
2893 /* PREFIX_0F5B */
2894 {
2895 { "cvtdq2ps", { XM, EXx } },
2896 { "cvttps2dq", { XM, EXx } },
2897 { "cvtps2dq", { XM, EXx } },
2898 },
2899
2900 /* PREFIX_0F5C */
2901 {
2902 { "subps", { XM, EXx } },
2903 { "subss", { XM, EXd } },
2904 { "subpd", { XM, EXx } },
2905 { "subsd", { XM, EXq } },
2906 },
2907
2908 /* PREFIX_0F5D */
2909 {
2910 { "minps", { XM, EXx } },
2911 { "minss", { XM, EXd } },
2912 { "minpd", { XM, EXx } },
2913 { "minsd", { XM, EXq } },
2914 },
2915
2916 /* PREFIX_0F5E */
2917 {
2918 { "divps", { XM, EXx } },
2919 { "divss", { XM, EXd } },
2920 { "divpd", { XM, EXx } },
2921 { "divsd", { XM, EXq } },
2922 },
2923
2924 /* PREFIX_0F5F */
2925 {
2926 { "maxps", { XM, EXx } },
2927 { "maxss", { XM, EXd } },
2928 { "maxpd", { XM, EXx } },
2929 { "maxsd", { XM, EXq } },
2930 },
2931
2932 /* PREFIX_0F60 */
2933 {
2934 { "punpcklbw",{ MX, EMd } },
2935 { Bad_Opcode },
2936 { "punpcklbw",{ MX, EMx } },
2937 },
2938
2939 /* PREFIX_0F61 */
2940 {
2941 { "punpcklwd",{ MX, EMd } },
2942 { Bad_Opcode },
2943 { "punpcklwd",{ MX, EMx } },
2944 },
2945
2946 /* PREFIX_0F62 */
2947 {
2948 { "punpckldq",{ MX, EMd } },
2949 { Bad_Opcode },
2950 { "punpckldq",{ MX, EMx } },
2951 },
2952
2953 /* PREFIX_0F6C */
2954 {
2955 { Bad_Opcode },
2956 { Bad_Opcode },
2957 { "punpcklqdq", { XM, EXx } },
2958 },
2959
2960 /* PREFIX_0F6D */
2961 {
2962 { Bad_Opcode },
2963 { Bad_Opcode },
2964 { "punpckhqdq", { XM, EXx } },
2965 },
2966
2967 /* PREFIX_0F6F */
2968 {
2969 { "movq", { MX, EM } },
2970 { "movdqu", { XM, EXx } },
2971 { "movdqa", { XM, EXx } },
2972 },
2973
2974 /* PREFIX_0F70 */
2975 {
2976 { "pshufw", { MX, EM, Ib } },
2977 { "pshufhw",{ XM, EXx, Ib } },
2978 { "pshufd", { XM, EXx, Ib } },
2979 { "pshuflw",{ XM, EXx, Ib } },
2980 },
2981
2982 /* PREFIX_0F73_REG_3 */
2983 {
2984 { Bad_Opcode },
2985 { Bad_Opcode },
2986 { "psrldq", { XS, Ib } },
2987 },
2988
2989 /* PREFIX_0F73_REG_7 */
2990 {
2991 { Bad_Opcode },
2992 { Bad_Opcode },
2993 { "pslldq", { XS, Ib } },
2994 },
2995
2996 /* PREFIX_0F78 */
2997 {
2998 {"vmread", { Em, Gm } },
2999 { Bad_Opcode },
3000 {"extrq", { XS, Ib, Ib } },
3001 {"insertq", { XM, XS, Ib, Ib } },
3002 },
3003
3004 /* PREFIX_0F79 */
3005 {
3006 {"vmwrite", { Gm, Em } },
3007 { Bad_Opcode },
3008 {"extrq", { XM, XS } },
3009 {"insertq", { XM, XS } },
3010 },
3011
3012 /* PREFIX_0F7C */
3013 {
3014 { Bad_Opcode },
3015 { Bad_Opcode },
3016 { "haddpd", { XM, EXx } },
3017 { "haddps", { XM, EXx } },
3018 },
3019
3020 /* PREFIX_0F7D */
3021 {
3022 { Bad_Opcode },
3023 { Bad_Opcode },
3024 { "hsubpd", { XM, EXx } },
3025 { "hsubps", { XM, EXx } },
3026 },
3027
3028 /* PREFIX_0F7E */
3029 {
3030 { "movK", { Edq, MX } },
3031 { "movq", { XM, EXq } },
3032 { "movK", { Edq, XM } },
3033 },
3034
3035 /* PREFIX_0F7F */
3036 {
3037 { "movq", { EMS, MX } },
3038 { "movdqu", { EXxS, XM } },
3039 { "movdqa", { EXxS, XM } },
3040 },
3041
3042 /* PREFIX_0FAE_REG_0 */
3043 {
3044 { Bad_Opcode },
3045 { "rdfsbase", { Ev } },
3046 },
3047
3048 /* PREFIX_0FAE_REG_1 */
3049 {
3050 { Bad_Opcode },
3051 { "rdgsbase", { Ev } },
3052 },
3053
3054 /* PREFIX_0FAE_REG_2 */
3055 {
3056 { Bad_Opcode },
3057 { "wrfsbase", { Ev } },
3058 },
3059
3060 /* PREFIX_0FAE_REG_3 */
3061 {
3062 { Bad_Opcode },
3063 { "wrgsbase", { Ev } },
3064 },
3065
3066 /* PREFIX_0FB8 */
3067 {
3068 { Bad_Opcode },
3069 { "popcntS", { Gv, Ev } },
3070 },
3071
3072 /* PREFIX_0FBD */
3073 {
3074 { "bsrS", { Gv, Ev } },
3075 { "lzcntS", { Gv, Ev } },
3076 { "bsrS", { Gv, Ev } },
3077 },
3078
3079 /* PREFIX_0FC2 */
3080 {
3081 { "cmpps", { XM, EXx, CMP } },
3082 { "cmpss", { XM, EXd, CMP } },
3083 { "cmppd", { XM, EXx, CMP } },
3084 { "cmpsd", { XM, EXq, CMP } },
3085 },
3086
3087 /* PREFIX_0FC3 */
3088 {
3089 { "movntiS", { Ma, Gv } },
3090 },
3091
3092 /* PREFIX_0FC7_REG_6 */
3093 {
3094 { "vmptrld",{ Mq } },
3095 { "vmxon", { Mq } },
3096 { "vmclear",{ Mq } },
3097 },
3098
3099 /* PREFIX_0FD0 */
3100 {
3101 { Bad_Opcode },
3102 { Bad_Opcode },
3103 { "addsubpd", { XM, EXx } },
3104 { "addsubps", { XM, EXx } },
3105 },
3106
3107 /* PREFIX_0FD6 */
3108 {
3109 { Bad_Opcode },
3110 { "movq2dq",{ XM, MS } },
3111 { "movq", { EXqS, XM } },
3112 { "movdq2q",{ MX, XS } },
3113 },
3114
3115 /* PREFIX_0FE6 */
3116 {
3117 { Bad_Opcode },
3118 { "cvtdq2pd", { XM, EXq } },
3119 { "cvttpd2dq", { XM, EXx } },
3120 { "cvtpd2dq", { XM, EXx } },
3121 },
3122
3123 /* PREFIX_0FE7 */
3124 {
3125 { "movntq", { Mq, MX } },
3126 { Bad_Opcode },
3127 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3128 },
3129
3130 /* PREFIX_0FF0 */
3131 {
3132 { Bad_Opcode },
3133 { Bad_Opcode },
3134 { Bad_Opcode },
3135 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3136 },
3137
3138 /* PREFIX_0FF7 */
3139 {
3140 { "maskmovq", { MX, MS } },
3141 { Bad_Opcode },
3142 { "maskmovdqu", { XM, XS } },
3143 },
3144
3145 /* PREFIX_0F3810 */
3146 {
3147 { Bad_Opcode },
3148 { Bad_Opcode },
3149 { "pblendvb", { XM, EXx, XMM0 } },
3150 },
3151
3152 /* PREFIX_0F3814 */
3153 {
3154 { Bad_Opcode },
3155 { Bad_Opcode },
3156 { "blendvps", { XM, EXx, XMM0 } },
3157 },
3158
3159 /* PREFIX_0F3815 */
3160 {
3161 { Bad_Opcode },
3162 { Bad_Opcode },
3163 { "blendvpd", { XM, EXx, XMM0 } },
3164 },
3165
3166 /* PREFIX_0F3817 */
3167 {
3168 { Bad_Opcode },
3169 { Bad_Opcode },
3170 { "ptest", { XM, EXx } },
3171 },
3172
3173 /* PREFIX_0F3820 */
3174 {
3175 { Bad_Opcode },
3176 { Bad_Opcode },
3177 { "pmovsxbw", { XM, EXq } },
3178 },
3179
3180 /* PREFIX_0F3821 */
3181 {
3182 { Bad_Opcode },
3183 { Bad_Opcode },
3184 { "pmovsxbd", { XM, EXd } },
3185 },
3186
3187 /* PREFIX_0F3822 */
3188 {
3189 { Bad_Opcode },
3190 { Bad_Opcode },
3191 { "pmovsxbq", { XM, EXw } },
3192 },
3193
3194 /* PREFIX_0F3823 */
3195 {
3196 { Bad_Opcode },
3197 { Bad_Opcode },
3198 { "pmovsxwd", { XM, EXq } },
3199 },
3200
3201 /* PREFIX_0F3824 */
3202 {
3203 { Bad_Opcode },
3204 { Bad_Opcode },
3205 { "pmovsxwq", { XM, EXd } },
3206 },
3207
3208 /* PREFIX_0F3825 */
3209 {
3210 { Bad_Opcode },
3211 { Bad_Opcode },
3212 { "pmovsxdq", { XM, EXq } },
3213 },
3214
3215 /* PREFIX_0F3828 */
3216 {
3217 { Bad_Opcode },
3218 { Bad_Opcode },
3219 { "pmuldq", { XM, EXx } },
3220 },
3221
3222 /* PREFIX_0F3829 */
3223 {
3224 { Bad_Opcode },
3225 { Bad_Opcode },
3226 { "pcmpeqq", { XM, EXx } },
3227 },
3228
3229 /* PREFIX_0F382A */
3230 {
3231 { Bad_Opcode },
3232 { Bad_Opcode },
3233 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3234 },
3235
3236 /* PREFIX_0F382B */
3237 {
3238 { Bad_Opcode },
3239 { Bad_Opcode },
3240 { "packusdw", { XM, EXx } },
3241 },
3242
3243 /* PREFIX_0F3830 */
3244 {
3245 { Bad_Opcode },
3246 { Bad_Opcode },
3247 { "pmovzxbw", { XM, EXq } },
3248 },
3249
3250 /* PREFIX_0F3831 */
3251 {
3252 { Bad_Opcode },
3253 { Bad_Opcode },
3254 { "pmovzxbd", { XM, EXd } },
3255 },
3256
3257 /* PREFIX_0F3832 */
3258 {
3259 { Bad_Opcode },
3260 { Bad_Opcode },
3261 { "pmovzxbq", { XM, EXw } },
3262 },
3263
3264 /* PREFIX_0F3833 */
3265 {
3266 { Bad_Opcode },
3267 { Bad_Opcode },
3268 { "pmovzxwd", { XM, EXq } },
3269 },
3270
3271 /* PREFIX_0F3834 */
3272 {
3273 { Bad_Opcode },
3274 { Bad_Opcode },
3275 { "pmovzxwq", { XM, EXd } },
3276 },
3277
3278 /* PREFIX_0F3835 */
3279 {
3280 { Bad_Opcode },
3281 { Bad_Opcode },
3282 { "pmovzxdq", { XM, EXq } },
3283 },
3284
3285 /* PREFIX_0F3837 */
3286 {
3287 { Bad_Opcode },
3288 { Bad_Opcode },
3289 { "pcmpgtq", { XM, EXx } },
3290 },
3291
3292 /* PREFIX_0F3838 */
3293 {
3294 { Bad_Opcode },
3295 { Bad_Opcode },
3296 { "pminsb", { XM, EXx } },
3297 },
3298
3299 /* PREFIX_0F3839 */
3300 {
3301 { Bad_Opcode },
3302 { Bad_Opcode },
3303 { "pminsd", { XM, EXx } },
3304 },
3305
3306 /* PREFIX_0F383A */
3307 {
3308 { Bad_Opcode },
3309 { Bad_Opcode },
3310 { "pminuw", { XM, EXx } },
3311 },
3312
3313 /* PREFIX_0F383B */
3314 {
3315 { Bad_Opcode },
3316 { Bad_Opcode },
3317 { "pminud", { XM, EXx } },
3318 },
3319
3320 /* PREFIX_0F383C */
3321 {
3322 { Bad_Opcode },
3323 { Bad_Opcode },
3324 { "pmaxsb", { XM, EXx } },
3325 },
3326
3327 /* PREFIX_0F383D */
3328 {
3329 { Bad_Opcode },
3330 { Bad_Opcode },
3331 { "pmaxsd", { XM, EXx } },
3332 },
3333
3334 /* PREFIX_0F383E */
3335 {
3336 { Bad_Opcode },
3337 { Bad_Opcode },
3338 { "pmaxuw", { XM, EXx } },
3339 },
3340
3341 /* PREFIX_0F383F */
3342 {
3343 { Bad_Opcode },
3344 { Bad_Opcode },
3345 { "pmaxud", { XM, EXx } },
3346 },
3347
3348 /* PREFIX_0F3840 */
3349 {
3350 { Bad_Opcode },
3351 { Bad_Opcode },
3352 { "pmulld", { XM, EXx } },
3353 },
3354
3355 /* PREFIX_0F3841 */
3356 {
3357 { Bad_Opcode },
3358 { Bad_Opcode },
3359 { "phminposuw", { XM, EXx } },
3360 },
3361
3362 /* PREFIX_0F3880 */
3363 {
3364 { Bad_Opcode },
3365 { Bad_Opcode },
3366 { "invept", { Gm, Mo } },
3367 },
3368
3369 /* PREFIX_0F3881 */
3370 {
3371 { Bad_Opcode },
3372 { Bad_Opcode },
3373 { "invvpid", { Gm, Mo } },
3374 },
3375
3376 /* PREFIX_0F38DB */
3377 {
3378 { Bad_Opcode },
3379 { Bad_Opcode },
3380 { "aesimc", { XM, EXx } },
3381 },
3382
3383 /* PREFIX_0F38DC */
3384 {
3385 { Bad_Opcode },
3386 { Bad_Opcode },
3387 { "aesenc", { XM, EXx } },
3388 },
3389
3390 /* PREFIX_0F38DD */
3391 {
3392 { Bad_Opcode },
3393 { Bad_Opcode },
3394 { "aesenclast", { XM, EXx } },
3395 },
3396
3397 /* PREFIX_0F38DE */
3398 {
3399 { Bad_Opcode },
3400 { Bad_Opcode },
3401 { "aesdec", { XM, EXx } },
3402 },
3403
3404 /* PREFIX_0F38DF */
3405 {
3406 { Bad_Opcode },
3407 { Bad_Opcode },
3408 { "aesdeclast", { XM, EXx } },
3409 },
3410
3411 /* PREFIX_0F38F0 */
3412 {
3413 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3414 { Bad_Opcode },
3415 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3416 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3417 },
3418
3419 /* PREFIX_0F38F1 */
3420 {
3421 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3422 { Bad_Opcode },
3423 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3424 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3425 },
3426
3427 /* PREFIX_0F3A08 */
3428 {
3429 { Bad_Opcode },
3430 { Bad_Opcode },
3431 { "roundps", { XM, EXx, Ib } },
3432 },
3433
3434 /* PREFIX_0F3A09 */
3435 {
3436 { Bad_Opcode },
3437 { Bad_Opcode },
3438 { "roundpd", { XM, EXx, Ib } },
3439 },
3440
3441 /* PREFIX_0F3A0A */
3442 {
3443 { Bad_Opcode },
3444 { Bad_Opcode },
3445 { "roundss", { XM, EXd, Ib } },
3446 },
3447
3448 /* PREFIX_0F3A0B */
3449 {
3450 { Bad_Opcode },
3451 { Bad_Opcode },
3452 { "roundsd", { XM, EXq, Ib } },
3453 },
3454
3455 /* PREFIX_0F3A0C */
3456 {
3457 { Bad_Opcode },
3458 { Bad_Opcode },
3459 { "blendps", { XM, EXx, Ib } },
3460 },
3461
3462 /* PREFIX_0F3A0D */
3463 {
3464 { Bad_Opcode },
3465 { Bad_Opcode },
3466 { "blendpd", { XM, EXx, Ib } },
3467 },
3468
3469 /* PREFIX_0F3A0E */
3470 {
3471 { Bad_Opcode },
3472 { Bad_Opcode },
3473 { "pblendw", { XM, EXx, Ib } },
3474 },
3475
3476 /* PREFIX_0F3A14 */
3477 {
3478 { Bad_Opcode },
3479 { Bad_Opcode },
3480 { "pextrb", { Edqb, XM, Ib } },
3481 },
3482
3483 /* PREFIX_0F3A15 */
3484 {
3485 { Bad_Opcode },
3486 { Bad_Opcode },
3487 { "pextrw", { Edqw, XM, Ib } },
3488 },
3489
3490 /* PREFIX_0F3A16 */
3491 {
3492 { Bad_Opcode },
3493 { Bad_Opcode },
3494 { "pextrK", { Edq, XM, Ib } },
3495 },
3496
3497 /* PREFIX_0F3A17 */
3498 {
3499 { Bad_Opcode },
3500 { Bad_Opcode },
3501 { "extractps", { Edqd, XM, Ib } },
3502 },
3503
3504 /* PREFIX_0F3A20 */
3505 {
3506 { Bad_Opcode },
3507 { Bad_Opcode },
3508 { "pinsrb", { XM, Edqb, Ib } },
3509 },
3510
3511 /* PREFIX_0F3A21 */
3512 {
3513 { Bad_Opcode },
3514 { Bad_Opcode },
3515 { "insertps", { XM, EXd, Ib } },
3516 },
3517
3518 /* PREFIX_0F3A22 */
3519 {
3520 { Bad_Opcode },
3521 { Bad_Opcode },
3522 { "pinsrK", { XM, Edq, Ib } },
3523 },
3524
3525 /* PREFIX_0F3A40 */
3526 {
3527 { Bad_Opcode },
3528 { Bad_Opcode },
3529 { "dpps", { XM, EXx, Ib } },
3530 },
3531
3532 /* PREFIX_0F3A41 */
3533 {
3534 { Bad_Opcode },
3535 { Bad_Opcode },
3536 { "dppd", { XM, EXx, Ib } },
3537 },
3538
3539 /* PREFIX_0F3A42 */
3540 {
3541 { Bad_Opcode },
3542 { Bad_Opcode },
3543 { "mpsadbw", { XM, EXx, Ib } },
3544 },
3545
3546 /* PREFIX_0F3A44 */
3547 {
3548 { Bad_Opcode },
3549 { Bad_Opcode },
3550 { "pclmulqdq", { XM, EXx, PCLMUL } },
3551 },
3552
3553 /* PREFIX_0F3A60 */
3554 {
3555 { Bad_Opcode },
3556 { Bad_Opcode },
3557 { "pcmpestrm", { XM, EXx, Ib } },
3558 },
3559
3560 /* PREFIX_0F3A61 */
3561 {
3562 { Bad_Opcode },
3563 { Bad_Opcode },
3564 { "pcmpestri", { XM, EXx, Ib } },
3565 },
3566
3567 /* PREFIX_0F3A62 */
3568 {
3569 { Bad_Opcode },
3570 { Bad_Opcode },
3571 { "pcmpistrm", { XM, EXx, Ib } },
3572 },
3573
3574 /* PREFIX_0F3A63 */
3575 {
3576 { Bad_Opcode },
3577 { Bad_Opcode },
3578 { "pcmpistri", { XM, EXx, Ib } },
3579 },
3580
3581 /* PREFIX_0F3ADF */
3582 {
3583 { Bad_Opcode },
3584 { Bad_Opcode },
3585 { "aeskeygenassist", { XM, EXx, Ib } },
3586 },
3587
3588 /* PREFIX_VEX_10 */
3589 {
3590 { VEX_W_TABLE (VEX_W_10_P_0) },
3591 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3592 { VEX_W_TABLE (VEX_W_10_P_2) },
3593 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3594 },
3595
3596 /* PREFIX_VEX_11 */
3597 {
3598 { VEX_W_TABLE (VEX_W_11_P_0) },
3599 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3600 { VEX_W_TABLE (VEX_W_11_P_2) },
3601 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3602 },
3603
3604 /* PREFIX_VEX_12 */
3605 {
3606 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3607 { VEX_W_TABLE (VEX_W_12_P_1) },
3608 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3609 { VEX_W_TABLE (VEX_W_12_P_3) },
3610 },
3611
3612 /* PREFIX_VEX_16 */
3613 {
3614 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3615 { VEX_W_TABLE (VEX_W_16_P_1) },
3616 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3617 },
3618
3619 /* PREFIX_VEX_2A */
3620 {
3621 { Bad_Opcode },
3622 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3623 { Bad_Opcode },
3624 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3625 },
3626
3627 /* PREFIX_VEX_2C */
3628 {
3629 { Bad_Opcode },
3630 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3631 { Bad_Opcode },
3632 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3633 },
3634
3635 /* PREFIX_VEX_2D */
3636 {
3637 { Bad_Opcode },
3638 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3639 { Bad_Opcode },
3640 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3641 },
3642
3643 /* PREFIX_VEX_2E */
3644 {
3645 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3646 { Bad_Opcode },
3647 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3648 },
3649
3650 /* PREFIX_VEX_2F */
3651 {
3652 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3653 { Bad_Opcode },
3654 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3655 },
3656
3657 /* PREFIX_VEX_51 */
3658 {
3659 { VEX_W_TABLE (VEX_W_51_P_0) },
3660 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3661 { VEX_W_TABLE (VEX_W_51_P_2) },
3662 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3663 },
3664
3665 /* PREFIX_VEX_52 */
3666 {
3667 { VEX_W_TABLE (VEX_W_52_P_0) },
3668 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3669 },
3670
3671 /* PREFIX_VEX_53 */
3672 {
3673 { VEX_W_TABLE (VEX_W_53_P_0) },
3674 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3675 },
3676
3677 /* PREFIX_VEX_58 */
3678 {
3679 { VEX_W_TABLE (VEX_W_58_P_0) },
3680 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3681 { VEX_W_TABLE (VEX_W_58_P_2) },
3682 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3683 },
3684
3685 /* PREFIX_VEX_59 */
3686 {
3687 { VEX_W_TABLE (VEX_W_59_P_0) },
3688 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3689 { VEX_W_TABLE (VEX_W_59_P_2) },
3690 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3691 },
3692
3693 /* PREFIX_VEX_5A */
3694 {
3695 { VEX_W_TABLE (VEX_W_5A_P_0) },
3696 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3697 { "vcvtpd2ps%XY", { XMM, EXx } },
3698 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3699 },
3700
3701 /* PREFIX_VEX_5B */
3702 {
3703 { VEX_W_TABLE (VEX_W_5B_P_0) },
3704 { VEX_W_TABLE (VEX_W_5B_P_1) },
3705 { VEX_W_TABLE (VEX_W_5B_P_2) },
3706 },
3707
3708 /* PREFIX_VEX_5C */
3709 {
3710 { VEX_W_TABLE (VEX_W_5C_P_0) },
3711 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3712 { VEX_W_TABLE (VEX_W_5C_P_2) },
3713 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3714 },
3715
3716 /* PREFIX_VEX_5D */
3717 {
3718 { VEX_W_TABLE (VEX_W_5D_P_0) },
3719 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3720 { VEX_W_TABLE (VEX_W_5D_P_2) },
3721 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3722 },
3723
3724 /* PREFIX_VEX_5E */
3725 {
3726 { VEX_W_TABLE (VEX_W_5E_P_0) },
3727 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3728 { VEX_W_TABLE (VEX_W_5E_P_2) },
3729 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3730 },
3731
3732 /* PREFIX_VEX_5F */
3733 {
3734 { VEX_W_TABLE (VEX_W_5F_P_0) },
3735 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3736 { VEX_W_TABLE (VEX_W_5F_P_2) },
3737 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3738 },
3739
3740 /* PREFIX_VEX_60 */
3741 {
3742 { Bad_Opcode },
3743 { Bad_Opcode },
3744 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3745 },
3746
3747 /* PREFIX_VEX_61 */
3748 {
3749 { Bad_Opcode },
3750 { Bad_Opcode },
3751 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3752 },
3753
3754 /* PREFIX_VEX_62 */
3755 {
3756 { Bad_Opcode },
3757 { Bad_Opcode },
3758 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3759 },
3760
3761 /* PREFIX_VEX_63 */
3762 {
3763 { Bad_Opcode },
3764 { Bad_Opcode },
3765 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3766 },
3767
3768 /* PREFIX_VEX_64 */
3769 {
3770 { Bad_Opcode },
3771 { Bad_Opcode },
3772 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3773 },
3774
3775 /* PREFIX_VEX_65 */
3776 {
3777 { Bad_Opcode },
3778 { Bad_Opcode },
3779 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3780 },
3781
3782 /* PREFIX_VEX_66 */
3783 {
3784 { Bad_Opcode },
3785 { Bad_Opcode },
3786 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3787 },
3788
3789 /* PREFIX_VEX_67 */
3790 {
3791 { Bad_Opcode },
3792 { Bad_Opcode },
3793 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3794 },
3795
3796 /* PREFIX_VEX_68 */
3797 {
3798 { Bad_Opcode },
3799 { Bad_Opcode },
3800 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3801 },
3802
3803 /* PREFIX_VEX_69 */
3804 {
3805 { Bad_Opcode },
3806 { Bad_Opcode },
3807 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3808 },
3809
3810 /* PREFIX_VEX_6A */
3811 {
3812 { Bad_Opcode },
3813 { Bad_Opcode },
3814 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3815 },
3816
3817 /* PREFIX_VEX_6B */
3818 {
3819 { Bad_Opcode },
3820 { Bad_Opcode },
3821 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3822 },
3823
3824 /* PREFIX_VEX_6C */
3825 {
3826 { Bad_Opcode },
3827 { Bad_Opcode },
3828 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3829 },
3830
3831 /* PREFIX_VEX_6D */
3832 {
3833 { Bad_Opcode },
3834 { Bad_Opcode },
3835 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3836 },
3837
3838 /* PREFIX_VEX_6E */
3839 {
3840 { Bad_Opcode },
3841 { Bad_Opcode },
3842 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3843 },
3844
3845 /* PREFIX_VEX_6F */
3846 {
3847 { Bad_Opcode },
3848 { VEX_W_TABLE (VEX_W_6F_P_1) },
3849 { VEX_W_TABLE (VEX_W_6F_P_2) },
3850 },
3851
3852 /* PREFIX_VEX_70 */
3853 {
3854 { Bad_Opcode },
3855 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3856 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3857 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3858 },
3859
3860 /* PREFIX_VEX_71_REG_2 */
3861 {
3862 { Bad_Opcode },
3863 { Bad_Opcode },
3864 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3865 },
3866
3867 /* PREFIX_VEX_71_REG_4 */
3868 {
3869 { Bad_Opcode },
3870 { Bad_Opcode },
3871 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3872 },
3873
3874 /* PREFIX_VEX_71_REG_6 */
3875 {
3876 { Bad_Opcode },
3877 { Bad_Opcode },
3878 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3879 },
3880
3881 /* PREFIX_VEX_72_REG_2 */
3882 {
3883 { Bad_Opcode },
3884 { Bad_Opcode },
3885 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3886 },
3887
3888 /* PREFIX_VEX_72_REG_4 */
3889 {
3890 { Bad_Opcode },
3891 { Bad_Opcode },
3892 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3893 },
3894
3895 /* PREFIX_VEX_72_REG_6 */
3896 {
3897 { Bad_Opcode },
3898 { Bad_Opcode },
3899 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3900 },
3901
3902 /* PREFIX_VEX_73_REG_2 */
3903 {
3904 { Bad_Opcode },
3905 { Bad_Opcode },
3906 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3907 },
3908
3909 /* PREFIX_VEX_73_REG_3 */
3910 {
3911 { Bad_Opcode },
3912 { Bad_Opcode },
3913 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3914 },
3915
3916 /* PREFIX_VEX_73_REG_6 */
3917 {
3918 { Bad_Opcode },
3919 { Bad_Opcode },
3920 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3921 },
3922
3923 /* PREFIX_VEX_73_REG_7 */
3924 {
3925 { Bad_Opcode },
3926 { Bad_Opcode },
3927 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3928 },
3929
3930 /* PREFIX_VEX_74 */
3931 {
3932 { Bad_Opcode },
3933 { Bad_Opcode },
3934 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3935 },
3936
3937 /* PREFIX_VEX_75 */
3938 {
3939 { Bad_Opcode },
3940 { Bad_Opcode },
3941 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3942 },
3943
3944 /* PREFIX_VEX_76 */
3945 {
3946 { Bad_Opcode },
3947 { Bad_Opcode },
3948 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3949 },
3950
3951 /* PREFIX_VEX_77 */
3952 {
3953 { VEX_W_TABLE (VEX_W_77_P_0) },
3954 },
3955
3956 /* PREFIX_VEX_7C */
3957 {
3958 { Bad_Opcode },
3959 { Bad_Opcode },
3960 { VEX_W_TABLE (VEX_W_7C_P_2) },
3961 { VEX_W_TABLE (VEX_W_7C_P_3) },
3962 },
3963
3964 /* PREFIX_VEX_7D */
3965 {
3966 { Bad_Opcode },
3967 { Bad_Opcode },
3968 { VEX_W_TABLE (VEX_W_7D_P_2) },
3969 { VEX_W_TABLE (VEX_W_7D_P_3) },
3970 },
3971
3972 /* PREFIX_VEX_7E */
3973 {
3974 { Bad_Opcode },
3975 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3976 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3977 },
3978
3979 /* PREFIX_VEX_7F */
3980 {
3981 { Bad_Opcode },
3982 { VEX_W_TABLE (VEX_W_7F_P_1) },
3983 { VEX_W_TABLE (VEX_W_7F_P_2) },
3984 },
3985
3986 /* PREFIX_VEX_C2 */
3987 {
3988 { VEX_W_TABLE (VEX_W_C2_P_0) },
3989 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3990 { VEX_W_TABLE (VEX_W_C2_P_2) },
3991 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3992 },
3993
3994 /* PREFIX_VEX_C4 */
3995 {
3996 { Bad_Opcode },
3997 { Bad_Opcode },
3998 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3999 },
4000
4001 /* PREFIX_VEX_C5 */
4002 {
4003 { Bad_Opcode },
4004 { Bad_Opcode },
4005 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
4006 },
4007
4008 /* PREFIX_VEX_D0 */
4009 {
4010 { Bad_Opcode },
4011 { Bad_Opcode },
4012 { VEX_W_TABLE (VEX_W_D0_P_2) },
4013 { VEX_W_TABLE (VEX_W_D0_P_3) },
4014 },
4015
4016 /* PREFIX_VEX_D1 */
4017 {
4018 { Bad_Opcode },
4019 { Bad_Opcode },
4020 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
4021 },
4022
4023 /* PREFIX_VEX_D2 */
4024 {
4025 { Bad_Opcode },
4026 { Bad_Opcode },
4027 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
4028 },
4029
4030 /* PREFIX_VEX_D3 */
4031 {
4032 { Bad_Opcode },
4033 { Bad_Opcode },
4034 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
4035 },
4036
4037 /* PREFIX_VEX_D4 */
4038 {
4039 { Bad_Opcode },
4040 { Bad_Opcode },
4041 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
4042 },
4043
4044 /* PREFIX_VEX_D5 */
4045 {
4046 { Bad_Opcode },
4047 { Bad_Opcode },
4048 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
4049 },
4050
4051 /* PREFIX_VEX_D6 */
4052 {
4053 { Bad_Opcode },
4054 { Bad_Opcode },
4055 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
4056 },
4057
4058 /* PREFIX_VEX_D7 */
4059 {
4060 { Bad_Opcode },
4061 { Bad_Opcode },
4062 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
4063 },
4064
4065 /* PREFIX_VEX_D8 */
4066 {
4067 { Bad_Opcode },
4068 { Bad_Opcode },
4069 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
4070 },
4071
4072 /* PREFIX_VEX_D9 */
4073 {
4074 { Bad_Opcode },
4075 { Bad_Opcode },
4076 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
4077 },
4078
4079 /* PREFIX_VEX_DA */
4080 {
4081 { Bad_Opcode },
4082 { Bad_Opcode },
4083 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
4084 },
4085
4086 /* PREFIX_VEX_DB */
4087 {
4088 { Bad_Opcode },
4089 { Bad_Opcode },
4090 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
4091 },
4092
4093 /* PREFIX_VEX_DC */
4094 {
4095 { Bad_Opcode },
4096 { Bad_Opcode },
4097 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
4098 },
4099
4100 /* PREFIX_VEX_DD */
4101 {
4102 { Bad_Opcode },
4103 { Bad_Opcode },
4104 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
4105 },
4106
4107 /* PREFIX_VEX_DE */
4108 {
4109 { Bad_Opcode },
4110 { Bad_Opcode },
4111 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
4112 },
4113
4114 /* PREFIX_VEX_DF */
4115 {
4116 { Bad_Opcode },
4117 { Bad_Opcode },
4118 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
4119 },
4120
4121 /* PREFIX_VEX_E0 */
4122 {
4123 { Bad_Opcode },
4124 { Bad_Opcode },
4125 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
4126 },
4127
4128 /* PREFIX_VEX_E1 */
4129 {
4130 { Bad_Opcode },
4131 { Bad_Opcode },
4132 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
4133 },
4134
4135 /* PREFIX_VEX_E2 */
4136 {
4137 { Bad_Opcode },
4138 { Bad_Opcode },
4139 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
4140 },
4141
4142 /* PREFIX_VEX_E3 */
4143 {
4144 { Bad_Opcode },
4145 { Bad_Opcode },
4146 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
4147 },
4148
4149 /* PREFIX_VEX_E4 */
4150 {
4151 { Bad_Opcode },
4152 { Bad_Opcode },
4153 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
4154 },
4155
4156 /* PREFIX_VEX_E5 */
4157 {
4158 { Bad_Opcode },
4159 { Bad_Opcode },
4160 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4161 },
4162
4163 /* PREFIX_VEX_E6 */
4164 {
4165 { Bad_Opcode },
4166 { VEX_W_TABLE (VEX_W_E6_P_1) },
4167 { VEX_W_TABLE (VEX_W_E6_P_2) },
4168 { VEX_W_TABLE (VEX_W_E6_P_3) },
4169 },
4170
4171 /* PREFIX_VEX_E7 */
4172 {
4173 { Bad_Opcode },
4174 { Bad_Opcode },
4175 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4176 },
4177
4178 /* PREFIX_VEX_E8 */
4179 {
4180 { Bad_Opcode },
4181 { Bad_Opcode },
4182 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4183 },
4184
4185 /* PREFIX_VEX_E9 */
4186 {
4187 { Bad_Opcode },
4188 { Bad_Opcode },
4189 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4190 },
4191
4192 /* PREFIX_VEX_EA */
4193 {
4194 { Bad_Opcode },
4195 { Bad_Opcode },
4196 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4197 },
4198
4199 /* PREFIX_VEX_EB */
4200 {
4201 { Bad_Opcode },
4202 { Bad_Opcode },
4203 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4204 },
4205
4206 /* PREFIX_VEX_EC */
4207 {
4208 { Bad_Opcode },
4209 { Bad_Opcode },
4210 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4211 },
4212
4213 /* PREFIX_VEX_ED */
4214 {
4215 { Bad_Opcode },
4216 { Bad_Opcode },
4217 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4218 },
4219
4220 /* PREFIX_VEX_EE */
4221 {
4222 { Bad_Opcode },
4223 { Bad_Opcode },
4224 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4225 },
4226
4227 /* PREFIX_VEX_EF */
4228 {
4229 { Bad_Opcode },
4230 { Bad_Opcode },
4231 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4232 },
4233
4234 /* PREFIX_VEX_F0 */
4235 {
4236 { Bad_Opcode },
4237 { Bad_Opcode },
4238 { Bad_Opcode },
4239 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4240 },
4241
4242 /* PREFIX_VEX_F1 */
4243 {
4244 { Bad_Opcode },
4245 { Bad_Opcode },
4246 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4247 },
4248
4249 /* PREFIX_VEX_F2 */
4250 {
4251 { Bad_Opcode },
4252 { Bad_Opcode },
4253 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4254 },
4255
4256 /* PREFIX_VEX_F3 */
4257 {
4258 { Bad_Opcode },
4259 { Bad_Opcode },
4260 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4261 },
4262
4263 /* PREFIX_VEX_F4 */
4264 {
4265 { Bad_Opcode },
4266 { Bad_Opcode },
4267 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4268 },
4269
4270 /* PREFIX_VEX_F5 */
4271 {
4272 { Bad_Opcode },
4273 { Bad_Opcode },
4274 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4275 },
4276
4277 /* PREFIX_VEX_F6 */
4278 {
4279 { Bad_Opcode },
4280 { Bad_Opcode },
4281 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4282 },
4283
4284 /* PREFIX_VEX_F7 */
4285 {
4286 { Bad_Opcode },
4287 { Bad_Opcode },
4288 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4289 },
4290
4291 /* PREFIX_VEX_F8 */
4292 {
4293 { Bad_Opcode },
4294 { Bad_Opcode },
4295 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4296 },
4297
4298 /* PREFIX_VEX_F9 */
4299 {
4300 { Bad_Opcode },
4301 { Bad_Opcode },
4302 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4303 },
4304
4305 /* PREFIX_VEX_FA */
4306 {
4307 { Bad_Opcode },
4308 { Bad_Opcode },
4309 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4310 },
4311
4312 /* PREFIX_VEX_FB */
4313 {
4314 { Bad_Opcode },
4315 { Bad_Opcode },
4316 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4317 },
4318
4319 /* PREFIX_VEX_FC */
4320 {
4321 { Bad_Opcode },
4322 { Bad_Opcode },
4323 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4324 },
4325
4326 /* PREFIX_VEX_FD */
4327 {
4328 { Bad_Opcode },
4329 { Bad_Opcode },
4330 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4331 },
4332
4333 /* PREFIX_VEX_FE */
4334 {
4335 { Bad_Opcode },
4336 { Bad_Opcode },
4337 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4338 },
4339
4340 /* PREFIX_VEX_3800 */
4341 {
4342 { Bad_Opcode },
4343 { Bad_Opcode },
4344 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4345 },
4346
4347 /* PREFIX_VEX_3801 */
4348 {
4349 { Bad_Opcode },
4350 { Bad_Opcode },
4351 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4352 },
4353
4354 /* PREFIX_VEX_3802 */
4355 {
4356 { Bad_Opcode },
4357 { Bad_Opcode },
4358 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4359 },
4360
4361 /* PREFIX_VEX_3803 */
4362 {
4363 { Bad_Opcode },
4364 { Bad_Opcode },
4365 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4366 },
4367
4368 /* PREFIX_VEX_3804 */
4369 {
4370 { Bad_Opcode },
4371 { Bad_Opcode },
4372 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4373 },
4374
4375 /* PREFIX_VEX_3805 */
4376 {
4377 { Bad_Opcode },
4378 { Bad_Opcode },
4379 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4380 },
4381
4382 /* PREFIX_VEX_3806 */
4383 {
4384 { Bad_Opcode },
4385 { Bad_Opcode },
4386 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4387 },
4388
4389 /* PREFIX_VEX_3807 */
4390 {
4391 { Bad_Opcode },
4392 { Bad_Opcode },
4393 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4394 },
4395
4396 /* PREFIX_VEX_3808 */
4397 {
4398 { Bad_Opcode },
4399 { Bad_Opcode },
4400 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4401 },
4402
4403 /* PREFIX_VEX_3809 */
4404 {
4405 { Bad_Opcode },
4406 { Bad_Opcode },
4407 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4408 },
4409
4410 /* PREFIX_VEX_380A */
4411 {
4412 { Bad_Opcode },
4413 { Bad_Opcode },
4414 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4415 },
4416
4417 /* PREFIX_VEX_380B */
4418 {
4419 { Bad_Opcode },
4420 { Bad_Opcode },
4421 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4422 },
4423
4424 /* PREFIX_VEX_380C */
4425 {
4426 { Bad_Opcode },
4427 { Bad_Opcode },
4428 { VEX_W_TABLE (VEX_W_380C_P_2) },
4429 },
4430
4431 /* PREFIX_VEX_380D */
4432 {
4433 { Bad_Opcode },
4434 { Bad_Opcode },
4435 { VEX_W_TABLE (VEX_W_380D_P_2) },
4436 },
4437
4438 /* PREFIX_VEX_380E */
4439 {
4440 { Bad_Opcode },
4441 { Bad_Opcode },
4442 { VEX_W_TABLE (VEX_W_380E_P_2) },
4443 },
4444
4445 /* PREFIX_VEX_380F */
4446 {
4447 { Bad_Opcode },
4448 { Bad_Opcode },
4449 { VEX_W_TABLE (VEX_W_380F_P_2) },
4450 },
4451
4452 /* PREFIX_VEX_3813 */
4453 {
4454 { Bad_Opcode },
4455 { Bad_Opcode },
4456 { "vcvtph2ps", { XM, EXxmmq } },
4457 },
4458
4459 /* PREFIX_VEX_3817 */
4460 {
4461 { Bad_Opcode },
4462 { Bad_Opcode },
4463 { VEX_W_TABLE (VEX_W_3817_P_2) },
4464 },
4465
4466 /* PREFIX_VEX_3818 */
4467 {
4468 { Bad_Opcode },
4469 { Bad_Opcode },
4470 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4471 },
4472
4473 /* PREFIX_VEX_3819 */
4474 {
4475 { Bad_Opcode },
4476 { Bad_Opcode },
4477 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4478 },
4479
4480 /* PREFIX_VEX_381A */
4481 {
4482 { Bad_Opcode },
4483 { Bad_Opcode },
4484 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4485 },
4486
4487 /* PREFIX_VEX_381C */
4488 {
4489 { Bad_Opcode },
4490 { Bad_Opcode },
4491 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4492 },
4493
4494 /* PREFIX_VEX_381D */
4495 {
4496 { Bad_Opcode },
4497 { Bad_Opcode },
4498 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4499 },
4500
4501 /* PREFIX_VEX_381E */
4502 {
4503 { Bad_Opcode },
4504 { Bad_Opcode },
4505 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4506 },
4507
4508 /* PREFIX_VEX_3820 */
4509 {
4510 { Bad_Opcode },
4511 { Bad_Opcode },
4512 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4513 },
4514
4515 /* PREFIX_VEX_3821 */
4516 {
4517 { Bad_Opcode },
4518 { Bad_Opcode },
4519 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4520 },
4521
4522 /* PREFIX_VEX_3822 */
4523 {
4524 { Bad_Opcode },
4525 { Bad_Opcode },
4526 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4527 },
4528
4529 /* PREFIX_VEX_3823 */
4530 {
4531 { Bad_Opcode },
4532 { Bad_Opcode },
4533 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4534 },
4535
4536 /* PREFIX_VEX_3824 */
4537 {
4538 { Bad_Opcode },
4539 { Bad_Opcode },
4540 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4541 },
4542
4543 /* PREFIX_VEX_3825 */
4544 {
4545 { Bad_Opcode },
4546 { Bad_Opcode },
4547 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4548 },
4549
4550 /* PREFIX_VEX_3828 */
4551 {
4552 { Bad_Opcode },
4553 { Bad_Opcode },
4554 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4555 },
4556
4557 /* PREFIX_VEX_3829 */
4558 {
4559 { Bad_Opcode },
4560 { Bad_Opcode },
4561 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4562 },
4563
4564 /* PREFIX_VEX_382A */
4565 {
4566 { Bad_Opcode },
4567 { Bad_Opcode },
4568 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4569 },
4570
4571 /* PREFIX_VEX_382B */
4572 {
4573 { Bad_Opcode },
4574 { Bad_Opcode },
4575 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4576 },
4577
4578 /* PREFIX_VEX_382C */
4579 {
4580 { Bad_Opcode },
4581 { Bad_Opcode },
4582 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4583 },
4584
4585 /* PREFIX_VEX_382D */
4586 {
4587 { Bad_Opcode },
4588 { Bad_Opcode },
4589 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4590 },
4591
4592 /* PREFIX_VEX_382E */
4593 {
4594 { Bad_Opcode },
4595 { Bad_Opcode },
4596 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4597 },
4598
4599 /* PREFIX_VEX_382F */
4600 {
4601 { Bad_Opcode },
4602 { Bad_Opcode },
4603 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4604 },
4605
4606 /* PREFIX_VEX_3830 */
4607 {
4608 { Bad_Opcode },
4609 { Bad_Opcode },
4610 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4611 },
4612
4613 /* PREFIX_VEX_3831 */
4614 {
4615 { Bad_Opcode },
4616 { Bad_Opcode },
4617 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4618 },
4619
4620 /* PREFIX_VEX_3832 */
4621 {
4622 { Bad_Opcode },
4623 { Bad_Opcode },
4624 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4625 },
4626
4627 /* PREFIX_VEX_3833 */
4628 {
4629 { Bad_Opcode },
4630 { Bad_Opcode },
4631 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4632 },
4633
4634 /* PREFIX_VEX_3834 */
4635 {
4636 { Bad_Opcode },
4637 { Bad_Opcode },
4638 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4639 },
4640
4641 /* PREFIX_VEX_3835 */
4642 {
4643 { Bad_Opcode },
4644 { Bad_Opcode },
4645 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4646 },
4647
4648 /* PREFIX_VEX_3837 */
4649 {
4650 { Bad_Opcode },
4651 { Bad_Opcode },
4652 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4653 },
4654
4655 /* PREFIX_VEX_3838 */
4656 {
4657 { Bad_Opcode },
4658 { Bad_Opcode },
4659 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4660 },
4661
4662 /* PREFIX_VEX_3839 */
4663 {
4664 { Bad_Opcode },
4665 { Bad_Opcode },
4666 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4667 },
4668
4669 /* PREFIX_VEX_383A */
4670 {
4671 { Bad_Opcode },
4672 { Bad_Opcode },
4673 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4674 },
4675
4676 /* PREFIX_VEX_383B */
4677 {
4678 { Bad_Opcode },
4679 { Bad_Opcode },
4680 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4681 },
4682
4683 /* PREFIX_VEX_383C */
4684 {
4685 { Bad_Opcode },
4686 { Bad_Opcode },
4687 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4688 },
4689
4690 /* PREFIX_VEX_383D */
4691 {
4692 { Bad_Opcode },
4693 { Bad_Opcode },
4694 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4695 },
4696
4697 /* PREFIX_VEX_383E */
4698 {
4699 { Bad_Opcode },
4700 { Bad_Opcode },
4701 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4702 },
4703
4704 /* PREFIX_VEX_383F */
4705 {
4706 { Bad_Opcode },
4707 { Bad_Opcode },
4708 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4709 },
4710
4711 /* PREFIX_VEX_3840 */
4712 {
4713 { Bad_Opcode },
4714 { Bad_Opcode },
4715 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4716 },
4717
4718 /* PREFIX_VEX_3841 */
4719 {
4720 { Bad_Opcode },
4721 { Bad_Opcode },
4722 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4723 },
4724
4725 /* PREFIX_VEX_3896 */
4726 {
4727 { Bad_Opcode },
4728 { Bad_Opcode },
4729 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4730 },
4731
4732 /* PREFIX_VEX_3897 */
4733 {
4734 { Bad_Opcode },
4735 { Bad_Opcode },
4736 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4737 },
4738
4739 /* PREFIX_VEX_3898 */
4740 {
4741 { Bad_Opcode },
4742 { Bad_Opcode },
4743 { "vfmadd132p%XW", { XM, Vex, EXx } },
4744 },
4745
4746 /* PREFIX_VEX_3899 */
4747 {
4748 { Bad_Opcode },
4749 { Bad_Opcode },
4750 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4751 },
4752
4753 /* PREFIX_VEX_389A */
4754 {
4755 { Bad_Opcode },
4756 { Bad_Opcode },
4757 { "vfmsub132p%XW", { XM, Vex, EXx } },
4758 },
4759
4760 /* PREFIX_VEX_389B */
4761 {
4762 { Bad_Opcode },
4763 { Bad_Opcode },
4764 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4765 },
4766
4767 /* PREFIX_VEX_389C */
4768 {
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { "vfnmadd132p%XW", { XM, Vex, EXx } },
4772 },
4773
4774 /* PREFIX_VEX_389D */
4775 {
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4779 },
4780
4781 /* PREFIX_VEX_389E */
4782 {
4783 { Bad_Opcode },
4784 { Bad_Opcode },
4785 { "vfnmsub132p%XW", { XM, Vex, EXx } },
4786 },
4787
4788 /* PREFIX_VEX_389F */
4789 {
4790 { Bad_Opcode },
4791 { Bad_Opcode },
4792 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4793 },
4794
4795 /* PREFIX_VEX_38A6 */
4796 {
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4800 { Bad_Opcode },
4801 },
4802
4803 /* PREFIX_VEX_38A7 */
4804 {
4805 { Bad_Opcode },
4806 { Bad_Opcode },
4807 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4808 },
4809
4810 /* PREFIX_VEX_38A8 */
4811 {
4812 { Bad_Opcode },
4813 { Bad_Opcode },
4814 { "vfmadd213p%XW", { XM, Vex, EXx } },
4815 },
4816
4817 /* PREFIX_VEX_38A9 */
4818 {
4819 { Bad_Opcode },
4820 { Bad_Opcode },
4821 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4822 },
4823
4824 /* PREFIX_VEX_38AA */
4825 {
4826 { Bad_Opcode },
4827 { Bad_Opcode },
4828 { "vfmsub213p%XW", { XM, Vex, EXx } },
4829 },
4830
4831 /* PREFIX_VEX_38AB */
4832 {
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4836 },
4837
4838 /* PREFIX_VEX_38AC */
4839 {
4840 { Bad_Opcode },
4841 { Bad_Opcode },
4842 { "vfnmadd213p%XW", { XM, Vex, EXx } },
4843 },
4844
4845 /* PREFIX_VEX_38AD */
4846 {
4847 { Bad_Opcode },
4848 { Bad_Opcode },
4849 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4850 },
4851
4852 /* PREFIX_VEX_38AE */
4853 {
4854 { Bad_Opcode },
4855 { Bad_Opcode },
4856 { "vfnmsub213p%XW", { XM, Vex, EXx } },
4857 },
4858
4859 /* PREFIX_VEX_38AF */
4860 {
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4864 },
4865
4866 /* PREFIX_VEX_38B6 */
4867 {
4868 { Bad_Opcode },
4869 { Bad_Opcode },
4870 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4871 },
4872
4873 /* PREFIX_VEX_38B7 */
4874 {
4875 { Bad_Opcode },
4876 { Bad_Opcode },
4877 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4878 },
4879
4880 /* PREFIX_VEX_38B8 */
4881 {
4882 { Bad_Opcode },
4883 { Bad_Opcode },
4884 { "vfmadd231p%XW", { XM, Vex, EXx } },
4885 },
4886
4887 /* PREFIX_VEX_38B9 */
4888 {
4889 { Bad_Opcode },
4890 { Bad_Opcode },
4891 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4892 },
4893
4894 /* PREFIX_VEX_38BA */
4895 {
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 { "vfmsub231p%XW", { XM, Vex, EXx } },
4899 },
4900
4901 /* PREFIX_VEX_38BB */
4902 {
4903 { Bad_Opcode },
4904 { Bad_Opcode },
4905 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4906 },
4907
4908 /* PREFIX_VEX_38BC */
4909 {
4910 { Bad_Opcode },
4911 { Bad_Opcode },
4912 { "vfnmadd231p%XW", { XM, Vex, EXx } },
4913 },
4914
4915 /* PREFIX_VEX_38BD */
4916 {
4917 { Bad_Opcode },
4918 { Bad_Opcode },
4919 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4920 },
4921
4922 /* PREFIX_VEX_38BE */
4923 {
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 { "vfnmsub231p%XW", { XM, Vex, EXx } },
4927 },
4928
4929 /* PREFIX_VEX_38BF */
4930 {
4931 { Bad_Opcode },
4932 { Bad_Opcode },
4933 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4934 },
4935
4936 /* PREFIX_VEX_38DB */
4937 {
4938 { Bad_Opcode },
4939 { Bad_Opcode },
4940 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4941 },
4942
4943 /* PREFIX_VEX_38DC */
4944 {
4945 { Bad_Opcode },
4946 { Bad_Opcode },
4947 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4948 },
4949
4950 /* PREFIX_VEX_38DD */
4951 {
4952 { Bad_Opcode },
4953 { Bad_Opcode },
4954 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4955 },
4956
4957 /* PREFIX_VEX_38DE */
4958 {
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4962 },
4963
4964 /* PREFIX_VEX_38DF */
4965 {
4966 { Bad_Opcode },
4967 { Bad_Opcode },
4968 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4969 },
4970
4971 /* PREFIX_VEX_3A04 */
4972 {
4973 { Bad_Opcode },
4974 { Bad_Opcode },
4975 { VEX_W_TABLE (VEX_W_3A04_P_2) },
4976 },
4977
4978 /* PREFIX_VEX_3A05 */
4979 {
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 { VEX_W_TABLE (VEX_W_3A05_P_2) },
4983 },
4984
4985 /* PREFIX_VEX_3A06 */
4986 {
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4990 },
4991
4992 /* PREFIX_VEX_3A08 */
4993 {
4994 { Bad_Opcode },
4995 { Bad_Opcode },
4996 { VEX_W_TABLE (VEX_W_3A08_P_2) },
4997 },
4998
4999 /* PREFIX_VEX_3A09 */
5000 {
5001 { Bad_Opcode },
5002 { Bad_Opcode },
5003 { VEX_W_TABLE (VEX_W_3A09_P_2) },
5004 },
5005
5006 /* PREFIX_VEX_3A0A */
5007 {
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
5011 },
5012
5013 /* PREFIX_VEX_3A0B */
5014 {
5015 { Bad_Opcode },
5016 { Bad_Opcode },
5017 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
5018 },
5019
5020 /* PREFIX_VEX_3A0C */
5021 {
5022 { Bad_Opcode },
5023 { Bad_Opcode },
5024 { VEX_W_TABLE (VEX_W_3A0C_P_2) },
5025 },
5026
5027 /* PREFIX_VEX_3A0D */
5028 {
5029 { Bad_Opcode },
5030 { Bad_Opcode },
5031 { VEX_W_TABLE (VEX_W_3A0D_P_2) },
5032 },
5033
5034 /* PREFIX_VEX_3A0E */
5035 {
5036 { Bad_Opcode },
5037 { Bad_Opcode },
5038 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
5039 },
5040
5041 /* PREFIX_VEX_3A0F */
5042 {
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
5046 },
5047
5048 /* PREFIX_VEX_3A14 */
5049 {
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5053 },
5054
5055 /* PREFIX_VEX_3A15 */
5056 {
5057 { Bad_Opcode },
5058 { Bad_Opcode },
5059 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5060 },
5061
5062 /* PREFIX_VEX_3A16 */
5063 {
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
5067 },
5068
5069 /* PREFIX_VEX_3A17 */
5070 {
5071 { Bad_Opcode },
5072 { Bad_Opcode },
5073 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5074 },
5075
5076 /* PREFIX_VEX_3A18 */
5077 {
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5081 },
5082
5083 /* PREFIX_VEX_3A19 */
5084 {
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5088 },
5089
5090 /* PREFIX_VEX_3A1D */
5091 {
5092 { Bad_Opcode },
5093 { Bad_Opcode },
5094 { "vcvtps2ph", { EXxmmq, XM, Ib } },
5095 },
5096
5097 /* PREFIX_VEX_3A20 */
5098 {
5099 { Bad_Opcode },
5100 { Bad_Opcode },
5101 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5102 },
5103
5104 /* PREFIX_VEX_3A21 */
5105 {
5106 { Bad_Opcode },
5107 { Bad_Opcode },
5108 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5109 },
5110
5111 /* PREFIX_VEX_3A22 */
5112 {
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5116 },
5117
5118 /* PREFIX_VEX_3A40 */
5119 {
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { VEX_W_TABLE (VEX_W_3A40_P_2) },
5123 },
5124
5125 /* PREFIX_VEX_3A41 */
5126 {
5127 { Bad_Opcode },
5128 { Bad_Opcode },
5129 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5130 },
5131
5132 /* PREFIX_VEX_3A42 */
5133 {
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5137 },
5138
5139 /* PREFIX_VEX_3A44 */
5140 {
5141 { Bad_Opcode },
5142 { Bad_Opcode },
5143 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5144 },
5145
5146 /* PREFIX_VEX_3A48 */
5147 {
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 { VEX_W_TABLE (VEX_W_3A48_P_2) },
5151 },
5152
5153 /* PREFIX_VEX_3A49 */
5154 {
5155 { Bad_Opcode },
5156 { Bad_Opcode },
5157 { VEX_W_TABLE (VEX_W_3A49_P_2) },
5158 },
5159
5160 /* PREFIX_VEX_3A4A */
5161 {
5162 { Bad_Opcode },
5163 { Bad_Opcode },
5164 { VEX_W_TABLE (VEX_W_3A4A_P_2) },
5165 },
5166
5167 /* PREFIX_VEX_3A4B */
5168 {
5169 { Bad_Opcode },
5170 { Bad_Opcode },
5171 { VEX_W_TABLE (VEX_W_3A4B_P_2) },
5172 },
5173
5174 /* PREFIX_VEX_3A4C */
5175 {
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5179 },
5180
5181 /* PREFIX_VEX_3A5C */
5182 {
5183 { Bad_Opcode },
5184 { Bad_Opcode },
5185 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5186 },
5187
5188 /* PREFIX_VEX_3A5D */
5189 {
5190 { Bad_Opcode },
5191 { Bad_Opcode },
5192 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5193 },
5194
5195 /* PREFIX_VEX_3A5E */
5196 {
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5200 },
5201
5202 /* PREFIX_VEX_3A5F */
5203 {
5204 { Bad_Opcode },
5205 { Bad_Opcode },
5206 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5207 },
5208
5209 /* PREFIX_VEX_3A60 */
5210 {
5211 { Bad_Opcode },
5212 { Bad_Opcode },
5213 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5214 { Bad_Opcode },
5215 },
5216
5217 /* PREFIX_VEX_3A61 */
5218 {
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5222 },
5223
5224 /* PREFIX_VEX_3A62 */
5225 {
5226 { Bad_Opcode },
5227 { Bad_Opcode },
5228 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5229 },
5230
5231 /* PREFIX_VEX_3A63 */
5232 {
5233 { Bad_Opcode },
5234 { Bad_Opcode },
5235 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5236 },
5237
5238 /* PREFIX_VEX_3A68 */
5239 {
5240 { Bad_Opcode },
5241 { Bad_Opcode },
5242 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5243 },
5244
5245 /* PREFIX_VEX_3A69 */
5246 {
5247 { Bad_Opcode },
5248 { Bad_Opcode },
5249 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5250 },
5251
5252 /* PREFIX_VEX_3A6A */
5253 {
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5257 },
5258
5259 /* PREFIX_VEX_3A6B */
5260 {
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5264 },
5265
5266 /* PREFIX_VEX_3A6C */
5267 {
5268 { Bad_Opcode },
5269 { Bad_Opcode },
5270 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5271 },
5272
5273 /* PREFIX_VEX_3A6D */
5274 {
5275 { Bad_Opcode },
5276 { Bad_Opcode },
5277 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5278 },
5279
5280 /* PREFIX_VEX_3A6E */
5281 {
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5285 },
5286
5287 /* PREFIX_VEX_3A6F */
5288 {
5289 { Bad_Opcode },
5290 { Bad_Opcode },
5291 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5292 },
5293
5294 /* PREFIX_VEX_3A78 */
5295 {
5296 { Bad_Opcode },
5297 { Bad_Opcode },
5298 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5299 },
5300
5301 /* PREFIX_VEX_3A79 */
5302 {
5303 { Bad_Opcode },
5304 { Bad_Opcode },
5305 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5306 },
5307
5308 /* PREFIX_VEX_3A7A */
5309 {
5310 { Bad_Opcode },
5311 { Bad_Opcode },
5312 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5313 },
5314
5315 /* PREFIX_VEX_3A7B */
5316 {
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5320 },
5321
5322 /* PREFIX_VEX_3A7C */
5323 {
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5327 { Bad_Opcode },
5328 },
5329
5330 /* PREFIX_VEX_3A7D */
5331 {
5332 { Bad_Opcode },
5333 { Bad_Opcode },
5334 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5335 },
5336
5337 /* PREFIX_VEX_3A7E */
5338 {
5339 { Bad_Opcode },
5340 { Bad_Opcode },
5341 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5342 },
5343
5344 /* PREFIX_VEX_3A7F */
5345 {
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5349 },
5350
5351 /* PREFIX_VEX_3ADF */
5352 {
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5356 },
5357};
5358
5359static const struct dis386 x86_64_table[][2] = {
5360 /* X86_64_06 */
5361 {
5362 { "push{T|}", { es } },
5363 },
5364
5365 /* X86_64_07 */
5366 {
5367 { "pop{T|}", { es } },
5368 },
5369
5370 /* X86_64_0D */
5371 {
5372 { "push{T|}", { cs } },
5373 },
5374
5375 /* X86_64_16 */
5376 {
5377 { "push{T|}", { ss } },
5378 },
5379
5380 /* X86_64_17 */
5381 {
5382 { "pop{T|}", { ss } },
5383 },
5384
5385 /* X86_64_1E */
5386 {
5387 { "push{T|}", { ds } },
5388 },
5389
5390 /* X86_64_1F */
5391 {
5392 { "pop{T|}", { ds } },
5393 },
5394
5395 /* X86_64_27 */
5396 {
5397 { "daa", { XX } },
5398 },
5399
5400 /* X86_64_2F */
5401 {
5402 { "das", { XX } },
5403 },
5404
5405 /* X86_64_37 */
5406 {
5407 { "aaa", { XX } },
5408 },
5409
5410 /* X86_64_3F */
5411 {
5412 { "aas", { XX } },
5413 },
5414
5415 /* X86_64_60 */
5416 {
5417 { "pusha{P|}", { XX } },
5418 },
5419
5420 /* X86_64_61 */
5421 {
5422 { "popa{P|}", { XX } },
5423 },
5424
5425 /* X86_64_62 */
5426 {
5427 { MOD_TABLE (MOD_62_32BIT) },
5428 },
5429
5430 /* X86_64_63 */
5431 {
5432 { "arpl", { Ew, Gw } },
5433 { "movs{lq|xd}", { Gv, Ed } },
5434 },
5435
5436 /* X86_64_6D */
5437 {
5438 { "ins{R|}", { Yzr, indirDX } },
5439 { "ins{G|}", { Yzr, indirDX } },
5440 },
5441
5442 /* X86_64_6F */
5443 {
5444 { "outs{R|}", { indirDXr, Xz } },
5445 { "outs{G|}", { indirDXr, Xz } },
5446 },
5447
5448 /* X86_64_9A */
5449 {
5450 { "Jcall{T|}", { Ap } },
5451 },
5452
5453 /* X86_64_C4 */
5454 {
5455 { MOD_TABLE (MOD_C4_32BIT) },
5456 { VEX_C4_TABLE (VEX_0F) },
5457 },
5458
5459 /* X86_64_C5 */
5460 {
5461 { MOD_TABLE (MOD_C5_32BIT) },
5462 { VEX_C5_TABLE (VEX_0F) },
5463 },
5464
5465 /* X86_64_CE */
5466 {
5467 { "into", { XX } },
5468 },
5469
5470 /* X86_64_D4 */
5471 {
5472 { "aam", { sIb } },
5473 },
5474
5475 /* X86_64_D5 */
5476 {
5477 { "aad", { sIb } },
5478 },
5479
5480 /* X86_64_EA */
5481 {
5482 { "Jjmp{T|}", { Ap } },
5483 },
5484
5485 /* X86_64_0F01_REG_0 */
5486 {
5487 { "sgdt{Q|IQ}", { M } },
5488 { "sgdt", { M } },
5489 },
5490
5491 /* X86_64_0F01_REG_1 */
5492 {
5493 { "sidt{Q|IQ}", { M } },
5494 { "sidt", { M } },
5495 },
5496
5497 /* X86_64_0F01_REG_2 */
5498 {
5499 { "lgdt{Q|Q}", { M } },
5500 { "lgdt", { M } },
5501 },
5502
5503 /* X86_64_0F01_REG_3 */
5504 {
5505 { "lidt{Q|Q}", { M } },
5506 { "lidt", { M } },
5507 },
5508};
5509
5510static const struct dis386 three_byte_table[][256] = {
5511
5512 /* THREE_BYTE_0F38 */
5513 {
5514 /* 00 */
5515 { "pshufb", { MX, EM } },
5516 { "phaddw", { MX, EM } },
5517 { "phaddd", { MX, EM } },
5518 { "phaddsw", { MX, EM } },
5519 { "pmaddubsw", { MX, EM } },
5520 { "phsubw", { MX, EM } },
5521 { "phsubd", { MX, EM } },
5522 { "phsubsw", { MX, EM } },
5523 /* 08 */
5524 { "psignb", { MX, EM } },
5525 { "psignw", { MX, EM } },
5526 { "psignd", { MX, EM } },
5527 { "pmulhrsw", { MX, EM } },
5528 { Bad_Opcode },
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 { Bad_Opcode },
5532 /* 10 */
5533 { PREFIX_TABLE (PREFIX_0F3810) },
5534 { Bad_Opcode },
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 { PREFIX_TABLE (PREFIX_0F3814) },
5538 { PREFIX_TABLE (PREFIX_0F3815) },
5539 { Bad_Opcode },
5540 { PREFIX_TABLE (PREFIX_0F3817) },
5541 /* 18 */
5542 { Bad_Opcode },
5543 { Bad_Opcode },
5544 { Bad_Opcode },
5545 { Bad_Opcode },
5546 { "pabsb", { MX, EM } },
5547 { "pabsw", { MX, EM } },
5548 { "pabsd", { MX, EM } },
5549 { Bad_Opcode },
5550 /* 20 */
5551 { PREFIX_TABLE (PREFIX_0F3820) },
5552 { PREFIX_TABLE (PREFIX_0F3821) },
5553 { PREFIX_TABLE (PREFIX_0F3822) },
5554 { PREFIX_TABLE (PREFIX_0F3823) },
5555 { PREFIX_TABLE (PREFIX_0F3824) },
5556 { PREFIX_TABLE (PREFIX_0F3825) },
5557 { Bad_Opcode },
5558 { Bad_Opcode },
5559 /* 28 */
5560 { PREFIX_TABLE (PREFIX_0F3828) },
5561 { PREFIX_TABLE (PREFIX_0F3829) },
5562 { PREFIX_TABLE (PREFIX_0F382A) },
5563 { PREFIX_TABLE (PREFIX_0F382B) },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 /* 30 */
5569 { PREFIX_TABLE (PREFIX_0F3830) },
5570 { PREFIX_TABLE (PREFIX_0F3831) },
5571 { PREFIX_TABLE (PREFIX_0F3832) },
5572 { PREFIX_TABLE (PREFIX_0F3833) },
5573 { PREFIX_TABLE (PREFIX_0F3834) },
5574 { PREFIX_TABLE (PREFIX_0F3835) },
5575 { Bad_Opcode },
5576 { PREFIX_TABLE (PREFIX_0F3837) },
5577 /* 38 */
5578 { PREFIX_TABLE (PREFIX_0F3838) },
5579 { PREFIX_TABLE (PREFIX_0F3839) },
5580 { PREFIX_TABLE (PREFIX_0F383A) },
5581 { PREFIX_TABLE (PREFIX_0F383B) },
5582 { PREFIX_TABLE (PREFIX_0F383C) },
5583 { PREFIX_TABLE (PREFIX_0F383D) },
5584 { PREFIX_TABLE (PREFIX_0F383E) },
5585 { PREFIX_TABLE (PREFIX_0F383F) },
5586 /* 40 */
5587 { PREFIX_TABLE (PREFIX_0F3840) },
5588 { PREFIX_TABLE (PREFIX_0F3841) },
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 /* 48 */
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 /* 50 */
5605 { Bad_Opcode },
5606 { Bad_Opcode },
5607 { Bad_Opcode },
5608 { Bad_Opcode },
5609 { Bad_Opcode },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 /* 58 */
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 /* 60 */
5623 { Bad_Opcode },
5624 { Bad_Opcode },
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 /* 68 */
5632 { Bad_Opcode },
5633 { Bad_Opcode },
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 /* 70 */
5641 { Bad_Opcode },
5642 { Bad_Opcode },
5643 { Bad_Opcode },
5644 { Bad_Opcode },
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 /* 78 */
5650 { Bad_Opcode },
5651 { Bad_Opcode },
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 { Bad_Opcode },
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 /* 80 */
5659 { PREFIX_TABLE (PREFIX_0F3880) },
5660 { PREFIX_TABLE (PREFIX_0F3881) },
5661 { Bad_Opcode },
5662 { Bad_Opcode },
5663 { Bad_Opcode },
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { Bad_Opcode },
5667 /* 88 */
5668 { Bad_Opcode },
5669 { Bad_Opcode },
5670 { Bad_Opcode },
5671 { Bad_Opcode },
5672 { Bad_Opcode },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 /* 90 */
5677 { Bad_Opcode },
5678 { Bad_Opcode },
5679 { Bad_Opcode },
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 /* 98 */
5686 { Bad_Opcode },
5687 { Bad_Opcode },
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 { Bad_Opcode },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 /* a0 */
5695 { Bad_Opcode },
5696 { Bad_Opcode },
5697 { Bad_Opcode },
5698 { Bad_Opcode },
5699 { Bad_Opcode },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 /* a8 */
5704 { Bad_Opcode },
5705 { Bad_Opcode },
5706 { Bad_Opcode },
5707 { Bad_Opcode },
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 /* b0 */
5713 { Bad_Opcode },
5714 { Bad_Opcode },
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 /* b8 */
5722 { Bad_Opcode },
5723 { Bad_Opcode },
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 /* c0 */
5731 { Bad_Opcode },
5732 { Bad_Opcode },
5733 { Bad_Opcode },
5734 { Bad_Opcode },
5735 { Bad_Opcode },
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 /* c8 */
5740 { Bad_Opcode },
5741 { Bad_Opcode },
5742 { Bad_Opcode },
5743 { Bad_Opcode },
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 /* d0 */
5749 { Bad_Opcode },
5750 { Bad_Opcode },
5751 { Bad_Opcode },
5752 { Bad_Opcode },
5753 { Bad_Opcode },
5754 { Bad_Opcode },
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 /* d8 */
5758 { Bad_Opcode },
5759 { Bad_Opcode },
5760 { Bad_Opcode },
5761 { PREFIX_TABLE (PREFIX_0F38DB) },
5762 { PREFIX_TABLE (PREFIX_0F38DC) },
5763 { PREFIX_TABLE (PREFIX_0F38DD) },
5764 { PREFIX_TABLE (PREFIX_0F38DE) },
5765 { PREFIX_TABLE (PREFIX_0F38DF) },
5766 /* e0 */
5767 { Bad_Opcode },
5768 { Bad_Opcode },
5769 { Bad_Opcode },
5770 { Bad_Opcode },
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 /* e8 */
5776 { Bad_Opcode },
5777 { Bad_Opcode },
5778 { Bad_Opcode },
5779 { Bad_Opcode },
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 /* f0 */
5785 { PREFIX_TABLE (PREFIX_0F38F0) },
5786 { PREFIX_TABLE (PREFIX_0F38F1) },
5787 { Bad_Opcode },
5788 { Bad_Opcode },
5789 { Bad_Opcode },
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 /* f8 */
5794 { Bad_Opcode },
5795 { Bad_Opcode },
5796 { Bad_Opcode },
5797 { Bad_Opcode },
5798 { Bad_Opcode },
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 },
5803 /* THREE_BYTE_0F3A */
5804 {
5805 /* 00 */
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 { Bad_Opcode },
5812 { Bad_Opcode },
5813 { Bad_Opcode },
5814 /* 08 */
5815 { PREFIX_TABLE (PREFIX_0F3A08) },
5816 { PREFIX_TABLE (PREFIX_0F3A09) },
5817 { PREFIX_TABLE (PREFIX_0F3A0A) },
5818 { PREFIX_TABLE (PREFIX_0F3A0B) },
5819 { PREFIX_TABLE (PREFIX_0F3A0C) },
5820 { PREFIX_TABLE (PREFIX_0F3A0D) },
5821 { PREFIX_TABLE (PREFIX_0F3A0E) },
5822 { "palignr", { MX, EM, Ib } },
5823 /* 10 */
5824 { Bad_Opcode },
5825 { Bad_Opcode },
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { PREFIX_TABLE (PREFIX_0F3A14) },
5829 { PREFIX_TABLE (PREFIX_0F3A15) },
5830 { PREFIX_TABLE (PREFIX_0F3A16) },
5831 { PREFIX_TABLE (PREFIX_0F3A17) },
5832 /* 18 */
5833 { Bad_Opcode },
5834 { Bad_Opcode },
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 /* 20 */
5842 { PREFIX_TABLE (PREFIX_0F3A20) },
5843 { PREFIX_TABLE (PREFIX_0F3A21) },
5844 { PREFIX_TABLE (PREFIX_0F3A22) },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 /* 28 */
5851 { Bad_Opcode },
5852 { Bad_Opcode },
5853 { Bad_Opcode },
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 /* 30 */
5860 { Bad_Opcode },
5861 { Bad_Opcode },
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 /* 38 */
5869 { Bad_Opcode },
5870 { Bad_Opcode },
5871 { Bad_Opcode },
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 { Bad_Opcode },
5875 { Bad_Opcode },
5876 { Bad_Opcode },
5877 /* 40 */
5878 { PREFIX_TABLE (PREFIX_0F3A40) },
5879 { PREFIX_TABLE (PREFIX_0F3A41) },
5880 { PREFIX_TABLE (PREFIX_0F3A42) },
5881 { Bad_Opcode },
5882 { PREFIX_TABLE (PREFIX_0F3A44) },
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 /* 48 */
5887 { Bad_Opcode },
5888 { Bad_Opcode },
5889 { Bad_Opcode },
5890 { Bad_Opcode },
5891 { Bad_Opcode },
5892 { Bad_Opcode },
5893 { Bad_Opcode },
5894 { Bad_Opcode },
5895 /* 50 */
5896 { Bad_Opcode },
5897 { Bad_Opcode },
5898 { Bad_Opcode },
5899 { Bad_Opcode },
5900 { Bad_Opcode },
5901 { Bad_Opcode },
5902 { Bad_Opcode },
5903 { Bad_Opcode },
5904 /* 58 */
5905 { Bad_Opcode },
5906 { Bad_Opcode },
5907 { Bad_Opcode },
5908 { Bad_Opcode },
5909 { Bad_Opcode },
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 { Bad_Opcode },
5913 /* 60 */
5914 { PREFIX_TABLE (PREFIX_0F3A60) },
5915 { PREFIX_TABLE (PREFIX_0F3A61) },
5916 { PREFIX_TABLE (PREFIX_0F3A62) },
5917 { PREFIX_TABLE (PREFIX_0F3A63) },
5918 { Bad_Opcode },
5919 { Bad_Opcode },
5920 { Bad_Opcode },
5921 { Bad_Opcode },
5922 /* 68 */
5923 { Bad_Opcode },
5924 { Bad_Opcode },
5925 { Bad_Opcode },
5926 { Bad_Opcode },
5927 { Bad_Opcode },
5928 { Bad_Opcode },
5929 { Bad_Opcode },
5930 { Bad_Opcode },
5931 /* 70 */
5932 { Bad_Opcode },
5933 { Bad_Opcode },
5934 { Bad_Opcode },
5935 { Bad_Opcode },
5936 { Bad_Opcode },
5937 { Bad_Opcode },
5938 { Bad_Opcode },
5939 { Bad_Opcode },
5940 /* 78 */
5941 { Bad_Opcode },
5942 { Bad_Opcode },
5943 { Bad_Opcode },
5944 { Bad_Opcode },
5945 { Bad_Opcode },
5946 { Bad_Opcode },
5947 { Bad_Opcode },
5948 { Bad_Opcode },
5949 /* 80 */
5950 { Bad_Opcode },
5951 { Bad_Opcode },
5952 { Bad_Opcode },
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { Bad_Opcode },
5956 { Bad_Opcode },
5957 { Bad_Opcode },
5958 /* 88 */
5959 { Bad_Opcode },
5960 { Bad_Opcode },
5961 { Bad_Opcode },
5962 { Bad_Opcode },
5963 { Bad_Opcode },
5964 { Bad_Opcode },
5965 { Bad_Opcode },
5966 { Bad_Opcode },
5967 /* 90 */
5968 { Bad_Opcode },
5969 { Bad_Opcode },
5970 { Bad_Opcode },
5971 { Bad_Opcode },
5972 { Bad_Opcode },
5973 { Bad_Opcode },
5974 { Bad_Opcode },
5975 { Bad_Opcode },
5976 /* 98 */
5977 { Bad_Opcode },
5978 { Bad_Opcode },
5979 { Bad_Opcode },
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 { Bad_Opcode },
5983 { Bad_Opcode },
5984 { Bad_Opcode },
5985 /* a0 */
5986 { Bad_Opcode },
5987 { Bad_Opcode },
5988 { Bad_Opcode },
5989 { Bad_Opcode },
5990 { Bad_Opcode },
5991 { Bad_Opcode },
5992 { Bad_Opcode },
5993 { Bad_Opcode },
5994 /* a8 */
5995 { Bad_Opcode },
5996 { Bad_Opcode },
5997 { Bad_Opcode },
5998 { Bad_Opcode },
5999 { Bad_Opcode },
6000 { Bad_Opcode },
6001 { Bad_Opcode },
6002 { Bad_Opcode },
6003 /* b0 */
6004 { Bad_Opcode },
6005 { Bad_Opcode },
6006 { Bad_Opcode },
6007 { Bad_Opcode },
6008 { Bad_Opcode },
6009 { Bad_Opcode },
6010 { Bad_Opcode },
6011 { Bad_Opcode },
6012 /* b8 */
6013 { Bad_Opcode },
6014 { Bad_Opcode },
6015 { Bad_Opcode },
6016 { Bad_Opcode },
6017 { Bad_Opcode },
6018 { Bad_Opcode },
6019 { Bad_Opcode },
6020 { Bad_Opcode },
6021 /* c0 */
6022 { Bad_Opcode },
6023 { Bad_Opcode },
6024 { Bad_Opcode },
6025 { Bad_Opcode },
6026 { Bad_Opcode },
6027 { Bad_Opcode },
6028 { Bad_Opcode },
6029 { Bad_Opcode },
6030 /* c8 */
6031 { Bad_Opcode },
6032 { Bad_Opcode },
6033 { Bad_Opcode },
6034 { Bad_Opcode },
6035 { Bad_Opcode },
6036 { Bad_Opcode },
6037 { Bad_Opcode },
6038 { Bad_Opcode },
6039 /* d0 */
6040 { Bad_Opcode },
6041 { Bad_Opcode },
6042 { Bad_Opcode },
6043 { Bad_Opcode },
6044 { Bad_Opcode },
6045 { Bad_Opcode },
6046 { Bad_Opcode },
6047 { Bad_Opcode },
6048 /* d8 */
6049 { Bad_Opcode },
6050 { Bad_Opcode },
6051 { Bad_Opcode },
6052 { Bad_Opcode },
6053 { Bad_Opcode },
6054 { Bad_Opcode },
6055 { Bad_Opcode },
6056 { PREFIX_TABLE (PREFIX_0F3ADF) },
6057 /* e0 */
6058 { Bad_Opcode },
6059 { Bad_Opcode },
6060 { Bad_Opcode },
6061 { Bad_Opcode },
6062 { Bad_Opcode },
6063 { Bad_Opcode },
6064 { Bad_Opcode },
6065 { Bad_Opcode },
6066 /* e8 */
6067 { Bad_Opcode },
6068 { Bad_Opcode },
6069 { Bad_Opcode },
6070 { Bad_Opcode },
6071 { Bad_Opcode },
6072 { Bad_Opcode },
6073 { Bad_Opcode },
6074 { Bad_Opcode },
6075 /* f0 */
6076 { Bad_Opcode },
6077 { Bad_Opcode },
6078 { Bad_Opcode },
6079 { Bad_Opcode },
6080 { Bad_Opcode },
6081 { Bad_Opcode },
6082 { Bad_Opcode },
6083 { Bad_Opcode },
6084 /* f8 */
6085 { Bad_Opcode },
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 { Bad_Opcode },
6089 { Bad_Opcode },
6090 { Bad_Opcode },
6091 { Bad_Opcode },
6092 { Bad_Opcode },
6093 },
6094
6095 /* THREE_BYTE_0F7A */
6096 {
6097 /* 00 */
6098 { Bad_Opcode },
6099 { Bad_Opcode },
6100 { Bad_Opcode },
6101 { Bad_Opcode },
6102 { Bad_Opcode },
6103 { Bad_Opcode },
6104 { Bad_Opcode },
6105 { Bad_Opcode },
6106 /* 08 */
6107 { Bad_Opcode },
6108 { Bad_Opcode },
6109 { Bad_Opcode },
6110 { Bad_Opcode },
6111 { Bad_Opcode },
6112 { Bad_Opcode },
6113 { Bad_Opcode },
6114 { Bad_Opcode },
6115 /* 10 */
6116 { Bad_Opcode },
6117 { Bad_Opcode },
6118 { Bad_Opcode },
6119 { Bad_Opcode },
6120 { Bad_Opcode },
6121 { Bad_Opcode },
6122 { Bad_Opcode },
6123 { Bad_Opcode },
6124 /* 18 */
6125 { Bad_Opcode },
6126 { Bad_Opcode },
6127 { Bad_Opcode },
6128 { Bad_Opcode },
6129 { Bad_Opcode },
6130 { Bad_Opcode },
6131 { Bad_Opcode },
6132 { Bad_Opcode },
6133 /* 20 */
6134 { "ptest", { XX } },
6135 { Bad_Opcode },
6136 { Bad_Opcode },
6137 { Bad_Opcode },
6138 { Bad_Opcode },
6139 { Bad_Opcode },
6140 { Bad_Opcode },
6141 { Bad_Opcode },
6142 /* 28 */
6143 { Bad_Opcode },
6144 { Bad_Opcode },
6145 { Bad_Opcode },
6146 { Bad_Opcode },
6147 { Bad_Opcode },
6148 { Bad_Opcode },
6149 { Bad_Opcode },
6150 { Bad_Opcode },
6151 /* 30 */
6152 { Bad_Opcode },
6153 { Bad_Opcode },
6154 { Bad_Opcode },
6155 { Bad_Opcode },
6156 { Bad_Opcode },
6157 { Bad_Opcode },
6158 { Bad_Opcode },
6159 { Bad_Opcode },
6160 /* 38 */
6161 { Bad_Opcode },
6162 { Bad_Opcode },
6163 { Bad_Opcode },
6164 { Bad_Opcode },
6165 { Bad_Opcode },
6166 { Bad_Opcode },
6167 { Bad_Opcode },
6168 { Bad_Opcode },
6169 /* 40 */
6170 { Bad_Opcode },
6171 { "phaddbw", { XM, EXq } },
6172 { "phaddbd", { XM, EXq } },
6173 { "phaddbq", { XM, EXq } },
6174 { Bad_Opcode },
6175 { Bad_Opcode },
6176 { "phaddwd", { XM, EXq } },
6177 { "phaddwq", { XM, EXq } },
6178 /* 48 */
6179 { Bad_Opcode },
6180 { Bad_Opcode },
6181 { Bad_Opcode },
6182 { "phadddq", { XM, EXq } },
6183 { Bad_Opcode },
6184 { Bad_Opcode },
6185 { Bad_Opcode },
6186 { Bad_Opcode },
6187 /* 50 */
6188 { Bad_Opcode },
6189 { "phaddubw", { XM, EXq } },
6190 { "phaddubd", { XM, EXq } },
6191 { "phaddubq", { XM, EXq } },
6192 { Bad_Opcode },
6193 { Bad_Opcode },
6194 { "phadduwd", { XM, EXq } },
6195 { "phadduwq", { XM, EXq } },
6196 /* 58 */
6197 { Bad_Opcode },
6198 { Bad_Opcode },
6199 { Bad_Opcode },
6200 { "phaddudq", { XM, EXq } },
6201 { Bad_Opcode },
6202 { Bad_Opcode },
6203 { Bad_Opcode },
6204 { Bad_Opcode },
6205 /* 60 */
6206 { Bad_Opcode },
6207 { "phsubbw", { XM, EXq } },
6208 { "phsubbd", { XM, EXq } },
6209 { "phsubbq", { XM, EXq } },
6210 { Bad_Opcode },
6211 { Bad_Opcode },
6212 { Bad_Opcode },
6213 { Bad_Opcode },
6214 /* 68 */
6215 { Bad_Opcode },
6216 { Bad_Opcode },
6217 { Bad_Opcode },
6218 { Bad_Opcode },
6219 { Bad_Opcode },
6220 { Bad_Opcode },
6221 { Bad_Opcode },
6222 { Bad_Opcode },
6223 /* 70 */
6224 { Bad_Opcode },
6225 { Bad_Opcode },
6226 { Bad_Opcode },
6227 { Bad_Opcode },
6228 { Bad_Opcode },
6229 { Bad_Opcode },
6230 { Bad_Opcode },
6231 { Bad_Opcode },
6232 /* 78 */
6233 { Bad_Opcode },
6234 { Bad_Opcode },
6235 { Bad_Opcode },
6236 { Bad_Opcode },
6237 { Bad_Opcode },
6238 { Bad_Opcode },
6239 { Bad_Opcode },
6240 { Bad_Opcode },
6241 /* 80 */
6242 { Bad_Opcode },
6243 { Bad_Opcode },
6244 { Bad_Opcode },
6245 { Bad_Opcode },
6246 { Bad_Opcode },
6247 { Bad_Opcode },
6248 { Bad_Opcode },
6249 { Bad_Opcode },
6250 /* 88 */
6251 { Bad_Opcode },
6252 { Bad_Opcode },
6253 { Bad_Opcode },
6254 { Bad_Opcode },
6255 { Bad_Opcode },
6256 { Bad_Opcode },
6257 { Bad_Opcode },
6258 { Bad_Opcode },
6259 /* 90 */
6260 { Bad_Opcode },
6261 { Bad_Opcode },
6262 { Bad_Opcode },
6263 { Bad_Opcode },
6264 { Bad_Opcode },
6265 { Bad_Opcode },
6266 { Bad_Opcode },
6267 { Bad_Opcode },
6268 /* 98 */
6269 { Bad_Opcode },
6270 { Bad_Opcode },
6271 { Bad_Opcode },
6272 { Bad_Opcode },
6273 { Bad_Opcode },
6274 { Bad_Opcode },
6275 { Bad_Opcode },
6276 { Bad_Opcode },
6277 /* a0 */
6278 { Bad_Opcode },
6279 { Bad_Opcode },
6280 { Bad_Opcode },
6281 { Bad_Opcode },
6282 { Bad_Opcode },
6283 { Bad_Opcode },
6284 { Bad_Opcode },
6285 { Bad_Opcode },
6286 /* a8 */
6287 { Bad_Opcode },
6288 { Bad_Opcode },
6289 { Bad_Opcode },
6290 { Bad_Opcode },
6291 { Bad_Opcode },
6292 { Bad_Opcode },
6293 { Bad_Opcode },
6294 { Bad_Opcode },
6295 /* b0 */
6296 { Bad_Opcode },
6297 { Bad_Opcode },
6298 { Bad_Opcode },
6299 { Bad_Opcode },
6300 { Bad_Opcode },
6301 { Bad_Opcode },
6302 { Bad_Opcode },
6303 { Bad_Opcode },
6304 /* b8 */
6305 { Bad_Opcode },
6306 { Bad_Opcode },
6307 { Bad_Opcode },
6308 { Bad_Opcode },
6309 { Bad_Opcode },
6310 { Bad_Opcode },
6311 { Bad_Opcode },
6312 { Bad_Opcode },
6313 /* c0 */
6314 { Bad_Opcode },
6315 { Bad_Opcode },
6316 { Bad_Opcode },
6317 { Bad_Opcode },
6318 { Bad_Opcode },
6319 { Bad_Opcode },
6320 { Bad_Opcode },
6321 { Bad_Opcode },
6322 /* c8 */
6323 { Bad_Opcode },
6324 { Bad_Opcode },
6325 { Bad_Opcode },
6326 { Bad_Opcode },
6327 { Bad_Opcode },
6328 { Bad_Opcode },
6329 { Bad_Opcode },
6330 { Bad_Opcode },
6331 /* d0 */
6332 { Bad_Opcode },
6333 { Bad_Opcode },
6334 { Bad_Opcode },
6335 { Bad_Opcode },
6336 { Bad_Opcode },
6337 { Bad_Opcode },
6338 { Bad_Opcode },
6339 { Bad_Opcode },
6340 /* d8 */
6341 { Bad_Opcode },
6342 { Bad_Opcode },
6343 { Bad_Opcode },
6344 { Bad_Opcode },
6345 { Bad_Opcode },
6346 { Bad_Opcode },
6347 { Bad_Opcode },
6348 { Bad_Opcode },
6349 /* e0 */
6350 { Bad_Opcode },
6351 { Bad_Opcode },
6352 { Bad_Opcode },
6353 { Bad_Opcode },
6354 { Bad_Opcode },
6355 { Bad_Opcode },
6356 { Bad_Opcode },
6357 { Bad_Opcode },
6358 /* e8 */
6359 { Bad_Opcode },
6360 { Bad_Opcode },
6361 { Bad_Opcode },
6362 { Bad_Opcode },
6363 { Bad_Opcode },
6364 { Bad_Opcode },
6365 { Bad_Opcode },
6366 { Bad_Opcode },
6367 /* f0 */
6368 { Bad_Opcode },
6369 { Bad_Opcode },
6370 { Bad_Opcode },
6371 { Bad_Opcode },
6372 { Bad_Opcode },
6373 { Bad_Opcode },
6374 { Bad_Opcode },
6375 { Bad_Opcode },
6376 /* f8 */
6377 { Bad_Opcode },
6378 { Bad_Opcode },
6379 { Bad_Opcode },
6380 { Bad_Opcode },
6381 { Bad_Opcode },
6382 { Bad_Opcode },
6383 { Bad_Opcode },
6384 { Bad_Opcode },
6385 },
6386};
6387
6388static const struct dis386 xop_table[][256] = {
6389 /* XOP_08 */
6390 {
6391 /* 00 */
6392 { Bad_Opcode },
6393 { Bad_Opcode },
6394 { Bad_Opcode },
6395 { Bad_Opcode },
6396 { Bad_Opcode },
6397 { Bad_Opcode },
6398 { Bad_Opcode },
6399 { Bad_Opcode },
6400 /* 08 */
6401 { Bad_Opcode },
6402 { Bad_Opcode },
6403 { Bad_Opcode },
6404 { Bad_Opcode },
6405 { Bad_Opcode },
6406 { Bad_Opcode },
6407 { Bad_Opcode },
6408 { Bad_Opcode },
6409 /* 10 */
6410 { Bad_Opcode },
6411 { Bad_Opcode },
6412 { Bad_Opcode },
6413 { Bad_Opcode },
6414 { Bad_Opcode },
6415 { Bad_Opcode },
6416 { Bad_Opcode },
6417 { Bad_Opcode },
6418 /* 18 */
6419 { Bad_Opcode },
6420 { Bad_Opcode },
6421 { Bad_Opcode },
6422 { Bad_Opcode },
6423 { Bad_Opcode },
6424 { Bad_Opcode },
6425 { Bad_Opcode },
6426 { Bad_Opcode },
6427 /* 20 */
6428 { Bad_Opcode },
6429 { Bad_Opcode },
6430 { Bad_Opcode },
6431 { Bad_Opcode },
6432 { Bad_Opcode },
6433 { Bad_Opcode },
6434 { Bad_Opcode },
6435 { Bad_Opcode },
6436 /* 28 */
6437 { Bad_Opcode },
6438 { Bad_Opcode },
6439 { Bad_Opcode },
6440 { Bad_Opcode },
6441 { Bad_Opcode },
6442 { Bad_Opcode },
6443 { Bad_Opcode },
6444 { Bad_Opcode },
6445 /* 30 */
6446 { Bad_Opcode },
6447 { Bad_Opcode },
6448 { Bad_Opcode },
6449 { Bad_Opcode },
6450 { Bad_Opcode },
6451 { Bad_Opcode },
6452 { Bad_Opcode },
6453 { Bad_Opcode },
6454 /* 38 */
6455 { Bad_Opcode },
6456 { Bad_Opcode },
6457 { Bad_Opcode },
6458 { Bad_Opcode },
6459 { Bad_Opcode },
6460 { Bad_Opcode },
6461 { Bad_Opcode },
6462 { Bad_Opcode },
6463 /* 40 */
6464 { Bad_Opcode },
6465 { Bad_Opcode },
6466 { Bad_Opcode },
6467 { Bad_Opcode },
6468 { Bad_Opcode },
6469 { Bad_Opcode },
6470 { Bad_Opcode },
6471 { Bad_Opcode },
6472 /* 48 */
6473 { Bad_Opcode },
6474 { Bad_Opcode },
6475 { Bad_Opcode },
6476 { Bad_Opcode },
6477 { Bad_Opcode },
6478 { Bad_Opcode },
6479 { Bad_Opcode },
6480 { Bad_Opcode },
6481 /* 50 */
6482 { Bad_Opcode },
6483 { Bad_Opcode },
6484 { Bad_Opcode },
6485 { Bad_Opcode },
6486 { Bad_Opcode },
6487 { Bad_Opcode },
6488 { Bad_Opcode },
6489 { Bad_Opcode },
6490 /* 58 */
6491 { Bad_Opcode },
6492 { Bad_Opcode },
6493 { Bad_Opcode },
6494 { Bad_Opcode },
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 { Bad_Opcode },
6498 { Bad_Opcode },
6499 /* 60 */
6500 { Bad_Opcode },
6501 { Bad_Opcode },
6502 { Bad_Opcode },
6503 { Bad_Opcode },
6504 { Bad_Opcode },
6505 { Bad_Opcode },
6506 { Bad_Opcode },
6507 { Bad_Opcode },
6508 /* 68 */
6509 { Bad_Opcode },
6510 { Bad_Opcode },
6511 { Bad_Opcode },
6512 { Bad_Opcode },
6513 { Bad_Opcode },
6514 { Bad_Opcode },
6515 { Bad_Opcode },
6516 { Bad_Opcode },
6517 /* 70 */
6518 { Bad_Opcode },
6519 { Bad_Opcode },
6520 { Bad_Opcode },
6521 { Bad_Opcode },
6522 { Bad_Opcode },
6523 { Bad_Opcode },
6524 { Bad_Opcode },
6525 { Bad_Opcode },
6526 /* 78 */
6527 { Bad_Opcode },
6528 { Bad_Opcode },
6529 { Bad_Opcode },
6530 { Bad_Opcode },
6531 { Bad_Opcode },
6532 { Bad_Opcode },
6533 { Bad_Opcode },
6534 { Bad_Opcode },
6535 /* 80 */
6536 { Bad_Opcode },
6537 { Bad_Opcode },
6538 { Bad_Opcode },
6539 { Bad_Opcode },
6540 { Bad_Opcode },
6541 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6542 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6543 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6544 /* 88 */
6545 { Bad_Opcode },
6546 { Bad_Opcode },
6547 { Bad_Opcode },
6548 { Bad_Opcode },
6549 { Bad_Opcode },
6550 { Bad_Opcode },
6551 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6552 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6553 /* 90 */
6554 { Bad_Opcode },
6555 { Bad_Opcode },
6556 { Bad_Opcode },
6557 { Bad_Opcode },
6558 { Bad_Opcode },
6559 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6560 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6561 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6562 /* 98 */
6563 { Bad_Opcode },
6564 { Bad_Opcode },
6565 { Bad_Opcode },
6566 { Bad_Opcode },
6567 { Bad_Opcode },
6568 { Bad_Opcode },
6569 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6570 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6571 /* a0 */
6572 { Bad_Opcode },
6573 { Bad_Opcode },
6574 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6575 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6576 { Bad_Opcode },
6577 { Bad_Opcode },
6578 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6579 { Bad_Opcode },
6580 /* a8 */
6581 { Bad_Opcode },
6582 { Bad_Opcode },
6583 { Bad_Opcode },
6584 { Bad_Opcode },
6585 { Bad_Opcode },
6586 { Bad_Opcode },
6587 { Bad_Opcode },
6588 { Bad_Opcode },
6589 /* b0 */
6590 { Bad_Opcode },
6591 { Bad_Opcode },
6592 { Bad_Opcode },
6593 { Bad_Opcode },
6594 { Bad_Opcode },
6595 { Bad_Opcode },
6596 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6597 { Bad_Opcode },
6598 /* b8 */
6599 { Bad_Opcode },
6600 { Bad_Opcode },
6601 { Bad_Opcode },
6602 { Bad_Opcode },
6603 { Bad_Opcode },
6604 { Bad_Opcode },
6605 { Bad_Opcode },
6606 { Bad_Opcode },
6607 /* c0 */
6608 { "vprotb", { XM, Vex_2src_1, Ib } },
6609 { "vprotw", { XM, Vex_2src_1, Ib } },
6610 { "vprotd", { XM, Vex_2src_1, Ib } },
6611 { "vprotq", { XM, Vex_2src_1, Ib } },
6612 { Bad_Opcode },
6613 { Bad_Opcode },
6614 { Bad_Opcode },
6615 { Bad_Opcode },
6616 /* c8 */
6617 { Bad_Opcode },
6618 { Bad_Opcode },
6619 { Bad_Opcode },
6620 { Bad_Opcode },
6621 { "vpcomb", { XM, Vex128, EXx, Ib } },
6622 { "vpcomw", { XM, Vex128, EXx, Ib } },
6623 { "vpcomd", { XM, Vex128, EXx, Ib } },
6624 { "vpcomq", { XM, Vex128, EXx, Ib } },
6625 /* d0 */
6626 { Bad_Opcode },
6627 { Bad_Opcode },
6628 { Bad_Opcode },
6629 { Bad_Opcode },
6630 { Bad_Opcode },
6631 { Bad_Opcode },
6632 { Bad_Opcode },
6633 { Bad_Opcode },
6634 /* d8 */
6635 { Bad_Opcode },
6636 { Bad_Opcode },
6637 { Bad_Opcode },
6638 { Bad_Opcode },
6639 { Bad_Opcode },
6640 { Bad_Opcode },
6641 { Bad_Opcode },
6642 { Bad_Opcode },
6643 /* e0 */
6644 { Bad_Opcode },
6645 { Bad_Opcode },
6646 { Bad_Opcode },
6647 { Bad_Opcode },
6648 { Bad_Opcode },
6649 { Bad_Opcode },
6650 { Bad_Opcode },
6651 { Bad_Opcode },
6652 /* e8 */
6653 { Bad_Opcode },
6654 { Bad_Opcode },
6655 { Bad_Opcode },
6656 { Bad_Opcode },
6657 { "vpcomub", { XM, Vex128, EXx, Ib } },
6658 { "vpcomuw", { XM, Vex128, EXx, Ib } },
6659 { "vpcomud", { XM, Vex128, EXx, Ib } },
6660 { "vpcomuq", { XM, Vex128, EXx, Ib } },
6661 /* f0 */
6662 { Bad_Opcode },
6663 { Bad_Opcode },
6664 { Bad_Opcode },
6665 { Bad_Opcode },
6666 { Bad_Opcode },
6667 { Bad_Opcode },
6668 { Bad_Opcode },
6669 { Bad_Opcode },
6670 /* f8 */
6671 { Bad_Opcode },
6672 { Bad_Opcode },
6673 { Bad_Opcode },
6674 { Bad_Opcode },
6675 { Bad_Opcode },
6676 { Bad_Opcode },
6677 { Bad_Opcode },
6678 { Bad_Opcode },
6679 },
6680 /* XOP_09 */
6681 {
6682 /* 00 */
6683 { Bad_Opcode },
6684 { Bad_Opcode },
6685 { Bad_Opcode },
6686 { Bad_Opcode },
6687 { Bad_Opcode },
6688 { Bad_Opcode },
6689 { Bad_Opcode },
6690 { Bad_Opcode },
6691 /* 08 */
6692 { Bad_Opcode },
6693 { Bad_Opcode },
6694 { Bad_Opcode },
6695 { Bad_Opcode },
6696 { Bad_Opcode },
6697 { Bad_Opcode },
6698 { Bad_Opcode },
6699 { Bad_Opcode },
6700 /* 10 */
6701 { Bad_Opcode },
6702 { Bad_Opcode },
6703 { REG_TABLE (REG_XOP_LWPCB) },
6704 { Bad_Opcode },
6705 { Bad_Opcode },
6706 { Bad_Opcode },
6707 { Bad_Opcode },
6708 { Bad_Opcode },
6709 /* 18 */
6710 { Bad_Opcode },
6711 { Bad_Opcode },
6712 { Bad_Opcode },
6713 { Bad_Opcode },
6714 { Bad_Opcode },
6715 { Bad_Opcode },
6716 { Bad_Opcode },
6717 { Bad_Opcode },
6718 /* 20 */
6719 { Bad_Opcode },
6720 { Bad_Opcode },
6721 { Bad_Opcode },
6722 { Bad_Opcode },
6723 { Bad_Opcode },
6724 { Bad_Opcode },
6725 { Bad_Opcode },
6726 { Bad_Opcode },
6727 /* 28 */
6728 { Bad_Opcode },
6729 { Bad_Opcode },
6730 { Bad_Opcode },
6731 { Bad_Opcode },
6732 { Bad_Opcode },
6733 { Bad_Opcode },
6734 { Bad_Opcode },
6735 { Bad_Opcode },
6736 /* 30 */
6737 { Bad_Opcode },
6738 { Bad_Opcode },
6739 { Bad_Opcode },
6740 { Bad_Opcode },
6741 { Bad_Opcode },
6742 { Bad_Opcode },
6743 { Bad_Opcode },
6744 { Bad_Opcode },
6745 /* 38 */
6746 { Bad_Opcode },
6747 { Bad_Opcode },
6748 { Bad_Opcode },
6749 { Bad_Opcode },
6750 { Bad_Opcode },
6751 { Bad_Opcode },
6752 { Bad_Opcode },
6753 { Bad_Opcode },
6754 /* 40 */
6755 { Bad_Opcode },
6756 { Bad_Opcode },
6757 { Bad_Opcode },
6758 { Bad_Opcode },
6759 { Bad_Opcode },
6760 { Bad_Opcode },
6761 { Bad_Opcode },
6762 { Bad_Opcode },
6763 /* 48 */
6764 { Bad_Opcode },
6765 { Bad_Opcode },
6766 { Bad_Opcode },
6767 { Bad_Opcode },
6768 { Bad_Opcode },
6769 { Bad_Opcode },
6770 { Bad_Opcode },
6771 { Bad_Opcode },
6772 /* 50 */
6773 { Bad_Opcode },
6774 { Bad_Opcode },
6775 { Bad_Opcode },
6776 { Bad_Opcode },
6777 { Bad_Opcode },
6778 { Bad_Opcode },
6779 { Bad_Opcode },
6780 { Bad_Opcode },
6781 /* 58 */
6782 { Bad_Opcode },
6783 { Bad_Opcode },
6784 { Bad_Opcode },
6785 { Bad_Opcode },
6786 { Bad_Opcode },
6787 { Bad_Opcode },
6788 { Bad_Opcode },
6789 { Bad_Opcode },
6790 /* 60 */
6791 { Bad_Opcode },
6792 { Bad_Opcode },
6793 { Bad_Opcode },
6794 { Bad_Opcode },
6795 { Bad_Opcode },
6796 { Bad_Opcode },
6797 { Bad_Opcode },
6798 { Bad_Opcode },
6799 /* 68 */
6800 { Bad_Opcode },
6801 { Bad_Opcode },
6802 { Bad_Opcode },
6803 { Bad_Opcode },
6804 { Bad_Opcode },
6805 { Bad_Opcode },
6806 { Bad_Opcode },
6807 { Bad_Opcode },
6808 /* 70 */
6809 { Bad_Opcode },
6810 { Bad_Opcode },
6811 { Bad_Opcode },
6812 { Bad_Opcode },
6813 { Bad_Opcode },
6814 { Bad_Opcode },
6815 { Bad_Opcode },
6816 { Bad_Opcode },
6817 /* 78 */
6818 { Bad_Opcode },
6819 { Bad_Opcode },
6820 { Bad_Opcode },
6821 { Bad_Opcode },
6822 { Bad_Opcode },
6823 { Bad_Opcode },
6824 { Bad_Opcode },
6825 { Bad_Opcode },
6826 /* 80 */
6827 { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
6828 { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
6829 { "vfrczss", { XM, EXd } },
6830 { "vfrczsd", { XM, EXq } },
6831 { Bad_Opcode },
6832 { Bad_Opcode },
6833 { Bad_Opcode },
6834 { Bad_Opcode },
6835 /* 88 */
6836 { Bad_Opcode },
6837 { Bad_Opcode },
6838 { Bad_Opcode },
6839 { Bad_Opcode },
6840 { Bad_Opcode },
6841 { Bad_Opcode },
6842 { Bad_Opcode },
6843 { Bad_Opcode },
6844 /* 90 */
6845 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
6846 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
6847 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
6848 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
6849 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
6850 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
6851 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
6852 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
6853 /* 98 */
6854 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
6855 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
6856 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
6857 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
6858 { Bad_Opcode },
6859 { Bad_Opcode },
6860 { Bad_Opcode },
6861 { Bad_Opcode },
6862 /* a0 */
6863 { Bad_Opcode },
6864 { Bad_Opcode },
6865 { Bad_Opcode },
6866 { Bad_Opcode },
6867 { Bad_Opcode },
6868 { Bad_Opcode },
6869 { Bad_Opcode },
6870 { Bad_Opcode },
6871 /* a8 */
6872 { Bad_Opcode },
6873 { Bad_Opcode },
6874 { Bad_Opcode },
6875 { Bad_Opcode },
6876 { Bad_Opcode },
6877 { Bad_Opcode },
6878 { Bad_Opcode },
6879 { Bad_Opcode },
6880 /* b0 */
6881 { Bad_Opcode },
6882 { Bad_Opcode },
6883 { Bad_Opcode },
6884 { Bad_Opcode },
6885 { Bad_Opcode },
6886 { Bad_Opcode },
6887 { Bad_Opcode },
6888 { Bad_Opcode },
6889 /* b8 */
6890 { Bad_Opcode },
6891 { Bad_Opcode },
6892 { Bad_Opcode },
6893 { Bad_Opcode },
6894 { Bad_Opcode },
6895 { Bad_Opcode },
6896 { Bad_Opcode },
6897 { Bad_Opcode },
6898 /* c0 */
6899 { Bad_Opcode },
6900 { "vphaddbw", { XM, EXxmm } },
6901 { "vphaddbd", { XM, EXxmm } },
6902 { "vphaddbq", { XM, EXxmm } },
6903 { Bad_Opcode },
6904 { Bad_Opcode },
6905 { "vphaddwd", { XM, EXxmm } },
6906 { "vphaddwq", { XM, EXxmm } },
6907 /* c8 */
6908 { Bad_Opcode },
6909 { Bad_Opcode },
6910 { Bad_Opcode },
6911 { "vphadddq", { XM, EXxmm } },
6912 { Bad_Opcode },
6913 { Bad_Opcode },
6914 { Bad_Opcode },
6915 { Bad_Opcode },
6916 /* d0 */
6917 { Bad_Opcode },
6918 { "vphaddubw", { XM, EXxmm } },
6919 { "vphaddubd", { XM, EXxmm } },
6920 { "vphaddubq", { XM, EXxmm } },
6921 { Bad_Opcode },
6922 { Bad_Opcode },
6923 { "vphadduwd", { XM, EXxmm } },
6924 { "vphadduwq", { XM, EXxmm } },
6925 /* d8 */
6926 { Bad_Opcode },
6927 { Bad_Opcode },
6928 { Bad_Opcode },
6929 { "vphaddudq", { XM, EXxmm } },
6930 { Bad_Opcode },
6931 { Bad_Opcode },
6932 { Bad_Opcode },
6933 { Bad_Opcode },
6934 /* e0 */
6935 { Bad_Opcode },
6936 { "vphsubbw", { XM, EXxmm } },
6937 { "vphsubwd", { XM, EXxmm } },
6938 { "vphsubdq", { XM, EXxmm } },
6939 { Bad_Opcode },
6940 { Bad_Opcode },
6941 { Bad_Opcode },
6942 { Bad_Opcode },
6943 /* e8 */
6944 { Bad_Opcode },
6945 { Bad_Opcode },
6946 { Bad_Opcode },
6947 { Bad_Opcode },
6948 { Bad_Opcode },
6949 { Bad_Opcode },
6950 { Bad_Opcode },
6951 { Bad_Opcode },
6952 /* f0 */
6953 { Bad_Opcode },
6954 { Bad_Opcode },
6955 { Bad_Opcode },
6956 { Bad_Opcode },
6957 { Bad_Opcode },
6958 { Bad_Opcode },
6959 { Bad_Opcode },
6960 { Bad_Opcode },
6961 /* f8 */
6962 { Bad_Opcode },
6963 { Bad_Opcode },
6964 { Bad_Opcode },
6965 { Bad_Opcode },
6966 { Bad_Opcode },
6967 { Bad_Opcode },
6968 { Bad_Opcode },
6969 { Bad_Opcode },
6970 },
6971 /* XOP_0A */
6972 {
6973 /* 00 */
6974 { Bad_Opcode },
6975 { Bad_Opcode },
6976 { Bad_Opcode },
6977 { Bad_Opcode },
6978 { Bad_Opcode },
6979 { Bad_Opcode },
6980 { Bad_Opcode },
6981 { Bad_Opcode },
6982 /* 08 */
6983 { Bad_Opcode },
6984 { Bad_Opcode },
6985 { Bad_Opcode },
6986 { Bad_Opcode },
6987 { Bad_Opcode },
6988 { Bad_Opcode },
6989 { Bad_Opcode },
6990 { Bad_Opcode },
6991 /* 10 */
6992 { Bad_Opcode },
6993 { Bad_Opcode },
6994 { REG_TABLE (REG_XOP_LWP) },
6995 { Bad_Opcode },
6996 { Bad_Opcode },
6997 { Bad_Opcode },
6998 { Bad_Opcode },
6999 { Bad_Opcode },
7000 /* 18 */
7001 { Bad_Opcode },
7002 { Bad_Opcode },
7003 { Bad_Opcode },
7004 { Bad_Opcode },
7005 { Bad_Opcode },
7006 { Bad_Opcode },
7007 { Bad_Opcode },
7008 { Bad_Opcode },
7009 /* 20 */
7010 { Bad_Opcode },
7011 { Bad_Opcode },
7012 { Bad_Opcode },
7013 { Bad_Opcode },
7014 { Bad_Opcode },
7015 { Bad_Opcode },
7016 { Bad_Opcode },
7017 { Bad_Opcode },
7018 /* 28 */
7019 { Bad_Opcode },
7020 { Bad_Opcode },
7021 { Bad_Opcode },
7022 { Bad_Opcode },
7023 { Bad_Opcode },
7024 { Bad_Opcode },
7025 { Bad_Opcode },
7026 { Bad_Opcode },
7027 /* 30 */
7028 { Bad_Opcode },
7029 { Bad_Opcode },
7030 { Bad_Opcode },
7031 { Bad_Opcode },
7032 { Bad_Opcode },
7033 { Bad_Opcode },
7034 { Bad_Opcode },
7035 { Bad_Opcode },
7036 /* 38 */
7037 { Bad_Opcode },
7038 { Bad_Opcode },
7039 { Bad_Opcode },
7040 { Bad_Opcode },
7041 { Bad_Opcode },
7042 { Bad_Opcode },
7043 { Bad_Opcode },
7044 { Bad_Opcode },
7045 /* 40 */
7046 { Bad_Opcode },
7047 { Bad_Opcode },
7048 { Bad_Opcode },
7049 { Bad_Opcode },
7050 { Bad_Opcode },
7051 { Bad_Opcode },
7052 { Bad_Opcode },
7053 { Bad_Opcode },
7054 /* 48 */
7055 { Bad_Opcode },
7056 { Bad_Opcode },
7057 { Bad_Opcode },
7058 { Bad_Opcode },
7059 { Bad_Opcode },
7060 { Bad_Opcode },
7061 { Bad_Opcode },
7062 { Bad_Opcode },
7063 /* 50 */
7064 { Bad_Opcode },
7065 { Bad_Opcode },
7066 { Bad_Opcode },
7067 { Bad_Opcode },
7068 { Bad_Opcode },
7069 { Bad_Opcode },
7070 { Bad_Opcode },
7071 { Bad_Opcode },
7072 /* 58 */
7073 { Bad_Opcode },
7074 { Bad_Opcode },
7075 { Bad_Opcode },
7076 { Bad_Opcode },
7077 { Bad_Opcode },
7078 { Bad_Opcode },
7079 { Bad_Opcode },
7080 { Bad_Opcode },
7081 /* 60 */
7082 { Bad_Opcode },
7083 { Bad_Opcode },
7084 { Bad_Opcode },
7085 { Bad_Opcode },
7086 { Bad_Opcode },
7087 { Bad_Opcode },
7088 { Bad_Opcode },
7089 { Bad_Opcode },
7090 /* 68 */
7091 { Bad_Opcode },
7092 { Bad_Opcode },
7093 { Bad_Opcode },
7094 { Bad_Opcode },
7095 { Bad_Opcode },
7096 { Bad_Opcode },
7097 { Bad_Opcode },
7098 { Bad_Opcode },
7099 /* 70 */
7100 { Bad_Opcode },
7101 { Bad_Opcode },
7102 { Bad_Opcode },
7103 { Bad_Opcode },
7104 { Bad_Opcode },
7105 { Bad_Opcode },
7106 { Bad_Opcode },
7107 { Bad_Opcode },
7108 /* 78 */
7109 { Bad_Opcode },
7110 { Bad_Opcode },
7111 { Bad_Opcode },
7112 { Bad_Opcode },
7113 { Bad_Opcode },
7114 { Bad_Opcode },
7115 { Bad_Opcode },
7116 { Bad_Opcode },
7117 /* 80 */
7118 { Bad_Opcode },
7119 { Bad_Opcode },
7120 { Bad_Opcode },
7121 { Bad_Opcode },
7122 { Bad_Opcode },
7123 { Bad_Opcode },
7124 { Bad_Opcode },
7125 { Bad_Opcode },
7126 /* 88 */
7127 { Bad_Opcode },
7128 { Bad_Opcode },
7129 { Bad_Opcode },
7130 { Bad_Opcode },
7131 { Bad_Opcode },
7132 { Bad_Opcode },
7133 { Bad_Opcode },
7134 { Bad_Opcode },
7135 /* 90 */
7136 { Bad_Opcode },
7137 { Bad_Opcode },
7138 { Bad_Opcode },
7139 { Bad_Opcode },
7140 { Bad_Opcode },
7141 { Bad_Opcode },
7142 { Bad_Opcode },
7143 { Bad_Opcode },
7144 /* 98 */
7145 { Bad_Opcode },
7146 { Bad_Opcode },
7147 { Bad_Opcode },
7148 { Bad_Opcode },
7149 { Bad_Opcode },
7150 { Bad_Opcode },
7151 { Bad_Opcode },
7152 { Bad_Opcode },
7153 /* a0 */
7154 { Bad_Opcode },
7155 { Bad_Opcode },
7156 { Bad_Opcode },
7157 { Bad_Opcode },
7158 { Bad_Opcode },
7159 { Bad_Opcode },
7160 { Bad_Opcode },
7161 { Bad_Opcode },
7162 /* a8 */
7163 { Bad_Opcode },
7164 { Bad_Opcode },
7165 { Bad_Opcode },
7166 { Bad_Opcode },
7167 { Bad_Opcode },
7168 { Bad_Opcode },
7169 { Bad_Opcode },
7170 { Bad_Opcode },
7171 /* b0 */
7172 { Bad_Opcode },
7173 { Bad_Opcode },
7174 { Bad_Opcode },
7175 { Bad_Opcode },
7176 { Bad_Opcode },
7177 { Bad_Opcode },
7178 { Bad_Opcode },
7179 { Bad_Opcode },
7180 /* b8 */
7181 { Bad_Opcode },
7182 { Bad_Opcode },
7183 { Bad_Opcode },
7184 { Bad_Opcode },
7185 { Bad_Opcode },
7186 { Bad_Opcode },
7187 { Bad_Opcode },
7188 { Bad_Opcode },
7189 /* c0 */
7190 { Bad_Opcode },
7191 { Bad_Opcode },
7192 { Bad_Opcode },
7193 { Bad_Opcode },
7194 { Bad_Opcode },
7195 { Bad_Opcode },
7196 { Bad_Opcode },
7197 { Bad_Opcode },
7198 /* c8 */
7199 { Bad_Opcode },
7200 { Bad_Opcode },
7201 { Bad_Opcode },
7202 { Bad_Opcode },
7203 { Bad_Opcode },
7204 { Bad_Opcode },
7205 { Bad_Opcode },
7206 { Bad_Opcode },
7207 /* d0 */
7208 { Bad_Opcode },
7209 { Bad_Opcode },
7210 { Bad_Opcode },
7211 { Bad_Opcode },
7212 { Bad_Opcode },
7213 { Bad_Opcode },
7214 { Bad_Opcode },
7215 { Bad_Opcode },
7216 /* d8 */
7217 { Bad_Opcode },
7218 { Bad_Opcode },
7219 { Bad_Opcode },
7220 { Bad_Opcode },
7221 { Bad_Opcode },
7222 { Bad_Opcode },
7223 { Bad_Opcode },
7224 { Bad_Opcode },
7225 /* e0 */
7226 { Bad_Opcode },
7227 { Bad_Opcode },
7228 { Bad_Opcode },
7229 { Bad_Opcode },
7230 { Bad_Opcode },
7231 { Bad_Opcode },
7232 { Bad_Opcode },
7233 { Bad_Opcode },
7234 /* e8 */
7235 { Bad_Opcode },
7236 { Bad_Opcode },
7237 { Bad_Opcode },
7238 { Bad_Opcode },
7239 { Bad_Opcode },
7240 { Bad_Opcode },
7241 { Bad_Opcode },
7242 { Bad_Opcode },
7243 /* f0 */
7244 { Bad_Opcode },
7245 { Bad_Opcode },
7246 { Bad_Opcode },
7247 { Bad_Opcode },
7248 { Bad_Opcode },
7249 { Bad_Opcode },
7250 { Bad_Opcode },
7251 { Bad_Opcode },
7252 /* f8 */
7253 { Bad_Opcode },
7254 { Bad_Opcode },
7255 { Bad_Opcode },
7256 { Bad_Opcode },
7257 { Bad_Opcode },
7258 { Bad_Opcode },
7259 { Bad_Opcode },
7260 { Bad_Opcode },
7261 },
7262};
7263
7264static const struct dis386 vex_table[][256] = {
7265 /* VEX_0F */
7266 {
7267 /* 00 */
7268 { Bad_Opcode },
7269 { Bad_Opcode },
7270 { Bad_Opcode },
7271 { Bad_Opcode },
7272 { Bad_Opcode },
7273 { Bad_Opcode },
7274 { Bad_Opcode },
7275 { Bad_Opcode },
7276 /* 08 */
7277 { Bad_Opcode },
7278 { Bad_Opcode },
7279 { Bad_Opcode },
7280 { Bad_Opcode },
7281 { Bad_Opcode },
7282 { Bad_Opcode },
7283 { Bad_Opcode },
7284 { Bad_Opcode },
7285 /* 10 */
7286 { PREFIX_TABLE (PREFIX_VEX_10) },
7287 { PREFIX_TABLE (PREFIX_VEX_11) },
7288 { PREFIX_TABLE (PREFIX_VEX_12) },
7289 { MOD_TABLE (MOD_VEX_13) },
7290 { VEX_W_TABLE (VEX_W_14) },
7291 { VEX_W_TABLE (VEX_W_15) },
7292 { PREFIX_TABLE (PREFIX_VEX_16) },
7293 { MOD_TABLE (MOD_VEX_17) },
7294 /* 18 */
7295 { Bad_Opcode },
7296 { Bad_Opcode },
7297 { Bad_Opcode },
7298 { Bad_Opcode },
7299 { Bad_Opcode },
7300 { Bad_Opcode },
7301 { Bad_Opcode },
7302 { Bad_Opcode },
7303 /* 20 */
7304 { Bad_Opcode },
7305 { Bad_Opcode },
7306 { Bad_Opcode },
7307 { Bad_Opcode },
7308 { Bad_Opcode },
7309 { Bad_Opcode },
7310 { Bad_Opcode },
7311 { Bad_Opcode },
7312 /* 28 */
7313 { VEX_W_TABLE (VEX_W_28) },
7314 { VEX_W_TABLE (VEX_W_29) },
7315 { PREFIX_TABLE (PREFIX_VEX_2A) },
7316 { MOD_TABLE (MOD_VEX_2B) },
7317 { PREFIX_TABLE (PREFIX_VEX_2C) },
7318 { PREFIX_TABLE (PREFIX_VEX_2D) },
7319 { PREFIX_TABLE (PREFIX_VEX_2E) },
7320 { PREFIX_TABLE (PREFIX_VEX_2F) },
7321 /* 30 */
7322 { Bad_Opcode },
7323 { Bad_Opcode },
7324 { Bad_Opcode },
7325 { Bad_Opcode },
7326 { Bad_Opcode },
7327 { Bad_Opcode },
7328 { Bad_Opcode },
7329 { Bad_Opcode },
7330 /* 38 */
7331 { Bad_Opcode },
7332 { Bad_Opcode },
7333 { Bad_Opcode },
7334 { Bad_Opcode },
7335 { Bad_Opcode },
7336 { Bad_Opcode },
7337 { Bad_Opcode },
7338 { Bad_Opcode },
7339 /* 40 */
7340 { Bad_Opcode },
7341 { Bad_Opcode },
7342 { Bad_Opcode },
7343 { Bad_Opcode },
7344 { Bad_Opcode },
7345 { Bad_Opcode },
7346 { Bad_Opcode },
7347 { Bad_Opcode },
7348 /* 48 */
7349 { Bad_Opcode },
7350 { Bad_Opcode },
7351 { Bad_Opcode },
7352 { Bad_Opcode },
7353 { Bad_Opcode },
7354 { Bad_Opcode },
7355 { Bad_Opcode },
7356 { Bad_Opcode },
7357 /* 50 */
7358 { MOD_TABLE (MOD_VEX_50) },
7359 { PREFIX_TABLE (PREFIX_VEX_51) },
7360 { PREFIX_TABLE (PREFIX_VEX_52) },
7361 { PREFIX_TABLE (PREFIX_VEX_53) },
7362 { "vandpX", { XM, Vex, EXx } },
7363 { "vandnpX", { XM, Vex, EXx } },
7364 { "vorpX", { XM, Vex, EXx } },
7365 { "vxorpX", { XM, Vex, EXx } },
7366 /* 58 */
7367 { PREFIX_TABLE (PREFIX_VEX_58) },
7368 { PREFIX_TABLE (PREFIX_VEX_59) },
7369 { PREFIX_TABLE (PREFIX_VEX_5A) },
7370 { PREFIX_TABLE (PREFIX_VEX_5B) },
7371 { PREFIX_TABLE (PREFIX_VEX_5C) },
7372 { PREFIX_TABLE (PREFIX_VEX_5D) },
7373 { PREFIX_TABLE (PREFIX_VEX_5E) },
7374 { PREFIX_TABLE (PREFIX_VEX_5F) },
7375 /* 60 */
7376 { PREFIX_TABLE (PREFIX_VEX_60) },
7377 { PREFIX_TABLE (PREFIX_VEX_61) },
7378 { PREFIX_TABLE (PREFIX_VEX_62) },
7379 { PREFIX_TABLE (PREFIX_VEX_63) },
7380 { PREFIX_TABLE (PREFIX_VEX_64) },
7381 { PREFIX_TABLE (PREFIX_VEX_65) },
7382 { PREFIX_TABLE (PREFIX_VEX_66) },
7383 { PREFIX_TABLE (PREFIX_VEX_67) },
7384 /* 68 */
7385 { PREFIX_TABLE (PREFIX_VEX_68) },
7386 { PREFIX_TABLE (PREFIX_VEX_69) },
7387 { PREFIX_TABLE (PREFIX_VEX_6A) },
7388 { PREFIX_TABLE (PREFIX_VEX_6B) },
7389 { PREFIX_TABLE (PREFIX_VEX_6C) },
7390 { PREFIX_TABLE (PREFIX_VEX_6D) },
7391 { PREFIX_TABLE (PREFIX_VEX_6E) },
7392 { PREFIX_TABLE (PREFIX_VEX_6F) },
7393 /* 70 */
7394 { PREFIX_TABLE (PREFIX_VEX_70) },
7395 { REG_TABLE (REG_VEX_71) },
7396 { REG_TABLE (REG_VEX_72) },
7397 { REG_TABLE (REG_VEX_73) },
7398 { PREFIX_TABLE (PREFIX_VEX_74) },
7399 { PREFIX_TABLE (PREFIX_VEX_75) },
7400 { PREFIX_TABLE (PREFIX_VEX_76) },
7401 { PREFIX_TABLE (PREFIX_VEX_77) },
7402 /* 78 */
7403 { Bad_Opcode },
7404 { Bad_Opcode },
7405 { Bad_Opcode },
7406 { Bad_Opcode },
7407 { PREFIX_TABLE (PREFIX_VEX_7C) },
7408 { PREFIX_TABLE (PREFIX_VEX_7D) },
7409 { PREFIX_TABLE (PREFIX_VEX_7E) },
7410 { PREFIX_TABLE (PREFIX_VEX_7F) },
7411 /* 80 */
7412 { Bad_Opcode },
7413 { Bad_Opcode },
7414 { Bad_Opcode },
7415 { Bad_Opcode },
7416 { Bad_Opcode },
7417 { Bad_Opcode },
7418 { Bad_Opcode },
7419 { Bad_Opcode },
7420 /* 88 */
7421 { Bad_Opcode },
7422 { Bad_Opcode },
7423 { Bad_Opcode },
7424 { Bad_Opcode },
7425 { Bad_Opcode },
7426 { Bad_Opcode },
7427 { Bad_Opcode },
7428 { Bad_Opcode },
7429 /* 90 */
7430 { Bad_Opcode },
7431 { Bad_Opcode },
7432 { Bad_Opcode },
7433 { Bad_Opcode },
7434 { Bad_Opcode },
7435 { Bad_Opcode },
7436 { Bad_Opcode },
7437 { Bad_Opcode },
7438 /* 98 */
7439 { Bad_Opcode },
7440 { Bad_Opcode },
7441 { Bad_Opcode },
7442 { Bad_Opcode },
7443 { Bad_Opcode },
7444 { Bad_Opcode },
7445 { Bad_Opcode },
7446 { Bad_Opcode },
7447 /* a0 */
7448 { Bad_Opcode },
7449 { Bad_Opcode },
7450 { Bad_Opcode },
7451 { Bad_Opcode },
7452 { Bad_Opcode },
7453 { Bad_Opcode },
7454 { Bad_Opcode },
7455 { Bad_Opcode },
7456 /* a8 */
7457 { Bad_Opcode },
7458 { Bad_Opcode },
7459 { Bad_Opcode },
7460 { Bad_Opcode },
7461 { Bad_Opcode },
7462 { Bad_Opcode },
7463 { REG_TABLE (REG_VEX_AE) },
7464 { Bad_Opcode },
7465 /* b0 */
7466 { Bad_Opcode },
7467 { Bad_Opcode },
7468 { Bad_Opcode },
7469 { Bad_Opcode },
7470 { Bad_Opcode },
7471 { Bad_Opcode },
7472 { Bad_Opcode },
7473 { Bad_Opcode },
7474 /* b8 */
7475 { Bad_Opcode },
7476 { Bad_Opcode },
7477 { Bad_Opcode },
7478 { Bad_Opcode },
7479 { Bad_Opcode },
7480 { Bad_Opcode },
7481 { Bad_Opcode },
7482 { Bad_Opcode },
7483 /* c0 */
7484 { Bad_Opcode },
7485 { Bad_Opcode },
7486 { PREFIX_TABLE (PREFIX_VEX_C2) },
7487 { Bad_Opcode },
7488 { PREFIX_TABLE (PREFIX_VEX_C4) },
7489 { PREFIX_TABLE (PREFIX_VEX_C5) },
7490 { "vshufpX", { XM, Vex, EXx, Ib } },
7491 { Bad_Opcode },
7492 /* c8 */
7493 { Bad_Opcode },
7494 { Bad_Opcode },
7495 { Bad_Opcode },
7496 { Bad_Opcode },
7497 { Bad_Opcode },
7498 { Bad_Opcode },
7499 { Bad_Opcode },
7500 { Bad_Opcode },
7501 /* d0 */
7502 { PREFIX_TABLE (PREFIX_VEX_D0) },
7503 { PREFIX_TABLE (PREFIX_VEX_D1) },
7504 { PREFIX_TABLE (PREFIX_VEX_D2) },
7505 { PREFIX_TABLE (PREFIX_VEX_D3) },
7506 { PREFIX_TABLE (PREFIX_VEX_D4) },
7507 { PREFIX_TABLE (PREFIX_VEX_D5) },
7508 { PREFIX_TABLE (PREFIX_VEX_D6) },
7509 { PREFIX_TABLE (PREFIX_VEX_D7) },
7510 /* d8 */
7511 { PREFIX_TABLE (PREFIX_VEX_D8) },
7512 { PREFIX_TABLE (PREFIX_VEX_D9) },
7513 { PREFIX_TABLE (PREFIX_VEX_DA) },
7514 { PREFIX_TABLE (PREFIX_VEX_DB) },
7515 { PREFIX_TABLE (PREFIX_VEX_DC) },
7516 { PREFIX_TABLE (PREFIX_VEX_DD) },
7517 { PREFIX_TABLE (PREFIX_VEX_DE) },
7518 { PREFIX_TABLE (PREFIX_VEX_DF) },
7519 /* e0 */
7520 { PREFIX_TABLE (PREFIX_VEX_E0) },
7521 { PREFIX_TABLE (PREFIX_VEX_E1) },
7522 { PREFIX_TABLE (PREFIX_VEX_E2) },
7523 { PREFIX_TABLE (PREFIX_VEX_E3) },
7524 { PREFIX_TABLE (PREFIX_VEX_E4) },
7525 { PREFIX_TABLE (PREFIX_VEX_E5) },
7526 { PREFIX_TABLE (PREFIX_VEX_E6) },
7527 { PREFIX_TABLE (PREFIX_VEX_E7) },
7528 /* e8 */
7529 { PREFIX_TABLE (PREFIX_VEX_E8) },
7530 { PREFIX_TABLE (PREFIX_VEX_E9) },
7531 { PREFIX_TABLE (PREFIX_VEX_EA) },
7532 { PREFIX_TABLE (PREFIX_VEX_EB) },
7533 { PREFIX_TABLE (PREFIX_VEX_EC) },
7534 { PREFIX_TABLE (PREFIX_VEX_ED) },
7535 { PREFIX_TABLE (PREFIX_VEX_EE) },
7536 { PREFIX_TABLE (PREFIX_VEX_EF) },
7537 /* f0 */
7538 { PREFIX_TABLE (PREFIX_VEX_F0) },
7539 { PREFIX_TABLE (PREFIX_VEX_F1) },
7540 { PREFIX_TABLE (PREFIX_VEX_F2) },
7541 { PREFIX_TABLE (PREFIX_VEX_F3) },
7542 { PREFIX_TABLE (PREFIX_VEX_F4) },
7543 { PREFIX_TABLE (PREFIX_VEX_F5) },
7544 { PREFIX_TABLE (PREFIX_VEX_F6) },
7545 { PREFIX_TABLE (PREFIX_VEX_F7) },
7546 /* f8 */
7547 { PREFIX_TABLE (PREFIX_VEX_F8) },
7548 { PREFIX_TABLE (PREFIX_VEX_F9) },
7549 { PREFIX_TABLE (PREFIX_VEX_FA) },
7550 { PREFIX_TABLE (PREFIX_VEX_FB) },
7551 { PREFIX_TABLE (PREFIX_VEX_FC) },
7552 { PREFIX_TABLE (PREFIX_VEX_FD) },
7553 { PREFIX_TABLE (PREFIX_VEX_FE) },
7554 { Bad_Opcode },
7555 },
7556 /* VEX_0F38 */
7557 {
7558 /* 00 */
7559 { PREFIX_TABLE (PREFIX_VEX_3800) },
7560 { PREFIX_TABLE (PREFIX_VEX_3801) },
7561 { PREFIX_TABLE (PREFIX_VEX_3802) },
7562 { PREFIX_TABLE (PREFIX_VEX_3803) },
7563 { PREFIX_TABLE (PREFIX_VEX_3804) },
7564 { PREFIX_TABLE (PREFIX_VEX_3805) },
7565 { PREFIX_TABLE (PREFIX_VEX_3806) },
7566 { PREFIX_TABLE (PREFIX_VEX_3807) },
7567 /* 08 */
7568 { PREFIX_TABLE (PREFIX_VEX_3808) },
7569 { PREFIX_TABLE (PREFIX_VEX_3809) },
7570 { PREFIX_TABLE (PREFIX_VEX_380A) },
7571 { PREFIX_TABLE (PREFIX_VEX_380B) },
7572 { PREFIX_TABLE (PREFIX_VEX_380C) },
7573 { PREFIX_TABLE (PREFIX_VEX_380D) },
7574 { PREFIX_TABLE (PREFIX_VEX_380E) },
7575 { PREFIX_TABLE (PREFIX_VEX_380F) },
7576 /* 10 */
7577 { Bad_Opcode },
7578 { Bad_Opcode },
7579 { Bad_Opcode },
7580 { PREFIX_TABLE (PREFIX_VEX_3813) },
7581 { Bad_Opcode },
7582 { Bad_Opcode },
7583 { Bad_Opcode },
7584 { PREFIX_TABLE (PREFIX_VEX_3817) },
7585 /* 18 */
7586 { PREFIX_TABLE (PREFIX_VEX_3818) },
7587 { PREFIX_TABLE (PREFIX_VEX_3819) },
7588 { PREFIX_TABLE (PREFIX_VEX_381A) },
7589 { Bad_Opcode },
7590 { PREFIX_TABLE (PREFIX_VEX_381C) },
7591 { PREFIX_TABLE (PREFIX_VEX_381D) },
7592 { PREFIX_TABLE (PREFIX_VEX_381E) },
7593 { Bad_Opcode },
7594 /* 20 */
7595 { PREFIX_TABLE (PREFIX_VEX_3820) },
7596 { PREFIX_TABLE (PREFIX_VEX_3821) },
7597 { PREFIX_TABLE (PREFIX_VEX_3822) },
7598 { PREFIX_TABLE (PREFIX_VEX_3823) },
7599 { PREFIX_TABLE (PREFIX_VEX_3824) },
7600 { PREFIX_TABLE (PREFIX_VEX_3825) },
7601 { Bad_Opcode },
7602 { Bad_Opcode },
7603 /* 28 */
7604 { PREFIX_TABLE (PREFIX_VEX_3828) },
7605 { PREFIX_TABLE (PREFIX_VEX_3829) },
7606 { PREFIX_TABLE (PREFIX_VEX_382A) },
7607 { PREFIX_TABLE (PREFIX_VEX_382B) },
7608 { PREFIX_TABLE (PREFIX_VEX_382C) },
7609 { PREFIX_TABLE (PREFIX_VEX_382D) },
7610 { PREFIX_TABLE (PREFIX_VEX_382E) },
7611 { PREFIX_TABLE (PREFIX_VEX_382F) },
7612 /* 30 */
7613 { PREFIX_TABLE (PREFIX_VEX_3830) },
7614 { PREFIX_TABLE (PREFIX_VEX_3831) },
7615 { PREFIX_TABLE (PREFIX_VEX_3832) },
7616 { PREFIX_TABLE (PREFIX_VEX_3833) },
7617 { PREFIX_TABLE (PREFIX_VEX_3834) },
7618 { PREFIX_TABLE (PREFIX_VEX_3835) },
7619 { Bad_Opcode },
7620 { PREFIX_TABLE (PREFIX_VEX_3837) },
7621 /* 38 */
7622 { PREFIX_TABLE (PREFIX_VEX_3838) },
7623 { PREFIX_TABLE (PREFIX_VEX_3839) },
7624 { PREFIX_TABLE (PREFIX_VEX_383A) },
7625 { PREFIX_TABLE (PREFIX_VEX_383B) },
7626 { PREFIX_TABLE (PREFIX_VEX_383C) },
7627 { PREFIX_TABLE (PREFIX_VEX_383D) },
7628 { PREFIX_TABLE (PREFIX_VEX_383E) },
7629 { PREFIX_TABLE (PREFIX_VEX_383F) },
7630 /* 40 */
7631 { PREFIX_TABLE (PREFIX_VEX_3840) },
7632 { PREFIX_TABLE (PREFIX_VEX_3841) },
7633 { Bad_Opcode },
7634 { Bad_Opcode },
7635 { Bad_Opcode },
7636 { Bad_Opcode },
7637 { Bad_Opcode },
7638 { Bad_Opcode },
7639 /* 48 */
7640 { Bad_Opcode },
7641 { Bad_Opcode },
7642 { Bad_Opcode },
7643 { Bad_Opcode },
7644 { Bad_Opcode },
7645 { Bad_Opcode },
7646 { Bad_Opcode },
7647 { Bad_Opcode },
7648 /* 50 */
7649 { Bad_Opcode },
7650 { Bad_Opcode },
7651 { Bad_Opcode },
7652 { Bad_Opcode },
7653 { Bad_Opcode },
7654 { Bad_Opcode },
7655 { Bad_Opcode },
7656 { Bad_Opcode },
7657 /* 58 */
7658 { Bad_Opcode },
7659 { Bad_Opcode },
7660 { Bad_Opcode },
7661 { Bad_Opcode },
7662 { Bad_Opcode },
7663 { Bad_Opcode },
7664 { Bad_Opcode },
7665 { Bad_Opcode },
7666 /* 60 */
7667 { Bad_Opcode },
7668 { Bad_Opcode },
7669 { Bad_Opcode },
7670 { Bad_Opcode },
7671 { Bad_Opcode },
7672 { Bad_Opcode },
7673 { Bad_Opcode },
7674 { Bad_Opcode },
7675 /* 68 */
7676 { Bad_Opcode },
7677 { Bad_Opcode },
7678 { Bad_Opcode },
7679 { Bad_Opcode },
7680 { Bad_Opcode },
7681 { Bad_Opcode },
7682 { Bad_Opcode },
7683 { Bad_Opcode },
7684 /* 70 */
7685 { Bad_Opcode },
7686 { Bad_Opcode },
7687 { Bad_Opcode },
7688 { Bad_Opcode },
7689 { Bad_Opcode },
7690 { Bad_Opcode },
7691 { Bad_Opcode },
7692 { Bad_Opcode },
7693 /* 78 */
7694 { Bad_Opcode },
7695 { Bad_Opcode },
7696 { Bad_Opcode },
7697 { Bad_Opcode },
7698 { Bad_Opcode },
7699 { Bad_Opcode },
7700 { Bad_Opcode },
7701 { Bad_Opcode },
7702 /* 80 */
7703 { Bad_Opcode },
7704 { Bad_Opcode },
7705 { Bad_Opcode },
7706 { Bad_Opcode },
7707 { Bad_Opcode },
7708 { Bad_Opcode },
7709 { Bad_Opcode },
7710 { Bad_Opcode },
7711 /* 88 */
7712 { Bad_Opcode },
7713 { Bad_Opcode },
7714 { Bad_Opcode },
7715 { Bad_Opcode },
7716 { Bad_Opcode },
7717 { Bad_Opcode },
7718 { Bad_Opcode },
7719 { Bad_Opcode },
7720 /* 90 */
7721 { Bad_Opcode },
7722 { Bad_Opcode },
7723 { Bad_Opcode },
7724 { Bad_Opcode },
7725 { Bad_Opcode },
7726 { Bad_Opcode },
7727 { PREFIX_TABLE (PREFIX_VEX_3896) },
7728 { PREFIX_TABLE (PREFIX_VEX_3897) },
7729 /* 98 */
7730 { PREFIX_TABLE (PREFIX_VEX_3898) },
7731 { PREFIX_TABLE (PREFIX_VEX_3899) },
7732 { PREFIX_TABLE (PREFIX_VEX_389A) },
7733 { PREFIX_TABLE (PREFIX_VEX_389B) },
7734 { PREFIX_TABLE (PREFIX_VEX_389C) },
7735 { PREFIX_TABLE (PREFIX_VEX_389D) },
7736 { PREFIX_TABLE (PREFIX_VEX_389E) },
7737 { PREFIX_TABLE (PREFIX_VEX_389F) },
7738 /* a0 */
7739 { Bad_Opcode },
7740 { Bad_Opcode },
7741 { Bad_Opcode },
7742 { Bad_Opcode },
7743 { Bad_Opcode },
7744 { Bad_Opcode },
7745 { PREFIX_TABLE (PREFIX_VEX_38A6) },
7746 { PREFIX_TABLE (PREFIX_VEX_38A7) },
7747 /* a8 */
7748 { PREFIX_TABLE (PREFIX_VEX_38A8) },
7749 { PREFIX_TABLE (PREFIX_VEX_38A9) },
7750 { PREFIX_TABLE (PREFIX_VEX_38AA) },
7751 { PREFIX_TABLE (PREFIX_VEX_38AB) },
7752 { PREFIX_TABLE (PREFIX_VEX_38AC) },
7753 { PREFIX_TABLE (PREFIX_VEX_38AD) },
7754 { PREFIX_TABLE (PREFIX_VEX_38AE) },
7755 { PREFIX_TABLE (PREFIX_VEX_38AF) },
7756 /* b0 */
7757 { Bad_Opcode },
7758 { Bad_Opcode },
7759 { Bad_Opcode },
7760 { Bad_Opcode },
7761 { Bad_Opcode },
7762 { Bad_Opcode },
7763 { PREFIX_TABLE (PREFIX_VEX_38B6) },
7764 { PREFIX_TABLE (PREFIX_VEX_38B7) },
7765 /* b8 */
7766 { PREFIX_TABLE (PREFIX_VEX_38B8) },
7767 { PREFIX_TABLE (PREFIX_VEX_38B9) },
7768 { PREFIX_TABLE (PREFIX_VEX_38BA) },
7769 { PREFIX_TABLE (PREFIX_VEX_38BB) },
7770 { PREFIX_TABLE (PREFIX_VEX_38BC) },
7771 { PREFIX_TABLE (PREFIX_VEX_38BD) },
7772 { PREFIX_TABLE (PREFIX_VEX_38BE) },
7773 { PREFIX_TABLE (PREFIX_VEX_38BF) },
7774 /* c0 */
7775 { Bad_Opcode },
7776 { Bad_Opcode },
7777 { Bad_Opcode },
7778 { Bad_Opcode },
7779 { Bad_Opcode },
7780 { Bad_Opcode },
7781 { Bad_Opcode },
7782 { Bad_Opcode },
7783 /* c8 */
7784 { Bad_Opcode },
7785 { Bad_Opcode },
7786 { Bad_Opcode },
7787 { Bad_Opcode },
7788 { Bad_Opcode },
7789 { Bad_Opcode },
7790 { Bad_Opcode },
7791 { Bad_Opcode },
7792 /* d0 */
7793 { Bad_Opcode },
7794 { Bad_Opcode },
7795 { Bad_Opcode },
7796 { Bad_Opcode },
7797 { Bad_Opcode },
7798 { Bad_Opcode },
7799 { Bad_Opcode },
7800 { Bad_Opcode },
7801 /* d8 */
7802 { Bad_Opcode },
7803 { Bad_Opcode },
7804 { Bad_Opcode },
7805 { PREFIX_TABLE (PREFIX_VEX_38DB) },
7806 { PREFIX_TABLE (PREFIX_VEX_38DC) },
7807 { PREFIX_TABLE (PREFIX_VEX_38DD) },
7808 { PREFIX_TABLE (PREFIX_VEX_38DE) },
7809 { PREFIX_TABLE (PREFIX_VEX_38DF) },
7810 /* e0 */
7811 { Bad_Opcode },
7812 { Bad_Opcode },
7813 { Bad_Opcode },
7814 { Bad_Opcode },
7815 { Bad_Opcode },
7816 { Bad_Opcode },
7817 { Bad_Opcode },
7818 { Bad_Opcode },
7819 /* e8 */
7820 { Bad_Opcode },
7821 { Bad_Opcode },
7822 { Bad_Opcode },
7823 { Bad_Opcode },
7824 { Bad_Opcode },
7825 { Bad_Opcode },
7826 { Bad_Opcode },
7827 { Bad_Opcode },
7828 /* f0 */
7829 { Bad_Opcode },
7830 { Bad_Opcode },
7831 { Bad_Opcode },
7832 { Bad_Opcode },
7833 { Bad_Opcode },
7834 { Bad_Opcode },
7835 { Bad_Opcode },
7836 { Bad_Opcode },
7837 /* f8 */
7838 { Bad_Opcode },
7839 { Bad_Opcode },
7840 { Bad_Opcode },
7841 { Bad_Opcode },
7842 { Bad_Opcode },
7843 { Bad_Opcode },
7844 { Bad_Opcode },
7845 { Bad_Opcode },
7846 },
7847 /* VEX_0F3A */
7848 {
7849 /* 00 */
7850 { Bad_Opcode },
7851 { Bad_Opcode },
7852 { Bad_Opcode },
7853 { Bad_Opcode },
7854 { PREFIX_TABLE (PREFIX_VEX_3A04) },
7855 { PREFIX_TABLE (PREFIX_VEX_3A05) },
7856 { PREFIX_TABLE (PREFIX_VEX_3A06) },
7857 { Bad_Opcode },
7858 /* 08 */
7859 { PREFIX_TABLE (PREFIX_VEX_3A08) },
7860 { PREFIX_TABLE (PREFIX_VEX_3A09) },
7861 { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7862 { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7863 { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7864 { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7865 { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7866 { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7867 /* 10 */
7868 { Bad_Opcode },
7869 { Bad_Opcode },
7870 { Bad_Opcode },
7871 { Bad_Opcode },
7872 { PREFIX_TABLE (PREFIX_VEX_3A14) },
7873 { PREFIX_TABLE (PREFIX_VEX_3A15) },
7874 { PREFIX_TABLE (PREFIX_VEX_3A16) },
7875 { PREFIX_TABLE (PREFIX_VEX_3A17) },
7876 /* 18 */
7877 { PREFIX_TABLE (PREFIX_VEX_3A18) },
7878 { PREFIX_TABLE (PREFIX_VEX_3A19) },
7879 { Bad_Opcode },
7880 { Bad_Opcode },
7881 { Bad_Opcode },
7882 { PREFIX_TABLE (PREFIX_VEX_3A1D) },
7883 { Bad_Opcode },
7884 { Bad_Opcode },
7885 /* 20 */
7886 { PREFIX_TABLE (PREFIX_VEX_3A20) },
7887 { PREFIX_TABLE (PREFIX_VEX_3A21) },
7888 { PREFIX_TABLE (PREFIX_VEX_3A22) },
7889 { Bad_Opcode },
7890 { Bad_Opcode },
7891 { Bad_Opcode },
7892 { Bad_Opcode },
7893 { Bad_Opcode },
7894 /* 28 */
7895 { Bad_Opcode },
7896 { Bad_Opcode },
7897 { Bad_Opcode },
7898 { Bad_Opcode },
7899 { Bad_Opcode },
7900 { Bad_Opcode },
7901 { Bad_Opcode },
7902 { Bad_Opcode },
7903 /* 30 */
7904 { Bad_Opcode },
7905 { Bad_Opcode },
7906 { Bad_Opcode },
7907 { Bad_Opcode },
7908 { Bad_Opcode },
7909 { Bad_Opcode },
7910 { Bad_Opcode },
7911 { Bad_Opcode },
7912 /* 38 */
7913 { Bad_Opcode },
7914 { Bad_Opcode },
7915 { Bad_Opcode },
7916 { Bad_Opcode },
7917 { Bad_Opcode },
7918 { Bad_Opcode },
7919 { Bad_Opcode },
7920 { Bad_Opcode },
7921 /* 40 */
7922 { PREFIX_TABLE (PREFIX_VEX_3A40) },
7923 { PREFIX_TABLE (PREFIX_VEX_3A41) },
7924 { PREFIX_TABLE (PREFIX_VEX_3A42) },
7925 { Bad_Opcode },
7926 { PREFIX_TABLE (PREFIX_VEX_3A44) },
7927 { Bad_Opcode },
7928 { Bad_Opcode },
7929 { Bad_Opcode },
7930 /* 48 */
7931 { PREFIX_TABLE (PREFIX_VEX_3A48) },
7932 { PREFIX_TABLE (PREFIX_VEX_3A49) },
7933 { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7934 { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7935 { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7936 { Bad_Opcode },
7937 { Bad_Opcode },
7938 { Bad_Opcode },
7939 /* 50 */
7940 { Bad_Opcode },
7941 { Bad_Opcode },
7942 { Bad_Opcode },
7943 { Bad_Opcode },
7944 { Bad_Opcode },
7945 { Bad_Opcode },
7946 { Bad_Opcode },
7947 { Bad_Opcode },
7948 /* 58 */
7949 { Bad_Opcode },
7950 { Bad_Opcode },
7951 { Bad_Opcode },
7952 { Bad_Opcode },
7953 { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7954 { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7955 { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7956 { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7957 /* 60 */
7958 { PREFIX_TABLE (PREFIX_VEX_3A60) },
7959 { PREFIX_TABLE (PREFIX_VEX_3A61) },
7960 { PREFIX_TABLE (PREFIX_VEX_3A62) },
7961 { PREFIX_TABLE (PREFIX_VEX_3A63) },
7962 { Bad_Opcode },
7963 { Bad_Opcode },
7964 { Bad_Opcode },
7965 { Bad_Opcode },
7966 /* 68 */
7967 { PREFIX_TABLE (PREFIX_VEX_3A68) },
7968 { PREFIX_TABLE (PREFIX_VEX_3A69) },
7969 { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7970 { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7971 { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7972 { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7973 { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7974 { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7975 /* 70 */
7976 { Bad_Opcode },
7977 { Bad_Opcode },
7978 { Bad_Opcode },
7979 { Bad_Opcode },
7980 { Bad_Opcode },
7981 { Bad_Opcode },
7982 { Bad_Opcode },
7983 { Bad_Opcode },
7984 /* 78 */
7985 { PREFIX_TABLE (PREFIX_VEX_3A78) },
7986 { PREFIX_TABLE (PREFIX_VEX_3A79) },
7987 { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7988 { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7989 { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7990 { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7991 { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7992 { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7993 /* 80 */
7994 { Bad_Opcode },
7995 { Bad_Opcode },
7996 { Bad_Opcode },
7997 { Bad_Opcode },
7998 { Bad_Opcode },
7999 { Bad_Opcode },
8000 { Bad_Opcode },
8001 { Bad_Opcode },
8002 /* 88 */
8003 { Bad_Opcode },
8004 { Bad_Opcode },
8005 { Bad_Opcode },
8006 { Bad_Opcode },
8007 { Bad_Opcode },
8008 { Bad_Opcode },
8009 { Bad_Opcode },
8010 { Bad_Opcode },
8011 /* 90 */
8012 { Bad_Opcode },
8013 { Bad_Opcode },
8014 { Bad_Opcode },
8015 { Bad_Opcode },
8016 { Bad_Opcode },
8017 { Bad_Opcode },
8018 { Bad_Opcode },
8019 { Bad_Opcode },
8020 /* 98 */
8021 { Bad_Opcode },
8022 { Bad_Opcode },
8023 { Bad_Opcode },
8024 { Bad_Opcode },
8025 { Bad_Opcode },
8026 { Bad_Opcode },
8027 { Bad_Opcode },
8028 { Bad_Opcode },
8029 /* a0 */
8030 { Bad_Opcode },
8031 { Bad_Opcode },
8032 { Bad_Opcode },
8033 { Bad_Opcode },
8034 { Bad_Opcode },
8035 { Bad_Opcode },
8036 { Bad_Opcode },
8037 { Bad_Opcode },
8038 /* a8 */
8039 { Bad_Opcode },
8040 { Bad_Opcode },
8041 { Bad_Opcode },
8042 { Bad_Opcode },
8043 { Bad_Opcode },
8044 { Bad_Opcode },
8045 { Bad_Opcode },
8046 { Bad_Opcode },
8047 /* b0 */
8048 { Bad_Opcode },
8049 { Bad_Opcode },
8050 { Bad_Opcode },
8051 { Bad_Opcode },
8052 { Bad_Opcode },
8053 { Bad_Opcode },
8054 { Bad_Opcode },
8055 { Bad_Opcode },
8056 /* b8 */
8057 { Bad_Opcode },
8058 { Bad_Opcode },
8059 { Bad_Opcode },
8060 { Bad_Opcode },
8061 { Bad_Opcode },
8062 { Bad_Opcode },
8063 { Bad_Opcode },
8064 { Bad_Opcode },
8065 /* c0 */
8066 { Bad_Opcode },
8067 { Bad_Opcode },
8068 { Bad_Opcode },
8069 { Bad_Opcode },
8070 { Bad_Opcode },
8071 { Bad_Opcode },
8072 { Bad_Opcode },
8073 { Bad_Opcode },
8074 /* c8 */
8075 { Bad_Opcode },
8076 { Bad_Opcode },
8077 { Bad_Opcode },
8078 { Bad_Opcode },
8079 { Bad_Opcode },
8080 { Bad_Opcode },
8081 { Bad_Opcode },
8082 { Bad_Opcode },
8083 /* d0 */
8084 { Bad_Opcode },
8085 { Bad_Opcode },
8086 { Bad_Opcode },
8087 { Bad_Opcode },
8088 { Bad_Opcode },
8089 { Bad_Opcode },
8090 { Bad_Opcode },
8091 { Bad_Opcode },
8092 /* d8 */
8093 { Bad_Opcode },
8094 { Bad_Opcode },
8095 { Bad_Opcode },
8096 { Bad_Opcode },
8097 { Bad_Opcode },
8098 { Bad_Opcode },
8099 { Bad_Opcode },
8100 { PREFIX_TABLE (PREFIX_VEX_3ADF) },
8101 /* e0 */
8102 { Bad_Opcode },
8103 { Bad_Opcode },
8104 { Bad_Opcode },
8105 { Bad_Opcode },
8106 { Bad_Opcode },
8107 { Bad_Opcode },
8108 { Bad_Opcode },
8109 { Bad_Opcode },
8110 /* e8 */
8111 { Bad_Opcode },
8112 { Bad_Opcode },
8113 { Bad_Opcode },
8114 { Bad_Opcode },
8115 { Bad_Opcode },
8116 { Bad_Opcode },
8117 { Bad_Opcode },
8118 { Bad_Opcode },
8119 /* f0 */
8120 { Bad_Opcode },
8121 { Bad_Opcode },
8122 { Bad_Opcode },
8123 { Bad_Opcode },
8124 { Bad_Opcode },
8125 { Bad_Opcode },
8126 { Bad_Opcode },
8127 { Bad_Opcode },
8128 /* f8 */
8129 { Bad_Opcode },
8130 { Bad_Opcode },
8131 { Bad_Opcode },
8132 { Bad_Opcode },
8133 { Bad_Opcode },
8134 { Bad_Opcode },
8135 { Bad_Opcode },
8136 { Bad_Opcode },
8137 },
8138};
8139
8140static const struct dis386 vex_len_table[][2] = {
8141 /* VEX_LEN_10_P_1 */
8142 {
8143 { VEX_W_TABLE (VEX_W_10_P_1) },
8144 { VEX_W_TABLE (VEX_W_10_P_1) },
8145 },
8146
8147 /* VEX_LEN_10_P_3 */
8148 {
8149 { VEX_W_TABLE (VEX_W_10_P_3) },
8150 { VEX_W_TABLE (VEX_W_10_P_3) },
8151 },
8152
8153 /* VEX_LEN_11_P_1 */
8154 {
8155 { VEX_W_TABLE (VEX_W_11_P_1) },
8156 { VEX_W_TABLE (VEX_W_11_P_1) },
8157 },
8158
8159 /* VEX_LEN_11_P_3 */
8160 {
8161 { VEX_W_TABLE (VEX_W_11_P_3) },
8162 { VEX_W_TABLE (VEX_W_11_P_3) },
8163 },
8164
8165 /* VEX_LEN_12_P_0_M_0 */
8166 {
8167 { VEX_W_TABLE (VEX_W_12_P_0_M_0) },
8168 },
8169
8170 /* VEX_LEN_12_P_0_M_1 */
8171 {
8172 { VEX_W_TABLE (VEX_W_12_P_0_M_1) },
8173 },
8174
8175 /* VEX_LEN_12_P_2 */
8176 {
8177 { VEX_W_TABLE (VEX_W_12_P_2) },
8178 },
8179
8180 /* VEX_LEN_13_M_0 */
8181 {
8182 { VEX_W_TABLE (VEX_W_13_M_0) },
8183 },
8184
8185 /* VEX_LEN_16_P_0_M_0 */
8186 {
8187 { VEX_W_TABLE (VEX_W_16_P_0_M_0) },
8188 },
8189
8190 /* VEX_LEN_16_P_0_M_1 */
8191 {
8192 { VEX_W_TABLE (VEX_W_16_P_0_M_1) },
8193 },
8194
8195 /* VEX_LEN_16_P_2 */
8196 {
8197 { VEX_W_TABLE (VEX_W_16_P_2) },
8198 },
8199
8200 /* VEX_LEN_17_M_0 */
8201 {
8202 { VEX_W_TABLE (VEX_W_17_M_0) },
8203 },
8204
8205 /* VEX_LEN_2A_P_1 */
8206 {
8207 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
8208 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
8209 },
8210
8211 /* VEX_LEN_2A_P_3 */
8212 {
8213 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
8214 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
8215 },
8216
8217 /* VEX_LEN_2C_P_1 */
8218 {
8219 { "vcvttss2siY", { Gv, EXdScalar } },
8220 { "vcvttss2siY", { Gv, EXdScalar } },
8221 },
8222
8223 /* VEX_LEN_2C_P_3 */
8224 {
8225 { "vcvttsd2siY", { Gv, EXqScalar } },
8226 { "vcvttsd2siY", { Gv, EXqScalar } },
8227 },
8228
8229 /* VEX_LEN_2D_P_1 */
8230 {
8231 { "vcvtss2siY", { Gv, EXdScalar } },
8232 { "vcvtss2siY", { Gv, EXdScalar } },
8233 },
8234
8235 /* VEX_LEN_2D_P_3 */
8236 {
8237 { "vcvtsd2siY", { Gv, EXqScalar } },
8238 { "vcvtsd2siY", { Gv, EXqScalar } },
8239 },
8240
8241 /* VEX_LEN_2E_P_0 */
8242 {
8243 { VEX_W_TABLE (VEX_W_2E_P_0) },
8244 { VEX_W_TABLE (VEX_W_2E_P_0) },
8245 },
8246
8247 /* VEX_LEN_2E_P_2 */
8248 {
8249 { VEX_W_TABLE (VEX_W_2E_P_2) },
8250 { VEX_W_TABLE (VEX_W_2E_P_2) },
8251 },
8252
8253 /* VEX_LEN_2F_P_0 */
8254 {
8255 { VEX_W_TABLE (VEX_W_2F_P_0) },
8256 { VEX_W_TABLE (VEX_W_2F_P_0) },
8257 },
8258
8259 /* VEX_LEN_2F_P_2 */
8260 {
8261 { VEX_W_TABLE (VEX_W_2F_P_2) },
8262 { VEX_W_TABLE (VEX_W_2F_P_2) },
8263 },
8264
8265 /* VEX_LEN_51_P_1 */
8266 {
8267 { VEX_W_TABLE (VEX_W_51_P_1) },
8268 { VEX_W_TABLE (VEX_W_51_P_1) },
8269 },
8270
8271 /* VEX_LEN_51_P_3 */
8272 {
8273 { VEX_W_TABLE (VEX_W_51_P_3) },
8274 { VEX_W_TABLE (VEX_W_51_P_3) },
8275 },
8276
8277 /* VEX_LEN_52_P_1 */
8278 {
8279 { VEX_W_TABLE (VEX_W_52_P_1) },
8280 { VEX_W_TABLE (VEX_W_52_P_1) },
8281 },
8282
8283 /* VEX_LEN_53_P_1 */
8284 {
8285 { VEX_W_TABLE (VEX_W_53_P_1) },
8286 { VEX_W_TABLE (VEX_W_53_P_1) },
8287 },
8288
8289 /* VEX_LEN_58_P_1 */
8290 {
8291 { VEX_W_TABLE (VEX_W_58_P_1) },
8292 { VEX_W_TABLE (VEX_W_58_P_1) },
8293 },
8294
8295 /* VEX_LEN_58_P_3 */
8296 {
8297 { VEX_W_TABLE (VEX_W_58_P_3) },
8298 { VEX_W_TABLE (VEX_W_58_P_3) },
8299 },
8300
8301 /* VEX_LEN_59_P_1 */
8302 {
8303 { VEX_W_TABLE (VEX_W_59_P_1) },
8304 { VEX_W_TABLE (VEX_W_59_P_1) },
8305 },
8306
8307 /* VEX_LEN_59_P_3 */
8308 {
8309 { VEX_W_TABLE (VEX_W_59_P_3) },
8310 { VEX_W_TABLE (VEX_W_59_P_3) },
8311 },
8312
8313 /* VEX_LEN_5A_P_1 */
8314 {
8315 { VEX_W_TABLE (VEX_W_5A_P_1) },
8316 { VEX_W_TABLE (VEX_W_5A_P_1) },
8317 },
8318
8319 /* VEX_LEN_5A_P_3 */
8320 {
8321 { VEX_W_TABLE (VEX_W_5A_P_3) },
8322 { VEX_W_TABLE (VEX_W_5A_P_3) },
8323 },
8324
8325 /* VEX_LEN_5C_P_1 */
8326 {
8327 { VEX_W_TABLE (VEX_W_5C_P_1) },
8328 { VEX_W_TABLE (VEX_W_5C_P_1) },
8329 },
8330
8331 /* VEX_LEN_5C_P_3 */
8332 {
8333 { VEX_W_TABLE (VEX_W_5C_P_3) },
8334 { VEX_W_TABLE (VEX_W_5C_P_3) },
8335 },
8336
8337 /* VEX_LEN_5D_P_1 */
8338 {
8339 { VEX_W_TABLE (VEX_W_5D_P_1) },
8340 { VEX_W_TABLE (VEX_W_5D_P_1) },
8341 },
8342
8343 /* VEX_LEN_5D_P_3 */
8344 {
8345 { VEX_W_TABLE (VEX_W_5D_P_3) },
8346 { VEX_W_TABLE (VEX_W_5D_P_3) },
8347 },
8348
8349 /* VEX_LEN_5E_P_1 */
8350 {
8351 { VEX_W_TABLE (VEX_W_5E_P_1) },
8352 { VEX_W_TABLE (VEX_W_5E_P_1) },
8353 },
8354
8355 /* VEX_LEN_5E_P_3 */
8356 {
8357 { VEX_W_TABLE (VEX_W_5E_P_3) },
8358 { VEX_W_TABLE (VEX_W_5E_P_3) },
8359 },
8360
8361 /* VEX_LEN_5F_P_1 */
8362 {
8363 { VEX_W_TABLE (VEX_W_5F_P_1) },
8364 { VEX_W_TABLE (VEX_W_5F_P_1) },
8365 },
8366
8367 /* VEX_LEN_5F_P_3 */
8368 {
8369 { VEX_W_TABLE (VEX_W_5F_P_3) },
8370 { VEX_W_TABLE (VEX_W_5F_P_3) },
8371 },
8372
8373 /* VEX_LEN_60_P_2 */
8374 {
8375 { VEX_W_TABLE (VEX_W_60_P_2) },
8376 },
8377
8378 /* VEX_LEN_61_P_2 */
8379 {
8380 { VEX_W_TABLE (VEX_W_61_P_2) },
8381 },
8382
8383 /* VEX_LEN_62_P_2 */
8384 {
8385 { VEX_W_TABLE (VEX_W_62_P_2) },
8386 },
8387
8388 /* VEX_LEN_63_P_2 */
8389 {
8390 { VEX_W_TABLE (VEX_W_63_P_2) },
8391 },
8392
8393 /* VEX_LEN_64_P_2 */
8394 {
8395 { VEX_W_TABLE (VEX_W_64_P_2) },
8396 },
8397
8398 /* VEX_LEN_65_P_2 */
8399 {
8400 { VEX_W_TABLE (VEX_W_65_P_2) },
8401 },
8402
8403 /* VEX_LEN_66_P_2 */
8404 {
8405 { VEX_W_TABLE (VEX_W_66_P_2) },
8406 },
8407
8408 /* VEX_LEN_67_P_2 */
8409 {
8410 { VEX_W_TABLE (VEX_W_67_P_2) },
8411 },
8412
8413 /* VEX_LEN_68_P_2 */
8414 {
8415 { VEX_W_TABLE (VEX_W_68_P_2) },
8416 },
8417
8418 /* VEX_LEN_69_P_2 */
8419 {
8420 { VEX_W_TABLE (VEX_W_69_P_2) },
8421 },
8422
8423 /* VEX_LEN_6A_P_2 */
8424 {
8425 { VEX_W_TABLE (VEX_W_6A_P_2) },
8426 },
8427
8428 /* VEX_LEN_6B_P_2 */
8429 {
8430 { VEX_W_TABLE (VEX_W_6B_P_2) },
8431 },
8432
8433 /* VEX_LEN_6C_P_2 */
8434 {
8435 { VEX_W_TABLE (VEX_W_6C_P_2) },
8436 },
8437
8438 /* VEX_LEN_6D_P_2 */
8439 {
8440 { VEX_W_TABLE (VEX_W_6D_P_2) },
8441 },
8442
8443 /* VEX_LEN_6E_P_2 */
8444 {
8445 { "vmovK", { XMScalar, Edq } },
8446 { "vmovK", { XMScalar, Edq } },
8447 },
8448
8449 /* VEX_LEN_70_P_1 */
8450 {
8451 { VEX_W_TABLE (VEX_W_70_P_1) },
8452 },
8453
8454 /* VEX_LEN_70_P_2 */
8455 {
8456 { VEX_W_TABLE (VEX_W_70_P_2) },
8457 },
8458
8459 /* VEX_LEN_70_P_3 */
8460 {
8461 { VEX_W_TABLE (VEX_W_70_P_3) },
8462 },
8463
8464 /* VEX_LEN_71_R_2_P_2 */
8465 {
8466 { VEX_W_TABLE (VEX_W_71_R_2_P_2) },
8467 },
8468
8469 /* VEX_LEN_71_R_4_P_2 */
8470 {
8471 { VEX_W_TABLE (VEX_W_71_R_4_P_2) },
8472 },
8473
8474 /* VEX_LEN_71_R_6_P_2 */
8475 {
8476 { VEX_W_TABLE (VEX_W_71_R_6_P_2) },
8477 },
8478
8479 /* VEX_LEN_72_R_2_P_2 */
8480 {
8481 { VEX_W_TABLE (VEX_W_72_R_2_P_2) },
8482 },
8483
8484 /* VEX_LEN_72_R_4_P_2 */
8485 {
8486 { VEX_W_TABLE (VEX_W_72_R_4_P_2) },
8487 },
8488
8489 /* VEX_LEN_72_R_6_P_2 */
8490 {
8491 { VEX_W_TABLE (VEX_W_72_R_6_P_2) },
8492 },
8493
8494 /* VEX_LEN_73_R_2_P_2 */
8495 {
8496 { VEX_W_TABLE (VEX_W_73_R_2_P_2) },
8497 },
8498
8499 /* VEX_LEN_73_R_3_P_2 */
8500 {
8501 { VEX_W_TABLE (VEX_W_73_R_3_P_2) },
8502 },
8503
8504 /* VEX_LEN_73_R_6_P_2 */
8505 {
8506 { VEX_W_TABLE (VEX_W_73_R_6_P_2) },
8507 },
8508
8509 /* VEX_LEN_73_R_7_P_2 */
8510 {
8511 { VEX_W_TABLE (VEX_W_73_R_7_P_2) },
8512 },
8513
8514 /* VEX_LEN_74_P_2 */
8515 {
8516 { VEX_W_TABLE (VEX_W_74_P_2) },
8517 },
8518
8519 /* VEX_LEN_75_P_2 */
8520 {
8521 { VEX_W_TABLE (VEX_W_75_P_2) },
8522 },
8523
8524 /* VEX_LEN_76_P_2 */
8525 {
8526 { VEX_W_TABLE (VEX_W_76_P_2) },
8527 },
8528
8529 /* VEX_LEN_7E_P_1 */
8530 {
8531 { VEX_W_TABLE (VEX_W_7E_P_1) },
8532 { VEX_W_TABLE (VEX_W_7E_P_1) },
8533 },
8534
8535 /* VEX_LEN_7E_P_2 */
8536 {
8537 { "vmovK", { Edq, XMScalar } },
8538 { "vmovK", { Edq, XMScalar } },
8539 },
8540
8541 /* VEX_LEN_AE_R_2_M_0 */
8542 {
8543 { VEX_W_TABLE (VEX_W_AE_R_2_M_0) },
8544 },
8545
8546 /* VEX_LEN_AE_R_3_M_0 */
8547 {
8548 { VEX_W_TABLE (VEX_W_AE_R_3_M_0) },
8549 },
8550
8551 /* VEX_LEN_C2_P_1 */
8552 {
8553 { VEX_W_TABLE (VEX_W_C2_P_1) },
8554 { VEX_W_TABLE (VEX_W_C2_P_1) },
8555 },
8556
8557 /* VEX_LEN_C2_P_3 */
8558 {
8559 { VEX_W_TABLE (VEX_W_C2_P_3) },
8560 { VEX_W_TABLE (VEX_W_C2_P_3) },
8561 },
8562
8563 /* VEX_LEN_C4_P_2 */
8564 {
8565 { VEX_W_TABLE (VEX_W_C4_P_2) },
8566 },
8567
8568 /* VEX_LEN_C5_P_2 */
8569 {
8570 { VEX_W_TABLE (VEX_W_C5_P_2) },
8571 },
8572
8573 /* VEX_LEN_D1_P_2 */
8574 {
8575 { VEX_W_TABLE (VEX_W_D1_P_2) },
8576 },
8577
8578 /* VEX_LEN_D2_P_2 */
8579 {
8580 { VEX_W_TABLE (VEX_W_D2_P_2) },
8581 },
8582
8583 /* VEX_LEN_D3_P_2 */
8584 {
8585 { VEX_W_TABLE (VEX_W_D3_P_2) },
8586 },
8587
8588 /* VEX_LEN_D4_P_2 */
8589 {
8590 { VEX_W_TABLE (VEX_W_D4_P_2) },
8591 },
8592
8593 /* VEX_LEN_D5_P_2 */
8594 {
8595 { VEX_W_TABLE (VEX_W_D5_P_2) },
8596 },
8597
8598 /* VEX_LEN_D6_P_2 */
8599 {
8600 { VEX_W_TABLE (VEX_W_D6_P_2) },
8601 { VEX_W_TABLE (VEX_W_D6_P_2) },
8602 },
8603
8604 /* VEX_LEN_D7_P_2_M_1 */
8605 {
8606 { VEX_W_TABLE (VEX_W_D7_P_2_M_1) },
8607 },
8608
8609 /* VEX_LEN_D8_P_2 */
8610 {
8611 { VEX_W_TABLE (VEX_W_D8_P_2) },
8612 },
8613
8614 /* VEX_LEN_D9_P_2 */
8615 {
8616 { VEX_W_TABLE (VEX_W_D9_P_2) },
8617 },
8618
8619 /* VEX_LEN_DA_P_2 */
8620 {
8621 { VEX_W_TABLE (VEX_W_DA_P_2) },
8622 },
8623
8624 /* VEX_LEN_DB_P_2 */
8625 {
8626 { VEX_W_TABLE (VEX_W_DB_P_2) },
8627 },
8628
8629 /* VEX_LEN_DC_P_2 */
8630 {
8631 { VEX_W_TABLE (VEX_W_DC_P_2) },
8632 },
8633
8634 /* VEX_LEN_DD_P_2 */
8635 {
8636 { VEX_W_TABLE (VEX_W_DD_P_2) },
8637 },
8638
8639 /* VEX_LEN_DE_P_2 */
8640 {
8641 { VEX_W_TABLE (VEX_W_DE_P_2) },
8642 },
8643
8644 /* VEX_LEN_DF_P_2 */
8645 {
8646 { VEX_W_TABLE (VEX_W_DF_P_2) },
8647 },
8648
8649 /* VEX_LEN_E0_P_2 */
8650 {
8651 { VEX_W_TABLE (VEX_W_E0_P_2) },
8652 },
8653
8654 /* VEX_LEN_E1_P_2 */
8655 {
8656 { VEX_W_TABLE (VEX_W_E1_P_2) },
8657 },
8658
8659 /* VEX_LEN_E2_P_2 */
8660 {
8661 { VEX_W_TABLE (VEX_W_E2_P_2) },
8662 },
8663
8664 /* VEX_LEN_E3_P_2 */
8665 {
8666 { VEX_W_TABLE (VEX_W_E3_P_2) },
8667 },
8668
8669 /* VEX_LEN_E4_P_2 */
8670 {
8671 { VEX_W_TABLE (VEX_W_E4_P_2) },
8672 },
8673
8674 /* VEX_LEN_E5_P_2 */
8675 {
8676 { VEX_W_TABLE (VEX_W_E5_P_2) },
8677 },
8678
8679 /* VEX_LEN_E8_P_2 */
8680 {
8681 { VEX_W_TABLE (VEX_W_E8_P_2) },
8682 },
8683
8684 /* VEX_LEN_E9_P_2 */
8685 {
8686 { VEX_W_TABLE (VEX_W_E9_P_2) },
8687 },
8688
8689 /* VEX_LEN_EA_P_2 */
8690 {
8691 { VEX_W_TABLE (VEX_W_EA_P_2) },
8692 },
8693
8694 /* VEX_LEN_EB_P_2 */
8695 {
8696 { VEX_W_TABLE (VEX_W_EB_P_2) },
8697 },
8698
8699 /* VEX_LEN_EC_P_2 */
8700 {
8701 { VEX_W_TABLE (VEX_W_EC_P_2) },
8702 },
8703
8704 /* VEX_LEN_ED_P_2 */
8705 {
8706 { VEX_W_TABLE (VEX_W_ED_P_2) },
8707 },
8708
8709 /* VEX_LEN_EE_P_2 */
8710 {
8711 { VEX_W_TABLE (VEX_W_EE_P_2) },
8712 },
8713
8714 /* VEX_LEN_EF_P_2 */
8715 {
8716 { VEX_W_TABLE (VEX_W_EF_P_2) },
8717 },
8718
8719 /* VEX_LEN_F1_P_2 */
8720 {
8721 { VEX_W_TABLE (VEX_W_F1_P_2) },
8722 },
8723
8724 /* VEX_LEN_F2_P_2 */
8725 {
8726 { VEX_W_TABLE (VEX_W_F2_P_2) },
8727 },
8728
8729 /* VEX_LEN_F3_P_2 */
8730 {
8731 { VEX_W_TABLE (VEX_W_F3_P_2) },
8732 },
8733
8734 /* VEX_LEN_F4_P_2 */
8735 {
8736 { VEX_W_TABLE (VEX_W_F4_P_2) },
8737 },
8738
8739 /* VEX_LEN_F5_P_2 */
8740 {
8741 { VEX_W_TABLE (VEX_W_F5_P_2) },
8742 },
8743
8744 /* VEX_LEN_F6_P_2 */
8745 {
8746 { VEX_W_TABLE (VEX_W_F6_P_2) },
8747 },
8748
8749 /* VEX_LEN_F7_P_2 */
8750 {
8751 { VEX_W_TABLE (VEX_W_F7_P_2) },
8752 },
8753
8754 /* VEX_LEN_F8_P_2 */
8755 {
8756 { VEX_W_TABLE (VEX_W_F8_P_2) },
8757 },
8758
8759 /* VEX_LEN_F9_P_2 */
8760 {
8761 { VEX_W_TABLE (VEX_W_F9_P_2) },
8762 },
8763
8764 /* VEX_LEN_FA_P_2 */
8765 {
8766 { VEX_W_TABLE (VEX_W_FA_P_2) },
8767 },
8768
8769 /* VEX_LEN_FB_P_2 */
8770 {
8771 { VEX_W_TABLE (VEX_W_FB_P_2) },
8772 },
8773
8774 /* VEX_LEN_FC_P_2 */
8775 {
8776 { VEX_W_TABLE (VEX_W_FC_P_2) },
8777 },
8778
8779 /* VEX_LEN_FD_P_2 */
8780 {
8781 { VEX_W_TABLE (VEX_W_FD_P_2) },
8782 },
8783
8784 /* VEX_LEN_FE_P_2 */
8785 {
8786 { VEX_W_TABLE (VEX_W_FE_P_2) },
8787 },
8788
8789 /* VEX_LEN_3800_P_2 */
8790 {
8791 { VEX_W_TABLE (VEX_W_3800_P_2) },
8792 },
8793
8794 /* VEX_LEN_3801_P_2 */
8795 {
8796 { VEX_W_TABLE (VEX_W_3801_P_2) },
8797 },
8798
8799 /* VEX_LEN_3802_P_2 */
8800 {
8801 { VEX_W_TABLE (VEX_W_3802_P_2) },
8802 },
8803
8804 /* VEX_LEN_3803_P_2 */
8805 {
8806 { VEX_W_TABLE (VEX_W_3803_P_2) },
8807 },
8808
8809 /* VEX_LEN_3804_P_2 */
8810 {
8811 { VEX_W_TABLE (VEX_W_3804_P_2) },
8812 },
8813
8814 /* VEX_LEN_3805_P_2 */
8815 {
8816 { VEX_W_TABLE (VEX_W_3805_P_2) },
8817 },
8818
8819 /* VEX_LEN_3806_P_2 */
8820 {
8821 { VEX_W_TABLE (VEX_W_3806_P_2) },
8822 },
8823
8824 /* VEX_LEN_3807_P_2 */
8825 {
8826 { VEX_W_TABLE (VEX_W_3807_P_2) },
8827 },
8828
8829 /* VEX_LEN_3808_P_2 */
8830 {
8831 { VEX_W_TABLE (VEX_W_3808_P_2) },
8832 },
8833
8834 /* VEX_LEN_3809_P_2 */
8835 {
8836 { VEX_W_TABLE (VEX_W_3809_P_2) },
8837 },
8838
8839 /* VEX_LEN_380A_P_2 */
8840 {
8841 { VEX_W_TABLE (VEX_W_380A_P_2) },
8842 },
8843
8844 /* VEX_LEN_380B_P_2 */
8845 {
8846 { VEX_W_TABLE (VEX_W_380B_P_2) },
8847 },
8848
8849 /* VEX_LEN_3819_P_2_M_0 */
8850 {
8851 { Bad_Opcode },
8852 { VEX_W_TABLE (VEX_W_3819_P_2_M_0) },
8853 },
8854
8855 /* VEX_LEN_381A_P_2_M_0 */
8856 {
8857 { Bad_Opcode },
8858 { VEX_W_TABLE (VEX_W_381A_P_2_M_0) },
8859 },
8860
8861 /* VEX_LEN_381C_P_2 */
8862 {
8863 { VEX_W_TABLE (VEX_W_381C_P_2) },
8864 },
8865
8866 /* VEX_LEN_381D_P_2 */
8867 {
8868 { VEX_W_TABLE (VEX_W_381D_P_2) },
8869 },
8870
8871 /* VEX_LEN_381E_P_2 */
8872 {
8873 { VEX_W_TABLE (VEX_W_381E_P_2) },
8874 },
8875
8876 /* VEX_LEN_3820_P_2 */
8877 {
8878 { VEX_W_TABLE (VEX_W_3820_P_2) },
8879 },
8880
8881 /* VEX_LEN_3821_P_2 */
8882 {
8883 { VEX_W_TABLE (VEX_W_3821_P_2) },
8884 },
8885
8886 /* VEX_LEN_3822_P_2 */
8887 {
8888 { VEX_W_TABLE (VEX_W_3822_P_2) },
8889 },
8890
8891 /* VEX_LEN_3823_P_2 */
8892 {
8893 { VEX_W_TABLE (VEX_W_3823_P_2) },
8894 },
8895
8896 /* VEX_LEN_3824_P_2 */
8897 {
8898 { VEX_W_TABLE (VEX_W_3824_P_2) },
8899 },
8900
8901 /* VEX_LEN_3825_P_2 */
8902 {
8903 { VEX_W_TABLE (VEX_W_3825_P_2) },
8904 },
8905
8906 /* VEX_LEN_3828_P_2 */
8907 {
8908 { VEX_W_TABLE (VEX_W_3828_P_2) },
8909 },
8910
8911 /* VEX_LEN_3829_P_2 */
8912 {
8913 { VEX_W_TABLE (VEX_W_3829_P_2) },
8914 },
8915
8916 /* VEX_LEN_382A_P_2_M_0 */
8917 {
8918 { VEX_W_TABLE (VEX_W_382A_P_2_M_0) },
8919 },
8920
8921 /* VEX_LEN_382B_P_2 */
8922 {
8923 { VEX_W_TABLE (VEX_W_382B_P_2) },
8924 },
8925
8926 /* VEX_LEN_3830_P_2 */
8927 {
8928 { VEX_W_TABLE (VEX_W_3830_P_2) },
8929 },
8930
8931 /* VEX_LEN_3831_P_2 */
8932 {
8933 { VEX_W_TABLE (VEX_W_3831_P_2) },
8934 },
8935
8936 /* VEX_LEN_3832_P_2 */
8937 {
8938 { VEX_W_TABLE (VEX_W_3832_P_2) },
8939 },
8940
8941 /* VEX_LEN_3833_P_2 */
8942 {
8943 { VEX_W_TABLE (VEX_W_3833_P_2) },
8944 },
8945
8946 /* VEX_LEN_3834_P_2 */
8947 {
8948 { VEX_W_TABLE (VEX_W_3834_P_2) },
8949 },
8950
8951 /* VEX_LEN_3835_P_2 */
8952 {
8953 { VEX_W_TABLE (VEX_W_3835_P_2) },
8954 },
8955
8956 /* VEX_LEN_3837_P_2 */
8957 {
8958 { VEX_W_TABLE (VEX_W_3837_P_2) },
8959 },
8960
8961 /* VEX_LEN_3838_P_2 */
8962 {
8963 { VEX_W_TABLE (VEX_W_3838_P_2) },
8964 },
8965
8966 /* VEX_LEN_3839_P_2 */
8967 {
8968 { VEX_W_TABLE (VEX_W_3839_P_2) },
8969 },
8970
8971 /* VEX_LEN_383A_P_2 */
8972 {
8973 { VEX_W_TABLE (VEX_W_383A_P_2) },
8974 },
8975
8976 /* VEX_LEN_383B_P_2 */
8977 {
8978 { VEX_W_TABLE (VEX_W_383B_P_2) },
8979 },
8980
8981 /* VEX_LEN_383C_P_2 */
8982 {
8983 { VEX_W_TABLE (VEX_W_383C_P_2) },
8984 },
8985
8986 /* VEX_LEN_383D_P_2 */
8987 {
8988 { VEX_W_TABLE (VEX_W_383D_P_2) },
8989 },
8990
8991 /* VEX_LEN_383E_P_2 */
8992 {
8993 { VEX_W_TABLE (VEX_W_383E_P_2) },
8994 },
8995
8996 /* VEX_LEN_383F_P_2 */
8997 {
8998 { VEX_W_TABLE (VEX_W_383F_P_2) },
8999 },
9000
9001 /* VEX_LEN_3840_P_2 */
9002 {
9003 { VEX_W_TABLE (VEX_W_3840_P_2) },
9004 },
9005
9006 /* VEX_LEN_3841_P_2 */
9007 {
9008 { VEX_W_TABLE (VEX_W_3841_P_2) },
9009 },
9010
9011 /* VEX_LEN_38DB_P_2 */
9012 {
9013 { VEX_W_TABLE (VEX_W_38DB_P_2) },
9014 },
9015
9016 /* VEX_LEN_38DC_P_2 */
9017 {
9018 { VEX_W_TABLE (VEX_W_38DC_P_2) },
9019 },
9020
9021 /* VEX_LEN_38DD_P_2 */
9022 {
9023 { VEX_W_TABLE (VEX_W_38DD_P_2) },
9024 },
9025
9026 /* VEX_LEN_38DE_P_2 */
9027 {
9028 { VEX_W_TABLE (VEX_W_38DE_P_2) },
9029 },
9030
9031 /* VEX_LEN_38DF_P_2 */
9032 {
9033 { VEX_W_TABLE (VEX_W_38DF_P_2) },
9034 },
9035
9036 /* VEX_LEN_3A06_P_2 */
9037 {
9038 { Bad_Opcode },
9039 { VEX_W_TABLE (VEX_W_3A06_P_2) },
9040 },
9041
9042 /* VEX_LEN_3A0A_P_2 */
9043 {
9044 { VEX_W_TABLE (VEX_W_3A0A_P_2) },
9045 { VEX_W_TABLE (VEX_W_3A0A_P_2) },
9046 },
9047
9048 /* VEX_LEN_3A0B_P_2 */
9049 {
9050 { VEX_W_TABLE (VEX_W_3A0B_P_2) },
9051 { VEX_W_TABLE (VEX_W_3A0B_P_2) },
9052 },
9053
9054 /* VEX_LEN_3A0E_P_2 */
9055 {
9056 { VEX_W_TABLE (VEX_W_3A0E_P_2) },
9057 },
9058
9059 /* VEX_LEN_3A0F_P_2 */
9060 {
9061 { VEX_W_TABLE (VEX_W_3A0F_P_2) },
9062 },
9063
9064 /* VEX_LEN_3A14_P_2 */
9065 {
9066 { VEX_W_TABLE (VEX_W_3A14_P_2) },
9067 },
9068
9069 /* VEX_LEN_3A15_P_2 */
9070 {
9071 { VEX_W_TABLE (VEX_W_3A15_P_2) },
9072 },
9073
9074 /* VEX_LEN_3A16_P_2 */
9075 {
9076 { "vpextrK", { Edq, XM, Ib } },
9077 },
9078
9079 /* VEX_LEN_3A17_P_2 */
9080 {
9081 { "vextractps", { Edqd, XM, Ib } },
9082 },
9083
9084 /* VEX_LEN_3A18_P_2 */
9085 {
9086 { Bad_Opcode },
9087 { VEX_W_TABLE (VEX_W_3A18_P_2) },
9088 },
9089
9090 /* VEX_LEN_3A19_P_2 */
9091 {
9092 { Bad_Opcode },
9093 { VEX_W_TABLE (VEX_W_3A19_P_2) },
9094 },
9095
9096 /* VEX_LEN_3A20_P_2 */
9097 {
9098 { VEX_W_TABLE (VEX_W_3A20_P_2) },
9099 },
9100
9101 /* VEX_LEN_3A21_P_2 */
9102 {
9103 { VEX_W_TABLE (VEX_W_3A21_P_2) },
9104 },
9105
9106 /* VEX_LEN_3A22_P_2 */
9107 {
9108 { "vpinsrK", { XM, Vex128, Edq, Ib } },
9109 },
9110
9111 /* VEX_LEN_3A41_P_2 */
9112 {
9113 { VEX_W_TABLE (VEX_W_3A41_P_2) },
9114 },
9115
9116 /* VEX_LEN_3A42_P_2 */
9117 {
9118 { VEX_W_TABLE (VEX_W_3A42_P_2) },
9119 },
9120
9121 /* VEX_LEN_3A44_P_2 */
9122 {
9123 { VEX_W_TABLE (VEX_W_3A44_P_2) },
9124 },
9125
9126 /* VEX_LEN_3A4C_P_2 */
9127 {
9128 { VEX_W_TABLE (VEX_W_3A4C_P_2) },
9129 },
9130
9131 /* VEX_LEN_3A60_P_2 */
9132 {
9133 { VEX_W_TABLE (VEX_W_3A60_P_2) },
9134 },
9135
9136 /* VEX_LEN_3A61_P_2 */
9137 {
9138 { VEX_W_TABLE (VEX_W_3A61_P_2) },
9139 },
9140
9141 /* VEX_LEN_3A62_P_2 */
9142 {
9143 { VEX_W_TABLE (VEX_W_3A62_P_2) },
9144 },
9145
9146 /* VEX_LEN_3A63_P_2 */
9147 {
9148 { VEX_W_TABLE (VEX_W_3A63_P_2) },
9149 },
9150
9151 /* VEX_LEN_3A6A_P_2 */
9152 {
9153 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9154 },
9155
9156 /* VEX_LEN_3A6B_P_2 */
9157 {
9158 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9159 },
9160
9161 /* VEX_LEN_3A6E_P_2 */
9162 {
9163 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9164 },
9165
9166 /* VEX_LEN_3A6F_P_2 */
9167 {
9168 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9169 },
9170
9171 /* VEX_LEN_3A7A_P_2 */
9172 {
9173 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9174 },
9175
9176 /* VEX_LEN_3A7B_P_2 */
9177 {
9178 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9179 },
9180
9181 /* VEX_LEN_3A7E_P_2 */
9182 {
9183 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9184 },
9185
9186 /* VEX_LEN_3A7F_P_2 */
9187 {
9188 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9189 },
9190
9191 /* VEX_LEN_3ADF_P_2 */
9192 {
9193 { VEX_W_TABLE (VEX_W_3ADF_P_2) },
9194 },
9195
9196 /* VEX_LEN_XOP_09_80 */
9197 {
9198 { "vfrczps", { XM, EXxmm } },
9199 { "vfrczps", { XM, EXymmq } },
9200 },
9201
9202 /* VEX_LEN_XOP_09_81 */
9203 {
9204 { "vfrczpd", { XM, EXxmm } },
9205 { "vfrczpd", { XM, EXymmq } },
9206 },
9207};
9208
9209static const struct dis386 vex_w_table[][2] = {
9210 {
9211 /* VEX_W_10_P_0 */
9212 { "vmovups", { XM, EXx } },
9213 },
9214 {
9215 /* VEX_W_10_P_1 */
9216 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },
9217 },
9218 {
9219 /* VEX_W_10_P_2 */
9220 { "vmovupd", { XM, EXx } },
9221 },
9222 {
9223 /* VEX_W_10_P_3 */
9224 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },
9225 },
9226 {
9227 /* VEX_W_11_P_0 */
9228 { "vmovups", { EXxS, XM } },
9229 },
9230 {
9231 /* VEX_W_11_P_1 */
9232 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },
9233 },
9234 {
9235 /* VEX_W_11_P_2 */
9236 { "vmovupd", { EXxS, XM } },
9237 },
9238 {
9239 /* VEX_W_11_P_3 */
9240 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },
9241 },
9242 {
9243 /* VEX_W_12_P_0_M_0 */
9244 { "vmovlps", { XM, Vex128, EXq } },
9245 },
9246 {
9247 /* VEX_W_12_P_0_M_1 */
9248 { "vmovhlps", { XM, Vex128, EXq } },
9249 },
9250 {
9251 /* VEX_W_12_P_1 */
9252 { "vmovsldup", { XM, EXx } },
9253 },
9254 {
9255 /* VEX_W_12_P_2 */
9256 { "vmovlpd", { XM, Vex128, EXq } },
9257 },
9258 {
9259 /* VEX_W_12_P_3 */
9260 { "vmovddup", { XM, EXymmq } },
9261 },
9262 {
9263 /* VEX_W_13_M_0 */
9264 { "vmovlpX", { EXq, XM } },
9265 },
9266 {
9267 /* VEX_W_14 */
9268 { "vunpcklpX", { XM, Vex, EXx } },
9269 },
9270 {
9271 /* VEX_W_15 */
9272 { "vunpckhpX", { XM, Vex, EXx } },
9273 },
9274 {
9275 /* VEX_W_16_P_0_M_0 */
9276 { "vmovhps", { XM, Vex128, EXq } },
9277 },
9278 {
9279 /* VEX_W_16_P_0_M_1 */
9280 { "vmovlhps", { XM, Vex128, EXq } },
9281 },
9282 {
9283 /* VEX_W_16_P_1 */
9284 { "vmovshdup", { XM, EXx } },
9285 },
9286 {
9287 /* VEX_W_16_P_2 */
9288 { "vmovhpd", { XM, Vex128, EXq } },
9289 },
9290 {
9291 /* VEX_W_17_M_0 */
9292 { "vmovhpX", { EXq, XM } },
9293 },
9294 {
9295 /* VEX_W_28 */
9296 { "vmovapX", { XM, EXx } },
9297 },
9298 {
9299 /* VEX_W_29 */
9300 { "vmovapX", { EXxS, XM } },
9301 },
9302 {
9303 /* VEX_W_2B_M_0 */
9304 { "vmovntpX", { Mx, XM } },
9305 },
9306 {
9307 /* VEX_W_2E_P_0 */
9308 { "vucomiss", { XMScalar, EXdScalar } },
9309 },
9310 {
9311 /* VEX_W_2E_P_2 */
9312 { "vucomisd", { XMScalar, EXqScalar } },
9313 },
9314 {
9315 /* VEX_W_2F_P_0 */
9316 { "vcomiss", { XMScalar, EXdScalar } },
9317 },
9318 {
9319 /* VEX_W_2F_P_2 */
9320 { "vcomisd", { XMScalar, EXqScalar } },
9321 },
9322 {
9323 /* VEX_W_50_M_0 */
9324 { "vmovmskpX", { Gdq, XS } },
9325 },
9326 {
9327 /* VEX_W_51_P_0 */
9328 { "vsqrtps", { XM, EXx } },
9329 },
9330 {
9331 /* VEX_W_51_P_1 */
9332 { "vsqrtss", { XMScalar, VexScalar, EXdScalar } },
9333 },
9334 {
9335 /* VEX_W_51_P_2 */
9336 { "vsqrtpd", { XM, EXx } },
9337 },
9338 {
9339 /* VEX_W_51_P_3 */
9340 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } },
9341 },
9342 {
9343 /* VEX_W_52_P_0 */
9344 { "vrsqrtps", { XM, EXx } },
9345 },
9346 {
9347 /* VEX_W_52_P_1 */
9348 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } },
9349 },
9350 {
9351 /* VEX_W_53_P_0 */
9352 { "vrcpps", { XM, EXx } },
9353 },
9354 {
9355 /* VEX_W_53_P_1 */
9356 { "vrcpss", { XMScalar, VexScalar, EXdScalar } },
9357 },
9358 {
9359 /* VEX_W_58_P_0 */
9360 { "vaddps", { XM, Vex, EXx } },
9361 },
9362 {
9363 /* VEX_W_58_P_1 */
9364 { "vaddss", { XMScalar, VexScalar, EXdScalar } },
9365 },
9366 {
9367 /* VEX_W_58_P_2 */
9368 { "vaddpd", { XM, Vex, EXx } },
9369 },
9370 {
9371 /* VEX_W_58_P_3 */
9372 { "vaddsd", { XMScalar, VexScalar, EXqScalar } },
9373 },
9374 {
9375 /* VEX_W_59_P_0 */
9376 { "vmulps", { XM, Vex, EXx } },
9377 },
9378 {
9379 /* VEX_W_59_P_1 */
9380 { "vmulss", { XMScalar, VexScalar, EXdScalar } },
9381 },
9382 {
9383 /* VEX_W_59_P_2 */
9384 { "vmulpd", { XM, Vex, EXx } },
9385 },
9386 {
9387 /* VEX_W_59_P_3 */
9388 { "vmulsd", { XMScalar, VexScalar, EXqScalar } },
9389 },
9390 {
9391 /* VEX_W_5A_P_0 */
9392 { "vcvtps2pd", { XM, EXxmmq } },
9393 },
9394 {
9395 /* VEX_W_5A_P_1 */
9396 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } },
9397 },
9398 {
9399 /* VEX_W_5A_P_3 */
9400 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } },
9401 },
9402 {
9403 /* VEX_W_5B_P_0 */
9404 { "vcvtdq2ps", { XM, EXx } },
9405 },
9406 {
9407 /* VEX_W_5B_P_1 */
9408 { "vcvttps2dq", { XM, EXx } },
9409 },
9410 {
9411 /* VEX_W_5B_P_2 */
9412 { "vcvtps2dq", { XM, EXx } },
9413 },
9414 {
9415 /* VEX_W_5C_P_0 */
9416 { "vsubps", { XM, Vex, EXx } },
9417 },
9418 {
9419 /* VEX_W_5C_P_1 */
9420 { "vsubss", { XMScalar, VexScalar, EXdScalar } },
9421 },
9422 {
9423 /* VEX_W_5C_P_2 */
9424 { "vsubpd", { XM, Vex, EXx } },
9425 },
9426 {
9427 /* VEX_W_5C_P_3 */
9428 { "vsubsd", { XMScalar, VexScalar, EXqScalar } },
9429 },
9430 {
9431 /* VEX_W_5D_P_0 */
9432 { "vminps", { XM, Vex, EXx } },
9433 },
9434 {
9435 /* VEX_W_5D_P_1 */
9436 { "vminss", { XMScalar, VexScalar, EXdScalar } },
9437 },
9438 {
9439 /* VEX_W_5D_P_2 */
9440 { "vminpd", { XM, Vex, EXx } },
9441 },
9442 {
9443 /* VEX_W_5D_P_3 */
9444 { "vminsd", { XMScalar, VexScalar, EXqScalar } },
9445 },
9446 {
9447 /* VEX_W_5E_P_0 */
9448 { "vdivps", { XM, Vex, EXx } },
9449 },
9450 {
9451 /* VEX_W_5E_P_1 */
9452 { "vdivss", { XMScalar, VexScalar, EXdScalar } },
9453 },
9454 {
9455 /* VEX_W_5E_P_2 */
9456 { "vdivpd", { XM, Vex, EXx } },
9457 },
9458 {
9459 /* VEX_W_5E_P_3 */
9460 { "vdivsd", { XMScalar, VexScalar, EXqScalar } },
9461 },
9462 {
9463 /* VEX_W_5F_P_0 */
9464 { "vmaxps", { XM, Vex, EXx } },
9465 },
9466 {
9467 /* VEX_W_5F_P_1 */
9468 { "vmaxss", { XMScalar, VexScalar, EXdScalar } },
9469 },
9470 {
9471 /* VEX_W_5F_P_2 */
9472 { "vmaxpd", { XM, Vex, EXx } },
9473 },
9474 {
9475 /* VEX_W_5F_P_3 */
9476 { "vmaxsd", { XMScalar, VexScalar, EXqScalar } },
9477 },
9478 {
9479 /* VEX_W_60_P_2 */
9480 { "vpunpcklbw", { XM, Vex128, EXx } },
9481 },
9482 {
9483 /* VEX_W_61_P_2 */
9484 { "vpunpcklwd", { XM, Vex128, EXx } },
9485 },
9486 {
9487 /* VEX_W_62_P_2 */
9488 { "vpunpckldq", { XM, Vex128, EXx } },
9489 },
9490 {
9491 /* VEX_W_63_P_2 */
9492 { "vpacksswb", { XM, Vex128, EXx } },
9493 },
9494 {
9495 /* VEX_W_64_P_2 */
9496 { "vpcmpgtb", { XM, Vex128, EXx } },
9497 },
9498 {
9499 /* VEX_W_65_P_2 */
9500 { "vpcmpgtw", { XM, Vex128, EXx } },
9501 },
9502 {
9503 /* VEX_W_66_P_2 */
9504 { "vpcmpgtd", { XM, Vex128, EXx } },
9505 },
9506 {
9507 /* VEX_W_67_P_2 */
9508 { "vpackuswb", { XM, Vex128, EXx } },
9509 },
9510 {
9511 /* VEX_W_68_P_2 */
9512 { "vpunpckhbw", { XM, Vex128, EXx } },
9513 },
9514 {
9515 /* VEX_W_69_P_2 */
9516 { "vpunpckhwd", { XM, Vex128, EXx } },
9517 },
9518 {
9519 /* VEX_W_6A_P_2 */
9520 { "vpunpckhdq", { XM, Vex128, EXx } },
9521 },
9522 {
9523 /* VEX_W_6B_P_2 */
9524 { "vpackssdw", { XM, Vex128, EXx } },
9525 },
9526 {
9527 /* VEX_W_6C_P_2 */
9528 { "vpunpcklqdq", { XM, Vex128, EXx } },
9529 },
9530 {
9531 /* VEX_W_6D_P_2 */
9532 { "vpunpckhqdq", { XM, Vex128, EXx } },
9533 },
9534 {
9535 /* VEX_W_6F_P_1 */
9536 { "vmovdqu", { XM, EXx } },
9537 },
9538 {
9539 /* VEX_W_6F_P_2 */
9540 { "vmovdqa", { XM, EXx } },
9541 },
9542 {
9543 /* VEX_W_70_P_1 */
9544 { "vpshufhw", { XM, EXx, Ib } },
9545 },
9546 {
9547 /* VEX_W_70_P_2 */
9548 { "vpshufd", { XM, EXx, Ib } },
9549 },
9550 {
9551 /* VEX_W_70_P_3 */
9552 { "vpshuflw", { XM, EXx, Ib } },
9553 },
9554 {
9555 /* VEX_W_71_R_2_P_2 */
9556 { "vpsrlw", { Vex128, XS, Ib } },
9557 },
9558 {
9559 /* VEX_W_71_R_4_P_2 */
9560 { "vpsraw", { Vex128, XS, Ib } },
9561 },
9562 {
9563 /* VEX_W_71_R_6_P_2 */
9564 { "vpsllw", { Vex128, XS, Ib } },
9565 },
9566 {
9567 /* VEX_W_72_R_2_P_2 */
9568 { "vpsrld", { Vex128, XS, Ib } },
9569 },
9570 {
9571 /* VEX_W_72_R_4_P_2 */
9572 { "vpsrad", { Vex128, XS, Ib } },
9573 },
9574 {
9575 /* VEX_W_72_R_6_P_2 */
9576 { "vpslld", { Vex128, XS, Ib } },
9577 },
9578 {
9579 /* VEX_W_73_R_2_P_2 */
9580 { "vpsrlq", { Vex128, XS, Ib } },
9581 },
9582 {
9583 /* VEX_W_73_R_3_P_2 */
9584 { "vpsrldq", { Vex128, XS, Ib } },
9585 },
9586 {
9587 /* VEX_W_73_R_6_P_2 */
9588 { "vpsllq", { Vex128, XS, Ib } },
9589 },
9590 {
9591 /* VEX_W_73_R_7_P_2 */
9592 { "vpslldq", { Vex128, XS, Ib } },
9593 },
9594 {
9595 /* VEX_W_74_P_2 */
9596 { "vpcmpeqb", { XM, Vex128, EXx } },
9597 },
9598 {
9599 /* VEX_W_75_P_2 */
9600 { "vpcmpeqw", { XM, Vex128, EXx } },
9601 },
9602 {
9603 /* VEX_W_76_P_2 */
9604 { "vpcmpeqd", { XM, Vex128, EXx } },
9605 },
9606 {
9607 /* VEX_W_77_P_0 */
9608 { "", { VZERO } },
9609 },
9610 {
9611 /* VEX_W_7C_P_2 */
9612 { "vhaddpd", { XM, Vex, EXx } },
9613 },
9614 {
9615 /* VEX_W_7C_P_3 */
9616 { "vhaddps", { XM, Vex, EXx } },
9617 },
9618 {
9619 /* VEX_W_7D_P_2 */
9620 { "vhsubpd", { XM, Vex, EXx } },
9621 },
9622 {
9623 /* VEX_W_7D_P_3 */
9624 { "vhsubps", { XM, Vex, EXx } },
9625 },
9626 {
9627 /* VEX_W_7E_P_1 */
9628 { "vmovq", { XMScalar, EXqScalar } },
9629 },
9630 {
9631 /* VEX_W_7F_P_1 */
9632 { "vmovdqu", { EXxS, XM } },
9633 },
9634 {
9635 /* VEX_W_7F_P_2 */
9636 { "vmovdqa", { EXxS, XM } },
9637 },
9638 {
9639 /* VEX_W_AE_R_2_M_0 */
9640 { "vldmxcsr", { Md } },
9641 },
9642 {
9643 /* VEX_W_AE_R_3_M_0 */
9644 { "vstmxcsr", { Md } },
9645 },
9646 {
9647 /* VEX_W_C2_P_0 */
9648 { "vcmpps", { XM, Vex, EXx, VCMP } },
9649 },
9650 {
9651 /* VEX_W_C2_P_1 */
9652 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } },
9653 },
9654 {
9655 /* VEX_W_C2_P_2 */
9656 { "vcmppd", { XM, Vex, EXx, VCMP } },
9657 },
9658 {
9659 /* VEX_W_C2_P_3 */
9660 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } },
9661 },
9662 {
9663 /* VEX_W_C4_P_2 */
9664 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
9665 },
9666 {
9667 /* VEX_W_C5_P_2 */
9668 { "vpextrw", { Gdq, XS, Ib } },
9669 },
9670 {
9671 /* VEX_W_D0_P_2 */
9672 { "vaddsubpd", { XM, Vex, EXx } },
9673 },
9674 {
9675 /* VEX_W_D0_P_3 */
9676 { "vaddsubps", { XM, Vex, EXx } },
9677 },
9678 {
9679 /* VEX_W_D1_P_2 */
9680 { "vpsrlw", { XM, Vex128, EXx } },
9681 },
9682 {
9683 /* VEX_W_D2_P_2 */
9684 { "vpsrld", { XM, Vex128, EXx } },
9685 },
9686 {
9687 /* VEX_W_D3_P_2 */
9688 { "vpsrlq", { XM, Vex128, EXx } },
9689 },
9690 {
9691 /* VEX_W_D4_P_2 */
9692 { "vpaddq", { XM, Vex128, EXx } },
9693 },
9694 {
9695 /* VEX_W_D5_P_2 */
9696 { "vpmullw", { XM, Vex128, EXx } },
9697 },
9698 {
9699 /* VEX_W_D6_P_2 */
9700 { "vmovq", { EXqScalarS, XMScalar } },
9701 },
9702 {
9703 /* VEX_W_D7_P_2_M_1 */
9704 { "vpmovmskb", { Gdq, XS } },
9705 },
9706 {
9707 /* VEX_W_D8_P_2 */
9708 { "vpsubusb", { XM, Vex128, EXx } },
9709 },
9710 {
9711 /* VEX_W_D9_P_2 */
9712 { "vpsubusw", { XM, Vex128, EXx } },
9713 },
9714 {
9715 /* VEX_W_DA_P_2 */
9716 { "vpminub", { XM, Vex128, EXx } },
9717 },
9718 {
9719 /* VEX_W_DB_P_2 */
9720 { "vpand", { XM, Vex128, EXx } },
9721 },
9722 {
9723 /* VEX_W_DC_P_2 */
9724 { "vpaddusb", { XM, Vex128, EXx } },
9725 },
9726 {
9727 /* VEX_W_DD_P_2 */
9728 { "vpaddusw", { XM, Vex128, EXx } },
9729 },
9730 {
9731 /* VEX_W_DE_P_2 */
9732 { "vpmaxub", { XM, Vex128, EXx } },
9733 },
9734 {
9735 /* VEX_W_DF_P_2 */
9736 { "vpandn", { XM, Vex128, EXx } },
9737 },
9738 {
9739 /* VEX_W_E0_P_2 */
9740 { "vpavgb", { XM, Vex128, EXx } },
9741 },
9742 {
9743 /* VEX_W_E1_P_2 */
9744 { "vpsraw", { XM, Vex128, EXx } },
9745 },
9746 {
9747 /* VEX_W_E2_P_2 */
9748 { "vpsrad", { XM, Vex128, EXx } },
9749 },
9750 {
9751 /* VEX_W_E3_P_2 */
9752 { "vpavgw", { XM, Vex128, EXx } },
9753 },
9754 {
9755 /* VEX_W_E4_P_2 */
9756 { "vpmulhuw", { XM, Vex128, EXx } },
9757 },
9758 {
9759 /* VEX_W_E5_P_2 */
9760 { "vpmulhw", { XM, Vex128, EXx } },
9761 },
9762 {
9763 /* VEX_W_E6_P_1 */
9764 { "vcvtdq2pd", { XM, EXxmmq } },
9765 },
9766 {
9767 /* VEX_W_E6_P_2 */
9768 { "vcvttpd2dq%XY", { XMM, EXx } },
9769 },
9770 {
9771 /* VEX_W_E6_P_3 */
9772 { "vcvtpd2dq%XY", { XMM, EXx } },
9773 },
9774 {
9775 /* VEX_W_E7_P_2_M_0 */
9776 { "vmovntdq", { Mx, XM } },
9777 },
9778 {
9779 /* VEX_W_E8_P_2 */
9780 { "vpsubsb", { XM, Vex128, EXx } },
9781 },
9782 {
9783 /* VEX_W_E9_P_2 */
9784 { "vpsubsw", { XM, Vex128, EXx } },
9785 },
9786 {
9787 /* VEX_W_EA_P_2 */
9788 { "vpminsw", { XM, Vex128, EXx } },
9789 },
9790 {
9791 /* VEX_W_EB_P_2 */
9792 { "vpor", { XM, Vex128, EXx } },
9793 },
9794 {
9795 /* VEX_W_EC_P_2 */
9796 { "vpaddsb", { XM, Vex128, EXx } },
9797 },
9798 {
9799 /* VEX_W_ED_P_2 */
9800 { "vpaddsw", { XM, Vex128, EXx } },
9801 },
9802 {
9803 /* VEX_W_EE_P_2 */
9804 { "vpmaxsw", { XM, Vex128, EXx } },
9805 },
9806 {
9807 /* VEX_W_EF_P_2 */
9808 { "vpxor", { XM, Vex128, EXx } },
9809 },
9810 {
9811 /* VEX_W_F0_P_3_M_0 */
9812 { "vlddqu", { XM, M } },
9813 },
9814 {
9815 /* VEX_W_F1_P_2 */
9816 { "vpsllw", { XM, Vex128, EXx } },
9817 },
9818 {
9819 /* VEX_W_F2_P_2 */
9820 { "vpslld", { XM, Vex128, EXx } },
9821 },
9822 {
9823 /* VEX_W_F3_P_2 */
9824 { "vpsllq", { XM, Vex128, EXx } },
9825 },
9826 {
9827 /* VEX_W_F4_P_2 */
9828 { "vpmuludq", { XM, Vex128, EXx } },
9829 },
9830 {
9831 /* VEX_W_F5_P_2 */
9832 { "vpmaddwd", { XM, Vex128, EXx } },
9833 },
9834 {
9835 /* VEX_W_F6_P_2 */
9836 { "vpsadbw", { XM, Vex128, EXx } },
9837 },
9838 {
9839 /* VEX_W_F7_P_2 */
9840 { "vmaskmovdqu", { XM, XS } },
9841 },
9842 {
9843 /* VEX_W_F8_P_2 */
9844 { "vpsubb", { XM, Vex128, EXx } },
9845 },
9846 {
9847 /* VEX_W_F9_P_2 */
9848 { "vpsubw", { XM, Vex128, EXx } },
9849 },
9850 {
9851 /* VEX_W_FA_P_2 */
9852 { "vpsubd", { XM, Vex128, EXx } },
9853 },
9854 {
9855 /* VEX_W_FB_P_2 */
9856 { "vpsubq", { XM, Vex128, EXx } },
9857 },
9858 {
9859 /* VEX_W_FC_P_2 */
9860 { "vpaddb", { XM, Vex128, EXx } },
9861 },
9862 {
9863 /* VEX_W_FD_P_2 */
9864 { "vpaddw", { XM, Vex128, EXx } },
9865 },
9866 {
9867 /* VEX_W_FE_P_2 */
9868 { "vpaddd", { XM, Vex128, EXx } },
9869 },
9870 {
9871 /* VEX_W_3800_P_2 */
9872 { "vpshufb", { XM, Vex128, EXx } },
9873 },
9874 {
9875 /* VEX_W_3801_P_2 */
9876 { "vphaddw", { XM, Vex128, EXx } },
9877 },
9878 {
9879 /* VEX_W_3802_P_2 */
9880 { "vphaddd", { XM, Vex128, EXx } },
9881 },
9882 {
9883 /* VEX_W_3803_P_2 */
9884 { "vphaddsw", { XM, Vex128, EXx } },
9885 },
9886 {
9887 /* VEX_W_3804_P_2 */
9888 { "vpmaddubsw", { XM, Vex128, EXx } },
9889 },
9890 {
9891 /* VEX_W_3805_P_2 */
9892 { "vphsubw", { XM, Vex128, EXx } },
9893 },
9894 {
9895 /* VEX_W_3806_P_2 */
9896 { "vphsubd", { XM, Vex128, EXx } },
9897 },
9898 {
9899 /* VEX_W_3807_P_2 */
9900 { "vphsubsw", { XM, Vex128, EXx } },
9901 },
9902 {
9903 /* VEX_W_3808_P_2 */
9904 { "vpsignb", { XM, Vex128, EXx } },
9905 },
9906 {
9907 /* VEX_W_3809_P_2 */
9908 { "vpsignw", { XM, Vex128, EXx } },
9909 },
9910 {
9911 /* VEX_W_380A_P_2 */
9912 { "vpsignd", { XM, Vex128, EXx } },
9913 },
9914 {
9915 /* VEX_W_380B_P_2 */
9916 { "vpmulhrsw", { XM, Vex128, EXx } },
9917 },
9918 {
9919 /* VEX_W_380C_P_2 */
9920 { "vpermilps", { XM, Vex, EXx } },
9921 },
9922 {
9923 /* VEX_W_380D_P_2 */
9924 { "vpermilpd", { XM, Vex, EXx } },
9925 },
9926 {
9927 /* VEX_W_380E_P_2 */
9928 { "vtestps", { XM, EXx } },
9929 },
9930 {
9931 /* VEX_W_380F_P_2 */
9932 { "vtestpd", { XM, EXx } },
9933 },
9934 {
9935 /* VEX_W_3817_P_2 */
9936 { "vptest", { XM, EXx } },
9937 },
9938 {
9939 /* VEX_W_3818_P_2_M_0 */
9940 { "vbroadcastss", { XM, Md } },
9941 },
9942 {
9943 /* VEX_W_3819_P_2_M_0 */
9944 { "vbroadcastsd", { XM, Mq } },
9945 },
9946 {
9947 /* VEX_W_381A_P_2_M_0 */
9948 { "vbroadcastf128", { XM, Mxmm } },
9949 },
9950 {
9951 /* VEX_W_381C_P_2 */
9952 { "vpabsb", { XM, EXx } },
9953 },
9954 {
9955 /* VEX_W_381D_P_2 */
9956 { "vpabsw", { XM, EXx } },
9957 },
9958 {
9959 /* VEX_W_381E_P_2 */
9960 { "vpabsd", { XM, EXx } },
9961 },
9962 {
9963 /* VEX_W_3820_P_2 */
9964 { "vpmovsxbw", { XM, EXq } },
9965 },
9966 {
9967 /* VEX_W_3821_P_2 */
9968 { "vpmovsxbd", { XM, EXd } },
9969 },
9970 {
9971 /* VEX_W_3822_P_2 */
9972 { "vpmovsxbq", { XM, EXw } },
9973 },
9974 {
9975 /* VEX_W_3823_P_2 */
9976 { "vpmovsxwd", { XM, EXq } },
9977 },
9978 {
9979 /* VEX_W_3824_P_2 */
9980 { "vpmovsxwq", { XM, EXd } },
9981 },
9982 {
9983 /* VEX_W_3825_P_2 */
9984 { "vpmovsxdq", { XM, EXq } },
9985 },
9986 {
9987 /* VEX_W_3828_P_2 */
9988 { "vpmuldq", { XM, Vex128, EXx } },
9989 },
9990 {
9991 /* VEX_W_3829_P_2 */
9992 { "vpcmpeqq", { XM, Vex128, EXx } },
9993 },
9994 {
9995 /* VEX_W_382A_P_2_M_0 */
9996 { "vmovntdqa", { XM, Mx } },
9997 },
9998 {
9999 /* VEX_W_382B_P_2 */
10000 { "vpackusdw", { XM, Vex128, EXx } },
10001 },
10002 {
10003 /* VEX_W_382C_P_2_M_0 */
10004 { "vmaskmovps", { XM, Vex, Mx } },
10005 },
10006 {
10007 /* VEX_W_382D_P_2_M_0 */
10008 { "vmaskmovpd", { XM, Vex, Mx } },
10009 },
10010 {
10011 /* VEX_W_382E_P_2_M_0 */
10012 { "vmaskmovps", { Mx, Vex, XM } },
10013 },
10014 {
10015 /* VEX_W_382F_P_2_M_0 */
10016 { "vmaskmovpd", { Mx, Vex, XM } },
10017 },
10018 {
10019 /* VEX_W_3830_P_2 */
10020 { "vpmovzxbw", { XM, EXq } },
10021 },
10022 {
10023 /* VEX_W_3831_P_2 */
10024 { "vpmovzxbd", { XM, EXd } },
10025 },
10026 {
10027 /* VEX_W_3832_P_2 */
10028 { "vpmovzxbq", { XM, EXw } },
10029 },
10030 {
10031 /* VEX_W_3833_P_2 */
10032 { "vpmovzxwd", { XM, EXq } },
10033 },
10034 {
10035 /* VEX_W_3834_P_2 */
10036 { "vpmovzxwq", { XM, EXd } },
10037 },
10038 {
10039 /* VEX_W_3835_P_2 */
10040 { "vpmovzxdq", { XM, EXq } },
10041 },
10042 {
10043 /* VEX_W_3837_P_2 */
10044 { "vpcmpgtq", { XM, Vex128, EXx } },
10045 },
10046 {
10047 /* VEX_W_3838_P_2 */
10048 { "vpminsb", { XM, Vex128, EXx } },
10049 },
10050 {
10051 /* VEX_W_3839_P_2 */
10052 { "vpminsd", { XM, Vex128, EXx } },
10053 },
10054 {
10055 /* VEX_W_383A_P_2 */
10056 { "vpminuw", { XM, Vex128, EXx } },
10057 },
10058 {
10059 /* VEX_W_383B_P_2 */
10060 { "vpminud", { XM, Vex128, EXx } },
10061 },
10062 {
10063 /* VEX_W_383C_P_2 */
10064 { "vpmaxsb", { XM, Vex128, EXx } },
10065 },
10066 {
10067 /* VEX_W_383D_P_2 */
10068 { "vpmaxsd", { XM, Vex128, EXx } },
10069 },
10070 {
10071 /* VEX_W_383E_P_2 */
10072 { "vpmaxuw", { XM, Vex128, EXx } },
10073 },
10074 {
10075 /* VEX_W_383F_P_2 */
10076 { "vpmaxud", { XM, Vex128, EXx } },
10077 },
10078 {
10079 /* VEX_W_3840_P_2 */
10080 { "vpmulld", { XM, Vex128, EXx } },
10081 },
10082 {
10083 /* VEX_W_3841_P_2 */
10084 { "vphminposuw", { XM, EXx } },
10085 },
10086 {
10087 /* VEX_W_38DB_P_2 */
10088 { "vaesimc", { XM, EXx } },
10089 },
10090 {
10091 /* VEX_W_38DC_P_2 */
10092 { "vaesenc", { XM, Vex128, EXx } },
10093 },
10094 {
10095 /* VEX_W_38DD_P_2 */
10096 { "vaesenclast", { XM, Vex128, EXx } },
10097 },
10098 {
10099 /* VEX_W_38DE_P_2 */
10100 { "vaesdec", { XM, Vex128, EXx } },
10101 },
10102 {
10103 /* VEX_W_38DF_P_2 */
10104 { "vaesdeclast", { XM, Vex128, EXx } },
10105 },
10106 {
10107 /* VEX_W_3A04_P_2 */
10108 { "vpermilps", { XM, EXx, Ib } },
10109 },
10110 {
10111 /* VEX_W_3A05_P_2 */
10112 { "vpermilpd", { XM, EXx, Ib } },
10113 },
10114 {
10115 /* VEX_W_3A06_P_2 */
10116 { "vperm2f128", { XM, Vex256, EXx, Ib } },
10117 },
10118 {
10119 /* VEX_W_3A08_P_2 */
10120 { "vroundps", { XM, EXx, Ib } },
10121 },
10122 {
10123 /* VEX_W_3A09_P_2 */
10124 { "vroundpd", { XM, EXx, Ib } },
10125 },
10126 {
10127 /* VEX_W_3A0A_P_2 */
10128 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } },
10129 },
10130 {
10131 /* VEX_W_3A0B_P_2 */
10132 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } },
10133 },
10134 {
10135 /* VEX_W_3A0C_P_2 */
10136 { "vblendps", { XM, Vex, EXx, Ib } },
10137 },
10138 {
10139 /* VEX_W_3A0D_P_2 */
10140 { "vblendpd", { XM, Vex, EXx, Ib } },
10141 },
10142 {
10143 /* VEX_W_3A0E_P_2 */
10144 { "vpblendw", { XM, Vex128, EXx, Ib } },
10145 },
10146 {
10147 /* VEX_W_3A0F_P_2 */
10148 { "vpalignr", { XM, Vex128, EXx, Ib } },
10149 },
10150 {
10151 /* VEX_W_3A14_P_2 */
10152 { "vpextrb", { Edqb, XM, Ib } },
10153 },
10154 {
10155 /* VEX_W_3A15_P_2 */
10156 { "vpextrw", { Edqw, XM, Ib } },
10157 },
10158 {
10159 /* VEX_W_3A18_P_2 */
10160 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
10161 },
10162 {
10163 /* VEX_W_3A19_P_2 */
10164 { "vextractf128", { EXxmm, XM, Ib } },
10165 },
10166 {
10167 /* VEX_W_3A20_P_2 */
10168 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
10169 },
10170 {
10171 /* VEX_W_3A21_P_2 */
10172 { "vinsertps", { XM, Vex128, EXd, Ib } },
10173 },
10174 {
10175 /* VEX_W_3A40_P_2 */
10176 { "vdpps", { XM, Vex, EXx, Ib } },
10177 },
10178 {
10179 /* VEX_W_3A41_P_2 */
10180 { "vdppd", { XM, Vex128, EXx, Ib } },
10181 },
10182 {
10183 /* VEX_W_3A42_P_2 */
10184 { "vmpsadbw", { XM, Vex128, EXx, Ib } },
10185 },
10186 {
10187 /* VEX_W_3A44_P_2 */
10188 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
10189 },
10190 {
10191 /* VEX_W_3A48_P_2 */
10192 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10193 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10194 },
10195 {
10196 /* VEX_W_3A49_P_2 */
10197 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10198 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10199 },
10200 {
10201 /* VEX_W_3A4A_P_2 */
10202 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
10203 },
10204 {
10205 /* VEX_W_3A4B_P_2 */
10206 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
10207 },
10208 {
10209 /* VEX_W_3A4C_P_2 */
10210 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
10211 },
10212 {
10213 /* VEX_W_3A60_P_2 */
10214 { "vpcmpestrm", { XM, EXx, Ib } },
10215 },
10216 {
10217 /* VEX_W_3A61_P_2 */
10218 { "vpcmpestri", { XM, EXx, Ib } },
10219 },
10220 {
10221 /* VEX_W_3A62_P_2 */
10222 { "vpcmpistrm", { XM, EXx, Ib } },
10223 },
10224 {
10225 /* VEX_W_3A63_P_2 */
10226 { "vpcmpistri", { XM, EXx, Ib } },
10227 },
10228 {
10229 /* VEX_W_3ADF_P_2 */
10230 { "vaeskeygenassist", { XM, EXx, Ib } },
10231 },
10232};
10233
10234static const struct dis386 mod_table[][2] = {
10235 {
10236 /* MOD_8D */
10237 { "leaS", { Gv, M } },
10238 },
10239 {
10240 /* MOD_0F01_REG_0 */
10241 { X86_64_TABLE (X86_64_0F01_REG_0) },
10242 { RM_TABLE (RM_0F01_REG_0) },
10243 },
10244 {
10245 /* MOD_0F01_REG_1 */
10246 { X86_64_TABLE (X86_64_0F01_REG_1) },
10247 { RM_TABLE (RM_0F01_REG_1) },
10248 },
10249 {
10250 /* MOD_0F01_REG_2 */
10251 { X86_64_TABLE (X86_64_0F01_REG_2) },
10252 { RM_TABLE (RM_0F01_REG_2) },
10253 },
10254 {
10255 /* MOD_0F01_REG_3 */
10256 { X86_64_TABLE (X86_64_0F01_REG_3) },
10257 { RM_TABLE (RM_0F01_REG_3) },
10258 },
10259 {
10260 /* MOD_0F01_REG_7 */
10261 { "invlpg", { Mb } },
10262 { RM_TABLE (RM_0F01_REG_7) },
10263 },
10264 {
10265 /* MOD_0F12_PREFIX_0 */
10266 { "movlps", { XM, EXq } },
10267 { "movhlps", { XM, EXq } },
10268 },
10269 {
10270 /* MOD_0F13 */
10271 { "movlpX", { EXq, XM } },
10272 },
10273 {
10274 /* MOD_0F16_PREFIX_0 */
10275 { "movhps", { XM, EXq } },
10276 { "movlhps", { XM, EXq } },
10277 },
10278 {
10279 /* MOD_0F17 */
10280 { "movhpX", { EXq, XM } },
10281 },
10282 {
10283 /* MOD_0F18_REG_0 */
10284 { "prefetchnta", { Mb } },
10285 },
10286 {
10287 /* MOD_0F18_REG_1 */
10288 { "prefetcht0", { Mb } },
10289 },
10290 {
10291 /* MOD_0F18_REG_2 */
10292 { "prefetcht1", { Mb } },
10293 },
10294 {
10295 /* MOD_0F18_REG_3 */
10296 { "prefetcht2", { Mb } },
10297 },
10298 {
10299 /* MOD_0F20 */
10300 { Bad_Opcode },
10301 { "movZ", { Rm, Cm } },
10302 },
10303 {
10304 /* MOD_0F21 */
10305 { Bad_Opcode },
10306 { "movZ", { Rm, Dm } },
10307 },
10308 {
10309 /* MOD_0F22 */
10310 { Bad_Opcode },
10311 { "movZ", { Cm, Rm } },
10312 },
10313 {
10314 /* MOD_0F23 */
10315 { Bad_Opcode },
10316 { "movZ", { Dm, Rm } },
10317 },
10318 {
10319 /* MOD_0F24 */
10320 { Bad_Opcode },
10321 { "movL", { Rd, Td } },
10322 },
10323 {
10324 /* MOD_0F26 */
10325 { Bad_Opcode },
10326 { "movL", { Td, Rd } },
10327 },
10328 {
10329 /* MOD_0F2B_PREFIX_0 */
10330 {"movntps", { Mx, XM } },
10331 },
10332 {
10333 /* MOD_0F2B_PREFIX_1 */
10334 {"movntss", { Md, XM } },
10335 },
10336 {
10337 /* MOD_0F2B_PREFIX_2 */
10338 {"movntpd", { Mx, XM } },
10339 },
10340 {
10341 /* MOD_0F2B_PREFIX_3 */
10342 {"movntsd", { Mq, XM } },
10343 },
10344 {
10345 /* MOD_0F51 */
10346 { Bad_Opcode },
10347 { "movmskpX", { Gdq, XS } },
10348 },
10349 {
10350 /* MOD_0F71_REG_2 */
10351 { Bad_Opcode },
10352 { "psrlw", { MS, Ib } },
10353 },
10354 {
10355 /* MOD_0F71_REG_4 */
10356 { Bad_Opcode },
10357 { "psraw", { MS, Ib } },
10358 },
10359 {
10360 /* MOD_0F71_REG_6 */
10361 { Bad_Opcode },
10362 { "psllw", { MS, Ib } },
10363 },
10364 {
10365 /* MOD_0F72_REG_2 */
10366 { Bad_Opcode },
10367 { "psrld", { MS, Ib } },
10368 },
10369 {
10370 /* MOD_0F72_REG_4 */
10371 { Bad_Opcode },
10372 { "psrad", { MS, Ib } },
10373 },
10374 {
10375 /* MOD_0F72_REG_6 */
10376 { Bad_Opcode },
10377 { "pslld", { MS, Ib } },
10378 },
10379 {
10380 /* MOD_0F73_REG_2 */
10381 { Bad_Opcode },
10382 { "psrlq", { MS, Ib } },
10383 },
10384 {
10385 /* MOD_0F73_REG_3 */
10386 { Bad_Opcode },
10387 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10388 },
10389 {
10390 /* MOD_0F73_REG_6 */
10391 { Bad_Opcode },
10392 { "psllq", { MS, Ib } },
10393 },
10394 {
10395 /* MOD_0F73_REG_7 */
10396 { Bad_Opcode },
10397 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10398 },
10399 {
10400 /* MOD_0FAE_REG_0 */
10401 { "fxsave", { FXSAVE } },
10402 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10403 },
10404 {
10405 /* MOD_0FAE_REG_1 */
10406 { "fxrstor", { FXSAVE } },
10407 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10408 },
10409 {
10410 /* MOD_0FAE_REG_2 */
10411 { "ldmxcsr", { Md } },
10412 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10413 },
10414 {
10415 /* MOD_0FAE_REG_3 */
10416 { "stmxcsr", { Md } },
10417 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10418 },
10419 {
10420 /* MOD_0FAE_REG_4 */
10421 { "xsave", { FXSAVE } },
10422 },
10423 {
10424 /* MOD_0FAE_REG_5 */
10425 { "xrstor", { FXSAVE } },
10426 { RM_TABLE (RM_0FAE_REG_5) },
10427 },
10428 {
10429 /* MOD_0FAE_REG_6 */
10430 { "xsaveopt", { FXSAVE } },
10431 { RM_TABLE (RM_0FAE_REG_6) },
10432 },
10433 {
10434 /* MOD_0FAE_REG_7 */
10435 { "clflush", { Mb } },
10436 { RM_TABLE (RM_0FAE_REG_7) },
10437 },
10438 {
10439 /* MOD_0FB2 */
10440 { "lssS", { Gv, Mp } },
10441 },
10442 {
10443 /* MOD_0FB4 */
10444 { "lfsS", { Gv, Mp } },
10445 },
10446 {
10447 /* MOD_0FB5 */
10448 { "lgsS", { Gv, Mp } },
10449 },
10450 {
10451 /* MOD_0FC7_REG_6 */
10452 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10453 { "rdrand", { Ev } },
10454 },
10455 {
10456 /* MOD_0FC7_REG_7 */
10457 { "vmptrst", { Mq } },
10458 },
10459 {
10460 /* MOD_0FD7 */
10461 { Bad_Opcode },
10462 { "pmovmskb", { Gdq, MS } },
10463 },
10464 {
10465 /* MOD_0FE7_PREFIX_2 */
10466 { "movntdq", { Mx, XM } },
10467 },
10468 {
10469 /* MOD_0FF0_PREFIX_3 */
10470 { "lddqu", { XM, M } },
10471 },
10472 {
10473 /* MOD_0F382A_PREFIX_2 */
10474 { "movntdqa", { XM, Mx } },
10475 },
10476 {
10477 /* MOD_62_32BIT */
10478 { "bound{S|}", { Gv, Ma } },
10479 },
10480 {
10481 /* MOD_C4_32BIT */
10482 { "lesS", { Gv, Mp } },
10483 { VEX_C4_TABLE (VEX_0F) },
10484 },
10485 {
10486 /* MOD_C5_32BIT */
10487 { "ldsS", { Gv, Mp } },
10488 { VEX_C5_TABLE (VEX_0F) },
10489 },
10490 {
10491 /* MOD_VEX_12_PREFIX_0 */
10492 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
10493 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
10494 },
10495 {
10496 /* MOD_VEX_13 */
10497 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
10498 },
10499 {
10500 /* MOD_VEX_16_PREFIX_0 */
10501 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
10502 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
10503 },
10504 {
10505 /* MOD_VEX_17 */
10506 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
10507 },
10508 {
10509 /* MOD_VEX_2B */
10510 { VEX_W_TABLE (VEX_W_2B_M_0) },
10511 },
10512 {
10513 /* MOD_VEX_50 */
10514 { Bad_Opcode },
10515 { VEX_W_TABLE (VEX_W_50_M_0) },
10516 },
10517 {
10518 /* MOD_VEX_71_REG_2 */
10519 { Bad_Opcode },
10520 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
10521 },
10522 {
10523 /* MOD_VEX_71_REG_4 */
10524 { Bad_Opcode },
10525 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
10526 },
10527 {
10528 /* MOD_VEX_71_REG_6 */
10529 { Bad_Opcode },
10530 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
10531 },
10532 {
10533 /* MOD_VEX_72_REG_2 */
10534 { Bad_Opcode },
10535 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
10536 },
10537 {
10538 /* MOD_VEX_72_REG_4 */
10539 { Bad_Opcode },
10540 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
10541 },
10542 {
10543 /* MOD_VEX_72_REG_6 */
10544 { Bad_Opcode },
10545 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
10546 },
10547 {
10548 /* MOD_VEX_73_REG_2 */
10549 { Bad_Opcode },
10550 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
10551 },
10552 {
10553 /* MOD_VEX_73_REG_3 */
10554 { Bad_Opcode },
10555 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
10556 },
10557 {
10558 /* MOD_VEX_73_REG_6 */
10559 { Bad_Opcode },
10560 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
10561 },
10562 {
10563 /* MOD_VEX_73_REG_7 */
10564 { Bad_Opcode },
10565 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
10566 },
10567 {
10568 /* MOD_VEX_AE_REG_2 */
10569 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
10570 },
10571 {
10572 /* MOD_VEX_AE_REG_3 */
10573 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
10574 },
10575 {
10576 /* MOD_VEX_D7_PREFIX_2 */
10577 { Bad_Opcode },
10578 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
10579 },
10580 {
10581 /* MOD_VEX_E7_PREFIX_2 */
10582 { VEX_W_TABLE (VEX_W_E7_P_2_M_0) },
10583 },
10584 {
10585 /* MOD_VEX_F0_PREFIX_3 */
10586 { VEX_W_TABLE (VEX_W_F0_P_3_M_0) },
10587 },
10588 {
10589 /* MOD_VEX_3818_PREFIX_2 */
10590 { VEX_W_TABLE (VEX_W_3818_P_2_M_0) },
10591 },
10592 {
10593 /* MOD_VEX_3819_PREFIX_2 */
10594 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
10595 },
10596 {
10597 /* MOD_VEX_381A_PREFIX_2 */
10598 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
10599 },
10600 {
10601 /* MOD_VEX_382A_PREFIX_2 */
10602 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
10603 },
10604 {
10605 /* MOD_VEX_382C_PREFIX_2 */
10606 { VEX_W_TABLE (VEX_W_382C_P_2_M_0) },
10607 },
10608 {
10609 /* MOD_VEX_382D_PREFIX_2 */
10610 { VEX_W_TABLE (VEX_W_382D_P_2_M_0) },
10611 },
10612 {
10613 /* MOD_VEX_382E_PREFIX_2 */
10614 { VEX_W_TABLE (VEX_W_382E_P_2_M_0) },
10615 },
10616 {
10617 /* MOD_VEX_382F_PREFIX_2 */
10618 { VEX_W_TABLE (VEX_W_382F_P_2_M_0) },
10619 },
10620};
10621
10622static const struct dis386 rm_table[][8] = {
10623 {
10624 /* RM_0F01_REG_0 */
10625 { Bad_Opcode },
10626 { "vmcall", { Skip_MODRM } },
10627 { "vmlaunch", { Skip_MODRM } },
10628 { "vmresume", { Skip_MODRM } },
10629 { "vmxoff", { Skip_MODRM } },
10630 },
10631 {
10632 /* RM_0F01_REG_1 */
10633 { "monitor", { { OP_Monitor, 0 } } },
10634 { "mwait", { { OP_Mwait, 0 } } },
10635 },
10636 {
10637 /* RM_0F01_REG_2 */
10638 { "xgetbv", { Skip_MODRM } },
10639 { "xsetbv", { Skip_MODRM } },
10640 },
10641 {
10642 /* RM_0F01_REG_3 */
10643 { "vmrun", { Skip_MODRM } },
10644 { "vmmcall", { Skip_MODRM } },
10645 { "vmload", { Skip_MODRM } },
10646 { "vmsave", { Skip_MODRM } },
10647 { "stgi", { Skip_MODRM } },
10648 { "clgi", { Skip_MODRM } },
10649 { "skinit", { Skip_MODRM } },
10650 { "invlpga", { Skip_MODRM } },
10651 },
10652 {
10653 /* RM_0F01_REG_7 */
10654 { "swapgs", { Skip_MODRM } },
10655 { "rdtscp", { Skip_MODRM } },
10656 },
10657 {
10658 /* RM_0FAE_REG_5 */
10659 { "lfence", { Skip_MODRM } },
10660 },
10661 {
10662 /* RM_0FAE_REG_6 */
10663 { "mfence", { Skip_MODRM } },
10664 },
10665 {
10666 /* RM_0FAE_REG_7 */
10667 { "sfence", { Skip_MODRM } },
10668 },
10669};
10670
10671#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10672
10673/* We use the high bit to indicate different name for the same
10674 prefix. */
10675#define ADDR16_PREFIX (0x67 | 0x100)
10676#define ADDR32_PREFIX (0x67 | 0x200)
10677#define DATA16_PREFIX (0x66 | 0x100)
10678#define DATA32_PREFIX (0x66 | 0x200)
10679#define REP_PREFIX (0xf3 | 0x100)
10680
10681static int
10682ckprefix (void)
10683{
10684 int newrex, i, length;
10685 rex = 0;
10686 rex_ignored = 0;
10687 prefixes = 0;
10688 used_prefixes = 0;
10689 rex_used = 0;
10690 last_lock_prefix = -1;
10691 last_repz_prefix = -1;
10692 last_repnz_prefix = -1;
10693 last_data_prefix = -1;
10694 last_addr_prefix = -1;
10695 last_rex_prefix = -1;
10696 last_seg_prefix = -1;
10697 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10698 all_prefixes[i] = 0;
10699 i = 0;
10700 length = 0;
10701 /* The maximum instruction length is 15bytes. */
10702 while (length < MAX_CODE_LENGTH - 1)
10703 {
10704 FETCH_DATA (the_info, codep + 1);
10705 newrex = 0;
10706 switch (*codep)
10707 {
10708 /* REX prefixes family. */
10709 case 0x40:
10710 case 0x41:
10711 case 0x42:
10712 case 0x43:
10713 case 0x44:
10714 case 0x45:
10715 case 0x46:
10716 case 0x47:
10717 case 0x48:
10718 case 0x49:
10719 case 0x4a:
10720 case 0x4b:
10721 case 0x4c:
10722 case 0x4d:
10723 case 0x4e:
10724 case 0x4f:
10725 if (address_mode == mode_64bit)
10726 newrex = *codep;
10727 else
10728 return 1;
10729 last_rex_prefix = i;
10730 break;
10731 case 0xf3:
10732 prefixes |= PREFIX_REPZ;
10733 last_repz_prefix = i;
10734 break;
10735 case 0xf2:
10736 prefixes |= PREFIX_REPNZ;
10737 last_repnz_prefix = i;
10738 break;
10739 case 0xf0:
10740 prefixes |= PREFIX_LOCK;
10741 last_lock_prefix = i;
10742 break;
10743 case 0x2e:
10744 prefixes |= PREFIX_CS;
10745 last_seg_prefix = i;
10746 break;
10747 case 0x36:
10748 prefixes |= PREFIX_SS;
10749 last_seg_prefix = i;
10750 break;
10751 case 0x3e:
10752 prefixes |= PREFIX_DS;
10753 last_seg_prefix = i;
10754 break;
10755 case 0x26:
10756 prefixes |= PREFIX_ES;
10757 last_seg_prefix = i;
10758 break;
10759 case 0x64:
10760 prefixes |= PREFIX_FS;
10761 last_seg_prefix = i;
10762 break;
10763 case 0x65:
10764 prefixes |= PREFIX_GS;
10765 last_seg_prefix = i;
10766 break;
10767 case 0x66:
10768 prefixes |= PREFIX_DATA;
10769 last_data_prefix = i;
10770 break;
10771 case 0x67:
10772 prefixes |= PREFIX_ADDR;
10773 last_addr_prefix = i;
10774 break;
10775 case FWAIT_OPCODE:
10776 /* fwait is really an instruction. If there are prefixes
10777 before the fwait, they belong to the fwait, *not* to the
10778 following instruction. */
10779 if (prefixes || rex)
10780 {
10781 prefixes |= PREFIX_FWAIT;
10782 codep++;
10783 return 1;
10784 }
10785 prefixes = PREFIX_FWAIT;
10786 break;
10787 default:
10788 return 1;
10789 }
10790 /* Rex is ignored when followed by another prefix. */
10791 if (rex)
10792 {
10793 rex_used = rex;
10794 return 1;
10795 }
10796 if (*codep != FWAIT_OPCODE)
10797 all_prefixes[i++] = *codep;
10798 rex = newrex;
10799 codep++;
10800 length++;
10801 }
10802 return 0;
10803}
10804
10805static int
10806seg_prefix (int pref)
10807{
10808 switch (pref)
10809 {
10810 case 0x2e:
10811 return PREFIX_CS;
10812 case 0x36:
10813 return PREFIX_SS;
10814 case 0x3e:
10815 return PREFIX_DS;
10816 case 0x26:
10817 return PREFIX_ES;
10818 case 0x64:
10819 return PREFIX_FS;
10820 case 0x65:
10821 return PREFIX_GS;
10822 default:
10823 return 0;
10824 }
10825}
10826
10827/* Return the name of the prefix byte PREF, or NULL if PREF is not a
10828 prefix byte. */
10829
10830static const char *
10831prefix_name (int pref, int sizeflag)
10832{
10833 static const char *rexes [16] =
10834 {
10835 "rex", /* 0x40 */
10836 "rex.B", /* 0x41 */
10837 "rex.X", /* 0x42 */
10838 "rex.XB", /* 0x43 */
10839 "rex.R", /* 0x44 */
10840 "rex.RB", /* 0x45 */
10841 "rex.RX", /* 0x46 */
10842 "rex.RXB", /* 0x47 */
10843 "rex.W", /* 0x48 */
10844 "rex.WB", /* 0x49 */
10845 "rex.WX", /* 0x4a */
10846 "rex.WXB", /* 0x4b */
10847 "rex.WR", /* 0x4c */
10848 "rex.WRB", /* 0x4d */
10849 "rex.WRX", /* 0x4e */
10850 "rex.WRXB", /* 0x4f */
10851 };
10852
10853 switch (pref)
10854 {
10855 /* REX prefixes family. */
10856 case 0x40:
10857 case 0x41:
10858 case 0x42:
10859 case 0x43:
10860 case 0x44:
10861 case 0x45:
10862 case 0x46:
10863 case 0x47:
10864 case 0x48:
10865 case 0x49:
10866 case 0x4a:
10867 case 0x4b:
10868 case 0x4c:
10869 case 0x4d:
10870 case 0x4e:
10871 case 0x4f:
10872 return rexes [pref - 0x40];
10873 case 0xf3:
10874 return "repz";
10875 case 0xf2:
10876 return "repnz";
10877 case 0xf0:
10878 return "lock";
10879 case 0x2e:
10880 return "cs";
10881 case 0x36:
10882 return "ss";
10883 case 0x3e:
10884 return "ds";
10885 case 0x26:
10886 return "es";
10887 case 0x64:
10888 return "fs";
10889 case 0x65:
10890 return "gs";
10891 case 0x66:
10892 return (sizeflag & DFLAG) ? "data16" : "data32";
10893 case 0x67:
10894 if (address_mode == mode_64bit)
10895 return (sizeflag & AFLAG) ? "addr32" : "addr64";
10896 else
10897 return (sizeflag & AFLAG) ? "addr16" : "addr32";
10898 case FWAIT_OPCODE:
10899 return "fwait";
10900 case ADDR16_PREFIX:
10901 return "addr16";
10902 case ADDR32_PREFIX:
10903 return "addr32";
10904 case DATA16_PREFIX:
10905 return "data16";
10906 case DATA32_PREFIX:
10907 return "data32";
10908 case REP_PREFIX:
10909 return "rep";
10910 default:
10911 return NULL;
10912 }
10913}
10914
10915static char op_out[MAX_OPERANDS][100];
10916static int op_ad, op_index[MAX_OPERANDS];
10917static int two_source_ops;
10918static bfd_vma op_address[MAX_OPERANDS];
10919static bfd_vma op_riprel[MAX_OPERANDS];
10920static bfd_vma start_pc;
10921
10922/*
10923 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10924 * (see topic "Redundant prefixes" in the "Differences from 8086"
10925 * section of the "Virtual 8086 Mode" chapter.)
10926 * 'pc' should be the address of this instruction, it will
10927 * be used to print the target address if this is a relative jump or call
10928 * The function returns the length of this instruction in bytes.
10929 */
10930
10931static char intel_syntax;
10932static char intel_mnemonic = !SYSV386_COMPAT;
10933static char open_char;
10934static char close_char;
10935static char separator_char;
10936static char scale_char;
10937
10938/* Here for backwards compatibility. When gdb stops using
10939 print_insn_i386_att and print_insn_i386_intel these functions can
10940 disappear, and print_insn_i386 be merged into print_insn. */
10941int
10942print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10943{
10944 intel_syntax = 0;
10945
10946 return print_insn (pc, info);
10947}
10948
10949int
10950print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10951{
10952 intel_syntax = 1;
10953
10954 return print_insn (pc, info);
10955}
10956
10957int
10958print_insn_i386 (bfd_vma pc, disassemble_info *info)
10959{
10960 intel_syntax = -1;
10961
10962 return print_insn (pc, info);
10963}
10964
10965void
10966print_i386_disassembler_options (FILE *stream)
10967{
10968 fprintf (stream, _("\n\
10969The following i386/x86-64 specific disassembler options are supported for use\n\
10970with the -M switch (multiple options should be separated by commas):\n"));
10971
10972 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
10973 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
10974 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
10975 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
10976 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
10977 fprintf (stream, _(" att-mnemonic\n"
10978 " Display instruction in AT&T mnemonic\n"));
10979 fprintf (stream, _(" intel-mnemonic\n"
10980 " Display instruction in Intel mnemonic\n"));
10981 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
10982 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
10983 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
10984 fprintf (stream, _(" data32 Assume 32bit data size\n"));
10985 fprintf (stream, _(" data16 Assume 16bit data size\n"));
10986 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
10987}
10988
10989/* Bad opcode. */
10990static const struct dis386 bad_opcode = { "(bad)", { XX } };
10991
10992/* Get a pointer to struct dis386 with a valid name. */
10993
10994static const struct dis386 *
10995get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10996{
10997 int vindex, vex_table_index;
10998
10999 if (dp->name != NULL)
11000 return dp;
11001
11002 switch (dp->op[0].bytemode)
11003 {
11004 case USE_REG_TABLE:
11005 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11006 break;
11007
11008 case USE_MOD_TABLE:
11009 vindex = modrm.mod == 0x3 ? 1 : 0;
11010 dp = &mod_table[dp->op[1].bytemode][vindex];
11011 break;
11012
11013 case USE_RM_TABLE:
11014 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11015 break;
11016
11017 case USE_PREFIX_TABLE:
11018 if (need_vex)
11019 {
11020 /* The prefix in VEX is implicit. */
11021 switch (vex.prefix)
11022 {
11023 case 0:
11024 vindex = 0;
11025 break;
11026 case REPE_PREFIX_OPCODE:
11027 vindex = 1;
11028 break;
11029 case DATA_PREFIX_OPCODE:
11030 vindex = 2;
11031 break;
11032 case REPNE_PREFIX_OPCODE:
11033 vindex = 3;
11034 break;
11035 default:
11036 abort ();
11037 break;
11038 }
11039 }
11040 else
11041 {
11042 vindex = 0;
11043 used_prefixes |= (prefixes & PREFIX_REPZ);
11044 if (prefixes & PREFIX_REPZ)
11045 {
11046 vindex = 1;
11047 all_prefixes[last_repz_prefix] = 0;
11048 }
11049 else
11050 {
11051 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11052 PREFIX_DATA. */
11053 used_prefixes |= (prefixes & PREFIX_REPNZ);
11054 if (prefixes & PREFIX_REPNZ)
11055 {
11056 vindex = 3;
11057 all_prefixes[last_repnz_prefix] = 0;
11058 }
11059 else
11060 {
11061 used_prefixes |= (prefixes & PREFIX_DATA);
11062 if (prefixes & PREFIX_DATA)
11063 {
11064 vindex = 2;
11065 all_prefixes[last_data_prefix] = 0;
11066 }
11067 }
11068 }
11069 }
11070 dp = &prefix_table[dp->op[1].bytemode][vindex];
11071 break;
11072
11073 case USE_X86_64_TABLE:
11074 vindex = address_mode == mode_64bit ? 1 : 0;
11075 dp = &x86_64_table[dp->op[1].bytemode][vindex];
11076 break;
11077
11078 case USE_3BYTE_TABLE:
11079 FETCH_DATA (info, codep + 2);
11080 vindex = *codep++;
11081 dp = &three_byte_table[dp->op[1].bytemode][vindex];
11082 modrm.mod = (*codep >> 6) & 3;
11083 modrm.reg = (*codep >> 3) & 7;
11084 modrm.rm = *codep & 7;
11085 break;
11086
11087 case USE_VEX_LEN_TABLE:
11088 if (!need_vex)
11089 abort ();
11090
11091 switch (vex.length)
11092 {
11093 case 128:
11094 vindex = 0;
11095 break;
11096 case 256:
11097 vindex = 1;
11098 break;
11099 default:
11100 abort ();
11101 break;
11102 }
11103
11104 dp = &vex_len_table[dp->op[1].bytemode][vindex];
11105 break;
11106
11107 case USE_XOP_8F_TABLE:
11108 FETCH_DATA (info, codep + 3);
11109 /* All bits in the REX prefix are ignored. */
11110 rex_ignored = rex;
11111 rex = ~(*codep >> 5) & 0x7;
11112
11113 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11114 switch ((*codep & 0x1f))
11115 {
11116 default:
11117 dp = &bad_opcode;
11118 return dp;
11119 case 0x8:
11120 vex_table_index = XOP_08;
11121 break;
11122 case 0x9:
11123 vex_table_index = XOP_09;
11124 break;
11125 case 0xa:
11126 vex_table_index = XOP_0A;
11127 break;
11128 }
11129 codep++;
11130 vex.w = *codep & 0x80;
11131 if (vex.w && address_mode == mode_64bit)
11132 rex |= REX_W;
11133
11134 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11135 if (address_mode != mode_64bit
11136 && vex.register_specifier > 0x7)
11137 {
11138 dp = &bad_opcode;
11139 return dp;
11140 }
11141
11142 vex.length = (*codep & 0x4) ? 256 : 128;
11143 switch ((*codep & 0x3))
11144 {
11145 case 0:
11146 vex.prefix = 0;
11147 break;
11148 case 1:
11149 vex.prefix = DATA_PREFIX_OPCODE;
11150 break;
11151 case 2:
11152 vex.prefix = REPE_PREFIX_OPCODE;
11153 break;
11154 case 3:
11155 vex.prefix = REPNE_PREFIX_OPCODE;
11156 break;
11157 }
11158 need_vex = 1;
11159 need_vex_reg = 1;
11160 codep++;
11161 vindex = *codep++;
11162 dp = &xop_table[vex_table_index][vindex];
11163
11164 FETCH_DATA (info, codep + 1);
11165 modrm.mod = (*codep >> 6) & 3;
11166 modrm.reg = (*codep >> 3) & 7;
11167 modrm.rm = *codep & 7;
11168 break;
11169
11170 case USE_VEX_C4_TABLE:
11171 FETCH_DATA (info, codep + 3);
11172 /* All bits in the REX prefix are ignored. */
11173 rex_ignored = rex;
11174 rex = ~(*codep >> 5) & 0x7;
11175 switch ((*codep & 0x1f))
11176 {
11177 default:
11178 dp = &bad_opcode;
11179 return dp;
11180 case 0x1:
11181 vex_table_index = VEX_0F;
11182 break;
11183 case 0x2:
11184 vex_table_index = VEX_0F38;
11185 break;
11186 case 0x3:
11187 vex_table_index = VEX_0F3A;
11188 break;
11189 }
11190 codep++;
11191 vex.w = *codep & 0x80;
11192 if (vex.w && address_mode == mode_64bit)
11193 rex |= REX_W;
11194
11195 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11196 if (address_mode != mode_64bit
11197 && vex.register_specifier > 0x7)
11198 {
11199 dp = &bad_opcode;
11200 return dp;
11201 }
11202
11203 vex.length = (*codep & 0x4) ? 256 : 128;
11204 switch ((*codep & 0x3))
11205 {
11206 case 0:
11207 vex.prefix = 0;
11208 break;
11209 case 1:
11210 vex.prefix = DATA_PREFIX_OPCODE;
11211 break;
11212 case 2:
11213 vex.prefix = REPE_PREFIX_OPCODE;
11214 break;
11215 case 3:
11216 vex.prefix = REPNE_PREFIX_OPCODE;
11217 break;
11218 }
11219 need_vex = 1;
11220 need_vex_reg = 1;
11221 codep++;
11222 vindex = *codep++;
11223 dp = &vex_table[vex_table_index][vindex];
11224 /* There is no MODRM byte for VEX [82|77]. */
11225 if (vindex != 0x77 && vindex != 0x82)
11226 {
11227 FETCH_DATA (info, codep + 1);
11228 modrm.mod = (*codep >> 6) & 3;
11229 modrm.reg = (*codep >> 3) & 7;
11230 modrm.rm = *codep & 7;
11231 }
11232 break;
11233
11234 case USE_VEX_C5_TABLE:
11235 FETCH_DATA (info, codep + 2);
11236 /* All bits in the REX prefix are ignored. */
11237 rex_ignored = rex;
11238 rex = (*codep & 0x80) ? 0 : REX_R;
11239
11240 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11241 if (address_mode != mode_64bit
11242 && vex.register_specifier > 0x7)
11243 {
11244 dp = &bad_opcode;
11245 return dp;
11246 }
11247
11248 vex.w = 0;
11249
11250 vex.length = (*codep & 0x4) ? 256 : 128;
11251 switch ((*codep & 0x3))
11252 {
11253 case 0:
11254 vex.prefix = 0;
11255 break;
11256 case 1:
11257 vex.prefix = DATA_PREFIX_OPCODE;
11258 break;
11259 case 2:
11260 vex.prefix = REPE_PREFIX_OPCODE;
11261 break;
11262 case 3:
11263 vex.prefix = REPNE_PREFIX_OPCODE;
11264 break;
11265 }
11266 need_vex = 1;
11267 need_vex_reg = 1;
11268 codep++;
11269 vindex = *codep++;
11270 dp = &vex_table[dp->op[1].bytemode][vindex];
11271 /* There is no MODRM byte for VEX [82|77]. */
11272 if (vindex != 0x77 && vindex != 0x82)
11273 {
11274 FETCH_DATA (info, codep + 1);
11275 modrm.mod = (*codep >> 6) & 3;
11276 modrm.reg = (*codep >> 3) & 7;
11277 modrm.rm = *codep & 7;
11278 }
11279 break;
11280
11281 case USE_VEX_W_TABLE:
11282 if (!need_vex)
11283 abort ();
11284
11285 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11286 break;
11287
11288 case 0:
11289 dp = &bad_opcode;
11290 break;
11291
11292 default:
11293 abort ();
11294 }
11295
11296 if (dp->name != NULL)
11297 return dp;
11298 else
11299 return get_valid_dis386 (dp, info);
11300}
11301
11302static void
11303get_sib (disassemble_info *info)
11304{
11305 /* If modrm.mod == 3, operand must be register. */
11306 if (need_modrm
11307 && address_mode != mode_16bit
11308 && modrm.mod != 3
11309 && modrm.rm == 4)
11310 {
11311 FETCH_DATA (info, codep + 2);
11312 sib.index = (codep [1] >> 3) & 7;
11313 sib.scale = (codep [1] >> 6) & 3;
11314 sib.base = codep [1] & 7;
11315 }
11316}
11317
11318static int
11319print_insn (bfd_vma pc, disassemble_info *info)
11320{
11321 const struct dis386 *dp;
11322 int i;
11323 char *op_txt[MAX_OPERANDS];
11324 int needcomma;
11325 int sizeflag;
11326 const char *p;
11327 struct dis_private priv;
11328 int prefix_length;
11329 int default_prefixes;
11330
11331 if (info->mach == bfd_mach_x86_64_intel_syntax
11332 || info->mach == bfd_mach_x86_64
11333 || info->mach == bfd_mach_l1om
11334 || info->mach == bfd_mach_l1om_intel_syntax)
11335 address_mode = mode_64bit;
11336 else
11337 address_mode = mode_32bit;
11338
11339 if (intel_syntax == (char) -1)
11340 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11341 || info->mach == bfd_mach_x86_64_intel_syntax
11342 || info->mach == bfd_mach_l1om_intel_syntax);
11343
11344 if (info->mach == bfd_mach_i386_i386
11345 || info->mach == bfd_mach_x86_64
11346 || info->mach == bfd_mach_l1om
11347 || info->mach == bfd_mach_i386_i386_intel_syntax
11348 || info->mach == bfd_mach_x86_64_intel_syntax
11349 || info->mach == bfd_mach_l1om_intel_syntax)
11350 priv.orig_sizeflag = AFLAG | DFLAG;
11351 else if (info->mach == bfd_mach_i386_i8086)
11352 priv.orig_sizeflag = 0;
11353 else
11354 abort ();
11355
11356 for (p = info->disassembler_options; p != NULL; )
11357 {
11358 if (CONST_STRNEQ (p, "x86-64"))
11359 {
11360 address_mode = mode_64bit;
11361 priv.orig_sizeflag = AFLAG | DFLAG;
11362 }
11363 else if (CONST_STRNEQ (p, "i386"))
11364 {
11365 address_mode = mode_32bit;
11366 priv.orig_sizeflag = AFLAG | DFLAG;
11367 }
11368 else if (CONST_STRNEQ (p, "i8086"))
11369 {
11370 address_mode = mode_16bit;
11371 priv.orig_sizeflag = 0;
11372 }
11373 else if (CONST_STRNEQ (p, "intel"))
11374 {
11375 intel_syntax = 1;
11376 if (CONST_STRNEQ (p + 5, "-mnemonic"))
11377 intel_mnemonic = 1;
11378 }
11379 else if (CONST_STRNEQ (p, "att"))
11380 {
11381 intel_syntax = 0;
11382 if (CONST_STRNEQ (p + 3, "-mnemonic"))
11383 intel_mnemonic = 0;
11384 }
11385 else if (CONST_STRNEQ (p, "addr"))
11386 {
11387 if (address_mode == mode_64bit)
11388 {
11389 if (p[4] == '3' && p[5] == '2')
11390 priv.orig_sizeflag &= ~AFLAG;
11391 else if (p[4] == '6' && p[5] == '4')
11392 priv.orig_sizeflag |= AFLAG;
11393 }
11394 else
11395 {
11396 if (p[4] == '1' && p[5] == '6')
11397 priv.orig_sizeflag &= ~AFLAG;
11398 else if (p[4] == '3' && p[5] == '2')
11399 priv.orig_sizeflag |= AFLAG;
11400 }
11401 }
11402 else if (CONST_STRNEQ (p, "data"))
11403 {
11404 if (p[4] == '1' && p[5] == '6')
11405 priv.orig_sizeflag &= ~DFLAG;
11406 else if (p[4] == '3' && p[5] == '2')
11407 priv.orig_sizeflag |= DFLAG;
11408 }
11409 else if (CONST_STRNEQ (p, "suffix"))
11410 priv.orig_sizeflag |= SUFFIX_ALWAYS;
11411
11412 p = strchr (p, ',');
11413 if (p != NULL)
11414 p++;
11415 }
11416
11417 if (intel_syntax)
11418 {
11419 names64 = intel_names64;
11420 names32 = intel_names32;
11421 names16 = intel_names16;
11422 names8 = intel_names8;
11423 names8rex = intel_names8rex;
11424 names_seg = intel_names_seg;
11425 names_mm = intel_names_mm;
11426 names_xmm = intel_names_xmm;
11427 names_ymm = intel_names_ymm;
11428 index64 = intel_index64;
11429 index32 = intel_index32;
11430 index16 = intel_index16;
11431 open_char = '[';
11432 close_char = ']';
11433 separator_char = '+';
11434 scale_char = '*';
11435 }
11436 else
11437 {
11438 names64 = att_names64;
11439 names32 = att_names32;
11440 names16 = att_names16;
11441 names8 = att_names8;
11442 names8rex = att_names8rex;
11443 names_seg = att_names_seg;
11444 names_mm = att_names_mm;
11445 names_xmm = att_names_xmm;
11446 names_ymm = att_names_ymm;
11447 index64 = att_index64;
11448 index32 = att_index32;
11449 index16 = att_index16;
11450 open_char = '(';
11451 close_char = ')';
11452 separator_char = ',';
11453 scale_char = ',';
11454 }
11455
11456 /* The output looks better if we put 7 bytes on a line, since that
11457 puts most long word instructions on a single line. Use 8 bytes
11458 for Intel L1OM. */
11459 if (info->mach == bfd_mach_l1om
11460 || info->mach == bfd_mach_l1om_intel_syntax)
11461 info->bytes_per_line = 8;
11462 else
11463 info->bytes_per_line = 7;
11464
11465 info->private_data = &priv;
11466 priv.max_fetched = priv.the_buffer;
11467 priv.insn_start = pc;
11468
11469 obuf[0] = 0;
11470 for (i = 0; i < MAX_OPERANDS; ++i)
11471 {
11472 op_out[i][0] = 0;
11473 op_index[i] = -1;
11474 }
11475
11476 the_info = info;
11477 start_pc = pc;
11478 start_codep = priv.the_buffer;
11479 codep = priv.the_buffer;
11480
11481 if (setjmp (priv.bailout) != 0)
11482 {
11483 const char *name;
11484
11485 /* Getting here means we tried for data but didn't get it. That
11486 means we have an incomplete instruction of some sort. Just
11487 print the first byte as a prefix or a .byte pseudo-op. */
11488 if (codep > priv.the_buffer)
11489 {
11490 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11491 if (name != NULL)
11492 (*info->fprintf_func) (info->stream, "%s", name);
11493 else
11494 {
11495 /* Just print the first byte as a .byte instruction. */
11496 (*info->fprintf_func) (info->stream, ".byte 0x%x",
11497 (unsigned int) priv.the_buffer[0]);
11498 }
11499
11500 return 1;
11501 }
11502
11503 return -1;
11504 }
11505
11506 obufp = obuf;
11507 sizeflag = priv.orig_sizeflag;
11508
11509 if (!ckprefix () || rex_used)
11510 {
11511 /* Too many prefixes or unused REX prefixes. */
11512 for (i = 0;
11513 all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11514 i++)
11515 (*info->fprintf_func) (info->stream, "%s",
11516 prefix_name (all_prefixes[i], sizeflag));
11517 return 1;
11518 }
11519
11520 insn_codep = codep;
11521
11522 FETCH_DATA (info, codep + 1);
11523 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11524
11525 if (((prefixes & PREFIX_FWAIT)
11526 && ((*codep < 0xd8) || (*codep > 0xdf))))
11527 {
11528 (*info->fprintf_func) (info->stream, "fwait");
11529 return 1;
11530 }
11531
11532 if (*codep == 0x0f)
11533 {
11534 unsigned char threebyte;
11535 FETCH_DATA (info, codep + 2);
11536 threebyte = *++codep;
11537 dp = &dis386_twobyte[threebyte];
11538 need_modrm = twobyte_has_modrm[*codep];
11539 codep++;
11540 }
11541 else
11542 {
11543 dp = &dis386[*codep];
11544 need_modrm = onebyte_has_modrm[*codep];
11545 codep++;
11546 }
11547
11548 if ((prefixes & PREFIX_REPZ))
11549 used_prefixes |= PREFIX_REPZ;
11550 if ((prefixes & PREFIX_REPNZ))
11551 used_prefixes |= PREFIX_REPNZ;
11552 if ((prefixes & PREFIX_LOCK))
11553 used_prefixes |= PREFIX_LOCK;
11554
11555 default_prefixes = 0;
11556 if (prefixes & PREFIX_ADDR)
11557 {
11558 sizeflag ^= AFLAG;
11559 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11560 {
11561 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11562 all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11563 else
11564 all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11565 default_prefixes |= PREFIX_ADDR;
11566 }
11567 }
11568
11569 if ((prefixes & PREFIX_DATA))
11570 {
11571 sizeflag ^= DFLAG;
11572 if (dp->op[2].bytemode == cond_jump_mode
11573 && dp->op[0].bytemode == v_mode
11574 && !intel_syntax)
11575 {
11576 if (sizeflag & DFLAG)
11577 all_prefixes[last_data_prefix] = DATA32_PREFIX;
11578 else
11579 all_prefixes[last_data_prefix] = DATA16_PREFIX;
11580 default_prefixes |= PREFIX_DATA;
11581 }
11582 else if (rex & REX_W)
11583 {
11584 /* REX_W will override PREFIX_DATA. */
11585 default_prefixes |= PREFIX_DATA;
11586 }
11587 }
11588
11589 if (need_modrm)
11590 {
11591 FETCH_DATA (info, codep + 1);
11592 modrm.mod = (*codep >> 6) & 3;
11593 modrm.reg = (*codep >> 3) & 7;
11594 modrm.rm = *codep & 7;
11595 }
11596
11597 need_vex = 0;
11598 need_vex_reg = 0;
11599 vex_w_done = 0;
11600
11601 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11602 {
11603 get_sib (info);
11604 dofloat (sizeflag);
11605 }
11606 else
11607 {
11608 dp = get_valid_dis386 (dp, info);
11609 if (dp != NULL && putop (dp->name, sizeflag) == 0)
11610 {
11611 get_sib (info);
11612 for (i = 0; i < MAX_OPERANDS; ++i)
11613 {
11614 obufp = op_out[i];
11615 op_ad = MAX_OPERANDS - 1 - i;
11616 if (dp->op[i].rtn)
11617 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11618 }
11619 }
11620 }
11621
11622 /* See if any prefixes were not used. If so, print the first one
11623 separately. If we don't do this, we'll wind up printing an
11624 instruction stream which does not precisely correspond to the
11625 bytes we are disassembling. */
11626 if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11627 {
11628 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11629 if (all_prefixes[i])
11630 {
11631 const char *name;
11632 name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11633 if (name == NULL)
11634 name = INTERNAL_DISASSEMBLER_ERROR;
11635 (*info->fprintf_func) (info->stream, "%s", name);
11636 return 1;
11637 }
11638 }
11639
11640 /* Check if the REX prefix is used. */
11641 if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11642 all_prefixes[last_rex_prefix] = 0;
11643
11644 /* Check if the SEG prefix is used. */
11645 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11646 | PREFIX_FS | PREFIX_GS)) != 0
11647 && (used_prefixes
11648 & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11649 all_prefixes[last_seg_prefix] = 0;
11650
11651 /* Check if the ADDR prefix is used. */
11652 if ((prefixes & PREFIX_ADDR) != 0
11653 && (used_prefixes & PREFIX_ADDR) != 0)
11654 all_prefixes[last_addr_prefix] = 0;
11655
11656 /* Check if the DATA prefix is used. */
11657 if ((prefixes & PREFIX_DATA) != 0
11658 && (used_prefixes & PREFIX_DATA) != 0)
11659 all_prefixes[last_data_prefix] = 0;
11660
11661 prefix_length = 0;
11662 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11663 if (all_prefixes[i])
11664 {
11665 const char *name;
11666 name = prefix_name (all_prefixes[i], sizeflag);
11667 if (name == NULL)
11668 abort ();
11669 prefix_length += strlen (name) + 1;
11670 (*info->fprintf_func) (info->stream, "%s ", name);
11671 }
11672
11673 /* Check maximum code length. */
11674 if ((codep - start_codep) > MAX_CODE_LENGTH)
11675 {
11676 (*info->fprintf_func) (info->stream, "(bad)");
11677 return MAX_CODE_LENGTH;
11678 }
11679
11680 obufp = mnemonicendp;
11681 for (i = strlen (obuf) + prefix_length; i < 6; i++)
11682 oappend (" ");
11683 oappend (" ");
11684 (*info->fprintf_func) (info->stream, "%s", obuf);
11685
11686 /* The enter and bound instructions are printed with operands in the same
11687 order as the intel book; everything else is printed in reverse order. */
11688 if (intel_syntax || two_source_ops)
11689 {
11690 bfd_vma riprel;
11691
11692 for (i = 0; i < MAX_OPERANDS; ++i)
11693 op_txt[i] = op_out[i];
11694
11695 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11696 {
11697 op_ad = op_index[i];
11698 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11699 op_index[MAX_OPERANDS - 1 - i] = op_ad;
11700 riprel = op_riprel[i];
11701 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11702 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11703 }
11704 }
11705 else
11706 {
11707 for (i = 0; i < MAX_OPERANDS; ++i)
11708 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11709 }
11710
11711 needcomma = 0;
11712 for (i = 0; i < MAX_OPERANDS; ++i)
11713 if (*op_txt[i])
11714 {
11715 if (needcomma)
11716 (*info->fprintf_func) (info->stream, ",");
11717 if (op_index[i] != -1 && !op_riprel[i])
11718 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11719 else
11720 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11721 needcomma = 1;
11722 }
11723
11724 for (i = 0; i < MAX_OPERANDS; i++)
11725 if (op_index[i] != -1 && op_riprel[i])
11726 {
11727 (*info->fprintf_func) (info->stream, " # ");
11728 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11729 + op_address[op_index[i]]), info);
11730 break;
11731 }
11732 return codep - priv.the_buffer;
11733}
11734
11735static const char *float_mem[] = {
11736 /* d8 */
11737 "fadd{s|}",
11738 "fmul{s|}",
11739 "fcom{s|}",
11740 "fcomp{s|}",
11741 "fsub{s|}",
11742 "fsubr{s|}",
11743 "fdiv{s|}",
11744 "fdivr{s|}",
11745 /* d9 */
11746 "fld{s|}",
11747 "(bad)",
11748 "fst{s|}",
11749 "fstp{s|}",
11750 "fldenvIC",
11751 "fldcw",
11752 "fNstenvIC",
11753 "fNstcw",
11754 /* da */
11755 "fiadd{l|}",
11756 "fimul{l|}",
11757 "ficom{l|}",
11758 "ficomp{l|}",
11759 "fisub{l|}",
11760 "fisubr{l|}",
11761 "fidiv{l|}",
11762 "fidivr{l|}",
11763 /* db */
11764 "fild{l|}",
11765 "fisttp{l|}",
11766 "fist{l|}",
11767 "fistp{l|}",
11768 "(bad)",
11769 "fld{t||t|}",
11770 "(bad)",
11771 "fstp{t||t|}",
11772 /* dc */
11773 "fadd{l|}",
11774 "fmul{l|}",
11775 "fcom{l|}",
11776 "fcomp{l|}",
11777 "fsub{l|}",
11778 "fsubr{l|}",
11779 "fdiv{l|}",
11780 "fdivr{l|}",
11781 /* dd */
11782 "fld{l|}",
11783 "fisttp{ll|}",
11784 "fst{l||}",
11785 "fstp{l|}",
11786 "frstorIC",
11787 "(bad)",
11788 "fNsaveIC",
11789 "fNstsw",
11790 /* de */
11791 "fiadd",
11792 "fimul",
11793 "ficom",
11794 "ficomp",
11795 "fisub",
11796 "fisubr",
11797 "fidiv",
11798 "fidivr",
11799 /* df */
11800 "fild",
11801 "fisttp",
11802 "fist",
11803 "fistp",
11804 "fbld",
11805 "fild{ll|}",
11806 "fbstp",
11807 "fistp{ll|}",
11808};
11809
11810static const unsigned char float_mem_mode[] = {
11811 /* d8 */
11812 d_mode,
11813 d_mode,
11814 d_mode,
11815 d_mode,
11816 d_mode,
11817 d_mode,
11818 d_mode,
11819 d_mode,
11820 /* d9 */
11821 d_mode,
11822 0,
11823 d_mode,
11824 d_mode,
11825 0,
11826 w_mode,
11827 0,
11828 w_mode,
11829 /* da */
11830 d_mode,
11831 d_mode,
11832 d_mode,
11833 d_mode,
11834 d_mode,
11835 d_mode,
11836 d_mode,
11837 d_mode,
11838 /* db */
11839 d_mode,
11840 d_mode,
11841 d_mode,
11842 d_mode,
11843 0,
11844 t_mode,
11845 0,
11846 t_mode,
11847 /* dc */
11848 q_mode,
11849 q_mode,
11850 q_mode,
11851 q_mode,
11852 q_mode,
11853 q_mode,
11854 q_mode,
11855 q_mode,
11856 /* dd */
11857 q_mode,
11858 q_mode,
11859 q_mode,
11860 q_mode,
11861 0,
11862 0,
11863 0,
11864 w_mode,
11865 /* de */
11866 w_mode,
11867 w_mode,
11868 w_mode,
11869 w_mode,
11870 w_mode,
11871 w_mode,
11872 w_mode,
11873 w_mode,
11874 /* df */
11875 w_mode,
11876 w_mode,
11877 w_mode,
11878 w_mode,
11879 t_mode,
11880 q_mode,
11881 t_mode,
11882 q_mode
11883};
11884
11885#define ST { OP_ST, 0 }
11886#define STi { OP_STi, 0 }
11887
11888#define FGRPd9_2 NULL, { { NULL, 0 } }
11889#define FGRPd9_4 NULL, { { NULL, 1 } }
11890#define FGRPd9_5 NULL, { { NULL, 2 } }
11891#define FGRPd9_6 NULL, { { NULL, 3 } }
11892#define FGRPd9_7 NULL, { { NULL, 4 } }
11893#define FGRPda_5 NULL, { { NULL, 5 } }
11894#define FGRPdb_4 NULL, { { NULL, 6 } }
11895#define FGRPde_3 NULL, { { NULL, 7 } }
11896#define FGRPdf_4 NULL, { { NULL, 8 } }
11897
11898static const struct dis386 float_reg[][8] = {
11899 /* d8 */
11900 {
11901 { "fadd", { ST, STi } },
11902 { "fmul", { ST, STi } },
11903 { "fcom", { STi } },
11904 { "fcomp", { STi } },
11905 { "fsub", { ST, STi } },
11906 { "fsubr", { ST, STi } },
11907 { "fdiv", { ST, STi } },
11908 { "fdivr", { ST, STi } },
11909 },
11910 /* d9 */
11911 {
11912 { "fld", { STi } },
11913 { "fxch", { STi } },
11914 { FGRPd9_2 },
11915 { Bad_Opcode },
11916 { FGRPd9_4 },
11917 { FGRPd9_5 },
11918 { FGRPd9_6 },
11919 { FGRPd9_7 },
11920 },
11921 /* da */
11922 {
11923 { "fcmovb", { ST, STi } },
11924 { "fcmove", { ST, STi } },
11925 { "fcmovbe",{ ST, STi } },
11926 { "fcmovu", { ST, STi } },
11927 { Bad_Opcode },
11928 { FGRPda_5 },
11929 { Bad_Opcode },
11930 { Bad_Opcode },
11931 },
11932 /* db */
11933 {
11934 { "fcmovnb",{ ST, STi } },
11935 { "fcmovne",{ ST, STi } },
11936 { "fcmovnbe",{ ST, STi } },
11937 { "fcmovnu",{ ST, STi } },
11938 { FGRPdb_4 },
11939 { "fucomi", { ST, STi } },
11940 { "fcomi", { ST, STi } },
11941 { Bad_Opcode },
11942 },
11943 /* dc */
11944 {
11945 { "fadd", { STi, ST } },
11946 { "fmul", { STi, ST } },
11947 { Bad_Opcode },
11948 { Bad_Opcode },
11949 { "fsub!M", { STi, ST } },
11950 { "fsubM", { STi, ST } },
11951 { "fdiv!M", { STi, ST } },
11952 { "fdivM", { STi, ST } },
11953 },
11954 /* dd */
11955 {
11956 { "ffree", { STi } },
11957 { Bad_Opcode },
11958 { "fst", { STi } },
11959 { "fstp", { STi } },
11960 { "fucom", { STi } },
11961 { "fucomp", { STi } },
11962 { Bad_Opcode },
11963 { Bad_Opcode },
11964 },
11965 /* de */
11966 {
11967 { "faddp", { STi, ST } },
11968 { "fmulp", { STi, ST } },
11969 { Bad_Opcode },
11970 { FGRPde_3 },
11971 { "fsub!Mp", { STi, ST } },
11972 { "fsubMp", { STi, ST } },
11973 { "fdiv!Mp", { STi, ST } },
11974 { "fdivMp", { STi, ST } },
11975 },
11976 /* df */
11977 {
11978 { "ffreep", { STi } },
11979 { Bad_Opcode },
11980 { Bad_Opcode },
11981 { Bad_Opcode },
11982 { FGRPdf_4 },
11983 { "fucomip", { ST, STi } },
11984 { "fcomip", { ST, STi } },
11985 { Bad_Opcode },
11986 },
11987};
11988
11989static char *fgrps[][8] = {
11990 /* d9_2 0 */
11991 {
11992 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11993 },
11994
11995 /* d9_4 1 */
11996 {
11997 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11998 },
11999
12000 /* d9_5 2 */
12001 {
12002 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12003 },
12004
12005 /* d9_6 3 */
12006 {
12007 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12008 },
12009
12010 /* d9_7 4 */
12011 {
12012 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12013 },
12014
12015 /* da_5 5 */
12016 {
12017 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12018 },
12019
12020 /* db_4 6 */
12021 {
12022 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12023 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12024 },
12025
12026 /* de_3 7 */
12027 {
12028 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12029 },
12030
12031 /* df_4 8 */
12032 {
12033 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12034 },
12035};
12036
12037static void
12038swap_operand (void)
12039{
12040 mnemonicendp[0] = '.';
12041 mnemonicendp[1] = 's';
12042 mnemonicendp += 2;
12043}
12044
12045static void
12046OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12047 int sizeflag ATTRIBUTE_UNUSED)
12048{
12049 /* Skip mod/rm byte. */
12050 MODRM_CHECK;
12051 codep++;
12052}
12053
12054static void
12055dofloat (int sizeflag)
12056{
12057 const struct dis386 *dp;
12058 unsigned char floatop;
12059
12060 floatop = codep[-1];
12061
12062 if (modrm.mod != 3)
12063 {
12064 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12065
12066 putop (float_mem[fp_indx], sizeflag);
12067 obufp = op_out[0];
12068 op_ad = 2;
12069 OP_E (float_mem_mode[fp_indx], sizeflag);
12070 return;
12071 }
12072 /* Skip mod/rm byte. */
12073 MODRM_CHECK;
12074 codep++;
12075
12076 dp = &float_reg[floatop - 0xd8][modrm.reg];
12077 if (dp->name == NULL)
12078 {
12079 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12080
12081 /* Instruction fnstsw is only one with strange arg. */
12082 if (floatop == 0xdf && codep[-1] == 0xe0)
12083 strcpy (op_out[0], names16[0]);
12084 }
12085 else
12086 {
12087 putop (dp->name, sizeflag);
12088
12089 obufp = op_out[0];
12090 op_ad = 2;
12091 if (dp->op[0].rtn)
12092 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12093
12094 obufp = op_out[1];
12095 op_ad = 1;
12096 if (dp->op[1].rtn)
12097 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12098 }
12099}
12100
12101static void
12102OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12103{
12104 oappend ("%st" + intel_syntax);
12105}
12106
12107static void
12108OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12109{
12110 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12111 oappend (scratchbuf + intel_syntax);
12112}
12113
12114/* Capital letters in template are macros. */
12115static int
12116putop (const char *in_template, int sizeflag)
12117{
12118 const char *p;
12119 int alt = 0;
12120 int cond = 1;
12121 unsigned int l = 0, len = 1;
12122 char last[4];
12123
12124#define SAVE_LAST(c) \
12125 if (l < len && l < sizeof (last)) \
12126 last[l++] = c; \
12127 else \
12128 abort ();
12129
12130 for (p = in_template; *p; p++)
12131 {
12132 switch (*p)
12133 {
12134 default:
12135 *obufp++ = *p;
12136 break;
12137 case '%':
12138 len++;
12139 break;
12140 case '!':
12141 cond = 0;
12142 break;
12143 case '{':
12144 alt = 0;
12145 if (intel_syntax)
12146 {
12147 while (*++p != '|')
12148 if (*p == '}' || *p == '\0')
12149 abort ();
12150 }
12151 /* Fall through. */
12152 case 'I':
12153 alt = 1;
12154 continue;
12155 case '|':
12156 while (*++p != '}')
12157 {
12158 if (*p == '\0')
12159 abort ();
12160 }
12161 break;
12162 case '}':
12163 break;
12164 case 'A':
12165 if (intel_syntax)
12166 break;
12167 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12168 *obufp++ = 'b';
12169 break;
12170 case 'B':
12171 if (l == 0 && len == 1)
12172 {
12173case_B:
12174 if (intel_syntax)
12175 break;
12176 if (sizeflag & SUFFIX_ALWAYS)
12177 *obufp++ = 'b';
12178 }
12179 else
12180 {
12181 if (l != 1
12182 || len != 2
12183 || last[0] != 'L')
12184 {
12185 SAVE_LAST (*p);
12186 break;
12187 }
12188
12189 if (address_mode == mode_64bit
12190 && !(prefixes & PREFIX_ADDR))
12191 {
12192 *obufp++ = 'a';
12193 *obufp++ = 'b';
12194 *obufp++ = 's';
12195 }
12196
12197 goto case_B;
12198 }
12199 break;
12200 case 'C':
12201 if (intel_syntax && !alt)
12202 break;
12203 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12204 {
12205 if (sizeflag & DFLAG)
12206 *obufp++ = intel_syntax ? 'd' : 'l';
12207 else
12208 *obufp++ = intel_syntax ? 'w' : 's';
12209 used_prefixes |= (prefixes & PREFIX_DATA);
12210 }
12211 break;
12212 case 'D':
12213 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12214 break;
12215 USED_REX (REX_W);
12216 if (modrm.mod == 3)
12217 {
12218 if (rex & REX_W)
12219 *obufp++ = 'q';
12220 else
12221 {
12222 if (sizeflag & DFLAG)
12223 *obufp++ = intel_syntax ? 'd' : 'l';
12224 else
12225 *obufp++ = 'w';
12226 used_prefixes |= (prefixes & PREFIX_DATA);
12227 }
12228 }
12229 else
12230 *obufp++ = 'w';
12231 break;
12232 case 'E': /* For jcxz/jecxz */
12233 if (address_mode == mode_64bit)
12234 {
12235 if (sizeflag & AFLAG)
12236 *obufp++ = 'r';
12237 else
12238 *obufp++ = 'e';
12239 }
12240 else
12241 if (sizeflag & AFLAG)
12242 *obufp++ = 'e';
12243 used_prefixes |= (prefixes & PREFIX_ADDR);
12244 break;
12245 case 'F':
12246 if (intel_syntax)
12247 break;
12248 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12249 {
12250 if (sizeflag & AFLAG)
12251 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12252 else
12253 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12254 used_prefixes |= (prefixes & PREFIX_ADDR);
12255 }
12256 break;
12257 case 'G':
12258 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12259 break;
12260 if ((rex & REX_W) || (sizeflag & DFLAG))
12261 *obufp++ = 'l';
12262 else
12263 *obufp++ = 'w';
12264 if (!(rex & REX_W))
12265 used_prefixes |= (prefixes & PREFIX_DATA);
12266 break;
12267 case 'H':
12268 if (intel_syntax)
12269 break;
12270 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12271 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12272 {
12273 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12274 *obufp++ = ',';
12275 *obufp++ = 'p';
12276 if (prefixes & PREFIX_DS)
12277 *obufp++ = 't';
12278 else
12279 *obufp++ = 'n';
12280 }
12281 break;
12282 case 'J':
12283 if (intel_syntax)
12284 break;
12285 *obufp++ = 'l';
12286 break;
12287 case 'K':
12288 USED_REX (REX_W);
12289 if (rex & REX_W)
12290 *obufp++ = 'q';
12291 else
12292 *obufp++ = 'd';
12293 break;
12294 case 'Z':
12295 if (intel_syntax)
12296 break;
12297 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12298 {
12299 *obufp++ = 'q';
12300 break;
12301 }
12302 /* Fall through. */
12303 goto case_L;
12304 case 'L':
12305 if (l != 0 || len != 1)
12306 {
12307 SAVE_LAST (*p);
12308 break;
12309 }
12310case_L:
12311 if (intel_syntax)
12312 break;
12313 if (sizeflag & SUFFIX_ALWAYS)
12314 *obufp++ = 'l';
12315 break;
12316 case 'M':
12317 if (intel_mnemonic != cond)
12318 *obufp++ = 'r';
12319 break;
12320 case 'N':
12321 if ((prefixes & PREFIX_FWAIT) == 0)
12322 *obufp++ = 'n';
12323 else
12324 used_prefixes |= PREFIX_FWAIT;
12325 break;
12326 case 'O':
12327 USED_REX (REX_W);
12328 if (rex & REX_W)
12329 *obufp++ = 'o';
12330 else if (intel_syntax && (sizeflag & DFLAG))
12331 *obufp++ = 'q';
12332 else
12333 *obufp++ = 'd';
12334 if (!(rex & REX_W))
12335 used_prefixes |= (prefixes & PREFIX_DATA);
12336 break;
12337 case 'T':
12338 if (intel_syntax)
12339 break;
12340 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12341 {
12342 *obufp++ = 'q';
12343 break;
12344 }
12345 /* Fall through. */
12346 case 'P':
12347 if (intel_syntax)
12348 break;
12349 if ((prefixes & PREFIX_DATA)
12350 || (rex & REX_W)
12351 || (sizeflag & SUFFIX_ALWAYS))
12352 {
12353 USED_REX (REX_W);
12354 if (rex & REX_W)
12355 *obufp++ = 'q';
12356 else
12357 {
12358 if (sizeflag & DFLAG)
12359 *obufp++ = 'l';
12360 else
12361 *obufp++ = 'w';
12362 used_prefixes |= (prefixes & PREFIX_DATA);
12363 }
12364 }
12365 break;
12366 case 'U':
12367 if (intel_syntax)
12368 break;
12369 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12370 {
12371 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12372 *obufp++ = 'q';
12373 break;
12374 }
12375 /* Fall through. */
12376 goto case_Q;
12377 case 'Q':
12378 if (l == 0 && len == 1)
12379 {
12380case_Q:
12381 if (intel_syntax && !alt)
12382 break;
12383 USED_REX (REX_W);
12384 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12385 {
12386 if (rex & REX_W)
12387 *obufp++ = 'q';
12388 else
12389 {
12390 if (sizeflag & DFLAG)
12391 *obufp++ = intel_syntax ? 'd' : 'l';
12392 else
12393 *obufp++ = 'w';
12394 used_prefixes |= (prefixes & PREFIX_DATA);
12395 }
12396 }
12397 }
12398 else
12399 {
12400 if (l != 1 || len != 2 || last[0] != 'L')
12401 {
12402 SAVE_LAST (*p);
12403 break;
12404 }
12405 if (intel_syntax
12406 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12407 break;
12408 if ((rex & REX_W))
12409 {
12410 USED_REX (REX_W);
12411 *obufp++ = 'q';
12412 }
12413 else
12414 *obufp++ = 'l';
12415 }
12416 break;
12417 case 'R':
12418 USED_REX (REX_W);
12419 if (rex & REX_W)
12420 *obufp++ = 'q';
12421 else if (sizeflag & DFLAG)
12422 {
12423 if (intel_syntax)
12424 *obufp++ = 'd';
12425 else
12426 *obufp++ = 'l';
12427 }
12428 else
12429 *obufp++ = 'w';
12430 if (intel_syntax && !p[1]
12431 && ((rex & REX_W) || (sizeflag & DFLAG)))
12432 *obufp++ = 'e';
12433 if (!(rex & REX_W))
12434 used_prefixes |= (prefixes & PREFIX_DATA);
12435 break;
12436 case 'V':
12437 if (l == 0 && len == 1)
12438 {
12439 if (intel_syntax)
12440 break;
12441 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12442 {
12443 if (sizeflag & SUFFIX_ALWAYS)
12444 *obufp++ = 'q';
12445 break;
12446 }
12447 }
12448 else
12449 {
12450 if (l != 1
12451 || len != 2
12452 || last[0] != 'L')
12453 {
12454 SAVE_LAST (*p);
12455 break;
12456 }
12457
12458 if (rex & REX_W)
12459 {
12460 *obufp++ = 'a';
12461 *obufp++ = 'b';
12462 *obufp++ = 's';
12463 }
12464 }
12465 /* Fall through. */
12466 goto case_S;
12467 case 'S':
12468 if (l == 0 && len == 1)
12469 {
12470case_S:
12471 if (intel_syntax)
12472 break;
12473 if (sizeflag & SUFFIX_ALWAYS)
12474 {
12475 if (rex & REX_W)
12476 *obufp++ = 'q';
12477 else
12478 {
12479 if (sizeflag & DFLAG)
12480 *obufp++ = 'l';
12481 else
12482 *obufp++ = 'w';
12483 used_prefixes |= (prefixes & PREFIX_DATA);
12484 }
12485 }
12486 }
12487 else
12488 {
12489 if (l != 1
12490 || len != 2
12491 || last[0] != 'L')
12492 {
12493 SAVE_LAST (*p);
12494 break;
12495 }
12496
12497 if (address_mode == mode_64bit
12498 && !(prefixes & PREFIX_ADDR))
12499 {
12500 *obufp++ = 'a';
12501 *obufp++ = 'b';
12502 *obufp++ = 's';
12503 }
12504
12505 goto case_S;
12506 }
12507 break;
12508 case 'X':
12509 if (l != 0 || len != 1)
12510 {
12511 SAVE_LAST (*p);
12512 break;
12513 }
12514 if (need_vex && vex.prefix)
12515 {
12516 if (vex.prefix == DATA_PREFIX_OPCODE)
12517 *obufp++ = 'd';
12518 else
12519 *obufp++ = 's';
12520 }
12521 else
12522 {
12523 if (prefixes & PREFIX_DATA)
12524 *obufp++ = 'd';
12525 else
12526 *obufp++ = 's';
12527 used_prefixes |= (prefixes & PREFIX_DATA);
12528 }
12529 break;
12530 case 'Y':
12531 if (l == 0 && len == 1)
12532 {
12533 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12534 break;
12535 if (rex & REX_W)
12536 {
12537 USED_REX (REX_W);
12538 *obufp++ = 'q';
12539 }
12540 break;
12541 }
12542 else
12543 {
12544 if (l != 1 || len != 2 || last[0] != 'X')
12545 {
12546 SAVE_LAST (*p);
12547 break;
12548 }
12549 if (!need_vex)
12550 abort ();
12551 if (intel_syntax
12552 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12553 break;
12554 switch (vex.length)
12555 {
12556 case 128:
12557 *obufp++ = 'x';
12558 break;
12559 case 256:
12560 *obufp++ = 'y';
12561 break;
12562 default:
12563 abort ();
12564 }
12565 }
12566 break;
12567 case 'W':
12568 if (l == 0 && len == 1)
12569 {
12570 /* operand size flag for cwtl, cbtw */
12571 USED_REX (REX_W);
12572 if (rex & REX_W)
12573 {
12574 if (intel_syntax)
12575 *obufp++ = 'd';
12576 else
12577 *obufp++ = 'l';
12578 }
12579 else if (sizeflag & DFLAG)
12580 *obufp++ = 'w';
12581 else
12582 *obufp++ = 'b';
12583 if (!(rex & REX_W))
12584 used_prefixes |= (prefixes & PREFIX_DATA);
12585 }
12586 else
12587 {
12588 if (l != 1 || len != 2 || last[0] != 'X')
12589 {
12590 SAVE_LAST (*p);
12591 break;
12592 }
12593 if (!need_vex)
12594 abort ();
12595 *obufp++ = vex.w ? 'd': 's';
12596 }
12597 break;
12598 }
12599 alt = 0;
12600 }
12601 *obufp = 0;
12602 mnemonicendp = obufp;
12603 return 0;
12604}
12605
12606static void
12607oappend (const char *s)
12608{
12609 obufp = stpcpy (obufp, s);
12610}
12611
12612static void
12613append_seg (void)
12614{
12615 if (prefixes & PREFIX_CS)
12616 {
12617 used_prefixes |= PREFIX_CS;
12618 oappend ("%cs:" + intel_syntax);
12619 }
12620 if (prefixes & PREFIX_DS)
12621 {
12622 used_prefixes |= PREFIX_DS;
12623 oappend ("%ds:" + intel_syntax);
12624 }
12625 if (prefixes & PREFIX_SS)
12626 {
12627 used_prefixes |= PREFIX_SS;
12628 oappend ("%ss:" + intel_syntax);
12629 }
12630 if (prefixes & PREFIX_ES)
12631 {
12632 used_prefixes |= PREFIX_ES;
12633 oappend ("%es:" + intel_syntax);
12634 }
12635 if (prefixes & PREFIX_FS)
12636 {
12637 used_prefixes |= PREFIX_FS;
12638 oappend ("%fs:" + intel_syntax);
12639 }
12640 if (prefixes & PREFIX_GS)
12641 {
12642 used_prefixes |= PREFIX_GS;
12643 oappend ("%gs:" + intel_syntax);
12644 }
12645}
12646
12647static void
12648OP_indirE (int bytemode, int sizeflag)
12649{
12650 if (!intel_syntax)
12651 oappend ("*");
12652 OP_E (bytemode, sizeflag);
12653}
12654
12655static void
12656print_operand_value (char *buf, int hex, bfd_vma disp)
12657{
12658 if (address_mode == mode_64bit)
12659 {
12660 if (hex)
12661 {
12662 char tmp[30];
12663 int i;
12664 buf[0] = '0';
12665 buf[1] = 'x';
12666 sprintf_vma (tmp, disp);
12667 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12668 strcpy (buf + 2, tmp + i);
12669 }
12670 else
12671 {
12672 bfd_signed_vma v = disp;
12673 char tmp[30];
12674 int i;
12675 if (v < 0)
12676 {
12677 *(buf++) = '-';
12678 v = -disp;
12679 /* Check for possible overflow on 0x8000000000000000. */
12680 if (v < 0)
12681 {
12682 strcpy (buf, "9223372036854775808");
12683 return;
12684 }
12685 }
12686 if (!v)
12687 {
12688 strcpy (buf, "0");
12689 return;
12690 }
12691
12692 i = 0;
12693 tmp[29] = 0;
12694 while (v)
12695 {
12696 tmp[28 - i] = (v % 10) + '0';
12697 v /= 10;
12698 i++;
12699 }
12700 strcpy (buf, tmp + 29 - i);
12701 }
12702 }
12703 else
12704 {
12705 if (hex)
12706 sprintf (buf, "0x%x", (unsigned int) disp);
12707 else
12708 sprintf (buf, "%d", (int) disp);
12709 }
12710}
12711
12712/* Put DISP in BUF as signed hex number. */
12713
12714static void
12715print_displacement (char *buf, bfd_vma disp)
12716{
12717 bfd_signed_vma val = disp;
12718 char tmp[30];
12719 int i, j = 0;
12720
12721 if (val < 0)
12722 {
12723 buf[j++] = '-';
12724 val = -disp;
12725
12726 /* Check for possible overflow. */
12727 if (val < 0)
12728 {
12729 switch (address_mode)
12730 {
12731 case mode_64bit:
12732 strcpy (buf + j, "0x8000000000000000");
12733 break;
12734 case mode_32bit:
12735 strcpy (buf + j, "0x80000000");
12736 break;
12737 case mode_16bit:
12738 strcpy (buf + j, "0x8000");
12739 break;
12740 }
12741 return;
12742 }
12743 }
12744
12745 buf[j++] = '0';
12746 buf[j++] = 'x';
12747
12748 sprintf_vma (tmp, (bfd_vma) val);
12749 for (i = 0; tmp[i] == '0'; i++)
12750 continue;
12751 if (tmp[i] == '\0')
12752 i--;
12753 strcpy (buf + j, tmp + i);
12754}
12755
12756static void
12757intel_operand_size (int bytemode, int sizeflag)
12758{
12759 switch (bytemode)
12760 {
12761 case b_mode:
12762 case b_swap_mode:
12763 case dqb_mode:
12764 oappend ("BYTE PTR ");
12765 break;
12766 case w_mode:
12767 case dqw_mode:
12768 oappend ("WORD PTR ");
12769 break;
12770 case stack_v_mode:
12771 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12772 {
12773 oappend ("QWORD PTR ");
12774 break;
12775 }
12776 /* FALLTHRU */
12777 case v_mode:
12778 case v_swap_mode:
12779 case dq_mode:
12780 USED_REX (REX_W);
12781 if (rex & REX_W)
12782 oappend ("QWORD PTR ");
12783 else
12784 {
12785 if ((sizeflag & DFLAG) || bytemode == dq_mode)
12786 oappend ("DWORD PTR ");
12787 else
12788 oappend ("WORD PTR ");
12789 used_prefixes |= (prefixes & PREFIX_DATA);
12790 }
12791 break;
12792 case z_mode:
12793 if ((rex & REX_W) || (sizeflag & DFLAG))
12794 *obufp++ = 'D';
12795 oappend ("WORD PTR ");
12796 if (!(rex & REX_W))
12797 used_prefixes |= (prefixes & PREFIX_DATA);
12798 break;
12799 case a_mode:
12800 if (sizeflag & DFLAG)
12801 oappend ("QWORD PTR ");
12802 else
12803 oappend ("DWORD PTR ");
12804 used_prefixes |= (prefixes & PREFIX_DATA);
12805 break;
12806 case d_mode:
12807 case d_scalar_mode:
12808 case d_scalar_swap_mode:
12809 case d_swap_mode:
12810 case dqd_mode:
12811 oappend ("DWORD PTR ");
12812 break;
12813 case q_mode:
12814 case q_scalar_mode:
12815 case q_scalar_swap_mode:
12816 case q_swap_mode:
12817 oappend ("QWORD PTR ");
12818 break;
12819 case m_mode:
12820 if (address_mode == mode_64bit)
12821 oappend ("QWORD PTR ");
12822 else
12823 oappend ("DWORD PTR ");
12824 break;
12825 case f_mode:
12826 if (sizeflag & DFLAG)
12827 oappend ("FWORD PTR ");
12828 else
12829 oappend ("DWORD PTR ");
12830 used_prefixes |= (prefixes & PREFIX_DATA);
12831 break;
12832 case t_mode:
12833 oappend ("TBYTE PTR ");
12834 break;
12835 case x_mode:
12836 case x_swap_mode:
12837 if (need_vex)
12838 {
12839 switch (vex.length)
12840 {
12841 case 128:
12842 oappend ("XMMWORD PTR ");
12843 break;
12844 case 256:
12845 oappend ("YMMWORD PTR ");
12846 break;
12847 default:
12848 abort ();
12849 }
12850 }
12851 else
12852 oappend ("XMMWORD PTR ");
12853 break;
12854 case xmm_mode:
12855 oappend ("XMMWORD PTR ");
12856 break;
12857 case xmmq_mode:
12858 if (!need_vex)
12859 abort ();
12860
12861 switch (vex.length)
12862 {
12863 case 128:
12864 oappend ("QWORD PTR ");
12865 break;
12866 case 256:
12867 oappend ("XMMWORD PTR ");
12868 break;
12869 default:
12870 abort ();
12871 }
12872 break;
12873 case ymmq_mode:
12874 if (!need_vex)
12875 abort ();
12876
12877 switch (vex.length)
12878 {
12879 case 128:
12880 oappend ("QWORD PTR ");
12881 break;
12882 case 256:
12883 oappend ("YMMWORD PTR ");
12884 break;
12885 default:
12886 abort ();
12887 }
12888 break;
12889 case o_mode:
12890 oappend ("OWORD PTR ");
12891 break;
12892 case vex_w_dq_mode:
12893 case vex_scalar_w_dq_mode:
12894 if (!need_vex)
12895 abort ();
12896
12897 if (vex.w)
12898 oappend ("QWORD PTR ");
12899 else
12900 oappend ("DWORD PTR ");
12901 break;
12902 default:
12903 break;
12904 }
12905}
12906
12907static void
12908OP_E_register (int bytemode, int sizeflag)
12909{
12910 int reg = modrm.rm;
12911 const char **names;
12912
12913 USED_REX (REX_B);
12914 if ((rex & REX_B))
12915 reg += 8;
12916
12917 if ((sizeflag & SUFFIX_ALWAYS)
12918 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12919 swap_operand ();
12920
12921 switch (bytemode)
12922 {
12923 case b_mode:
12924 case b_swap_mode:
12925 USED_REX (0);
12926 if (rex)
12927 names = names8rex;
12928 else
12929 names = names8;
12930 break;
12931 case w_mode:
12932 names = names16;
12933 break;
12934 case d_mode:
12935 names = names32;
12936 break;
12937 case q_mode:
12938 names = names64;
12939 break;
12940 case m_mode:
12941 names = address_mode == mode_64bit ? names64 : names32;
12942 break;
12943 case stack_v_mode:
12944 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12945 {
12946 names = names64;
12947 break;
12948 }
12949 bytemode = v_mode;
12950 /* FALLTHRU */
12951 case v_mode:
12952 case v_swap_mode:
12953 case dq_mode:
12954 case dqb_mode:
12955 case dqd_mode:
12956 case dqw_mode:
12957 USED_REX (REX_W);
12958 if (rex & REX_W)
12959 names = names64;
12960 else
12961 {
12962 if ((sizeflag & DFLAG)
12963 || (bytemode != v_mode
12964 && bytemode != v_swap_mode))
12965 names = names32;
12966 else
12967 names = names16;
12968 used_prefixes |= (prefixes & PREFIX_DATA);
12969 }
12970 break;
12971 case 0:
12972 return;
12973 default:
12974 oappend (INTERNAL_DISASSEMBLER_ERROR);
12975 return;
12976 }
12977 oappend (names[reg]);
12978}
12979
12980static void
12981OP_E_memory (int bytemode, int sizeflag)
12982{
12983 bfd_vma disp = 0;
12984 int add = (rex & REX_B) ? 8 : 0;
12985 int riprel = 0;
12986
12987 USED_REX (REX_B);
12988 if (intel_syntax)
12989 intel_operand_size (bytemode, sizeflag);
12990 append_seg ();
12991
12992 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12993 {
12994 /* 32/64 bit address mode */
12995 int havedisp;
12996 int havesib;
12997 int havebase;
12998 int haveindex;
12999 int needindex;
13000 int base, rbase;
13001 int vindex = 0;
13002 int scale = 0;
13003
13004 havesib = 0;
13005 havebase = 1;
13006 haveindex = 0;
13007 base = modrm.rm;
13008
13009 if (base == 4)
13010 {
13011 havesib = 1;
13012 vindex = sib.index;
13013 scale = sib.scale;
13014 base = sib.base;
13015 USED_REX (REX_X);
13016 if (rex & REX_X)
13017 vindex += 8;
13018 haveindex = vindex != 4;
13019 codep++;
13020 }
13021 rbase = base + add;
13022
13023 switch (modrm.mod)
13024 {
13025 case 0:
13026 if (base == 5)
13027 {
13028 havebase = 0;
13029 if (address_mode == mode_64bit && !havesib)
13030 riprel = 1;
13031 disp = get32s ();
13032 }
13033 break;
13034 case 1:
13035 FETCH_DATA (the_info, codep + 1);
13036 disp = *codep++;
13037 if ((disp & 0x80) != 0)
13038 disp -= 0x100;
13039 break;
13040 case 2:
13041 disp = get32s ();
13042 break;
13043 }
13044
13045 /* In 32bit mode, we need index register to tell [offset] from
13046 [eiz*1 + offset]. */
13047 needindex = (havesib
13048 && !havebase
13049 && !haveindex
13050 && address_mode == mode_32bit);
13051 havedisp = (havebase
13052 || needindex
13053 || (havesib && (haveindex || scale != 0)));
13054
13055 if (!intel_syntax)
13056 if (modrm.mod != 0 || base == 5)
13057 {
13058 if (havedisp || riprel)
13059 print_displacement (scratchbuf, disp);
13060 else
13061 print_operand_value (scratchbuf, 1, disp);
13062 oappend (scratchbuf);
13063 if (riprel)
13064 {
13065 set_op (disp, 1);
13066 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
13067 }
13068 }
13069
13070 if (havebase || haveindex || riprel)
13071 used_prefixes |= PREFIX_ADDR;
13072
13073 if (havedisp || (intel_syntax && riprel))
13074 {
13075 *obufp++ = open_char;
13076 if (intel_syntax && riprel)
13077 {
13078 set_op (disp, 1);
13079 oappend (sizeflag & AFLAG ? "rip" : "eip");
13080 }
13081 *obufp = '\0';
13082 if (havebase)
13083 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13084 ? names64[rbase] : names32[rbase]);
13085 if (havesib)
13086 {
13087 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
13088 print index to tell base + index from base. */
13089 if (scale != 0
13090 || needindex
13091 || haveindex
13092 || (havebase && base != ESP_REG_NUM))
13093 {
13094 if (!intel_syntax || havebase)
13095 {
13096 *obufp++ = separator_char;
13097 *obufp = '\0';
13098 }
13099 if (haveindex)
13100 oappend (address_mode == mode_64bit
13101 && (sizeflag & AFLAG)
13102 ? names64[vindex] : names32[vindex]);
13103 else
13104 oappend (address_mode == mode_64bit
13105 && (sizeflag & AFLAG)
13106 ? index64 : index32);
13107
13108 *obufp++ = scale_char;
13109 *obufp = '\0';
13110 sprintf (scratchbuf, "%d", 1 << scale);
13111 oappend (scratchbuf);
13112 }
13113 }
13114 if (intel_syntax
13115 && (disp || modrm.mod != 0 || base == 5))
13116 {
13117 if (!havedisp || (bfd_signed_vma) disp >= 0)
13118 {
13119 *obufp++ = '+';
13120 *obufp = '\0';
13121 }
13122 else if (modrm.mod != 1 && disp != -disp)
13123 {
13124 *obufp++ = '-';
13125 *obufp = '\0';
13126 disp = - (bfd_signed_vma) disp;
13127 }
13128
13129 if (havedisp)
13130 print_displacement (scratchbuf, disp);
13131 else
13132 print_operand_value (scratchbuf, 1, disp);
13133 oappend (scratchbuf);
13134 }
13135
13136 *obufp++ = close_char;
13137 *obufp = '\0';
13138 }
13139 else if (intel_syntax)
13140 {
13141 if (modrm.mod != 0 || base == 5)
13142 {
13143 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13144 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13145 ;
13146 else
13147 {
13148 oappend (names_seg[ds_reg - es_reg]);
13149 oappend (":");
13150 }
13151 print_operand_value (scratchbuf, 1, disp);
13152 oappend (scratchbuf);
13153 }
13154 }
13155 }
13156 else
13157 {
13158 /* 16 bit address mode */
13159 used_prefixes |= prefixes & PREFIX_ADDR;
13160 switch (modrm.mod)
13161 {
13162 case 0:
13163 if (modrm.rm == 6)
13164 {
13165 disp = get16 ();
13166 if ((disp & 0x8000) != 0)
13167 disp -= 0x10000;
13168 }
13169 break;
13170 case 1:
13171 FETCH_DATA (the_info, codep + 1);
13172 disp = *codep++;
13173 if ((disp & 0x80) != 0)
13174 disp -= 0x100;
13175 break;
13176 case 2:
13177 disp = get16 ();
13178 if ((disp & 0x8000) != 0)
13179 disp -= 0x10000;
13180 break;
13181 }
13182
13183 if (!intel_syntax)
13184 if (modrm.mod != 0 || modrm.rm == 6)
13185 {
13186 print_displacement (scratchbuf, disp);
13187 oappend (scratchbuf);
13188 }
13189
13190 if (modrm.mod != 0 || modrm.rm != 6)
13191 {
13192 *obufp++ = open_char;
13193 *obufp = '\0';
13194 oappend (index16[modrm.rm]);
13195 if (intel_syntax
13196 && (disp || modrm.mod != 0 || modrm.rm == 6))
13197 {
13198 if ((bfd_signed_vma) disp >= 0)
13199 {
13200 *obufp++ = '+';
13201 *obufp = '\0';
13202 }
13203 else if (modrm.mod != 1)
13204 {
13205 *obufp++ = '-';
13206 *obufp = '\0';
13207 disp = - (bfd_signed_vma) disp;
13208 }
13209
13210 print_displacement (scratchbuf, disp);
13211 oappend (scratchbuf);
13212 }
13213
13214 *obufp++ = close_char;
13215 *obufp = '\0';
13216 }
13217 else if (intel_syntax)
13218 {
13219 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13220 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13221 ;
13222 else
13223 {
13224 oappend (names_seg[ds_reg - es_reg]);
13225 oappend (":");
13226 }
13227 print_operand_value (scratchbuf, 1, disp & 0xffff);
13228 oappend (scratchbuf);
13229 }
13230 }
13231}
13232
13233static void
13234OP_E (int bytemode, int sizeflag)
13235{
13236 /* Skip mod/rm byte. */
13237 MODRM_CHECK;
13238 codep++;
13239
13240 if (modrm.mod == 3)
13241 OP_E_register (bytemode, sizeflag);
13242 else
13243 OP_E_memory (bytemode, sizeflag);
13244}
13245
13246static void
13247OP_G (int bytemode, int sizeflag)
13248{
13249 int add = 0;
13250 USED_REX (REX_R);
13251 if (rex & REX_R)
13252 add += 8;
13253 switch (bytemode)
13254 {
13255 case b_mode:
13256 USED_REX (0);
13257 if (rex)
13258 oappend (names8rex[modrm.reg + add]);
13259 else
13260 oappend (names8[modrm.reg + add]);
13261 break;
13262 case w_mode:
13263 oappend (names16[modrm.reg + add]);
13264 break;
13265 case d_mode:
13266 oappend (names32[modrm.reg + add]);
13267 break;
13268 case q_mode:
13269 oappend (names64[modrm.reg + add]);
13270 break;
13271 case v_mode:
13272 case dq_mode:
13273 case dqb_mode:
13274 case dqd_mode:
13275 case dqw_mode:
13276 USED_REX (REX_W);
13277 if (rex & REX_W)
13278 oappend (names64[modrm.reg + add]);
13279 else
13280 {
13281 if ((sizeflag & DFLAG) || bytemode != v_mode)
13282 oappend (names32[modrm.reg + add]);
13283 else
13284 oappend (names16[modrm.reg + add]);
13285 used_prefixes |= (prefixes & PREFIX_DATA);
13286 }
13287 break;
13288 case m_mode:
13289 if (address_mode == mode_64bit)
13290 oappend (names64[modrm.reg + add]);
13291 else
13292 oappend (names32[modrm.reg + add]);
13293 break;
13294 default:
13295 oappend (INTERNAL_DISASSEMBLER_ERROR);
13296 break;
13297 }
13298}
13299
13300static bfd_vma
13301get64 (void)
13302{
13303 bfd_vma x;
13304#ifdef BFD64
13305 unsigned int a;
13306 unsigned int b;
13307
13308 FETCH_DATA (the_info, codep + 8);
13309 a = *codep++ & 0xff;
13310 a |= (*codep++ & 0xff) << 8;
13311 a |= (*codep++ & 0xff) << 16;
13312 a |= (*codep++ & 0xff) << 24;
13313 b = *codep++ & 0xff;
13314 b |= (*codep++ & 0xff) << 8;
13315 b |= (*codep++ & 0xff) << 16;
13316 b |= (*codep++ & 0xff) << 24;
13317 x = a + ((bfd_vma) b << 32);
13318#else
13319 abort ();
13320 x = 0;
13321#endif
13322 return x;
13323}
13324
13325static bfd_signed_vma
13326get32 (void)
13327{
13328 bfd_signed_vma x = 0;
13329
13330 FETCH_DATA (the_info, codep + 4);
13331 x = *codep++ & (bfd_signed_vma) 0xff;
13332 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13333 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13334 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13335 return x;
13336}
13337
13338static bfd_signed_vma
13339get32s (void)
13340{
13341 bfd_signed_vma x = 0;
13342
13343 FETCH_DATA (the_info, codep + 4);
13344 x = *codep++ & (bfd_signed_vma) 0xff;
13345 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13346 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13347 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13348
13349 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13350
13351 return x;
13352}
13353
13354static int
13355get16 (void)
13356{
13357 int x = 0;
13358
13359 FETCH_DATA (the_info, codep + 2);
13360 x = *codep++ & 0xff;
13361 x |= (*codep++ & 0xff) << 8;
13362 return x;
13363}
13364
13365static void
13366set_op (bfd_vma op, int riprel)
13367{
13368 op_index[op_ad] = op_ad;
13369 if (address_mode == mode_64bit)
13370 {
13371 op_address[op_ad] = op;
13372 op_riprel[op_ad] = riprel;
13373 }
13374 else
13375 {
13376 /* Mask to get a 32-bit address. */
13377 op_address[op_ad] = op & 0xffffffff;
13378 op_riprel[op_ad] = riprel & 0xffffffff;
13379 }
13380}
13381
13382static void
13383OP_REG (int code, int sizeflag)
13384{
13385 const char *s;
13386 int add;
13387 USED_REX (REX_B);
13388 if (rex & REX_B)
13389 add = 8;
13390 else
13391 add = 0;
13392
13393 switch (code)
13394 {
13395 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13396 case sp_reg: case bp_reg: case si_reg: case di_reg:
13397 s = names16[code - ax_reg + add];
13398 break;
13399 case es_reg: case ss_reg: case cs_reg:
13400 case ds_reg: case fs_reg: case gs_reg:
13401 s = names_seg[code - es_reg + add];
13402 break;
13403 case al_reg: case ah_reg: case cl_reg: case ch_reg:
13404 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13405 USED_REX (0);
13406 if (rex)
13407 s = names8rex[code - al_reg + add];
13408 else
13409 s = names8[code - al_reg];
13410 break;
13411 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13412 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13413 if (address_mode == mode_64bit && (sizeflag & DFLAG))
13414 {
13415 s = names64[code - rAX_reg + add];
13416 break;
13417 }
13418 code += eAX_reg - rAX_reg;
13419 /* Fall through. */
13420 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13421 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13422 USED_REX (REX_W);
13423 if (rex & REX_W)
13424 s = names64[code - eAX_reg + add];
13425 else
13426 {
13427 if (sizeflag & DFLAG)
13428 s = names32[code - eAX_reg + add];
13429 else
13430 s = names16[code - eAX_reg + add];
13431 used_prefixes |= (prefixes & PREFIX_DATA);
13432 }
13433 break;
13434 default:
13435 s = INTERNAL_DISASSEMBLER_ERROR;
13436 break;
13437 }
13438 oappend (s);
13439}
13440
13441static void
13442OP_IMREG (int code, int sizeflag)
13443{
13444 const char *s;
13445
13446 switch (code)
13447 {
13448 case indir_dx_reg:
13449 if (intel_syntax)
13450 s = "dx";
13451 else
13452 s = "(%dx)";
13453 break;
13454 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13455 case sp_reg: case bp_reg: case si_reg: case di_reg:
13456 s = names16[code - ax_reg];
13457 break;
13458 case es_reg: case ss_reg: case cs_reg:
13459 case ds_reg: case fs_reg: case gs_reg:
13460 s = names_seg[code - es_reg];
13461 break;
13462 case al_reg: case ah_reg: case cl_reg: case ch_reg:
13463 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13464 USED_REX (0);
13465 if (rex)
13466 s = names8rex[code - al_reg];
13467 else
13468 s = names8[code - al_reg];
13469 break;
13470 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13471 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13472 USED_REX (REX_W);
13473 if (rex & REX_W)
13474 s = names64[code - eAX_reg];
13475 else
13476 {
13477 if (sizeflag & DFLAG)
13478 s = names32[code - eAX_reg];
13479 else
13480 s = names16[code - eAX_reg];
13481 used_prefixes |= (prefixes & PREFIX_DATA);
13482 }
13483 break;
13484 case z_mode_ax_reg:
13485 if ((rex & REX_W) || (sizeflag & DFLAG))
13486 s = *names32;
13487 else
13488 s = *names16;
13489 if (!(rex & REX_W))
13490 used_prefixes |= (prefixes & PREFIX_DATA);
13491 break;
13492 default:
13493 s = INTERNAL_DISASSEMBLER_ERROR;
13494 break;
13495 }
13496 oappend (s);
13497}
13498
13499static void
13500OP_I (int bytemode, int sizeflag)
13501{
13502 bfd_signed_vma op;
13503 bfd_signed_vma mask = -1;
13504
13505 switch (bytemode)
13506 {
13507 case b_mode:
13508 FETCH_DATA (the_info, codep + 1);
13509 op = *codep++;
13510 mask = 0xff;
13511 break;
13512 case q_mode:
13513 if (address_mode == mode_64bit)
13514 {
13515 op = get32s ();
13516 break;
13517 }
13518 /* Fall through. */
13519 case v_mode:
13520 USED_REX (REX_W);
13521 if (rex & REX_W)
13522 op = get32s ();
13523 else
13524 {
13525 if (sizeflag & DFLAG)
13526 {
13527 op = get32 ();
13528 mask = 0xffffffff;
13529 }
13530 else
13531 {
13532 op = get16 ();
13533 mask = 0xfffff;
13534 }
13535 used_prefixes |= (prefixes & PREFIX_DATA);
13536 }
13537 break;
13538 case w_mode:
13539 mask = 0xfffff;
13540 op = get16 ();
13541 break;
13542 case const_1_mode:
13543 if (intel_syntax)
13544 oappend ("1");
13545 return;
13546 default:
13547 oappend (INTERNAL_DISASSEMBLER_ERROR);
13548 return;
13549 }
13550
13551 op &= mask;
13552 scratchbuf[0] = '$';
13553 print_operand_value (scratchbuf + 1, 1, op);
13554 oappend (scratchbuf + intel_syntax);
13555 scratchbuf[0] = '\0';
13556}
13557
13558static void
13559OP_I64 (int bytemode, int sizeflag)
13560{
13561 bfd_signed_vma op;
13562 bfd_signed_vma mask = -1;
13563
13564 if (address_mode != mode_64bit)
13565 {
13566 OP_I (bytemode, sizeflag);
13567 return;
13568 }
13569
13570 switch (bytemode)
13571 {
13572 case b_mode:
13573 FETCH_DATA (the_info, codep + 1);
13574 op = *codep++;
13575 mask = 0xff;
13576 break;
13577 case v_mode:
13578 USED_REX (REX_W);
13579 if (rex & REX_W)
13580 op = get64 ();
13581 else
13582 {
13583 if (sizeflag & DFLAG)
13584 {
13585 op = get32 ();
13586 mask = 0xffffffff;
13587 }
13588 else
13589 {
13590 op = get16 ();
13591 mask = 0xfffff;
13592 }
13593 used_prefixes |= (prefixes & PREFIX_DATA);
13594 }
13595 break;
13596 case w_mode:
13597 mask = 0xfffff;
13598 op = get16 ();
13599 break;
13600 default:
13601 oappend (INTERNAL_DISASSEMBLER_ERROR);
13602 return;
13603 }
13604
13605 op &= mask;
13606 scratchbuf[0] = '$';
13607 print_operand_value (scratchbuf + 1, 1, op);
13608 oappend (scratchbuf + intel_syntax);
13609 scratchbuf[0] = '\0';
13610}
13611
13612static void
13613OP_sI (int bytemode, int sizeflag)
13614{
13615 bfd_signed_vma op;
13616
13617 switch (bytemode)
13618 {
13619 case b_mode:
13620 FETCH_DATA (the_info, codep + 1);
13621 op = *codep++;
13622 if ((op & 0x80) != 0)
13623 op -= 0x100;
13624 break;
13625 case v_mode:
13626 USED_REX (REX_W);
13627 if (rex & REX_W)
13628 op = get32s ();
13629 else
13630 {
13631 if (sizeflag & DFLAG)
13632 {
13633 op = get32s ();
13634 }
13635 else
13636 {
13637 op = get16 ();
13638 if ((op & 0x8000) != 0)
13639 op -= 0x10000;
13640 }
13641 used_prefixes |= (prefixes & PREFIX_DATA);
13642 }
13643 break;
13644 case w_mode:
13645 op = get16 ();
13646 if ((op & 0x8000) != 0)
13647 op -= 0x10000;
13648 break;
13649 default:
13650 oappend (INTERNAL_DISASSEMBLER_ERROR);
13651 return;
13652 }
13653
13654 scratchbuf[0] = '$';
13655 print_operand_value (scratchbuf + 1, 1, op);
13656 oappend (scratchbuf + intel_syntax);
13657}
13658
13659static void
13660OP_J (int bytemode, int sizeflag)
13661{
13662 bfd_vma disp;
13663 bfd_vma mask = -1;
13664 bfd_vma segment = 0;
13665
13666 switch (bytemode)
13667 {
13668 case b_mode:
13669 FETCH_DATA (the_info, codep + 1);
13670 disp = *codep++;
13671 if ((disp & 0x80) != 0)
13672 disp -= 0x100;
13673 break;
13674 case v_mode:
13675 USED_REX (REX_W);
13676 if ((sizeflag & DFLAG) || (rex & REX_W))
13677 disp = get32s ();
13678 else
13679 {
13680 disp = get16 ();
13681 if ((disp & 0x8000) != 0)
13682 disp -= 0x10000;
13683 /* In 16bit mode, address is wrapped around at 64k within
13684 the same segment. Otherwise, a data16 prefix on a jump
13685 instruction means that the pc is masked to 16 bits after
13686 the displacement is added! */
13687 mask = 0xffff;
13688 if ((prefixes & PREFIX_DATA) == 0)
13689 segment = ((start_pc + codep - start_codep)
13690 & ~((bfd_vma) 0xffff));
13691 }
13692 if (!(rex & REX_W))
13693 used_prefixes |= (prefixes & PREFIX_DATA);
13694 break;
13695 default:
13696 oappend (INTERNAL_DISASSEMBLER_ERROR);
13697 return;
13698 }
13699 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
13700 set_op (disp, 0);
13701 print_operand_value (scratchbuf, 1, disp);
13702 oappend (scratchbuf);
13703}
13704
13705static void
13706OP_SEG (int bytemode, int sizeflag)
13707{
13708 if (bytemode == w_mode)
13709 oappend (names_seg[modrm.reg]);
13710 else
13711 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13712}
13713
13714static void
13715OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13716{
13717 int seg, offset;
13718
13719 if (sizeflag & DFLAG)
13720 {
13721 offset = get32 ();
13722 seg = get16 ();
13723 }
13724 else
13725 {
13726 offset = get16 ();
13727 seg = get16 ();
13728 }
13729 used_prefixes |= (prefixes & PREFIX_DATA);
13730 if (intel_syntax)
13731 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13732 else
13733 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13734 oappend (scratchbuf);
13735}
13736
13737static void
13738OP_OFF (int bytemode, int sizeflag)
13739{
13740 bfd_vma off;
13741
13742 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13743 intel_operand_size (bytemode, sizeflag);
13744 append_seg ();
13745
13746 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13747 off = get32 ();
13748 else
13749 off = get16 ();
13750
13751 if (intel_syntax)
13752 {
13753 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13754 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13755 {
13756 oappend (names_seg[ds_reg - es_reg]);
13757 oappend (":");
13758 }
13759 }
13760 print_operand_value (scratchbuf, 1, off);
13761 oappend (scratchbuf);
13762}
13763
13764static void
13765OP_OFF64 (int bytemode, int sizeflag)
13766{
13767 bfd_vma off;
13768
13769 if (address_mode != mode_64bit
13770 || (prefixes & PREFIX_ADDR))
13771 {
13772 OP_OFF (bytemode, sizeflag);
13773 return;
13774 }
13775
13776 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13777 intel_operand_size (bytemode, sizeflag);
13778 append_seg ();
13779
13780 off = get64 ();
13781
13782 if (intel_syntax)
13783 {
13784 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13785 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13786 {
13787 oappend (names_seg[ds_reg - es_reg]);
13788 oappend (":");
13789 }
13790 }
13791 print_operand_value (scratchbuf, 1, off);
13792 oappend (scratchbuf);
13793}
13794
13795static void
13796ptr_reg (int code, int sizeflag)
13797{
13798 const char *s;
13799
13800 *obufp++ = open_char;
13801 used_prefixes |= (prefixes & PREFIX_ADDR);
13802 if (address_mode == mode_64bit)
13803 {
13804 if (!(sizeflag & AFLAG))
13805 s = names32[code - eAX_reg];
13806 else
13807 s = names64[code - eAX_reg];
13808 }
13809 else if (sizeflag & AFLAG)
13810 s = names32[code - eAX_reg];
13811 else
13812 s = names16[code - eAX_reg];
13813 oappend (s);
13814 *obufp++ = close_char;
13815 *obufp = 0;
13816}
13817
13818static void
13819OP_ESreg (int code, int sizeflag)
13820{
13821 if (intel_syntax)
13822 {
13823 switch (codep[-1])
13824 {
13825 case 0x6d: /* insw/insl */
13826 intel_operand_size (z_mode, sizeflag);
13827 break;
13828 case 0xa5: /* movsw/movsl/movsq */
13829 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13830 case 0xab: /* stosw/stosl */
13831 case 0xaf: /* scasw/scasl */
13832 intel_operand_size (v_mode, sizeflag);
13833 break;
13834 default:
13835 intel_operand_size (b_mode, sizeflag);
13836 }
13837 }
13838 oappend ("%es:" + intel_syntax);
13839 ptr_reg (code, sizeflag);
13840}
13841
13842static void
13843OP_DSreg (int code, int sizeflag)
13844{
13845 if (intel_syntax)
13846 {
13847 switch (codep[-1])
13848 {
13849 case 0x6f: /* outsw/outsl */
13850 intel_operand_size (z_mode, sizeflag);
13851 break;
13852 case 0xa5: /* movsw/movsl/movsq */
13853 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13854 case 0xad: /* lodsw/lodsl/lodsq */
13855 intel_operand_size (v_mode, sizeflag);
13856 break;
13857 default:
13858 intel_operand_size (b_mode, sizeflag);
13859 }
13860 }
13861 if ((prefixes
13862 & (PREFIX_CS
13863 | PREFIX_DS
13864 | PREFIX_SS
13865 | PREFIX_ES
13866 | PREFIX_FS
13867 | PREFIX_GS)) == 0)
13868 prefixes |= PREFIX_DS;
13869 append_seg ();
13870 ptr_reg (code, sizeflag);
13871}
13872
13873static void
13874OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13875{
13876 int add;
13877 if (rex & REX_R)
13878 {
13879 USED_REX (REX_R);
13880 add = 8;
13881 }
13882 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13883 {
13884 all_prefixes[last_lock_prefix] = 0;
13885 used_prefixes |= PREFIX_LOCK;
13886 add = 8;
13887 }
13888 else
13889 add = 0;
13890 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13891 oappend (scratchbuf + intel_syntax);
13892}
13893
13894static void
13895OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13896{
13897 int add;
13898 USED_REX (REX_R);
13899 if (rex & REX_R)
13900 add = 8;
13901 else
13902 add = 0;
13903 if (intel_syntax)
13904 sprintf (scratchbuf, "db%d", modrm.reg + add);
13905 else
13906 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13907 oappend (scratchbuf);
13908}
13909
13910static void
13911OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13912{
13913 sprintf (scratchbuf, "%%tr%d", modrm.reg);
13914 oappend (scratchbuf + intel_syntax);
13915}
13916
13917static void
13918OP_R (int bytemode, int sizeflag)
13919{
13920 if (modrm.mod == 3)
13921 OP_E (bytemode, sizeflag);
13922 else
13923 BadOp ();
13924}
13925
13926static void
13927OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13928{
13929 int reg = modrm.reg;
13930 const char **names;
13931
13932 used_prefixes |= (prefixes & PREFIX_DATA);
13933 if (prefixes & PREFIX_DATA)
13934 {
13935 names = names_xmm;
13936 USED_REX (REX_R);
13937 if (rex & REX_R)
13938 reg += 8;
13939 }
13940 else
13941 names = names_mm;
13942 oappend (names[reg]);
13943}
13944
13945static void
13946OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13947{
13948 int reg = modrm.reg;
13949 const char **names;
13950
13951 USED_REX (REX_R);
13952 if (rex & REX_R)
13953 reg += 8;
13954 if (need_vex
13955 && bytemode != xmm_mode
13956 && bytemode != scalar_mode)
13957 {
13958 switch (vex.length)
13959 {
13960 case 128:
13961 names = names_xmm;
13962 break;
13963 case 256:
13964 names = names_ymm;
13965 break;
13966 default:
13967 abort ();
13968 }
13969 }
13970 else
13971 names = names_xmm;
13972 oappend (names[reg]);
13973}
13974
13975static void
13976OP_EM (int bytemode, int sizeflag)
13977{
13978 int reg;
13979 const char **names;
13980
13981 if (modrm.mod != 3)
13982 {
13983 if (intel_syntax
13984 && (bytemode == v_mode || bytemode == v_swap_mode))
13985 {
13986 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13987 used_prefixes |= (prefixes & PREFIX_DATA);
13988 }
13989 OP_E (bytemode, sizeflag);
13990 return;
13991 }
13992
13993 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13994 swap_operand ();
13995
13996 /* Skip mod/rm byte. */
13997 MODRM_CHECK;
13998 codep++;
13999 used_prefixes |= (prefixes & PREFIX_DATA);
14000 reg = modrm.rm;
14001 if (prefixes & PREFIX_DATA)
14002 {
14003 names = names_xmm;
14004 USED_REX (REX_B);
14005 if (rex & REX_B)
14006 reg += 8;
14007 }
14008 else
14009 names = names_mm;
14010 oappend (names[reg]);
14011}
14012
14013/* cvt* are the only instructions in sse2 which have
14014 both SSE and MMX operands and also have 0x66 prefix
14015 in their opcode. 0x66 was originally used to differentiate
14016 between SSE and MMX instruction(operands). So we have to handle the
14017 cvt* separately using OP_EMC and OP_MXC */
14018static void
14019OP_EMC (int bytemode, int sizeflag)
14020{
14021 if (modrm.mod != 3)
14022 {
14023 if (intel_syntax && bytemode == v_mode)
14024 {
14025 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14026 used_prefixes |= (prefixes & PREFIX_DATA);
14027 }
14028 OP_E (bytemode, sizeflag);
14029 return;
14030 }
14031
14032 /* Skip mod/rm byte. */
14033 MODRM_CHECK;
14034 codep++;
14035 used_prefixes |= (prefixes & PREFIX_DATA);
14036 oappend (names_mm[modrm.rm]);
14037}
14038
14039static void
14040OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14041{
14042 used_prefixes |= (prefixes & PREFIX_DATA);
14043 oappend (names_mm[modrm.reg]);
14044}
14045
14046static void
14047OP_EX (int bytemode, int sizeflag)
14048{
14049 int reg;
14050 const char **names;
14051
14052 /* Skip mod/rm byte. */
14053 MODRM_CHECK;
14054 codep++;
14055
14056 if (modrm.mod != 3)
14057 {
14058 OP_E_memory (bytemode, sizeflag);
14059 return;
14060 }
14061
14062 reg = modrm.rm;
14063 USED_REX (REX_B);
14064 if (rex & REX_B)
14065 reg += 8;
14066
14067 if ((sizeflag & SUFFIX_ALWAYS)
14068 && (bytemode == x_swap_mode
14069 || bytemode == d_swap_mode
14070 || bytemode == d_scalar_swap_mode
14071 || bytemode == q_swap_mode
14072 || bytemode == q_scalar_swap_mode))
14073 swap_operand ();
14074
14075 if (need_vex
14076 && bytemode != xmm_mode
14077 && bytemode != xmmq_mode
14078 && bytemode != d_scalar_mode
14079 && bytemode != d_scalar_swap_mode
14080 && bytemode != q_scalar_mode
14081 && bytemode != q_scalar_swap_mode
14082 && bytemode != vex_scalar_w_dq_mode)
14083 {
14084 switch (vex.length)
14085 {
14086 case 128:
14087 names = names_xmm;
14088 break;
14089 case 256:
14090 names = names_ymm;
14091 break;
14092 default:
14093 abort ();
14094 }
14095 }
14096 else
14097 names = names_xmm;
14098 oappend (names[reg]);
14099}
14100
14101static void
14102OP_MS (int bytemode, int sizeflag)
14103{
14104 if (modrm.mod == 3)
14105 OP_EM (bytemode, sizeflag);
14106 else
14107 BadOp ();
14108}
14109
14110static void
14111OP_XS (int bytemode, int sizeflag)
14112{
14113 if (modrm.mod == 3)
14114 OP_EX (bytemode, sizeflag);
14115 else
14116 BadOp ();
14117}
14118
14119static void
14120OP_M (int bytemode, int sizeflag)
14121{
14122 if (modrm.mod == 3)
14123 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14124 BadOp ();
14125 else
14126 OP_E (bytemode, sizeflag);
14127}
14128
14129static void
14130OP_0f07 (int bytemode, int sizeflag)
14131{
14132 if (modrm.mod != 3 || modrm.rm != 0)
14133 BadOp ();
14134 else
14135 OP_E (bytemode, sizeflag);
14136}
14137
14138/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14139 32bit mode and "xchg %rax,%rax" in 64bit mode. */
14140
14141static void
14142NOP_Fixup1 (int bytemode, int sizeflag)
14143{
14144 if ((prefixes & PREFIX_DATA) != 0
14145 || (rex != 0
14146 && rex != 0x48
14147 && address_mode == mode_64bit))
14148 OP_REG (bytemode, sizeflag);
14149 else
14150 strcpy (obuf, "nop");
14151}
14152
14153static void
14154NOP_Fixup2 (int bytemode, int sizeflag)
14155{
14156 if ((prefixes & PREFIX_DATA) != 0
14157 || (rex != 0
14158 && rex != 0x48
14159 && address_mode == mode_64bit))
14160 OP_IMREG (bytemode, sizeflag);
14161}
14162
14163static const char *const Suffix3DNow[] = {
14164/* 00 */ NULL, NULL, NULL, NULL,
14165/* 04 */ NULL, NULL, NULL, NULL,
14166/* 08 */ NULL, NULL, NULL, NULL,
14167/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
14168/* 10 */ NULL, NULL, NULL, NULL,
14169/* 14 */ NULL, NULL, NULL, NULL,
14170/* 18 */ NULL, NULL, NULL, NULL,
14171/* 1C */ "pf2iw", "pf2id", NULL, NULL,
14172/* 20 */ NULL, NULL, NULL, NULL,
14173/* 24 */ NULL, NULL, NULL, NULL,
14174/* 28 */ NULL, NULL, NULL, NULL,
14175/* 2C */ NULL, NULL, NULL, NULL,
14176/* 30 */ NULL, NULL, NULL, NULL,
14177/* 34 */ NULL, NULL, NULL, NULL,
14178/* 38 */ NULL, NULL, NULL, NULL,
14179/* 3C */ NULL, NULL, NULL, NULL,
14180/* 40 */ NULL, NULL, NULL, NULL,
14181/* 44 */ NULL, NULL, NULL, NULL,
14182/* 48 */ NULL, NULL, NULL, NULL,
14183/* 4C */ NULL, NULL, NULL, NULL,
14184/* 50 */ NULL, NULL, NULL, NULL,
14185/* 54 */ NULL, NULL, NULL, NULL,
14186/* 58 */ NULL, NULL, NULL, NULL,
14187/* 5C */ NULL, NULL, NULL, NULL,
14188/* 60 */ NULL, NULL, NULL, NULL,
14189/* 64 */ NULL, NULL, NULL, NULL,
14190/* 68 */ NULL, NULL, NULL, NULL,
14191/* 6C */ NULL, NULL, NULL, NULL,
14192/* 70 */ NULL, NULL, NULL, NULL,
14193/* 74 */ NULL, NULL, NULL, NULL,
14194/* 78 */ NULL, NULL, NULL, NULL,
14195/* 7C */ NULL, NULL, NULL, NULL,
14196/* 80 */ NULL, NULL, NULL, NULL,
14197/* 84 */ NULL, NULL, NULL, NULL,
14198/* 88 */ NULL, NULL, "pfnacc", NULL,
14199/* 8C */ NULL, NULL, "pfpnacc", NULL,
14200/* 90 */ "pfcmpge", NULL, NULL, NULL,
14201/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
14202/* 98 */ NULL, NULL, "pfsub", NULL,
14203/* 9C */ NULL, NULL, "pfadd", NULL,
14204/* A0 */ "pfcmpgt", NULL, NULL, NULL,
14205/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
14206/* A8 */ NULL, NULL, "pfsubr", NULL,
14207/* AC */ NULL, NULL, "pfacc", NULL,
14208/* B0 */ "pfcmpeq", NULL, NULL, NULL,
14209/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
14210/* B8 */ NULL, NULL, NULL, "pswapd",
14211/* BC */ NULL, NULL, NULL, "pavgusb",
14212/* C0 */ NULL, NULL, NULL, NULL,
14213/* C4 */ NULL, NULL, NULL, NULL,
14214/* C8 */ NULL, NULL, NULL, NULL,
14215/* CC */ NULL, NULL, NULL, NULL,
14216/* D0 */ NULL, NULL, NULL, NULL,
14217/* D4 */ NULL, NULL, NULL, NULL,
14218/* D8 */ NULL, NULL, NULL, NULL,
14219/* DC */ NULL, NULL, NULL, NULL,
14220/* E0 */ NULL, NULL, NULL, NULL,
14221/* E4 */ NULL, NULL, NULL, NULL,
14222/* E8 */ NULL, NULL, NULL, NULL,
14223/* EC */ NULL, NULL, NULL, NULL,
14224/* F0 */ NULL, NULL, NULL, NULL,
14225/* F4 */ NULL, NULL, NULL, NULL,
14226/* F8 */ NULL, NULL, NULL, NULL,
14227/* FC */ NULL, NULL, NULL, NULL,
14228};
14229
14230static void
14231OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14232{
14233 const char *mnemonic;
14234
14235 FETCH_DATA (the_info, codep + 1);
14236 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14237 place where an 8-bit immediate would normally go. ie. the last
14238 byte of the instruction. */
14239 obufp = mnemonicendp;
14240 mnemonic = Suffix3DNow[*codep++ & 0xff];
14241 if (mnemonic)
14242 oappend (mnemonic);
14243 else
14244 {
14245 /* Since a variable sized modrm/sib chunk is between the start
14246 of the opcode (0x0f0f) and the opcode suffix, we need to do
14247 all the modrm processing first, and don't know until now that
14248 we have a bad opcode. This necessitates some cleaning up. */
14249 op_out[0][0] = '\0';
14250 op_out[1][0] = '\0';
14251 BadOp ();
14252 }
14253 mnemonicendp = obufp;
14254}
14255
14256static struct op simd_cmp_op[] =
14257{
14258 { STRING_COMMA_LEN ("eq") },
14259 { STRING_COMMA_LEN ("lt") },
14260 { STRING_COMMA_LEN ("le") },
14261 { STRING_COMMA_LEN ("unord") },
14262 { STRING_COMMA_LEN ("neq") },
14263 { STRING_COMMA_LEN ("nlt") },
14264 { STRING_COMMA_LEN ("nle") },
14265 { STRING_COMMA_LEN ("ord") }
14266};
14267
14268static void
14269CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14270{
14271 unsigned int cmp_type;
14272
14273 FETCH_DATA (the_info, codep + 1);
14274 cmp_type = *codep++ & 0xff;
14275 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14276 {
14277 char suffix [3];
14278 char *p = mnemonicendp - 2;
14279 suffix[0] = p[0];
14280 suffix[1] = p[1];
14281 suffix[2] = '\0';
14282 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14283 mnemonicendp += simd_cmp_op[cmp_type].len;
14284 }
14285 else
14286 {
14287 /* We have a reserved extension byte. Output it directly. */
14288 scratchbuf[0] = '$';
14289 print_operand_value (scratchbuf + 1, 1, cmp_type);
14290 oappend (scratchbuf + intel_syntax);
14291 scratchbuf[0] = '\0';
14292 }
14293}
14294
14295static void
14296OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14297 int sizeflag ATTRIBUTE_UNUSED)
14298{
14299 /* mwait %eax,%ecx */
14300 if (!intel_syntax)
14301 {
14302 const char **names = (address_mode == mode_64bit
14303 ? names64 : names32);
14304 strcpy (op_out[0], names[0]);
14305 strcpy (op_out[1], names[1]);
14306 two_source_ops = 1;
14307 }
14308 /* Skip mod/rm byte. */
14309 MODRM_CHECK;
14310 codep++;
14311}
14312
14313static void
14314OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14315 int sizeflag ATTRIBUTE_UNUSED)
14316{
14317 /* monitor %eax,%ecx,%edx" */
14318 if (!intel_syntax)
14319 {
14320 const char **op1_names;
14321 const char **names = (address_mode == mode_64bit
14322 ? names64 : names32);
14323
14324 if (!(prefixes & PREFIX_ADDR))
14325 op1_names = (address_mode == mode_16bit
14326 ? names16 : names);
14327 else
14328 {
14329 /* Remove "addr16/addr32". */
14330 all_prefixes[last_addr_prefix] = 0;
14331 op1_names = (address_mode != mode_32bit
14332 ? names32 : names16);
14333 used_prefixes |= PREFIX_ADDR;
14334 }
14335 strcpy (op_out[0], op1_names[0]);
14336 strcpy (op_out[1], names[1]);
14337 strcpy (op_out[2], names[2]);
14338 two_source_ops = 1;
14339 }
14340 /* Skip mod/rm byte. */
14341 MODRM_CHECK;
14342 codep++;
14343}
14344
14345static void
14346BadOp (void)
14347{
14348 /* Throw away prefixes and 1st. opcode byte. */
14349 codep = insn_codep + 1;
14350 oappend ("(bad)");
14351}
14352
14353static void
14354REP_Fixup (int bytemode, int sizeflag)
14355{
14356 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14357 lods and stos. */
14358 if (prefixes & PREFIX_REPZ)
14359 all_prefixes[last_repz_prefix] = REP_PREFIX;
14360
14361 switch (bytemode)
14362 {
14363 case al_reg:
14364 case eAX_reg:
14365 case indir_dx_reg:
14366 OP_IMREG (bytemode, sizeflag);
14367 break;
14368 case eDI_reg:
14369 OP_ESreg (bytemode, sizeflag);
14370 break;
14371 case eSI_reg:
14372 OP_DSreg (bytemode, sizeflag);
14373 break;
14374 default:
14375 abort ();
14376 break;
14377 }
14378}
14379
14380static void
14381CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14382{
14383 USED_REX (REX_W);
14384 if (rex & REX_W)
14385 {
14386 /* Change cmpxchg8b to cmpxchg16b. */
14387 char *p = mnemonicendp - 2;
14388 mnemonicendp = stpcpy (p, "16b");
14389 bytemode = o_mode;
14390 }
14391 OP_M (bytemode, sizeflag);
14392}
14393
14394static void
14395XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14396{
14397 const char **names;
14398
14399 if (need_vex)
14400 {
14401 switch (vex.length)
14402 {
14403 case 128:
14404 names = names_xmm;
14405 break;
14406 case 256:
14407 names = names_ymm;
14408 break;
14409 default:
14410 abort ();
14411 }
14412 }
14413 else
14414 names = names_xmm;
14415 oappend (names[reg]);
14416}
14417
14418static void
14419CRC32_Fixup (int bytemode, int sizeflag)
14420{
14421 /* Add proper suffix to "crc32". */
14422 char *p = mnemonicendp;
14423
14424 switch (bytemode)
14425 {
14426 case b_mode:
14427 if (intel_syntax)
14428 goto skip;
14429
14430 *p++ = 'b';
14431 break;
14432 case v_mode:
14433 if (intel_syntax)
14434 goto skip;
14435
14436 USED_REX (REX_W);
14437 if (rex & REX_W)
14438 *p++ = 'q';
14439 else
14440 {
14441 if (sizeflag & DFLAG)
14442 *p++ = 'l';
14443 else
14444 *p++ = 'w';
14445 used_prefixes |= (prefixes & PREFIX_DATA);
14446 }
14447 break;
14448 default:
14449 oappend (INTERNAL_DISASSEMBLER_ERROR);
14450 break;
14451 }
14452 mnemonicendp = p;
14453 *p = '\0';
14454
14455skip:
14456 if (modrm.mod == 3)
14457 {
14458 int add;
14459
14460 /* Skip mod/rm byte. */
14461 MODRM_CHECK;
14462 codep++;
14463
14464 USED_REX (REX_B);
14465 add = (rex & REX_B) ? 8 : 0;
14466 if (bytemode == b_mode)
14467 {
14468 USED_REX (0);
14469 if (rex)
14470 oappend (names8rex[modrm.rm + add]);
14471 else
14472 oappend (names8[modrm.rm + add]);
14473 }
14474 else
14475 {
14476 USED_REX (REX_W);
14477 if (rex & REX_W)
14478 oappend (names64[modrm.rm + add]);
14479 else if ((prefixes & PREFIX_DATA))
14480 oappend (names16[modrm.rm + add]);
14481 else
14482 oappend (names32[modrm.rm + add]);
14483 }
14484 }
14485 else
14486 OP_E (bytemode, sizeflag);
14487}
14488
14489static void
14490FXSAVE_Fixup (int bytemode, int sizeflag)
14491{
14492 /* Add proper suffix to "fxsave" and "fxrstor". */
14493 USED_REX (REX_W);
14494 if (rex & REX_W)
14495 {
14496 char *p = mnemonicendp;
14497 *p++ = '6';
14498 *p++ = '4';
14499 *p = '\0';
14500 mnemonicendp = p;
14501 }
14502 OP_M (bytemode, sizeflag);
14503}
14504
14505/* Display the destination register operand for instructions with
14506 VEX. */
14507
14508static void
14509OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14510{
14511 int reg;
14512 const char **names;
14513
14514 if (!need_vex)
14515 abort ();
14516
14517 if (!need_vex_reg)
14518 return;
14519
14520 reg = vex.register_specifier;
14521 if (bytemode == vex_scalar_mode)
14522 {
14523 oappend (names_xmm[reg]);
14524 return;
14525 }
14526
14527 switch (vex.length)
14528 {
14529 case 128:
14530 switch (bytemode)
14531 {
14532 case vex_mode:
14533 case vex128_mode:
14534 break;
14535 default:
14536 abort ();
14537 return;
14538 }
14539
14540 names = names_xmm;
14541 break;
14542 case 256:
14543 switch (bytemode)
14544 {
14545 case vex_mode:
14546 case vex256_mode:
14547 break;
14548 default:
14549 abort ();
14550 return;
14551 }
14552
14553 names = names_ymm;
14554 break;
14555 default:
14556 abort ();
14557 break;
14558 }
14559 oappend (names[reg]);
14560}
14561
14562/* Get the VEX immediate byte without moving codep. */
14563
14564static unsigned char
14565get_vex_imm8 (int sizeflag, int opnum)
14566{
14567 int bytes_before_imm = 0;
14568
14569 if (modrm.mod != 3)
14570 {
14571 /* There are SIB/displacement bytes. */
14572 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14573 {
14574 /* 32/64 bit address mode */
14575 int base = modrm.rm;
14576
14577 /* Check SIB byte. */
14578 if (base == 4)
14579 {
14580 FETCH_DATA (the_info, codep + 1);
14581 base = *codep & 7;
14582 /* When decoding the third source, don't increase
14583 bytes_before_imm as this has already been incremented
14584 by one in OP_E_memory while decoding the second
14585 source operand. */
14586 if (opnum == 0)
14587 bytes_before_imm++;
14588 }
14589
14590 /* Don't increase bytes_before_imm when decoding the third source,
14591 it has already been incremented by OP_E_memory while decoding
14592 the second source operand. */
14593 if (opnum == 0)
14594 {
14595 switch (modrm.mod)
14596 {
14597 case 0:
14598 /* When modrm.rm == 5 or modrm.rm == 4 and base in
14599 SIB == 5, there is a 4 byte displacement. */
14600 if (base != 5)
14601 /* No displacement. */
14602 break;
14603 case 2:
14604 /* 4 byte displacement. */
14605 bytes_before_imm += 4;
14606 break;
14607 case 1:
14608 /* 1 byte displacement. */
14609 bytes_before_imm++;
14610 break;
14611 }
14612 }
14613 }
14614 else
14615 {
14616 /* 16 bit address mode */
14617 /* Don't increase bytes_before_imm when decoding the third source,
14618 it has already been incremented by OP_E_memory while decoding
14619 the second source operand. */
14620 if (opnum == 0)
14621 {
14622 switch (modrm.mod)
14623 {
14624 case 0:
14625 /* When modrm.rm == 6, there is a 2 byte displacement. */
14626 if (modrm.rm != 6)
14627 /* No displacement. */
14628 break;
14629 case 2:
14630 /* 2 byte displacement. */
14631 bytes_before_imm += 2;
14632 break;
14633 case 1:
14634 /* 1 byte displacement: when decoding the third source,
14635 don't increase bytes_before_imm as this has already
14636 been incremented by one in OP_E_memory while decoding
14637 the second source operand. */
14638 if (opnum == 0)
14639 bytes_before_imm++;
14640
14641 break;
14642 }
14643 }
14644 }
14645 }
14646
14647 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14648 return codep [bytes_before_imm];
14649}
14650
14651static void
14652OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14653{
14654 const char **names;
14655
14656 if (reg == -1 && modrm.mod != 3)
14657 {
14658 OP_E_memory (bytemode, sizeflag);
14659 return;
14660 }
14661 else
14662 {
14663 if (reg == -1)
14664 {
14665 reg = modrm.rm;
14666 USED_REX (REX_B);
14667 if (rex & REX_B)
14668 reg += 8;
14669 }
14670 else if (reg > 7 && address_mode != mode_64bit)
14671 BadOp ();
14672 }
14673
14674 switch (vex.length)
14675 {
14676 case 128:
14677 names = names_xmm;
14678 break;
14679 case 256:
14680 names = names_ymm;
14681 break;
14682 default:
14683 abort ();
14684 }
14685 oappend (names[reg]);
14686}
14687
14688static void
14689OP_EX_VexImmW (int bytemode, int sizeflag)
14690{
14691 int reg = -1;
14692 static unsigned char vex_imm8;
14693
14694 if (vex_w_done == 0)
14695 {
14696 vex_w_done = 1;
14697
14698 /* Skip mod/rm byte. */
14699 MODRM_CHECK;
14700 codep++;
14701
14702 vex_imm8 = get_vex_imm8 (sizeflag, 0);
14703
14704 if (vex.w)
14705 reg = vex_imm8 >> 4;
14706
14707 OP_EX_VexReg (bytemode, sizeflag, reg);
14708 }
14709 else if (vex_w_done == 1)
14710 {
14711 vex_w_done = 2;
14712
14713 if (!vex.w)
14714 reg = vex_imm8 >> 4;
14715
14716 OP_EX_VexReg (bytemode, sizeflag, reg);
14717 }
14718 else
14719 {
14720 /* Output the imm8 directly. */
14721 scratchbuf[0] = '$';
14722 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14723 oappend (scratchbuf + intel_syntax);
14724 scratchbuf[0] = '\0';
14725 codep++;
14726 }
14727}
14728
14729static void
14730OP_Vex_2src (int bytemode, int sizeflag)
14731{
14732 if (modrm.mod == 3)
14733 {
14734 int reg = modrm.rm;
14735 USED_REX (REX_B);
14736 if (rex & REX_B)
14737 reg += 8;
14738 oappend (names_xmm[reg]);
14739 }
14740 else
14741 {
14742 if (intel_syntax
14743 && (bytemode == v_mode || bytemode == v_swap_mode))
14744 {
14745 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14746 used_prefixes |= (prefixes & PREFIX_DATA);
14747 }
14748 OP_E (bytemode, sizeflag);
14749 }
14750}
14751
14752static void
14753OP_Vex_2src_1 (int bytemode, int sizeflag)
14754{
14755 if (modrm.mod == 3)
14756 {
14757 /* Skip mod/rm byte. */
14758 MODRM_CHECK;
14759 codep++;
14760 }
14761
14762 if (vex.w)
14763 oappend (names_xmm[vex.register_specifier]);
14764 else
14765 OP_Vex_2src (bytemode, sizeflag);
14766}
14767
14768static void
14769OP_Vex_2src_2 (int bytemode, int sizeflag)
14770{
14771 if (vex.w)
14772 OP_Vex_2src (bytemode, sizeflag);
14773 else
14774 oappend (names_xmm[vex.register_specifier]);
14775}
14776
14777static void
14778OP_EX_VexW (int bytemode, int sizeflag)
14779{
14780 int reg = -1;
14781
14782 if (!vex_w_done)
14783 {
14784 vex_w_done = 1;
14785
14786 /* Skip mod/rm byte. */
14787 MODRM_CHECK;
14788 codep++;
14789
14790 if (vex.w)
14791 reg = get_vex_imm8 (sizeflag, 0) >> 4;
14792 }
14793 else
14794 {
14795 if (!vex.w)
14796 reg = get_vex_imm8 (sizeflag, 1) >> 4;
14797 }
14798
14799 OP_EX_VexReg (bytemode, sizeflag, reg);
14800}
14801
14802static void
14803VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14804 int sizeflag ATTRIBUTE_UNUSED)
14805{
14806 /* Skip the immediate byte and check for invalid bits. */
14807 FETCH_DATA (the_info, codep + 1);
14808 if (*codep++ & 0xf)
14809 BadOp ();
14810}
14811
14812static void
14813OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14814{
14815 int reg;
14816 const char **names;
14817
14818 FETCH_DATA (the_info, codep + 1);
14819 reg = *codep++;
14820
14821 if (bytemode != x_mode)
14822 abort ();
14823
14824 if (reg & 0xf)
14825 BadOp ();
14826
14827 reg >>= 4;
14828 if (reg > 7 && address_mode != mode_64bit)
14829 BadOp ();
14830
14831 switch (vex.length)
14832 {
14833 case 128:
14834 names = names_xmm;
14835 break;
14836 case 256:
14837 names = names_ymm;
14838 break;
14839 default:
14840 abort ();
14841 }
14842 oappend (names[reg]);
14843}
14844
14845static void
14846OP_XMM_VexW (int bytemode, int sizeflag)
14847{
14848 /* Turn off the REX.W bit since it is used for swapping operands
14849 now. */
14850 rex &= ~REX_W;
14851 OP_XMM (bytemode, sizeflag);
14852}
14853
14854static void
14855OP_EX_Vex (int bytemode, int sizeflag)
14856{
14857 if (modrm.mod != 3)
14858 {
14859 if (vex.register_specifier != 0)
14860 BadOp ();
14861 need_vex_reg = 0;
14862 }
14863 OP_EX (bytemode, sizeflag);
14864}
14865
14866static void
14867OP_XMM_Vex (int bytemode, int sizeflag)
14868{
14869 if (modrm.mod != 3)
14870 {
14871 if (vex.register_specifier != 0)
14872 BadOp ();
14873 need_vex_reg = 0;
14874 }
14875 OP_XMM (bytemode, sizeflag);
14876}
14877
14878static void
14879VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14880{
14881 switch (vex.length)
14882 {
14883 case 128:
14884 mnemonicendp = stpcpy (obuf, "vzeroupper");
14885 break;
14886 case 256:
14887 mnemonicendp = stpcpy (obuf, "vzeroall");
14888 break;
14889 default:
14890 abort ();
14891 }
14892}
14893
14894static struct op vex_cmp_op[] =
14895{
14896 { STRING_COMMA_LEN ("eq") },
14897 { STRING_COMMA_LEN ("lt") },
14898 { STRING_COMMA_LEN ("le") },
14899 { STRING_COMMA_LEN ("unord") },
14900 { STRING_COMMA_LEN ("neq") },
14901 { STRING_COMMA_LEN ("nlt") },
14902 { STRING_COMMA_LEN ("nle") },
14903 { STRING_COMMA_LEN ("ord") },
14904 { STRING_COMMA_LEN ("eq_uq") },
14905 { STRING_COMMA_LEN ("nge") },
14906 { STRING_COMMA_LEN ("ngt") },
14907 { STRING_COMMA_LEN ("false") },
14908 { STRING_COMMA_LEN ("neq_oq") },
14909 { STRING_COMMA_LEN ("ge") },
14910 { STRING_COMMA_LEN ("gt") },
14911 { STRING_COMMA_LEN ("true") },
14912 { STRING_COMMA_LEN ("eq_os") },
14913 { STRING_COMMA_LEN ("lt_oq") },
14914 { STRING_COMMA_LEN ("le_oq") },
14915 { STRING_COMMA_LEN ("unord_s") },
14916 { STRING_COMMA_LEN ("neq_us") },
14917 { STRING_COMMA_LEN ("nlt_uq") },
14918 { STRING_COMMA_LEN ("nle_uq") },
14919 { STRING_COMMA_LEN ("ord_s") },
14920 { STRING_COMMA_LEN ("eq_us") },
14921 { STRING_COMMA_LEN ("nge_uq") },
14922 { STRING_COMMA_LEN ("ngt_uq") },
14923 { STRING_COMMA_LEN ("false_os") },
14924 { STRING_COMMA_LEN ("neq_os") },
14925 { STRING_COMMA_LEN ("ge_oq") },
14926 { STRING_COMMA_LEN ("gt_oq") },
14927 { STRING_COMMA_LEN ("true_us") },
14928};
14929
14930static void
14931VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14932{
14933 unsigned int cmp_type;
14934
14935 FETCH_DATA (the_info, codep + 1);
14936 cmp_type = *codep++ & 0xff;
14937 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14938 {
14939 char suffix [3];
14940 char *p = mnemonicendp - 2;
14941 suffix[0] = p[0];
14942 suffix[1] = p[1];
14943 suffix[2] = '\0';
14944 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14945 mnemonicendp += vex_cmp_op[cmp_type].len;
14946 }
14947 else
14948 {
14949 /* We have a reserved extension byte. Output it directly. */
14950 scratchbuf[0] = '$';
14951 print_operand_value (scratchbuf + 1, 1, cmp_type);
14952 oappend (scratchbuf + intel_syntax);
14953 scratchbuf[0] = '\0';
14954 }
14955}
14956
14957static const struct op pclmul_op[] =
14958{
14959 { STRING_COMMA_LEN ("lql") },
14960 { STRING_COMMA_LEN ("hql") },
14961 { STRING_COMMA_LEN ("lqh") },
14962 { STRING_COMMA_LEN ("hqh") }
14963};
14964
14965static void
14966PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14967 int sizeflag ATTRIBUTE_UNUSED)
14968{
14969 unsigned int pclmul_type;
14970
14971 FETCH_DATA (the_info, codep + 1);
14972 pclmul_type = *codep++ & 0xff;
14973 switch (pclmul_type)
14974 {
14975 case 0x10:
14976 pclmul_type = 2;
14977 break;
14978 case 0x11:
14979 pclmul_type = 3;
14980 break;
14981 default:
14982 break;
14983 }
14984 if (pclmul_type < ARRAY_SIZE (pclmul_op))
14985 {
14986 char suffix [4];
14987 char *p = mnemonicendp - 3;
14988 suffix[0] = p[0];
14989 suffix[1] = p[1];
14990 suffix[2] = p[2];
14991 suffix[3] = '\0';
14992 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14993 mnemonicendp += pclmul_op[pclmul_type].len;
14994 }
14995 else
14996 {
14997 /* We have a reserved extension byte. Output it directly. */
14998 scratchbuf[0] = '$';
14999 print_operand_value (scratchbuf + 1, 1, pclmul_type);
15000 oappend (scratchbuf + intel_syntax);
15001 scratchbuf[0] = '\0';
15002 }
15003}
15004
15005static void
15006MOVBE_Fixup (int bytemode, int sizeflag)
15007{
15008 /* Add proper suffix to "movbe". */
15009 char *p = mnemonicendp;
15010
15011 switch (bytemode)
15012 {
15013 case v_mode:
15014 if (intel_syntax)
15015 goto skip;
15016
15017 USED_REX (REX_W);
15018 if (sizeflag & SUFFIX_ALWAYS)
15019 {
15020 if (rex & REX_W)
15021 *p++ = 'q';
15022 else
15023 {
15024 if (sizeflag & DFLAG)
15025 *p++ = 'l';
15026 else
15027 *p++ = 'w';
15028 used_prefixes |= (prefixes & PREFIX_DATA);
15029 }
15030 }
15031 break;
15032 default:
15033 oappend (INTERNAL_DISASSEMBLER_ERROR);
15034 break;
15035 }
15036 mnemonicendp = p;
15037 *p = '\0';
15038
15039skip:
15040 OP_M (bytemode, sizeflag);
15041}
15042
15043static void
15044OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15045{
15046 int reg;
15047 const char **names;
15048
15049 /* Skip mod/rm byte. */
15050 MODRM_CHECK;
15051 codep++;
15052
15053 if (vex.w)
15054 names = names64;
15055 else
15056 names = names32;
15057
15058 reg = modrm.rm;
15059 USED_REX (REX_B);
15060 if (rex & REX_B)
15061 reg += 8;
15062
15063 oappend (names[reg]);
15064}
15065
15066static void
15067OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15068{
15069 const char **names;
15070
15071 if (vex.w)
15072 names = names64;
15073 else
15074 names = names32;
15075
15076 oappend (names[vex.register_specifier]);
15077}
15078
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