| | 1 | /* Simulator for Motorola's MCore processor |
| | 2 | Copyright (C) 1999-2021 Free Software Foundation, Inc. |
| | 3 | Contributed by Cygnus Solutions. |
| | 4 | |
| | 5 | This file is part of GDB, the GNU debugger. |
| | 6 | |
| | 7 | This program is free software; you can redistribute it and/or modify |
| | 8 | it under the terms of the GNU General Public License as published by |
| | 9 | the Free Software Foundation; either version 3 of the License, or |
| | 10 | (at your option) any later version. |
| | 11 | |
| | 12 | This program is distributed in the hope that it will be useful, |
| | 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| | 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| | 15 | GNU General Public License for more details. |
| | 16 | |
| | 17 | You should have received a copy of the GNU General Public License |
| | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| | 19 | |
| | 20 | #include "config.h" |
| | 21 | #include <signal.h> |
| | 22 | #include <stdlib.h> |
| | 23 | #include <string.h> |
| | 24 | #include <sys/param.h> |
| | 25 | #include <unistd.h> |
| | 26 | #include "bfd.h" |
| | 27 | #include "sim/callback.h" |
| | 28 | #include "libiberty.h" |
| | 29 | #include "sim/sim.h" |
| | 30 | |
| | 31 | #include "sim-main.h" |
| | 32 | #include "sim-base.h" |
| | 33 | #include "sim-syscall.h" |
| | 34 | #include "sim-options.h" |
| | 35 | |
| | 36 | #define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) |
| | 37 | |
| | 38 | |
| | 39 | static unsigned long |
| | 40 | mcore_extract_unsigned_integer (unsigned char *addr, int len) |
| | 41 | { |
| | 42 | unsigned long retval; |
| | 43 | unsigned char * p; |
| | 44 | unsigned char * startaddr = (unsigned char *)addr; |
| | 45 | unsigned char * endaddr = startaddr + len; |
| | 46 | |
| | 47 | if (len > (int) sizeof (unsigned long)) |
| | 48 | printf ("That operation is not available on integers of more than %zu bytes.", |
| | 49 | sizeof (unsigned long)); |
| | 50 | |
| | 51 | /* Start at the most significant end of the integer, and work towards |
| | 52 | the least significant. */ |
| | 53 | retval = 0; |
| | 54 | |
| | 55 | if (! target_big_endian) |
| | 56 | { |
| | 57 | for (p = endaddr; p > startaddr;) |
| | 58 | retval = (retval << 8) | * -- p; |
| | 59 | } |
| | 60 | else |
| | 61 | { |
| | 62 | for (p = startaddr; p < endaddr;) |
| | 63 | retval = (retval << 8) | * p ++; |
| | 64 | } |
| | 65 | |
| | 66 | return retval; |
| | 67 | } |
| | 68 | |
| | 69 | static void |
| | 70 | mcore_store_unsigned_integer (unsigned char *addr, int len, unsigned long val) |
| | 71 | { |
| | 72 | unsigned char * p; |
| | 73 | unsigned char * startaddr = (unsigned char *)addr; |
| | 74 | unsigned char * endaddr = startaddr + len; |
| | 75 | |
| | 76 | if (! target_big_endian) |
| | 77 | { |
| | 78 | for (p = startaddr; p < endaddr;) |
| | 79 | { |
| | 80 | * p ++ = val & 0xff; |
| | 81 | val >>= 8; |
| | 82 | } |
| | 83 | } |
| | 84 | else |
| | 85 | { |
| | 86 | for (p = endaddr; p > startaddr;) |
| | 87 | { |
| | 88 | * -- p = val & 0xff; |
| | 89 | val >>= 8; |
| | 90 | } |
| | 91 | } |
| | 92 | } |
| | 93 | |
| | 94 | static int memcycles = 1; |
| | 95 | |
| | 96 | #define gr cpu->active_gregs |
| | 97 | #define cr cpu->regs.cregs |
| | 98 | #define sr cr[0] |
| | 99 | #define vbr cr[1] |
| | 100 | #define esr cr[2] |
| | 101 | #define fsr cr[3] |
| | 102 | #define epc cr[4] |
| | 103 | #define fpc cr[5] |
| | 104 | #define ss0 cr[6] |
| | 105 | #define ss1 cr[7] |
| | 106 | #define ss2 cr[8] |
| | 107 | #define ss3 cr[9] |
| | 108 | #define ss4 cr[10] |
| | 109 | #define gcr cr[11] |
| | 110 | #define gsr cr[12] |
| | 111 | |
| | 112 | /* maniuplate the carry bit */ |
| | 113 | #define C_ON() (sr & 1) |
| | 114 | #define C_VALUE() (sr & 1) |
| | 115 | #define C_OFF() ((sr & 1) == 0) |
| | 116 | #define SET_C() {sr |= 1;} |
| | 117 | #define CLR_C() {sr &= 0xfffffffe;} |
| | 118 | #define NEW_C(v) {CLR_C(); sr |= ((v) & 1);} |
| | 119 | |
| | 120 | #define SR_AF() ((sr >> 1) & 1) |
| | 121 | static void set_active_regs (SIM_CPU *cpu) |
| | 122 | { |
| | 123 | if (SR_AF()) |
| | 124 | cpu->active_gregs = cpu->regs.alt_gregs; |
| | 125 | else |
| | 126 | cpu->active_gregs = cpu->regs.gregs; |
| | 127 | } |
| | 128 | |
| | 129 | #define TRAPCODE 1 /* r1 holds which function we want */ |
| | 130 | #define PARM1 2 /* first parameter */ |
| | 131 | #define PARM2 3 |
| | 132 | #define PARM3 4 |
| | 133 | #define PARM4 5 |
| | 134 | #define RET1 2 /* register for return values. */ |
| | 135 | |
| | 136 | /* Default to a 8 Mbyte (== 2^23) memory space. */ |
| | 137 | #define DEFAULT_MEMORY_SIZE 0x800000 |
| | 138 | |
| | 139 | static void |
| | 140 | set_initial_gprs (SIM_CPU *cpu) |
| | 141 | { |
| | 142 | /* Set up machine just out of reset. */ |
| | 143 | CPU_PC_SET (cpu, 0); |
| | 144 | sr = 0; |
| | 145 | |
| | 146 | /* Clean out the GPRs and alternate GPRs. */ |
| | 147 | memset (&cpu->regs.gregs, 0, sizeof(cpu->regs.gregs)); |
| | 148 | memset (&cpu->regs.alt_gregs, 0, sizeof(cpu->regs.alt_gregs)); |
| | 149 | |
| | 150 | /* Make our register set point to the right place. */ |
| | 151 | set_active_regs (cpu); |
| | 152 | |
| | 153 | /* ABI specifies initial values for these registers. */ |
| | 154 | gr[0] = DEFAULT_MEMORY_SIZE - 4; |
| | 155 | |
| | 156 | /* dac fix, the stack address must be 8-byte aligned! */ |
| | 157 | gr[0] = gr[0] - gr[0] % 8; |
| | 158 | gr[PARM1] = 0; |
| | 159 | gr[PARM2] = 0; |
| | 160 | gr[PARM3] = 0; |
| | 161 | gr[PARM4] = gr[0]; |
| | 162 | } |
| | 163 | |
| | 164 | /* Simulate a monitor trap. */ |
| | 165 | |
| | 166 | static void |
| | 167 | handle_trap1 (SIM_DESC sd, SIM_CPU *cpu) |
| | 168 | { |
| | 169 | /* XXX: We don't pass back the actual errno value. */ |
| | 170 | gr[RET1] = sim_syscall (cpu, gr[TRAPCODE], gr[PARM1], gr[PARM2], gr[PARM3], |
| | 171 | gr[PARM4]); |
| | 172 | } |
| | 173 | |
| | 174 | static void |
| | 175 | process_stub (SIM_DESC sd, SIM_CPU *cpu, int what) |
| | 176 | { |
| | 177 | /* These values should match those in libgloss/mcore/syscalls.s. */ |
| | 178 | switch (what) |
| | 179 | { |
| | 180 | case 3: /* _read */ |
| | 181 | case 4: /* _write */ |
| | 182 | case 5: /* _open */ |
| | 183 | case 6: /* _close */ |
| | 184 | case 10: /* _unlink */ |
| | 185 | case 19: /* _lseek */ |
| | 186 | case 43: /* _times */ |
| | 187 | gr[TRAPCODE] = what; |
| | 188 | handle_trap1 (sd, cpu); |
| | 189 | break; |
| | 190 | |
| | 191 | default: |
| | 192 | if (STATE_VERBOSE_P (sd)) |
| | 193 | fprintf (stderr, "Unhandled stub opcode: %d\n", what); |
| | 194 | break; |
| | 195 | } |
| | 196 | } |
| | 197 | |
| | 198 | static void |
| | 199 | util (SIM_DESC sd, SIM_CPU *cpu, unsigned what) |
| | 200 | { |
| | 201 | switch (what) |
| | 202 | { |
| | 203 | case 0: /* exit */ |
| | 204 | sim_engine_halt (sd, cpu, NULL, cpu->regs.pc, sim_exited, gr[PARM1]); |
| | 205 | break; |
| | 206 | |
| | 207 | case 1: /* printf */ |
| | 208 | if (STATE_VERBOSE_P (sd)) |
| | 209 | fprintf (stderr, "WARNING: printf unimplemented\n"); |
| | 210 | break; |
| | 211 | |
| | 212 | case 2: /* scanf */ |
| | 213 | if (STATE_VERBOSE_P (sd)) |
| | 214 | fprintf (stderr, "WARNING: scanf unimplemented\n"); |
| | 215 | break; |
| | 216 | |
| | 217 | case 3: /* utime */ |
| | 218 | gr[RET1] = cpu->insts; |
| | 219 | break; |
| | 220 | |
| | 221 | case 0xFF: |
| | 222 | process_stub (sd, cpu, gr[1]); |
| | 223 | break; |
| | 224 | |
| | 225 | default: |
| | 226 | if (STATE_VERBOSE_P (sd)) |
| | 227 | fprintf (stderr, "Unhandled util code: %x\n", what); |
| | 228 | break; |
| | 229 | } |
| | 230 | } |
| | 231 | |
| | 232 | /* For figuring out whether we carried; addc/subc use this. */ |
| | 233 | static int |
| | 234 | iu_carry (unsigned long a, unsigned long b, int cin) |
| | 235 | { |
| | 236 | unsigned long x; |
| | 237 | |
| | 238 | x = (a & 0xffff) + (b & 0xffff) + cin; |
| | 239 | x = (x >> 16) + (a >> 16) + (b >> 16); |
| | 240 | x >>= 16; |
| | 241 | |
| | 242 | return (x != 0); |
| | 243 | } |
| | 244 | |
| | 245 | /* TODO: Convert to common watchpoints. */ |
| | 246 | #undef WATCHFUNCTIONS |
| | 247 | #ifdef WATCHFUNCTIONS |
| | 248 | |
| | 249 | #define MAXWL 80 |
| | 250 | word WL[MAXWL]; |
| | 251 | char * WLstr[MAXWL]; |
| | 252 | |
| | 253 | int ENDWL=0; |
| | 254 | int WLincyc; |
| | 255 | int WLcyc[MAXWL]; |
| | 256 | int WLcnts[MAXWL]; |
| | 257 | int WLmax[MAXWL]; |
| | 258 | int WLmin[MAXWL]; |
| | 259 | word WLendpc; |
| | 260 | int WLbcyc; |
| | 261 | int WLW; |
| | 262 | #endif |
| | 263 | |
| | 264 | #define RD (inst & 0xF) |
| | 265 | #define RS ((inst >> 4) & 0xF) |
| | 266 | #define RX ((inst >> 8) & 0xF) |
| | 267 | #define IMM5 ((inst >> 4) & 0x1F) |
| | 268 | #define IMM4 ((inst) & 0xF) |
| | 269 | |
| | 270 | #define rbat(X) sim_core_read_1 (cpu, 0, read_map, X) |
| | 271 | #define rhat(X) sim_core_read_2 (cpu, 0, read_map, X) |
| | 272 | #define rlat(X) sim_core_read_4 (cpu, 0, read_map, X) |
| | 273 | #define wbat(X, D) sim_core_write_1 (cpu, 0, write_map, X, D) |
| | 274 | #define what(X, D) sim_core_write_2 (cpu, 0, write_map, X, D) |
| | 275 | #define wlat(X, D) sim_core_write_4 (cpu, 0, write_map, X, D) |
| | 276 | |
| | 277 | static int tracing = 0; |
| | 278 | |
| | 279 | #define ILLEGAL() \ |
| | 280 | sim_engine_halt (sd, cpu, NULL, pc, sim_stopped, SIM_SIGILL) |
| | 281 | |
| | 282 | static void |
| | 283 | step_once (SIM_DESC sd, SIM_CPU *cpu) |
| | 284 | { |
| | 285 | int needfetch; |
| | 286 | word ibuf; |
| | 287 | word pc; |
| | 288 | unsigned short inst; |
| | 289 | int memops; |
| | 290 | int bonus_cycles; |
| | 291 | int insts; |
| | 292 | int w; |
| | 293 | int cycs; |
| | 294 | #ifdef WATCHFUNCTIONS |
| | 295 | word WLhash; |
| | 296 | #endif |
| | 297 | |
| | 298 | pc = CPU_PC_GET (cpu); |
| | 299 | |
| | 300 | /* Fetch the initial instructions that we'll decode. */ |
| | 301 | ibuf = rlat (pc & 0xFFFFFFFC); |
| | 302 | needfetch = 0; |
| | 303 | |
| | 304 | memops = 0; |
| | 305 | bonus_cycles = 0; |
| | 306 | insts = 0; |
| | 307 | |
| | 308 | /* make our register set point to the right place */ |
| | 309 | set_active_regs (cpu); |
| | 310 | |
| | 311 | #ifdef WATCHFUNCTIONS |
| | 312 | /* make a hash to speed exec loop, hope it's nonzero */ |
| | 313 | WLhash = 0xFFFFFFFF; |
| | 314 | |
| | 315 | for (w = 1; w <= ENDWL; w++) |
| | 316 | WLhash = WLhash & WL[w]; |
| | 317 | #endif |
| | 318 | |
| | 319 | /* TODO: Unindent this block. */ |
| | 320 | { |
| | 321 | word oldpc; |
| | 322 | |
| | 323 | insts ++; |
| | 324 | |
| | 325 | if (pc & 02) |
| | 326 | { |
| | 327 | if (! target_big_endian) |
| | 328 | inst = ibuf >> 16; |
| | 329 | else |
| | 330 | inst = ibuf & 0xFFFF; |
| | 331 | needfetch = 1; |
| | 332 | } |
| | 333 | else |
| | 334 | { |
| | 335 | if (! target_big_endian) |
| | 336 | inst = ibuf & 0xFFFF; |
| | 337 | else |
| | 338 | inst = ibuf >> 16; |
| | 339 | } |
| | 340 | |
| | 341 | #ifdef WATCHFUNCTIONS |
| | 342 | /* now scan list of watch addresses, if match, count it and |
| | 343 | note return address and count cycles until pc=return address */ |
| | 344 | |
| | 345 | if ((WLincyc == 1) && (pc == WLendpc)) |
| | 346 | { |
| | 347 | cycs = (cpu->cycles + (insts + bonus_cycles + |
| | 348 | (memops * memcycles)) - WLbcyc); |
| | 349 | |
| | 350 | if (WLcnts[WLW] == 1) |
| | 351 | { |
| | 352 | WLmax[WLW] = cycs; |
| | 353 | WLmin[WLW] = cycs; |
| | 354 | WLcyc[WLW] = 0; |
| | 355 | } |
| | 356 | |
| | 357 | if (cycs > WLmax[WLW]) |
| | 358 | { |
| | 359 | WLmax[WLW] = cycs; |
| | 360 | } |
| | 361 | |
| | 362 | if (cycs < WLmin[WLW]) |
| | 363 | { |
| | 364 | WLmin[WLW] = cycs; |
| | 365 | } |
| | 366 | |
| | 367 | WLcyc[WLW] += cycs; |
| | 368 | WLincyc = 0; |
| | 369 | WLendpc = 0; |
| | 370 | } |
| | 371 | |
| | 372 | /* Optimize with a hash to speed loop. */ |
| | 373 | if (WLincyc == 0) |
| | 374 | { |
| | 375 | if ((WLhash == 0) || ((WLhash & pc) != 0)) |
| | 376 | { |
| | 377 | for (w=1; w <= ENDWL; w++) |
| | 378 | { |
| | 379 | if (pc == WL[w]) |
| | 380 | { |
| | 381 | WLcnts[w]++; |
| | 382 | WLbcyc = cpu->cycles + insts |
| | 383 | + bonus_cycles + (memops * memcycles); |
| | 384 | WLendpc = gr[15]; |
| | 385 | WLincyc = 1; |
| | 386 | WLW = w; |
| | 387 | break; |
| | 388 | } |
| | 389 | } |
| | 390 | } |
| | 391 | } |
| | 392 | #endif |
| | 393 | |
| | 394 | if (tracing) |
| | 395 | fprintf (stderr, "%.4lx: inst = %.4x ", pc, inst); |
| | 396 | |
| | 397 | oldpc = pc; |
| | 398 | |
| | 399 | pc += 2; |
| | 400 | |
| | 401 | switch (inst >> 8) |
| | 402 | { |
| | 403 | case 0x00: |
| | 404 | switch RS |
| | 405 | { |
| | 406 | case 0x0: |
| | 407 | switch RD |
| | 408 | { |
| | 409 | case 0x0: /* bkpt */ |
| | 410 | pc -= 2; |
| | 411 | sim_engine_halt (sd, cpu, NULL, pc - 2, |
| | 412 | sim_stopped, SIM_SIGTRAP); |
| | 413 | break; |
| | 414 | |
| | 415 | case 0x1: /* sync */ |
| | 416 | break; |
| | 417 | |
| | 418 | case 0x2: /* rte */ |
| | 419 | pc = epc; |
| | 420 | sr = esr; |
| | 421 | needfetch = 1; |
| | 422 | |
| | 423 | set_active_regs (cpu); |
| | 424 | break; |
| | 425 | |
| | 426 | case 0x3: /* rfi */ |
| | 427 | pc = fpc; |
| | 428 | sr = fsr; |
| | 429 | needfetch = 1; |
| | 430 | |
| | 431 | set_active_regs (cpu); |
| | 432 | break; |
| | 433 | |
| | 434 | case 0x4: /* stop */ |
| | 435 | if (STATE_VERBOSE_P (sd)) |
| | 436 | fprintf (stderr, "WARNING: stop unimplemented\n"); |
| | 437 | break; |
| | 438 | |
| | 439 | case 0x5: /* wait */ |
| | 440 | if (STATE_VERBOSE_P (sd)) |
| | 441 | fprintf (stderr, "WARNING: wait unimplemented\n"); |
| | 442 | break; |
| | 443 | |
| | 444 | case 0x6: /* doze */ |
| | 445 | if (STATE_VERBOSE_P (sd)) |
| | 446 | fprintf (stderr, "WARNING: doze unimplemented\n"); |
| | 447 | break; |
| | 448 | |
| | 449 | case 0x7: |
| | 450 | ILLEGAL (); /* illegal */ |
| | 451 | break; |
| | 452 | |
| | 453 | case 0x8: /* trap 0 */ |
| | 454 | case 0xA: /* trap 2 */ |
| | 455 | case 0xB: /* trap 3 */ |
| | 456 | sim_engine_halt (sd, cpu, NULL, pc, |
| | 457 | sim_stopped, SIM_SIGTRAP); |
| | 458 | break; |
| | 459 | |
| | 460 | case 0xC: /* trap 4 */ |
| | 461 | case 0xD: /* trap 5 */ |
| | 462 | case 0xE: /* trap 6 */ |
| | 463 | ILLEGAL (); /* illegal */ |
| | 464 | break; |
| | 465 | |
| | 466 | case 0xF: /* trap 7 */ |
| | 467 | sim_engine_halt (sd, cpu, NULL, pc, /* integer div-by-0 */ |
| | 468 | sim_stopped, SIM_SIGTRAP); |
| | 469 | break; |
| | 470 | |
| | 471 | case 0x9: /* trap 1 */ |
| | 472 | handle_trap1 (sd, cpu); |
| | 473 | break; |
| | 474 | } |
| | 475 | break; |
| | 476 | |
| | 477 | case 0x1: |
| | 478 | ILLEGAL (); /* illegal */ |
| | 479 | break; |
| | 480 | |
| | 481 | case 0x2: /* mvc */ |
| | 482 | gr[RD] = C_VALUE(); |
| | 483 | break; |
| | 484 | case 0x3: /* mvcv */ |
| | 485 | gr[RD] = C_OFF(); |
| | 486 | break; |
| | 487 | case 0x4: /* ldq */ |
| | 488 | { |
| | 489 | word addr = gr[RD]; |
| | 490 | int regno = 4; /* always r4-r7 */ |
| | 491 | |
| | 492 | bonus_cycles++; |
| | 493 | memops += 4; |
| | 494 | do |
| | 495 | { |
| | 496 | gr[regno] = rlat (addr); |
| | 497 | addr += 4; |
| | 498 | regno++; |
| | 499 | } |
| | 500 | while ((regno&0x3) != 0); |
| | 501 | } |
| | 502 | break; |
| | 503 | case 0x5: /* stq */ |
| | 504 | { |
| | 505 | word addr = gr[RD]; |
| | 506 | int regno = 4; /* always r4-r7 */ |
| | 507 | |
| | 508 | memops += 4; |
| | 509 | bonus_cycles++; |
| | 510 | do |
| | 511 | { |
| | 512 | wlat (addr, gr[regno]); |
| | 513 | addr += 4; |
| | 514 | regno++; |
| | 515 | } |
| | 516 | while ((regno & 0x3) != 0); |
| | 517 | } |
| | 518 | break; |
| | 519 | case 0x6: /* ldm */ |
| | 520 | { |
| | 521 | word addr = gr[0]; |
| | 522 | int regno = RD; |
| | 523 | |
| | 524 | /* bonus cycle is really only needed if |
| | 525 | the next insn shifts the last reg loaded. |
| | 526 | |
| | 527 | bonus_cycles++; |
| | 528 | */ |
| | 529 | memops += 16-regno; |
| | 530 | while (regno <= 0xF) |
| | 531 | { |
| | 532 | gr[regno] = rlat (addr); |
| | 533 | addr += 4; |
| | 534 | regno++; |
| | 535 | } |
| | 536 | } |
| | 537 | break; |
| | 538 | case 0x7: /* stm */ |
| | 539 | { |
| | 540 | word addr = gr[0]; |
| | 541 | int regno = RD; |
| | 542 | |
| | 543 | /* this should be removed! */ |
| | 544 | /* bonus_cycles ++; */ |
| | 545 | |
| | 546 | memops += 16 - regno; |
| | 547 | while (regno <= 0xF) |
| | 548 | { |
| | 549 | wlat (addr, gr[regno]); |
| | 550 | addr += 4; |
| | 551 | regno++; |
| | 552 | } |
| | 553 | } |
| | 554 | break; |
| | 555 | |
| | 556 | case 0x8: /* dect */ |
| | 557 | gr[RD] -= C_VALUE(); |
| | 558 | break; |
| | 559 | case 0x9: /* decf */ |
| | 560 | gr[RD] -= C_OFF(); |
| | 561 | break; |
| | 562 | case 0xA: /* inct */ |
| | 563 | gr[RD] += C_VALUE(); |
| | 564 | break; |
| | 565 | case 0xB: /* incf */ |
| | 566 | gr[RD] += C_OFF(); |
| | 567 | break; |
| | 568 | case 0xC: /* jmp */ |
| | 569 | pc = gr[RD]; |
| | 570 | if (tracing && RD == 15) |
| | 571 | fprintf (stderr, "Func return, r2 = %lxx, r3 = %lx\n", |
| | 572 | gr[2], gr[3]); |
| | 573 | bonus_cycles++; |
| | 574 | needfetch = 1; |
| | 575 | break; |
| | 576 | case 0xD: /* jsr */ |
| | 577 | gr[15] = pc; |
| | 578 | pc = gr[RD]; |
| | 579 | bonus_cycles++; |
| | 580 | needfetch = 1; |
| | 581 | break; |
| | 582 | case 0xE: /* ff1 */ |
| | 583 | { |
| | 584 | word tmp, i; |
| | 585 | tmp = gr[RD]; |
| | 586 | for (i = 0; !(tmp & 0x80000000) && i < 32; i++) |
| | 587 | tmp <<= 1; |
| | 588 | gr[RD] = i; |
| | 589 | } |
| | 590 | break; |
| | 591 | case 0xF: /* brev */ |
| | 592 | { |
| | 593 | word tmp; |
| | 594 | tmp = gr[RD]; |
| | 595 | tmp = ((tmp & 0xaaaaaaaa) >> 1) | ((tmp & 0x55555555) << 1); |
| | 596 | tmp = ((tmp & 0xcccccccc) >> 2) | ((tmp & 0x33333333) << 2); |
| | 597 | tmp = ((tmp & 0xf0f0f0f0) >> 4) | ((tmp & 0x0f0f0f0f) << 4); |
| | 598 | tmp = ((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8); |
| | 599 | gr[RD] = ((tmp & 0xffff0000) >> 16) | ((tmp & 0x0000ffff) << 16); |
| | 600 | } |
| | 601 | break; |
| | 602 | } |
| | 603 | break; |
| | 604 | case 0x01: |
| | 605 | switch RS |
| | 606 | { |
| | 607 | case 0x0: /* xtrb3 */ |
| | 608 | gr[1] = (gr[RD]) & 0xFF; |
| | 609 | NEW_C (gr[RD] != 0); |
| | 610 | break; |
| | 611 | case 0x1: /* xtrb2 */ |
| | 612 | gr[1] = (gr[RD]>>8) & 0xFF; |
| | 613 | NEW_C (gr[RD] != 0); |
| | 614 | break; |
| | 615 | case 0x2: /* xtrb1 */ |
| | 616 | gr[1] = (gr[RD]>>16) & 0xFF; |
| | 617 | NEW_C (gr[RD] != 0); |
| | 618 | break; |
| | 619 | case 0x3: /* xtrb0 */ |
| | 620 | gr[1] = (gr[RD]>>24) & 0xFF; |
| | 621 | NEW_C (gr[RD] != 0); |
| | 622 | break; |
| | 623 | case 0x4: /* zextb */ |
| | 624 | gr[RD] &= 0x000000FF; |
| | 625 | break; |
| | 626 | case 0x5: /* sextb */ |
| | 627 | { |
| | 628 | long tmp; |
| | 629 | tmp = gr[RD]; |
| | 630 | tmp <<= 24; |
| | 631 | tmp >>= 24; |
| | 632 | gr[RD] = tmp; |
| | 633 | } |
| | 634 | break; |
| | 635 | case 0x6: /* zexth */ |
| | 636 | gr[RD] &= 0x0000FFFF; |
| | 637 | break; |
| | 638 | case 0x7: /* sexth */ |
| | 639 | { |
| | 640 | long tmp; |
| | 641 | tmp = gr[RD]; |
| | 642 | tmp <<= 16; |
| | 643 | tmp >>= 16; |
| | 644 | gr[RD] = tmp; |
| | 645 | } |
| | 646 | break; |
| | 647 | case 0x8: /* declt */ |
| | 648 | --gr[RD]; |
| | 649 | NEW_C ((long)gr[RD] < 0); |
| | 650 | break; |
| | 651 | case 0x9: /* tstnbz */ |
| | 652 | { |
| | 653 | word tmp = gr[RD]; |
| | 654 | NEW_C ((tmp & 0xFF000000) != 0 && |
| | 655 | (tmp & 0x00FF0000) != 0 && (tmp & 0x0000FF00) != 0 && |
| | 656 | (tmp & 0x000000FF) != 0); |
| | 657 | } |
| | 658 | break; |
| | 659 | case 0xA: /* decgt */ |
| | 660 | --gr[RD]; |
| | 661 | NEW_C ((long)gr[RD] > 0); |
| | 662 | break; |
| | 663 | case 0xB: /* decne */ |
| | 664 | --gr[RD]; |
| | 665 | NEW_C ((long)gr[RD] != 0); |
| | 666 | break; |
| | 667 | case 0xC: /* clrt */ |
| | 668 | if (C_ON()) |
| | 669 | gr[RD] = 0; |
| | 670 | break; |
| | 671 | case 0xD: /* clrf */ |
| | 672 | if (C_OFF()) |
| | 673 | gr[RD] = 0; |
| | 674 | break; |
| | 675 | case 0xE: /* abs */ |
| | 676 | if (gr[RD] & 0x80000000) |
| | 677 | gr[RD] = ~gr[RD] + 1; |
| | 678 | break; |
| | 679 | case 0xF: /* not */ |
| | 680 | gr[RD] = ~gr[RD]; |
| | 681 | break; |
| | 682 | } |
| | 683 | break; |
| | 684 | case 0x02: /* movt */ |
| | 685 | if (C_ON()) |
| | 686 | gr[RD] = gr[RS]; |
| | 687 | break; |
| | 688 | case 0x03: /* mult */ |
| | 689 | /* consume 2 bits per cycle from rs, until rs is 0 */ |
| | 690 | { |
| | 691 | unsigned int t = gr[RS]; |
| | 692 | int ticks; |
| | 693 | for (ticks = 0; t != 0 ; t >>= 2) |
| | 694 | ticks++; |
| | 695 | bonus_cycles += ticks; |
| | 696 | } |
| | 697 | bonus_cycles += 2; /* min. is 3, so add 2, plus ticks above */ |
| | 698 | if (tracing) |
| | 699 | fprintf (stderr, " mult %lx by %lx to give %lx", |
| | 700 | gr[RD], gr[RS], gr[RD] * gr[RS]); |
| | 701 | gr[RD] = gr[RD] * gr[RS]; |
| | 702 | break; |
| | 703 | case 0x04: /* loopt */ |
| | 704 | if (C_ON()) |
| | 705 | { |
| | 706 | pc += (IMM4 << 1) - 32; |
| | 707 | bonus_cycles ++; |
| | 708 | needfetch = 1; |
| | 709 | } |
| | 710 | --gr[RS]; /* not RD! */ |
| | 711 | NEW_C (((long)gr[RS]) > 0); |
| | 712 | break; |
| | 713 | case 0x05: /* subu */ |
| | 714 | gr[RD] -= gr[RS]; |
| | 715 | break; |
| | 716 | case 0x06: /* addc */ |
| | 717 | { |
| | 718 | unsigned long tmp, a, b; |
| | 719 | a = gr[RD]; |
| | 720 | b = gr[RS]; |
| | 721 | gr[RD] = a + b + C_VALUE (); |
| | 722 | tmp = iu_carry (a, b, C_VALUE ()); |
| | 723 | NEW_C (tmp); |
| | 724 | } |
| | 725 | break; |
| | 726 | case 0x07: /* subc */ |
| | 727 | { |
| | 728 | unsigned long tmp, a, b; |
| | 729 | a = gr[RD]; |
| | 730 | b = gr[RS]; |
| | 731 | gr[RD] = a - b + C_VALUE () - 1; |
| | 732 | tmp = iu_carry (a,~b, C_VALUE ()); |
| | 733 | NEW_C (tmp); |
| | 734 | } |
| | 735 | break; |
| | 736 | case 0x08: /* illegal */ |
| | 737 | case 0x09: /* illegal*/ |
| | 738 | ILLEGAL (); |
| | 739 | break; |
| | 740 | case 0x0A: /* movf */ |
| | 741 | if (C_OFF()) |
| | 742 | gr[RD] = gr[RS]; |
| | 743 | break; |
| | 744 | case 0x0B: /* lsr */ |
| | 745 | { |
| | 746 | unsigned long dst, src; |
| | 747 | dst = gr[RD]; |
| | 748 | src = gr[RS]; |
| | 749 | /* We must not rely solely upon the native shift operations, since they |
| | 750 | may not match the M*Core's behaviour on boundary conditions. */ |
| | 751 | dst = src > 31 ? 0 : dst >> src; |
| | 752 | gr[RD] = dst; |
| | 753 | } |
| | 754 | break; |
| | 755 | case 0x0C: /* cmphs */ |
| | 756 | NEW_C ((unsigned long )gr[RD] >= |
| | 757 | (unsigned long)gr[RS]); |
| | 758 | break; |
| | 759 | case 0x0D: /* cmplt */ |
| | 760 | NEW_C ((long)gr[RD] < (long)gr[RS]); |
| | 761 | break; |
| | 762 | case 0x0E: /* tst */ |
| | 763 | NEW_C ((gr[RD] & gr[RS]) != 0); |
| | 764 | break; |
| | 765 | case 0x0F: /* cmpne */ |
| | 766 | NEW_C (gr[RD] != gr[RS]); |
| | 767 | break; |
| | 768 | case 0x10: case 0x11: /* mfcr */ |
| | 769 | { |
| | 770 | unsigned r; |
| | 771 | r = IMM5; |
| | 772 | if (r <= LAST_VALID_CREG) |
| | 773 | gr[RD] = cr[r]; |
| | 774 | else |
| | 775 | ILLEGAL (); |
| | 776 | } |
| | 777 | break; |
| | 778 | |
| | 779 | case 0x12: /* mov */ |
| | 780 | gr[RD] = gr[RS]; |
| | 781 | if (tracing) |
| | 782 | fprintf (stderr, "MOV %lx into reg %d", gr[RD], RD); |
| | 783 | break; |
| | 784 | |
| | 785 | case 0x13: /* bgenr */ |
| | 786 | if (gr[RS] & 0x20) |
| | 787 | gr[RD] = 0; |
| | 788 | else |
| | 789 | gr[RD] = 1 << (gr[RS] & 0x1F); |
| | 790 | break; |
| | 791 | |
| | 792 | case 0x14: /* rsub */ |
| | 793 | gr[RD] = gr[RS] - gr[RD]; |
| | 794 | break; |
| | 795 | |
| | 796 | case 0x15: /* ixw */ |
| | 797 | gr[RD] += gr[RS]<<2; |
| | 798 | break; |
| | 799 | |
| | 800 | case 0x16: /* and */ |
| | 801 | gr[RD] &= gr[RS]; |
| | 802 | break; |
| | 803 | |
| | 804 | case 0x17: /* xor */ |
| | 805 | gr[RD] ^= gr[RS]; |
| | 806 | break; |
| | 807 | |
| | 808 | case 0x18: case 0x19: /* mtcr */ |
| | 809 | { |
| | 810 | unsigned r; |
| | 811 | r = IMM5; |
| | 812 | if (r <= LAST_VALID_CREG) |
| | 813 | cr[r] = gr[RD]; |
| | 814 | else |
| | 815 | ILLEGAL (); |
| | 816 | |
| | 817 | /* we might have changed register sets... */ |
| | 818 | set_active_regs (cpu); |
| | 819 | } |
| | 820 | break; |
| | 821 | |
| | 822 | case 0x1A: /* asr */ |
| | 823 | /* We must not rely solely upon the native shift operations, since they |
| | 824 | may not match the M*Core's behaviour on boundary conditions. */ |
| | 825 | if (gr[RS] > 30) |
| | 826 | gr[RD] = ((long) gr[RD]) < 0 ? -1 : 0; |
| | 827 | else |
| | 828 | gr[RD] = (long) gr[RD] >> gr[RS]; |
| | 829 | break; |
| | 830 | |
| | 831 | case 0x1B: /* lsl */ |
| | 832 | /* We must not rely solely upon the native shift operations, since they |
| | 833 | may not match the M*Core's behaviour on boundary conditions. */ |
| | 834 | gr[RD] = gr[RS] > 31 ? 0 : gr[RD] << gr[RS]; |
| | 835 | break; |
| | 836 | |
| | 837 | case 0x1C: /* addu */ |
| | 838 | gr[RD] += gr[RS]; |
| | 839 | break; |
| | 840 | |
| | 841 | case 0x1D: /* ixh */ |
| | 842 | gr[RD] += gr[RS] << 1; |
| | 843 | break; |
| | 844 | |
| | 845 | case 0x1E: /* or */ |
| | 846 | gr[RD] |= gr[RS]; |
| | 847 | break; |
| | 848 | |
| | 849 | case 0x1F: /* andn */ |
| | 850 | gr[RD] &= ~gr[RS]; |
| | 851 | break; |
| | 852 | case 0x20: case 0x21: /* addi */ |
| | 853 | gr[RD] = |
| | 854 | gr[RD] + (IMM5 + 1); |
| | 855 | break; |
| | 856 | case 0x22: case 0x23: /* cmplti */ |
| | 857 | { |
| | 858 | int tmp = (IMM5 + 1); |
| | 859 | if (gr[RD] < tmp) |
| | 860 | { |
| | 861 | SET_C(); |
| | 862 | } |
| | 863 | else |
| | 864 | { |
| | 865 | CLR_C(); |
| | 866 | } |
| | 867 | } |
| | 868 | break; |
| | 869 | case 0x24: case 0x25: /* subi */ |
| | 870 | gr[RD] = |
| | 871 | gr[RD] - (IMM5 + 1); |
| | 872 | break; |
| | 873 | case 0x26: case 0x27: /* illegal */ |
| | 874 | ILLEGAL (); |
| | 875 | break; |
| | 876 | case 0x28: case 0x29: /* rsubi */ |
| | 877 | gr[RD] = |
| | 878 | IMM5 - gr[RD]; |
| | 879 | break; |
| | 880 | case 0x2A: case 0x2B: /* cmpnei */ |
| | 881 | if (gr[RD] != IMM5) |
| | 882 | { |
| | 883 | SET_C(); |
| | 884 | } |
| | 885 | else |
| | 886 | { |
| | 887 | CLR_C(); |
| | 888 | } |
| | 889 | break; |
| | 890 | |
| | 891 | case 0x2C: case 0x2D: /* bmaski, divu */ |
| | 892 | { |
| | 893 | unsigned imm = IMM5; |
| | 894 | |
| | 895 | if (imm == 1) |
| | 896 | { |
| | 897 | int exe; |
| | 898 | int rxnlz, r1nlz; |
| | 899 | unsigned int rx, r1; |
| | 900 | |
| | 901 | rx = gr[RD]; |
| | 902 | r1 = gr[1]; |
| | 903 | exe = 0; |
| | 904 | |
| | 905 | /* unsigned divide */ |
| | 906 | gr[RD] = (word) ((unsigned int) gr[RD] / (unsigned int)gr[1] ); |
| | 907 | |
| | 908 | /* compute bonus_cycles for divu */ |
| | 909 | for (r1nlz = 0; ((r1 & 0x80000000) == 0) && (r1nlz < 32); r1nlz ++) |
| | 910 | r1 = r1 << 1; |
| | 911 | |
| | 912 | for (rxnlz = 0; ((rx & 0x80000000) == 0) && (rxnlz < 32); rxnlz ++) |
| | 913 | rx = rx << 1; |
| | 914 | |
| | 915 | if (r1nlz < rxnlz) |
| | 916 | exe += 4; |
| | 917 | else |
| | 918 | exe += 5 + r1nlz - rxnlz; |
| | 919 | |
| | 920 | if (exe >= (2 * memcycles - 1)) |
| | 921 | { |
| | 922 | bonus_cycles += exe - (2 * memcycles) + 1; |
| | 923 | } |
| | 924 | } |
| | 925 | else if (imm == 0 || imm >= 8) |
| | 926 | { |
| | 927 | /* bmaski */ |
| | 928 | if (imm == 0) |
| | 929 | gr[RD] = -1; |
| | 930 | else |
| | 931 | gr[RD] = (1 << imm) - 1; |
| | 932 | } |
| | 933 | else |
| | 934 | { |
| | 935 | /* illegal */ |
| | 936 | ILLEGAL (); |
| | 937 | } |
| | 938 | } |
| | 939 | break; |
| | 940 | case 0x2E: case 0x2F: /* andi */ |
| | 941 | gr[RD] = gr[RD] & IMM5; |
| | 942 | break; |
| | 943 | case 0x30: case 0x31: /* bclri */ |
| | 944 | gr[RD] = gr[RD] & ~(1<<IMM5); |
| | 945 | break; |
| | 946 | case 0x32: case 0x33: /* bgeni, divs */ |
| | 947 | { |
| | 948 | unsigned imm = IMM5; |
| | 949 | if (imm == 1) |
| | 950 | { |
| | 951 | int exe,sc; |
| | 952 | int rxnlz, r1nlz; |
| | 953 | signed int rx, r1; |
| | 954 | |
| | 955 | /* compute bonus_cycles for divu */ |
| | 956 | rx = gr[RD]; |
| | 957 | r1 = gr[1]; |
| | 958 | exe = 0; |
| | 959 | |
| | 960 | if (((rx < 0) && (r1 > 0)) || ((rx >= 0) && (r1 < 0))) |
| | 961 | sc = 1; |
| | 962 | else |
| | 963 | sc = 0; |
| | 964 | |
| | 965 | rx = abs (rx); |
| | 966 | r1 = abs (r1); |
| | 967 | |
| | 968 | /* signed divide, general registers are of type int, so / op is OK */ |
| | 969 | gr[RD] = gr[RD] / gr[1]; |
| | 970 | |
| | 971 | for (r1nlz = 0; ((r1 & 0x80000000) == 0) && (r1nlz < 32) ; r1nlz ++ ) |
| | 972 | r1 = r1 << 1; |
| | 973 | |
| | 974 | for (rxnlz = 0; ((rx & 0x80000000) == 0) && (rxnlz < 32) ; rxnlz ++ ) |
| | 975 | rx = rx << 1; |
| | 976 | |
| | 977 | if (r1nlz < rxnlz) |
| | 978 | exe += 5; |
| | 979 | else |
| | 980 | exe += 6 + r1nlz - rxnlz + sc; |
| | 981 | |
| | 982 | if (exe >= (2 * memcycles - 1)) |
| | 983 | { |
| | 984 | bonus_cycles += exe - (2 * memcycles) + 1; |
| | 985 | } |
| | 986 | } |
| | 987 | else if (imm >= 7) |
| | 988 | { |
| | 989 | /* bgeni */ |
| | 990 | gr[RD] = (1 << IMM5); |
| | 991 | } |
| | 992 | else |
| | 993 | { |
| | 994 | /* illegal */ |
| | 995 | ILLEGAL (); |
| | 996 | } |
| | 997 | break; |
| | 998 | } |
| | 999 | case 0x34: case 0x35: /* bseti */ |
| | 1000 | gr[RD] = gr[RD] | (1 << IMM5); |
| | 1001 | break; |
| | 1002 | case 0x36: case 0x37: /* btsti */ |
| | 1003 | NEW_C (gr[RD] >> IMM5); |
| | 1004 | break; |
| | 1005 | case 0x38: case 0x39: /* xsr, rotli */ |
| | 1006 | { |
| | 1007 | unsigned imm = IMM5; |
| | 1008 | unsigned long tmp = gr[RD]; |
| | 1009 | if (imm == 0) |
| | 1010 | { |
| | 1011 | word cbit; |
| | 1012 | cbit = C_VALUE(); |
| | 1013 | NEW_C (tmp); |
| | 1014 | gr[RD] = (cbit << 31) | (tmp >> 1); |
| | 1015 | } |
| | 1016 | else |
| | 1017 | gr[RD] = (tmp << imm) | (tmp >> (32 - imm)); |
| | 1018 | } |
| | 1019 | break; |
| | 1020 | case 0x3A: case 0x3B: /* asrc, asri */ |
| | 1021 | { |
| | 1022 | unsigned imm = IMM5; |
| | 1023 | long tmp = gr[RD]; |
| | 1024 | if (imm == 0) |
| | 1025 | { |
| | 1026 | NEW_C (tmp); |
| | 1027 | gr[RD] = tmp >> 1; |
| | 1028 | } |
| | 1029 | else |
| | 1030 | gr[RD] = tmp >> imm; |
| | 1031 | } |
| | 1032 | break; |
| | 1033 | case 0x3C: case 0x3D: /* lslc, lsli */ |
| | 1034 | { |
| | 1035 | unsigned imm = IMM5; |
| | 1036 | unsigned long tmp = gr[RD]; |
| | 1037 | if (imm == 0) |
| | 1038 | { |
| | 1039 | NEW_C (tmp >> 31); |
| | 1040 | gr[RD] = tmp << 1; |
| | 1041 | } |
| | 1042 | else |
| | 1043 | gr[RD] = tmp << imm; |
| | 1044 | } |
| | 1045 | break; |
| | 1046 | case 0x3E: case 0x3F: /* lsrc, lsri */ |
| | 1047 | { |
| | 1048 | unsigned imm = IMM5; |
| | 1049 | unsigned long tmp = gr[RD]; |
| | 1050 | if (imm == 0) |
| | 1051 | { |
| | 1052 | NEW_C (tmp); |
| | 1053 | gr[RD] = tmp >> 1; |
| | 1054 | } |
| | 1055 | else |
| | 1056 | gr[RD] = tmp >> imm; |
| | 1057 | } |
| | 1058 | break; |
| | 1059 | case 0x40: case 0x41: case 0x42: case 0x43: |
| | 1060 | case 0x44: case 0x45: case 0x46: case 0x47: |
| | 1061 | case 0x48: case 0x49: case 0x4A: case 0x4B: |
| | 1062 | case 0x4C: case 0x4D: case 0x4E: case 0x4F: |
| | 1063 | ILLEGAL (); |
| | 1064 | break; |
| | 1065 | case 0x50: |
| | 1066 | util (sd, cpu, inst & 0xFF); |
| | 1067 | break; |
| | 1068 | case 0x51: case 0x52: case 0x53: |
| | 1069 | case 0x54: case 0x55: case 0x56: case 0x57: |
| | 1070 | case 0x58: case 0x59: case 0x5A: case 0x5B: |
| | 1071 | case 0x5C: case 0x5D: case 0x5E: case 0x5F: |
| | 1072 | ILLEGAL (); |
| | 1073 | break; |
| | 1074 | case 0x60: case 0x61: case 0x62: case 0x63: /* movi */ |
| | 1075 | case 0x64: case 0x65: case 0x66: case 0x67: |
| | 1076 | gr[RD] = (inst >> 4) & 0x7F; |
| | 1077 | break; |
| | 1078 | case 0x68: case 0x69: case 0x6A: case 0x6B: |
| | 1079 | case 0x6C: case 0x6D: case 0x6E: case 0x6F: /* illegal */ |
| | 1080 | ILLEGAL (); |
| | 1081 | break; |
| | 1082 | case 0x71: case 0x72: case 0x73: |
| | 1083 | case 0x74: case 0x75: case 0x76: case 0x77: |
| | 1084 | case 0x78: case 0x79: case 0x7A: case 0x7B: |
| | 1085 | case 0x7C: case 0x7D: case 0x7E: /* lrw */ |
| | 1086 | gr[RX] = rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); |
| | 1087 | if (tracing) |
| | 1088 | fprintf (stderr, "LRW of 0x%x from 0x%lx to reg %d", |
| | 1089 | rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC), |
| | 1090 | (pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC, RX); |
| | 1091 | memops++; |
| | 1092 | break; |
| | 1093 | case 0x7F: /* jsri */ |
| | 1094 | gr[15] = pc; |
| | 1095 | if (tracing) |
| | 1096 | fprintf (stderr, |
| | 1097 | "func call: r2 = %lx r3 = %lx r4 = %lx r5 = %lx r6 = %lx r7 = %lx\n", |
| | 1098 | gr[2], gr[3], gr[4], gr[5], gr[6], gr[7]); |
| | 1099 | case 0x70: /* jmpi */ |
| | 1100 | pc = rlat ((pc + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); |
| | 1101 | memops++; |
| | 1102 | bonus_cycles++; |
| | 1103 | needfetch = 1; |
| | 1104 | break; |
| | 1105 | |
| | 1106 | case 0x80: case 0x81: case 0x82: case 0x83: |
| | 1107 | case 0x84: case 0x85: case 0x86: case 0x87: |
| | 1108 | case 0x88: case 0x89: case 0x8A: case 0x8B: |
| | 1109 | case 0x8C: case 0x8D: case 0x8E: case 0x8F: /* ld */ |
| | 1110 | gr[RX] = rlat (gr[RD] + ((inst >> 2) & 0x003C)); |
| | 1111 | if (tracing) |
| | 1112 | fprintf (stderr, "load reg %d from 0x%lx with 0x%lx", |
| | 1113 | RX, |
| | 1114 | gr[RD] + ((inst >> 2) & 0x003C), gr[RX]); |
| | 1115 | memops++; |
| | 1116 | break; |
| | 1117 | case 0x90: case 0x91: case 0x92: case 0x93: |
| | 1118 | case 0x94: case 0x95: case 0x96: case 0x97: |
| | 1119 | case 0x98: case 0x99: case 0x9A: case 0x9B: |
| | 1120 | case 0x9C: case 0x9D: case 0x9E: case 0x9F: /* st */ |
| | 1121 | wlat (gr[RD] + ((inst >> 2) & 0x003C), gr[RX]); |
| | 1122 | if (tracing) |
| | 1123 | fprintf (stderr, "store reg %d (containing 0x%lx) to 0x%lx", |
| | 1124 | RX, gr[RX], |
| | 1125 | gr[RD] + ((inst >> 2) & 0x003C)); |
| | 1126 | memops++; |
| | 1127 | break; |
| | 1128 | case 0xA0: case 0xA1: case 0xA2: case 0xA3: |
| | 1129 | case 0xA4: case 0xA5: case 0xA6: case 0xA7: |
| | 1130 | case 0xA8: case 0xA9: case 0xAA: case 0xAB: |
| | 1131 | case 0xAC: case 0xAD: case 0xAE: case 0xAF: /* ld.b */ |
| | 1132 | gr[RX] = rbat (gr[RD] + RS); |
| | 1133 | memops++; |
| | 1134 | break; |
| | 1135 | case 0xB0: case 0xB1: case 0xB2: case 0xB3: |
| | 1136 | case 0xB4: case 0xB5: case 0xB6: case 0xB7: |
| | 1137 | case 0xB8: case 0xB9: case 0xBA: case 0xBB: |
| | 1138 | case 0xBC: case 0xBD: case 0xBE: case 0xBF: /* st.b */ |
| | 1139 | wbat (gr[RD] + RS, gr[RX]); |
| | 1140 | memops++; |
| | 1141 | break; |
| | 1142 | case 0xC0: case 0xC1: case 0xC2: case 0xC3: |
| | 1143 | case 0xC4: case 0xC5: case 0xC6: case 0xC7: |
| | 1144 | case 0xC8: case 0xC9: case 0xCA: case 0xCB: |
| | 1145 | case 0xCC: case 0xCD: case 0xCE: case 0xCF: /* ld.h */ |
| | 1146 | gr[RX] = rhat (gr[RD] + ((inst >> 3) & 0x001E)); |
| | 1147 | memops++; |
| | 1148 | break; |
| | 1149 | case 0xD0: case 0xD1: case 0xD2: case 0xD3: |
| | 1150 | case 0xD4: case 0xD5: case 0xD6: case 0xD7: |
| | 1151 | case 0xD8: case 0xD9: case 0xDA: case 0xDB: |
| | 1152 | case 0xDC: case 0xDD: case 0xDE: case 0xDF: /* st.h */ |
| | 1153 | what (gr[RD] + ((inst >> 3) & 0x001E), gr[RX]); |
| | 1154 | memops++; |
| | 1155 | break; |
| | 1156 | case 0xE8: case 0xE9: case 0xEA: case 0xEB: |
| | 1157 | case 0xEC: case 0xED: case 0xEE: case 0xEF: /* bf */ |
| | 1158 | if (C_OFF()) |
| | 1159 | { |
| | 1160 | int disp; |
| | 1161 | disp = inst & 0x03FF; |
| | 1162 | if (inst & 0x0400) |
| | 1163 | disp |= 0xFFFFFC00; |
| | 1164 | pc += disp<<1; |
| | 1165 | bonus_cycles++; |
| | 1166 | needfetch = 1; |
| | 1167 | } |
| | 1168 | break; |
| | 1169 | case 0xE0: case 0xE1: case 0xE2: case 0xE3: |
| | 1170 | case 0xE4: case 0xE5: case 0xE6: case 0xE7: /* bt */ |
| | 1171 | if (C_ON()) |
| | 1172 | { |
| | 1173 | int disp; |
| | 1174 | disp = inst & 0x03FF; |
| | 1175 | if (inst & 0x0400) |
| | 1176 | disp |= 0xFFFFFC00; |
| | 1177 | pc += disp<<1; |
| | 1178 | bonus_cycles++; |
| | 1179 | needfetch = 1; |
| | 1180 | } |
| | 1181 | break; |
| | 1182 | |
| | 1183 | case 0xF8: case 0xF9: case 0xFA: case 0xFB: |
| | 1184 | case 0xFC: case 0xFD: case 0xFE: case 0xFF: /* bsr */ |
| | 1185 | gr[15] = pc; |
| | 1186 | case 0xF0: case 0xF1: case 0xF2: case 0xF3: |
| | 1187 | case 0xF4: case 0xF5: case 0xF6: case 0xF7: /* br */ |
| | 1188 | { |
| | 1189 | int disp; |
| | 1190 | disp = inst & 0x03FF; |
| | 1191 | if (inst & 0x0400) |
| | 1192 | disp |= 0xFFFFFC00; |
| | 1193 | pc += disp<<1; |
| | 1194 | bonus_cycles++; |
| | 1195 | needfetch = 1; |
| | 1196 | } |
| | 1197 | break; |
| | 1198 | |
| | 1199 | } |
| | 1200 | |
| | 1201 | if (tracing) |
| | 1202 | fprintf (stderr, "\n"); |
| | 1203 | |
| | 1204 | if (needfetch) |
| | 1205 | { |
| | 1206 | ibuf = rlat (pc & 0xFFFFFFFC); |
| | 1207 | needfetch = 0; |
| | 1208 | } |
| | 1209 | } |
| | 1210 | |
| | 1211 | /* Hide away the things we've cached while executing. */ |
| | 1212 | CPU_PC_SET (cpu, pc); |
| | 1213 | cpu->insts += insts; /* instructions done ... */ |
| | 1214 | cpu->cycles += insts; /* and each takes a cycle */ |
| | 1215 | cpu->cycles += bonus_cycles; /* and extra cycles for branches */ |
| | 1216 | cpu->cycles += memops * memcycles; /* and memop cycle delays */ |
| | 1217 | } |
| | 1218 | |
| | 1219 | void |
| | 1220 | sim_engine_run (SIM_DESC sd, |
| | 1221 | int next_cpu_nr, /* ignore */ |
| | 1222 | int nr_cpus, /* ignore */ |
| | 1223 | int siggnal) /* ignore */ |
| | 1224 | { |
| | 1225 | sim_cpu *cpu; |
| | 1226 | |
| | 1227 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
| | 1228 | |
| | 1229 | cpu = STATE_CPU (sd, 0); |
| | 1230 | |
| | 1231 | while (1) |
| | 1232 | { |
| | 1233 | step_once (sd, cpu); |
| | 1234 | if (sim_events_tick (sd)) |
| | 1235 | sim_events_process (sd); |
| | 1236 | } |
| | 1237 | } |
| | 1238 | |
| | 1239 | static int |
| | 1240 | mcore_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) |
| | 1241 | { |
| | 1242 | if (rn < NUM_MCORE_REGS && rn >= 0) |
| | 1243 | { |
| | 1244 | if (length == 4) |
| | 1245 | { |
| | 1246 | long ival; |
| | 1247 | |
| | 1248 | /* misalignment safe */ |
| | 1249 | ival = mcore_extract_unsigned_integer (memory, 4); |
| | 1250 | cpu->asints[rn] = ival; |
| | 1251 | } |
| | 1252 | |
| | 1253 | return 4; |
| | 1254 | } |
| | 1255 | else |
| | 1256 | return 0; |
| | 1257 | } |
| | 1258 | |
| | 1259 | static int |
| | 1260 | mcore_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) |
| | 1261 | { |
| | 1262 | if (rn < NUM_MCORE_REGS && rn >= 0) |
| | 1263 | { |
| | 1264 | if (length == 4) |
| | 1265 | { |
| | 1266 | long ival = cpu->asints[rn]; |
| | 1267 | |
| | 1268 | /* misalignment-safe */ |
| | 1269 | mcore_store_unsigned_integer (memory, 4, ival); |
| | 1270 | } |
| | 1271 | |
| | 1272 | return 4; |
| | 1273 | } |
| | 1274 | else |
| | 1275 | return 0; |
| | 1276 | } |
| | 1277 | |
| | 1278 | void |
| | 1279 | sim_info (SIM_DESC sd, int verbose) |
| | 1280 | { |
| | 1281 | SIM_CPU *cpu = STATE_CPU (sd, 0); |
| | 1282 | #ifdef WATCHFUNCTIONS |
| | 1283 | int w, wcyc; |
| | 1284 | #endif |
| | 1285 | double virttime = cpu->cycles / 36.0e6; |
| | 1286 | host_callback *callback = STATE_CALLBACK (sd); |
| | 1287 | |
| | 1288 | callback->printf_filtered (callback, "\n\n# instructions executed %10d\n", |
| | 1289 | cpu->insts); |
| | 1290 | callback->printf_filtered (callback, "# cycles %10d\n", |
| | 1291 | cpu->cycles); |
| | 1292 | callback->printf_filtered (callback, "# pipeline stalls %10d\n", |
| | 1293 | cpu->stalls); |
| | 1294 | callback->printf_filtered (callback, "# virtual time taken %10.4f\n", |
| | 1295 | virttime); |
| | 1296 | |
| | 1297 | #ifdef WATCHFUNCTIONS |
| | 1298 | callback->printf_filtered (callback, "\nNumber of watched functions: %d\n", |
| | 1299 | ENDWL); |
| | 1300 | |
| | 1301 | wcyc = 0; |
| | 1302 | |
| | 1303 | for (w = 1; w <= ENDWL; w++) |
| | 1304 | { |
| | 1305 | callback->printf_filtered (callback, "WL = %s %8x\n",WLstr[w],WL[w]); |
| | 1306 | callback->printf_filtered (callback, " calls = %d, cycles = %d\n", |
| | 1307 | WLcnts[w],WLcyc[w]); |
| | 1308 | |
| | 1309 | if (WLcnts[w] != 0) |
| | 1310 | callback->printf_filtered (callback, |
| | 1311 | " maxcpc = %d, mincpc = %d, avecpc = %d\n", |
| | 1312 | WLmax[w],WLmin[w],WLcyc[w]/WLcnts[w]); |
| | 1313 | wcyc += WLcyc[w]; |
| | 1314 | } |
| | 1315 | |
| | 1316 | callback->printf_filtered (callback, |
| | 1317 | "Total cycles for watched functions: %d\n",wcyc); |
| | 1318 | #endif |
| | 1319 | } |
| | 1320 | |
| | 1321 | static sim_cia |
| | 1322 | mcore_pc_get (sim_cpu *cpu) |
| | 1323 | { |
| | 1324 | return cpu->regs.pc; |
| | 1325 | } |
| | 1326 | |
| | 1327 | static void |
| | 1328 | mcore_pc_set (sim_cpu *cpu, sim_cia pc) |
| | 1329 | { |
| | 1330 | cpu->regs.pc = pc; |
| | 1331 | } |
| | 1332 | |
| | 1333 | static void |
| | 1334 | free_state (SIM_DESC sd) |
| | 1335 | { |
| | 1336 | if (STATE_MODULES (sd) != NULL) |
| | 1337 | sim_module_uninstall (sd); |
| | 1338 | sim_cpu_free_all (sd); |
| | 1339 | sim_state_free (sd); |
| | 1340 | } |
| | 1341 | |
| | 1342 | SIM_DESC |
| | 1343 | sim_open (SIM_OPEN_KIND kind, host_callback *cb, |
| | 1344 | struct bfd *abfd, char * const *argv) |
| | 1345 | { |
| | 1346 | int i; |
| | 1347 | SIM_DESC sd = sim_state_alloc (kind, cb); |
| | 1348 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
| | 1349 | |
| | 1350 | /* The cpu data is kept in a separately allocated chunk of memory. */ |
| | 1351 | if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK) |
| | 1352 | { |
| | 1353 | free_state (sd); |
| | 1354 | return 0; |
| | 1355 | } |
| | 1356 | |
| | 1357 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
| | 1358 | { |
| | 1359 | free_state (sd); |
| | 1360 | return 0; |
| | 1361 | } |
| | 1362 | |
| | 1363 | /* The parser will print an error message for us, so we silently return. */ |
| | 1364 | if (sim_parse_args (sd, argv) != SIM_RC_OK) |
| | 1365 | { |
| | 1366 | free_state (sd); |
| | 1367 | return 0; |
| | 1368 | } |
| | 1369 | |
| | 1370 | /* Check for/establish the a reference program image. */ |
| | 1371 | if (sim_analyze_program (sd, |
| | 1372 | (STATE_PROG_ARGV (sd) != NULL |
| | 1373 | ? *STATE_PROG_ARGV (sd) |
| | 1374 | : NULL), abfd) != SIM_RC_OK) |
| | 1375 | { |
| | 1376 | free_state (sd); |
| | 1377 | return 0; |
| | 1378 | } |
| | 1379 | |
| | 1380 | /* Configure/verify the target byte order and other runtime |
| | 1381 | configuration options. */ |
| | 1382 | if (sim_config (sd) != SIM_RC_OK) |
| | 1383 | { |
| | 1384 | sim_module_uninstall (sd); |
| | 1385 | return 0; |
| | 1386 | } |
| | 1387 | |
| | 1388 | if (sim_post_argv_init (sd) != SIM_RC_OK) |
| | 1389 | { |
| | 1390 | /* Uninstall the modules to avoid memory leaks, |
| | 1391 | file descriptor leaks, etc. */ |
| | 1392 | sim_module_uninstall (sd); |
| | 1393 | return 0; |
| | 1394 | } |
| | 1395 | |
| | 1396 | /* CPU specific initialization. */ |
| | 1397 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) |
| | 1398 | { |
| | 1399 | SIM_CPU *cpu = STATE_CPU (sd, i); |
| | 1400 | |
| | 1401 | CPU_REG_FETCH (cpu) = mcore_reg_fetch; |
| | 1402 | CPU_REG_STORE (cpu) = mcore_reg_store; |
| | 1403 | CPU_PC_FETCH (cpu) = mcore_pc_get; |
| | 1404 | CPU_PC_STORE (cpu) = mcore_pc_set; |
| | 1405 | |
| | 1406 | set_initial_gprs (cpu); /* Reset the GPR registers. */ |
| | 1407 | } |
| | 1408 | |
| | 1409 | /* Default to a 8 Mbyte (== 2^23) memory space. */ |
| | 1410 | sim_do_commandf (sd, "memory-size %#x", DEFAULT_MEMORY_SIZE); |
| | 1411 | |
| | 1412 | return sd; |
| | 1413 | } |
| | 1414 | |
| | 1415 | SIM_RC |
| | 1416 | sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, |
| | 1417 | char * const *argv, char * const *env) |
| | 1418 | { |
| | 1419 | SIM_CPU *cpu = STATE_CPU (sd, 0); |
| | 1420 | char * const *avp; |
| | 1421 | int nargs = 0; |
| | 1422 | int nenv = 0; |
| | 1423 | int s_length; |
| | 1424 | int l; |
| | 1425 | unsigned long strings; |
| | 1426 | unsigned long pointers; |
| | 1427 | unsigned long hi_stack; |
| | 1428 | |
| | 1429 | |
| | 1430 | /* Set the initial register set. */ |
| | 1431 | set_initial_gprs (cpu); |
| | 1432 | |
| | 1433 | hi_stack = DEFAULT_MEMORY_SIZE - 4; |
| | 1434 | CPU_PC_SET (cpu, bfd_get_start_address (prog_bfd)); |
| | 1435 | |
| | 1436 | /* Calculate the argument and environment strings. */ |
| | 1437 | s_length = 0; |
| | 1438 | nargs = 0; |
| | 1439 | avp = argv; |
| | 1440 | while (avp && *avp) |
| | 1441 | { |
| | 1442 | l = strlen (*avp) + 1; /* include the null */ |
| | 1443 | s_length += (l + 3) & ~3; /* make it a 4 byte boundary */ |
| | 1444 | nargs++; avp++; |
| | 1445 | } |
| | 1446 | |
| | 1447 | nenv = 0; |
| | 1448 | avp = env; |
| | 1449 | while (avp && *avp) |
| | 1450 | { |
| | 1451 | l = strlen (*avp) + 1; /* include the null */ |
| | 1452 | s_length += (l + 3) & ~ 3;/* make it a 4 byte boundary */ |
| | 1453 | nenv++; avp++; |
| | 1454 | } |
| | 1455 | |
| | 1456 | /* Claim some memory for the pointers and strings. */ |
| | 1457 | pointers = hi_stack - sizeof(word) * (nenv+1+nargs+1); |
| | 1458 | pointers &= ~3; /* must be 4-byte aligned */ |
| | 1459 | gr[0] = pointers; |
| | 1460 | |
| | 1461 | strings = gr[0] - s_length; |
| | 1462 | strings &= ~3; /* want to make it 4-byte aligned */ |
| | 1463 | gr[0] = strings; |
| | 1464 | /* dac fix, the stack address must be 8-byte aligned! */ |
| | 1465 | gr[0] = gr[0] - gr[0] % 8; |
| | 1466 | |
| | 1467 | /* Loop through the arguments and fill them in. */ |
| | 1468 | gr[PARM1] = nargs; |
| | 1469 | if (nargs == 0) |
| | 1470 | { |
| | 1471 | /* No strings to fill in. */ |
| | 1472 | gr[PARM2] = 0; |
| | 1473 | } |
| | 1474 | else |
| | 1475 | { |
| | 1476 | gr[PARM2] = pointers; |
| | 1477 | avp = argv; |
| | 1478 | while (avp && *avp) |
| | 1479 | { |
| | 1480 | /* Save where we're putting it. */ |
| | 1481 | wlat (pointers, strings); |
| | 1482 | |
| | 1483 | /* Copy the string. */ |
| | 1484 | l = strlen (* avp) + 1; |
| | 1485 | sim_core_write_buffer (sd, cpu, write_map, *avp, strings, l); |
| | 1486 | |
| | 1487 | /* Bump the pointers. */ |
| | 1488 | avp++; |
| | 1489 | pointers += 4; |
| | 1490 | strings += l+1; |
| | 1491 | } |
| | 1492 | |
| | 1493 | /* A null to finish the list. */ |
| | 1494 | wlat (pointers, 0); |
| | 1495 | pointers += 4; |
| | 1496 | } |
| | 1497 | |
| | 1498 | /* Now do the environment pointers. */ |
| | 1499 | if (nenv == 0) |
| | 1500 | { |
| | 1501 | /* No strings to fill in. */ |
| | 1502 | gr[PARM3] = 0; |
| | 1503 | } |
| | 1504 | else |
| | 1505 | { |
| | 1506 | gr[PARM3] = pointers; |
| | 1507 | avp = env; |
| | 1508 | |
| | 1509 | while (avp && *avp) |
| | 1510 | { |
| | 1511 | /* Save where we're putting it. */ |
| | 1512 | wlat (pointers, strings); |
| | 1513 | |
| | 1514 | /* Copy the string. */ |
| | 1515 | l = strlen (* avp) + 1; |
| | 1516 | sim_core_write_buffer (sd, cpu, write_map, *avp, strings, l); |
| | 1517 | |
| | 1518 | /* Bump the pointers. */ |
| | 1519 | avp++; |
| | 1520 | pointers += 4; |
| | 1521 | strings += l+1; |
| | 1522 | } |
| | 1523 | |
| | 1524 | /* A null to finish the list. */ |
| | 1525 | wlat (pointers, 0); |
| | 1526 | pointers += 4; |
| | 1527 | } |
| | 1528 | |
| | 1529 | return SIM_RC_OK; |
| | 1530 | } |
projects / thirdparty / binutils-gdb.git / blame_incremental