1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2019 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
57 typedef arelent, howto manager, Relocations, Relocations
62 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. Note - the value 2 is used so that it
69 . will not be mistaken for the boolean TRUE or FALSE values. *}
72 . {* The relocation was performed, but there was an overflow. *}
75 . {* The address to relocate was not within the section supplied. *}
76 . bfd_reloc_outofrange,
78 . {* Used by special functions. *}
81 . {* Unsupported relocation size requested. *}
82 . bfd_reloc_notsupported,
87 . {* The symbol to relocate against was undefined. *}
88 . bfd_reloc_undefined,
90 . {* The relocation was performed, but may not be ok. If this type is
91 . returned, the error_message argument to bfd_perform_relocation
95 . bfd_reloc_status_type;
97 .typedef const struct reloc_howto_struct reloc_howto_type;
99 .typedef struct reloc_cache_entry
101 . {* A pointer into the canonical table of pointers. *}
102 . struct bfd_symbol **sym_ptr_ptr;
104 . {* offset in section. *}
105 . bfd_size_type address;
107 . {* addend for relocation value. *}
110 . {* Pointer to how to perform the required relocation. *}
111 . reloc_howto_type *howto;
121 Here is a description of each of the fields within an <<arelent>>:
125 The symbol table pointer points to a pointer to the symbol
126 associated with the relocation request. It is the pointer
127 into the table returned by the back end's
128 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
129 referenced through a pointer to a pointer so that tools like
130 the linker can fix up all the symbols of the same name by
131 modifying only one pointer. The relocation routine looks in
132 the symbol and uses the base of the section the symbol is
133 attached to and the value of the symbol as the initial
134 relocation offset. If the symbol pointer is zero, then the
135 section provided is looked up.
139 The <<address>> field gives the offset in bytes from the base of
140 the section data which owns the relocation record to the first
141 byte of relocatable information. The actual data relocated
142 will be relative to this point; for example, a relocation
143 type which modifies the bottom two bytes of a four byte word
144 would not touch the first byte pointed to in a big endian
149 The <<addend>> is a value provided by the back end to be added (!)
150 to the relocation offset. Its interpretation is dependent upon
151 the howto. For example, on the 68k the code:
156 | return foo[0x12345678];
159 Could be compiled into:
162 | moveb @@#12345678,d0
167 This could create a reloc pointing to <<foo>>, but leave the
168 offset in the data, something like:
170 |RELOCATION RECORDS FOR [.text]:
174 |00000000 4e56 fffc ; linkw fp,#-4
175 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
176 |0000000a 49c0 ; extbl d0
177 |0000000c 4e5e ; unlk fp
180 Using coff and an 88k, some instructions don't have enough
181 space in them to represent the full address range, and
182 pointers have to be loaded in two parts. So you'd get something like:
184 | or.u r13,r0,hi16(_foo+0x12345678)
185 | ld.b r2,r13,lo16(_foo+0x12345678)
188 This should create two relocs, both pointing to <<_foo>>, and with
189 0x12340000 in their addend field. The data would consist of:
191 |RELOCATION RECORDS FOR [.text]:
193 |00000002 HVRT16 _foo+0x12340000
194 |00000006 LVRT16 _foo+0x12340000
196 |00000000 5da05678 ; or.u r13,r0,0x5678
197 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
198 |00000008 f400c001 ; jmp r1
200 The relocation routine digs out the value from the data, adds
201 it to the addend to get the original offset, and then adds the
202 value of <<_foo>>. Note that all 32 bits have to be kept around
203 somewhere, to cope with carry from bit 15 to bit 16.
205 One further example is the sparc and the a.out format. The
206 sparc has a similar problem to the 88k, in that some
207 instructions don't have room for an entire offset, but on the
208 sparc the parts are created in odd sized lumps. The designers of
209 the a.out format chose to not use the data within the section
210 for storing part of the offset; all the offset is kept within
211 the reloc. Anything in the data should be ignored.
214 | sethi %hi(_foo+0x12345678),%g2
215 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
219 Both relocs contain a pointer to <<foo>>, and the offsets
222 |RELOCATION RECORDS FOR [.text]:
224 |00000004 HI22 _foo+0x12345678
225 |00000008 LO10 _foo+0x12345678
227 |00000000 9de3bf90 ; save %sp,-112,%sp
228 |00000004 05000000 ; sethi %hi(_foo+0),%g2
229 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
230 |0000000c 81c7e008 ; ret
231 |00000010 81e80000 ; restore
235 The <<howto>> field can be imagined as a
236 relocation instruction. It is a pointer to a structure which
237 contains information on what to do with all of the other
238 information in the reloc record and data section. A back end
239 would normally have a relocation instruction set and turn
240 relocations into pointers to the correct structure on input -
241 but it would be possible to create each howto field on demand.
247 <<enum complain_overflow>>
249 Indicates what sort of overflow checking should be done when
250 performing a relocation.
254 .enum complain_overflow
256 . {* Do not complain on overflow. *}
257 . complain_overflow_dont,
259 . {* Complain if the value overflows when considered as a signed
260 . number one bit larger than the field. ie. A bitfield of N bits
261 . is allowed to represent -2**n to 2**n-1. *}
262 . complain_overflow_bitfield,
264 . {* Complain if the value overflows when considered as a signed
266 . complain_overflow_signed,
268 . {* Complain if the value overflows when considered as an
269 . unsigned number. *}
270 . complain_overflow_unsigned
279 The <<reloc_howto_type>> is a structure which contains all the
280 information that libbfd needs to know to tie up a back end's data.
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's idea of
287 . an external reloc number is stored in this field. *}
290 . {* The encoded size of the item to be relocated. This is *not* a
291 . power-of-two measure. Use bfd_get_reloc_size to find the size
292 . of the item in bytes. *}
293 . unsigned int size:3;
295 . {* The number of bits in the field to be relocated. This is used
296 . when doing overflow checking. *}
297 . unsigned int bitsize:7;
299 . {* The value the final relocation is shifted right by. This drops
300 . unwanted data from the relocation. *}
301 . unsigned int rightshift:6;
303 . {* The bit position of the reloc value in the destination.
304 . The relocated value is left shifted by this amount. *}
305 . unsigned int bitpos:6;
307 . {* What type of overflow error should be checked for when
309 . ENUM_BITFIELD (complain_overflow) complain_on_overflow:2;
311 . {* The relocation value should be negated before applying. *}
312 . unsigned int negate:1;
314 . {* The relocation is relative to the item being relocated. *}
315 . unsigned int pc_relative:1;
317 . {* Some formats record a relocation addend in the section contents
318 . rather than with the relocation. For ELF formats this is the
319 . distinction between USE_REL and USE_RELA (though the code checks
320 . for USE_REL == 1/0). The value of this field is TRUE if the
321 . addend is recorded with the section contents; when performing a
322 . partial link (ld -r) the section contents (the data) will be
323 . modified. The value of this field is FALSE if addends are
324 . recorded with the relocation (in arelent.addend); when performing
325 . a partial link the relocation will be modified.
326 . All relocations for all ELF USE_RELA targets should set this field
327 . to FALSE (values of TRUE should be looked on with suspicion).
328 . However, the converse is not true: not all relocations of all ELF
329 . USE_REL targets set this field to TRUE. Why this is so is peculiar
330 . to each particular target. For relocs that aren't used in partial
331 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
332 . unsigned int partial_inplace:1;
334 . {* When some formats create PC relative instructions, they leave
335 . the value of the pc of the place being relocated in the offset
336 . slot of the instruction, so that a PC relative relocation can
337 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
338 . Some formats leave the displacement part of an instruction
339 . empty (e.g., ELF); this flag signals the fact. *}
340 . unsigned int pcrel_offset:1;
342 . {* src_mask selects the part of the instruction (or data) to be used
343 . in the relocation sum. If the target relocations don't have an
344 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
345 . dst_mask to extract the addend from the section contents. If
346 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
347 . field should normally be zero. Non-zero values for ELF USE_RELA
348 . targets should be viewed with suspicion as normally the value in
349 . the dst_mask part of the section contents should be ignored. *}
352 . {* dst_mask selects which parts of the instruction (or data) are
353 . replaced with a relocated value. *}
356 . {* If this field is non null, then the supplied function is
357 . called rather than the normal function. This allows really
358 . strange relocation methods to be accommodated. *}
359 . bfd_reloc_status_type (*special_function)
360 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
363 . {* The textual name of the relocation type. *}
374 The HOWTO macro fills in a reloc_howto_type (a typedef for
375 const struct reloc_howto_struct).
377 .#define HOWTO(type, right, size, bits, pcrel, left, ovf, func, name, \
378 . inplace, src_mask, dst_mask, pcrel_off) \
379 . { (unsigned) type, size < 0 ? -size : size, bits, right, left, ovf, \
380 . size < 0, pcrel, inplace, pcrel_off, src_mask, dst_mask, func, name }
383 This is used to fill in an empty howto entry in an array.
385 .#define EMPTY_HOWTO(C) \
386 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
387 . NULL, FALSE, 0, 0, FALSE)
396 unsigned int bfd_get_reloc_size (reloc_howto_type *);
399 For a reloc_howto_type that operates on a fixed number of bytes,
400 this returns the number of bytes operated on.
404 bfd_get_reloc_size (reloc_howto_type
*howto
)
424 How relocs are tied together in an <<asection>>:
426 .typedef struct relent_chain
429 . struct relent_chain *next;
435 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
436 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
443 bfd_reloc_status_type bfd_check_overflow
444 (enum complain_overflow how,
445 unsigned int bitsize,
446 unsigned int rightshift,
447 unsigned int addrsize,
451 Perform overflow checking on @var{relocation} which has
452 @var{bitsize} significant bits and will be shifted right by
453 @var{rightshift} bits, on a machine with addresses containing
454 @var{addrsize} significant bits. The result is either of
455 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
459 bfd_reloc_status_type
460 bfd_check_overflow (enum complain_overflow how
,
461 unsigned int bitsize
,
462 unsigned int rightshift
,
463 unsigned int addrsize
,
466 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
467 bfd_reloc_status_type flag
= bfd_reloc_ok
;
469 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
470 we'll be permissive: extra bits in the field mask will
471 automatically extend the address mask for purposes of the
473 fieldmask
= N_ONES (bitsize
);
474 signmask
= ~fieldmask
;
475 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
476 a
= (relocation
& addrmask
) >> rightshift
;
480 case complain_overflow_dont
:
483 case complain_overflow_signed
:
484 /* If any sign bits are set, all sign bits must be set. That
485 is, A must be a valid negative address after shifting. */
486 signmask
= ~ (fieldmask
>> 1);
489 case complain_overflow_bitfield
:
490 /* Bitfields are sometimes signed, sometimes unsigned. We
491 explicitly allow an address wrap too, which means a bitfield
492 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
493 if the value has some, but not all, bits set outside the
496 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
497 flag
= bfd_reloc_overflow
;
500 case complain_overflow_unsigned
:
501 /* We have an overflow if the address does not fit in the field. */
502 if ((a
& signmask
) != 0)
503 flag
= bfd_reloc_overflow
;
515 bfd_reloc_offset_in_range
518 bfd_boolean bfd_reloc_offset_in_range
519 (reloc_howto_type *howto,
522 bfd_size_type offset);
525 Returns TRUE if the reloc described by @var{HOWTO} can be
526 applied at @var{OFFSET} octets in @var{SECTION}.
530 /* HOWTO describes a relocation, at offset OCTET. Return whether the
531 relocation field is within SECTION of ABFD. */
534 bfd_reloc_offset_in_range (reloc_howto_type
*howto
,
539 bfd_size_type octet_end
= bfd_get_section_limit_octets (abfd
, section
);
540 bfd_size_type reloc_size
= bfd_get_reloc_size (howto
);
542 /* The reloc field must be contained entirely within the section.
543 Allow zero length fields (marker relocs or NONE relocs where no
544 relocation will be performed) at the end of the section. */
545 return octet
<= octet_end
&& octet
+ reloc_size
<= octet_end
;
548 /* Read and return the section contents at DATA converted to a host
549 integer (bfd_vma). The number of bytes read is given by the HOWTO. */
552 read_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
)
557 return bfd_get_8 (abfd
, data
);
560 return bfd_get_16 (abfd
, data
);
563 return bfd_get_32 (abfd
, data
);
570 return bfd_get_64 (abfd
, data
);
574 return bfd_get_24 (abfd
, data
);
582 /* Convert VAL to target format and write to DATA. The number of
583 bytes written is given by the HOWTO. */
586 write_reloc (bfd
*abfd
, bfd_vma val
, bfd_byte
*data
, reloc_howto_type
*howto
)
591 bfd_put_8 (abfd
, val
, data
);
595 bfd_put_16 (abfd
, val
, data
);
599 bfd_put_32 (abfd
, val
, data
);
607 bfd_put_64 (abfd
, val
, data
);
612 bfd_put_24 (abfd
, val
, data
);
620 /* Apply RELOCATION value to target bytes at DATA, according to
624 apply_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
,
627 bfd_vma val
= read_reloc (abfd
, data
, howto
);
630 relocation
= -relocation
;
632 val
= ((val
& ~howto
->dst_mask
)
633 | (((val
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
635 write_reloc (abfd
, val
, data
, howto
);
640 bfd_perform_relocation
643 bfd_reloc_status_type bfd_perform_relocation
645 arelent *reloc_entry,
647 asection *input_section,
649 char **error_message);
652 If @var{output_bfd} is supplied to this function, the
653 generated image will be relocatable; the relocations are
654 copied to the output file after they have been changed to
655 reflect the new state of the world. There are two ways of
656 reflecting the results of partial linkage in an output file:
657 by modifying the output data in place, and by modifying the
658 relocation record. Some native formats (e.g., basic a.out and
659 basic coff) have no way of specifying an addend in the
660 relocation type, so the addend has to go in the output data.
661 This is no big deal since in these formats the output data
662 slot will always be big enough for the addend. Complex reloc
663 types with addends were invented to solve just this problem.
664 The @var{error_message} argument is set to an error message if
665 this return @code{bfd_reloc_dangerous}.
669 bfd_reloc_status_type
670 bfd_perform_relocation (bfd
*abfd
,
671 arelent
*reloc_entry
,
673 asection
*input_section
,
675 char **error_message
)
678 bfd_reloc_status_type flag
= bfd_reloc_ok
;
679 bfd_size_type octets
;
680 bfd_vma output_base
= 0;
681 reloc_howto_type
*howto
= reloc_entry
->howto
;
682 asection
*reloc_target_output_section
;
685 symbol
= *(reloc_entry
->sym_ptr_ptr
);
687 /* If we are not producing relocatable output, return an error if
688 the symbol is not defined. An undefined weak symbol is
689 considered to have a value of zero (SVR4 ABI, p. 4-27). */
690 if (bfd_is_und_section (symbol
->section
)
691 && (symbol
->flags
& BSF_WEAK
) == 0
692 && output_bfd
== NULL
)
693 flag
= bfd_reloc_undefined
;
695 /* If there is a function supplied to handle this relocation type,
696 call it. It'll return `bfd_reloc_continue' if further processing
698 if (howto
&& howto
->special_function
)
700 bfd_reloc_status_type cont
;
702 /* Note - we do not call bfd_reloc_offset_in_range here as the
703 reloc_entry->address field might actually be valid for the
704 backend concerned. It is up to the special_function itself
705 to call bfd_reloc_offset_in_range if needed. */
706 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
707 input_section
, output_bfd
,
709 if (cont
!= bfd_reloc_continue
)
713 if (bfd_is_abs_section (symbol
->section
)
714 && output_bfd
!= NULL
)
716 reloc_entry
->address
+= input_section
->output_offset
;
720 /* PR 17512: file: 0f67f69d. */
722 return bfd_reloc_undefined
;
724 /* Is the address of the relocation really within the section? */
725 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
726 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
727 return bfd_reloc_outofrange
;
729 /* Work out which section the relocation is targeted at and the
730 initial relocation command value. */
732 /* Get symbol value. (Common symbols are special.) */
733 if (bfd_is_com_section (symbol
->section
))
736 relocation
= symbol
->value
;
738 reloc_target_output_section
= symbol
->section
->output_section
;
740 /* Convert input-section-relative symbol value to absolute. */
741 if ((output_bfd
&& ! howto
->partial_inplace
)
742 || reloc_target_output_section
== NULL
)
745 output_base
= reloc_target_output_section
->vma
;
747 relocation
+= output_base
+ symbol
->section
->output_offset
;
749 /* Add in supplied addend. */
750 relocation
+= reloc_entry
->addend
;
752 /* Here the variable relocation holds the final address of the
753 symbol we are relocating against, plus any addend. */
755 if (howto
->pc_relative
)
757 /* This is a PC relative relocation. We want to set RELOCATION
758 to the distance between the address of the symbol and the
759 location. RELOCATION is already the address of the symbol.
761 We start by subtracting the address of the section containing
764 If pcrel_offset is set, we must further subtract the position
765 of the location within the section. Some targets arrange for
766 the addend to be the negative of the position of the location
767 within the section; for example, i386-aout does this. For
768 i386-aout, pcrel_offset is FALSE. Some other targets do not
769 include the position of the location; for example, ELF.
770 For those targets, pcrel_offset is TRUE.
772 If we are producing relocatable output, then we must ensure
773 that this reloc will be correctly computed when the final
774 relocation is done. If pcrel_offset is FALSE we want to wind
775 up with the negative of the location within the section,
776 which means we must adjust the existing addend by the change
777 in the location within the section. If pcrel_offset is TRUE
778 we do not want to adjust the existing addend at all.
780 FIXME: This seems logical to me, but for the case of
781 producing relocatable output it is not what the code
782 actually does. I don't want to change it, because it seems
783 far too likely that something will break. */
786 input_section
->output_section
->vma
+ input_section
->output_offset
;
788 if (howto
->pcrel_offset
)
789 relocation
-= reloc_entry
->address
;
792 if (output_bfd
!= NULL
)
794 if (! howto
->partial_inplace
)
796 /* This is a partial relocation, and we want to apply the relocation
797 to the reloc entry rather than the raw data. Modify the reloc
798 inplace to reflect what we now know. */
799 reloc_entry
->addend
= relocation
;
800 reloc_entry
->address
+= input_section
->output_offset
;
805 /* This is a partial relocation, but inplace, so modify the
808 If we've relocated with a symbol with a section, change
809 into a ref to the section belonging to the symbol. */
811 reloc_entry
->address
+= input_section
->output_offset
;
814 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
815 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
816 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
818 /* For m68k-coff, the addend was being subtracted twice during
819 relocation with -r. Removing the line below this comment
820 fixes that problem; see PR 2953.
822 However, Ian wrote the following, regarding removing the line below,
823 which explains why it is still enabled: --djm
825 If you put a patch like that into BFD you need to check all the COFF
826 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
827 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
828 problem in a different way. There may very well be a reason that the
829 code works as it does.
831 Hmmm. The first obvious point is that bfd_perform_relocation should
832 not have any tests that depend upon the flavour. It's seem like
833 entirely the wrong place for such a thing. The second obvious point
834 is that the current code ignores the reloc addend when producing
835 relocatable output for COFF. That's peculiar. In fact, I really
836 have no idea what the point of the line you want to remove is.
838 A typical COFF reloc subtracts the old value of the symbol and adds in
839 the new value to the location in the object file (if it's a pc
840 relative reloc it adds the difference between the symbol value and the
841 location). When relocating we need to preserve that property.
843 BFD handles this by setting the addend to the negative of the old
844 value of the symbol. Unfortunately it handles common symbols in a
845 non-standard way (it doesn't subtract the old value) but that's a
846 different story (we can't change it without losing backward
847 compatibility with old object files) (coff-i386 does subtract the old
848 value, to be compatible with existing coff-i386 targets, like SCO).
850 So everything works fine when not producing relocatable output. When
851 we are producing relocatable output, logically we should do exactly
852 what we do when not producing relocatable output. Therefore, your
853 patch is correct. In fact, it should probably always just set
854 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
855 add the value into the object file. This won't hurt the COFF code,
856 which doesn't use the addend; I'm not sure what it will do to other
857 formats (the thing to check for would be whether any formats both use
858 the addend and set partial_inplace).
860 When I wanted to make coff-i386 produce relocatable output, I ran
861 into the problem that you are running into: I wanted to remove that
862 line. Rather than risk it, I made the coff-i386 relocs use a special
863 function; it's coff_i386_reloc in coff-i386.c. The function
864 specifically adds the addend field into the object file, knowing that
865 bfd_perform_relocation is not going to. If you remove that line, then
866 coff-i386.c will wind up adding the addend field in twice. It's
867 trivial to fix; it just needs to be done.
869 The problem with removing the line is just that it may break some
870 working code. With BFD it's hard to be sure of anything. The right
871 way to deal with this is simply to build and test at least all the
872 supported COFF targets. It should be straightforward if time and disk
873 space consuming. For each target:
875 2) generate some executable, and link it using -r (I would
876 probably use paranoia.o and link against newlib/libc.a, which
877 for all the supported targets would be available in
878 /usr/cygnus/progressive/H-host/target/lib/libc.a).
879 3) make the change to reloc.c
880 4) rebuild the linker
882 6) if the resulting object files are the same, you have at least
884 7) if they are different you have to figure out which version is
887 relocation
-= reloc_entry
->addend
;
888 reloc_entry
->addend
= 0;
892 reloc_entry
->addend
= relocation
;
897 /* FIXME: This overflow checking is incomplete, because the value
898 might have overflowed before we get here. For a correct check we
899 need to compute the value in a size larger than bitsize, but we
900 can't reasonably do that for a reloc the same size as a host
902 FIXME: We should also do overflow checking on the result after
903 adding in the value contained in the object file. */
904 if (howto
->complain_on_overflow
!= complain_overflow_dont
905 && flag
== bfd_reloc_ok
)
906 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
909 bfd_arch_bits_per_address (abfd
),
912 /* Either we are relocating all the way, or we don't want to apply
913 the relocation to the reloc entry (probably because there isn't
914 any room in the output format to describe addends to relocs). */
916 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
917 (OSF version 1.3, compiler version 3.11). It miscompiles the
931 x <<= (unsigned long) s.i0;
935 printf ("succeeded (%lx)\n", x);
939 relocation
>>= (bfd_vma
) howto
->rightshift
;
941 /* Shift everything up to where it's going to be used. */
942 relocation
<<= (bfd_vma
) howto
->bitpos
;
944 /* Wait for the day when all have the mask in them. */
947 i instruction to be left alone
948 o offset within instruction
949 r relocation offset to apply
958 (( i i i i i o o o o o from bfd_get<size>
959 and S S S S S) to get the size offset we want
960 + r r r r r r r r r r) to get the final value to place
961 and D D D D D to chop to right size
962 -----------------------
965 ( i i i i i o o o o o from bfd_get<size>
966 and N N N N N ) get instruction
967 -----------------------
973 -----------------------
974 = R R R R R R R R R R put into bfd_put<size>
977 data
= (bfd_byte
*) data
+ octets
;
978 apply_reloc (abfd
, data
, howto
, relocation
);
984 bfd_install_relocation
987 bfd_reloc_status_type bfd_install_relocation
989 arelent *reloc_entry,
990 void *data, bfd_vma data_start,
991 asection *input_section,
992 char **error_message);
995 This looks remarkably like <<bfd_perform_relocation>>, except it
996 does not expect that the section contents have been filled in.
997 I.e., it's suitable for use when creating, rather than applying
1000 For now, this function should be considered reserved for the
1004 bfd_reloc_status_type
1005 bfd_install_relocation (bfd
*abfd
,
1006 arelent
*reloc_entry
,
1008 bfd_vma data_start_offset
,
1009 asection
*input_section
,
1010 char **error_message
)
1013 bfd_reloc_status_type flag
= bfd_reloc_ok
;
1014 bfd_size_type octets
;
1015 bfd_vma output_base
= 0;
1016 reloc_howto_type
*howto
= reloc_entry
->howto
;
1017 asection
*reloc_target_output_section
;
1021 symbol
= *(reloc_entry
->sym_ptr_ptr
);
1023 /* If there is a function supplied to handle this relocation type,
1024 call it. It'll return `bfd_reloc_continue' if further processing
1026 if (howto
&& howto
->special_function
)
1028 bfd_reloc_status_type cont
;
1030 /* Note - we do not call bfd_reloc_offset_in_range here as the
1031 reloc_entry->address field might actually be valid for the
1032 backend concerned. It is up to the special_function itself
1033 to call bfd_reloc_offset_in_range if needed. */
1034 /* XXX - The special_function calls haven't been fixed up to deal
1035 with creating new relocations and section contents. */
1036 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
1037 /* XXX - Non-portable! */
1038 ((bfd_byte
*) data_start
1039 - data_start_offset
),
1040 input_section
, abfd
, error_message
);
1041 if (cont
!= bfd_reloc_continue
)
1045 if (bfd_is_abs_section (symbol
->section
))
1047 reloc_entry
->address
+= input_section
->output_offset
;
1048 return bfd_reloc_ok
;
1051 /* No need to check for howto != NULL if !bfd_is_abs_section as
1052 it will have been checked in `bfd_perform_relocation already'. */
1054 /* Is the address of the relocation really within the section? */
1055 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
1056 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
1057 return bfd_reloc_outofrange
;
1059 /* Work out which section the relocation is targeted at and the
1060 initial relocation command value. */
1062 /* Get symbol value. (Common symbols are special.) */
1063 if (bfd_is_com_section (symbol
->section
))
1066 relocation
= symbol
->value
;
1068 reloc_target_output_section
= symbol
->section
->output_section
;
1070 /* Convert input-section-relative symbol value to absolute. */
1071 if (! howto
->partial_inplace
)
1074 output_base
= reloc_target_output_section
->vma
;
1076 relocation
+= output_base
+ symbol
->section
->output_offset
;
1078 /* Add in supplied addend. */
1079 relocation
+= reloc_entry
->addend
;
1081 /* Here the variable relocation holds the final address of the
1082 symbol we are relocating against, plus any addend. */
1084 if (howto
->pc_relative
)
1086 /* This is a PC relative relocation. We want to set RELOCATION
1087 to the distance between the address of the symbol and the
1088 location. RELOCATION is already the address of the symbol.
1090 We start by subtracting the address of the section containing
1093 If pcrel_offset is set, we must further subtract the position
1094 of the location within the section. Some targets arrange for
1095 the addend to be the negative of the position of the location
1096 within the section; for example, i386-aout does this. For
1097 i386-aout, pcrel_offset is FALSE. Some other targets do not
1098 include the position of the location; for example, ELF.
1099 For those targets, pcrel_offset is TRUE.
1101 If we are producing relocatable output, then we must ensure
1102 that this reloc will be correctly computed when the final
1103 relocation is done. If pcrel_offset is FALSE we want to wind
1104 up with the negative of the location within the section,
1105 which means we must adjust the existing addend by the change
1106 in the location within the section. If pcrel_offset is TRUE
1107 we do not want to adjust the existing addend at all.
1109 FIXME: This seems logical to me, but for the case of
1110 producing relocatable output it is not what the code
1111 actually does. I don't want to change it, because it seems
1112 far too likely that something will break. */
1115 input_section
->output_section
->vma
+ input_section
->output_offset
;
1117 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1118 relocation
-= reloc_entry
->address
;
1121 if (! howto
->partial_inplace
)
1123 /* This is a partial relocation, and we want to apply the relocation
1124 to the reloc entry rather than the raw data. Modify the reloc
1125 inplace to reflect what we now know. */
1126 reloc_entry
->addend
= relocation
;
1127 reloc_entry
->address
+= input_section
->output_offset
;
1132 /* This is a partial relocation, but inplace, so modify the
1135 If we've relocated with a symbol with a section, change
1136 into a ref to the section belonging to the symbol. */
1137 reloc_entry
->address
+= input_section
->output_offset
;
1140 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1141 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1142 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1145 /* For m68k-coff, the addend was being subtracted twice during
1146 relocation with -r. Removing the line below this comment
1147 fixes that problem; see PR 2953.
1149 However, Ian wrote the following, regarding removing the line below,
1150 which explains why it is still enabled: --djm
1152 If you put a patch like that into BFD you need to check all the COFF
1153 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1154 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1155 problem in a different way. There may very well be a reason that the
1156 code works as it does.
1158 Hmmm. The first obvious point is that bfd_install_relocation should
1159 not have any tests that depend upon the flavour. It's seem like
1160 entirely the wrong place for such a thing. The second obvious point
1161 is that the current code ignores the reloc addend when producing
1162 relocatable output for COFF. That's peculiar. In fact, I really
1163 have no idea what the point of the line you want to remove is.
1165 A typical COFF reloc subtracts the old value of the symbol and adds in
1166 the new value to the location in the object file (if it's a pc
1167 relative reloc it adds the difference between the symbol value and the
1168 location). When relocating we need to preserve that property.
1170 BFD handles this by setting the addend to the negative of the old
1171 value of the symbol. Unfortunately it handles common symbols in a
1172 non-standard way (it doesn't subtract the old value) but that's a
1173 different story (we can't change it without losing backward
1174 compatibility with old object files) (coff-i386 does subtract the old
1175 value, to be compatible with existing coff-i386 targets, like SCO).
1177 So everything works fine when not producing relocatable output. When
1178 we are producing relocatable output, logically we should do exactly
1179 what we do when not producing relocatable output. Therefore, your
1180 patch is correct. In fact, it should probably always just set
1181 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1182 add the value into the object file. This won't hurt the COFF code,
1183 which doesn't use the addend; I'm not sure what it will do to other
1184 formats (the thing to check for would be whether any formats both use
1185 the addend and set partial_inplace).
1187 When I wanted to make coff-i386 produce relocatable output, I ran
1188 into the problem that you are running into: I wanted to remove that
1189 line. Rather than risk it, I made the coff-i386 relocs use a special
1190 function; it's coff_i386_reloc in coff-i386.c. The function
1191 specifically adds the addend field into the object file, knowing that
1192 bfd_install_relocation is not going to. If you remove that line, then
1193 coff-i386.c will wind up adding the addend field in twice. It's
1194 trivial to fix; it just needs to be done.
1196 The problem with removing the line is just that it may break some
1197 working code. With BFD it's hard to be sure of anything. The right
1198 way to deal with this is simply to build and test at least all the
1199 supported COFF targets. It should be straightforward if time and disk
1200 space consuming. For each target:
1202 2) generate some executable, and link it using -r (I would
1203 probably use paranoia.o and link against newlib/libc.a, which
1204 for all the supported targets would be available in
1205 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1206 3) make the change to reloc.c
1207 4) rebuild the linker
1209 6) if the resulting object files are the same, you have at least
1211 7) if they are different you have to figure out which version is
1213 relocation
-= reloc_entry
->addend
;
1214 /* FIXME: There should be no target specific code here... */
1215 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1216 reloc_entry
->addend
= 0;
1220 reloc_entry
->addend
= relocation
;
1224 /* FIXME: This overflow checking is incomplete, because the value
1225 might have overflowed before we get here. For a correct check we
1226 need to compute the value in a size larger than bitsize, but we
1227 can't reasonably do that for a reloc the same size as a host
1229 FIXME: We should also do overflow checking on the result after
1230 adding in the value contained in the object file. */
1231 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1232 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1235 bfd_arch_bits_per_address (abfd
),
1238 /* Either we are relocating all the way, or we don't want to apply
1239 the relocation to the reloc entry (probably because there isn't
1240 any room in the output format to describe addends to relocs). */
1242 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1243 (OSF version 1.3, compiler version 3.11). It miscompiles the
1257 x <<= (unsigned long) s.i0;
1259 printf ("failed\n");
1261 printf ("succeeded (%lx)\n", x);
1265 relocation
>>= (bfd_vma
) howto
->rightshift
;
1267 /* Shift everything up to where it's going to be used. */
1268 relocation
<<= (bfd_vma
) howto
->bitpos
;
1270 /* Wait for the day when all have the mask in them. */
1273 i instruction to be left alone
1274 o offset within instruction
1275 r relocation offset to apply
1284 (( i i i i i o o o o o from bfd_get<size>
1285 and S S S S S) to get the size offset we want
1286 + r r r r r r r r r r) to get the final value to place
1287 and D D D D D to chop to right size
1288 -----------------------
1291 ( i i i i i o o o o o from bfd_get<size>
1292 and N N N N N ) get instruction
1293 -----------------------
1299 -----------------------
1300 = R R R R R R R R R R put into bfd_put<size>
1303 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1304 apply_reloc (abfd
, data
, howto
, relocation
);
1308 /* This relocation routine is used by some of the backend linkers.
1309 They do not construct asymbol or arelent structures, so there is no
1310 reason for them to use bfd_perform_relocation. Also,
1311 bfd_perform_relocation is so hacked up it is easier to write a new
1312 function than to try to deal with it.
1314 This routine does a final relocation. Whether it is useful for a
1315 relocatable link depends upon how the object format defines
1318 FIXME: This routine ignores any special_function in the HOWTO,
1319 since the existing special_function values have been written for
1320 bfd_perform_relocation.
1322 HOWTO is the reloc howto information.
1323 INPUT_BFD is the BFD which the reloc applies to.
1324 INPUT_SECTION is the section which the reloc applies to.
1325 CONTENTS is the contents of the section.
1326 ADDRESS is the address of the reloc within INPUT_SECTION.
1327 VALUE is the value of the symbol the reloc refers to.
1328 ADDEND is the addend of the reloc. */
1330 bfd_reloc_status_type
1331 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1333 asection
*input_section
,
1340 bfd_size_type octets
= address
* bfd_octets_per_byte (input_bfd
);
1342 /* Sanity check the address. */
1343 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, octets
))
1344 return bfd_reloc_outofrange
;
1346 /* This function assumes that we are dealing with a basic relocation
1347 against a symbol. We want to compute the value of the symbol to
1348 relocate to. This is just VALUE, the value of the symbol, plus
1349 ADDEND, any addend associated with the reloc. */
1350 relocation
= value
+ addend
;
1352 /* If the relocation is PC relative, we want to set RELOCATION to
1353 the distance between the symbol (currently in RELOCATION) and the
1354 location we are relocating. Some targets (e.g., i386-aout)
1355 arrange for the contents of the section to be the negative of the
1356 offset of the location within the section; for such targets
1357 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1358 the contents of the section as zero; for such targets
1359 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1360 subtract out the offset of the location within the section (which
1361 is just ADDRESS). */
1362 if (howto
->pc_relative
)
1364 relocation
-= (input_section
->output_section
->vma
1365 + input_section
->output_offset
);
1366 if (howto
->pcrel_offset
)
1367 relocation
-= address
;
1370 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1372 + address
* bfd_octets_per_byte (input_bfd
));
1375 /* Relocate a given location using a given value and howto. */
1377 bfd_reloc_status_type
1378 _bfd_relocate_contents (reloc_howto_type
*howto
,
1384 bfd_reloc_status_type flag
;
1385 unsigned int rightshift
= howto
->rightshift
;
1386 unsigned int bitpos
= howto
->bitpos
;
1389 relocation
= -relocation
;
1391 /* Get the value we are going to relocate. */
1392 x
= read_reloc (input_bfd
, location
, howto
);
1394 /* Check for overflow. FIXME: We may drop bits during the addition
1395 which we don't check for. We must either check at every single
1396 operation, which would be tedious, or we must do the computations
1397 in a type larger than bfd_vma, which would be inefficient. */
1398 flag
= bfd_reloc_ok
;
1399 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1401 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1404 /* Get the values to be added together. For signed and unsigned
1405 relocations, we assume that all values should be truncated to
1406 the size of an address. For bitfields, all the bits matter.
1407 See also bfd_check_overflow. */
1408 fieldmask
= N_ONES (howto
->bitsize
);
1409 signmask
= ~fieldmask
;
1410 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1411 | (fieldmask
<< rightshift
));
1412 a
= (relocation
& addrmask
) >> rightshift
;
1413 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1414 addrmask
>>= rightshift
;
1416 switch (howto
->complain_on_overflow
)
1418 case complain_overflow_signed
:
1419 /* If any sign bits are set, all sign bits must be set.
1420 That is, A must be a valid negative address after
1422 signmask
= ~(fieldmask
>> 1);
1425 case complain_overflow_bitfield
:
1426 /* Much like the signed check, but for a field one bit
1427 wider. We allow a bitfield to represent numbers in the
1428 range -2**n to 2**n-1, where n is the number of bits in the
1429 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1430 can't overflow, which is exactly what we want. */
1432 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1433 flag
= bfd_reloc_overflow
;
1435 /* We only need this next bit of code if the sign bit of B
1436 is below the sign bit of A. This would only happen if
1437 SRC_MASK had fewer bits than BITSIZE. Note that if
1438 SRC_MASK has more bits than BITSIZE, we can get into
1439 trouble; we would need to verify that B is in range, as
1440 we do for A above. */
1441 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1444 /* Set all the bits above the sign bit. */
1447 /* Now we can do the addition. */
1450 /* See if the result has the correct sign. Bits above the
1451 sign bit are junk now; ignore them. If the sum is
1452 positive, make sure we did not have all negative inputs;
1453 if the sum is negative, make sure we did not have all
1454 positive inputs. The test below looks only at the sign
1455 bits, and it really just
1456 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1458 We mask with addrmask here to explicitly allow an address
1459 wrap-around. The Linux kernel relies on it, and it is
1460 the only way to write assembler code which can run when
1461 loaded at a location 0x80000000 away from the location at
1462 which it is linked. */
1463 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1464 flag
= bfd_reloc_overflow
;
1467 case complain_overflow_unsigned
:
1468 /* Checking for an unsigned overflow is relatively easy:
1469 trim the addresses and add, and trim the result as well.
1470 Overflow is normally indicated when the result does not
1471 fit in the field. However, we also need to consider the
1472 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1473 input is 0x80000000, and bfd_vma is only 32 bits; then we
1474 will get sum == 0, but there is an overflow, since the
1475 inputs did not fit in the field. Instead of doing a
1476 separate test, we can check for this by or-ing in the
1477 operands when testing for the sum overflowing its final
1479 sum
= (a
+ b
) & addrmask
;
1480 if ((a
| b
| sum
) & signmask
)
1481 flag
= bfd_reloc_overflow
;
1489 /* Put RELOCATION in the right bits. */
1490 relocation
>>= (bfd_vma
) rightshift
;
1491 relocation
<<= (bfd_vma
) bitpos
;
1493 /* Add RELOCATION to the right bits of X. */
1494 x
= ((x
& ~howto
->dst_mask
)
1495 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1497 /* Put the relocated value back in the object file. */
1498 write_reloc (input_bfd
, x
, location
, howto
);
1502 /* Clear a given location using a given howto, by applying a fixed relocation
1503 value and discarding any in-place addend. This is used for fixed-up
1504 relocations against discarded symbols, to make ignorable debug or unwind
1505 information more obvious. */
1507 bfd_reloc_status_type
1508 _bfd_clear_contents (reloc_howto_type
*howto
,
1510 asection
*input_section
,
1517 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, off
))
1518 return bfd_reloc_outofrange
;
1520 /* Get the value we are going to relocate. */
1521 location
= buf
+ off
;
1522 x
= read_reloc (input_bfd
, location
, howto
);
1524 /* Zero out the unwanted bits of X. */
1525 x
&= ~howto
->dst_mask
;
1527 /* For a range list, use 1 instead of 0 as placeholder. 0
1528 would terminate the list, hiding any later entries. */
1529 if (strcmp (bfd_get_section_name (input_bfd
, input_section
),
1530 ".debug_ranges") == 0
1531 && (howto
->dst_mask
& 1) != 0)
1534 /* Put the relocated value back in the object file. */
1535 write_reloc (input_bfd
, x
, location
, howto
);
1536 return bfd_reloc_ok
;
1542 howto manager, , typedef arelent, Relocations
1547 When an application wants to create a relocation, but doesn't
1548 know what the target machine might call it, it can find out by
1549 using this bit of code.
1558 The insides of a reloc code. The idea is that, eventually, there
1559 will be one enumerator for every type of relocation we ever do.
1560 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1561 return a howto pointer.
1563 This does mean that the application must determine the correct
1564 enumerator value; you can't get a howto pointer from a random set
1585 Basic absolute relocations of N bits.
1600 PC-relative relocations. Sometimes these are relative to the address
1601 of the relocation itself; sometimes they are relative to the start of
1602 the section containing the relocation. It depends on the specific target.
1607 Section relative relocations. Some targets need this for DWARF2.
1610 BFD_RELOC_32_GOT_PCREL
1612 BFD_RELOC_16_GOT_PCREL
1614 BFD_RELOC_8_GOT_PCREL
1620 BFD_RELOC_LO16_GOTOFF
1622 BFD_RELOC_HI16_GOTOFF
1624 BFD_RELOC_HI16_S_GOTOFF
1628 BFD_RELOC_64_PLT_PCREL
1630 BFD_RELOC_32_PLT_PCREL
1632 BFD_RELOC_24_PLT_PCREL
1634 BFD_RELOC_16_PLT_PCREL
1636 BFD_RELOC_8_PLT_PCREL
1644 BFD_RELOC_LO16_PLTOFF
1646 BFD_RELOC_HI16_PLTOFF
1648 BFD_RELOC_HI16_S_PLTOFF
1662 BFD_RELOC_68K_GLOB_DAT
1664 BFD_RELOC_68K_JMP_SLOT
1666 BFD_RELOC_68K_RELATIVE
1668 BFD_RELOC_68K_TLS_GD32
1670 BFD_RELOC_68K_TLS_GD16
1672 BFD_RELOC_68K_TLS_GD8
1674 BFD_RELOC_68K_TLS_LDM32
1676 BFD_RELOC_68K_TLS_LDM16
1678 BFD_RELOC_68K_TLS_LDM8
1680 BFD_RELOC_68K_TLS_LDO32
1682 BFD_RELOC_68K_TLS_LDO16
1684 BFD_RELOC_68K_TLS_LDO8
1686 BFD_RELOC_68K_TLS_IE32
1688 BFD_RELOC_68K_TLS_IE16
1690 BFD_RELOC_68K_TLS_IE8
1692 BFD_RELOC_68K_TLS_LE32
1694 BFD_RELOC_68K_TLS_LE16
1696 BFD_RELOC_68K_TLS_LE8
1698 Relocations used by 68K ELF.
1701 BFD_RELOC_32_BASEREL
1703 BFD_RELOC_16_BASEREL
1705 BFD_RELOC_LO16_BASEREL
1707 BFD_RELOC_HI16_BASEREL
1709 BFD_RELOC_HI16_S_BASEREL
1715 Linkage-table relative.
1720 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1723 BFD_RELOC_32_PCREL_S2
1725 BFD_RELOC_16_PCREL_S2
1727 BFD_RELOC_23_PCREL_S2
1729 These PC-relative relocations are stored as word displacements --
1730 i.e., byte displacements shifted right two bits. The 30-bit word
1731 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1732 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1733 signed 16-bit displacement is used on the MIPS, and the 23-bit
1734 displacement is used on the Alpha.
1741 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1742 the target word. These are used on the SPARC.
1749 For systems that allocate a Global Pointer register, these are
1750 displacements off that register. These relocation types are
1751 handled specially, because the value the register will have is
1752 decided relatively late.
1757 BFD_RELOC_SPARC_WDISP22
1763 BFD_RELOC_SPARC_GOT10
1765 BFD_RELOC_SPARC_GOT13
1767 BFD_RELOC_SPARC_GOT22
1769 BFD_RELOC_SPARC_PC10
1771 BFD_RELOC_SPARC_PC22
1773 BFD_RELOC_SPARC_WPLT30
1775 BFD_RELOC_SPARC_COPY
1777 BFD_RELOC_SPARC_GLOB_DAT
1779 BFD_RELOC_SPARC_JMP_SLOT
1781 BFD_RELOC_SPARC_RELATIVE
1783 BFD_RELOC_SPARC_UA16
1785 BFD_RELOC_SPARC_UA32
1787 BFD_RELOC_SPARC_UA64
1789 BFD_RELOC_SPARC_GOTDATA_HIX22
1791 BFD_RELOC_SPARC_GOTDATA_LOX10
1793 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1795 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1797 BFD_RELOC_SPARC_GOTDATA_OP
1799 BFD_RELOC_SPARC_JMP_IREL
1801 BFD_RELOC_SPARC_IRELATIVE
1803 SPARC ELF relocations. There is probably some overlap with other
1804 relocation types already defined.
1807 BFD_RELOC_SPARC_BASE13
1809 BFD_RELOC_SPARC_BASE22
1811 I think these are specific to SPARC a.out (e.g., Sun 4).
1821 BFD_RELOC_SPARC_OLO10
1823 BFD_RELOC_SPARC_HH22
1825 BFD_RELOC_SPARC_HM10
1827 BFD_RELOC_SPARC_LM22
1829 BFD_RELOC_SPARC_PC_HH22
1831 BFD_RELOC_SPARC_PC_HM10
1833 BFD_RELOC_SPARC_PC_LM22
1835 BFD_RELOC_SPARC_WDISP16
1837 BFD_RELOC_SPARC_WDISP19
1845 BFD_RELOC_SPARC_DISP64
1848 BFD_RELOC_SPARC_PLT32
1850 BFD_RELOC_SPARC_PLT64
1852 BFD_RELOC_SPARC_HIX22
1854 BFD_RELOC_SPARC_LOX10
1862 BFD_RELOC_SPARC_REGISTER
1866 BFD_RELOC_SPARC_SIZE32
1868 BFD_RELOC_SPARC_SIZE64
1870 BFD_RELOC_SPARC_WDISP10
1875 BFD_RELOC_SPARC_REV32
1877 SPARC little endian relocation
1879 BFD_RELOC_SPARC_TLS_GD_HI22
1881 BFD_RELOC_SPARC_TLS_GD_LO10
1883 BFD_RELOC_SPARC_TLS_GD_ADD
1885 BFD_RELOC_SPARC_TLS_GD_CALL
1887 BFD_RELOC_SPARC_TLS_LDM_HI22
1889 BFD_RELOC_SPARC_TLS_LDM_LO10
1891 BFD_RELOC_SPARC_TLS_LDM_ADD
1893 BFD_RELOC_SPARC_TLS_LDM_CALL
1895 BFD_RELOC_SPARC_TLS_LDO_HIX22
1897 BFD_RELOC_SPARC_TLS_LDO_LOX10
1899 BFD_RELOC_SPARC_TLS_LDO_ADD
1901 BFD_RELOC_SPARC_TLS_IE_HI22
1903 BFD_RELOC_SPARC_TLS_IE_LO10
1905 BFD_RELOC_SPARC_TLS_IE_LD
1907 BFD_RELOC_SPARC_TLS_IE_LDX
1909 BFD_RELOC_SPARC_TLS_IE_ADD
1911 BFD_RELOC_SPARC_TLS_LE_HIX22
1913 BFD_RELOC_SPARC_TLS_LE_LOX10
1915 BFD_RELOC_SPARC_TLS_DTPMOD32
1917 BFD_RELOC_SPARC_TLS_DTPMOD64
1919 BFD_RELOC_SPARC_TLS_DTPOFF32
1921 BFD_RELOC_SPARC_TLS_DTPOFF64
1923 BFD_RELOC_SPARC_TLS_TPOFF32
1925 BFD_RELOC_SPARC_TLS_TPOFF64
1927 SPARC TLS relocations
1936 BFD_RELOC_SPU_IMM10W
1940 BFD_RELOC_SPU_IMM16W
1944 BFD_RELOC_SPU_PCREL9a
1946 BFD_RELOC_SPU_PCREL9b
1948 BFD_RELOC_SPU_PCREL16
1958 BFD_RELOC_SPU_ADD_PIC
1963 BFD_RELOC_ALPHA_GPDISP_HI16
1965 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
1966 "addend" in some special way.
1967 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
1968 writing; when reading, it will be the absolute section symbol. The
1969 addend is the displacement in bytes of the "lda" instruction from
1970 the "ldah" instruction (which is at the address of this reloc).
1972 BFD_RELOC_ALPHA_GPDISP_LO16
1974 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
1975 with GPDISP_HI16 relocs. The addend is ignored when writing the
1976 relocations out, and is filled in with the file's GP value on
1977 reading, for convenience.
1980 BFD_RELOC_ALPHA_GPDISP
1982 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
1983 relocation except that there is no accompanying GPDISP_LO16
1987 BFD_RELOC_ALPHA_LITERAL
1989 BFD_RELOC_ALPHA_ELF_LITERAL
1991 BFD_RELOC_ALPHA_LITUSE
1993 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
1994 the assembler turns it into a LDQ instruction to load the address of
1995 the symbol, and then fills in a register in the real instruction.
1997 The LITERAL reloc, at the LDQ instruction, refers to the .lita
1998 section symbol. The addend is ignored when writing, but is filled
1999 in with the file's GP value on reading, for convenience, as with the
2002 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2003 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2004 but it generates output not based on the position within the .got
2005 section, but relative to the GP value chosen for the file during the
2008 The LITUSE reloc, on the instruction using the loaded address, gives
2009 information to the linker that it might be able to use to optimize
2010 away some literal section references. The symbol is ignored (read
2011 as the absolute section symbol), and the "addend" indicates the type
2012 of instruction using the register:
2013 1 - "memory" fmt insn
2014 2 - byte-manipulation (byte offset reg)
2015 3 - jsr (target of branch)
2018 BFD_RELOC_ALPHA_HINT
2020 The HINT relocation indicates a value that should be filled into the
2021 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2022 prediction logic which may be provided on some processors.
2025 BFD_RELOC_ALPHA_LINKAGE
2027 The LINKAGE relocation outputs a linkage pair in the object file,
2028 which is filled by the linker.
2031 BFD_RELOC_ALPHA_CODEADDR
2033 The CODEADDR relocation outputs a STO_CA in the object file,
2034 which is filled by the linker.
2037 BFD_RELOC_ALPHA_GPREL_HI16
2039 BFD_RELOC_ALPHA_GPREL_LO16
2041 The GPREL_HI/LO relocations together form a 32-bit offset from the
2045 BFD_RELOC_ALPHA_BRSGP
2047 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2048 share a common GP, and the target address is adjusted for
2049 STO_ALPHA_STD_GPLOAD.
2054 The NOP relocation outputs a NOP if the longword displacement
2055 between two procedure entry points is < 2^21.
2060 The BSR relocation outputs a BSR if the longword displacement
2061 between two procedure entry points is < 2^21.
2066 The LDA relocation outputs a LDA if the longword displacement
2067 between two procedure entry points is < 2^16.
2072 The BOH relocation outputs a BSR if the longword displacement
2073 between two procedure entry points is < 2^21, or else a hint.
2076 BFD_RELOC_ALPHA_TLSGD
2078 BFD_RELOC_ALPHA_TLSLDM
2080 BFD_RELOC_ALPHA_DTPMOD64
2082 BFD_RELOC_ALPHA_GOTDTPREL16
2084 BFD_RELOC_ALPHA_DTPREL64
2086 BFD_RELOC_ALPHA_DTPREL_HI16
2088 BFD_RELOC_ALPHA_DTPREL_LO16
2090 BFD_RELOC_ALPHA_DTPREL16
2092 BFD_RELOC_ALPHA_GOTTPREL16
2094 BFD_RELOC_ALPHA_TPREL64
2096 BFD_RELOC_ALPHA_TPREL_HI16
2098 BFD_RELOC_ALPHA_TPREL_LO16
2100 BFD_RELOC_ALPHA_TPREL16
2102 Alpha thread-local storage relocations.
2107 BFD_RELOC_MICROMIPS_JMP
2109 The MIPS jump instruction.
2112 BFD_RELOC_MIPS16_JMP
2114 The MIPS16 jump instruction.
2117 BFD_RELOC_MIPS16_GPREL
2119 MIPS16 GP relative reloc.
2124 High 16 bits of 32-bit value; simple reloc.
2129 High 16 bits of 32-bit value but the low 16 bits will be sign
2130 extended and added to form the final result. If the low 16
2131 bits form a negative number, we need to add one to the high value
2132 to compensate for the borrow when the low bits are added.
2140 BFD_RELOC_HI16_PCREL
2142 High 16 bits of 32-bit pc-relative value
2144 BFD_RELOC_HI16_S_PCREL
2146 High 16 bits of 32-bit pc-relative value, adjusted
2148 BFD_RELOC_LO16_PCREL
2150 Low 16 bits of pc-relative value
2153 BFD_RELOC_MIPS16_GOT16
2155 BFD_RELOC_MIPS16_CALL16
2157 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2158 16-bit immediate fields
2160 BFD_RELOC_MIPS16_HI16
2162 MIPS16 high 16 bits of 32-bit value.
2164 BFD_RELOC_MIPS16_HI16_S
2166 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2167 extended and added to form the final result. If the low 16
2168 bits form a negative number, we need to add one to the high value
2169 to compensate for the borrow when the low bits are added.
2171 BFD_RELOC_MIPS16_LO16
2176 BFD_RELOC_MIPS16_TLS_GD
2178 BFD_RELOC_MIPS16_TLS_LDM
2180 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2182 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2184 BFD_RELOC_MIPS16_TLS_GOTTPREL
2186 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2188 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2190 MIPS16 TLS relocations
2193 BFD_RELOC_MIPS_LITERAL
2195 BFD_RELOC_MICROMIPS_LITERAL
2197 Relocation against a MIPS literal section.
2200 BFD_RELOC_MICROMIPS_7_PCREL_S1
2202 BFD_RELOC_MICROMIPS_10_PCREL_S1
2204 BFD_RELOC_MICROMIPS_16_PCREL_S1
2206 microMIPS PC-relative relocations.
2209 BFD_RELOC_MIPS16_16_PCREL_S1
2211 MIPS16 PC-relative relocation.
2214 BFD_RELOC_MIPS_21_PCREL_S2
2216 BFD_RELOC_MIPS_26_PCREL_S2
2218 BFD_RELOC_MIPS_18_PCREL_S3
2220 BFD_RELOC_MIPS_19_PCREL_S2
2222 MIPS PC-relative relocations.
2225 BFD_RELOC_MICROMIPS_GPREL16
2227 BFD_RELOC_MICROMIPS_HI16
2229 BFD_RELOC_MICROMIPS_HI16_S
2231 BFD_RELOC_MICROMIPS_LO16
2233 microMIPS versions of generic BFD relocs.
2236 BFD_RELOC_MIPS_GOT16
2238 BFD_RELOC_MICROMIPS_GOT16
2240 BFD_RELOC_MIPS_CALL16
2242 BFD_RELOC_MICROMIPS_CALL16
2244 BFD_RELOC_MIPS_GOT_HI16
2246 BFD_RELOC_MICROMIPS_GOT_HI16
2248 BFD_RELOC_MIPS_GOT_LO16
2250 BFD_RELOC_MICROMIPS_GOT_LO16
2252 BFD_RELOC_MIPS_CALL_HI16
2254 BFD_RELOC_MICROMIPS_CALL_HI16
2256 BFD_RELOC_MIPS_CALL_LO16
2258 BFD_RELOC_MICROMIPS_CALL_LO16
2262 BFD_RELOC_MICROMIPS_SUB
2264 BFD_RELOC_MIPS_GOT_PAGE
2266 BFD_RELOC_MICROMIPS_GOT_PAGE
2268 BFD_RELOC_MIPS_GOT_OFST
2270 BFD_RELOC_MICROMIPS_GOT_OFST
2272 BFD_RELOC_MIPS_GOT_DISP
2274 BFD_RELOC_MICROMIPS_GOT_DISP
2276 BFD_RELOC_MIPS_SHIFT5
2278 BFD_RELOC_MIPS_SHIFT6
2280 BFD_RELOC_MIPS_INSERT_A
2282 BFD_RELOC_MIPS_INSERT_B
2284 BFD_RELOC_MIPS_DELETE
2286 BFD_RELOC_MIPS_HIGHEST
2288 BFD_RELOC_MICROMIPS_HIGHEST
2290 BFD_RELOC_MIPS_HIGHER
2292 BFD_RELOC_MICROMIPS_HIGHER
2294 BFD_RELOC_MIPS_SCN_DISP
2296 BFD_RELOC_MICROMIPS_SCN_DISP
2298 BFD_RELOC_MIPS_REL16
2300 BFD_RELOC_MIPS_RELGOT
2304 BFD_RELOC_MICROMIPS_JALR
2306 BFD_RELOC_MIPS_TLS_DTPMOD32
2308 BFD_RELOC_MIPS_TLS_DTPREL32
2310 BFD_RELOC_MIPS_TLS_DTPMOD64
2312 BFD_RELOC_MIPS_TLS_DTPREL64
2314 BFD_RELOC_MIPS_TLS_GD
2316 BFD_RELOC_MICROMIPS_TLS_GD
2318 BFD_RELOC_MIPS_TLS_LDM
2320 BFD_RELOC_MICROMIPS_TLS_LDM
2322 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2324 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2326 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2328 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2330 BFD_RELOC_MIPS_TLS_GOTTPREL
2332 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2334 BFD_RELOC_MIPS_TLS_TPREL32
2336 BFD_RELOC_MIPS_TLS_TPREL64
2338 BFD_RELOC_MIPS_TLS_TPREL_HI16
2340 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2342 BFD_RELOC_MIPS_TLS_TPREL_LO16
2344 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2348 MIPS ELF relocations.
2354 BFD_RELOC_MIPS_JUMP_SLOT
2356 MIPS ELF relocations (VxWorks and PLT extensions).
2360 BFD_RELOC_MOXIE_10_PCREL
2362 Moxie ELF relocations.
2374 BFD_RELOC_FT32_RELAX
2382 BFD_RELOC_FT32_DIFF32
2384 FT32 ELF relocations.
2388 BFD_RELOC_FRV_LABEL16
2390 BFD_RELOC_FRV_LABEL24
2396 BFD_RELOC_FRV_GPREL12
2398 BFD_RELOC_FRV_GPRELU12
2400 BFD_RELOC_FRV_GPREL32
2402 BFD_RELOC_FRV_GPRELHI
2404 BFD_RELOC_FRV_GPRELLO
2412 BFD_RELOC_FRV_FUNCDESC
2414 BFD_RELOC_FRV_FUNCDESC_GOT12
2416 BFD_RELOC_FRV_FUNCDESC_GOTHI
2418 BFD_RELOC_FRV_FUNCDESC_GOTLO
2420 BFD_RELOC_FRV_FUNCDESC_VALUE
2422 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2424 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2426 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2428 BFD_RELOC_FRV_GOTOFF12
2430 BFD_RELOC_FRV_GOTOFFHI
2432 BFD_RELOC_FRV_GOTOFFLO
2434 BFD_RELOC_FRV_GETTLSOFF
2436 BFD_RELOC_FRV_TLSDESC_VALUE
2438 BFD_RELOC_FRV_GOTTLSDESC12
2440 BFD_RELOC_FRV_GOTTLSDESCHI
2442 BFD_RELOC_FRV_GOTTLSDESCLO
2444 BFD_RELOC_FRV_TLSMOFF12
2446 BFD_RELOC_FRV_TLSMOFFHI
2448 BFD_RELOC_FRV_TLSMOFFLO
2450 BFD_RELOC_FRV_GOTTLSOFF12
2452 BFD_RELOC_FRV_GOTTLSOFFHI
2454 BFD_RELOC_FRV_GOTTLSOFFLO
2456 BFD_RELOC_FRV_TLSOFF
2458 BFD_RELOC_FRV_TLSDESC_RELAX
2460 BFD_RELOC_FRV_GETTLSOFF_RELAX
2462 BFD_RELOC_FRV_TLSOFF_RELAX
2464 BFD_RELOC_FRV_TLSMOFF
2466 Fujitsu Frv Relocations.
2470 BFD_RELOC_MN10300_GOTOFF24
2472 This is a 24bit GOT-relative reloc for the mn10300.
2474 BFD_RELOC_MN10300_GOT32
2476 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2479 BFD_RELOC_MN10300_GOT24
2481 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2484 BFD_RELOC_MN10300_GOT16
2486 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2489 BFD_RELOC_MN10300_COPY
2491 Copy symbol at runtime.
2493 BFD_RELOC_MN10300_GLOB_DAT
2497 BFD_RELOC_MN10300_JMP_SLOT
2501 BFD_RELOC_MN10300_RELATIVE
2503 Adjust by program base.
2505 BFD_RELOC_MN10300_SYM_DIFF
2507 Together with another reloc targeted at the same location,
2508 allows for a value that is the difference of two symbols
2509 in the same section.
2511 BFD_RELOC_MN10300_ALIGN
2513 The addend of this reloc is an alignment power that must
2514 be honoured at the offset's location, regardless of linker
2517 BFD_RELOC_MN10300_TLS_GD
2519 BFD_RELOC_MN10300_TLS_LD
2521 BFD_RELOC_MN10300_TLS_LDO
2523 BFD_RELOC_MN10300_TLS_GOTIE
2525 BFD_RELOC_MN10300_TLS_IE
2527 BFD_RELOC_MN10300_TLS_LE
2529 BFD_RELOC_MN10300_TLS_DTPMOD
2531 BFD_RELOC_MN10300_TLS_DTPOFF
2533 BFD_RELOC_MN10300_TLS_TPOFF
2535 Various TLS-related relocations.
2537 BFD_RELOC_MN10300_32_PCREL
2539 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2542 BFD_RELOC_MN10300_16_PCREL
2544 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2555 BFD_RELOC_386_GLOB_DAT
2557 BFD_RELOC_386_JUMP_SLOT
2559 BFD_RELOC_386_RELATIVE
2561 BFD_RELOC_386_GOTOFF
2565 BFD_RELOC_386_TLS_TPOFF
2567 BFD_RELOC_386_TLS_IE
2569 BFD_RELOC_386_TLS_GOTIE
2571 BFD_RELOC_386_TLS_LE
2573 BFD_RELOC_386_TLS_GD
2575 BFD_RELOC_386_TLS_LDM
2577 BFD_RELOC_386_TLS_LDO_32
2579 BFD_RELOC_386_TLS_IE_32
2581 BFD_RELOC_386_TLS_LE_32
2583 BFD_RELOC_386_TLS_DTPMOD32
2585 BFD_RELOC_386_TLS_DTPOFF32
2587 BFD_RELOC_386_TLS_TPOFF32
2589 BFD_RELOC_386_TLS_GOTDESC
2591 BFD_RELOC_386_TLS_DESC_CALL
2593 BFD_RELOC_386_TLS_DESC
2595 BFD_RELOC_386_IRELATIVE
2597 BFD_RELOC_386_GOT32X
2599 i386/elf relocations
2602 BFD_RELOC_X86_64_GOT32
2604 BFD_RELOC_X86_64_PLT32
2606 BFD_RELOC_X86_64_COPY
2608 BFD_RELOC_X86_64_GLOB_DAT
2610 BFD_RELOC_X86_64_JUMP_SLOT
2612 BFD_RELOC_X86_64_RELATIVE
2614 BFD_RELOC_X86_64_GOTPCREL
2616 BFD_RELOC_X86_64_32S
2618 BFD_RELOC_X86_64_DTPMOD64
2620 BFD_RELOC_X86_64_DTPOFF64
2622 BFD_RELOC_X86_64_TPOFF64
2624 BFD_RELOC_X86_64_TLSGD
2626 BFD_RELOC_X86_64_TLSLD
2628 BFD_RELOC_X86_64_DTPOFF32
2630 BFD_RELOC_X86_64_GOTTPOFF
2632 BFD_RELOC_X86_64_TPOFF32
2634 BFD_RELOC_X86_64_GOTOFF64
2636 BFD_RELOC_X86_64_GOTPC32
2638 BFD_RELOC_X86_64_GOT64
2640 BFD_RELOC_X86_64_GOTPCREL64
2642 BFD_RELOC_X86_64_GOTPC64
2644 BFD_RELOC_X86_64_GOTPLT64
2646 BFD_RELOC_X86_64_PLTOFF64
2648 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2650 BFD_RELOC_X86_64_TLSDESC_CALL
2652 BFD_RELOC_X86_64_TLSDESC
2654 BFD_RELOC_X86_64_IRELATIVE
2656 BFD_RELOC_X86_64_PC32_BND
2658 BFD_RELOC_X86_64_PLT32_BND
2660 BFD_RELOC_X86_64_GOTPCRELX
2662 BFD_RELOC_X86_64_REX_GOTPCRELX
2664 x86-64/elf relocations
2667 BFD_RELOC_NS32K_IMM_8
2669 BFD_RELOC_NS32K_IMM_16
2671 BFD_RELOC_NS32K_IMM_32
2673 BFD_RELOC_NS32K_IMM_8_PCREL
2675 BFD_RELOC_NS32K_IMM_16_PCREL
2677 BFD_RELOC_NS32K_IMM_32_PCREL
2679 BFD_RELOC_NS32K_DISP_8
2681 BFD_RELOC_NS32K_DISP_16
2683 BFD_RELOC_NS32K_DISP_32
2685 BFD_RELOC_NS32K_DISP_8_PCREL
2687 BFD_RELOC_NS32K_DISP_16_PCREL
2689 BFD_RELOC_NS32K_DISP_32_PCREL
2694 BFD_RELOC_PDP11_DISP_8_PCREL
2696 BFD_RELOC_PDP11_DISP_6_PCREL
2701 BFD_RELOC_PJ_CODE_HI16
2703 BFD_RELOC_PJ_CODE_LO16
2705 BFD_RELOC_PJ_CODE_DIR16
2707 BFD_RELOC_PJ_CODE_DIR32
2709 BFD_RELOC_PJ_CODE_REL16
2711 BFD_RELOC_PJ_CODE_REL32
2713 Picojava relocs. Not all of these appear in object files.
2724 BFD_RELOC_PPC_B16_BRTAKEN
2726 BFD_RELOC_PPC_B16_BRNTAKEN
2730 BFD_RELOC_PPC_BA16_BRTAKEN
2732 BFD_RELOC_PPC_BA16_BRNTAKEN
2736 BFD_RELOC_PPC_GLOB_DAT
2738 BFD_RELOC_PPC_JMP_SLOT
2740 BFD_RELOC_PPC_RELATIVE
2742 BFD_RELOC_PPC_LOCAL24PC
2744 BFD_RELOC_PPC_EMB_NADDR32
2746 BFD_RELOC_PPC_EMB_NADDR16
2748 BFD_RELOC_PPC_EMB_NADDR16_LO
2750 BFD_RELOC_PPC_EMB_NADDR16_HI
2752 BFD_RELOC_PPC_EMB_NADDR16_HA
2754 BFD_RELOC_PPC_EMB_SDAI16
2756 BFD_RELOC_PPC_EMB_SDA2I16
2758 BFD_RELOC_PPC_EMB_SDA2REL
2760 BFD_RELOC_PPC_EMB_SDA21
2762 BFD_RELOC_PPC_EMB_MRKREF
2764 BFD_RELOC_PPC_EMB_RELSEC16
2766 BFD_RELOC_PPC_EMB_RELST_LO
2768 BFD_RELOC_PPC_EMB_RELST_HI
2770 BFD_RELOC_PPC_EMB_RELST_HA
2772 BFD_RELOC_PPC_EMB_BIT_FLD
2774 BFD_RELOC_PPC_EMB_RELSDA
2776 BFD_RELOC_PPC_VLE_REL8
2778 BFD_RELOC_PPC_VLE_REL15
2780 BFD_RELOC_PPC_VLE_REL24
2782 BFD_RELOC_PPC_VLE_LO16A
2784 BFD_RELOC_PPC_VLE_LO16D
2786 BFD_RELOC_PPC_VLE_HI16A
2788 BFD_RELOC_PPC_VLE_HI16D
2790 BFD_RELOC_PPC_VLE_HA16A
2792 BFD_RELOC_PPC_VLE_HA16D
2794 BFD_RELOC_PPC_VLE_SDA21
2796 BFD_RELOC_PPC_VLE_SDA21_LO
2798 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2800 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2802 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2804 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2806 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2808 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2810 BFD_RELOC_PPC_16DX_HA
2812 BFD_RELOC_PPC_REL16DX_HA
2814 BFD_RELOC_PPC64_HIGHER
2816 BFD_RELOC_PPC64_HIGHER_S
2818 BFD_RELOC_PPC64_HIGHEST
2820 BFD_RELOC_PPC64_HIGHEST_S
2822 BFD_RELOC_PPC64_TOC16_LO
2824 BFD_RELOC_PPC64_TOC16_HI
2826 BFD_RELOC_PPC64_TOC16_HA
2830 BFD_RELOC_PPC64_PLTGOT16
2832 BFD_RELOC_PPC64_PLTGOT16_LO
2834 BFD_RELOC_PPC64_PLTGOT16_HI
2836 BFD_RELOC_PPC64_PLTGOT16_HA
2838 BFD_RELOC_PPC64_ADDR16_DS
2840 BFD_RELOC_PPC64_ADDR16_LO_DS
2842 BFD_RELOC_PPC64_GOT16_DS
2844 BFD_RELOC_PPC64_GOT16_LO_DS
2846 BFD_RELOC_PPC64_PLT16_LO_DS
2848 BFD_RELOC_PPC64_SECTOFF_DS
2850 BFD_RELOC_PPC64_SECTOFF_LO_DS
2852 BFD_RELOC_PPC64_TOC16_DS
2854 BFD_RELOC_PPC64_TOC16_LO_DS
2856 BFD_RELOC_PPC64_PLTGOT16_DS
2858 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2860 BFD_RELOC_PPC64_ADDR16_HIGH
2862 BFD_RELOC_PPC64_ADDR16_HIGHA
2864 BFD_RELOC_PPC64_REL16_HIGH
2866 BFD_RELOC_PPC64_REL16_HIGHA
2868 BFD_RELOC_PPC64_REL16_HIGHER
2870 BFD_RELOC_PPC64_REL16_HIGHERA
2872 BFD_RELOC_PPC64_REL16_HIGHEST
2874 BFD_RELOC_PPC64_REL16_HIGHESTA
2876 BFD_RELOC_PPC64_ADDR64_LOCAL
2878 BFD_RELOC_PPC64_ENTRY
2880 BFD_RELOC_PPC64_REL24_NOTOC
2882 Power(rs6000) and PowerPC relocations.
2891 BFD_RELOC_PPC_DTPMOD
2893 BFD_RELOC_PPC_TPREL16
2895 BFD_RELOC_PPC_TPREL16_LO
2897 BFD_RELOC_PPC_TPREL16_HI
2899 BFD_RELOC_PPC_TPREL16_HA
2903 BFD_RELOC_PPC_DTPREL16
2905 BFD_RELOC_PPC_DTPREL16_LO
2907 BFD_RELOC_PPC_DTPREL16_HI
2909 BFD_RELOC_PPC_DTPREL16_HA
2911 BFD_RELOC_PPC_DTPREL
2913 BFD_RELOC_PPC_GOT_TLSGD16
2915 BFD_RELOC_PPC_GOT_TLSGD16_LO
2917 BFD_RELOC_PPC_GOT_TLSGD16_HI
2919 BFD_RELOC_PPC_GOT_TLSGD16_HA
2921 BFD_RELOC_PPC_GOT_TLSLD16
2923 BFD_RELOC_PPC_GOT_TLSLD16_LO
2925 BFD_RELOC_PPC_GOT_TLSLD16_HI
2927 BFD_RELOC_PPC_GOT_TLSLD16_HA
2929 BFD_RELOC_PPC_GOT_TPREL16
2931 BFD_RELOC_PPC_GOT_TPREL16_LO
2933 BFD_RELOC_PPC_GOT_TPREL16_HI
2935 BFD_RELOC_PPC_GOT_TPREL16_HA
2937 BFD_RELOC_PPC_GOT_DTPREL16
2939 BFD_RELOC_PPC_GOT_DTPREL16_LO
2941 BFD_RELOC_PPC_GOT_DTPREL16_HI
2943 BFD_RELOC_PPC_GOT_DTPREL16_HA
2945 BFD_RELOC_PPC64_TPREL16_DS
2947 BFD_RELOC_PPC64_TPREL16_LO_DS
2949 BFD_RELOC_PPC64_TPREL16_HIGHER
2951 BFD_RELOC_PPC64_TPREL16_HIGHERA
2953 BFD_RELOC_PPC64_TPREL16_HIGHEST
2955 BFD_RELOC_PPC64_TPREL16_HIGHESTA
2957 BFD_RELOC_PPC64_DTPREL16_DS
2959 BFD_RELOC_PPC64_DTPREL16_LO_DS
2961 BFD_RELOC_PPC64_DTPREL16_HIGHER
2963 BFD_RELOC_PPC64_DTPREL16_HIGHERA
2965 BFD_RELOC_PPC64_DTPREL16_HIGHEST
2967 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
2969 BFD_RELOC_PPC64_TPREL16_HIGH
2971 BFD_RELOC_PPC64_TPREL16_HIGHA
2973 BFD_RELOC_PPC64_DTPREL16_HIGH
2975 BFD_RELOC_PPC64_DTPREL16_HIGHA
2977 PowerPC and PowerPC64 thread-local storage relocations.
2982 IBM 370/390 relocations
2987 The type of reloc used to build a constructor table - at the moment
2988 probably a 32 bit wide absolute relocation, but the target can choose.
2989 It generally does map to one of the other relocation types.
2992 BFD_RELOC_ARM_PCREL_BRANCH
2994 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
2995 not stored in the instruction.
2997 BFD_RELOC_ARM_PCREL_BLX
2999 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3000 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3001 field in the instruction.
3003 BFD_RELOC_THUMB_PCREL_BLX
3005 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3006 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3007 field in the instruction.
3009 BFD_RELOC_ARM_PCREL_CALL
3011 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3013 BFD_RELOC_ARM_PCREL_JUMP
3015 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3018 BFD_RELOC_THUMB_PCREL_BRANCH5
3020 ARM 5-bit pc-relative branch for Branch Future instructions.
3023 BFD_RELOC_THUMB_PCREL_BRANCH7
3025 BFD_RELOC_THUMB_PCREL_BRANCH9
3027 BFD_RELOC_THUMB_PCREL_BRANCH12
3029 BFD_RELOC_THUMB_PCREL_BRANCH20
3031 BFD_RELOC_THUMB_PCREL_BRANCH23
3033 BFD_RELOC_THUMB_PCREL_BRANCH25
3035 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3036 The lowest bit must be zero and is not stored in the instruction.
3037 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3038 "nn" one smaller in all cases. Note further that BRANCH23
3039 corresponds to R_ARM_THM_CALL.
3042 BFD_RELOC_ARM_OFFSET_IMM
3044 12-bit immediate offset, used in ARM-format ldr and str instructions.
3047 BFD_RELOC_ARM_THUMB_OFFSET
3049 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3052 BFD_RELOC_ARM_TARGET1
3054 Pc-relative or absolute relocation depending on target. Used for
3055 entries in .init_array sections.
3057 BFD_RELOC_ARM_ROSEGREL32
3059 Read-only segment base relative address.
3061 BFD_RELOC_ARM_SBREL32
3063 Data segment base relative address.
3065 BFD_RELOC_ARM_TARGET2
3067 This reloc is used for references to RTTI data from exception handling
3068 tables. The actual definition depends on the target. It may be a
3069 pc-relative or some form of GOT-indirect relocation.
3071 BFD_RELOC_ARM_PREL31
3073 31-bit PC relative address.
3079 BFD_RELOC_ARM_MOVW_PCREL
3081 BFD_RELOC_ARM_MOVT_PCREL
3083 BFD_RELOC_ARM_THUMB_MOVW
3085 BFD_RELOC_ARM_THUMB_MOVT
3087 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3089 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3091 Low and High halfword relocations for MOVW and MOVT instructions.
3094 BFD_RELOC_ARM_GOTFUNCDESC
3096 BFD_RELOC_ARM_GOTOFFFUNCDESC
3098 BFD_RELOC_ARM_FUNCDESC
3100 BFD_RELOC_ARM_FUNCDESC_VALUE
3102 BFD_RELOC_ARM_TLS_GD32_FDPIC
3104 BFD_RELOC_ARM_TLS_LDM32_FDPIC
3106 BFD_RELOC_ARM_TLS_IE32_FDPIC
3108 ARM FDPIC specific relocations.
3111 BFD_RELOC_ARM_JUMP_SLOT
3113 BFD_RELOC_ARM_GLOB_DAT
3119 BFD_RELOC_ARM_RELATIVE
3121 BFD_RELOC_ARM_GOTOFF
3125 BFD_RELOC_ARM_GOT_PREL
3127 Relocations for setting up GOTs and PLTs for shared libraries.
3130 BFD_RELOC_ARM_TLS_GD32
3132 BFD_RELOC_ARM_TLS_LDO32
3134 BFD_RELOC_ARM_TLS_LDM32
3136 BFD_RELOC_ARM_TLS_DTPOFF32
3138 BFD_RELOC_ARM_TLS_DTPMOD32
3140 BFD_RELOC_ARM_TLS_TPOFF32
3142 BFD_RELOC_ARM_TLS_IE32
3144 BFD_RELOC_ARM_TLS_LE32
3146 BFD_RELOC_ARM_TLS_GOTDESC
3148 BFD_RELOC_ARM_TLS_CALL
3150 BFD_RELOC_ARM_THM_TLS_CALL
3152 BFD_RELOC_ARM_TLS_DESCSEQ
3154 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3156 BFD_RELOC_ARM_TLS_DESC
3158 ARM thread-local storage relocations.
3161 BFD_RELOC_ARM_ALU_PC_G0_NC
3163 BFD_RELOC_ARM_ALU_PC_G0
3165 BFD_RELOC_ARM_ALU_PC_G1_NC
3167 BFD_RELOC_ARM_ALU_PC_G1
3169 BFD_RELOC_ARM_ALU_PC_G2
3171 BFD_RELOC_ARM_LDR_PC_G0
3173 BFD_RELOC_ARM_LDR_PC_G1
3175 BFD_RELOC_ARM_LDR_PC_G2
3177 BFD_RELOC_ARM_LDRS_PC_G0
3179 BFD_RELOC_ARM_LDRS_PC_G1
3181 BFD_RELOC_ARM_LDRS_PC_G2
3183 BFD_RELOC_ARM_LDC_PC_G0
3185 BFD_RELOC_ARM_LDC_PC_G1
3187 BFD_RELOC_ARM_LDC_PC_G2
3189 BFD_RELOC_ARM_ALU_SB_G0_NC
3191 BFD_RELOC_ARM_ALU_SB_G0
3193 BFD_RELOC_ARM_ALU_SB_G1_NC
3195 BFD_RELOC_ARM_ALU_SB_G1
3197 BFD_RELOC_ARM_ALU_SB_G2
3199 BFD_RELOC_ARM_LDR_SB_G0
3201 BFD_RELOC_ARM_LDR_SB_G1
3203 BFD_RELOC_ARM_LDR_SB_G2
3205 BFD_RELOC_ARM_LDRS_SB_G0
3207 BFD_RELOC_ARM_LDRS_SB_G1
3209 BFD_RELOC_ARM_LDRS_SB_G2
3211 BFD_RELOC_ARM_LDC_SB_G0
3213 BFD_RELOC_ARM_LDC_SB_G1
3215 BFD_RELOC_ARM_LDC_SB_G2
3217 ARM group relocations.
3222 Annotation of BX instructions.
3225 BFD_RELOC_ARM_IRELATIVE
3227 ARM support for STT_GNU_IFUNC.
3230 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3232 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3234 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3236 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3238 Thumb1 relocations to support execute-only code.
3241 BFD_RELOC_ARM_IMMEDIATE
3243 BFD_RELOC_ARM_ADRL_IMMEDIATE
3245 BFD_RELOC_ARM_T32_IMMEDIATE
3247 BFD_RELOC_ARM_T32_ADD_IMM
3249 BFD_RELOC_ARM_T32_IMM12
3251 BFD_RELOC_ARM_T32_ADD_PC12
3253 BFD_RELOC_ARM_SHIFT_IMM
3263 BFD_RELOC_ARM_CP_OFF_IMM
3265 BFD_RELOC_ARM_CP_OFF_IMM_S2
3267 BFD_RELOC_ARM_T32_CP_OFF_IMM
3269 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3271 BFD_RELOC_ARM_ADR_IMM
3273 BFD_RELOC_ARM_LDR_IMM
3275 BFD_RELOC_ARM_LITERAL
3277 BFD_RELOC_ARM_IN_POOL
3279 BFD_RELOC_ARM_OFFSET_IMM8
3281 BFD_RELOC_ARM_T32_OFFSET_U8
3283 BFD_RELOC_ARM_T32_OFFSET_IMM
3285 BFD_RELOC_ARM_HWLITERAL
3287 BFD_RELOC_ARM_THUMB_ADD
3289 BFD_RELOC_ARM_THUMB_IMM
3291 BFD_RELOC_ARM_THUMB_SHIFT
3293 These relocs are only used within the ARM assembler. They are not
3294 (at present) written to any object files.
3297 BFD_RELOC_SH_PCDISP8BY2
3299 BFD_RELOC_SH_PCDISP12BY2
3307 BFD_RELOC_SH_DISP12BY2
3309 BFD_RELOC_SH_DISP12BY4
3311 BFD_RELOC_SH_DISP12BY8
3315 BFD_RELOC_SH_DISP20BY8
3319 BFD_RELOC_SH_IMM4BY2
3321 BFD_RELOC_SH_IMM4BY4
3325 BFD_RELOC_SH_IMM8BY2
3327 BFD_RELOC_SH_IMM8BY4
3329 BFD_RELOC_SH_PCRELIMM8BY2
3331 BFD_RELOC_SH_PCRELIMM8BY4
3333 BFD_RELOC_SH_SWITCH16
3335 BFD_RELOC_SH_SWITCH32
3349 BFD_RELOC_SH_LOOP_START
3351 BFD_RELOC_SH_LOOP_END
3355 BFD_RELOC_SH_GLOB_DAT
3357 BFD_RELOC_SH_JMP_SLOT
3359 BFD_RELOC_SH_RELATIVE
3363 BFD_RELOC_SH_GOT_LOW16
3365 BFD_RELOC_SH_GOT_MEDLOW16
3367 BFD_RELOC_SH_GOT_MEDHI16
3369 BFD_RELOC_SH_GOT_HI16
3371 BFD_RELOC_SH_GOTPLT_LOW16
3373 BFD_RELOC_SH_GOTPLT_MEDLOW16
3375 BFD_RELOC_SH_GOTPLT_MEDHI16
3377 BFD_RELOC_SH_GOTPLT_HI16
3379 BFD_RELOC_SH_PLT_LOW16
3381 BFD_RELOC_SH_PLT_MEDLOW16
3383 BFD_RELOC_SH_PLT_MEDHI16
3385 BFD_RELOC_SH_PLT_HI16
3387 BFD_RELOC_SH_GOTOFF_LOW16
3389 BFD_RELOC_SH_GOTOFF_MEDLOW16
3391 BFD_RELOC_SH_GOTOFF_MEDHI16
3393 BFD_RELOC_SH_GOTOFF_HI16
3395 BFD_RELOC_SH_GOTPC_LOW16
3397 BFD_RELOC_SH_GOTPC_MEDLOW16
3399 BFD_RELOC_SH_GOTPC_MEDHI16
3401 BFD_RELOC_SH_GOTPC_HI16
3405 BFD_RELOC_SH_GLOB_DAT64
3407 BFD_RELOC_SH_JMP_SLOT64
3409 BFD_RELOC_SH_RELATIVE64
3411 BFD_RELOC_SH_GOT10BY4
3413 BFD_RELOC_SH_GOT10BY8
3415 BFD_RELOC_SH_GOTPLT10BY4
3417 BFD_RELOC_SH_GOTPLT10BY8
3419 BFD_RELOC_SH_GOTPLT32
3421 BFD_RELOC_SH_SHMEDIA_CODE
3427 BFD_RELOC_SH_IMMS6BY32
3433 BFD_RELOC_SH_IMMS10BY2
3435 BFD_RELOC_SH_IMMS10BY4
3437 BFD_RELOC_SH_IMMS10BY8
3443 BFD_RELOC_SH_IMM_LOW16
3445 BFD_RELOC_SH_IMM_LOW16_PCREL
3447 BFD_RELOC_SH_IMM_MEDLOW16
3449 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3451 BFD_RELOC_SH_IMM_MEDHI16
3453 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3455 BFD_RELOC_SH_IMM_HI16
3457 BFD_RELOC_SH_IMM_HI16_PCREL
3461 BFD_RELOC_SH_TLS_GD_32
3463 BFD_RELOC_SH_TLS_LD_32
3465 BFD_RELOC_SH_TLS_LDO_32
3467 BFD_RELOC_SH_TLS_IE_32
3469 BFD_RELOC_SH_TLS_LE_32
3471 BFD_RELOC_SH_TLS_DTPMOD32
3473 BFD_RELOC_SH_TLS_DTPOFF32
3475 BFD_RELOC_SH_TLS_TPOFF32
3479 BFD_RELOC_SH_GOTOFF20
3481 BFD_RELOC_SH_GOTFUNCDESC
3483 BFD_RELOC_SH_GOTFUNCDESC20
3485 BFD_RELOC_SH_GOTOFFFUNCDESC
3487 BFD_RELOC_SH_GOTOFFFUNCDESC20
3489 BFD_RELOC_SH_FUNCDESC
3491 Renesas / SuperH SH relocs. Not all of these appear in object files.
3514 BFD_RELOC_ARC_SECTOFF
3516 BFD_RELOC_ARC_S21H_PCREL
3518 BFD_RELOC_ARC_S21W_PCREL
3520 BFD_RELOC_ARC_S25H_PCREL
3522 BFD_RELOC_ARC_S25W_PCREL
3526 BFD_RELOC_ARC_SDA_LDST
3528 BFD_RELOC_ARC_SDA_LDST1
3530 BFD_RELOC_ARC_SDA_LDST2
3532 BFD_RELOC_ARC_SDA16_LD
3534 BFD_RELOC_ARC_SDA16_LD1
3536 BFD_RELOC_ARC_SDA16_LD2
3538 BFD_RELOC_ARC_S13_PCREL
3544 BFD_RELOC_ARC_32_ME_S
3546 BFD_RELOC_ARC_N32_ME
3548 BFD_RELOC_ARC_SECTOFF_ME
3550 BFD_RELOC_ARC_SDA32_ME
3554 BFD_RELOC_AC_SECTOFF_U8
3556 BFD_RELOC_AC_SECTOFF_U8_1
3558 BFD_RELOC_AC_SECTOFF_U8_2
3560 BFD_RELOC_AC_SECTOFF_S9
3562 BFD_RELOC_AC_SECTOFF_S9_1
3564 BFD_RELOC_AC_SECTOFF_S9_2
3566 BFD_RELOC_ARC_SECTOFF_ME_1
3568 BFD_RELOC_ARC_SECTOFF_ME_2
3570 BFD_RELOC_ARC_SECTOFF_1
3572 BFD_RELOC_ARC_SECTOFF_2
3574 BFD_RELOC_ARC_SDA_12
3576 BFD_RELOC_ARC_SDA16_ST2
3578 BFD_RELOC_ARC_32_PCREL
3584 BFD_RELOC_ARC_GOTPC32
3590 BFD_RELOC_ARC_GLOB_DAT
3592 BFD_RELOC_ARC_JMP_SLOT
3594 BFD_RELOC_ARC_RELATIVE
3596 BFD_RELOC_ARC_GOTOFF
3600 BFD_RELOC_ARC_S21W_PCREL_PLT
3602 BFD_RELOC_ARC_S25H_PCREL_PLT
3604 BFD_RELOC_ARC_TLS_DTPMOD
3606 BFD_RELOC_ARC_TLS_TPOFF
3608 BFD_RELOC_ARC_TLS_GD_GOT
3610 BFD_RELOC_ARC_TLS_GD_LD
3612 BFD_RELOC_ARC_TLS_GD_CALL
3614 BFD_RELOC_ARC_TLS_IE_GOT
3616 BFD_RELOC_ARC_TLS_DTPOFF
3618 BFD_RELOC_ARC_TLS_DTPOFF_S9
3620 BFD_RELOC_ARC_TLS_LE_S9
3622 BFD_RELOC_ARC_TLS_LE_32
3624 BFD_RELOC_ARC_S25W_PCREL_PLT
3626 BFD_RELOC_ARC_S21H_PCREL_PLT
3628 BFD_RELOC_ARC_NPS_CMEM16
3630 BFD_RELOC_ARC_JLI_SECTOFF
3635 BFD_RELOC_BFIN_16_IMM
3637 ADI Blackfin 16 bit immediate absolute reloc.
3639 BFD_RELOC_BFIN_16_HIGH
3641 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3643 BFD_RELOC_BFIN_4_PCREL
3645 ADI Blackfin 'a' part of LSETUP.
3647 BFD_RELOC_BFIN_5_PCREL
3651 BFD_RELOC_BFIN_16_LOW
3653 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3655 BFD_RELOC_BFIN_10_PCREL
3659 BFD_RELOC_BFIN_11_PCREL
3661 ADI Blackfin 'b' part of LSETUP.
3663 BFD_RELOC_BFIN_12_PCREL_JUMP
3667 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3669 ADI Blackfin Short jump, pcrel.
3671 BFD_RELOC_BFIN_24_PCREL_CALL_X
3673 ADI Blackfin Call.x not implemented.
3675 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3677 ADI Blackfin Long Jump pcrel.
3679 BFD_RELOC_BFIN_GOT17M4
3681 BFD_RELOC_BFIN_GOTHI
3683 BFD_RELOC_BFIN_GOTLO
3685 BFD_RELOC_BFIN_FUNCDESC
3687 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3689 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3691 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3693 BFD_RELOC_BFIN_FUNCDESC_VALUE
3695 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3697 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3699 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3701 BFD_RELOC_BFIN_GOTOFF17M4
3703 BFD_RELOC_BFIN_GOTOFFHI
3705 BFD_RELOC_BFIN_GOTOFFLO
3707 ADI Blackfin FD-PIC relocations.
3711 ADI Blackfin GOT relocation.
3713 BFD_RELOC_BFIN_PLTPC
3715 ADI Blackfin PLTPC relocation.
3717 BFD_ARELOC_BFIN_PUSH
3719 ADI Blackfin arithmetic relocation.
3721 BFD_ARELOC_BFIN_CONST
3723 ADI Blackfin arithmetic relocation.
3727 ADI Blackfin arithmetic relocation.
3731 ADI Blackfin arithmetic relocation.
3733 BFD_ARELOC_BFIN_MULT
3735 ADI Blackfin arithmetic relocation.
3739 ADI Blackfin arithmetic relocation.
3743 ADI Blackfin arithmetic relocation.
3745 BFD_ARELOC_BFIN_LSHIFT
3747 ADI Blackfin arithmetic relocation.
3749 BFD_ARELOC_BFIN_RSHIFT
3751 ADI Blackfin arithmetic relocation.
3755 ADI Blackfin arithmetic relocation.
3759 ADI Blackfin arithmetic relocation.
3763 ADI Blackfin arithmetic relocation.
3765 BFD_ARELOC_BFIN_LAND
3767 ADI Blackfin arithmetic relocation.
3771 ADI Blackfin arithmetic relocation.
3775 ADI Blackfin arithmetic relocation.
3779 ADI Blackfin arithmetic relocation.
3781 BFD_ARELOC_BFIN_COMP
3783 ADI Blackfin arithmetic relocation.
3785 BFD_ARELOC_BFIN_PAGE
3787 ADI Blackfin arithmetic relocation.
3789 BFD_ARELOC_BFIN_HWPAGE
3791 ADI Blackfin arithmetic relocation.
3793 BFD_ARELOC_BFIN_ADDR
3795 ADI Blackfin arithmetic relocation.
3798 BFD_RELOC_D10V_10_PCREL_R
3800 Mitsubishi D10V relocs.
3801 This is a 10-bit reloc with the right 2 bits
3804 BFD_RELOC_D10V_10_PCREL_L
3806 Mitsubishi D10V relocs.
3807 This is a 10-bit reloc with the right 2 bits
3808 assumed to be 0. This is the same as the previous reloc
3809 except it is in the left container, i.e.,
3810 shifted left 15 bits.
3814 This is an 18-bit reloc with the right 2 bits
3817 BFD_RELOC_D10V_18_PCREL
3819 This is an 18-bit reloc with the right 2 bits
3825 Mitsubishi D30V relocs.
3826 This is a 6-bit absolute reloc.
3828 BFD_RELOC_D30V_9_PCREL
3830 This is a 6-bit pc-relative reloc with
3831 the right 3 bits assumed to be 0.
3833 BFD_RELOC_D30V_9_PCREL_R
3835 This is a 6-bit pc-relative reloc with
3836 the right 3 bits assumed to be 0. Same
3837 as the previous reloc but on the right side
3842 This is a 12-bit absolute reloc with the
3843 right 3 bitsassumed to be 0.
3845 BFD_RELOC_D30V_15_PCREL
3847 This is a 12-bit pc-relative reloc with
3848 the right 3 bits assumed to be 0.
3850 BFD_RELOC_D30V_15_PCREL_R
3852 This is a 12-bit pc-relative reloc with
3853 the right 3 bits assumed to be 0. Same
3854 as the previous reloc but on the right side
3859 This is an 18-bit absolute reloc with
3860 the right 3 bits assumed to be 0.
3862 BFD_RELOC_D30V_21_PCREL
3864 This is an 18-bit pc-relative reloc with
3865 the right 3 bits assumed to be 0.
3867 BFD_RELOC_D30V_21_PCREL_R
3869 This is an 18-bit pc-relative reloc with
3870 the right 3 bits assumed to be 0. Same
3871 as the previous reloc but on the right side
3876 This is a 32-bit absolute reloc.
3878 BFD_RELOC_D30V_32_PCREL
3880 This is a 32-bit pc-relative reloc.
3883 BFD_RELOC_DLX_HI16_S
3898 BFD_RELOC_M32C_RL_JUMP
3900 BFD_RELOC_M32C_RL_1ADDR
3902 BFD_RELOC_M32C_RL_2ADDR
3904 Renesas M16C/M32C Relocations.
3909 Renesas M32R (formerly Mitsubishi M32R) relocs.
3910 This is a 24 bit absolute address.
3912 BFD_RELOC_M32R_10_PCREL
3914 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3916 BFD_RELOC_M32R_18_PCREL
3918 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3920 BFD_RELOC_M32R_26_PCREL
3922 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3924 BFD_RELOC_M32R_HI16_ULO
3926 This is a 16-bit reloc containing the high 16 bits of an address
3927 used when the lower 16 bits are treated as unsigned.
3929 BFD_RELOC_M32R_HI16_SLO
3931 This is a 16-bit reloc containing the high 16 bits of an address
3932 used when the lower 16 bits are treated as signed.
3936 This is a 16-bit reloc containing the lower 16 bits of an address.
3938 BFD_RELOC_M32R_SDA16
3940 This is a 16-bit reloc containing the small data area offset for use in
3941 add3, load, and store instructions.
3943 BFD_RELOC_M32R_GOT24
3945 BFD_RELOC_M32R_26_PLTREL
3949 BFD_RELOC_M32R_GLOB_DAT
3951 BFD_RELOC_M32R_JMP_SLOT
3953 BFD_RELOC_M32R_RELATIVE
3955 BFD_RELOC_M32R_GOTOFF
3957 BFD_RELOC_M32R_GOTOFF_HI_ULO
3959 BFD_RELOC_M32R_GOTOFF_HI_SLO
3961 BFD_RELOC_M32R_GOTOFF_LO
3963 BFD_RELOC_M32R_GOTPC24
3965 BFD_RELOC_M32R_GOT16_HI_ULO
3967 BFD_RELOC_M32R_GOT16_HI_SLO
3969 BFD_RELOC_M32R_GOT16_LO
3971 BFD_RELOC_M32R_GOTPC_HI_ULO
3973 BFD_RELOC_M32R_GOTPC_HI_SLO
3975 BFD_RELOC_M32R_GOTPC_LO
3984 This is a 20 bit absolute address.
3986 BFD_RELOC_NDS32_9_PCREL
3988 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
3990 BFD_RELOC_NDS32_WORD_9_PCREL
3992 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
3994 BFD_RELOC_NDS32_15_PCREL
3996 This is an 15-bit reloc with the right 1 bit assumed to be 0.
3998 BFD_RELOC_NDS32_17_PCREL
4000 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4002 BFD_RELOC_NDS32_25_PCREL
4004 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4006 BFD_RELOC_NDS32_HI20
4008 This is a 20-bit reloc containing the high 20 bits of an address
4009 used with the lower 12 bits
4011 BFD_RELOC_NDS32_LO12S3
4013 This is a 12-bit reloc containing the lower 12 bits of an address
4014 then shift right by 3. This is used with ldi,sdi...
4016 BFD_RELOC_NDS32_LO12S2
4018 This is a 12-bit reloc containing the lower 12 bits of an address
4019 then shift left by 2. This is used with lwi,swi...
4021 BFD_RELOC_NDS32_LO12S1
4023 This is a 12-bit reloc containing the lower 12 bits of an address
4024 then shift left by 1. This is used with lhi,shi...
4026 BFD_RELOC_NDS32_LO12S0
4028 This is a 12-bit reloc containing the lower 12 bits of an address
4029 then shift left by 0. This is used with lbisbi...
4031 BFD_RELOC_NDS32_LO12S0_ORI
4033 This is a 12-bit reloc containing the lower 12 bits of an address
4034 then shift left by 0. This is only used with branch relaxations
4036 BFD_RELOC_NDS32_SDA15S3
4038 This is a 15-bit reloc containing the small data area 18-bit signed offset
4039 and shift left by 3 for use in ldi, sdi...
4041 BFD_RELOC_NDS32_SDA15S2
4043 This is a 15-bit reloc containing the small data area 17-bit signed offset
4044 and shift left by 2 for use in lwi, swi...
4046 BFD_RELOC_NDS32_SDA15S1
4048 This is a 15-bit reloc containing the small data area 16-bit signed offset
4049 and shift left by 1 for use in lhi, shi...
4051 BFD_RELOC_NDS32_SDA15S0
4053 This is a 15-bit reloc containing the small data area 15-bit signed offset
4054 and shift left by 0 for use in lbi, sbi...
4056 BFD_RELOC_NDS32_SDA16S3
4058 This is a 16-bit reloc containing the small data area 16-bit signed offset
4061 BFD_RELOC_NDS32_SDA17S2
4063 This is a 17-bit reloc containing the small data area 17-bit signed offset
4064 and shift left by 2 for use in lwi.gp, swi.gp...
4066 BFD_RELOC_NDS32_SDA18S1
4068 This is a 18-bit reloc containing the small data area 18-bit signed offset
4069 and shift left by 1 for use in lhi.gp, shi.gp...
4071 BFD_RELOC_NDS32_SDA19S0
4073 This is a 19-bit reloc containing the small data area 19-bit signed offset
4074 and shift left by 0 for use in lbi.gp, sbi.gp...
4076 BFD_RELOC_NDS32_GOT20
4078 BFD_RELOC_NDS32_9_PLTREL
4080 BFD_RELOC_NDS32_25_PLTREL
4082 BFD_RELOC_NDS32_COPY
4084 BFD_RELOC_NDS32_GLOB_DAT
4086 BFD_RELOC_NDS32_JMP_SLOT
4088 BFD_RELOC_NDS32_RELATIVE
4090 BFD_RELOC_NDS32_GOTOFF
4092 BFD_RELOC_NDS32_GOTOFF_HI20
4094 BFD_RELOC_NDS32_GOTOFF_LO12
4096 BFD_RELOC_NDS32_GOTPC20
4098 BFD_RELOC_NDS32_GOT_HI20
4100 BFD_RELOC_NDS32_GOT_LO12
4102 BFD_RELOC_NDS32_GOTPC_HI20
4104 BFD_RELOC_NDS32_GOTPC_LO12
4108 BFD_RELOC_NDS32_INSN16
4110 BFD_RELOC_NDS32_LABEL
4112 BFD_RELOC_NDS32_LONGCALL1
4114 BFD_RELOC_NDS32_LONGCALL2
4116 BFD_RELOC_NDS32_LONGCALL3
4118 BFD_RELOC_NDS32_LONGJUMP1
4120 BFD_RELOC_NDS32_LONGJUMP2
4122 BFD_RELOC_NDS32_LONGJUMP3
4124 BFD_RELOC_NDS32_LOADSTORE
4126 BFD_RELOC_NDS32_9_FIXED
4128 BFD_RELOC_NDS32_15_FIXED
4130 BFD_RELOC_NDS32_17_FIXED
4132 BFD_RELOC_NDS32_25_FIXED
4134 BFD_RELOC_NDS32_LONGCALL4
4136 BFD_RELOC_NDS32_LONGCALL5
4138 BFD_RELOC_NDS32_LONGCALL6
4140 BFD_RELOC_NDS32_LONGJUMP4
4142 BFD_RELOC_NDS32_LONGJUMP5
4144 BFD_RELOC_NDS32_LONGJUMP6
4146 BFD_RELOC_NDS32_LONGJUMP7
4150 BFD_RELOC_NDS32_PLTREL_HI20
4152 BFD_RELOC_NDS32_PLTREL_LO12
4154 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4156 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4160 BFD_RELOC_NDS32_SDA12S2_DP
4162 BFD_RELOC_NDS32_SDA12S2_SP
4164 BFD_RELOC_NDS32_LO12S2_DP
4166 BFD_RELOC_NDS32_LO12S2_SP
4170 BFD_RELOC_NDS32_DWARF2_OP1
4172 BFD_RELOC_NDS32_DWARF2_OP2
4174 BFD_RELOC_NDS32_DWARF2_LEB
4176 for dwarf2 debug_line.
4178 BFD_RELOC_NDS32_UPDATE_TA
4180 for eliminate 16-bit instructions
4182 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4184 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4186 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4188 BFD_RELOC_NDS32_GOT_LO15
4190 BFD_RELOC_NDS32_GOT_LO19
4192 BFD_RELOC_NDS32_GOTOFF_LO15
4194 BFD_RELOC_NDS32_GOTOFF_LO19
4196 BFD_RELOC_NDS32_GOT15S2
4198 BFD_RELOC_NDS32_GOT17S2
4200 for PIC object relaxation
4205 This is a 5 bit absolute address.
4207 BFD_RELOC_NDS32_10_UPCREL
4209 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4211 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4213 If fp were omitted, fp can used as another gp.
4215 BFD_RELOC_NDS32_RELAX_ENTRY
4217 BFD_RELOC_NDS32_GOT_SUFF
4219 BFD_RELOC_NDS32_GOTOFF_SUFF
4221 BFD_RELOC_NDS32_PLT_GOT_SUFF
4223 BFD_RELOC_NDS32_MULCALL_SUFF
4227 BFD_RELOC_NDS32_PTR_COUNT
4229 BFD_RELOC_NDS32_PTR_RESOLVED
4231 BFD_RELOC_NDS32_PLTBLOCK
4233 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4235 BFD_RELOC_NDS32_RELAX_REGION_END
4237 BFD_RELOC_NDS32_MINUEND
4239 BFD_RELOC_NDS32_SUBTRAHEND
4241 BFD_RELOC_NDS32_DIFF8
4243 BFD_RELOC_NDS32_DIFF16
4245 BFD_RELOC_NDS32_DIFF32
4247 BFD_RELOC_NDS32_DIFF_ULEB128
4249 BFD_RELOC_NDS32_EMPTY
4251 relaxation relative relocation types
4253 BFD_RELOC_NDS32_25_ABS
4255 This is a 25 bit absolute address.
4257 BFD_RELOC_NDS32_DATA
4259 BFD_RELOC_NDS32_TRAN
4261 BFD_RELOC_NDS32_17IFC_PCREL
4263 BFD_RELOC_NDS32_10IFCU_PCREL
4265 For ex9 and ifc using.
4267 BFD_RELOC_NDS32_TPOFF
4269 BFD_RELOC_NDS32_GOTTPOFF
4271 BFD_RELOC_NDS32_TLS_LE_HI20
4273 BFD_RELOC_NDS32_TLS_LE_LO12
4275 BFD_RELOC_NDS32_TLS_LE_20
4277 BFD_RELOC_NDS32_TLS_LE_15S0
4279 BFD_RELOC_NDS32_TLS_LE_15S1
4281 BFD_RELOC_NDS32_TLS_LE_15S2
4283 BFD_RELOC_NDS32_TLS_LE_ADD
4285 BFD_RELOC_NDS32_TLS_LE_LS
4287 BFD_RELOC_NDS32_TLS_IE_HI20
4289 BFD_RELOC_NDS32_TLS_IE_LO12
4291 BFD_RELOC_NDS32_TLS_IE_LO12S2
4293 BFD_RELOC_NDS32_TLS_IEGP_HI20
4295 BFD_RELOC_NDS32_TLS_IEGP_LO12
4297 BFD_RELOC_NDS32_TLS_IEGP_LO12S2
4299 BFD_RELOC_NDS32_TLS_IEGP_LW
4301 BFD_RELOC_NDS32_TLS_DESC
4303 BFD_RELOC_NDS32_TLS_DESC_HI20
4305 BFD_RELOC_NDS32_TLS_DESC_LO12
4307 BFD_RELOC_NDS32_TLS_DESC_20
4309 BFD_RELOC_NDS32_TLS_DESC_SDA17S2
4311 BFD_RELOC_NDS32_TLS_DESC_ADD
4313 BFD_RELOC_NDS32_TLS_DESC_FUNC
4315 BFD_RELOC_NDS32_TLS_DESC_CALL
4317 BFD_RELOC_NDS32_TLS_DESC_MEM
4319 BFD_RELOC_NDS32_REMOVE
4321 BFD_RELOC_NDS32_GROUP
4327 For floating load store relaxation.
4331 BFD_RELOC_V850_9_PCREL
4333 This is a 9-bit reloc
4335 BFD_RELOC_V850_22_PCREL
4337 This is a 22-bit reloc
4340 BFD_RELOC_V850_SDA_16_16_OFFSET
4342 This is a 16 bit offset from the short data area pointer.
4344 BFD_RELOC_V850_SDA_15_16_OFFSET
4346 This is a 16 bit offset (of which only 15 bits are used) from the
4347 short data area pointer.
4349 BFD_RELOC_V850_ZDA_16_16_OFFSET
4351 This is a 16 bit offset from the zero data area pointer.
4353 BFD_RELOC_V850_ZDA_15_16_OFFSET
4355 This is a 16 bit offset (of which only 15 bits are used) from the
4356 zero data area pointer.
4358 BFD_RELOC_V850_TDA_6_8_OFFSET
4360 This is an 8 bit offset (of which only 6 bits are used) from the
4361 tiny data area pointer.
4363 BFD_RELOC_V850_TDA_7_8_OFFSET
4365 This is an 8bit offset (of which only 7 bits are used) from the tiny
4368 BFD_RELOC_V850_TDA_7_7_OFFSET
4370 This is a 7 bit offset from the tiny data area pointer.
4372 BFD_RELOC_V850_TDA_16_16_OFFSET
4374 This is a 16 bit offset from the tiny data area pointer.
4377 BFD_RELOC_V850_TDA_4_5_OFFSET
4379 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4382 BFD_RELOC_V850_TDA_4_4_OFFSET
4384 This is a 4 bit offset from the tiny data area pointer.
4386 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4388 This is a 16 bit offset from the short data area pointer, with the
4389 bits placed non-contiguously in the instruction.
4391 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4393 This is a 16 bit offset from the zero data area pointer, with the
4394 bits placed non-contiguously in the instruction.
4396 BFD_RELOC_V850_CALLT_6_7_OFFSET
4398 This is a 6 bit offset from the call table base pointer.
4400 BFD_RELOC_V850_CALLT_16_16_OFFSET
4402 This is a 16 bit offset from the call table base pointer.
4404 BFD_RELOC_V850_LONGCALL
4406 Used for relaxing indirect function calls.
4408 BFD_RELOC_V850_LONGJUMP
4410 Used for relaxing indirect jumps.
4412 BFD_RELOC_V850_ALIGN
4414 Used to maintain alignment whilst relaxing.
4416 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4418 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4421 BFD_RELOC_V850_16_PCREL
4423 This is a 16-bit reloc.
4425 BFD_RELOC_V850_17_PCREL
4427 This is a 17-bit reloc.
4431 This is a 23-bit reloc.
4433 BFD_RELOC_V850_32_PCREL
4435 This is a 32-bit reloc.
4437 BFD_RELOC_V850_32_ABS
4439 This is a 32-bit reloc.
4441 BFD_RELOC_V850_16_SPLIT_OFFSET
4443 This is a 16-bit reloc.
4445 BFD_RELOC_V850_16_S1
4447 This is a 16-bit reloc.
4449 BFD_RELOC_V850_LO16_S1
4451 Low 16 bits. 16 bit shifted by 1.
4453 BFD_RELOC_V850_CALLT_15_16_OFFSET
4455 This is a 16 bit offset from the call table base pointer.
4457 BFD_RELOC_V850_32_GOTPCREL
4461 BFD_RELOC_V850_16_GOT
4465 BFD_RELOC_V850_32_GOT
4469 BFD_RELOC_V850_22_PLT_PCREL
4473 BFD_RELOC_V850_32_PLT_PCREL
4481 BFD_RELOC_V850_GLOB_DAT
4485 BFD_RELOC_V850_JMP_SLOT
4489 BFD_RELOC_V850_RELATIVE
4493 BFD_RELOC_V850_16_GOTOFF
4497 BFD_RELOC_V850_32_GOTOFF
4512 This is a 8bit DP reloc for the tms320c30, where the most
4513 significant 8 bits of a 24 bit word are placed into the least
4514 significant 8 bits of the opcode.
4517 BFD_RELOC_TIC54X_PARTLS7
4519 This is a 7bit reloc for the tms320c54x, where the least
4520 significant 7 bits of a 16 bit word are placed into the least
4521 significant 7 bits of the opcode.
4524 BFD_RELOC_TIC54X_PARTMS9
4526 This is a 9bit DP reloc for the tms320c54x, where the most
4527 significant 9 bits of a 16 bit word are placed into the least
4528 significant 9 bits of the opcode.
4533 This is an extended address 23-bit reloc for the tms320c54x.
4536 BFD_RELOC_TIC54X_16_OF_23
4538 This is a 16-bit reloc for the tms320c54x, where the least
4539 significant 16 bits of a 23-bit extended address are placed into
4543 BFD_RELOC_TIC54X_MS7_OF_23
4545 This is a reloc for the tms320c54x, where the most
4546 significant 7 bits of a 23-bit extended address are placed into
4550 BFD_RELOC_C6000_PCR_S21
4552 BFD_RELOC_C6000_PCR_S12
4554 BFD_RELOC_C6000_PCR_S10
4556 BFD_RELOC_C6000_PCR_S7
4558 BFD_RELOC_C6000_ABS_S16
4560 BFD_RELOC_C6000_ABS_L16
4562 BFD_RELOC_C6000_ABS_H16
4564 BFD_RELOC_C6000_SBR_U15_B
4566 BFD_RELOC_C6000_SBR_U15_H
4568 BFD_RELOC_C6000_SBR_U15_W
4570 BFD_RELOC_C6000_SBR_S16
4572 BFD_RELOC_C6000_SBR_L16_B
4574 BFD_RELOC_C6000_SBR_L16_H
4576 BFD_RELOC_C6000_SBR_L16_W
4578 BFD_RELOC_C6000_SBR_H16_B
4580 BFD_RELOC_C6000_SBR_H16_H
4582 BFD_RELOC_C6000_SBR_H16_W
4584 BFD_RELOC_C6000_SBR_GOT_U15_W
4586 BFD_RELOC_C6000_SBR_GOT_L16_W
4588 BFD_RELOC_C6000_SBR_GOT_H16_W
4590 BFD_RELOC_C6000_DSBT_INDEX
4592 BFD_RELOC_C6000_PREL31
4594 BFD_RELOC_C6000_COPY
4596 BFD_RELOC_C6000_JUMP_SLOT
4598 BFD_RELOC_C6000_EHTYPE
4600 BFD_RELOC_C6000_PCR_H16
4602 BFD_RELOC_C6000_PCR_L16
4604 BFD_RELOC_C6000_ALIGN
4606 BFD_RELOC_C6000_FPHEAD
4608 BFD_RELOC_C6000_NOCMP
4610 TMS320C6000 relocations.
4615 This is a 48 bit reloc for the FR30 that stores 32 bits.
4619 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4622 BFD_RELOC_FR30_6_IN_4
4624 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4627 BFD_RELOC_FR30_8_IN_8
4629 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4632 BFD_RELOC_FR30_9_IN_8
4634 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4637 BFD_RELOC_FR30_10_IN_8
4639 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4642 BFD_RELOC_FR30_9_PCREL
4644 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4645 short offset into 8 bits.
4647 BFD_RELOC_FR30_12_PCREL
4649 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4650 short offset into 11 bits.
4653 BFD_RELOC_MCORE_PCREL_IMM8BY4
4655 BFD_RELOC_MCORE_PCREL_IMM11BY2
4657 BFD_RELOC_MCORE_PCREL_IMM4BY2
4659 BFD_RELOC_MCORE_PCREL_32
4661 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4665 Motorola Mcore relocations.
4674 BFD_RELOC_MEP_PCREL8A2
4676 BFD_RELOC_MEP_PCREL12A2
4678 BFD_RELOC_MEP_PCREL17A2
4680 BFD_RELOC_MEP_PCREL24A2
4682 BFD_RELOC_MEP_PCABS24A2
4694 BFD_RELOC_MEP_TPREL7
4696 BFD_RELOC_MEP_TPREL7A2
4698 BFD_RELOC_MEP_TPREL7A4
4700 BFD_RELOC_MEP_UIMM24
4702 BFD_RELOC_MEP_ADDR24A4
4704 BFD_RELOC_MEP_GNU_VTINHERIT
4706 BFD_RELOC_MEP_GNU_VTENTRY
4708 Toshiba Media Processor Relocations.
4712 BFD_RELOC_METAG_HIADDR16
4714 BFD_RELOC_METAG_LOADDR16
4716 BFD_RELOC_METAG_RELBRANCH
4718 BFD_RELOC_METAG_GETSETOFF
4720 BFD_RELOC_METAG_HIOG
4722 BFD_RELOC_METAG_LOOG
4724 BFD_RELOC_METAG_REL8
4726 BFD_RELOC_METAG_REL16
4728 BFD_RELOC_METAG_HI16_GOTOFF
4730 BFD_RELOC_METAG_LO16_GOTOFF
4732 BFD_RELOC_METAG_GETSET_GOTOFF
4734 BFD_RELOC_METAG_GETSET_GOT
4736 BFD_RELOC_METAG_HI16_GOTPC
4738 BFD_RELOC_METAG_LO16_GOTPC
4740 BFD_RELOC_METAG_HI16_PLT
4742 BFD_RELOC_METAG_LO16_PLT
4744 BFD_RELOC_METAG_RELBRANCH_PLT
4746 BFD_RELOC_METAG_GOTOFF
4750 BFD_RELOC_METAG_COPY
4752 BFD_RELOC_METAG_JMP_SLOT
4754 BFD_RELOC_METAG_RELATIVE
4756 BFD_RELOC_METAG_GLOB_DAT
4758 BFD_RELOC_METAG_TLS_GD
4760 BFD_RELOC_METAG_TLS_LDM
4762 BFD_RELOC_METAG_TLS_LDO_HI16
4764 BFD_RELOC_METAG_TLS_LDO_LO16
4766 BFD_RELOC_METAG_TLS_LDO
4768 BFD_RELOC_METAG_TLS_IE
4770 BFD_RELOC_METAG_TLS_IENONPIC
4772 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4774 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4776 BFD_RELOC_METAG_TLS_TPOFF
4778 BFD_RELOC_METAG_TLS_DTPMOD
4780 BFD_RELOC_METAG_TLS_DTPOFF
4782 BFD_RELOC_METAG_TLS_LE
4784 BFD_RELOC_METAG_TLS_LE_HI16
4786 BFD_RELOC_METAG_TLS_LE_LO16
4788 Imagination Technologies Meta relocations.
4793 BFD_RELOC_MMIX_GETA_1
4795 BFD_RELOC_MMIX_GETA_2
4797 BFD_RELOC_MMIX_GETA_3
4799 These are relocations for the GETA instruction.
4801 BFD_RELOC_MMIX_CBRANCH
4803 BFD_RELOC_MMIX_CBRANCH_J
4805 BFD_RELOC_MMIX_CBRANCH_1
4807 BFD_RELOC_MMIX_CBRANCH_2
4809 BFD_RELOC_MMIX_CBRANCH_3
4811 These are relocations for a conditional branch instruction.
4813 BFD_RELOC_MMIX_PUSHJ
4815 BFD_RELOC_MMIX_PUSHJ_1
4817 BFD_RELOC_MMIX_PUSHJ_2
4819 BFD_RELOC_MMIX_PUSHJ_3
4821 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4823 These are relocations for the PUSHJ instruction.
4827 BFD_RELOC_MMIX_JMP_1
4829 BFD_RELOC_MMIX_JMP_2
4831 BFD_RELOC_MMIX_JMP_3
4833 These are relocations for the JMP instruction.
4835 BFD_RELOC_MMIX_ADDR19
4837 This is a relocation for a relative address as in a GETA instruction or
4840 BFD_RELOC_MMIX_ADDR27
4842 This is a relocation for a relative address as in a JMP instruction.
4844 BFD_RELOC_MMIX_REG_OR_BYTE
4846 This is a relocation for an instruction field that may be a general
4847 register or a value 0..255.
4851 This is a relocation for an instruction field that may be a general
4854 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4856 This is a relocation for two instruction fields holding a register and
4857 an offset, the equivalent of the relocation.
4859 BFD_RELOC_MMIX_LOCAL
4861 This relocation is an assertion that the expression is not allocated as
4862 a global register. It does not modify contents.
4865 BFD_RELOC_AVR_7_PCREL
4867 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4868 short offset into 7 bits.
4870 BFD_RELOC_AVR_13_PCREL
4872 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4873 short offset into 12 bits.
4877 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4878 program memory address) into 16 bits.
4880 BFD_RELOC_AVR_LO8_LDI
4882 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4883 data memory address) into 8 bit immediate value of LDI insn.
4885 BFD_RELOC_AVR_HI8_LDI
4887 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4888 of data memory address) into 8 bit immediate value of LDI insn.
4890 BFD_RELOC_AVR_HH8_LDI
4892 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4893 of program memory address) into 8 bit immediate value of LDI insn.
4895 BFD_RELOC_AVR_MS8_LDI
4897 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4898 of 32 bit value) into 8 bit immediate value of LDI insn.
4900 BFD_RELOC_AVR_LO8_LDI_NEG
4902 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4903 (usually data memory address) into 8 bit immediate value of SUBI insn.
4905 BFD_RELOC_AVR_HI8_LDI_NEG
4907 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4908 (high 8 bit of data memory address) into 8 bit immediate value of
4911 BFD_RELOC_AVR_HH8_LDI_NEG
4913 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4914 (most high 8 bit of program memory address) into 8 bit immediate value
4915 of LDI or SUBI insn.
4917 BFD_RELOC_AVR_MS8_LDI_NEG
4919 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4920 of 32 bit value) into 8 bit immediate value of LDI insn.
4922 BFD_RELOC_AVR_LO8_LDI_PM
4924 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4925 command address) into 8 bit immediate value of LDI insn.
4927 BFD_RELOC_AVR_LO8_LDI_GS
4929 This is a 16 bit reloc for the AVR that stores 8 bit value
4930 (command address) into 8 bit immediate value of LDI insn. If the address
4931 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4934 BFD_RELOC_AVR_HI8_LDI_PM
4936 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4937 of command address) into 8 bit immediate value of LDI insn.
4939 BFD_RELOC_AVR_HI8_LDI_GS
4941 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4942 of command address) into 8 bit immediate value of LDI insn. If the address
4943 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4946 BFD_RELOC_AVR_HH8_LDI_PM
4948 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4949 of command address) into 8 bit immediate value of LDI insn.
4951 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4953 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4954 (usually command address) into 8 bit immediate value of SUBI insn.
4956 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4958 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4959 (high 8 bit of 16 bit command address) into 8 bit immediate value
4962 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4964 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4965 (high 6 bit of 22 bit command address) into 8 bit immediate
4970 This is a 32 bit reloc for the AVR that stores 23 bit value
4975 This is a 16 bit reloc for the AVR that stores all needed bits
4976 for absolute addressing with ldi with overflow check to linktime
4980 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4983 BFD_RELOC_AVR_6_ADIW
4985 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4990 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4991 in .byte lo8(symbol)
4995 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
4996 in .byte hi8(symbol)
5000 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5001 in .byte hlo8(symbol)
5005 BFD_RELOC_AVR_DIFF16
5007 BFD_RELOC_AVR_DIFF32
5009 AVR relocations to mark the difference of two local symbols.
5010 These are only needed to support linker relaxation and can be ignored
5011 when not relaxing. The field is set to the value of the difference
5012 assuming no relaxation. The relocation encodes the position of the
5013 second symbol so the linker can determine whether to adjust the field
5016 BFD_RELOC_AVR_LDS_STS_16
5018 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5019 lds and sts instructions supported only tiny core.
5023 This is a 6 bit reloc for the AVR that stores an I/O register
5024 number for the IN and OUT instructions
5028 This is a 5 bit reloc for the AVR that stores an I/O register
5029 number for the SBIC, SBIS, SBI and CBI instructions
5032 BFD_RELOC_RISCV_HI20
5034 BFD_RELOC_RISCV_PCREL_HI20
5036 BFD_RELOC_RISCV_PCREL_LO12_I
5038 BFD_RELOC_RISCV_PCREL_LO12_S
5040 BFD_RELOC_RISCV_LO12_I
5042 BFD_RELOC_RISCV_LO12_S
5044 BFD_RELOC_RISCV_GPREL12_I
5046 BFD_RELOC_RISCV_GPREL12_S
5048 BFD_RELOC_RISCV_TPREL_HI20
5050 BFD_RELOC_RISCV_TPREL_LO12_I
5052 BFD_RELOC_RISCV_TPREL_LO12_S
5054 BFD_RELOC_RISCV_TPREL_ADD
5056 BFD_RELOC_RISCV_CALL
5058 BFD_RELOC_RISCV_CALL_PLT
5060 BFD_RELOC_RISCV_ADD8
5062 BFD_RELOC_RISCV_ADD16
5064 BFD_RELOC_RISCV_ADD32
5066 BFD_RELOC_RISCV_ADD64
5068 BFD_RELOC_RISCV_SUB8
5070 BFD_RELOC_RISCV_SUB16
5072 BFD_RELOC_RISCV_SUB32
5074 BFD_RELOC_RISCV_SUB64
5076 BFD_RELOC_RISCV_GOT_HI20
5078 BFD_RELOC_RISCV_TLS_GOT_HI20
5080 BFD_RELOC_RISCV_TLS_GD_HI20
5084 BFD_RELOC_RISCV_TLS_DTPMOD32
5086 BFD_RELOC_RISCV_TLS_DTPREL32
5088 BFD_RELOC_RISCV_TLS_DTPMOD64
5090 BFD_RELOC_RISCV_TLS_DTPREL64
5092 BFD_RELOC_RISCV_TLS_TPREL32
5094 BFD_RELOC_RISCV_TLS_TPREL64
5096 BFD_RELOC_RISCV_ALIGN
5098 BFD_RELOC_RISCV_RVC_BRANCH
5100 BFD_RELOC_RISCV_RVC_JUMP
5102 BFD_RELOC_RISCV_RVC_LUI
5104 BFD_RELOC_RISCV_GPREL_I
5106 BFD_RELOC_RISCV_GPREL_S
5108 BFD_RELOC_RISCV_TPREL_I
5110 BFD_RELOC_RISCV_TPREL_S
5112 BFD_RELOC_RISCV_RELAX
5116 BFD_RELOC_RISCV_SUB6
5118 BFD_RELOC_RISCV_SET6
5120 BFD_RELOC_RISCV_SET8
5122 BFD_RELOC_RISCV_SET16
5124 BFD_RELOC_RISCV_SET32
5126 BFD_RELOC_RISCV_32_PCREL
5133 BFD_RELOC_RL78_NEG16
5135 BFD_RELOC_RL78_NEG24
5137 BFD_RELOC_RL78_NEG32
5139 BFD_RELOC_RL78_16_OP
5141 BFD_RELOC_RL78_24_OP
5143 BFD_RELOC_RL78_32_OP
5151 BFD_RELOC_RL78_DIR3U_PCREL
5155 BFD_RELOC_RL78_GPRELB
5157 BFD_RELOC_RL78_GPRELW
5159 BFD_RELOC_RL78_GPRELL
5163 BFD_RELOC_RL78_OP_SUBTRACT
5165 BFD_RELOC_RL78_OP_NEG
5167 BFD_RELOC_RL78_OP_AND
5169 BFD_RELOC_RL78_OP_SHRA
5173 BFD_RELOC_RL78_ABS16
5175 BFD_RELOC_RL78_ABS16_REV
5177 BFD_RELOC_RL78_ABS32
5179 BFD_RELOC_RL78_ABS32_REV
5181 BFD_RELOC_RL78_ABS16U
5183 BFD_RELOC_RL78_ABS16UW
5185 BFD_RELOC_RL78_ABS16UL
5187 BFD_RELOC_RL78_RELAX
5197 BFD_RELOC_RL78_SADDR
5199 Renesas RL78 Relocations.
5222 BFD_RELOC_RX_DIR3U_PCREL
5234 BFD_RELOC_RX_OP_SUBTRACT
5242 BFD_RELOC_RX_ABS16_REV
5246 BFD_RELOC_RX_ABS32_REV
5250 BFD_RELOC_RX_ABS16UW
5252 BFD_RELOC_RX_ABS16UL
5256 Renesas RX Relocations.
5269 32 bit PC relative PLT address.
5273 Copy symbol at runtime.
5275 BFD_RELOC_390_GLOB_DAT
5279 BFD_RELOC_390_JMP_SLOT
5283 BFD_RELOC_390_RELATIVE
5285 Adjust by program base.
5289 32 bit PC relative offset to GOT.
5295 BFD_RELOC_390_PC12DBL
5297 PC relative 12 bit shifted by 1.
5299 BFD_RELOC_390_PLT12DBL
5301 12 bit PC rel. PLT shifted by 1.
5303 BFD_RELOC_390_PC16DBL
5305 PC relative 16 bit shifted by 1.
5307 BFD_RELOC_390_PLT16DBL
5309 16 bit PC rel. PLT shifted by 1.
5311 BFD_RELOC_390_PC24DBL
5313 PC relative 24 bit shifted by 1.
5315 BFD_RELOC_390_PLT24DBL
5317 24 bit PC rel. PLT shifted by 1.
5319 BFD_RELOC_390_PC32DBL
5321 PC relative 32 bit shifted by 1.
5323 BFD_RELOC_390_PLT32DBL
5325 32 bit PC rel. PLT shifted by 1.
5327 BFD_RELOC_390_GOTPCDBL
5329 32 bit PC rel. GOT shifted by 1.
5337 64 bit PC relative PLT address.
5339 BFD_RELOC_390_GOTENT
5341 32 bit rel. offset to GOT entry.
5343 BFD_RELOC_390_GOTOFF64
5345 64 bit offset to GOT.
5347 BFD_RELOC_390_GOTPLT12
5349 12-bit offset to symbol-entry within GOT, with PLT handling.
5351 BFD_RELOC_390_GOTPLT16
5353 16-bit offset to symbol-entry within GOT, with PLT handling.
5355 BFD_RELOC_390_GOTPLT32
5357 32-bit offset to symbol-entry within GOT, with PLT handling.
5359 BFD_RELOC_390_GOTPLT64
5361 64-bit offset to symbol-entry within GOT, with PLT handling.
5363 BFD_RELOC_390_GOTPLTENT
5365 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5367 BFD_RELOC_390_PLTOFF16
5369 16-bit rel. offset from the GOT to a PLT entry.
5371 BFD_RELOC_390_PLTOFF32
5373 32-bit rel. offset from the GOT to a PLT entry.
5375 BFD_RELOC_390_PLTOFF64
5377 64-bit rel. offset from the GOT to a PLT entry.
5380 BFD_RELOC_390_TLS_LOAD
5382 BFD_RELOC_390_TLS_GDCALL
5384 BFD_RELOC_390_TLS_LDCALL
5386 BFD_RELOC_390_TLS_GD32
5388 BFD_RELOC_390_TLS_GD64
5390 BFD_RELOC_390_TLS_GOTIE12
5392 BFD_RELOC_390_TLS_GOTIE32
5394 BFD_RELOC_390_TLS_GOTIE64
5396 BFD_RELOC_390_TLS_LDM32
5398 BFD_RELOC_390_TLS_LDM64
5400 BFD_RELOC_390_TLS_IE32
5402 BFD_RELOC_390_TLS_IE64
5404 BFD_RELOC_390_TLS_IEENT
5406 BFD_RELOC_390_TLS_LE32
5408 BFD_RELOC_390_TLS_LE64
5410 BFD_RELOC_390_TLS_LDO32
5412 BFD_RELOC_390_TLS_LDO64
5414 BFD_RELOC_390_TLS_DTPMOD
5416 BFD_RELOC_390_TLS_DTPOFF
5418 BFD_RELOC_390_TLS_TPOFF
5420 s390 tls relocations.
5427 BFD_RELOC_390_GOTPLT20
5429 BFD_RELOC_390_TLS_GOTIE20
5431 Long displacement extension.
5434 BFD_RELOC_390_IRELATIVE
5436 STT_GNU_IFUNC relocation.
5439 BFD_RELOC_SCORE_GPREL15
5442 Low 16 bit for load/store
5444 BFD_RELOC_SCORE_DUMMY2
5448 This is a 24-bit reloc with the right 1 bit assumed to be 0
5450 BFD_RELOC_SCORE_BRANCH
5452 This is a 19-bit reloc with the right 1 bit assumed to be 0
5454 BFD_RELOC_SCORE_IMM30
5456 This is a 32-bit reloc for 48-bit instructions.
5458 BFD_RELOC_SCORE_IMM32
5460 This is a 32-bit reloc for 48-bit instructions.
5462 BFD_RELOC_SCORE16_JMP
5464 This is a 11-bit reloc with the right 1 bit assumed to be 0
5466 BFD_RELOC_SCORE16_BRANCH
5468 This is a 8-bit reloc with the right 1 bit assumed to be 0
5470 BFD_RELOC_SCORE_BCMP
5472 This is a 9-bit reloc with the right 1 bit assumed to be 0
5474 BFD_RELOC_SCORE_GOT15
5476 BFD_RELOC_SCORE_GOT_LO16
5478 BFD_RELOC_SCORE_CALL15
5480 BFD_RELOC_SCORE_DUMMY_HI16
5482 Undocumented Score relocs
5487 Scenix IP2K - 9-bit register number / data address
5491 Scenix IP2K - 4-bit register/data bank number
5493 BFD_RELOC_IP2K_ADDR16CJP
5495 Scenix IP2K - low 13 bits of instruction word address
5497 BFD_RELOC_IP2K_PAGE3
5499 Scenix IP2K - high 3 bits of instruction word address
5501 BFD_RELOC_IP2K_LO8DATA
5503 BFD_RELOC_IP2K_HI8DATA
5505 BFD_RELOC_IP2K_EX8DATA
5507 Scenix IP2K - ext/low/high 8 bits of data address
5509 BFD_RELOC_IP2K_LO8INSN
5511 BFD_RELOC_IP2K_HI8INSN
5513 Scenix IP2K - low/high 8 bits of instruction word address
5515 BFD_RELOC_IP2K_PC_SKIP
5517 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5521 Scenix IP2K - 16 bit word address in text section.
5523 BFD_RELOC_IP2K_FR_OFFSET
5525 Scenix IP2K - 7-bit sp or dp offset
5527 BFD_RELOC_VPE4KMATH_DATA
5529 BFD_RELOC_VPE4KMATH_INSN
5531 Scenix VPE4K coprocessor - data/insn-space addressing
5534 BFD_RELOC_VTABLE_INHERIT
5536 BFD_RELOC_VTABLE_ENTRY
5538 These two relocations are used by the linker to determine which of
5539 the entries in a C++ virtual function table are actually used. When
5540 the --gc-sections option is given, the linker will zero out the entries
5541 that are not used, so that the code for those functions need not be
5542 included in the output.
5544 VTABLE_INHERIT is a zero-space relocation used to describe to the
5545 linker the inheritance tree of a C++ virtual function table. The
5546 relocation's symbol should be the parent class' vtable, and the
5547 relocation should be located at the child vtable.
5549 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5550 virtual function table entry. The reloc's symbol should refer to the
5551 table of the class mentioned in the code. Off of that base, an offset
5552 describes the entry that is being used. For Rela hosts, this offset
5553 is stored in the reloc's addend. For Rel hosts, we are forced to put
5554 this offset in the reloc's section offset.
5557 BFD_RELOC_IA64_IMM14
5559 BFD_RELOC_IA64_IMM22
5561 BFD_RELOC_IA64_IMM64
5563 BFD_RELOC_IA64_DIR32MSB
5565 BFD_RELOC_IA64_DIR32LSB
5567 BFD_RELOC_IA64_DIR64MSB
5569 BFD_RELOC_IA64_DIR64LSB
5571 BFD_RELOC_IA64_GPREL22
5573 BFD_RELOC_IA64_GPREL64I
5575 BFD_RELOC_IA64_GPREL32MSB
5577 BFD_RELOC_IA64_GPREL32LSB
5579 BFD_RELOC_IA64_GPREL64MSB
5581 BFD_RELOC_IA64_GPREL64LSB
5583 BFD_RELOC_IA64_LTOFF22
5585 BFD_RELOC_IA64_LTOFF64I
5587 BFD_RELOC_IA64_PLTOFF22
5589 BFD_RELOC_IA64_PLTOFF64I
5591 BFD_RELOC_IA64_PLTOFF64MSB
5593 BFD_RELOC_IA64_PLTOFF64LSB
5595 BFD_RELOC_IA64_FPTR64I
5597 BFD_RELOC_IA64_FPTR32MSB
5599 BFD_RELOC_IA64_FPTR32LSB
5601 BFD_RELOC_IA64_FPTR64MSB
5603 BFD_RELOC_IA64_FPTR64LSB
5605 BFD_RELOC_IA64_PCREL21B
5607 BFD_RELOC_IA64_PCREL21BI
5609 BFD_RELOC_IA64_PCREL21M
5611 BFD_RELOC_IA64_PCREL21F
5613 BFD_RELOC_IA64_PCREL22
5615 BFD_RELOC_IA64_PCREL60B
5617 BFD_RELOC_IA64_PCREL64I
5619 BFD_RELOC_IA64_PCREL32MSB
5621 BFD_RELOC_IA64_PCREL32LSB
5623 BFD_RELOC_IA64_PCREL64MSB
5625 BFD_RELOC_IA64_PCREL64LSB
5627 BFD_RELOC_IA64_LTOFF_FPTR22
5629 BFD_RELOC_IA64_LTOFF_FPTR64I
5631 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5633 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5635 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5637 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5639 BFD_RELOC_IA64_SEGREL32MSB
5641 BFD_RELOC_IA64_SEGREL32LSB
5643 BFD_RELOC_IA64_SEGREL64MSB
5645 BFD_RELOC_IA64_SEGREL64LSB
5647 BFD_RELOC_IA64_SECREL32MSB
5649 BFD_RELOC_IA64_SECREL32LSB
5651 BFD_RELOC_IA64_SECREL64MSB
5653 BFD_RELOC_IA64_SECREL64LSB
5655 BFD_RELOC_IA64_REL32MSB
5657 BFD_RELOC_IA64_REL32LSB
5659 BFD_RELOC_IA64_REL64MSB
5661 BFD_RELOC_IA64_REL64LSB
5663 BFD_RELOC_IA64_LTV32MSB
5665 BFD_RELOC_IA64_LTV32LSB
5667 BFD_RELOC_IA64_LTV64MSB
5669 BFD_RELOC_IA64_LTV64LSB
5671 BFD_RELOC_IA64_IPLTMSB
5673 BFD_RELOC_IA64_IPLTLSB
5677 BFD_RELOC_IA64_LTOFF22X
5679 BFD_RELOC_IA64_LDXMOV
5681 BFD_RELOC_IA64_TPREL14
5683 BFD_RELOC_IA64_TPREL22
5685 BFD_RELOC_IA64_TPREL64I
5687 BFD_RELOC_IA64_TPREL64MSB
5689 BFD_RELOC_IA64_TPREL64LSB
5691 BFD_RELOC_IA64_LTOFF_TPREL22
5693 BFD_RELOC_IA64_DTPMOD64MSB
5695 BFD_RELOC_IA64_DTPMOD64LSB
5697 BFD_RELOC_IA64_LTOFF_DTPMOD22
5699 BFD_RELOC_IA64_DTPREL14
5701 BFD_RELOC_IA64_DTPREL22
5703 BFD_RELOC_IA64_DTPREL64I
5705 BFD_RELOC_IA64_DTPREL32MSB
5707 BFD_RELOC_IA64_DTPREL32LSB
5709 BFD_RELOC_IA64_DTPREL64MSB
5711 BFD_RELOC_IA64_DTPREL64LSB
5713 BFD_RELOC_IA64_LTOFF_DTPREL22
5715 Intel IA64 Relocations.
5718 BFD_RELOC_M68HC11_HI8
5720 Motorola 68HC11 reloc.
5721 This is the 8 bit high part of an absolute address.
5723 BFD_RELOC_M68HC11_LO8
5725 Motorola 68HC11 reloc.
5726 This is the 8 bit low part of an absolute address.
5728 BFD_RELOC_M68HC11_3B
5730 Motorola 68HC11 reloc.
5731 This is the 3 bit of a value.
5733 BFD_RELOC_M68HC11_RL_JUMP
5735 Motorola 68HC11 reloc.
5736 This reloc marks the beginning of a jump/call instruction.
5737 It is used for linker relaxation to correctly identify beginning
5738 of instruction and change some branches to use PC-relative
5741 BFD_RELOC_M68HC11_RL_GROUP
5743 Motorola 68HC11 reloc.
5744 This reloc marks a group of several instructions that gcc generates
5745 and for which the linker relaxation pass can modify and/or remove
5748 BFD_RELOC_M68HC11_LO16
5750 Motorola 68HC11 reloc.
5751 This is the 16-bit lower part of an address. It is used for 'call'
5752 instruction to specify the symbol address without any special
5753 transformation (due to memory bank window).
5755 BFD_RELOC_M68HC11_PAGE
5757 Motorola 68HC11 reloc.
5758 This is a 8-bit reloc that specifies the page number of an address.
5759 It is used by 'call' instruction to specify the page number of
5762 BFD_RELOC_M68HC11_24
5764 Motorola 68HC11 reloc.
5765 This is a 24-bit reloc that represents the address with a 16-bit
5766 value and a 8-bit page number. The symbol address is transformed
5767 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5769 BFD_RELOC_M68HC12_5B
5771 Motorola 68HC12 reloc.
5772 This is the 5 bits of a value.
5774 BFD_RELOC_XGATE_RL_JUMP
5776 Freescale XGATE reloc.
5777 This reloc marks the beginning of a bra/jal instruction.
5779 BFD_RELOC_XGATE_RL_GROUP
5781 Freescale XGATE reloc.
5782 This reloc marks a group of several instructions that gcc generates
5783 and for which the linker relaxation pass can modify and/or remove
5786 BFD_RELOC_XGATE_LO16
5788 Freescale XGATE reloc.
5789 This is the 16-bit lower part of an address. It is used for the '16-bit'
5792 BFD_RELOC_XGATE_GPAGE
5794 Freescale XGATE reloc.
5798 Freescale XGATE reloc.
5800 BFD_RELOC_XGATE_PCREL_9
5802 Freescale XGATE reloc.
5803 This is a 9-bit pc-relative reloc.
5805 BFD_RELOC_XGATE_PCREL_10
5807 Freescale XGATE reloc.
5808 This is a 10-bit pc-relative reloc.
5810 BFD_RELOC_XGATE_IMM8_LO
5812 Freescale XGATE reloc.
5813 This is the 16-bit lower part of an address. It is used for the '16-bit'
5816 BFD_RELOC_XGATE_IMM8_HI
5818 Freescale XGATE reloc.
5819 This is the 16-bit higher part of an address. It is used for the '16-bit'
5822 BFD_RELOC_XGATE_IMM3
5824 Freescale XGATE reloc.
5825 This is a 3-bit pc-relative reloc.
5827 BFD_RELOC_XGATE_IMM4
5829 Freescale XGATE reloc.
5830 This is a 4-bit pc-relative reloc.
5832 BFD_RELOC_XGATE_IMM5
5834 Freescale XGATE reloc.
5835 This is a 5-bit pc-relative reloc.
5837 BFD_RELOC_M68HC12_9B
5839 Motorola 68HC12 reloc.
5840 This is the 9 bits of a value.
5842 BFD_RELOC_M68HC12_16B
5844 Motorola 68HC12 reloc.
5845 This is the 16 bits of a value.
5847 BFD_RELOC_M68HC12_9_PCREL
5849 Motorola 68HC12/XGATE reloc.
5850 This is a PCREL9 branch.
5852 BFD_RELOC_M68HC12_10_PCREL
5854 Motorola 68HC12/XGATE reloc.
5855 This is a PCREL10 branch.
5857 BFD_RELOC_M68HC12_LO8XG
5859 Motorola 68HC12/XGATE reloc.
5860 This is the 8 bit low part of an absolute address and immediately precedes
5861 a matching HI8XG part.
5863 BFD_RELOC_M68HC12_HI8XG
5865 Motorola 68HC12/XGATE reloc.
5866 This is the 8 bit high part of an absolute address and immediately follows
5867 a matching LO8XG part.
5869 BFD_RELOC_S12Z_15_PCREL
5871 Freescale S12Z reloc.
5872 This is a 15 bit relative address. If the most significant bits are all zero
5873 then it may be truncated to 8 bits.
5877 BFD_RELOC_16C_NUM08_C
5881 BFD_RELOC_16C_NUM16_C
5885 BFD_RELOC_16C_NUM32_C
5887 BFD_RELOC_16C_DISP04
5889 BFD_RELOC_16C_DISP04_C
5891 BFD_RELOC_16C_DISP08
5893 BFD_RELOC_16C_DISP08_C
5895 BFD_RELOC_16C_DISP16
5897 BFD_RELOC_16C_DISP16_C
5899 BFD_RELOC_16C_DISP24
5901 BFD_RELOC_16C_DISP24_C
5903 BFD_RELOC_16C_DISP24a
5905 BFD_RELOC_16C_DISP24a_C
5909 BFD_RELOC_16C_REG04_C
5911 BFD_RELOC_16C_REG04a
5913 BFD_RELOC_16C_REG04a_C
5917 BFD_RELOC_16C_REG14_C
5921 BFD_RELOC_16C_REG16_C
5925 BFD_RELOC_16C_REG20_C
5929 BFD_RELOC_16C_ABS20_C
5933 BFD_RELOC_16C_ABS24_C
5937 BFD_RELOC_16C_IMM04_C
5941 BFD_RELOC_16C_IMM16_C
5945 BFD_RELOC_16C_IMM20_C
5949 BFD_RELOC_16C_IMM24_C
5953 BFD_RELOC_16C_IMM32_C
5955 NS CR16C Relocations.
5960 BFD_RELOC_CR16_NUM16
5962 BFD_RELOC_CR16_NUM32
5964 BFD_RELOC_CR16_NUM32a
5966 BFD_RELOC_CR16_REGREL0
5968 BFD_RELOC_CR16_REGREL4
5970 BFD_RELOC_CR16_REGREL4a
5972 BFD_RELOC_CR16_REGREL14
5974 BFD_RELOC_CR16_REGREL14a
5976 BFD_RELOC_CR16_REGREL16
5978 BFD_RELOC_CR16_REGREL20
5980 BFD_RELOC_CR16_REGREL20a
5982 BFD_RELOC_CR16_ABS20
5984 BFD_RELOC_CR16_ABS24
5990 BFD_RELOC_CR16_IMM16
5992 BFD_RELOC_CR16_IMM20
5994 BFD_RELOC_CR16_IMM24
5996 BFD_RELOC_CR16_IMM32
5998 BFD_RELOC_CR16_IMM32a
6000 BFD_RELOC_CR16_DISP4
6002 BFD_RELOC_CR16_DISP8
6004 BFD_RELOC_CR16_DISP16
6006 BFD_RELOC_CR16_DISP20
6008 BFD_RELOC_CR16_DISP24
6010 BFD_RELOC_CR16_DISP24a
6012 BFD_RELOC_CR16_SWITCH8
6014 BFD_RELOC_CR16_SWITCH16
6016 BFD_RELOC_CR16_SWITCH32
6018 BFD_RELOC_CR16_GOT_REGREL20
6020 BFD_RELOC_CR16_GOTC_REGREL20
6022 BFD_RELOC_CR16_GLOB_DAT
6024 NS CR16 Relocations.
6031 BFD_RELOC_CRX_REL8_CMP
6039 BFD_RELOC_CRX_REGREL12
6041 BFD_RELOC_CRX_REGREL22
6043 BFD_RELOC_CRX_REGREL28
6045 BFD_RELOC_CRX_REGREL32
6061 BFD_RELOC_CRX_SWITCH8
6063 BFD_RELOC_CRX_SWITCH16
6065 BFD_RELOC_CRX_SWITCH32
6070 BFD_RELOC_CRIS_BDISP8
6072 BFD_RELOC_CRIS_UNSIGNED_5
6074 BFD_RELOC_CRIS_SIGNED_6
6076 BFD_RELOC_CRIS_UNSIGNED_6
6078 BFD_RELOC_CRIS_SIGNED_8
6080 BFD_RELOC_CRIS_UNSIGNED_8
6082 BFD_RELOC_CRIS_SIGNED_16
6084 BFD_RELOC_CRIS_UNSIGNED_16
6086 BFD_RELOC_CRIS_LAPCQ_OFFSET
6088 BFD_RELOC_CRIS_UNSIGNED_4
6090 These relocs are only used within the CRIS assembler. They are not
6091 (at present) written to any object files.
6095 BFD_RELOC_CRIS_GLOB_DAT
6097 BFD_RELOC_CRIS_JUMP_SLOT
6099 BFD_RELOC_CRIS_RELATIVE
6101 Relocs used in ELF shared libraries for CRIS.
6103 BFD_RELOC_CRIS_32_GOT
6105 32-bit offset to symbol-entry within GOT.
6107 BFD_RELOC_CRIS_16_GOT
6109 16-bit offset to symbol-entry within GOT.
6111 BFD_RELOC_CRIS_32_GOTPLT
6113 32-bit offset to symbol-entry within GOT, with PLT handling.
6115 BFD_RELOC_CRIS_16_GOTPLT
6117 16-bit offset to symbol-entry within GOT, with PLT handling.
6119 BFD_RELOC_CRIS_32_GOTREL
6121 32-bit offset to symbol, relative to GOT.
6123 BFD_RELOC_CRIS_32_PLT_GOTREL
6125 32-bit offset to symbol with PLT entry, relative to GOT.
6127 BFD_RELOC_CRIS_32_PLT_PCREL
6129 32-bit offset to symbol with PLT entry, relative to this relocation.
6132 BFD_RELOC_CRIS_32_GOT_GD
6134 BFD_RELOC_CRIS_16_GOT_GD
6136 BFD_RELOC_CRIS_32_GD
6140 BFD_RELOC_CRIS_32_DTPREL
6142 BFD_RELOC_CRIS_16_DTPREL
6144 BFD_RELOC_CRIS_32_GOT_TPREL
6146 BFD_RELOC_CRIS_16_GOT_TPREL
6148 BFD_RELOC_CRIS_32_TPREL
6150 BFD_RELOC_CRIS_16_TPREL
6152 BFD_RELOC_CRIS_DTPMOD
6154 BFD_RELOC_CRIS_32_IE
6156 Relocs used in TLS code for CRIS.
6159 BFD_RELOC_OR1K_REL_26
6161 BFD_RELOC_OR1K_SLO16
6163 BFD_RELOC_OR1K_PCREL_PG21
6167 BFD_RELOC_OR1K_SLO13
6169 BFD_RELOC_OR1K_GOTPC_HI16
6171 BFD_RELOC_OR1K_GOTPC_LO16
6173 BFD_RELOC_OR1K_GOT16
6175 BFD_RELOC_OR1K_GOT_PG21
6177 BFD_RELOC_OR1K_GOT_LO13
6179 BFD_RELOC_OR1K_PLT26
6181 BFD_RELOC_OR1K_PLTA26
6183 BFD_RELOC_OR1K_GOTOFF_SLO16
6187 BFD_RELOC_OR1K_GLOB_DAT
6189 BFD_RELOC_OR1K_JMP_SLOT
6191 BFD_RELOC_OR1K_RELATIVE
6193 BFD_RELOC_OR1K_TLS_GD_HI16
6195 BFD_RELOC_OR1K_TLS_GD_LO16
6197 BFD_RELOC_OR1K_TLS_GD_PG21
6199 BFD_RELOC_OR1K_TLS_GD_LO13
6201 BFD_RELOC_OR1K_TLS_LDM_HI16
6203 BFD_RELOC_OR1K_TLS_LDM_LO16
6205 BFD_RELOC_OR1K_TLS_LDM_PG21
6207 BFD_RELOC_OR1K_TLS_LDM_LO13
6209 BFD_RELOC_OR1K_TLS_LDO_HI16
6211 BFD_RELOC_OR1K_TLS_LDO_LO16
6213 BFD_RELOC_OR1K_TLS_IE_HI16
6215 BFD_RELOC_OR1K_TLS_IE_AHI16
6217 BFD_RELOC_OR1K_TLS_IE_LO16
6219 BFD_RELOC_OR1K_TLS_IE_PG21
6221 BFD_RELOC_OR1K_TLS_IE_LO13
6223 BFD_RELOC_OR1K_TLS_LE_HI16
6225 BFD_RELOC_OR1K_TLS_LE_AHI16
6227 BFD_RELOC_OR1K_TLS_LE_LO16
6229 BFD_RELOC_OR1K_TLS_LE_SLO16
6231 BFD_RELOC_OR1K_TLS_TPOFF
6233 BFD_RELOC_OR1K_TLS_DTPOFF
6235 BFD_RELOC_OR1K_TLS_DTPMOD
6237 OpenRISC 1000 Relocations.
6240 BFD_RELOC_H8_DIR16A8
6242 BFD_RELOC_H8_DIR16R8
6244 BFD_RELOC_H8_DIR24A8
6246 BFD_RELOC_H8_DIR24R8
6248 BFD_RELOC_H8_DIR32A16
6250 BFD_RELOC_H8_DISP32A16
6255 BFD_RELOC_XSTORMY16_REL_12
6257 BFD_RELOC_XSTORMY16_12
6259 BFD_RELOC_XSTORMY16_24
6261 BFD_RELOC_XSTORMY16_FPTR16
6263 Sony Xstormy16 Relocations.
6268 Self-describing complex relocations.
6280 Infineon Relocations.
6283 BFD_RELOC_VAX_GLOB_DAT
6285 BFD_RELOC_VAX_JMP_SLOT
6287 BFD_RELOC_VAX_RELATIVE
6289 Relocations used by VAX ELF.
6294 Morpho MT - 16 bit immediate relocation.
6298 Morpho MT - Hi 16 bits of an address.
6302 Morpho MT - Low 16 bits of an address.
6304 BFD_RELOC_MT_GNU_VTINHERIT
6306 Morpho MT - Used to tell the linker which vtable entries are used.
6308 BFD_RELOC_MT_GNU_VTENTRY
6310 Morpho MT - Used to tell the linker which vtable entries are used.
6312 BFD_RELOC_MT_PCINSN8
6314 Morpho MT - 8 bit immediate relocation.
6317 BFD_RELOC_MSP430_10_PCREL
6319 BFD_RELOC_MSP430_16_PCREL
6323 BFD_RELOC_MSP430_16_PCREL_BYTE
6325 BFD_RELOC_MSP430_16_BYTE
6327 BFD_RELOC_MSP430_2X_PCREL
6329 BFD_RELOC_MSP430_RL_PCREL
6331 BFD_RELOC_MSP430_ABS8
6333 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6335 BFD_RELOC_MSP430X_PCR20_EXT_DST
6337 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6339 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6341 BFD_RELOC_MSP430X_ABS20_EXT_DST
6343 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6345 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6347 BFD_RELOC_MSP430X_ABS20_ADR_DST
6349 BFD_RELOC_MSP430X_PCR16
6351 BFD_RELOC_MSP430X_PCR20_CALL
6353 BFD_RELOC_MSP430X_ABS16
6355 BFD_RELOC_MSP430_ABS_HI16
6357 BFD_RELOC_MSP430_PREL31
6359 BFD_RELOC_MSP430_SYM_DIFF
6361 msp430 specific relocation codes
6368 BFD_RELOC_NIOS2_CALL26
6370 BFD_RELOC_NIOS2_IMM5
6372 BFD_RELOC_NIOS2_CACHE_OPX
6374 BFD_RELOC_NIOS2_IMM6
6376 BFD_RELOC_NIOS2_IMM8
6378 BFD_RELOC_NIOS2_HI16
6380 BFD_RELOC_NIOS2_LO16
6382 BFD_RELOC_NIOS2_HIADJ16
6384 BFD_RELOC_NIOS2_GPREL
6386 BFD_RELOC_NIOS2_UJMP
6388 BFD_RELOC_NIOS2_CJMP
6390 BFD_RELOC_NIOS2_CALLR
6392 BFD_RELOC_NIOS2_ALIGN
6394 BFD_RELOC_NIOS2_GOT16
6396 BFD_RELOC_NIOS2_CALL16
6398 BFD_RELOC_NIOS2_GOTOFF_LO
6400 BFD_RELOC_NIOS2_GOTOFF_HA
6402 BFD_RELOC_NIOS2_PCREL_LO
6404 BFD_RELOC_NIOS2_PCREL_HA
6406 BFD_RELOC_NIOS2_TLS_GD16
6408 BFD_RELOC_NIOS2_TLS_LDM16
6410 BFD_RELOC_NIOS2_TLS_LDO16
6412 BFD_RELOC_NIOS2_TLS_IE16
6414 BFD_RELOC_NIOS2_TLS_LE16
6416 BFD_RELOC_NIOS2_TLS_DTPMOD
6418 BFD_RELOC_NIOS2_TLS_DTPREL
6420 BFD_RELOC_NIOS2_TLS_TPREL
6422 BFD_RELOC_NIOS2_COPY
6424 BFD_RELOC_NIOS2_GLOB_DAT
6426 BFD_RELOC_NIOS2_JUMP_SLOT
6428 BFD_RELOC_NIOS2_RELATIVE
6430 BFD_RELOC_NIOS2_GOTOFF
6432 BFD_RELOC_NIOS2_CALL26_NOAT
6434 BFD_RELOC_NIOS2_GOT_LO
6436 BFD_RELOC_NIOS2_GOT_HA
6438 BFD_RELOC_NIOS2_CALL_LO
6440 BFD_RELOC_NIOS2_CALL_HA
6442 BFD_RELOC_NIOS2_R2_S12
6444 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6446 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6448 BFD_RELOC_NIOS2_R2_T1I7_2
6450 BFD_RELOC_NIOS2_R2_T2I4
6452 BFD_RELOC_NIOS2_R2_T2I4_1
6454 BFD_RELOC_NIOS2_R2_T2I4_2
6456 BFD_RELOC_NIOS2_R2_X1I7_2
6458 BFD_RELOC_NIOS2_R2_X2L5
6460 BFD_RELOC_NIOS2_R2_F1I5_2
6462 BFD_RELOC_NIOS2_R2_L5I4X1
6464 BFD_RELOC_NIOS2_R2_T1X1I6
6466 BFD_RELOC_NIOS2_R2_T1X1I6_2
6468 Relocations used by the Altera Nios II core.
6473 PRU LDI 16-bit unsigned data-memory relocation.
6475 BFD_RELOC_PRU_U16_PMEMIMM
6477 PRU LDI 16-bit unsigned instruction-memory relocation.
6481 PRU relocation for two consecutive LDI load instructions that load a
6482 32 bit value into a register. If the higher bits are all zero, then
6483 the second instruction may be relaxed.
6485 BFD_RELOC_PRU_S10_PCREL
6487 PRU QBBx 10-bit signed PC-relative relocation.
6489 BFD_RELOC_PRU_U8_PCREL
6491 PRU 8-bit unsigned relocation used for the LOOP instruction.
6493 BFD_RELOC_PRU_32_PMEM
6495 BFD_RELOC_PRU_16_PMEM
6497 PRU Program Memory relocations. Used to convert from byte addressing to
6498 32-bit word addressing.
6500 BFD_RELOC_PRU_GNU_DIFF8
6502 BFD_RELOC_PRU_GNU_DIFF16
6504 BFD_RELOC_PRU_GNU_DIFF32
6506 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6508 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6510 PRU relocations to mark the difference of two local symbols.
6511 These are only needed to support linker relaxation and can be ignored
6512 when not relaxing. The field is set to the value of the difference
6513 assuming no relaxation. The relocation encodes the position of the
6514 second symbol so the linker can determine whether to adjust the field
6515 value. The PMEM variants encode the word difference, instead of byte
6516 difference between symbols.
6519 BFD_RELOC_IQ2000_OFFSET_16
6521 BFD_RELOC_IQ2000_OFFSET_21
6523 BFD_RELOC_IQ2000_UHI16
6528 BFD_RELOC_XTENSA_RTLD
6530 Special Xtensa relocation used only by PLT entries in ELF shared
6531 objects to indicate that the runtime linker should set the value
6532 to one of its own internal functions or data structures.
6534 BFD_RELOC_XTENSA_GLOB_DAT
6536 BFD_RELOC_XTENSA_JMP_SLOT
6538 BFD_RELOC_XTENSA_RELATIVE
6540 Xtensa relocations for ELF shared objects.
6542 BFD_RELOC_XTENSA_PLT
6544 Xtensa relocation used in ELF object files for symbols that may require
6545 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6547 BFD_RELOC_XTENSA_DIFF8
6549 BFD_RELOC_XTENSA_DIFF16
6551 BFD_RELOC_XTENSA_DIFF32
6553 Xtensa relocations to mark the difference of two local symbols.
6554 These are only needed to support linker relaxation and can be ignored
6555 when not relaxing. The field is set to the value of the difference
6556 assuming no relaxation. The relocation encodes the position of the
6557 first symbol so the linker can determine whether to adjust the field
6560 BFD_RELOC_XTENSA_SLOT0_OP
6562 BFD_RELOC_XTENSA_SLOT1_OP
6564 BFD_RELOC_XTENSA_SLOT2_OP
6566 BFD_RELOC_XTENSA_SLOT3_OP
6568 BFD_RELOC_XTENSA_SLOT4_OP
6570 BFD_RELOC_XTENSA_SLOT5_OP
6572 BFD_RELOC_XTENSA_SLOT6_OP
6574 BFD_RELOC_XTENSA_SLOT7_OP
6576 BFD_RELOC_XTENSA_SLOT8_OP
6578 BFD_RELOC_XTENSA_SLOT9_OP
6580 BFD_RELOC_XTENSA_SLOT10_OP
6582 BFD_RELOC_XTENSA_SLOT11_OP
6584 BFD_RELOC_XTENSA_SLOT12_OP
6586 BFD_RELOC_XTENSA_SLOT13_OP
6588 BFD_RELOC_XTENSA_SLOT14_OP
6590 Generic Xtensa relocations for instruction operands. Only the slot
6591 number is encoded in the relocation. The relocation applies to the
6592 last PC-relative immediate operand, or if there are no PC-relative
6593 immediates, to the last immediate operand.
6595 BFD_RELOC_XTENSA_SLOT0_ALT
6597 BFD_RELOC_XTENSA_SLOT1_ALT
6599 BFD_RELOC_XTENSA_SLOT2_ALT
6601 BFD_RELOC_XTENSA_SLOT3_ALT
6603 BFD_RELOC_XTENSA_SLOT4_ALT
6605 BFD_RELOC_XTENSA_SLOT5_ALT
6607 BFD_RELOC_XTENSA_SLOT6_ALT
6609 BFD_RELOC_XTENSA_SLOT7_ALT
6611 BFD_RELOC_XTENSA_SLOT8_ALT
6613 BFD_RELOC_XTENSA_SLOT9_ALT
6615 BFD_RELOC_XTENSA_SLOT10_ALT
6617 BFD_RELOC_XTENSA_SLOT11_ALT
6619 BFD_RELOC_XTENSA_SLOT12_ALT
6621 BFD_RELOC_XTENSA_SLOT13_ALT
6623 BFD_RELOC_XTENSA_SLOT14_ALT
6625 Alternate Xtensa relocations. Only the slot is encoded in the
6626 relocation. The meaning of these relocations is opcode-specific.
6628 BFD_RELOC_XTENSA_OP0
6630 BFD_RELOC_XTENSA_OP1
6632 BFD_RELOC_XTENSA_OP2
6634 Xtensa relocations for backward compatibility. These have all been
6635 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6637 BFD_RELOC_XTENSA_ASM_EXPAND
6639 Xtensa relocation to mark that the assembler expanded the
6640 instructions from an original target. The expansion size is
6641 encoded in the reloc size.
6643 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6645 Xtensa relocation to mark that the linker should simplify
6646 assembler-expanded instructions. This is commonly used
6647 internally by the linker after analysis of a
6648 BFD_RELOC_XTENSA_ASM_EXPAND.
6650 BFD_RELOC_XTENSA_TLSDESC_FN
6652 BFD_RELOC_XTENSA_TLSDESC_ARG
6654 BFD_RELOC_XTENSA_TLS_DTPOFF
6656 BFD_RELOC_XTENSA_TLS_TPOFF
6658 BFD_RELOC_XTENSA_TLS_FUNC
6660 BFD_RELOC_XTENSA_TLS_ARG
6662 BFD_RELOC_XTENSA_TLS_CALL
6664 Xtensa TLS relocations.
6669 8 bit signed offset in (ix+d) or (iy+d).
6687 BFD_RELOC_LM32_BRANCH
6689 BFD_RELOC_LM32_16_GOT
6691 BFD_RELOC_LM32_GOTOFF_HI16
6693 BFD_RELOC_LM32_GOTOFF_LO16
6697 BFD_RELOC_LM32_GLOB_DAT
6699 BFD_RELOC_LM32_JMP_SLOT
6701 BFD_RELOC_LM32_RELATIVE
6703 Lattice Mico32 relocations.
6706 BFD_RELOC_MACH_O_SECTDIFF
6708 Difference between two section addreses. Must be followed by a
6709 BFD_RELOC_MACH_O_PAIR.
6711 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6713 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6715 BFD_RELOC_MACH_O_PAIR
6717 Pair of relocation. Contains the first symbol.
6719 BFD_RELOC_MACH_O_SUBTRACTOR32
6721 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6723 BFD_RELOC_MACH_O_SUBTRACTOR64
6725 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6728 BFD_RELOC_MACH_O_X86_64_BRANCH32
6730 BFD_RELOC_MACH_O_X86_64_BRANCH8
6732 PCREL relocations. They are marked as branch to create PLT entry if
6735 BFD_RELOC_MACH_O_X86_64_GOT
6737 Used when referencing a GOT entry.
6739 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6741 Used when loading a GOT entry with movq. It is specially marked so that
6742 the linker could optimize the movq to a leaq if possible.
6744 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6746 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6748 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6750 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6752 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6754 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6756 BFD_RELOC_MACH_O_X86_64_TLV
6758 Used when referencing a TLV entry.
6762 BFD_RELOC_MACH_O_ARM64_ADDEND
6764 Addend for PAGE or PAGEOFF.
6766 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6768 Relative offset to page of GOT slot.
6770 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6772 Relative offset within page of GOT slot.
6774 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6776 Address of a GOT entry.
6779 BFD_RELOC_MICROBLAZE_32_LO
6781 This is a 32 bit reloc for the microblaze that stores the
6782 low 16 bits of a value
6784 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6786 This is a 32 bit pc-relative reloc for the microblaze that
6787 stores the low 16 bits of a value
6789 BFD_RELOC_MICROBLAZE_32_ROSDA
6791 This is a 32 bit reloc for the microblaze that stores a
6792 value relative to the read-only small data area anchor
6794 BFD_RELOC_MICROBLAZE_32_RWSDA
6796 This is a 32 bit reloc for the microblaze that stores a
6797 value relative to the read-write small data area anchor
6799 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6801 This is a 32 bit reloc for the microblaze to handle
6802 expressions of the form "Symbol Op Symbol"
6804 BFD_RELOC_MICROBLAZE_64_NONE
6806 This is a 64 bit reloc that stores the 32 bit pc relative
6807 value in two words (with an imm instruction). No relocation is
6808 done here - only used for relaxing
6810 BFD_RELOC_MICROBLAZE_64_GOTPC
6812 This is a 64 bit reloc that stores the 32 bit pc relative
6813 value in two words (with an imm instruction). The relocation is
6814 PC-relative GOT offset
6816 BFD_RELOC_MICROBLAZE_64_GOT
6818 This is a 64 bit reloc that stores the 32 bit pc relative
6819 value in two words (with an imm instruction). The relocation is
6822 BFD_RELOC_MICROBLAZE_64_PLT
6824 This is a 64 bit reloc that stores the 32 bit pc relative
6825 value in two words (with an imm instruction). The relocation is
6826 PC-relative offset into PLT
6828 BFD_RELOC_MICROBLAZE_64_GOTOFF
6830 This is a 64 bit reloc that stores the 32 bit GOT relative
6831 value in two words (with an imm instruction). The relocation is
6832 relative offset from _GLOBAL_OFFSET_TABLE_
6834 BFD_RELOC_MICROBLAZE_32_GOTOFF
6836 This is a 32 bit reloc that stores the 32 bit GOT relative
6837 value in a word. The relocation is relative offset from
6838 _GLOBAL_OFFSET_TABLE_
6840 BFD_RELOC_MICROBLAZE_COPY
6842 This is used to tell the dynamic linker to copy the value out of
6843 the dynamic object into the runtime process image.
6845 BFD_RELOC_MICROBLAZE_64_TLS
6849 BFD_RELOC_MICROBLAZE_64_TLSGD
6851 This is a 64 bit reloc that stores the 32 bit GOT relative value
6852 of the GOT TLS GD info entry in two words (with an imm instruction). The
6853 relocation is GOT offset.
6855 BFD_RELOC_MICROBLAZE_64_TLSLD
6857 This is a 64 bit reloc that stores the 32 bit GOT relative value
6858 of the GOT TLS LD info entry in two words (with an imm instruction). The
6859 relocation is GOT offset.
6861 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6863 This is a 32 bit reloc that stores the Module ID to GOT(n).
6865 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6867 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6869 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6871 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6874 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6876 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6877 to two words (uses imm instruction).
6879 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6881 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6882 to two words (uses imm instruction).
6884 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6886 This is a 64 bit reloc that stores the 32 bit pc relative
6887 value in two words (with an imm instruction). The relocation is
6888 PC-relative offset from start of TEXT.
6890 BFD_RELOC_MICROBLAZE_64_TEXTREL
6892 This is a 64 bit reloc that stores the 32 bit offset
6893 value in two words (with an imm instruction). The relocation is
6894 relative offset from start of TEXT.
6897 BFD_RELOC_AARCH64_RELOC_START
6899 AArch64 pseudo relocation code to mark the start of the AArch64
6900 relocation enumerators. N.B. the order of the enumerators is
6901 important as several tables in the AArch64 bfd backend are indexed
6902 by these enumerators; make sure they are all synced.
6904 BFD_RELOC_AARCH64_NULL
6906 Deprecated AArch64 null relocation code.
6908 BFD_RELOC_AARCH64_NONE
6910 AArch64 null relocation code.
6912 BFD_RELOC_AARCH64_64
6914 BFD_RELOC_AARCH64_32
6916 BFD_RELOC_AARCH64_16
6918 Basic absolute relocations of N bits. These are equivalent to
6919 BFD_RELOC_N and they were added to assist the indexing of the howto
6922 BFD_RELOC_AARCH64_64_PCREL
6924 BFD_RELOC_AARCH64_32_PCREL
6926 BFD_RELOC_AARCH64_16_PCREL
6928 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6929 and they were added to assist the indexing of the howto table.
6931 BFD_RELOC_AARCH64_MOVW_G0
6933 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6934 of an unsigned address/value.
6936 BFD_RELOC_AARCH64_MOVW_G0_NC
6938 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6939 an address/value. No overflow checking.
6941 BFD_RELOC_AARCH64_MOVW_G1
6943 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6944 of an unsigned address/value.
6946 BFD_RELOC_AARCH64_MOVW_G1_NC
6948 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6949 of an address/value. No overflow checking.
6951 BFD_RELOC_AARCH64_MOVW_G2
6953 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6954 of an unsigned address/value.
6956 BFD_RELOC_AARCH64_MOVW_G2_NC
6958 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6959 of an address/value. No overflow checking.
6961 BFD_RELOC_AARCH64_MOVW_G3
6963 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
6964 of a signed or unsigned address/value.
6966 BFD_RELOC_AARCH64_MOVW_G0_S
6968 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6969 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6972 BFD_RELOC_AARCH64_MOVW_G1_S
6974 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
6975 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6978 BFD_RELOC_AARCH64_MOVW_G2_S
6980 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
6981 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6984 BFD_RELOC_AARCH64_MOVW_PREL_G0
6986 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6987 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6990 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
6992 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6993 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6996 BFD_RELOC_AARCH64_MOVW_PREL_G1
6998 AArch64 MOVK instruction with most significant bits 16 to 31
7001 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7003 AArch64 MOVK instruction with most significant bits 16 to 31
7006 BFD_RELOC_AARCH64_MOVW_PREL_G2
7008 AArch64 MOVK instruction with most significant bits 32 to 47
7011 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7013 AArch64 MOVK instruction with most significant bits 32 to 47
7016 BFD_RELOC_AARCH64_MOVW_PREL_G3
7018 AArch64 MOVK instruction with most significant bits 47 to 63
7021 BFD_RELOC_AARCH64_LD_LO19_PCREL
7023 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7024 offset. The lowest two bits must be zero and are not stored in the
7025 instruction, giving a 21 bit signed byte offset.
7027 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7029 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7031 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7033 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7034 offset, giving a 4KB aligned page base address.
7036 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7038 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7039 offset, giving a 4KB aligned page base address, but with no overflow
7042 BFD_RELOC_AARCH64_ADD_LO12
7044 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7045 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7047 BFD_RELOC_AARCH64_LDST8_LO12
7049 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7050 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7052 BFD_RELOC_AARCH64_TSTBR14
7054 AArch64 14 bit pc-relative test bit and branch.
7055 The lowest two bits must be zero and are not stored in the instruction,
7056 giving a 16 bit signed byte offset.
7058 BFD_RELOC_AARCH64_BRANCH19
7060 AArch64 19 bit pc-relative conditional branch and compare & branch.
7061 The lowest two bits must be zero and are not stored in the instruction,
7062 giving a 21 bit signed byte offset.
7064 BFD_RELOC_AARCH64_JUMP26
7066 AArch64 26 bit pc-relative unconditional branch.
7067 The lowest two bits must be zero and are not stored in the instruction,
7068 giving a 28 bit signed byte offset.
7070 BFD_RELOC_AARCH64_CALL26
7072 AArch64 26 bit pc-relative unconditional branch and link.
7073 The lowest two bits must be zero and are not stored in the instruction,
7074 giving a 28 bit signed byte offset.
7076 BFD_RELOC_AARCH64_LDST16_LO12
7078 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7079 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7081 BFD_RELOC_AARCH64_LDST32_LO12
7083 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7084 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7086 BFD_RELOC_AARCH64_LDST64_LO12
7088 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7089 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7091 BFD_RELOC_AARCH64_LDST128_LO12
7093 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7094 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7096 BFD_RELOC_AARCH64_GOT_LD_PREL19
7098 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7099 offset of the global offset table entry for a symbol. The lowest two
7100 bits must be zero and are not stored in the instruction, giving a 21
7101 bit signed byte offset. This relocation type requires signed overflow
7104 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7106 Get to the page base of the global offset table entry for a symbol as
7107 part of an ADRP instruction using a 21 bit PC relative value.Used in
7108 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7110 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7112 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7113 the GOT entry for this symbol. Used in conjunction with
7114 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7116 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7118 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7119 the GOT entry for this symbol. Used in conjunction with
7120 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7122 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7124 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7125 for this symbol. Valid in LP64 ABI only.
7127 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7129 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7130 for this symbol. Valid in LP64 ABI only.
7132 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7134 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7135 the GOT entry for this symbol. Valid in LP64 ABI only.
7137 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7139 Scaled 14 bit byte offset to the page base of the global offset table.
7141 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7143 Scaled 15 bit byte offset to the page base of the global offset table.
7145 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7147 Get to the page base of the global offset table entry for a symbols
7148 tls_index structure as part of an adrp instruction using a 21 bit PC
7149 relative value. Used in conjunction with
7150 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7152 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7154 AArch64 TLS General Dynamic
7156 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7158 Unsigned 12 bit byte offset to global offset table entry for a symbols
7159 tls_index structure. Used in conjunction with
7160 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7162 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7164 AArch64 TLS General Dynamic relocation.
7166 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7168 AArch64 TLS General Dynamic relocation.
7170 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7172 AArch64 TLS INITIAL EXEC relocation.
7174 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7176 AArch64 TLS INITIAL EXEC relocation.
7178 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7180 AArch64 TLS INITIAL EXEC relocation.
7182 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7184 AArch64 TLS INITIAL EXEC relocation.
7186 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7188 AArch64 TLS INITIAL EXEC relocation.
7190 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7192 AArch64 TLS INITIAL EXEC relocation.
7194 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7196 bit[23:12] of byte offset to module TLS base address.
7198 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7200 Unsigned 12 bit byte offset to module TLS base address.
7202 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7204 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7206 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7208 Unsigned 12 bit byte offset to global offset table entry for a symbols
7209 tls_index structure. Used in conjunction with
7210 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7212 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7214 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7217 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7219 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7221 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7223 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7226 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7228 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7230 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7232 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7235 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7237 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7239 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7241 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7244 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7246 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7248 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7250 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7253 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7255 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7257 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7259 bit[15:0] of byte offset to module TLS base address.
7261 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7263 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7265 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7267 bit[31:16] of byte offset to module TLS base address.
7269 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7271 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7273 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7275 bit[47:32] of byte offset to module TLS base address.
7277 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7279 AArch64 TLS LOCAL EXEC relocation.
7281 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7283 AArch64 TLS LOCAL EXEC relocation.
7285 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7287 AArch64 TLS LOCAL EXEC relocation.
7289 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7291 AArch64 TLS LOCAL EXEC relocation.
7293 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7295 AArch64 TLS LOCAL EXEC relocation.
7297 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7299 AArch64 TLS LOCAL EXEC relocation.
7301 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7303 AArch64 TLS LOCAL EXEC relocation.
7305 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7307 AArch64 TLS LOCAL EXEC relocation.
7309 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7311 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7314 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7316 Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
7318 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7320 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7323 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7325 Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
7327 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7329 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7332 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7334 Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
7336 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7338 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7341 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7343 Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
7345 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7347 AArch64 TLS DESC relocation.
7349 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7351 AArch64 TLS DESC relocation.
7353 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7355 AArch64 TLS DESC relocation.
7357 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7359 AArch64 TLS DESC relocation.
7361 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7363 AArch64 TLS DESC relocation.
7365 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7367 AArch64 TLS DESC relocation.
7369 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7371 AArch64 TLS DESC relocation.
7373 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7375 AArch64 TLS DESC relocation.
7377 BFD_RELOC_AARCH64_TLSDESC_LDR
7379 AArch64 TLS DESC relocation.
7381 BFD_RELOC_AARCH64_TLSDESC_ADD
7383 AArch64 TLS DESC relocation.
7385 BFD_RELOC_AARCH64_TLSDESC_CALL
7387 AArch64 TLS DESC relocation.
7389 BFD_RELOC_AARCH64_COPY
7391 AArch64 TLS relocation.
7393 BFD_RELOC_AARCH64_GLOB_DAT
7395 AArch64 TLS relocation.
7397 BFD_RELOC_AARCH64_JUMP_SLOT
7399 AArch64 TLS relocation.
7401 BFD_RELOC_AARCH64_RELATIVE
7403 AArch64 TLS relocation.
7405 BFD_RELOC_AARCH64_TLS_DTPMOD
7407 AArch64 TLS relocation.
7409 BFD_RELOC_AARCH64_TLS_DTPREL
7411 AArch64 TLS relocation.
7413 BFD_RELOC_AARCH64_TLS_TPREL
7415 AArch64 TLS relocation.
7417 BFD_RELOC_AARCH64_TLSDESC
7419 AArch64 TLS relocation.
7421 BFD_RELOC_AARCH64_IRELATIVE
7423 AArch64 support for STT_GNU_IFUNC.
7425 BFD_RELOC_AARCH64_RELOC_END
7427 AArch64 pseudo relocation code to mark the end of the AArch64
7428 relocation enumerators that have direct mapping to ELF reloc codes.
7429 There are a few more enumerators after this one; those are mainly
7430 used by the AArch64 assembler for the internal fixup or to select
7431 one of the above enumerators.
7433 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7435 AArch64 pseudo relocation code to be used internally by the AArch64
7436 assembler and not (currently) written to any object files.
7438 BFD_RELOC_AARCH64_LDST_LO12
7440 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7441 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7443 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7445 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7446 used internally by the AArch64 assembler and not (currently) written to
7449 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7451 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7453 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7455 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7456 used internally by the AArch64 assembler and not (currently) written to
7459 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7461 Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
7463 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7465 AArch64 pseudo relocation code to be used internally by the AArch64
7466 assembler and not (currently) written to any object files.
7468 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7470 AArch64 pseudo relocation code to be used internally by the AArch64
7471 assembler and not (currently) written to any object files.
7473 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7475 AArch64 pseudo relocation code to be used internally by the AArch64
7476 assembler and not (currently) written to any object files.
7478 BFD_RELOC_TILEPRO_COPY
7480 BFD_RELOC_TILEPRO_GLOB_DAT
7482 BFD_RELOC_TILEPRO_JMP_SLOT
7484 BFD_RELOC_TILEPRO_RELATIVE
7486 BFD_RELOC_TILEPRO_BROFF_X1
7488 BFD_RELOC_TILEPRO_JOFFLONG_X1
7490 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7492 BFD_RELOC_TILEPRO_IMM8_X0
7494 BFD_RELOC_TILEPRO_IMM8_Y0
7496 BFD_RELOC_TILEPRO_IMM8_X1
7498 BFD_RELOC_TILEPRO_IMM8_Y1
7500 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7502 BFD_RELOC_TILEPRO_MT_IMM15_X1
7504 BFD_RELOC_TILEPRO_MF_IMM15_X1
7506 BFD_RELOC_TILEPRO_IMM16_X0
7508 BFD_RELOC_TILEPRO_IMM16_X1
7510 BFD_RELOC_TILEPRO_IMM16_X0_LO
7512 BFD_RELOC_TILEPRO_IMM16_X1_LO
7514 BFD_RELOC_TILEPRO_IMM16_X0_HI
7516 BFD_RELOC_TILEPRO_IMM16_X1_HI
7518 BFD_RELOC_TILEPRO_IMM16_X0_HA
7520 BFD_RELOC_TILEPRO_IMM16_X1_HA
7522 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7524 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7526 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7528 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7530 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7532 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7534 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7536 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7538 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7540 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7542 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7544 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7546 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7548 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7550 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7552 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7554 BFD_RELOC_TILEPRO_MMSTART_X0
7556 BFD_RELOC_TILEPRO_MMEND_X0
7558 BFD_RELOC_TILEPRO_MMSTART_X1
7560 BFD_RELOC_TILEPRO_MMEND_X1
7562 BFD_RELOC_TILEPRO_SHAMT_X0
7564 BFD_RELOC_TILEPRO_SHAMT_X1
7566 BFD_RELOC_TILEPRO_SHAMT_Y0
7568 BFD_RELOC_TILEPRO_SHAMT_Y1
7570 BFD_RELOC_TILEPRO_TLS_GD_CALL
7572 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7574 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7576 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7578 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7580 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7582 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7584 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7586 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7588 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7590 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7592 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7594 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7596 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7598 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7600 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7602 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7604 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7606 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7608 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7610 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7612 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7614 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7616 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7618 BFD_RELOC_TILEPRO_TLS_TPOFF32
7620 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7622 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7624 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7626 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7628 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7630 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7632 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7634 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7636 Tilera TILEPro Relocations.
7638 BFD_RELOC_TILEGX_HW0
7640 BFD_RELOC_TILEGX_HW1
7642 BFD_RELOC_TILEGX_HW2
7644 BFD_RELOC_TILEGX_HW3
7646 BFD_RELOC_TILEGX_HW0_LAST
7648 BFD_RELOC_TILEGX_HW1_LAST
7650 BFD_RELOC_TILEGX_HW2_LAST
7652 BFD_RELOC_TILEGX_COPY
7654 BFD_RELOC_TILEGX_GLOB_DAT
7656 BFD_RELOC_TILEGX_JMP_SLOT
7658 BFD_RELOC_TILEGX_RELATIVE
7660 BFD_RELOC_TILEGX_BROFF_X1
7662 BFD_RELOC_TILEGX_JUMPOFF_X1
7664 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7666 BFD_RELOC_TILEGX_IMM8_X0
7668 BFD_RELOC_TILEGX_IMM8_Y0
7670 BFD_RELOC_TILEGX_IMM8_X1
7672 BFD_RELOC_TILEGX_IMM8_Y1
7674 BFD_RELOC_TILEGX_DEST_IMM8_X1
7676 BFD_RELOC_TILEGX_MT_IMM14_X1
7678 BFD_RELOC_TILEGX_MF_IMM14_X1
7680 BFD_RELOC_TILEGX_MMSTART_X0
7682 BFD_RELOC_TILEGX_MMEND_X0
7684 BFD_RELOC_TILEGX_SHAMT_X0
7686 BFD_RELOC_TILEGX_SHAMT_X1
7688 BFD_RELOC_TILEGX_SHAMT_Y0
7690 BFD_RELOC_TILEGX_SHAMT_Y1
7692 BFD_RELOC_TILEGX_IMM16_X0_HW0
7694 BFD_RELOC_TILEGX_IMM16_X1_HW0
7696 BFD_RELOC_TILEGX_IMM16_X0_HW1
7698 BFD_RELOC_TILEGX_IMM16_X1_HW1
7700 BFD_RELOC_TILEGX_IMM16_X0_HW2
7702 BFD_RELOC_TILEGX_IMM16_X1_HW2
7704 BFD_RELOC_TILEGX_IMM16_X0_HW3
7706 BFD_RELOC_TILEGX_IMM16_X1_HW3
7708 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7710 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7712 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7714 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7716 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7718 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7720 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7722 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7724 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7726 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7728 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7730 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7732 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7734 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7736 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7738 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7740 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7742 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7744 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7746 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7748 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7750 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7752 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7754 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7756 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7758 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7760 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7762 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7764 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7766 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7768 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7770 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7772 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7774 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7776 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7778 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7780 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7782 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7784 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7786 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7788 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7790 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7792 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7794 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7796 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7798 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7800 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7802 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7804 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7806 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7808 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7810 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7812 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7814 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7816 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7818 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7820 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7822 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7824 BFD_RELOC_TILEGX_TLS_DTPMOD64
7826 BFD_RELOC_TILEGX_TLS_DTPOFF64
7828 BFD_RELOC_TILEGX_TLS_TPOFF64
7830 BFD_RELOC_TILEGX_TLS_DTPMOD32
7832 BFD_RELOC_TILEGX_TLS_DTPOFF32
7834 BFD_RELOC_TILEGX_TLS_TPOFF32
7836 BFD_RELOC_TILEGX_TLS_GD_CALL
7838 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7840 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7842 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7844 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7846 BFD_RELOC_TILEGX_TLS_IE_LOAD
7848 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7850 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7852 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7854 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7856 Tilera TILE-Gx Relocations.
7859 BFD_RELOC_EPIPHANY_SIMM8
7861 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7863 BFD_RELOC_EPIPHANY_SIMM24
7865 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7867 BFD_RELOC_EPIPHANY_HIGH
7869 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7871 BFD_RELOC_EPIPHANY_LOW
7873 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7875 BFD_RELOC_EPIPHANY_SIMM11
7877 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7879 BFD_RELOC_EPIPHANY_IMM11
7881 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7883 BFD_RELOC_EPIPHANY_IMM8
7885 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7888 BFD_RELOC_VISIUM_HI16
7890 BFD_RELOC_VISIUM_LO16
7892 BFD_RELOC_VISIUM_IM16
7894 BFD_RELOC_VISIUM_REL16
7896 BFD_RELOC_VISIUM_HI16_PCREL
7898 BFD_RELOC_VISIUM_LO16_PCREL
7900 BFD_RELOC_VISIUM_IM16_PCREL
7905 BFD_RELOC_WASM32_LEB128
7907 BFD_RELOC_WASM32_LEB128_GOT
7909 BFD_RELOC_WASM32_LEB128_GOT_CODE
7911 BFD_RELOC_WASM32_LEB128_PLT
7913 BFD_RELOC_WASM32_PLT_INDEX
7915 BFD_RELOC_WASM32_ABS32_CODE
7917 BFD_RELOC_WASM32_COPY
7919 BFD_RELOC_WASM32_CODE_POINTER
7921 BFD_RELOC_WASM32_INDEX
7923 BFD_RELOC_WASM32_PLT_SIG
7925 WebAssembly relocations.
7928 BFD_RELOC_CKCORE_NONE
7930 BFD_RELOC_CKCORE_ADDR32
7932 BFD_RELOC_CKCORE_PCREL_IMM8BY4
7934 BFD_RELOC_CKCORE_PCREL_IMM11BY2
7936 BFD_RELOC_CKCORE_PCREL_IMM4BY2
7938 BFD_RELOC_CKCORE_PCREL32
7940 BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2
7942 BFD_RELOC_CKCORE_GNU_VTINHERIT
7944 BFD_RELOC_CKCORE_GNU_VTENTRY
7946 BFD_RELOC_CKCORE_RELATIVE
7948 BFD_RELOC_CKCORE_COPY
7950 BFD_RELOC_CKCORE_GLOB_DAT
7952 BFD_RELOC_CKCORE_JUMP_SLOT
7954 BFD_RELOC_CKCORE_GOTOFF
7956 BFD_RELOC_CKCORE_GOTPC
7958 BFD_RELOC_CKCORE_GOT32
7960 BFD_RELOC_CKCORE_PLT32
7962 BFD_RELOC_CKCORE_ADDRGOT
7964 BFD_RELOC_CKCORE_ADDRPLT
7966 BFD_RELOC_CKCORE_PCREL_IMM26BY2
7968 BFD_RELOC_CKCORE_PCREL_IMM16BY2
7970 BFD_RELOC_CKCORE_PCREL_IMM16BY4
7972 BFD_RELOC_CKCORE_PCREL_IMM10BY2
7974 BFD_RELOC_CKCORE_PCREL_IMM10BY4
7976 BFD_RELOC_CKCORE_ADDR_HI16
7978 BFD_RELOC_CKCORE_ADDR_LO16
7980 BFD_RELOC_CKCORE_GOTPC_HI16
7982 BFD_RELOC_CKCORE_GOTPC_LO16
7984 BFD_RELOC_CKCORE_GOTOFF_HI16
7986 BFD_RELOC_CKCORE_GOTOFF_LO16
7988 BFD_RELOC_CKCORE_GOT12
7990 BFD_RELOC_CKCORE_GOT_HI16
7992 BFD_RELOC_CKCORE_GOT_LO16
7994 BFD_RELOC_CKCORE_PLT12
7996 BFD_RELOC_CKCORE_PLT_HI16
7998 BFD_RELOC_CKCORE_PLT_LO16
8000 BFD_RELOC_CKCORE_ADDRGOT_HI16
8002 BFD_RELOC_CKCORE_ADDRGOT_LO16
8004 BFD_RELOC_CKCORE_ADDRPLT_HI16
8006 BFD_RELOC_CKCORE_ADDRPLT_LO16
8008 BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2
8010 BFD_RELOC_CKCORE_TOFFSET_LO16
8012 BFD_RELOC_CKCORE_DOFFSET_LO16
8014 BFD_RELOC_CKCORE_PCREL_IMM18BY2
8016 BFD_RELOC_CKCORE_DOFFSET_IMM18
8018 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2
8020 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4
8022 BFD_RELOC_CKCORE_GOTOFF_IMM18
8024 BFD_RELOC_CKCORE_GOT_IMM18BY4
8026 BFD_RELOC_CKCORE_PLT_IMM18BY4
8028 BFD_RELOC_CKCORE_PCREL_IMM7BY4
8030 BFD_RELOC_CKCORE_TLS_LE32
8032 BFD_RELOC_CKCORE_TLS_IE32
8034 BFD_RELOC_CKCORE_TLS_GD32
8036 BFD_RELOC_CKCORE_TLS_LDM32
8038 BFD_RELOC_CKCORE_TLS_LDO32
8040 BFD_RELOC_CKCORE_TLS_DTPMOD32
8042 BFD_RELOC_CKCORE_TLS_DTPOFF32
8044 BFD_RELOC_CKCORE_TLS_TPOFF32
8046 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
8048 BFD_RELOC_CKCORE_NOJSRI
8050 BFD_RELOC_CKCORE_CALLGRAPH
8052 BFD_RELOC_CKCORE_IRELATIVE
8054 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4
8056 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4
8069 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
8074 bfd_reloc_type_lookup
8075 bfd_reloc_name_lookup
8078 reloc_howto_type *bfd_reloc_type_lookup
8079 (bfd *abfd, bfd_reloc_code_real_type code);
8080 reloc_howto_type *bfd_reloc_name_lookup
8081 (bfd *abfd, const char *reloc_name);
8084 Return a pointer to a howto structure which, when
8085 invoked, will perform the relocation @var{code} on data from the
8091 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8093 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
8097 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
8099 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
8102 static reloc_howto_type bfd_howto_32
=
8103 HOWTO (0, 00, 2, 32, FALSE
, 0, complain_overflow_dont
, 0, "VRT32", FALSE
, 0xffffffff, 0xffffffff, TRUE
);
8107 bfd_default_reloc_type_lookup
8110 reloc_howto_type *bfd_default_reloc_type_lookup
8111 (bfd *abfd, bfd_reloc_code_real_type code);
8114 Provides a default relocation lookup routine for any architecture.
8119 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8123 case BFD_RELOC_CTOR
:
8124 /* The type of reloc used in a ctor, which will be as wide as the
8125 address - so either a 64, 32, or 16 bitter. */
8126 switch (bfd_arch_bits_per_address (abfd
))
8132 return &bfd_howto_32
;
8148 bfd_get_reloc_code_name
8151 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8154 Provides a printable name for the supplied relocation code.
8155 Useful mainly for printing error messages.
8159 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
8161 if (code
> BFD_RELOC_UNUSED
)
8163 return bfd_reloc_code_real_names
[code
];
8168 bfd_generic_relax_section
8171 bfd_boolean bfd_generic_relax_section
8174 struct bfd_link_info *,
8178 Provides default handling for relaxing for back ends which
8183 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
8184 asection
*section ATTRIBUTE_UNUSED
,
8185 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
8188 if (bfd_link_relocatable (link_info
))
8189 (*link_info
->callbacks
->einfo
)
8190 (_("%P%F: --relax and -r may not be used together\n"));
8198 bfd_generic_gc_sections
8201 bfd_boolean bfd_generic_gc_sections
8202 (bfd *, struct bfd_link_info *);
8205 Provides default handling for relaxing for back ends which
8206 don't do section gc -- i.e., does nothing.
8210 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8211 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
8218 bfd_generic_lookup_section_flags
8221 bfd_boolean bfd_generic_lookup_section_flags
8222 (struct bfd_link_info *, struct flag_info *, asection *);
8225 Provides default handling for section flags lookup
8226 -- i.e., does nothing.
8227 Returns FALSE if the section should be omitted, otherwise TRUE.
8231 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
8232 struct flag_info
*flaginfo
,
8233 asection
*section ATTRIBUTE_UNUSED
)
8235 if (flaginfo
!= NULL
)
8237 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8245 bfd_generic_merge_sections
8248 bfd_boolean bfd_generic_merge_sections
8249 (bfd *, struct bfd_link_info *);
8252 Provides default handling for SEC_MERGE section merging for back ends
8253 which don't have SEC_MERGE support -- i.e., does nothing.
8257 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8258 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
8265 bfd_generic_get_relocated_section_contents
8268 bfd_byte *bfd_generic_get_relocated_section_contents
8270 struct bfd_link_info *link_info,
8271 struct bfd_link_order *link_order,
8273 bfd_boolean relocatable,
8277 Provides default handling of relocation effort for back ends
8278 which can't be bothered to do it efficiently.
8283 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
8284 struct bfd_link_info
*link_info
,
8285 struct bfd_link_order
*link_order
,
8287 bfd_boolean relocatable
,
8290 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
8291 asection
*input_section
= link_order
->u
.indirect
.section
;
8293 arelent
**reloc_vector
;
8296 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
8300 /* Read in the section. */
8301 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
8307 if (reloc_size
== 0)
8310 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
8311 if (reloc_vector
== NULL
)
8314 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
8318 if (reloc_count
< 0)
8321 if (reloc_count
> 0)
8325 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
8327 char *error_message
= NULL
;
8329 bfd_reloc_status_type r
;
8331 symbol
= *(*parent
)->sym_ptr_ptr
;
8332 /* PR ld/19628: A specially crafted input file
8333 can result in a NULL symbol pointer here. */
8336 link_info
->callbacks
->einfo
8337 /* xgettext:c-format */
8338 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8339 abfd
, input_section
, (* parent
)->address
);
8343 /* Zap reloc field when the symbol is from a discarded
8344 section, ignoring any addend. Do the same when called
8345 from bfd_simple_get_relocated_section_contents for
8346 undefined symbols in debug sections. This is to keep
8347 debug info reasonably sane, in particular so that
8348 DW_FORM_ref_addr to another file's .debug_info isn't
8349 confused with an offset into the current file's
8351 if ((symbol
->section
!= NULL
&& discarded_section (symbol
->section
))
8352 || (symbol
->section
== bfd_und_section_ptr
8353 && (input_section
->flags
& SEC_DEBUGGING
) != 0
8354 && link_info
->input_bfds
== link_info
->output_bfd
))
8357 static reloc_howto_type none_howto
8358 = HOWTO (0, 0, 0, 0, FALSE
, 0, complain_overflow_dont
, NULL
,
8359 "unused", FALSE
, 0, 0, FALSE
);
8361 off
= (*parent
)->address
* bfd_octets_per_byte (input_bfd
);
8362 _bfd_clear_contents ((*parent
)->howto
, input_bfd
,
8363 input_section
, data
, off
);
8364 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
8365 (*parent
)->addend
= 0;
8366 (*parent
)->howto
= &none_howto
;
8370 r
= bfd_perform_relocation (input_bfd
,
8374 relocatable
? abfd
: NULL
,
8379 asection
*os
= input_section
->output_section
;
8381 /* A partial link, so keep the relocs. */
8382 os
->orelocation
[os
->reloc_count
] = *parent
;
8386 if (r
!= bfd_reloc_ok
)
8390 case bfd_reloc_undefined
:
8391 (*link_info
->callbacks
->undefined_symbol
)
8392 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8393 input_bfd
, input_section
, (*parent
)->address
, TRUE
);
8395 case bfd_reloc_dangerous
:
8396 BFD_ASSERT (error_message
!= NULL
);
8397 (*link_info
->callbacks
->reloc_dangerous
)
8398 (link_info
, error_message
,
8399 input_bfd
, input_section
, (*parent
)->address
);
8401 case bfd_reloc_overflow
:
8402 (*link_info
->callbacks
->reloc_overflow
)
8404 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8405 (*parent
)->howto
->name
, (*parent
)->addend
,
8406 input_bfd
, input_section
, (*parent
)->address
);
8408 case bfd_reloc_outofrange
:
8410 This error can result when processing some partially
8411 complete binaries. Do not abort, but issue an error
8413 link_info
->callbacks
->einfo
8414 /* xgettext:c-format */
8415 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8416 abfd
, input_section
, * parent
);
8419 case bfd_reloc_notsupported
:
8421 This error can result when processing a corrupt binary.
8422 Do not abort. Issue an error message instead. */
8423 link_info
->callbacks
->einfo
8424 /* xgettext:c-format */
8425 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8426 abfd
, input_section
, * parent
);
8430 /* PR 17512; file: 90c2a92e.
8431 Report unexpected results, without aborting. */
8432 link_info
->callbacks
->einfo
8433 /* xgettext:c-format */
8434 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8435 abfd
, input_section
, * parent
, r
);
8443 free (reloc_vector
);
8447 free (reloc_vector
);
8453 _bfd_generic_set_reloc
8456 void _bfd_generic_set_reloc
8460 unsigned int count);
8463 Installs a new set of internal relocations in SECTION.
8467 _bfd_generic_set_reloc (bfd
*abfd ATTRIBUTE_UNUSED
,
8472 section
->orelocation
= relptr
;
8473 section
->reloc_count
= count
;
8478 _bfd_unrecognized_reloc
8481 bfd_boolean _bfd_unrecognized_reloc
8484 unsigned int r_type);
8487 Reports an unrecognized reloc.
8488 Written as a function in order to reduce code duplication.
8489 Returns FALSE so that it can be called from a return statement.
8493 _bfd_unrecognized_reloc (bfd
* abfd
, sec_ptr section
, unsigned int r_type
)
8495 /* xgettext:c-format */
8496 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8497 abfd
, r_type
, section
);
8499 /* PR 21803: Suggest the most likely cause of this error. */
8500 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8501 BFD_VERSION_STRING
);
8503 bfd_set_error (bfd_error_bad_value
);
8508 _bfd_norelocs_bfd_reloc_type_lookup
8510 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED
)
8512 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8516 _bfd_norelocs_bfd_reloc_name_lookup (bfd
*abfd
,
8517 const char *reloc_name ATTRIBUTE_UNUSED
)
8519 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8523 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd
*abfd
,
8524 arelent
**relp ATTRIBUTE_UNUSED
,
8525 asymbol
**symp ATTRIBUTE_UNUSED
)
8527 return _bfd_long_bfd_n1_error (abfd
);