1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2022 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* SME horizontal or vertical slice indicator, encoded in "V".
113 /* Bits for DEFINED field in vector_type_el. */
114 #define NTA_HASTYPE 1
115 #define NTA_HASINDEX 2
116 #define NTA_HASVARWIDTH 4
118 struct vector_type_el
120 enum vector_el_type type
;
121 unsigned char defined
;
126 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
130 bfd_reloc_code_real_type type
;
133 enum aarch64_opnd opnd
;
135 unsigned need_libopcodes_p
: 1;
138 struct aarch64_instruction
140 /* libopcodes structure for instruction intermediate representation. */
142 /* Record assembly errors found during the parsing. */
145 enum aarch64_operand_error_kind kind
;
148 /* The condition that appears in the assembly line. */
150 /* Relocation information (including the GAS internal fixup). */
152 /* Need to generate an immediate in the literal pool. */
153 unsigned gen_lit_pool
: 1;
156 typedef struct aarch64_instruction aarch64_instruction
;
158 static aarch64_instruction inst
;
160 static bool parse_operands (char *, const aarch64_opcode
*);
161 static bool programmer_friendly_fixup (aarch64_instruction
*);
163 /* Diagnostics inline function utilities.
165 These are lightweight utilities which should only be called by parse_operands
166 and other parsers. GAS processes each assembly line by parsing it against
167 instruction template(s), in the case of multiple templates (for the same
168 mnemonic name), those templates are tried one by one until one succeeds or
169 all fail. An assembly line may fail a few templates before being
170 successfully parsed; an error saved here in most cases is not a user error
171 but an error indicating the current template is not the right template.
172 Therefore it is very important that errors can be saved at a low cost during
173 the parsing; we don't want to slow down the whole parsing by recording
174 non-user errors in detail.
176 Remember that the objective is to help GAS pick up the most appropriate
177 error message in the case of multiple templates, e.g. FMOV which has 8
183 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
184 inst
.parsing_error
.error
= NULL
;
190 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
193 static inline const char *
194 get_error_message (void)
196 return inst
.parsing_error
.error
;
199 static inline enum aarch64_operand_error_kind
200 get_error_kind (void)
202 return inst
.parsing_error
.kind
;
206 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
208 inst
.parsing_error
.kind
= kind
;
209 inst
.parsing_error
.error
= error
;
213 set_recoverable_error (const char *error
)
215 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
218 /* Use the DESC field of the corresponding aarch64_operand entry to compose
219 the error message. */
221 set_default_error (void)
223 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
227 set_syntax_error (const char *error
)
229 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
233 set_first_syntax_error (const char *error
)
236 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
240 set_fatal_syntax_error (const char *error
)
242 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
245 /* Return value for certain parsers when the parsing fails; those parsers
246 return the information of the parsed result, e.g. register number, on
248 #define PARSE_FAIL -1
250 /* This is an invalid condition code that means no conditional field is
252 #define COND_ALWAYS 0x10
256 const char *template;
263 bfd_reloc_code_real_type reloc
;
266 /* Macros to define the register types and masks for the purpose
269 #undef AARCH64_REG_TYPES
270 #define AARCH64_REG_TYPES \
271 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
272 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
273 BASIC_REG_TYPE(SP_32) /* wsp */ \
274 BASIC_REG_TYPE(SP_64) /* sp */ \
275 BASIC_REG_TYPE(Z_32) /* wzr */ \
276 BASIC_REG_TYPE(Z_64) /* xzr */ \
277 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
278 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
279 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
280 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
281 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
282 BASIC_REG_TYPE(VN) /* v[0-31] */ \
283 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
284 BASIC_REG_TYPE(PN) /* p[0-15] */ \
285 BASIC_REG_TYPE(ZA) /* za[0-15] */ \
286 BASIC_REG_TYPE(ZAH) /* za[0-15]h */ \
287 BASIC_REG_TYPE(ZAV) /* za[0-15]v */ \
288 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
289 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
290 /* Typecheck: same, plus SVE registers. */ \
291 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
293 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
294 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
295 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
296 /* Typecheck: same, plus SVE registers. */ \
297 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
298 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
300 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
301 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
302 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
303 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
304 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
305 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
306 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
307 /* Typecheck: any [BHSDQ]P FP. */ \
308 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
309 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
310 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
311 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
312 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
313 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
314 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
315 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
316 be used for SVE instructions, since Zn and Pn are valid symbols \
317 in other contexts. */ \
318 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
319 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
320 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
321 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
322 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
323 | REG_TYPE(ZN) | REG_TYPE(PN)) \
324 /* Any integer register; used for error messages only. */ \
325 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
326 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
327 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
328 /* Pseudo type to mark the end of the enumerator sequence. */ \
331 #undef BASIC_REG_TYPE
332 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
333 #undef MULTI_REG_TYPE
334 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
336 /* Register type enumerators. */
337 typedef enum aarch64_reg_type_
339 /* A list of REG_TYPE_*. */
343 #undef BASIC_REG_TYPE
344 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
346 #define REG_TYPE(T) (1 << REG_TYPE_##T)
347 #undef MULTI_REG_TYPE
348 #define MULTI_REG_TYPE(T,V) V,
350 /* Structure for a hash table entry for a register. */
354 unsigned char number
;
355 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
356 unsigned char builtin
;
359 /* Values indexed by aarch64_reg_type to assist the type checking. */
360 static const unsigned reg_type_masks
[] =
365 #undef BASIC_REG_TYPE
367 #undef MULTI_REG_TYPE
368 #undef AARCH64_REG_TYPES
370 /* Diagnostics used when we don't get a register of the expected type.
371 Note: this has to synchronized with aarch64_reg_type definitions
374 get_reg_expected_msg (aarch64_reg_type reg_type
)
381 msg
= N_("integer 32-bit register expected");
384 msg
= N_("integer 64-bit register expected");
387 msg
= N_("integer register expected");
389 case REG_TYPE_R64_SP
:
390 msg
= N_("64-bit integer or SP register expected");
392 case REG_TYPE_SVE_BASE
:
393 msg
= N_("base register expected");
396 msg
= N_("integer or zero register expected");
398 case REG_TYPE_SVE_OFFSET
:
399 msg
= N_("offset register expected");
402 msg
= N_("integer or SP register expected");
404 case REG_TYPE_R_Z_SP
:
405 msg
= N_("integer, zero or SP register expected");
408 msg
= N_("8-bit SIMD scalar register expected");
411 msg
= N_("16-bit SIMD scalar or floating-point half precision "
412 "register expected");
415 msg
= N_("32-bit SIMD scalar or floating-point single precision "
416 "register expected");
419 msg
= N_("64-bit SIMD scalar or floating-point double precision "
420 "register expected");
423 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
424 "register expected");
426 case REG_TYPE_R_Z_BHSDQ_V
:
427 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
428 msg
= N_("register expected");
430 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
431 msg
= N_("SIMD scalar or floating-point register expected");
433 case REG_TYPE_VN
: /* any V reg */
434 msg
= N_("vector register expected");
437 msg
= N_("SVE vector register expected");
440 msg
= N_("SVE predicate register expected");
443 as_fatal (_("invalid register type %d"), reg_type
);
448 /* Some well known registers that we refer to directly elsewhere. */
452 /* Instructions take 4 bytes in the object file. */
455 static htab_t aarch64_ops_hsh
;
456 static htab_t aarch64_cond_hsh
;
457 static htab_t aarch64_shift_hsh
;
458 static htab_t aarch64_sys_regs_hsh
;
459 static htab_t aarch64_pstatefield_hsh
;
460 static htab_t aarch64_sys_regs_ic_hsh
;
461 static htab_t aarch64_sys_regs_dc_hsh
;
462 static htab_t aarch64_sys_regs_at_hsh
;
463 static htab_t aarch64_sys_regs_tlbi_hsh
;
464 static htab_t aarch64_sys_regs_sr_hsh
;
465 static htab_t aarch64_reg_hsh
;
466 static htab_t aarch64_barrier_opt_hsh
;
467 static htab_t aarch64_nzcv_hsh
;
468 static htab_t aarch64_pldop_hsh
;
469 static htab_t aarch64_hint_opt_hsh
;
471 /* Stuff needed to resolve the label ambiguity
480 static symbolS
*last_label_seen
;
482 /* Literal pool structure. Held on a per-section
483 and per-sub-section basis. */
485 #define MAX_LITERAL_POOL_SIZE 1024
486 typedef struct literal_expression
489 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
490 LITTLENUM_TYPE
* bignum
;
491 } literal_expression
;
493 typedef struct literal_pool
495 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
496 unsigned int next_free_entry
;
502 struct literal_pool
*next
;
505 /* Pointer to a linked list of literal pools. */
506 static literal_pool
*list_of_pools
= NULL
;
510 /* This array holds the chars that always start a comment. If the
511 pre-processor is disabled, these aren't very useful. */
512 const char comment_chars
[] = "";
514 /* This array holds the chars that only start a comment at the beginning of
515 a line. If the line seems to have the form '# 123 filename'
516 .line and .file directives will appear in the pre-processed output. */
517 /* Note that input_file.c hand checks for '#' at the beginning of the
518 first line of the input file. This is because the compiler outputs
519 #NO_APP at the beginning of its output. */
520 /* Also note that comments like this one will always work. */
521 const char line_comment_chars
[] = "#";
523 const char line_separator_chars
[] = ";";
525 /* Chars that can be used to separate mant
526 from exp in floating point numbers. */
527 const char EXP_CHARS
[] = "eE";
529 /* Chars that mean this number is a floating point constant. */
533 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhHb";
535 /* Prefix character that indicates the start of an immediate value. */
536 #define is_immediate_prefix(C) ((C) == '#')
538 /* Separator character handling. */
540 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
543 skip_past_char (char **str
, char c
)
554 #define skip_past_comma(str) skip_past_char (str, ',')
556 /* Arithmetic expressions (possibly involving symbols). */
558 static bool in_aarch64_get_expression
= false;
560 /* Third argument to aarch64_get_expression. */
561 #define GE_NO_PREFIX false
562 #define GE_OPT_PREFIX true
564 /* Fourth argument to aarch64_get_expression. */
565 #define ALLOW_ABSENT false
566 #define REJECT_ABSENT true
568 /* Fifth argument to aarch64_get_expression. */
569 #define NORMAL_RESOLUTION false
571 /* Return TRUE if the string pointed by *STR is successfully parsed
572 as an valid expression; *EP will be filled with the information of
573 such an expression. Otherwise return FALSE.
575 If ALLOW_IMMEDIATE_PREFIX is true then skip a '#' at the start.
576 If REJECT_ABSENT is true then trat missing expressions as an error.
577 If DEFER_RESOLUTION is true, then do not resolve expressions against
578 constant symbols. Necessary if the expression is part of a fixup
579 that uses a reloc that must be emitted. */
582 aarch64_get_expression (expressionS
* ep
,
584 bool allow_immediate_prefix
,
586 bool defer_resolution
)
590 bool prefix_present
= false;
592 if (allow_immediate_prefix
)
594 if (is_immediate_prefix (**str
))
597 prefix_present
= true;
601 memset (ep
, 0, sizeof (expressionS
));
603 save_in
= input_line_pointer
;
604 input_line_pointer
= *str
;
605 in_aarch64_get_expression
= true;
606 if (defer_resolution
)
607 seg
= deferred_expression (ep
);
609 seg
= expression (ep
);
610 in_aarch64_get_expression
= false;
612 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
614 /* We found a bad expression in md_operand(). */
615 *str
= input_line_pointer
;
616 input_line_pointer
= save_in
;
617 if (prefix_present
&& ! error_p ())
618 set_fatal_syntax_error (_("bad expression"));
620 set_first_syntax_error (_("bad expression"));
625 if (seg
!= absolute_section
626 && seg
!= text_section
627 && seg
!= data_section
628 && seg
!= bss_section
629 && seg
!= undefined_section
)
631 set_syntax_error (_("bad segment"));
632 *str
= input_line_pointer
;
633 input_line_pointer
= save_in
;
640 *str
= input_line_pointer
;
641 input_line_pointer
= save_in
;
645 /* Turn a string in input_line_pointer into a floating point constant
646 of type TYPE, and store the appropriate bytes in *LITP. The number
647 of LITTLENUMS emitted is stored in *SIZEP. An error message is
648 returned, or NULL on OK. */
651 md_atof (int type
, char *litP
, int *sizeP
)
653 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
656 /* We handle all bad expressions here, so that we can report the faulty
657 instruction in the error message. */
659 md_operand (expressionS
* exp
)
661 if (in_aarch64_get_expression
)
662 exp
->X_op
= O_illegal
;
665 /* Immediate values. */
667 /* Errors may be set multiple times during parsing or bit encoding
668 (particularly in the Neon bits), but usually the earliest error which is set
669 will be the most meaningful. Avoid overwriting it with later (cascading)
670 errors by calling this function. */
673 first_error (const char *error
)
676 set_syntax_error (error
);
679 /* Similar to first_error, but this function accepts formatted error
682 first_error_fmt (const char *format
, ...)
687 /* N.B. this single buffer will not cause error messages for different
688 instructions to pollute each other; this is because at the end of
689 processing of each assembly line, error message if any will be
690 collected by as_bad. */
691 static char buffer
[size
];
695 int ret ATTRIBUTE_UNUSED
;
696 va_start (args
, format
);
697 ret
= vsnprintf (buffer
, size
, format
, args
);
698 know (ret
<= size
- 1 && ret
>= 0);
700 set_syntax_error (buffer
);
704 /* Register parsing. */
706 /* Generic register parser which is called by other specialized
708 CCP points to what should be the beginning of a register name.
709 If it is indeed a valid register name, advance CCP over it and
710 return the reg_entry structure; otherwise return NULL.
711 It does not issue diagnostics. */
714 parse_reg (char **ccp
)
720 #ifdef REGISTER_PREFIX
721 if (*start
!= REGISTER_PREFIX
)
727 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
732 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
734 reg
= (reg_entry
*) str_hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
743 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
746 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
748 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
751 /* Try to parse a base or offset register. Allow SVE base and offset
752 registers if REG_TYPE includes SVE registers. Return the register
753 entry on success, setting *QUALIFIER to the register qualifier.
754 Return null otherwise.
756 Note that this function does not issue any diagnostics. */
758 static const reg_entry
*
759 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
760 aarch64_opnd_qualifier_t
*qualifier
)
763 const reg_entry
*reg
= parse_reg (&str
);
773 *qualifier
= AARCH64_OPND_QLF_W
;
779 *qualifier
= AARCH64_OPND_QLF_X
;
783 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
786 switch (TOLOWER (str
[1]))
789 *qualifier
= AARCH64_OPND_QLF_S_S
;
792 *qualifier
= AARCH64_OPND_QLF_S_D
;
809 /* Try to parse a base or offset register. Return the register entry
810 on success, setting *QUALIFIER to the register qualifier. Return null
813 Note that this function does not issue any diagnostics. */
815 static const reg_entry
*
816 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
818 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
821 /* Parse the qualifier of a vector register or vector element of type
822 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
823 succeeds; otherwise return FALSE.
825 Accept only one occurrence of:
826 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
829 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
830 struct vector_type_el
*parsed_type
, char **str
)
834 unsigned element_size
;
835 enum vector_el_type type
;
838 gas_assert (*ptr
== '.');
841 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
846 width
= strtoul (ptr
, &ptr
, 10);
847 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
849 first_error_fmt (_("bad size %d in vector width specifier"), width
);
854 switch (TOLOWER (*ptr
))
873 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
882 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
884 first_error (_("missing element size"));
887 if (width
!= 0 && width
* element_size
!= 64
888 && width
* element_size
!= 128
889 && !(width
== 2 && element_size
== 16)
890 && !(width
== 4 && element_size
== 8))
893 ("invalid element size %d and vector size combination %c"),
899 parsed_type
->type
= type
;
900 parsed_type
->width
= width
;
907 /* *STR contains an SVE zero/merge predication suffix. Parse it into
908 *PARSED_TYPE and point *STR at the end of the suffix. */
911 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
916 gas_assert (*ptr
== '/');
918 switch (TOLOWER (*ptr
))
921 parsed_type
->type
= NT_zero
;
924 parsed_type
->type
= NT_merge
;
927 if (*ptr
!= '\0' && *ptr
!= ',')
928 first_error_fmt (_("unexpected character `%c' in predication type"),
931 first_error (_("missing predication type"));
934 parsed_type
->width
= 0;
939 /* Parse a register of the type TYPE.
941 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
942 name or the parsed register is not of TYPE.
944 Otherwise return the register number, and optionally fill in the actual
945 type of the register in *RTYPE when multiple alternatives were given, and
946 return the register shape and element index information in *TYPEINFO.
948 IN_REG_LIST should be set with TRUE if the caller is parsing a register
952 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
953 struct vector_type_el
*typeinfo
, bool in_reg_list
)
956 const reg_entry
*reg
= parse_reg (&str
);
957 struct vector_type_el atype
;
958 struct vector_type_el parsetype
;
959 bool is_typed_vecreg
= false;
962 atype
.type
= NT_invtype
;
970 set_default_error ();
974 if (! aarch64_check_reg_type (reg
, type
))
976 DEBUG_TRACE ("reg type check failed");
977 set_default_error ();
982 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
983 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
987 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
992 if (!parse_predication_for_operand (&parsetype
, &str
))
996 /* Register if of the form Vn.[bhsdq]. */
997 is_typed_vecreg
= true;
999 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
1001 /* The width is always variable; we don't allow an integer width
1003 gas_assert (parsetype
.width
== 0);
1004 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
1006 else if (parsetype
.width
== 0)
1007 /* Expect index. In the new scheme we cannot have
1008 Vn.[bhsdq] represent a scalar. Therefore any
1009 Vn.[bhsdq] should have an index following it.
1010 Except in reglists of course. */
1011 atype
.defined
|= NTA_HASINDEX
;
1013 atype
.defined
|= NTA_HASTYPE
;
1015 atype
.type
= parsetype
.type
;
1016 atype
.width
= parsetype
.width
;
1019 if (skip_past_char (&str
, '['))
1023 /* Reject Sn[index] syntax. */
1024 if (!is_typed_vecreg
)
1026 first_error (_("this type of register can't be indexed"));
1032 first_error (_("index not allowed inside register list"));
1036 atype
.defined
|= NTA_HASINDEX
;
1038 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
,
1041 if (exp
.X_op
!= O_constant
)
1043 first_error (_("constant expression required"));
1047 if (! skip_past_char (&str
, ']'))
1050 atype
.index
= exp
.X_add_number
;
1052 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1054 /* Indexed vector register expected. */
1055 first_error (_("indexed vector register expected"));
1059 /* A vector reg Vn should be typed or indexed. */
1060 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1062 first_error (_("invalid use of vector register"));
1078 Return the register number on success; return PARSE_FAIL otherwise.
1080 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1081 the register (e.g. NEON double or quad reg when either has been requested).
1083 If this is a NEON vector register with additional type information, fill
1084 in the struct pointed to by VECTYPE (if non-NULL).
1086 This parser does not handle register list. */
1089 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1090 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1092 struct vector_type_el atype
;
1094 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1095 /*in_reg_list= */ false);
1097 if (reg
== PARSE_FAIL
)
1109 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1113 && e1
.defined
== e2
.defined
1114 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1117 /* This function parses a list of vector registers of type TYPE.
1118 On success, it returns the parsed register list information in the
1119 following encoded format:
1121 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1122 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1124 The information of the register shape and/or index is returned in
1127 It returns PARSE_FAIL if the register list is invalid.
1129 The list contains one to four registers.
1130 Each register can be one of:
1133 All <T> should be identical.
1134 All <index> should be identical.
1135 There are restrictions on <Vt> numbers which are checked later
1136 (by reg_list_valid_p). */
1139 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1140 struct vector_type_el
*vectype
)
1144 struct vector_type_el typeinfo
, typeinfo_first
;
1150 bool expect_index
= false;
1154 set_syntax_error (_("expecting {"));
1160 typeinfo_first
.defined
= 0;
1161 typeinfo_first
.type
= NT_invtype
;
1162 typeinfo_first
.width
= -1;
1163 typeinfo_first
.index
= 0;
1172 str
++; /* skip over '-' */
1175 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1176 /*in_reg_list= */ true);
1177 if (val
== PARSE_FAIL
)
1179 set_first_syntax_error (_("invalid vector register in list"));
1183 /* reject [bhsd]n */
1184 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1186 set_first_syntax_error (_("invalid scalar register in list"));
1191 if (typeinfo
.defined
& NTA_HASINDEX
)
1192 expect_index
= true;
1196 if (val
< val_range
)
1198 set_first_syntax_error
1199 (_("invalid range in vector register list"));
1208 typeinfo_first
= typeinfo
;
1209 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1211 set_first_syntax_error
1212 (_("type mismatch in vector register list"));
1217 for (i
= val_range
; i
<= val
; i
++)
1219 ret_val
|= i
<< (5 * nb_regs
);
1224 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1226 skip_whitespace (str
);
1229 set_first_syntax_error (_("end of vector register list not found"));
1234 skip_whitespace (str
);
1238 if (skip_past_char (&str
, '['))
1242 aarch64_get_expression (&exp
, &str
, GE_NO_PREFIX
, REJECT_ABSENT
,
1244 if (exp
.X_op
!= O_constant
)
1246 set_first_syntax_error (_("constant expression required."));
1249 if (! skip_past_char (&str
, ']'))
1252 typeinfo_first
.index
= exp
.X_add_number
;
1256 set_first_syntax_error (_("expected index"));
1263 set_first_syntax_error (_("too many registers in vector register list"));
1266 else if (nb_regs
== 0)
1268 set_first_syntax_error (_("empty vector register list"));
1274 *vectype
= typeinfo_first
;
1276 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1279 /* Directives: register aliases. */
1282 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1287 if ((new = str_hash_find (aarch64_reg_hsh
, str
)) != 0)
1290 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1293 /* Only warn about a redefinition if it's not defined as the
1295 else if (new->number
!= number
|| new->type
!= type
)
1296 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1301 name
= xstrdup (str
);
1302 new = XNEW (reg_entry
);
1305 new->number
= number
;
1307 new->builtin
= false;
1309 str_hash_insert (aarch64_reg_hsh
, name
, new, 0);
1314 /* Look for the .req directive. This is of the form:
1316 new_register_name .req existing_register_name
1318 If we find one, or if it looks sufficiently like one that we want to
1319 handle any error here, return TRUE. Otherwise return FALSE. */
1322 create_register_alias (char *newname
, char *p
)
1324 const reg_entry
*old
;
1325 char *oldname
, *nbuf
;
1328 /* The input scrubber ensures that whitespace after the mnemonic is
1329 collapsed to single spaces. */
1331 if (!startswith (oldname
, " .req "))
1335 if (*oldname
== '\0')
1338 old
= str_hash_find (aarch64_reg_hsh
, oldname
);
1341 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1345 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1346 the desired alias name, and p points to its end. If not, then
1347 the desired alias name is in the global original_case_string. */
1348 #ifdef TC_CASE_SENSITIVE
1351 newname
= original_case_string
;
1352 nlen
= strlen (newname
);
1355 nbuf
= xmemdup0 (newname
, nlen
);
1357 /* Create aliases under the new name as stated; an all-lowercase
1358 version of the new name; and an all-uppercase version of the new
1360 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1362 for (p
= nbuf
; *p
; p
++)
1365 if (strncmp (nbuf
, newname
, nlen
))
1367 /* If this attempt to create an additional alias fails, do not bother
1368 trying to create the all-lower case alias. We will fail and issue
1369 a second, duplicate error message. This situation arises when the
1370 programmer does something like:
1373 The second .req creates the "Foo" alias but then fails to create
1374 the artificial FOO alias because it has already been created by the
1376 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1383 for (p
= nbuf
; *p
; p
++)
1386 if (strncmp (nbuf
, newname
, nlen
))
1387 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1394 /* Should never be called, as .req goes between the alias and the
1395 register name, not at the beginning of the line. */
1397 s_req (int a ATTRIBUTE_UNUSED
)
1399 as_bad (_("invalid syntax for .req directive"));
1402 /* The .unreq directive deletes an alias which was previously defined
1403 by .req. For example:
1409 s_unreq (int a ATTRIBUTE_UNUSED
)
1414 name
= input_line_pointer
;
1416 while (*input_line_pointer
!= 0
1417 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1418 ++input_line_pointer
;
1420 saved_char
= *input_line_pointer
;
1421 *input_line_pointer
= 0;
1424 as_bad (_("invalid syntax for .unreq directive"));
1427 reg_entry
*reg
= str_hash_find (aarch64_reg_hsh
, name
);
1430 as_bad (_("unknown register alias '%s'"), name
);
1431 else if (reg
->builtin
)
1432 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1439 str_hash_delete (aarch64_reg_hsh
, name
);
1440 free ((char *) reg
->name
);
1443 /* Also locate the all upper case and all lower case versions.
1444 Do not complain if we cannot find one or the other as it
1445 was probably deleted above. */
1447 nbuf
= strdup (name
);
1448 for (p
= nbuf
; *p
; p
++)
1450 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1453 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1454 free ((char *) reg
->name
);
1458 for (p
= nbuf
; *p
; p
++)
1460 reg
= str_hash_find (aarch64_reg_hsh
, nbuf
);
1463 str_hash_delete (aarch64_reg_hsh
, nbuf
);
1464 free ((char *) reg
->name
);
1472 *input_line_pointer
= saved_char
;
1473 demand_empty_rest_of_line ();
1476 /* Directives: Instruction set selection. */
1479 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1480 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1481 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1482 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1484 /* Create a new mapping symbol for the transition to STATE. */
1487 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1490 const char *symname
;
1497 type
= BSF_NO_FLAGS
;
1501 type
= BSF_NO_FLAGS
;
1507 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
1508 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1510 /* Save the mapping symbols for future reference. Also check that
1511 we do not place two mapping symbols at the same offset within a
1512 frag. We'll handle overlap between frags in
1513 check_mapping_symbols.
1515 If .fill or other data filling directive generates zero sized data,
1516 the mapping symbol for the following code will have the same value
1517 as the one generated for the data filling directive. In this case,
1518 we replace the old symbol with the new one at the same address. */
1521 if (frag
->tc_frag_data
.first_map
!= NULL
)
1523 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1524 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1527 frag
->tc_frag_data
.first_map
= symbolP
;
1529 if (frag
->tc_frag_data
.last_map
!= NULL
)
1531 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1532 S_GET_VALUE (symbolP
));
1533 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1534 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1537 frag
->tc_frag_data
.last_map
= symbolP
;
1540 /* We must sometimes convert a region marked as code to data during
1541 code alignment, if an odd number of bytes have to be padded. The
1542 code mapping symbol is pushed to an aligned address. */
1545 insert_data_mapping_symbol (enum mstate state
,
1546 valueT value
, fragS
* frag
, offsetT bytes
)
1548 /* If there was already a mapping symbol, remove it. */
1549 if (frag
->tc_frag_data
.last_map
!= NULL
1550 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1551 frag
->fr_address
+ value
)
1553 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1557 know (frag
->tc_frag_data
.first_map
== symp
);
1558 frag
->tc_frag_data
.first_map
= NULL
;
1560 frag
->tc_frag_data
.last_map
= NULL
;
1561 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1564 make_mapping_symbol (MAP_DATA
, value
, frag
);
1565 make_mapping_symbol (state
, value
+ bytes
, frag
);
1568 static void mapping_state_2 (enum mstate state
, int max_chars
);
1570 /* Set the mapping state to STATE. Only call this when about to
1571 emit some STATE bytes to the file. */
1574 mapping_state (enum mstate state
)
1576 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1578 if (state
== MAP_INSN
)
1579 /* AArch64 instructions require 4-byte alignment. When emitting
1580 instructions into any section, record the appropriate section
1582 record_alignment (now_seg
, 2);
1584 if (mapstate
== state
)
1585 /* The mapping symbol has already been emitted.
1586 There is nothing else to do. */
1589 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1590 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1591 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1592 evaluated later in the next else. */
1594 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1596 /* Only add the symbol if the offset is > 0:
1597 if we're at the first frag, check it's size > 0;
1598 if we're not at the first frag, then for sure
1599 the offset is > 0. */
1600 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1601 const int add_symbol
= (frag_now
!= frag_first
)
1602 || (frag_now_fix () > 0);
1605 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1609 mapping_state_2 (state
, 0);
1612 /* Same as mapping_state, but MAX_CHARS bytes have already been
1613 allocated. Put the mapping symbol that far back. */
1616 mapping_state_2 (enum mstate state
, int max_chars
)
1618 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1620 if (!SEG_NORMAL (now_seg
))
1623 if (mapstate
== state
)
1624 /* The mapping symbol has already been emitted.
1625 There is nothing else to do. */
1628 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1629 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1632 #define mapping_state(x) /* nothing */
1633 #define mapping_state_2(x, y) /* nothing */
1636 /* Directives: sectioning and alignment. */
1639 s_bss (int ignore ATTRIBUTE_UNUSED
)
1641 /* We don't support putting frags in the BSS segment, we fake it by
1642 marking in_bss, then looking at s_skip for clues. */
1643 subseg_set (bss_section
, 0);
1644 demand_empty_rest_of_line ();
1645 mapping_state (MAP_DATA
);
1649 s_even (int ignore ATTRIBUTE_UNUSED
)
1651 /* Never make frag if expect extra pass. */
1653 frag_align (1, 0, 0);
1655 record_alignment (now_seg
, 1);
1657 demand_empty_rest_of_line ();
1660 /* Directives: Literal pools. */
1662 static literal_pool
*
1663 find_literal_pool (int size
)
1667 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1669 if (pool
->section
== now_seg
1670 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1677 static literal_pool
*
1678 find_or_make_literal_pool (int size
)
1680 /* Next literal pool ID number. */
1681 static unsigned int latest_pool_num
= 1;
1684 pool
= find_literal_pool (size
);
1688 /* Create a new pool. */
1689 pool
= XNEW (literal_pool
);
1693 /* Currently we always put the literal pool in the current text
1694 section. If we were generating "small" model code where we
1695 knew that all code and initialised data was within 1MB then
1696 we could output literals to mergeable, read-only data
1699 pool
->next_free_entry
= 0;
1700 pool
->section
= now_seg
;
1701 pool
->sub_section
= now_subseg
;
1703 pool
->next
= list_of_pools
;
1704 pool
->symbol
= NULL
;
1706 /* Add it to the list. */
1707 list_of_pools
= pool
;
1710 /* New pools, and emptied pools, will have a NULL symbol. */
1711 if (pool
->symbol
== NULL
)
1713 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1714 &zero_address_frag
, 0);
1715 pool
->id
= latest_pool_num
++;
1722 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1723 Return TRUE on success, otherwise return FALSE. */
1725 add_to_lit_pool (expressionS
*exp
, int size
)
1730 pool
= find_or_make_literal_pool (size
);
1732 /* Check if this literal value is already in the pool. */
1733 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1735 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1737 if ((litexp
->X_op
== exp
->X_op
)
1738 && (exp
->X_op
== O_constant
)
1739 && (litexp
->X_add_number
== exp
->X_add_number
)
1740 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1743 if ((litexp
->X_op
== exp
->X_op
)
1744 && (exp
->X_op
== O_symbol
)
1745 && (litexp
->X_add_number
== exp
->X_add_number
)
1746 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1747 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1751 /* Do we need to create a new entry? */
1752 if (entry
== pool
->next_free_entry
)
1754 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1756 set_syntax_error (_("literal pool overflow"));
1760 pool
->literals
[entry
].exp
= *exp
;
1761 pool
->next_free_entry
+= 1;
1762 if (exp
->X_op
== O_big
)
1764 /* PR 16688: Bignums are held in a single global array. We must
1765 copy and preserve that value now, before it is overwritten. */
1766 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1768 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1769 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1772 pool
->literals
[entry
].bignum
= NULL
;
1775 exp
->X_op
= O_symbol
;
1776 exp
->X_add_number
= ((int) entry
) * size
;
1777 exp
->X_add_symbol
= pool
->symbol
;
1782 /* Can't use symbol_new here, so have to create a symbol and then at
1783 a later date assign it a value. That's what these functions do. */
1786 symbol_locate (symbolS
* symbolP
,
1787 const char *name
,/* It is copied, the caller can modify. */
1788 segT segment
, /* Segment identifier (SEG_<something>). */
1789 valueT valu
, /* Symbol value. */
1790 fragS
* frag
) /* Associated fragment. */
1793 char *preserved_copy_of_name
;
1795 name_length
= strlen (name
) + 1; /* +1 for \0. */
1796 obstack_grow (¬es
, name
, name_length
);
1797 preserved_copy_of_name
= obstack_finish (¬es
);
1799 #ifdef tc_canonicalize_symbol_name
1800 preserved_copy_of_name
=
1801 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1804 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1806 S_SET_SEGMENT (symbolP
, segment
);
1807 S_SET_VALUE (symbolP
, valu
);
1808 symbol_clear_list_pointers (symbolP
);
1810 symbol_set_frag (symbolP
, frag
);
1812 /* Link to end of symbol chain. */
1814 extern int symbol_table_frozen
;
1816 if (symbol_table_frozen
)
1820 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1822 obj_symbol_new_hook (symbolP
);
1824 #ifdef tc_symbol_new_hook
1825 tc_symbol_new_hook (symbolP
);
1829 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1830 #endif /* DEBUG_SYMS */
1835 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1842 for (align
= 2; align
<= 4; align
++)
1844 int size
= 1 << align
;
1846 pool
= find_literal_pool (size
);
1847 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1850 /* Align pool as you have word accesses.
1851 Only make a frag if we have to. */
1853 frag_align (align
, 0, 0);
1855 mapping_state (MAP_DATA
);
1857 record_alignment (now_seg
, align
);
1859 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1861 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1862 (valueT
) frag_now_fix (), frag_now
);
1863 symbol_table_insert (pool
->symbol
);
1865 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1867 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1869 if (exp
->X_op
== O_big
)
1871 /* PR 16688: Restore the global bignum value. */
1872 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1873 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1874 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1877 /* First output the expression in the instruction to the pool. */
1878 emit_expr (exp
, size
); /* .word|.xword */
1880 if (exp
->X_op
== O_big
)
1882 free (pool
->literals
[entry
].bignum
);
1883 pool
->literals
[entry
].bignum
= NULL
;
1887 /* Mark the pool as empty. */
1888 pool
->next_free_entry
= 0;
1889 pool
->symbol
= NULL
;
1894 /* Forward declarations for functions below, in the MD interface
1896 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1897 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1899 /* Directives: Data. */
1900 /* N.B. the support for relocation suffix in this directive needs to be
1901 implemented properly. */
1904 s_aarch64_elf_cons (int nbytes
)
1908 #ifdef md_flush_pending_output
1909 md_flush_pending_output ();
1912 if (is_it_end_of_statement ())
1914 demand_empty_rest_of_line ();
1918 #ifdef md_cons_align
1919 md_cons_align (nbytes
);
1922 mapping_state (MAP_DATA
);
1925 struct reloc_table_entry
*reloc
;
1929 if (exp
.X_op
!= O_symbol
)
1930 emit_expr (&exp
, (unsigned int) nbytes
);
1933 skip_past_char (&input_line_pointer
, '#');
1934 if (skip_past_char (&input_line_pointer
, ':'))
1936 reloc
= find_reloc_table_entry (&input_line_pointer
);
1938 as_bad (_("unrecognized relocation suffix"));
1940 as_bad (_("unimplemented relocation suffix"));
1941 ignore_rest_of_line ();
1945 emit_expr (&exp
, (unsigned int) nbytes
);
1948 while (*input_line_pointer
++ == ',');
1950 /* Put terminator back into stream. */
1951 input_line_pointer
--;
1952 demand_empty_rest_of_line ();
1955 /* Mark symbol that it follows a variant PCS convention. */
1958 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1964 elf_symbol_type
*elfsym
;
1966 c
= get_symbol_name (&name
);
1968 as_bad (_("Missing symbol name in directive"));
1969 sym
= symbol_find_or_make (name
);
1970 restore_line_pointer (c
);
1971 demand_empty_rest_of_line ();
1972 bfdsym
= symbol_get_bfdsym (sym
);
1973 elfsym
= elf_symbol_from (bfdsym
);
1974 gas_assert (elfsym
);
1975 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
1977 #endif /* OBJ_ELF */
1979 /* Output a 32-bit word, but mark as an instruction. */
1982 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1986 #ifdef md_flush_pending_output
1987 md_flush_pending_output ();
1990 if (is_it_end_of_statement ())
1992 demand_empty_rest_of_line ();
1996 /* Sections are assumed to start aligned. In executable section, there is no
1997 MAP_DATA symbol pending. So we only align the address during
1998 MAP_DATA --> MAP_INSN transition.
1999 For other sections, this is not guaranteed. */
2000 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2001 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
2002 frag_align_code (2, 0);
2005 mapping_state (MAP_INSN
);
2011 if (exp
.X_op
!= O_constant
)
2013 as_bad (_("constant expression required"));
2014 ignore_rest_of_line ();
2018 if (target_big_endian
)
2020 unsigned int val
= exp
.X_add_number
;
2021 exp
.X_add_number
= SWAP_32 (val
);
2023 emit_expr (&exp
, 4);
2025 while (*input_line_pointer
++ == ',');
2027 /* Put terminator back into stream. */
2028 input_line_pointer
--;
2029 demand_empty_rest_of_line ();
2033 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2035 demand_empty_rest_of_line ();
2036 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2037 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2041 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2044 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2050 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2051 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2053 demand_empty_rest_of_line ();
2056 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2059 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2063 /* Since we're just labelling the code, there's no need to define a
2066 /* Make sure there is enough room in this frag for the following
2067 blr. This trick only works if the blr follows immediately after
2068 the .tlsdesc directive. */
2070 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2071 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2073 demand_empty_rest_of_line ();
2076 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2079 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2085 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2086 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2088 demand_empty_rest_of_line ();
2090 #endif /* OBJ_ELF */
2092 static void s_aarch64_arch (int);
2093 static void s_aarch64_cpu (int);
2094 static void s_aarch64_arch_extension (int);
2096 /* This table describes all the machine specific pseudo-ops the assembler
2097 has to support. The fields are:
2098 pseudo-op name without dot
2099 function to call to execute this pseudo-op
2100 Integer arg to pass to the function. */
2102 const pseudo_typeS md_pseudo_table
[] = {
2103 /* Never called because '.req' does not start a line. */
2105 {"unreq", s_unreq
, 0},
2107 {"even", s_even
, 0},
2108 {"ltorg", s_ltorg
, 0},
2109 {"pool", s_ltorg
, 0},
2110 {"cpu", s_aarch64_cpu
, 0},
2111 {"arch", s_aarch64_arch
, 0},
2112 {"arch_extension", s_aarch64_arch_extension
, 0},
2113 {"inst", s_aarch64_inst
, 0},
2114 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2116 {"tlsdescadd", s_tlsdescadd
, 0},
2117 {"tlsdesccall", s_tlsdesccall
, 0},
2118 {"tlsdescldr", s_tlsdescldr
, 0},
2119 {"word", s_aarch64_elf_cons
, 4},
2120 {"long", s_aarch64_elf_cons
, 4},
2121 {"xword", s_aarch64_elf_cons
, 8},
2122 {"dword", s_aarch64_elf_cons
, 8},
2123 {"variant_pcs", s_variant_pcs
, 0},
2125 {"float16", float_cons
, 'h'},
2126 {"bfloat16", float_cons
, 'b'},
2131 /* Check whether STR points to a register name followed by a comma or the
2132 end of line; REG_TYPE indicates which register types are checked
2133 against. Return TRUE if STR is such a register name; otherwise return
2134 FALSE. The function does not intend to produce any diagnostics, but since
2135 the register parser aarch64_reg_parse, which is called by this function,
2136 does produce diagnostics, we call clear_error to clear any diagnostics
2137 that may be generated by aarch64_reg_parse.
2138 Also, the function returns FALSE directly if there is any user error
2139 present at the function entry. This prevents the existing diagnostics
2140 state from being spoiled.
2141 The function currently serves parse_constant_immediate and
2142 parse_big_immediate only. */
2144 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2148 /* Prevent the diagnostics state from being spoiled. */
2152 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2154 /* Clear the parsing error that may be set by the reg parser. */
2157 if (reg
== PARSE_FAIL
)
2160 skip_whitespace (str
);
2161 if (*str
== ',' || is_end_of_line
[(unsigned char) *str
])
2167 /* Parser functions used exclusively in instruction operands. */
2169 /* Parse an immediate expression which may not be constant.
2171 To prevent the expression parser from pushing a register name
2172 into the symbol table as an undefined symbol, firstly a check is
2173 done to find out whether STR is a register of type REG_TYPE followed
2174 by a comma or the end of line. Return FALSE if STR is such a string. */
2177 parse_immediate_expression (char **str
, expressionS
*exp
,
2178 aarch64_reg_type reg_type
)
2180 if (reg_name_p (*str
, reg_type
))
2182 set_recoverable_error (_("immediate operand required"));
2186 aarch64_get_expression (exp
, str
, GE_OPT_PREFIX
, REJECT_ABSENT
,
2189 if (exp
->X_op
== O_absent
)
2191 set_fatal_syntax_error (_("missing immediate expression"));
2198 /* Constant immediate-value read function for use in insn parsing.
2199 STR points to the beginning of the immediate (with the optional
2200 leading #); *VAL receives the value. REG_TYPE says which register
2201 names should be treated as registers rather than as symbolic immediates.
2203 Return TRUE on success; otherwise return FALSE. */
2206 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2210 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2213 if (exp
.X_op
!= O_constant
)
2215 set_syntax_error (_("constant expression required"));
2219 *val
= exp
.X_add_number
;
2224 encode_imm_float_bits (uint32_t imm
)
2226 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2227 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2230 /* Return TRUE if the single-precision floating-point value encoded in IMM
2231 can be expressed in the AArch64 8-bit signed floating-point format with
2232 3-bit exponent and normalized 4 bits of precision; in other words, the
2233 floating-point value must be expressable as
2234 (+/-) n / 16 * power (2, r)
2235 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2238 aarch64_imm_float_p (uint32_t imm
)
2240 /* If a single-precision floating-point value has the following bit
2241 pattern, it can be expressed in the AArch64 8-bit floating-point
2244 3 32222222 2221111111111
2245 1 09876543 21098765432109876543210
2246 n Eeeeeexx xxxx0000000000000000000
2248 where n, e and each x are either 0 or 1 independently, with
2253 /* Prepare the pattern for 'Eeeeee'. */
2254 if (((imm
>> 30) & 0x1) == 0)
2255 pattern
= 0x3e000000;
2257 pattern
= 0x40000000;
2259 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2260 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2263 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2264 as an IEEE float without any loss of precision. Store the value in
2268 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2270 /* If a double-precision floating-point value has the following bit
2271 pattern, it can be expressed in a float:
2273 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2274 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2275 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2277 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2278 if Eeee_eeee != 1111_1111
2280 where n, e, s and S are either 0 or 1 independently and where ~ is the
2284 uint32_t high32
= imm
>> 32;
2285 uint32_t low32
= imm
;
2287 /* Lower 29 bits need to be 0s. */
2288 if ((imm
& 0x1fffffff) != 0)
2291 /* Prepare the pattern for 'Eeeeeeeee'. */
2292 if (((high32
>> 30) & 0x1) == 0)
2293 pattern
= 0x38000000;
2295 pattern
= 0x40000000;
2298 if ((high32
& 0x78000000) != pattern
)
2301 /* Check Eeee_eeee != 1111_1111. */
2302 if ((high32
& 0x7ff00000) == 0x47f00000)
2305 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2306 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2307 | (low32
>> 29)); /* 3 S bits. */
2311 /* Return true if we should treat OPERAND as a double-precision
2312 floating-point operand rather than a single-precision one. */
2314 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2316 /* Check for unsuffixed SVE registers, which are allowed
2317 for LDR and STR but not in instructions that require an
2318 immediate. We get better error messages if we arbitrarily
2319 pick one size, parse the immediate normally, and then
2320 report the match failure in the normal way. */
2321 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2322 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2325 /* Parse a floating-point immediate. Return TRUE on success and return the
2326 value in *IMMED in the format of IEEE754 single-precision encoding.
2327 *CCP points to the start of the string; DP_P is TRUE when the immediate
2328 is expected to be in double-precision (N.B. this only matters when
2329 hexadecimal representation is involved). REG_TYPE says which register
2330 names should be treated as registers rather than as symbolic immediates.
2332 This routine accepts any IEEE float; it is up to the callers to reject
2336 parse_aarch64_imm_float (char **ccp
, int *immed
, bool dp_p
,
2337 aarch64_reg_type reg_type
)
2341 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2343 unsigned fpword
= 0;
2346 skip_past_char (&str
, '#');
2349 skip_whitespace (fpnum
);
2351 if (startswith (fpnum
, "0x"))
2353 /* Support the hexadecimal representation of the IEEE754 encoding.
2354 Double-precision is expected when DP_P is TRUE, otherwise the
2355 representation should be in single-precision. */
2356 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2361 if (!can_convert_double_to_float (val
, &fpword
))
2364 else if ((uint64_t) val
> 0xffffffff)
2371 else if (reg_name_p (str
, reg_type
))
2373 set_recoverable_error (_("immediate operand required"));
2381 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2384 /* Our FP word must be 32 bits (single-precision FP). */
2385 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2387 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2397 set_fatal_syntax_error (_("invalid floating-point constant"));
2401 /* Less-generic immediate-value read function with the possibility of loading
2402 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2405 To prevent the expression parser from pushing a register name into the
2406 symbol table as an undefined symbol, a check is firstly done to find
2407 out whether STR is a register of type REG_TYPE followed by a comma or
2408 the end of line. Return FALSE if STR is such a register. */
2411 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2415 if (reg_name_p (ptr
, reg_type
))
2417 set_syntax_error (_("immediate operand required"));
2421 aarch64_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, REJECT_ABSENT
,
2424 if (inst
.reloc
.exp
.X_op
== O_constant
)
2425 *imm
= inst
.reloc
.exp
.X_add_number
;
2432 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2433 if NEED_LIBOPCODES is non-zero, the fixup will need
2434 assistance from the libopcodes. */
2437 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2438 const aarch64_opnd_info
*operand
,
2439 int need_libopcodes_p
)
2441 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2442 reloc
->opnd
= operand
->type
;
2443 if (need_libopcodes_p
)
2444 reloc
->need_libopcodes_p
= 1;
2447 /* Return TRUE if the instruction needs to be fixed up later internally by
2448 the GAS; otherwise return FALSE. */
2451 aarch64_gas_internal_fixup_p (void)
2453 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2456 /* Assign the immediate value to the relevant field in *OPERAND if
2457 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2458 needs an internal fixup in a later stage.
2459 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2460 IMM.VALUE that may get assigned with the constant. */
2462 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2463 aarch64_opnd_info
*operand
,
2465 int need_libopcodes_p
,
2468 if (reloc
->exp
.X_op
== O_constant
)
2471 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2473 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2474 reloc
->type
= BFD_RELOC_UNUSED
;
2478 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2479 /* Tell libopcodes to ignore this operand or not. This is helpful
2480 when one of the operands needs to be fixed up later but we need
2481 libopcodes to check the other operands. */
2482 operand
->skip
= skip_p
;
2486 /* Relocation modifiers. Each entry in the table contains the textual
2487 name for the relocation which may be placed before a symbol used as
2488 a load/store offset, or add immediate. It must be surrounded by a
2489 leading and trailing colon, for example:
2491 ldr x0, [x1, #:rello:varsym]
2492 add x0, x1, #:rello:varsym */
2494 struct reloc_table_entry
2498 bfd_reloc_code_real_type adr_type
;
2499 bfd_reloc_code_real_type adrp_type
;
2500 bfd_reloc_code_real_type movw_type
;
2501 bfd_reloc_code_real_type add_type
;
2502 bfd_reloc_code_real_type ldst_type
;
2503 bfd_reloc_code_real_type ld_literal_type
;
2506 static struct reloc_table_entry reloc_table
[] =
2508 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2513 BFD_RELOC_AARCH64_ADD_LO12
,
2514 BFD_RELOC_AARCH64_LDST_LO12
,
2517 /* Higher 21 bits of pc-relative page offset: ADRP */
2520 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2526 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2529 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2535 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2539 BFD_RELOC_AARCH64_MOVW_G0
,
2544 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2548 BFD_RELOC_AARCH64_MOVW_G0_S
,
2553 /* Less significant bits 0-15 of address/value: MOVK, no check */
2557 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2562 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2566 BFD_RELOC_AARCH64_MOVW_G1
,
2571 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2575 BFD_RELOC_AARCH64_MOVW_G1_S
,
2580 /* Less significant bits 16-31 of address/value: MOVK, no check */
2584 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2589 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2593 BFD_RELOC_AARCH64_MOVW_G2
,
2598 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2602 BFD_RELOC_AARCH64_MOVW_G2_S
,
2607 /* Less significant bits 32-47 of address/value: MOVK, no check */
2611 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2616 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2620 BFD_RELOC_AARCH64_MOVW_G3
,
2625 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2629 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2634 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2638 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2643 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2647 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2652 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2656 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2661 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2665 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2670 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2674 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2679 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2683 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2688 /* Get to the page containing GOT entry for a symbol. */
2691 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2695 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2697 /* 12 bit offset into the page containing GOT entry for that symbol. */
2703 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2706 /* 0-15 bits of address/value: MOVk, no check. */
2710 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2715 /* Most significant bits 16-31 of address/value: MOVZ. */
2719 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2724 /* 15 bit offset into the page containing GOT entry for that symbol. */
2730 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2733 /* Get to the page containing GOT TLS entry for a symbol */
2734 {"gottprel_g0_nc", 0,
2737 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2742 /* Get to the page containing GOT TLS entry for a symbol */
2746 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2751 /* Get to the page containing GOT TLS entry for a symbol */
2753 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2754 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2760 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2765 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2769 /* Lower 16 bits address/value: MOVk. */
2773 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2778 /* Most significant bits 16-31 of address/value: MOVZ. */
2782 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2787 /* Get to the page containing GOT TLS entry for a symbol */
2789 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2790 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2794 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2796 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2801 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2802 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2805 /* Get to the page containing GOT TLS entry for a symbol.
2806 The same as GD, we allocate two consecutive GOT slots
2807 for module index and module offset, the only difference
2808 with GD is the module offset should be initialized to
2809 zero without any outstanding runtime relocation. */
2811 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2812 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2818 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2819 {"tlsldm_lo12_nc", 0,
2823 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2827 /* 12 bit offset into the module TLS base address. */
2832 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2833 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2836 /* Same as dtprel_lo12, no overflow check. */
2837 {"dtprel_lo12_nc", 0,
2841 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2842 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2845 /* bits[23:12] of offset to the module TLS base address. */
2850 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2854 /* bits[15:0] of offset to the module TLS base address. */
2858 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2863 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2867 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2872 /* bits[31:16] of offset to the module TLS base address. */
2876 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2881 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2885 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2890 /* bits[47:32] of offset to the module TLS base address. */
2894 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2899 /* Lower 16 bit offset into GOT entry for a symbol */
2900 {"tlsdesc_off_g0_nc", 0,
2903 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2908 /* Higher 16 bit offset into GOT entry for a symbol */
2909 {"tlsdesc_off_g1", 0,
2912 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2917 /* Get to the page containing GOT TLS entry for a symbol */
2920 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2924 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2926 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2927 {"gottprel_lo12", 0,
2932 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2935 /* Get tp offset for a symbol. */
2940 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2944 /* Get tp offset for a symbol. */
2949 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2950 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2953 /* Get tp offset for a symbol. */
2958 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2962 /* Get tp offset for a symbol. */
2963 {"tprel_lo12_nc", 0,
2967 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2968 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2971 /* Most significant bits 32-47 of address/value: MOVZ. */
2975 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2980 /* Most significant bits 16-31 of address/value: MOVZ. */
2984 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2989 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2993 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2998 /* Most significant bits 0-15 of address/value: MOVZ. */
3002 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
3007 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
3011 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
3016 /* 15bit offset from got entry to base address of GOT table. */
3022 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3025 /* 14bit offset from got entry to base address of GOT table. */
3031 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3035 /* Given the address of a pointer pointing to the textual name of a
3036 relocation as may appear in assembler source, attempt to find its
3037 details in reloc_table. The pointer will be updated to the character
3038 after the trailing colon. On failure, NULL will be returned;
3039 otherwise return the reloc_table_entry. */
3041 static struct reloc_table_entry
*
3042 find_reloc_table_entry (char **str
)
3045 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3047 int length
= strlen (reloc_table
[i
].name
);
3049 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3050 && (*str
)[length
] == ':')
3052 *str
+= (length
+ 1);
3053 return &reloc_table
[i
];
3060 /* Returns 0 if the relocation should never be forced,
3061 1 if the relocation must be forced, and -1 if either
3065 aarch64_force_reloc (unsigned int type
)
3069 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
3070 /* Perform these "immediate" internal relocations
3071 even if the symbol is extern or weak. */
3074 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
3075 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
3076 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
3077 /* Pseudo relocs that need to be fixed up according to
3081 case BFD_RELOC_AARCH64_ADD_LO12
:
3082 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
3083 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
3084 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
3085 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
3086 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
3087 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
3088 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
3089 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
3090 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
3091 case BFD_RELOC_AARCH64_LDST128_LO12
:
3092 case BFD_RELOC_AARCH64_LDST16_LO12
:
3093 case BFD_RELOC_AARCH64_LDST32_LO12
:
3094 case BFD_RELOC_AARCH64_LDST64_LO12
:
3095 case BFD_RELOC_AARCH64_LDST8_LO12
:
3096 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
3097 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
3098 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
3099 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
3100 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
3101 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
3102 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
3103 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
3104 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
3105 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
3106 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
3107 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
3108 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
3109 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
3110 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
3111 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
3112 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
3113 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
3114 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
3115 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
3116 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
3117 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
3118 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
3119 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
3120 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
3121 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
3122 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
3123 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
3124 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
3125 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
3126 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
3127 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
3128 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
3129 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
3130 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
3131 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
3132 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
3133 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
3134 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
3135 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
3136 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
3137 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
3138 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
3139 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
3140 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
3141 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
3142 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
3143 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
3144 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
3145 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
3146 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
3147 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
3148 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
3149 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
3150 /* Always leave these relocations for the linker. */
3159 aarch64_force_relocation (struct fix
*fixp
)
3161 int res
= aarch64_force_reloc (fixp
->fx_r_type
);
3164 return generic_force_reloc (fixp
);
3168 /* Mode argument to parse_shift and parser_shifter_operand. */
3169 enum parse_shift_mode
3171 SHIFTED_NONE
, /* no shifter allowed */
3172 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3174 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3176 SHIFTED_LSL
, /* bare "lsl #n" */
3177 SHIFTED_MUL
, /* bare "mul #n" */
3178 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3179 SHIFTED_MUL_VL
, /* "mul vl" */
3180 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3183 /* Parse a <shift> operator on an AArch64 data processing instruction.
3184 Return TRUE on success; otherwise return FALSE. */
3186 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3188 const struct aarch64_name_value_pair
*shift_op
;
3189 enum aarch64_modifier_kind kind
;
3195 for (p
= *str
; ISALPHA (*p
); p
++)
3200 set_syntax_error (_("shift expression expected"));
3204 shift_op
= str_hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3206 if (shift_op
== NULL
)
3208 set_syntax_error (_("shift operator expected"));
3212 kind
= aarch64_get_operand_modifier (shift_op
);
3214 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3216 set_syntax_error (_("invalid use of 'MSL'"));
3220 if (kind
== AARCH64_MOD_MUL
3221 && mode
!= SHIFTED_MUL
3222 && mode
!= SHIFTED_MUL_VL
)
3224 set_syntax_error (_("invalid use of 'MUL'"));
3230 case SHIFTED_LOGIC_IMM
:
3231 if (aarch64_extend_operator_p (kind
))
3233 set_syntax_error (_("extending shift is not permitted"));
3238 case SHIFTED_ARITH_IMM
:
3239 if (kind
== AARCH64_MOD_ROR
)
3241 set_syntax_error (_("'ROR' shift is not permitted"));
3247 if (kind
!= AARCH64_MOD_LSL
)
3249 set_syntax_error (_("only 'LSL' shift is permitted"));
3255 if (kind
!= AARCH64_MOD_MUL
)
3257 set_syntax_error (_("only 'MUL' is permitted"));
3262 case SHIFTED_MUL_VL
:
3263 /* "MUL VL" consists of two separate tokens. Require the first
3264 token to be "MUL" and look for a following "VL". */
3265 if (kind
== AARCH64_MOD_MUL
)
3267 skip_whitespace (p
);
3268 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3271 kind
= AARCH64_MOD_MUL_VL
;
3275 set_syntax_error (_("only 'MUL VL' is permitted"));
3278 case SHIFTED_REG_OFFSET
:
3279 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3280 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3282 set_fatal_syntax_error
3283 (_("invalid shift for the register offset addressing mode"));
3288 case SHIFTED_LSL_MSL
:
3289 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3291 set_syntax_error (_("invalid shift operator"));
3300 /* Whitespace can appear here if the next thing is a bare digit. */
3301 skip_whitespace (p
);
3303 /* Parse shift amount. */
3305 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3306 exp
.X_op
= O_absent
;
3309 if (is_immediate_prefix (*p
))
3314 (void) aarch64_get_expression (&exp
, &p
, GE_NO_PREFIX
, ALLOW_ABSENT
,
3317 if (kind
== AARCH64_MOD_MUL_VL
)
3318 /* For consistency, give MUL VL the same shift amount as an implicit
3320 operand
->shifter
.amount
= 1;
3321 else if (exp
.X_op
== O_absent
)
3323 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3325 set_syntax_error (_("missing shift amount"));
3328 operand
->shifter
.amount
= 0;
3330 else if (exp
.X_op
!= O_constant
)
3332 set_syntax_error (_("constant shift amount required"));
3335 /* For parsing purposes, MUL #n has no inherent range. The range
3336 depends on the operand and will be checked by operand-specific
3338 else if (kind
!= AARCH64_MOD_MUL
3339 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3341 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3346 operand
->shifter
.amount
= exp
.X_add_number
;
3347 operand
->shifter
.amount_present
= 1;
3350 operand
->shifter
.operator_present
= 1;
3351 operand
->shifter
.kind
= kind
;
3357 /* Parse a <shifter_operand> for a data processing instruction:
3360 #<immediate>, LSL #imm
3362 Validation of immediate operands is deferred to md_apply_fix.
3364 Return TRUE on success; otherwise return FALSE. */
3367 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3368 enum parse_shift_mode mode
)
3372 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3377 /* Accept an immediate expression. */
3378 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
,
3379 REJECT_ABSENT
, NORMAL_RESOLUTION
))
3382 /* Accept optional LSL for arithmetic immediate values. */
3383 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3384 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3387 /* Not accept any shifter for logical immediate values. */
3388 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3389 && parse_shift (&p
, operand
, mode
))
3391 set_syntax_error (_("unexpected shift operator"));
3399 /* Parse a <shifter_operand> for a data processing instruction:
3404 #<immediate>, LSL #imm
3406 where <shift> is handled by parse_shift above, and the last two
3407 cases are handled by the function above.
3409 Validation of immediate operands is deferred to md_apply_fix.
3411 Return TRUE on success; otherwise return FALSE. */
3414 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3415 enum parse_shift_mode mode
)
3417 const reg_entry
*reg
;
3418 aarch64_opnd_qualifier_t qualifier
;
3419 enum aarch64_operand_class opd_class
3420 = aarch64_get_operand_class (operand
->type
);
3422 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3425 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3427 set_syntax_error (_("unexpected register in the immediate operand"));
3431 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3433 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3437 operand
->reg
.regno
= reg
->number
;
3438 operand
->qualifier
= qualifier
;
3440 /* Accept optional shift operation on register. */
3441 if (! skip_past_comma (str
))
3444 if (! parse_shift (str
, operand
, mode
))
3449 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3452 (_("integer register expected in the extended/shifted operand "
3457 /* We have a shifted immediate variable. */
3458 return parse_shifter_operand_imm (str
, operand
, mode
);
3461 /* Return TRUE on success; return FALSE otherwise. */
3464 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3465 enum parse_shift_mode mode
)
3469 /* Determine if we have the sequence of characters #: or just :
3470 coming next. If we do, then we check for a :rello: relocation
3471 modifier. If we don't, punt the whole lot to
3472 parse_shifter_operand. */
3474 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3476 struct reloc_table_entry
*entry
;
3484 /* Try to parse a relocation. Anything else is an error. */
3485 if (!(entry
= find_reloc_table_entry (str
)))
3487 set_syntax_error (_("unknown relocation modifier"));
3491 if (entry
->add_type
== 0)
3494 (_("this relocation modifier is not allowed on this instruction"));
3498 /* Save str before we decompose it. */
3501 /* Next, we parse the expression. */
3502 if (! aarch64_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
,
3504 aarch64_force_reloc (entry
->add_type
) == 1))
3507 /* Record the relocation type (use the ADD variant here). */
3508 inst
.reloc
.type
= entry
->add_type
;
3509 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3511 /* If str is empty, we've reached the end, stop here. */
3515 /* Otherwise, we have a shifted reloc modifier, so rewind to
3516 recover the variable name and continue parsing for the shifter. */
3518 return parse_shifter_operand_imm (str
, operand
, mode
);
3521 return parse_shifter_operand (str
, operand
, mode
);
3524 /* Parse all forms of an address expression. Information is written
3525 to *OPERAND and/or inst.reloc.
3527 The A64 instruction set has the following addressing modes:
3530 [base] // in SIMD ld/st structure
3531 [base{,#0}] // in ld/st exclusive
3533 [base,Xm{,LSL #imm}]
3534 [base,Xm,SXTX {#imm}]
3535 [base,Wm,(S|U)XTW {#imm}]
3537 [base]! // in ldraa/ldrab exclusive
3541 [base],Xm // in SIMD ld/st structure
3542 PC-relative (literal)
3546 [base,Zm.D{,LSL #imm}]
3547 [base,Zm.S,(S|U)XTW {#imm}]
3548 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3552 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3553 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3554 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3556 (As a convenience, the notation "=immediate" is permitted in conjunction
3557 with the pc-relative literal load instructions to automatically place an
3558 immediate value or symbolic address in a nearby literal pool and generate
3559 a hidden label which references it.)
3561 Upon a successful parsing, the address structure in *OPERAND will be
3562 filled in the following way:
3564 .base_regno = <base>
3565 .offset.is_reg // 1 if the offset is a register
3567 .offset.regno = <Rm>
3569 For different addressing modes defined in the A64 ISA:
3572 .pcrel=0; .preind=1; .postind=0; .writeback=0
3574 .pcrel=0; .preind=1; .postind=0; .writeback=1
3576 .pcrel=0; .preind=0; .postind=1; .writeback=1
3577 PC-relative (literal)
3578 .pcrel=1; .preind=1; .postind=0; .writeback=0
3580 The shift/extension information, if any, will be stored in .shifter.
3581 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3582 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3583 corresponding register.
3585 BASE_TYPE says which types of base register should be accepted and
3586 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3587 is the type of shifter that is allowed for immediate offsets,
3588 or SHIFTED_NONE if none.
3590 In all other respects, it is the caller's responsibility to check
3591 for addressing modes not supported by the instruction, and to set
3595 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3596 aarch64_opnd_qualifier_t
*base_qualifier
,
3597 aarch64_opnd_qualifier_t
*offset_qualifier
,
3598 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3599 enum parse_shift_mode imm_shift_mode
)
3602 const reg_entry
*reg
;
3603 expressionS
*exp
= &inst
.reloc
.exp
;
3605 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3606 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3607 if (! skip_past_char (&p
, '['))
3609 /* =immediate or label. */
3610 operand
->addr
.pcrel
= 1;
3611 operand
->addr
.preind
= 1;
3613 /* #:<reloc_op>:<symbol> */
3614 skip_past_char (&p
, '#');
3615 if (skip_past_char (&p
, ':'))
3617 bfd_reloc_code_real_type ty
;
3618 struct reloc_table_entry
*entry
;
3620 /* Try to parse a relocation modifier. Anything else is
3622 entry
= find_reloc_table_entry (&p
);
3625 set_syntax_error (_("unknown relocation modifier"));
3629 switch (operand
->type
)
3631 case AARCH64_OPND_ADDR_PCREL21
:
3633 ty
= entry
->adr_type
;
3637 ty
= entry
->ld_literal_type
;
3644 (_("this relocation modifier is not allowed on this "
3650 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3651 aarch64_force_reloc (entry
->add_type
) == 1))
3653 set_syntax_error (_("invalid relocation expression"));
3656 /* #:<reloc_op>:<expr> */
3657 /* Record the relocation type. */
3658 inst
.reloc
.type
= ty
;
3659 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3663 if (skip_past_char (&p
, '='))
3664 /* =immediate; need to generate the literal in the literal pool. */
3665 inst
.gen_lit_pool
= 1;
3667 if (!aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3670 set_syntax_error (_("invalid address"));
3681 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3682 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3684 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3687 operand
->addr
.base_regno
= reg
->number
;
3690 if (skip_past_comma (&p
))
3693 operand
->addr
.preind
= 1;
3695 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3698 if (!aarch64_check_reg_type (reg
, offset_type
))
3700 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3705 operand
->addr
.offset
.regno
= reg
->number
;
3706 operand
->addr
.offset
.is_reg
= 1;
3707 /* Shifted index. */
3708 if (skip_past_comma (&p
))
3711 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3712 /* Use the diagnostics set in parse_shift, so not set new
3713 error message here. */
3717 [base,Xm] # For vector plus scalar SVE2 indexing.
3718 [base,Xm{,LSL #imm}]
3719 [base,Xm,SXTX {#imm}]
3720 [base,Wm,(S|U)XTW {#imm}] */
3721 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3722 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3723 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3725 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3727 set_syntax_error (_("invalid use of 32-bit register offset"));
3730 if (aarch64_get_qualifier_esize (*base_qualifier
)
3731 != aarch64_get_qualifier_esize (*offset_qualifier
)
3732 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3733 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3734 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3736 set_syntax_error (_("offset has different size from base"));
3740 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3742 set_syntax_error (_("invalid use of 64-bit register offset"));
3748 /* [Xn,#:<reloc_op>:<symbol> */
3749 skip_past_char (&p
, '#');
3750 if (skip_past_char (&p
, ':'))
3752 struct reloc_table_entry
*entry
;
3754 /* Try to parse a relocation modifier. Anything else is
3756 if (!(entry
= find_reloc_table_entry (&p
)))
3758 set_syntax_error (_("unknown relocation modifier"));
3762 if (entry
->ldst_type
== 0)
3765 (_("this relocation modifier is not allowed on this "
3770 /* [Xn,#:<reloc_op>: */
3771 /* We now have the group relocation table entry corresponding to
3772 the name in the assembler source. Next, we parse the
3774 if (! aarch64_get_expression (exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3775 aarch64_force_reloc (entry
->add_type
) == 1))
3777 set_syntax_error (_("invalid relocation expression"));
3781 /* [Xn,#:<reloc_op>:<expr> */
3782 /* Record the load/store relocation type. */
3783 inst
.reloc
.type
= entry
->ldst_type
;
3784 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3788 if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
,
3791 set_syntax_error (_("invalid expression in the address"));
3795 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3796 /* [Xn,<expr>,<shifter> */
3797 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3803 if (! skip_past_char (&p
, ']'))
3805 set_syntax_error (_("']' expected"));
3809 if (skip_past_char (&p
, '!'))
3811 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3813 set_syntax_error (_("register offset not allowed in pre-indexed "
3814 "addressing mode"));
3818 operand
->addr
.writeback
= 1;
3820 else if (skip_past_comma (&p
))
3823 operand
->addr
.postind
= 1;
3824 operand
->addr
.writeback
= 1;
3826 if (operand
->addr
.preind
)
3828 set_syntax_error (_("cannot combine pre- and post-indexing"));
3832 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3836 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3838 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3842 operand
->addr
.offset
.regno
= reg
->number
;
3843 operand
->addr
.offset
.is_reg
= 1;
3845 else if (! aarch64_get_expression (exp
, &p
, GE_OPT_PREFIX
, REJECT_ABSENT
,
3849 set_syntax_error (_("invalid expression in the address"));
3854 /* If at this point neither .preind nor .postind is set, we have a
3855 bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
3856 ldrab, accept [Rn] as a shorthand for [Rn,#0].
3857 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3859 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3861 if (operand
->addr
.writeback
)
3863 if (operand
->type
== AARCH64_OPND_ADDR_SIMM10
)
3865 /* Accept [Rn]! as a shorthand for [Rn,#0]! */
3866 operand
->addr
.offset
.is_reg
= 0;
3867 operand
->addr
.offset
.imm
= 0;
3868 operand
->addr
.preind
= 1;
3873 set_syntax_error (_("missing offset in the pre-indexed address"));
3879 operand
->addr
.preind
= 1;
3880 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3882 operand
->addr
.offset
.is_reg
= 1;
3883 operand
->addr
.offset
.regno
= REG_ZR
;
3884 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3888 inst
.reloc
.exp
.X_op
= O_constant
;
3889 inst
.reloc
.exp
.X_add_number
= 0;
3898 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3901 parse_address (char **str
, aarch64_opnd_info
*operand
)
3903 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3904 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3905 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3908 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3909 The arguments have the same meaning as for parse_address_main.
3910 Return TRUE on success. */
3912 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3913 aarch64_opnd_qualifier_t
*base_qualifier
,
3914 aarch64_opnd_qualifier_t
*offset_qualifier
)
3916 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3917 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3921 /* Parse a register X0-X30. The register must be 64-bit and register 31
3924 parse_x0_to_x30 (char **str
, aarch64_opnd_info
*operand
)
3926 const reg_entry
*reg
= parse_reg (str
);
3927 if (!reg
|| !aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3929 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3932 operand
->reg
.regno
= reg
->number
;
3933 operand
->qualifier
= AARCH64_OPND_QLF_X
;
3937 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3938 Return TRUE on success; otherwise return FALSE. */
3940 parse_half (char **str
, int *internal_fixup_p
)
3944 skip_past_char (&p
, '#');
3946 gas_assert (internal_fixup_p
);
3947 *internal_fixup_p
= 0;
3951 struct reloc_table_entry
*entry
;
3953 /* Try to parse a relocation. Anything else is an error. */
3956 if (!(entry
= find_reloc_table_entry (&p
)))
3958 set_syntax_error (_("unknown relocation modifier"));
3962 if (entry
->movw_type
== 0)
3965 (_("this relocation modifier is not allowed on this instruction"));
3969 inst
.reloc
.type
= entry
->movw_type
;
3972 *internal_fixup_p
= 1;
3974 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
3975 aarch64_force_reloc (inst
.reloc
.type
) == 1))
3982 /* Parse an operand for an ADRP instruction:
3984 Return TRUE on success; otherwise return FALSE. */
3987 parse_adrp (char **str
)
3994 struct reloc_table_entry
*entry
;
3996 /* Try to parse a relocation. Anything else is an error. */
3998 if (!(entry
= find_reloc_table_entry (&p
)))
4000 set_syntax_error (_("unknown relocation modifier"));
4004 if (entry
->adrp_type
== 0)
4007 (_("this relocation modifier is not allowed on this instruction"));
4011 inst
.reloc
.type
= entry
->adrp_type
;
4014 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
4016 inst
.reloc
.pc_rel
= 1;
4017 if (! aarch64_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, REJECT_ABSENT
,
4018 aarch64_force_reloc (inst
.reloc
.type
) == 1))
4024 /* Miscellaneous. */
4026 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
4027 of SIZE tokens in which index I gives the token for field value I,
4028 or is null if field value I is invalid. REG_TYPE says which register
4029 names should be treated as registers rather than as symbolic immediates.
4031 Return true on success, moving *STR past the operand and storing the
4032 field value in *VAL. */
4035 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
4036 size_t size
, aarch64_reg_type reg_type
)
4042 /* Match C-like tokens. */
4044 while (ISALNUM (*q
))
4047 for (i
= 0; i
< size
; ++i
)
4049 && strncasecmp (array
[i
], p
, q
- p
) == 0
4050 && array
[i
][q
- p
] == 0)
4057 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
4060 if (exp
.X_op
== O_constant
4061 && (uint64_t) exp
.X_add_number
< size
)
4063 *val
= exp
.X_add_number
;
4068 /* Use the default error for this operand. */
4072 /* Parse an option for a preload instruction. Returns the encoding for the
4073 option, or PARSE_FAIL. */
4076 parse_pldop (char **str
)
4079 const struct aarch64_name_value_pair
*o
;
4082 while (ISALNUM (*q
))
4085 o
= str_hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
4093 /* Parse an option for a barrier instruction. Returns the encoding for the
4094 option, or PARSE_FAIL. */
4097 parse_barrier (char **str
)
4100 const struct aarch64_name_value_pair
*o
;
4103 while (ISALPHA (*q
))
4106 o
= str_hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
4114 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
4115 return 0 if successful. Otherwise return PARSE_FAIL. */
4118 parse_barrier_psb (char **str
,
4119 const struct aarch64_name_value_pair
** hint_opt
)
4122 const struct aarch64_name_value_pair
*o
;
4125 while (ISALPHA (*q
))
4128 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4131 set_fatal_syntax_error
4132 ( _("unknown or missing option to PSB/TSB"));
4136 if (o
->value
!= 0x11)
4138 /* PSB only accepts option name 'CSYNC'. */
4140 (_("the specified option is not accepted for PSB/TSB"));
4149 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
4150 return 0 if successful. Otherwise return PARSE_FAIL. */
4153 parse_bti_operand (char **str
,
4154 const struct aarch64_name_value_pair
** hint_opt
)
4157 const struct aarch64_name_value_pair
*o
;
4160 while (ISALPHA (*q
))
4163 o
= str_hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4166 set_fatal_syntax_error
4167 ( _("unknown option to BTI"));
4173 /* Valid BTI operands. */
4181 (_("unknown option to BTI"));
4190 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4191 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4196 Side effect: Update STR with current parse position of success.
4199 static const reg_entry
*
4200 parse_reg_with_qual (char **str
, aarch64_reg_type reg_type
,
4201 aarch64_opnd_qualifier_t
*qualifier
)
4205 reg_entry
*reg
= parse_reg (str
);
4206 if (reg
!= NULL
&& reg
->type
== reg_type
)
4208 if (!skip_past_char (str
, '.'))
4210 set_syntax_error (_("missing ZA tile element size separator"));
4215 switch (TOLOWER (*q
))
4218 *qualifier
= AARCH64_OPND_QLF_S_B
;
4221 *qualifier
= AARCH64_OPND_QLF_S_H
;
4224 *qualifier
= AARCH64_OPND_QLF_S_S
;
4227 *qualifier
= AARCH64_OPND_QLF_S_D
;
4230 *qualifier
= AARCH64_OPND_QLF_S_Q
;
4244 /* Parse SME ZA tile encoded in <ZAda> assembler symbol.
4245 Function return tile QUALIFIER on success.
4247 Tiles are in example format: za[0-9]\.[bhsd]
4249 Function returns <ZAda> register number or PARSE_FAIL.
4252 parse_sme_zada_operand (char **str
, aarch64_opnd_qualifier_t
*qualifier
)
4255 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_ZA
, qualifier
);
4259 regno
= reg
->number
;
4263 case AARCH64_OPND_QLF_S_B
:
4266 set_syntax_error (_("invalid ZA tile register number, expected za0"));
4270 case AARCH64_OPND_QLF_S_H
:
4273 set_syntax_error (_("invalid ZA tile register number, expected za0-za1"));
4277 case AARCH64_OPND_QLF_S_S
:
4280 /* For the 32-bit variant: is the name of the ZA tile ZA0-ZA3. */
4281 set_syntax_error (_("invalid ZA tile register number, expected za0-za3"));
4285 case AARCH64_OPND_QLF_S_D
:
4288 /* For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 */
4289 set_syntax_error (_("invalid ZA tile register number, expected za0-za7"));
4294 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s and d"));
4301 /* Parse STR for unsigned, immediate (1-2 digits) in format:
4306 Function return TRUE if immediate was found, or FALSE.
4309 parse_sme_immediate (char **str
, int64_t *imm
)
4312 if (! parse_constant_immediate (str
, &val
, REG_TYPE_R_N
))
4319 /* Parse index with vector select register and immediate:
4323 where <Wv> is in W12-W15 range and # is optional for immediate.
4325 Function performs extra check for mandatory immediate value if REQUIRE_IMM
4328 On success function returns TRUE and populated VECTOR_SELECT_REGISTER and
4332 parse_sme_za_hv_tiles_operand_index (char **str
,
4333 int *vector_select_register
,
4336 const reg_entry
*reg
;
4338 if (!skip_past_char (str
, '['))
4340 set_syntax_error (_("expected '['"));
4344 /* Vector select register W12-W15 encoded in the 2-bit Rv field. */
4345 reg
= parse_reg (str
);
4346 if (reg
== NULL
|| reg
->type
!= REG_TYPE_R_32
4347 || reg
->number
< 12 || reg
->number
> 15)
4349 set_syntax_error (_("expected vector select register W12-W15"));
4352 *vector_select_register
= reg
->number
;
4354 if (!skip_past_char (str
, ',')) /* Optional index offset immediate. */
4356 set_syntax_error (_("expected ','"));
4360 if (!parse_sme_immediate (str
, imm
))
4362 set_syntax_error (_("index offset immediate expected"));
4366 if (!skip_past_char (str
, ']'))
4368 set_syntax_error (_("expected ']'"));
4375 /* Parse SME ZA horizontal or vertical vector access to tiles.
4376 Function extracts from STR to SLICE_INDICATOR <HV> horizontal (0) or
4377 vertical (1) ZA tile vector orientation. VECTOR_SELECT_REGISTER
4378 contains <Wv> select register and corresponding optional IMMEDIATE.
4379 In addition QUALIFIER is extracted.
4381 Field format examples:
4383 ZA0<HV>.B[<Wv>, #<imm>]
4384 <ZAn><HV>.H[<Wv>, #<imm>]
4385 <ZAn><HV>.S[<Wv>, #<imm>]
4386 <ZAn><HV>.D[<Wv>, #<imm>]
4387 <ZAn><HV>.Q[<Wv>, #<imm>]
4389 Function returns <ZAda> register number or PARSE_FAIL.
4392 parse_sme_za_hv_tiles_operand (char **str
,
4393 enum sme_hv_slice
*slice_indicator
,
4394 int *vector_select_register
,
4396 aarch64_opnd_qualifier_t
*qualifier
)
4403 const reg_entry
*reg
;
4406 if ((reg
= parse_reg_with_qual (&qh
, REG_TYPE_ZAH
, qualifier
)) != NULL
)
4408 *slice_indicator
= HV_horizontal
;
4411 else if ((reg
= parse_reg_with_qual (&qv
, REG_TYPE_ZAV
, qualifier
)) != NULL
)
4413 *slice_indicator
= HV_vertical
;
4418 regno
= reg
->number
;
4422 case AARCH64_OPND_QLF_S_B
:
4426 case AARCH64_OPND_QLF_S_H
:
4430 case AARCH64_OPND_QLF_S_S
:
4434 case AARCH64_OPND_QLF_S_D
:
4438 case AARCH64_OPND_QLF_S_Q
:
4443 set_syntax_error (_("invalid ZA tile element size, allowed b, h, s, d and q"));
4447 /* Check if destination register ZA tile vector is in range for given
4448 instruction variant. */
4449 if (regno
< 0 || regno
> regno_limit
)
4451 set_syntax_error (_("ZA tile vector out of range"));
4455 if (!parse_sme_za_hv_tiles_operand_index (str
, vector_select_register
,
4459 /* Check if optional index offset is in the range for instruction
4461 if (imm_value
< 0 || imm_value
> imm_limit
)
4463 set_syntax_error (_("index offset out of range"));
4474 parse_sme_za_hv_tiles_operand_with_braces (char **str
,
4475 enum sme_hv_slice
*slice_indicator
,
4476 int *vector_select_register
,
4478 aarch64_opnd_qualifier_t
*qualifier
)
4482 if (!skip_past_char (str
, '{'))
4484 set_syntax_error (_("expected '{'"));
4488 regno
= parse_sme_za_hv_tiles_operand (str
, slice_indicator
,
4489 vector_select_register
, imm
,
4492 if (regno
== PARSE_FAIL
)
4495 if (!skip_past_char (str
, '}'))
4497 set_syntax_error (_("expected '}'"));
4504 /* Parse list of up to eight 64-bit element tile names separated by commas in
4505 SME's ZERO instruction:
4509 Function returns <mask>:
4511 an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
4514 parse_sme_zero_mask(char **str
)
4518 aarch64_opnd_qualifier_t qualifier
;
4524 const reg_entry
*reg
= parse_reg_with_qual (&q
, REG_TYPE_ZA
, &qualifier
);
4527 int regno
= reg
->number
;
4528 if (qualifier
== AARCH64_OPND_QLF_S_B
&& regno
== 0)
4530 /* { ZA0.B } is assembled as all-ones immediate. */
4533 else if (qualifier
== AARCH64_OPND_QLF_S_H
&& regno
< 2)
4534 mask
|= 0x55 << regno
;
4535 else if (qualifier
== AARCH64_OPND_QLF_S_S
&& regno
< 4)
4536 mask
|= 0x11 << regno
;
4537 else if (qualifier
== AARCH64_OPND_QLF_S_D
&& regno
< 8)
4538 mask
|= 0x01 << regno
;
4541 set_syntax_error (_("wrong ZA tile element format"));
4546 else if (strncasecmp (q
, "za", 2) == 0
4549 /* { ZA } is assembled as all-ones immediate. */
4556 set_syntax_error (_("wrong ZA tile element format"));
4560 while (skip_past_char (&q
, ','));
4566 /* Wraps in curly braces <mask> operand ZERO instruction:
4570 Function returns value of <mask> bit-field.
4573 parse_sme_list_of_64bit_tiles (char **str
)
4577 if (!skip_past_char (str
, '{'))
4579 set_syntax_error (_("expected '{'"));
4583 /* Empty <mask> list is an all-zeros immediate. */
4584 if (!skip_past_char (str
, '}'))
4586 regno
= parse_sme_zero_mask (str
);
4587 if (regno
== PARSE_FAIL
)
4590 if (!skip_past_char (str
, '}'))
4592 set_syntax_error (_("expected '}'"));
4602 /* Parse ZA array operand used in e.g. STR and LDR instruction.
4608 Function returns <Wv> or PARSE_FAIL.
4611 parse_sme_za_array (char **str
, int *imm
)
4618 while (ISALPHA (*q
))
4621 if ((q
- p
!= 2) || strncasecmp ("za", p
, q
- p
) != 0)
4623 set_syntax_error (_("expected ZA array"));
4627 if (! parse_sme_za_hv_tiles_operand_index (&q
, ®no
, &imm_value
))
4630 if (imm_value
< 0 || imm_value
> 15)
4632 set_syntax_error (_("offset out of range"));
4641 /* Parse streaming mode operand for SMSTART and SMSTOP.
4645 Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
4648 parse_sme_sm_za (char **str
)
4653 while (ISALPHA (*q
))
4657 || (strncasecmp ("sm", p
, 2) != 0 && strncasecmp ("za", p
, 2) != 0))
4659 set_syntax_error (_("expected SM or ZA operand"));
4664 return TOLOWER (p
[0]);
4667 /* Parse the name of the source scalable predicate register, the index base
4668 register W12-W15 and the element index. Function performs element index
4669 limit checks as well as qualifier type checks.
4671 <Pn>.<T>[<Wv>, <imm>]
4672 <Pn>.<T>[<Wv>, #<imm>]
4674 On success function sets <Wv> to INDEX_BASE_REG, <T> to QUALIFIER and
4676 Function returns <Pn>, or PARSE_FAIL.
4679 parse_sme_pred_reg_with_index(char **str
,
4680 int *index_base_reg
,
4682 aarch64_opnd_qualifier_t
*qualifier
)
4687 const reg_entry
*reg
= parse_reg_with_qual (str
, REG_TYPE_PN
, qualifier
);
4691 regno
= reg
->number
;
4695 case AARCH64_OPND_QLF_S_B
:
4698 case AARCH64_OPND_QLF_S_H
:
4701 case AARCH64_OPND_QLF_S_S
:
4704 case AARCH64_OPND_QLF_S_D
:
4708 set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d"));
4712 if (! parse_sme_za_hv_tiles_operand_index (str
, index_base_reg
, &imm_value
))
4715 if (imm_value
< 0 || imm_value
> imm_limit
)
4717 set_syntax_error (_("element index out of range for given variant"));
4726 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4727 Returns the encoding for the option, or PARSE_FAIL.
4729 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4730 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4732 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4733 field, otherwise as a system register.
4737 parse_sys_reg (char **str
, htab_t sys_regs
,
4738 int imple_defined_p
, int pstatefield_p
,
4742 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4743 const aarch64_sys_reg
*o
;
4747 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4748 if (p
< buf
+ (sizeof (buf
) - 1))
4749 *p
++ = TOLOWER (*q
);
4752 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4753 valid system register. This is enforced by construction of the hash
4755 if (p
- buf
!= q
- *str
)
4758 o
= str_hash_find (sys_regs
, buf
);
4761 if (!imple_defined_p
)
4765 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4766 unsigned int op0
, op1
, cn
, cm
, op2
;
4768 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4771 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4773 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4780 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4781 as_bad (_("selected processor does not support PSTATE field "
4784 && !aarch64_sys_ins_reg_supported_p (cpu_variant
, o
->name
,
4785 o
->value
, o
->flags
, o
->features
))
4786 as_bad (_("selected processor does not support system register "
4788 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4789 as_warn (_("system register name '%s' is deprecated and may be "
4790 "removed in a future release"), buf
);
4800 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4801 for the option, or NULL. */
4803 static const aarch64_sys_ins_reg
*
4804 parse_sys_ins_reg (char **str
, htab_t sys_ins_regs
)
4807 char buf
[AARCH64_MAX_SYSREG_NAME_LEN
];
4808 const aarch64_sys_ins_reg
*o
;
4811 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4812 if (p
< buf
+ (sizeof (buf
) - 1))
4813 *p
++ = TOLOWER (*q
);
4816 /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
4817 valid system register. This is enforced by construction of the hash
4819 if (p
- buf
!= q
- *str
)
4822 o
= str_hash_find (sys_ins_regs
, buf
);
4826 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
,
4827 o
->name
, o
->value
, o
->flags
, 0))
4828 as_bad (_("selected processor does not support system register "
4830 if (aarch64_sys_reg_deprecated_p (o
->flags
))
4831 as_warn (_("system register name '%s' is deprecated and may be "
4832 "removed in a future release"), buf
);
4838 #define po_char_or_fail(chr) do { \
4839 if (! skip_past_char (&str, chr)) \
4843 #define po_reg_or_fail(regtype) do { \
4844 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4845 if (val == PARSE_FAIL) \
4847 set_default_error (); \
4852 #define po_int_reg_or_fail(reg_type) do { \
4853 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4854 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4856 set_default_error (); \
4859 info->reg.regno = reg->number; \
4860 info->qualifier = qualifier; \
4863 #define po_imm_nc_or_fail() do { \
4864 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4868 #define po_imm_or_fail(min, max) do { \
4869 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4871 if (val < min || val > max) \
4873 set_fatal_syntax_error (_("immediate value out of range "\
4874 #min " to "#max)); \
4879 #define po_enum_or_fail(array) do { \
4880 if (!parse_enum_string (&str, &val, array, \
4881 ARRAY_SIZE (array), imm_reg_type)) \
4885 #define po_misc_or_fail(expr) do { \
4890 /* encode the 12-bit imm field of Add/sub immediate */
4891 static inline uint32_t
4892 encode_addsub_imm (uint32_t imm
)
4897 /* encode the shift amount field of Add/sub immediate */
4898 static inline uint32_t
4899 encode_addsub_imm_shift_amount (uint32_t cnt
)
4905 /* encode the imm field of Adr instruction */
4906 static inline uint32_t
4907 encode_adr_imm (uint32_t imm
)
4909 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4910 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4913 /* encode the immediate field of Move wide immediate */
4914 static inline uint32_t
4915 encode_movw_imm (uint32_t imm
)
4920 /* encode the 26-bit offset of unconditional branch */
4921 static inline uint32_t
4922 encode_branch_ofs_26 (uint32_t ofs
)
4924 return ofs
& ((1 << 26) - 1);
4927 /* encode the 19-bit offset of conditional branch and compare & branch */
4928 static inline uint32_t
4929 encode_cond_branch_ofs_19 (uint32_t ofs
)
4931 return (ofs
& ((1 << 19) - 1)) << 5;
4934 /* encode the 19-bit offset of ld literal */
4935 static inline uint32_t
4936 encode_ld_lit_ofs_19 (uint32_t ofs
)
4938 return (ofs
& ((1 << 19) - 1)) << 5;
4941 /* Encode the 14-bit offset of test & branch. */
4942 static inline uint32_t
4943 encode_tst_branch_ofs_14 (uint32_t ofs
)
4945 return (ofs
& ((1 << 14) - 1)) << 5;
4948 /* Encode the 16-bit imm field of svc/hvc/smc. */
4949 static inline uint32_t
4950 encode_svc_imm (uint32_t imm
)
4955 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4956 static inline uint32_t
4957 reencode_addsub_switch_add_sub (uint32_t opcode
)
4959 return opcode
^ (1 << 30);
4962 static inline uint32_t
4963 reencode_movzn_to_movz (uint32_t opcode
)
4965 return opcode
| (1 << 30);
4968 static inline uint32_t
4969 reencode_movzn_to_movn (uint32_t opcode
)
4971 return opcode
& ~(1 << 30);
4974 /* Overall per-instruction processing. */
4976 /* We need to be able to fix up arbitrary expressions in some statements.
4977 This is so that we can handle symbols that are an arbitrary distance from
4978 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4979 which returns part of an address in a form which will be valid for
4980 a data instruction. We do this by pushing the expression into a symbol
4981 in the expr_section, and creating a fix for that. */
4984 fix_new_aarch64 (fragS
* frag
,
4999 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
5003 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
5010 /* Diagnostics on operands errors. */
5012 /* By default, output verbose error message.
5013 Disable the verbose error message by -mno-verbose-error. */
5014 static int verbose_error_p
= 1;
5016 #ifdef DEBUG_AARCH64
5017 /* N.B. this is only for the purpose of debugging. */
5018 const char* operand_mismatch_kind_names
[] =
5021 "AARCH64_OPDE_RECOVERABLE",
5022 "AARCH64_OPDE_A_SHOULD_FOLLOW_B",
5023 "AARCH64_OPDE_EXPECTED_A_AFTER_B",
5024 "AARCH64_OPDE_SYNTAX_ERROR",
5025 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
5026 "AARCH64_OPDE_INVALID_VARIANT",
5027 "AARCH64_OPDE_OUT_OF_RANGE",
5028 "AARCH64_OPDE_UNALIGNED",
5029 "AARCH64_OPDE_REG_LIST",
5030 "AARCH64_OPDE_OTHER_ERROR",
5032 #endif /* DEBUG_AARCH64 */
5034 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
5036 When multiple errors of different kinds are found in the same assembly
5037 line, only the error of the highest severity will be picked up for
5038 issuing the diagnostics. */
5041 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
5042 enum aarch64_operand_error_kind rhs
)
5044 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
5045 gas_assert (AARCH64_OPDE_A_SHOULD_FOLLOW_B
> AARCH64_OPDE_RECOVERABLE
);
5046 gas_assert (AARCH64_OPDE_EXPECTED_A_AFTER_B
> AARCH64_OPDE_RECOVERABLE
);
5047 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_A_SHOULD_FOLLOW_B
);
5048 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_EXPECTED_A_AFTER_B
);
5049 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
5050 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
5051 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
5052 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
5053 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
5054 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
5058 /* Helper routine to get the mnemonic name from the assembly instruction
5059 line; should only be called for the diagnosis purpose, as there is
5060 string copy operation involved, which may affect the runtime
5061 performance if used in elsewhere. */
5064 get_mnemonic_name (const char *str
)
5066 static char mnemonic
[32];
5069 /* Get the first 15 bytes and assume that the full name is included. */
5070 strncpy (mnemonic
, str
, 31);
5071 mnemonic
[31] = '\0';
5073 /* Scan up to the end of the mnemonic, which must end in white space,
5074 '.', or end of string. */
5075 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
5080 /* Append '...' to the truncated long name. */
5081 if (ptr
- mnemonic
== 31)
5082 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
5088 reset_aarch64_instruction (aarch64_instruction
*instruction
)
5090 memset (instruction
, '\0', sizeof (aarch64_instruction
));
5091 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
5094 /* Data structures storing one user error in the assembly code related to
5097 struct operand_error_record
5099 const aarch64_opcode
*opcode
;
5100 aarch64_operand_error detail
;
5101 struct operand_error_record
*next
;
5104 typedef struct operand_error_record operand_error_record
;
5106 struct operand_errors
5108 operand_error_record
*head
;
5109 operand_error_record
*tail
;
5112 typedef struct operand_errors operand_errors
;
5114 /* Top-level data structure reporting user errors for the current line of
5116 The way md_assemble works is that all opcodes sharing the same mnemonic
5117 name are iterated to find a match to the assembly line. In this data
5118 structure, each of the such opcodes will have one operand_error_record
5119 allocated and inserted. In other words, excessive errors related with
5120 a single opcode are disregarded. */
5121 operand_errors operand_error_report
;
5123 /* Free record nodes. */
5124 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
5126 /* Initialize the data structure that stores the operand mismatch
5127 information on assembling one line of the assembly code. */
5129 init_operand_error_report (void)
5131 if (operand_error_report
.head
!= NULL
)
5133 gas_assert (operand_error_report
.tail
!= NULL
);
5134 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
5135 free_opnd_error_record_nodes
= operand_error_report
.head
;
5136 operand_error_report
.head
= NULL
;
5137 operand_error_report
.tail
= NULL
;
5140 gas_assert (operand_error_report
.tail
== NULL
);
5143 /* Return TRUE if some operand error has been recorded during the
5144 parsing of the current assembly line using the opcode *OPCODE;
5145 otherwise return FALSE. */
5147 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
5149 operand_error_record
*record
= operand_error_report
.head
;
5150 return record
&& record
->opcode
== opcode
;
5153 /* Add the error record *NEW_RECORD to operand_error_report. The record's
5154 OPCODE field is initialized with OPCODE.
5155 N.B. only one record for each opcode, i.e. the maximum of one error is
5156 recorded for each instruction template. */
5159 add_operand_error_record (const operand_error_record
* new_record
)
5161 const aarch64_opcode
*opcode
= new_record
->opcode
;
5162 operand_error_record
* record
= operand_error_report
.head
;
5164 /* The record may have been created for this opcode. If not, we need
5166 if (! opcode_has_operand_error_p (opcode
))
5168 /* Get one empty record. */
5169 if (free_opnd_error_record_nodes
== NULL
)
5171 record
= XNEW (operand_error_record
);
5175 record
= free_opnd_error_record_nodes
;
5176 free_opnd_error_record_nodes
= record
->next
;
5178 record
->opcode
= opcode
;
5179 /* Insert at the head. */
5180 record
->next
= operand_error_report
.head
;
5181 operand_error_report
.head
= record
;
5182 if (operand_error_report
.tail
== NULL
)
5183 operand_error_report
.tail
= record
;
5185 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
5186 && record
->detail
.index
<= new_record
->detail
.index
5187 && operand_error_higher_severity_p (record
->detail
.kind
,
5188 new_record
->detail
.kind
))
5190 /* In the case of multiple errors found on operands related with a
5191 single opcode, only record the error of the leftmost operand and
5192 only if the error is of higher severity. */
5193 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
5194 " the existing error %s on operand %d",
5195 operand_mismatch_kind_names
[new_record
->detail
.kind
],
5196 new_record
->detail
.index
,
5197 operand_mismatch_kind_names
[record
->detail
.kind
],
5198 record
->detail
.index
);
5202 record
->detail
= new_record
->detail
;
5206 record_operand_error_info (const aarch64_opcode
*opcode
,
5207 aarch64_operand_error
*error_info
)
5209 operand_error_record record
;
5210 record
.opcode
= opcode
;
5211 record
.detail
= *error_info
;
5212 add_operand_error_record (&record
);
5215 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
5216 error message *ERROR, for operand IDX (count from 0). */
5219 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
5220 enum aarch64_operand_error_kind kind
,
5223 aarch64_operand_error info
;
5224 memset(&info
, 0, sizeof (info
));
5228 info
.non_fatal
= false;
5229 record_operand_error_info (opcode
, &info
);
5233 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
5234 enum aarch64_operand_error_kind kind
,
5235 const char* error
, const int *extra_data
)
5237 aarch64_operand_error info
;
5241 info
.data
[0].i
= extra_data
[0];
5242 info
.data
[1].i
= extra_data
[1];
5243 info
.data
[2].i
= extra_data
[2];
5244 info
.non_fatal
= false;
5245 record_operand_error_info (opcode
, &info
);
5249 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
5250 const char* error
, int lower_bound
,
5253 int data
[3] = {lower_bound
, upper_bound
, 0};
5254 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
5258 /* Remove the operand error record for *OPCODE. */
5259 static void ATTRIBUTE_UNUSED
5260 remove_operand_error_record (const aarch64_opcode
*opcode
)
5262 if (opcode_has_operand_error_p (opcode
))
5264 operand_error_record
* record
= operand_error_report
.head
;
5265 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
5266 operand_error_report
.head
= record
->next
;
5267 record
->next
= free_opnd_error_record_nodes
;
5268 free_opnd_error_record_nodes
= record
;
5269 if (operand_error_report
.head
== NULL
)
5271 gas_assert (operand_error_report
.tail
== record
);
5272 operand_error_report
.tail
= NULL
;
5277 /* Given the instruction in *INSTR, return the index of the best matched
5278 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5280 Return -1 if there is no qualifier sequence; return the first match
5281 if there is multiple matches found. */
5284 find_best_match (const aarch64_inst
*instr
,
5285 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
5287 int i
, num_opnds
, max_num_matched
, idx
;
5289 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5292 DEBUG_TRACE ("no operand");
5296 max_num_matched
= 0;
5299 /* For each pattern. */
5300 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5303 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
5305 /* Most opcodes has much fewer patterns in the list. */
5306 if (empty_qualifier_sequence_p (qualifiers
))
5308 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
5312 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
5313 if (*qualifiers
== instr
->operands
[j
].qualifier
)
5316 if (num_matched
> max_num_matched
)
5318 max_num_matched
= num_matched
;
5323 DEBUG_TRACE ("return with %d", idx
);
5327 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5328 corresponding operands in *INSTR. */
5331 assign_qualifier_sequence (aarch64_inst
*instr
,
5332 const aarch64_opnd_qualifier_t
*qualifiers
)
5335 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
5336 gas_assert (num_opnds
);
5337 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
5338 instr
->operands
[i
].qualifier
= *qualifiers
;
5341 /* Print operands for the diagnosis purpose. */
5344 print_operands (char *buf
, const aarch64_opcode
*opcode
,
5345 const aarch64_opnd_info
*opnds
)
5349 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
5353 /* We regard the opcode operand info more, however we also look into
5354 the inst->operands to support the disassembling of the optional
5356 The two operand code should be the same in all cases, apart from
5357 when the operand can be optional. */
5358 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
5359 || opnds
[i
].type
== AARCH64_OPND_NIL
)
5362 /* Generate the operand string in STR. */
5363 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
5368 strcat (buf
, i
== 0 ? " " : ", ");
5370 /* Append the operand string. */
5375 /* Send to stderr a string as information. */
5378 output_info (const char *format
, ...)
5384 file
= as_where (&line
);
5388 fprintf (stderr
, "%s:%u: ", file
, line
);
5390 fprintf (stderr
, "%s: ", file
);
5392 fprintf (stderr
, _("Info: "));
5393 va_start (args
, format
);
5394 vfprintf (stderr
, format
, args
);
5396 (void) putc ('\n', stderr
);
5399 /* Output one operand error record. */
5402 output_operand_error_record (const operand_error_record
*record
, char *str
)
5404 const aarch64_operand_error
*detail
= &record
->detail
;
5405 int idx
= detail
->index
;
5406 const aarch64_opcode
*opcode
= record
->opcode
;
5407 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
5408 : AARCH64_OPND_NIL
);
5410 typedef void (*handler_t
)(const char *format
, ...);
5411 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
5413 switch (detail
->kind
)
5415 case AARCH64_OPDE_NIL
:
5419 case AARCH64_OPDE_A_SHOULD_FOLLOW_B
:
5420 handler (_("this `%s' should have an immediately preceding `%s'"
5422 detail
->data
[0].s
, detail
->data
[1].s
, str
);
5425 case AARCH64_OPDE_EXPECTED_A_AFTER_B
:
5426 handler (_("the preceding `%s' should be followed by `%s` rather"
5427 " than `%s` -- `%s'"),
5428 detail
->data
[1].s
, detail
->data
[0].s
, opcode
->name
, str
);
5431 case AARCH64_OPDE_SYNTAX_ERROR
:
5432 case AARCH64_OPDE_RECOVERABLE
:
5433 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
5434 case AARCH64_OPDE_OTHER_ERROR
:
5435 /* Use the prepared error message if there is, otherwise use the
5436 operand description string to describe the error. */
5437 if (detail
->error
!= NULL
)
5440 handler (_("%s -- `%s'"), detail
->error
, str
);
5442 handler (_("%s at operand %d -- `%s'"),
5443 detail
->error
, idx
+ 1, str
);
5447 gas_assert (idx
>= 0);
5448 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
5449 aarch64_get_operand_desc (opd_code
), str
);
5453 case AARCH64_OPDE_INVALID_VARIANT
:
5454 handler (_("operand mismatch -- `%s'"), str
);
5455 if (verbose_error_p
)
5457 /* We will try to correct the erroneous instruction and also provide
5458 more information e.g. all other valid variants.
5460 The string representation of the corrected instruction and other
5461 valid variants are generated by
5463 1) obtaining the intermediate representation of the erroneous
5465 2) manipulating the IR, e.g. replacing the operand qualifier;
5466 3) printing out the instruction by calling the printer functions
5467 shared with the disassembler.
5469 The limitation of this method is that the exact input assembly
5470 line cannot be accurately reproduced in some cases, for example an
5471 optional operand present in the actual assembly line will be
5472 omitted in the output; likewise for the optional syntax rules,
5473 e.g. the # before the immediate. Another limitation is that the
5474 assembly symbols and relocation operations in the assembly line
5475 currently cannot be printed out in the error report. Last but not
5476 least, when there is other error(s) co-exist with this error, the
5477 'corrected' instruction may be still incorrect, e.g. given
5478 'ldnp h0,h1,[x0,#6]!'
5479 this diagnosis will provide the version:
5480 'ldnp s0,s1,[x0,#6]!'
5481 which is still not right. */
5482 size_t len
= strlen (get_mnemonic_name (str
));
5486 aarch64_inst
*inst_base
= &inst
.base
;
5487 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
5490 reset_aarch64_instruction (&inst
);
5491 inst_base
->opcode
= opcode
;
5493 /* Reset the error report so that there is no side effect on the
5494 following operand parsing. */
5495 init_operand_error_report ();
5498 result
= parse_operands (str
+ len
, opcode
)
5499 && programmer_friendly_fixup (&inst
);
5500 gas_assert (result
);
5501 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
5502 NULL
, NULL
, insn_sequence
);
5503 gas_assert (!result
);
5505 /* Find the most matched qualifier sequence. */
5506 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
5507 gas_assert (qlf_idx
> -1);
5509 /* Assign the qualifiers. */
5510 assign_qualifier_sequence (inst_base
,
5511 opcode
->qualifiers_list
[qlf_idx
]);
5513 /* Print the hint. */
5514 output_info (_(" did you mean this?"));
5515 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5516 print_operands (buf
, opcode
, inst_base
->operands
);
5517 output_info (_(" %s"), buf
);
5519 /* Print out other variant(s) if there is any. */
5521 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
5522 output_info (_(" other valid variant(s):"));
5524 /* For each pattern. */
5525 qualifiers_list
= opcode
->qualifiers_list
;
5526 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
5528 /* Most opcodes has much fewer patterns in the list.
5529 First NIL qualifier indicates the end in the list. */
5530 if (empty_qualifier_sequence_p (*qualifiers_list
))
5535 /* Mnemonics name. */
5536 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
5538 /* Assign the qualifiers. */
5539 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
5541 /* Print instruction. */
5542 print_operands (buf
, opcode
, inst_base
->operands
);
5544 output_info (_(" %s"), buf
);
5550 case AARCH64_OPDE_UNTIED_IMMS
:
5551 handler (_("operand %d must have the same immediate value "
5552 "as operand 1 -- `%s'"),
5553 detail
->index
+ 1, str
);
5556 case AARCH64_OPDE_UNTIED_OPERAND
:
5557 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
5558 detail
->index
+ 1, str
);
5561 case AARCH64_OPDE_OUT_OF_RANGE
:
5562 if (detail
->data
[0].i
!= detail
->data
[1].i
)
5563 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
5564 detail
->error
? detail
->error
: _("immediate value"),
5565 detail
->data
[0].i
, detail
->data
[1].i
, idx
+ 1, str
);
5567 handler (_("%s must be %d at operand %d -- `%s'"),
5568 detail
->error
? detail
->error
: _("immediate value"),
5569 detail
->data
[0].i
, idx
+ 1, str
);
5572 case AARCH64_OPDE_REG_LIST
:
5573 if (detail
->data
[0].i
== 1)
5574 handler (_("invalid number of registers in the list; "
5575 "only 1 register is expected at operand %d -- `%s'"),
5578 handler (_("invalid number of registers in the list; "
5579 "%d registers are expected at operand %d -- `%s'"),
5580 detail
->data
[0].i
, idx
+ 1, str
);
5583 case AARCH64_OPDE_UNALIGNED
:
5584 handler (_("immediate value must be a multiple of "
5585 "%d at operand %d -- `%s'"),
5586 detail
->data
[0].i
, idx
+ 1, str
);
5595 /* Process and output the error message about the operand mismatching.
5597 When this function is called, the operand error information had
5598 been collected for an assembly line and there will be multiple
5599 errors in the case of multiple instruction templates; output the
5600 error message that most closely describes the problem.
5602 The errors to be printed can be filtered on printing all errors
5603 or only non-fatal errors. This distinction has to be made because
5604 the error buffer may already be filled with fatal errors we don't want to
5605 print due to the different instruction templates. */
5608 output_operand_error_report (char *str
, bool non_fatal_only
)
5610 int largest_error_pos
;
5611 const char *msg
= NULL
;
5612 enum aarch64_operand_error_kind kind
;
5613 operand_error_record
*curr
;
5614 operand_error_record
*head
= operand_error_report
.head
;
5615 operand_error_record
*record
= NULL
;
5617 /* No error to report. */
5621 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
5623 /* Only one error. */
5624 if (head
== operand_error_report
.tail
)
5626 /* If the only error is a non-fatal one and we don't want to print it,
5628 if (!non_fatal_only
|| head
->detail
.non_fatal
)
5630 DEBUG_TRACE ("single opcode entry with error kind: %s",
5631 operand_mismatch_kind_names
[head
->detail
.kind
]);
5632 output_operand_error_record (head
, str
);
5637 /* Find the error kind of the highest severity. */
5638 DEBUG_TRACE ("multiple opcode entries with error kind");
5639 kind
= AARCH64_OPDE_NIL
;
5640 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5642 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
5643 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
5644 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
5645 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
5646 kind
= curr
->detail
.kind
;
5649 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
5651 /* Pick up one of errors of KIND to report. */
5652 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
5653 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
5655 /* If we don't want to print non-fatal errors then don't consider them
5657 if (curr
->detail
.kind
!= kind
5658 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
5660 /* If there are multiple errors, pick up the one with the highest
5661 mismatching operand index. In the case of multiple errors with
5662 the equally highest operand index, pick up the first one or the
5663 first one with non-NULL error message. */
5664 if (curr
->detail
.index
> largest_error_pos
5665 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
5666 && curr
->detail
.error
!= NULL
))
5668 largest_error_pos
= curr
->detail
.index
;
5670 msg
= record
->detail
.error
;
5674 /* The way errors are collected in the back-end is a bit non-intuitive. But
5675 essentially, because each operand template is tried recursively you may
5676 always have errors collected from the previous tried OPND. These are
5677 usually skipped if there is one successful match. However now with the
5678 non-fatal errors we have to ignore those previously collected hard errors
5679 when we're only interested in printing the non-fatal ones. This condition
5680 prevents us from printing errors that are not appropriate, since we did
5681 match a condition, but it also has warnings that it wants to print. */
5682 if (non_fatal_only
&& !record
)
5685 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
5686 DEBUG_TRACE ("Pick up error kind %s to report",
5687 operand_mismatch_kind_names
[record
->detail
.kind
]);
5690 output_operand_error_record (record
, str
);
5693 /* Write an AARCH64 instruction to buf - always little-endian. */
5695 put_aarch64_insn (char *buf
, uint32_t insn
)
5697 unsigned char *where
= (unsigned char *) buf
;
5699 where
[1] = insn
>> 8;
5700 where
[2] = insn
>> 16;
5701 where
[3] = insn
>> 24;
5705 get_aarch64_insn (char *buf
)
5707 unsigned char *where
= (unsigned char *) buf
;
5709 result
= ((where
[0] | (where
[1] << 8) | (where
[2] << 16)
5710 | ((uint32_t) where
[3] << 24)));
5715 output_inst (struct aarch64_inst
*new_inst
)
5719 to
= frag_more (INSN_SIZE
);
5721 frag_now
->tc_frag_data
.recorded
= 1;
5723 put_aarch64_insn (to
, inst
.base
.value
);
5725 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5727 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
5728 INSN_SIZE
, &inst
.reloc
.exp
,
5731 DEBUG_TRACE ("Prepared relocation fix up");
5732 /* Don't check the addend value against the instruction size,
5733 that's the job of our code in md_apply_fix(). */
5734 fixp
->fx_no_overflow
= 1;
5735 if (new_inst
!= NULL
)
5736 fixp
->tc_fix_data
.inst
= new_inst
;
5737 if (aarch64_gas_internal_fixup_p ())
5739 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
5740 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
5741 fixp
->fx_addnumber
= inst
.reloc
.flags
;
5745 dwarf2_emit_insn (INSN_SIZE
);
5748 /* Link together opcodes of the same name. */
5752 const aarch64_opcode
*opcode
;
5753 struct templates
*next
;
5756 typedef struct templates templates
;
5759 lookup_mnemonic (const char *start
, int len
)
5761 templates
*templ
= NULL
;
5763 templ
= str_hash_find_n (aarch64_ops_hsh
, start
, len
);
5767 /* Subroutine of md_assemble, responsible for looking up the primary
5768 opcode from the mnemonic the user wrote. BASE points to the beginning
5769 of the mnemonic, DOT points to the first '.' within the mnemonic
5770 (if any) and END points to the end of the mnemonic. */
5773 opcode_lookup (char *base
, char *dot
, char *end
)
5775 const aarch64_cond
*cond
;
5782 inst
.cond
= COND_ALWAYS
;
5784 /* Handle a possible condition. */
5787 cond
= str_hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5790 inst
.cond
= cond
->value
;
5796 if (inst
.cond
== COND_ALWAYS
)
5798 /* Look for unaffixed mnemonic. */
5799 return lookup_mnemonic (base
, len
);
5803 /* append ".c" to mnemonic if conditional */
5804 memcpy (condname
, base
, len
);
5805 memcpy (condname
+ len
, ".c", 2);
5808 return lookup_mnemonic (base
, len
);
5814 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5815 to a corresponding operand qualifier. */
5817 static inline aarch64_opnd_qualifier_t
5818 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5820 /* Element size in bytes indexed by vector_el_type. */
5821 const unsigned char ele_size
[5]
5823 const unsigned int ele_base
[5] =
5825 AARCH64_OPND_QLF_V_4B
,
5826 AARCH64_OPND_QLF_V_2H
,
5827 AARCH64_OPND_QLF_V_2S
,
5828 AARCH64_OPND_QLF_V_1D
,
5829 AARCH64_OPND_QLF_V_1Q
5832 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5833 goto vectype_conversion_fail
;
5835 if (vectype
->type
== NT_zero
)
5836 return AARCH64_OPND_QLF_P_Z
;
5837 if (vectype
->type
== NT_merge
)
5838 return AARCH64_OPND_QLF_P_M
;
5840 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5842 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5844 /* Special case S_4B. */
5845 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5846 return AARCH64_OPND_QLF_S_4B
;
5848 /* Special case S_2H. */
5849 if (vectype
->type
== NT_h
&& vectype
->width
== 2)
5850 return AARCH64_OPND_QLF_S_2H
;
5852 /* Vector element register. */
5853 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5857 /* Vector register. */
5858 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5861 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5862 goto vectype_conversion_fail
;
5864 /* The conversion is by calculating the offset from the base operand
5865 qualifier for the vector type. The operand qualifiers are regular
5866 enough that the offset can established by shifting the vector width by
5867 a vector-type dependent amount. */
5869 if (vectype
->type
== NT_b
)
5871 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5873 else if (vectype
->type
>= NT_d
)
5878 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5879 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5880 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5884 vectype_conversion_fail
:
5885 first_error (_("bad vector arrangement type"));
5886 return AARCH64_OPND_QLF_NIL
;
5889 /* Process an optional operand that is found omitted from the assembly line.
5890 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5891 instruction's opcode entry while IDX is the index of this omitted operand.
5895 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5896 int idx
, aarch64_opnd_info
*operand
)
5898 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5899 gas_assert (optional_operand_p (opcode
, idx
));
5900 gas_assert (!operand
->present
);
5904 case AARCH64_OPND_Rd
:
5905 case AARCH64_OPND_Rn
:
5906 case AARCH64_OPND_Rm
:
5907 case AARCH64_OPND_Rt
:
5908 case AARCH64_OPND_Rt2
:
5909 case AARCH64_OPND_Rt_LS64
:
5910 case AARCH64_OPND_Rt_SP
:
5911 case AARCH64_OPND_Rs
:
5912 case AARCH64_OPND_Ra
:
5913 case AARCH64_OPND_Rt_SYS
:
5914 case AARCH64_OPND_Rd_SP
:
5915 case AARCH64_OPND_Rn_SP
:
5916 case AARCH64_OPND_Rm_SP
:
5917 case AARCH64_OPND_Fd
:
5918 case AARCH64_OPND_Fn
:
5919 case AARCH64_OPND_Fm
:
5920 case AARCH64_OPND_Fa
:
5921 case AARCH64_OPND_Ft
:
5922 case AARCH64_OPND_Ft2
:
5923 case AARCH64_OPND_Sd
:
5924 case AARCH64_OPND_Sn
:
5925 case AARCH64_OPND_Sm
:
5926 case AARCH64_OPND_Va
:
5927 case AARCH64_OPND_Vd
:
5928 case AARCH64_OPND_Vn
:
5929 case AARCH64_OPND_Vm
:
5930 case AARCH64_OPND_VdD1
:
5931 case AARCH64_OPND_VnD1
:
5932 operand
->reg
.regno
= default_value
;
5935 case AARCH64_OPND_Ed
:
5936 case AARCH64_OPND_En
:
5937 case AARCH64_OPND_Em
:
5938 case AARCH64_OPND_Em16
:
5939 case AARCH64_OPND_SM3_IMM2
:
5940 operand
->reglane
.regno
= default_value
;
5943 case AARCH64_OPND_IDX
:
5944 case AARCH64_OPND_BIT_NUM
:
5945 case AARCH64_OPND_IMMR
:
5946 case AARCH64_OPND_IMMS
:
5947 case AARCH64_OPND_SHLL_IMM
:
5948 case AARCH64_OPND_IMM_VLSL
:
5949 case AARCH64_OPND_IMM_VLSR
:
5950 case AARCH64_OPND_CCMP_IMM
:
5951 case AARCH64_OPND_FBITS
:
5952 case AARCH64_OPND_UIMM4
:
5953 case AARCH64_OPND_UIMM3_OP1
:
5954 case AARCH64_OPND_UIMM3_OP2
:
5955 case AARCH64_OPND_IMM
:
5956 case AARCH64_OPND_IMM_2
:
5957 case AARCH64_OPND_WIDTH
:
5958 case AARCH64_OPND_UIMM7
:
5959 case AARCH64_OPND_NZCV
:
5960 case AARCH64_OPND_SVE_PATTERN
:
5961 case AARCH64_OPND_SVE_PRFOP
:
5962 operand
->imm
.value
= default_value
;
5965 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5966 operand
->imm
.value
= default_value
;
5967 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5968 operand
->shifter
.amount
= 1;
5971 case AARCH64_OPND_EXCEPTION
:
5972 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5975 case AARCH64_OPND_BARRIER_ISB
:
5976 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5979 case AARCH64_OPND_BTI_TARGET
:
5980 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5988 /* Process the relocation type for move wide instructions.
5989 Return TRUE on success; otherwise return FALSE. */
5992 process_movw_reloc_info (void)
5997 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5999 if (inst
.base
.opcode
->op
== OP_MOVK
)
6000 switch (inst
.reloc
.type
)
6002 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6003 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6004 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6005 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6006 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6007 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6008 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6009 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6010 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6011 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6012 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6014 (_("the specified relocation type is not allowed for MOVK"));
6020 switch (inst
.reloc
.type
)
6022 case BFD_RELOC_AARCH64_MOVW_G0
:
6023 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6024 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6025 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6026 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
6027 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
6028 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6029 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
6030 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
6031 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
6032 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
6033 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
6034 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
6037 case BFD_RELOC_AARCH64_MOVW_G1
:
6038 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6039 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6040 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6041 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
6042 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
6043 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6044 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
6045 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
6046 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
6047 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
6048 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
6049 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
6052 case BFD_RELOC_AARCH64_MOVW_G2
:
6053 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6054 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6055 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
6056 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
6057 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
6058 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
6061 set_fatal_syntax_error
6062 (_("the specified relocation type is not allowed for 32-bit "
6068 case BFD_RELOC_AARCH64_MOVW_G3
:
6069 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
6072 set_fatal_syntax_error
6073 (_("the specified relocation type is not allowed for 32-bit "
6080 /* More cases should be added when more MOVW-related relocation types
6081 are supported in GAS. */
6082 gas_assert (aarch64_gas_internal_fixup_p ());
6083 /* The shift amount should have already been set by the parser. */
6086 inst
.base
.operands
[1].shifter
.amount
= shift
;
6090 /* A primitive log calculator. */
6092 static inline unsigned int
6093 get_logsz (unsigned int size
)
6095 const unsigned char ls
[16] =
6096 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
6102 gas_assert (ls
[size
- 1] != (unsigned char)-1);
6103 return ls
[size
- 1];
6106 /* Determine and return the real reloc type code for an instruction
6107 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
6109 static inline bfd_reloc_code_real_type
6110 ldst_lo12_determine_real_reloc_type (void)
6112 unsigned logsz
, max_logsz
;
6113 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
6114 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
6116 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
6118 BFD_RELOC_AARCH64_LDST8_LO12
,
6119 BFD_RELOC_AARCH64_LDST16_LO12
,
6120 BFD_RELOC_AARCH64_LDST32_LO12
,
6121 BFD_RELOC_AARCH64_LDST64_LO12
,
6122 BFD_RELOC_AARCH64_LDST128_LO12
6125 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
6126 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
6127 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
6128 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
6129 BFD_RELOC_AARCH64_NONE
6132 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
6133 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
6134 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
6135 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
6136 BFD_RELOC_AARCH64_NONE
6139 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
6140 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
6141 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
6142 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
6143 BFD_RELOC_AARCH64_NONE
6146 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
6147 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
6148 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
6149 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
6150 BFD_RELOC_AARCH64_NONE
6154 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6155 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6157 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6159 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6161 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
6162 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
6164 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
6166 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
6168 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
6170 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
6172 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
6173 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
6174 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
6175 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
6180 if (logsz
> max_logsz
)
6182 /* SEE PR 27904 for an example of this. */
6183 set_fatal_syntax_error
6184 (_("relocation qualifier does not match instruction size"));
6185 return BFD_RELOC_AARCH64_NONE
;
6188 /* In reloc.c, these pseudo relocation types should be defined in similar
6189 order as above reloc_ldst_lo12 array. Because the array index calculation
6190 below relies on this. */
6191 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
6194 /* Check whether a register list REGINFO is valid. The registers must be
6195 numbered in increasing order (modulo 32), in increments of one or two.
6197 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
6200 Return FALSE if such a register list is invalid, otherwise return TRUE. */
6203 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
6205 uint32_t i
, nb_regs
, prev_regno
, incr
;
6207 nb_regs
= 1 + (reginfo
& 0x3);
6209 prev_regno
= reginfo
& 0x1f;
6210 incr
= accept_alternate
? 2 : 1;
6212 for (i
= 1; i
< nb_regs
; ++i
)
6214 uint32_t curr_regno
;
6216 curr_regno
= reginfo
& 0x1f;
6217 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
6219 prev_regno
= curr_regno
;
6225 /* Generic instruction operand parser. This does no encoding and no
6226 semantic validation; it merely squirrels values away in the inst
6227 structure. Returns TRUE or FALSE depending on whether the
6228 specified grammar matched. */
6231 parse_operands (char *str
, const aarch64_opcode
*opcode
)
6234 char *backtrack_pos
= 0;
6235 const enum aarch64_opnd
*operands
= opcode
->operands
;
6236 aarch64_reg_type imm_reg_type
;
6239 skip_whitespace (str
);
6241 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
6242 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
6244 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
6246 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
6249 const reg_entry
*reg
;
6250 int comma_skipped_p
= 0;
6251 aarch64_reg_type rtype
;
6252 struct vector_type_el vectype
;
6253 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
6254 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
6255 aarch64_reg_type reg_type
;
6257 DEBUG_TRACE ("parse operand %d", i
);
6259 /* Assign the operand code. */
6260 info
->type
= operands
[i
];
6262 if (optional_operand_p (opcode
, i
))
6264 /* Remember where we are in case we need to backtrack. */
6265 gas_assert (!backtrack_pos
);
6266 backtrack_pos
= str
;
6269 /* Expect comma between operands; the backtrack mechanism will take
6270 care of cases of omitted optional operand. */
6271 if (i
> 0 && ! skip_past_char (&str
, ','))
6273 set_syntax_error (_("comma expected between operands"));
6277 comma_skipped_p
= 1;
6279 switch (operands
[i
])
6281 case AARCH64_OPND_Rd
:
6282 case AARCH64_OPND_Rn
:
6283 case AARCH64_OPND_Rm
:
6284 case AARCH64_OPND_Rt
:
6285 case AARCH64_OPND_Rt2
:
6286 case AARCH64_OPND_Rs
:
6287 case AARCH64_OPND_Ra
:
6288 case AARCH64_OPND_Rt_LS64
:
6289 case AARCH64_OPND_Rt_SYS
:
6290 case AARCH64_OPND_PAIRREG
:
6291 case AARCH64_OPND_SVE_Rm
:
6292 po_int_reg_or_fail (REG_TYPE_R_Z
);
6294 /* In LS64 load/store instructions Rt register number must be even
6296 if (operands
[i
] == AARCH64_OPND_Rt_LS64
)
6298 /* We've already checked if this is valid register.
6299 This will check if register number (Rt) is not undefined for LS64
6301 if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
6302 if ((info
->reg
.regno
& 0x18) == 0x18 || (info
->reg
.regno
& 0x01) == 0x01)
6304 set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
6310 case AARCH64_OPND_Rd_SP
:
6311 case AARCH64_OPND_Rn_SP
:
6312 case AARCH64_OPND_Rt_SP
:
6313 case AARCH64_OPND_SVE_Rn_SP
:
6314 case AARCH64_OPND_Rm_SP
:
6315 po_int_reg_or_fail (REG_TYPE_R_SP
);
6318 case AARCH64_OPND_Rm_EXT
:
6319 case AARCH64_OPND_Rm_SFT
:
6320 po_misc_or_fail (parse_shifter_operand
6321 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
6323 : SHIFTED_LOGIC_IMM
)));
6324 if (!info
->shifter
.operator_present
)
6326 /* Default to LSL if not present. Libopcodes prefers shifter
6327 kind to be explicit. */
6328 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6329 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6330 /* For Rm_EXT, libopcodes will carry out further check on whether
6331 or not stack pointer is used in the instruction (Recall that
6332 "the extend operator is not optional unless at least one of
6333 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
6337 case AARCH64_OPND_Fd
:
6338 case AARCH64_OPND_Fn
:
6339 case AARCH64_OPND_Fm
:
6340 case AARCH64_OPND_Fa
:
6341 case AARCH64_OPND_Ft
:
6342 case AARCH64_OPND_Ft2
:
6343 case AARCH64_OPND_Sd
:
6344 case AARCH64_OPND_Sn
:
6345 case AARCH64_OPND_Sm
:
6346 case AARCH64_OPND_SVE_VZn
:
6347 case AARCH64_OPND_SVE_Vd
:
6348 case AARCH64_OPND_SVE_Vm
:
6349 case AARCH64_OPND_SVE_Vn
:
6350 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
6351 if (val
== PARSE_FAIL
)
6353 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
6356 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
6358 info
->reg
.regno
= val
;
6359 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
6362 case AARCH64_OPND_SVE_Pd
:
6363 case AARCH64_OPND_SVE_Pg3
:
6364 case AARCH64_OPND_SVE_Pg4_5
:
6365 case AARCH64_OPND_SVE_Pg4_10
:
6366 case AARCH64_OPND_SVE_Pg4_16
:
6367 case AARCH64_OPND_SVE_Pm
:
6368 case AARCH64_OPND_SVE_Pn
:
6369 case AARCH64_OPND_SVE_Pt
:
6370 case AARCH64_OPND_SME_Pm
:
6371 reg_type
= REG_TYPE_PN
;
6374 case AARCH64_OPND_SVE_Za_5
:
6375 case AARCH64_OPND_SVE_Za_16
:
6376 case AARCH64_OPND_SVE_Zd
:
6377 case AARCH64_OPND_SVE_Zm_5
:
6378 case AARCH64_OPND_SVE_Zm_16
:
6379 case AARCH64_OPND_SVE_Zn
:
6380 case AARCH64_OPND_SVE_Zt
:
6381 reg_type
= REG_TYPE_ZN
;
6384 case AARCH64_OPND_Va
:
6385 case AARCH64_OPND_Vd
:
6386 case AARCH64_OPND_Vn
:
6387 case AARCH64_OPND_Vm
:
6388 reg_type
= REG_TYPE_VN
;
6390 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6391 if (val
== PARSE_FAIL
)
6393 first_error (_(get_reg_expected_msg (reg_type
)));
6396 if (vectype
.defined
& NTA_HASINDEX
)
6399 info
->reg
.regno
= val
;
6400 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
6401 && vectype
.type
== NT_invtype
)
6402 /* Unqualified Pn and Zn registers are allowed in certain
6403 contexts. Rely on F_STRICT qualifier checking to catch
6405 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
6408 info
->qualifier
= vectype_to_qualifier (&vectype
);
6409 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6414 case AARCH64_OPND_VdD1
:
6415 case AARCH64_OPND_VnD1
:
6416 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
6417 if (val
== PARSE_FAIL
)
6419 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
6422 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
6424 set_fatal_syntax_error
6425 (_("the top half of a 128-bit FP/SIMD register is expected"));
6428 info
->reg
.regno
= val
;
6429 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
6430 here; it is correct for the purpose of encoding/decoding since
6431 only the register number is explicitly encoded in the related
6432 instructions, although this appears a bit hacky. */
6433 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
6436 case AARCH64_OPND_SVE_Zm3_INDEX
:
6437 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
6438 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
6439 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
6440 case AARCH64_OPND_SVE_Zm4_INDEX
:
6441 case AARCH64_OPND_SVE_Zn_INDEX
:
6442 reg_type
= REG_TYPE_ZN
;
6443 goto vector_reg_index
;
6445 case AARCH64_OPND_Ed
:
6446 case AARCH64_OPND_En
:
6447 case AARCH64_OPND_Em
:
6448 case AARCH64_OPND_Em16
:
6449 case AARCH64_OPND_SM3_IMM2
:
6450 reg_type
= REG_TYPE_VN
;
6452 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6453 if (val
== PARSE_FAIL
)
6455 first_error (_(get_reg_expected_msg (reg_type
)));
6458 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
6461 info
->reglane
.regno
= val
;
6462 info
->reglane
.index
= vectype
.index
;
6463 info
->qualifier
= vectype_to_qualifier (&vectype
);
6464 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6468 case AARCH64_OPND_SVE_ZnxN
:
6469 case AARCH64_OPND_SVE_ZtxN
:
6470 reg_type
= REG_TYPE_ZN
;
6471 goto vector_reg_list
;
6473 case AARCH64_OPND_LVn
:
6474 case AARCH64_OPND_LVt
:
6475 case AARCH64_OPND_LVt_AL
:
6476 case AARCH64_OPND_LEt
:
6477 reg_type
= REG_TYPE_VN
;
6479 if (reg_type
== REG_TYPE_ZN
6480 && get_opcode_dependent_value (opcode
) == 1
6483 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
6484 if (val
== PARSE_FAIL
)
6486 first_error (_(get_reg_expected_msg (reg_type
)));
6489 info
->reglist
.first_regno
= val
;
6490 info
->reglist
.num_regs
= 1;
6494 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
6495 if (val
== PARSE_FAIL
)
6498 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
6500 set_fatal_syntax_error (_("invalid register list"));
6504 if (vectype
.width
!= 0 && *str
!= ',')
6506 set_fatal_syntax_error
6507 (_("expected element type rather than vector type"));
6511 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
6512 info
->reglist
.num_regs
= (val
& 0x3) + 1;
6514 if (operands
[i
] == AARCH64_OPND_LEt
)
6516 if (!(vectype
.defined
& NTA_HASINDEX
))
6518 info
->reglist
.has_index
= 1;
6519 info
->reglist
.index
= vectype
.index
;
6523 if (vectype
.defined
& NTA_HASINDEX
)
6525 if (!(vectype
.defined
& NTA_HASTYPE
))
6527 if (reg_type
== REG_TYPE_ZN
)
6528 set_fatal_syntax_error (_("missing type suffix"));
6532 info
->qualifier
= vectype_to_qualifier (&vectype
);
6533 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
6537 case AARCH64_OPND_CRn
:
6538 case AARCH64_OPND_CRm
:
6540 char prefix
= *(str
++);
6541 if (prefix
!= 'c' && prefix
!= 'C')
6544 po_imm_nc_or_fail ();
6547 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
6550 info
->qualifier
= AARCH64_OPND_QLF_CR
;
6551 info
->imm
.value
= val
;
6555 case AARCH64_OPND_SHLL_IMM
:
6556 case AARCH64_OPND_IMM_VLSR
:
6557 po_imm_or_fail (1, 64);
6558 info
->imm
.value
= val
;
6561 case AARCH64_OPND_CCMP_IMM
:
6562 case AARCH64_OPND_SIMM5
:
6563 case AARCH64_OPND_FBITS
:
6564 case AARCH64_OPND_TME_UIMM16
:
6565 case AARCH64_OPND_UIMM4
:
6566 case AARCH64_OPND_UIMM4_ADDG
:
6567 case AARCH64_OPND_UIMM10
:
6568 case AARCH64_OPND_UIMM3_OP1
:
6569 case AARCH64_OPND_UIMM3_OP2
:
6570 case AARCH64_OPND_IMM_VLSL
:
6571 case AARCH64_OPND_IMM
:
6572 case AARCH64_OPND_IMM_2
:
6573 case AARCH64_OPND_WIDTH
:
6574 case AARCH64_OPND_SVE_INV_LIMM
:
6575 case AARCH64_OPND_SVE_LIMM
:
6576 case AARCH64_OPND_SVE_LIMM_MOV
:
6577 case AARCH64_OPND_SVE_SHLIMM_PRED
:
6578 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
6579 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
6580 case AARCH64_OPND_SVE_SHRIMM_PRED
:
6581 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
6582 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
6583 case AARCH64_OPND_SVE_SIMM5
:
6584 case AARCH64_OPND_SVE_SIMM5B
:
6585 case AARCH64_OPND_SVE_SIMM6
:
6586 case AARCH64_OPND_SVE_SIMM8
:
6587 case AARCH64_OPND_SVE_UIMM3
:
6588 case AARCH64_OPND_SVE_UIMM7
:
6589 case AARCH64_OPND_SVE_UIMM8
:
6590 case AARCH64_OPND_SVE_UIMM8_53
:
6591 case AARCH64_OPND_IMM_ROT1
:
6592 case AARCH64_OPND_IMM_ROT2
:
6593 case AARCH64_OPND_IMM_ROT3
:
6594 case AARCH64_OPND_SVE_IMM_ROT1
:
6595 case AARCH64_OPND_SVE_IMM_ROT2
:
6596 case AARCH64_OPND_SVE_IMM_ROT3
:
6597 po_imm_nc_or_fail ();
6598 info
->imm
.value
= val
;
6601 case AARCH64_OPND_SVE_AIMM
:
6602 case AARCH64_OPND_SVE_ASIMM
:
6603 po_imm_nc_or_fail ();
6604 info
->imm
.value
= val
;
6605 skip_whitespace (str
);
6606 if (skip_past_comma (&str
))
6607 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6609 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6612 case AARCH64_OPND_SVE_PATTERN
:
6613 po_enum_or_fail (aarch64_sve_pattern_array
);
6614 info
->imm
.value
= val
;
6617 case AARCH64_OPND_SVE_PATTERN_SCALED
:
6618 po_enum_or_fail (aarch64_sve_pattern_array
);
6619 info
->imm
.value
= val
;
6620 if (skip_past_comma (&str
)
6621 && !parse_shift (&str
, info
, SHIFTED_MUL
))
6623 if (!info
->shifter
.operator_present
)
6625 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6626 info
->shifter
.kind
= AARCH64_MOD_MUL
;
6627 info
->shifter
.amount
= 1;
6631 case AARCH64_OPND_SVE_PRFOP
:
6632 po_enum_or_fail (aarch64_sve_prfop_array
);
6633 info
->imm
.value
= val
;
6636 case AARCH64_OPND_UIMM7
:
6637 po_imm_or_fail (0, 127);
6638 info
->imm
.value
= val
;
6641 case AARCH64_OPND_IDX
:
6642 case AARCH64_OPND_MASK
:
6643 case AARCH64_OPND_BIT_NUM
:
6644 case AARCH64_OPND_IMMR
:
6645 case AARCH64_OPND_IMMS
:
6646 po_imm_or_fail (0, 63);
6647 info
->imm
.value
= val
;
6650 case AARCH64_OPND_IMM0
:
6651 po_imm_nc_or_fail ();
6654 set_fatal_syntax_error (_("immediate zero expected"));
6657 info
->imm
.value
= 0;
6660 case AARCH64_OPND_FPIMM0
:
6663 bool res1
= false, res2
= false;
6664 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
6665 it is probably not worth the effort to support it. */
6666 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, false,
6669 || !(res2
= parse_constant_immediate (&str
, &val
,
6672 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
6674 info
->imm
.value
= 0;
6675 info
->imm
.is_fp
= 1;
6678 set_fatal_syntax_error (_("immediate zero expected"));
6682 case AARCH64_OPND_IMM_MOV
:
6685 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
6686 reg_name_p (str
, REG_TYPE_VN
))
6689 po_misc_or_fail (aarch64_get_expression (&inst
.reloc
.exp
, &str
,
6690 GE_OPT_PREFIX
, REJECT_ABSENT
,
6691 NORMAL_RESOLUTION
));
6692 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
6693 later. fix_mov_imm_insn will try to determine a machine
6694 instruction (MOVZ, MOVN or ORR) for it and will issue an error
6695 message if the immediate cannot be moved by a single
6697 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6698 inst
.base
.operands
[i
].skip
= 1;
6702 case AARCH64_OPND_SIMD_IMM
:
6703 case AARCH64_OPND_SIMD_IMM_SFT
:
6704 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
6706 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6708 /* need_libopcodes_p */ 1,
6711 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
6712 shift, we don't check it here; we leave the checking to
6713 the libopcodes (operand_general_constraint_met_p). By
6714 doing this, we achieve better diagnostics. */
6715 if (skip_past_comma (&str
)
6716 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
6718 if (!info
->shifter
.operator_present
6719 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
6721 /* Default to LSL if not present. Libopcodes prefers shifter
6722 kind to be explicit. */
6723 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6724 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6728 case AARCH64_OPND_FPIMM
:
6729 case AARCH64_OPND_SIMD_FPIMM
:
6730 case AARCH64_OPND_SVE_FPIMM8
:
6735 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6736 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
6737 || !aarch64_imm_float_p (qfloat
))
6740 set_fatal_syntax_error (_("invalid floating-point"
6744 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
6745 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6749 case AARCH64_OPND_SVE_I1_HALF_ONE
:
6750 case AARCH64_OPND_SVE_I1_HALF_TWO
:
6751 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
6756 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
6757 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
6760 set_fatal_syntax_error (_("invalid floating-point"
6764 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6765 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6769 case AARCH64_OPND_LIMM
:
6770 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6771 SHIFTED_LOGIC_IMM
));
6772 if (info
->shifter
.operator_present
)
6774 set_fatal_syntax_error
6775 (_("shift not allowed for bitmask immediate"));
6778 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6780 /* need_libopcodes_p */ 1,
6784 case AARCH64_OPND_AIMM
:
6785 if (opcode
->op
== OP_ADD
)
6786 /* ADD may have relocation types. */
6787 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6788 SHIFTED_ARITH_IMM
));
6790 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6791 SHIFTED_ARITH_IMM
));
6792 switch (inst
.reloc
.type
)
6794 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6795 info
->shifter
.amount
= 12;
6797 case BFD_RELOC_UNUSED
:
6798 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6799 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6800 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6801 inst
.reloc
.pc_rel
= 0;
6806 info
->imm
.value
= 0;
6807 if (!info
->shifter
.operator_present
)
6809 /* Default to LSL if not present. Libopcodes prefers shifter
6810 kind to be explicit. */
6811 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6812 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6816 case AARCH64_OPND_HALF
:
6818 /* #<imm16> or relocation. */
6819 int internal_fixup_p
;
6820 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6821 if (internal_fixup_p
)
6822 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6823 skip_whitespace (str
);
6824 if (skip_past_comma (&str
))
6826 /* {, LSL #<shift>} */
6827 if (! aarch64_gas_internal_fixup_p ())
6829 set_fatal_syntax_error (_("can't mix relocation modifier "
6830 "with explicit shift"));
6833 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6836 inst
.base
.operands
[i
].shifter
.amount
= 0;
6837 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6838 inst
.base
.operands
[i
].imm
.value
= 0;
6839 if (! process_movw_reloc_info ())
6844 case AARCH64_OPND_EXCEPTION
:
6845 case AARCH64_OPND_UNDEFINED
:
6846 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6848 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6850 /* need_libopcodes_p */ 0,
6854 case AARCH64_OPND_NZCV
:
6856 const asm_nzcv
*nzcv
= str_hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6860 info
->imm
.value
= nzcv
->value
;
6863 po_imm_or_fail (0, 15);
6864 info
->imm
.value
= val
;
6868 case AARCH64_OPND_COND
:
6869 case AARCH64_OPND_COND1
:
6874 while (ISALPHA (*str
));
6875 info
->cond
= str_hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6876 if (info
->cond
== NULL
)
6878 set_syntax_error (_("invalid condition"));
6881 else if (operands
[i
] == AARCH64_OPND_COND1
6882 && (info
->cond
->value
& 0xe) == 0xe)
6884 /* Do not allow AL or NV. */
6885 set_default_error ();
6891 case AARCH64_OPND_ADDR_ADRP
:
6892 po_misc_or_fail (parse_adrp (&str
));
6893 /* Clear the value as operand needs to be relocated. */
6894 info
->imm
.value
= 0;
6897 case AARCH64_OPND_ADDR_PCREL14
:
6898 case AARCH64_OPND_ADDR_PCREL19
:
6899 case AARCH64_OPND_ADDR_PCREL21
:
6900 case AARCH64_OPND_ADDR_PCREL26
:
6901 po_misc_or_fail (parse_address (&str
, info
));
6902 if (!info
->addr
.pcrel
)
6904 set_syntax_error (_("invalid pc-relative address"));
6907 if (inst
.gen_lit_pool
6908 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6910 /* Only permit "=value" in the literal load instructions.
6911 The literal will be generated by programmer_friendly_fixup. */
6912 set_syntax_error (_("invalid use of \"=immediate\""));
6915 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6917 set_syntax_error (_("unrecognized relocation suffix"));
6920 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6922 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6923 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6927 info
->imm
.value
= 0;
6928 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6929 switch (opcode
->iclass
)
6933 /* e.g. CBZ or B.COND */
6934 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6935 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6939 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6940 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6944 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6946 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6947 : BFD_RELOC_AARCH64_JUMP26
;
6950 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6951 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6954 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6955 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6961 inst
.reloc
.pc_rel
= 1;
6965 case AARCH64_OPND_ADDR_SIMPLE
:
6966 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6968 /* [<Xn|SP>{, #<simm>}] */
6970 /* First use the normal address-parsing routines, to get
6971 the usual syntax errors. */
6972 po_misc_or_fail (parse_address (&str
, info
));
6973 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6974 || !info
->addr
.preind
|| info
->addr
.postind
6975 || info
->addr
.writeback
)
6977 set_syntax_error (_("invalid addressing mode"));
6981 /* Then retry, matching the specific syntax of these addresses. */
6983 po_char_or_fail ('[');
6984 po_reg_or_fail (REG_TYPE_R64_SP
);
6985 /* Accept optional ", #0". */
6986 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6987 && skip_past_char (&str
, ','))
6989 skip_past_char (&str
, '#');
6990 if (! skip_past_char (&str
, '0'))
6992 set_fatal_syntax_error
6993 (_("the optional immediate offset can only be 0"));
6997 po_char_or_fail (']');
7001 case AARCH64_OPND_ADDR_REGOFF
:
7002 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
7003 po_misc_or_fail (parse_address (&str
, info
));
7005 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
7006 || !info
->addr
.preind
|| info
->addr
.postind
7007 || info
->addr
.writeback
)
7009 set_syntax_error (_("invalid addressing mode"));
7012 if (!info
->shifter
.operator_present
)
7014 /* Default to LSL if not present. Libopcodes prefers shifter
7015 kind to be explicit. */
7016 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
7017 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7019 /* Qualifier to be deduced by libopcodes. */
7022 case AARCH64_OPND_ADDR_SIMM7
:
7023 po_misc_or_fail (parse_address (&str
, info
));
7024 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7025 || (!info
->addr
.preind
&& !info
->addr
.postind
))
7027 set_syntax_error (_("invalid addressing mode"));
7030 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7032 set_syntax_error (_("relocation not allowed"));
7035 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7037 /* need_libopcodes_p */ 1,
7041 case AARCH64_OPND_ADDR_SIMM9
:
7042 case AARCH64_OPND_ADDR_SIMM9_2
:
7043 case AARCH64_OPND_ADDR_SIMM11
:
7044 case AARCH64_OPND_ADDR_SIMM13
:
7045 po_misc_or_fail (parse_address (&str
, info
));
7046 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7047 || (!info
->addr
.preind
&& !info
->addr
.postind
)
7048 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
7049 && info
->addr
.writeback
))
7051 set_syntax_error (_("invalid addressing mode"));
7054 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7056 set_syntax_error (_("relocation not allowed"));
7059 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7061 /* need_libopcodes_p */ 1,
7065 case AARCH64_OPND_ADDR_SIMM10
:
7066 case AARCH64_OPND_ADDR_OFFSET
:
7067 po_misc_or_fail (parse_address (&str
, info
));
7068 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7069 || !info
->addr
.preind
|| info
->addr
.postind
)
7071 set_syntax_error (_("invalid addressing mode"));
7074 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7076 set_syntax_error (_("relocation not allowed"));
7079 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
7081 /* need_libopcodes_p */ 1,
7085 case AARCH64_OPND_ADDR_UIMM12
:
7086 po_misc_or_fail (parse_address (&str
, info
));
7087 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7088 || !info
->addr
.preind
|| info
->addr
.writeback
)
7090 set_syntax_error (_("invalid addressing mode"));
7093 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7094 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
7095 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
7097 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
7099 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
7101 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
7103 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
7104 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
7105 /* Leave qualifier to be determined by libopcodes. */
7108 case AARCH64_OPND_SIMD_ADDR_POST
:
7109 /* [<Xn|SP>], <Xm|#<amount>> */
7110 po_misc_or_fail (parse_address (&str
, info
));
7111 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
7113 set_syntax_error (_("invalid addressing mode"));
7116 if (!info
->addr
.offset
.is_reg
)
7118 if (inst
.reloc
.exp
.X_op
== O_constant
)
7119 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7122 set_fatal_syntax_error
7123 (_("writeback value must be an immediate constant"));
7130 case AARCH64_OPND_SME_SM_ZA
:
7132 if ((val
= parse_sme_sm_za (&str
)) == PARSE_FAIL
)
7134 set_syntax_error (_("unknown or missing PSTATE field name"));
7137 info
->reg
.regno
= val
;
7140 case AARCH64_OPND_SME_PnT_Wm_imm
:
7141 /* <Pn>.<T>[<Wm>, #<imm>] */
7145 val
= parse_sme_pred_reg_with_index (&str
,
7149 if (val
== PARSE_FAIL
)
7152 info
->za_tile_vector
.regno
= val
;
7153 info
->za_tile_vector
.index
.regno
= index_base_reg
;
7154 info
->za_tile_vector
.index
.imm
= imm
;
7155 info
->qualifier
= qualifier
;
7159 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
7160 case AARCH64_OPND_SVE_ADDR_RI_S4x32
:
7161 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
7162 case AARCH64_OPND_SME_ADDR_RI_U4xVL
:
7163 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
7164 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
7165 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
7166 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
7167 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
7168 case AARCH64_OPND_SVE_ADDR_RI_U6
:
7169 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
7170 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
7171 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
7172 /* [X<n>{, #imm, MUL VL}]
7174 but recognizing SVE registers. */
7175 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7176 &offset_qualifier
));
7177 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
7179 set_syntax_error (_("invalid addressing mode"));
7183 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
7184 || !info
->addr
.preind
|| info
->addr
.writeback
)
7186 set_syntax_error (_("invalid addressing mode"));
7189 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
7190 || inst
.reloc
.exp
.X_op
!= O_constant
)
7192 /* Make sure this has priority over
7193 "invalid addressing mode". */
7194 set_fatal_syntax_error (_("constant offset required"));
7197 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
7200 case AARCH64_OPND_SVE_ADDR_R
:
7201 /* [<Xn|SP>{, <R><m>}]
7202 but recognizing SVE registers. */
7203 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7204 &offset_qualifier
));
7205 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
7207 offset_qualifier
= AARCH64_OPND_QLF_X
;
7208 info
->addr
.offset
.is_reg
= 1;
7209 info
->addr
.offset
.regno
= 31;
7211 else if (base_qualifier
!= AARCH64_OPND_QLF_X
7212 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7214 set_syntax_error (_("invalid addressing mode"));
7219 case AARCH64_OPND_SVE_ADDR_RR
:
7220 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
7221 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
7222 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
7223 case AARCH64_OPND_SVE_ADDR_RR_LSL4
:
7224 case AARCH64_OPND_SVE_ADDR_RX
:
7225 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
7226 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
7227 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
7228 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
7229 but recognizing SVE registers. */
7230 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7231 &offset_qualifier
));
7232 if (base_qualifier
!= AARCH64_OPND_QLF_X
7233 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7235 set_syntax_error (_("invalid addressing mode"));
7240 case AARCH64_OPND_SVE_ADDR_RZ
:
7241 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
7242 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
7243 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
7244 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
7245 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
7246 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
7247 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
7248 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
7249 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
7250 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
7251 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
7252 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
7253 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
7254 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7255 &offset_qualifier
));
7256 if (base_qualifier
!= AARCH64_OPND_QLF_X
7257 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
7258 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
7260 set_syntax_error (_("invalid addressing mode"));
7263 info
->qualifier
= offset_qualifier
;
7266 case AARCH64_OPND_SVE_ADDR_ZX
:
7267 /* [Zn.<T>{, <Xm>}]. */
7268 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7269 &offset_qualifier
));
7271 base_qualifier either S_S or S_D
7272 offset_qualifier must be X
7274 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7275 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7276 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
7278 set_syntax_error (_("invalid addressing mode"));
7281 info
->qualifier
= base_qualifier
;
7282 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
7283 || !info
->addr
.preind
|| info
->addr
.writeback
7284 || info
->shifter
.operator_present
!= 0)
7286 set_syntax_error (_("invalid addressing mode"));
7289 info
->shifter
.kind
= AARCH64_MOD_LSL
;
7293 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
7294 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
7295 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
7296 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
7297 /* [Z<n>.<T>{, #imm}] */
7298 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7299 &offset_qualifier
));
7300 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
7301 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7303 set_syntax_error (_("invalid addressing mode"));
7306 info
->qualifier
= base_qualifier
;
7309 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
7310 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
7311 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
7312 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
7313 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
7317 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
7319 here since we get better error messages by leaving it to
7320 the qualifier checking routines. */
7321 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
7322 &offset_qualifier
));
7323 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
7324 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
7325 || offset_qualifier
!= base_qualifier
)
7327 set_syntax_error (_("invalid addressing mode"));
7330 info
->qualifier
= base_qualifier
;
7333 case AARCH64_OPND_SYSREG
:
7335 uint32_t sysreg_flags
;
7336 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
7337 &sysreg_flags
)) == PARSE_FAIL
)
7339 set_syntax_error (_("unknown or missing system register name"));
7342 inst
.base
.operands
[i
].sysreg
.value
= val
;
7343 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7347 case AARCH64_OPND_PSTATEFIELD
:
7349 uint32_t sysreg_flags
;
7350 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1,
7351 &sysreg_flags
)) == PARSE_FAIL
)
7353 set_syntax_error (_("unknown or missing PSTATE field name"));
7356 inst
.base
.operands
[i
].pstatefield
= val
;
7357 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
7361 case AARCH64_OPND_SYSREG_IC
:
7362 inst
.base
.operands
[i
].sysins_op
=
7363 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
7366 case AARCH64_OPND_SYSREG_DC
:
7367 inst
.base
.operands
[i
].sysins_op
=
7368 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
7371 case AARCH64_OPND_SYSREG_AT
:
7372 inst
.base
.operands
[i
].sysins_op
=
7373 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
7376 case AARCH64_OPND_SYSREG_SR
:
7377 inst
.base
.operands
[i
].sysins_op
=
7378 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
7381 case AARCH64_OPND_SYSREG_TLBI
:
7382 inst
.base
.operands
[i
].sysins_op
=
7383 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
7385 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
7387 set_fatal_syntax_error ( _("unknown or missing operation name"));
7392 case AARCH64_OPND_BARRIER
:
7393 case AARCH64_OPND_BARRIER_ISB
:
7394 val
= parse_barrier (&str
);
7395 if (val
!= PARSE_FAIL
7396 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
7398 /* ISB only accepts options name 'sy'. */
7400 (_("the specified option is not accepted in ISB"));
7401 /* Turn off backtrack as this optional operand is present. */
7405 if (val
!= PARSE_FAIL
7406 && operands
[i
] == AARCH64_OPND_BARRIER
)
7408 /* Regular barriers accept options CRm (C0-C15).
7409 DSB nXS barrier variant accepts values > 15. */
7410 if (val
< 0 || val
> 15)
7412 set_syntax_error (_("the specified option is not accepted in DSB"));
7416 /* This is an extension to accept a 0..15 immediate. */
7417 if (val
== PARSE_FAIL
)
7418 po_imm_or_fail (0, 15);
7419 info
->barrier
= aarch64_barrier_options
+ val
;
7422 case AARCH64_OPND_BARRIER_DSB_NXS
:
7423 val
= parse_barrier (&str
);
7424 if (val
!= PARSE_FAIL
)
7426 /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
7427 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7429 set_syntax_error (_("the specified option is not accepted in DSB"));
7430 /* Turn off backtrack as this optional operand is present. */
7437 /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
7438 possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
7439 if (! parse_constant_immediate (&str
, &val
, imm_reg_type
))
7441 if (!(val
== 16 || val
== 20 || val
== 24 || val
== 28))
7443 set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
7447 /* Option index is encoded as 2-bit value in val<3:2>. */
7448 val
= (val
>> 2) - 4;
7449 info
->barrier
= aarch64_barrier_dsb_nxs_options
+ val
;
7452 case AARCH64_OPND_PRFOP
:
7453 val
= parse_pldop (&str
);
7454 /* This is an extension to accept a 0..31 immediate. */
7455 if (val
== PARSE_FAIL
)
7456 po_imm_or_fail (0, 31);
7457 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
7460 case AARCH64_OPND_BARRIER_PSB
:
7461 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
7462 if (val
== PARSE_FAIL
)
7466 case AARCH64_OPND_BTI_TARGET
:
7467 val
= parse_bti_operand (&str
, &(info
->hint_option
));
7468 if (val
== PARSE_FAIL
)
7472 case AARCH64_OPND_SME_ZAda_2b
:
7473 case AARCH64_OPND_SME_ZAda_3b
:
7474 val
= parse_sme_zada_operand (&str
, &qualifier
);
7475 if (val
== PARSE_FAIL
)
7477 info
->reg
.regno
= val
;
7478 info
->qualifier
= qualifier
;
7481 case AARCH64_OPND_SME_ZA_HV_idx_src
:
7482 case AARCH64_OPND_SME_ZA_HV_idx_dest
:
7483 case AARCH64_OPND_SME_ZA_HV_idx_ldstr
:
7485 enum sme_hv_slice slice_indicator
;
7486 int vector_select_register
;
7489 if (operands
[i
] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
)
7490 val
= parse_sme_za_hv_tiles_operand_with_braces (&str
,
7492 &vector_select_register
,
7496 val
= parse_sme_za_hv_tiles_operand (&str
, &slice_indicator
,
7497 &vector_select_register
,
7500 if (val
== PARSE_FAIL
)
7502 info
->za_tile_vector
.regno
= val
;
7503 info
->za_tile_vector
.index
.regno
= vector_select_register
;
7504 info
->za_tile_vector
.index
.imm
= imm
;
7505 info
->za_tile_vector
.v
= slice_indicator
;
7506 info
->qualifier
= qualifier
;
7510 case AARCH64_OPND_SME_list_of_64bit_tiles
:
7511 val
= parse_sme_list_of_64bit_tiles (&str
);
7512 if (val
== PARSE_FAIL
)
7514 info
->imm
.value
= val
;
7517 case AARCH64_OPND_SME_ZA_array
:
7520 val
= parse_sme_za_array (&str
, &imm
);
7521 if (val
== PARSE_FAIL
)
7523 info
->za_tile_vector
.index
.regno
= val
;
7524 info
->za_tile_vector
.index
.imm
= imm
;
7528 case AARCH64_OPND_MOPS_ADDR_Rd
:
7529 case AARCH64_OPND_MOPS_ADDR_Rs
:
7530 po_char_or_fail ('[');
7531 if (!parse_x0_to_x30 (&str
, info
))
7533 po_char_or_fail (']');
7534 po_char_or_fail ('!');
7537 case AARCH64_OPND_MOPS_WB_Rn
:
7538 if (!parse_x0_to_x30 (&str
, info
))
7540 po_char_or_fail ('!');
7544 as_fatal (_("unhandled operand code %d"), operands
[i
]);
7547 /* If we get here, this operand was successfully parsed. */
7548 inst
.base
.operands
[i
].present
= 1;
7552 /* The parse routine should already have set the error, but in case
7553 not, set a default one here. */
7555 set_default_error ();
7557 if (! backtrack_pos
)
7558 goto parse_operands_return
;
7561 /* We reach here because this operand is marked as optional, and
7562 either no operand was supplied or the operand was supplied but it
7563 was syntactically incorrect. In the latter case we report an
7564 error. In the former case we perform a few more checks before
7565 dropping through to the code to insert the default operand. */
7567 char *tmp
= backtrack_pos
;
7568 char endchar
= END_OF_INSN
;
7570 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
7572 skip_past_char (&tmp
, ',');
7574 if (*tmp
!= endchar
)
7575 /* The user has supplied an operand in the wrong format. */
7576 goto parse_operands_return
;
7578 /* Make sure there is not a comma before the optional operand.
7579 For example the fifth operand of 'sys' is optional:
7581 sys #0,c0,c0,#0, <--- wrong
7582 sys #0,c0,c0,#0 <--- correct. */
7583 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
7585 set_fatal_syntax_error
7586 (_("unexpected comma before the omitted optional operand"));
7587 goto parse_operands_return
;
7591 /* Reaching here means we are dealing with an optional operand that is
7592 omitted from the assembly line. */
7593 gas_assert (optional_operand_p (opcode
, i
));
7595 process_omitted_operand (operands
[i
], opcode
, i
, info
);
7597 /* Try again, skipping the optional operand at backtrack_pos. */
7598 str
= backtrack_pos
;
7601 /* Clear any error record after the omitted optional operand has been
7602 successfully handled. */
7606 /* Check if we have parsed all the operands. */
7607 if (*str
!= '\0' && ! error_p ())
7609 /* Set I to the index of the last present operand; this is
7610 for the purpose of diagnostics. */
7611 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
7613 set_fatal_syntax_error
7614 (_("unexpected characters following instruction"));
7617 parse_operands_return
:
7621 DEBUG_TRACE ("parsing FAIL: %s - %s",
7622 operand_mismatch_kind_names
[get_error_kind ()],
7623 get_error_message ());
7624 /* Record the operand error properly; this is useful when there
7625 are multiple instruction templates for a mnemonic name, so that
7626 later on, we can select the error that most closely describes
7628 record_operand_error (opcode
, i
, get_error_kind (),
7629 get_error_message ());
7634 DEBUG_TRACE ("parsing SUCCESS");
7639 /* It does some fix-up to provide some programmer friendly feature while
7640 keeping the libopcodes happy, i.e. libopcodes only accepts
7641 the preferred architectural syntax.
7642 Return FALSE if there is any failure; otherwise return TRUE. */
7645 programmer_friendly_fixup (aarch64_instruction
*instr
)
7647 aarch64_inst
*base
= &instr
->base
;
7648 const aarch64_opcode
*opcode
= base
->opcode
;
7649 enum aarch64_op op
= opcode
->op
;
7650 aarch64_opnd_info
*operands
= base
->operands
;
7652 DEBUG_TRACE ("enter");
7654 switch (opcode
->iclass
)
7657 /* TBNZ Xn|Wn, #uimm6, label
7658 Test and Branch Not Zero: conditionally jumps to label if bit number
7659 uimm6 in register Xn is not zero. The bit number implies the width of
7660 the register, which may be written and should be disassembled as Wn if
7661 uimm is less than 32. */
7662 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
7664 if (operands
[1].imm
.value
>= 32)
7666 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
7670 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
7674 /* LDR Wt, label | =value
7675 As a convenience assemblers will typically permit the notation
7676 "=value" in conjunction with the pc-relative literal load instructions
7677 to automatically place an immediate value or symbolic address in a
7678 nearby literal pool and generate a hidden label which references it.
7679 ISREG has been set to 0 in the case of =value. */
7680 if (instr
->gen_lit_pool
7681 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
7683 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
7684 if (op
== OP_LDRSW_LIT
)
7686 if (instr
->reloc
.exp
.X_op
!= O_constant
7687 && instr
->reloc
.exp
.X_op
!= O_big
7688 && instr
->reloc
.exp
.X_op
!= O_symbol
)
7690 record_operand_error (opcode
, 1,
7691 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
7692 _("constant expression expected"));
7695 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
7697 record_operand_error (opcode
, 1,
7698 AARCH64_OPDE_OTHER_ERROR
,
7699 _("literal pool insertion failed"));
7707 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
7708 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
7709 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
7710 A programmer-friendly assembler should accept a destination Xd in
7711 place of Wd, however that is not the preferred form for disassembly.
7713 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
7714 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
7715 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
7716 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
7721 /* In the 64-bit form, the final register operand is written as Wm
7722 for all but the (possibly omitted) UXTX/LSL and SXTX
7724 As a programmer-friendly assembler, we accept e.g.
7725 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
7726 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
7727 int idx
= aarch64_operand_index (opcode
->operands
,
7728 AARCH64_OPND_Rm_EXT
);
7729 gas_assert (idx
== 1 || idx
== 2);
7730 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
7731 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
7732 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
7733 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
7734 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
7735 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
7743 DEBUG_TRACE ("exit with SUCCESS");
7747 /* Check for loads and stores that will cause unpredictable behavior. */
7750 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
7752 aarch64_inst
*base
= &instr
->base
;
7753 const aarch64_opcode
*opcode
= base
->opcode
;
7754 const aarch64_opnd_info
*opnds
= base
->operands
;
7755 switch (opcode
->iclass
)
7762 /* Loading/storing the base register is unpredictable if writeback. */
7763 if ((aarch64_get_operand_class (opnds
[0].type
)
7764 == AARCH64_OPND_CLASS_INT_REG
)
7765 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
7766 && opnds
[1].addr
.base_regno
!= REG_SP
7767 /* Exempt STG/STZG/ST2G/STZ2G. */
7768 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
7769 && opnds
[1].addr
.writeback
)
7770 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7774 case ldstnapair_offs
:
7775 case ldstpair_indexed
:
7776 /* Loading/storing the base register is unpredictable if writeback. */
7777 if ((aarch64_get_operand_class (opnds
[0].type
)
7778 == AARCH64_OPND_CLASS_INT_REG
)
7779 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
7780 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
7781 && opnds
[2].addr
.base_regno
!= REG_SP
7783 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
7784 && opnds
[2].addr
.writeback
)
7785 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
7786 /* Load operations must load different registers. */
7787 if ((opcode
->opcode
& (1 << 22))
7788 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7789 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7793 if ((aarch64_get_operand_class (opnds
[0].type
)
7794 == AARCH64_OPND_CLASS_INT_REG
)
7795 && (aarch64_get_operand_class (opnds
[1].type
)
7796 == AARCH64_OPND_CLASS_INT_REG
))
7798 if ((opcode
->opcode
& (1 << 22)))
7800 /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
7801 if ((opcode
->opcode
& (1 << 21))
7802 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7803 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
7807 /* Store-Exclusive is unpredictable if Rt == Rs. */
7808 if (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
7810 (_("unpredictable: identical transfer and status registers"
7813 if (opnds
[0].reg
.regno
== opnds
[2].reg
.regno
)
7815 if (!(opcode
->opcode
& (1 << 21)))
7816 /* Store-Exclusive is unpredictable if Rn == Rs. */
7818 (_("unpredictable: identical base and status registers"
7821 /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
7823 (_("unpredictable: "
7824 "identical transfer and status registers"
7828 /* Store-Exclusive pair is unpredictable if Rn == Rs. */
7829 if ((opcode
->opcode
& (1 << 21))
7830 && opnds
[0].reg
.regno
== opnds
[3].reg
.regno
7831 && opnds
[3].reg
.regno
!= REG_SP
)
7832 as_warn (_("unpredictable: identical base and status registers"
7844 force_automatic_sequence_close (void)
7846 struct aarch64_segment_info_type
*tc_seg_info
;
7848 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7849 if (tc_seg_info
->insn_sequence
.instr
)
7851 as_warn_where (tc_seg_info
->last_file
, tc_seg_info
->last_line
,
7852 _("previous `%s' sequence has not been closed"),
7853 tc_seg_info
->insn_sequence
.instr
->opcode
->name
);
7854 init_insn_sequence (NULL
, &tc_seg_info
->insn_sequence
);
7858 /* A wrapper function to interface with libopcodes on encoding and
7859 record the error message if there is any.
7861 Return TRUE on success; otherwise return FALSE. */
7864 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
7867 aarch64_operand_error error_info
;
7868 memset (&error_info
, '\0', sizeof (error_info
));
7869 error_info
.kind
= AARCH64_OPDE_NIL
;
7870 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
7871 && !error_info
.non_fatal
)
7874 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
7875 record_operand_error_info (opcode
, &error_info
);
7876 return error_info
.non_fatal
;
7879 #ifdef DEBUG_AARCH64
7881 dump_opcode_operands (const aarch64_opcode
*opcode
)
7884 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
7886 aarch64_verbose ("\t\t opnd%d: %s", i
,
7887 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
7888 ? aarch64_get_operand_name (opcode
->operands
[i
])
7889 : aarch64_get_operand_desc (opcode
->operands
[i
]));
7893 #endif /* DEBUG_AARCH64 */
7895 /* This is the guts of the machine-dependent assembler. STR points to a
7896 machine dependent instruction. This function is supposed to emit
7897 the frags/bytes it assembles to. */
7900 md_assemble (char *str
)
7902 templates
*template;
7903 const aarch64_opcode
*opcode
;
7904 struct aarch64_segment_info_type
*tc_seg_info
;
7905 aarch64_inst
*inst_base
;
7906 unsigned saved_cond
;
7908 /* Align the previous label if needed. */
7909 if (last_label_seen
!= NULL
)
7911 symbol_set_frag (last_label_seen
, frag_now
);
7912 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
7913 S_SET_SEGMENT (last_label_seen
, now_seg
);
7916 /* Update the current insn_sequence from the segment. */
7917 tc_seg_info
= &seg_info (now_seg
)->tc_segment_info_data
;
7918 insn_sequence
= &tc_seg_info
->insn_sequence
;
7919 tc_seg_info
->last_file
= as_where (&tc_seg_info
->last_line
);
7921 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7923 DEBUG_TRACE ("\n\n");
7924 DEBUG_TRACE ("==============================");
7925 DEBUG_TRACE ("Enter md_assemble with %s", str
);
7927 /* Scan up to the end of the mnemonic, which must end in whitespace,
7928 '.', or end of string. */
7931 for (; is_part_of_name (*p
); p
++)
7932 if (*p
== '.' && !dot
)
7937 as_bad (_("unknown mnemonic -- `%s'"), str
);
7941 if (!dot
&& create_register_alias (str
, p
))
7944 template = opcode_lookup (str
, dot
, p
);
7947 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
7952 skip_whitespace (p
);
7955 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
7956 get_mnemonic_name (str
), str
);
7960 init_operand_error_report ();
7962 /* Sections are assumed to start aligned. In executable section, there is no
7963 MAP_DATA symbol pending. So we only align the address during
7964 MAP_DATA --> MAP_INSN transition.
7965 For other sections, this is not guaranteed. */
7966 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7967 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7968 frag_align_code (2, 0);
7970 saved_cond
= inst
.cond
;
7971 reset_aarch64_instruction (&inst
);
7972 inst
.cond
= saved_cond
;
7974 /* Iterate through all opcode entries with the same mnemonic name. */
7977 opcode
= template->opcode
;
7979 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7980 #ifdef DEBUG_AARCH64
7982 dump_opcode_operands (opcode
);
7983 #endif /* DEBUG_AARCH64 */
7985 mapping_state (MAP_INSN
);
7987 inst_base
= &inst
.base
;
7988 inst_base
->opcode
= opcode
;
7990 /* Truly conditionally executed instructions, e.g. b.cond. */
7991 if (opcode
->flags
& F_COND
)
7993 gas_assert (inst
.cond
!= COND_ALWAYS
);
7994 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7995 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7997 else if (inst
.cond
!= COND_ALWAYS
)
7999 /* It shouldn't arrive here, where the assembly looks like a
8000 conditional instruction but the found opcode is unconditional. */
8005 if (parse_operands (p
, opcode
)
8006 && programmer_friendly_fixup (&inst
)
8007 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
8009 /* Check that this instruction is supported for this CPU. */
8010 if (!opcode
->avariant
8011 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
8013 as_bad (_("selected processor does not support `%s'"), str
);
8017 warn_unpredictable_ldst (&inst
, str
);
8019 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
8020 || !inst
.reloc
.need_libopcodes_p
)
8024 /* If there is relocation generated for the instruction,
8025 store the instruction information for the future fix-up. */
8026 struct aarch64_inst
*copy
;
8027 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
8028 copy
= XNEW (struct aarch64_inst
);
8029 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
8033 /* Issue non-fatal messages if any. */
8034 output_operand_error_report (str
, true);
8038 template = template->next
;
8039 if (template != NULL
)
8041 reset_aarch64_instruction (&inst
);
8042 inst
.cond
= saved_cond
;
8045 while (template != NULL
);
8047 /* Issue the error messages if any. */
8048 output_operand_error_report (str
, false);
8051 /* Various frobbings of labels and their addresses. */
8054 aarch64_start_line_hook (void)
8056 last_label_seen
= NULL
;
8060 aarch64_frob_label (symbolS
* sym
)
8062 last_label_seen
= sym
;
8064 dwarf2_emit_label (sym
);
8068 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
8070 /* Check to see if we have a block to close. */
8071 force_automatic_sequence_close ();
8075 aarch64_data_in_code (void)
8077 if (startswith (input_line_pointer
+ 1, "data:"))
8079 *input_line_pointer
= '/';
8080 input_line_pointer
+= 5;
8081 *input_line_pointer
= 0;
8089 aarch64_canonicalize_symbol_name (char *name
)
8093 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
8094 *(name
+ len
- 5) = 0;
8099 /* Table of all register names defined by default. The user can
8100 define additional names with .req. Note that all register names
8101 should appear in both upper and lowercase variants. Some registers
8102 also have mixed-case names. */
8104 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
8105 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
8106 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8107 #define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t)
8108 #define REGSET16(p,t) \
8109 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8110 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8111 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8112 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8113 #define REGSET16S(p,s,t) \
8114 REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \
8115 REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \
8116 REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \
8117 REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t)
8118 #define REGSET31(p,t) \
8120 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
8121 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
8122 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
8123 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
8124 #define REGSET(p,t) \
8125 REGSET31(p,t), REGNUM(p,31,t)
8127 /* These go into aarch64_reg_hsh hash-table. */
8128 static const reg_entry reg_names
[] = {
8129 /* Integer registers. */
8130 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
8131 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
8133 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
8134 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
8135 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
8136 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
8137 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
8138 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
8140 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
8141 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
8143 /* Floating-point single precision registers. */
8144 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
8146 /* Floating-point double precision registers. */
8147 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
8149 /* Floating-point half precision registers. */
8150 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
8152 /* Floating-point byte precision registers. */
8153 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
8155 /* Floating-point quad precision registers. */
8156 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
8158 /* FP/SIMD registers. */
8159 REGSET (v
, VN
), REGSET (V
, VN
),
8161 /* SVE vector registers. */
8162 REGSET (z
, ZN
), REGSET (Z
, ZN
),
8164 /* SVE predicate registers. */
8165 REGSET16 (p
, PN
), REGSET16 (P
, PN
),
8167 /* SME ZA tile registers. */
8168 REGSET16 (za
, ZA
), REGSET16 (ZA
, ZA
),
8170 /* SME ZA tile registers (horizontal slice). */
8171 REGSET16S (za
, h
, ZAH
), REGSET16S (ZA
, H
, ZAH
),
8173 /* SME ZA tile registers (vertical slice). */
8174 REGSET16S (za
, v
, ZAV
), REGSET16S (ZA
, V
, ZAV
)
8192 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
8193 static const asm_nzcv nzcv_names
[] = {
8194 {"nzcv", B (n
, z
, c
, v
)},
8195 {"nzcV", B (n
, z
, c
, V
)},
8196 {"nzCv", B (n
, z
, C
, v
)},
8197 {"nzCV", B (n
, z
, C
, V
)},
8198 {"nZcv", B (n
, Z
, c
, v
)},
8199 {"nZcV", B (n
, Z
, c
, V
)},
8200 {"nZCv", B (n
, Z
, C
, v
)},
8201 {"nZCV", B (n
, Z
, C
, V
)},
8202 {"Nzcv", B (N
, z
, c
, v
)},
8203 {"NzcV", B (N
, z
, c
, V
)},
8204 {"NzCv", B (N
, z
, C
, v
)},
8205 {"NzCV", B (N
, z
, C
, V
)},
8206 {"NZcv", B (N
, Z
, c
, v
)},
8207 {"NZcV", B (N
, Z
, c
, V
)},
8208 {"NZCv", B (N
, Z
, C
, v
)},
8209 {"NZCV", B (N
, Z
, C
, V
)}
8222 /* MD interface: bits in the object file. */
8224 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
8225 for use in the a.out file, and stores them in the array pointed to by buf.
8226 This knows about the endian-ness of the target machine and does
8227 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
8228 2 (short) and 4 (long) Floating numbers are put out as a series of
8229 LITTLENUMS (shorts, here at least). */
8232 md_number_to_chars (char *buf
, valueT val
, int n
)
8234 if (target_big_endian
)
8235 number_to_chars_bigendian (buf
, val
, n
);
8237 number_to_chars_littleendian (buf
, val
, n
);
8240 /* MD interface: Sections. */
8242 /* Estimate the size of a frag before relaxing. Assume everything fits in
8246 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
8252 /* Round up a section size to the appropriate boundary. */
8255 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
8260 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8261 of an rs_align_code fragment.
8263 Here we fill the frag with the appropriate info for padding the
8264 output stream. The resulting frag will consist of a fixed (fr_fix)
8265 and of a repeating (fr_var) part.
8267 The fixed content is always emitted before the repeating content and
8268 these two parts are used as follows in constructing the output:
8269 - the fixed part will be used to align to a valid instruction word
8270 boundary, in case that we start at a misaligned address; as no
8271 executable instruction can live at the misaligned location, we
8272 simply fill with zeros;
8273 - the variable part will be used to cover the remaining padding and
8274 we fill using the AArch64 NOP instruction.
8276 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
8277 enough storage space for up to 3 bytes for padding the back to a valid
8278 instruction alignment and exactly 4 bytes to store the NOP pattern. */
8281 aarch64_handle_align (fragS
* fragP
)
8283 /* NOP = d503201f */
8284 /* AArch64 instructions are always little-endian. */
8285 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
8287 int bytes
, fix
, noop_size
;
8290 if (fragP
->fr_type
!= rs_align_code
)
8293 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
8294 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
8297 gas_assert (fragP
->tc_frag_data
.recorded
);
8300 noop_size
= sizeof (aarch64_noop
);
8302 fix
= bytes
& (noop_size
- 1);
8306 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
8310 fragP
->fr_fix
+= fix
;
8314 memcpy (p
, aarch64_noop
, noop_size
);
8315 fragP
->fr_var
= noop_size
;
8318 /* Perform target specific initialisation of a frag.
8319 Note - despite the name this initialisation is not done when the frag
8320 is created, but only when its type is assigned. A frag can be created
8321 and used a long time before its type is set, so beware of assuming that
8322 this initialisation is performed first. */
8326 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
8327 int max_chars ATTRIBUTE_UNUSED
)
8331 #else /* OBJ_ELF is defined. */
8333 aarch64_init_frag (fragS
* fragP
, int max_chars
)
8335 /* Record a mapping symbol for alignment frags. We will delete this
8336 later if the alignment ends up empty. */
8337 if (!fragP
->tc_frag_data
.recorded
)
8338 fragP
->tc_frag_data
.recorded
= 1;
8340 /* PR 21809: Do not set a mapping state for debug sections
8341 - it just confuses other tools. */
8342 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
8345 switch (fragP
->fr_type
)
8349 mapping_state_2 (MAP_DATA
, max_chars
);
8352 /* PR 20364: We can get alignment frags in code sections,
8353 so do not just assume that we should use the MAP_DATA state. */
8354 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
8357 mapping_state_2 (MAP_INSN
, max_chars
);
8364 /* Initialize the DWARF-2 unwind information for this procedure. */
8367 tc_aarch64_frame_initial_instructions (void)
8369 cfi_add_CFA_def_cfa (REG_SP
, 0);
8371 #endif /* OBJ_ELF */
8373 /* Convert REGNAME to a DWARF-2 register number. */
8376 tc_aarch64_regname_to_dw2regnum (char *regname
)
8378 const reg_entry
*reg
= parse_reg (®name
);
8384 case REG_TYPE_SP_32
:
8385 case REG_TYPE_SP_64
:
8395 return reg
->number
+ 64;
8403 /* Implement DWARF2_ADDR_SIZE. */
8406 aarch64_dwarf2_addr_size (void)
8408 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8412 return bfd_arch_bits_per_address (stdoutput
) / 8;
8415 /* MD interface: Symbol and relocation handling. */
8417 /* Return the address within the segment that a PC-relative fixup is
8418 relative to. For AArch64 PC-relative fixups applied to instructions
8419 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
8422 md_pcrel_from_section (fixS
* fixP
, segT seg
)
8424 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8426 /* If this is pc-relative and we are going to emit a relocation
8427 then we just want to put out any pipeline compensation that the linker
8428 will need. Otherwise we want to use the calculated base. */
8430 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
8431 || aarch64_force_relocation (fixP
)))
8434 /* AArch64 should be consistent for all pc-relative relocations. */
8435 return base
+ AARCH64_PCREL_OFFSET
;
8438 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
8439 Otherwise we have no need to default values of symbols. */
8442 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
8445 if (name
[0] == '_' && name
[1] == 'G'
8446 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
8450 if (symbol_find (name
))
8451 as_bad (_("GOT already in the symbol table"));
8453 GOT_symbol
= symbol_new (name
, undefined_section
,
8454 &zero_address_frag
, 0);
8464 /* Return non-zero if the indicated VALUE has overflowed the maximum
8465 range expressible by a unsigned number with the indicated number of
8469 unsigned_overflow (valueT value
, unsigned bits
)
8472 if (bits
>= sizeof (valueT
) * 8)
8474 lim
= (valueT
) 1 << bits
;
8475 return (value
>= lim
);
8479 /* Return non-zero if the indicated VALUE has overflowed the maximum
8480 range expressible by an signed number with the indicated number of
8484 signed_overflow (offsetT value
, unsigned bits
)
8487 if (bits
>= sizeof (offsetT
) * 8)
8489 lim
= (offsetT
) 1 << (bits
- 1);
8490 return (value
< -lim
|| value
>= lim
);
8493 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
8494 unsigned immediate offset load/store instruction, try to encode it as
8495 an unscaled, 9-bit, signed immediate offset load/store instruction.
8496 Return TRUE if it is successful; otherwise return FALSE.
8498 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
8499 in response to the standard LDR/STR mnemonics when the immediate offset is
8500 unambiguous, i.e. when it is negative or unaligned. */
8503 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
8506 enum aarch64_op new_op
;
8507 const aarch64_opcode
*new_opcode
;
8509 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
8511 switch (instr
->opcode
->op
)
8513 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
8514 case OP_STRB_POS
: new_op
= OP_STURB
; break;
8515 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
8516 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
8517 case OP_STRH_POS
: new_op
= OP_STURH
; break;
8518 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
8519 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
8520 case OP_STR_POS
: new_op
= OP_STUR
; break;
8521 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
8522 case OP_STRF_POS
: new_op
= OP_STURV
; break;
8523 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
8524 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
8525 default: new_op
= OP_NIL
; break;
8528 if (new_op
== OP_NIL
)
8531 new_opcode
= aarch64_get_opcode (new_op
);
8532 gas_assert (new_opcode
!= NULL
);
8534 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
8535 instr
->opcode
->op
, new_opcode
->op
);
8537 aarch64_replace_opcode (instr
, new_opcode
);
8539 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
8540 qualifier matching may fail because the out-of-date qualifier will
8541 prevent the operand being updated with a new and correct qualifier. */
8542 idx
= aarch64_operand_index (instr
->opcode
->operands
,
8543 AARCH64_OPND_ADDR_SIMM9
);
8544 gas_assert (idx
== 1);
8545 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
8547 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
8549 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
8556 /* Called by fix_insn to fix a MOV immediate alias instruction.
8558 Operand for a generic move immediate instruction, which is an alias
8559 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
8560 a 32-bit/64-bit immediate value into general register. An assembler error
8561 shall result if the immediate cannot be created by a single one of these
8562 instructions. If there is a choice, then to ensure reversability an
8563 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
8566 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
8568 const aarch64_opcode
*opcode
;
8570 /* Need to check if the destination is SP/ZR. The check has to be done
8571 before any aarch64_replace_opcode. */
8572 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
8573 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
8575 instr
->operands
[1].imm
.value
= value
;
8576 instr
->operands
[1].skip
= 0;
8580 /* Try the MOVZ alias. */
8581 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
8582 aarch64_replace_opcode (instr
, opcode
);
8583 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8584 &instr
->value
, NULL
, NULL
, insn_sequence
))
8586 put_aarch64_insn (buf
, instr
->value
);
8589 /* Try the MOVK alias. */
8590 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
8591 aarch64_replace_opcode (instr
, opcode
);
8592 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8593 &instr
->value
, NULL
, NULL
, insn_sequence
))
8595 put_aarch64_insn (buf
, instr
->value
);
8600 if (try_mov_bitmask_p
)
8602 /* Try the ORR alias. */
8603 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
8604 aarch64_replace_opcode (instr
, opcode
);
8605 if (aarch64_opcode_encode (instr
->opcode
, instr
,
8606 &instr
->value
, NULL
, NULL
, insn_sequence
))
8608 put_aarch64_insn (buf
, instr
->value
);
8613 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8614 _("immediate cannot be moved by a single instruction"));
8617 /* An instruction operand which is immediate related may have symbol used
8618 in the assembly, e.g.
8621 .set u32, 0x00ffff00
8623 At the time when the assembly instruction is parsed, a referenced symbol,
8624 like 'u32' in the above example may not have been seen; a fixS is created
8625 in such a case and is handled here after symbols have been resolved.
8626 Instruction is fixed up with VALUE using the information in *FIXP plus
8627 extra information in FLAGS.
8629 This function is called by md_apply_fix to fix up instructions that need
8630 a fix-up described above but does not involve any linker-time relocation. */
8633 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
8637 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8638 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
8639 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
8643 /* Now the instruction is about to be fixed-up, so the operand that
8644 was previously marked as 'ignored' needs to be unmarked in order
8645 to get the encoding done properly. */
8646 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8647 new_inst
->operands
[idx
].skip
= 0;
8650 gas_assert (opnd
!= AARCH64_OPND_NIL
);
8654 case AARCH64_OPND_EXCEPTION
:
8655 case AARCH64_OPND_UNDEFINED
:
8656 if (unsigned_overflow (value
, 16))
8657 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8658 _("immediate out of range"));
8659 insn
= get_aarch64_insn (buf
);
8660 insn
|= (opnd
== AARCH64_OPND_EXCEPTION
) ? encode_svc_imm (value
) : value
;
8661 put_aarch64_insn (buf
, insn
);
8664 case AARCH64_OPND_AIMM
:
8665 /* ADD or SUB with immediate.
8666 NOTE this assumes we come here with a add/sub shifted reg encoding
8667 3 322|2222|2 2 2 21111 111111
8668 1 098|7654|3 2 1 09876 543210 98765 43210
8669 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
8670 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
8671 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
8672 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
8674 3 322|2222|2 2 221111111111
8675 1 098|7654|3 2 109876543210 98765 43210
8676 11000000 sf 001|0001|shift imm12 Rn Rd ADD
8677 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
8678 51000000 sf 101|0001|shift imm12 Rn Rd SUB
8679 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
8680 Fields sf Rn Rd are already set. */
8681 insn
= get_aarch64_insn (buf
);
8685 insn
= reencode_addsub_switch_add_sub (insn
);
8689 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
8690 && unsigned_overflow (value
, 12))
8692 /* Try to shift the value by 12 to make it fit. */
8693 if (((value
>> 12) << 12) == value
8694 && ! unsigned_overflow (value
, 12 + 12))
8697 insn
|= encode_addsub_imm_shift_amount (1);
8701 if (unsigned_overflow (value
, 12))
8702 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8703 _("immediate out of range"));
8705 insn
|= encode_addsub_imm (value
);
8707 put_aarch64_insn (buf
, insn
);
8710 case AARCH64_OPND_SIMD_IMM
:
8711 case AARCH64_OPND_SIMD_IMM_SFT
:
8712 case AARCH64_OPND_LIMM
:
8713 /* Bit mask immediate. */
8714 gas_assert (new_inst
!= NULL
);
8715 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
8716 new_inst
->operands
[idx
].imm
.value
= value
;
8717 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8718 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8719 put_aarch64_insn (buf
, new_inst
->value
);
8721 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8722 _("invalid immediate"));
8725 case AARCH64_OPND_HALF
:
8726 /* 16-bit unsigned immediate. */
8727 if (unsigned_overflow (value
, 16))
8728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8729 _("immediate out of range"));
8730 insn
= get_aarch64_insn (buf
);
8731 insn
|= encode_movw_imm (value
& 0xffff);
8732 put_aarch64_insn (buf
, insn
);
8735 case AARCH64_OPND_IMM_MOV
:
8736 /* Operand for a generic move immediate instruction, which is
8737 an alias instruction that generates a single MOVZ, MOVN or ORR
8738 instruction to loads a 32-bit/64-bit immediate value into general
8739 register. An assembler error shall result if the immediate cannot be
8740 created by a single one of these instructions. If there is a choice,
8741 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
8742 and MOVZ or MOVN to ORR. */
8743 gas_assert (new_inst
!= NULL
);
8744 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
8747 case AARCH64_OPND_ADDR_SIMM7
:
8748 case AARCH64_OPND_ADDR_SIMM9
:
8749 case AARCH64_OPND_ADDR_SIMM9_2
:
8750 case AARCH64_OPND_ADDR_SIMM10
:
8751 case AARCH64_OPND_ADDR_UIMM12
:
8752 case AARCH64_OPND_ADDR_SIMM11
:
8753 case AARCH64_OPND_ADDR_SIMM13
:
8754 /* Immediate offset in an address. */
8755 insn
= get_aarch64_insn (buf
);
8757 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
8758 gas_assert (new_inst
->opcode
->operands
[1] == opnd
8759 || new_inst
->opcode
->operands
[2] == opnd
);
8761 /* Get the index of the address operand. */
8762 if (new_inst
->opcode
->operands
[1] == opnd
)
8763 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
8766 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
8769 /* Update the resolved offset value. */
8770 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
8772 /* Encode/fix-up. */
8773 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
8774 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
8776 put_aarch64_insn (buf
, new_inst
->value
);
8779 else if (new_inst
->opcode
->iclass
== ldst_pos
8780 && try_to_encode_as_unscaled_ldst (new_inst
))
8782 put_aarch64_insn (buf
, new_inst
->value
);
8786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8787 _("immediate offset out of range"));
8792 as_fatal (_("unhandled operand code %d"), opnd
);
8796 /* Apply a fixup (fixP) to segment data, once it has been determined
8797 by our caller that we have all the info we need to fix it up.
8799 Parameter valP is the pointer to the value of the bits. */
8802 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
8804 offsetT value
= *valP
;
8806 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8808 unsigned flags
= fixP
->fx_addnumber
;
8810 DEBUG_TRACE ("\n\n");
8811 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
8812 DEBUG_TRACE ("Enter md_apply_fix");
8814 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
8816 /* Note whether this will delete the relocation. */
8818 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
8821 /* Process the relocations. */
8822 switch (fixP
->fx_r_type
)
8824 case BFD_RELOC_NONE
:
8825 /* This will need to go in the object file. */
8830 case BFD_RELOC_8_PCREL
:
8831 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8832 md_number_to_chars (buf
, value
, 1);
8836 case BFD_RELOC_16_PCREL
:
8837 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8838 md_number_to_chars (buf
, value
, 2);
8842 case BFD_RELOC_32_PCREL
:
8843 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8844 md_number_to_chars (buf
, value
, 4);
8848 case BFD_RELOC_64_PCREL
:
8849 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8850 md_number_to_chars (buf
, value
, 8);
8853 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8854 /* We claim that these fixups have been processed here, even if
8855 in fact we generate an error because we do not have a reloc
8856 for them, so tc_gen_reloc() will reject them. */
8858 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
8860 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8861 _("undefined symbol %s used as an immediate value"),
8862 S_GET_NAME (fixP
->fx_addsy
));
8863 goto apply_fix_return
;
8865 fix_insn (fixP
, flags
, value
);
8868 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
8869 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8872 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8873 _("pc-relative load offset not word aligned"));
8874 if (signed_overflow (value
, 21))
8875 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8876 _("pc-relative load offset out of range"));
8877 insn
= get_aarch64_insn (buf
);
8878 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
8879 put_aarch64_insn (buf
, insn
);
8883 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
8884 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8886 if (signed_overflow (value
, 21))
8887 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8888 _("pc-relative address offset out of range"));
8889 insn
= get_aarch64_insn (buf
);
8890 insn
|= encode_adr_imm (value
);
8891 put_aarch64_insn (buf
, insn
);
8895 case BFD_RELOC_AARCH64_BRANCH19
:
8896 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8899 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8900 _("conditional branch target not word aligned"));
8901 if (signed_overflow (value
, 21))
8902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8903 _("conditional branch out of range"));
8904 insn
= get_aarch64_insn (buf
);
8905 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
8906 put_aarch64_insn (buf
, insn
);
8910 case BFD_RELOC_AARCH64_TSTBR14
:
8911 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8914 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8915 _("conditional branch target not word aligned"));
8916 if (signed_overflow (value
, 16))
8917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8918 _("conditional branch out of range"));
8919 insn
= get_aarch64_insn (buf
);
8920 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
8921 put_aarch64_insn (buf
, insn
);
8925 case BFD_RELOC_AARCH64_CALL26
:
8926 case BFD_RELOC_AARCH64_JUMP26
:
8927 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8930 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8931 _("branch target not word aligned"));
8932 if (signed_overflow (value
, 28))
8933 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8934 _("branch out of range"));
8935 insn
= get_aarch64_insn (buf
);
8936 insn
|= encode_branch_ofs_26 (value
>> 2);
8937 put_aarch64_insn (buf
, insn
);
8941 case BFD_RELOC_AARCH64_MOVW_G0
:
8942 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
8943 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8944 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
8945 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8946 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
8949 case BFD_RELOC_AARCH64_MOVW_G1
:
8950 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
8951 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8952 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8953 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8954 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
8957 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8959 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8960 /* Should always be exported to object file, see
8961 aarch64_force_relocation(). */
8962 gas_assert (!fixP
->fx_done
);
8963 gas_assert (seg
->use_rela_p
);
8965 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8967 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8968 /* Should always be exported to object file, see
8969 aarch64_force_relocation(). */
8970 gas_assert (!fixP
->fx_done
);
8971 gas_assert (seg
->use_rela_p
);
8973 case BFD_RELOC_AARCH64_MOVW_G2
:
8974 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
8975 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8976 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8977 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8980 case BFD_RELOC_AARCH64_MOVW_G3
:
8981 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8984 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8986 insn
= get_aarch64_insn (buf
);
8990 /* REL signed addend must fit in 16 bits */
8991 if (signed_overflow (value
, 16))
8992 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8993 _("offset out of range"));
8997 /* Check for overflow and scale. */
8998 switch (fixP
->fx_r_type
)
9000 case BFD_RELOC_AARCH64_MOVW_G0
:
9001 case BFD_RELOC_AARCH64_MOVW_G1
:
9002 case BFD_RELOC_AARCH64_MOVW_G2
:
9003 case BFD_RELOC_AARCH64_MOVW_G3
:
9004 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
9005 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
9006 if (unsigned_overflow (value
, scale
+ 16))
9007 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9008 _("unsigned value out of range"));
9010 case BFD_RELOC_AARCH64_MOVW_G0_S
:
9011 case BFD_RELOC_AARCH64_MOVW_G1_S
:
9012 case BFD_RELOC_AARCH64_MOVW_G2_S
:
9013 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
9014 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
9015 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
9016 /* NOTE: We can only come here with movz or movn. */
9017 if (signed_overflow (value
, scale
+ 16))
9018 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9019 _("signed value out of range"));
9022 /* Force use of MOVN. */
9024 insn
= reencode_movzn_to_movn (insn
);
9028 /* Force use of MOVZ. */
9029 insn
= reencode_movzn_to_movz (insn
);
9033 /* Unchecked relocations. */
9039 /* Insert value into MOVN/MOVZ/MOVK instruction. */
9040 insn
|= encode_movw_imm (value
& 0xffff);
9042 put_aarch64_insn (buf
, insn
);
9046 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
9047 fixP
->fx_r_type
= (ilp32_p
9048 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
9049 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
9050 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9051 /* Should always be exported to object file, see
9052 aarch64_force_relocation(). */
9053 gas_assert (!fixP
->fx_done
);
9054 gas_assert (seg
->use_rela_p
);
9057 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
9058 fixP
->fx_r_type
= (ilp32_p
9059 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
9060 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
9061 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9062 /* Should always be exported to object file, see
9063 aarch64_force_relocation(). */
9064 gas_assert (!fixP
->fx_done
);
9065 gas_assert (seg
->use_rela_p
);
9068 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
9069 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
9070 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
9071 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
9072 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
9073 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
9074 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
9075 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
9076 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
9077 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
9078 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
9079 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
9080 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
9081 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
9082 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
9083 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
9084 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
9085 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
9086 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
9087 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
9088 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
9089 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
9090 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
9091 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
9092 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
9093 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
9094 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
9095 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
9096 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
9097 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
9098 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
9099 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
9100 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
9101 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
9102 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
9103 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
9104 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
9105 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
9106 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
9107 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
9108 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
9109 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
9110 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
9111 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
9112 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
9113 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
9114 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
9115 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
9116 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
9117 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
9118 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
9119 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
9120 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9121 /* Should always be exported to object file, see
9122 aarch64_force_relocation(). */
9123 gas_assert (!fixP
->fx_done
);
9124 gas_assert (seg
->use_rela_p
);
9127 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
9128 /* Should always be exported to object file, see
9129 aarch64_force_relocation(). */
9130 fixP
->fx_r_type
= (ilp32_p
9131 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
9132 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
9133 gas_assert (!fixP
->fx_done
);
9134 gas_assert (seg
->use_rela_p
);
9137 case BFD_RELOC_AARCH64_ADD_LO12
:
9138 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
9139 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
9140 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
9141 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
9142 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
9143 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
9144 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
9145 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
9146 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
9147 case BFD_RELOC_AARCH64_LDST128_LO12
:
9148 case BFD_RELOC_AARCH64_LDST16_LO12
:
9149 case BFD_RELOC_AARCH64_LDST32_LO12
:
9150 case BFD_RELOC_AARCH64_LDST64_LO12
:
9151 case BFD_RELOC_AARCH64_LDST8_LO12
:
9152 /* Should always be exported to object file, see
9153 aarch64_force_relocation(). */
9154 gas_assert (!fixP
->fx_done
);
9155 gas_assert (seg
->use_rela_p
);
9158 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
9159 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
9160 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
9163 case BFD_RELOC_UNUSED
:
9164 /* An error will already have been reported. */
9168 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9169 _("unexpected %s fixup"),
9170 bfd_get_reloc_code_name (fixP
->fx_r_type
));
9175 /* Free the allocated the struct aarch64_inst.
9176 N.B. currently there are very limited number of fix-up types actually use
9177 this field, so the impact on the performance should be minimal . */
9178 free (fixP
->tc_fix_data
.inst
);
9183 /* Translate internal representation of relocation info to BFD target
9187 tc_gen_reloc (asection
* section
, fixS
* fixp
)
9190 bfd_reloc_code_real_type code
;
9192 reloc
= XNEW (arelent
);
9194 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
9195 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9196 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9200 if (section
->use_rela_p
)
9201 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
9203 fixp
->fx_offset
= reloc
->address
;
9205 reloc
->addend
= fixp
->fx_offset
;
9207 code
= fixp
->fx_r_type
;
9212 code
= BFD_RELOC_16_PCREL
;
9217 code
= BFD_RELOC_32_PCREL
;
9222 code
= BFD_RELOC_64_PCREL
;
9229 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9230 if (reloc
->howto
== NULL
)
9232 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9234 ("cannot represent %s relocation in this object file format"),
9235 bfd_get_reloc_code_name (code
));
9242 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
9245 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
9247 bfd_reloc_code_real_type type
;
9251 FIXME: @@ Should look at CPU word size. */
9258 type
= BFD_RELOC_16
;
9261 type
= BFD_RELOC_32
;
9264 type
= BFD_RELOC_64
;
9267 as_bad (_("cannot do %u-byte relocation"), size
);
9268 type
= BFD_RELOC_UNUSED
;
9272 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
9277 /* Implement md_after_parse_args. This is the earliest time we need to decide
9278 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
9281 aarch64_after_parse_args (void)
9283 if (aarch64_abi
!= AARCH64_ABI_NONE
)
9286 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
9287 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
9288 aarch64_abi
= AARCH64_ABI_ILP32
;
9290 aarch64_abi
= AARCH64_ABI_LP64
;
9294 elf64_aarch64_target_format (void)
9297 /* FIXME: What to do for ilp32_p ? */
9298 if (target_big_endian
)
9299 return "elf64-bigaarch64-cloudabi";
9301 return "elf64-littleaarch64-cloudabi";
9303 if (target_big_endian
)
9304 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
9306 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
9311 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
9313 elf_frob_symbol (symp
, puntp
);
9317 /* MD interface: Finalization. */
9319 /* A good place to do this, although this was probably not intended
9320 for this kind of use. We need to dump the literal pool before
9321 references are made to a null symbol pointer. */
9324 aarch64_cleanup (void)
9328 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
9330 /* Put it at the end of the relevant section. */
9331 subseg_set (pool
->section
, pool
->sub_section
);
9337 /* Remove any excess mapping symbols generated for alignment frags in
9338 SEC. We may have created a mapping symbol before a zero byte
9339 alignment; remove it if there's a mapping symbol after the
9342 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
9343 void *dummy ATTRIBUTE_UNUSED
)
9345 segment_info_type
*seginfo
= seg_info (sec
);
9348 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
9351 for (fragp
= seginfo
->frchainP
->frch_root
;
9352 fragp
!= NULL
; fragp
= fragp
->fr_next
)
9354 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
9355 fragS
*next
= fragp
->fr_next
;
9357 /* Variable-sized frags have been converted to fixed size by
9358 this point. But if this was variable-sized to start with,
9359 there will be a fixed-size frag after it. So don't handle
9361 if (sym
== NULL
|| next
== NULL
)
9364 if (S_GET_VALUE (sym
) < next
->fr_address
)
9365 /* Not at the end of this frag. */
9367 know (S_GET_VALUE (sym
) == next
->fr_address
);
9371 if (next
->tc_frag_data
.first_map
!= NULL
)
9373 /* Next frag starts with a mapping symbol. Discard this
9375 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9379 if (next
->fr_next
== NULL
)
9381 /* This mapping symbol is at the end of the section. Discard
9383 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
9384 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
9388 /* As long as we have empty frags without any mapping symbols,
9390 /* If the next frag is non-empty and does not start with a
9391 mapping symbol, then this mapping symbol is required. */
9392 if (next
->fr_address
!= next
->fr_next
->fr_address
)
9395 next
= next
->fr_next
;
9397 while (next
!= NULL
);
9402 /* Adjust the symbol table. */
9405 aarch64_adjust_symtab (void)
9408 /* Remove any overlapping mapping symbols generated by alignment frags. */
9409 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
9410 /* Now do generic ELF adjustments. */
9411 elf_adjust_symtab ();
9416 checked_hash_insert (htab_t table
, const char *key
, void *value
)
9418 str_hash_insert (table
, key
, value
, 0);
9422 sysreg_hash_insert (htab_t table
, const char *key
, void *value
)
9424 gas_assert (strlen (key
) < AARCH64_MAX_SYSREG_NAME_LEN
);
9425 checked_hash_insert (table
, key
, value
);
9429 fill_instruction_hash_table (void)
9431 const aarch64_opcode
*opcode
= aarch64_opcode_table
;
9433 while (opcode
->name
!= NULL
)
9435 templates
*templ
, *new_templ
;
9436 templ
= str_hash_find (aarch64_ops_hsh
, opcode
->name
);
9438 new_templ
= XNEW (templates
);
9439 new_templ
->opcode
= opcode
;
9440 new_templ
->next
= NULL
;
9443 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
9446 new_templ
->next
= templ
->next
;
9447 templ
->next
= new_templ
;
9454 convert_to_upper (char *dst
, const char *src
, size_t num
)
9457 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
9458 *dst
= TOUPPER (*src
);
9462 /* Assume STR point to a lower-case string, allocate, convert and return
9463 the corresponding upper-case string. */
9464 static inline const char*
9465 get_upper_str (const char *str
)
9468 size_t len
= strlen (str
);
9469 ret
= XNEWVEC (char, len
+ 1);
9470 convert_to_upper (ret
, str
, len
);
9474 /* MD interface: Initialization. */
9482 aarch64_ops_hsh
= str_htab_create ();
9483 aarch64_cond_hsh
= str_htab_create ();
9484 aarch64_shift_hsh
= str_htab_create ();
9485 aarch64_sys_regs_hsh
= str_htab_create ();
9486 aarch64_pstatefield_hsh
= str_htab_create ();
9487 aarch64_sys_regs_ic_hsh
= str_htab_create ();
9488 aarch64_sys_regs_dc_hsh
= str_htab_create ();
9489 aarch64_sys_regs_at_hsh
= str_htab_create ();
9490 aarch64_sys_regs_tlbi_hsh
= str_htab_create ();
9491 aarch64_sys_regs_sr_hsh
= str_htab_create ();
9492 aarch64_reg_hsh
= str_htab_create ();
9493 aarch64_barrier_opt_hsh
= str_htab_create ();
9494 aarch64_nzcv_hsh
= str_htab_create ();
9495 aarch64_pldop_hsh
= str_htab_create ();
9496 aarch64_hint_opt_hsh
= str_htab_create ();
9498 fill_instruction_hash_table ();
9500 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
9501 sysreg_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
9502 (void *) (aarch64_sys_regs
+ i
));
9504 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
9505 sysreg_hash_insert (aarch64_pstatefield_hsh
,
9506 aarch64_pstatefields
[i
].name
,
9507 (void *) (aarch64_pstatefields
+ i
));
9509 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
9510 sysreg_hash_insert (aarch64_sys_regs_ic_hsh
,
9511 aarch64_sys_regs_ic
[i
].name
,
9512 (void *) (aarch64_sys_regs_ic
+ i
));
9514 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
9515 sysreg_hash_insert (aarch64_sys_regs_dc_hsh
,
9516 aarch64_sys_regs_dc
[i
].name
,
9517 (void *) (aarch64_sys_regs_dc
+ i
));
9519 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
9520 sysreg_hash_insert (aarch64_sys_regs_at_hsh
,
9521 aarch64_sys_regs_at
[i
].name
,
9522 (void *) (aarch64_sys_regs_at
+ i
));
9524 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
9525 sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh
,
9526 aarch64_sys_regs_tlbi
[i
].name
,
9527 (void *) (aarch64_sys_regs_tlbi
+ i
));
9529 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
9530 sysreg_hash_insert (aarch64_sys_regs_sr_hsh
,
9531 aarch64_sys_regs_sr
[i
].name
,
9532 (void *) (aarch64_sys_regs_sr
+ i
));
9534 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
9535 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
9536 (void *) (reg_names
+ i
));
9538 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
9539 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
9540 (void *) (nzcv_names
+ i
));
9542 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
9544 const char *name
= aarch64_operand_modifiers
[i
].name
;
9545 checked_hash_insert (aarch64_shift_hsh
, name
,
9546 (void *) (aarch64_operand_modifiers
+ i
));
9547 /* Also hash the name in the upper case. */
9548 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
9549 (void *) (aarch64_operand_modifiers
+ i
));
9552 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
9555 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
9556 the same condition code. */
9557 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
9559 const char *name
= aarch64_conds
[i
].names
[j
];
9562 checked_hash_insert (aarch64_cond_hsh
, name
,
9563 (void *) (aarch64_conds
+ i
));
9564 /* Also hash the name in the upper case. */
9565 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
9566 (void *) (aarch64_conds
+ i
));
9570 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
9572 const char *name
= aarch64_barrier_options
[i
].name
;
9573 /* Skip xx00 - the unallocated values of option. */
9576 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9577 (void *) (aarch64_barrier_options
+ i
));
9578 /* Also hash the name in the upper case. */
9579 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9580 (void *) (aarch64_barrier_options
+ i
));
9583 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_dsb_nxs_options
); i
++)
9585 const char *name
= aarch64_barrier_dsb_nxs_options
[i
].name
;
9586 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
9587 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9588 /* Also hash the name in the upper case. */
9589 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
9590 (void *) (aarch64_barrier_dsb_nxs_options
+ i
));
9593 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
9595 const char* name
= aarch64_prfops
[i
].name
;
9596 /* Skip the unallocated hint encodings. */
9599 checked_hash_insert (aarch64_pldop_hsh
, name
,
9600 (void *) (aarch64_prfops
+ i
));
9601 /* Also hash the name in the upper case. */
9602 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
9603 (void *) (aarch64_prfops
+ i
));
9606 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
9608 const char* name
= aarch64_hint_options
[i
].name
;
9609 const char* upper_name
= get_upper_str(name
);
9611 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
9612 (void *) (aarch64_hint_options
+ i
));
9614 /* Also hash the name in the upper case if not the same. */
9615 if (strcmp (name
, upper_name
) != 0)
9616 checked_hash_insert (aarch64_hint_opt_hsh
, upper_name
,
9617 (void *) (aarch64_hint_options
+ i
));
9620 /* Set the cpu variant based on the command-line options. */
9622 mcpu_cpu_opt
= march_cpu_opt
;
9625 mcpu_cpu_opt
= &cpu_default
;
9627 cpu_variant
= *mcpu_cpu_opt
;
9629 /* Record the CPU type. */
9630 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
9632 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
9635 /* Command line processing. */
9637 const char *md_shortopts
= "m:";
9639 #ifdef AARCH64_BI_ENDIAN
9640 #define OPTION_EB (OPTION_MD_BASE + 0)
9641 #define OPTION_EL (OPTION_MD_BASE + 1)
9643 #if TARGET_BYTES_BIG_ENDIAN
9644 #define OPTION_EB (OPTION_MD_BASE + 0)
9646 #define OPTION_EL (OPTION_MD_BASE + 1)
9650 struct option md_longopts
[] = {
9652 {"EB", no_argument
, NULL
, OPTION_EB
},
9655 {"EL", no_argument
, NULL
, OPTION_EL
},
9657 {NULL
, no_argument
, NULL
, 0}
9660 size_t md_longopts_size
= sizeof (md_longopts
);
9662 struct aarch64_option_table
9664 const char *option
; /* Option name to match. */
9665 const char *help
; /* Help information. */
9666 int *var
; /* Variable to change. */
9667 int value
; /* What to change it to. */
9668 char *deprecated
; /* If non-null, print this message. */
9671 static struct aarch64_option_table aarch64_opts
[] = {
9672 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
9673 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
9675 #ifdef DEBUG_AARCH64
9676 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
9677 #endif /* DEBUG_AARCH64 */
9678 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
9680 {"mno-verbose-error", N_("do not output verbose error messages"),
9681 &verbose_error_p
, 0, NULL
},
9682 {NULL
, NULL
, NULL
, 0, NULL
}
9685 struct aarch64_cpu_option_table
9688 const aarch64_feature_set value
;
9689 /* The canonical name of the CPU, or NULL to use NAME converted to upper
9691 const char *canonical_name
;
9694 /* This list should, at a minimum, contain all the cpu names
9695 recognized by GCC. */
9696 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
9697 {"all", AARCH64_ANY
, NULL
},
9698 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9699 AARCH64_FEATURE_CRC
), "Cortex-A34"},
9700 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9701 AARCH64_FEATURE_CRC
), "Cortex-A35"},
9702 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9703 AARCH64_FEATURE_CRC
), "Cortex-A53"},
9704 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9705 AARCH64_FEATURE_CRC
), "Cortex-A57"},
9706 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9707 AARCH64_FEATURE_CRC
), "Cortex-A72"},
9708 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9709 AARCH64_FEATURE_CRC
), "Cortex-A73"},
9710 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9711 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9713 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9714 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9716 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9717 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
9719 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9720 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9721 | AARCH64_FEATURE_DOTPROD
9722 | AARCH64_FEATURE_SSBS
),
9724 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9725 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9726 | AARCH64_FEATURE_DOTPROD
9727 | AARCH64_FEATURE_SSBS
),
9729 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9730 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9731 | AARCH64_FEATURE_DOTPROD
9732 | AARCH64_FEATURE_SSBS
),
9734 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9735 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
9736 | AARCH64_FEATURE_DOTPROD
9737 | AARCH64_FEATURE_SSBS
),
9739 {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9741 | AARCH64_FEATURE_RCPC
9742 | AARCH64_FEATURE_DOTPROD
9743 | AARCH64_FEATURE_SSBS
9744 | AARCH64_FEATURE_PROFILE
),
9746 {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9748 | AARCH64_FEATURE_RCPC
9749 | AARCH64_FEATURE_DOTPROD
9750 | AARCH64_FEATURE_SSBS
9751 | AARCH64_FEATURE_PROFILE
),
9753 {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9754 AARCH64_FEATURE_DOTPROD
9755 | AARCH64_FEATURE_F16
9756 | AARCH64_FEATURE_FLAGM
9757 | AARCH64_FEATURE_PAC
9758 | AARCH64_FEATURE_PROFILE
9759 | AARCH64_FEATURE_RCPC
9760 | AARCH64_FEATURE_SSBS
),
9762 {"cortex-a510", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9763 AARCH64_FEATURE_BFLOAT16
9764 | AARCH64_FEATURE_I8MM
9765 | AARCH64_FEATURE_MEMTAG
9766 | AARCH64_FEATURE_SVE2_BITPERM
),
9768 {"cortex-a710", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9769 AARCH64_FEATURE_BFLOAT16
9770 | AARCH64_FEATURE_I8MM
9771 | AARCH64_FEATURE_MEMTAG
9772 | AARCH64_FEATURE_SVE2_BITPERM
),
9774 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9775 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9776 | AARCH64_FEATURE_DOTPROD
9777 | AARCH64_FEATURE_PROFILE
),
9779 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9780 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9781 "Samsung Exynos M1"},
9782 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9783 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9784 | AARCH64_FEATURE_RDMA
),
9786 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9787 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9788 | AARCH64_FEATURE_DOTPROD
9789 | AARCH64_FEATURE_SSBS
),
9791 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9792 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
9793 | AARCH64_FEATURE_DOTPROD
9794 | AARCH64_FEATURE_PROFILE
),
9796 {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5
,
9797 AARCH64_FEATURE_BFLOAT16
9798 | AARCH64_FEATURE_I8MM
9799 | AARCH64_FEATURE_F16
9800 | AARCH64_FEATURE_SVE
9801 | AARCH64_FEATURE_SVE2
9802 | AARCH64_FEATURE_SVE2_BITPERM
9803 | AARCH64_FEATURE_MEMTAG
9804 | AARCH64_FEATURE_RNG
),
9806 {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9807 AARCH64_FEATURE_PROFILE
9808 | AARCH64_FEATURE_CVADP
9809 | AARCH64_FEATURE_SVE
9810 | AARCH64_FEATURE_SSBS
9811 | AARCH64_FEATURE_RNG
9812 | AARCH64_FEATURE_F16
9813 | AARCH64_FEATURE_BFLOAT16
9814 | AARCH64_FEATURE_I8MM
), "Neoverse V1"},
9815 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9816 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
9817 | AARCH64_FEATURE_RDMA
),
9818 "Qualcomm QDF24XX"},
9819 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
9820 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
9821 "Qualcomm Saphira"},
9822 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9823 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
9825 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
9826 AARCH64_FEATURE_CRYPTO
),
9828 /* The 'xgene-1' name is an older name for 'xgene1', which was used
9829 in earlier releases and is superseded by 'xgene1' in all
9831 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9832 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
9833 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
9834 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
9835 {"cortex-r82", AARCH64_ARCH_V8_R
, "Cortex-R82"},
9836 {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
9838 | AARCH64_FEATURE_RCPC
9839 | AARCH64_FEATURE_DOTPROD
9840 | AARCH64_FEATURE_SSBS
9841 | AARCH64_FEATURE_PROFILE
),
9843 {"cortex-x2", AARCH64_FEATURE (AARCH64_ARCH_V9
,
9844 AARCH64_FEATURE_BFLOAT16
9845 | AARCH64_FEATURE_I8MM
9846 | AARCH64_FEATURE_MEMTAG
9847 | AARCH64_FEATURE_SVE2_BITPERM
),
9849 {"generic", AARCH64_ARCH_V8
, NULL
},
9851 {NULL
, AARCH64_ARCH_NONE
, NULL
}
9854 struct aarch64_arch_option_table
9857 const aarch64_feature_set value
;
9860 /* This list should, at a minimum, contain all the architecture names
9861 recognized by GCC. */
9862 static const struct aarch64_arch_option_table aarch64_archs
[] = {
9863 {"all", AARCH64_ANY
},
9864 {"armv8-a", AARCH64_ARCH_V8
},
9865 {"armv8.1-a", AARCH64_ARCH_V8_1
},
9866 {"armv8.2-a", AARCH64_ARCH_V8_2
},
9867 {"armv8.3-a", AARCH64_ARCH_V8_3
},
9868 {"armv8.4-a", AARCH64_ARCH_V8_4
},
9869 {"armv8.5-a", AARCH64_ARCH_V8_5
},
9870 {"armv8.6-a", AARCH64_ARCH_V8_6
},
9871 {"armv8.7-a", AARCH64_ARCH_V8_7
},
9872 {"armv8.8-a", AARCH64_ARCH_V8_8
},
9873 {"armv8-r", AARCH64_ARCH_V8_R
},
9874 {"armv9-a", AARCH64_ARCH_V9
},
9875 {"armv9.1-a", AARCH64_ARCH_V9_1
},
9876 {"armv9.2-a", AARCH64_ARCH_V9_2
},
9877 {"armv9.3-a", AARCH64_ARCH_V9_3
},
9878 {NULL
, AARCH64_ARCH_NONE
}
9881 /* ISA extensions. */
9882 struct aarch64_option_cpu_value_table
9885 const aarch64_feature_set value
;
9886 const aarch64_feature_set require
; /* Feature dependencies. */
9889 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
9890 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
9892 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0),
9893 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9894 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
9896 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
9898 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
9899 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9900 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
9902 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
9904 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
9906 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
9907 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
9908 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
9909 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
9910 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
9911 AARCH64_FEATURE (AARCH64_FEATURE_FP
9912 | AARCH64_FEATURE_F16
, 0)},
9913 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
9915 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
9916 AARCH64_FEATURE (AARCH64_FEATURE_F16
9917 | AARCH64_FEATURE_SIMD
9918 | AARCH64_FEATURE_COMPNUM
, 0)},
9919 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
9921 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
9922 AARCH64_FEATURE (AARCH64_FEATURE_F16
9923 | AARCH64_FEATURE_SIMD
, 0)},
9924 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
9926 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
9928 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
9930 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
9932 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
9934 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
9936 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
9938 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3
, 0),
9939 AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0)},
9940 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
9942 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
9944 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
9946 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
9947 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9948 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
9949 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9950 | AARCH64_FEATURE_SM4
, 0)},
9951 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
9952 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9953 | AARCH64_FEATURE_AES
, 0)},
9954 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
9955 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9956 | AARCH64_FEATURE_SHA3
, 0)},
9957 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
9958 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
9959 {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME
, 0),
9960 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
9961 | AARCH64_FEATURE_BFLOAT16
, 0)},
9962 {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64
, 0),
9963 AARCH64_FEATURE (AARCH64_FEATURE_SME
9964 | AARCH64_FEATURE_SVE2
9965 | AARCH64_FEATURE_BFLOAT16
, 0)},
9966 {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I64
, 0),
9967 AARCH64_FEATURE (AARCH64_FEATURE_SME
9968 | AARCH64_FEATURE_SVE2
9969 | AARCH64_FEATURE_BFLOAT16
, 0)},
9970 {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16
, 0),
9972 {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM
, 0),
9974 {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM
, 0),
9975 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9976 {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM
, 0),
9977 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
9978 {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64
, 0),
9980 {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM
, 0),
9982 {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC
, 0),
9984 {"mops", AARCH64_FEATURE (AARCH64_FEATURE_MOPS
, 0),
9986 {"hbc", AARCH64_FEATURE (AARCH64_FEATURE_HBC
, 0),
9988 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
9991 struct aarch64_long_option_table
9993 const char *option
; /* Substring to match. */
9994 const char *help
; /* Help information. */
9995 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
9996 char *deprecated
; /* If non-null, print this message. */
9999 /* Transitive closure of features depending on set. */
10000 static aarch64_feature_set
10001 aarch64_feature_disable_set (aarch64_feature_set set
)
10003 const struct aarch64_option_cpu_value_table
*opt
;
10004 aarch64_feature_set prev
= 0;
10006 while (prev
!= set
) {
10008 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10009 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
10010 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
10015 /* Transitive closure of dependencies of set. */
10016 static aarch64_feature_set
10017 aarch64_feature_enable_set (aarch64_feature_set set
)
10019 const struct aarch64_option_cpu_value_table
*opt
;
10020 aarch64_feature_set prev
= 0;
10022 while (prev
!= set
) {
10024 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10025 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
10026 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
10032 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
10035 /* We insist on extensions being added before being removed. We achieve
10036 this by using the ADDING_VALUE variable to indicate whether we are
10037 adding an extension (1) or removing it (0) and only allowing it to
10038 change in the order -1 -> 1 -> 0. */
10039 int adding_value
= -1;
10040 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
10042 /* Copy the feature set, so that we can modify it. */
10043 *ext_set
= **opt_p
;
10046 while (str
!= NULL
&& *str
!= 0)
10048 const struct aarch64_option_cpu_value_table
*opt
;
10049 const char *ext
= NULL
;
10056 as_bad (_("invalid architectural extension"));
10060 ext
= strchr (++str
, '+');
10064 optlen
= ext
- str
;
10066 optlen
= strlen (str
);
10068 if (optlen
>= 2 && startswith (str
, "no"))
10070 if (adding_value
!= 0)
10075 else if (optlen
> 0)
10077 if (adding_value
== -1)
10079 else if (adding_value
!= 1)
10081 as_bad (_("must specify extensions to add before specifying "
10082 "those to remove"));
10089 as_bad (_("missing architectural extension"));
10093 gas_assert (adding_value
!= -1);
10095 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
10096 if (strncmp (opt
->name
, str
, optlen
) == 0)
10098 aarch64_feature_set set
;
10100 /* Add or remove the extension. */
10103 set
= aarch64_feature_enable_set (opt
->value
);
10104 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
10108 set
= aarch64_feature_disable_set (opt
->value
);
10109 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
10114 if (opt
->name
== NULL
)
10116 as_bad (_("unknown architectural extension `%s'"), str
);
10127 aarch64_parse_cpu (const char *str
)
10129 const struct aarch64_cpu_option_table
*opt
;
10130 const char *ext
= strchr (str
, '+');
10134 optlen
= ext
- str
;
10136 optlen
= strlen (str
);
10140 as_bad (_("missing cpu name `%s'"), str
);
10144 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
10145 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10147 mcpu_cpu_opt
= &opt
->value
;
10149 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, false);
10154 as_bad (_("unknown cpu `%s'"), str
);
10159 aarch64_parse_arch (const char *str
)
10161 const struct aarch64_arch_option_table
*opt
;
10162 const char *ext
= strchr (str
, '+');
10166 optlen
= ext
- str
;
10168 optlen
= strlen (str
);
10172 as_bad (_("missing architecture name `%s'"), str
);
10176 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
10177 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
10179 march_cpu_opt
= &opt
->value
;
10181 return aarch64_parse_features (ext
, &march_cpu_opt
, false);
10186 as_bad (_("unknown architecture `%s'\n"), str
);
10191 struct aarch64_option_abi_value_table
10194 enum aarch64_abi_type value
;
10197 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
10198 {"ilp32", AARCH64_ABI_ILP32
},
10199 {"lp64", AARCH64_ABI_LP64
},
10203 aarch64_parse_abi (const char *str
)
10207 if (str
[0] == '\0')
10209 as_bad (_("missing abi name `%s'"), str
);
10213 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
10214 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
10216 aarch64_abi
= aarch64_abis
[i
].value
;
10220 as_bad (_("unknown abi `%s'\n"), str
);
10224 static struct aarch64_long_option_table aarch64_long_opts
[] = {
10226 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
10227 aarch64_parse_abi
, NULL
},
10228 #endif /* OBJ_ELF */
10229 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
10230 aarch64_parse_cpu
, NULL
},
10231 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
10232 aarch64_parse_arch
, NULL
},
10233 {NULL
, NULL
, 0, NULL
}
10237 md_parse_option (int c
, const char *arg
)
10239 struct aarch64_option_table
*opt
;
10240 struct aarch64_long_option_table
*lopt
;
10246 target_big_endian
= 1;
10252 target_big_endian
= 0;
10257 /* Listing option. Just ignore these, we don't support additional
10262 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10264 if (c
== opt
->option
[0]
10265 && ((arg
== NULL
&& opt
->option
[1] == 0)
10266 || streq (arg
, opt
->option
+ 1)))
10268 /* If the option is deprecated, tell the user. */
10269 if (opt
->deprecated
!= NULL
)
10270 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
10271 arg
? arg
: "", _(opt
->deprecated
));
10273 if (opt
->var
!= NULL
)
10274 *opt
->var
= opt
->value
;
10280 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10282 /* These options are expected to have an argument. */
10283 if (c
== lopt
->option
[0]
10285 && startswith (arg
, lopt
->option
+ 1))
10287 /* If the option is deprecated, tell the user. */
10288 if (lopt
->deprecated
!= NULL
)
10289 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
10290 _(lopt
->deprecated
));
10292 /* Call the sup-option parser. */
10293 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
10304 md_show_usage (FILE * fp
)
10306 struct aarch64_option_table
*opt
;
10307 struct aarch64_long_option_table
*lopt
;
10309 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
10311 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
10312 if (opt
->help
!= NULL
)
10313 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
10315 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
10316 if (lopt
->help
!= NULL
)
10317 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
10321 -EB assemble code for a big-endian cpu\n"));
10326 -EL assemble code for a little-endian cpu\n"));
10330 /* Parse a .cpu directive. */
10333 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
10335 const struct aarch64_cpu_option_table
*opt
;
10341 name
= input_line_pointer
;
10342 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10343 input_line_pointer
++;
10344 saved_char
= *input_line_pointer
;
10345 *input_line_pointer
= 0;
10347 ext
= strchr (name
, '+');
10350 optlen
= ext
- name
;
10352 optlen
= strlen (name
);
10354 /* Skip the first "all" entry. */
10355 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
10356 if (strlen (opt
->name
) == optlen
10357 && strncmp (name
, opt
->name
, optlen
) == 0)
10359 mcpu_cpu_opt
= &opt
->value
;
10361 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10364 cpu_variant
= *mcpu_cpu_opt
;
10366 *input_line_pointer
= saved_char
;
10367 demand_empty_rest_of_line ();
10370 as_bad (_("unknown cpu `%s'"), name
);
10371 *input_line_pointer
= saved_char
;
10372 ignore_rest_of_line ();
10376 /* Parse a .arch directive. */
10379 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
10381 const struct aarch64_arch_option_table
*opt
;
10387 name
= input_line_pointer
;
10388 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10389 input_line_pointer
++;
10390 saved_char
= *input_line_pointer
;
10391 *input_line_pointer
= 0;
10393 ext
= strchr (name
, '+');
10396 optlen
= ext
- name
;
10398 optlen
= strlen (name
);
10400 /* Skip the first "all" entry. */
10401 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
10402 if (strlen (opt
->name
) == optlen
10403 && strncmp (name
, opt
->name
, optlen
) == 0)
10405 mcpu_cpu_opt
= &opt
->value
;
10407 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, false))
10410 cpu_variant
= *mcpu_cpu_opt
;
10412 *input_line_pointer
= saved_char
;
10413 demand_empty_rest_of_line ();
10417 as_bad (_("unknown architecture `%s'\n"), name
);
10418 *input_line_pointer
= saved_char
;
10419 ignore_rest_of_line ();
10422 /* Parse a .arch_extension directive. */
10425 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
10428 char *ext
= input_line_pointer
;;
10430 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
10431 input_line_pointer
++;
10432 saved_char
= *input_line_pointer
;
10433 *input_line_pointer
= 0;
10435 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, true))
10438 cpu_variant
= *mcpu_cpu_opt
;
10440 *input_line_pointer
= saved_char
;
10441 demand_empty_rest_of_line ();
10444 /* Copy symbol information. */
10447 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
10449 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
10453 /* Same as elf_copy_symbol_attributes, but without copying st_other.
10454 This is needed so AArch64 specific st_other values can be independently
10455 specified for an IFUNC resolver (that is called by the dynamic linker)
10456 and the symbol it resolves (aliased to the resolver). In particular,
10457 if a function symbol has special st_other value set via directives,
10458 then attaching an IFUNC resolver to that symbol should not override
10459 the st_other setting. Requiring the directive on the IFUNC resolver
10460 symbol would be unexpected and problematic in C code, where the two
10461 symbols appear as two independent function declarations. */
10464 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
10466 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
10467 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
10470 if (destelf
->size
== NULL
)
10471 destelf
->size
= XNEW (expressionS
);
10472 *destelf
->size
= *srcelf
->size
;
10476 free (destelf
->size
);
10477 destelf
->size
= NULL
;
10479 S_SET_SIZE (dest
, S_GET_SIZE (src
));