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New ARC implementation.
[thirdparty/binutils-gdb.git] / gas / config / tc-arc.c
1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 #include "as.h"
24 #include "subsegs.h"
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "safe-ctype.h"
28
29 #include "opcode/arc.h"
30 #include "elf/arc.h"
31
32 /* Defines section. */
33
34 #define MAX_FLAG_NAME_LENGHT 3
35 #define MAX_INSN_FIXUPS 2
36 #define MAX_CONSTR_STR 20
37
38 #ifdef DEBUG
39 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
40 #else
41 # define pr_debug(fmt, args...)
42 #endif
43
44 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
45 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
46 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \
47 (SUB_OPCODE (x) == 0x28))
48
49 /* Equal to MAX_PRECISION in atof-ieee.c. */
50 #define MAX_LITTLENUMS 6
51
52 /* Macros section. */
53
54 #define regno(x) ((x) & 0x3F)
55 #define is_ir_num(x) (((x) & ~0x3F) == 0)
56 #define is_code_density_p(op) (((op)->subclass == CD1 || (op)->subclass == CD2))
57 #define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP))
58 #define is_kernel_insn_p(op) (((op)->class == KERNEL))
59
60 /* Generic assembler global variables which must be defined by all
61 targets. */
62
63 /* Characters which always start a comment. */
64 const char comment_chars[] = "#;";
65
66 /* Characters which start a comment at the beginning of a line. */
67 const char line_comment_chars[] = "#";
68
69 /* Characters which may be used to separate multiple commands on a
70 single line. */
71 const char line_separator_chars[] = "`";
72
73 /* Characters which are used to indicate an exponent in a floating
74 point number. */
75 const char EXP_CHARS[] = "eE";
76
77 /* Chars that mean this number is a floating point constant
78 As in 0f12.456 or 0d1.2345e12. */
79 const char FLT_CHARS[] = "rRsSfFdD";
80
81 /* Byte order. */
82 extern int target_big_endian;
83 const char *arc_target_format = DEFAULT_TARGET_FORMAT;
84 static int byte_order = DEFAULT_BYTE_ORDER;
85
86 extern int arc_get_mach (char *);
87
88 /* Forward declaration. */
89 static void arc_lcomm (int);
90 static void arc_option (int);
91 static void arc_extra_reloc (int);
92
93 const pseudo_typeS md_pseudo_table[] =
94 {
95 /* Make sure that .word is 32 bits. */
96 { "word", cons, 4 },
97
98 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
99 { "lcomm", arc_lcomm, 0 },
100 { "lcommon", arc_lcomm, 0 },
101 { "cpu", arc_option, 0 },
102
103 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
104 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
105
106 { NULL, NULL, 0 }
107 };
108
109 const char *md_shortopts = "";
110
111 enum options
112 {
113 OPTION_EB = OPTION_MD_BASE,
114 OPTION_EL,
115
116 OPTION_ARC600,
117 OPTION_ARC601,
118 OPTION_ARC700,
119 OPTION_ARCEM,
120 OPTION_ARCHS,
121
122 OPTION_MCPU,
123 OPTION_CD,
124
125 /* The following options are deprecated and provided here only for
126 compatibility reasons. */
127 OPTION_USER_MODE,
128 OPTION_LD_EXT_MASK,
129 OPTION_SWAP,
130 OPTION_NORM,
131 OPTION_BARREL_SHIFT,
132 OPTION_MIN_MAX,
133 OPTION_NO_MPY,
134 OPTION_EA,
135 OPTION_MUL64,
136 OPTION_SIMD,
137 OPTION_SPFP,
138 OPTION_DPFP,
139 OPTION_XMAC_D16,
140 OPTION_XMAC_24,
141 OPTION_DSP_PACKA,
142 OPTION_CRC,
143 OPTION_DVBF,
144 OPTION_TELEPHONY,
145 OPTION_XYMEMORY,
146 OPTION_LOCK,
147 OPTION_SWAPE,
148 OPTION_RTSC,
149 OPTION_FPUDA
150 };
151
152 struct option md_longopts[] =
153 {
154 { "EB", no_argument, NULL, OPTION_EB },
155 { "EL", no_argument, NULL, OPTION_EL },
156 { "mcpu", required_argument, NULL, OPTION_MCPU },
157 { "mA6", no_argument, NULL, OPTION_ARC600 },
158 { "mARC600", no_argument, NULL, OPTION_ARC600 },
159 { "mARC601", no_argument, NULL, OPTION_ARC601 },
160 { "mARC700", no_argument, NULL, OPTION_ARC700 },
161 { "mA7", no_argument, NULL, OPTION_ARC700 },
162 { "mEM", no_argument, NULL, OPTION_ARCEM },
163 { "mHS", no_argument, NULL, OPTION_ARCHS },
164 { "mcode-density", no_argument, NULL, OPTION_CD },
165
166 /* The following options are deprecated and provided here only for
167 compatibility reasons. */
168 { "mav2em", no_argument, NULL, OPTION_ARCEM },
169 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
170 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
171 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
172 { "mswap", no_argument, NULL, OPTION_SWAP },
173 { "mnorm", no_argument, NULL, OPTION_NORM },
174 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
175 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
176 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
177 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
178 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
179 { "mea", no_argument, NULL, OPTION_EA },
180 { "mEA", no_argument, NULL, OPTION_EA },
181 { "mmul64", no_argument, NULL, OPTION_MUL64 },
182 { "msimd", no_argument, NULL, OPTION_SIMD},
183 { "mspfp", no_argument, NULL, OPTION_SPFP},
184 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
185 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
186 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
187 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
188 { "mdpfp", no_argument, NULL, OPTION_DPFP},
189 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
190 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
191 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
192 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
193 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
194 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
195 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
196 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
197 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
198 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
199 { "mcrc", no_argument, NULL, OPTION_CRC},
200 { "mdvbf", no_argument, NULL, OPTION_DVBF},
201 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
202 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
203 { "mlock", no_argument, NULL, OPTION_LOCK},
204 { "mswape", no_argument, NULL, OPTION_SWAPE},
205 { "mrtsc", no_argument, NULL, OPTION_RTSC},
206 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
207
208 { NULL, no_argument, NULL, 0 }
209 };
210
211 size_t md_longopts_size = sizeof (md_longopts);
212
213 /* Local data and data types. */
214
215 /* Used since new relocation types are introduced in this
216 file (DUMMY_RELOC_LITUSE_*). */
217 typedef int extended_bfd_reloc_code_real_type;
218
219 struct arc_fixup
220 {
221 expressionS exp;
222
223 extended_bfd_reloc_code_real_type reloc;
224
225 /* index into arc_operands. */
226 unsigned int opindex;
227
228 /* PC-relative, used by internals fixups. */
229 unsigned char pcrel;
230
231 /* TRUE if this fixup is for LIMM operand. */
232 bfd_boolean islong;
233 };
234
235 struct arc_insn
236 {
237 unsigned int insn;
238 int nfixups;
239 struct arc_fixup fixups[MAX_INSN_FIXUPS];
240 long limm;
241 bfd_boolean short_insn; /* Boolean value: TRUE if current insn is
242 short. */
243 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
244 valid. */
245 };
246
247 /* Structure to hold any last two instructions. */
248 static struct arc_last_insn
249 {
250 /* Saved instruction opcode. */
251 const struct arc_opcode *opcode;
252
253 /* Boolean value: TRUE if current insn is short. */
254 bfd_boolean has_limm;
255
256 /* Boolean value: TRUE if current insn has delay slot. */
257 bfd_boolean has_delay_slot;
258 } arc_last_insns[2];
259
260 /* The cpu for which we are generating code. */
261 static unsigned arc_target = ARC_OPCODE_BASE;
262 static const char *arc_target_name = "<all>";
263 static unsigned arc_features = 0x00;
264
265 /* The default architecture. */
266 static int arc_mach_type = bfd_mach_arc_arcv2;
267
268 /* Non-zero if the cpu type has been explicitly specified. */
269 static int mach_type_specified_p = 0;
270
271 /* The hash table of instruction opcodes. */
272 static struct hash_control *arc_opcode_hash;
273
274 /* The hash table of register symbols. */
275 static struct hash_control *arc_reg_hash;
276
277 /* A table of CPU names and opcode sets. */
278 static const struct cpu_type
279 {
280 const char *name;
281 unsigned flags;
282 int mach;
283 unsigned eflags;
284 unsigned features;
285 }
286 cpu_types[] =
287 {
288 { "arc600", ARC_OPCODE_ARC600, bfd_mach_arc_arc600,
289 E_ARC_MACH_ARC600, 0x00},
290 { "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
291 E_ARC_MACH_ARC700, 0x00},
292 { "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
293 EF_ARC_CPU_ARCV2EM, 0x00},
294 { "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
295 EF_ARC_CPU_ARCV2HS, ARC_CD},
296 { "all", ARC_OPCODE_BASE, bfd_mach_arc_arcv2,
297 0x00, 0x00 },
298 { 0, 0, 0, 0, 0 }
299 };
300
301 struct arc_flags
302 {
303 /* Name of the parsed flag. */
304 char name[MAX_FLAG_NAME_LENGHT+1];
305
306 /* The code of the parsed flag. Valid when is not zero. */
307 unsigned char code;
308 };
309
310 /* Used by the arc_reloc_op table. Order is important. */
311 #define O_gotoff O_md1 /* @gotoff relocation. */
312 #define O_gotpc O_md2 /* @gotpc relocation. */
313 #define O_plt O_md3 /* @plt relocation. */
314 #define O_sda O_md4 /* @sda relocation. */
315 #define O_pcl O_md5 /* @pcl relocation. */
316 #define O_tlsgd O_md6 /* @tlsgd relocation. */
317 #define O_tlsie O_md7 /* @tlsie relocation. */
318 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
319 #define O_tpoff O_md9 /* @tpoff relocation. */
320 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
321 #define O_dtpoff O_md11 /* @dtpoff relocation. */
322 #define O_last O_dtpoff
323
324 /* Used to define a bracket as operand in tokens. */
325 #define O_bracket O_md32
326
327 /* Dummy relocation, to be sorted out. */
328 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
329
330 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
331
332 /* A table to map the spelling of a relocation operand into an appropriate
333 bfd_reloc_code_real_type type. The table is assumed to be ordered such
334 that op-O_literal indexes into it. */
335 #define ARC_RELOC_TABLE(op) \
336 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
337 ? (abort (), 0) \
338 : (int) (op) - (int) O_gotoff) ])
339
340 #define DEF(NAME, RELOC, REQ) \
341 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
342
343 static const struct arc_reloc_op_tag
344 {
345 /* String to lookup. */
346 const char *name;
347 /* Size of the string. */
348 size_t length;
349 /* Which operator to use. */
350 operatorT op;
351 extended_bfd_reloc_code_real_type reloc;
352 /* Allows complex relocation expression like identifier@reloc +
353 const. */
354 unsigned int complex_expr : 1;
355 }
356 arc_reloc_op[] =
357 {
358 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
359 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
360 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
361 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
362 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
363 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
364 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
365 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
366 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 0),
367 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
368 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 0),
369 };
370
371 static const int arc_num_reloc_op
372 = sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
373
374 /* Flags to set in the elf header. */
375 static flagword arc_eflag = 0x00;
376
377 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
378 symbolS * GOT_symbol = 0;
379
380 /* Set to TRUE when we assemble instructions. */
381 static bfd_boolean assembling_insn = FALSE;
382
383 /* Functions declaration. */
384
385 static void assemble_tokens (const char *, expressionS *, int,
386 struct arc_flags *, int);
387 static const struct arc_opcode *find_opcode_match (const struct arc_opcode *,
388 expressionS *, int *,
389 struct arc_flags *,
390 int, int *);
391 static void assemble_insn (const struct arc_opcode *, const expressionS *,
392 int, const struct arc_flags *, int,
393 struct arc_insn *);
394 static void emit_insn (struct arc_insn *);
395 static unsigned insert_operand (unsigned, const struct arc_operand *,
396 offsetT, char *, unsigned);
397 static const struct arc_opcode *find_special_case_flag (const char *,
398 int *,
399 struct arc_flags *);
400 static const struct arc_opcode *find_special_case (const char *,
401 int *,
402 struct arc_flags *,
403 expressionS *, int *);
404 static const struct arc_opcode *find_special_case_pseudo (const char *,
405 int *,
406 expressionS *,
407 int *,
408 struct arc_flags *);
409
410 /* Functions implementation. */
411
412 /* Like md_number_to_chars but used for limms. The 4-byte limm value,
413 is encoded as 'middle-endian' for a little-endian target. FIXME!
414 this function is used for regular 4 byte instructions as well. */
415
416 static void
417 md_number_to_chars_midend (char *buf,
418 valueT val,
419 int n)
420 {
421 if (n == 4)
422 {
423 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
424 md_number_to_chars (buf + 2, (val & 0xffff), 2);
425 }
426 else
427 {
428 md_number_to_chars (buf, val, n);
429 }
430 }
431
432 /* Here ends all the ARCompact extension instruction assembling
433 stuff. */
434
435 static void
436 arc_extra_reloc (int r_type)
437 {
438 char *sym_name, c;
439 symbolS *sym, *lab = NULL;
440
441 if (*input_line_pointer == '@')
442 input_line_pointer++;
443 c = get_symbol_name (&sym_name);
444 sym = symbol_find_or_make (sym_name);
445 restore_line_pointer (c);
446 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
447 {
448 ++input_line_pointer;
449 char *lab_name;
450 c = get_symbol_name (&lab_name);
451 lab = symbol_find_or_make (lab_name);
452 restore_line_pointer (c);
453 }
454 fixS *fixP
455 = fix_new (frag_now, /* Which frag? */
456 frag_now_fix (), /* Where in that frag? */
457 2, /* size: 1, 2, or 4 usually. */
458 sym, /* X_add_symbol. */
459 0, /* X_add_number. */
460 FALSE, /* TRUE if PC-relative relocation. */
461 r_type /* Relocation type. */);
462 fixP->fx_subsy = lab;
463 }
464
465 static symbolS *
466 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
467 symbolS *symbolP, addressT size)
468 {
469 addressT align = 0;
470 SKIP_WHITESPACE ();
471
472 if (*input_line_pointer == ',')
473 {
474 align = parse_align (1);
475
476 if (align == (addressT) -1)
477 return NULL;
478 }
479 else
480 {
481 if (size >= 8)
482 align = 3;
483 else if (size >= 4)
484 align = 2;
485 else if (size >= 2)
486 align = 1;
487 else
488 align = 0;
489 }
490
491 bss_alloc (symbolP, size, align);
492 S_CLEAR_EXTERNAL (symbolP);
493
494 return symbolP;
495 }
496
497 static void
498 arc_lcomm (int ignore)
499 {
500 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
501
502 if (symbolP)
503 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
504 }
505
506 /* Select the cpu we're assembling for. */
507
508 static void
509 arc_option (int ignore ATTRIBUTE_UNUSED)
510 {
511 int mach = -1;
512 char c;
513 char *cpu;
514
515 c = get_symbol_name (&cpu);
516 mach = arc_get_mach (cpu);
517 restore_line_pointer (c);
518
519 if (mach == -1)
520 goto bad_cpu;
521
522 if (!mach_type_specified_p)
523 {
524 arc_mach_type = mach;
525 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
526 as_fatal ("could not set architecture and machine");
527
528 mach_type_specified_p = 1;
529 }
530 else
531 if (arc_mach_type != mach)
532 as_warn ("Command-line value overrides \".cpu\" directive");
533
534 demand_empty_rest_of_line ();
535
536 return;
537
538 bad_cpu:
539 as_bad ("invalid identifier for \".cpu\"");
540 ignore_rest_of_line ();
541 }
542
543 /* Smartly print an expression. */
544
545 static void
546 debug_exp (expressionS *t)
547 {
548 const char *name ATTRIBUTE_UNUSED;
549 const char *namemd ATTRIBUTE_UNUSED;
550
551 pr_debug ("debug_exp: ");
552
553 switch (t->X_op)
554 {
555 default: name = "unknown"; break;
556 case O_illegal: name = "O_illegal"; break;
557 case O_absent: name = "O_absent"; break;
558 case O_constant: name = "O_constant"; break;
559 case O_symbol: name = "O_symbol"; break;
560 case O_symbol_rva: name = "O_symbol_rva"; break;
561 case O_register: name = "O_register"; break;
562 case O_big: name = "O_big"; break;
563 case O_uminus: name = "O_uminus"; break;
564 case O_bit_not: name = "O_bit_not"; break;
565 case O_logical_not: name = "O_logical_not"; break;
566 case O_multiply: name = "O_multiply"; break;
567 case O_divide: name = "O_divide"; break;
568 case O_modulus: name = "O_modulus"; break;
569 case O_left_shift: name = "O_left_shift"; break;
570 case O_right_shift: name = "O_right_shift"; break;
571 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
572 case O_bit_or_not: name = "O_bit_or_not"; break;
573 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
574 case O_bit_and: name = "O_bit_and"; break;
575 case O_add: name = "O_add"; break;
576 case O_subtract: name = "O_subtract"; break;
577 case O_eq: name = "O_eq"; break;
578 case O_ne: name = "O_ne"; break;
579 case O_lt: name = "O_lt"; break;
580 case O_le: name = "O_le"; break;
581 case O_ge: name = "O_ge"; break;
582 case O_gt: name = "O_gt"; break;
583 case O_logical_and: name = "O_logical_and"; break;
584 case O_logical_or: name = "O_logical_or"; break;
585 case O_index: name = "O_index"; break;
586 case O_bracket: name = "O_bracket"; break;
587 }
588
589 switch (t->X_md)
590 {
591 default: namemd = "unknown"; break;
592 case O_gotoff: namemd = "O_gotoff"; break;
593 case O_gotpc: namemd = "O_gotpc"; break;
594 case O_plt: namemd = "O_plt"; break;
595 case O_sda: namemd = "O_sda"; break;
596 case O_pcl: namemd = "O_pcl"; break;
597 case O_tlsgd: namemd = "O_tlsgd"; break;
598 case O_tlsie: namemd = "O_tlsie"; break;
599 case O_tpoff9: namemd = "O_tpoff9"; break;
600 case O_tpoff: namemd = "O_tpoff"; break;
601 case O_dtpoff9: namemd = "O_dtpoff9"; break;
602 case O_dtpoff: namemd = "O_dtpoff"; break;
603 }
604
605 pr_debug ("%s (%s, %s, %d, %s)", name,
606 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
607 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
608 (int) t->X_add_number,
609 (t->X_md) ? namemd : "--");
610 pr_debug ("\n");
611 fflush (stderr);
612 }
613
614 /* Parse the arguments to an opcode. */
615
616 static int
617 tokenize_arguments (char *str,
618 expressionS *tok,
619 int ntok)
620 {
621 char *old_input_line_pointer;
622 bfd_boolean saw_comma = FALSE;
623 bfd_boolean saw_arg = FALSE;
624 int brk_lvl = 0;
625 int num_args = 0;
626 const char *p;
627 int i;
628 size_t len;
629 const struct arc_reloc_op_tag *r;
630 expressionS tmpE;
631
632 memset (tok, 0, sizeof (*tok) * ntok);
633
634 /* Save and restore input_line_pointer around this function. */
635 old_input_line_pointer = input_line_pointer;
636 input_line_pointer = str;
637
638 while (*input_line_pointer)
639 {
640 SKIP_WHITESPACE ();
641 switch (*input_line_pointer)
642 {
643 case '\0':
644 goto fini;
645
646 case ',':
647 input_line_pointer++;
648 if (saw_comma || !saw_arg)
649 goto err;
650 saw_comma = TRUE;
651 break;
652
653 case '}':
654 case ']':
655 ++input_line_pointer;
656 --brk_lvl;
657 if (!saw_arg)
658 goto err;
659 tok->X_op = O_bracket;
660 ++tok;
661 ++num_args;
662 break;
663
664 case '{':
665 case '[':
666 input_line_pointer++;
667 if (brk_lvl)
668 goto err;
669 ++brk_lvl;
670 tok->X_op = O_bracket;
671 ++tok;
672 ++num_args;
673 break;
674
675 case '@':
676 /* We have labels, function names and relocations, all
677 starting with @ symbol. Sort them out. */
678 if (saw_arg && !saw_comma)
679 goto err;
680
681 /* Parse @label. */
682 tok->X_op = O_symbol;
683 tok->X_md = O_absent;
684 expression (tok);
685 if (*input_line_pointer != '@')
686 goto normalsymbol; /* This is not a relocation. */
687
688 /* A relocation opernad has the following form
689 @identifier@relocation_type. The identifier is already
690 in tok! */
691 if (tok->X_op != O_symbol)
692 {
693 as_bad (_("No valid label relocation operand"));
694 goto err;
695 }
696
697 /* Parse @relocation_type. */
698 memset (&tmpE, 0, sizeof (tmpE));
699 tmpE.X_op = O_symbol;
700 expression (&tmpE);
701
702 if (tmpE.X_op != O_symbol)
703 {
704 as_bad (_("No relocation operand"));
705 goto err;
706 }
707 p = S_GET_NAME (tmpE.X_add_symbol);
708 len = strlen (p);
709
710 /* Go through known relocation and try to find a match. */
711 r = &arc_reloc_op[0];
712 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
713 if (len == r->length && memcmp (p, r->name, len) == 0)
714 break;
715
716 if (i < 0)
717 {
718 as_bad (_("Unknown relocation operand: @%s"), p);
719 goto err;
720 }
721 tok->X_md = r->op;
722 tok->X_add_number = tmpE.X_add_number;
723 if (tmpE.X_add_number && !r->complex_expr)
724 {
725 as_bad (_("Complex relocation operand."));
726 goto err;
727 }
728
729 /* Extra check for TLS: base. */
730 if (*input_line_pointer == '@')
731 {
732 symbolS *base;
733 if (tok->X_op_symbol != NULL
734 || tok->X_op != O_symbol)
735 {
736 as_bad (_("Unable to parse this reloc"));
737 goto err;
738 }
739 input_line_pointer++;
740 char *sym_name;
741 char c = get_symbol_name (&sym_name);
742 base = symbol_find_or_make (sym_name);
743 tok->X_op = O_subtract;
744 tok->X_op_symbol = base;
745 restore_line_pointer (c);
746 }
747
748 debug_exp (tok);
749
750 saw_comma = FALSE;
751 saw_arg = TRUE;
752 tok++;
753 num_args++;
754 break;
755
756 case '%':
757 /* Can be a register. */
758 ++input_line_pointer;
759 /* Fall through. */
760 default:
761
762 if (saw_arg && !saw_comma)
763 goto err;
764
765 tok->X_op = O_absent;
766 expression (tok);
767
768 normalsymbol:
769 debug_exp (tok);
770
771 if (tok->X_op == O_illegal || tok->X_op == O_absent)
772 goto err;
773
774 saw_comma = FALSE;
775 saw_arg = TRUE;
776 tok++;
777 num_args++;
778 break;
779 }
780 }
781
782 fini:
783 if (saw_comma || brk_lvl)
784 goto err;
785 input_line_pointer = old_input_line_pointer;
786
787 return num_args;
788
789 err:
790 if (brk_lvl)
791 as_bad (_("Brackets in operand field incorrect"));
792 else if (saw_comma)
793 as_bad (_("extra comma"));
794 else if (!saw_arg)
795 as_bad (_("missing argument"));
796 else
797 as_bad (_("missing comma or colon"));
798 input_line_pointer = old_input_line_pointer;
799 return -1;
800 }
801
802 /* Parse the flags to a structure. */
803
804 static int
805 tokenize_flags (const char *str,
806 struct arc_flags flags[],
807 int nflg)
808 {
809 char *old_input_line_pointer;
810 bfd_boolean saw_flg = FALSE;
811 bfd_boolean saw_dot = FALSE;
812 int num_flags = 0;
813 size_t flgnamelen;
814
815 memset (flags, 0, sizeof (*flags) * nflg);
816
817 /* Save and restore input_line_pointer around this function. */
818 old_input_line_pointer = input_line_pointer;
819 input_line_pointer = (char *) str;
820
821 while (*input_line_pointer)
822 {
823 switch (*input_line_pointer)
824 {
825 case ' ':
826 case '\0':
827 goto fini;
828
829 case '.':
830 input_line_pointer++;
831 if (saw_dot)
832 goto err;
833 saw_dot = TRUE;
834 saw_flg = FALSE;
835 break;
836
837 default:
838 if (saw_flg && !saw_dot)
839 goto err;
840
841 if (num_flags >= nflg)
842 goto err;
843
844 flgnamelen = strspn (input_line_pointer, "abcdefghilmnopqrstvwxz");
845 if (flgnamelen > MAX_FLAG_NAME_LENGHT)
846 goto err;
847
848 memcpy (flags->name, input_line_pointer, flgnamelen);
849
850 input_line_pointer += flgnamelen;
851 flags++;
852 saw_dot = FALSE;
853 saw_flg = TRUE;
854 num_flags++;
855 break;
856 }
857 }
858
859 fini:
860 input_line_pointer = old_input_line_pointer;
861 return num_flags;
862
863 err:
864 if (saw_dot)
865 as_bad (_("extra dot"));
866 else if (!saw_flg)
867 as_bad (_("unrecognized flag"));
868 else
869 as_bad (_("failed to parse flags"));
870 input_line_pointer = old_input_line_pointer;
871 return -1;
872 }
873
874 /* The public interface to the instruction assembler. */
875
876 void
877 md_assemble (char *str)
878 {
879 char *opname;
880 expressionS tok[MAX_INSN_ARGS];
881 int ntok, nflg;
882 size_t opnamelen;
883 struct arc_flags flags[MAX_INSN_FLGS];
884
885 /* Split off the opcode. */
886 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
887 opname = xmalloc (opnamelen + 1);
888 memcpy (opname, str, opnamelen);
889 opname[opnamelen] = '\0';
890
891 /* Signalize we are assmbling the instructions. */
892 assembling_insn = TRUE;
893
894 /* Tokenize the flags. */
895 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
896 {
897 as_bad (_("syntax error"));
898 return;
899 }
900
901 /* Scan up to the end of the mnemonic which must end in space or end
902 of string. */
903 str += opnamelen;
904 for (; *str != '\0'; str++)
905 if (*str == ' ')
906 break;
907
908 /* Tokenize the rest of the line. */
909 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
910 {
911 as_bad (_("syntax error"));
912 return;
913 }
914
915 /* Finish it off. */
916 assemble_tokens (opname, tok, ntok, flags, nflg);
917 assembling_insn = FALSE;
918 }
919
920 /* Callback to insert a register into the hash table. */
921
922 static void
923 declare_register (char *name, int number)
924 {
925 const char *err;
926 symbolS *regS = symbol_create (name, reg_section,
927 number, &zero_address_frag);
928
929 err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
930 if (err)
931 as_fatal ("Inserting \"%s\" into register table failed: %s",
932 name, err);
933 }
934
935 /* Construct symbols for each of the general registers. */
936
937 static void
938 declare_register_set (void)
939 {
940 int i;
941 for (i = 0; i < 32; ++i)
942 {
943 char name[7];
944
945 sprintf (name, "r%d", i);
946 declare_register (name, i);
947 if ((i & 0x01) == 0)
948 {
949 sprintf (name, "r%dr%d", i, i+1);
950 declare_register (name, i);
951 }
952 }
953 }
954
955 /* Port-specific assembler initialization. This function is called
956 once, at assembler startup time. */
957
958 void
959 md_begin (void)
960 {
961 unsigned int i;
962
963 /* The endianness can be chosen "at the factory". */
964 target_big_endian = byte_order == BIG_ENDIAN;
965
966 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type))
967 as_warn (_("could not set architecture and machine"));
968
969 /* Set elf header flags. */
970 bfd_set_private_flags (stdoutput, arc_eflag);
971
972 /* Set up a hash table for the instructions. */
973 arc_opcode_hash = hash_new ();
974 if (arc_opcode_hash == NULL)
975 as_fatal (_("Virtual memory exhausted"));
976
977 /* Initialize the hash table with the insns. */
978 for (i = 0; i < arc_num_opcodes;)
979 {
980 const char *name, *retval;
981
982 name = arc_opcodes[i].name;
983 retval = hash_insert (arc_opcode_hash, name, (void *) &arc_opcodes[i]);
984 if (retval)
985 as_fatal (_("internal error: can't hash opcode '%s': %s"),
986 name, retval);
987
988 while (++i < arc_num_opcodes
989 && (arc_opcodes[i].name == name
990 || !strcmp (arc_opcodes[i].name, name)))
991 continue;
992 }
993
994 /* Register declaration. */
995 arc_reg_hash = hash_new ();
996 if (arc_reg_hash == NULL)
997 as_fatal (_("Virtual memory exhausted"));
998
999 declare_register_set ();
1000 declare_register ("gp", 26);
1001 declare_register ("fp", 27);
1002 declare_register ("sp", 28);
1003 declare_register ("ilink", 29);
1004 declare_register ("ilink1", 29);
1005 declare_register ("ilink2", 30);
1006 declare_register ("blink", 31);
1007
1008 declare_register ("mlo", 57);
1009 declare_register ("mmid", 58);
1010 declare_register ("mhi", 59);
1011
1012 declare_register ("acc1", 56);
1013 declare_register ("acc2", 57);
1014
1015 declare_register ("lp_count", 60);
1016 declare_register ("pcl", 63);
1017
1018 /* Initialize the last instructions. */
1019 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
1020 }
1021
1022 /* Write a value out to the object file, using the appropriate
1023 endianness. */
1024
1025 void
1026 md_number_to_chars (char *buf,
1027 valueT val,
1028 int n)
1029 {
1030 if (target_big_endian)
1031 number_to_chars_bigendian (buf, val, n);
1032 else
1033 number_to_chars_littleendian (buf, val, n);
1034 }
1035
1036 /* Round up a section size to the appropriate boundary. */
1037
1038 valueT
1039 md_section_align (segT segment,
1040 valueT size)
1041 {
1042 int align = bfd_get_section_alignment (stdoutput, segment);
1043
1044 return ((size + (1 << align) - 1) & (-1 << align));
1045 }
1046
1047 /* The location from which a PC relative jump should be calculated,
1048 given a PC relative reloc. */
1049
1050 long
1051 md_pcrel_from_section (fixS *fixP,
1052 segT sec)
1053 {
1054 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
1055
1056 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
1057
1058 if (fixP->fx_addsy != (symbolS *) NULL
1059 && (!S_IS_DEFINED (fixP->fx_addsy)
1060 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1061 {
1062 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
1063
1064 /* The symbol is undefined (or is defined but not in this section).
1065 Let the linker figure it out. */
1066 return 0;
1067 }
1068
1069 if ((int) fixP->fx_r_type < 0)
1070 {
1071 /* These are the "internal" relocations. Align them to
1072 32 bit boundary (PCL), for the moment. */
1073 base &= ~3;
1074 }
1075 else
1076 {
1077 switch (fixP->fx_r_type)
1078 {
1079 case BFD_RELOC_ARC_PC32:
1080 /* The hardware calculates relative to the start of the
1081 insn, but this relocation is relative to location of the
1082 LIMM, compensate. TIP: the base always needs to be
1083 substracted by 4 as we do not support this type of PCrel
1084 relocation for short instructions. */
1085 base -= fixP->fx_where - fixP->fx_dot_value;
1086 gas_assert ((fixP->fx_where - fixP->fx_dot_value) == 4);
1087 /* Fall through. */
1088 case BFD_RELOC_ARC_PLT32:
1089 case BFD_RELOC_ARC_S25H_PCREL_PLT:
1090 case BFD_RELOC_ARC_S21H_PCREL_PLT:
1091 case BFD_RELOC_ARC_S25W_PCREL_PLT:
1092 case BFD_RELOC_ARC_S21W_PCREL_PLT:
1093
1094 case BFD_RELOC_ARC_S21H_PCREL:
1095 case BFD_RELOC_ARC_S25H_PCREL:
1096 case BFD_RELOC_ARC_S13_PCREL:
1097 case BFD_RELOC_ARC_S21W_PCREL:
1098 case BFD_RELOC_ARC_S25W_PCREL:
1099 base &= ~3;
1100 break;
1101 default:
1102 as_bad_where (fixP->fx_file, fixP->fx_line,
1103 _("unhandled reloc %s in md_pcrel_from_section"),
1104 bfd_get_reloc_code_name (fixP->fx_r_type));
1105 break;
1106 }
1107 }
1108
1109 pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n",
1110 fixP->fx_frag->fr_address, fixP->fx_where, base,
1111 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
1112 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
1113
1114 return base;
1115 }
1116
1117 /* Given a BFD relocation find the coresponding operand. */
1118
1119 static const struct arc_operand *
1120 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
1121 {
1122 unsigned i;
1123
1124 for (i = 0; i < arc_num_operands; i++)
1125 if (arc_operands[i].default_reloc == reloc)
1126 return &arc_operands[i];
1127 return NULL;
1128 }
1129
1130 /* Apply a fixup to the object code. At this point all symbol values
1131 should be fully resolved, and we attempt to completely resolve the
1132 reloc. If we can not do that, we determine the correct reloc code
1133 and put it back in the fixup. To indicate that a fixup has been
1134 eliminated, set fixP->fx_done. */
1135
1136 void
1137 md_apply_fix (fixS *fixP,
1138 valueT *valP,
1139 segT seg)
1140 {
1141 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
1142 valueT value = *valP;
1143 unsigned insn = 0;
1144 symbolS *fx_addsy, *fx_subsy;
1145 offsetT fx_offset;
1146 segT add_symbol_segment = absolute_section;
1147 segT sub_symbol_segment = absolute_section;
1148 const struct arc_operand *operand = NULL;
1149 extended_bfd_reloc_code_real_type reloc;
1150
1151 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
1152 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
1153 ((int) fixP->fx_r_type < 0) ? "Internal":
1154 bfd_get_reloc_code_name (fixP->fx_r_type), value,
1155 fixP->fx_offset);
1156
1157 fx_addsy = fixP->fx_addsy;
1158 fx_subsy = fixP->fx_subsy;
1159 fx_offset = 0;
1160
1161 if (fx_addsy)
1162 {
1163 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
1164 }
1165
1166 if (fx_subsy
1167 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
1168 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
1169 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
1170 {
1171 resolve_symbol_value (fx_subsy);
1172 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
1173
1174 if (sub_symbol_segment == absolute_section)
1175 {
1176 /* The symbol is really a constant. */
1177 fx_offset -= S_GET_VALUE (fx_subsy);
1178 fx_subsy = NULL;
1179 }
1180 else
1181 {
1182 as_bad_where (fixP->fx_file, fixP->fx_line,
1183 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
1184 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
1185 segment_name (add_symbol_segment),
1186 S_GET_NAME (fx_subsy),
1187 segment_name (sub_symbol_segment));
1188 return;
1189 }
1190 }
1191
1192 if (fx_addsy
1193 && !S_IS_WEAK (fx_addsy))
1194 {
1195 if (add_symbol_segment == seg
1196 && fixP->fx_pcrel)
1197 {
1198 value += S_GET_VALUE (fx_addsy);
1199 value -= md_pcrel_from_section (fixP, seg);
1200 fx_addsy = NULL;
1201 fixP->fx_pcrel = FALSE;
1202 }
1203 else if (add_symbol_segment == absolute_section)
1204 {
1205 value = fixP->fx_offset;
1206 fx_offset += S_GET_VALUE (fixP->fx_addsy);
1207 fx_addsy = NULL;
1208 fixP->fx_pcrel = FALSE;
1209 }
1210 }
1211
1212 if (!fx_addsy)
1213 fixP->fx_done = TRUE;
1214
1215 if (fixP->fx_pcrel)
1216 {
1217 if (fx_addsy
1218 && ((S_IS_DEFINED (fx_addsy)
1219 && S_GET_SEGMENT (fx_addsy) != seg)
1220 || S_IS_WEAK (fx_addsy)))
1221 value += md_pcrel_from_section (fixP, seg);
1222
1223 switch (fixP->fx_r_type)
1224 {
1225 case BFD_RELOC_ARC_32_ME:
1226 /* This is a pc-relative value in a LIMM. Adjust it to the
1227 address of the instruction not to the address of the
1228 LIMM. Note: it is not anylonger valid this afirmation as
1229 the linker consider ARC_PC32 a fixup to entire 64 bit
1230 insn. */
1231 fixP->fx_offset += fixP->fx_frag->fr_address;
1232 /* Fall through. */
1233 case BFD_RELOC_32:
1234 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
1235 /* Fall through. */
1236 case BFD_RELOC_ARC_PC32:
1237 break;
1238 default:
1239 if ((int) fixP->fx_r_type < 0)
1240 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
1241 fixP->fx_r_type);
1242 break;
1243 }
1244 }
1245
1246 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
1247 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
1248 ((int) fixP->fx_r_type < 0) ? "Internal":
1249 bfd_get_reloc_code_name (fixP->fx_r_type), value,
1250 fixP->fx_offset);
1251
1252 if (!fixP->fx_done)
1253 return;
1254
1255 /* Addjust the value if we have a constant. */
1256 value += fx_offset;
1257
1258 /* For hosts with longs bigger than 32-bits make sure that the top
1259 bits of a 32-bit negative value read in by the parser are set,
1260 so that the correct comparisons are made. */
1261 if (value & 0x80000000)
1262 value |= (-1L << 31);
1263
1264 reloc = fixP->fx_r_type;
1265 switch (reloc)
1266 {
1267 case BFD_RELOC_8:
1268 case BFD_RELOC_16:
1269 case BFD_RELOC_24:
1270 case BFD_RELOC_32:
1271 case BFD_RELOC_64:
1272 md_number_to_chars (fixpos, value, fixP->fx_size);
1273 return;
1274
1275 case BFD_RELOC_ARC_GOTPC32:
1276 /* I cannot fix an GOTPC relocation because I need to relax it
1277 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
1278 as_bad (_("Unsupported operation on reloc"));
1279 return;
1280 case BFD_RELOC_ARC_GOTOFF:
1281 case BFD_RELOC_ARC_32_ME:
1282 case BFD_RELOC_ARC_PC32:
1283 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
1284 return;
1285
1286 case BFD_RELOC_ARC_PLT32:
1287 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
1288 return;
1289
1290 case BFD_RELOC_ARC_S25H_PCREL_PLT:
1291 reloc = BFD_RELOC_ARC_S25W_PCREL;
1292 goto solve_plt;
1293
1294 case BFD_RELOC_ARC_S21H_PCREL_PLT:
1295 reloc = BFD_RELOC_ARC_S21H_PCREL;
1296 goto solve_plt;
1297
1298 case BFD_RELOC_ARC_S25W_PCREL_PLT:
1299 reloc = BFD_RELOC_ARC_S25W_PCREL;
1300 goto solve_plt;
1301
1302 case BFD_RELOC_ARC_S21W_PCREL_PLT:
1303 reloc = BFD_RELOC_ARC_S21W_PCREL;
1304
1305 case BFD_RELOC_ARC_S25W_PCREL:
1306 case BFD_RELOC_ARC_S21W_PCREL:
1307 case BFD_RELOC_ARC_S21H_PCREL:
1308 case BFD_RELOC_ARC_S25H_PCREL:
1309 case BFD_RELOC_ARC_S13_PCREL:
1310 solve_plt:
1311 operand = find_operand_for_reloc (reloc);
1312 gas_assert (operand);
1313 break;
1314
1315 case BFD_RELOC_ARC_TLS_DTPOFF:
1316 case BFD_RELOC_ARC_TLS_LE_32:
1317 if (fixP->fx_done)
1318 {
1319 gas_assert (!fixP->fx_addsy);
1320 gas_assert (!fixP->fx_subsy);
1321 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
1322 return;
1323 }
1324 else
1325 {
1326 value = fixP->fx_offset;
1327 fixP->fx_offset = 0;
1328 }
1329 /* Fall through. */
1330 case BFD_RELOC_ARC_TLS_GD_GOT:
1331 case BFD_RELOC_ARC_TLS_IE_GOT:
1332 S_SET_THREAD_LOCAL (fixP->fx_addsy);
1333 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
1334 return;
1335
1336 case BFD_RELOC_ARC_TLS_GD_LD:
1337 gas_assert (!fixP->fx_offset);
1338 if (fixP->fx_subsy)
1339 fixP->fx_offset
1340 = (S_GET_VALUE (fixP->fx_subsy)
1341 - fixP->fx_frag->fr_address- fixP->fx_where);
1342 fixP->fx_subsy = NULL;
1343 /* Fall through. */
1344 case BFD_RELOC_ARC_TLS_GD_CALL:
1345 /* These two relocs are there just to allow ld to change the tls
1346 model for this symbol, by patching the code. */
1347 /* Fall through. */
1348 /* The offset - and scale, if any - will be installed by the
1349 linker. */
1350 gas_assert (!fixP->fx_done);
1351 S_SET_THREAD_LOCAL (fixP->fx_addsy);
1352 return;
1353
1354 case BFD_RELOC_ARC_TLS_LE_S9:
1355 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
1356 as_bad (_("TLS_*_S9 relocs are not supported yet"));
1357 break;
1358
1359 default:
1360 {
1361 if ((int) fixP->fx_r_type >= 0)
1362 as_fatal (_("unhandled relocation type %s"),
1363 bfd_get_reloc_code_name (fixP->fx_r_type));
1364
1365 /* The rest of these fixups needs to be completely resolved as
1366 constants. */
1367 if (fixP->fx_addsy != 0
1368 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
1369 as_bad_where (fixP->fx_file, fixP->fx_line,
1370 _("non-absolute expression in constant field"));
1371
1372 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
1373 operand = &arc_operands[-(int) fixP->fx_r_type];
1374 break;
1375 }
1376 }
1377
1378 if (target_big_endian)
1379 {
1380 switch (fixP->fx_size)
1381 {
1382 case 4:
1383 insn = bfd_getb32 (fixpos);
1384 break;
1385 case 2:
1386 insn = bfd_getb16 (fixpos);
1387 break;
1388 default:
1389 as_bad_where (fixP->fx_file, fixP->fx_line,
1390 _("unknown fixup size"));
1391 }
1392 }
1393 else
1394 {
1395 insn = 0;
1396 switch (fixP->fx_size)
1397 {
1398 case 4:
1399 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
1400 break;
1401 case 2:
1402 insn = bfd_getl16 (fixpos);
1403 break;
1404 default:
1405 as_bad_where (fixP->fx_file, fixP->fx_line,
1406 _("unknown fixup size"));
1407 }
1408 }
1409
1410 insn = insert_operand (insn, operand, (offsetT) value,
1411 fixP->fx_file, fixP->fx_line);
1412
1413 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
1414 }
1415
1416 /* Prepare machine-dependent frags for relaxation.
1417
1418 Called just before relaxation starts. Any symbol that is now undefined
1419 will not become defined.
1420
1421 Return the correct fr_subtype in the frag.
1422
1423 Return the initial "guess for fr_var" to caller. The guess for fr_var
1424 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
1425 or fr_var contributes to our returned value.
1426
1427 Although it may not be explicit in the frag, pretend
1428 fr_var starts with a value. */
1429
1430 int
1431 md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,
1432 segT segment ATTRIBUTE_UNUSED)
1433 {
1434 int growth = 4;
1435
1436 fragP->fr_var = 4;
1437 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
1438 fragP->fr_file, fragP->fr_line, growth);
1439
1440 as_fatal (_("md_estimate_size_before_relax\n"));
1441 return growth;
1442 }
1443
1444 /* Translate internal representation of relocation info to BFD target
1445 format. */
1446
1447 arelent *
1448 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
1449 fixS *fixP)
1450 {
1451 arelent *reloc;
1452 bfd_reloc_code_real_type code;
1453
1454 reloc = (arelent *) xmalloc (sizeof (* reloc));
1455 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1456 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
1457 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
1458
1459 /* Make sure none of our internal relocations make it this far.
1460 They'd better have been fully resolved by this point. */
1461 gas_assert ((int) fixP->fx_r_type > 0);
1462
1463 code = fixP->fx_r_type;
1464
1465 /* if we have something like add gp, pcl,
1466 _GLOBAL_OFFSET_TABLE_@gotpc. */
1467 if (code == BFD_RELOC_ARC_GOTPC32
1468 && GOT_symbol
1469 && fixP->fx_addsy == GOT_symbol)
1470 code = BFD_RELOC_ARC_GOTPC;
1471
1472 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1473 if (reloc->howto == NULL)
1474 {
1475 as_bad_where (fixP->fx_file, fixP->fx_line,
1476 _("cannot represent `%s' relocation in object file"),
1477 bfd_get_reloc_code_name (code));
1478 return NULL;
1479 }
1480
1481 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
1482 as_fatal (_("internal error? cannot generate `%s' relocation"),
1483 bfd_get_reloc_code_name (code));
1484
1485 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
1486
1487 if (code == BFD_RELOC_ARC_TLS_DTPOFF
1488 || code == BFD_RELOC_ARC_TLS_DTPOFF_S9)
1489 {
1490 asymbol *sym
1491 = fixP->fx_subsy ? symbol_get_bfdsym (fixP->fx_subsy) : NULL;
1492 /* We just want to store a 24 bit index, but we have to wait
1493 till after write_contents has been called via
1494 bfd_map_over_sections before we can get the index from
1495 _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs
1496 function is elf32-arc.c has to pick up the slack.
1497 Unfortunately, this leads to problems with hosts that have
1498 pointers wider than long (bfd_vma). There would be various
1499 ways to handle this, all error-prone :-( */
1500 reloc->addend = (bfd_vma) sym;
1501 if ((asymbol *) reloc->addend != sym)
1502 {
1503 as_bad ("Can't store pointer\n");
1504 return NULL;
1505 }
1506 }
1507 else
1508 reloc->addend = fixP->fx_offset;
1509
1510 return reloc;
1511 }
1512
1513 /* Perform post-processing of machine-dependent frags after relaxation.
1514 Called after relaxation is finished.
1515 In: Address of frag.
1516 fr_type == rs_machine_dependent.
1517 fr_subtype is what the address relaxed to.
1518
1519 Out: Any fixS:s and constants are set up. */
1520
1521 void
1522 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
1523 segT segment ATTRIBUTE_UNUSED,
1524 fragS *fragP ATTRIBUTE_UNUSED)
1525 {
1526 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n",
1527 fragP->fr_file, fragP->fr_line,
1528 fragP->fr_subtype, fragP->fr_fix, fragP->fr_var);
1529 abort ();
1530 }
1531
1532 /* We have no need to default values of symbols. We could catch
1533 register names here, but that is handled by inserting them all in
1534 the symbol table to begin with. */
1535
1536 symbolS *
1537 md_undefined_symbol (char *name)
1538 {
1539 /* The arc abi demands that a GOT[0] should be referencible as
1540 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
1541 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
1542 if (((*name == '_')
1543 && (*(name+1) == 'G')
1544 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0))
1545 || ((*name == '_')
1546 && (*(name+1) == 'D')
1547 && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0)))
1548 {
1549 if (!GOT_symbol)
1550 {
1551 if (symbol_find (name))
1552 as_bad ("GOT already in symbol table");
1553
1554 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
1555 (valueT) 0, &zero_address_frag);
1556 };
1557 return GOT_symbol;
1558 }
1559 return NULL;
1560 }
1561
1562 /* Turn a string in input_line_pointer into a floating point constant
1563 of type type, and store the appropriate bytes in *litP. The number
1564 of LITTLENUMS emitted is stored in *sizeP. An error message is
1565 returned, or NULL on OK. */
1566
1567 char *
1568 md_atof (int type, char *litP, int *sizeP)
1569 {
1570 return ieee_md_atof (type, litP, sizeP, target_big_endian);
1571 }
1572
1573 /* Called for any expression that can not be recognized. When the
1574 function is called, `input_line_pointer' will point to the start of
1575 the expression. */
1576
1577 void
1578 md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
1579 {
1580 char *p = input_line_pointer;
1581 if (*p == '@')
1582 {
1583 input_line_pointer++;
1584 expressionP->X_op = O_symbol;
1585 expression (expressionP);
1586 }
1587 }
1588
1589 /* This function is called from the function 'expression', it attempts
1590 to parse special names (in our case register names). It fills in
1591 the expression with the identified register. It returns TRUE if
1592 it is a register and FALSE otherwise. */
1593
1594 bfd_boolean
1595 arc_parse_name (const char *name,
1596 struct expressionS *e)
1597 {
1598 struct symbol *sym;
1599
1600 if (!assembling_insn)
1601 return FALSE;
1602
1603 /* Handle only registers. */
1604 if (e->X_op != O_absent)
1605 return FALSE;
1606
1607 sym = hash_find (arc_reg_hash, name);
1608 if (sym)
1609 {
1610 e->X_op = O_register;
1611 e->X_add_number = S_GET_VALUE (sym);
1612 return TRUE;
1613 }
1614 return FALSE;
1615 }
1616
1617 /* md_parse_option
1618 Invocation line includes a switch not recognized by the base assembler.
1619 See if it's a processor-specific option.
1620
1621 New options (supported) are:
1622
1623 -mcpu=<cpu name> Assemble for selected processor
1624 -EB/-mbig-endian Big-endian
1625 -EL/-mlittle-endian Little-endian
1626
1627 The following CPU names are recognized:
1628 arc700, av2em, av2hs. */
1629
1630 int
1631 md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
1632 {
1633 int cpu_flags = EF_ARC_CPU_GENERIC;
1634
1635 switch (c)
1636 {
1637 case OPTION_ARC600:
1638 case OPTION_ARC601:
1639 return md_parse_option (OPTION_MCPU, "arc600");
1640
1641 case OPTION_ARC700:
1642 return md_parse_option (OPTION_MCPU, "arc700");
1643
1644 case OPTION_ARCEM:
1645 return md_parse_option (OPTION_MCPU, "arcem");
1646
1647 case OPTION_ARCHS:
1648 return md_parse_option (OPTION_MCPU, "archs");
1649
1650 case OPTION_MCPU:
1651 {
1652 int i;
1653 char *s = alloca (strlen (arg) + 1);
1654
1655 {
1656 char *t = s;
1657 char *arg1 = arg;
1658
1659 do
1660 *t = TOLOWER (*arg1++);
1661 while (*t++);
1662 }
1663
1664 for (i = 0; cpu_types[i].name; ++i)
1665 {
1666 if (!strcmp (cpu_types[i].name, s))
1667 {
1668 arc_target = cpu_types[i].flags;
1669 arc_target_name = cpu_types[i].name;
1670 arc_features = cpu_types[i].features;
1671 arc_mach_type = cpu_types[i].mach;
1672 cpu_flags = cpu_types[i].eflags;
1673
1674 mach_type_specified_p = 1;
1675 break;
1676 }
1677 }
1678
1679 if (!cpu_types[i].name)
1680 {
1681 as_fatal (_("unknown architecture: %s\n"), arg);
1682 }
1683 break;
1684 }
1685
1686 case OPTION_EB:
1687 arc_target_format = "elf32-bigarc";
1688 byte_order = BIG_ENDIAN;
1689 break;
1690
1691 case OPTION_EL:
1692 arc_target_format = "elf32-littlearc";
1693 byte_order = LITTLE_ENDIAN;
1694 break;
1695
1696 case OPTION_CD:
1697 /* This option has an effect only on ARC EM. */
1698 if (arc_target & ARC_OPCODE_ARCv2EM)
1699 arc_features |= ARC_CD;
1700 break;
1701
1702 case OPTION_USER_MODE:
1703 case OPTION_LD_EXT_MASK:
1704 case OPTION_SWAP:
1705 case OPTION_NORM:
1706 case OPTION_BARREL_SHIFT:
1707 case OPTION_MIN_MAX:
1708 case OPTION_NO_MPY:
1709 case OPTION_EA:
1710 case OPTION_MUL64:
1711 case OPTION_SIMD:
1712 case OPTION_SPFP:
1713 case OPTION_DPFP:
1714 case OPTION_XMAC_D16:
1715 case OPTION_XMAC_24:
1716 case OPTION_DSP_PACKA:
1717 case OPTION_CRC:
1718 case OPTION_DVBF:
1719 case OPTION_TELEPHONY:
1720 case OPTION_XYMEMORY:
1721 case OPTION_LOCK:
1722 case OPTION_SWAPE:
1723 case OPTION_RTSC:
1724 case OPTION_FPUDA:
1725 /* Dummy options. */
1726
1727 default:
1728 return 0;
1729 }
1730
1731 if (cpu_flags != EF_ARC_CPU_GENERIC)
1732 arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
1733
1734 return 1;
1735 }
1736
1737 void
1738 md_show_usage (FILE *stream)
1739 {
1740 fprintf (stream, _("ARC-specific assembler options:\n"));
1741
1742 fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n");
1743 fprintf (stream,
1744 " -mcode-density\t enable code density option for ARC EM\n");
1745
1746 fprintf (stream, _("\
1747 -EB assemble code for a big-endian cpu\n"));
1748 fprintf (stream, _("\
1749 -EL assemble code for a little-endian cpu\n"));
1750 }
1751
1752 static void
1753 preprocess_operands (const struct arc_opcode *opcode,
1754 expressionS *tok,
1755 int ntok)
1756 {
1757 int i;
1758 size_t len;
1759 const char *p;
1760 unsigned j;
1761 const struct arc_aux_reg *auxr;
1762
1763 for (i = 0; i < ntok; i++)
1764 {
1765 switch (tok[i].X_op)
1766 {
1767 case O_illegal:
1768 case O_absent:
1769 break; /* Throw and error. */
1770
1771 case O_symbol:
1772 if (opcode->class != AUXREG)
1773 break;
1774 /* Convert the symbol to a constant if possible. */
1775 p = S_GET_NAME (tok[i].X_add_symbol);
1776 len = strlen (p);
1777
1778 auxr = &arc_aux_regs[0];
1779 for (j = 0; j < arc_num_aux_regs; j++, auxr++)
1780 if (len == auxr->length
1781 && strcasecmp (auxr->name, p) == 0)
1782 {
1783 tok[i].X_op = O_constant;
1784 tok[i].X_add_number = auxr->address;
1785 break;
1786 }
1787 break;
1788 default:
1789 break;
1790 }
1791 }
1792 }
1793
1794 /* Given an opcode name, pre-tockenized set of argumenst and the
1795 opcode flags, take it all the way through emission. */
1796
1797 static void
1798 assemble_tokens (const char *opname,
1799 expressionS *tok,
1800 int ntok,
1801 struct arc_flags *pflags,
1802 int nflgs)
1803 {
1804 bfd_boolean found_something = FALSE;
1805 const struct arc_opcode *opcode;
1806 int cpumatch = 1;
1807
1808 /* Search opcodes. */
1809 opcode = (const struct arc_opcode *) hash_find (arc_opcode_hash, opname);
1810
1811 /* Couldn't find opcode conventional way, try special cases. */
1812 if (!opcode)
1813 opcode = find_special_case (opname, &nflgs, pflags, tok, &ntok);
1814
1815 if (opcode)
1816 {
1817 pr_debug ("%s:%d: assemble_tokens: %s trying opcode 0x%08X\n",
1818 frag_now->fr_file, frag_now->fr_line, opcode->name,
1819 opcode->opcode);
1820
1821 preprocess_operands (opcode, tok, ntok);
1822
1823 found_something = TRUE;
1824 opcode = find_opcode_match (opcode, tok, &ntok, pflags, nflgs, &cpumatch);
1825 if (opcode)
1826 {
1827 struct arc_insn insn;
1828 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
1829 emit_insn (&insn);
1830 return;
1831 }
1832 }
1833
1834 if (found_something)
1835 {
1836 if (cpumatch)
1837 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
1838 else
1839 as_bad (_("opcode '%s' not supported for target %s"), opname,
1840 arc_target_name);
1841 }
1842 else
1843 as_bad (_("unknown opcode '%s'"), opname);
1844 }
1845
1846 /* Used to find special case opcode. */
1847
1848 static const struct arc_opcode *
1849 find_special_case (const char *opname,
1850 int *nflgs,
1851 struct arc_flags *pflags,
1852 expressionS *tok,
1853 int *ntok)
1854 {
1855 const struct arc_opcode *opcode;
1856
1857 opcode = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
1858
1859 if (opcode == NULL)
1860 opcode = find_special_case_flag (opname, nflgs, pflags);
1861
1862 return opcode;
1863 }
1864
1865 /* Swap operand tokens. */
1866
1867 static void
1868 swap_operand (expressionS *operand_array,
1869 unsigned source,
1870 unsigned destination)
1871 {
1872 expressionS cpy_operand;
1873 expressionS *src_operand;
1874 expressionS *dst_operand;
1875 size_t size;
1876
1877 if (source == destination)
1878 return;
1879
1880 src_operand = &operand_array[source];
1881 dst_operand = &operand_array[destination];
1882 size = sizeof (expressionS);
1883
1884 /* Make copy of operand to swap with and swap. */
1885 memcpy (&cpy_operand, dst_operand, size);
1886 memcpy (dst_operand, src_operand, size);
1887 memcpy (src_operand, &cpy_operand, size);
1888 }
1889
1890 /* Check if *op matches *tok type.
1891 Returns FALSE if they don't match, TRUE if they match. */
1892
1893 static bfd_boolean
1894 pseudo_operand_match (const expressionS *tok,
1895 const struct arc_operand_operation *op)
1896 {
1897 offsetT min, max, val;
1898 bfd_boolean ret;
1899 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
1900
1901 ret = FALSE;
1902 switch (tok->X_op)
1903 {
1904 case O_constant:
1905 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
1906 ret = 1;
1907 else if (!(operand_real->flags & ARC_OPERAND_IR))
1908 {
1909 val = tok->X_add_number;
1910 if (operand_real->flags & ARC_OPERAND_SIGNED)
1911 {
1912 max = (1 << (operand_real->bits - 1)) - 1;
1913 min = -(1 << (operand_real->bits - 1));
1914 }
1915 else
1916 {
1917 max = (1 << operand_real->bits) - 1;
1918 min = 0;
1919 }
1920 if (min <= val && val <= max)
1921 ret = TRUE;
1922 }
1923 break;
1924
1925 case O_symbol:
1926 /* Handle all symbols as long immediates or signed 9. */
1927 if (operand_real->flags & ARC_OPERAND_LIMM ||
1928 ((operand_real->flags & ARC_OPERAND_SIGNED) && operand_real->bits == 9))
1929 ret = TRUE;
1930 break;
1931
1932 case O_register:
1933 if (operand_real->flags & ARC_OPERAND_IR)
1934 ret = TRUE;
1935 break;
1936
1937 case O_bracket:
1938 if (operand_real->flags & ARC_OPERAND_BRAKET)
1939 ret = TRUE;
1940 break;
1941
1942 default:
1943 /* Unknown. */
1944 break;
1945 }
1946 return ret;
1947 }
1948
1949 /* Find pseudo instruction in array. */
1950
1951 static const struct arc_pseudo_insn *
1952 find_pseudo_insn (const char *opname,
1953 int ntok,
1954 const expressionS *tok)
1955 {
1956 const struct arc_pseudo_insn *pseudo_insn = NULL;
1957 const struct arc_operand_operation *op;
1958 unsigned int i;
1959 int j;
1960
1961 for (i = 0; i < arc_num_pseudo_insn; ++i)
1962 {
1963 pseudo_insn = &arc_pseudo_insns[i];
1964 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
1965 {
1966 op = pseudo_insn->operand;
1967 for (j = 0; j < ntok; ++j)
1968 if (!pseudo_operand_match (&tok[j], &op[j]))
1969 break;
1970
1971 /* Found the right instruction. */
1972 if (j == ntok)
1973 return pseudo_insn;
1974 }
1975 }
1976 return NULL;
1977 }
1978
1979 /* Assumes the expressionS *tok is of sufficient size. */
1980
1981 static const struct arc_opcode *
1982 find_special_case_pseudo (const char *opname,
1983 int *ntok,
1984 expressionS *tok,
1985 int *nflgs,
1986 struct arc_flags *pflags)
1987 {
1988 const struct arc_pseudo_insn *pseudo_insn = NULL;
1989 const struct arc_operand_operation *operand_pseudo;
1990 const struct arc_operand *operand_real;
1991 unsigned i;
1992 char construct_operand[MAX_CONSTR_STR];
1993
1994 /* Find whether opname is in pseudo instruction array. */
1995 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
1996
1997 if (pseudo_insn == NULL)
1998 return NULL;
1999
2000 /* Handle flag, Limited to one flag at the moment. */
2001 if (pseudo_insn->flag_r != NULL)
2002 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2003 MAX_INSN_FLGS - *nflgs);
2004
2005 /* Handle operand operations. */
2006 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2007 {
2008 operand_pseudo = &pseudo_insn->operand[i];
2009 operand_real = &arc_operands[operand_pseudo->operand_idx];
2010
2011 if (operand_real->flags & ARC_OPERAND_BRAKET &&
2012 !operand_pseudo->needs_insert)
2013 continue;
2014
2015 /* Has to be inserted (i.e. this token does not exist yet). */
2016 if (operand_pseudo->needs_insert)
2017 {
2018 if (operand_real->flags & ARC_OPERAND_BRAKET)
2019 {
2020 tok[i].X_op = O_bracket;
2021 ++(*ntok);
2022 continue;
2023 }
2024
2025 /* Check if operand is a register or constant and handle it
2026 by type. */
2027 if (operand_real->flags & ARC_OPERAND_IR)
2028 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2029 operand_pseudo->count);
2030 else
2031 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2032 operand_pseudo->count);
2033
2034 tokenize_arguments (construct_operand, &tok[i], 1);
2035 ++(*ntok);
2036 }
2037
2038 else if (operand_pseudo->count)
2039 {
2040 /* Operand number has to be adjusted accordingly (by operand
2041 type). */
2042 switch (tok[i].X_op)
2043 {
2044 case O_constant:
2045 tok[i].X_add_number += operand_pseudo->count;
2046 break;
2047
2048 case O_symbol:
2049 break;
2050
2051 default:
2052 /* Ignored. */
2053 break;
2054 }
2055 }
2056 }
2057
2058 /* Swap operands if necessary. Only supports one swap at the
2059 moment. */
2060 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2061 {
2062 operand_pseudo = &pseudo_insn->operand[i];
2063
2064 if (operand_pseudo->swap_operand_idx == i)
2065 continue;
2066
2067 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2068
2069 /* Prevent a swap back later by breaking out. */
2070 break;
2071 }
2072
2073 return (const struct arc_opcode *)
2074 hash_find (arc_opcode_hash, pseudo_insn->mnemonic_r);
2075 }
2076
2077 static const struct arc_opcode *
2078 find_special_case_flag (const char *opname,
2079 int *nflgs,
2080 struct arc_flags *pflags)
2081 {
2082 unsigned int i;
2083 const char *flagnm;
2084 unsigned flag_idx, flag_arr_idx;
2085 size_t flaglen, oplen;
2086 const struct arc_flag_special *arc_flag_special_opcode;
2087 const struct arc_opcode *opcode;
2088
2089 /* Search for special case instruction. */
2090 for (i = 0; i < arc_num_flag_special; i++)
2091 {
2092 arc_flag_special_opcode = &arc_flag_special_cases[i];
2093 oplen = strlen (arc_flag_special_opcode->name);
2094
2095 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2096 continue;
2097
2098 /* Found a potential special case instruction, now test for
2099 flags. */
2100 for (flag_arr_idx = 0;; ++flag_arr_idx)
2101 {
2102 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2103 if (flag_idx == 0)
2104 break; /* End of array, nothing found. */
2105
2106 flagnm = arc_flag_operands[flag_idx].name;
2107 flaglen = strlen (flagnm);
2108 if (strcmp (opname + oplen, flagnm) == 0)
2109 {
2110 opcode = (const struct arc_opcode *)
2111 hash_find (arc_opcode_hash,
2112 arc_flag_special_opcode->name);
2113
2114 if (*nflgs + 1 > MAX_INSN_FLGS)
2115 break;
2116 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2117 pflags[*nflgs].name[flaglen] = '\0';
2118 (*nflgs)++;
2119 return opcode;
2120 }
2121 }
2122 }
2123 return NULL;
2124 }
2125
2126 /* Check whether a symbol involves a register. */
2127
2128 static int
2129 contains_register (symbolS *sym)
2130 {
2131 if (sym)
2132 {
2133 expressionS *ex = symbol_get_value_expression (sym);
2134 return ((O_register == ex->X_op)
2135 && !contains_register (ex->X_add_symbol)
2136 && !contains_register (ex->X_op_symbol));
2137 }
2138 else
2139 return 0;
2140 }
2141
2142 /* Returns the register number within a symbol. */
2143
2144 static int
2145 get_register (symbolS *sym)
2146 {
2147 if (!contains_register (sym))
2148 return -1;
2149
2150 expressionS *ex = symbol_get_value_expression (sym);
2151 return regno (ex->X_add_number);
2152 }
2153
2154 /* Allocates a tok entry. */
2155
2156 static int
2157 allocate_tok (expressionS *tok, int ntok, int cidx)
2158 {
2159 if (ntok > MAX_INSN_ARGS - 2)
2160 return 0; /* No space left. */
2161
2162 if (cidx > ntok)
2163 return 0; /* Incorect args. */
2164
2165 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
2166
2167 if (cidx == ntok)
2168 return 1; /* Success. */
2169 return allocate_tok (tok, ntok - 1, cidx);
2170 }
2171
2172 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
2173 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
2174
2175 static bfd_boolean
2176 generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
2177 {
2178 if (!reloc)
2179 return FALSE;
2180
2181 switch (reloc)
2182 {
2183 case BFD_RELOC_ARC_SDA_LDST:
2184 case BFD_RELOC_ARC_SDA_LDST1:
2185 case BFD_RELOC_ARC_SDA_LDST2:
2186 case BFD_RELOC_ARC_SDA16_LD:
2187 case BFD_RELOC_ARC_SDA16_LD1:
2188 case BFD_RELOC_ARC_SDA16_LD2:
2189 case BFD_RELOC_ARC_SDA16_ST2:
2190 case BFD_RELOC_ARC_SDA32_ME:
2191 return FALSE;
2192 default:
2193 break;
2194 }
2195 return TRUE;
2196 }
2197
2198 /* Search forward through all variants of an opcode looking for a
2199 syntax match. */
2200
2201 static const struct arc_opcode *
2202 find_opcode_match (const struct arc_opcode *first_opcode,
2203 expressionS *tok,
2204 int *pntok,
2205 struct arc_flags *first_pflag,
2206 int nflgs,
2207 int *pcpumatch)
2208 {
2209 const struct arc_opcode *opcode = first_opcode;
2210 int ntok = *pntok;
2211 int got_cpu_match = 0;
2212 expressionS bktok[MAX_INSN_ARGS];
2213 int bkntok;
2214 expressionS emptyE;
2215
2216 memset (&emptyE, 0, sizeof (emptyE));
2217 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
2218 bkntok = ntok;
2219
2220 do
2221 {
2222 const unsigned char *opidx;
2223 const unsigned char *flgidx;
2224 int tokidx = 0;
2225 const expressionS *t = &emptyE;
2226
2227 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
2228 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
2229
2230 /* Don't match opcodes that don't exist on this
2231 architecture. */
2232 if (!(opcode->cpu & arc_target))
2233 goto match_failed;
2234
2235 if (is_code_density_p (opcode) && !(arc_features & ARC_CD))
2236 goto match_failed;
2237
2238 got_cpu_match = 1;
2239 pr_debug ("cpu ");
2240
2241 /* Check the operands. */
2242 for (opidx = opcode->operands; *opidx; ++opidx)
2243 {
2244 const struct arc_operand *operand = &arc_operands[*opidx];
2245
2246 /* Only take input from real operands. */
2247 if ((operand->flags & ARC_OPERAND_FAKE)
2248 && !(operand->flags & ARC_OPERAND_BRAKET))
2249 continue;
2250
2251 /* When we expect input, make sure we have it. */
2252 if (tokidx >= ntok)
2253 goto match_failed;
2254
2255 /* Match operand type with expression type. */
2256 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
2257 {
2258 case ARC_OPERAND_IR:
2259 /* Check to be a register. */
2260 if ((tok[tokidx].X_op != O_register
2261 || !is_ir_num (tok[tokidx].X_add_number))
2262 && !(operand->flags & ARC_OPERAND_IGNORE))
2263 goto match_failed;
2264
2265 /* If expect duplicate, make sure it is duplicate. */
2266 if (operand->flags & ARC_OPERAND_DUPLICATE)
2267 {
2268 /* Check for duplicate. */
2269 if (t->X_op != O_register
2270 || !is_ir_num (t->X_add_number)
2271 || (regno (t->X_add_number) !=
2272 regno (tok[tokidx].X_add_number)))
2273 goto match_failed;
2274 }
2275
2276 /* Special handling? */
2277 if (operand->insert)
2278 {
2279 const char *errmsg = NULL;
2280 (*operand->insert)(0,
2281 regno (tok[tokidx].X_add_number),
2282 &errmsg);
2283 if (errmsg)
2284 {
2285 if (operand->flags & ARC_OPERAND_IGNORE)
2286 {
2287 /* Missing argument, create one. */
2288 if (!allocate_tok (tok, ntok - 1, tokidx))
2289 goto match_failed;
2290
2291 tok[tokidx].X_op = O_absent;
2292 ++ntok;
2293 }
2294 else
2295 goto match_failed;
2296 }
2297 }
2298
2299 t = &tok[tokidx];
2300 break;
2301
2302 case ARC_OPERAND_BRAKET:
2303 /* Check if bracket is also in opcode table as
2304 operand. */
2305 if (tok[tokidx].X_op != O_bracket)
2306 goto match_failed;
2307 break;
2308
2309 case ARC_OPERAND_LIMM:
2310 case ARC_OPERAND_SIGNED:
2311 case ARC_OPERAND_UNSIGNED:
2312 switch (tok[tokidx].X_op)
2313 {
2314 case O_illegal:
2315 case O_absent:
2316 case O_register:
2317 goto match_failed;
2318
2319 case O_bracket:
2320 /* Got an (too) early bracket, check if it is an
2321 ignored operand. N.B. This procedure works only
2322 when bracket is the last operand! */
2323 if (!(operand->flags & ARC_OPERAND_IGNORE))
2324 goto match_failed;
2325 /* Insert the missing operand. */
2326 if (!allocate_tok (tok, ntok - 1, tokidx))
2327 goto match_failed;
2328
2329 tok[tokidx].X_op = O_absent;
2330 ++ntok;
2331 break;
2332
2333 case O_constant:
2334 /* Check the range. */
2335 if (operand->bits != 32
2336 && !(operand->flags & ARC_OPERAND_NCHK))
2337 {
2338 offsetT min, max, val;
2339 val = tok[tokidx].X_add_number;
2340
2341 if (operand->flags & ARC_OPERAND_SIGNED)
2342 {
2343 max = (1 << (operand->bits - 1)) - 1;
2344 min = -(1 << (operand->bits - 1));
2345 }
2346 else
2347 {
2348 max = (1 << operand->bits) - 1;
2349 min = 0;
2350 }
2351
2352 if (val < min || val > max)
2353 goto match_failed;
2354
2355 /* Check alignmets. */
2356 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2357 && (val & 0x03))
2358 goto match_failed;
2359
2360 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2361 && (val & 0x01))
2362 goto match_failed;
2363 }
2364 else if (operand->flags & ARC_OPERAND_NCHK)
2365 {
2366 if (operand->insert)
2367 {
2368 const char *errmsg = NULL;
2369 (*operand->insert)(0,
2370 tok[tokidx].X_add_number,
2371 &errmsg);
2372 if (errmsg)
2373 goto match_failed;
2374 }
2375 else
2376 goto match_failed;
2377 }
2378 break;
2379
2380 case O_subtract:
2381 /* Check if it is register range. */
2382 if ((tok[tokidx].X_add_number == 0)
2383 && contains_register (tok[tokidx].X_add_symbol)
2384 && contains_register (tok[tokidx].X_op_symbol))
2385 {
2386 int regs;
2387
2388 regs = get_register (tok[tokidx].X_add_symbol);
2389 regs <<= 16;
2390 regs |= get_register (tok[tokidx].X_op_symbol);
2391 if (operand->insert)
2392 {
2393 const char *errmsg = NULL;
2394 (*operand->insert)(0,
2395 regs,
2396 &errmsg);
2397 if (errmsg)
2398 goto match_failed;
2399 }
2400 else
2401 goto match_failed;
2402 break;
2403 }
2404 default:
2405 if (operand->default_reloc == 0)
2406 goto match_failed; /* The operand needs relocation. */
2407
2408 /* Relocs requiring long immediate. FIXME! make it
2409 generic and move it to a function. */
2410 switch (tok[tokidx].X_md)
2411 {
2412 case O_gotoff:
2413 case O_gotpc:
2414 case O_pcl:
2415 case O_tpoff:
2416 case O_dtpoff:
2417 case O_tlsgd:
2418 case O_tlsie:
2419 if (!(operand->flags & ARC_OPERAND_LIMM))
2420 goto match_failed;
2421 case O_absent:
2422 if (!generic_reloc_p (operand->default_reloc))
2423 goto match_failed;
2424 default:
2425 break;
2426 }
2427 break;
2428 }
2429 /* If expect duplicate, make sure it is duplicate. */
2430 if (operand->flags & ARC_OPERAND_DUPLICATE)
2431 {
2432 if (t->X_op == O_illegal
2433 || t->X_op == O_absent
2434 || t->X_op == O_register
2435 || (t->X_add_number != tok[tokidx].X_add_number))
2436 goto match_failed;
2437 }
2438 t = &tok[tokidx];
2439 break;
2440
2441 default:
2442 /* Everything else should have been fake. */
2443 abort ();
2444 }
2445
2446 ++tokidx;
2447 }
2448 pr_debug ("opr ");
2449
2450 /* Check the flags. Iterate over the valid flag classes. */
2451 int lnflg = nflgs;
2452
2453 for (flgidx = opcode->flags; *flgidx && lnflg; ++flgidx)
2454 {
2455 /* Get a valid flag class. */
2456 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
2457 const unsigned *flgopridx;
2458
2459 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
2460 {
2461 const struct arc_flag_operand *flg_operand;
2462 struct arc_flags *pflag = first_pflag;
2463 int i;
2464
2465 flg_operand = &arc_flag_operands[*flgopridx];
2466 for (i = 0; i < nflgs; i++, pflag++)
2467 {
2468 /* Match against the parsed flags. */
2469 if (!strcmp (flg_operand->name, pflag->name))
2470 {
2471 /*TODO: Check if it is duplicated. */
2472 pflag->code = *flgopridx;
2473 lnflg--;
2474 break; /* goto next flag class and parsed flag. */
2475 }
2476 }
2477 }
2478 }
2479 /* Did I check all the parsed flags? */
2480 if (lnflg)
2481 goto match_failed;
2482
2483 pr_debug ("flg");
2484 /* Possible match -- did we use all of our input? */
2485 if (tokidx == ntok)
2486 {
2487 *pntok = ntok;
2488 pr_debug ("\n");
2489 return opcode;
2490 }
2491
2492 match_failed:;
2493 pr_debug ("\n");
2494 /* Restore the original parameters. */
2495 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
2496 ntok = bkntok;
2497 }
2498 while (++opcode - arc_opcodes < (int) arc_num_opcodes
2499 && !strcmp (opcode->name, first_opcode->name));
2500
2501 if (*pcpumatch)
2502 *pcpumatch = got_cpu_match;
2503
2504 return NULL;
2505 }
2506
2507 /* Find the proper relocation for the given opcode. */
2508
2509 static extended_bfd_reloc_code_real_type
2510 find_reloc (const char *name,
2511 const char *opcodename,
2512 const struct arc_flags *pflags,
2513 int nflg,
2514 extended_bfd_reloc_code_real_type reloc)
2515 {
2516 unsigned int i;
2517 int j;
2518 bfd_boolean found_flag;
2519 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
2520
2521 for (i = 0; i < arc_num_equiv_tab; i++)
2522 {
2523 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
2524
2525 /* Find the entry. */
2526 if (strcmp (name, r->name))
2527 continue;
2528 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
2529 continue;
2530 if (r->flagcode)
2531 {
2532 if (!nflg)
2533 continue;
2534 found_flag = FALSE;
2535 for (j = 0; j < nflg; j++)
2536 if (pflags[i].code == r->flagcode)
2537 {
2538 found_flag = TRUE;
2539 break;
2540 }
2541 if (!found_flag)
2542 continue;
2543 }
2544
2545 if (reloc != r->oldreloc)
2546 continue;
2547 /* Found it. */
2548 ret = r->newreloc;
2549 break;
2550 }
2551
2552 if (ret == BFD_RELOC_UNUSED)
2553 as_bad (_("Unable to find %s relocation for instruction %s"),
2554 name, opcodename);
2555 return ret;
2556 }
2557
2558 /* Turn an opcode description and a set of arguments into
2559 an instruction and a fixup. */
2560
2561 static void
2562 assemble_insn (const struct arc_opcode *opcode,
2563 const expressionS *tok,
2564 int ntok,
2565 const struct arc_flags *pflags,
2566 int nflg,
2567 struct arc_insn *insn)
2568 {
2569 const expressionS *reloc_exp = NULL;
2570 unsigned image;
2571 const unsigned char *argidx;
2572 int i;
2573 int tokidx = 0;
2574 unsigned char pcrel = 0;
2575 bfd_boolean needGOTSymbol;
2576 bfd_boolean has_delay_slot = FALSE;
2577 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
2578
2579 memset (insn, 0, sizeof (*insn));
2580 image = opcode->opcode;
2581
2582 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
2583 frag_now->fr_file, frag_now->fr_line, opcode->name,
2584 opcode->opcode);
2585
2586 /* Handle operands. */
2587 for (argidx = opcode->operands; *argidx; ++argidx)
2588 {
2589 const struct arc_operand *operand = &arc_operands[*argidx];
2590 const expressionS *t = (const expressionS *) 0;
2591
2592 if ((operand->flags & ARC_OPERAND_FAKE)
2593 && !(operand->flags & ARC_OPERAND_BRAKET))
2594 continue;
2595
2596 if (operand->flags & ARC_OPERAND_DUPLICATE)
2597 {
2598 /* Duplicate operand, already inserted. */
2599 tokidx ++;
2600 continue;
2601 }
2602
2603 if (tokidx >= ntok)
2604 {
2605 abort ();
2606 }
2607 else
2608 t = &tok[tokidx++];
2609
2610 /* Regardless if we have a reloc or not mark the instruction
2611 limm if it is the case. */
2612 if (operand->flags & ARC_OPERAND_LIMM)
2613 insn->has_limm = TRUE;
2614
2615 switch (t->X_op)
2616 {
2617 case O_register:
2618 image = insert_operand (image, operand, regno (t->X_add_number),
2619 NULL, 0);
2620 break;
2621
2622 case O_constant:
2623 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
2624 reloc_exp = t;
2625 if (operand->flags & ARC_OPERAND_LIMM)
2626 insn->limm = t->X_add_number;
2627 break;
2628
2629 case O_bracket:
2630 /* Ignore brackets. */
2631 break;
2632
2633 case O_absent:
2634 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
2635 break;
2636
2637 case O_subtract:
2638 /* Maybe register range. */
2639 if ((t->X_add_number == 0)
2640 && contains_register (t->X_add_symbol)
2641 && contains_register (t->X_op_symbol))
2642 {
2643 int regs;
2644
2645 regs = get_register (t->X_add_symbol);
2646 regs <<= 16;
2647 regs |= get_register (t->X_op_symbol);
2648 image = insert_operand (image, operand, regs, NULL, 0);
2649 break;
2650 }
2651
2652 default:
2653 /* This operand needs a relocation. */
2654 needGOTSymbol = FALSE;
2655
2656 switch (t->X_md)
2657 {
2658 case O_plt:
2659 needGOTSymbol = TRUE;
2660 reloc = find_reloc ("plt", opcode->name,
2661 pflags, nflg,
2662 operand->default_reloc);
2663 break;
2664
2665 case O_gotoff:
2666 case O_gotpc:
2667 needGOTSymbol = TRUE;
2668 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
2669 break;
2670 case O_pcl:
2671 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
2672 if (ARC_SHORT (opcode->mask))
2673 as_bad_where (frag_now->fr_file, frag_now->fr_line,
2674 _("Unable to use @pcl relocation for insn %s"),
2675 opcode->name);
2676 break;
2677 case O_sda:
2678 reloc = find_reloc ("sda", opcode->name,
2679 pflags, nflg,
2680 operand->default_reloc);
2681 break;
2682 case O_tlsgd:
2683 case O_tlsie:
2684 needGOTSymbol = TRUE;
2685 /* Fall-through. */
2686
2687 case O_tpoff:
2688 case O_dtpoff:
2689 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
2690 break;
2691
2692 case O_tpoff9: /*FIXME! Check for the conditionality of
2693 the insn. */
2694 case O_dtpoff9: /*FIXME! Check for the conditionality of
2695 the insn. */
2696 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2697 break;
2698
2699 default:
2700 /* Just consider the default relocation. */
2701 reloc = operand->default_reloc;
2702 break;
2703 }
2704
2705 if (needGOTSymbol && (GOT_symbol == NULL))
2706 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
2707
2708 reloc_exp = t;
2709
2710 #if 0
2711 if (reloc > 0)
2712 {
2713 /* sanity checks. */
2714 reloc_howto_type *reloc_howto
2715 = bfd_reloc_type_lookup (stdoutput,
2716 (bfd_reloc_code_real_type) reloc);
2717 unsigned reloc_bitsize = reloc_howto->bitsize;
2718 if (reloc_howto->rightshift)
2719 reloc_bitsize -= reloc_howto->rightshift;
2720 if (reloc_bitsize != operand->bits)
2721 {
2722 as_bad (_("invalid relocation %s for field"),
2723 bfd_get_reloc_code_name (reloc));
2724 return;
2725 }
2726 }
2727 #endif
2728 if (insn->nfixups >= MAX_INSN_FIXUPS)
2729 as_fatal (_("too many fixups"));
2730
2731 struct arc_fixup *fixup;
2732 fixup = &insn->fixups[insn->nfixups++];
2733 fixup->exp = *t;
2734 fixup->reloc = reloc;
2735 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
2736 fixup->pcrel = pcrel;
2737 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
2738 TRUE : FALSE;
2739 break;
2740 }
2741 }
2742
2743 /* Handle flags. */
2744 for (i = 0; i < nflg; i++)
2745 {
2746 const struct arc_flag_operand *flg_operand =
2747 &arc_flag_operands[pflags[i].code];
2748
2749 /* Check if the instruction has a delay slot. */
2750 if (!strcmp (flg_operand->name, "d"))
2751 has_delay_slot = TRUE;
2752
2753 /* There is an exceptional case when we cannot insert a flag
2754 just as it is. The .T flag must be handled in relation with
2755 the relative address. */
2756 if (!strcmp (flg_operand->name, "t")
2757 || !strcmp (flg_operand->name, "nt"))
2758 {
2759 unsigned bitYoperand = 0;
2760 /* FIXME! move selection bbit/brcc in arc-opc.c. */
2761 if (!strcmp (flg_operand->name, "t"))
2762 if (!strcmp (opcode->name, "bbit0")
2763 || !strcmp (opcode->name, "bbit1"))
2764 bitYoperand = arc_NToperand;
2765 else
2766 bitYoperand = arc_Toperand;
2767 else
2768 if (!strcmp (opcode->name, "bbit0")
2769 || !strcmp (opcode->name, "bbit1"))
2770 bitYoperand = arc_Toperand;
2771 else
2772 bitYoperand = arc_NToperand;
2773
2774 gas_assert (reloc_exp != NULL);
2775 if (reloc_exp->X_op == O_constant)
2776 {
2777 /* Check if we have a constant and solved it
2778 immediately. */
2779 offsetT val = reloc_exp->X_add_number;
2780 image |= insert_operand (image, &arc_operands[bitYoperand],
2781 val, NULL, 0);
2782 }
2783 else
2784 {
2785 struct arc_fixup *fixup;
2786
2787 if (insn->nfixups >= MAX_INSN_FIXUPS)
2788 as_fatal (_("too many fixups"));
2789
2790 fixup = &insn->fixups[insn->nfixups++];
2791 fixup->exp = *reloc_exp;
2792 fixup->reloc = -bitYoperand;
2793 fixup->pcrel = pcrel;
2794 fixup->islong = FALSE;
2795 }
2796 }
2797 else
2798 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
2799 << flg_operand->shift;
2800 }
2801
2802 /* Short instruction? */
2803 insn->short_insn = ARC_SHORT (opcode->mask) ? TRUE : FALSE;
2804
2805 insn->insn = image;
2806
2807 /* Update last insn status. */
2808 arc_last_insns[1] = arc_last_insns[0];
2809 arc_last_insns[0].opcode = opcode;
2810 arc_last_insns[0].has_limm = insn->has_limm;
2811 arc_last_insns[0].has_delay_slot = has_delay_slot;
2812
2813 /* Check if the current instruction is legally used. */
2814 if (arc_last_insns[1].has_delay_slot
2815 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
2816 as_bad_where (frag_now->fr_file, frag_now->fr_line,
2817 _("A jump/branch instruction in delay slot."));
2818 }
2819
2820 /* Actually output an instruction with its fixup. */
2821
2822 static void
2823 emit_insn (struct arc_insn *insn)
2824 {
2825 char *f;
2826 int i;
2827
2828 pr_debug ("Emit insn : 0x%x\n", insn->insn);
2829 pr_debug ("\tShort : 0x%d\n", insn->short_insn);
2830 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
2831
2832 /* Write out the instruction. */
2833 if (insn->short_insn)
2834 {
2835 if (insn->has_limm)
2836 {
2837 f = frag_more (6);
2838 md_number_to_chars (f, insn->insn, 2);
2839 md_number_to_chars_midend (f + 2, insn->limm, 4);
2840 dwarf2_emit_insn (6);
2841 }
2842 else
2843 {
2844 f = frag_more (2);
2845 md_number_to_chars (f, insn->insn, 2);
2846 dwarf2_emit_insn (2);
2847 }
2848 }
2849 else
2850 {
2851 if (insn->has_limm)
2852 {
2853 f = frag_more (8);
2854 md_number_to_chars_midend (f, insn->insn, 4);
2855 md_number_to_chars_midend (f + 4, insn->limm, 4);
2856 dwarf2_emit_insn (8);
2857 }
2858 else
2859 {
2860 f = frag_more (4);
2861 md_number_to_chars_midend (f, insn->insn, 4);
2862 dwarf2_emit_insn (4);
2863 }
2864 }
2865
2866 /* Apply the fixups in order. */
2867 for (i = 0; i < insn->nfixups; i++)
2868 {
2869 struct arc_fixup *fixup = &insn->fixups[i];
2870 int size, pcrel, offset = 0;
2871
2872 /*FIXME! the reloc size is wrong in the BFD file. When it will
2873 be fixed please delete me. */
2874 size = (insn->short_insn && !fixup->islong) ? 2 : 4;
2875
2876 if (fixup->islong)
2877 offset = (insn->short_insn) ? 2 : 4;
2878
2879 /* Some fixups are only used internally, thus no howto. */
2880 if ((int) fixup->reloc < 0)
2881 {
2882 /*FIXME! the reloc size is wrong in the BFD file. When it
2883 will be fixed please enable me.
2884 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
2885 pcrel = fixup->pcrel;
2886 }
2887 else
2888 {
2889 reloc_howto_type *reloc_howto =
2890 bfd_reloc_type_lookup (stdoutput,
2891 (bfd_reloc_code_real_type) fixup->reloc);
2892 gas_assert (reloc_howto);
2893 /*FIXME! the reloc size is wrong in the BFD file. When it
2894 will be fixed please enable me.
2895 size = bfd_get_reloc_size (reloc_howto); */
2896 pcrel = reloc_howto->pc_relative;
2897 }
2898
2899 pr_debug ("%s:%d: emit_insn: new %s fixup (PCrel:%s) of size %d @ offset %d\n",
2900 frag_now->fr_file, frag_now->fr_line,
2901 (fixup->reloc < 0) ? "Internal" :
2902 bfd_get_reloc_code_name (fixup->reloc),
2903 pcrel ? "Y" : "N",
2904 size, offset);
2905 fix_new_exp (frag_now, f - frag_now->fr_literal + offset,
2906 size, &fixup->exp, pcrel, fixup->reloc);
2907
2908 /* Check for ZOLs, and update symbol info if any. */
2909 if (LP_INSN (insn->insn))
2910 {
2911 gas_assert (fixup->exp.X_add_symbol);
2912 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
2913 }
2914 }
2915 }
2916
2917 /* Insert an operand value into an instruction. */
2918
2919 static unsigned
2920 insert_operand (unsigned insn,
2921 const struct arc_operand *operand,
2922 offsetT val,
2923 char *file,
2924 unsigned line)
2925 {
2926 offsetT min = 0, max = 0;
2927
2928 if (operand->bits != 32
2929 && !(operand->flags & ARC_OPERAND_NCHK)
2930 && !(operand->flags & ARC_OPERAND_FAKE))
2931 {
2932 if (operand->flags & ARC_OPERAND_SIGNED)
2933 {
2934 max = (1 << (operand->bits - 1)) - 1;
2935 min = -(1 << (operand->bits - 1));
2936 }
2937 else
2938 {
2939 max = (1 << operand->bits) - 1;
2940 min = 0;
2941 }
2942
2943 if (val < min || val > max)
2944 as_bad_value_out_of_range (_("operand"),
2945 val, min, max, file, line);
2946 }
2947
2948 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2949 min, val, max, insn);
2950
2951 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2952 && (val & 0x03))
2953 as_bad_where (file, line,
2954 _("Unaligned operand. Needs to be 32bit aligned"));
2955
2956 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2957 && (val & 0x01))
2958 as_bad_where (file, line,
2959 _("Unaligned operand. Needs to be 16bit aligned"));
2960
2961 if (operand->insert)
2962 {
2963 const char *errmsg = NULL;
2964
2965 insn = (*operand->insert) (insn, val, &errmsg);
2966 if (errmsg)
2967 as_warn_where (file, line, "%s", errmsg);
2968 }
2969 else
2970 {
2971 if (operand->flags & ARC_OPERAND_TRUNCATE)
2972 {
2973 if (operand->flags & ARC_OPERAND_ALIGNED32)
2974 val >>= 2;
2975 if (operand->flags & ARC_OPERAND_ALIGNED16)
2976 val >>= 1;
2977 }
2978 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2979 }
2980 return insn;
2981 }
2982
2983 void
2984 arc_handle_align (fragS* fragP)
2985 {
2986 if ((fragP)->fr_type == rs_align_code)
2987 {
2988 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
2989 valueT count = ((fragP)->fr_next->fr_address
2990 - (fragP)->fr_address - (fragP)->fr_fix);
2991
2992 (fragP)->fr_var = 2;
2993
2994 if (count & 1)/* Padding in the gap till the next 2-byte
2995 boundary with 0s. */
2996 {
2997 (fragP)->fr_fix++;
2998 *dest++ = 0;
2999 }
3000 /* Writing nop_s. */
3001 md_number_to_chars (dest, NOP_OPCODE_S, 2);
3002 }
3003 }
3004
3005 /* Here we decide which fixups can be adjusted to make them relative
3006 to the beginning of the section instead of the symbol. Basically
3007 we need to make sure that the dynamic relocations are done
3008 correctly, so in some cases we force the original symbol to be
3009 used. */
3010
3011 int
3012 tc_arc_fix_adjustable (fixS *fixP)
3013 {
3014
3015 /* Prevent all adjustments to global symbols. */
3016 if (S_IS_EXTERNAL (fixP->fx_addsy))
3017 return 0;
3018 if (S_IS_WEAK (fixP->fx_addsy))
3019 return 0;
3020
3021 /* Adjust_reloc_syms doesn't know about the GOT. */
3022 switch (fixP->fx_r_type)
3023 {
3024 case BFD_RELOC_ARC_GOTPC32:
3025 case BFD_RELOC_ARC_PLT32:
3026 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3027 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3028 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3029 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3030 return 0;
3031
3032 default:
3033 break;
3034 }
3035
3036 return 0; /* FIXME! return 1, fix it in the linker. */
3037 }
3038
3039 /* Compute the reloc type of an expression EXP. */
3040
3041 static void
3042 arc_check_reloc (expressionS *exp,
3043 bfd_reloc_code_real_type *r_type_p)
3044 {
3045 if (*r_type_p == BFD_RELOC_32
3046 && exp->X_op == O_subtract
3047 && exp->X_op_symbol != NULL
3048 && exp->X_op_symbol->bsym->section == now_seg)
3049 *r_type_p = BFD_RELOC_ARC_PC32;
3050 }
3051
3052
3053 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
3054
3055 void
3056 arc_cons_fix_new (fragS *frag,
3057 int off,
3058 int size,
3059 expressionS *exp,
3060 bfd_reloc_code_real_type r_type)
3061 {
3062 r_type = BFD_RELOC_UNUSED;
3063
3064 switch (size)
3065 {
3066 case 1:
3067 r_type = BFD_RELOC_8;
3068 break;
3069
3070 case 2:
3071 r_type = BFD_RELOC_16;
3072 break;
3073
3074 case 3:
3075 r_type = BFD_RELOC_24;
3076 break;
3077
3078 case 4:
3079 r_type = BFD_RELOC_32;
3080 arc_check_reloc (exp, &r_type);
3081 break;
3082
3083 case 8:
3084 r_type = BFD_RELOC_64;
3085 break;
3086
3087 default:
3088 as_bad (_("unsupported BFD relocation size %u"), size);
3089 r_type = BFD_RELOC_UNUSED;
3090 }
3091
3092 fix_new_exp (frag, off, size, exp, 0, r_type);
3093 }
3094
3095 /* The actual routine that checks the ZOL conditions. */
3096
3097 static void
3098 check_zol (symbolS *s)
3099 {
3100 switch (arc_mach_type)
3101 {
3102 case bfd_mach_arc_arcv2:
3103 if (arc_target & ARC_OPCODE_ARCv2EM)
3104 return;
3105
3106 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
3107 || arc_last_insns[1].has_delay_slot)
3108 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
3109 S_GET_NAME (s));
3110
3111 break;
3112 case bfd_mach_arc_arc600:
3113
3114 if (is_kernel_insn_p (arc_last_insns[0].opcode))
3115 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
3116 S_GET_NAME (s));
3117
3118 if (arc_last_insns[0].has_limm
3119 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
3120 as_bad (_("A jump instruction with long immediate detected at the \
3121 end of the ZOL label @%s"), S_GET_NAME (s));
3122
3123 /* Fall through. */
3124 case bfd_mach_arc_arc700:
3125 if (arc_last_insns[0].has_delay_slot)
3126 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
3127 S_GET_NAME (s));
3128
3129 break;
3130 default:
3131 break;
3132 }
3133 }
3134
3135 /* If ZOL end check the last two instruction for illegals. */
3136 void
3137 arc_frob_label (symbolS * sym)
3138 {
3139 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
3140 check_zol (sym);
3141
3142 dwarf2_emit_label (sym);
3143 }
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