1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2022 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "dwarf2dbg.h"
26 #include "dw2gencfi.h"
27 #include "safe-ctype.h"
29 #include "opcode/arc.h"
30 #include "opcode/arc-attrs.h"
32 #include "../opcodes/arc-ext.h"
34 /* Defines section. */
36 #define MAX_INSN_FIXUPS 2
37 #define MAX_CONSTR_STR 20
38 #define FRAG_MAX_GROWTH 8
41 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43 # define pr_debug(fmt, args...)
46 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
48 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
51 #ifndef TARGET_WITH_CPU
52 #define TARGET_WITH_CPU "arc700"
53 #endif /* TARGET_WITH_CPU */
55 #define ARC_GET_FLAG(s) (*symbol_get_tc (s))
56 #define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
57 #define streq(a, b) (strcmp (a, b) == 0)
59 /* Enum used to enumerate the relaxable ins operands. */
64 REGISTER_S
, /* Register for short instruction(s). */
65 REGISTER_NO_GP
, /* Is a register but not gp register specifically. */
66 REGISTER_DUP
, /* Duplication of previous operand of type register. */
100 #define regno(x) ((x) & 0x3F)
101 #define is_ir_num(x) (((x) & ~0x3F) == 0)
102 #define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
103 #define is_spfp_p(op) (((sc) == SPX))
104 #define is_dpfp_p(op) (((sc) == DPX))
105 #define is_fpuda_p(op) (((sc) == DPA))
106 #define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
107 || (op)->insn_class == JUMP \
108 || (op)->insn_class == BRCC \
109 || (op)->insn_class == BBIT0 \
110 || (op)->insn_class == BBIT1 \
111 || (op)->insn_class == BI \
112 || (op)->insn_class == EI \
113 || (op)->insn_class == ENTER \
114 || (op)->insn_class == JLI \
115 || (op)->insn_class == LOOP \
116 || (op)->insn_class == LEAVE \
118 #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
119 #define is_nps400_p(op) (((sc) == NPS400))
121 /* Generic assembler global variables which must be defined by all
124 /* Characters which always start a comment. */
125 const char comment_chars
[] = "#;";
127 /* Characters which start a comment at the beginning of a line. */
128 const char line_comment_chars
[] = "#";
130 /* Characters which may be used to separate multiple commands on a
132 const char line_separator_chars
[] = "`";
134 /* Characters which are used to indicate an exponent in a floating
136 const char EXP_CHARS
[] = "eE";
138 /* Chars that mean this number is a floating point constant
139 As in 0f12.456 or 0d1.2345e12. */
140 const char FLT_CHARS
[] = "rRsSfFdD";
143 extern int target_big_endian
;
144 const char *arc_target_format
= DEFAULT_TARGET_FORMAT
;
145 static int byte_order
= DEFAULT_BYTE_ORDER
;
147 /* Arc extension section. */
148 static segT arcext_section
;
150 /* By default relaxation is disabled. */
151 static int relaxation_state
= 0;
153 extern int arc_get_mach (char *);
155 /* Forward declarations. */
156 static void arc_lcomm (int);
157 static void arc_option (int);
158 static void arc_extra_reloc (int);
159 static void arc_extinsn (int);
160 static void arc_extcorereg (int);
161 static void arc_attribute (int);
163 const pseudo_typeS md_pseudo_table
[] =
165 /* Make sure that .word is 32 bits. */
168 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
169 { "lcomm", arc_lcomm
, 0 },
170 { "lcommon", arc_lcomm
, 0 },
171 { "cpu", arc_option
, 0 },
173 { "arc_attribute", arc_attribute
, 0 },
174 { "extinstruction", arc_extinsn
, 0 },
175 { "extcoreregister", arc_extcorereg
, EXT_CORE_REGISTER
},
176 { "extauxregister", arc_extcorereg
, EXT_AUX_REGISTER
},
177 { "extcondcode", arc_extcorereg
, EXT_COND_CODE
},
179 { "tls_gd_ld", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_LD
},
180 { "tls_gd_call", arc_extra_reloc
, BFD_RELOC_ARC_TLS_GD_CALL
},
185 const char *md_shortopts
= "";
189 OPTION_EB
= OPTION_MD_BASE
,
207 /* The following options are deprecated and provided here only for
208 compatibility reasons. */
231 struct option md_longopts
[] =
233 { "EB", no_argument
, NULL
, OPTION_EB
},
234 { "EL", no_argument
, NULL
, OPTION_EL
},
235 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
236 { "mA6", no_argument
, NULL
, OPTION_ARC600
},
237 { "mARC600", no_argument
, NULL
, OPTION_ARC600
},
238 { "mARC601", no_argument
, NULL
, OPTION_ARC601
},
239 { "mARC700", no_argument
, NULL
, OPTION_ARC700
},
240 { "mA7", no_argument
, NULL
, OPTION_ARC700
},
241 { "mEM", no_argument
, NULL
, OPTION_ARCEM
},
242 { "mHS", no_argument
, NULL
, OPTION_ARCHS
},
243 { "mcode-density", no_argument
, NULL
, OPTION_CD
},
244 { "mrelax", no_argument
, NULL
, OPTION_RELAX
},
245 { "mnps400", no_argument
, NULL
, OPTION_NPS400
},
247 /* Floating point options */
248 { "mspfp", no_argument
, NULL
, OPTION_SPFP
},
249 { "mspfp-compact", no_argument
, NULL
, OPTION_SPFP
},
250 { "mspfp_compact", no_argument
, NULL
, OPTION_SPFP
},
251 { "mspfp-fast", no_argument
, NULL
, OPTION_SPFP
},
252 { "mspfp_fast", no_argument
, NULL
, OPTION_SPFP
},
253 { "mdpfp", no_argument
, NULL
, OPTION_DPFP
},
254 { "mdpfp-compact", no_argument
, NULL
, OPTION_DPFP
},
255 { "mdpfp_compact", no_argument
, NULL
, OPTION_DPFP
},
256 { "mdpfp-fast", no_argument
, NULL
, OPTION_DPFP
},
257 { "mdpfp_fast", no_argument
, NULL
, OPTION_DPFP
},
258 { "mfpuda", no_argument
, NULL
, OPTION_FPUDA
},
260 /* The following options are deprecated and provided here only for
261 compatibility reasons. */
262 { "mav2em", no_argument
, NULL
, OPTION_ARCEM
},
263 { "mav2hs", no_argument
, NULL
, OPTION_ARCHS
},
264 { "muser-mode-only", no_argument
, NULL
, OPTION_USER_MODE
},
265 { "mld-extension-reg-mask", required_argument
, NULL
, OPTION_LD_EXT_MASK
},
266 { "mswap", no_argument
, NULL
, OPTION_SWAP
},
267 { "mnorm", no_argument
, NULL
, OPTION_NORM
},
268 { "mbarrel-shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
269 { "mbarrel_shifter", no_argument
, NULL
, OPTION_BARREL_SHIFT
},
270 { "mmin-max", no_argument
, NULL
, OPTION_MIN_MAX
},
271 { "mmin_max", no_argument
, NULL
, OPTION_MIN_MAX
},
272 { "mno-mpy", no_argument
, NULL
, OPTION_NO_MPY
},
273 { "mea", no_argument
, NULL
, OPTION_EA
},
274 { "mEA", no_argument
, NULL
, OPTION_EA
},
275 { "mmul64", no_argument
, NULL
, OPTION_MUL64
},
276 { "msimd", no_argument
, NULL
, OPTION_SIMD
},
277 { "mmac-d16", no_argument
, NULL
, OPTION_XMAC_D16
},
278 { "mmac_d16", no_argument
, NULL
, OPTION_XMAC_D16
},
279 { "mmac-24", no_argument
, NULL
, OPTION_XMAC_24
},
280 { "mmac_24", no_argument
, NULL
, OPTION_XMAC_24
},
281 { "mdsp-packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
282 { "mdsp_packa", no_argument
, NULL
, OPTION_DSP_PACKA
},
283 { "mcrc", no_argument
, NULL
, OPTION_CRC
},
284 { "mdvbf", no_argument
, NULL
, OPTION_DVBF
},
285 { "mtelephony", no_argument
, NULL
, OPTION_TELEPHONY
},
286 { "mxy", no_argument
, NULL
, OPTION_XYMEMORY
},
287 { "mlock", no_argument
, NULL
, OPTION_LOCK
},
288 { "mswape", no_argument
, NULL
, OPTION_SWAPE
},
289 { "mrtsc", no_argument
, NULL
, OPTION_RTSC
},
291 { NULL
, no_argument
, NULL
, 0 }
294 size_t md_longopts_size
= sizeof (md_longopts
);
296 /* Local data and data types. */
298 /* Used since new relocation types are introduced in this
299 file (DUMMY_RELOC_LITUSE_*). */
300 typedef int extended_bfd_reloc_code_real_type
;
306 extended_bfd_reloc_code_real_type reloc
;
308 /* index into arc_operands. */
309 unsigned int opindex
;
311 /* PC-relative, used by internals fixups. */
314 /* TRUE if this fixup is for LIMM operand. */
320 unsigned long long int insn
;
322 struct arc_fixup fixups
[MAX_INSN_FIXUPS
];
324 unsigned int len
; /* Length of instruction in bytes. */
325 bool has_limm
; /* Boolean value: TRUE if limm field is valid. */
326 bool relax
; /* Boolean value: TRUE if needs relaxation. */
329 /* Structure to hold any last two instructions. */
330 static struct arc_last_insn
332 /* Saved instruction opcode. */
333 const struct arc_opcode
*opcode
;
335 /* Boolean value: TRUE if current insn is short. */
338 /* Boolean value: TRUE if current insn has delay slot. */
342 /* Extension instruction suffix classes. */
350 static const attributes_t suffixclass
[] =
352 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG
},
353 { "SUFFIX_COND", 11, ARC_SUFFIX_COND
},
354 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE
}
357 /* Extension instruction syntax classes. */
358 static const attributes_t syntaxclass
[] =
360 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP
},
361 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP
},
362 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP
},
363 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP
}
366 /* Extension instruction syntax classes modifiers. */
367 static const attributes_t syntaxclassmod
[] =
369 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED
},
370 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM
}
373 /* Extension register type. */
381 /* A structure to hold the additional conditional codes. */
384 struct arc_flag_operand
*arc_ext_condcode
;
386 } ext_condcode
= { NULL
, 0 };
388 /* Structure to hold an entry in ARC_OPCODE_HASH. */
389 struct arc_opcode_hash_entry
391 /* The number of pointers in the OPCODE list. */
394 /* Points to a list of opcode pointers. */
395 const struct arc_opcode
**opcode
;
398 /* Structure used for iterating through an arc_opcode_hash_entry. */
399 struct arc_opcode_hash_entry_iterator
401 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
404 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
405 returned by this iterator. */
406 const struct arc_opcode
*opcode
;
409 /* Forward declaration. */
410 static void assemble_insn
411 (const struct arc_opcode
*, const expressionS
*, int,
412 const struct arc_flags
*, int, struct arc_insn
*);
414 /* The selection of the machine type can come from different sources. This
415 enum is used to track how the selection was made in order to perform
417 enum mach_selection_type
420 MACH_SELECTION_FROM_DEFAULT
,
421 MACH_SELECTION_FROM_CPU_DIRECTIVE
,
422 MACH_SELECTION_FROM_COMMAND_LINE
425 /* How the current machine type was selected. */
426 static enum mach_selection_type mach_selection_mode
= MACH_SELECTION_NONE
;
428 /* The hash table of instruction opcodes. */
429 static htab_t arc_opcode_hash
;
431 /* The hash table of register symbols. */
432 static htab_t arc_reg_hash
;
434 /* The hash table of aux register symbols. */
435 static htab_t arc_aux_hash
;
437 /* The hash table of address types. */
438 static htab_t arc_addrtype_hash
;
440 #define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
441 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
442 E_ARC_MACH_ARC600, EXTRA}
443 #define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
444 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
445 E_ARC_MACH_ARC700, EXTRA}
446 #define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
447 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
448 EF_ARC_CPU_ARCV2EM, EXTRA}
449 #define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
450 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
451 EF_ARC_CPU_ARCV2HS, EXTRA}
452 #define ARC_CPU_TYPE_NONE \
455 /* A table of CPU names and opcode sets. */
456 static const struct cpu_type
466 #include "elf/arc-cpu.def"
469 /* Information about the cpu/variant we're assembling for. */
470 static struct cpu_type selected_cpu
= { 0, 0, 0, E_ARC_OSABI_CURRENT
, 0 };
472 /* TRUE if current assembly code uses RF16 only registers. */
473 static bool rf16_only
= true;
476 static unsigned mpy_option
= 0;
479 static unsigned pic_option
= 0;
481 /* Use small data. */
482 static unsigned sda_option
= 0;
485 static unsigned tls_option
= 0;
487 /* Command line given features. */
488 static unsigned cl_features
= 0;
490 /* Used by the arc_reloc_op table. Order is important. */
491 #define O_gotoff O_md1 /* @gotoff relocation. */
492 #define O_gotpc O_md2 /* @gotpc relocation. */
493 #define O_plt O_md3 /* @plt relocation. */
494 #define O_sda O_md4 /* @sda relocation. */
495 #define O_pcl O_md5 /* @pcl relocation. */
496 #define O_tlsgd O_md6 /* @tlsgd relocation. */
497 #define O_tlsie O_md7 /* @tlsie relocation. */
498 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
499 #define O_tpoff O_md9 /* @tpoff relocation. */
500 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
501 #define O_dtpoff O_md11 /* @dtpoff relocation. */
502 #define O_last O_dtpoff
504 /* Used to define a bracket as operand in tokens. */
505 #define O_bracket O_md32
507 /* Used to define a colon as an operand in tokens. */
508 #define O_colon O_md31
510 /* Used to define address types in nps400. */
511 #define O_addrtype O_md30
513 /* Dummy relocation, to be sorted out. */
514 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
516 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
518 /* A table to map the spelling of a relocation operand into an appropriate
519 bfd_reloc_code_real_type type. The table is assumed to be ordered such
520 that op-O_literal indexes into it. */
521 #define ARC_RELOC_TABLE(op) \
522 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
524 : (int) (op) - (int) O_gotoff) ])
526 #define DEF(NAME, RELOC, REQ) \
527 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
529 static const struct arc_reloc_op_tag
531 /* String to lookup. */
533 /* Size of the string. */
535 /* Which operator to use. */
537 extended_bfd_reloc_code_real_type reloc
;
538 /* Allows complex relocation expression like identifier@reloc +
540 unsigned int complex_expr
: 1;
544 DEF (gotoff
, BFD_RELOC_ARC_GOTOFF
, 1),
545 DEF (gotpc
, BFD_RELOC_ARC_GOTPC32
, 0),
546 DEF (plt
, BFD_RELOC_ARC_PLT32
, 0),
547 DEF (sda
, DUMMY_RELOC_ARC_ENTRY
, 1),
548 DEF (pcl
, BFD_RELOC_ARC_PC32
, 1),
549 DEF (tlsgd
, BFD_RELOC_ARC_TLS_GD_GOT
, 0),
550 DEF (tlsie
, BFD_RELOC_ARC_TLS_IE_GOT
, 0),
551 DEF (tpoff9
, BFD_RELOC_ARC_TLS_LE_S9
, 0),
552 DEF (tpoff
, BFD_RELOC_ARC_TLS_LE_32
, 1),
553 DEF (dtpoff9
, BFD_RELOC_ARC_TLS_DTPOFF_S9
, 0),
554 DEF (dtpoff
, BFD_RELOC_ARC_TLS_DTPOFF
, 1),
557 static const int arc_num_reloc_op
558 = sizeof (arc_reloc_op
) / sizeof (*arc_reloc_op
);
560 /* Structure for relaxable instruction that have to be swapped with a
561 smaller alternative instruction. */
562 struct arc_relaxable_ins
564 /* Mnemonic that should be checked. */
565 const char *mnemonic_r
;
567 /* Operands that should be checked.
568 Indexes of operands from operand array. */
569 enum rlx_operand_type operands
[6];
571 /* Flags that should be checked. */
572 unsigned flag_classes
[5];
574 /* Mnemonic (smaller) alternative to be used later for relaxation. */
575 const char *mnemonic_alt
;
577 /* Index of operand that generic relaxation has to check. */
580 /* Base subtype index used. */
581 enum arc_rlx_types subtype
;
584 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
585 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
586 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
590 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
591 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
592 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
597 /* ARC relaxation table. */
598 const relax_typeS md_relax_table
[] =
605 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL
),
606 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
610 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B
),
611 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE
),
616 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6
),
617 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM
),
618 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
620 /* LD_S a, [b, u7] ->
621 LD<zz><.x><.aa><.di> a, [b, s9] ->
622 LD<zz><.x><.aa><.di> a, [b, limm] */
623 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9
),
624 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM
),
625 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE
),
630 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12
),
631 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM
),
632 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
636 SUB<.f> a, b, limm. */
637 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6
),
638 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM
),
639 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
641 /* MPY<.f> a, b, u6 ->
642 MPY<.f> a, b, limm. */
643 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM
),
644 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
646 /* MOV<.f><.cc> b, u6 ->
647 MOV<.f><.cc> b, limm. */
648 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM
),
649 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
651 /* ADD<.f><.cc> b, b, u6 ->
652 ADD<.f><.cc> b, b, limm. */
653 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM
),
654 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE
),
657 /* Order of this table's entries matters! */
658 const struct arc_relaxable_ins arc_relaxable_insns
[] =
660 { "bl", { IMMEDIATE
}, { 0 }, "bl_s", 0, ARC_RLX_BL_S
},
661 { "b", { IMMEDIATE
}, { 0 }, "b_s", 0, ARC_RLX_B_S
},
662 { "add", { REGISTER
, REGISTER_DUP
, IMMEDIATE
}, { 5, 1, 0 }, "add",
663 2, ARC_RLX_ADD_RRU6
},
664 { "add", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "add_s", 2,
666 { "add", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "add", 2,
668 { "ld", { REGISTER_S
, BRACKET
, REGISTER_S
, IMMEDIATE
, BRACKET
},
669 { 0 }, "ld_s", 3, ARC_RLX_LD_U7
},
670 { "ld", { REGISTER
, BRACKET
, REGISTER_NO_GP
, IMMEDIATE
, BRACKET
},
671 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9
},
672 { "mov", { REGISTER_S
, IMMEDIATE
}, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8
},
673 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12
},
674 { "mov", { REGISTER
, IMMEDIATE
}, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6
},
675 { "sub", { REGISTER_S
, REGISTER_S
, IMMEDIATE
}, { 0 }, "sub_s", 2,
677 { "sub", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "sub", 2,
679 { "mpy", { REGISTER
, REGISTER
, IMMEDIATE
}, { 5, 0 }, "mpy", 2,
683 const unsigned arc_num_relaxable_ins
= ARRAY_SIZE (arc_relaxable_insns
);
685 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
686 symbolS
* GOT_symbol
= 0;
688 /* Set to TRUE when we assemble instructions. */
689 static bool assembling_insn
= false;
691 /* List with attributes set explicitly. */
692 static bool attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
694 /* Functions implementation. */
696 /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
697 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
698 are no matching entries in ARC_OPCODE_HASH. */
700 static const struct arc_opcode_hash_entry
*
701 arc_find_opcode (const char *name
)
703 const struct arc_opcode_hash_entry
*entry
;
705 entry
= str_hash_find (arc_opcode_hash
, name
);
709 /* Initialise the iterator ITER. */
712 arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator
*iter
)
718 /* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
719 calls to this function. Return NULL when all ARC_OPCODE entries have
722 static const struct arc_opcode
*
723 arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry
*entry
,
724 struct arc_opcode_hash_entry_iterator
*iter
)
726 if (iter
->opcode
== NULL
&& iter
->index
== 0)
728 gas_assert (entry
->count
> 0);
729 iter
->opcode
= entry
->opcode
[iter
->index
];
731 else if (iter
->opcode
!= NULL
)
733 const char *old_name
= iter
->opcode
->name
;
736 if (iter
->opcode
->name
== NULL
737 || strcmp (old_name
, iter
->opcode
->name
) != 0)
740 if (iter
->index
== entry
->count
)
743 iter
->opcode
= entry
->opcode
[iter
->index
];
750 /* Insert an opcode into opcode hash structure. */
753 arc_insert_opcode (const struct arc_opcode
*opcode
)
756 struct arc_opcode_hash_entry
*entry
;
759 entry
= str_hash_find (arc_opcode_hash
, name
);
762 entry
= XNEW (struct arc_opcode_hash_entry
);
764 entry
->opcode
= NULL
;
766 if (str_hash_insert (arc_opcode_hash
, name
, entry
, 0) != NULL
)
767 as_fatal (_("duplicate %s"), name
);
770 entry
->opcode
= XRESIZEVEC (const struct arc_opcode
*, entry
->opcode
,
773 entry
->opcode
[entry
->count
] = opcode
;
778 arc_opcode_free (void *elt
)
780 string_tuple_t
*tuple
= (string_tuple_t
*) elt
;
781 struct arc_opcode_hash_entry
*entry
= (void *) tuple
->value
;
782 free (entry
->opcode
);
787 /* Like md_number_to_chars but for middle-endian values. The 4-byte limm
788 value, is encoded as 'middle-endian' for a little-endian target. This
789 function is used for regular 4, 6, and 8 byte instructions as well. */
792 md_number_to_chars_midend (char *buf
, unsigned long long val
, int n
)
797 md_number_to_chars (buf
, val
, n
);
800 md_number_to_chars (buf
, (val
& 0xffff00000000ull
) >> 32, 2);
801 md_number_to_chars_midend (buf
+ 2, (val
& 0xffffffff), 4);
804 md_number_to_chars (buf
, (val
& 0xffff0000) >> 16, 2);
805 md_number_to_chars (buf
+ 2, (val
& 0xffff), 2);
808 md_number_to_chars_midend (buf
, (val
& 0xffffffff00000000ull
) >> 32, 4);
809 md_number_to_chars_midend (buf
+ 4, (val
& 0xffffffff), 4);
816 /* Check if a feature is allowed for a specific CPU. */
819 arc_check_feature (void)
823 if (!selected_cpu
.features
824 || !selected_cpu
.name
)
827 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
828 if ((selected_cpu
.features
& feature_list
[i
].feature
)
829 && !(selected_cpu
.flags
& feature_list
[i
].cpus
))
830 as_bad (_("invalid %s option for %s cpu"), feature_list
[i
].name
,
833 for (i
= 0; i
< ARRAY_SIZE (conflict_list
); i
++)
834 if ((selected_cpu
.features
& conflict_list
[i
]) == conflict_list
[i
])
835 as_bad(_("conflicting ISA extension attributes."));
838 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
839 the relevant static global variables. Parameter SEL describes where
840 this selection originated from. */
843 arc_select_cpu (const char *arg
, enum mach_selection_type sel
)
846 static struct cpu_type old_cpu
= { 0, 0, 0, E_ARC_OSABI_CURRENT
, 0 };
848 /* We should only set a default if we've not made a selection from some
850 gas_assert (sel
!= MACH_SELECTION_FROM_DEFAULT
851 || mach_selection_mode
== MACH_SELECTION_NONE
);
853 if ((mach_selection_mode
== MACH_SELECTION_FROM_CPU_DIRECTIVE
)
854 && (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
))
855 as_bad (_("Multiple .cpu directives found"));
857 /* Look for a matching entry in CPU_TYPES array. */
858 for (i
= 0; cpu_types
[i
].name
; ++i
)
860 if (!strcasecmp (cpu_types
[i
].name
, arg
))
862 /* If a previous selection was made on the command line, then we
863 allow later selections on the command line to override earlier
864 ones. However, a selection from a '.cpu NAME' directive must
865 match the command line selection, or we give a warning. */
866 if (mach_selection_mode
== MACH_SELECTION_FROM_COMMAND_LINE
)
868 gas_assert (sel
== MACH_SELECTION_FROM_COMMAND_LINE
869 || sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
);
870 if (sel
== MACH_SELECTION_FROM_CPU_DIRECTIVE
871 && selected_cpu
.mach
!= cpu_types
[i
].mach
)
873 as_warn (_("Command-line value overrides \".cpu\" directive"));
877 /* Initialise static global data about selected machine type. */
878 selected_cpu
.flags
= cpu_types
[i
].flags
;
879 selected_cpu
.name
= cpu_types
[i
].name
;
880 selected_cpu
.features
= cpu_types
[i
].features
| cl_features
;
881 selected_cpu
.mach
= cpu_types
[i
].mach
;
882 selected_cpu
.eflags
= ((selected_cpu
.eflags
& ~EF_ARC_MACH_MSK
)
883 | cpu_types
[i
].eflags
);
888 if (!cpu_types
[i
].name
)
889 as_fatal (_("unknown architecture: %s\n"), arg
);
891 /* Check if set features are compatible with the chosen CPU. */
892 arc_check_feature ();
894 /* If we change the CPU, we need to re-init the bfd. */
895 if (mach_selection_mode
!= MACH_SELECTION_NONE
896 && (old_cpu
.mach
!= selected_cpu
.mach
))
898 bfd_find_target (arc_target_format
, stdoutput
);
899 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
900 as_warn (_("Could not set architecture and machine"));
903 mach_selection_mode
= sel
;
904 old_cpu
= selected_cpu
;
907 /* Here ends all the ARCompact extension instruction assembling
911 arc_extra_reloc (int r_type
)
914 symbolS
*sym
, *lab
= NULL
;
916 if (*input_line_pointer
== '@')
917 input_line_pointer
++;
918 c
= get_symbol_name (&sym_name
);
919 sym
= symbol_find_or_make (sym_name
);
920 restore_line_pointer (c
);
921 if (c
== ',' && r_type
== BFD_RELOC_ARC_TLS_GD_LD
)
923 ++input_line_pointer
;
925 c
= get_symbol_name (&lab_name
);
926 lab
= symbol_find_or_make (lab_name
);
927 restore_line_pointer (c
);
930 /* These relocations exist as a mechanism for the compiler to tell the
931 linker how to patch the code if the tls model is optimised. However,
932 the relocation itself does not require any space within the assembler
933 fragment, and so we pass a size of 0.
935 The lines that generate these relocations look like this:
937 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
939 The '.tls_gd_ld @.tdata' is processed first and generates the
940 additional relocation, while the 'bl __tls_get_addr@plt' is processed
941 second and generates the additional branch.
943 It is possible that the additional relocation generated by the
944 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
945 while the 'bl __tls_get_addr@plt' will be generated as the first thing
946 in the next fragment. This will be fine; both relocations will still
947 appear to be at the same address in the generated object file.
948 However, this only works as the additional relocation is generated
949 with size of 0 bytes. */
951 = fix_new (frag_now
, /* Which frag? */
952 frag_now_fix (), /* Where in that frag? */
953 0, /* size: 1, 2, or 4 usually. */
954 sym
, /* X_add_symbol. */
955 0, /* X_add_number. */
956 false, /* TRUE if PC-relative relocation. */
957 r_type
/* Relocation type. */);
958 fixP
->fx_subsy
= lab
;
962 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED
,
963 symbolS
*symbolP
, addressT size
)
968 if (*input_line_pointer
== ',')
970 align
= parse_align (1);
972 if (align
== (addressT
) -1)
987 bss_alloc (symbolP
, size
, align
);
988 S_CLEAR_EXTERNAL (symbolP
);
994 arc_lcomm (int ignore
)
996 symbolS
*symbolP
= s_comm_internal (ignore
, arc_lcomm_internal
);
999 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
1002 /* Select the cpu we're assembling for. */
1005 arc_option (int ignore ATTRIBUTE_UNUSED
)
1009 const char *cpu_name
;
1011 c
= get_symbol_name (&cpu
);
1014 if ((!strcmp ("ARC600", cpu
))
1015 || (!strcmp ("ARC601", cpu
))
1016 || (!strcmp ("A6", cpu
)))
1017 cpu_name
= "arc600";
1018 else if ((!strcmp ("ARC700", cpu
))
1019 || (!strcmp ("A7", cpu
)))
1020 cpu_name
= "arc700";
1021 else if (!strcmp ("EM", cpu
))
1023 else if (!strcmp ("HS", cpu
))
1025 else if (!strcmp ("NPS400", cpu
))
1026 cpu_name
= "nps400";
1028 arc_select_cpu (cpu_name
, MACH_SELECTION_FROM_CPU_DIRECTIVE
);
1030 restore_line_pointer (c
);
1031 demand_empty_rest_of_line ();
1034 /* Smartly print an expression. */
1037 debug_exp (expressionS
*t
)
1039 const char *name ATTRIBUTE_UNUSED
;
1040 const char *namemd ATTRIBUTE_UNUSED
;
1042 pr_debug ("debug_exp: ");
1046 default: name
= "unknown"; break;
1047 case O_illegal
: name
= "O_illegal"; break;
1048 case O_absent
: name
= "O_absent"; break;
1049 case O_constant
: name
= "O_constant"; break;
1050 case O_symbol
: name
= "O_symbol"; break;
1051 case O_symbol_rva
: name
= "O_symbol_rva"; break;
1052 case O_register
: name
= "O_register"; break;
1053 case O_big
: name
= "O_big"; break;
1054 case O_uminus
: name
= "O_uminus"; break;
1055 case O_bit_not
: name
= "O_bit_not"; break;
1056 case O_logical_not
: name
= "O_logical_not"; break;
1057 case O_multiply
: name
= "O_multiply"; break;
1058 case O_divide
: name
= "O_divide"; break;
1059 case O_modulus
: name
= "O_modulus"; break;
1060 case O_left_shift
: name
= "O_left_shift"; break;
1061 case O_right_shift
: name
= "O_right_shift"; break;
1062 case O_bit_inclusive_or
: name
= "O_bit_inclusive_or"; break;
1063 case O_bit_or_not
: name
= "O_bit_or_not"; break;
1064 case O_bit_exclusive_or
: name
= "O_bit_exclusive_or"; break;
1065 case O_bit_and
: name
= "O_bit_and"; break;
1066 case O_add
: name
= "O_add"; break;
1067 case O_subtract
: name
= "O_subtract"; break;
1068 case O_eq
: name
= "O_eq"; break;
1069 case O_ne
: name
= "O_ne"; break;
1070 case O_lt
: name
= "O_lt"; break;
1071 case O_le
: name
= "O_le"; break;
1072 case O_ge
: name
= "O_ge"; break;
1073 case O_gt
: name
= "O_gt"; break;
1074 case O_logical_and
: name
= "O_logical_and"; break;
1075 case O_logical_or
: name
= "O_logical_or"; break;
1076 case O_index
: name
= "O_index"; break;
1077 case O_bracket
: name
= "O_bracket"; break;
1078 case O_colon
: name
= "O_colon"; break;
1079 case O_addrtype
: name
= "O_addrtype"; break;
1084 default: namemd
= "unknown"; break;
1085 case O_gotoff
: namemd
= "O_gotoff"; break;
1086 case O_gotpc
: namemd
= "O_gotpc"; break;
1087 case O_plt
: namemd
= "O_plt"; break;
1088 case O_sda
: namemd
= "O_sda"; break;
1089 case O_pcl
: namemd
= "O_pcl"; break;
1090 case O_tlsgd
: namemd
= "O_tlsgd"; break;
1091 case O_tlsie
: namemd
= "O_tlsie"; break;
1092 case O_tpoff9
: namemd
= "O_tpoff9"; break;
1093 case O_tpoff
: namemd
= "O_tpoff"; break;
1094 case O_dtpoff9
: namemd
= "O_dtpoff9"; break;
1095 case O_dtpoff
: namemd
= "O_dtpoff"; break;
1098 pr_debug ("%s (%s, %s, %d, %s)", name
,
1099 (t
->X_add_symbol
) ? S_GET_NAME (t
->X_add_symbol
) : "--",
1100 (t
->X_op_symbol
) ? S_GET_NAME (t
->X_op_symbol
) : "--",
1101 (int) t
->X_add_number
,
1102 (t
->X_md
) ? namemd
: "--");
1107 /* Helper for parsing an argument, used for sorting out the relocation
1111 parse_reloc_symbol (expressionS
*resultP
)
1113 char *reloc_name
, c
, *sym_name
;
1116 const struct arc_reloc_op_tag
*r
;
1120 /* A relocation operand has the following form
1121 @identifier@relocation_type. The identifier is already in
1123 if (resultP
->X_op
!= O_symbol
)
1125 as_bad (_("No valid label relocation operand"));
1126 resultP
->X_op
= O_illegal
;
1130 /* Parse @relocation_type. */
1131 input_line_pointer
++;
1132 c
= get_symbol_name (&reloc_name
);
1133 len
= input_line_pointer
- reloc_name
;
1136 as_bad (_("No relocation operand"));
1137 resultP
->X_op
= O_illegal
;
1141 /* Go through known relocation and try to find a match. */
1142 r
= &arc_reloc_op
[0];
1143 for (i
= arc_num_reloc_op
- 1; i
>= 0; i
--, r
++)
1144 if (len
== r
->length
1145 && memcmp (reloc_name
, r
->name
, len
) == 0)
1149 as_bad (_("Unknown relocation operand: @%s"), reloc_name
);
1150 resultP
->X_op
= O_illegal
;
1154 *input_line_pointer
= c
;
1155 SKIP_WHITESPACE_AFTER_NAME ();
1156 /* Extra check for TLS: base. */
1157 if (*input_line_pointer
== '@')
1159 if (resultP
->X_op_symbol
!= NULL
1160 || resultP
->X_op
!= O_symbol
)
1162 as_bad (_("Unable to parse TLS base: %s"),
1163 input_line_pointer
);
1164 resultP
->X_op
= O_illegal
;
1167 input_line_pointer
++;
1168 c
= get_symbol_name (&sym_name
);
1169 base
= symbol_find_or_make (sym_name
);
1170 resultP
->X_op
= O_subtract
;
1171 resultP
->X_op_symbol
= base
;
1172 restore_line_pointer (c
);
1173 right
.X_add_number
= 0;
1176 if ((*input_line_pointer
!= '+')
1177 && (*input_line_pointer
!= '-'))
1178 right
.X_add_number
= 0;
1181 /* Parse the constant of a complex relocation expression
1182 like @identifier@reloc +/- const. */
1183 if (! r
->complex_expr
)
1185 as_bad (_("@%s is not a complex relocation."), r
->name
);
1186 resultP
->X_op
= O_illegal
;
1189 expression (&right
);
1190 if (right
.X_op
!= O_constant
)
1192 as_bad (_("Bad expression: @%s + %s."),
1193 r
->name
, input_line_pointer
);
1194 resultP
->X_op
= O_illegal
;
1199 resultP
->X_md
= r
->op
;
1200 resultP
->X_add_number
= right
.X_add_number
;
1203 /* Parse the arguments to an opcode. */
1206 tokenize_arguments (char *str
,
1210 char *old_input_line_pointer
;
1211 bool saw_comma
= false;
1212 bool saw_arg
= false;
1216 memset (tok
, 0, sizeof (*tok
) * ntok
);
1218 /* Save and restore input_line_pointer around this function. */
1219 old_input_line_pointer
= input_line_pointer
;
1220 input_line_pointer
= str
;
1222 while (*input_line_pointer
)
1225 switch (*input_line_pointer
)
1231 input_line_pointer
++;
1232 if (saw_comma
|| !saw_arg
)
1239 ++input_line_pointer
;
1241 if (!saw_arg
|| num_args
== ntok
)
1243 tok
->X_op
= O_bracket
;
1250 input_line_pointer
++;
1251 if (brk_lvl
|| num_args
== ntok
)
1254 tok
->X_op
= O_bracket
;
1260 input_line_pointer
++;
1261 if (!saw_arg
|| num_args
== ntok
)
1263 tok
->X_op
= O_colon
;
1270 /* We have labels, function names and relocations, all
1271 starting with @ symbol. Sort them out. */
1272 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1276 input_line_pointer
++;
1277 tok
->X_op
= O_symbol
;
1278 tok
->X_md
= O_absent
;
1281 if (*input_line_pointer
== '@')
1282 parse_reloc_symbol (tok
);
1286 if (tok
->X_op
== O_illegal
1287 || tok
->X_op
== O_absent
1288 || num_args
== ntok
)
1298 /* Can be a register. */
1299 ++input_line_pointer
;
1303 if ((saw_arg
&& !saw_comma
) || num_args
== ntok
)
1306 tok
->X_op
= O_absent
;
1307 tok
->X_md
= O_absent
;
1310 /* Legacy: There are cases when we have
1311 identifier@relocation_type, if it is the case parse the
1312 relocation type as well. */
1313 if (*input_line_pointer
== '@')
1314 parse_reloc_symbol (tok
);
1318 if (tok
->X_op
== O_illegal
1319 || tok
->X_op
== O_absent
1320 || num_args
== ntok
)
1332 if (saw_comma
|| brk_lvl
)
1334 input_line_pointer
= old_input_line_pointer
;
1340 as_bad (_("Brackets in operand field incorrect"));
1342 as_bad (_("extra comma"));
1344 as_bad (_("missing argument"));
1346 as_bad (_("missing comma or colon"));
1347 input_line_pointer
= old_input_line_pointer
;
1351 /* Parse the flags to a structure. */
1354 tokenize_flags (const char *str
,
1355 struct arc_flags flags
[],
1358 char *old_input_line_pointer
;
1359 bool saw_flg
= false;
1360 bool saw_dot
= false;
1364 memset (flags
, 0, sizeof (*flags
) * nflg
);
1366 /* Save and restore input_line_pointer around this function. */
1367 old_input_line_pointer
= input_line_pointer
;
1368 input_line_pointer
= (char *) str
;
1370 while (*input_line_pointer
)
1372 switch (*input_line_pointer
)
1379 input_line_pointer
++;
1387 if (saw_flg
&& !saw_dot
)
1390 if (num_flags
>= nflg
)
1393 flgnamelen
= strspn (input_line_pointer
,
1394 "abcdefghijklmnopqrstuvwxyz0123456789");
1395 if (flgnamelen
> MAX_FLAG_NAME_LENGTH
)
1398 memcpy (flags
->name
, input_line_pointer
, flgnamelen
);
1400 input_line_pointer
+= flgnamelen
;
1410 input_line_pointer
= old_input_line_pointer
;
1415 as_bad (_("extra dot"));
1417 as_bad (_("unrecognized flag"));
1419 as_bad (_("failed to parse flags"));
1420 input_line_pointer
= old_input_line_pointer
;
1424 /* Apply the fixups in order. */
1427 apply_fixups (struct arc_insn
*insn
, fragS
*fragP
, int fix
)
1431 for (i
= 0; i
< insn
->nfixups
; i
++)
1433 struct arc_fixup
*fixup
= &insn
->fixups
[i
];
1434 int size
, pcrel
, offset
= 0;
1436 /* FIXME! the reloc size is wrong in the BFD file.
1437 When it is fixed please delete me. */
1438 size
= ((insn
->len
== 2) && !fixup
->islong
) ? 2 : 4;
1443 /* Some fixups are only used internally, thus no howto. */
1444 if ((int) fixup
->reloc
== 0)
1445 as_fatal (_("Unhandled reloc type"));
1447 if ((int) fixup
->reloc
< 0)
1449 /* FIXME! the reloc size is wrong in the BFD file.
1450 When it is fixed please enable me.
1451 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
1452 pcrel
= fixup
->pcrel
;
1456 reloc_howto_type
*reloc_howto
=
1457 bfd_reloc_type_lookup (stdoutput
,
1458 (bfd_reloc_code_real_type
) fixup
->reloc
);
1459 gas_assert (reloc_howto
);
1461 /* FIXME! the reloc size is wrong in the BFD file.
1462 When it is fixed please enable me.
1463 size = bfd_get_reloc_size (reloc_howto); */
1464 pcrel
= reloc_howto
->pc_relative
;
1467 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1469 fragP
->fr_file
, fragP
->fr_line
,
1470 (fixup
->reloc
< 0) ? "Internal" :
1471 bfd_get_reloc_code_name (fixup
->reloc
),
1474 fix_new_exp (fragP
, fix
+ offset
,
1475 size
, &fixup
->exp
, pcrel
, fixup
->reloc
);
1477 /* Check for ZOLs, and update symbol info if any. */
1478 if (LP_INSN (insn
->insn
))
1480 gas_assert (fixup
->exp
.X_add_symbol
);
1481 ARC_SET_FLAG (fixup
->exp
.X_add_symbol
, ARC_FLAG_ZOL
);
1486 /* Actually output an instruction with its fixup. */
1489 emit_insn0 (struct arc_insn
*insn
, char *where
, bool relax
)
1494 pr_debug ("Emit insn : 0x%llx\n", insn
->insn
);
1495 pr_debug ("\tLength : %d\n", insn
->len
);
1496 pr_debug ("\tLong imm: 0x%lx\n", insn
->limm
);
1498 /* Write out the instruction. */
1499 total_len
= insn
->len
+ (insn
->has_limm
? 4 : 0);
1501 f
= frag_more (total_len
);
1503 md_number_to_chars_midend(f
, insn
->insn
, insn
->len
);
1506 md_number_to_chars_midend (f
+ insn
->len
, insn
->limm
, 4);
1507 dwarf2_emit_insn (total_len
);
1510 apply_fixups (insn
, frag_now
, (f
- frag_now
->fr_literal
));
1514 emit_insn1 (struct arc_insn
*insn
)
1516 /* How frag_var's args are currently configured:
1517 - rs_machine_dependent, to dictate it's a relaxation frag.
1518 - FRAG_MAX_GROWTH, maximum size of instruction
1519 - 0, variable size that might grow...unused by generic relaxation.
1520 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1521 - s, opand expression.
1522 - 0, offset but it's unused.
1523 - 0, opcode but it's unused. */
1524 symbolS
*s
= make_expr_symbol (&insn
->fixups
[0].exp
);
1525 frag_now
->tc_frag_data
.pcrel
= insn
->fixups
[0].pcrel
;
1527 if (frag_room () < FRAG_MAX_GROWTH
)
1529 /* Handle differently when frag literal memory is exhausted.
1530 This is used because when there's not enough memory left in
1531 the current frag, a new frag is created and the information
1532 we put into frag_now->tc_frag_data is disregarded. */
1534 struct arc_relax_type relax_info_copy
;
1535 relax_substateT subtype
= frag_now
->fr_subtype
;
1537 memcpy (&relax_info_copy
, &frag_now
->tc_frag_data
,
1538 sizeof (struct arc_relax_type
));
1540 frag_wane (frag_now
);
1541 frag_grow (FRAG_MAX_GROWTH
);
1543 memcpy (&frag_now
->tc_frag_data
, &relax_info_copy
,
1544 sizeof (struct arc_relax_type
));
1546 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1550 frag_var (rs_machine_dependent
, FRAG_MAX_GROWTH
, 0,
1551 frag_now
->fr_subtype
, s
, 0, 0);
1555 emit_insn (struct arc_insn
*insn
)
1560 emit_insn0 (insn
, NULL
, false);
1563 /* Check whether a symbol involves a register. */
1566 contains_register (symbolS
*sym
)
1570 expressionS
*ex
= symbol_get_value_expression (sym
);
1572 return ((O_register
== ex
->X_op
)
1573 && !contains_register (ex
->X_add_symbol
)
1574 && !contains_register (ex
->X_op_symbol
));
1580 /* Returns the register number within a symbol. */
1583 get_register (symbolS
*sym
)
1585 if (!contains_register (sym
))
1588 expressionS
*ex
= symbol_get_value_expression (sym
);
1589 return regno (ex
->X_add_number
);
1592 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1593 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1596 generic_reloc_p (extended_bfd_reloc_code_real_type reloc
)
1603 case BFD_RELOC_ARC_SDA_LDST
:
1604 case BFD_RELOC_ARC_SDA_LDST1
:
1605 case BFD_RELOC_ARC_SDA_LDST2
:
1606 case BFD_RELOC_ARC_SDA16_LD
:
1607 case BFD_RELOC_ARC_SDA16_LD1
:
1608 case BFD_RELOC_ARC_SDA16_LD2
:
1609 case BFD_RELOC_ARC_SDA16_ST2
:
1610 case BFD_RELOC_ARC_SDA32_ME
:
1617 /* Allocates a tok entry. */
1620 allocate_tok (expressionS
*tok
, int ntok
, int cidx
)
1622 if (ntok
> MAX_INSN_ARGS
- 2)
1623 return 0; /* No space left. */
1626 return 0; /* Incorrect args. */
1628 memcpy (&tok
[ntok
+1], &tok
[ntok
], sizeof (*tok
));
1631 return 1; /* Success. */
1632 return allocate_tok (tok
, ntok
- 1, cidx
);
1635 /* Check if an particular ARC feature is enabled. */
1638 check_cpu_feature (insn_subclass_t sc
)
1640 if (is_code_density_p (sc
) && !(selected_cpu
.features
& CD
))
1643 if (is_spfp_p (sc
) && !(selected_cpu
.features
& SPX
))
1646 if (is_dpfp_p (sc
) && !(selected_cpu
.features
& DPX
))
1649 if (is_fpuda_p (sc
) && !(selected_cpu
.features
& DPA
))
1652 if (is_nps400_p (sc
) && !(selected_cpu
.features
& NPS400
))
1658 /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1659 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1660 array and returns TRUE if the flag operands all match, otherwise,
1661 returns FALSE, in which case the FIRST_PFLAG array may have been
1665 parse_opcode_flags (const struct arc_opcode
*opcode
,
1667 struct arc_flags
*first_pflag
)
1670 const unsigned char *flgidx
;
1673 for (i
= 0; i
< nflgs
; i
++)
1674 first_pflag
[i
].flgp
= NULL
;
1676 /* Check the flags. Iterate over the valid flag classes. */
1677 for (flgidx
= opcode
->flags
; *flgidx
; ++flgidx
)
1679 /* Get a valid flag class. */
1680 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
1681 const unsigned *flgopridx
;
1683 struct arc_flags
*pflag
= NULL
;
1685 /* Check if opcode has implicit flag classes. */
1686 if (cl_flags
->flag_class
& F_CLASS_IMPLICIT
)
1689 /* Check for extension conditional codes. */
1690 if (ext_condcode
.arc_ext_condcode
1691 && cl_flags
->flag_class
& F_CLASS_EXTEND
)
1693 struct arc_flag_operand
*pf
= ext_condcode
.arc_ext_condcode
;
1696 pflag
= first_pflag
;
1697 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1699 if (!strcmp (pf
->name
, pflag
->name
))
1701 if (pflag
->flgp
!= NULL
)
1714 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
1716 const struct arc_flag_operand
*flg_operand
;
1718 pflag
= first_pflag
;
1719 flg_operand
= &arc_flag_operands
[*flgopridx
];
1720 for (i
= 0; i
< nflgs
; i
++, pflag
++)
1722 /* Match against the parsed flags. */
1723 if (!strcmp (flg_operand
->name
, pflag
->name
))
1725 if (pflag
->flgp
!= NULL
)
1728 pflag
->flgp
= flg_operand
;
1730 break; /* goto next flag class and parsed flag. */
1735 if ((cl_flags
->flag_class
& F_CLASS_REQUIRED
) && cl_matches
== 0)
1737 if ((cl_flags
->flag_class
& F_CLASS_OPTIONAL
) && cl_matches
> 1)
1741 /* Did I check all the parsed flags? */
1746 /* Search forward through all variants of an opcode looking for a
1749 static const struct arc_opcode
*
1750 find_opcode_match (const struct arc_opcode_hash_entry
*entry
,
1753 struct arc_flags
*first_pflag
,
1756 const char **errmsg
)
1758 const struct arc_opcode
*opcode
;
1759 struct arc_opcode_hash_entry_iterator iter
;
1761 int got_cpu_match
= 0;
1762 expressionS bktok
[MAX_INSN_ARGS
];
1763 int bkntok
, maxerridx
= 0;
1765 const char *tmpmsg
= NULL
;
1767 arc_opcode_hash_entry_iterator_init (&iter
);
1768 memset (&emptyE
, 0, sizeof (emptyE
));
1769 memcpy (bktok
, tok
, MAX_INSN_ARGS
* sizeof (*tok
));
1772 for (opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
);
1774 opcode
= arc_opcode_hash_entry_iterator_next (entry
, &iter
))
1776 const unsigned char *opidx
;
1778 const expressionS
*t
= &emptyE
;
1780 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
1781 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->opcode
);
1783 /* Don't match opcodes that don't exist on this
1785 if (!(opcode
->cpu
& selected_cpu
.flags
))
1788 if (!check_cpu_feature (opcode
->subclass
))
1794 /* Check the operands. */
1795 for (opidx
= opcode
->operands
; *opidx
; ++opidx
)
1797 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
1799 /* Only take input from real operands. */
1800 if (ARC_OPERAND_IS_FAKE (operand
))
1803 /* When we expect input, make sure we have it. */
1807 /* Match operand type with expression type. */
1808 switch (operand
->flags
& ARC_OPERAND_TYPECHECK_MASK
)
1810 case ARC_OPERAND_ADDRTYPE
:
1814 /* Check to be an address type. */
1815 if (tok
[tokidx
].X_op
!= O_addrtype
)
1818 /* All address type operands need to have an insert
1819 method in order to check that we have the correct
1821 gas_assert (operand
->insert
!= NULL
);
1822 (*operand
->insert
) (0, tok
[tokidx
].X_add_number
,
1829 case ARC_OPERAND_IR
:
1830 /* Check to be a register. */
1831 if ((tok
[tokidx
].X_op
!= O_register
1832 || !is_ir_num (tok
[tokidx
].X_add_number
))
1833 && !(operand
->flags
& ARC_OPERAND_IGNORE
))
1836 /* If expect duplicate, make sure it is duplicate. */
1837 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
1839 /* Check for duplicate. */
1840 if (t
->X_op
!= O_register
1841 || !is_ir_num (t
->X_add_number
)
1842 || (regno (t
->X_add_number
) !=
1843 regno (tok
[tokidx
].X_add_number
)))
1847 /* Special handling? */
1848 if (operand
->insert
)
1851 (*operand
->insert
)(0,
1852 regno (tok
[tokidx
].X_add_number
),
1856 if (operand
->flags
& ARC_OPERAND_IGNORE
)
1858 /* Missing argument, create one. */
1859 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1862 tok
[tokidx
].X_op
= O_absent
;
1873 case ARC_OPERAND_BRAKET
:
1874 /* Check if bracket is also in opcode table as
1876 if (tok
[tokidx
].X_op
!= O_bracket
)
1880 case ARC_OPERAND_COLON
:
1881 /* Check if colon is also in opcode table as operand. */
1882 if (tok
[tokidx
].X_op
!= O_colon
)
1886 case ARC_OPERAND_LIMM
:
1887 case ARC_OPERAND_SIGNED
:
1888 case ARC_OPERAND_UNSIGNED
:
1889 switch (tok
[tokidx
].X_op
)
1897 /* Got an (too) early bracket, check if it is an
1898 ignored operand. N.B. This procedure works only
1899 when bracket is the last operand! */
1900 if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
1902 /* Insert the missing operand. */
1903 if (!allocate_tok (tok
, ntok
- 1, tokidx
))
1906 tok
[tokidx
].X_op
= O_absent
;
1914 const struct arc_aux_reg
*auxr
;
1916 if (opcode
->insn_class
!= AUXREG
)
1918 p
= S_GET_NAME (tok
[tokidx
].X_add_symbol
);
1920 /* For compatibility reasons, an aux register can
1921 be spelled with upper or lower case
1924 for (pp
= tmpp
; *pp
; ++pp
) *pp
= TOLOWER (*pp
);
1926 auxr
= str_hash_find (arc_aux_hash
, tmpp
);
1929 /* We modify the token array here, safe in the
1930 knowledge, that if this was the wrong
1931 choice then the original contents will be
1932 restored from BKTOK. */
1933 tok
[tokidx
].X_op
= O_constant
;
1934 tok
[tokidx
].X_add_number
= auxr
->address
;
1935 ARC_SET_FLAG (tok
[tokidx
].X_add_symbol
, ARC_FLAG_AUX
);
1939 if (tok
[tokidx
].X_op
!= O_constant
)
1944 /* Check the range. */
1945 if (operand
->bits
!= 32
1946 && !(operand
->flags
& ARC_OPERAND_NCHK
))
1948 offsetT min
, max
, val
;
1949 val
= tok
[tokidx
].X_add_number
;
1951 if (operand
->flags
& ARC_OPERAND_SIGNED
)
1953 max
= (1 << (operand
->bits
- 1)) - 1;
1954 min
= -(1 << (operand
->bits
- 1));
1958 max
= (1 << operand
->bits
) - 1;
1962 if (val
< min
|| val
> max
)
1964 tmpmsg
= _("immediate is out of bounds");
1968 /* Check alignments. */
1969 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
1972 tmpmsg
= _("immediate is not 32bit aligned");
1976 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
1979 tmpmsg
= _("immediate is not 16bit aligned");
1983 else if (operand
->flags
& ARC_OPERAND_NCHK
)
1985 if (operand
->insert
)
1988 (*operand
->insert
)(0,
1989 tok
[tokidx
].X_add_number
,
1994 else if (!(operand
->flags
& ARC_OPERAND_IGNORE
))
2000 /* Check if it is register range. */
2001 if ((tok
[tokidx
].X_add_number
== 0)
2002 && contains_register (tok
[tokidx
].X_add_symbol
)
2003 && contains_register (tok
[tokidx
].X_op_symbol
))
2007 regs
= get_register (tok
[tokidx
].X_add_symbol
);
2009 regs
|= get_register (tok
[tokidx
].X_op_symbol
);
2010 if (operand
->insert
)
2013 (*operand
->insert
)(0,
2026 if (operand
->default_reloc
== 0)
2027 goto match_failed
; /* The operand needs relocation. */
2029 /* Relocs requiring long immediate. FIXME! make it
2030 generic and move it to a function. */
2031 switch (tok
[tokidx
].X_md
)
2040 if (!(operand
->flags
& ARC_OPERAND_LIMM
))
2044 if (!generic_reloc_p (operand
->default_reloc
))
2052 /* If expect duplicate, make sure it is duplicate. */
2053 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
2055 if (t
->X_op
== O_illegal
2056 || t
->X_op
== O_absent
2057 || t
->X_op
== O_register
2058 || (t
->X_add_number
!= tok
[tokidx
].X_add_number
))
2060 tmpmsg
= _("operand is not duplicate of the "
2069 /* Everything else should have been fake. */
2077 /* Setup ready for flag parsing. */
2078 if (!parse_opcode_flags (opcode
, nflgs
, first_pflag
))
2080 tmpmsg
= _("flag mismatch");
2085 /* Possible match -- did we use all of our input? */
2092 tmpmsg
= _("too many arguments");
2096 /* Restore the original parameters. */
2097 memcpy (tok
, bktok
, MAX_INSN_ARGS
* sizeof (*tok
));
2099 if (tokidx
>= maxerridx
2108 *pcpumatch
= got_cpu_match
;
2113 /* Swap operand tokens. */
2116 swap_operand (expressionS
*operand_array
,
2118 unsigned destination
)
2120 expressionS cpy_operand
;
2121 expressionS
*src_operand
;
2122 expressionS
*dst_operand
;
2125 if (source
== destination
)
2128 src_operand
= &operand_array
[source
];
2129 dst_operand
= &operand_array
[destination
];
2130 size
= sizeof (expressionS
);
2132 /* Make copy of operand to swap with and swap. */
2133 memcpy (&cpy_operand
, dst_operand
, size
);
2134 memcpy (dst_operand
, src_operand
, size
);
2135 memcpy (src_operand
, &cpy_operand
, size
);
2138 /* Check if *op matches *tok type.
2139 Returns FALSE if they don't match, TRUE if they match. */
2142 pseudo_operand_match (const expressionS
*tok
,
2143 const struct arc_operand_operation
*op
)
2145 offsetT min
, max
, val
;
2147 const struct arc_operand
*operand_real
= &arc_operands
[op
->operand_idx
];
2153 if (operand_real
->bits
== 32 && (operand_real
->flags
& ARC_OPERAND_LIMM
))
2155 else if (!(operand_real
->flags
& ARC_OPERAND_IR
))
2157 val
= tok
->X_add_number
+ op
->count
;
2158 if (operand_real
->flags
& ARC_OPERAND_SIGNED
)
2160 max
= (1 << (operand_real
->bits
- 1)) - 1;
2161 min
= -(1 << (operand_real
->bits
- 1));
2165 max
= (1 << operand_real
->bits
) - 1;
2168 if (min
<= val
&& val
<= max
)
2174 /* Handle all symbols as long immediates or signed 9. */
2175 if (operand_real
->flags
& ARC_OPERAND_LIMM
2176 || ((operand_real
->flags
& ARC_OPERAND_SIGNED
)
2177 && operand_real
->bits
== 9))
2182 if (operand_real
->flags
& ARC_OPERAND_IR
)
2187 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2198 /* Find pseudo instruction in array. */
2200 static const struct arc_pseudo_insn
*
2201 find_pseudo_insn (const char *opname
,
2203 const expressionS
*tok
)
2205 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2206 const struct arc_operand_operation
*op
;
2210 for (i
= 0; i
< arc_num_pseudo_insn
; ++i
)
2212 pseudo_insn
= &arc_pseudo_insns
[i
];
2213 if (strcmp (pseudo_insn
->mnemonic_p
, opname
) == 0)
2215 op
= pseudo_insn
->operand
;
2216 for (j
= 0; j
< ntok
; ++j
)
2217 if (!pseudo_operand_match (&tok
[j
], &op
[j
]))
2220 /* Found the right instruction. */
2228 /* Assumes the expressionS *tok is of sufficient size. */
2230 static const struct arc_opcode_hash_entry
*
2231 find_special_case_pseudo (const char *opname
,
2235 struct arc_flags
*pflags
)
2237 const struct arc_pseudo_insn
*pseudo_insn
= NULL
;
2238 const struct arc_operand_operation
*operand_pseudo
;
2239 const struct arc_operand
*operand_real
;
2241 char construct_operand
[MAX_CONSTR_STR
];
2243 /* Find whether opname is in pseudo instruction array. */
2244 pseudo_insn
= find_pseudo_insn (opname
, *ntok
, tok
);
2246 if (pseudo_insn
== NULL
)
2249 /* Handle flag, Limited to one flag at the moment. */
2250 if (pseudo_insn
->flag_r
!= NULL
)
2251 *nflgs
+= tokenize_flags (pseudo_insn
->flag_r
, &pflags
[*nflgs
],
2252 MAX_INSN_FLGS
- *nflgs
);
2254 /* Handle operand operations. */
2255 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2257 operand_pseudo
= &pseudo_insn
->operand
[i
];
2258 operand_real
= &arc_operands
[operand_pseudo
->operand_idx
];
2260 if (operand_real
->flags
& ARC_OPERAND_BRAKET
2261 && !operand_pseudo
->needs_insert
)
2264 /* Has to be inserted (i.e. this token does not exist yet). */
2265 if (operand_pseudo
->needs_insert
)
2267 if (operand_real
->flags
& ARC_OPERAND_BRAKET
)
2269 tok
[i
].X_op
= O_bracket
;
2274 /* Check if operand is a register or constant and handle it
2276 if (operand_real
->flags
& ARC_OPERAND_IR
)
2277 snprintf (construct_operand
, MAX_CONSTR_STR
, "r%d",
2278 operand_pseudo
->count
);
2280 snprintf (construct_operand
, MAX_CONSTR_STR
, "%d",
2281 operand_pseudo
->count
);
2283 tokenize_arguments (construct_operand
, &tok
[i
], 1);
2287 else if (operand_pseudo
->count
)
2289 /* Operand number has to be adjusted accordingly (by operand
2291 switch (tok
[i
].X_op
)
2294 tok
[i
].X_add_number
+= operand_pseudo
->count
;
2307 /* Swap operands if necessary. Only supports one swap at the
2309 for (i
= 0; i
< pseudo_insn
->operand_cnt
; ++i
)
2311 operand_pseudo
= &pseudo_insn
->operand
[i
];
2313 if (operand_pseudo
->swap_operand_idx
== i
)
2316 swap_operand (tok
, i
, operand_pseudo
->swap_operand_idx
);
2318 /* Prevent a swap back later by breaking out. */
2322 return arc_find_opcode (pseudo_insn
->mnemonic_r
);
2325 static const struct arc_opcode_hash_entry
*
2326 find_special_case_flag (const char *opname
,
2328 struct arc_flags
*pflags
)
2332 unsigned flag_idx
, flag_arr_idx
;
2333 size_t flaglen
, oplen
;
2334 const struct arc_flag_special
*arc_flag_special_opcode
;
2335 const struct arc_opcode_hash_entry
*entry
;
2337 /* Search for special case instruction. */
2338 for (i
= 0; i
< arc_num_flag_special
; i
++)
2340 arc_flag_special_opcode
= &arc_flag_special_cases
[i
];
2341 oplen
= strlen (arc_flag_special_opcode
->name
);
2343 if (strncmp (opname
, arc_flag_special_opcode
->name
, oplen
) != 0)
2346 /* Found a potential special case instruction, now test for
2348 for (flag_arr_idx
= 0;; ++flag_arr_idx
)
2350 flag_idx
= arc_flag_special_opcode
->flags
[flag_arr_idx
];
2352 break; /* End of array, nothing found. */
2354 flagnm
= arc_flag_operands
[flag_idx
].name
;
2355 flaglen
= strlen (flagnm
);
2356 if (strcmp (opname
+ oplen
, flagnm
) == 0)
2358 entry
= arc_find_opcode (arc_flag_special_opcode
->name
);
2360 if (*nflgs
+ 1 > MAX_INSN_FLGS
)
2362 memcpy (pflags
[*nflgs
].name
, flagnm
, flaglen
);
2363 pflags
[*nflgs
].name
[flaglen
] = '\0';
2372 /* Used to find special case opcode. */
2374 static const struct arc_opcode_hash_entry
*
2375 find_special_case (const char *opname
,
2377 struct arc_flags
*pflags
,
2381 const struct arc_opcode_hash_entry
*entry
;
2383 entry
= find_special_case_pseudo (opname
, ntok
, tok
, nflgs
, pflags
);
2386 entry
= find_special_case_flag (opname
, nflgs
, pflags
);
2391 /* Autodetect cpu attribute list. */
2394 autodetect_attributes (const struct arc_opcode
*opcode
,
2395 const expressionS
*tok
,
2403 } mpy_list
[] = {{ MPY1E
, 1 }, { MPY6E
, 6 }, { MPY7E
, 7 }, { MPY8E
, 8 },
2406 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
2407 if (opcode
->subclass
== feature_list
[i
].feature
)
2408 selected_cpu
.features
|= feature_list
[i
].feature
;
2410 for (i
= 0; i
< ARRAY_SIZE (mpy_list
); i
++)
2411 if (opcode
->subclass
== mpy_list
[i
].feature
)
2412 mpy_option
= mpy_list
[i
].encoding
;
2414 for (i
= 0; i
< (unsigned) ntok
; i
++)
2416 switch (tok
[i
].X_md
)
2438 switch (tok
[i
].X_op
)
2441 if ((tok
[i
].X_add_number
>= 4 && tok
[i
].X_add_number
<= 9)
2442 || (tok
[i
].X_add_number
>= 16 && tok
[i
].X_add_number
<= 25))
2451 /* Given an opcode name, pre-tockenized set of argumenst and the
2452 opcode flags, take it all the way through emission. */
2455 assemble_tokens (const char *opname
,
2458 struct arc_flags
*pflags
,
2461 bool found_something
= false;
2462 const struct arc_opcode_hash_entry
*entry
;
2464 const char *errmsg
= NULL
;
2466 /* Search opcodes. */
2467 entry
= arc_find_opcode (opname
);
2469 /* Couldn't find opcode conventional way, try special cases. */
2471 entry
= find_special_case (opname
, &nflgs
, pflags
, tok
, &ntok
);
2475 const struct arc_opcode
*opcode
;
2477 pr_debug ("%s:%d: assemble_tokens: %s\n",
2478 frag_now
->fr_file
, frag_now
->fr_line
, opname
);
2479 found_something
= true;
2480 opcode
= find_opcode_match (entry
, tok
, &ntok
, pflags
,
2481 nflgs
, &cpumatch
, &errmsg
);
2484 struct arc_insn insn
;
2486 autodetect_attributes (opcode
, tok
, ntok
);
2487 assemble_insn (opcode
, tok
, ntok
, pflags
, nflgs
, &insn
);
2493 if (found_something
)
2497 as_bad (_("%s for instruction '%s'"), errmsg
, opname
);
2499 as_bad (_("inappropriate arguments for opcode '%s'"), opname
);
2501 as_bad (_("opcode '%s' not supported for target %s"), opname
,
2505 as_bad (_("unknown opcode '%s'"), opname
);
2508 /* The public interface to the instruction assembler. */
2511 md_assemble (char *str
)
2514 expressionS tok
[MAX_INSN_ARGS
];
2517 struct arc_flags flags
[MAX_INSN_FLGS
];
2519 /* Split off the opcode. */
2520 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_0123468");
2521 opname
= xmemdup0 (str
, opnamelen
);
2523 /* Signalize we are assembling the instructions. */
2524 assembling_insn
= true;
2526 /* Tokenize the flags. */
2527 if ((nflg
= tokenize_flags (str
+ opnamelen
, flags
, MAX_INSN_FLGS
)) == -1)
2529 as_bad (_("syntax error"));
2533 /* Scan up to the end of the mnemonic which must end in space or end
2536 for (; *str
!= '\0'; str
++)
2540 /* Tokenize the rest of the line. */
2541 if ((ntok
= tokenize_arguments (str
, tok
, MAX_INSN_ARGS
)) < 0)
2543 as_bad (_("syntax error"));
2547 /* Finish it off. */
2548 assemble_tokens (opname
, tok
, ntok
, flags
, nflg
);
2549 assembling_insn
= false;
2552 /* Callback to insert a register into the hash table. */
2555 declare_register (const char *name
, int number
)
2557 symbolS
*regS
= symbol_create (name
, reg_section
,
2558 &zero_address_frag
, number
);
2560 if (str_hash_insert (arc_reg_hash
, S_GET_NAME (regS
), regS
, 0) != NULL
)
2561 as_fatal (_("duplicate %s"), name
);
2564 /* Construct symbols for each of the general registers. */
2567 declare_register_set (void)
2570 for (i
= 0; i
< 64; ++i
)
2574 sprintf (name
, "r%d", i
);
2575 declare_register (name
, i
);
2576 if ((i
& 0x01) == 0)
2578 sprintf (name
, "r%dr%d", i
, i
+1);
2579 declare_register (name
, i
);
2584 /* Construct a symbol for an address type. */
2587 declare_addrtype (const char *name
, int number
)
2589 symbolS
*addrtypeS
= symbol_create (name
, undefined_section
,
2590 &zero_address_frag
, number
);
2592 if (str_hash_insert (arc_addrtype_hash
, S_GET_NAME (addrtypeS
), addrtypeS
, 0))
2593 as_fatal (_("duplicate %s"), name
);
2596 /* Port-specific assembler initialization. This function is called
2597 once, at assembler startup time. */
2602 const struct arc_opcode
*opcode
= arc_opcodes
;
2604 if (mach_selection_mode
== MACH_SELECTION_NONE
)
2605 arc_select_cpu (TARGET_WITH_CPU
, MACH_SELECTION_FROM_DEFAULT
);
2607 /* The endianness can be chosen "at the factory". */
2608 target_big_endian
= byte_order
== BIG_ENDIAN
;
2610 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
2611 as_warn (_("could not set architecture and machine"));
2613 /* Set elf header flags. */
2614 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
2616 /* Set up a hash table for the instructions. */
2617 arc_opcode_hash
= htab_create_alloc (16, hash_string_tuple
, eq_string_tuple
,
2618 arc_opcode_free
, xcalloc
, free
);
2620 /* Initialize the hash table with the insns. */
2623 const char *name
= opcode
->name
;
2625 arc_insert_opcode (opcode
);
2627 while (++opcode
&& opcode
->name
2628 && (opcode
->name
== name
2629 || !strcmp (opcode
->name
, name
)))
2631 }while (opcode
->name
);
2633 /* Register declaration. */
2634 arc_reg_hash
= str_htab_create ();
2636 declare_register_set ();
2637 declare_register ("gp", 26);
2638 declare_register ("fp", 27);
2639 declare_register ("sp", 28);
2640 declare_register ("ilink", 29);
2641 declare_register ("ilink1", 29);
2642 declare_register ("ilink2", 30);
2643 declare_register ("blink", 31);
2645 /* XY memory registers. */
2646 declare_register ("x0_u0", 32);
2647 declare_register ("x0_u1", 33);
2648 declare_register ("x1_u0", 34);
2649 declare_register ("x1_u1", 35);
2650 declare_register ("x2_u0", 36);
2651 declare_register ("x2_u1", 37);
2652 declare_register ("x3_u0", 38);
2653 declare_register ("x3_u1", 39);
2654 declare_register ("y0_u0", 40);
2655 declare_register ("y0_u1", 41);
2656 declare_register ("y1_u0", 42);
2657 declare_register ("y1_u1", 43);
2658 declare_register ("y2_u0", 44);
2659 declare_register ("y2_u1", 45);
2660 declare_register ("y3_u0", 46);
2661 declare_register ("y3_u1", 47);
2662 declare_register ("x0_nu", 48);
2663 declare_register ("x1_nu", 49);
2664 declare_register ("x2_nu", 50);
2665 declare_register ("x3_nu", 51);
2666 declare_register ("y0_nu", 52);
2667 declare_register ("y1_nu", 53);
2668 declare_register ("y2_nu", 54);
2669 declare_register ("y3_nu", 55);
2671 declare_register ("mlo", 57);
2672 declare_register ("mmid", 58);
2673 declare_register ("mhi", 59);
2675 declare_register ("acc1", 56);
2676 declare_register ("acc2", 57);
2678 declare_register ("lp_count", 60);
2679 declare_register ("pcl", 63);
2681 /* Initialize the last instructions. */
2682 memset (&arc_last_insns
[0], 0, sizeof (arc_last_insns
));
2684 /* Aux register declaration. */
2685 arc_aux_hash
= str_htab_create ();
2687 const struct arc_aux_reg
*auxr
= &arc_aux_regs
[0];
2689 for (i
= 0; i
< arc_num_aux_regs
; i
++, auxr
++)
2691 if (!(auxr
->cpu
& selected_cpu
.flags
))
2694 if ((auxr
->subclass
!= NONE
)
2695 && !check_cpu_feature (auxr
->subclass
))
2698 if (str_hash_insert (arc_aux_hash
, auxr
->name
, auxr
, 0) != 0)
2699 as_fatal (_("duplicate %s"), auxr
->name
);
2702 /* Address type declaration. */
2703 arc_addrtype_hash
= str_htab_create ();
2705 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD
);
2706 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID
);
2707 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD
);
2708 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD
);
2709 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD
);
2710 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM
);
2711 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA
);
2712 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD
);
2713 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD
);
2714 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD
);
2715 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID
);
2716 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD
);
2717 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM
);
2718 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD
);
2719 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA
);
2720 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD
);
2726 htab_delete (arc_opcode_hash
);
2727 htab_delete (arc_reg_hash
);
2728 htab_delete (arc_aux_hash
);
2729 htab_delete (arc_addrtype_hash
);
2732 /* Write a value out to the object file, using the appropriate
2736 md_number_to_chars (char *buf
,
2740 if (target_big_endian
)
2741 number_to_chars_bigendian (buf
, val
, n
);
2743 number_to_chars_littleendian (buf
, val
, n
);
2746 /* Round up a section size to the appropriate boundary. */
2749 md_section_align (segT segment
,
2752 int align
= bfd_section_alignment (segment
);
2754 return ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
2757 /* The location from which a PC relative jump should be calculated,
2758 given a PC relative reloc. */
2761 md_pcrel_from_section (fixS
*fixP
,
2764 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2766 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP
->fx_offset
);
2768 if (fixP
->fx_addsy
!= (symbolS
*) NULL
2769 && (!S_IS_DEFINED (fixP
->fx_addsy
)
2770 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
2772 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP
->fx_addsy
));
2774 /* The symbol is undefined (or is defined but not in this section).
2775 Let the linker figure it out. */
2779 if ((int) fixP
->fx_r_type
< 0)
2781 /* These are the "internal" relocations. Align them to
2782 32 bit boundary (PCL), for the moment. */
2787 switch (fixP
->fx_r_type
)
2789 case BFD_RELOC_ARC_PC32
:
2790 /* The hardware calculates relative to the start of the
2791 insn, but this relocation is relative to location of the
2792 LIMM, compensate. The base always needs to be
2793 subtracted by 4 as we do not support this type of PCrel
2794 relocation for short instructions. */
2797 case BFD_RELOC_ARC_PLT32
:
2798 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
2799 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
2800 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
2801 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
2803 case BFD_RELOC_ARC_S21H_PCREL
:
2804 case BFD_RELOC_ARC_S25H_PCREL
:
2805 case BFD_RELOC_ARC_S13_PCREL
:
2806 case BFD_RELOC_ARC_S21W_PCREL
:
2807 case BFD_RELOC_ARC_S25W_PCREL
:
2811 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2812 _("unhandled reloc %s in md_pcrel_from_section"),
2813 bfd_get_reloc_code_name (fixP
->fx_r_type
));
2818 pr_debug ("pcrel from %"BFD_VMA_FMT
"x + %lx = %"BFD_VMA_FMT
"x, "
2819 "symbol: %s (%"BFD_VMA_FMT
"x)\n",
2820 fixP
->fx_frag
->fr_address
, fixP
->fx_where
, base
,
2821 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "(null)",
2822 fixP
->fx_addsy
? S_GET_VALUE (fixP
->fx_addsy
) : 0);
2827 /* Given a BFD relocation find the corresponding operand. */
2829 static const struct arc_operand
*
2830 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc
)
2834 for (i
= 0; i
< arc_num_operands
; i
++)
2835 if (arc_operands
[i
].default_reloc
== reloc
)
2836 return &arc_operands
[i
];
2840 /* Insert an operand value into an instruction. */
2842 static unsigned long long
2843 insert_operand (unsigned long long insn
,
2844 const struct arc_operand
*operand
,
2849 offsetT min
= 0, max
= 0;
2851 if (operand
->bits
!= 32
2852 && !(operand
->flags
& ARC_OPERAND_NCHK
)
2853 && !(operand
->flags
& ARC_OPERAND_FAKE
))
2855 if (operand
->flags
& ARC_OPERAND_SIGNED
)
2857 max
= (1 << (operand
->bits
- 1)) - 1;
2858 min
= -(1 << (operand
->bits
- 1));
2862 max
= (1 << operand
->bits
) - 1;
2866 if (val
< min
|| val
> max
)
2867 as_bad_value_out_of_range (_("operand"),
2868 val
, min
, max
, file
, line
);
2871 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
2872 min
, val
, max
, insn
);
2874 if ((operand
->flags
& ARC_OPERAND_ALIGNED32
)
2876 as_bad_where (file
, line
,
2877 _("Unaligned operand. Needs to be 32bit aligned"));
2879 if ((operand
->flags
& ARC_OPERAND_ALIGNED16
)
2881 as_bad_where (file
, line
,
2882 _("Unaligned operand. Needs to be 16bit aligned"));
2884 if (operand
->insert
)
2886 const char *errmsg
= NULL
;
2888 insn
= (*operand
->insert
) (insn
, val
, &errmsg
);
2890 as_warn_where (file
, line
, "%s", errmsg
);
2894 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
2896 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
2898 if (operand
->flags
& ARC_OPERAND_ALIGNED16
)
2901 insn
|= ((val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2906 /* Apply a fixup to the object code. At this point all symbol values
2907 should be fully resolved, and we attempt to completely resolve the
2908 reloc. If we can not do that, we determine the correct reloc code
2909 and put it back in the fixup. To indicate that a fixup has been
2910 eliminated, set fixP->fx_done. */
2913 md_apply_fix (fixS
*fixP
,
2917 char * const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
2918 valueT value
= *valP
;
2920 symbolS
*fx_addsy
, *fx_subsy
;
2922 segT add_symbol_segment
= absolute_section
;
2923 segT sub_symbol_segment
= absolute_section
;
2924 const struct arc_operand
*operand
= NULL
;
2925 extended_bfd_reloc_code_real_type reloc
;
2927 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2928 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
2929 ((int) fixP
->fx_r_type
< 0) ? "Internal":
2930 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
2933 fx_addsy
= fixP
->fx_addsy
;
2934 fx_subsy
= fixP
->fx_subsy
;
2939 add_symbol_segment
= S_GET_SEGMENT (fx_addsy
);
2943 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF
2944 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_DTPOFF_S9
2945 && fixP
->fx_r_type
!= BFD_RELOC_ARC_TLS_GD_LD
)
2947 resolve_symbol_value (fx_subsy
);
2948 sub_symbol_segment
= S_GET_SEGMENT (fx_subsy
);
2950 if (sub_symbol_segment
== absolute_section
)
2952 /* The symbol is really a constant. */
2953 fx_offset
-= S_GET_VALUE (fx_subsy
);
2958 as_bad_subtract (fixP
);
2964 && !S_IS_WEAK (fx_addsy
))
2966 if (add_symbol_segment
== seg
2969 value
+= S_GET_VALUE (fx_addsy
);
2970 value
-= md_pcrel_from_section (fixP
, seg
);
2972 fixP
->fx_pcrel
= false;
2974 else if (add_symbol_segment
== absolute_section
)
2976 value
= fixP
->fx_offset
;
2977 fx_offset
+= S_GET_VALUE (fixP
->fx_addsy
);
2979 fixP
->fx_pcrel
= false;
2984 fixP
->fx_done
= true;
2989 && ((S_IS_DEFINED (fx_addsy
)
2990 && S_GET_SEGMENT (fx_addsy
) != seg
)
2991 || S_IS_WEAK (fx_addsy
)))
2992 value
+= md_pcrel_from_section (fixP
, seg
);
2994 switch (fixP
->fx_r_type
)
2996 case BFD_RELOC_ARC_32_ME
:
2997 /* This is a pc-relative value in a LIMM. Adjust it to the
2998 address of the instruction not to the address of the
2999 LIMM. Note: it is not any longer valid this affirmation as
3000 the linker consider ARC_PC32 a fixup to entire 64 bit
3002 fixP
->fx_offset
+= fixP
->fx_frag
->fr_address
;
3005 fixP
->fx_r_type
= BFD_RELOC_ARC_PC32
;
3007 case BFD_RELOC_ARC_PC32
:
3008 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
3011 if ((int) fixP
->fx_r_type
< 0)
3012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3013 _("PC relative relocation not allowed for (internal)"
3020 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
3021 fixP
->fx_file
, fixP
->fx_line
, fixP
->fx_r_type
,
3022 ((int) fixP
->fx_r_type
< 0) ? "Internal":
3023 bfd_get_reloc_code_name (fixP
->fx_r_type
), value
,
3027 /* Now check for TLS relocations. */
3028 reloc
= fixP
->fx_r_type
;
3031 case BFD_RELOC_ARC_TLS_DTPOFF
:
3032 case BFD_RELOC_ARC_TLS_LE_32
:
3036 case BFD_RELOC_ARC_TLS_GD_GOT
:
3037 case BFD_RELOC_ARC_TLS_IE_GOT
:
3038 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3041 case BFD_RELOC_ARC_TLS_GD_LD
:
3042 gas_assert (!fixP
->fx_offset
);
3045 = (S_GET_VALUE (fixP
->fx_subsy
)
3046 - fixP
->fx_frag
->fr_address
- fixP
->fx_where
);
3047 fixP
->fx_subsy
= NULL
;
3049 case BFD_RELOC_ARC_TLS_GD_CALL
:
3050 /* These two relocs are there just to allow ld to change the tls
3051 model for this symbol, by patching the code. The offset -
3052 and scale, if any - will be installed by the linker. */
3053 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3056 case BFD_RELOC_ARC_TLS_LE_S9
:
3057 case BFD_RELOC_ARC_TLS_DTPOFF_S9
:
3058 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3070 /* Adjust the value if we have a constant. */
3073 /* For hosts with longs bigger than 32-bits make sure that the top
3074 bits of a 32-bit negative value read in by the parser are set,
3075 so that the correct comparisons are made. */
3076 if (value
& 0x80000000)
3077 value
|= (-1UL << 31);
3079 reloc
= fixP
->fx_r_type
;
3087 case BFD_RELOC_ARC_32_PCREL
:
3088 md_number_to_chars (fixpos
, value
, fixP
->fx_size
);
3091 case BFD_RELOC_ARC_GOTPC32
:
3092 /* I cannot fix an GOTPC relocation because I need to relax it
3093 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3094 as_bad (_("Unsupported operation on reloc"));
3097 case BFD_RELOC_ARC_TLS_DTPOFF
:
3098 case BFD_RELOC_ARC_TLS_LE_32
:
3099 gas_assert (!fixP
->fx_addsy
);
3100 gas_assert (!fixP
->fx_subsy
);
3103 case BFD_RELOC_ARC_GOTOFF
:
3104 case BFD_RELOC_ARC_32_ME
:
3105 case BFD_RELOC_ARC_PC32
:
3106 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3109 case BFD_RELOC_ARC_PLT32
:
3110 md_number_to_chars_midend (fixpos
, value
, fixP
->fx_size
);
3113 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
3114 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3117 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
3118 reloc
= BFD_RELOC_ARC_S21H_PCREL
;
3121 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
3122 reloc
= BFD_RELOC_ARC_S25W_PCREL
;
3125 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
3126 reloc
= BFD_RELOC_ARC_S21W_PCREL
;
3129 case BFD_RELOC_ARC_S25W_PCREL
:
3130 case BFD_RELOC_ARC_S21W_PCREL
:
3131 case BFD_RELOC_ARC_S21H_PCREL
:
3132 case BFD_RELOC_ARC_S25H_PCREL
:
3133 case BFD_RELOC_ARC_S13_PCREL
:
3135 operand
= find_operand_for_reloc (reloc
);
3136 gas_assert (operand
);
3141 if ((int) fixP
->fx_r_type
>= 0)
3142 as_fatal (_("unhandled relocation type %s"),
3143 bfd_get_reloc_code_name (fixP
->fx_r_type
));
3145 /* The rest of these fixups needs to be completely resolved as
3147 if (fixP
->fx_addsy
!= 0
3148 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
)
3149 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3150 _("non-absolute expression in constant field"));
3152 gas_assert (-(int) fixP
->fx_r_type
< (int) arc_num_operands
);
3153 operand
= &arc_operands
[-(int) fixP
->fx_r_type
];
3158 if (target_big_endian
)
3160 switch (fixP
->fx_size
)
3163 insn
= bfd_getb32 (fixpos
);
3166 insn
= bfd_getb16 (fixpos
);
3169 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3170 _("unknown fixup size"));
3176 switch (fixP
->fx_size
)
3179 insn
= bfd_getl16 (fixpos
) << 16 | bfd_getl16 (fixpos
+ 2);
3182 insn
= bfd_getl16 (fixpos
);
3185 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3186 _("unknown fixup size"));
3190 insn
= insert_operand (insn
, operand
, (offsetT
) value
,
3191 fixP
->fx_file
, fixP
->fx_line
);
3193 md_number_to_chars_midend (fixpos
, insn
, fixP
->fx_size
);
3196 /* Prepare machine-dependent frags for relaxation.
3198 Called just before relaxation starts. Any symbol that is now undefined
3199 will not become defined.
3201 Return the correct fr_subtype in the frag.
3203 Return the initial "guess for fr_var" to caller. The guess for fr_var
3204 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3205 or fr_var contributes to our returned value.
3207 Although it may not be explicit in the frag, pretend
3208 fr_var starts with a value. */
3211 md_estimate_size_before_relax (fragS
*fragP
,
3216 /* If the symbol is not located within the same section AND it's not
3217 an absolute section, use the maximum. OR if the symbol is a
3218 constant AND the insn is by nature not pc-rel, use the maximum.
3219 OR if the symbol is being equated against another symbol, use the
3220 maximum. OR if the symbol is weak use the maximum. */
3221 if ((S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3222 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3223 || (symbol_constant_p (fragP
->fr_symbol
)
3224 && !fragP
->tc_frag_data
.pcrel
)
3225 || symbol_equated_p (fragP
->fr_symbol
)
3226 || S_IS_WEAK (fragP
->fr_symbol
))
3228 while (md_relax_table
[fragP
->fr_subtype
].rlx_more
!= ARC_RLX_NONE
)
3229 ++fragP
->fr_subtype
;
3232 growth
= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3233 fragP
->fr_var
= growth
;
3235 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3236 fragP
->fr_file
, fragP
->fr_line
, growth
);
3241 /* Translate internal representation of relocation info to BFD target
3245 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
,
3249 bfd_reloc_code_real_type code
;
3251 reloc
= XNEW (arelent
);
3252 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3253 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
3254 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
3256 /* Make sure none of our internal relocations make it this far.
3257 They'd better have been fully resolved by this point. */
3258 gas_assert ((int) fixP
->fx_r_type
> 0);
3260 code
= fixP
->fx_r_type
;
3262 /* if we have something like add gp, pcl,
3263 _GLOBAL_OFFSET_TABLE_@gotpc. */
3264 if (code
== BFD_RELOC_ARC_GOTPC32
3266 && fixP
->fx_addsy
== GOT_symbol
)
3267 code
= BFD_RELOC_ARC_GOTPC
;
3269 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3270 if (reloc
->howto
== NULL
)
3272 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3273 _("cannot represent `%s' relocation in object file"),
3274 bfd_get_reloc_code_name (code
));
3278 if (!fixP
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
3279 as_fatal (_("internal error? cannot generate `%s' relocation"),
3280 bfd_get_reloc_code_name (code
));
3282 gas_assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
3284 reloc
->addend
= fixP
->fx_offset
;
3289 /* Perform post-processing of machine-dependent frags after relaxation.
3290 Called after relaxation is finished.
3291 In: Address of frag.
3292 fr_type == rs_machine_dependent.
3293 fr_subtype is what the address relaxed to.
3295 Out: Any fixS:s and constants are set up. */
3298 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
3299 segT segment ATTRIBUTE_UNUSED
,
3302 const relax_typeS
*table_entry
;
3304 const struct arc_opcode
*opcode
;
3305 struct arc_insn insn
;
3307 struct arc_relax_type
*relax_arg
= &fragP
->tc_frag_data
;
3309 fix
= fragP
->fr_fix
;
3310 dest
= fragP
->fr_literal
+ fix
;
3311 table_entry
= TC_GENERIC_RELAX_TABLE
+ fragP
->fr_subtype
;
3313 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3314 "var: %"BFD_VMA_FMT
"d\n",
3315 fragP
->fr_file
, fragP
->fr_line
,
3316 fragP
->fr_subtype
, fix
, fragP
->fr_var
);
3318 if (fragP
->fr_subtype
<= 0
3319 && fragP
->fr_subtype
>= arc_num_relax_opcodes
)
3320 as_fatal (_("no relaxation found for this instruction."));
3322 opcode
= &arc_relax_opcodes
[fragP
->fr_subtype
];
3324 assemble_insn (opcode
, relax_arg
->tok
, relax_arg
->ntok
, relax_arg
->pflags
,
3325 relax_arg
->nflg
, &insn
);
3327 apply_fixups (&insn
, fragP
, fix
);
3329 size
= insn
.len
+ (insn
.has_limm
? 4 : 0);
3330 gas_assert (table_entry
->rlx_length
== size
);
3331 emit_insn0 (&insn
, dest
, true);
3333 fragP
->fr_fix
+= table_entry
->rlx_length
;
3337 /* We have no need to default values of symbols. We could catch
3338 register names here, but that is handled by inserting them all in
3339 the symbol table to begin with. */
3342 md_undefined_symbol (char *name
)
3344 /* The arc abi demands that a GOT[0] should be referencible as
3345 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3346 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3348 && (*(name
+1) == 'G')
3349 && (strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)))
3353 if (symbol_find (name
))
3354 as_bad ("GOT already in symbol table");
3356 GOT_symbol
= symbol_new (GLOBAL_OFFSET_TABLE_NAME
, undefined_section
,
3357 &zero_address_frag
, 0);
3364 /* Turn a string in input_line_pointer into a floating point constant
3365 of type type, and store the appropriate bytes in *litP. The number
3366 of LITTLENUMS emitted is stored in *sizeP. An error message is
3367 returned, or NULL on OK. */
3370 md_atof (int type
, char *litP
, int *sizeP
)
3372 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3375 /* Called for any expression that can not be recognized. When the
3376 function is called, `input_line_pointer' will point to the start of
3377 the expression. We use it when we have complex operations like
3378 @label1 - @label2. */
3381 md_operand (expressionS
*expressionP
)
3383 char *p
= input_line_pointer
;
3386 input_line_pointer
++;
3387 expressionP
->X_op
= O_symbol
;
3388 expressionP
->X_md
= O_absent
;
3389 expression (expressionP
);
3393 /* This function is called from the function 'expression', it attempts
3394 to parse special names (in our case register names). It fills in
3395 the expression with the identified register. It returns TRUE if
3396 it is a register and FALSE otherwise. */
3399 arc_parse_name (const char *name
,
3400 struct expressionS
*e
)
3404 if (!assembling_insn
)
3407 if (e
->X_op
== O_symbol
3408 && e
->X_md
== O_absent
)
3411 sym
= str_hash_find (arc_reg_hash
, name
);
3414 e
->X_op
= O_register
;
3415 e
->X_add_number
= S_GET_VALUE (sym
);
3419 sym
= str_hash_find (arc_addrtype_hash
, name
);
3422 e
->X_op
= O_addrtype
;
3423 e
->X_add_number
= S_GET_VALUE (sym
);
3431 Invocation line includes a switch not recognized by the base assembler.
3432 See if it's a processor-specific option.
3434 New options (supported) are:
3436 -mcpu=<cpu name> Assemble for selected processor
3437 -EB/-mbig-endian Big-endian
3438 -EL/-mlittle-endian Little-endian
3439 -mrelax Enable relaxation
3441 The following CPU names are recognized:
3442 arc600, arc700, arcem, archs, nps400. */
3445 md_parse_option (int c
, const char *arg ATTRIBUTE_UNUSED
)
3451 return md_parse_option (OPTION_MCPU
, "arc600");
3454 return md_parse_option (OPTION_MCPU
, "arc700");
3457 return md_parse_option (OPTION_MCPU
, "arcem");
3460 return md_parse_option (OPTION_MCPU
, "archs");
3464 arc_select_cpu (arg
, MACH_SELECTION_FROM_COMMAND_LINE
);
3469 arc_target_format
= "elf32-bigarc";
3470 byte_order
= BIG_ENDIAN
;
3474 arc_target_format
= "elf32-littlearc";
3475 byte_order
= LITTLE_ENDIAN
;
3479 selected_cpu
.features
|= CD
;
3481 arc_check_feature ();
3485 relaxation_state
= 1;
3489 selected_cpu
.features
|= NPS400
;
3490 cl_features
|= NPS400
;
3491 arc_check_feature ();
3495 selected_cpu
.features
|= SPX
;
3497 arc_check_feature ();
3501 selected_cpu
.features
|= DPX
;
3503 arc_check_feature ();
3507 selected_cpu
.features
|= DPA
;
3509 arc_check_feature ();
3512 /* Dummy options are accepted but have no effect. */
3513 case OPTION_USER_MODE
:
3514 case OPTION_LD_EXT_MASK
:
3517 case OPTION_BARREL_SHIFT
:
3518 case OPTION_MIN_MAX
:
3523 case OPTION_XMAC_D16
:
3524 case OPTION_XMAC_24
:
3525 case OPTION_DSP_PACKA
:
3528 case OPTION_TELEPHONY
:
3529 case OPTION_XYMEMORY
:
3542 /* Display the list of cpu names for use in the help text. */
3545 arc_show_cpu_list (FILE *stream
)
3548 static const char *space_buf
= " ";
3550 fprintf (stream
, "%s", space_buf
);
3551 offset
= strlen (space_buf
);
3552 for (i
= 0; cpu_types
[i
].name
!= NULL
; ++i
)
3554 bool last
= (cpu_types
[i
+ 1].name
== NULL
);
3556 /* If displaying the new cpu name string, and the ', ' (for all
3557 but the last one) will take us past a target width of 80
3558 characters, then it's time for a new line. */
3559 if (offset
+ strlen (cpu_types
[i
].name
) + (last
? 0 : 2) > 80)
3561 fprintf (stream
, "\n%s", space_buf
);
3562 offset
= strlen (space_buf
);
3565 fprintf (stream
, "%s%s", cpu_types
[i
].name
, (last
? "\n" : ", "));
3566 offset
+= strlen (cpu_types
[i
].name
) + (last
? 0 : 2);
3571 md_show_usage (FILE *stream
)
3573 fprintf (stream
, _("ARC-specific assembler options:\n"));
3575 fprintf (stream
, " -mcpu=<cpu name>\t (default: %s), assemble for"
3576 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU
);
3577 arc_show_cpu_list (stream
);
3578 fprintf (stream
, "\n");
3579 fprintf (stream
, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3580 fprintf (stream
, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3581 fprintf (stream
, " -mEM\t\t\t same as -mcpu=arcem\n");
3582 fprintf (stream
, " -mHS\t\t\t same as -mcpu=archs\n");
3584 fprintf (stream
, " -mnps400\t\t enable NPS-400 extended instructions\n");
3585 fprintf (stream
, " -mspfp\t\t enable single-precision floating point"
3587 fprintf (stream
, " -mdpfp\t\t enable double-precision floating point"
3589 fprintf (stream
, " -mfpuda\t\t enable double-precision assist floating "
3590 "point\n\t\t\t instructions for ARC EM\n");
3593 " -mcode-density\t enable code density option for ARC EM\n");
3595 fprintf (stream
, _("\
3596 -EB assemble code for a big-endian cpu\n"));
3597 fprintf (stream
, _("\
3598 -EL assemble code for a little-endian cpu\n"));
3599 fprintf (stream
, _("\
3600 -mrelax enable relaxation\n"));
3602 fprintf (stream
, _("The following ARC-specific assembler options are "
3603 "deprecated and are accepted\nfor compatibility only:\n"));
3605 fprintf (stream
, _(" -mEA\n"
3606 " -mbarrel-shifter\n"
3607 " -mbarrel_shifter\n"
3612 " -mld-extension-reg-mask\n"
3628 " -muser-mode-only\n"
3632 /* Find the proper relocation for the given opcode. */
3634 static extended_bfd_reloc_code_real_type
3635 find_reloc (const char *name
,
3636 const char *opcodename
,
3637 const struct arc_flags
*pflags
,
3639 extended_bfd_reloc_code_real_type reloc
)
3643 bool found_flag
, tmp
;
3644 extended_bfd_reloc_code_real_type ret
= BFD_RELOC_UNUSED
;
3646 for (i
= 0; i
< arc_num_equiv_tab
; i
++)
3648 const struct arc_reloc_equiv_tab
*r
= &arc_reloc_equiv
[i
];
3650 /* Find the entry. */
3651 if (strcmp (name
, r
->name
))
3653 if (r
->mnemonic
&& (strcmp (r
->mnemonic
, opcodename
)))
3660 unsigned * psflg
= (unsigned *)r
->flags
;
3664 for (j
= 0; j
< nflg
; j
++)
3665 if (!strcmp (pflags
[j
].name
,
3666 arc_flag_operands
[*psflg
].name
))
3687 if (reloc
!= r
->oldreloc
)
3694 if (ret
== BFD_RELOC_UNUSED
)
3695 as_bad (_("Unable to find %s relocation for instruction %s"),
3700 /* All the symbol types that are allowed to be used for
3704 may_relax_expr (expressionS tok
)
3706 /* Check if we have unrelaxable relocs. */
3731 /* Checks if flags are in line with relaxable insn. */
3734 relaxable_flag (const struct arc_relaxable_ins
*ins
,
3735 const struct arc_flags
*pflags
,
3738 unsigned flag_class
,
3743 const struct arc_flag_operand
*flag_opand
;
3744 int i
, counttrue
= 0;
3746 /* Iterate through flags classes. */
3747 while ((flag_class
= ins
->flag_classes
[flag_class_idx
]) != 0)
3749 /* Iterate through flags in flag class. */
3750 while ((flag
= arc_flag_classes
[flag_class
].flags
[flag_idx
])
3753 flag_opand
= &arc_flag_operands
[flag
];
3754 /* Iterate through flags in ins to compare. */
3755 for (i
= 0; i
< nflgs
; ++i
)
3757 if (strcmp (flag_opand
->name
, pflags
[i
].name
) == 0)
3768 /* If counttrue == nflgs, then all flags have been found. */
3769 return counttrue
== nflgs
;
3772 /* Checks if operands are in line with relaxable insn. */
3775 relaxable_operand (const struct arc_relaxable_ins
*ins
,
3776 const expressionS
*tok
,
3779 const enum rlx_operand_type
*operand
= &ins
->operands
[0];
3782 while (*operand
!= EMPTY
)
3784 const expressionS
*epr
= &tok
[i
];
3786 if (i
!= 0 && i
>= ntok
)
3792 if (!(epr
->X_op
== O_multiply
3793 || epr
->X_op
== O_divide
3794 || epr
->X_op
== O_modulus
3795 || epr
->X_op
== O_add
3796 || epr
->X_op
== O_subtract
3797 || epr
->X_op
== O_symbol
))
3803 || (epr
->X_add_number
!= tok
[i
- 1].X_add_number
))
3807 if (epr
->X_op
!= O_register
)
3812 if (epr
->X_op
!= O_register
)
3815 switch (epr
->X_add_number
)
3817 case 0: case 1: case 2: case 3:
3818 case 12: case 13: case 14: case 15:
3825 case REGISTER_NO_GP
:
3826 if ((epr
->X_op
!= O_register
)
3827 || (epr
->X_add_number
== 26)) /* 26 is the gp register. */
3832 if (epr
->X_op
!= O_bracket
)
3837 /* Don't understand, bail out. */
3843 operand
= &ins
->operands
[i
];
3849 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3852 relax_insn_p (const struct arc_opcode
*opcode
,
3853 const expressionS
*tok
,
3855 const struct arc_flags
*pflags
,
3861 /* Check the relaxation table. */
3862 for (i
= 0; i
< arc_num_relaxable_ins
&& relaxation_state
; ++i
)
3864 const struct arc_relaxable_ins
*arc_rlx_ins
= &arc_relaxable_insns
[i
];
3866 if ((strcmp (opcode
->name
, arc_rlx_ins
->mnemonic_r
) == 0)
3867 && may_relax_expr (tok
[arc_rlx_ins
->opcheckidx
])
3868 && relaxable_operand (arc_rlx_ins
, tok
, ntok
)
3869 && relaxable_flag (arc_rlx_ins
, pflags
, nflg
))
3872 frag_now
->fr_subtype
= arc_relaxable_insns
[i
].subtype
;
3873 memcpy (&frag_now
->tc_frag_data
.tok
, tok
,
3874 sizeof (expressionS
) * ntok
);
3875 memcpy (&frag_now
->tc_frag_data
.pflags
, pflags
,
3876 sizeof (struct arc_flags
) * nflg
);
3877 frag_now
->tc_frag_data
.nflg
= nflg
;
3878 frag_now
->tc_frag_data
.ntok
= ntok
;
3886 /* Turn an opcode description and a set of arguments into
3887 an instruction and a fixup. */
3890 assemble_insn (const struct arc_opcode
*opcode
,
3891 const expressionS
*tok
,
3893 const struct arc_flags
*pflags
,
3895 struct arc_insn
*insn
)
3897 const expressionS
*reloc_exp
= NULL
;
3898 unsigned long long image
;
3899 const unsigned char *argidx
;
3902 unsigned char pcrel
= 0;
3904 bool has_delay_slot
= false;
3905 extended_bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
3907 memset (insn
, 0, sizeof (*insn
));
3908 image
= opcode
->opcode
;
3910 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
3911 frag_now
->fr_file
, frag_now
->fr_line
, opcode
->name
,
3914 /* Handle operands. */
3915 for (argidx
= opcode
->operands
; *argidx
; ++argidx
)
3917 const struct arc_operand
*operand
= &arc_operands
[*argidx
];
3918 const expressionS
*t
= (const expressionS
*) 0;
3920 if (ARC_OPERAND_IS_FAKE (operand
))
3923 if (operand
->flags
& ARC_OPERAND_DUPLICATE
)
3925 /* Duplicate operand, already inserted. */
3937 /* Regardless if we have a reloc or not mark the instruction
3938 limm if it is the case. */
3939 if (operand
->flags
& ARC_OPERAND_LIMM
)
3940 insn
->has_limm
= true;
3945 image
= insert_operand (image
, operand
, regno (t
->X_add_number
),
3950 image
= insert_operand (image
, operand
, t
->X_add_number
, NULL
, 0);
3952 if (operand
->flags
& ARC_OPERAND_LIMM
)
3953 insn
->limm
= t
->X_add_number
;
3959 /* Ignore brackets, colons, and address types. */
3963 gas_assert (operand
->flags
& ARC_OPERAND_IGNORE
);
3967 /* Maybe register range. */
3968 if ((t
->X_add_number
== 0)
3969 && contains_register (t
->X_add_symbol
)
3970 && contains_register (t
->X_op_symbol
))
3974 regs
= get_register (t
->X_add_symbol
);
3976 regs
|= get_register (t
->X_op_symbol
);
3977 image
= insert_operand (image
, operand
, regs
, NULL
, 0);
3983 /* This operand needs a relocation. */
3984 needGOTSymbol
= false;
3989 if (opcode
->insn_class
== JUMP
)
3990 as_bad (_("Unable to use @plt relocation for insn %s"),
3992 needGOTSymbol
= true;
3993 reloc
= find_reloc ("plt", opcode
->name
,
3995 operand
->default_reloc
);
4000 needGOTSymbol
= true;
4001 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
4004 if (operand
->flags
& ARC_OPERAND_LIMM
)
4006 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
4007 if (arc_opcode_len (opcode
) == 2
4008 || opcode
->insn_class
== JUMP
)
4009 as_bad (_("Unable to use @pcl relocation for insn %s"),
4014 /* This is a relaxed operand which initially was
4015 limm, choose whatever we have defined in the
4017 reloc
= operand
->default_reloc
;
4021 reloc
= find_reloc ("sda", opcode
->name
,
4023 operand
->default_reloc
);
4027 needGOTSymbol
= true;
4032 reloc
= ARC_RELOC_TABLE (t
->X_md
)->reloc
;
4035 case O_tpoff9
: /*FIXME! Check for the conditionality of
4037 case O_dtpoff9
: /*FIXME! Check for the conditionality of
4039 as_bad (_("TLS_*_S9 relocs are not supported yet"));
4043 /* Just consider the default relocation. */
4044 reloc
= operand
->default_reloc
;
4048 if (needGOTSymbol
&& (GOT_symbol
== NULL
))
4049 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4056 /* sanity checks. */
4057 reloc_howto_type
*reloc_howto
4058 = bfd_reloc_type_lookup (stdoutput
,
4059 (bfd_reloc_code_real_type
) reloc
);
4060 unsigned reloc_bitsize
= reloc_howto
->bitsize
;
4061 if (reloc_howto
->rightshift
)
4062 reloc_bitsize
-= reloc_howto
->rightshift
;
4063 if (reloc_bitsize
!= operand
->bits
)
4065 as_bad (_("invalid relocation %s for field"),
4066 bfd_get_reloc_code_name (reloc
));
4071 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4072 as_fatal (_("too many fixups"));
4074 struct arc_fixup
*fixup
;
4075 fixup
= &insn
->fixups
[insn
->nfixups
++];
4077 fixup
->reloc
= reloc
;
4078 if ((int) reloc
< 0)
4079 pcrel
= (operand
->flags
& ARC_OPERAND_PCREL
) ? 1 : 0;
4082 reloc_howto_type
*reloc_howto
=
4083 bfd_reloc_type_lookup (stdoutput
,
4084 (bfd_reloc_code_real_type
) fixup
->reloc
);
4085 pcrel
= reloc_howto
->pc_relative
;
4087 fixup
->pcrel
= pcrel
;
4088 fixup
->islong
= (operand
->flags
& ARC_OPERAND_LIMM
) != 0;
4094 for (i
= 0; i
< nflg
; i
++)
4096 const struct arc_flag_operand
*flg_operand
= pflags
[i
].flgp
;
4098 /* Check if the instruction has a delay slot. */
4099 if (!strcmp (flg_operand
->name
, "d"))
4100 has_delay_slot
= true;
4102 /* There is an exceptional case when we cannot insert a flag just as
4103 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4104 relation with the relative address. Unfortunately, some of the
4105 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4106 handled in the normal way.
4108 Flag operands don't have an architecture field, so we can't
4109 directly validate that FLAG_OPERAND is valid for the current
4110 architecture, what we do instead is just validate that we're
4111 assembling for an ARCv2 architecture. */
4112 if ((selected_cpu
.flags
& ARC_OPCODE_ARCV2
)
4113 && (!strcmp (flg_operand
->name
, "t")
4114 || !strcmp (flg_operand
->name
, "nt")))
4116 unsigned bitYoperand
= 0;
4117 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4118 if (!strcmp (flg_operand
->name
, "t"))
4119 if (!strcmp (opcode
->name
, "bbit0")
4120 || !strcmp (opcode
->name
, "bbit1"))
4121 bitYoperand
= arc_NToperand
;
4123 bitYoperand
= arc_Toperand
;
4125 if (!strcmp (opcode
->name
, "bbit0")
4126 || !strcmp (opcode
->name
, "bbit1"))
4127 bitYoperand
= arc_Toperand
;
4129 bitYoperand
= arc_NToperand
;
4131 gas_assert (reloc_exp
!= NULL
);
4132 if (reloc_exp
->X_op
== O_constant
)
4134 /* Check if we have a constant and solved it
4136 offsetT val
= reloc_exp
->X_add_number
;
4137 image
|= insert_operand (image
, &arc_operands
[bitYoperand
],
4142 struct arc_fixup
*fixup
;
4144 if (insn
->nfixups
>= MAX_INSN_FIXUPS
)
4145 as_fatal (_("too many fixups"));
4147 fixup
= &insn
->fixups
[insn
->nfixups
++];
4148 fixup
->exp
= *reloc_exp
;
4149 fixup
->reloc
= -bitYoperand
;
4150 fixup
->pcrel
= pcrel
;
4151 fixup
->islong
= false;
4155 image
|= (flg_operand
->code
& ((1 << flg_operand
->bits
) - 1))
4156 << flg_operand
->shift
;
4159 insn
->relax
= relax_insn_p (opcode
, tok
, ntok
, pflags
, nflg
);
4161 /* Instruction length. */
4162 insn
->len
= arc_opcode_len (opcode
);
4166 /* Update last insn status. */
4167 arc_last_insns
[1] = arc_last_insns
[0];
4168 arc_last_insns
[0].opcode
= opcode
;
4169 arc_last_insns
[0].has_limm
= insn
->has_limm
;
4170 arc_last_insns
[0].has_delay_slot
= has_delay_slot
;
4172 /* Check if the current instruction is legally used. */
4173 if (arc_last_insns
[1].has_delay_slot
4174 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4175 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4176 arc_last_insns
[1].opcode
->name
,
4177 arc_last_insns
[0].opcode
->name
);
4178 if (arc_last_insns
[1].has_delay_slot
4179 && arc_last_insns
[0].has_limm
)
4180 as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
4181 arc_last_insns
[1].opcode
->name
,
4182 arc_last_insns
[0].opcode
->name
);
4186 arc_handle_align (fragS
* fragP
)
4188 if ((fragP
)->fr_type
== rs_align_code
)
4190 char *dest
= (fragP
)->fr_literal
+ (fragP
)->fr_fix
;
4191 valueT count
= ((fragP
)->fr_next
->fr_address
4192 - (fragP
)->fr_address
- (fragP
)->fr_fix
);
4194 (fragP
)->fr_var
= 2;
4196 if (count
& 1)/* Padding in the gap till the next 2-byte
4197 boundary with 0s. */
4202 /* Writing nop_s. */
4203 md_number_to_chars (dest
, NOP_OPCODE_S
, 2);
4207 /* Here we decide which fixups can be adjusted to make them relative
4208 to the beginning of the section instead of the symbol. Basically
4209 we need to make sure that the dynamic relocations are done
4210 correctly, so in some cases we force the original symbol to be
4214 tc_arc_fix_adjustable (fixS
*fixP
)
4217 /* Prevent all adjustments to global symbols. */
4218 if (S_IS_EXTERNAL (fixP
->fx_addsy
))
4220 if (S_IS_WEAK (fixP
->fx_addsy
))
4223 /* Adjust_reloc_syms doesn't know about the GOT. */
4224 switch (fixP
->fx_r_type
)
4226 case BFD_RELOC_ARC_GOTPC32
:
4227 case BFD_RELOC_ARC_PLT32
:
4228 case BFD_RELOC_ARC_S25H_PCREL_PLT
:
4229 case BFD_RELOC_ARC_S21H_PCREL_PLT
:
4230 case BFD_RELOC_ARC_S25W_PCREL_PLT
:
4231 case BFD_RELOC_ARC_S21W_PCREL_PLT
:
4241 /* Compute the reloc type of an expression EXP. */
4244 arc_check_reloc (expressionS
*exp
,
4245 bfd_reloc_code_real_type
*r_type_p
)
4247 if (*r_type_p
== BFD_RELOC_32
4248 && exp
->X_op
== O_subtract
4249 && exp
->X_op_symbol
!= NULL
4250 && S_GET_SEGMENT (exp
->X_op_symbol
) == now_seg
)
4251 *r_type_p
= BFD_RELOC_ARC_32_PCREL
;
4255 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4258 arc_cons_fix_new (fragS
*frag
,
4262 bfd_reloc_code_real_type r_type
)
4264 r_type
= BFD_RELOC_UNUSED
;
4269 r_type
= BFD_RELOC_8
;
4273 r_type
= BFD_RELOC_16
;
4277 r_type
= BFD_RELOC_24
;
4281 r_type
= BFD_RELOC_32
;
4282 arc_check_reloc (exp
, &r_type
);
4286 r_type
= BFD_RELOC_64
;
4290 as_bad (_("unsupported BFD relocation size %u"), size
);
4291 r_type
= BFD_RELOC_UNUSED
;
4294 fix_new_exp (frag
, off
, size
, exp
, 0, r_type
);
4297 /* The actual routine that checks the ZOL conditions. */
4300 check_zol (symbolS
*s
)
4302 switch (selected_cpu
.mach
)
4304 case bfd_mach_arc_arcv2
:
4305 if (selected_cpu
.flags
& ARC_OPCODE_ARCv2EM
)
4308 if (is_br_jmp_insn_p (arc_last_insns
[0].opcode
)
4309 || arc_last_insns
[1].has_delay_slot
)
4310 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4314 case bfd_mach_arc_arc600
:
4316 if (is_kernel_insn_p (arc_last_insns
[0].opcode
))
4317 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4320 if (arc_last_insns
[0].has_limm
4321 && is_br_jmp_insn_p (arc_last_insns
[0].opcode
))
4322 as_bad (_("A jump instruction with long immediate detected at the \
4323 end of the ZOL label @%s"), S_GET_NAME (s
));
4326 case bfd_mach_arc_arc700
:
4327 if (arc_last_insns
[0].has_delay_slot
)
4328 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4337 /* If ZOL end check the last two instruction for illegals. */
4339 arc_frob_label (symbolS
* sym
)
4341 if (ARC_GET_FLAG (sym
) & ARC_FLAG_ZOL
)
4344 dwarf2_emit_label (sym
);
4347 /* Used because generic relaxation assumes a pc-rel value whilst we
4348 also relax instructions that use an absolute value resolved out of
4349 relative values (if that makes any sense). An example: 'add r1,
4350 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4351 but if they're in the same section we can subtract the section
4352 offset relocation which ends up in a resolved value. So if @.L2 is
4353 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4354 .text + 0x40 = 0x10. */
4356 arc_pcrel_adjust (fragS
*fragP
)
4358 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4359 fragP
->fr_address
, fragP
->fr_fix
,
4360 fragP
->tc_frag_data
.pcrel
? "Y" : "N");
4362 if (!fragP
->tc_frag_data
.pcrel
)
4363 return fragP
->fr_address
+ fragP
->fr_fix
;
4365 /* Take into account the PCL rounding. */
4366 return (fragP
->fr_address
+ fragP
->fr_fix
) & 0x03;
4369 /* Initialize the DWARF-2 unwind information for this procedure. */
4372 tc_arc_frame_initial_instructions (void)
4374 /* Stack pointer is register 28. */
4375 cfi_add_CFA_def_cfa (28, 0);
4379 tc_arc_regname_to_dw2regnum (char *regname
)
4383 sym
= str_hash_find (arc_reg_hash
, regname
);
4385 return S_GET_VALUE (sym
);
4390 /* Adjust the symbol table. Delete found AUX register symbols. */
4393 arc_adjust_symtab (void)
4397 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4399 /* I've created a symbol during parsing process. Now, remove
4400 the symbol as it is found to be an AUX register. */
4401 if (ARC_GET_FLAG (sym
) & ARC_FLAG_AUX
)
4402 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4405 /* Now do generic ELF adjustments. */
4406 elf_adjust_symtab ();
4410 tokenize_extinsn (extInstruction_t
*einsn
)
4414 unsigned char major_opcode
;
4415 unsigned char sub_opcode
;
4416 unsigned char syntax_class
= 0;
4417 unsigned char syntax_class_modifiers
= 0;
4418 unsigned char suffix_class
= 0;
4423 /* 1st: get instruction name. */
4424 p
= input_line_pointer
;
4425 c
= get_symbol_name (&p
);
4427 insn_name
= xstrdup (p
);
4428 restore_line_pointer (c
);
4430 /* Convert to lower case. */
4431 for (p
= insn_name
; *p
; ++p
)
4434 /* 2nd: get major opcode. */
4435 if (*input_line_pointer
!= ',')
4437 as_bad (_("expected comma after instruction name"));
4438 ignore_rest_of_line ();
4441 input_line_pointer
++;
4442 major_opcode
= get_absolute_expression ();
4444 /* 3rd: get sub-opcode. */
4447 if (*input_line_pointer
!= ',')
4449 as_bad (_("expected comma after major opcode"));
4450 ignore_rest_of_line ();
4453 input_line_pointer
++;
4454 sub_opcode
= get_absolute_expression ();
4456 /* 4th: get suffix class. */
4459 if (*input_line_pointer
!= ',')
4461 as_bad ("expected comma after sub opcode");
4462 ignore_rest_of_line ();
4465 input_line_pointer
++;
4471 for (i
= 0; i
< ARRAY_SIZE (suffixclass
); i
++)
4473 if (!strncmp (suffixclass
[i
].name
, input_line_pointer
,
4474 suffixclass
[i
].len
))
4476 suffix_class
|= suffixclass
[i
].attr_class
;
4477 input_line_pointer
+= suffixclass
[i
].len
;
4482 if (i
== ARRAY_SIZE (suffixclass
))
4484 as_bad ("invalid suffix class");
4485 ignore_rest_of_line ();
4491 if (*input_line_pointer
== '|')
4492 input_line_pointer
++;
4497 /* 5th: get syntax class and syntax class modifiers. */
4498 if (*input_line_pointer
!= ',')
4500 as_bad ("expected comma after suffix class");
4501 ignore_rest_of_line ();
4504 input_line_pointer
++;
4510 for (i
= 0; i
< ARRAY_SIZE (syntaxclassmod
); i
++)
4512 if (!strncmp (syntaxclassmod
[i
].name
,
4514 syntaxclassmod
[i
].len
))
4516 syntax_class_modifiers
|= syntaxclassmod
[i
].attr_class
;
4517 input_line_pointer
+= syntaxclassmod
[i
].len
;
4522 if (i
== ARRAY_SIZE (syntaxclassmod
))
4524 for (i
= 0; i
< ARRAY_SIZE (syntaxclass
); i
++)
4526 if (!strncmp (syntaxclass
[i
].name
,
4528 syntaxclass
[i
].len
))
4530 syntax_class
|= syntaxclass
[i
].attr_class
;
4531 input_line_pointer
+= syntaxclass
[i
].len
;
4536 if (i
== ARRAY_SIZE (syntaxclass
))
4538 as_bad ("missing syntax class");
4539 ignore_rest_of_line ();
4546 if (*input_line_pointer
== '|')
4547 input_line_pointer
++;
4552 demand_empty_rest_of_line ();
4554 einsn
->name
= insn_name
;
4555 einsn
->major
= major_opcode
;
4556 einsn
->minor
= sub_opcode
;
4557 einsn
->syntax
= syntax_class
;
4558 einsn
->modsyn
= syntax_class_modifiers
;
4559 einsn
->suffix
= suffix_class
;
4560 einsn
->flags
= syntax_class
4561 | (syntax_class_modifiers
& ARC_OP1_IMM_IMPLIED
? 0x10 : 0);
4564 /* Generate an extension section. */
4567 arc_set_ext_seg (void)
4569 if (!arcext_section
)
4571 arcext_section
= subseg_new (".arcextmap", 0);
4572 bfd_set_section_flags (arcext_section
, SEC_READONLY
| SEC_HAS_CONTENTS
);
4575 subseg_set (arcext_section
, 0);
4579 /* Create an extension instruction description in the arc extension
4580 section of the output file.
4581 The structure for an instruction is like this:
4582 [0]: Length of the record.
4583 [1]: Type of the record.
4587 [4]: Syntax (flags).
4588 [5]+ Name instruction.
4590 The sequence is terminated by an empty entry. */
4593 create_extinst_section (extInstruction_t
*einsn
)
4596 segT old_sec
= now_seg
;
4597 int old_subsec
= now_subseg
;
4599 int name_len
= strlen (einsn
->name
);
4604 *p
= 5 + name_len
+ 1;
4606 *p
= EXT_INSTRUCTION
;
4613 p
= frag_more (name_len
+ 1);
4614 strcpy (p
, einsn
->name
);
4616 subseg_set (old_sec
, old_subsec
);
4619 /* Handler .extinstruction pseudo-op. */
4622 arc_extinsn (int ignore ATTRIBUTE_UNUSED
)
4624 extInstruction_t einsn
;
4625 struct arc_opcode
*arc_ext_opcodes
;
4626 const char *errmsg
= NULL
;
4627 unsigned char moplow
, mophigh
;
4629 memset (&einsn
, 0, sizeof (einsn
));
4630 tokenize_extinsn (&einsn
);
4632 /* Check if the name is already used. */
4633 if (arc_find_opcode (einsn
.name
))
4634 as_warn (_("Pseudocode already used %s"), einsn
.name
);
4636 /* Check the opcode ranges. */
4638 mophigh
= (selected_cpu
.flags
& (ARC_OPCODE_ARCv2EM
4639 | ARC_OPCODE_ARCv2HS
)) ? 0x07 : 0x0a;
4641 if ((einsn
.major
> mophigh
) || (einsn
.major
< moplow
))
4642 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow
, mophigh
);
4644 if ((einsn
.minor
> 0x3f) && (einsn
.major
!= 0x0a)
4645 && (einsn
.major
!= 5) && (einsn
.major
!= 9))
4646 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4648 switch (einsn
.syntax
& ARC_SYNTAX_MASK
)
4650 case ARC_SYNTAX_3OP
:
4651 if (einsn
.modsyn
& ARC_OP1_IMM_IMPLIED
)
4652 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4654 case ARC_SYNTAX_2OP
:
4655 case ARC_SYNTAX_1OP
:
4656 case ARC_SYNTAX_NOP
:
4657 if (einsn
.modsyn
& ARC_OP1_MUST_BE_IMM
)
4658 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4664 arc_ext_opcodes
= arcExtMap_genOpcode (&einsn
, selected_cpu
.flags
, &errmsg
);
4665 if (arc_ext_opcodes
== NULL
)
4668 as_fatal ("%s", errmsg
);
4670 as_fatal (_("Couldn't generate extension instruction opcodes"));
4673 as_warn ("%s", errmsg
);
4675 /* Insert the extension instruction. */
4676 arc_insert_opcode ((const struct arc_opcode
*) arc_ext_opcodes
);
4678 create_extinst_section (&einsn
);
4682 tokenize_extregister (extRegister_t
*ereg
, int opertype
)
4688 int number
, imode
= 0;
4689 bool isCore_p
= opertype
== EXT_CORE_REGISTER
;
4690 bool isReg_p
= opertype
== EXT_CORE_REGISTER
|| opertype
== EXT_AUX_REGISTER
;
4692 /* 1st: get register name. */
4694 p
= input_line_pointer
;
4695 c
= get_symbol_name (&p
);
4698 restore_line_pointer (c
);
4700 /* 2nd: get register number. */
4703 if (*input_line_pointer
!= ',')
4705 as_bad (_("expected comma after name"));
4706 ignore_rest_of_line ();
4710 input_line_pointer
++;
4711 number
= get_absolute_expression ();
4714 && (opertype
!= EXT_AUX_REGISTER
))
4716 as_bad (_("%s second argument cannot be a negative number %d"),
4717 isCore_p
? "extCoreRegister's" : "extCondCode's",
4719 ignore_rest_of_line ();
4726 /* 3rd: get register mode. */
4729 if (*input_line_pointer
!= ',')
4731 as_bad (_("expected comma after register number"));
4732 ignore_rest_of_line ();
4737 input_line_pointer
++;
4738 mode
= input_line_pointer
;
4740 if (startswith (mode
, "r|w"))
4743 input_line_pointer
+= 3;
4745 else if (startswith (mode
, "r"))
4747 imode
= ARC_REGISTER_READONLY
;
4748 input_line_pointer
+= 1;
4750 else if (!startswith (mode
, "w"))
4752 as_bad (_("invalid mode"));
4753 ignore_rest_of_line ();
4759 imode
= ARC_REGISTER_WRITEONLY
;
4760 input_line_pointer
+= 1;
4766 /* 4th: get core register shortcut. */
4768 if (*input_line_pointer
!= ',')
4770 as_bad (_("expected comma after register mode"));
4771 ignore_rest_of_line ();
4776 input_line_pointer
++;
4778 if (startswith (input_line_pointer
, "cannot_shortcut"))
4780 imode
|= ARC_REGISTER_NOSHORT_CUT
;
4781 input_line_pointer
+= 15;
4783 else if (!startswith (input_line_pointer
, "can_shortcut"))
4785 as_bad (_("shortcut designator invalid"));
4786 ignore_rest_of_line ();
4792 input_line_pointer
+= 12;
4795 demand_empty_rest_of_line ();
4798 ereg
->number
= number
;
4799 ereg
->imode
= imode
;
4803 /* Create an extension register/condition description in the arc
4804 extension section of the output file.
4806 The structure for an instruction is like this:
4807 [0]: Length of the record.
4808 [1]: Type of the record.
4810 For core regs and condition codes:
4814 For auxiliary registers:
4818 The sequence is terminated by an empty entry. */
4821 create_extcore_section (extRegister_t
*ereg
, int opertype
)
4823 segT old_sec
= now_seg
;
4824 int old_subsec
= now_subseg
;
4826 int name_len
= strlen (ereg
->name
);
4833 case EXT_CORE_REGISTER
:
4835 *p
= 3 + name_len
+ 1;
4841 case EXT_AUX_REGISTER
:
4843 *p
= 6 + name_len
+ 1;
4845 *p
= EXT_AUX_REGISTER
;
4847 *p
= (ereg
->number
>> 24) & 0xff;
4849 *p
= (ereg
->number
>> 16) & 0xff;
4851 *p
= (ereg
->number
>> 8) & 0xff;
4853 *p
= (ereg
->number
) & 0xff;
4859 p
= frag_more (name_len
+ 1);
4860 strcpy (p
, ereg
->name
);
4862 subseg_set (old_sec
, old_subsec
);
4865 /* Handler .extCoreRegister pseudo-op. */
4868 arc_extcorereg (int opertype
)
4871 struct arc_aux_reg
*auxr
;
4872 struct arc_flag_operand
*ccode
;
4874 memset (&ereg
, 0, sizeof (ereg
));
4875 if (!tokenize_extregister (&ereg
, opertype
))
4880 case EXT_CORE_REGISTER
:
4881 /* Core register. */
4882 if (ereg
.number
> 60)
4883 as_bad (_("core register %s value (%d) too large"), ereg
.name
,
4885 declare_register (ereg
.name
, ereg
.number
);
4887 case EXT_AUX_REGISTER
:
4888 /* Auxiliary register. */
4889 auxr
= XNEW (struct arc_aux_reg
);
4890 auxr
->name
= ereg
.name
;
4891 auxr
->cpu
= selected_cpu
.flags
;
4892 auxr
->subclass
= NONE
;
4893 auxr
->address
= ereg
.number
;
4894 if (str_hash_insert (arc_aux_hash
, auxr
->name
, auxr
, 0) != NULL
)
4895 as_bad (_("duplicate aux register %s"), auxr
->name
);
4898 /* Condition code. */
4899 if (ereg
.number
> 31)
4900 as_bad (_("condition code %s value (%d) too large"), ereg
.name
,
4902 ext_condcode
.size
++;
4903 ext_condcode
.arc_ext_condcode
=
4904 XRESIZEVEC (struct arc_flag_operand
, ext_condcode
.arc_ext_condcode
,
4905 ext_condcode
.size
+ 1);
4907 ccode
= ext_condcode
.arc_ext_condcode
+ ext_condcode
.size
- 1;
4908 ccode
->name
= ereg
.name
;
4909 ccode
->code
= ereg
.number
;
4912 ccode
->favail
= 0; /* not used. */
4914 memset (ccode
, 0, sizeof (struct arc_flag_operand
));
4917 as_bad (_("Unknown extension"));
4920 create_extcore_section (&ereg
, opertype
);
4923 /* Parse a .arc_attribute directive. */
4926 arc_attribute (int ignored ATTRIBUTE_UNUSED
)
4928 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4930 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4931 attributes_set_explicitly
[tag
] = true;
4934 /* Set an attribute if it has not already been set by the user. */
4937 arc_set_attribute_int (int tag
, int value
)
4940 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
4941 || !attributes_set_explicitly
[tag
])
4942 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
4946 arc_set_attribute_string (int tag
, const char *value
)
4949 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
4950 || !attributes_set_explicitly
[tag
])
4951 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
4954 /* Allocate and concatenate two strings. s1 can be NULL but not
4955 s2. s1 pointer is freed at end of this procedure. */
4958 arc_stralloc (char * s1
, const char * s2
)
4964 len
= strlen (s1
) + 1;
4966 /* Only s1 can be null. */
4968 len
+= strlen (s2
) + 1;
4970 p
= (char *) xmalloc (len
);
4985 /* Set the public ARC object attributes. */
4988 arc_set_public_attributes (void)
4994 /* Tag_ARC_CPU_name. */
4995 arc_set_attribute_string (Tag_ARC_CPU_name
, selected_cpu
.name
);
4997 /* Tag_ARC_CPU_base. */
4998 switch (selected_cpu
.eflags
& EF_ARC_MACH_MSK
)
5000 case E_ARC_MACH_ARC600
:
5001 case E_ARC_MACH_ARC601
:
5002 base
= TAG_CPU_ARC6xx
;
5004 case E_ARC_MACH_ARC700
:
5005 base
= TAG_CPU_ARC7xx
;
5007 case EF_ARC_CPU_ARCV2EM
:
5008 base
= TAG_CPU_ARCEM
;
5010 case EF_ARC_CPU_ARCV2HS
:
5011 base
= TAG_CPU_ARCHS
;
5017 if (attributes_set_explicitly
[Tag_ARC_CPU_base
]
5018 && (base
!= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
5020 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
5021 bfd_elf_add_proc_attr_int (stdoutput
, Tag_ARC_CPU_base
, base
);
5023 /* Tag_ARC_ABI_osver. */
5024 if (attributes_set_explicitly
[Tag_ARC_ABI_osver
])
5026 int val
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
5029 selected_cpu
.eflags
= ((selected_cpu
.eflags
& ~EF_ARC_OSABI_MSK
)
5030 | (val
& 0x0f << 8));
5034 arc_set_attribute_int (Tag_ARC_ABI_osver
, E_ARC_OSABI_CURRENT
>> 8);
5037 /* Tag_ARC_ISA_config. */
5038 arc_check_feature();
5040 for (i
= 0; i
< ARRAY_SIZE (feature_list
); i
++)
5041 if (selected_cpu
.features
& feature_list
[i
].feature
)
5042 s
= arc_stralloc (s
, feature_list
[i
].attr
);
5045 arc_set_attribute_string (Tag_ARC_ISA_config
, s
);
5047 /* Tag_ARC_ISA_mpy_option. */
5048 arc_set_attribute_int (Tag_ARC_ISA_mpy_option
, mpy_option
);
5050 /* Tag_ARC_ABI_pic. */
5051 arc_set_attribute_int (Tag_ARC_ABI_pic
, pic_option
);
5053 /* Tag_ARC_ABI_sda. */
5054 arc_set_attribute_int (Tag_ARC_ABI_sda
, sda_option
);
5056 /* Tag_ARC_ABI_tls. */
5057 arc_set_attribute_int (Tag_ARC_ABI_tls
, tls_option
);
5059 /* Tag_ARC_ATR_version. */
5060 arc_set_attribute_int (Tag_ARC_ATR_version
, 1);
5062 /* Tag_ARC_ABI_rf16. */
5063 if (attributes_set_explicitly
[Tag_ARC_ABI_rf16
]
5064 && bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_PROC
,
5068 as_warn (_("Overwrite explicitly set Tag_ARC_ABI_rf16 to full "
5070 bfd_elf_add_proc_attr_int (stdoutput
, Tag_ARC_ABI_rf16
, 0);
5074 /* Add the default contents for the .ARC.attributes section. */
5077 arc_md_finish (void)
5079 arc_set_public_attributes ();
5081 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_arc
, selected_cpu
.mach
))
5082 as_fatal (_("could not set architecture and machine"));
5084 bfd_set_private_flags (stdoutput
, selected_cpu
.eflags
);
5087 void arc_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
5089 ARC_GET_FLAG (dest
) = ARC_GET_FLAG (src
);
5092 int arc_convert_symbolic_attribute (const char *name
)
5101 #define T(tag) {#tag, tag}
5102 T (Tag_ARC_PCS_config
),
5103 T (Tag_ARC_CPU_base
),
5104 T (Tag_ARC_CPU_variation
),
5105 T (Tag_ARC_CPU_name
),
5106 T (Tag_ARC_ABI_rf16
),
5107 T (Tag_ARC_ABI_osver
),
5108 T (Tag_ARC_ABI_sda
),
5109 T (Tag_ARC_ABI_pic
),
5110 T (Tag_ARC_ABI_tls
),
5111 T (Tag_ARC_ABI_enumsize
),
5112 T (Tag_ARC_ABI_exceptions
),
5113 T (Tag_ARC_ABI_double_size
),
5114 T (Tag_ARC_ISA_config
),
5115 T (Tag_ARC_ISA_apex
),
5116 T (Tag_ARC_ISA_mpy_option
),
5117 T (Tag_ARC_ATR_version
)
5125 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
5126 if (streq (name
, attribute_table
[i
].name
))
5127 return attribute_table
[i
].tag
;
5133 eval: (c-set-style "gnu")