1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
80 /* Bit N indicates that an R_ARM_NONE relocation has been output for
81 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
82 emitted only once per section, to save unnecessary bloat. */
83 static unsigned int marked_pr_dependency
= 0;
87 /* Results from operand parsing worker functions. */
91 PARSE_OPERAND_SUCCESS
,
93 PARSE_OPERAND_FAIL_NO_BACKTRACK
94 } parse_operand_result
;
103 /* Types of processor to assemble for. */
105 #if defined __XSCALE__
106 #define CPU_DEFAULT ARM_ARCH_XSCALE
108 #if defined __thumb__
109 #define CPU_DEFAULT ARM_ARCH_V5T
116 # define FPU_DEFAULT FPU_ARCH_FPA
117 # elif defined (TE_NetBSD)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
121 /* Legacy a.out format. */
122 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
124 # elif defined (TE_VXWORKS)
125 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
127 /* For backwards compatibility, default to FPA. */
128 # define FPU_DEFAULT FPU_ARCH_FPA
130 #endif /* ifndef FPU_DEFAULT */
132 #define streq(a, b) (strcmp (a, b) == 0)
134 static arm_feature_set cpu_variant
;
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
149 /* Variables that we set while parsing command-line options. Once all
150 options have been read we re-process these values to set the real
152 static const arm_feature_set
*legacy_cpu
= NULL
;
153 static const arm_feature_set
*legacy_fpu
= NULL
;
155 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
156 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
157 static const arm_feature_set
*march_cpu_opt
= NULL
;
158 static const arm_feature_set
*march_fpu_opt
= NULL
;
159 static const arm_feature_set
*mfpu_opt
= NULL
;
160 static const arm_feature_set
*object_arch
= NULL
;
162 /* Constants for known architecture features. */
163 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
164 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
165 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
166 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
167 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
168 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
169 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
170 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
171 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
174 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
177 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
178 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
179 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
180 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
181 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
182 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
183 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
184 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
185 static const arm_feature_set arm_ext_v4t_5
=
186 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
187 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
188 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
189 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
190 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
191 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
192 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
193 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
194 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
195 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
196 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
197 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
198 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
199 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
200 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
201 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
202 static const arm_feature_set arm_ext_m
=
203 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
205 static const arm_feature_set arm_arch_any
= ARM_ANY
;
206 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
207 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
208 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_cext_iwmmxt2
=
211 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
212 static const arm_feature_set arm_cext_iwmmxt
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
214 static const arm_feature_set arm_cext_xscale
=
215 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
216 static const arm_feature_set arm_cext_maverick
=
217 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
218 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
219 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v1xd
=
221 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
222 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
223 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
224 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
225 static const arm_feature_set fpu_vfp_ext_d32
=
226 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
227 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
228 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
229 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
230 static const arm_feature_set fpu_neon_fp16
= ARM_FEATURE (0, FPU_NEON_FP16
);
232 static int mfloat_abi_opt
= -1;
233 /* Record user cpu selection for object attributes. */
234 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
235 /* Must be long enough to hold any of the names in arm_cpus. */
236 static char selected_cpu_name
[16];
239 static int meabi_flags
= EABI_DEFAULT
;
241 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
244 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
249 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
254 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
255 symbolS
* GOT_symbol
;
258 /* 0: assemble for ARM,
259 1: assemble for Thumb,
260 2: assemble for Thumb even though target CPU does not support thumb
262 static int thumb_mode
= 0;
263 /* A value distinct from the possible values for thumb_mode that we
264 can use to record whether thumb_mode has been copied into the
265 tc_frag_data field of a frag. */
266 #define MODE_RECORDED (1 << 4)
268 /* Specifies the intrinsic IT insn behavior mode. */
269 enum implicit_it_mode
271 IMPLICIT_IT_MODE_NEVER
= 0x00,
272 IMPLICIT_IT_MODE_ARM
= 0x01,
273 IMPLICIT_IT_MODE_THUMB
= 0x02,
274 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
276 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
278 /* If unified_syntax is true, we are processing the new unified
279 ARM/Thumb syntax. Important differences from the old ARM mode:
281 - Immediate operands do not require a # prefix.
282 - Conditional affixes always appear at the end of the
283 instruction. (For backward compatibility, those instructions
284 that formerly had them in the middle, continue to accept them
286 - The IT instruction may appear, and if it does is validated
287 against subsequent conditional affixes. It does not generate
290 Important differences from the old Thumb mode:
292 - Immediate operands do not require a # prefix.
293 - Most of the V6T2 instructions are only available in unified mode.
294 - The .N and .W suffixes are recognized and honored (it is an error
295 if they cannot be honored).
296 - All instructions set the flags if and only if they have an 's' affix.
297 - Conditional affixes may be used. They are validated against
298 preceding IT instructions. Unlike ARM mode, you cannot use a
299 conditional affix except in the scope of an IT instruction. */
301 static bfd_boolean unified_syntax
= FALSE
;
316 enum neon_el_type type
;
320 #define NEON_MAX_TYPE_ELS 4
324 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
328 enum it_instruction_type
333 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
334 if inside, should be the last one. */
335 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
336 i.e. BKPT and NOP. */
337 IT_INSN
/* The IT insn has been parsed. */
343 unsigned long instruction
;
347 /* "uncond_value" is set to the value in place of the conditional field in
348 unconditional versions of the instruction, or -1 if nothing is
351 struct neon_type vectype
;
352 /* Set to the opcode if the instruction needs relaxation.
353 Zero if the instruction is not relaxed. */
357 bfd_reloc_code_real_type type
;
362 enum it_instruction_type it_insn_type
;
368 struct neon_type_el vectype
;
369 unsigned present
: 1; /* Operand present. */
370 unsigned isreg
: 1; /* Operand was a register. */
371 unsigned immisreg
: 1; /* .imm field is a second register. */
372 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
373 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
374 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
375 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
376 instructions. This allows us to disambiguate ARM <-> vector insns. */
377 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
378 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
379 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
380 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
381 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
382 unsigned writeback
: 1; /* Operand has trailing ! */
383 unsigned preind
: 1; /* Preindexed address. */
384 unsigned postind
: 1; /* Postindexed address. */
385 unsigned negative
: 1; /* Index register was negated. */
386 unsigned shifted
: 1; /* Shift applied to operation. */
387 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
391 static struct arm_it inst
;
393 #define NUM_FLOAT_VALS 8
395 const char * fp_const
[] =
397 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
400 /* Number of littlenums required to hold an extended precision number. */
401 #define MAX_LITTLENUMS 6
403 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
413 #define CP_T_X 0x00008000
414 #define CP_T_Y 0x00400000
416 #define CONDS_BIT 0x00100000
417 #define LOAD_BIT 0x00100000
419 #define DOUBLE_LOAD_FLAG 0x00000001
423 const char * template;
427 #define COND_ALWAYS 0xE
431 const char * template;
435 struct asm_barrier_opt
437 const char * template;
441 /* The bit that distinguishes CPSR and SPSR. */
442 #define SPSR_BIT (1 << 22)
444 /* The individual PSR flag bits. */
445 #define PSR_c (1 << 16)
446 #define PSR_x (1 << 17)
447 #define PSR_s (1 << 18)
448 #define PSR_f (1 << 19)
453 bfd_reloc_code_real_type reloc
;
458 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
459 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
464 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
467 /* Bits for DEFINED field in neon_typed_alias. */
468 #define NTA_HASTYPE 1
469 #define NTA_HASINDEX 2
471 struct neon_typed_alias
473 unsigned char defined
;
475 struct neon_type_el eltype
;
478 /* ARM register categories. This includes coprocessor numbers and various
479 architecture extensions' registers. */
505 /* Structure for a hash table entry for a register.
506 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
507 information which states whether a vector type or index is specified (for a
508 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
512 unsigned char number
;
514 unsigned char builtin
;
515 struct neon_typed_alias
* neon
;
518 /* Diagnostics used when we don't get a register of the expected type. */
519 const char * const reg_expected_msgs
[] =
521 N_("ARM register expected"),
522 N_("bad or missing co-processor number"),
523 N_("co-processor register expected"),
524 N_("FPA register expected"),
525 N_("VFP single precision register expected"),
526 N_("VFP/Neon double precision register expected"),
527 N_("Neon quad precision register expected"),
528 N_("VFP single or double precision register expected"),
529 N_("Neon double or quad precision register expected"),
530 N_("VFP single, double or Neon quad precision register expected"),
531 N_("VFP system register expected"),
532 N_("Maverick MVF register expected"),
533 N_("Maverick MVD register expected"),
534 N_("Maverick MVFX register expected"),
535 N_("Maverick MVDX register expected"),
536 N_("Maverick MVAX register expected"),
537 N_("Maverick DSPSC register expected"),
538 N_("iWMMXt data register expected"),
539 N_("iWMMXt control register expected"),
540 N_("iWMMXt scalar register expected"),
541 N_("XScale accumulator register expected"),
544 /* Some well known registers that we refer to directly elsewhere. */
549 /* ARM instructions take 4bytes in the object file, Thumb instructions
555 /* Basic string to match. */
556 const char * template;
558 /* Parameters to instruction. */
559 unsigned char operands
[8];
561 /* Conditional tag - see opcode_lookup. */
562 unsigned int tag
: 4;
564 /* Basic instruction code. */
565 unsigned int avalue
: 28;
567 /* Thumb-format instruction code. */
570 /* Which architecture variant provides this instruction. */
571 const arm_feature_set
* avariant
;
572 const arm_feature_set
* tvariant
;
574 /* Function to call to encode instruction in ARM format. */
575 void (* aencode
) (void);
577 /* Function to call to encode instruction in Thumb format. */
578 void (* tencode
) (void);
581 /* Defines for various bits that we will want to toggle. */
582 #define INST_IMMEDIATE 0x02000000
583 #define OFFSET_REG 0x02000000
584 #define HWOFFSET_IMM 0x00400000
585 #define SHIFT_BY_REG 0x00000010
586 #define PRE_INDEX 0x01000000
587 #define INDEX_UP 0x00800000
588 #define WRITE_BACK 0x00200000
589 #define LDM_TYPE_2_OR_3 0x00400000
590 #define CPSI_MMOD 0x00020000
592 #define LITERAL_MASK 0xf000f000
593 #define OPCODE_MASK 0xfe1fffff
594 #define V4_STR_BIT 0x00000020
596 #define T2_SUBS_PC_LR 0xf3de8f00
598 #define DATA_OP_SHIFT 21
600 #define T2_OPCODE_MASK 0xfe1fffff
601 #define T2_DATA_OP_SHIFT 21
603 /* Codes to distinguish the arithmetic instructions. */
614 #define OPCODE_CMP 10
615 #define OPCODE_CMN 11
616 #define OPCODE_ORR 12
617 #define OPCODE_MOV 13
618 #define OPCODE_BIC 14
619 #define OPCODE_MVN 15
621 #define T2_OPCODE_AND 0
622 #define T2_OPCODE_BIC 1
623 #define T2_OPCODE_ORR 2
624 #define T2_OPCODE_ORN 3
625 #define T2_OPCODE_EOR 4
626 #define T2_OPCODE_ADD 8
627 #define T2_OPCODE_ADC 10
628 #define T2_OPCODE_SBC 11
629 #define T2_OPCODE_SUB 13
630 #define T2_OPCODE_RSB 14
632 #define T_OPCODE_MUL 0x4340
633 #define T_OPCODE_TST 0x4200
634 #define T_OPCODE_CMN 0x42c0
635 #define T_OPCODE_NEG 0x4240
636 #define T_OPCODE_MVN 0x43c0
638 #define T_OPCODE_ADD_R3 0x1800
639 #define T_OPCODE_SUB_R3 0x1a00
640 #define T_OPCODE_ADD_HI 0x4400
641 #define T_OPCODE_ADD_ST 0xb000
642 #define T_OPCODE_SUB_ST 0xb080
643 #define T_OPCODE_ADD_SP 0xa800
644 #define T_OPCODE_ADD_PC 0xa000
645 #define T_OPCODE_ADD_I8 0x3000
646 #define T_OPCODE_SUB_I8 0x3800
647 #define T_OPCODE_ADD_I3 0x1c00
648 #define T_OPCODE_SUB_I3 0x1e00
650 #define T_OPCODE_ASR_R 0x4100
651 #define T_OPCODE_LSL_R 0x4080
652 #define T_OPCODE_LSR_R 0x40c0
653 #define T_OPCODE_ROR_R 0x41c0
654 #define T_OPCODE_ASR_I 0x1000
655 #define T_OPCODE_LSL_I 0x0000
656 #define T_OPCODE_LSR_I 0x0800
658 #define T_OPCODE_MOV_I8 0x2000
659 #define T_OPCODE_CMP_I8 0x2800
660 #define T_OPCODE_CMP_LR 0x4280
661 #define T_OPCODE_MOV_HR 0x4600
662 #define T_OPCODE_CMP_HR 0x4500
664 #define T_OPCODE_LDR_PC 0x4800
665 #define T_OPCODE_LDR_SP 0x9800
666 #define T_OPCODE_STR_SP 0x9000
667 #define T_OPCODE_LDR_IW 0x6800
668 #define T_OPCODE_STR_IW 0x6000
669 #define T_OPCODE_LDR_IH 0x8800
670 #define T_OPCODE_STR_IH 0x8000
671 #define T_OPCODE_LDR_IB 0x7800
672 #define T_OPCODE_STR_IB 0x7000
673 #define T_OPCODE_LDR_RW 0x5800
674 #define T_OPCODE_STR_RW 0x5000
675 #define T_OPCODE_LDR_RH 0x5a00
676 #define T_OPCODE_STR_RH 0x5200
677 #define T_OPCODE_LDR_RB 0x5c00
678 #define T_OPCODE_STR_RB 0x5400
680 #define T_OPCODE_PUSH 0xb400
681 #define T_OPCODE_POP 0xbc00
683 #define T_OPCODE_BRANCH 0xe000
685 #define THUMB_SIZE 2 /* Size of thumb instruction. */
686 #define THUMB_PP_PC_LR 0x0100
687 #define THUMB_LOAD_BIT 0x0800
688 #define THUMB2_LOAD_BIT 0x00100000
690 #define BAD_ARGS _("bad arguments to instruction")
691 #define BAD_SP _("r13 not allowed here")
692 #define BAD_PC _("r15 not allowed here")
693 #define BAD_COND _("instruction cannot be conditional")
694 #define BAD_OVERLAP _("registers may not be the same")
695 #define BAD_HIREG _("lo register required")
696 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
697 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
698 #define BAD_BRANCH _("branch must be last instruction in IT block")
699 #define BAD_NOT_IT _("instruction not allowed in IT block")
700 #define BAD_FPU _("selected FPU does not support instruction")
701 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
702 #define BAD_IT_COND _("incorrect condition in IT block")
703 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
704 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
706 static struct hash_control
* arm_ops_hsh
;
707 static struct hash_control
* arm_cond_hsh
;
708 static struct hash_control
* arm_shift_hsh
;
709 static struct hash_control
* arm_psr_hsh
;
710 static struct hash_control
* arm_v7m_psr_hsh
;
711 static struct hash_control
* arm_reg_hsh
;
712 static struct hash_control
* arm_reloc_hsh
;
713 static struct hash_control
* arm_barrier_opt_hsh
;
715 /* Stuff needed to resolve the label ambiguity
724 symbolS
* last_label_seen
;
725 static int label_is_thumb_function_name
= FALSE
;
727 /* Literal pool structure. Held on a per-section
728 and per-sub-section basis. */
730 #define MAX_LITERAL_POOL_SIZE 1024
731 typedef struct literal_pool
733 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
734 unsigned int next_free_entry
;
739 struct literal_pool
* next
;
742 /* Pointer to a linked list of literal pools. */
743 literal_pool
* list_of_pools
= NULL
;
746 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
748 static struct current_it now_it
;
752 now_it_compatible (int cond
)
754 return (cond
& ~1) == (now_it
.cc
& ~1);
758 conditional_insn (void)
760 return inst
.cond
!= COND_ALWAYS
;
763 static int in_it_block (void);
765 static int handle_it_state (void);
767 static void force_automatic_it_block_close (void);
769 static void it_fsm_post_encode (void);
771 #define set_it_insn_type(type) \
774 inst.it_insn_type = type; \
775 if (handle_it_state () == FAIL) \
780 #define set_it_insn_type_nonvoid(type, failret) \
783 inst.it_insn_type = type; \
784 if (handle_it_state () == FAIL) \
789 #define set_it_insn_type_last() \
792 if (inst.cond == COND_ALWAYS) \
793 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
795 set_it_insn_type (INSIDE_IT_LAST_INSN); \
801 /* This array holds the chars that always start a comment. If the
802 pre-processor is disabled, these aren't very useful. */
803 const char comment_chars
[] = "@";
805 /* This array holds the chars that only start a comment at the beginning of
806 a line. If the line seems to have the form '# 123 filename'
807 .line and .file directives will appear in the pre-processed output. */
808 /* Note that input_file.c hand checks for '#' at the beginning of the
809 first line of the input file. This is because the compiler outputs
810 #NO_APP at the beginning of its output. */
811 /* Also note that comments like this one will always work. */
812 const char line_comment_chars
[] = "#";
814 const char line_separator_chars
[] = ";";
816 /* Chars that can be used to separate mant
817 from exp in floating point numbers. */
818 const char EXP_CHARS
[] = "eE";
820 /* Chars that mean this number is a floating point constant. */
824 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
826 /* Prefix characters that indicate the start of an immediate
828 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
830 /* Separator character handling. */
832 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
835 skip_past_char (char ** str
, char c
)
846 #define skip_past_comma(str) skip_past_char (str, ',')
848 /* Arithmetic expressions (possibly involving symbols). */
850 /* Return TRUE if anything in the expression is a bignum. */
853 walk_no_bignums (symbolS
* sp
)
855 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
858 if (symbol_get_value_expression (sp
)->X_add_symbol
)
860 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
861 || (symbol_get_value_expression (sp
)->X_op_symbol
862 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
868 static int in_my_get_expression
= 0;
870 /* Third argument to my_get_expression. */
871 #define GE_NO_PREFIX 0
872 #define GE_IMM_PREFIX 1
873 #define GE_OPT_PREFIX 2
874 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
875 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
876 #define GE_OPT_PREFIX_BIG 3
879 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
884 /* In unified syntax, all prefixes are optional. */
886 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
891 case GE_NO_PREFIX
: break;
893 if (!is_immediate_prefix (**str
))
895 inst
.error
= _("immediate expression requires a # prefix");
901 case GE_OPT_PREFIX_BIG
:
902 if (is_immediate_prefix (**str
))
908 memset (ep
, 0, sizeof (expressionS
));
910 save_in
= input_line_pointer
;
911 input_line_pointer
= *str
;
912 in_my_get_expression
= 1;
913 seg
= expression (ep
);
914 in_my_get_expression
= 0;
916 if (ep
->X_op
== O_illegal
)
918 /* We found a bad expression in md_operand(). */
919 *str
= input_line_pointer
;
920 input_line_pointer
= save_in
;
921 if (inst
.error
== NULL
)
922 inst
.error
= _("bad expression");
927 if (seg
!= absolute_section
928 && seg
!= text_section
929 && seg
!= data_section
930 && seg
!= bss_section
931 && seg
!= undefined_section
)
933 inst
.error
= _("bad segment");
934 *str
= input_line_pointer
;
935 input_line_pointer
= save_in
;
940 /* Get rid of any bignums now, so that we don't generate an error for which
941 we can't establish a line number later on. Big numbers are never valid
942 in instructions, which is where this routine is always called. */
943 if (prefix_mode
!= GE_OPT_PREFIX_BIG
944 && (ep
->X_op
== O_big
946 && (walk_no_bignums (ep
->X_add_symbol
)
948 && walk_no_bignums (ep
->X_op_symbol
))))))
950 inst
.error
= _("invalid constant");
951 *str
= input_line_pointer
;
952 input_line_pointer
= save_in
;
956 *str
= input_line_pointer
;
957 input_line_pointer
= save_in
;
961 /* Turn a string in input_line_pointer into a floating point constant
962 of type TYPE, and store the appropriate bytes in *LITP. The number
963 of LITTLENUMS emitted is stored in *SIZEP. An error message is
964 returned, or NULL on OK.
966 Note that fp constants aren't represent in the normal way on the ARM.
967 In big endian mode, things are as expected. However, in little endian
968 mode fp constants are big-endian word-wise, and little-endian byte-wise
969 within the words. For example, (double) 1.1 in big endian mode is
970 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
971 the byte sequence 99 99 f1 3f 9a 99 99 99.
973 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
976 md_atof (int type
, char * litP
, int * sizeP
)
979 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1011 return _("Unrecognized or unsupported floating point constant");
1014 t
= atof_ieee (input_line_pointer
, type
, words
);
1016 input_line_pointer
= t
;
1017 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1019 if (target_big_endian
)
1021 for (i
= 0; i
< prec
; i
++)
1023 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1024 litP
+= sizeof (LITTLENUM_TYPE
);
1029 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1030 for (i
= prec
- 1; i
>= 0; i
--)
1032 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1033 litP
+= sizeof (LITTLENUM_TYPE
);
1036 /* For a 4 byte float the order of elements in `words' is 1 0.
1037 For an 8 byte float the order is 1 0 3 2. */
1038 for (i
= 0; i
< prec
; i
+= 2)
1040 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1041 sizeof (LITTLENUM_TYPE
));
1042 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1043 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1044 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1051 /* We handle all bad expressions here, so that we can report the faulty
1052 instruction in the error message. */
1054 md_operand (expressionS
* expr
)
1056 if (in_my_get_expression
)
1057 expr
->X_op
= O_illegal
;
1060 /* Immediate values. */
1062 /* Generic immediate-value read function for use in directives.
1063 Accepts anything that 'expression' can fold to a constant.
1064 *val receives the number. */
1067 immediate_for_directive (int *val
)
1070 exp
.X_op
= O_illegal
;
1072 if (is_immediate_prefix (*input_line_pointer
))
1074 input_line_pointer
++;
1078 if (exp
.X_op
!= O_constant
)
1080 as_bad (_("expected #constant"));
1081 ignore_rest_of_line ();
1084 *val
= exp
.X_add_number
;
1089 /* Register parsing. */
1091 /* Generic register parser. CCP points to what should be the
1092 beginning of a register name. If it is indeed a valid register
1093 name, advance CCP over it and return the reg_entry structure;
1094 otherwise return NULL. Does not issue diagnostics. */
1096 static struct reg_entry
*
1097 arm_reg_parse_multi (char **ccp
)
1101 struct reg_entry
*reg
;
1103 #ifdef REGISTER_PREFIX
1104 if (*start
!= REGISTER_PREFIX
)
1108 #ifdef OPTIONAL_REGISTER_PREFIX
1109 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1114 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1119 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1121 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1131 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1132 enum arm_reg_type type
)
1134 /* Alternative syntaxes are accepted for a few register classes. */
1141 /* Generic coprocessor register names are allowed for these. */
1142 if (reg
&& reg
->type
== REG_TYPE_CN
)
1147 /* For backward compatibility, a bare number is valid here. */
1149 unsigned long processor
= strtoul (start
, ccp
, 10);
1150 if (*ccp
!= start
&& processor
<= 15)
1154 case REG_TYPE_MMXWC
:
1155 /* WC includes WCG. ??? I'm not sure this is true for all
1156 instructions that take WC registers. */
1157 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1168 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1169 return value is the register number or FAIL. */
1172 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1175 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1178 /* Do not allow a scalar (reg+index) to parse as a register. */
1179 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1182 if (reg
&& reg
->type
== type
)
1185 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1192 /* Parse a Neon type specifier. *STR should point at the leading '.'
1193 character. Does no verification at this stage that the type fits the opcode
1200 Can all be legally parsed by this function.
1202 Fills in neon_type struct pointer with parsed information, and updates STR
1203 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1204 type, FAIL if not. */
1207 parse_neon_type (struct neon_type
*type
, char **str
)
1214 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1216 enum neon_el_type thistype
= NT_untyped
;
1217 unsigned thissize
= -1u;
1224 /* Just a size without an explicit type. */
1228 switch (TOLOWER (*ptr
))
1230 case 'i': thistype
= NT_integer
; break;
1231 case 'f': thistype
= NT_float
; break;
1232 case 'p': thistype
= NT_poly
; break;
1233 case 's': thistype
= NT_signed
; break;
1234 case 'u': thistype
= NT_unsigned
; break;
1236 thistype
= NT_float
;
1241 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1247 /* .f is an abbreviation for .f32. */
1248 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1253 thissize
= strtoul (ptr
, &ptr
, 10);
1255 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1258 as_bad (_("bad size %d in type specifier"), thissize
);
1266 type
->el
[type
->elems
].type
= thistype
;
1267 type
->el
[type
->elems
].size
= thissize
;
1272 /* Empty/missing type is not a successful parse. */
1273 if (type
->elems
== 0)
1281 /* Errors may be set multiple times during parsing or bit encoding
1282 (particularly in the Neon bits), but usually the earliest error which is set
1283 will be the most meaningful. Avoid overwriting it with later (cascading)
1284 errors by calling this function. */
1287 first_error (const char *err
)
1293 /* Parse a single type, e.g. ".s32", leading period included. */
1295 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1298 struct neon_type optype
;
1302 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1304 if (optype
.elems
== 1)
1305 *vectype
= optype
.el
[0];
1308 first_error (_("only one type should be specified for operand"));
1314 first_error (_("vector type expected"));
1326 /* Special meanings for indices (which have a range of 0-7), which will fit into
1329 #define NEON_ALL_LANES 15
1330 #define NEON_INTERLEAVE_LANES 14
1332 /* Parse either a register or a scalar, with an optional type. Return the
1333 register number, and optionally fill in the actual type of the register
1334 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1335 type/index information in *TYPEINFO. */
1338 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1339 enum arm_reg_type
*rtype
,
1340 struct neon_typed_alias
*typeinfo
)
1343 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1344 struct neon_typed_alias atype
;
1345 struct neon_type_el parsetype
;
1349 atype
.eltype
.type
= NT_invtype
;
1350 atype
.eltype
.size
= -1;
1352 /* Try alternate syntax for some types of register. Note these are mutually
1353 exclusive with the Neon syntax extensions. */
1356 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1364 /* Undo polymorphism when a set of register types may be accepted. */
1365 if ((type
== REG_TYPE_NDQ
1366 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1367 || (type
== REG_TYPE_VFSD
1368 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1369 || (type
== REG_TYPE_NSDQ
1370 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1371 || reg
->type
== REG_TYPE_NQ
))
1372 || (type
== REG_TYPE_MMXWC
1373 && (reg
->type
== REG_TYPE_MMXWCG
)))
1376 if (type
!= reg
->type
)
1382 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1384 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1386 first_error (_("can't redefine type for operand"));
1389 atype
.defined
|= NTA_HASTYPE
;
1390 atype
.eltype
= parsetype
;
1393 if (skip_past_char (&str
, '[') == SUCCESS
)
1395 if (type
!= REG_TYPE_VFD
)
1397 first_error (_("only D registers may be indexed"));
1401 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1403 first_error (_("can't change index for operand"));
1407 atype
.defined
|= NTA_HASINDEX
;
1409 if (skip_past_char (&str
, ']') == SUCCESS
)
1410 atype
.index
= NEON_ALL_LANES
;
1415 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1417 if (exp
.X_op
!= O_constant
)
1419 first_error (_("constant expression required"));
1423 if (skip_past_char (&str
, ']') == FAIL
)
1426 atype
.index
= exp
.X_add_number
;
1441 /* Like arm_reg_parse, but allow allow the following extra features:
1442 - If RTYPE is non-zero, return the (possibly restricted) type of the
1443 register (e.g. Neon double or quad reg when either has been requested).
1444 - If this is a Neon vector type with additional type information, fill
1445 in the struct pointed to by VECTYPE (if non-NULL).
1446 This function will fault on encountering a scalar. */
1449 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1450 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1452 struct neon_typed_alias atype
;
1454 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1459 /* Do not allow a scalar (reg+index) to parse as a register. */
1460 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1462 first_error (_("register operand expected, but got scalar"));
1467 *vectype
= atype
.eltype
;
1474 #define NEON_SCALAR_REG(X) ((X) >> 4)
1475 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1477 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1478 have enough information to be able to do a good job bounds-checking. So, we
1479 just do easy checks here, and do further checks later. */
1482 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1486 struct neon_typed_alias atype
;
1488 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1490 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1493 if (atype
.index
== NEON_ALL_LANES
)
1495 first_error (_("scalar must have an index"));
1498 else if (atype
.index
>= 64 / elsize
)
1500 first_error (_("scalar index out of range"));
1505 *type
= atype
.eltype
;
1509 return reg
* 16 + atype
.index
;
1512 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1515 parse_reg_list (char ** strp
)
1517 char * str
= * strp
;
1521 /* We come back here if we get ranges concatenated by '+' or '|'. */
1536 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1538 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1548 first_error (_("bad range in register list"));
1552 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1554 if (range
& (1 << i
))
1556 (_("Warning: duplicated register (r%d) in register list"),
1564 if (range
& (1 << reg
))
1565 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1567 else if (reg
<= cur_reg
)
1568 as_tsktsk (_("Warning: register range not in ascending order"));
1573 while (skip_past_comma (&str
) != FAIL
1574 || (in_range
= 1, *str
++ == '-'));
1579 first_error (_("missing `}'"));
1587 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1590 if (expr
.X_op
== O_constant
)
1592 if (expr
.X_add_number
1593 != (expr
.X_add_number
& 0x0000ffff))
1595 inst
.error
= _("invalid register mask");
1599 if ((range
& expr
.X_add_number
) != 0)
1601 int regno
= range
& expr
.X_add_number
;
1604 regno
= (1 << regno
) - 1;
1606 (_("Warning: duplicated register (r%d) in register list"),
1610 range
|= expr
.X_add_number
;
1614 if (inst
.reloc
.type
!= 0)
1616 inst
.error
= _("expression too complex");
1620 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1621 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1622 inst
.reloc
.pc_rel
= 0;
1626 if (*str
== '|' || *str
== '+')
1632 while (another_range
);
1638 /* Types of registers in a list. */
1647 /* Parse a VFP register list. If the string is invalid return FAIL.
1648 Otherwise return the number of registers, and set PBASE to the first
1649 register. Parses registers of type ETYPE.
1650 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1651 - Q registers can be used to specify pairs of D registers
1652 - { } can be omitted from around a singleton register list
1653 FIXME: This is not implemented, as it would require backtracking in
1656 This could be done (the meaning isn't really ambiguous), but doesn't
1657 fit in well with the current parsing framework.
1658 - 32 D registers may be used (also true for VFPv3).
1659 FIXME: Types are ignored in these register lists, which is probably a
1663 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1668 enum arm_reg_type regtype
= 0;
1672 unsigned long mask
= 0;
1677 inst
.error
= _("expecting {");
1686 regtype
= REG_TYPE_VFS
;
1691 regtype
= REG_TYPE_VFD
;
1694 case REGLIST_NEON_D
:
1695 regtype
= REG_TYPE_NDQ
;
1699 if (etype
!= REGLIST_VFP_S
)
1701 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1702 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1706 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1709 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1716 base_reg
= max_regs
;
1720 int setmask
= 1, addregs
= 1;
1722 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1724 if (new_base
== FAIL
)
1726 first_error (_(reg_expected_msgs
[regtype
]));
1730 if (new_base
>= max_regs
)
1732 first_error (_("register out of range in list"));
1736 /* Note: a value of 2 * n is returned for the register Q<n>. */
1737 if (regtype
== REG_TYPE_NQ
)
1743 if (new_base
< base_reg
)
1744 base_reg
= new_base
;
1746 if (mask
& (setmask
<< new_base
))
1748 first_error (_("invalid register list"));
1752 if ((mask
>> new_base
) != 0 && ! warned
)
1754 as_tsktsk (_("register list not in ascending order"));
1758 mask
|= setmask
<< new_base
;
1761 if (*str
== '-') /* We have the start of a range expression */
1767 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1770 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1774 if (high_range
>= max_regs
)
1776 first_error (_("register out of range in list"));
1780 if (regtype
== REG_TYPE_NQ
)
1781 high_range
= high_range
+ 1;
1783 if (high_range
<= new_base
)
1785 inst
.error
= _("register range not in ascending order");
1789 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1791 if (mask
& (setmask
<< new_base
))
1793 inst
.error
= _("invalid register list");
1797 mask
|= setmask
<< new_base
;
1802 while (skip_past_comma (&str
) != FAIL
);
1806 /* Sanity check -- should have raised a parse error above. */
1807 if (count
== 0 || count
> max_regs
)
1812 /* Final test -- the registers must be consecutive. */
1814 for (i
= 0; i
< count
; i
++)
1816 if ((mask
& (1u << i
)) == 0)
1818 inst
.error
= _("non-contiguous register range");
1828 /* True if two alias types are the same. */
1831 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1839 if (a
->defined
!= b
->defined
)
1842 if ((a
->defined
& NTA_HASTYPE
) != 0
1843 && (a
->eltype
.type
!= b
->eltype
.type
1844 || a
->eltype
.size
!= b
->eltype
.size
))
1847 if ((a
->defined
& NTA_HASINDEX
) != 0
1848 && (a
->index
!= b
->index
))
1854 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1855 The base register is put in *PBASE.
1856 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1858 The register stride (minus one) is put in bit 4 of the return value.
1859 Bits [6:5] encode the list length (minus one).
1860 The type of the list elements is put in *ELTYPE, if non-NULL. */
1862 #define NEON_LANE(X) ((X) & 0xf)
1863 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1864 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1867 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1868 struct neon_type_el
*eltype
)
1875 int leading_brace
= 0;
1876 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1878 const char *const incr_error
= _("register stride must be 1 or 2");
1879 const char *const type_error
= _("mismatched element/structure types in list");
1880 struct neon_typed_alias firsttype
;
1882 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1887 struct neon_typed_alias atype
;
1888 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1892 first_error (_(reg_expected_msgs
[rtype
]));
1899 if (rtype
== REG_TYPE_NQ
)
1906 else if (reg_incr
== -1)
1908 reg_incr
= getreg
- base_reg
;
1909 if (reg_incr
< 1 || reg_incr
> 2)
1911 first_error (_(incr_error
));
1915 else if (getreg
!= base_reg
+ reg_incr
* count
)
1917 first_error (_(incr_error
));
1921 if (! neon_alias_types_same (&atype
, &firsttype
))
1923 first_error (_(type_error
));
1927 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1931 struct neon_typed_alias htype
;
1932 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1934 lane
= NEON_INTERLEAVE_LANES
;
1935 else if (lane
!= NEON_INTERLEAVE_LANES
)
1937 first_error (_(type_error
));
1942 else if (reg_incr
!= 1)
1944 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1948 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1951 first_error (_(reg_expected_msgs
[rtype
]));
1954 if (! neon_alias_types_same (&htype
, &firsttype
))
1956 first_error (_(type_error
));
1959 count
+= hireg
+ dregs
- getreg
;
1963 /* If we're using Q registers, we can't use [] or [n] syntax. */
1964 if (rtype
== REG_TYPE_NQ
)
1970 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1974 else if (lane
!= atype
.index
)
1976 first_error (_(type_error
));
1980 else if (lane
== -1)
1981 lane
= NEON_INTERLEAVE_LANES
;
1982 else if (lane
!= NEON_INTERLEAVE_LANES
)
1984 first_error (_(type_error
));
1989 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1991 /* No lane set by [x]. We must be interleaving structures. */
1993 lane
= NEON_INTERLEAVE_LANES
;
1996 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1997 || (count
> 1 && reg_incr
== -1))
1999 first_error (_("error parsing element/structure list"));
2003 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2005 first_error (_("expected }"));
2013 *eltype
= firsttype
.eltype
;
2018 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2021 /* Parse an explicit relocation suffix on an expression. This is
2022 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2023 arm_reloc_hsh contains no entries, so this function can only
2024 succeed if there is no () after the word. Returns -1 on error,
2025 BFD_RELOC_UNUSED if there wasn't any suffix. */
2027 parse_reloc (char **str
)
2029 struct reloc_entry
*r
;
2033 return BFD_RELOC_UNUSED
;
2038 while (*q
&& *q
!= ')' && *q
!= ',')
2043 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2050 /* Directives: register aliases. */
2052 static struct reg_entry
*
2053 insert_reg_alias (char *str
, int number
, int type
)
2055 struct reg_entry
*new;
2058 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
2061 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2063 /* Only warn about a redefinition if it's not defined as the
2065 else if (new->number
!= number
|| new->type
!= type
)
2066 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2071 name
= xstrdup (str
);
2072 new = xmalloc (sizeof (struct reg_entry
));
2075 new->number
= number
;
2077 new->builtin
= FALSE
;
2080 if (hash_insert (arm_reg_hsh
, name
, (void *) new))
2087 insert_neon_reg_alias (char *str
, int number
, int type
,
2088 struct neon_typed_alias
*atype
)
2090 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2094 first_error (_("attempt to redefine typed alias"));
2100 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2101 *reg
->neon
= *atype
;
2105 /* Look for the .req directive. This is of the form:
2107 new_register_name .req existing_register_name
2109 If we find one, or if it looks sufficiently like one that we want to
2110 handle any error here, return TRUE. Otherwise return FALSE. */
2113 create_register_alias (char * newname
, char *p
)
2115 struct reg_entry
*old
;
2116 char *oldname
, *nbuf
;
2119 /* The input scrubber ensures that whitespace after the mnemonic is
2120 collapsed to single spaces. */
2122 if (strncmp (oldname
, " .req ", 6) != 0)
2126 if (*oldname
== '\0')
2129 old
= hash_find (arm_reg_hsh
, oldname
);
2132 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2136 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2137 the desired alias name, and p points to its end. If not, then
2138 the desired alias name is in the global original_case_string. */
2139 #ifdef TC_CASE_SENSITIVE
2142 newname
= original_case_string
;
2143 nlen
= strlen (newname
);
2146 nbuf
= alloca (nlen
+ 1);
2147 memcpy (nbuf
, newname
, nlen
);
2150 /* Create aliases under the new name as stated; an all-lowercase
2151 version of the new name; and an all-uppercase version of the new
2153 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2155 for (p
= nbuf
; *p
; p
++)
2158 if (strncmp (nbuf
, newname
, nlen
))
2160 /* If this attempt to create an additional alias fails, do not bother
2161 trying to create the all-lower case alias. We will fail and issue
2162 a second, duplicate error message. This situation arises when the
2163 programmer does something like:
2166 The second .req creates the "Foo" alias but then fails to create
2167 the artificial FOO alias because it has already been created by the
2169 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2173 for (p
= nbuf
; *p
; p
++)
2176 if (strncmp (nbuf
, newname
, nlen
))
2177 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2183 /* Create a Neon typed/indexed register alias using directives, e.g.:
2188 These typed registers can be used instead of the types specified after the
2189 Neon mnemonic, so long as all operands given have types. Types can also be
2190 specified directly, e.g.:
2191 vadd d0.s32, d1.s32, d2.s32 */
2194 create_neon_reg_alias (char *newname
, char *p
)
2196 enum arm_reg_type basetype
;
2197 struct reg_entry
*basereg
;
2198 struct reg_entry mybasereg
;
2199 struct neon_type ntype
;
2200 struct neon_typed_alias typeinfo
;
2201 char *namebuf
, *nameend
;
2204 typeinfo
.defined
= 0;
2205 typeinfo
.eltype
.type
= NT_invtype
;
2206 typeinfo
.eltype
.size
= -1;
2207 typeinfo
.index
= -1;
2211 if (strncmp (p
, " .dn ", 5) == 0)
2212 basetype
= REG_TYPE_VFD
;
2213 else if (strncmp (p
, " .qn ", 5) == 0)
2214 basetype
= REG_TYPE_NQ
;
2223 basereg
= arm_reg_parse_multi (&p
);
2225 if (basereg
&& basereg
->type
!= basetype
)
2227 as_bad (_("bad type for register"));
2231 if (basereg
== NULL
)
2234 /* Try parsing as an integer. */
2235 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2236 if (exp
.X_op
!= O_constant
)
2238 as_bad (_("expression must be constant"));
2241 basereg
= &mybasereg
;
2242 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2248 typeinfo
= *basereg
->neon
;
2250 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2252 /* We got a type. */
2253 if (typeinfo
.defined
& NTA_HASTYPE
)
2255 as_bad (_("can't redefine the type of a register alias"));
2259 typeinfo
.defined
|= NTA_HASTYPE
;
2260 if (ntype
.elems
!= 1)
2262 as_bad (_("you must specify a single type only"));
2265 typeinfo
.eltype
= ntype
.el
[0];
2268 if (skip_past_char (&p
, '[') == SUCCESS
)
2271 /* We got a scalar index. */
2273 if (typeinfo
.defined
& NTA_HASINDEX
)
2275 as_bad (_("can't redefine the index of a scalar alias"));
2279 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2281 if (exp
.X_op
!= O_constant
)
2283 as_bad (_("scalar index must be constant"));
2287 typeinfo
.defined
|= NTA_HASINDEX
;
2288 typeinfo
.index
= exp
.X_add_number
;
2290 if (skip_past_char (&p
, ']') == FAIL
)
2292 as_bad (_("expecting ]"));
2297 namelen
= nameend
- newname
;
2298 namebuf
= alloca (namelen
+ 1);
2299 strncpy (namebuf
, newname
, namelen
);
2300 namebuf
[namelen
] = '\0';
2302 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2303 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2305 /* Insert name in all uppercase. */
2306 for (p
= namebuf
; *p
; p
++)
2309 if (strncmp (namebuf
, newname
, namelen
))
2310 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2311 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2313 /* Insert name in all lowercase. */
2314 for (p
= namebuf
; *p
; p
++)
2317 if (strncmp (namebuf
, newname
, namelen
))
2318 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2319 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2324 /* Should never be called, as .req goes between the alias and the
2325 register name, not at the beginning of the line. */
2328 s_req (int a ATTRIBUTE_UNUSED
)
2330 as_bad (_("invalid syntax for .req directive"));
2334 s_dn (int a ATTRIBUTE_UNUSED
)
2336 as_bad (_("invalid syntax for .dn directive"));
2340 s_qn (int a ATTRIBUTE_UNUSED
)
2342 as_bad (_("invalid syntax for .qn directive"));
2345 /* The .unreq directive deletes an alias which was previously defined
2346 by .req. For example:
2352 s_unreq (int a ATTRIBUTE_UNUSED
)
2357 name
= input_line_pointer
;
2359 while (*input_line_pointer
!= 0
2360 && *input_line_pointer
!= ' '
2361 && *input_line_pointer
!= '\n')
2362 ++input_line_pointer
;
2364 saved_char
= *input_line_pointer
;
2365 *input_line_pointer
= 0;
2368 as_bad (_("invalid syntax for .unreq directive"));
2371 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2374 as_bad (_("unknown register alias '%s'"), name
);
2375 else if (reg
->builtin
)
2376 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2383 hash_delete (arm_reg_hsh
, name
, FALSE
);
2384 free ((char *) reg
->name
);
2389 /* Also locate the all upper case and all lower case versions.
2390 Do not complain if we cannot find one or the other as it
2391 was probably deleted above. */
2393 nbuf
= strdup (name
);
2394 for (p
= nbuf
; *p
; p
++)
2396 reg
= hash_find (arm_reg_hsh
, nbuf
);
2399 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2400 free ((char *) reg
->name
);
2406 for (p
= nbuf
; *p
; p
++)
2408 reg
= hash_find (arm_reg_hsh
, nbuf
);
2411 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2412 free ((char *) reg
->name
);
2422 *input_line_pointer
= saved_char
;
2423 demand_empty_rest_of_line ();
2426 /* Directives: Instruction set selection. */
2429 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2430 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2431 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2432 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2434 static enum mstate mapstate
= MAP_UNDEFINED
;
2437 mapping_state (enum mstate state
)
2440 const char * symname
;
2443 if (mapstate
== state
)
2444 /* The mapping symbol has already been emitted.
2445 There is nothing else to do. */
2454 type
= BSF_NO_FLAGS
;
2458 type
= BSF_NO_FLAGS
;
2462 type
= BSF_NO_FLAGS
;
2470 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2472 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2473 symbol_table_insert (symbolP
);
2474 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2479 THUMB_SET_FUNC (symbolP
, 0);
2480 ARM_SET_THUMB (symbolP
, 0);
2481 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2485 THUMB_SET_FUNC (symbolP
, 1);
2486 ARM_SET_THUMB (symbolP
, 1);
2487 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2496 #define mapping_state(x) /* nothing */
2499 /* Find the real, Thumb encoded start of a Thumb function. */
2503 find_real_start (symbolS
* symbolP
)
2506 const char * name
= S_GET_NAME (symbolP
);
2507 symbolS
* new_target
;
2509 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2510 #define STUB_NAME ".real_start_of"
2515 /* The compiler may generate BL instructions to local labels because
2516 it needs to perform a branch to a far away location. These labels
2517 do not have a corresponding ".real_start_of" label. We check
2518 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2519 the ".real_start_of" convention for nonlocal branches. */
2520 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2523 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2524 new_target
= symbol_find (real_start
);
2526 if (new_target
== NULL
)
2528 as_warn (_("Failed to find real start of function: %s\n"), name
);
2529 new_target
= symbolP
;
2537 opcode_select (int width
)
2544 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2545 as_bad (_("selected processor does not support THUMB opcodes"));
2548 /* No need to force the alignment, since we will have been
2549 coming from ARM mode, which is word-aligned. */
2550 record_alignment (now_seg
, 1);
2552 mapping_state (MAP_THUMB
);
2558 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2559 as_bad (_("selected processor does not support ARM opcodes"));
2564 frag_align (2, 0, 0);
2566 record_alignment (now_seg
, 1);
2568 mapping_state (MAP_ARM
);
2572 as_bad (_("invalid instruction size selected (%d)"), width
);
2577 s_arm (int ignore ATTRIBUTE_UNUSED
)
2580 demand_empty_rest_of_line ();
2584 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2587 demand_empty_rest_of_line ();
2591 s_code (int unused ATTRIBUTE_UNUSED
)
2595 temp
= get_absolute_expression ();
2600 opcode_select (temp
);
2604 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2609 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2611 /* If we are not already in thumb mode go into it, EVEN if
2612 the target processor does not support thumb instructions.
2613 This is used by gcc/config/arm/lib1funcs.asm for example
2614 to compile interworking support functions even if the
2615 target processor should not support interworking. */
2619 record_alignment (now_seg
, 1);
2622 demand_empty_rest_of_line ();
2626 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2630 /* The following label is the name/address of the start of a Thumb function.
2631 We need to know this for the interworking support. */
2632 label_is_thumb_function_name
= TRUE
;
2635 /* Perform a .set directive, but also mark the alias as
2636 being a thumb function. */
2639 s_thumb_set (int equiv
)
2641 /* XXX the following is a duplicate of the code for s_set() in read.c
2642 We cannot just call that code as we need to get at the symbol that
2649 /* Especial apologies for the random logic:
2650 This just grew, and could be parsed much more simply!
2652 name
= input_line_pointer
;
2653 delim
= get_symbol_end ();
2654 end_name
= input_line_pointer
;
2657 if (*input_line_pointer
!= ',')
2660 as_bad (_("expected comma after name \"%s\""), name
);
2662 ignore_rest_of_line ();
2666 input_line_pointer
++;
2669 if (name
[0] == '.' && name
[1] == '\0')
2671 /* XXX - this should not happen to .thumb_set. */
2675 if ((symbolP
= symbol_find (name
)) == NULL
2676 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2679 /* When doing symbol listings, play games with dummy fragments living
2680 outside the normal fragment chain to record the file and line info
2682 if (listing
& LISTING_SYMBOLS
)
2684 extern struct list_info_struct
* listing_tail
;
2685 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2687 memset (dummy_frag
, 0, sizeof (fragS
));
2688 dummy_frag
->fr_type
= rs_fill
;
2689 dummy_frag
->line
= listing_tail
;
2690 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2691 dummy_frag
->fr_symbol
= symbolP
;
2695 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2698 /* "set" symbols are local unless otherwise specified. */
2699 SF_SET_LOCAL (symbolP
);
2700 #endif /* OBJ_COFF */
2701 } /* Make a new symbol. */
2703 symbol_table_insert (symbolP
);
2708 && S_IS_DEFINED (symbolP
)
2709 && S_GET_SEGMENT (symbolP
) != reg_section
)
2710 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2712 pseudo_set (symbolP
);
2714 demand_empty_rest_of_line ();
2716 /* XXX Now we come to the Thumb specific bit of code. */
2718 THUMB_SET_FUNC (symbolP
, 1);
2719 ARM_SET_THUMB (symbolP
, 1);
2720 #if defined OBJ_ELF || defined OBJ_COFF
2721 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2725 /* Directives: Mode selection. */
2727 /* .syntax [unified|divided] - choose the new unified syntax
2728 (same for Arm and Thumb encoding, modulo slight differences in what
2729 can be represented) or the old divergent syntax for each mode. */
2731 s_syntax (int unused ATTRIBUTE_UNUSED
)
2735 name
= input_line_pointer
;
2736 delim
= get_symbol_end ();
2738 if (!strcasecmp (name
, "unified"))
2739 unified_syntax
= TRUE
;
2740 else if (!strcasecmp (name
, "divided"))
2741 unified_syntax
= FALSE
;
2744 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2747 *input_line_pointer
= delim
;
2748 demand_empty_rest_of_line ();
2751 /* Directives: sectioning and alignment. */
2753 /* Same as s_align_ptwo but align 0 => align 2. */
2756 s_align (int unused ATTRIBUTE_UNUSED
)
2761 long max_alignment
= 15;
2763 temp
= get_absolute_expression ();
2764 if (temp
> max_alignment
)
2765 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2768 as_bad (_("alignment negative. 0 assumed."));
2772 if (*input_line_pointer
== ',')
2774 input_line_pointer
++;
2775 temp_fill
= get_absolute_expression ();
2787 /* Only make a frag if we HAVE to. */
2788 if (temp
&& !need_pass_2
)
2790 if (!fill_p
&& subseg_text_p (now_seg
))
2791 frag_align_code (temp
, 0);
2793 frag_align (temp
, (int) temp_fill
, 0);
2795 demand_empty_rest_of_line ();
2797 record_alignment (now_seg
, temp
);
2801 s_bss (int ignore ATTRIBUTE_UNUSED
)
2803 /* We don't support putting frags in the BSS segment, we fake it by
2804 marking in_bss, then looking at s_skip for clues. */
2805 subseg_set (bss_section
, 0);
2806 demand_empty_rest_of_line ();
2807 mapping_state (MAP_DATA
);
2811 s_even (int ignore ATTRIBUTE_UNUSED
)
2813 /* Never make frag if expect extra pass. */
2815 frag_align (1, 0, 0);
2817 record_alignment (now_seg
, 1);
2819 demand_empty_rest_of_line ();
2822 /* Directives: Literal pools. */
2824 static literal_pool
*
2825 find_literal_pool (void)
2827 literal_pool
* pool
;
2829 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2831 if (pool
->section
== now_seg
2832 && pool
->sub_section
== now_subseg
)
2839 static literal_pool
*
2840 find_or_make_literal_pool (void)
2842 /* Next literal pool ID number. */
2843 static unsigned int latest_pool_num
= 1;
2844 literal_pool
* pool
;
2846 pool
= find_literal_pool ();
2850 /* Create a new pool. */
2851 pool
= xmalloc (sizeof (* pool
));
2855 pool
->next_free_entry
= 0;
2856 pool
->section
= now_seg
;
2857 pool
->sub_section
= now_subseg
;
2858 pool
->next
= list_of_pools
;
2859 pool
->symbol
= NULL
;
2861 /* Add it to the list. */
2862 list_of_pools
= pool
;
2865 /* New pools, and emptied pools, will have a NULL symbol. */
2866 if (pool
->symbol
== NULL
)
2868 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2869 (valueT
) 0, &zero_address_frag
);
2870 pool
->id
= latest_pool_num
++;
2877 /* Add the literal in the global 'inst'
2878 structure to the relevant literal pool. */
2881 add_to_lit_pool (void)
2883 literal_pool
* pool
;
2886 pool
= find_or_make_literal_pool ();
2888 /* Check if this literal value is already in the pool. */
2889 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2891 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2892 && (inst
.reloc
.exp
.X_op
== O_constant
)
2893 && (pool
->literals
[entry
].X_add_number
2894 == inst
.reloc
.exp
.X_add_number
)
2895 && (pool
->literals
[entry
].X_unsigned
2896 == inst
.reloc
.exp
.X_unsigned
))
2899 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2900 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2901 && (pool
->literals
[entry
].X_add_number
2902 == inst
.reloc
.exp
.X_add_number
)
2903 && (pool
->literals
[entry
].X_add_symbol
2904 == inst
.reloc
.exp
.X_add_symbol
)
2905 && (pool
->literals
[entry
].X_op_symbol
2906 == inst
.reloc
.exp
.X_op_symbol
))
2910 /* Do we need to create a new entry? */
2911 if (entry
== pool
->next_free_entry
)
2913 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2915 inst
.error
= _("literal pool overflow");
2919 pool
->literals
[entry
] = inst
.reloc
.exp
;
2920 pool
->next_free_entry
+= 1;
2923 inst
.reloc
.exp
.X_op
= O_symbol
;
2924 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2925 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2930 /* Can't use symbol_new here, so have to create a symbol and then at
2931 a later date assign it a value. Thats what these functions do. */
2934 symbol_locate (symbolS
* symbolP
,
2935 const char * name
, /* It is copied, the caller can modify. */
2936 segT segment
, /* Segment identifier (SEG_<something>). */
2937 valueT valu
, /* Symbol value. */
2938 fragS
* frag
) /* Associated fragment. */
2940 unsigned int name_length
;
2941 char * preserved_copy_of_name
;
2943 name_length
= strlen (name
) + 1; /* +1 for \0. */
2944 obstack_grow (¬es
, name
, name_length
);
2945 preserved_copy_of_name
= obstack_finish (¬es
);
2947 #ifdef tc_canonicalize_symbol_name
2948 preserved_copy_of_name
=
2949 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2952 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2954 S_SET_SEGMENT (symbolP
, segment
);
2955 S_SET_VALUE (symbolP
, valu
);
2956 symbol_clear_list_pointers (symbolP
);
2958 symbol_set_frag (symbolP
, frag
);
2960 /* Link to end of symbol chain. */
2962 extern int symbol_table_frozen
;
2964 if (symbol_table_frozen
)
2968 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2970 obj_symbol_new_hook (symbolP
);
2972 #ifdef tc_symbol_new_hook
2973 tc_symbol_new_hook (symbolP
);
2977 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2978 #endif /* DEBUG_SYMS */
2983 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2986 literal_pool
* pool
;
2989 pool
= find_literal_pool ();
2991 || pool
->symbol
== NULL
2992 || pool
->next_free_entry
== 0)
2995 mapping_state (MAP_DATA
);
2997 /* Align pool as you have word accesses.
2998 Only make a frag if we have to. */
3000 frag_align (2, 0, 0);
3002 record_alignment (now_seg
, 2);
3004 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3006 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3007 (valueT
) frag_now_fix (), frag_now
);
3008 symbol_table_insert (pool
->symbol
);
3010 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3012 #if defined OBJ_COFF || defined OBJ_ELF
3013 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3016 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3017 /* First output the expression in the instruction to the pool. */
3018 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3020 /* Mark the pool as empty. */
3021 pool
->next_free_entry
= 0;
3022 pool
->symbol
= NULL
;
3026 /* Forward declarations for functions below, in the MD interface
3028 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3029 static valueT
create_unwind_entry (int);
3030 static void start_unwind_section (const segT
, int);
3031 static void add_unwind_opcode (valueT
, int);
3032 static void flush_pending_unwind (void);
3034 /* Directives: Data. */
3037 s_arm_elf_cons (int nbytes
)
3041 #ifdef md_flush_pending_output
3042 md_flush_pending_output ();
3045 if (is_it_end_of_statement ())
3047 demand_empty_rest_of_line ();
3051 #ifdef md_cons_align
3052 md_cons_align (nbytes
);
3055 mapping_state (MAP_DATA
);
3059 char *base
= input_line_pointer
;
3063 if (exp
.X_op
!= O_symbol
)
3064 emit_expr (&exp
, (unsigned int) nbytes
);
3067 char *before_reloc
= input_line_pointer
;
3068 reloc
= parse_reloc (&input_line_pointer
);
3071 as_bad (_("unrecognized relocation suffix"));
3072 ignore_rest_of_line ();
3075 else if (reloc
== BFD_RELOC_UNUSED
)
3076 emit_expr (&exp
, (unsigned int) nbytes
);
3079 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
3080 int size
= bfd_get_reloc_size (howto
);
3082 if (reloc
== BFD_RELOC_ARM_PLT32
)
3084 as_bad (_("(plt) is only valid on branch targets"));
3085 reloc
= BFD_RELOC_UNUSED
;
3090 as_bad (_("%s relocations do not fit in %d bytes"),
3091 howto
->name
, nbytes
);
3094 /* We've parsed an expression stopping at O_symbol.
3095 But there may be more expression left now that we
3096 have parsed the relocation marker. Parse it again.
3097 XXX Surely there is a cleaner way to do this. */
3098 char *p
= input_line_pointer
;
3100 char *save_buf
= alloca (input_line_pointer
- base
);
3101 memcpy (save_buf
, base
, input_line_pointer
- base
);
3102 memmove (base
+ (input_line_pointer
- before_reloc
),
3103 base
, before_reloc
- base
);
3105 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3107 memcpy (base
, save_buf
, p
- base
);
3109 offset
= nbytes
- size
;
3110 p
= frag_more ((int) nbytes
);
3111 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3112 size
, &exp
, 0, reloc
);
3117 while (*input_line_pointer
++ == ',');
3119 /* Put terminator back into stream. */
3120 input_line_pointer
--;
3121 demand_empty_rest_of_line ();
3124 /* Emit an expression containing a 32-bit thumb instruction.
3125 Implementation based on put_thumb32_insn. */
3128 emit_thumb32_expr (expressionS
* exp
)
3130 expressionS exp_high
= *exp
;
3132 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3133 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3134 exp
->X_add_number
&= 0xffff;
3135 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3138 /* Guess the instruction size based on the opcode. */
3141 thumb_insn_size (int opcode
)
3143 if ((unsigned int) opcode
< 0xe800u
)
3145 else if ((unsigned int) opcode
>= 0xe8000000u
)
3152 emit_insn (expressionS
*exp
, int nbytes
)
3156 if (exp
->X_op
== O_constant
)
3161 size
= thumb_insn_size (exp
->X_add_number
);
3165 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3167 as_bad (_(".inst.n operand too big. "\
3168 "Use .inst.w instead"));
3173 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3174 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3176 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3178 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3179 emit_thumb32_expr (exp
);
3181 emit_expr (exp
, (unsigned int) size
);
3183 it_fsm_post_encode ();
3187 as_bad (_("cannot determine Thumb instruction size. " \
3188 "Use .inst.n/.inst.w instead"));
3191 as_bad (_("constant expression required"));
3196 /* Like s_arm_elf_cons but do not use md_cons_align and
3197 set the mapping state to MAP_ARM/MAP_THUMB. */
3200 s_arm_elf_inst (int nbytes
)
3202 if (is_it_end_of_statement ())
3204 demand_empty_rest_of_line ();
3208 /* Calling mapping_state () here will not change ARM/THUMB,
3209 but will ensure not to be in DATA state. */
3212 mapping_state (MAP_THUMB
);
3217 as_bad (_("width suffixes are invalid in ARM mode"));
3218 ignore_rest_of_line ();
3224 mapping_state (MAP_ARM
);
3233 if (! emit_insn (& exp
, nbytes
))
3235 ignore_rest_of_line ();
3239 while (*input_line_pointer
++ == ',');
3241 /* Put terminator back into stream. */
3242 input_line_pointer
--;
3243 demand_empty_rest_of_line ();
3246 /* Parse a .rel31 directive. */
3249 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3256 if (*input_line_pointer
== '1')
3257 highbit
= 0x80000000;
3258 else if (*input_line_pointer
!= '0')
3259 as_bad (_("expected 0 or 1"));
3261 input_line_pointer
++;
3262 if (*input_line_pointer
!= ',')
3263 as_bad (_("missing comma"));
3264 input_line_pointer
++;
3266 #ifdef md_flush_pending_output
3267 md_flush_pending_output ();
3270 #ifdef md_cons_align
3274 mapping_state (MAP_DATA
);
3279 md_number_to_chars (p
, highbit
, 4);
3280 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3281 BFD_RELOC_ARM_PREL31
);
3283 demand_empty_rest_of_line ();
3286 /* Directives: AEABI stack-unwind tables. */
3288 /* Parse an unwind_fnstart directive. Simply records the current location. */
3291 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3293 demand_empty_rest_of_line ();
3294 if (unwind
.proc_start
)
3296 as_bad (_("duplicate .fnstart directive"));
3300 /* Mark the start of the function. */
3301 unwind
.proc_start
= expr_build_dot ();
3303 /* Reset the rest of the unwind info. */
3304 unwind
.opcode_count
= 0;
3305 unwind
.table_entry
= NULL
;
3306 unwind
.personality_routine
= NULL
;
3307 unwind
.personality_index
= -1;
3308 unwind
.frame_size
= 0;
3309 unwind
.fp_offset
= 0;
3310 unwind
.fp_reg
= REG_SP
;
3312 unwind
.sp_restored
= 0;
3316 /* Parse a handlerdata directive. Creates the exception handling table entry
3317 for the function. */
3320 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3322 demand_empty_rest_of_line ();
3323 if (!unwind
.proc_start
)
3324 as_bad (MISSING_FNSTART
);
3326 if (unwind
.table_entry
)
3327 as_bad (_("duplicate .handlerdata directive"));
3329 create_unwind_entry (1);
3332 /* Parse an unwind_fnend directive. Generates the index table entry. */
3335 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3341 demand_empty_rest_of_line ();
3343 if (!unwind
.proc_start
)
3345 as_bad (_(".fnend directive without .fnstart"));
3349 /* Add eh table entry. */
3350 if (unwind
.table_entry
== NULL
)
3351 val
= create_unwind_entry (0);
3355 /* Add index table entry. This is two words. */
3356 start_unwind_section (unwind
.saved_seg
, 1);
3357 frag_align (2, 0, 0);
3358 record_alignment (now_seg
, 2);
3360 ptr
= frag_more (8);
3361 where
= frag_now_fix () - 8;
3363 /* Self relative offset of the function start. */
3364 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3365 BFD_RELOC_ARM_PREL31
);
3367 /* Indicate dependency on EHABI-defined personality routines to the
3368 linker, if it hasn't been done already. */
3369 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3370 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3372 static const char *const name
[] =
3374 "__aeabi_unwind_cpp_pr0",
3375 "__aeabi_unwind_cpp_pr1",
3376 "__aeabi_unwind_cpp_pr2"
3378 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3379 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3380 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3381 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3382 = marked_pr_dependency
;
3386 /* Inline exception table entry. */
3387 md_number_to_chars (ptr
+ 4, val
, 4);
3389 /* Self relative offset of the table entry. */
3390 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3391 BFD_RELOC_ARM_PREL31
);
3393 /* Restore the original section. */
3394 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3396 unwind
.proc_start
= NULL
;
3400 /* Parse an unwind_cantunwind directive. */
3403 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3405 demand_empty_rest_of_line ();
3406 if (!unwind
.proc_start
)
3407 as_bad (MISSING_FNSTART
);
3409 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3410 as_bad (_("personality routine specified for cantunwind frame"));
3412 unwind
.personality_index
= -2;
3416 /* Parse a personalityindex directive. */
3419 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3423 if (!unwind
.proc_start
)
3424 as_bad (MISSING_FNSTART
);
3426 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3427 as_bad (_("duplicate .personalityindex directive"));
3431 if (exp
.X_op
!= O_constant
3432 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3434 as_bad (_("bad personality routine number"));
3435 ignore_rest_of_line ();
3439 unwind
.personality_index
= exp
.X_add_number
;
3441 demand_empty_rest_of_line ();
3445 /* Parse a personality directive. */
3448 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3452 if (!unwind
.proc_start
)
3453 as_bad (MISSING_FNSTART
);
3455 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3456 as_bad (_("duplicate .personality directive"));
3458 name
= input_line_pointer
;
3459 c
= get_symbol_end ();
3460 p
= input_line_pointer
;
3461 unwind
.personality_routine
= symbol_find_or_make (name
);
3463 demand_empty_rest_of_line ();
3467 /* Parse a directive saving core registers. */
3470 s_arm_unwind_save_core (void)
3476 range
= parse_reg_list (&input_line_pointer
);
3479 as_bad (_("expected register list"));
3480 ignore_rest_of_line ();
3484 demand_empty_rest_of_line ();
3486 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3487 into .unwind_save {..., sp...}. We aren't bothered about the value of
3488 ip because it is clobbered by calls. */
3489 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3490 && (range
& 0x3000) == 0x1000)
3492 unwind
.opcode_count
--;
3493 unwind
.sp_restored
= 0;
3494 range
= (range
| 0x2000) & ~0x1000;
3495 unwind
.pending_offset
= 0;
3501 /* See if we can use the short opcodes. These pop a block of up to 8
3502 registers starting with r4, plus maybe r14. */
3503 for (n
= 0; n
< 8; n
++)
3505 /* Break at the first non-saved register. */
3506 if ((range
& (1 << (n
+ 4))) == 0)
3509 /* See if there are any other bits set. */
3510 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3512 /* Use the long form. */
3513 op
= 0x8000 | ((range
>> 4) & 0xfff);
3514 add_unwind_opcode (op
, 2);
3518 /* Use the short form. */
3520 op
= 0xa8; /* Pop r14. */
3522 op
= 0xa0; /* Do not pop r14. */
3524 add_unwind_opcode (op
, 1);
3531 op
= 0xb100 | (range
& 0xf);
3532 add_unwind_opcode (op
, 2);
3535 /* Record the number of bytes pushed. */
3536 for (n
= 0; n
< 16; n
++)
3538 if (range
& (1 << n
))
3539 unwind
.frame_size
+= 4;
3544 /* Parse a directive saving FPA registers. */
3547 s_arm_unwind_save_fpa (int reg
)
3553 /* Get Number of registers to transfer. */
3554 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3557 exp
.X_op
= O_illegal
;
3559 if (exp
.X_op
!= O_constant
)
3561 as_bad (_("expected , <constant>"));
3562 ignore_rest_of_line ();
3566 num_regs
= exp
.X_add_number
;
3568 if (num_regs
< 1 || num_regs
> 4)
3570 as_bad (_("number of registers must be in the range [1:4]"));
3571 ignore_rest_of_line ();
3575 demand_empty_rest_of_line ();
3580 op
= 0xb4 | (num_regs
- 1);
3581 add_unwind_opcode (op
, 1);
3586 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3587 add_unwind_opcode (op
, 2);
3589 unwind
.frame_size
+= num_regs
* 12;
3593 /* Parse a directive saving VFP registers for ARMv6 and above. */
3596 s_arm_unwind_save_vfp_armv6 (void)
3601 int num_vfpv3_regs
= 0;
3602 int num_regs_below_16
;
3604 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3607 as_bad (_("expected register list"));
3608 ignore_rest_of_line ();
3612 demand_empty_rest_of_line ();
3614 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3615 than FSTMX/FLDMX-style ones). */
3617 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3619 num_vfpv3_regs
= count
;
3620 else if (start
+ count
> 16)
3621 num_vfpv3_regs
= start
+ count
- 16;
3623 if (num_vfpv3_regs
> 0)
3625 int start_offset
= start
> 16 ? start
- 16 : 0;
3626 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3627 add_unwind_opcode (op
, 2);
3630 /* Generate opcode for registers numbered in the range 0 .. 15. */
3631 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3632 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3633 if (num_regs_below_16
> 0)
3635 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3636 add_unwind_opcode (op
, 2);
3639 unwind
.frame_size
+= count
* 8;
3643 /* Parse a directive saving VFP registers for pre-ARMv6. */
3646 s_arm_unwind_save_vfp (void)
3652 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3655 as_bad (_("expected register list"));
3656 ignore_rest_of_line ();
3660 demand_empty_rest_of_line ();
3665 op
= 0xb8 | (count
- 1);
3666 add_unwind_opcode (op
, 1);
3671 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3672 add_unwind_opcode (op
, 2);
3674 unwind
.frame_size
+= count
* 8 + 4;
3678 /* Parse a directive saving iWMMXt data registers. */
3681 s_arm_unwind_save_mmxwr (void)
3689 if (*input_line_pointer
== '{')
3690 input_line_pointer
++;
3694 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3698 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3703 as_tsktsk (_("register list not in ascending order"));
3706 if (*input_line_pointer
== '-')
3708 input_line_pointer
++;
3709 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3712 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3715 else if (reg
>= hi_reg
)
3717 as_bad (_("bad register range"));
3720 for (; reg
< hi_reg
; reg
++)
3724 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3726 if (*input_line_pointer
== '}')
3727 input_line_pointer
++;
3729 demand_empty_rest_of_line ();
3731 /* Generate any deferred opcodes because we're going to be looking at
3733 flush_pending_unwind ();
3735 for (i
= 0; i
< 16; i
++)
3737 if (mask
& (1 << i
))
3738 unwind
.frame_size
+= 8;
3741 /* Attempt to combine with a previous opcode. We do this because gcc
3742 likes to output separate unwind directives for a single block of
3744 if (unwind
.opcode_count
> 0)
3746 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3747 if ((i
& 0xf8) == 0xc0)
3750 /* Only merge if the blocks are contiguous. */
3753 if ((mask
& 0xfe00) == (1 << 9))
3755 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3756 unwind
.opcode_count
--;
3759 else if (i
== 6 && unwind
.opcode_count
>= 2)
3761 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3765 op
= 0xffff << (reg
- 1);
3767 && ((mask
& op
) == (1u << (reg
- 1))))
3769 op
= (1 << (reg
+ i
+ 1)) - 1;
3770 op
&= ~((1 << reg
) - 1);
3772 unwind
.opcode_count
-= 2;
3779 /* We want to generate opcodes in the order the registers have been
3780 saved, ie. descending order. */
3781 for (reg
= 15; reg
>= -1; reg
--)
3783 /* Save registers in blocks. */
3785 || !(mask
& (1 << reg
)))
3787 /* We found an unsaved reg. Generate opcodes to save the
3794 op
= 0xc0 | (hi_reg
- 10);
3795 add_unwind_opcode (op
, 1);
3800 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3801 add_unwind_opcode (op
, 2);
3810 ignore_rest_of_line ();
3814 s_arm_unwind_save_mmxwcg (void)
3821 if (*input_line_pointer
== '{')
3822 input_line_pointer
++;
3826 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3830 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3836 as_tsktsk (_("register list not in ascending order"));
3839 if (*input_line_pointer
== '-')
3841 input_line_pointer
++;
3842 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3845 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3848 else if (reg
>= hi_reg
)
3850 as_bad (_("bad register range"));
3853 for (; reg
< hi_reg
; reg
++)
3857 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3859 if (*input_line_pointer
== '}')
3860 input_line_pointer
++;
3862 demand_empty_rest_of_line ();
3864 /* Generate any deferred opcodes because we're going to be looking at
3866 flush_pending_unwind ();
3868 for (reg
= 0; reg
< 16; reg
++)
3870 if (mask
& (1 << reg
))
3871 unwind
.frame_size
+= 4;
3874 add_unwind_opcode (op
, 2);
3877 ignore_rest_of_line ();
3881 /* Parse an unwind_save directive.
3882 If the argument is non-zero, this is a .vsave directive. */
3885 s_arm_unwind_save (int arch_v6
)
3888 struct reg_entry
*reg
;
3889 bfd_boolean had_brace
= FALSE
;
3891 if (!unwind
.proc_start
)
3892 as_bad (MISSING_FNSTART
);
3894 /* Figure out what sort of save we have. */
3895 peek
= input_line_pointer
;
3903 reg
= arm_reg_parse_multi (&peek
);
3907 as_bad (_("register expected"));
3908 ignore_rest_of_line ();
3917 as_bad (_("FPA .unwind_save does not take a register list"));
3918 ignore_rest_of_line ();
3921 input_line_pointer
= peek
;
3922 s_arm_unwind_save_fpa (reg
->number
);
3925 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3928 s_arm_unwind_save_vfp_armv6 ();
3930 s_arm_unwind_save_vfp ();
3932 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3933 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3936 as_bad (_(".unwind_save does not support this kind of register"));
3937 ignore_rest_of_line ();
3942 /* Parse an unwind_movsp directive. */
3945 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3951 if (!unwind
.proc_start
)
3952 as_bad (MISSING_FNSTART
);
3954 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3957 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
3958 ignore_rest_of_line ();
3962 /* Optional constant. */
3963 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3965 if (immediate_for_directive (&offset
) == FAIL
)
3971 demand_empty_rest_of_line ();
3973 if (reg
== REG_SP
|| reg
== REG_PC
)
3975 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3979 if (unwind
.fp_reg
!= REG_SP
)
3980 as_bad (_("unexpected .unwind_movsp directive"));
3982 /* Generate opcode to restore the value. */
3984 add_unwind_opcode (op
, 1);
3986 /* Record the information for later. */
3987 unwind
.fp_reg
= reg
;
3988 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3989 unwind
.sp_restored
= 1;
3992 /* Parse an unwind_pad directive. */
3995 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3999 if (!unwind
.proc_start
)
4000 as_bad (MISSING_FNSTART
);
4002 if (immediate_for_directive (&offset
) == FAIL
)
4007 as_bad (_("stack increment must be multiple of 4"));
4008 ignore_rest_of_line ();
4012 /* Don't generate any opcodes, just record the details for later. */
4013 unwind
.frame_size
+= offset
;
4014 unwind
.pending_offset
+= offset
;
4016 demand_empty_rest_of_line ();
4019 /* Parse an unwind_setfp directive. */
4022 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4028 if (!unwind
.proc_start
)
4029 as_bad (MISSING_FNSTART
);
4031 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4032 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4035 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4037 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4039 as_bad (_("expected <reg>, <reg>"));
4040 ignore_rest_of_line ();
4044 /* Optional constant. */
4045 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4047 if (immediate_for_directive (&offset
) == FAIL
)
4053 demand_empty_rest_of_line ();
4055 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4057 as_bad (_("register must be either sp or set by a previous"
4058 "unwind_movsp directive"));
4062 /* Don't generate any opcodes, just record the information for later. */
4063 unwind
.fp_reg
= fp_reg
;
4065 if (sp_reg
== REG_SP
)
4066 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4068 unwind
.fp_offset
-= offset
;
4071 /* Parse an unwind_raw directive. */
4074 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4077 /* This is an arbitrary limit. */
4078 unsigned char op
[16];
4081 if (!unwind
.proc_start
)
4082 as_bad (MISSING_FNSTART
);
4085 if (exp
.X_op
== O_constant
4086 && skip_past_comma (&input_line_pointer
) != FAIL
)
4088 unwind
.frame_size
+= exp
.X_add_number
;
4092 exp
.X_op
= O_illegal
;
4094 if (exp
.X_op
!= O_constant
)
4096 as_bad (_("expected <offset>, <opcode>"));
4097 ignore_rest_of_line ();
4103 /* Parse the opcode. */
4108 as_bad (_("unwind opcode too long"));
4109 ignore_rest_of_line ();
4111 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4113 as_bad (_("invalid unwind opcode"));
4114 ignore_rest_of_line ();
4117 op
[count
++] = exp
.X_add_number
;
4119 /* Parse the next byte. */
4120 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4126 /* Add the opcode bytes in reverse order. */
4128 add_unwind_opcode (op
[count
], 1);
4130 demand_empty_rest_of_line ();
4134 /* Parse a .eabi_attribute directive. */
4137 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4139 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4141 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4142 attributes_set_explicitly
[tag
] = 1;
4144 #endif /* OBJ_ELF */
4146 static void s_arm_arch (int);
4147 static void s_arm_object_arch (int);
4148 static void s_arm_cpu (int);
4149 static void s_arm_fpu (int);
4154 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4161 if (exp
.X_op
== O_symbol
)
4162 exp
.X_op
= O_secrel
;
4164 emit_expr (&exp
, 4);
4166 while (*input_line_pointer
++ == ',');
4168 input_line_pointer
--;
4169 demand_empty_rest_of_line ();
4173 /* This table describes all the machine specific pseudo-ops the assembler
4174 has to support. The fields are:
4175 pseudo-op name without dot
4176 function to call to execute this pseudo-op
4177 Integer arg to pass to the function. */
4179 const pseudo_typeS md_pseudo_table
[] =
4181 /* Never called because '.req' does not start a line. */
4182 { "req", s_req
, 0 },
4183 /* Following two are likewise never called. */
4186 { "unreq", s_unreq
, 0 },
4187 { "bss", s_bss
, 0 },
4188 { "align", s_align
, 0 },
4189 { "arm", s_arm
, 0 },
4190 { "thumb", s_thumb
, 0 },
4191 { "code", s_code
, 0 },
4192 { "force_thumb", s_force_thumb
, 0 },
4193 { "thumb_func", s_thumb_func
, 0 },
4194 { "thumb_set", s_thumb_set
, 0 },
4195 { "even", s_even
, 0 },
4196 { "ltorg", s_ltorg
, 0 },
4197 { "pool", s_ltorg
, 0 },
4198 { "syntax", s_syntax
, 0 },
4199 { "cpu", s_arm_cpu
, 0 },
4200 { "arch", s_arm_arch
, 0 },
4201 { "object_arch", s_arm_object_arch
, 0 },
4202 { "fpu", s_arm_fpu
, 0 },
4204 { "word", s_arm_elf_cons
, 4 },
4205 { "long", s_arm_elf_cons
, 4 },
4206 { "inst.n", s_arm_elf_inst
, 2 },
4207 { "inst.w", s_arm_elf_inst
, 4 },
4208 { "inst", s_arm_elf_inst
, 0 },
4209 { "rel31", s_arm_rel31
, 0 },
4210 { "fnstart", s_arm_unwind_fnstart
, 0 },
4211 { "fnend", s_arm_unwind_fnend
, 0 },
4212 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4213 { "personality", s_arm_unwind_personality
, 0 },
4214 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4215 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4216 { "save", s_arm_unwind_save
, 0 },
4217 { "vsave", s_arm_unwind_save
, 1 },
4218 { "movsp", s_arm_unwind_movsp
, 0 },
4219 { "pad", s_arm_unwind_pad
, 0 },
4220 { "setfp", s_arm_unwind_setfp
, 0 },
4221 { "unwind_raw", s_arm_unwind_raw
, 0 },
4222 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4226 /* These are used for dwarf. */
4230 /* These are used for dwarf2. */
4231 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4232 { "loc", dwarf2_directive_loc
, 0 },
4233 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4235 { "extend", float_cons
, 'x' },
4236 { "ldouble", float_cons
, 'x' },
4237 { "packed", float_cons
, 'p' },
4239 {"secrel32", pe_directive_secrel
, 0},
4244 /* Parser functions used exclusively in instruction operands. */
4246 /* Generic immediate-value read function for use in insn parsing.
4247 STR points to the beginning of the immediate (the leading #);
4248 VAL receives the value; if the value is outside [MIN, MAX]
4249 issue an error. PREFIX_OPT is true if the immediate prefix is
4253 parse_immediate (char **str
, int *val
, int min
, int max
,
4254 bfd_boolean prefix_opt
)
4257 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4258 if (exp
.X_op
!= O_constant
)
4260 inst
.error
= _("constant expression required");
4264 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4266 inst
.error
= _("immediate value out of range");
4270 *val
= exp
.X_add_number
;
4274 /* Less-generic immediate-value read function with the possibility of loading a
4275 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4276 instructions. Puts the result directly in inst.operands[i]. */
4279 parse_big_immediate (char **str
, int i
)
4284 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4286 if (exp
.X_op
== O_constant
)
4288 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4289 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4290 O_constant. We have to be careful not to break compilation for
4291 32-bit X_add_number, though. */
4292 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4294 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4295 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4296 inst
.operands
[i
].regisimm
= 1;
4299 else if (exp
.X_op
== O_big
4300 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4301 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4303 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4304 /* Bignums have their least significant bits in
4305 generic_bignum[0]. Make sure we put 32 bits in imm and
4306 32 bits in reg, in a (hopefully) portable way. */
4307 gas_assert (parts
!= 0);
4308 inst
.operands
[i
].imm
= 0;
4309 for (j
= 0; j
< parts
; j
++, idx
++)
4310 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4311 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4312 inst
.operands
[i
].reg
= 0;
4313 for (j
= 0; j
< parts
; j
++, idx
++)
4314 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4315 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4316 inst
.operands
[i
].regisimm
= 1;
4326 /* Returns the pseudo-register number of an FPA immediate constant,
4327 or FAIL if there isn't a valid constant here. */
4330 parse_fpa_immediate (char ** str
)
4332 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4338 /* First try and match exact strings, this is to guarantee
4339 that some formats will work even for cross assembly. */
4341 for (i
= 0; fp_const
[i
]; i
++)
4343 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4347 *str
+= strlen (fp_const
[i
]);
4348 if (is_end_of_line
[(unsigned char) **str
])
4354 /* Just because we didn't get a match doesn't mean that the constant
4355 isn't valid, just that it is in a format that we don't
4356 automatically recognize. Try parsing it with the standard
4357 expression routines. */
4359 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4361 /* Look for a raw floating point number. */
4362 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4363 && is_end_of_line
[(unsigned char) *save_in
])
4365 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4367 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4369 if (words
[j
] != fp_values
[i
][j
])
4373 if (j
== MAX_LITTLENUMS
)
4381 /* Try and parse a more complex expression, this will probably fail
4382 unless the code uses a floating point prefix (eg "0f"). */
4383 save_in
= input_line_pointer
;
4384 input_line_pointer
= *str
;
4385 if (expression (&exp
) == absolute_section
4386 && exp
.X_op
== O_big
4387 && exp
.X_add_number
< 0)
4389 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4391 if (gen_to_words (words
, 5, (long) 15) == 0)
4393 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4395 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4397 if (words
[j
] != fp_values
[i
][j
])
4401 if (j
== MAX_LITTLENUMS
)
4403 *str
= input_line_pointer
;
4404 input_line_pointer
= save_in
;
4411 *str
= input_line_pointer
;
4412 input_line_pointer
= save_in
;
4413 inst
.error
= _("invalid FPA immediate expression");
4417 /* Returns 1 if a number has "quarter-precision" float format
4418 0baBbbbbbc defgh000 00000000 00000000. */
4421 is_quarter_float (unsigned imm
)
4423 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4424 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4427 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4428 0baBbbbbbc defgh000 00000000 00000000.
4429 The zero and minus-zero cases need special handling, since they can't be
4430 encoded in the "quarter-precision" float format, but can nonetheless be
4431 loaded as integer constants. */
4434 parse_qfloat_immediate (char **ccp
, int *immed
)
4438 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4439 int found_fpchar
= 0;
4441 skip_past_char (&str
, '#');
4443 /* We must not accidentally parse an integer as a floating-point number. Make
4444 sure that the value we parse is not an integer by checking for special
4445 characters '.' or 'e'.
4446 FIXME: This is a horrible hack, but doing better is tricky because type
4447 information isn't in a very usable state at parse time. */
4449 skip_whitespace (fpnum
);
4451 if (strncmp (fpnum
, "0x", 2) == 0)
4455 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4456 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4466 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4468 unsigned fpword
= 0;
4471 /* Our FP word must be 32 bits (single-precision FP). */
4472 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4474 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4478 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4491 /* Shift operands. */
4494 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4497 struct asm_shift_name
4500 enum shift_kind kind
;
4503 /* Third argument to parse_shift. */
4504 enum parse_shift_mode
4506 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4507 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4508 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4509 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4510 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4513 /* Parse a <shift> specifier on an ARM data processing instruction.
4514 This has three forms:
4516 (LSL|LSR|ASL|ASR|ROR) Rs
4517 (LSL|LSR|ASL|ASR|ROR) #imm
4520 Note that ASL is assimilated to LSL in the instruction encoding, and
4521 RRX to ROR #0 (which cannot be written as such). */
4524 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4526 const struct asm_shift_name
*shift_name
;
4527 enum shift_kind shift
;
4532 for (p
= *str
; ISALPHA (*p
); p
++)
4537 inst
.error
= _("shift expression expected");
4541 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4543 if (shift_name
== NULL
)
4545 inst
.error
= _("shift expression expected");
4549 shift
= shift_name
->kind
;
4553 case NO_SHIFT_RESTRICT
:
4554 case SHIFT_IMMEDIATE
: break;
4556 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4557 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4559 inst
.error
= _("'LSL' or 'ASR' required");
4564 case SHIFT_LSL_IMMEDIATE
:
4565 if (shift
!= SHIFT_LSL
)
4567 inst
.error
= _("'LSL' required");
4572 case SHIFT_ASR_IMMEDIATE
:
4573 if (shift
!= SHIFT_ASR
)
4575 inst
.error
= _("'ASR' required");
4583 if (shift
!= SHIFT_RRX
)
4585 /* Whitespace can appear here if the next thing is a bare digit. */
4586 skip_whitespace (p
);
4588 if (mode
== NO_SHIFT_RESTRICT
4589 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4591 inst
.operands
[i
].imm
= reg
;
4592 inst
.operands
[i
].immisreg
= 1;
4594 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4597 inst
.operands
[i
].shift_kind
= shift
;
4598 inst
.operands
[i
].shifted
= 1;
4603 /* Parse a <shifter_operand> for an ARM data processing instruction:
4606 #<immediate>, <rotate>
4610 where <shift> is defined by parse_shift above, and <rotate> is a
4611 multiple of 2 between 0 and 30. Validation of immediate operands
4612 is deferred to md_apply_fix. */
4615 parse_shifter_operand (char **str
, int i
)
4620 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4622 inst
.operands
[i
].reg
= value
;
4623 inst
.operands
[i
].isreg
= 1;
4625 /* parse_shift will override this if appropriate */
4626 inst
.reloc
.exp
.X_op
= O_constant
;
4627 inst
.reloc
.exp
.X_add_number
= 0;
4629 if (skip_past_comma (str
) == FAIL
)
4632 /* Shift operation on register. */
4633 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4636 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4639 if (skip_past_comma (str
) == SUCCESS
)
4641 /* #x, y -- ie explicit rotation by Y. */
4642 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4645 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4647 inst
.error
= _("constant expression expected");
4651 value
= expr
.X_add_number
;
4652 if (value
< 0 || value
> 30 || value
% 2 != 0)
4654 inst
.error
= _("invalid rotation");
4657 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4659 inst
.error
= _("invalid constant");
4663 /* Convert to decoded value. md_apply_fix will put it back. */
4664 inst
.reloc
.exp
.X_add_number
4665 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4666 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4669 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4670 inst
.reloc
.pc_rel
= 0;
4674 /* Group relocation information. Each entry in the table contains the
4675 textual name of the relocation as may appear in assembler source
4676 and must end with a colon.
4677 Along with this textual name are the relocation codes to be used if
4678 the corresponding instruction is an ALU instruction (ADD or SUB only),
4679 an LDR, an LDRS, or an LDC. */
4681 struct group_reloc_table_entry
4692 /* Varieties of non-ALU group relocation. */
4699 static struct group_reloc_table_entry group_reloc_table
[] =
4700 { /* Program counter relative: */
4702 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4707 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4708 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4709 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4710 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4712 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4717 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4718 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4719 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4720 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4722 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4723 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4724 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4725 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4726 /* Section base relative */
4728 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4733 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4734 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4735 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4736 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4738 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4743 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4744 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4745 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4746 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4748 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4749 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4750 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4751 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4753 /* Given the address of a pointer pointing to the textual name of a group
4754 relocation as may appear in assembler source, attempt to find its details
4755 in group_reloc_table. The pointer will be updated to the character after
4756 the trailing colon. On failure, FAIL will be returned; SUCCESS
4757 otherwise. On success, *entry will be updated to point at the relevant
4758 group_reloc_table entry. */
4761 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4764 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4766 int length
= strlen (group_reloc_table
[i
].name
);
4768 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4769 && (*str
)[length
] == ':')
4771 *out
= &group_reloc_table
[i
];
4772 *str
+= (length
+ 1);
4780 /* Parse a <shifter_operand> for an ARM data processing instruction
4781 (as for parse_shifter_operand) where group relocations are allowed:
4784 #<immediate>, <rotate>
4785 #:<group_reloc>:<expression>
4789 where <group_reloc> is one of the strings defined in group_reloc_table.
4790 The hashes are optional.
4792 Everything else is as for parse_shifter_operand. */
4794 static parse_operand_result
4795 parse_shifter_operand_group_reloc (char **str
, int i
)
4797 /* Determine if we have the sequence of characters #: or just :
4798 coming next. If we do, then we check for a group relocation.
4799 If we don't, punt the whole lot to parse_shifter_operand. */
4801 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4802 || (*str
)[0] == ':')
4804 struct group_reloc_table_entry
*entry
;
4806 if ((*str
)[0] == '#')
4811 /* Try to parse a group relocation. Anything else is an error. */
4812 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4814 inst
.error
= _("unknown group relocation");
4815 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4818 /* We now have the group relocation table entry corresponding to
4819 the name in the assembler source. Next, we parse the expression. */
4820 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4821 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4823 /* Record the relocation type (always the ALU variant here). */
4824 inst
.reloc
.type
= entry
->alu_code
;
4825 gas_assert (inst
.reloc
.type
!= 0);
4827 return PARSE_OPERAND_SUCCESS
;
4830 return parse_shifter_operand (str
, i
) == SUCCESS
4831 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4833 /* Never reached. */
4836 /* Parse all forms of an ARM address expression. Information is written
4837 to inst.operands[i] and/or inst.reloc.
4839 Preindexed addressing (.preind=1):
4841 [Rn, #offset] .reg=Rn .reloc.exp=offset
4842 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4843 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4844 .shift_kind=shift .reloc.exp=shift_imm
4846 These three may have a trailing ! which causes .writeback to be set also.
4848 Postindexed addressing (.postind=1, .writeback=1):
4850 [Rn], #offset .reg=Rn .reloc.exp=offset
4851 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4852 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4853 .shift_kind=shift .reloc.exp=shift_imm
4855 Unindexed addressing (.preind=0, .postind=0):
4857 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4861 [Rn]{!} shorthand for [Rn,#0]{!}
4862 =immediate .isreg=0 .reloc.exp=immediate
4863 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4865 It is the caller's responsibility to check for addressing modes not
4866 supported by the instruction, and to set inst.reloc.type. */
4868 static parse_operand_result
4869 parse_address_main (char **str
, int i
, int group_relocations
,
4870 group_reloc_type group_type
)
4875 if (skip_past_char (&p
, '[') == FAIL
)
4877 if (skip_past_char (&p
, '=') == FAIL
)
4879 /* bare address - translate to PC-relative offset */
4880 inst
.reloc
.pc_rel
= 1;
4881 inst
.operands
[i
].reg
= REG_PC
;
4882 inst
.operands
[i
].isreg
= 1;
4883 inst
.operands
[i
].preind
= 1;
4885 /* else a load-constant pseudo op, no special treatment needed here */
4887 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4888 return PARSE_OPERAND_FAIL
;
4891 return PARSE_OPERAND_SUCCESS
;
4894 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4896 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4897 return PARSE_OPERAND_FAIL
;
4899 inst
.operands
[i
].reg
= reg
;
4900 inst
.operands
[i
].isreg
= 1;
4902 if (skip_past_comma (&p
) == SUCCESS
)
4904 inst
.operands
[i
].preind
= 1;
4907 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4909 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4911 inst
.operands
[i
].imm
= reg
;
4912 inst
.operands
[i
].immisreg
= 1;
4914 if (skip_past_comma (&p
) == SUCCESS
)
4915 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4916 return PARSE_OPERAND_FAIL
;
4918 else if (skip_past_char (&p
, ':') == SUCCESS
)
4920 /* FIXME: '@' should be used here, but it's filtered out by generic
4921 code before we get to see it here. This may be subject to
4924 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4925 if (exp
.X_op
!= O_constant
)
4927 inst
.error
= _("alignment must be constant");
4928 return PARSE_OPERAND_FAIL
;
4930 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4931 inst
.operands
[i
].immisalign
= 1;
4932 /* Alignments are not pre-indexes. */
4933 inst
.operands
[i
].preind
= 0;
4937 if (inst
.operands
[i
].negative
)
4939 inst
.operands
[i
].negative
= 0;
4943 if (group_relocations
4944 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4946 struct group_reloc_table_entry
*entry
;
4948 /* Skip over the #: or : sequence. */
4954 /* Try to parse a group relocation. Anything else is an
4956 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4958 inst
.error
= _("unknown group relocation");
4959 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4962 /* We now have the group relocation table entry corresponding to
4963 the name in the assembler source. Next, we parse the
4965 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4966 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4968 /* Record the relocation type. */
4972 inst
.reloc
.type
= entry
->ldr_code
;
4976 inst
.reloc
.type
= entry
->ldrs_code
;
4980 inst
.reloc
.type
= entry
->ldc_code
;
4987 if (inst
.reloc
.type
== 0)
4989 inst
.error
= _("this group relocation is not allowed on this instruction");
4990 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4994 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4995 return PARSE_OPERAND_FAIL
;
4999 if (skip_past_char (&p
, ']') == FAIL
)
5001 inst
.error
= _("']' expected");
5002 return PARSE_OPERAND_FAIL
;
5005 if (skip_past_char (&p
, '!') == SUCCESS
)
5006 inst
.operands
[i
].writeback
= 1;
5008 else if (skip_past_comma (&p
) == SUCCESS
)
5010 if (skip_past_char (&p
, '{') == SUCCESS
)
5012 /* [Rn], {expr} - unindexed, with option */
5013 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5014 0, 255, TRUE
) == FAIL
)
5015 return PARSE_OPERAND_FAIL
;
5017 if (skip_past_char (&p
, '}') == FAIL
)
5019 inst
.error
= _("'}' expected at end of 'option' field");
5020 return PARSE_OPERAND_FAIL
;
5022 if (inst
.operands
[i
].preind
)
5024 inst
.error
= _("cannot combine index with option");
5025 return PARSE_OPERAND_FAIL
;
5028 return PARSE_OPERAND_SUCCESS
;
5032 inst
.operands
[i
].postind
= 1;
5033 inst
.operands
[i
].writeback
= 1;
5035 if (inst
.operands
[i
].preind
)
5037 inst
.error
= _("cannot combine pre- and post-indexing");
5038 return PARSE_OPERAND_FAIL
;
5042 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5044 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5046 /* We might be using the immediate for alignment already. If we
5047 are, OR the register number into the low-order bits. */
5048 if (inst
.operands
[i
].immisalign
)
5049 inst
.operands
[i
].imm
|= reg
;
5051 inst
.operands
[i
].imm
= reg
;
5052 inst
.operands
[i
].immisreg
= 1;
5054 if (skip_past_comma (&p
) == SUCCESS
)
5055 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5056 return PARSE_OPERAND_FAIL
;
5060 if (inst
.operands
[i
].negative
)
5062 inst
.operands
[i
].negative
= 0;
5065 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5066 return PARSE_OPERAND_FAIL
;
5071 /* If at this point neither .preind nor .postind is set, we have a
5072 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5073 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5075 inst
.operands
[i
].preind
= 1;
5076 inst
.reloc
.exp
.X_op
= O_constant
;
5077 inst
.reloc
.exp
.X_add_number
= 0;
5080 return PARSE_OPERAND_SUCCESS
;
5084 parse_address (char **str
, int i
)
5086 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
5090 static parse_operand_result
5091 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5093 return parse_address_main (str
, i
, 1, type
);
5096 /* Parse an operand for a MOVW or MOVT instruction. */
5098 parse_half (char **str
)
5103 skip_past_char (&p
, '#');
5104 if (strncasecmp (p
, ":lower16:", 9) == 0)
5105 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5106 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5107 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5109 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5112 skip_whitespace (p
);
5115 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5118 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5120 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5122 inst
.error
= _("constant expression expected");
5125 if (inst
.reloc
.exp
.X_add_number
< 0
5126 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5128 inst
.error
= _("immediate value out of range");
5136 /* Miscellaneous. */
5138 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5139 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5141 parse_psr (char **str
)
5144 unsigned long psr_field
;
5145 const struct asm_psr
*psr
;
5148 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5149 feature for ease of use and backwards compatibility. */
5151 if (strncasecmp (p
, "SPSR", 4) == 0)
5152 psr_field
= SPSR_BIT
;
5153 else if (strncasecmp (p
, "CPSR", 4) == 0)
5160 while (ISALNUM (*p
) || *p
== '_');
5162 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
5173 /* A suffix follows. */
5179 while (ISALNUM (*p
) || *p
== '_');
5181 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
5185 psr_field
|= psr
->field
;
5190 goto error
; /* Garbage after "[CS]PSR". */
5192 psr_field
|= (PSR_c
| PSR_f
);
5198 inst
.error
= _("flag for {c}psr instruction expected");
5202 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5203 value suitable for splatting into the AIF field of the instruction. */
5206 parse_cps_flags (char **str
)
5215 case '\0': case ',':
5218 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5219 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5220 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5223 inst
.error
= _("unrecognized CPS flag");
5228 if (saw_a_flag
== 0)
5230 inst
.error
= _("missing CPS flags");
5238 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5239 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5242 parse_endian_specifier (char **str
)
5247 if (strncasecmp (s
, "BE", 2))
5249 else if (strncasecmp (s
, "LE", 2))
5253 inst
.error
= _("valid endian specifiers are be or le");
5257 if (ISALNUM (s
[2]) || s
[2] == '_')
5259 inst
.error
= _("valid endian specifiers are be or le");
5264 return little_endian
;
5267 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5268 value suitable for poking into the rotate field of an sxt or sxta
5269 instruction, or FAIL on error. */
5272 parse_ror (char **str
)
5277 if (strncasecmp (s
, "ROR", 3) == 0)
5281 inst
.error
= _("missing rotation field after comma");
5285 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5290 case 0: *str
= s
; return 0x0;
5291 case 8: *str
= s
; return 0x1;
5292 case 16: *str
= s
; return 0x2;
5293 case 24: *str
= s
; return 0x3;
5296 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5301 /* Parse a conditional code (from conds[] below). The value returned is in the
5302 range 0 .. 14, or FAIL. */
5304 parse_cond (char **str
)
5307 const struct asm_cond
*c
;
5309 /* Condition codes are always 2 characters, so matching up to
5310 3 characters is sufficient. */
5315 while (ISALPHA (*q
) && n
< 3)
5317 cond
[n
] = TOLOWER (*q
);
5322 c
= hash_find_n (arm_cond_hsh
, cond
, n
);
5325 inst
.error
= _("condition required");
5333 /* Parse an option for a barrier instruction. Returns the encoding for the
5336 parse_barrier (char **str
)
5339 const struct asm_barrier_opt
*o
;
5342 while (ISALPHA (*q
))
5345 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5353 /* Parse the operands of a table branch instruction. Similar to a memory
5356 parse_tb (char **str
)
5361 if (skip_past_char (&p
, '[') == FAIL
)
5363 inst
.error
= _("'[' expected");
5367 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5369 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5372 inst
.operands
[0].reg
= reg
;
5374 if (skip_past_comma (&p
) == FAIL
)
5376 inst
.error
= _("',' expected");
5380 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5382 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5385 inst
.operands
[0].imm
= reg
;
5387 if (skip_past_comma (&p
) == SUCCESS
)
5389 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5391 if (inst
.reloc
.exp
.X_add_number
!= 1)
5393 inst
.error
= _("invalid shift");
5396 inst
.operands
[0].shifted
= 1;
5399 if (skip_past_char (&p
, ']') == FAIL
)
5401 inst
.error
= _("']' expected");
5408 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5409 information on the types the operands can take and how they are encoded.
5410 Up to four operands may be read; this function handles setting the
5411 ".present" field for each read operand itself.
5412 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5413 else returns FAIL. */
5416 parse_neon_mov (char **str
, int *which_operand
)
5418 int i
= *which_operand
, val
;
5419 enum arm_reg_type rtype
;
5421 struct neon_type_el optype
;
5423 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5425 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5426 inst
.operands
[i
].reg
= val
;
5427 inst
.operands
[i
].isscalar
= 1;
5428 inst
.operands
[i
].vectype
= optype
;
5429 inst
.operands
[i
++].present
= 1;
5431 if (skip_past_comma (&ptr
) == FAIL
)
5434 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5437 inst
.operands
[i
].reg
= val
;
5438 inst
.operands
[i
].isreg
= 1;
5439 inst
.operands
[i
].present
= 1;
5441 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5444 /* Cases 0, 1, 2, 3, 5 (D only). */
5445 if (skip_past_comma (&ptr
) == FAIL
)
5448 inst
.operands
[i
].reg
= val
;
5449 inst
.operands
[i
].isreg
= 1;
5450 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5451 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5452 inst
.operands
[i
].isvec
= 1;
5453 inst
.operands
[i
].vectype
= optype
;
5454 inst
.operands
[i
++].present
= 1;
5456 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5458 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5459 Case 13: VMOV <Sd>, <Rm> */
5460 inst
.operands
[i
].reg
= val
;
5461 inst
.operands
[i
].isreg
= 1;
5462 inst
.operands
[i
].present
= 1;
5464 if (rtype
== REG_TYPE_NQ
)
5466 first_error (_("can't use Neon quad register here"));
5469 else if (rtype
!= REG_TYPE_VFS
)
5472 if (skip_past_comma (&ptr
) == FAIL
)
5474 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5476 inst
.operands
[i
].reg
= val
;
5477 inst
.operands
[i
].isreg
= 1;
5478 inst
.operands
[i
].present
= 1;
5481 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5484 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5485 Case 1: VMOV<c><q> <Dd>, <Dm>
5486 Case 8: VMOV.F32 <Sd>, <Sm>
5487 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5489 inst
.operands
[i
].reg
= val
;
5490 inst
.operands
[i
].isreg
= 1;
5491 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5492 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5493 inst
.operands
[i
].isvec
= 1;
5494 inst
.operands
[i
].vectype
= optype
;
5495 inst
.operands
[i
].present
= 1;
5497 if (skip_past_comma (&ptr
) == SUCCESS
)
5502 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5505 inst
.operands
[i
].reg
= val
;
5506 inst
.operands
[i
].isreg
= 1;
5507 inst
.operands
[i
++].present
= 1;
5509 if (skip_past_comma (&ptr
) == FAIL
)
5512 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5515 inst
.operands
[i
].reg
= val
;
5516 inst
.operands
[i
].isreg
= 1;
5517 inst
.operands
[i
++].present
= 1;
5520 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5521 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5522 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5523 Case 10: VMOV.F32 <Sd>, #<imm>
5524 Case 11: VMOV.F64 <Dd>, #<imm> */
5525 inst
.operands
[i
].immisfloat
= 1;
5526 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5527 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5528 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5532 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5536 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5539 inst
.operands
[i
].reg
= val
;
5540 inst
.operands
[i
].isreg
= 1;
5541 inst
.operands
[i
++].present
= 1;
5543 if (skip_past_comma (&ptr
) == FAIL
)
5546 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5548 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5549 inst
.operands
[i
].reg
= val
;
5550 inst
.operands
[i
].isscalar
= 1;
5551 inst
.operands
[i
].present
= 1;
5552 inst
.operands
[i
].vectype
= optype
;
5554 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5556 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5557 inst
.operands
[i
].reg
= val
;
5558 inst
.operands
[i
].isreg
= 1;
5559 inst
.operands
[i
++].present
= 1;
5561 if (skip_past_comma (&ptr
) == FAIL
)
5564 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5567 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5571 inst
.operands
[i
].reg
= val
;
5572 inst
.operands
[i
].isreg
= 1;
5573 inst
.operands
[i
].isvec
= 1;
5574 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5575 inst
.operands
[i
].vectype
= optype
;
5576 inst
.operands
[i
].present
= 1;
5578 if (rtype
== REG_TYPE_VFS
)
5582 if (skip_past_comma (&ptr
) == FAIL
)
5584 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5587 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5590 inst
.operands
[i
].reg
= val
;
5591 inst
.operands
[i
].isreg
= 1;
5592 inst
.operands
[i
].isvec
= 1;
5593 inst
.operands
[i
].issingle
= 1;
5594 inst
.operands
[i
].vectype
= optype
;
5595 inst
.operands
[i
].present
= 1;
5598 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5602 inst
.operands
[i
].reg
= val
;
5603 inst
.operands
[i
].isreg
= 1;
5604 inst
.operands
[i
].isvec
= 1;
5605 inst
.operands
[i
].issingle
= 1;
5606 inst
.operands
[i
].vectype
= optype
;
5607 inst
.operands
[i
++].present
= 1;
5612 first_error (_("parse error"));
5616 /* Successfully parsed the operands. Update args. */
5622 first_error (_("expected comma"));
5626 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5630 /* Matcher codes for parse_operands. */
5631 enum operand_parse_code
5633 OP_stop
, /* end of line */
5635 OP_RR
, /* ARM register */
5636 OP_RRnpc
, /* ARM register, not r15 */
5637 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5638 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5639 OP_RCP
, /* Coprocessor number */
5640 OP_RCN
, /* Coprocessor register */
5641 OP_RF
, /* FPA register */
5642 OP_RVS
, /* VFP single precision register */
5643 OP_RVD
, /* VFP double precision register (0..15) */
5644 OP_RND
, /* Neon double precision register (0..31) */
5645 OP_RNQ
, /* Neon quad precision register */
5646 OP_RVSD
, /* VFP single or double precision register */
5647 OP_RNDQ
, /* Neon double or quad precision register */
5648 OP_RNSDQ
, /* Neon single, double or quad precision register */
5649 OP_RNSC
, /* Neon scalar D[X] */
5650 OP_RVC
, /* VFP control register */
5651 OP_RMF
, /* Maverick F register */
5652 OP_RMD
, /* Maverick D register */
5653 OP_RMFX
, /* Maverick FX register */
5654 OP_RMDX
, /* Maverick DX register */
5655 OP_RMAX
, /* Maverick AX register */
5656 OP_RMDS
, /* Maverick DSPSC register */
5657 OP_RIWR
, /* iWMMXt wR register */
5658 OP_RIWC
, /* iWMMXt wC register */
5659 OP_RIWG
, /* iWMMXt wCG register */
5660 OP_RXA
, /* XScale accumulator register */
5662 OP_REGLST
, /* ARM register list */
5663 OP_VRSLST
, /* VFP single-precision register list */
5664 OP_VRDLST
, /* VFP double-precision register list */
5665 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5666 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5667 OP_NSTRLST
, /* Neon element/structure list */
5669 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5670 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5671 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5672 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5673 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5674 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5675 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5676 OP_VMOV
, /* Neon VMOV operands. */
5677 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5678 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5679 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5681 OP_I0
, /* immediate zero */
5682 OP_I7
, /* immediate value 0 .. 7 */
5683 OP_I15
, /* 0 .. 15 */
5684 OP_I16
, /* 1 .. 16 */
5685 OP_I16z
, /* 0 .. 16 */
5686 OP_I31
, /* 0 .. 31 */
5687 OP_I31w
, /* 0 .. 31, optional trailing ! */
5688 OP_I32
, /* 1 .. 32 */
5689 OP_I32z
, /* 0 .. 32 */
5690 OP_I63
, /* 0 .. 63 */
5691 OP_I63s
, /* -64 .. 63 */
5692 OP_I64
, /* 1 .. 64 */
5693 OP_I64z
, /* 0 .. 64 */
5694 OP_I255
, /* 0 .. 255 */
5696 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5697 OP_I7b
, /* 0 .. 7 */
5698 OP_I15b
, /* 0 .. 15 */
5699 OP_I31b
, /* 0 .. 31 */
5701 OP_SH
, /* shifter operand */
5702 OP_SHG
, /* shifter operand with possible group relocation */
5703 OP_ADDR
, /* Memory address expression (any mode) */
5704 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5705 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5706 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5707 OP_EXP
, /* arbitrary expression */
5708 OP_EXPi
, /* same, with optional immediate prefix */
5709 OP_EXPr
, /* same, with optional relocation suffix */
5710 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5712 OP_CPSF
, /* CPS flags */
5713 OP_ENDI
, /* Endianness specifier */
5714 OP_PSR
, /* CPSR/SPSR mask for msr */
5715 OP_COND
, /* conditional code */
5716 OP_TB
, /* Table branch. */
5718 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5719 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5721 OP_RRnpc_I0
, /* ARM register or literal 0 */
5722 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5723 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5724 OP_RF_IF
, /* FPA register or immediate */
5725 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5726 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5728 /* Optional operands. */
5729 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5730 OP_oI31b
, /* 0 .. 31 */
5731 OP_oI32b
, /* 1 .. 32 */
5732 OP_oIffffb
, /* 0 .. 65535 */
5733 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5735 OP_oRR
, /* ARM register */
5736 OP_oRRnpc
, /* ARM register, not the PC */
5737 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5738 OP_oRND
, /* Optional Neon double precision register */
5739 OP_oRNQ
, /* Optional Neon quad precision register */
5740 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5741 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5742 OP_oSHll
, /* LSL immediate */
5743 OP_oSHar
, /* ASR immediate */
5744 OP_oSHllar
, /* LSL or ASR immediate */
5745 OP_oROR
, /* ROR 0/8/16/24 */
5746 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5748 OP_FIRST_OPTIONAL
= OP_oI7b
5751 /* Generic instruction operand parser. This does no encoding and no
5752 semantic validation; it merely squirrels values away in the inst
5753 structure. Returns SUCCESS or FAIL depending on whether the
5754 specified grammar matched. */
5756 parse_operands (char *str
, const unsigned char *pattern
)
5758 unsigned const char *upat
= pattern
;
5759 char *backtrack_pos
= 0;
5760 const char *backtrack_error
= 0;
5761 int i
, val
, backtrack_index
= 0;
5762 enum arm_reg_type rtype
;
5763 parse_operand_result result
;
5765 #define po_char_or_fail(chr) \
5768 if (skip_past_char (&str, chr) == FAIL) \
5773 #define po_reg_or_fail(regtype) \
5776 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5777 & inst.operands[i].vectype); \
5780 first_error (_(reg_expected_msgs[regtype])); \
5783 inst.operands[i].reg = val; \
5784 inst.operands[i].isreg = 1; \
5785 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5786 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5787 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5788 || rtype == REG_TYPE_VFD \
5789 || rtype == REG_TYPE_NQ); \
5793 #define po_reg_or_goto(regtype, label) \
5796 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5797 & inst.operands[i].vectype); \
5801 inst.operands[i].reg = val; \
5802 inst.operands[i].isreg = 1; \
5803 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5804 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5805 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5806 || rtype == REG_TYPE_VFD \
5807 || rtype == REG_TYPE_NQ); \
5811 #define po_imm_or_fail(min, max, popt) \
5814 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5816 inst.operands[i].imm = val; \
5820 #define po_scalar_or_goto(elsz, label) \
5823 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5826 inst.operands[i].reg = val; \
5827 inst.operands[i].isscalar = 1; \
5831 #define po_misc_or_fail(expr) \
5839 #define po_misc_or_fail_no_backtrack(expr) \
5843 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
5844 backtrack_pos = 0; \
5845 if (result != PARSE_OPERAND_SUCCESS) \
5850 skip_whitespace (str
);
5852 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5854 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5856 /* Remember where we are in case we need to backtrack. */
5857 gas_assert (!backtrack_pos
);
5858 backtrack_pos
= str
;
5859 backtrack_error
= inst
.error
;
5860 backtrack_index
= i
;
5863 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5864 po_char_or_fail (',');
5872 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5873 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5874 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5875 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5876 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5877 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5879 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5881 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5883 /* Also accept generic coprocessor regs for unknown registers. */
5885 po_reg_or_fail (REG_TYPE_CN
);
5887 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5888 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5889 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5890 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5891 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5892 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5893 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5894 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5895 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5896 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5898 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5900 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5901 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5903 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5905 /* Neon scalar. Using an element size of 8 means that some invalid
5906 scalars are accepted here, so deal with those in later code. */
5907 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5909 /* WARNING: We can expand to two operands here. This has the potential
5910 to totally confuse the backtracking mechanism! It will be OK at
5911 least as long as we don't try to use optional args as well,
5915 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5916 inst
.operands
[i
].present
= 1;
5918 skip_past_comma (&str
);
5919 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5922 /* Optional register operand was omitted. Unfortunately, it's in
5923 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5924 here (this is a bit grotty). */
5925 inst
.operands
[i
] = inst
.operands
[i
-1];
5926 inst
.operands
[i
-1].present
= 0;
5929 /* There's a possibility of getting a 64-bit immediate here, so
5930 we need special handling. */
5931 if (parse_big_immediate (&str
, i
) == FAIL
)
5933 inst
.error
= _("immediate value is out of range");
5941 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5944 po_imm_or_fail (0, 0, TRUE
);
5949 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5954 po_scalar_or_goto (8, try_rr
);
5957 po_reg_or_fail (REG_TYPE_RN
);
5963 po_scalar_or_goto (8, try_nsdq
);
5966 po_reg_or_fail (REG_TYPE_NSDQ
);
5972 po_scalar_or_goto (8, try_ndq
);
5975 po_reg_or_fail (REG_TYPE_NDQ
);
5981 po_scalar_or_goto (8, try_vfd
);
5984 po_reg_or_fail (REG_TYPE_VFD
);
5989 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5990 not careful then bad things might happen. */
5991 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5996 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5999 /* There's a possibility of getting a 64-bit immediate here, so
6000 we need special handling. */
6001 if (parse_big_immediate (&str
, i
) == FAIL
)
6003 inst
.error
= _("immediate value is out of range");
6011 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6014 po_imm_or_fail (0, 63, TRUE
);
6019 po_char_or_fail ('[');
6020 po_reg_or_fail (REG_TYPE_RN
);
6021 po_char_or_fail (']');
6026 po_reg_or_fail (REG_TYPE_RN
);
6027 if (skip_past_char (&str
, '!') == SUCCESS
)
6028 inst
.operands
[i
].writeback
= 1;
6032 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6033 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6034 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6035 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6036 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6037 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6038 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6039 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6040 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6041 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6042 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6043 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6045 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6047 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6048 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6050 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6051 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6052 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6054 /* Immediate variants */
6056 po_char_or_fail ('{');
6057 po_imm_or_fail (0, 255, TRUE
);
6058 po_char_or_fail ('}');
6062 /* The expression parser chokes on a trailing !, so we have
6063 to find it first and zap it. */
6066 while (*s
&& *s
!= ',')
6071 inst
.operands
[i
].writeback
= 1;
6073 po_imm_or_fail (0, 31, TRUE
);
6081 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6086 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6091 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6093 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6095 val
= parse_reloc (&str
);
6098 inst
.error
= _("unrecognized relocation suffix");
6101 else if (val
!= BFD_RELOC_UNUSED
)
6103 inst
.operands
[i
].imm
= val
;
6104 inst
.operands
[i
].hasreloc
= 1;
6109 /* Operand for MOVW or MOVT. */
6111 po_misc_or_fail (parse_half (&str
));
6114 /* Register or expression. */
6115 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6116 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6118 /* Register or immediate. */
6119 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6120 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6122 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6124 if (!is_immediate_prefix (*str
))
6127 val
= parse_fpa_immediate (&str
);
6130 /* FPA immediates are encoded as registers 8-15.
6131 parse_fpa_immediate has already applied the offset. */
6132 inst
.operands
[i
].reg
= val
;
6133 inst
.operands
[i
].isreg
= 1;
6136 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6137 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6139 /* Two kinds of register. */
6142 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6144 || (rege
->type
!= REG_TYPE_MMXWR
6145 && rege
->type
!= REG_TYPE_MMXWC
6146 && rege
->type
!= REG_TYPE_MMXWCG
))
6148 inst
.error
= _("iWMMXt data or control register expected");
6151 inst
.operands
[i
].reg
= rege
->number
;
6152 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6158 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6160 || (rege
->type
!= REG_TYPE_MMXWC
6161 && rege
->type
!= REG_TYPE_MMXWCG
))
6163 inst
.error
= _("iWMMXt control register expected");
6166 inst
.operands
[i
].reg
= rege
->number
;
6167 inst
.operands
[i
].isreg
= 1;
6172 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6173 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6174 case OP_oROR
: val
= parse_ror (&str
); break;
6175 case OP_PSR
: val
= parse_psr (&str
); break;
6176 case OP_COND
: val
= parse_cond (&str
); break;
6177 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
6180 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6181 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6184 val
= parse_psr (&str
);
6188 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6191 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6193 if (strncasecmp (str
, "APSR_", 5) == 0)
6200 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6201 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6202 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6203 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6204 default: found
= 16;
6208 inst
.operands
[i
].isvec
= 1;
6215 po_misc_or_fail (parse_tb (&str
));
6218 /* Register lists. */
6220 val
= parse_reg_list (&str
);
6223 inst
.operands
[1].writeback
= 1;
6229 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6233 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6237 /* Allow Q registers too. */
6238 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6243 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6245 inst
.operands
[i
].issingle
= 1;
6250 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6255 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6256 &inst
.operands
[i
].vectype
);
6259 /* Addressing modes */
6261 po_misc_or_fail (parse_address (&str
, i
));
6265 po_misc_or_fail_no_backtrack (
6266 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6270 po_misc_or_fail_no_backtrack (
6271 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6275 po_misc_or_fail_no_backtrack (
6276 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6280 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6284 po_misc_or_fail_no_backtrack (
6285 parse_shifter_operand_group_reloc (&str
, i
));
6289 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6293 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6297 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6301 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6304 /* Various value-based sanity checks and shared operations. We
6305 do not signal immediate failures for the register constraints;
6306 this allows a syntax error to take precedence. */
6315 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6316 inst
.error
= BAD_PC
;
6334 inst
.operands
[i
].imm
= val
;
6341 /* If we get here, this operand was successfully parsed. */
6342 inst
.operands
[i
].present
= 1;
6346 inst
.error
= BAD_ARGS
;
6351 /* The parse routine should already have set inst.error, but set a
6352 default here just in case. */
6354 inst
.error
= _("syntax error");
6358 /* Do not backtrack over a trailing optional argument that
6359 absorbed some text. We will only fail again, with the
6360 'garbage following instruction' error message, which is
6361 probably less helpful than the current one. */
6362 if (backtrack_index
== i
&& backtrack_pos
!= str
6363 && upat
[i
+1] == OP_stop
)
6366 inst
.error
= _("syntax error");
6370 /* Try again, skipping the optional argument at backtrack_pos. */
6371 str
= backtrack_pos
;
6372 inst
.error
= backtrack_error
;
6373 inst
.operands
[backtrack_index
].present
= 0;
6374 i
= backtrack_index
;
6378 /* Check that we have parsed all the arguments. */
6379 if (*str
!= '\0' && !inst
.error
)
6380 inst
.error
= _("garbage following instruction");
6382 return inst
.error
? FAIL
: SUCCESS
;
6385 #undef po_char_or_fail
6386 #undef po_reg_or_fail
6387 #undef po_reg_or_goto
6388 #undef po_imm_or_fail
6389 #undef po_scalar_or_fail
6391 /* Shorthand macro for instruction encoding functions issuing errors. */
6392 #define constraint(expr, err) \
6403 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6404 instructions are unpredictable if these registers are used. This
6405 is the BadReg predicate in ARM's Thumb-2 documentation. */
6406 #define reject_bad_reg(reg) \
6408 if (reg == REG_SP || reg == REG_PC) \
6410 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6415 /* If REG is R13 (the stack pointer), warn that its use is
6417 #define warn_deprecated_sp(reg) \
6419 if (warn_on_deprecated && reg == REG_SP) \
6420 as_warn (_("use of r13 is deprecated")); \
6423 /* Functions for operand encoding. ARM, then Thumb. */
6425 #define rotate_left(v, n) (v << n | v >> (32 - n))
6427 /* If VAL can be encoded in the immediate field of an ARM instruction,
6428 return the encoded form. Otherwise, return FAIL. */
6431 encode_arm_immediate (unsigned int val
)
6435 for (i
= 0; i
< 32; i
+= 2)
6436 if ((a
= rotate_left (val
, i
)) <= 0xff)
6437 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6442 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6443 return the encoded form. Otherwise, return FAIL. */
6445 encode_thumb32_immediate (unsigned int val
)
6452 for (i
= 1; i
<= 24; i
++)
6455 if ((val
& ~(0xff << i
)) == 0)
6456 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6460 if (val
== ((a
<< 16) | a
))
6462 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6466 if (val
== ((a
<< 16) | a
))
6467 return 0x200 | (a
>> 8);
6471 /* Encode a VFP SP or DP register number into inst.instruction. */
6474 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6476 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6479 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6482 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6485 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6490 first_error (_("D register out of range for selected VFP version"));
6498 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6502 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6506 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6510 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6514 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6518 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6526 /* Encode a <shift> in an ARM-format instruction. The immediate,
6527 if any, is handled by md_apply_fix. */
6529 encode_arm_shift (int i
)
6531 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6532 inst
.instruction
|= SHIFT_ROR
<< 5;
6535 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6536 if (inst
.operands
[i
].immisreg
)
6538 inst
.instruction
|= SHIFT_BY_REG
;
6539 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6542 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6547 encode_arm_shifter_operand (int i
)
6549 if (inst
.operands
[i
].isreg
)
6551 inst
.instruction
|= inst
.operands
[i
].reg
;
6552 encode_arm_shift (i
);
6555 inst
.instruction
|= INST_IMMEDIATE
;
6558 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6560 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6562 gas_assert (inst
.operands
[i
].isreg
);
6563 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6565 if (inst
.operands
[i
].preind
)
6569 inst
.error
= _("instruction does not accept preindexed addressing");
6572 inst
.instruction
|= PRE_INDEX
;
6573 if (inst
.operands
[i
].writeback
)
6574 inst
.instruction
|= WRITE_BACK
;
6577 else if (inst
.operands
[i
].postind
)
6579 gas_assert (inst
.operands
[i
].writeback
);
6581 inst
.instruction
|= WRITE_BACK
;
6583 else /* unindexed - only for coprocessor */
6585 inst
.error
= _("instruction does not accept unindexed addressing");
6589 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6590 && (((inst
.instruction
& 0x000f0000) >> 16)
6591 == ((inst
.instruction
& 0x0000f000) >> 12)))
6592 as_warn ((inst
.instruction
& LOAD_BIT
)
6593 ? _("destination register same as write-back base")
6594 : _("source register same as write-back base"));
6597 /* inst.operands[i] was set up by parse_address. Encode it into an
6598 ARM-format mode 2 load or store instruction. If is_t is true,
6599 reject forms that cannot be used with a T instruction (i.e. not
6602 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6604 encode_arm_addr_mode_common (i
, is_t
);
6606 if (inst
.operands
[i
].immisreg
)
6608 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6609 inst
.instruction
|= inst
.operands
[i
].imm
;
6610 if (!inst
.operands
[i
].negative
)
6611 inst
.instruction
|= INDEX_UP
;
6612 if (inst
.operands
[i
].shifted
)
6614 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6615 inst
.instruction
|= SHIFT_ROR
<< 5;
6618 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6619 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6623 else /* immediate offset in inst.reloc */
6625 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6626 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6630 /* inst.operands[i] was set up by parse_address. Encode it into an
6631 ARM-format mode 3 load or store instruction. Reject forms that
6632 cannot be used with such instructions. If is_t is true, reject
6633 forms that cannot be used with a T instruction (i.e. not
6636 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6638 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6640 inst
.error
= _("instruction does not accept scaled register index");
6644 encode_arm_addr_mode_common (i
, is_t
);
6646 if (inst
.operands
[i
].immisreg
)
6648 inst
.instruction
|= inst
.operands
[i
].imm
;
6649 if (!inst
.operands
[i
].negative
)
6650 inst
.instruction
|= INDEX_UP
;
6652 else /* immediate offset in inst.reloc */
6654 inst
.instruction
|= HWOFFSET_IMM
;
6655 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6656 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6660 /* inst.operands[i] was set up by parse_address. Encode it into an
6661 ARM-format instruction. Reject all forms which cannot be encoded
6662 into a coprocessor load/store instruction. If wb_ok is false,
6663 reject use of writeback; if unind_ok is false, reject use of
6664 unindexed addressing. If reloc_override is not 0, use it instead
6665 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6666 (in which case it is preserved). */
6669 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6671 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6673 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6675 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6677 gas_assert (!inst
.operands
[i
].writeback
);
6680 inst
.error
= _("instruction does not support unindexed addressing");
6683 inst
.instruction
|= inst
.operands
[i
].imm
;
6684 inst
.instruction
|= INDEX_UP
;
6688 if (inst
.operands
[i
].preind
)
6689 inst
.instruction
|= PRE_INDEX
;
6691 if (inst
.operands
[i
].writeback
)
6693 if (inst
.operands
[i
].reg
== REG_PC
)
6695 inst
.error
= _("pc may not be used with write-back");
6700 inst
.error
= _("instruction does not support writeback");
6703 inst
.instruction
|= WRITE_BACK
;
6707 inst
.reloc
.type
= reloc_override
;
6708 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6709 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6710 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6713 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6715 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6721 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6722 Determine whether it can be performed with a move instruction; if
6723 it can, convert inst.instruction to that move instruction and
6724 return TRUE; if it can't, convert inst.instruction to a literal-pool
6725 load and return FALSE. If this is not a valid thing to do in the
6726 current context, set inst.error and return TRUE.
6728 inst.operands[i] describes the destination register. */
6731 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6736 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6740 if ((inst
.instruction
& tbit
) == 0)
6742 inst
.error
= _("invalid pseudo operation");
6745 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6747 inst
.error
= _("constant expression expected");
6750 if (inst
.reloc
.exp
.X_op
== O_constant
)
6754 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6756 /* This can be done with a mov(1) instruction. */
6757 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6758 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6764 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6767 /* This can be done with a mov instruction. */
6768 inst
.instruction
&= LITERAL_MASK
;
6769 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6770 inst
.instruction
|= value
& 0xfff;
6774 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6777 /* This can be done with a mvn instruction. */
6778 inst
.instruction
&= LITERAL_MASK
;
6779 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6780 inst
.instruction
|= value
& 0xfff;
6786 if (add_to_lit_pool () == FAIL
)
6788 inst
.error
= _("literal pool insertion failed");
6791 inst
.operands
[1].reg
= REG_PC
;
6792 inst
.operands
[1].isreg
= 1;
6793 inst
.operands
[1].preind
= 1;
6794 inst
.reloc
.pc_rel
= 1;
6795 inst
.reloc
.type
= (thumb_p
6796 ? BFD_RELOC_ARM_THUMB_OFFSET
6798 ? BFD_RELOC_ARM_HWLITERAL
6799 : BFD_RELOC_ARM_LITERAL
));
6803 /* Functions for instruction encoding, sorted by sub-architecture.
6804 First some generics; their names are taken from the conventional
6805 bit positions for register arguments in ARM format instructions. */
6815 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6821 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6822 inst
.instruction
|= inst
.operands
[1].reg
;
6828 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6829 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6835 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6836 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6842 unsigned Rn
= inst
.operands
[2].reg
;
6843 /* Enforce restrictions on SWP instruction. */
6844 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6845 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6846 _("Rn must not overlap other operands"));
6847 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6848 inst
.instruction
|= inst
.operands
[1].reg
;
6849 inst
.instruction
|= Rn
<< 16;
6855 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6856 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6857 inst
.instruction
|= inst
.operands
[2].reg
;
6863 inst
.instruction
|= inst
.operands
[0].reg
;
6864 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6865 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6871 inst
.instruction
|= inst
.operands
[0].imm
;
6877 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6878 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6881 /* ARM instructions, in alphabetical order by function name (except
6882 that wrapper functions appear immediately after the function they
6885 /* This is a pseudo-op of the form "adr rd, label" to be converted
6886 into a relative address of the form "add rd, pc, #label-.-8". */
6891 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6893 /* Frag hacking will turn this into a sub instruction if the offset turns
6894 out to be negative. */
6895 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6896 inst
.reloc
.pc_rel
= 1;
6897 inst
.reloc
.exp
.X_add_number
-= 8;
6900 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6901 into a relative address of the form:
6902 add rd, pc, #low(label-.-8)"
6903 add rd, rd, #high(label-.-8)" */
6908 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6910 /* Frag hacking will turn this into a sub instruction if the offset turns
6911 out to be negative. */
6912 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6913 inst
.reloc
.pc_rel
= 1;
6914 inst
.size
= INSN_SIZE
* 2;
6915 inst
.reloc
.exp
.X_add_number
-= 8;
6921 if (!inst
.operands
[1].present
)
6922 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6923 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6924 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6925 encode_arm_shifter_operand (2);
6931 if (inst
.operands
[0].present
)
6933 constraint ((inst
.instruction
& 0xf0) != 0x40
6934 && inst
.operands
[0].imm
!= 0xf,
6935 _("bad barrier type"));
6936 inst
.instruction
|= inst
.operands
[0].imm
;
6939 inst
.instruction
|= 0xf;
6945 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6946 constraint (msb
> 32, _("bit-field extends past end of register"));
6947 /* The instruction encoding stores the LSB and MSB,
6948 not the LSB and width. */
6949 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6950 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6951 inst
.instruction
|= (msb
- 1) << 16;
6959 /* #0 in second position is alternative syntax for bfc, which is
6960 the same instruction but with REG_PC in the Rm field. */
6961 if (!inst
.operands
[1].isreg
)
6962 inst
.operands
[1].reg
= REG_PC
;
6964 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6965 constraint (msb
> 32, _("bit-field extends past end of register"));
6966 /* The instruction encoding stores the LSB and MSB,
6967 not the LSB and width. */
6968 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6969 inst
.instruction
|= inst
.operands
[1].reg
;
6970 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6971 inst
.instruction
|= (msb
- 1) << 16;
6977 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6978 _("bit-field extends past end of register"));
6979 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6980 inst
.instruction
|= inst
.operands
[1].reg
;
6981 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6982 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6985 /* ARM V5 breakpoint instruction (argument parse)
6986 BKPT <16 bit unsigned immediate>
6987 Instruction is not conditional.
6988 The bit pattern given in insns[] has the COND_ALWAYS condition,
6989 and it is an error if the caller tried to override that. */
6994 /* Top 12 of 16 bits to bits 19:8. */
6995 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6997 /* Bottom 4 of 16 bits to bits 3:0. */
6998 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7002 encode_branch (int default_reloc
)
7004 if (inst
.operands
[0].hasreloc
)
7006 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7007 _("the only suffix valid here is '(plt)'"));
7008 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7012 inst
.reloc
.type
= default_reloc
;
7014 inst
.reloc
.pc_rel
= 1;
7021 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7022 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7025 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7032 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7034 if (inst
.cond
== COND_ALWAYS
)
7035 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7037 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7041 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7044 /* ARM V5 branch-link-exchange instruction (argument parse)
7045 BLX <target_addr> ie BLX(1)
7046 BLX{<condition>} <Rm> ie BLX(2)
7047 Unfortunately, there are two different opcodes for this mnemonic.
7048 So, the insns[].value is not used, and the code here zaps values
7049 into inst.instruction.
7050 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7055 if (inst
.operands
[0].isreg
)
7057 /* Arg is a register; the opcode provided by insns[] is correct.
7058 It is not illegal to do "blx pc", just useless. */
7059 if (inst
.operands
[0].reg
== REG_PC
)
7060 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7062 inst
.instruction
|= inst
.operands
[0].reg
;
7066 /* Arg is an address; this instruction cannot be executed
7067 conditionally, and the opcode must be adjusted.
7068 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7069 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7070 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7071 inst
.instruction
= 0xfa000000;
7072 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7079 bfd_boolean want_reloc
;
7081 if (inst
.operands
[0].reg
== REG_PC
)
7082 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7084 inst
.instruction
|= inst
.operands
[0].reg
;
7085 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7086 it is for ARMv4t or earlier. */
7087 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7088 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7092 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7097 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7101 /* ARM v5TEJ. Jump to Jazelle code. */
7106 if (inst
.operands
[0].reg
== REG_PC
)
7107 as_tsktsk (_("use of r15 in bxj is not really useful"));
7109 inst
.instruction
|= inst
.operands
[0].reg
;
7112 /* Co-processor data operation:
7113 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7114 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7118 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7119 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7120 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7121 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7122 inst
.instruction
|= inst
.operands
[4].reg
;
7123 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7129 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7130 encode_arm_shifter_operand (1);
7133 /* Transfer between coprocessor and ARM registers.
7134 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7139 No special properties. */
7146 Rd
= inst
.operands
[2].reg
;
7149 if (inst
.instruction
== 0xee000010
7150 || inst
.instruction
== 0xfe000010)
7152 reject_bad_reg (Rd
);
7155 constraint (Rd
== REG_SP
, BAD_SP
);
7160 if (inst
.instruction
== 0xe000010)
7161 constraint (Rd
== REG_PC
, BAD_PC
);
7165 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7166 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7167 inst
.instruction
|= Rd
<< 12;
7168 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7169 inst
.instruction
|= inst
.operands
[4].reg
;
7170 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7173 /* Transfer between coprocessor register and pair of ARM registers.
7174 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7179 Two XScale instructions are special cases of these:
7181 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7182 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7184 Result unpredictable if Rd or Rn is R15. */
7191 Rd
= inst
.operands
[2].reg
;
7192 Rn
= inst
.operands
[3].reg
;
7196 reject_bad_reg (Rd
);
7197 reject_bad_reg (Rn
);
7201 constraint (Rd
== REG_PC
, BAD_PC
);
7202 constraint (Rn
== REG_PC
, BAD_PC
);
7205 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7206 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7207 inst
.instruction
|= Rd
<< 12;
7208 inst
.instruction
|= Rn
<< 16;
7209 inst
.instruction
|= inst
.operands
[4].reg
;
7215 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7216 if (inst
.operands
[1].present
)
7218 inst
.instruction
|= CPSI_MMOD
;
7219 inst
.instruction
|= inst
.operands
[1].imm
;
7226 inst
.instruction
|= inst
.operands
[0].imm
;
7232 /* There is no IT instruction in ARM mode. We
7233 process it to do the validation as if in
7234 thumb mode, just in case the code gets
7235 assembled for thumb using the unified syntax. */
7240 set_it_insn_type (IT_INSN
);
7241 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7242 now_it
.cc
= inst
.operands
[0].imm
;
7249 int base_reg
= inst
.operands
[0].reg
;
7250 int range
= inst
.operands
[1].imm
;
7252 inst
.instruction
|= base_reg
<< 16;
7253 inst
.instruction
|= range
;
7255 if (inst
.operands
[1].writeback
)
7256 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7258 if (inst
.operands
[0].writeback
)
7260 inst
.instruction
|= WRITE_BACK
;
7261 /* Check for unpredictable uses of writeback. */
7262 if (inst
.instruction
& LOAD_BIT
)
7264 /* Not allowed in LDM type 2. */
7265 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7266 && ((range
& (1 << REG_PC
)) == 0))
7267 as_warn (_("writeback of base register is UNPREDICTABLE"));
7268 /* Only allowed if base reg not in list for other types. */
7269 else if (range
& (1 << base_reg
))
7270 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7274 /* Not allowed for type 2. */
7275 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7276 as_warn (_("writeback of base register is UNPREDICTABLE"));
7277 /* Only allowed if base reg not in list, or first in list. */
7278 else if ((range
& (1 << base_reg
))
7279 && (range
& ((1 << base_reg
) - 1)))
7280 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7285 /* ARMv5TE load-consecutive (argument parse)
7294 constraint (inst
.operands
[0].reg
% 2 != 0,
7295 _("first destination register must be even"));
7296 constraint (inst
.operands
[1].present
7297 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7298 _("can only load two consecutive registers"));
7299 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7300 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7302 if (!inst
.operands
[1].present
)
7303 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7305 if (inst
.instruction
& LOAD_BIT
)
7307 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7308 register and the first register written; we have to diagnose
7309 overlap between the base and the second register written here. */
7311 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7312 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7313 as_warn (_("base register written back, and overlaps "
7314 "second destination register"));
7316 /* For an index-register load, the index register must not overlap the
7317 destination (even if not write-back). */
7318 else if (inst
.operands
[2].immisreg
7319 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7320 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7321 as_warn (_("index register overlaps destination register"));
7324 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7325 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7331 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7332 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7333 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7334 || inst
.operands
[1].negative
7335 /* This can arise if the programmer has written
7337 or if they have mistakenly used a register name as the last
7340 It is very difficult to distinguish between these two cases
7341 because "rX" might actually be a label. ie the register
7342 name has been occluded by a symbol of the same name. So we
7343 just generate a general 'bad addressing mode' type error
7344 message and leave it up to the programmer to discover the
7345 true cause and fix their mistake. */
7346 || (inst
.operands
[1].reg
== REG_PC
),
7349 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7350 || inst
.reloc
.exp
.X_add_number
!= 0,
7351 _("offset must be zero in ARM encoding"));
7353 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7354 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7355 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7361 constraint (inst
.operands
[0].reg
% 2 != 0,
7362 _("even register required"));
7363 constraint (inst
.operands
[1].present
7364 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7365 _("can only load two consecutive registers"));
7366 /* If op 1 were present and equal to PC, this function wouldn't
7367 have been called in the first place. */
7368 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7370 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7371 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7377 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7378 if (!inst
.operands
[1].isreg
)
7379 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7381 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7387 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7389 if (inst
.operands
[1].preind
)
7391 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7392 || inst
.reloc
.exp
.X_add_number
!= 0,
7393 _("this instruction requires a post-indexed address"));
7395 inst
.operands
[1].preind
= 0;
7396 inst
.operands
[1].postind
= 1;
7397 inst
.operands
[1].writeback
= 1;
7399 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7400 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7403 /* Halfword and signed-byte load/store operations. */
7408 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7409 if (!inst
.operands
[1].isreg
)
7410 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7412 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7418 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7420 if (inst
.operands
[1].preind
)
7422 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7423 || inst
.reloc
.exp
.X_add_number
!= 0,
7424 _("this instruction requires a post-indexed address"));
7426 inst
.operands
[1].preind
= 0;
7427 inst
.operands
[1].postind
= 1;
7428 inst
.operands
[1].writeback
= 1;
7430 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7431 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7434 /* Co-processor register load/store.
7435 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7439 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7440 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7441 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7447 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7448 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7449 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7450 && !(inst
.instruction
& 0x00400000))
7451 as_tsktsk (_("Rd and Rm should be different in mla"));
7453 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7454 inst
.instruction
|= inst
.operands
[1].reg
;
7455 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7456 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7462 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7463 encode_arm_shifter_operand (1);
7466 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7473 top
= (inst
.instruction
& 0x00400000) != 0;
7474 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7475 _(":lower16: not allowed this instruction"));
7476 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7477 _(":upper16: not allowed instruction"));
7478 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7479 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7481 imm
= inst
.reloc
.exp
.X_add_number
;
7482 /* The value is in two pieces: 0:11, 16:19. */
7483 inst
.instruction
|= (imm
& 0x00000fff);
7484 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7488 static void do_vfp_nsyn_opcode (const char *);
7491 do_vfp_nsyn_mrs (void)
7493 if (inst
.operands
[0].isvec
)
7495 if (inst
.operands
[1].reg
!= 1)
7496 first_error (_("operand 1 must be FPSCR"));
7497 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7498 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7499 do_vfp_nsyn_opcode ("fmstat");
7501 else if (inst
.operands
[1].isvec
)
7502 do_vfp_nsyn_opcode ("fmrx");
7510 do_vfp_nsyn_msr (void)
7512 if (inst
.operands
[0].isvec
)
7513 do_vfp_nsyn_opcode ("fmxr");
7523 if (do_vfp_nsyn_mrs () == SUCCESS
)
7526 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7527 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7529 _("'CPSR' or 'SPSR' expected"));
7530 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7531 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7534 /* Two possible forms:
7535 "{C|S}PSR_<field>, Rm",
7536 "{C|S}PSR_f, #expression". */
7541 if (do_vfp_nsyn_msr () == SUCCESS
)
7544 inst
.instruction
|= inst
.operands
[0].imm
;
7545 if (inst
.operands
[1].isreg
)
7546 inst
.instruction
|= inst
.operands
[1].reg
;
7549 inst
.instruction
|= INST_IMMEDIATE
;
7550 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7551 inst
.reloc
.pc_rel
= 0;
7558 if (!inst
.operands
[2].present
)
7559 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7560 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7561 inst
.instruction
|= inst
.operands
[1].reg
;
7562 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7564 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7565 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7566 as_tsktsk (_("Rd and Rm should be different in mul"));
7569 /* Long Multiply Parser
7570 UMULL RdLo, RdHi, Rm, Rs
7571 SMULL RdLo, RdHi, Rm, Rs
7572 UMLAL RdLo, RdHi, Rm, Rs
7573 SMLAL RdLo, RdHi, Rm, Rs. */
7578 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7579 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7580 inst
.instruction
|= inst
.operands
[2].reg
;
7581 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7583 /* rdhi and rdlo must be different. */
7584 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7585 as_tsktsk (_("rdhi and rdlo must be different"));
7587 /* rdhi, rdlo and rm must all be different before armv6. */
7588 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7589 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7590 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7591 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7597 if (inst
.operands
[0].present
7598 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7600 /* Architectural NOP hints are CPSR sets with no bits selected. */
7601 inst
.instruction
&= 0xf0000000;
7602 inst
.instruction
|= 0x0320f000;
7603 if (inst
.operands
[0].present
)
7604 inst
.instruction
|= inst
.operands
[0].imm
;
7608 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7609 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7610 Condition defaults to COND_ALWAYS.
7611 Error if Rd, Rn or Rm are R15. */
7616 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7617 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7618 inst
.instruction
|= inst
.operands
[2].reg
;
7619 if (inst
.operands
[3].present
)
7620 encode_arm_shift (3);
7623 /* ARM V6 PKHTB (Argument Parse). */
7628 if (!inst
.operands
[3].present
)
7630 /* If the shift specifier is omitted, turn the instruction
7631 into pkhbt rd, rm, rn. */
7632 inst
.instruction
&= 0xfff00010;
7633 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7634 inst
.instruction
|= inst
.operands
[1].reg
;
7635 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7639 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7640 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7641 inst
.instruction
|= inst
.operands
[2].reg
;
7642 encode_arm_shift (3);
7646 /* ARMv5TE: Preload-Cache
7650 Syntactically, like LDR with B=1, W=0, L=1. */
7655 constraint (!inst
.operands
[0].isreg
,
7656 _("'[' expected after PLD mnemonic"));
7657 constraint (inst
.operands
[0].postind
,
7658 _("post-indexed expression used in preload instruction"));
7659 constraint (inst
.operands
[0].writeback
,
7660 _("writeback used in preload instruction"));
7661 constraint (!inst
.operands
[0].preind
,
7662 _("unindexed addressing used in preload instruction"));
7663 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7666 /* ARMv7: PLI <addr_mode> */
7670 constraint (!inst
.operands
[0].isreg
,
7671 _("'[' expected after PLI mnemonic"));
7672 constraint (inst
.operands
[0].postind
,
7673 _("post-indexed expression used in preload instruction"));
7674 constraint (inst
.operands
[0].writeback
,
7675 _("writeback used in preload instruction"));
7676 constraint (!inst
.operands
[0].preind
,
7677 _("unindexed addressing used in preload instruction"));
7678 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7679 inst
.instruction
&= ~PRE_INDEX
;
7685 inst
.operands
[1] = inst
.operands
[0];
7686 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7687 inst
.operands
[0].isreg
= 1;
7688 inst
.operands
[0].writeback
= 1;
7689 inst
.operands
[0].reg
= REG_SP
;
7693 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7694 word at the specified address and the following word
7696 Unconditionally executed.
7697 Error if Rn is R15. */
7702 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7703 if (inst
.operands
[0].writeback
)
7704 inst
.instruction
|= WRITE_BACK
;
7707 /* ARM V6 ssat (argument parse). */
7712 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7713 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7714 inst
.instruction
|= inst
.operands
[2].reg
;
7716 if (inst
.operands
[3].present
)
7717 encode_arm_shift (3);
7720 /* ARM V6 usat (argument parse). */
7725 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7726 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7727 inst
.instruction
|= inst
.operands
[2].reg
;
7729 if (inst
.operands
[3].present
)
7730 encode_arm_shift (3);
7733 /* ARM V6 ssat16 (argument parse). */
7738 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7739 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7740 inst
.instruction
|= inst
.operands
[2].reg
;
7746 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7747 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7748 inst
.instruction
|= inst
.operands
[2].reg
;
7751 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7752 preserving the other bits.
7754 setend <endian_specifier>, where <endian_specifier> is either
7760 if (inst
.operands
[0].imm
)
7761 inst
.instruction
|= 0x200;
7767 unsigned int Rm
= (inst
.operands
[1].present
7768 ? inst
.operands
[1].reg
7769 : inst
.operands
[0].reg
);
7771 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7772 inst
.instruction
|= Rm
;
7773 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7775 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7776 inst
.instruction
|= SHIFT_BY_REG
;
7779 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7785 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7786 inst
.reloc
.pc_rel
= 0;
7792 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7793 inst
.reloc
.pc_rel
= 0;
7796 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7797 SMLAxy{cond} Rd,Rm,Rs,Rn
7798 SMLAWy{cond} Rd,Rm,Rs,Rn
7799 Error if any register is R15. */
7804 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7805 inst
.instruction
|= inst
.operands
[1].reg
;
7806 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7807 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7810 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7811 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7812 Error if any register is R15.
7813 Warning if Rdlo == Rdhi. */
7818 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7819 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7820 inst
.instruction
|= inst
.operands
[2].reg
;
7821 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7823 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7824 as_tsktsk (_("rdhi and rdlo must be different"));
7827 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7828 SMULxy{cond} Rd,Rm,Rs
7829 Error if any register is R15. */
7834 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7835 inst
.instruction
|= inst
.operands
[1].reg
;
7836 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7839 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7840 the same for both ARM and Thumb-2. */
7847 if (inst
.operands
[0].present
)
7849 reg
= inst
.operands
[0].reg
;
7850 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
7855 inst
.instruction
|= reg
<< 16;
7856 inst
.instruction
|= inst
.operands
[1].imm
;
7857 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7858 inst
.instruction
|= WRITE_BACK
;
7861 /* ARM V6 strex (argument parse). */
7866 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7867 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7868 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7869 || inst
.operands
[2].negative
7870 /* See comment in do_ldrex(). */
7871 || (inst
.operands
[2].reg
== REG_PC
),
7874 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7875 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7877 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7878 || inst
.reloc
.exp
.X_add_number
!= 0,
7879 _("offset must be zero in ARM encoding"));
7881 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7882 inst
.instruction
|= inst
.operands
[1].reg
;
7883 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7884 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7890 constraint (inst
.operands
[1].reg
% 2 != 0,
7891 _("even register required"));
7892 constraint (inst
.operands
[2].present
7893 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7894 _("can only store two consecutive registers"));
7895 /* If op 2 were present and equal to PC, this function wouldn't
7896 have been called in the first place. */
7897 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7899 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7900 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7901 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7904 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7905 inst
.instruction
|= inst
.operands
[1].reg
;
7906 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7909 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7910 extends it to 32-bits, and adds the result to a value in another
7911 register. You can specify a rotation by 0, 8, 16, or 24 bits
7912 before extracting the 16-bit value.
7913 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7914 Condition defaults to COND_ALWAYS.
7915 Error if any register uses R15. */
7920 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7921 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7922 inst
.instruction
|= inst
.operands
[2].reg
;
7923 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7928 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7929 Condition defaults to COND_ALWAYS.
7930 Error if any register uses R15. */
7935 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7936 inst
.instruction
|= inst
.operands
[1].reg
;
7937 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7940 /* VFP instructions. In a logical order: SP variant first, monad
7941 before dyad, arithmetic then move then load/store. */
7944 do_vfp_sp_monadic (void)
7946 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7947 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7951 do_vfp_sp_dyadic (void)
7953 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7954 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7955 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7959 do_vfp_sp_compare_z (void)
7961 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7965 do_vfp_dp_sp_cvt (void)
7967 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7968 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7972 do_vfp_sp_dp_cvt (void)
7974 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7975 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7979 do_vfp_reg_from_sp (void)
7981 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7982 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7986 do_vfp_reg2_from_sp2 (void)
7988 constraint (inst
.operands
[2].imm
!= 2,
7989 _("only two consecutive VFP SP registers allowed here"));
7990 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7991 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7992 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7996 do_vfp_sp_from_reg (void)
7998 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7999 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8003 do_vfp_sp2_from_reg2 (void)
8005 constraint (inst
.operands
[0].imm
!= 2,
8006 _("only two consecutive VFP SP registers allowed here"));
8007 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8008 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8009 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8013 do_vfp_sp_ldst (void)
8015 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8016 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8020 do_vfp_dp_ldst (void)
8022 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8023 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8028 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8030 if (inst
.operands
[0].writeback
)
8031 inst
.instruction
|= WRITE_BACK
;
8033 constraint (ldstm_type
!= VFP_LDSTMIA
,
8034 _("this addressing mode requires base-register writeback"));
8035 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8036 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8037 inst
.instruction
|= inst
.operands
[1].imm
;
8041 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8045 if (inst
.operands
[0].writeback
)
8046 inst
.instruction
|= WRITE_BACK
;
8048 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8049 _("this addressing mode requires base-register writeback"));
8051 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8052 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8054 count
= inst
.operands
[1].imm
<< 1;
8055 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8058 inst
.instruction
|= count
;
8062 do_vfp_sp_ldstmia (void)
8064 vfp_sp_ldstm (VFP_LDSTMIA
);
8068 do_vfp_sp_ldstmdb (void)
8070 vfp_sp_ldstm (VFP_LDSTMDB
);
8074 do_vfp_dp_ldstmia (void)
8076 vfp_dp_ldstm (VFP_LDSTMIA
);
8080 do_vfp_dp_ldstmdb (void)
8082 vfp_dp_ldstm (VFP_LDSTMDB
);
8086 do_vfp_xp_ldstmia (void)
8088 vfp_dp_ldstm (VFP_LDSTMIAX
);
8092 do_vfp_xp_ldstmdb (void)
8094 vfp_dp_ldstm (VFP_LDSTMDBX
);
8098 do_vfp_dp_rd_rm (void)
8100 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8101 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8105 do_vfp_dp_rn_rd (void)
8107 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8108 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8112 do_vfp_dp_rd_rn (void)
8114 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8115 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8119 do_vfp_dp_rd_rn_rm (void)
8121 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8122 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8123 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8129 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8133 do_vfp_dp_rm_rd_rn (void)
8135 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8136 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8137 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8140 /* VFPv3 instructions. */
8142 do_vfp_sp_const (void)
8144 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8145 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8146 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8150 do_vfp_dp_const (void)
8152 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8153 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8154 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8158 vfp_conv (int srcsize
)
8160 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8161 inst
.instruction
|= (immbits
& 1) << 5;
8162 inst
.instruction
|= (immbits
>> 1);
8166 do_vfp_sp_conv_16 (void)
8168 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8173 do_vfp_dp_conv_16 (void)
8175 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8180 do_vfp_sp_conv_32 (void)
8182 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8187 do_vfp_dp_conv_32 (void)
8189 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8193 /* FPA instructions. Also in a logical order. */
8198 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8199 inst
.instruction
|= inst
.operands
[1].reg
;
8203 do_fpa_ldmstm (void)
8205 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8206 switch (inst
.operands
[1].imm
)
8208 case 1: inst
.instruction
|= CP_T_X
; break;
8209 case 2: inst
.instruction
|= CP_T_Y
; break;
8210 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8215 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8217 /* The instruction specified "ea" or "fd", so we can only accept
8218 [Rn]{!}. The instruction does not really support stacking or
8219 unstacking, so we have to emulate these by setting appropriate
8220 bits and offsets. */
8221 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8222 || inst
.reloc
.exp
.X_add_number
!= 0,
8223 _("this instruction does not support indexing"));
8225 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8226 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8228 if (!(inst
.instruction
& INDEX_UP
))
8229 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8231 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8233 inst
.operands
[2].preind
= 0;
8234 inst
.operands
[2].postind
= 1;
8238 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8241 /* iWMMXt instructions: strictly in alphabetical order. */
8244 do_iwmmxt_tandorc (void)
8246 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8250 do_iwmmxt_textrc (void)
8252 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8253 inst
.instruction
|= inst
.operands
[1].imm
;
8257 do_iwmmxt_textrm (void)
8259 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8260 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8261 inst
.instruction
|= inst
.operands
[2].imm
;
8265 do_iwmmxt_tinsr (void)
8267 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8268 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8269 inst
.instruction
|= inst
.operands
[2].imm
;
8273 do_iwmmxt_tmia (void)
8275 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8276 inst
.instruction
|= inst
.operands
[1].reg
;
8277 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8281 do_iwmmxt_waligni (void)
8283 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8284 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8285 inst
.instruction
|= inst
.operands
[2].reg
;
8286 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8290 do_iwmmxt_wmerge (void)
8292 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8293 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8294 inst
.instruction
|= inst
.operands
[2].reg
;
8295 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8299 do_iwmmxt_wmov (void)
8301 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8302 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8303 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8304 inst
.instruction
|= inst
.operands
[1].reg
;
8308 do_iwmmxt_wldstbh (void)
8311 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8313 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8315 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8316 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8320 do_iwmmxt_wldstw (void)
8322 /* RIWR_RIWC clears .isreg for a control register. */
8323 if (!inst
.operands
[0].isreg
)
8325 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8326 inst
.instruction
|= 0xf0000000;
8329 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8330 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8334 do_iwmmxt_wldstd (void)
8336 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8337 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8338 && inst
.operands
[1].immisreg
)
8340 inst
.instruction
&= ~0x1a000ff;
8341 inst
.instruction
|= (0xf << 28);
8342 if (inst
.operands
[1].preind
)
8343 inst
.instruction
|= PRE_INDEX
;
8344 if (!inst
.operands
[1].negative
)
8345 inst
.instruction
|= INDEX_UP
;
8346 if (inst
.operands
[1].writeback
)
8347 inst
.instruction
|= WRITE_BACK
;
8348 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8349 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8350 inst
.instruction
|= inst
.operands
[1].imm
;
8353 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8357 do_iwmmxt_wshufh (void)
8359 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8360 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8361 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8362 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8366 do_iwmmxt_wzero (void)
8368 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8369 inst
.instruction
|= inst
.operands
[0].reg
;
8370 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8371 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8375 do_iwmmxt_wrwrwr_or_imm5 (void)
8377 if (inst
.operands
[2].isreg
)
8380 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8381 _("immediate operand requires iWMMXt2"));
8383 if (inst
.operands
[2].imm
== 0)
8385 switch ((inst
.instruction
>> 20) & 0xf)
8391 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8392 inst
.operands
[2].imm
= 16;
8393 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8399 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8400 inst
.operands
[2].imm
= 32;
8401 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8408 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8410 wrn
= (inst
.instruction
>> 16) & 0xf;
8411 inst
.instruction
&= 0xff0fff0f;
8412 inst
.instruction
|= wrn
;
8413 /* Bail out here; the instruction is now assembled. */
8418 /* Map 32 -> 0, etc. */
8419 inst
.operands
[2].imm
&= 0x1f;
8420 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8424 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8425 operations first, then control, shift, and load/store. */
8427 /* Insns like "foo X,Y,Z". */
8430 do_mav_triple (void)
8432 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8433 inst
.instruction
|= inst
.operands
[1].reg
;
8434 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8437 /* Insns like "foo W,X,Y,Z".
8438 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8443 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8444 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8445 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8446 inst
.instruction
|= inst
.operands
[3].reg
;
8449 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8453 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8456 /* Maverick shift immediate instructions.
8457 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8458 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8463 int imm
= inst
.operands
[2].imm
;
8465 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8466 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8468 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8469 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8470 Bit 4 should be 0. */
8471 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8473 inst
.instruction
|= imm
;
8476 /* XScale instructions. Also sorted arithmetic before move. */
8478 /* Xscale multiply-accumulate (argument parse)
8481 MIAxycc acc0,Rm,Rs. */
8486 inst
.instruction
|= inst
.operands
[1].reg
;
8487 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8490 /* Xscale move-accumulator-register (argument parse)
8492 MARcc acc0,RdLo,RdHi. */
8497 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8498 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8501 /* Xscale move-register-accumulator (argument parse)
8503 MRAcc RdLo,RdHi,acc0. */
8508 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8509 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8510 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8513 /* Encoding functions relevant only to Thumb. */
8515 /* inst.operands[i] is a shifted-register operand; encode
8516 it into inst.instruction in the format used by Thumb32. */
8519 encode_thumb32_shifted_operand (int i
)
8521 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8522 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8524 constraint (inst
.operands
[i
].immisreg
,
8525 _("shift by register not allowed in thumb mode"));
8526 inst
.instruction
|= inst
.operands
[i
].reg
;
8527 if (shift
== SHIFT_RRX
)
8528 inst
.instruction
|= SHIFT_ROR
<< 4;
8531 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8532 _("expression too complex"));
8534 constraint (value
> 32
8535 || (value
== 32 && (shift
== SHIFT_LSL
8536 || shift
== SHIFT_ROR
)),
8537 _("shift expression is too large"));
8541 else if (value
== 32)
8544 inst
.instruction
|= shift
<< 4;
8545 inst
.instruction
|= (value
& 0x1c) << 10;
8546 inst
.instruction
|= (value
& 0x03) << 6;
8551 /* inst.operands[i] was set up by parse_address. Encode it into a
8552 Thumb32 format load or store instruction. Reject forms that cannot
8553 be used with such instructions. If is_t is true, reject forms that
8554 cannot be used with a T instruction; if is_d is true, reject forms
8555 that cannot be used with a D instruction. */
8558 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8560 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8562 constraint (!inst
.operands
[i
].isreg
,
8563 _("Instruction does not support =N addresses"));
8565 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8566 if (inst
.operands
[i
].immisreg
)
8568 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8569 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8570 constraint (inst
.operands
[i
].negative
,
8571 _("Thumb does not support negative register indexing"));
8572 constraint (inst
.operands
[i
].postind
,
8573 _("Thumb does not support register post-indexing"));
8574 constraint (inst
.operands
[i
].writeback
,
8575 _("Thumb does not support register indexing with writeback"));
8576 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8577 _("Thumb supports only LSL in shifted register indexing"));
8579 inst
.instruction
|= inst
.operands
[i
].imm
;
8580 if (inst
.operands
[i
].shifted
)
8582 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8583 _("expression too complex"));
8584 constraint (inst
.reloc
.exp
.X_add_number
< 0
8585 || inst
.reloc
.exp
.X_add_number
> 3,
8586 _("shift out of range"));
8587 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8589 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8591 else if (inst
.operands
[i
].preind
)
8593 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8594 _("cannot use writeback with PC-relative addressing"));
8595 constraint (is_t
&& inst
.operands
[i
].writeback
,
8596 _("cannot use writeback with this instruction"));
8600 inst
.instruction
|= 0x01000000;
8601 if (inst
.operands
[i
].writeback
)
8602 inst
.instruction
|= 0x00200000;
8606 inst
.instruction
|= 0x00000c00;
8607 if (inst
.operands
[i
].writeback
)
8608 inst
.instruction
|= 0x00000100;
8610 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8612 else if (inst
.operands
[i
].postind
)
8614 gas_assert (inst
.operands
[i
].writeback
);
8615 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8616 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8619 inst
.instruction
|= 0x00200000;
8621 inst
.instruction
|= 0x00000900;
8622 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8624 else /* unindexed - only for coprocessor */
8625 inst
.error
= _("instruction does not accept unindexed addressing");
8628 /* Table of Thumb instructions which exist in both 16- and 32-bit
8629 encodings (the latter only in post-V6T2 cores). The index is the
8630 value used in the insns table below. When there is more than one
8631 possible 16-bit encoding for the instruction, this table always
8633 Also contains several pseudo-instructions used during relaxation. */
8634 #define T16_32_TAB \
8635 X(adc, 4140, eb400000), \
8636 X(adcs, 4140, eb500000), \
8637 X(add, 1c00, eb000000), \
8638 X(adds, 1c00, eb100000), \
8639 X(addi, 0000, f1000000), \
8640 X(addis, 0000, f1100000), \
8641 X(add_pc,000f, f20f0000), \
8642 X(add_sp,000d, f10d0000), \
8643 X(adr, 000f, f20f0000), \
8644 X(and, 4000, ea000000), \
8645 X(ands, 4000, ea100000), \
8646 X(asr, 1000, fa40f000), \
8647 X(asrs, 1000, fa50f000), \
8648 X(b, e000, f000b000), \
8649 X(bcond, d000, f0008000), \
8650 X(bic, 4380, ea200000), \
8651 X(bics, 4380, ea300000), \
8652 X(cmn, 42c0, eb100f00), \
8653 X(cmp, 2800, ebb00f00), \
8654 X(cpsie, b660, f3af8400), \
8655 X(cpsid, b670, f3af8600), \
8656 X(cpy, 4600, ea4f0000), \
8657 X(dec_sp,80dd, f1ad0d00), \
8658 X(eor, 4040, ea800000), \
8659 X(eors, 4040, ea900000), \
8660 X(inc_sp,00dd, f10d0d00), \
8661 X(ldmia, c800, e8900000), \
8662 X(ldr, 6800, f8500000), \
8663 X(ldrb, 7800, f8100000), \
8664 X(ldrh, 8800, f8300000), \
8665 X(ldrsb, 5600, f9100000), \
8666 X(ldrsh, 5e00, f9300000), \
8667 X(ldr_pc,4800, f85f0000), \
8668 X(ldr_pc2,4800, f85f0000), \
8669 X(ldr_sp,9800, f85d0000), \
8670 X(lsl, 0000, fa00f000), \
8671 X(lsls, 0000, fa10f000), \
8672 X(lsr, 0800, fa20f000), \
8673 X(lsrs, 0800, fa30f000), \
8674 X(mov, 2000, ea4f0000), \
8675 X(movs, 2000, ea5f0000), \
8676 X(mul, 4340, fb00f000), \
8677 X(muls, 4340, ffffffff), /* no 32b muls */ \
8678 X(mvn, 43c0, ea6f0000), \
8679 X(mvns, 43c0, ea7f0000), \
8680 X(neg, 4240, f1c00000), /* rsb #0 */ \
8681 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8682 X(orr, 4300, ea400000), \
8683 X(orrs, 4300, ea500000), \
8684 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8685 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8686 X(rev, ba00, fa90f080), \
8687 X(rev16, ba40, fa90f090), \
8688 X(revsh, bac0, fa90f0b0), \
8689 X(ror, 41c0, fa60f000), \
8690 X(rors, 41c0, fa70f000), \
8691 X(sbc, 4180, eb600000), \
8692 X(sbcs, 4180, eb700000), \
8693 X(stmia, c000, e8800000), \
8694 X(str, 6000, f8400000), \
8695 X(strb, 7000, f8000000), \
8696 X(strh, 8000, f8200000), \
8697 X(str_sp,9000, f84d0000), \
8698 X(sub, 1e00, eba00000), \
8699 X(subs, 1e00, ebb00000), \
8700 X(subi, 8000, f1a00000), \
8701 X(subis, 8000, f1b00000), \
8702 X(sxtb, b240, fa4ff080), \
8703 X(sxth, b200, fa0ff080), \
8704 X(tst, 4200, ea100f00), \
8705 X(uxtb, b2c0, fa5ff080), \
8706 X(uxth, b280, fa1ff080), \
8707 X(nop, bf00, f3af8000), \
8708 X(yield, bf10, f3af8001), \
8709 X(wfe, bf20, f3af8002), \
8710 X(wfi, bf30, f3af8003), \
8711 X(sev, bf40, f3af8004),
8713 /* To catch errors in encoding functions, the codes are all offset by
8714 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8715 as 16-bit instructions. */
8716 #define X(a,b,c) T_MNEM_##a
8717 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8720 #define X(a,b,c) 0x##b
8721 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8722 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8725 #define X(a,b,c) 0x##c
8726 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8727 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8728 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8732 /* Thumb instruction encoders, in alphabetical order. */
8737 do_t_add_sub_w (void)
8741 Rd
= inst
.operands
[0].reg
;
8742 Rn
= inst
.operands
[1].reg
;
8744 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this is the
8745 SP-{plus,minute}-immediate form of the instruction. */
8746 reject_bad_reg (Rd
);
8748 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8749 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8752 /* Parse an add or subtract instruction. We get here with inst.instruction
8753 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8760 Rd
= inst
.operands
[0].reg
;
8761 Rs
= (inst
.operands
[1].present
8762 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8763 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8766 set_it_insn_type_last ();
8774 flags
= (inst
.instruction
== T_MNEM_adds
8775 || inst
.instruction
== T_MNEM_subs
);
8777 narrow
= !in_it_block ();
8779 narrow
= in_it_block ();
8780 if (!inst
.operands
[2].isreg
)
8784 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8786 add
= (inst
.instruction
== T_MNEM_add
8787 || inst
.instruction
== T_MNEM_adds
);
8789 if (inst
.size_req
!= 4)
8791 /* Attempt to use a narrow opcode, with relaxation if
8793 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8794 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8795 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8796 opcode
= T_MNEM_add_sp
;
8797 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8798 opcode
= T_MNEM_add_pc
;
8799 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8802 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8804 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8808 inst
.instruction
= THUMB_OP16(opcode
);
8809 inst
.instruction
|= (Rd
<< 4) | Rs
;
8810 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8811 if (inst
.size_req
!= 2)
8812 inst
.relax
= opcode
;
8815 constraint (inst
.size_req
== 2, BAD_HIREG
);
8817 if (inst
.size_req
== 4
8818 || (inst
.size_req
!= 2 && !opcode
))
8822 constraint (add
, BAD_PC
);
8823 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8824 _("only SUBS PC, LR, #const allowed"));
8825 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8826 _("expression too complex"));
8827 constraint (inst
.reloc
.exp
.X_add_number
< 0
8828 || inst
.reloc
.exp
.X_add_number
> 0xff,
8829 _("immediate value out of range"));
8830 inst
.instruction
= T2_SUBS_PC_LR
8831 | inst
.reloc
.exp
.X_add_number
;
8832 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8835 else if (Rs
== REG_PC
)
8837 /* Always use addw/subw. */
8838 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8839 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8843 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8844 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8847 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8849 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8851 inst
.instruction
|= Rd
<< 8;
8852 inst
.instruction
|= Rs
<< 16;
8857 Rn
= inst
.operands
[2].reg
;
8858 /* See if we can do this with a 16-bit instruction. */
8859 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8861 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8866 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8867 || inst
.instruction
== T_MNEM_add
)
8870 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8874 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
8876 /* Thumb-1 cores (except v6-M) require at least one high
8877 register in a narrow non flag setting add. */
8878 if (Rd
> 7 || Rn
> 7
8879 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
8880 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
8887 inst
.instruction
= T_OPCODE_ADD_HI
;
8888 inst
.instruction
|= (Rd
& 8) << 4;
8889 inst
.instruction
|= (Rd
& 7);
8890 inst
.instruction
|= Rn
<< 3;
8896 constraint (Rd
== REG_PC
, BAD_PC
);
8897 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8898 constraint (Rs
== REG_PC
, BAD_PC
);
8899 reject_bad_reg (Rn
);
8901 /* If we get here, it can't be done in 16 bits. */
8902 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8903 _("shift must be constant"));
8904 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8905 inst
.instruction
|= Rd
<< 8;
8906 inst
.instruction
|= Rs
<< 16;
8907 encode_thumb32_shifted_operand (2);
8912 constraint (inst
.instruction
== T_MNEM_adds
8913 || inst
.instruction
== T_MNEM_subs
,
8916 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8918 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8919 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8922 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8924 inst
.instruction
|= (Rd
<< 4) | Rs
;
8925 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8929 Rn
= inst
.operands
[2].reg
;
8930 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8932 /* We now have Rd, Rs, and Rn set to registers. */
8933 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8935 /* Can't do this for SUB. */
8936 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8937 inst
.instruction
= T_OPCODE_ADD_HI
;
8938 inst
.instruction
|= (Rd
& 8) << 4;
8939 inst
.instruction
|= (Rd
& 7);
8941 inst
.instruction
|= Rn
<< 3;
8943 inst
.instruction
|= Rs
<< 3;
8945 constraint (1, _("dest must overlap one source register"));
8949 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8950 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8951 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8961 Rd
= inst
.operands
[0].reg
;
8962 reject_bad_reg (Rd
);
8964 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
8966 /* Defer to section relaxation. */
8967 inst
.relax
= inst
.instruction
;
8968 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8969 inst
.instruction
|= Rd
<< 4;
8971 else if (unified_syntax
&& inst
.size_req
!= 2)
8973 /* Generate a 32-bit opcode. */
8974 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8975 inst
.instruction
|= Rd
<< 8;
8976 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8977 inst
.reloc
.pc_rel
= 1;
8981 /* Generate a 16-bit opcode. */
8982 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8983 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8984 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8985 inst
.reloc
.pc_rel
= 1;
8987 inst
.instruction
|= Rd
<< 4;
8991 /* Arithmetic instructions for which there is just one 16-bit
8992 instruction encoding, and it allows only two low registers.
8993 For maximal compatibility with ARM syntax, we allow three register
8994 operands even when Thumb-32 instructions are not available, as long
8995 as the first two are identical. For instance, both "sbc r0,r1" and
8996 "sbc r0,r0,r1" are allowed. */
9002 Rd
= inst
.operands
[0].reg
;
9003 Rs
= (inst
.operands
[1].present
9004 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9005 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9006 Rn
= inst
.operands
[2].reg
;
9008 reject_bad_reg (Rd
);
9009 reject_bad_reg (Rs
);
9010 if (inst
.operands
[2].isreg
)
9011 reject_bad_reg (Rn
);
9015 if (!inst
.operands
[2].isreg
)
9017 /* For an immediate, we always generate a 32-bit opcode;
9018 section relaxation will shrink it later if possible. */
9019 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9020 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9021 inst
.instruction
|= Rd
<< 8;
9022 inst
.instruction
|= Rs
<< 16;
9023 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9029 /* See if we can do this with a 16-bit instruction. */
9030 if (THUMB_SETS_FLAGS (inst
.instruction
))
9031 narrow
= !in_it_block ();
9033 narrow
= in_it_block ();
9035 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9037 if (inst
.operands
[2].shifted
)
9039 if (inst
.size_req
== 4)
9045 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9046 inst
.instruction
|= Rd
;
9047 inst
.instruction
|= Rn
<< 3;
9051 /* If we get here, it can't be done in 16 bits. */
9052 constraint (inst
.operands
[2].shifted
9053 && inst
.operands
[2].immisreg
,
9054 _("shift must be constant"));
9055 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9056 inst
.instruction
|= Rd
<< 8;
9057 inst
.instruction
|= Rs
<< 16;
9058 encode_thumb32_shifted_operand (2);
9063 /* On its face this is a lie - the instruction does set the
9064 flags. However, the only supported mnemonic in this mode
9066 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9068 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9069 _("unshifted register required"));
9070 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9071 constraint (Rd
!= Rs
,
9072 _("dest and source1 must be the same register"));
9074 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9075 inst
.instruction
|= Rd
;
9076 inst
.instruction
|= Rn
<< 3;
9080 /* Similarly, but for instructions where the arithmetic operation is
9081 commutative, so we can allow either of them to be different from
9082 the destination operand in a 16-bit instruction. For instance, all
9083 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9090 Rd
= inst
.operands
[0].reg
;
9091 Rs
= (inst
.operands
[1].present
9092 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9093 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9094 Rn
= inst
.operands
[2].reg
;
9096 reject_bad_reg (Rd
);
9097 reject_bad_reg (Rs
);
9098 if (inst
.operands
[2].isreg
)
9099 reject_bad_reg (Rn
);
9103 if (!inst
.operands
[2].isreg
)
9105 /* For an immediate, we always generate a 32-bit opcode;
9106 section relaxation will shrink it later if possible. */
9107 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9108 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9109 inst
.instruction
|= Rd
<< 8;
9110 inst
.instruction
|= Rs
<< 16;
9111 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9117 /* See if we can do this with a 16-bit instruction. */
9118 if (THUMB_SETS_FLAGS (inst
.instruction
))
9119 narrow
= !in_it_block ();
9121 narrow
= in_it_block ();
9123 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9125 if (inst
.operands
[2].shifted
)
9127 if (inst
.size_req
== 4)
9134 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9135 inst
.instruction
|= Rd
;
9136 inst
.instruction
|= Rn
<< 3;
9141 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9142 inst
.instruction
|= Rd
;
9143 inst
.instruction
|= Rs
<< 3;
9148 /* If we get here, it can't be done in 16 bits. */
9149 constraint (inst
.operands
[2].shifted
9150 && inst
.operands
[2].immisreg
,
9151 _("shift must be constant"));
9152 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9153 inst
.instruction
|= Rd
<< 8;
9154 inst
.instruction
|= Rs
<< 16;
9155 encode_thumb32_shifted_operand (2);
9160 /* On its face this is a lie - the instruction does set the
9161 flags. However, the only supported mnemonic in this mode
9163 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9165 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9166 _("unshifted register required"));
9167 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9169 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9170 inst
.instruction
|= Rd
;
9173 inst
.instruction
|= Rn
<< 3;
9175 inst
.instruction
|= Rs
<< 3;
9177 constraint (1, _("dest must overlap one source register"));
9184 if (inst
.operands
[0].present
)
9186 constraint ((inst
.instruction
& 0xf0) != 0x40
9187 && inst
.operands
[0].imm
!= 0xf,
9188 _("bad barrier type"));
9189 inst
.instruction
|= inst
.operands
[0].imm
;
9192 inst
.instruction
|= 0xf;
9199 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9200 constraint (msb
> 32, _("bit-field extends past end of register"));
9201 /* The instruction encoding stores the LSB and MSB,
9202 not the LSB and width. */
9203 Rd
= inst
.operands
[0].reg
;
9204 reject_bad_reg (Rd
);
9205 inst
.instruction
|= Rd
<< 8;
9206 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9207 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9208 inst
.instruction
|= msb
- 1;
9217 Rd
= inst
.operands
[0].reg
;
9218 reject_bad_reg (Rd
);
9220 /* #0 in second position is alternative syntax for bfc, which is
9221 the same instruction but with REG_PC in the Rm field. */
9222 if (!inst
.operands
[1].isreg
)
9226 Rn
= inst
.operands
[1].reg
;
9227 reject_bad_reg (Rn
);
9230 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9231 constraint (msb
> 32, _("bit-field extends past end of register"));
9232 /* The instruction encoding stores the LSB and MSB,
9233 not the LSB and width. */
9234 inst
.instruction
|= Rd
<< 8;
9235 inst
.instruction
|= Rn
<< 16;
9236 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9237 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9238 inst
.instruction
|= msb
- 1;
9246 Rd
= inst
.operands
[0].reg
;
9247 Rn
= inst
.operands
[1].reg
;
9249 reject_bad_reg (Rd
);
9250 reject_bad_reg (Rn
);
9252 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9253 _("bit-field extends past end of register"));
9254 inst
.instruction
|= Rd
<< 8;
9255 inst
.instruction
|= Rn
<< 16;
9256 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9257 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9258 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9261 /* ARM V5 Thumb BLX (argument parse)
9262 BLX <target_addr> which is BLX(1)
9263 BLX <Rm> which is BLX(2)
9264 Unfortunately, there are two different opcodes for this mnemonic.
9265 So, the insns[].value is not used, and the code here zaps values
9266 into inst.instruction.
9268 ??? How to take advantage of the additional two bits of displacement
9269 available in Thumb32 mode? Need new relocation? */
9274 set_it_insn_type_last ();
9276 if (inst
.operands
[0].isreg
)
9278 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9279 /* We have a register, so this is BLX(2). */
9280 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9284 /* No register. This must be BLX(1). */
9285 inst
.instruction
= 0xf000e800;
9286 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9287 inst
.reloc
.pc_rel
= 1;
9298 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9302 /* Conditional branches inside IT blocks are encoded as unconditional
9309 if (cond
!= COND_ALWAYS
)
9310 opcode
= T_MNEM_bcond
;
9312 opcode
= inst
.instruction
;
9314 if (unified_syntax
&& inst
.size_req
== 4)
9316 inst
.instruction
= THUMB_OP32(opcode
);
9317 if (cond
== COND_ALWAYS
)
9318 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9321 gas_assert (cond
!= 0xF);
9322 inst
.instruction
|= cond
<< 22;
9323 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9328 inst
.instruction
= THUMB_OP16(opcode
);
9329 if (cond
== COND_ALWAYS
)
9330 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9333 inst
.instruction
|= cond
<< 8;
9334 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9336 /* Allow section relaxation. */
9337 if (unified_syntax
&& inst
.size_req
!= 2)
9338 inst
.relax
= opcode
;
9341 inst
.reloc
.pc_rel
= 1;
9347 constraint (inst
.cond
!= COND_ALWAYS
,
9348 _("instruction is always unconditional"));
9349 if (inst
.operands
[0].present
)
9351 constraint (inst
.operands
[0].imm
> 255,
9352 _("immediate value out of range"));
9353 inst
.instruction
|= inst
.operands
[0].imm
;
9354 set_it_insn_type (NEUTRAL_IT_INSN
);
9359 do_t_branch23 (void)
9361 set_it_insn_type_last ();
9362 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9363 inst
.reloc
.pc_rel
= 1;
9365 #if defined(OBJ_COFF)
9366 /* If the destination of the branch is a defined symbol which does not have
9367 the THUMB_FUNC attribute, then we must be calling a function which has
9368 the (interfacearm) attribute. We look for the Thumb entry point to that
9369 function and change the branch to refer to that function instead. */
9370 if ( inst
.reloc
.exp
.X_op
== O_symbol
9371 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9372 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9373 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9374 inst
.reloc
.exp
.X_add_symbol
=
9375 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9382 set_it_insn_type_last ();
9383 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9384 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9385 should cause the alignment to be checked once it is known. This is
9386 because BX PC only works if the instruction is word aligned. */
9394 set_it_insn_type_last ();
9395 Rm
= inst
.operands
[0].reg
;
9396 reject_bad_reg (Rm
);
9397 inst
.instruction
|= Rm
<< 16;
9406 Rd
= inst
.operands
[0].reg
;
9407 Rm
= inst
.operands
[1].reg
;
9409 reject_bad_reg (Rd
);
9410 reject_bad_reg (Rm
);
9412 inst
.instruction
|= Rd
<< 8;
9413 inst
.instruction
|= Rm
<< 16;
9414 inst
.instruction
|= Rm
;
9420 set_it_insn_type (OUTSIDE_IT_INSN
);
9421 inst
.instruction
|= inst
.operands
[0].imm
;
9427 set_it_insn_type (OUTSIDE_IT_INSN
);
9429 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9430 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9432 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9433 inst
.instruction
= 0xf3af8000;
9434 inst
.instruction
|= imod
<< 9;
9435 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9436 if (inst
.operands
[1].present
)
9437 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9441 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9442 && (inst
.operands
[0].imm
& 4),
9443 _("selected processor does not support 'A' form "
9444 "of this instruction"));
9445 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9446 _("Thumb does not support the 2-argument "
9447 "form of this instruction"));
9448 inst
.instruction
|= inst
.operands
[0].imm
;
9452 /* THUMB CPY instruction (argument parse). */
9457 if (inst
.size_req
== 4)
9459 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9460 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9461 inst
.instruction
|= inst
.operands
[1].reg
;
9465 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9466 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9467 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9474 set_it_insn_type (OUTSIDE_IT_INSN
);
9475 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9476 inst
.instruction
|= inst
.operands
[0].reg
;
9477 inst
.reloc
.pc_rel
= 1;
9478 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9484 inst
.instruction
|= inst
.operands
[0].imm
;
9490 unsigned Rd
, Rn
, Rm
;
9492 Rd
= inst
.operands
[0].reg
;
9493 Rn
= (inst
.operands
[1].present
9494 ? inst
.operands
[1].reg
: Rd
);
9495 Rm
= inst
.operands
[2].reg
;
9497 reject_bad_reg (Rd
);
9498 reject_bad_reg (Rn
);
9499 reject_bad_reg (Rm
);
9501 inst
.instruction
|= Rd
<< 8;
9502 inst
.instruction
|= Rn
<< 16;
9503 inst
.instruction
|= Rm
;
9509 if (unified_syntax
&& inst
.size_req
== 4)
9510 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9512 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9518 unsigned int cond
= inst
.operands
[0].imm
;
9520 set_it_insn_type (IT_INSN
);
9521 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9524 /* If the condition is a negative condition, invert the mask. */
9525 if ((cond
& 0x1) == 0x0)
9527 unsigned int mask
= inst
.instruction
& 0x000f;
9529 if ((mask
& 0x7) == 0)
9530 /* no conversion needed */;
9531 else if ((mask
& 0x3) == 0)
9533 else if ((mask
& 0x1) == 0)
9538 inst
.instruction
&= 0xfff0;
9539 inst
.instruction
|= mask
;
9542 inst
.instruction
|= cond
<< 4;
9545 /* Helper function used for both push/pop and ldm/stm. */
9547 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9551 load
= (inst
.instruction
& (1 << 20)) != 0;
9553 if (mask
& (1 << 13))
9554 inst
.error
= _("SP not allowed in register list");
9557 if (mask
& (1 << 15))
9559 if (mask
& (1 << 14))
9560 inst
.error
= _("LR and PC should not both be in register list");
9562 set_it_insn_type_last ();
9565 if ((mask
& (1 << base
)) != 0
9567 as_warn (_("base register should not be in register list "
9568 "when written back"));
9572 if (mask
& (1 << 15))
9573 inst
.error
= _("PC not allowed in register list");
9575 if (mask
& (1 << base
))
9576 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9579 if ((mask
& (mask
- 1)) == 0)
9581 /* Single register transfers implemented as str/ldr. */
9584 if (inst
.instruction
& (1 << 23))
9585 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9587 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9591 if (inst
.instruction
& (1 << 23))
9592 inst
.instruction
= 0x00800000; /* ia -> [base] */
9594 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9597 inst
.instruction
|= 0xf8400000;
9599 inst
.instruction
|= 0x00100000;
9601 mask
= ffs (mask
) - 1;
9605 inst
.instruction
|= WRITE_BACK
;
9607 inst
.instruction
|= mask
;
9608 inst
.instruction
|= base
<< 16;
9614 /* This really doesn't seem worth it. */
9615 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9616 _("expression too complex"));
9617 constraint (inst
.operands
[1].writeback
,
9618 _("Thumb load/store multiple does not support {reglist}^"));
9626 /* See if we can use a 16-bit instruction. */
9627 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9628 && inst
.size_req
!= 4
9629 && !(inst
.operands
[1].imm
& ~0xff))
9631 mask
= 1 << inst
.operands
[0].reg
;
9633 if (inst
.operands
[0].reg
<= 7
9634 && (inst
.instruction
== T_MNEM_stmia
9635 ? inst
.operands
[0].writeback
9636 : (inst
.operands
[0].writeback
9637 == !(inst
.operands
[1].imm
& mask
))))
9639 if (inst
.instruction
== T_MNEM_stmia
9640 && (inst
.operands
[1].imm
& mask
)
9641 && (inst
.operands
[1].imm
& (mask
- 1)))
9642 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9643 inst
.operands
[0].reg
);
9645 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9646 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9647 inst
.instruction
|= inst
.operands
[1].imm
;
9650 else if (inst
.operands
[0] .reg
== REG_SP
9651 && inst
.operands
[0].writeback
)
9653 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9654 ? T_MNEM_push
: T_MNEM_pop
);
9655 inst
.instruction
|= inst
.operands
[1].imm
;
9662 if (inst
.instruction
< 0xffff)
9663 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9665 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9666 inst
.operands
[0].writeback
);
9671 constraint (inst
.operands
[0].reg
> 7
9672 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9673 constraint (inst
.instruction
!= T_MNEM_ldmia
9674 && inst
.instruction
!= T_MNEM_stmia
,
9675 _("Thumb-2 instruction only valid in unified syntax"));
9676 if (inst
.instruction
== T_MNEM_stmia
)
9678 if (!inst
.operands
[0].writeback
)
9679 as_warn (_("this instruction will write back the base register"));
9680 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9681 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9682 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9683 inst
.operands
[0].reg
);
9687 if (!inst
.operands
[0].writeback
9688 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9689 as_warn (_("this instruction will write back the base register"));
9690 else if (inst
.operands
[0].writeback
9691 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9692 as_warn (_("this instruction will not write back the base register"));
9695 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9696 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9697 inst
.instruction
|= inst
.operands
[1].imm
;
9704 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9705 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9706 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9707 || inst
.operands
[1].negative
,
9710 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9711 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9712 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9718 if (!inst
.operands
[1].present
)
9720 constraint (inst
.operands
[0].reg
== REG_LR
,
9721 _("r14 not allowed as first register "
9722 "when second register is omitted"));
9723 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9725 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9728 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9729 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9730 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9736 unsigned long opcode
;
9739 if (inst
.operands
[0].isreg
9740 && !inst
.operands
[0].preind
9741 && inst
.operands
[0].reg
== REG_PC
)
9742 set_it_insn_type_last ();
9744 opcode
= inst
.instruction
;
9747 if (!inst
.operands
[1].isreg
)
9749 if (opcode
<= 0xffff)
9750 inst
.instruction
= THUMB_OP32 (opcode
);
9751 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9754 if (inst
.operands
[1].isreg
9755 && !inst
.operands
[1].writeback
9756 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9757 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9759 && inst
.size_req
!= 4)
9761 /* Insn may have a 16-bit form. */
9762 Rn
= inst
.operands
[1].reg
;
9763 if (inst
.operands
[1].immisreg
)
9765 inst
.instruction
= THUMB_OP16 (opcode
);
9767 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9770 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9771 && opcode
!= T_MNEM_ldrsb
)
9772 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9773 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9780 if (inst
.reloc
.pc_rel
)
9781 opcode
= T_MNEM_ldr_pc2
;
9783 opcode
= T_MNEM_ldr_pc
;
9787 if (opcode
== T_MNEM_ldr
)
9788 opcode
= T_MNEM_ldr_sp
;
9790 opcode
= T_MNEM_str_sp
;
9792 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9796 inst
.instruction
= inst
.operands
[0].reg
;
9797 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9799 inst
.instruction
|= THUMB_OP16 (opcode
);
9800 if (inst
.size_req
== 2)
9801 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9803 inst
.relax
= opcode
;
9807 /* Definitely a 32-bit variant. */
9808 inst
.instruction
= THUMB_OP32 (opcode
);
9809 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9810 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9814 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9816 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9818 /* Only [Rn,Rm] is acceptable. */
9819 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9820 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9821 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9822 || inst
.operands
[1].negative
,
9823 _("Thumb does not support this addressing mode"));
9824 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9828 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9829 if (!inst
.operands
[1].isreg
)
9830 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9833 constraint (!inst
.operands
[1].preind
9834 || inst
.operands
[1].shifted
9835 || inst
.operands
[1].writeback
,
9836 _("Thumb does not support this addressing mode"));
9837 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9839 constraint (inst
.instruction
& 0x0600,
9840 _("byte or halfword not valid for base register"));
9841 constraint (inst
.operands
[1].reg
== REG_PC
9842 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9843 _("r15 based store not allowed"));
9844 constraint (inst
.operands
[1].immisreg
,
9845 _("invalid base register for register offset"));
9847 if (inst
.operands
[1].reg
== REG_PC
)
9848 inst
.instruction
= T_OPCODE_LDR_PC
;
9849 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9850 inst
.instruction
= T_OPCODE_LDR_SP
;
9852 inst
.instruction
= T_OPCODE_STR_SP
;
9854 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9855 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9859 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9860 if (!inst
.operands
[1].immisreg
)
9862 /* Immediate offset. */
9863 inst
.instruction
|= inst
.operands
[0].reg
;
9864 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9865 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9869 /* Register offset. */
9870 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9871 constraint (inst
.operands
[1].negative
,
9872 _("Thumb does not support this addressing mode"));
9875 switch (inst
.instruction
)
9877 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9878 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9879 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9880 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9881 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9882 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9883 case 0x5600 /* ldrsb */:
9884 case 0x5e00 /* ldrsh */: break;
9888 inst
.instruction
|= inst
.operands
[0].reg
;
9889 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9890 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9896 if (!inst
.operands
[1].present
)
9898 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9899 constraint (inst
.operands
[0].reg
== REG_LR
,
9900 _("r14 not allowed here"));
9902 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9903 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9904 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9910 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9911 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9917 unsigned Rd
, Rn
, Rm
, Ra
;
9919 Rd
= inst
.operands
[0].reg
;
9920 Rn
= inst
.operands
[1].reg
;
9921 Rm
= inst
.operands
[2].reg
;
9922 Ra
= inst
.operands
[3].reg
;
9924 reject_bad_reg (Rd
);
9925 reject_bad_reg (Rn
);
9926 reject_bad_reg (Rm
);
9927 reject_bad_reg (Ra
);
9929 inst
.instruction
|= Rd
<< 8;
9930 inst
.instruction
|= Rn
<< 16;
9931 inst
.instruction
|= Rm
;
9932 inst
.instruction
|= Ra
<< 12;
9938 unsigned RdLo
, RdHi
, Rn
, Rm
;
9940 RdLo
= inst
.operands
[0].reg
;
9941 RdHi
= inst
.operands
[1].reg
;
9942 Rn
= inst
.operands
[2].reg
;
9943 Rm
= inst
.operands
[3].reg
;
9945 reject_bad_reg (RdLo
);
9946 reject_bad_reg (RdHi
);
9947 reject_bad_reg (Rn
);
9948 reject_bad_reg (Rm
);
9950 inst
.instruction
|= RdLo
<< 12;
9951 inst
.instruction
|= RdHi
<< 8;
9952 inst
.instruction
|= Rn
<< 16;
9953 inst
.instruction
|= Rm
;
9961 Rn
= inst
.operands
[0].reg
;
9962 Rm
= inst
.operands
[1].reg
;
9965 set_it_insn_type_last ();
9969 int r0off
= (inst
.instruction
== T_MNEM_mov
9970 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9971 unsigned long opcode
;
9973 bfd_boolean low_regs
;
9975 low_regs
= (Rn
<= 7 && Rm
<= 7);
9976 opcode
= inst
.instruction
;
9978 narrow
= opcode
!= T_MNEM_movs
;
9980 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9981 if (inst
.size_req
== 4
9982 || inst
.operands
[1].shifted
)
9985 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9986 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
9987 && !inst
.operands
[1].shifted
9991 inst
.instruction
= T2_SUBS_PC_LR
;
9995 if (opcode
== T_MNEM_cmp
)
9997 constraint (Rn
== REG_PC
, BAD_PC
);
10000 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10002 warn_deprecated_sp (Rm
);
10003 /* R15 was documented as a valid choice for Rm in ARMv6,
10004 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10005 tools reject R15, so we do too. */
10006 constraint (Rm
== REG_PC
, BAD_PC
);
10009 reject_bad_reg (Rm
);
10011 else if (opcode
== T_MNEM_mov
10012 || opcode
== T_MNEM_movs
)
10014 if (inst
.operands
[1].isreg
)
10016 if (opcode
== T_MNEM_movs
)
10018 reject_bad_reg (Rn
);
10019 reject_bad_reg (Rm
);
10021 else if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10022 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10023 reject_bad_reg (Rm
);
10026 reject_bad_reg (Rn
);
10029 if (!inst
.operands
[1].isreg
)
10031 /* Immediate operand. */
10032 if (!in_it_block () && opcode
== T_MNEM_mov
)
10034 if (low_regs
&& narrow
)
10036 inst
.instruction
= THUMB_OP16 (opcode
);
10037 inst
.instruction
|= Rn
<< 8;
10038 if (inst
.size_req
== 2)
10039 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10041 inst
.relax
= opcode
;
10045 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10046 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10047 inst
.instruction
|= Rn
<< r0off
;
10048 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10051 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10052 && (inst
.instruction
== T_MNEM_mov
10053 || inst
.instruction
== T_MNEM_movs
))
10055 /* Register shifts are encoded as separate shift instructions. */
10056 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10058 if (in_it_block ())
10063 if (inst
.size_req
== 4)
10066 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10072 switch (inst
.operands
[1].shift_kind
)
10075 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10078 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10081 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10084 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10090 inst
.instruction
= opcode
;
10093 inst
.instruction
|= Rn
;
10094 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10099 inst
.instruction
|= CONDS_BIT
;
10101 inst
.instruction
|= Rn
<< 8;
10102 inst
.instruction
|= Rm
<< 16;
10103 inst
.instruction
|= inst
.operands
[1].imm
;
10108 /* Some mov with immediate shift have narrow variants.
10109 Register shifts are handled above. */
10110 if (low_regs
&& inst
.operands
[1].shifted
10111 && (inst
.instruction
== T_MNEM_mov
10112 || inst
.instruction
== T_MNEM_movs
))
10114 if (in_it_block ())
10115 narrow
= (inst
.instruction
== T_MNEM_mov
);
10117 narrow
= (inst
.instruction
== T_MNEM_movs
);
10122 switch (inst
.operands
[1].shift_kind
)
10124 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10125 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10126 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10127 default: narrow
= FALSE
; break;
10133 inst
.instruction
|= Rn
;
10134 inst
.instruction
|= Rm
<< 3;
10135 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10139 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10140 inst
.instruction
|= Rn
<< r0off
;
10141 encode_thumb32_shifted_operand (1);
10145 switch (inst
.instruction
)
10148 inst
.instruction
= T_OPCODE_MOV_HR
;
10149 inst
.instruction
|= (Rn
& 0x8) << 4;
10150 inst
.instruction
|= (Rn
& 0x7);
10151 inst
.instruction
|= Rm
<< 3;
10155 /* We know we have low registers at this point.
10156 Generate ADD Rd, Rs, #0. */
10157 inst
.instruction
= T_OPCODE_ADD_I3
;
10158 inst
.instruction
|= Rn
;
10159 inst
.instruction
|= Rm
<< 3;
10165 inst
.instruction
= T_OPCODE_CMP_LR
;
10166 inst
.instruction
|= Rn
;
10167 inst
.instruction
|= Rm
<< 3;
10171 inst
.instruction
= T_OPCODE_CMP_HR
;
10172 inst
.instruction
|= (Rn
& 0x8) << 4;
10173 inst
.instruction
|= (Rn
& 0x7);
10174 inst
.instruction
|= Rm
<< 3;
10181 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10182 if (inst
.operands
[1].isreg
)
10184 if (Rn
< 8 && Rm
< 8)
10186 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10187 since a MOV instruction produces unpredictable results. */
10188 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10189 inst
.instruction
= T_OPCODE_ADD_I3
;
10191 inst
.instruction
= T_OPCODE_CMP_LR
;
10193 inst
.instruction
|= Rn
;
10194 inst
.instruction
|= Rm
<< 3;
10198 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10199 inst
.instruction
= T_OPCODE_MOV_HR
;
10201 inst
.instruction
= T_OPCODE_CMP_HR
;
10207 constraint (Rn
> 7,
10208 _("only lo regs allowed with immediate"));
10209 inst
.instruction
|= Rn
<< 8;
10210 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10221 top
= (inst
.instruction
& 0x00800000) != 0;
10222 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10224 constraint (top
, _(":lower16: not allowed this instruction"));
10225 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10227 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10229 constraint (!top
, _(":upper16: not allowed this instruction"));
10230 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10233 Rd
= inst
.operands
[0].reg
;
10234 reject_bad_reg (Rd
);
10236 inst
.instruction
|= Rd
<< 8;
10237 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10239 imm
= inst
.reloc
.exp
.X_add_number
;
10240 inst
.instruction
|= (imm
& 0xf000) << 4;
10241 inst
.instruction
|= (imm
& 0x0800) << 15;
10242 inst
.instruction
|= (imm
& 0x0700) << 4;
10243 inst
.instruction
|= (imm
& 0x00ff);
10248 do_t_mvn_tst (void)
10252 Rn
= inst
.operands
[0].reg
;
10253 Rm
= inst
.operands
[1].reg
;
10255 if (inst
.instruction
== T_MNEM_cmp
10256 || inst
.instruction
== T_MNEM_cmn
)
10257 constraint (Rn
== REG_PC
, BAD_PC
);
10259 reject_bad_reg (Rn
);
10260 reject_bad_reg (Rm
);
10262 if (unified_syntax
)
10264 int r0off
= (inst
.instruction
== T_MNEM_mvn
10265 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10266 bfd_boolean narrow
;
10268 if (inst
.size_req
== 4
10269 || inst
.instruction
> 0xffff
10270 || inst
.operands
[1].shifted
10271 || Rn
> 7 || Rm
> 7)
10273 else if (inst
.instruction
== T_MNEM_cmn
)
10275 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10276 narrow
= !in_it_block ();
10278 narrow
= in_it_block ();
10280 if (!inst
.operands
[1].isreg
)
10282 /* For an immediate, we always generate a 32-bit opcode;
10283 section relaxation will shrink it later if possible. */
10284 if (inst
.instruction
< 0xffff)
10285 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10286 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10287 inst
.instruction
|= Rn
<< r0off
;
10288 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10292 /* See if we can do this with a 16-bit instruction. */
10295 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10296 inst
.instruction
|= Rn
;
10297 inst
.instruction
|= Rm
<< 3;
10301 constraint (inst
.operands
[1].shifted
10302 && inst
.operands
[1].immisreg
,
10303 _("shift must be constant"));
10304 if (inst
.instruction
< 0xffff)
10305 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10306 inst
.instruction
|= Rn
<< r0off
;
10307 encode_thumb32_shifted_operand (1);
10313 constraint (inst
.instruction
> 0xffff
10314 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10315 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10316 _("unshifted register required"));
10317 constraint (Rn
> 7 || Rm
> 7,
10320 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10321 inst
.instruction
|= Rn
;
10322 inst
.instruction
|= Rm
<< 3;
10332 if (do_vfp_nsyn_mrs () == SUCCESS
)
10335 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10338 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10339 _("selected processor does not support "
10340 "requested special purpose register"));
10344 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10345 _("selected processor does not support "
10346 "requested special purpose register"));
10347 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10348 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10349 _("'CPSR' or 'SPSR' expected"));
10352 Rd
= inst
.operands
[0].reg
;
10353 reject_bad_reg (Rd
);
10355 inst
.instruction
|= Rd
<< 8;
10356 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10357 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10366 if (do_vfp_nsyn_msr () == SUCCESS
)
10369 constraint (!inst
.operands
[1].isreg
,
10370 _("Thumb encoding does not support an immediate here"));
10371 flags
= inst
.operands
[0].imm
;
10374 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10375 _("selected processor does not support "
10376 "requested special purpose register"));
10380 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10381 _("selected processor does not support "
10382 "requested special purpose register"));
10386 Rn
= inst
.operands
[1].reg
;
10387 reject_bad_reg (Rn
);
10389 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10390 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10391 inst
.instruction
|= (flags
& 0xff);
10392 inst
.instruction
|= Rn
<< 16;
10398 bfd_boolean narrow
;
10399 unsigned Rd
, Rn
, Rm
;
10401 if (!inst
.operands
[2].present
)
10402 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10404 Rd
= inst
.operands
[0].reg
;
10405 Rn
= inst
.operands
[1].reg
;
10406 Rm
= inst
.operands
[2].reg
;
10408 if (unified_syntax
)
10410 if (inst
.size_req
== 4
10416 else if (inst
.instruction
== T_MNEM_muls
)
10417 narrow
= !in_it_block ();
10419 narrow
= in_it_block ();
10423 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10424 constraint (Rn
> 7 || Rm
> 7,
10431 /* 16-bit MULS/Conditional MUL. */
10432 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10433 inst
.instruction
|= Rd
;
10436 inst
.instruction
|= Rm
<< 3;
10438 inst
.instruction
|= Rn
<< 3;
10440 constraint (1, _("dest must overlap one source register"));
10444 constraint (inst
.instruction
!= T_MNEM_mul
,
10445 _("Thumb-2 MUL must not set flags"));
10447 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10448 inst
.instruction
|= Rd
<< 8;
10449 inst
.instruction
|= Rn
<< 16;
10450 inst
.instruction
|= Rm
<< 0;
10452 reject_bad_reg (Rd
);
10453 reject_bad_reg (Rn
);
10454 reject_bad_reg (Rm
);
10461 unsigned RdLo
, RdHi
, Rn
, Rm
;
10463 RdLo
= inst
.operands
[0].reg
;
10464 RdHi
= inst
.operands
[1].reg
;
10465 Rn
= inst
.operands
[2].reg
;
10466 Rm
= inst
.operands
[3].reg
;
10468 reject_bad_reg (RdLo
);
10469 reject_bad_reg (RdHi
);
10470 reject_bad_reg (Rn
);
10471 reject_bad_reg (Rm
);
10473 inst
.instruction
|= RdLo
<< 12;
10474 inst
.instruction
|= RdHi
<< 8;
10475 inst
.instruction
|= Rn
<< 16;
10476 inst
.instruction
|= Rm
;
10479 as_tsktsk (_("rdhi and rdlo must be different"));
10485 set_it_insn_type (NEUTRAL_IT_INSN
);
10487 if (unified_syntax
)
10489 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10491 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10492 inst
.instruction
|= inst
.operands
[0].imm
;
10496 /* PR9722: Check for Thumb2 availability before
10497 generating a thumb2 nop instruction. */
10498 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
10500 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10501 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10504 inst
.instruction
= 0x46c0;
10509 constraint (inst
.operands
[0].present
,
10510 _("Thumb does not support NOP with hints"));
10511 inst
.instruction
= 0x46c0;
10518 if (unified_syntax
)
10520 bfd_boolean narrow
;
10522 if (THUMB_SETS_FLAGS (inst
.instruction
))
10523 narrow
= !in_it_block ();
10525 narrow
= in_it_block ();
10526 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10528 if (inst
.size_req
== 4)
10533 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10534 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10535 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10539 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10540 inst
.instruction
|= inst
.operands
[0].reg
;
10541 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10546 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10548 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10550 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10551 inst
.instruction
|= inst
.operands
[0].reg
;
10552 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10561 Rd
= inst
.operands
[0].reg
;
10562 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10564 reject_bad_reg (Rd
);
10565 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10566 reject_bad_reg (Rn
);
10568 inst
.instruction
|= Rd
<< 8;
10569 inst
.instruction
|= Rn
<< 16;
10571 if (!inst
.operands
[2].isreg
)
10573 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10574 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10580 Rm
= inst
.operands
[2].reg
;
10581 reject_bad_reg (Rm
);
10583 constraint (inst
.operands
[2].shifted
10584 && inst
.operands
[2].immisreg
,
10585 _("shift must be constant"));
10586 encode_thumb32_shifted_operand (2);
10593 unsigned Rd
, Rn
, Rm
;
10595 Rd
= inst
.operands
[0].reg
;
10596 Rn
= inst
.operands
[1].reg
;
10597 Rm
= inst
.operands
[2].reg
;
10599 reject_bad_reg (Rd
);
10600 reject_bad_reg (Rn
);
10601 reject_bad_reg (Rm
);
10603 inst
.instruction
|= Rd
<< 8;
10604 inst
.instruction
|= Rn
<< 16;
10605 inst
.instruction
|= Rm
;
10606 if (inst
.operands
[3].present
)
10608 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10609 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10610 _("expression too complex"));
10611 inst
.instruction
|= (val
& 0x1c) << 10;
10612 inst
.instruction
|= (val
& 0x03) << 6;
10619 if (!inst
.operands
[3].present
)
10623 inst
.instruction
&= ~0x00000020;
10625 /* PR 10168. Swap the Rm and Rn registers. */
10626 Rtmp
= inst
.operands
[1].reg
;
10627 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10628 inst
.operands
[2].reg
= Rtmp
;
10636 if (inst
.operands
[0].immisreg
)
10637 reject_bad_reg (inst
.operands
[0].imm
);
10639 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10643 do_t_push_pop (void)
10647 constraint (inst
.operands
[0].writeback
,
10648 _("push/pop do not support {reglist}^"));
10649 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10650 _("expression too complex"));
10652 mask
= inst
.operands
[0].imm
;
10653 if ((mask
& ~0xff) == 0)
10654 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10655 else if ((inst
.instruction
== T_MNEM_push
10656 && (mask
& ~0xff) == 1 << REG_LR
)
10657 || (inst
.instruction
== T_MNEM_pop
10658 && (mask
& ~0xff) == 1 << REG_PC
))
10660 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10661 inst
.instruction
|= THUMB_PP_PC_LR
;
10662 inst
.instruction
|= mask
& 0xff;
10664 else if (unified_syntax
)
10666 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10667 encode_thumb2_ldmstm (13, mask
, TRUE
);
10671 inst
.error
= _("invalid register list to push/pop instruction");
10681 Rd
= inst
.operands
[0].reg
;
10682 Rm
= inst
.operands
[1].reg
;
10684 reject_bad_reg (Rd
);
10685 reject_bad_reg (Rm
);
10687 inst
.instruction
|= Rd
<< 8;
10688 inst
.instruction
|= Rm
<< 16;
10689 inst
.instruction
|= Rm
;
10697 Rd
= inst
.operands
[0].reg
;
10698 Rm
= inst
.operands
[1].reg
;
10700 reject_bad_reg (Rd
);
10701 reject_bad_reg (Rm
);
10703 if (Rd
<= 7 && Rm
<= 7
10704 && inst
.size_req
!= 4)
10706 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10707 inst
.instruction
|= Rd
;
10708 inst
.instruction
|= Rm
<< 3;
10710 else if (unified_syntax
)
10712 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10713 inst
.instruction
|= Rd
<< 8;
10714 inst
.instruction
|= Rm
<< 16;
10715 inst
.instruction
|= Rm
;
10718 inst
.error
= BAD_HIREG
;
10726 Rd
= inst
.operands
[0].reg
;
10727 Rm
= inst
.operands
[1].reg
;
10729 reject_bad_reg (Rd
);
10730 reject_bad_reg (Rm
);
10732 inst
.instruction
|= Rd
<< 8;
10733 inst
.instruction
|= Rm
;
10741 Rd
= inst
.operands
[0].reg
;
10742 Rs
= (inst
.operands
[1].present
10743 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10744 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10746 reject_bad_reg (Rd
);
10747 reject_bad_reg (Rs
);
10748 if (inst
.operands
[2].isreg
)
10749 reject_bad_reg (inst
.operands
[2].reg
);
10751 inst
.instruction
|= Rd
<< 8;
10752 inst
.instruction
|= Rs
<< 16;
10753 if (!inst
.operands
[2].isreg
)
10755 bfd_boolean narrow
;
10757 if ((inst
.instruction
& 0x00100000) != 0)
10758 narrow
= !in_it_block ();
10760 narrow
= in_it_block ();
10762 if (Rd
> 7 || Rs
> 7)
10765 if (inst
.size_req
== 4 || !unified_syntax
)
10768 if (inst
.reloc
.exp
.X_op
!= O_constant
10769 || inst
.reloc
.exp
.X_add_number
!= 0)
10772 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10773 relaxation, but it doesn't seem worth the hassle. */
10776 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10777 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10778 inst
.instruction
|= Rs
<< 3;
10779 inst
.instruction
|= Rd
;
10783 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10784 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10788 encode_thumb32_shifted_operand (2);
10794 set_it_insn_type (OUTSIDE_IT_INSN
);
10795 if (inst
.operands
[0].imm
)
10796 inst
.instruction
|= 0x8;
10802 if (!inst
.operands
[1].present
)
10803 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10805 if (unified_syntax
)
10807 bfd_boolean narrow
;
10810 switch (inst
.instruction
)
10813 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10815 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10817 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10819 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10823 if (THUMB_SETS_FLAGS (inst
.instruction
))
10824 narrow
= !in_it_block ();
10826 narrow
= in_it_block ();
10827 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10829 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10831 if (inst
.operands
[2].isreg
10832 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10833 || inst
.operands
[2].reg
> 7))
10835 if (inst
.size_req
== 4)
10838 reject_bad_reg (inst
.operands
[0].reg
);
10839 reject_bad_reg (inst
.operands
[1].reg
);
10843 if (inst
.operands
[2].isreg
)
10845 reject_bad_reg (inst
.operands
[2].reg
);
10846 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10847 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10848 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10849 inst
.instruction
|= inst
.operands
[2].reg
;
10853 inst
.operands
[1].shifted
= 1;
10854 inst
.operands
[1].shift_kind
= shift_kind
;
10855 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10856 ? T_MNEM_movs
: T_MNEM_mov
);
10857 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10858 encode_thumb32_shifted_operand (1);
10859 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10860 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10865 if (inst
.operands
[2].isreg
)
10867 switch (shift_kind
)
10869 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10870 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10871 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10872 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10876 inst
.instruction
|= inst
.operands
[0].reg
;
10877 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10881 switch (shift_kind
)
10883 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10884 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10885 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10888 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10889 inst
.instruction
|= inst
.operands
[0].reg
;
10890 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10896 constraint (inst
.operands
[0].reg
> 7
10897 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10898 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10900 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10902 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10903 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10904 _("source1 and dest must be same register"));
10906 switch (inst
.instruction
)
10908 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10909 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10910 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10911 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10915 inst
.instruction
|= inst
.operands
[0].reg
;
10916 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10920 switch (inst
.instruction
)
10922 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10923 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10924 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10925 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10928 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10929 inst
.instruction
|= inst
.operands
[0].reg
;
10930 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10938 unsigned Rd
, Rn
, Rm
;
10940 Rd
= inst
.operands
[0].reg
;
10941 Rn
= inst
.operands
[1].reg
;
10942 Rm
= inst
.operands
[2].reg
;
10944 reject_bad_reg (Rd
);
10945 reject_bad_reg (Rn
);
10946 reject_bad_reg (Rm
);
10948 inst
.instruction
|= Rd
<< 8;
10949 inst
.instruction
|= Rn
<< 16;
10950 inst
.instruction
|= Rm
;
10956 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10957 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10958 _("expression too complex"));
10959 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10960 inst
.instruction
|= (value
& 0xf000) >> 12;
10961 inst
.instruction
|= (value
& 0x0ff0);
10962 inst
.instruction
|= (value
& 0x000f) << 16;
10966 do_t_ssat_usat (int bias
)
10970 Rd
= inst
.operands
[0].reg
;
10971 Rn
= inst
.operands
[2].reg
;
10973 reject_bad_reg (Rd
);
10974 reject_bad_reg (Rn
);
10976 inst
.instruction
|= Rd
<< 8;
10977 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
10978 inst
.instruction
|= Rn
<< 16;
10980 if (inst
.operands
[3].present
)
10982 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
10984 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10986 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10987 _("expression too complex"));
10989 if (shift_amount
!= 0)
10991 constraint (shift_amount
> 31,
10992 _("shift expression is too large"));
10994 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10995 inst
.instruction
|= 0x00200000; /* sh bit. */
10997 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
10998 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11006 do_t_ssat_usat (1);
11014 Rd
= inst
.operands
[0].reg
;
11015 Rn
= inst
.operands
[2].reg
;
11017 reject_bad_reg (Rd
);
11018 reject_bad_reg (Rn
);
11020 inst
.instruction
|= Rd
<< 8;
11021 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11022 inst
.instruction
|= Rn
<< 16;
11028 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11029 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11030 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11031 || inst
.operands
[2].negative
,
11034 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11035 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11036 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11037 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11043 if (!inst
.operands
[2].present
)
11044 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11046 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11047 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11048 || inst
.operands
[0].reg
== inst
.operands
[3].reg
11049 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
11052 inst
.instruction
|= inst
.operands
[0].reg
;
11053 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11054 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11055 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11061 unsigned Rd
, Rn
, Rm
;
11063 Rd
= inst
.operands
[0].reg
;
11064 Rn
= inst
.operands
[1].reg
;
11065 Rm
= inst
.operands
[2].reg
;
11067 reject_bad_reg (Rd
);
11068 reject_bad_reg (Rn
);
11069 reject_bad_reg (Rm
);
11071 inst
.instruction
|= Rd
<< 8;
11072 inst
.instruction
|= Rn
<< 16;
11073 inst
.instruction
|= Rm
;
11074 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11082 Rd
= inst
.operands
[0].reg
;
11083 Rm
= inst
.operands
[1].reg
;
11085 reject_bad_reg (Rd
);
11086 reject_bad_reg (Rm
);
11088 if (inst
.instruction
<= 0xffff
11089 && inst
.size_req
!= 4
11090 && Rd
<= 7 && Rm
<= 7
11091 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11093 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11094 inst
.instruction
|= Rd
;
11095 inst
.instruction
|= Rm
<< 3;
11097 else if (unified_syntax
)
11099 if (inst
.instruction
<= 0xffff)
11100 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11101 inst
.instruction
|= Rd
<< 8;
11102 inst
.instruction
|= Rm
;
11103 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11107 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11108 _("Thumb encoding does not support rotation"));
11109 constraint (1, BAD_HIREG
);
11116 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11125 half
= (inst
.instruction
& 0x10) != 0;
11126 set_it_insn_type_last ();
11127 constraint (inst
.operands
[0].immisreg
,
11128 _("instruction requires register index"));
11130 Rn
= inst
.operands
[0].reg
;
11131 Rm
= inst
.operands
[0].imm
;
11133 constraint (Rn
== REG_SP
, BAD_SP
);
11134 reject_bad_reg (Rm
);
11136 constraint (!half
&& inst
.operands
[0].shifted
,
11137 _("instruction does not allow shifted index"));
11138 inst
.instruction
|= (Rn
<< 16) | Rm
;
11144 do_t_ssat_usat (0);
11152 Rd
= inst
.operands
[0].reg
;
11153 Rn
= inst
.operands
[2].reg
;
11155 reject_bad_reg (Rd
);
11156 reject_bad_reg (Rn
);
11158 inst
.instruction
|= Rd
<< 8;
11159 inst
.instruction
|= inst
.operands
[1].imm
;
11160 inst
.instruction
|= Rn
<< 16;
11163 /* Neon instruction encoder helpers. */
11165 /* Encodings for the different types for various Neon opcodes. */
11167 /* An "invalid" code for the following tables. */
11170 struct neon_tab_entry
11173 unsigned float_or_poly
;
11174 unsigned scalar_or_imm
;
11177 /* Map overloaded Neon opcodes to their respective encodings. */
11178 #define NEON_ENC_TAB \
11179 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11180 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11181 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11182 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11183 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11184 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11185 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11186 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11187 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11188 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11189 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11190 /* Register variants of the following two instructions are encoded as
11191 vcge / vcgt with the operands reversed. */ \
11192 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11193 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11194 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11195 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11196 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11197 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11198 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11199 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11200 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11201 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11202 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11203 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11204 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11205 X(vshl, 0x0000400, N_INV, 0x0800510), \
11206 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11207 X(vand, 0x0000110, N_INV, 0x0800030), \
11208 X(vbic, 0x0100110, N_INV, 0x0800030), \
11209 X(veor, 0x1000110, N_INV, N_INV), \
11210 X(vorn, 0x0300110, N_INV, 0x0800010), \
11211 X(vorr, 0x0200110, N_INV, 0x0800010), \
11212 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11213 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11214 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11215 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11216 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11217 X(vst1, 0x0000000, 0x0800000, N_INV), \
11218 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11219 X(vst2, 0x0000100, 0x0800100, N_INV), \
11220 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11221 X(vst3, 0x0000200, 0x0800200, N_INV), \
11222 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11223 X(vst4, 0x0000300, 0x0800300, N_INV), \
11224 X(vmovn, 0x1b20200, N_INV, N_INV), \
11225 X(vtrn, 0x1b20080, N_INV, N_INV), \
11226 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11227 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11228 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11229 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
11230 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
11231 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11232 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11233 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11234 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11238 #define X(OPC,I,F,S) N_MNEM_##OPC
11243 static const struct neon_tab_entry neon_enc_tab
[] =
11245 #define X(OPC,I,F,S) { (I), (F), (S) }
11250 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11251 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11252 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11253 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11254 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11255 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11256 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11257 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11258 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11259 #define NEON_ENC_SINGLE(X) \
11260 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11261 #define NEON_ENC_DOUBLE(X) \
11262 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11264 /* Define shapes for instruction operands. The following mnemonic characters
11265 are used in this table:
11267 F - VFP S<n> register
11268 D - Neon D<n> register
11269 Q - Neon Q<n> register
11273 L - D<n> register list
11275 This table is used to generate various data:
11276 - enumerations of the form NS_DDR to be used as arguments to
11278 - a table classifying shapes into single, double, quad, mixed.
11279 - a table used to drive neon_select_shape. */
11281 #define NEON_SHAPE_DEF \
11282 X(3, (D, D, D), DOUBLE), \
11283 X(3, (Q, Q, Q), QUAD), \
11284 X(3, (D, D, I), DOUBLE), \
11285 X(3, (Q, Q, I), QUAD), \
11286 X(3, (D, D, S), DOUBLE), \
11287 X(3, (Q, Q, S), QUAD), \
11288 X(2, (D, D), DOUBLE), \
11289 X(2, (Q, Q), QUAD), \
11290 X(2, (D, S), DOUBLE), \
11291 X(2, (Q, S), QUAD), \
11292 X(2, (D, R), DOUBLE), \
11293 X(2, (Q, R), QUAD), \
11294 X(2, (D, I), DOUBLE), \
11295 X(2, (Q, I), QUAD), \
11296 X(3, (D, L, D), DOUBLE), \
11297 X(2, (D, Q), MIXED), \
11298 X(2, (Q, D), MIXED), \
11299 X(3, (D, Q, I), MIXED), \
11300 X(3, (Q, D, I), MIXED), \
11301 X(3, (Q, D, D), MIXED), \
11302 X(3, (D, Q, Q), MIXED), \
11303 X(3, (Q, Q, D), MIXED), \
11304 X(3, (Q, D, S), MIXED), \
11305 X(3, (D, Q, S), MIXED), \
11306 X(4, (D, D, D, I), DOUBLE), \
11307 X(4, (Q, Q, Q, I), QUAD), \
11308 X(2, (F, F), SINGLE), \
11309 X(3, (F, F, F), SINGLE), \
11310 X(2, (F, I), SINGLE), \
11311 X(2, (F, D), MIXED), \
11312 X(2, (D, F), MIXED), \
11313 X(3, (F, F, I), MIXED), \
11314 X(4, (R, R, F, F), SINGLE), \
11315 X(4, (F, F, R, R), SINGLE), \
11316 X(3, (D, R, R), DOUBLE), \
11317 X(3, (R, R, D), DOUBLE), \
11318 X(2, (S, R), SINGLE), \
11319 X(2, (R, S), SINGLE), \
11320 X(2, (F, R), SINGLE), \
11321 X(2, (R, F), SINGLE)
11323 #define S2(A,B) NS_##A##B
11324 #define S3(A,B,C) NS_##A##B##C
11325 #define S4(A,B,C,D) NS_##A##B##C##D
11327 #define X(N, L, C) S##N L
11340 enum neon_shape_class
11348 #define X(N, L, C) SC_##C
11350 static enum neon_shape_class neon_shape_class
[] =
11368 /* Register widths of above. */
11369 static unsigned neon_shape_el_size
[] =
11380 struct neon_shape_info
11383 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11386 #define S2(A,B) { SE_##A, SE_##B }
11387 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11388 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11390 #define X(N, L, C) { N, S##N L }
11392 static struct neon_shape_info neon_shape_tab
[] =
11402 /* Bit masks used in type checking given instructions.
11403 'N_EQK' means the type must be the same as (or based on in some way) the key
11404 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11405 set, various other bits can be set as well in order to modify the meaning of
11406 the type constraint. */
11408 enum neon_type_mask
11431 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11432 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11433 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11434 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11435 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11436 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11437 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11438 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11439 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11440 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11442 N_MAX_NONSPECIAL
= N_F64
11445 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11447 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11448 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11449 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11450 #define N_SUF_32 (N_SU_32 | N_F32)
11451 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11452 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11454 /* Pass this as the first type argument to neon_check_type to ignore types
11456 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11458 /* Select a "shape" for the current instruction (describing register types or
11459 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11460 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11461 function of operand parsing, so this function doesn't need to be called.
11462 Shapes should be listed in order of decreasing length. */
11464 static enum neon_shape
11465 neon_select_shape (enum neon_shape shape
, ...)
11468 enum neon_shape first_shape
= shape
;
11470 /* Fix missing optional operands. FIXME: we don't know at this point how
11471 many arguments we should have, so this makes the assumption that we have
11472 > 1. This is true of all current Neon opcodes, I think, but may not be
11473 true in the future. */
11474 if (!inst
.operands
[1].present
)
11475 inst
.operands
[1] = inst
.operands
[0];
11477 va_start (ap
, shape
);
11479 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
11484 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11486 if (!inst
.operands
[j
].present
)
11492 switch (neon_shape_tab
[shape
].el
[j
])
11495 if (!(inst
.operands
[j
].isreg
11496 && inst
.operands
[j
].isvec
11497 && inst
.operands
[j
].issingle
11498 && !inst
.operands
[j
].isquad
))
11503 if (!(inst
.operands
[j
].isreg
11504 && inst
.operands
[j
].isvec
11505 && !inst
.operands
[j
].isquad
11506 && !inst
.operands
[j
].issingle
))
11511 if (!(inst
.operands
[j
].isreg
11512 && !inst
.operands
[j
].isvec
))
11517 if (!(inst
.operands
[j
].isreg
11518 && inst
.operands
[j
].isvec
11519 && inst
.operands
[j
].isquad
11520 && !inst
.operands
[j
].issingle
))
11525 if (!(!inst
.operands
[j
].isreg
11526 && !inst
.operands
[j
].isscalar
))
11531 if (!(!inst
.operands
[j
].isreg
11532 && inst
.operands
[j
].isscalar
))
11546 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11547 first_error (_("invalid instruction shape"));
11552 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11553 means the Q bit should be set). */
11556 neon_quad (enum neon_shape shape
)
11558 return neon_shape_class
[shape
] == SC_QUAD
;
11562 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11565 /* Allow modification to be made to types which are constrained to be
11566 based on the key element, based on bits set alongside N_EQK. */
11567 if ((typebits
& N_EQK
) != 0)
11569 if ((typebits
& N_HLF
) != 0)
11571 else if ((typebits
& N_DBL
) != 0)
11573 if ((typebits
& N_SGN
) != 0)
11574 *g_type
= NT_signed
;
11575 else if ((typebits
& N_UNS
) != 0)
11576 *g_type
= NT_unsigned
;
11577 else if ((typebits
& N_INT
) != 0)
11578 *g_type
= NT_integer
;
11579 else if ((typebits
& N_FLT
) != 0)
11580 *g_type
= NT_float
;
11581 else if ((typebits
& N_SIZ
) != 0)
11582 *g_type
= NT_untyped
;
11586 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11587 operand type, i.e. the single type specified in a Neon instruction when it
11588 is the only one given. */
11590 static struct neon_type_el
11591 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11593 struct neon_type_el dest
= *key
;
11595 gas_assert ((thisarg
& N_EQK
) != 0);
11597 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11602 /* Convert Neon type and size into compact bitmask representation. */
11604 static enum neon_type_mask
11605 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11612 case 8: return N_8
;
11613 case 16: return N_16
;
11614 case 32: return N_32
;
11615 case 64: return N_64
;
11623 case 8: return N_I8
;
11624 case 16: return N_I16
;
11625 case 32: return N_I32
;
11626 case 64: return N_I64
;
11634 case 16: return N_F16
;
11635 case 32: return N_F32
;
11636 case 64: return N_F64
;
11644 case 8: return N_P8
;
11645 case 16: return N_P16
;
11653 case 8: return N_S8
;
11654 case 16: return N_S16
;
11655 case 32: return N_S32
;
11656 case 64: return N_S64
;
11664 case 8: return N_U8
;
11665 case 16: return N_U16
;
11666 case 32: return N_U32
;
11667 case 64: return N_U64
;
11678 /* Convert compact Neon bitmask type representation to a type and size. Only
11679 handles the case where a single bit is set in the mask. */
11682 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11683 enum neon_type_mask mask
)
11685 if ((mask
& N_EQK
) != 0)
11688 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11690 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11692 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11694 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
11699 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
11701 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
11702 *type
= NT_unsigned
;
11703 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
11704 *type
= NT_integer
;
11705 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
11706 *type
= NT_untyped
;
11707 else if ((mask
& (N_P8
| N_P16
)) != 0)
11709 else if ((mask
& (N_F32
| N_F64
)) != 0)
11717 /* Modify a bitmask of allowed types. This is only needed for type
11721 modify_types_allowed (unsigned allowed
, unsigned mods
)
11724 enum neon_el_type type
;
11730 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11732 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
11734 neon_modify_type_size (mods
, &type
, &size
);
11735 destmask
|= type_chk_of_el_type (type
, size
);
11742 /* Check type and return type classification.
11743 The manual states (paraphrase): If one datatype is given, it indicates the
11745 - the second operand, if there is one
11746 - the operand, if there is no second operand
11747 - the result, if there are no operands.
11748 This isn't quite good enough though, so we use a concept of a "key" datatype
11749 which is set on a per-instruction basis, which is the one which matters when
11750 only one data type is written.
11751 Note: this function has side-effects (e.g. filling in missing operands). All
11752 Neon instructions should call it before performing bit encoding. */
11754 static struct neon_type_el
11755 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11758 unsigned i
, pass
, key_el
= 0;
11759 unsigned types
[NEON_MAX_TYPE_ELS
];
11760 enum neon_el_type k_type
= NT_invtype
;
11761 unsigned k_size
= -1u;
11762 struct neon_type_el badtype
= {NT_invtype
, -1};
11763 unsigned key_allowed
= 0;
11765 /* Optional registers in Neon instructions are always (not) in operand 1.
11766 Fill in the missing operand here, if it was omitted. */
11767 if (els
> 1 && !inst
.operands
[1].present
)
11768 inst
.operands
[1] = inst
.operands
[0];
11770 /* Suck up all the varargs. */
11772 for (i
= 0; i
< els
; i
++)
11774 unsigned thisarg
= va_arg (ap
, unsigned);
11775 if (thisarg
== N_IGNORE_TYPE
)
11780 types
[i
] = thisarg
;
11781 if ((thisarg
& N_KEY
) != 0)
11786 if (inst
.vectype
.elems
> 0)
11787 for (i
= 0; i
< els
; i
++)
11788 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11790 first_error (_("types specified in both the mnemonic and operands"));
11794 /* Duplicate inst.vectype elements here as necessary.
11795 FIXME: No idea if this is exactly the same as the ARM assembler,
11796 particularly when an insn takes one register and one non-register
11798 if (inst
.vectype
.elems
== 1 && els
> 1)
11801 inst
.vectype
.elems
= els
;
11802 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11803 for (j
= 0; j
< els
; j
++)
11805 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11808 else if (inst
.vectype
.elems
== 0 && els
> 0)
11811 /* No types were given after the mnemonic, so look for types specified
11812 after each operand. We allow some flexibility here; as long as the
11813 "key" operand has a type, we can infer the others. */
11814 for (j
= 0; j
< els
; j
++)
11815 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11816 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11818 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11820 for (j
= 0; j
< els
; j
++)
11821 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11822 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11827 first_error (_("operand types can't be inferred"));
11831 else if (inst
.vectype
.elems
!= els
)
11833 first_error (_("type specifier has the wrong number of parts"));
11837 for (pass
= 0; pass
< 2; pass
++)
11839 for (i
= 0; i
< els
; i
++)
11841 unsigned thisarg
= types
[i
];
11842 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11843 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11844 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11845 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11847 /* Decay more-specific signed & unsigned types to sign-insensitive
11848 integer types if sign-specific variants are unavailable. */
11849 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11850 && (types_allowed
& N_SU_ALL
) == 0)
11851 g_type
= NT_integer
;
11853 /* If only untyped args are allowed, decay any more specific types to
11854 them. Some instructions only care about signs for some element
11855 sizes, so handle that properly. */
11856 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11857 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11858 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11859 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11860 g_type
= NT_untyped
;
11864 if ((thisarg
& N_KEY
) != 0)
11868 key_allowed
= thisarg
& ~N_KEY
;
11873 if ((thisarg
& N_VFP
) != 0)
11875 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11876 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11878 /* In VFP mode, operands must match register widths. If we
11879 have a key operand, use its width, else use the width of
11880 the current operand. */
11886 if (regwidth
!= match
)
11888 first_error (_("operand size must match register width"));
11893 if ((thisarg
& N_EQK
) == 0)
11895 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11897 if ((given_type
& types_allowed
) == 0)
11899 first_error (_("bad type in Neon instruction"));
11905 enum neon_el_type mod_k_type
= k_type
;
11906 unsigned mod_k_size
= k_size
;
11907 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11908 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11910 first_error (_("inconsistent types in Neon instruction"));
11918 return inst
.vectype
.el
[key_el
];
11921 /* Neon-style VFP instruction forwarding. */
11923 /* Thumb VFP instructions have 0xE in the condition field. */
11926 do_vfp_cond_or_thumb (void)
11929 inst
.instruction
|= 0xe0000000;
11931 inst
.instruction
|= inst
.cond
<< 28;
11934 /* Look up and encode a simple mnemonic, for use as a helper function for the
11935 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11936 etc. It is assumed that operand parsing has already been done, and that the
11937 operands are in the form expected by the given opcode (this isn't necessarily
11938 the same as the form in which they were parsed, hence some massaging must
11939 take place before this function is called).
11940 Checks current arch version against that in the looked-up opcode. */
11943 do_vfp_nsyn_opcode (const char *opname
)
11945 const struct asm_opcode
*opcode
;
11947 opcode
= hash_find (arm_ops_hsh
, opname
);
11952 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11953 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11958 inst
.instruction
= opcode
->tvalue
;
11959 opcode
->tencode ();
11963 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11964 opcode
->aencode ();
11969 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11971 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11976 do_vfp_nsyn_opcode ("fadds");
11978 do_vfp_nsyn_opcode ("fsubs");
11983 do_vfp_nsyn_opcode ("faddd");
11985 do_vfp_nsyn_opcode ("fsubd");
11989 /* Check operand types to see if this is a VFP instruction, and if so call
11993 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11995 enum neon_shape rs
;
11996 struct neon_type_el et
;
12001 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12002 et
= neon_check_type (2, rs
,
12003 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12007 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12008 et
= neon_check_type (3, rs
,
12009 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12016 if (et
.type
!= NT_invtype
)
12028 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12030 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12035 do_vfp_nsyn_opcode ("fmacs");
12037 do_vfp_nsyn_opcode ("fmscs");
12042 do_vfp_nsyn_opcode ("fmacd");
12044 do_vfp_nsyn_opcode ("fmscd");
12049 do_vfp_nsyn_mul (enum neon_shape rs
)
12052 do_vfp_nsyn_opcode ("fmuls");
12054 do_vfp_nsyn_opcode ("fmuld");
12058 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12060 int is_neg
= (inst
.instruction
& 0x80) != 0;
12061 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12066 do_vfp_nsyn_opcode ("fnegs");
12068 do_vfp_nsyn_opcode ("fabss");
12073 do_vfp_nsyn_opcode ("fnegd");
12075 do_vfp_nsyn_opcode ("fabsd");
12079 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12080 insns belong to Neon, and are handled elsewhere. */
12083 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12085 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12089 do_vfp_nsyn_opcode ("fldmdbs");
12091 do_vfp_nsyn_opcode ("fldmias");
12096 do_vfp_nsyn_opcode ("fstmdbs");
12098 do_vfp_nsyn_opcode ("fstmias");
12103 do_vfp_nsyn_sqrt (void)
12105 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12106 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12109 do_vfp_nsyn_opcode ("fsqrts");
12111 do_vfp_nsyn_opcode ("fsqrtd");
12115 do_vfp_nsyn_div (void)
12117 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12118 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12119 N_F32
| N_F64
| N_KEY
| N_VFP
);
12122 do_vfp_nsyn_opcode ("fdivs");
12124 do_vfp_nsyn_opcode ("fdivd");
12128 do_vfp_nsyn_nmul (void)
12130 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12131 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12132 N_F32
| N_F64
| N_KEY
| N_VFP
);
12136 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12137 do_vfp_sp_dyadic ();
12141 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12142 do_vfp_dp_rd_rn_rm ();
12144 do_vfp_cond_or_thumb ();
12148 do_vfp_nsyn_cmp (void)
12150 if (inst
.operands
[1].isreg
)
12152 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12153 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12157 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12158 do_vfp_sp_monadic ();
12162 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12163 do_vfp_dp_rd_rm ();
12168 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12169 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12171 switch (inst
.instruction
& 0x0fffffff)
12174 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12177 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12185 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12186 do_vfp_sp_compare_z ();
12190 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12194 do_vfp_cond_or_thumb ();
12198 nsyn_insert_sp (void)
12200 inst
.operands
[1] = inst
.operands
[0];
12201 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12202 inst
.operands
[0].reg
= REG_SP
;
12203 inst
.operands
[0].isreg
= 1;
12204 inst
.operands
[0].writeback
= 1;
12205 inst
.operands
[0].present
= 1;
12209 do_vfp_nsyn_push (void)
12212 if (inst
.operands
[1].issingle
)
12213 do_vfp_nsyn_opcode ("fstmdbs");
12215 do_vfp_nsyn_opcode ("fstmdbd");
12219 do_vfp_nsyn_pop (void)
12222 if (inst
.operands
[1].issingle
)
12223 do_vfp_nsyn_opcode ("fldmias");
12225 do_vfp_nsyn_opcode ("fldmiad");
12228 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12229 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12232 neon_dp_fixup (unsigned i
)
12236 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12250 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12254 neon_logbits (unsigned x
)
12256 return ffs (x
) - 4;
12259 #define LOW4(R) ((R) & 0xf)
12260 #define HI1(R) (((R) >> 4) & 1)
12262 /* Encode insns with bit pattern:
12264 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12265 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12267 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12268 different meaning for some instruction. */
12271 neon_three_same (int isquad
, int ubit
, int size
)
12273 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12274 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12275 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12276 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12277 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12278 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12279 inst
.instruction
|= (isquad
!= 0) << 6;
12280 inst
.instruction
|= (ubit
!= 0) << 24;
12282 inst
.instruction
|= neon_logbits (size
) << 20;
12284 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12287 /* Encode instructions of the form:
12289 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12290 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12292 Don't write size if SIZE == -1. */
12295 neon_two_same (int qbit
, int ubit
, int size
)
12297 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12298 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12299 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12300 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12301 inst
.instruction
|= (qbit
!= 0) << 6;
12302 inst
.instruction
|= (ubit
!= 0) << 24;
12305 inst
.instruction
|= neon_logbits (size
) << 18;
12307 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12310 /* Neon instruction encoders, in approximate order of appearance. */
12313 do_neon_dyadic_i_su (void)
12315 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12316 struct neon_type_el et
= neon_check_type (3, rs
,
12317 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12318 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12322 do_neon_dyadic_i64_su (void)
12324 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12325 struct neon_type_el et
= neon_check_type (3, rs
,
12326 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12327 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12331 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12334 unsigned size
= et
.size
>> 3;
12335 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12336 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12337 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12338 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12339 inst
.instruction
|= (isquad
!= 0) << 6;
12340 inst
.instruction
|= immbits
<< 16;
12341 inst
.instruction
|= (size
>> 3) << 7;
12342 inst
.instruction
|= (size
& 0x7) << 19;
12344 inst
.instruction
|= (uval
!= 0) << 24;
12346 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12350 do_neon_shl_imm (void)
12352 if (!inst
.operands
[2].isreg
)
12354 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12355 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12356 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12357 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12361 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12362 struct neon_type_el et
= neon_check_type (3, rs
,
12363 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12366 /* VSHL/VQSHL 3-register variants have syntax such as:
12368 whereas other 3-register operations encoded by neon_three_same have
12371 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12373 tmp
= inst
.operands
[2].reg
;
12374 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12375 inst
.operands
[1].reg
= tmp
;
12376 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12377 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12382 do_neon_qshl_imm (void)
12384 if (!inst
.operands
[2].isreg
)
12386 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12387 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12389 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12390 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12391 inst
.operands
[2].imm
);
12395 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12396 struct neon_type_el et
= neon_check_type (3, rs
,
12397 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12400 /* See note in do_neon_shl_imm. */
12401 tmp
= inst
.operands
[2].reg
;
12402 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12403 inst
.operands
[1].reg
= tmp
;
12404 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12405 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12410 do_neon_rshl (void)
12412 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12413 struct neon_type_el et
= neon_check_type (3, rs
,
12414 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12417 tmp
= inst
.operands
[2].reg
;
12418 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12419 inst
.operands
[1].reg
= tmp
;
12420 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12424 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12426 /* Handle .I8 pseudo-instructions. */
12429 /* Unfortunately, this will make everything apart from zero out-of-range.
12430 FIXME is this the intended semantics? There doesn't seem much point in
12431 accepting .I8 if so. */
12432 immediate
|= immediate
<< 8;
12438 if (immediate
== (immediate
& 0x000000ff))
12440 *immbits
= immediate
;
12443 else if (immediate
== (immediate
& 0x0000ff00))
12445 *immbits
= immediate
>> 8;
12448 else if (immediate
== (immediate
& 0x00ff0000))
12450 *immbits
= immediate
>> 16;
12453 else if (immediate
== (immediate
& 0xff000000))
12455 *immbits
= immediate
>> 24;
12458 if ((immediate
& 0xffff) != (immediate
>> 16))
12459 goto bad_immediate
;
12460 immediate
&= 0xffff;
12463 if (immediate
== (immediate
& 0x000000ff))
12465 *immbits
= immediate
;
12468 else if (immediate
== (immediate
& 0x0000ff00))
12470 *immbits
= immediate
>> 8;
12475 first_error (_("immediate value out of range"));
12479 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12483 neon_bits_same_in_bytes (unsigned imm
)
12485 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12486 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12487 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12488 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12491 /* For immediate of above form, return 0bABCD. */
12494 neon_squash_bits (unsigned imm
)
12496 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12497 | ((imm
& 0x01000000) >> 21);
12500 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12503 neon_qfloat_bits (unsigned imm
)
12505 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12508 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12509 the instruction. *OP is passed as the initial value of the op field, and
12510 may be set to a different value depending on the constant (i.e.
12511 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12512 MVN). If the immediate looks like a repeated pattern then also
12513 try smaller element sizes. */
12516 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12517 unsigned *immbits
, int *op
, int size
,
12518 enum neon_el_type type
)
12520 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12522 if (type
== NT_float
&& !float_p
)
12525 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12527 if (size
!= 32 || *op
== 1)
12529 *immbits
= neon_qfloat_bits (immlo
);
12535 if (neon_bits_same_in_bytes (immhi
)
12536 && neon_bits_same_in_bytes (immlo
))
12540 *immbits
= (neon_squash_bits (immhi
) << 4)
12541 | neon_squash_bits (immlo
);
12546 if (immhi
!= immlo
)
12552 if (immlo
== (immlo
& 0x000000ff))
12557 else if (immlo
== (immlo
& 0x0000ff00))
12559 *immbits
= immlo
>> 8;
12562 else if (immlo
== (immlo
& 0x00ff0000))
12564 *immbits
= immlo
>> 16;
12567 else if (immlo
== (immlo
& 0xff000000))
12569 *immbits
= immlo
>> 24;
12572 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12574 *immbits
= (immlo
>> 8) & 0xff;
12577 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12579 *immbits
= (immlo
>> 16) & 0xff;
12583 if ((immlo
& 0xffff) != (immlo
>> 16))
12590 if (immlo
== (immlo
& 0x000000ff))
12595 else if (immlo
== (immlo
& 0x0000ff00))
12597 *immbits
= immlo
>> 8;
12601 if ((immlo
& 0xff) != (immlo
>> 8))
12606 if (immlo
== (immlo
& 0x000000ff))
12608 /* Don't allow MVN with 8-bit immediate. */
12618 /* Write immediate bits [7:0] to the following locations:
12620 |28/24|23 19|18 16|15 4|3 0|
12621 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12623 This function is used by VMOV/VMVN/VORR/VBIC. */
12626 neon_write_immbits (unsigned immbits
)
12628 inst
.instruction
|= immbits
& 0xf;
12629 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12630 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12633 /* Invert low-order SIZE bits of XHI:XLO. */
12636 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12638 unsigned immlo
= xlo
? *xlo
: 0;
12639 unsigned immhi
= xhi
? *xhi
: 0;
12644 immlo
= (~immlo
) & 0xff;
12648 immlo
= (~immlo
) & 0xffff;
12652 immhi
= (~immhi
) & 0xffffffff;
12653 /* fall through. */
12656 immlo
= (~immlo
) & 0xffffffff;
12671 do_neon_logic (void)
12673 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
12675 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12676 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12677 /* U bit and size field were set as part of the bitmask. */
12678 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12679 neon_three_same (neon_quad (rs
), 0, -1);
12683 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12684 struct neon_type_el et
= neon_check_type (2, rs
,
12685 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12686 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
12690 if (et
.type
== NT_invtype
)
12693 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12695 immbits
= inst
.operands
[1].imm
;
12698 /* .i64 is a pseudo-op, so the immediate must be a repeating
12700 if (immbits
!= (inst
.operands
[1].regisimm
?
12701 inst
.operands
[1].reg
: 0))
12703 /* Set immbits to an invalid constant. */
12704 immbits
= 0xdeadbeef;
12711 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12715 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12719 /* Pseudo-instruction for VBIC. */
12720 neon_invert_size (&immbits
, 0, et
.size
);
12721 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12725 /* Pseudo-instruction for VORR. */
12726 neon_invert_size (&immbits
, 0, et
.size
);
12727 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12737 inst
.instruction
|= neon_quad (rs
) << 6;
12738 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12739 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12740 inst
.instruction
|= cmode
<< 8;
12741 neon_write_immbits (immbits
);
12743 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12748 do_neon_bitfield (void)
12750 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12751 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12752 neon_three_same (neon_quad (rs
), 0, -1);
12756 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12759 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12760 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12762 if (et
.type
== NT_float
)
12764 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12765 neon_three_same (neon_quad (rs
), 0, -1);
12769 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12770 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12775 do_neon_dyadic_if_su (void)
12777 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12781 do_neon_dyadic_if_su_d (void)
12783 /* This version only allow D registers, but that constraint is enforced during
12784 operand parsing so we don't need to do anything extra here. */
12785 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12789 do_neon_dyadic_if_i_d (void)
12791 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12792 affected if we specify unsigned args. */
12793 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12796 enum vfp_or_neon_is_neon_bits
12799 NEON_CHECK_ARCH
= 2
12802 /* Call this function if an instruction which may have belonged to the VFP or
12803 Neon instruction sets, but turned out to be a Neon instruction (due to the
12804 operand types involved, etc.). We have to check and/or fix-up a couple of
12807 - Make sure the user hasn't attempted to make a Neon instruction
12809 - Alter the value in the condition code field if necessary.
12810 - Make sure that the arch supports Neon instructions.
12812 Which of these operations take place depends on bits from enum
12813 vfp_or_neon_is_neon_bits.
12815 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12816 current instruction's condition is COND_ALWAYS, the condition field is
12817 changed to inst.uncond_value. This is necessary because instructions shared
12818 between VFP and Neon may be conditional for the VFP variants only, and the
12819 unconditional Neon version must have, e.g., 0xF in the condition field. */
12822 vfp_or_neon_is_neon (unsigned check
)
12824 /* Conditions are always legal in Thumb mode (IT blocks). */
12825 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12827 if (inst
.cond
!= COND_ALWAYS
)
12829 first_error (_(BAD_COND
));
12832 if (inst
.uncond_value
!= -1)
12833 inst
.instruction
|= inst
.uncond_value
<< 28;
12836 if ((check
& NEON_CHECK_ARCH
)
12837 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12839 first_error (_(BAD_FPU
));
12847 do_neon_addsub_if_i (void)
12849 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12852 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12855 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12856 affected if we specify unsigned args. */
12857 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12860 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12862 V<op> A,B (A is operand 0, B is operand 2)
12867 so handle that case specially. */
12870 neon_exchange_operands (void)
12872 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12873 if (inst
.operands
[1].present
)
12875 /* Swap operands[1] and operands[2]. */
12876 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12877 inst
.operands
[1] = inst
.operands
[2];
12878 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12882 inst
.operands
[1] = inst
.operands
[2];
12883 inst
.operands
[2] = inst
.operands
[0];
12888 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12890 if (inst
.operands
[2].isreg
)
12893 neon_exchange_operands ();
12894 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12898 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12899 struct neon_type_el et
= neon_check_type (2, rs
,
12900 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12902 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12903 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12904 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12905 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12906 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12907 inst
.instruction
|= neon_quad (rs
) << 6;
12908 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12909 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12911 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12918 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
12922 do_neon_cmp_inv (void)
12924 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
12930 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
12933 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12934 scalars, which are encoded in 5 bits, M : Rm.
12935 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12936 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12940 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
12942 unsigned regno
= NEON_SCALAR_REG (scalar
);
12943 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
12948 if (regno
> 7 || elno
> 3)
12950 return regno
| (elno
<< 3);
12953 if (regno
> 15 || elno
> 1)
12955 return regno
| (elno
<< 4);
12959 first_error (_("scalar out of range for multiply instruction"));
12965 /* Encode multiply / multiply-accumulate scalar instructions. */
12968 neon_mul_mac (struct neon_type_el et
, int ubit
)
12972 /* Give a more helpful error message if we have an invalid type. */
12973 if (et
.type
== NT_invtype
)
12976 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12977 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12978 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12979 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12980 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12981 inst
.instruction
|= LOW4 (scalar
);
12982 inst
.instruction
|= HI1 (scalar
) << 5;
12983 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12984 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12985 inst
.instruction
|= (ubit
!= 0) << 24;
12987 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12991 do_neon_mac_maybe_scalar (void)
12993 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12996 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12999 if (inst
.operands
[2].isscalar
)
13001 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13002 struct neon_type_el et
= neon_check_type (3, rs
,
13003 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13004 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13005 neon_mul_mac (et
, neon_quad (rs
));
13009 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13010 affected if we specify unsigned args. */
13011 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13018 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13019 struct neon_type_el et
= neon_check_type (3, rs
,
13020 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13021 neon_three_same (neon_quad (rs
), 0, et
.size
);
13024 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13025 same types as the MAC equivalents. The polynomial type for this instruction
13026 is encoded the same as the integer type. */
13031 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13034 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13037 if (inst
.operands
[2].isscalar
)
13038 do_neon_mac_maybe_scalar ();
13040 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13044 do_neon_qdmulh (void)
13046 if (inst
.operands
[2].isscalar
)
13048 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13049 struct neon_type_el et
= neon_check_type (3, rs
,
13050 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13051 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13052 neon_mul_mac (et
, neon_quad (rs
));
13056 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13057 struct neon_type_el et
= neon_check_type (3, rs
,
13058 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13059 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13060 /* The U bit (rounding) comes from bit mask. */
13061 neon_three_same (neon_quad (rs
), 0, et
.size
);
13066 do_neon_fcmp_absolute (void)
13068 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13069 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13070 /* Size field comes from bit mask. */
13071 neon_three_same (neon_quad (rs
), 1, -1);
13075 do_neon_fcmp_absolute_inv (void)
13077 neon_exchange_operands ();
13078 do_neon_fcmp_absolute ();
13082 do_neon_step (void)
13084 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13085 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13086 neon_three_same (neon_quad (rs
), 0, -1);
13090 do_neon_abs_neg (void)
13092 enum neon_shape rs
;
13093 struct neon_type_el et
;
13095 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13098 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13101 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13102 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13104 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13105 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13106 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13107 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13108 inst
.instruction
|= neon_quad (rs
) << 6;
13109 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13110 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13112 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13118 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13119 struct neon_type_el et
= neon_check_type (2, rs
,
13120 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13121 int imm
= inst
.operands
[2].imm
;
13122 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13123 _("immediate out of range for insert"));
13124 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13130 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13131 struct neon_type_el et
= neon_check_type (2, rs
,
13132 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13133 int imm
= inst
.operands
[2].imm
;
13134 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13135 _("immediate out of range for insert"));
13136 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13140 do_neon_qshlu_imm (void)
13142 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13143 struct neon_type_el et
= neon_check_type (2, rs
,
13144 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13145 int imm
= inst
.operands
[2].imm
;
13146 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13147 _("immediate out of range for shift"));
13148 /* Only encodes the 'U present' variant of the instruction.
13149 In this case, signed types have OP (bit 8) set to 0.
13150 Unsigned types have OP set to 1. */
13151 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13152 /* The rest of the bits are the same as other immediate shifts. */
13153 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13157 do_neon_qmovn (void)
13159 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13160 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13161 /* Saturating move where operands can be signed or unsigned, and the
13162 destination has the same signedness. */
13163 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13164 if (et
.type
== NT_unsigned
)
13165 inst
.instruction
|= 0xc0;
13167 inst
.instruction
|= 0x80;
13168 neon_two_same (0, 1, et
.size
/ 2);
13172 do_neon_qmovun (void)
13174 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13175 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13176 /* Saturating move with unsigned results. Operands must be signed. */
13177 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13178 neon_two_same (0, 1, et
.size
/ 2);
13182 do_neon_rshift_sat_narrow (void)
13184 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13185 or unsigned. If operands are unsigned, results must also be unsigned. */
13186 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13187 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13188 int imm
= inst
.operands
[2].imm
;
13189 /* This gets the bounds check, size encoding and immediate bits calculation
13193 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13194 VQMOVN.I<size> <Dd>, <Qm>. */
13197 inst
.operands
[2].present
= 0;
13198 inst
.instruction
= N_MNEM_vqmovn
;
13203 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13204 _("immediate out of range"));
13205 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13209 do_neon_rshift_sat_narrow_u (void)
13211 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13212 or unsigned. If operands are unsigned, results must also be unsigned. */
13213 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13214 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13215 int imm
= inst
.operands
[2].imm
;
13216 /* This gets the bounds check, size encoding and immediate bits calculation
13220 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13221 VQMOVUN.I<size> <Dd>, <Qm>. */
13224 inst
.operands
[2].present
= 0;
13225 inst
.instruction
= N_MNEM_vqmovun
;
13230 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13231 _("immediate out of range"));
13232 /* FIXME: The manual is kind of unclear about what value U should have in
13233 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13235 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13239 do_neon_movn (void)
13241 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13242 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13243 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13244 neon_two_same (0, 1, et
.size
/ 2);
13248 do_neon_rshift_narrow (void)
13250 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13251 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13252 int imm
= inst
.operands
[2].imm
;
13253 /* This gets the bounds check, size encoding and immediate bits calculation
13257 /* If immediate is zero then we are a pseudo-instruction for
13258 VMOVN.I<size> <Dd>, <Qm> */
13261 inst
.operands
[2].present
= 0;
13262 inst
.instruction
= N_MNEM_vmovn
;
13267 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13268 _("immediate out of range for narrowing operation"));
13269 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13273 do_neon_shll (void)
13275 /* FIXME: Type checking when lengthening. */
13276 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13277 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13278 unsigned imm
= inst
.operands
[2].imm
;
13280 if (imm
== et
.size
)
13282 /* Maximum shift variant. */
13283 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13284 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13285 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13286 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13287 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13288 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13290 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13294 /* A more-specific type check for non-max versions. */
13295 et
= neon_check_type (2, NS_QDI
,
13296 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13297 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13298 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13302 /* Check the various types for the VCVT instruction, and return which version
13303 the current instruction is. */
13306 neon_cvt_flavour (enum neon_shape rs
)
13308 #define CVT_VAR(C,X,Y) \
13309 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13310 if (et.type != NT_invtype) \
13312 inst.error = NULL; \
13315 struct neon_type_el et
;
13316 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13317 || rs
== NS_FF
) ? N_VFP
: 0;
13318 /* The instruction versions which take an immediate take one register
13319 argument, which is extended to the width of the full register. Thus the
13320 "source" and "destination" registers must have the same width. Hack that
13321 here by making the size equal to the key (wider, in this case) operand. */
13322 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13324 CVT_VAR (0, N_S32
, N_F32
);
13325 CVT_VAR (1, N_U32
, N_F32
);
13326 CVT_VAR (2, N_F32
, N_S32
);
13327 CVT_VAR (3, N_F32
, N_U32
);
13328 /* Half-precision conversions. */
13329 CVT_VAR (4, N_F32
, N_F16
);
13330 CVT_VAR (5, N_F16
, N_F32
);
13334 /* VFP instructions. */
13335 CVT_VAR (6, N_F32
, N_F64
);
13336 CVT_VAR (7, N_F64
, N_F32
);
13337 CVT_VAR (8, N_S32
, N_F64
| key
);
13338 CVT_VAR (9, N_U32
, N_F64
| key
);
13339 CVT_VAR (10, N_F64
| key
, N_S32
);
13340 CVT_VAR (11, N_F64
| key
, N_U32
);
13341 /* VFP instructions with bitshift. */
13342 CVT_VAR (12, N_F32
| key
, N_S16
);
13343 CVT_VAR (13, N_F32
| key
, N_U16
);
13344 CVT_VAR (14, N_F64
| key
, N_S16
);
13345 CVT_VAR (15, N_F64
| key
, N_U16
);
13346 CVT_VAR (16, N_S16
, N_F32
| key
);
13347 CVT_VAR (17, N_U16
, N_F32
| key
);
13348 CVT_VAR (18, N_S16
, N_F64
| key
);
13349 CVT_VAR (19, N_U16
, N_F64
| key
);
13355 /* Neon-syntax VFP conversions. */
13358 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13360 const char *opname
= 0;
13362 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13364 /* Conversions with immediate bitshift. */
13365 const char *enc
[] =
13389 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13391 opname
= enc
[flavour
];
13392 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13393 _("operands 0 and 1 must be the same register"));
13394 inst
.operands
[1] = inst
.operands
[2];
13395 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13400 /* Conversions without bitshift. */
13401 const char *enc
[] =
13417 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13418 opname
= enc
[flavour
];
13422 do_vfp_nsyn_opcode (opname
);
13426 do_vfp_nsyn_cvtz (void)
13428 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13429 int flavour
= neon_cvt_flavour (rs
);
13430 const char *enc
[] =
13444 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13445 do_vfp_nsyn_opcode (enc
[flavour
]);
13451 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13452 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13453 int flavour
= neon_cvt_flavour (rs
);
13455 /* VFP rather than Neon conversions. */
13458 do_vfp_nsyn_cvt (rs
, flavour
);
13468 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13470 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13473 /* Fixed-point conversion with #0 immediate is encoded as an
13474 integer conversion. */
13475 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13477 immbits
= 32 - inst
.operands
[2].imm
;
13478 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13480 inst
.instruction
|= enctab
[flavour
];
13481 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13482 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13483 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13484 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13485 inst
.instruction
|= neon_quad (rs
) << 6;
13486 inst
.instruction
|= 1 << 21;
13487 inst
.instruction
|= immbits
<< 16;
13489 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13497 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13499 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13501 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13505 inst
.instruction
|= enctab
[flavour
];
13507 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13508 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13509 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13510 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13511 inst
.instruction
|= neon_quad (rs
) << 6;
13512 inst
.instruction
|= 2 << 18;
13514 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13518 /* Half-precision conversions for Advanced SIMD -- neon. */
13523 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13525 as_bad (_("operand size must match register width"));
13530 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13532 as_bad (_("operand size must match register width"));
13537 inst
.instruction
= 0x3b60600;
13539 inst
.instruction
= 0x3b60700;
13541 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13542 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13543 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13544 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13545 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13549 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13550 do_vfp_nsyn_cvt (rs
, flavour
);
13555 do_neon_cvtb (void)
13557 inst
.instruction
= 0xeb20a40;
13559 /* The sizes are attached to the mnemonic. */
13560 if (inst
.vectype
.el
[0].type
!= NT_invtype
13561 && inst
.vectype
.el
[0].size
== 16)
13562 inst
.instruction
|= 0x00010000;
13564 /* Programmer's syntax: the sizes are attached to the operands. */
13565 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13566 && inst
.operands
[0].vectype
.size
== 16)
13567 inst
.instruction
|= 0x00010000;
13569 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13570 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13571 do_vfp_cond_or_thumb ();
13576 do_neon_cvtt (void)
13579 inst
.instruction
|= 0x80;
13583 neon_move_immediate (void)
13585 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13586 struct neon_type_el et
= neon_check_type (2, rs
,
13587 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13588 unsigned immlo
, immhi
= 0, immbits
;
13589 int op
, cmode
, float_p
;
13591 constraint (et
.type
== NT_invtype
,
13592 _("operand size must be specified for immediate VMOV"));
13594 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13595 op
= (inst
.instruction
& (1 << 5)) != 0;
13597 immlo
= inst
.operands
[1].imm
;
13598 if (inst
.operands
[1].regisimm
)
13599 immhi
= inst
.operands
[1].reg
;
13601 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
13602 _("immediate has bits set outside the operand size"));
13604 float_p
= inst
.operands
[1].immisfloat
;
13606 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
13607 et
.size
, et
.type
)) == FAIL
)
13609 /* Invert relevant bits only. */
13610 neon_invert_size (&immlo
, &immhi
, et
.size
);
13611 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13612 with one or the other; those cases are caught by
13613 neon_cmode_for_move_imm. */
13615 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
13616 &op
, et
.size
, et
.type
)) == FAIL
)
13618 first_error (_("immediate out of range"));
13623 inst
.instruction
&= ~(1 << 5);
13624 inst
.instruction
|= op
<< 5;
13626 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13627 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13628 inst
.instruction
|= neon_quad (rs
) << 6;
13629 inst
.instruction
|= cmode
<< 8;
13631 neon_write_immbits (immbits
);
13637 if (inst
.operands
[1].isreg
)
13639 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13641 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13642 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13643 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13644 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13645 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13646 inst
.instruction
|= neon_quad (rs
) << 6;
13650 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13651 neon_move_immediate ();
13654 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13657 /* Encode instructions of form:
13659 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13660 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
13663 neon_mixed_length (struct neon_type_el et
, unsigned size
)
13665 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13666 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13667 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13668 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13669 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13670 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13671 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
13672 inst
.instruction
|= neon_logbits (size
) << 20;
13674 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13678 do_neon_dyadic_long (void)
13680 /* FIXME: Type checking for lengthening op. */
13681 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13682 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13683 neon_mixed_length (et
, et
.size
);
13687 do_neon_abal (void)
13689 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13690 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13691 neon_mixed_length (et
, et
.size
);
13695 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
13697 if (inst
.operands
[2].isscalar
)
13699 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
13700 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
13701 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13702 neon_mul_mac (et
, et
.type
== NT_unsigned
);
13706 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13707 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
13708 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13709 neon_mixed_length (et
, et
.size
);
13714 do_neon_mac_maybe_scalar_long (void)
13716 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
13720 do_neon_dyadic_wide (void)
13722 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
13723 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13724 neon_mixed_length (et
, et
.size
);
13728 do_neon_dyadic_narrow (void)
13730 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13731 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
13732 /* Operand sign is unimportant, and the U bit is part of the opcode,
13733 so force the operand type to integer. */
13734 et
.type
= NT_integer
;
13735 neon_mixed_length (et
, et
.size
/ 2);
13739 do_neon_mul_sat_scalar_long (void)
13741 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
13745 do_neon_vmull (void)
13747 if (inst
.operands
[2].isscalar
)
13748 do_neon_mac_maybe_scalar_long ();
13751 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13752 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
13753 if (et
.type
== NT_poly
)
13754 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
13756 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13757 /* For polynomial encoding, size field must be 0b00 and the U bit must be
13758 zero. Should be OK as-is. */
13759 neon_mixed_length (et
, et
.size
);
13766 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
13767 struct neon_type_el et
= neon_check_type (3, rs
,
13768 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13769 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
13771 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
13772 _("shift out of range"));
13773 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13774 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13775 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13776 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13777 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13778 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13779 inst
.instruction
|= neon_quad (rs
) << 6;
13780 inst
.instruction
|= imm
<< 8;
13782 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13788 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13789 struct neon_type_el et
= neon_check_type (2, rs
,
13790 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13791 unsigned op
= (inst
.instruction
>> 7) & 3;
13792 /* N (width of reversed regions) is encoded as part of the bitmask. We
13793 extract it here to check the elements to be reversed are smaller.
13794 Otherwise we'd get a reserved instruction. */
13795 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
13796 gas_assert (elsize
!= 0);
13797 constraint (et
.size
>= elsize
,
13798 _("elements must be smaller than reversal region"));
13799 neon_two_same (neon_quad (rs
), 1, et
.size
);
13805 if (inst
.operands
[1].isscalar
)
13807 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
13808 struct neon_type_el et
= neon_check_type (2, rs
,
13809 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13810 unsigned sizebits
= et
.size
>> 3;
13811 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13812 int logsize
= neon_logbits (et
.size
);
13813 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
13815 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
13818 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13819 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13820 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13821 inst
.instruction
|= LOW4 (dm
);
13822 inst
.instruction
|= HI1 (dm
) << 5;
13823 inst
.instruction
|= neon_quad (rs
) << 6;
13824 inst
.instruction
|= x
<< 17;
13825 inst
.instruction
|= sizebits
<< 16;
13827 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13831 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13832 struct neon_type_el et
= neon_check_type (2, rs
,
13833 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13834 /* Duplicate ARM register to lanes of vector. */
13835 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13838 case 8: inst
.instruction
|= 0x400000; break;
13839 case 16: inst
.instruction
|= 0x000020; break;
13840 case 32: inst
.instruction
|= 0x000000; break;
13843 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13844 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13845 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13846 inst
.instruction
|= neon_quad (rs
) << 21;
13847 /* The encoding for this instruction is identical for the ARM and Thumb
13848 variants, except for the condition field. */
13849 do_vfp_cond_or_thumb ();
13853 /* VMOV has particularly many variations. It can be one of:
13854 0. VMOV<c><q> <Qd>, <Qm>
13855 1. VMOV<c><q> <Dd>, <Dm>
13856 (Register operations, which are VORR with Rm = Rn.)
13857 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13858 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13860 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13861 (ARM register to scalar.)
13862 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13863 (Two ARM registers to vector.)
13864 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13865 (Scalar to ARM register.)
13866 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13867 (Vector to two ARM registers.)
13868 8. VMOV.F32 <Sd>, <Sm>
13869 9. VMOV.F64 <Dd>, <Dm>
13870 (VFP register moves.)
13871 10. VMOV.F32 <Sd>, #imm
13872 11. VMOV.F64 <Dd>, #imm
13873 (VFP float immediate load.)
13874 12. VMOV <Rd>, <Sm>
13875 (VFP single to ARM reg.)
13876 13. VMOV <Sd>, <Rm>
13877 (ARM reg to VFP single.)
13878 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13879 (Two ARM regs to two VFP singles.)
13880 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13881 (Two VFP singles to two ARM regs.)
13883 These cases can be disambiguated using neon_select_shape, except cases 1/9
13884 and 3/11 which depend on the operand type too.
13886 All the encoded bits are hardcoded by this function.
13888 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13889 Cases 5, 7 may be used with VFPv2 and above.
13891 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13892 can specify a type where it doesn't make sense to, and is ignored). */
13897 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
13898 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
13900 struct neon_type_el et
;
13901 const char *ldconst
= 0;
13905 case NS_DD
: /* case 1/9. */
13906 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13907 /* It is not an error here if no type is given. */
13909 if (et
.type
== NT_float
&& et
.size
== 64)
13911 do_vfp_nsyn_opcode ("fcpyd");
13914 /* fall through. */
13916 case NS_QQ
: /* case 0/1. */
13918 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13920 /* The architecture manual I have doesn't explicitly state which
13921 value the U bit should have for register->register moves, but
13922 the equivalent VORR instruction has U = 0, so do that. */
13923 inst
.instruction
= 0x0200110;
13924 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13925 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13926 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13927 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13928 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13929 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13930 inst
.instruction
|= neon_quad (rs
) << 6;
13932 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13936 case NS_DI
: /* case 3/11. */
13937 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13939 if (et
.type
== NT_float
&& et
.size
== 64)
13941 /* case 11 (fconstd). */
13942 ldconst
= "fconstd";
13943 goto encode_fconstd
;
13945 /* fall through. */
13947 case NS_QI
: /* case 2/3. */
13948 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13950 inst
.instruction
= 0x0800010;
13951 neon_move_immediate ();
13952 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13955 case NS_SR
: /* case 4. */
13957 unsigned bcdebits
= 0;
13958 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13959 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13960 int logsize
= neon_logbits (et
.size
);
13961 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
13962 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
13964 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13966 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13967 && et
.size
!= 32, _(BAD_FPU
));
13968 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13969 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13973 case 8: bcdebits
= 0x8; break;
13974 case 16: bcdebits
= 0x1; break;
13975 case 32: bcdebits
= 0x0; break;
13979 bcdebits
|= x
<< logsize
;
13981 inst
.instruction
= 0xe000b10;
13982 do_vfp_cond_or_thumb ();
13983 inst
.instruction
|= LOW4 (dn
) << 16;
13984 inst
.instruction
|= HI1 (dn
) << 7;
13985 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13986 inst
.instruction
|= (bcdebits
& 3) << 5;
13987 inst
.instruction
|= (bcdebits
>> 2) << 21;
13991 case NS_DRR
: /* case 5 (fmdrr). */
13992 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13995 inst
.instruction
= 0xc400b10;
13996 do_vfp_cond_or_thumb ();
13997 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
13998 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
13999 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14000 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14003 case NS_RS
: /* case 6. */
14005 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
14006 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14007 unsigned logsize
= neon_logbits (et
.size
);
14008 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14009 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14010 unsigned abcdebits
= 0;
14012 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14014 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14015 && et
.size
!= 32, _(BAD_FPU
));
14016 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14017 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14021 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14022 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14023 case 32: abcdebits
= 0x00; break;
14027 abcdebits
|= x
<< logsize
;
14028 inst
.instruction
= 0xe100b10;
14029 do_vfp_cond_or_thumb ();
14030 inst
.instruction
|= LOW4 (dn
) << 16;
14031 inst
.instruction
|= HI1 (dn
) << 7;
14032 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14033 inst
.instruction
|= (abcdebits
& 3) << 5;
14034 inst
.instruction
|= (abcdebits
>> 2) << 21;
14038 case NS_RRD
: /* case 7 (fmrrd). */
14039 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14042 inst
.instruction
= 0xc500b10;
14043 do_vfp_cond_or_thumb ();
14044 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14045 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14046 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14047 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14050 case NS_FF
: /* case 8 (fcpys). */
14051 do_vfp_nsyn_opcode ("fcpys");
14054 case NS_FI
: /* case 10 (fconsts). */
14055 ldconst
= "fconsts";
14057 if (is_quarter_float (inst
.operands
[1].imm
))
14059 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14060 do_vfp_nsyn_opcode (ldconst
);
14063 first_error (_("immediate out of range"));
14066 case NS_RF
: /* case 12 (fmrs). */
14067 do_vfp_nsyn_opcode ("fmrs");
14070 case NS_FR
: /* case 13 (fmsr). */
14071 do_vfp_nsyn_opcode ("fmsr");
14074 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14075 (one of which is a list), but we have parsed four. Do some fiddling to
14076 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14078 case NS_RRFF
: /* case 14 (fmrrs). */
14079 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14080 _("VFP registers must be adjacent"));
14081 inst
.operands
[2].imm
= 2;
14082 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14083 do_vfp_nsyn_opcode ("fmrrs");
14086 case NS_FFRR
: /* case 15 (fmsrr). */
14087 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14088 _("VFP registers must be adjacent"));
14089 inst
.operands
[1] = inst
.operands
[2];
14090 inst
.operands
[2] = inst
.operands
[3];
14091 inst
.operands
[0].imm
= 2;
14092 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14093 do_vfp_nsyn_opcode ("fmsrr");
14102 do_neon_rshift_round_imm (void)
14104 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14105 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14106 int imm
= inst
.operands
[2].imm
;
14108 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14111 inst
.operands
[2].present
= 0;
14116 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14117 _("immediate out of range for shift"));
14118 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14123 do_neon_movl (void)
14125 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14126 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14127 unsigned sizebits
= et
.size
>> 3;
14128 inst
.instruction
|= sizebits
<< 19;
14129 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14135 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14136 struct neon_type_el et
= neon_check_type (2, rs
,
14137 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14138 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
14139 neon_two_same (neon_quad (rs
), 1, et
.size
);
14143 do_neon_zip_uzp (void)
14145 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14146 struct neon_type_el et
= neon_check_type (2, rs
,
14147 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14148 if (rs
== NS_DD
&& et
.size
== 32)
14150 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14151 inst
.instruction
= N_MNEM_vtrn
;
14155 neon_two_same (neon_quad (rs
), 1, et
.size
);
14159 do_neon_sat_abs_neg (void)
14161 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14162 struct neon_type_el et
= neon_check_type (2, rs
,
14163 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14164 neon_two_same (neon_quad (rs
), 1, et
.size
);
14168 do_neon_pair_long (void)
14170 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14171 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14172 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14173 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14174 neon_two_same (neon_quad (rs
), 1, et
.size
);
14178 do_neon_recip_est (void)
14180 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14181 struct neon_type_el et
= neon_check_type (2, rs
,
14182 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14183 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14184 neon_two_same (neon_quad (rs
), 1, et
.size
);
14190 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14191 struct neon_type_el et
= neon_check_type (2, rs
,
14192 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14193 neon_two_same (neon_quad (rs
), 1, et
.size
);
14199 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14200 struct neon_type_el et
= neon_check_type (2, rs
,
14201 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14202 neon_two_same (neon_quad (rs
), 1, et
.size
);
14208 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14209 struct neon_type_el et
= neon_check_type (2, rs
,
14210 N_EQK
| N_INT
, N_8
| N_KEY
);
14211 neon_two_same (neon_quad (rs
), 1, et
.size
);
14217 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14218 neon_two_same (neon_quad (rs
), 1, -1);
14222 do_neon_tbl_tbx (void)
14224 unsigned listlenbits
;
14225 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14227 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14229 first_error (_("bad list length for table lookup"));
14233 listlenbits
= inst
.operands
[1].imm
- 1;
14234 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14235 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14236 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14237 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14238 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14239 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14240 inst
.instruction
|= listlenbits
<< 8;
14242 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14246 do_neon_ldm_stm (void)
14248 /* P, U and L bits are part of bitmask. */
14249 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14250 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14252 if (inst
.operands
[1].issingle
)
14254 do_vfp_nsyn_ldm_stm (is_dbmode
);
14258 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14259 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14261 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14262 _("register list must contain at least 1 and at most 16 "
14265 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14266 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14267 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14268 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14270 inst
.instruction
|= offsetbits
;
14272 do_vfp_cond_or_thumb ();
14276 do_neon_ldr_str (void)
14278 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14280 if (inst
.operands
[0].issingle
)
14283 do_vfp_nsyn_opcode ("flds");
14285 do_vfp_nsyn_opcode ("fsts");
14290 do_vfp_nsyn_opcode ("fldd");
14292 do_vfp_nsyn_opcode ("fstd");
14296 /* "interleave" version also handles non-interleaving register VLD1/VST1
14300 do_neon_ld_st_interleave (void)
14302 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14303 N_8
| N_16
| N_32
| N_64
);
14304 unsigned alignbits
= 0;
14306 /* The bits in this table go:
14307 0: register stride of one (0) or two (1)
14308 1,2: register list length, minus one (1, 2, 3, 4).
14309 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14310 We use -1 for invalid entries. */
14311 const int typetable
[] =
14313 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14314 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14315 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14316 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14320 if (et
.type
== NT_invtype
)
14323 if (inst
.operands
[1].immisalign
)
14324 switch (inst
.operands
[1].imm
>> 8)
14326 case 64: alignbits
= 1; break;
14328 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14329 goto bad_alignment
;
14333 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14334 goto bad_alignment
;
14339 first_error (_("bad alignment"));
14343 inst
.instruction
|= alignbits
<< 4;
14344 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14346 /* Bits [4:6] of the immediate in a list specifier encode register stride
14347 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14348 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14349 up the right value for "type" in a table based on this value and the given
14350 list style, then stick it back. */
14351 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14352 | (((inst
.instruction
>> 8) & 3) << 3);
14354 typebits
= typetable
[idx
];
14356 constraint (typebits
== -1, _("bad list type for instruction"));
14358 inst
.instruction
&= ~0xf00;
14359 inst
.instruction
|= typebits
<< 8;
14362 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14363 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14364 otherwise. The variable arguments are a list of pairs of legal (size, align)
14365 values, terminated with -1. */
14368 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14371 int result
= FAIL
, thissize
, thisalign
;
14373 if (!inst
.operands
[1].immisalign
)
14379 va_start (ap
, do_align
);
14383 thissize
= va_arg (ap
, int);
14384 if (thissize
== -1)
14386 thisalign
= va_arg (ap
, int);
14388 if (size
== thissize
&& align
== thisalign
)
14391 while (result
!= SUCCESS
);
14395 if (result
== SUCCESS
)
14398 first_error (_("unsupported alignment for instruction"));
14404 do_neon_ld_st_lane (void)
14406 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14407 int align_good
, do_align
= 0;
14408 int logsize
= neon_logbits (et
.size
);
14409 int align
= inst
.operands
[1].imm
>> 8;
14410 int n
= (inst
.instruction
>> 8) & 3;
14411 int max_el
= 64 / et
.size
;
14413 if (et
.type
== NT_invtype
)
14416 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14417 _("bad list length"));
14418 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14419 _("scalar index out of range"));
14420 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14422 _("stride of 2 unavailable when element size is 8"));
14426 case 0: /* VLD1 / VST1. */
14427 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14429 if (align_good
== FAIL
)
14433 unsigned alignbits
= 0;
14436 case 16: alignbits
= 0x1; break;
14437 case 32: alignbits
= 0x3; break;
14440 inst
.instruction
|= alignbits
<< 4;
14444 case 1: /* VLD2 / VST2. */
14445 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14447 if (align_good
== FAIL
)
14450 inst
.instruction
|= 1 << 4;
14453 case 2: /* VLD3 / VST3. */
14454 constraint (inst
.operands
[1].immisalign
,
14455 _("can't use alignment with this instruction"));
14458 case 3: /* VLD4 / VST4. */
14459 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14460 16, 64, 32, 64, 32, 128, -1);
14461 if (align_good
== FAIL
)
14465 unsigned alignbits
= 0;
14468 case 8: alignbits
= 0x1; break;
14469 case 16: alignbits
= 0x1; break;
14470 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14473 inst
.instruction
|= alignbits
<< 4;
14480 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14481 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14482 inst
.instruction
|= 1 << (4 + logsize
);
14484 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14485 inst
.instruction
|= logsize
<< 10;
14488 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14491 do_neon_ld_dup (void)
14493 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14494 int align_good
, do_align
= 0;
14496 if (et
.type
== NT_invtype
)
14499 switch ((inst
.instruction
>> 8) & 3)
14501 case 0: /* VLD1. */
14502 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14503 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14504 &do_align
, 16, 16, 32, 32, -1);
14505 if (align_good
== FAIL
)
14507 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14510 case 2: inst
.instruction
|= 1 << 5; break;
14511 default: first_error (_("bad list length")); return;
14513 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14516 case 1: /* VLD2. */
14517 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14518 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14519 if (align_good
== FAIL
)
14521 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14522 _("bad list length"));
14523 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14524 inst
.instruction
|= 1 << 5;
14525 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14528 case 2: /* VLD3. */
14529 constraint (inst
.operands
[1].immisalign
,
14530 _("can't use alignment with this instruction"));
14531 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14532 _("bad list length"));
14533 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14534 inst
.instruction
|= 1 << 5;
14535 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14538 case 3: /* VLD4. */
14540 int align
= inst
.operands
[1].imm
>> 8;
14541 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14542 16, 64, 32, 64, 32, 128, -1);
14543 if (align_good
== FAIL
)
14545 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14546 _("bad list length"));
14547 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14548 inst
.instruction
|= 1 << 5;
14549 if (et
.size
== 32 && align
== 128)
14550 inst
.instruction
|= 0x3 << 6;
14552 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14559 inst
.instruction
|= do_align
<< 4;
14562 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14563 apart from bits [11:4]. */
14566 do_neon_ldx_stx (void)
14568 switch (NEON_LANE (inst
.operands
[0].imm
))
14570 case NEON_INTERLEAVE_LANES
:
14571 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
14572 do_neon_ld_st_interleave ();
14575 case NEON_ALL_LANES
:
14576 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
14581 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
14582 do_neon_ld_st_lane ();
14585 /* L bit comes from bit mask. */
14586 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14587 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14588 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14590 if (inst
.operands
[1].postind
)
14592 int postreg
= inst
.operands
[1].imm
& 0xf;
14593 constraint (!inst
.operands
[1].immisreg
,
14594 _("post-index must be a register"));
14595 constraint (postreg
== 0xd || postreg
== 0xf,
14596 _("bad register for post-index"));
14597 inst
.instruction
|= postreg
;
14599 else if (inst
.operands
[1].writeback
)
14601 inst
.instruction
|= 0xd;
14604 inst
.instruction
|= 0xf;
14607 inst
.instruction
|= 0xf9000000;
14609 inst
.instruction
|= 0xf4000000;
14612 /* Overall per-instruction processing. */
14614 /* We need to be able to fix up arbitrary expressions in some statements.
14615 This is so that we can handle symbols that are an arbitrary distance from
14616 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
14617 which returns part of an address in a form which will be valid for
14618 a data instruction. We do this by pushing the expression into a symbol
14619 in the expr_section, and creating a fix for that. */
14622 fix_new_arm (fragS
* frag
,
14637 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
14641 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
14646 /* Mark whether the fix is to a THUMB instruction, or an ARM
14648 new_fix
->tc_fix_data
= thumb_mode
;
14651 /* Create a frg for an instruction requiring relaxation. */
14653 output_relax_insn (void)
14659 /* The size of the instruction is unknown, so tie the debug info to the
14660 start of the instruction. */
14661 dwarf2_emit_insn (0);
14663 switch (inst
.reloc
.exp
.X_op
)
14666 sym
= inst
.reloc
.exp
.X_add_symbol
;
14667 offset
= inst
.reloc
.exp
.X_add_number
;
14671 offset
= inst
.reloc
.exp
.X_add_number
;
14674 sym
= make_expr_symbol (&inst
.reloc
.exp
);
14678 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
14679 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
14680 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
14683 /* Write a 32-bit thumb instruction to buf. */
14685 put_thumb32_insn (char * buf
, unsigned long insn
)
14687 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
14688 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
14692 output_inst (const char * str
)
14698 as_bad ("%s -- `%s'", inst
.error
, str
);
14703 output_relax_insn ();
14706 if (inst
.size
== 0)
14709 to
= frag_more (inst
.size
);
14710 /* PR 9814: Record the thumb mode into the current frag so that we know
14711 what type of NOP padding to use, if necessary. We override any previous
14712 setting so that if the mode has changed then the NOPS that we use will
14713 match the encoding of the last instruction in the frag. */
14714 frag_now
->tc_frag_data
= thumb_mode
| MODE_RECORDED
;
14716 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
14718 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
14719 put_thumb32_insn (to
, inst
.instruction
);
14721 else if (inst
.size
> INSN_SIZE
)
14723 gas_assert (inst
.size
== (2 * INSN_SIZE
));
14724 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
14725 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
14728 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
14730 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
14731 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
14732 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
14735 dwarf2_emit_insn (inst
.size
);
14739 output_it_inst (int cond
, int mask
, char * to
)
14741 unsigned long instruction
= 0xbf00;
14744 instruction
|= mask
;
14745 instruction
|= cond
<< 4;
14749 to
= frag_more (2);
14751 dwarf2_emit_insn (2);
14755 md_number_to_chars (to
, instruction
, 2);
14760 /* Tag values used in struct asm_opcode's tag field. */
14763 OT_unconditional
, /* Instruction cannot be conditionalized.
14764 The ARM condition field is still 0xE. */
14765 OT_unconditionalF
, /* Instruction cannot be conditionalized
14766 and carries 0xF in its ARM condition field. */
14767 OT_csuffix
, /* Instruction takes a conditional suffix. */
14768 OT_csuffixF
, /* Some forms of the instruction take a conditional
14769 suffix, others place 0xF where the condition field
14771 OT_cinfix3
, /* Instruction takes a conditional infix,
14772 beginning at character index 3. (In
14773 unified mode, it becomes a suffix.) */
14774 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
14775 tsts, cmps, cmns, and teqs. */
14776 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
14777 character index 3, even in unified mode. Used for
14778 legacy instructions where suffix and infix forms
14779 may be ambiguous. */
14780 OT_csuf_or_in3
, /* Instruction takes either a conditional
14781 suffix or an infix at character index 3. */
14782 OT_odd_infix_unc
, /* This is the unconditional variant of an
14783 instruction that takes a conditional infix
14784 at an unusual position. In unified mode,
14785 this variant will accept a suffix. */
14786 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
14787 are the conditional variants of instructions that
14788 take conditional infixes in unusual positions.
14789 The infix appears at character index
14790 (tag - OT_odd_infix_0). These are not accepted
14791 in unified mode. */
14794 /* Subroutine of md_assemble, responsible for looking up the primary
14795 opcode from the mnemonic the user wrote. STR points to the
14796 beginning of the mnemonic.
14798 This is not simply a hash table lookup, because of conditional
14799 variants. Most instructions have conditional variants, which are
14800 expressed with a _conditional affix_ to the mnemonic. If we were
14801 to encode each conditional variant as a literal string in the opcode
14802 table, it would have approximately 20,000 entries.
14804 Most mnemonics take this affix as a suffix, and in unified syntax,
14805 'most' is upgraded to 'all'. However, in the divided syntax, some
14806 instructions take the affix as an infix, notably the s-variants of
14807 the arithmetic instructions. Of those instructions, all but six
14808 have the infix appear after the third character of the mnemonic.
14810 Accordingly, the algorithm for looking up primary opcodes given
14813 1. Look up the identifier in the opcode table.
14814 If we find a match, go to step U.
14816 2. Look up the last two characters of the identifier in the
14817 conditions table. If we find a match, look up the first N-2
14818 characters of the identifier in the opcode table. If we
14819 find a match, go to step CE.
14821 3. Look up the fourth and fifth characters of the identifier in
14822 the conditions table. If we find a match, extract those
14823 characters from the identifier, and look up the remaining
14824 characters in the opcode table. If we find a match, go
14829 U. Examine the tag field of the opcode structure, in case this is
14830 one of the six instructions with its conditional infix in an
14831 unusual place. If it is, the tag tells us where to find the
14832 infix; look it up in the conditions table and set inst.cond
14833 accordingly. Otherwise, this is an unconditional instruction.
14834 Again set inst.cond accordingly. Return the opcode structure.
14836 CE. Examine the tag field to make sure this is an instruction that
14837 should receive a conditional suffix. If it is not, fail.
14838 Otherwise, set inst.cond from the suffix we already looked up,
14839 and return the opcode structure.
14841 CM. Examine the tag field to make sure this is an instruction that
14842 should receive a conditional infix after the third character.
14843 If it is not, fail. Otherwise, undo the edits to the current
14844 line of input and proceed as for case CE. */
14846 static const struct asm_opcode
*
14847 opcode_lookup (char **str
)
14851 const struct asm_opcode
*opcode
;
14852 const struct asm_cond
*cond
;
14854 bfd_boolean neon_supported
;
14856 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
14858 /* Scan up to the end of the mnemonic, which must end in white space,
14859 '.' (in unified mode, or for Neon instructions), or end of string. */
14860 for (base
= end
= *str
; *end
!= '\0'; end
++)
14861 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
14867 /* Handle a possible width suffix and/or Neon type suffix. */
14872 /* The .w and .n suffixes are only valid if the unified syntax is in
14874 if (unified_syntax
&& end
[1] == 'w')
14876 else if (unified_syntax
&& end
[1] == 'n')
14881 inst
.vectype
.elems
= 0;
14883 *str
= end
+ offset
;
14885 if (end
[offset
] == '.')
14887 /* See if we have a Neon type suffix (possible in either unified or
14888 non-unified ARM syntax mode). */
14889 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14892 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14898 /* Look for unaffixed or special-case affixed mnemonic. */
14899 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
14903 if (opcode
->tag
< OT_odd_infix_0
)
14905 inst
.cond
= COND_ALWAYS
;
14909 if (warn_on_deprecated
&& unified_syntax
)
14910 as_warn (_("conditional infixes are deprecated in unified syntax"));
14911 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
14912 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14915 inst
.cond
= cond
->value
;
14919 /* Cannot have a conditional suffix on a mnemonic of less than two
14921 if (end
- base
< 3)
14924 /* Look for suffixed mnemonic. */
14926 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14927 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
14928 if (opcode
&& cond
)
14931 switch (opcode
->tag
)
14933 case OT_cinfix3_legacy
:
14934 /* Ignore conditional suffixes matched on infix only mnemonics. */
14938 case OT_cinfix3_deprecated
:
14939 case OT_odd_infix_unc
:
14940 if (!unified_syntax
)
14942 /* else fall through */
14946 case OT_csuf_or_in3
:
14947 inst
.cond
= cond
->value
;
14950 case OT_unconditional
:
14951 case OT_unconditionalF
:
14953 inst
.cond
= cond
->value
;
14956 /* Delayed diagnostic. */
14957 inst
.error
= BAD_COND
;
14958 inst
.cond
= COND_ALWAYS
;
14967 /* Cannot have a usual-position infix on a mnemonic of less than
14968 six characters (five would be a suffix). */
14969 if (end
- base
< 6)
14972 /* Look for infixed mnemonic in the usual position. */
14974 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14978 memcpy (save
, affix
, 2);
14979 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
14980 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
14981 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
14982 memcpy (affix
, save
, 2);
14985 && (opcode
->tag
== OT_cinfix3
14986 || opcode
->tag
== OT_cinfix3_deprecated
14987 || opcode
->tag
== OT_csuf_or_in3
14988 || opcode
->tag
== OT_cinfix3_legacy
))
14991 if (warn_on_deprecated
&& unified_syntax
14992 && (opcode
->tag
== OT_cinfix3
14993 || opcode
->tag
== OT_cinfix3_deprecated
))
14994 as_warn (_("conditional infixes are deprecated in unified syntax"));
14996 inst
.cond
= cond
->value
;
15003 /* This function generates an initial IT instruction, leaving its block
15004 virtually open for the new instructions. Eventually,
15005 the mask will be updated by now_it_add_mask () each time
15006 a new instruction needs to be included in the IT block.
15007 Finally, the block is closed with close_automatic_it_block ().
15008 The block closure can be requested either from md_assemble (),
15009 a tencode (), or due to a label hook. */
15012 new_automatic_it_block (int cond
)
15014 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15015 now_it
.mask
= 0x18;
15017 now_it
.block_length
= 1;
15018 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15021 /* Close an automatic IT block.
15022 See comments in new_automatic_it_block (). */
15025 close_automatic_it_block (void)
15027 now_it
.mask
= 0x10;
15028 now_it
.block_length
= 0;
15031 /* Update the mask of the current automatically-generated IT
15032 instruction. See comments in new_automatic_it_block (). */
15035 now_it_add_mask (int cond
)
15037 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15038 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15039 | ((bitvalue) << (nbit)))
15040 const int resulting_bit
= (cond
& 1);
15042 now_it
.mask
&= 0xf;
15043 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15045 (5 - now_it
.block_length
));
15046 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15048 ((5 - now_it
.block_length
) - 1) );
15049 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15052 #undef SET_BIT_VALUE
15055 /* The IT blocks handling machinery is accessed through the these functions:
15056 it_fsm_pre_encode () from md_assemble ()
15057 set_it_insn_type () optional, from the tencode functions
15058 set_it_insn_type_last () ditto
15059 in_it_block () ditto
15060 it_fsm_post_encode () from md_assemble ()
15061 force_automatic_it_block_close () from label habdling functions
15064 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15065 initializing the IT insn type with a generic initial value depending
15066 on the inst.condition.
15067 2) During the tencode function, two things may happen:
15068 a) The tencode function overrides the IT insn type by
15069 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15070 b) The tencode function queries the IT block state by
15071 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15073 Both set_it_insn_type and in_it_block run the internal FSM state
15074 handling function (handle_it_state), because: a) setting the IT insn
15075 type may incur in an invalid state (exiting the function),
15076 and b) querying the state requires the FSM to be updated.
15077 Specifically we want to avoid creating an IT block for conditional
15078 branches, so it_fsm_pre_encode is actually a guess and we can't
15079 determine whether an IT block is required until the tencode () routine
15080 has decided what type of instruction this actually it.
15081 Because of this, if set_it_insn_type and in_it_block have to be used,
15082 set_it_insn_type has to be called first.
15084 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15085 determines the insn IT type depending on the inst.cond code.
15086 When a tencode () routine encodes an instruction that can be
15087 either outside an IT block, or, in the case of being inside, has to be
15088 the last one, set_it_insn_type_last () will determine the proper
15089 IT instruction type based on the inst.cond code. Otherwise,
15090 set_it_insn_type can be called for overriding that logic or
15091 for covering other cases.
15093 Calling handle_it_state () may not transition the IT block state to
15094 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15095 still queried. Instead, if the FSM determines that the state should
15096 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15097 after the tencode () function: that's what it_fsm_post_encode () does.
15099 Since in_it_block () calls the state handling function to get an
15100 updated state, an error may occur (due to invalid insns combination).
15101 In that case, inst.error is set.
15102 Therefore, inst.error has to be checked after the execution of
15103 the tencode () routine.
15105 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15106 any pending state change (if any) that didn't take place in
15107 handle_it_state () as explained above. */
15110 it_fsm_pre_encode (void)
15112 if (inst
.cond
!= COND_ALWAYS
)
15113 inst
.it_insn_type
= INSIDE_IT_INSN
;
15115 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15117 now_it
.state_handled
= 0;
15120 /* IT state FSM handling function. */
15123 handle_it_state (void)
15125 now_it
.state_handled
= 1;
15127 switch (now_it
.state
)
15129 case OUTSIDE_IT_BLOCK
:
15130 switch (inst
.it_insn_type
)
15132 case OUTSIDE_IT_INSN
:
15135 case INSIDE_IT_INSN
:
15136 case INSIDE_IT_LAST_INSN
:
15137 if (thumb_mode
== 0)
15140 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15141 as_tsktsk (_("Warning: conditional outside an IT block"\
15146 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15147 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15149 /* Automatically generate the IT instruction. */
15150 new_automatic_it_block (inst
.cond
);
15151 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15152 close_automatic_it_block ();
15156 inst
.error
= BAD_OUT_IT
;
15162 case IF_INSIDE_IT_LAST_INSN
:
15163 case NEUTRAL_IT_INSN
:
15167 now_it
.state
= MANUAL_IT_BLOCK
;
15168 now_it
.block_length
= 0;
15173 case AUTOMATIC_IT_BLOCK
:
15174 /* Three things may happen now:
15175 a) We should increment current it block size;
15176 b) We should close current it block (closing insn or 4 insns);
15177 c) We should close current it block and start a new one (due
15178 to incompatible conditions or
15179 4 insns-length block reached). */
15181 switch (inst
.it_insn_type
)
15183 case OUTSIDE_IT_INSN
:
15184 /* The closure of the block shall happen immediatelly,
15185 so any in_it_block () call reports the block as closed. */
15186 force_automatic_it_block_close ();
15189 case INSIDE_IT_INSN
:
15190 case INSIDE_IT_LAST_INSN
:
15191 case IF_INSIDE_IT_LAST_INSN
:
15192 now_it
.block_length
++;
15194 if (now_it
.block_length
> 4
15195 || !now_it_compatible (inst
.cond
))
15197 force_automatic_it_block_close ();
15198 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15199 new_automatic_it_block (inst
.cond
);
15203 now_it_add_mask (inst
.cond
);
15206 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15207 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15208 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15209 close_automatic_it_block ();
15212 case NEUTRAL_IT_INSN
:
15213 now_it
.block_length
++;
15215 if (now_it
.block_length
> 4)
15216 force_automatic_it_block_close ();
15218 now_it_add_mask (now_it
.cc
& 1);
15222 close_automatic_it_block ();
15223 now_it
.state
= MANUAL_IT_BLOCK
;
15228 case MANUAL_IT_BLOCK
:
15230 /* Check conditional suffixes. */
15231 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15234 now_it
.mask
&= 0x1f;
15235 is_last
= (now_it
.mask
== 0x10);
15237 switch (inst
.it_insn_type
)
15239 case OUTSIDE_IT_INSN
:
15240 inst
.error
= BAD_NOT_IT
;
15243 case INSIDE_IT_INSN
:
15244 if (cond
!= inst
.cond
)
15246 inst
.error
= BAD_IT_COND
;
15251 case INSIDE_IT_LAST_INSN
:
15252 case IF_INSIDE_IT_LAST_INSN
:
15253 if (cond
!= inst
.cond
)
15255 inst
.error
= BAD_IT_COND
;
15260 inst
.error
= BAD_BRANCH
;
15265 case NEUTRAL_IT_INSN
:
15266 /* The BKPT instruction is unconditional even in an IT block. */
15270 inst
.error
= BAD_IT_IT
;
15281 it_fsm_post_encode (void)
15285 if (!now_it
.state_handled
)
15286 handle_it_state ();
15288 is_last
= (now_it
.mask
== 0x10);
15291 now_it
.state
= OUTSIDE_IT_BLOCK
;
15297 force_automatic_it_block_close (void)
15299 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15301 close_automatic_it_block ();
15302 now_it
.state
= OUTSIDE_IT_BLOCK
;
15310 if (!now_it
.state_handled
)
15311 handle_it_state ();
15313 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15317 md_assemble (char *str
)
15320 const struct asm_opcode
* opcode
;
15322 /* Align the previous label if needed. */
15323 if (last_label_seen
!= NULL
)
15325 symbol_set_frag (last_label_seen
, frag_now
);
15326 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15327 S_SET_SEGMENT (last_label_seen
, now_seg
);
15330 memset (&inst
, '\0', sizeof (inst
));
15331 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15333 opcode
= opcode_lookup (&p
);
15336 /* It wasn't an instruction, but it might be a register alias of
15337 the form alias .req reg, or a Neon .dn/.qn directive. */
15338 if (! create_register_alias (str
, p
)
15339 && ! create_neon_reg_alias (str
, p
))
15340 as_bad (_("bad instruction `%s'"), str
);
15345 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15346 as_warn (_("s suffix on comparison instruction is deprecated"));
15348 /* The value which unconditional instructions should have in place of the
15349 condition field. */
15350 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15354 arm_feature_set variant
;
15356 variant
= cpu_variant
;
15357 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15358 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15359 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15360 /* Check that this instruction is supported for this CPU. */
15361 if (!opcode
->tvariant
15362 || (thumb_mode
== 1
15363 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15365 as_bad (_("selected processor does not support `%s'"), str
);
15368 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15369 && opcode
->tencode
!= do_t_branch
)
15371 as_bad (_("Thumb does not support conditional execution"));
15375 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15377 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15378 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15379 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15381 /* Two things are addressed here.
15382 1) Implicit require narrow instructions on Thumb-1.
15383 This avoids relaxation accidentally introducing Thumb-2
15385 2) Reject wide instructions in non Thumb-2 cores. */
15386 if (inst
.size_req
== 0)
15388 else if (inst
.size_req
== 4)
15390 as_bad (_("selected processor does not support `%s'"), str
);
15396 mapping_state (MAP_THUMB
);
15397 inst
.instruction
= opcode
->tvalue
;
15399 if (!parse_operands (p
, opcode
->operands
))
15401 /* Prepare the it_insn_type for those encodings that don't set
15403 it_fsm_pre_encode ();
15405 opcode
->tencode ();
15407 it_fsm_post_encode ();
15410 if (!(inst
.error
|| inst
.relax
))
15412 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15413 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15414 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15416 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15421 /* Something has gone badly wrong if we try to relax a fixed size
15423 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15425 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15426 *opcode
->tvariant
);
15427 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15428 set those bits when Thumb-2 32-bit instructions are seen. ie.
15429 anything other than bl/blx and v6-M instructions.
15430 This is overly pessimistic for relaxable instructions. */
15431 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15433 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15434 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15435 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15438 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15442 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15443 is_bx
= (opcode
->aencode
== do_bx
);
15445 /* Check that this instruction is supported for this CPU. */
15446 if (!(is_bx
&& fix_v4bx
)
15447 && !(opcode
->avariant
&&
15448 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15450 as_bad (_("selected processor does not support `%s'"), str
);
15455 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15459 mapping_state (MAP_ARM
);
15460 inst
.instruction
= opcode
->avalue
;
15461 if (opcode
->tag
== OT_unconditionalF
)
15462 inst
.instruction
|= 0xF << 28;
15464 inst
.instruction
|= inst
.cond
<< 28;
15465 inst
.size
= INSN_SIZE
;
15466 if (!parse_operands (p
, opcode
->operands
))
15468 it_fsm_pre_encode ();
15469 opcode
->aencode ();
15470 it_fsm_post_encode ();
15472 /* Arm mode bx is marked as both v4T and v5 because it's still required
15473 on a hypothetical non-thumb v5 core. */
15475 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15477 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15478 *opcode
->avariant
);
15482 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15490 check_it_blocks_finished (void)
15495 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15496 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15497 == MANUAL_IT_BLOCK
)
15499 as_warn (_("section '%s' finished with an open IT block."),
15503 if (now_it
.state
== MANUAL_IT_BLOCK
)
15504 as_warn (_("file finished with an open IT block."));
15508 /* Various frobbings of labels and their addresses. */
15511 arm_start_line_hook (void)
15513 last_label_seen
= NULL
;
15517 arm_frob_label (symbolS
* sym
)
15519 last_label_seen
= sym
;
15521 ARM_SET_THUMB (sym
, thumb_mode
);
15523 #if defined OBJ_COFF || defined OBJ_ELF
15524 ARM_SET_INTERWORK (sym
, support_interwork
);
15527 force_automatic_it_block_close ();
15529 /* Note - do not allow local symbols (.Lxxx) to be labelled
15530 as Thumb functions. This is because these labels, whilst
15531 they exist inside Thumb code, are not the entry points for
15532 possible ARM->Thumb calls. Also, these labels can be used
15533 as part of a computed goto or switch statement. eg gcc
15534 can generate code that looks like this:
15536 ldr r2, [pc, .Laaa]
15546 The first instruction loads the address of the jump table.
15547 The second instruction converts a table index into a byte offset.
15548 The third instruction gets the jump address out of the table.
15549 The fourth instruction performs the jump.
15551 If the address stored at .Laaa is that of a symbol which has the
15552 Thumb_Func bit set, then the linker will arrange for this address
15553 to have the bottom bit set, which in turn would mean that the
15554 address computation performed by the third instruction would end
15555 up with the bottom bit set. Since the ARM is capable of unaligned
15556 word loads, the instruction would then load the incorrect address
15557 out of the jump table, and chaos would ensue. */
15558 if (label_is_thumb_function_name
15559 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
15560 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
15562 /* When the address of a Thumb function is taken the bottom
15563 bit of that address should be set. This will allow
15564 interworking between Arm and Thumb functions to work
15567 THUMB_SET_FUNC (sym
, 1);
15569 label_is_thumb_function_name
= FALSE
;
15572 dwarf2_emit_label (sym
);
15576 arm_data_in_code (void)
15578 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
15580 *input_line_pointer
= '/';
15581 input_line_pointer
+= 5;
15582 *input_line_pointer
= 0;
15590 arm_canonicalize_symbol_name (char * name
)
15594 if (thumb_mode
&& (len
= strlen (name
)) > 5
15595 && streq (name
+ len
- 5, "/data"))
15596 *(name
+ len
- 5) = 0;
15601 /* Table of all register names defined by default. The user can
15602 define additional names with .req. Note that all register names
15603 should appear in both upper and lowercase variants. Some registers
15604 also have mixed-case names. */
15606 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
15607 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
15608 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
15609 #define REGSET(p,t) \
15610 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
15611 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
15612 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
15613 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
15614 #define REGSETH(p,t) \
15615 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
15616 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
15617 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
15618 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
15619 #define REGSET2(p,t) \
15620 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
15621 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
15622 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
15623 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
15625 static const struct reg_entry reg_names
[] =
15627 /* ARM integer registers. */
15628 REGSET(r
, RN
), REGSET(R
, RN
),
15630 /* ATPCS synonyms. */
15631 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
15632 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
15633 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
15635 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
15636 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
15637 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
15639 /* Well-known aliases. */
15640 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
15641 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
15643 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
15644 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
15646 /* Coprocessor numbers. */
15647 REGSET(p
, CP
), REGSET(P
, CP
),
15649 /* Coprocessor register numbers. The "cr" variants are for backward
15651 REGSET(c
, CN
), REGSET(C
, CN
),
15652 REGSET(cr
, CN
), REGSET(CR
, CN
),
15654 /* FPA registers. */
15655 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
15656 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
15658 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
15659 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
15661 /* VFP SP registers. */
15662 REGSET(s
,VFS
), REGSET(S
,VFS
),
15663 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
15665 /* VFP DP Registers. */
15666 REGSET(d
,VFD
), REGSET(D
,VFD
),
15667 /* Extra Neon DP registers. */
15668 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
15670 /* Neon QP registers. */
15671 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
15673 /* VFP control registers. */
15674 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
15675 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
15676 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
15677 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
15678 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
15679 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
15681 /* Maverick DSP coprocessor registers. */
15682 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
15683 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
15685 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
15686 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
15687 REGDEF(dspsc
,0,DSPSC
),
15689 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
15690 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
15691 REGDEF(DSPSC
,0,DSPSC
),
15693 /* iWMMXt data registers - p0, c0-15. */
15694 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
15696 /* iWMMXt control registers - p1, c0-3. */
15697 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
15698 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
15699 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
15700 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
15702 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
15703 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
15704 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
15705 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
15706 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
15708 /* XScale accumulator registers. */
15709 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
15715 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
15716 within psr_required_here. */
15717 static const struct asm_psr psrs
[] =
15719 /* Backward compatibility notation. Note that "all" is no longer
15720 truly all possible PSR bits. */
15721 {"all", PSR_c
| PSR_f
},
15725 /* Individual flags. */
15730 /* Combinations of flags. */
15731 {"fs", PSR_f
| PSR_s
},
15732 {"fx", PSR_f
| PSR_x
},
15733 {"fc", PSR_f
| PSR_c
},
15734 {"sf", PSR_s
| PSR_f
},
15735 {"sx", PSR_s
| PSR_x
},
15736 {"sc", PSR_s
| PSR_c
},
15737 {"xf", PSR_x
| PSR_f
},
15738 {"xs", PSR_x
| PSR_s
},
15739 {"xc", PSR_x
| PSR_c
},
15740 {"cf", PSR_c
| PSR_f
},
15741 {"cs", PSR_c
| PSR_s
},
15742 {"cx", PSR_c
| PSR_x
},
15743 {"fsx", PSR_f
| PSR_s
| PSR_x
},
15744 {"fsc", PSR_f
| PSR_s
| PSR_c
},
15745 {"fxs", PSR_f
| PSR_x
| PSR_s
},
15746 {"fxc", PSR_f
| PSR_x
| PSR_c
},
15747 {"fcs", PSR_f
| PSR_c
| PSR_s
},
15748 {"fcx", PSR_f
| PSR_c
| PSR_x
},
15749 {"sfx", PSR_s
| PSR_f
| PSR_x
},
15750 {"sfc", PSR_s
| PSR_f
| PSR_c
},
15751 {"sxf", PSR_s
| PSR_x
| PSR_f
},
15752 {"sxc", PSR_s
| PSR_x
| PSR_c
},
15753 {"scf", PSR_s
| PSR_c
| PSR_f
},
15754 {"scx", PSR_s
| PSR_c
| PSR_x
},
15755 {"xfs", PSR_x
| PSR_f
| PSR_s
},
15756 {"xfc", PSR_x
| PSR_f
| PSR_c
},
15757 {"xsf", PSR_x
| PSR_s
| PSR_f
},
15758 {"xsc", PSR_x
| PSR_s
| PSR_c
},
15759 {"xcf", PSR_x
| PSR_c
| PSR_f
},
15760 {"xcs", PSR_x
| PSR_c
| PSR_s
},
15761 {"cfs", PSR_c
| PSR_f
| PSR_s
},
15762 {"cfx", PSR_c
| PSR_f
| PSR_x
},
15763 {"csf", PSR_c
| PSR_s
| PSR_f
},
15764 {"csx", PSR_c
| PSR_s
| PSR_x
},
15765 {"cxf", PSR_c
| PSR_x
| PSR_f
},
15766 {"cxs", PSR_c
| PSR_x
| PSR_s
},
15767 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
15768 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
15769 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
15770 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
15771 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
15772 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
15773 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
15774 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
15775 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
15776 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
15777 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
15778 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
15779 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
15780 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
15781 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
15782 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
15783 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
15784 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
15785 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
15786 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
15787 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
15788 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
15789 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
15790 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
15793 /* Table of V7M psr names. */
15794 static const struct asm_psr v7m_psrs
[] =
15796 {"apsr", 0 }, {"APSR", 0 },
15797 {"iapsr", 1 }, {"IAPSR", 1 },
15798 {"eapsr", 2 }, {"EAPSR", 2 },
15799 {"psr", 3 }, {"PSR", 3 },
15800 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
15801 {"ipsr", 5 }, {"IPSR", 5 },
15802 {"epsr", 6 }, {"EPSR", 6 },
15803 {"iepsr", 7 }, {"IEPSR", 7 },
15804 {"msp", 8 }, {"MSP", 8 },
15805 {"psp", 9 }, {"PSP", 9 },
15806 {"primask", 16}, {"PRIMASK", 16},
15807 {"basepri", 17}, {"BASEPRI", 17},
15808 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
15809 {"faultmask", 19}, {"FAULTMASK", 19},
15810 {"control", 20}, {"CONTROL", 20}
15813 /* Table of all shift-in-operand names. */
15814 static const struct asm_shift_name shift_names
[] =
15816 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
15817 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
15818 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
15819 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
15820 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
15821 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
15824 /* Table of all explicit relocation names. */
15826 static struct reloc_entry reloc_names
[] =
15828 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
15829 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
15830 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
15831 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
15832 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
15833 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
15834 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
15835 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
15836 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
15837 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
15838 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
15842 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
15843 static const struct asm_cond conds
[] =
15847 {"cs", 0x2}, {"hs", 0x2},
15848 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
15862 static struct asm_barrier_opt barrier_opt_names
[] =
15870 /* Table of ARM-format instructions. */
15872 /* Macros for gluing together operand strings. N.B. In all cases
15873 other than OPS0, the trailing OP_stop comes from default
15874 zero-initialization of the unspecified elements of the array. */
15875 #define OPS0() { OP_stop, }
15876 #define OPS1(a) { OP_##a, }
15877 #define OPS2(a,b) { OP_##a,OP_##b, }
15878 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
15879 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
15880 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
15881 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
15883 /* These macros abstract out the exact format of the mnemonic table and
15884 save some repeated characters. */
15886 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
15887 #define TxCE(mnem, op, top, nops, ops, ae, te) \
15888 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
15889 THUMB_VARIANT, do_##ae, do_##te }
15891 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
15892 a T_MNEM_xyz enumerator. */
15893 #define TCE(mnem, aop, top, nops, ops, ae, te) \
15894 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
15895 #define tCE(mnem, aop, top, nops, ops, ae, te) \
15896 TxCE (mnem, aop, T_MNEM_##top, nops, ops, ae, te)
15898 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
15899 infix after the third character. */
15900 #define TxC3(mnem, op, top, nops, ops, ae, te) \
15901 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
15902 THUMB_VARIANT, do_##ae, do_##te }
15903 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
15904 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
15905 THUMB_VARIANT, do_##ae, do_##te }
15906 #define TC3(mnem, aop, top, nops, ops, ae, te) \
15907 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
15908 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
15909 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
15910 #define tC3(mnem, aop, top, nops, ops, ae, te) \
15911 TxC3 (mnem, aop, T_MNEM_##top, nops, ops, ae, te)
15912 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
15913 TxC3w (mnem, aop, T_MNEM_##top, nops, ops, ae, te)
15915 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
15916 appear in the condition table. */
15917 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
15918 { #m1 #m2 #m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (#m1) - 1, \
15919 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
15921 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
15922 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
15923 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
15924 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
15925 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
15926 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
15927 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
15928 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
15929 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
15930 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
15931 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
15932 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
15933 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
15934 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
15935 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
15936 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
15937 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
15938 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
15939 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
15940 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
15942 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
15943 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
15944 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
15945 TxCM (m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
15947 /* Mnemonic that cannot be conditionalized. The ARM condition-code
15948 field is still 0xE. Many of the Thumb variants can be executed
15949 conditionally, so this is checked separately. */
15950 #define TUE(mnem, op, top, nops, ops, ae, te) \
15951 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
15952 THUMB_VARIANT, do_##ae, do_##te }
15954 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
15955 condition code field. */
15956 #define TUF(mnem, op, top, nops, ops, ae, te) \
15957 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
15958 THUMB_VARIANT, do_##ae, do_##te }
15960 /* ARM-only variants of all the above. */
15961 #define CE(mnem, op, nops, ops, ae) \
15962 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15964 #define C3(mnem, op, nops, ops, ae) \
15965 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15967 /* Legacy mnemonics that always have conditional infix after the third
15969 #define CL(mnem, op, nops, ops, ae) \
15970 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
15971 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15973 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
15974 #define cCE(mnem, op, nops, ops, ae) \
15975 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
15977 /* Legacy coprocessor instructions where conditional infix and conditional
15978 suffix are ambiguous. For consistency this includes all FPA instructions,
15979 not just the potentially ambiguous ones. */
15980 #define cCL(mnem, op, nops, ops, ae) \
15981 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
15982 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
15984 /* Coprocessor, takes either a suffix or a position-3 infix
15985 (for an FPA corner case). */
15986 #define C3E(mnem, op, nops, ops, ae) \
15987 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
15988 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
15990 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
15991 { #m1 #m2 #m3, OPS##nops ops, \
15992 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (#m1) - 1, \
15993 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15995 #define CM(m1, m2, op, nops, ops, ae) \
15996 xCM_ (m1, , m2, op, nops, ops, ae), \
15997 xCM_ (m1, eq, m2, op, nops, ops, ae), \
15998 xCM_ (m1, ne, m2, op, nops, ops, ae), \
15999 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16000 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16001 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16002 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16003 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16004 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16005 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16006 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16007 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16008 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16009 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16010 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16011 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16012 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16013 xCM_ (m1, le, m2, op, nops, ops, ae), \
16014 xCM_ (m1, al, m2, op, nops, ops, ae)
16016 #define UE(mnem, op, nops, ops, ae) \
16017 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16019 #define UF(mnem, op, nops, ops, ae) \
16020 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16022 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16023 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16024 use the same encoding function for each. */
16025 #define NUF(mnem, op, nops, ops, enc) \
16026 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16027 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16029 /* Neon data processing, version which indirects through neon_enc_tab for
16030 the various overloaded versions of opcodes. */
16031 #define nUF(mnem, op, nops, ops, enc) \
16032 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
16033 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16035 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16037 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16038 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16039 THUMB_VARIANT, do_##enc, do_##enc }
16041 #define NCE(mnem, op, nops, ops, enc) \
16042 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16044 #define NCEF(mnem, op, nops, ops, enc) \
16045 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16047 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16048 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16049 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
16050 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16052 #define nCE(mnem, op, nops, ops, enc) \
16053 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16055 #define nCEF(mnem, op, nops, ops, enc) \
16056 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16060 /* Thumb-only, unconditional. */
16061 #define UT(mnem, op, nops, ops, te) TUE (mnem, 0, op, nops, ops, 0, te)
16063 static const struct asm_opcode insns
[] =
16065 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16066 #define THUMB_VARIANT &arm_ext_v4t
16067 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16068 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16069 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16070 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16071 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16072 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16073 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16074 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16075 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16076 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16077 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16078 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16079 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16080 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16081 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16082 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16084 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16085 for setting PSR flag bits. They are obsolete in V6 and do not
16086 have Thumb equivalents. */
16087 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16088 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16089 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
16090 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16091 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16092 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
16093 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16094 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16095 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
16097 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16098 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16099 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16100 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16102 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16103 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16104 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16105 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16107 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16108 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16109 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16110 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16111 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16112 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16114 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16115 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16116 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
16117 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16120 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
16121 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16122 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
16124 /* Thumb-compatibility pseudo ops. */
16125 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16126 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16127 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16128 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16129 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16130 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16131 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16132 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16133 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16134 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16135 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
16136 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16138 /* These may simplify to neg. */
16139 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16140 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16142 #undef THUMB_VARIANT
16143 #define THUMB_VARIANT & arm_ext_v6
16145 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16147 /* V1 instructions with no Thumb analogue prior to V6T2. */
16148 #undef THUMB_VARIANT
16149 #define THUMB_VARIANT & arm_ext_v6t2
16151 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16152 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16153 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
16155 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16156 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16157 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16158 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16160 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16161 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16163 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16164 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16166 /* V1 instructions with no Thumb analogue at all. */
16167 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16168 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16170 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16171 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16172 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16173 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16174 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16175 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16176 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16177 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16180 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16181 #undef THUMB_VARIANT
16182 #define THUMB_VARIANT & arm_ext_v4t
16184 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16185 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16187 #undef THUMB_VARIANT
16188 #define THUMB_VARIANT & arm_ext_v6t2
16190 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16191 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16193 /* Generic coprocessor instructions. */
16194 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16195 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16196 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16197 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16198 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16199 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16200 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16203 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16205 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16206 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16209 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16210 #undef THUMB_VARIANT
16211 #define THUMB_VARIANT & arm_ext_msr
16213 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16214 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16217 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16218 #undef THUMB_VARIANT
16219 #define THUMB_VARIANT & arm_ext_v6t2
16221 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16222 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16223 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16224 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16225 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16226 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16227 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16228 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16231 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16232 #undef THUMB_VARIANT
16233 #define THUMB_VARIANT & arm_ext_v4t
16235 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16236 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16237 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16238 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16239 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16240 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16243 #define ARM_VARIANT & arm_ext_v4t_5
16245 /* ARM Architecture 4T. */
16246 /* Note: bx (and blx) are required on V5, even if the processor does
16247 not support Thumb. */
16248 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16251 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16252 #undef THUMB_VARIANT
16253 #define THUMB_VARIANT & arm_ext_v5t
16255 /* Note: blx has 2 variants; the .value coded here is for
16256 BLX(2). Only this variant has conditional execution. */
16257 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16258 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16260 #undef THUMB_VARIANT
16261 #define THUMB_VARIANT & arm_ext_v6t2
16263 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16264 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16265 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16266 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16267 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16268 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16269 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16270 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16273 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16275 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16276 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16277 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16278 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16280 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16281 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16283 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16284 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16285 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16286 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16288 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16289 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16290 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16291 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16293 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16294 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16296 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16297 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16298 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16299 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16302 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16304 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16305 TC3(ldrd
, 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16306 TC3(strd
, 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16308 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16309 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16312 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16314 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16317 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16318 #undef THUMB_VARIANT
16319 #define THUMB_VARIANT & arm_ext_v6
16321 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16322 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16323 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16324 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16325 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16326 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16327 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16328 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16329 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16330 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16332 #undef THUMB_VARIANT
16333 #define THUMB_VARIANT & arm_ext_v6t2
16335 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
16336 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
16337 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16338 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16340 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16341 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16343 /* ARM V6 not included in V7M (eg. integer SIMD). */
16344 #undef THUMB_VARIANT
16345 #define THUMB_VARIANT & arm_ext_v6_notm
16347 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16348 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16349 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16350 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16351 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16352 TCE(qasx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16353 /* Old name for QASX. */
16354 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16355 TCE(qsax
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16356 /* Old name for QSAX. */
16357 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16358 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16359 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16360 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16361 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16362 TCE(sasx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16363 /* Old name for SASX. */
16364 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16365 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16366 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16367 TCE(shasx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16368 /* Old name for SHASX. */
16369 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16370 TCE(shsax
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16371 /* Old name for SHSAX. */
16372 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16373 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16374 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16375 TCE(ssax
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16376 /* Old name for SSAX. */
16377 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16378 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16379 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16380 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16381 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16382 TCE(uasx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16383 /* Old name for UASX. */
16384 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16385 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16386 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16387 TCE(uhasx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16388 /* Old name for UHASX. */
16389 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16390 TCE(uhsax
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16391 /* Old name for UHSAX. */
16392 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16393 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16394 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16395 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16396 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16397 TCE(uqasx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16398 /* Old name for UQASX. */
16399 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16400 TCE(uqsax
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16401 /* Old name for UQSAX. */
16402 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16403 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16404 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16405 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16406 TCE(usax
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16407 /* Old name for USAX. */
16408 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16409 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16410 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16411 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16412 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16413 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16414 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16415 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16416 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16417 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16418 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16419 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16420 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16421 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16422 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16423 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16424 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16425 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16426 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16427 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16428 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16429 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16430 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16431 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16432 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16433 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16434 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16435 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16436 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16437 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16438 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16439 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16440 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16441 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16442 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16443 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16444 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16445 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16446 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16447 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16448 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16449 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16450 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16451 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16452 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16453 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16456 #define ARM_VARIANT & arm_ext_v6k
16457 #undef THUMB_VARIANT
16458 #define THUMB_VARIANT & arm_ext_v6k
16460 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
16461 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
16462 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
16463 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
16465 #undef THUMB_VARIANT
16466 #define THUMB_VARIANT & arm_ext_v6_notm
16468 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
16469 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
16471 #undef THUMB_VARIANT
16472 #define THUMB_VARIANT & arm_ext_v6t2
16474 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16475 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16476 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16477 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16478 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
16481 #define ARM_VARIANT & arm_ext_v6z
16483 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
16486 #define ARM_VARIANT & arm_ext_v6t2
16488 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
16489 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
16490 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16491 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16493 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16494 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16495 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16496 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
16498 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16499 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16500 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16501 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16503 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
16504 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
16506 /* ARM does not really have an IT instruction, so always allow it.
16507 The opcode is copied from Thumb in order to allow warnings in
16508 -mimplicit-it=[never | arm] modes. */
16510 #define ARM_VARIANT & arm_ext_v1
16512 TUE(it
, bf08
, bf08
, 1, (COND
), it
, t_it
),
16513 TUE(itt
, bf0c
, bf0c
, 1, (COND
), it
, t_it
),
16514 TUE(ite
, bf04
, bf04
, 1, (COND
), it
, t_it
),
16515 TUE(ittt
, bf0e
, bf0e
, 1, (COND
), it
, t_it
),
16516 TUE(itet
, bf06
, bf06
, 1, (COND
), it
, t_it
),
16517 TUE(itte
, bf0a
, bf0a
, 1, (COND
), it
, t_it
),
16518 TUE(itee
, bf02
, bf02
, 1, (COND
), it
, t_it
),
16519 TUE(itttt
, bf0f
, bf0f
, 1, (COND
), it
, t_it
),
16520 TUE(itett
, bf07
, bf07
, 1, (COND
), it
, t_it
),
16521 TUE(ittet
, bf0b
, bf0b
, 1, (COND
), it
, t_it
),
16522 TUE(iteet
, bf03
, bf03
, 1, (COND
), it
, t_it
),
16523 TUE(ittte
, bf0d
, bf0d
, 1, (COND
), it
, t_it
),
16524 TUE(itete
, bf05
, bf05
, 1, (COND
), it
, t_it
),
16525 TUE(ittee
, bf09
, bf09
, 1, (COND
), it
, t_it
),
16526 TUE(iteee
, bf01
, bf01
, 1, (COND
), it
, t_it
),
16527 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
16528 TC3(rrx
, 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16529 TC3(rrxs
, 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16531 /* Thumb2 only instructions. */
16533 #define ARM_VARIANT NULL
16535 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16536 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16537 TCE(orn
, 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16538 TCE(orns
, 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16539 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
16540 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
16542 /* Thumb-2 hardware division instructions (R and M profiles only). */
16543 #undef THUMB_VARIANT
16544 #define THUMB_VARIANT & arm_ext_div
16546 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16547 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16549 /* ARM V6M/V7 instructions. */
16551 #define ARM_VARIANT & arm_ext_barrier
16552 #undef THUMB_VARIANT
16553 #define THUMB_VARIANT & arm_ext_barrier
16555 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
16556 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
16557 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
16559 /* ARM V7 instructions. */
16561 #define ARM_VARIANT & arm_ext_v7
16562 #undef THUMB_VARIANT
16563 #define THUMB_VARIANT & arm_ext_v7
16565 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
16566 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
16569 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
16571 cCE(wfs
, e200110
, 1, (RR
), rd
),
16572 cCE(rfs
, e300110
, 1, (RR
), rd
),
16573 cCE(wfc
, e400110
, 1, (RR
), rd
),
16574 cCE(rfc
, e500110
, 1, (RR
), rd
),
16576 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16577 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16578 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16579 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16581 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16582 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16583 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16584 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16586 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
16587 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
16588 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
16589 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
16590 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
16591 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
16592 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
16593 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
16594 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
16595 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
16596 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
16597 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
16599 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
16600 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
16601 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
16602 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
16603 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
16604 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
16605 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
16606 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
16607 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
16608 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
16609 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
16610 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
16612 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
16613 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
16614 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
16615 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
16616 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
16617 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
16618 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
16619 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
16620 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
16621 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
16622 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
16623 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
16625 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
16626 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
16627 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
16628 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
16629 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
16630 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
16631 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
16632 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
16633 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
16634 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
16635 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
16636 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
16638 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
16639 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
16640 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
16641 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
16642 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
16643 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
16644 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
16645 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
16646 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
16647 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
16648 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
16649 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
16651 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
16652 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
16653 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
16654 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
16655 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
16656 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
16657 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
16658 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
16659 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
16660 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
16661 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
16662 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
16664 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
16665 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
16666 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
16667 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
16668 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
16669 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
16670 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
16671 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
16672 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
16673 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
16674 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
16675 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
16677 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
16678 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
16679 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
16680 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
16681 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
16682 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
16683 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
16684 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
16685 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
16686 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
16687 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
16688 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
16690 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
16691 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
16692 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
16693 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
16694 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
16695 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
16696 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
16697 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
16698 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
16699 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
16700 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
16701 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
16703 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
16704 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
16705 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
16706 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
16707 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
16708 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
16709 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
16710 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
16711 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
16712 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
16713 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
16714 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
16716 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
16717 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
16718 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
16719 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
16720 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
16721 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
16722 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
16723 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
16724 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
16725 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
16726 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
16727 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
16729 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
16730 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
16731 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
16732 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
16733 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
16734 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
16735 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
16736 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
16737 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
16738 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
16739 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
16740 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
16742 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
16743 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
16744 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
16745 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
16746 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
16747 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
16748 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
16749 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
16750 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
16751 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
16752 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
16753 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
16755 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
16756 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
16757 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
16758 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
16759 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
16760 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
16761 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
16762 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
16763 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
16764 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
16765 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
16766 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
16768 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
16769 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
16770 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
16771 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
16772 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
16773 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
16774 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
16775 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
16776 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
16777 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
16778 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
16779 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
16781 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
16782 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
16783 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
16784 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
16785 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
16786 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
16787 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
16788 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
16789 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
16790 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
16791 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
16792 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
16794 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16795 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16796 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16797 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16798 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16799 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16800 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16801 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16802 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16803 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16804 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16805 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16807 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16808 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16809 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16810 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16811 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16812 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16813 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16814 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16815 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16816 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16817 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16818 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16820 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16821 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16822 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16823 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16824 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16825 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16826 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16827 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16828 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16829 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16830 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16831 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16833 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16834 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16835 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16836 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16837 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16838 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16839 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16840 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16841 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16842 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16843 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16844 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16846 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16847 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16848 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16849 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16850 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16851 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16852 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16853 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16854 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16855 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16856 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16857 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16859 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16860 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16861 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16862 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16863 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16864 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16865 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16866 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16867 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16868 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16869 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16870 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16872 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16873 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16874 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16875 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16876 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16877 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16878 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16879 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16880 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16881 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16882 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16883 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16885 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16886 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16887 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16888 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16889 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16890 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16891 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16892 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16893 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16894 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16895 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16896 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16898 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16899 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16900 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16901 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16902 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16903 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16904 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16905 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16906 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16907 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16908 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16909 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16911 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16912 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16913 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16914 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16915 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16916 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16917 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16918 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16919 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16920 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16921 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16922 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16924 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16925 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16926 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16927 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16928 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16929 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16930 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16931 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16932 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16933 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16934 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16935 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16937 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16938 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16939 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16940 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16941 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16942 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16943 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16944 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16945 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16946 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16947 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16948 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16950 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16951 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16952 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16953 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16954 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16955 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16956 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16957 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16958 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16959 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16960 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16961 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16963 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16964 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16965 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16966 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16968 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
16969 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
16970 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
16971 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
16972 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
16973 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
16974 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
16975 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
16976 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
16977 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
16978 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
16979 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
16981 /* The implementation of the FIX instruction is broken on some
16982 assemblers, in that it accepts a precision specifier as well as a
16983 rounding specifier, despite the fact that this is meaningless.
16984 To be more compatible, we accept it as well, though of course it
16985 does not set any bits. */
16986 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
16987 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
16988 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
16989 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
16990 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
16991 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
16992 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
16993 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
16994 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
16995 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
16996 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
16997 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
16998 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
17000 /* Instructions that were new with the real FPA, call them V2. */
17002 #define ARM_VARIANT & fpu_fpa_ext_v2
17004 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17005 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17006 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17007 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17008 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17009 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17012 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17014 /* Moves and type conversions. */
17015 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17016 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17017 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17018 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
17019 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17020 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17021 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17022 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17023 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17024 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17025 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
17026 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
17028 /* Memory operations. */
17029 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17030 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17031 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17032 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17033 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17034 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17035 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17036 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17037 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17038 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17039 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17040 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17041 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17042 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17043 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17044 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17045 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17046 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17048 /* Monadic operations. */
17049 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17050 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17051 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17053 /* Dyadic operations. */
17054 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17055 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17056 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17057 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17058 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17059 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17060 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17061 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17062 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17065 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17066 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17067 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17068 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17071 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17073 /* Moves and type conversions. */
17074 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17075 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17076 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17077 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17078 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17079 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17080 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17081 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17082 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17083 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17084 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17085 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17086 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17088 /* Memory operations. */
17089 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17090 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17091 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17092 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17093 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17094 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17095 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17096 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17097 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17098 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17100 /* Monadic operations. */
17101 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17102 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17103 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17105 /* Dyadic operations. */
17106 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17107 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17108 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17109 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17110 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17111 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17112 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17113 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17114 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17117 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17118 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
17119 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17120 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17123 #define ARM_VARIANT & fpu_vfp_ext_v2
17125 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17126 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17127 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17128 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17130 /* Instructions which may belong to either the Neon or VFP instruction sets.
17131 Individual encoder functions perform additional architecture checks. */
17133 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17134 #undef THUMB_VARIANT
17135 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17137 /* These mnemonics are unique to VFP. */
17138 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17139 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17140 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17141 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17142 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17143 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17144 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17145 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17146 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17147 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17149 /* Mnemonics shared by Neon and VFP. */
17150 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17151 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17152 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17154 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17155 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17157 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17158 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17160 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17161 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17162 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17163 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17164 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17165 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17166 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17167 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17169 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17170 nCEF(vcvtb
, vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17171 nCEF(vcvtt
, vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17174 /* NOTE: All VMOV encoding is special-cased! */
17175 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17176 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17178 #undef THUMB_VARIANT
17179 #define THUMB_VARIANT & fpu_neon_ext_v1
17181 #define ARM_VARIANT & fpu_neon_ext_v1
17183 /* Data processing with three registers of the same length. */
17184 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17185 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17186 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17187 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17188 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17189 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17190 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17191 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17192 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17193 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17194 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17195 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17196 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17197 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17198 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17199 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17200 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17201 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17202 /* If not immediate, fall back to neon_dyadic_i64_su.
17203 shl_imm should accept I8 I16 I32 I64,
17204 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17205 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17206 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17207 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17208 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17209 /* Logic ops, types optional & ignored. */
17210 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
17211 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
17212 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
17213 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
17214 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
17215 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
17216 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
17217 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
17218 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17219 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17220 /* Bitfield ops, untyped. */
17221 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17222 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17223 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17224 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17225 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17226 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17227 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17228 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17229 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17230 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17231 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17232 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17233 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17234 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17235 back to neon_dyadic_if_su. */
17236 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17237 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17238 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17239 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17240 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17241 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17242 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17243 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17244 /* Comparison. Type I8 I16 I32 F32. */
17245 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17246 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17247 /* As above, D registers only. */
17248 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17249 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17250 /* Int and float variants, signedness unimportant. */
17251 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17252 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17253 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17254 /* Add/sub take types I8 I16 I32 I64 F32. */
17255 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17256 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17257 /* vtst takes sizes 8, 16, 32. */
17258 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17259 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17260 /* VMUL takes I8 I16 I32 F32 P8. */
17261 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17262 /* VQD{R}MULH takes S16 S32. */
17263 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17264 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17265 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17266 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17267 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17268 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17269 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17270 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17271 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17272 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17273 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17274 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17275 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17276 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17277 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17278 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17280 /* Two address, int/float. Types S8 S16 S32 F32. */
17281 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17282 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17284 /* Data processing with two registers and a shift amount. */
17285 /* Right shifts, and variants with rounding.
17286 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17287 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17288 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17289 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17290 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17291 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17292 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17293 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17294 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17295 /* Shift and insert. Sizes accepted 8 16 32 64. */
17296 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17297 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17298 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17299 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17300 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17301 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17302 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17303 /* Right shift immediate, saturating & narrowing, with rounding variants.
17304 Types accepted S16 S32 S64 U16 U32 U64. */
17305 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17306 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17307 /* As above, unsigned. Types accepted S16 S32 S64. */
17308 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17309 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17310 /* Right shift narrowing. Types accepted I16 I32 I64. */
17311 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17312 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17313 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17314 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17315 /* CVT with optional immediate for fixed-point variant. */
17316 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17318 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
17319 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
17321 /* Data processing, three registers of different lengths. */
17322 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17323 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17324 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17325 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17326 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17327 /* If not scalar, fall back to neon_dyadic_long.
17328 Vector types as above, scalar types S16 S32 U16 U32. */
17329 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17330 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17331 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17332 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17333 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17334 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17335 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17336 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17337 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17338 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17339 /* Saturating doubling multiplies. Types S16 S32. */
17340 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17341 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17342 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17343 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17344 S16 S32 U16 U32. */
17345 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17347 /* Extract. Size 8. */
17348 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17349 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17351 /* Two registers, miscellaneous. */
17352 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17353 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17354 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17355 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17356 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17357 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17358 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17359 /* Vector replicate. Sizes 8 16 32. */
17360 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17361 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17362 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17363 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17364 /* VMOVN. Types I16 I32 I64. */
17365 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
17366 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17367 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17368 /* VQMOVUN. Types S16 S32 S64. */
17369 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17370 /* VZIP / VUZP. Sizes 8 16 32. */
17371 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17372 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17373 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17374 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17375 /* VQABS / VQNEG. Types S8 S16 S32. */
17376 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17377 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17378 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17379 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17380 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17381 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17382 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17383 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17384 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17385 /* Reciprocal estimates. Types U32 F32. */
17386 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17387 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17388 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17389 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17390 /* VCLS. Types S8 S16 S32. */
17391 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17392 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17393 /* VCLZ. Types I8 I16 I32. */
17394 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17395 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17396 /* VCNT. Size 8. */
17397 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17398 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17399 /* Two address, untyped. */
17400 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17401 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17402 /* VTRN. Sizes 8 16 32. */
17403 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17404 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17406 /* Table lookup. Size 8. */
17407 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17408 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17410 #undef THUMB_VARIANT
17411 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17413 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17415 /* Neon element/structure load/store. */
17416 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17417 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17418 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17419 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17420 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17421 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17422 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17423 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17425 #undef THUMB_VARIANT
17426 #define THUMB_VARIANT & fpu_vfp_ext_v3
17428 #define ARM_VARIANT & fpu_vfp_ext_v3
17430 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17431 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17432 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17433 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17434 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17435 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17436 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17437 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17438 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17439 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17440 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17441 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17442 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17443 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17444 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17445 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17446 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17447 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17449 #undef THUMB_VARIANT
17451 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17453 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17454 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17455 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17456 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17457 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17458 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17459 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
17460 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
17463 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17465 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
17466 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
17467 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
17468 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
17469 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
17470 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
17471 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
17472 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
17473 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
17474 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17475 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17476 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17477 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17478 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17479 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17480 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17481 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17482 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17483 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
17484 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
17485 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17486 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17487 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17488 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17489 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17490 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17491 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
17492 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
17493 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
17494 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
17495 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
17496 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
17497 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
17498 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
17499 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17500 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17501 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17502 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17503 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17504 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17505 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17506 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17507 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17508 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17509 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17510 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17511 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
17512 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17513 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17514 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17515 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17516 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17517 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17518 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17519 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17520 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17521 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17522 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17523 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17524 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17525 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17526 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17527 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17528 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17529 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17530 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17531 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17532 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17533 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17534 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17535 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17536 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17537 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17538 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17539 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17540 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17541 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17542 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17543 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17544 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17545 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17546 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17547 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17548 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17549 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17550 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17551 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17552 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17553 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
17554 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17555 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17556 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17557 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17558 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17559 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17560 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17561 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17562 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17563 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17564 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17565 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17566 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17567 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17568 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17569 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17570 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17571 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17572 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17573 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17574 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17575 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
17576 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17577 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17578 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17579 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17580 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17581 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17582 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17583 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17584 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17585 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17586 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17587 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17588 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17589 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17590 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17591 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17592 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17593 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17594 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17595 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17596 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17597 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17598 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17599 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17600 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17601 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17602 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17603 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17604 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17605 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17606 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17607 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17608 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17609 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17610 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17611 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17612 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17613 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17614 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17615 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17616 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17617 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17618 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17619 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17620 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17621 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17622 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17623 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17624 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17625 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17626 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
17629 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
17631 cCE(torvscb
, e12f190
, 1, (RR
), iwmmxt_tandorc
),
17632 cCE(torvsch
, e52f190
, 1, (RR
), iwmmxt_tandorc
),
17633 cCE(torvscw
, e92f190
, 1, (RR
), iwmmxt_tandorc
),
17634 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17635 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17636 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17637 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17638 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17639 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17640 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17641 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17642 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17643 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17644 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17645 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17646 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17647 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17648 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17649 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17650 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17651 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
17652 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17653 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17654 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17655 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17656 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17657 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17658 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17659 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17660 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17661 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17662 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17663 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17664 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17665 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17666 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17667 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17668 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17669 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17670 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17671 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17672 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17673 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17674 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17675 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17676 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17677 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17678 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17679 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17680 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17681 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17682 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17683 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17684 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17685 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17686 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17687 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17690 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
17692 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17693 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17694 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17695 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17696 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17697 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17698 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17699 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17700 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
17701 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
17702 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
17703 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
17704 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
17705 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
17706 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
17707 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
17708 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
17709 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
17710 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
17711 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
17712 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
17713 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
17714 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
17715 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
17716 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
17717 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
17718 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
17719 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
17720 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
17721 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
17722 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
17723 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
17724 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
17725 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
17726 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
17727 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
17728 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
17729 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
17730 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
17731 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
17732 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
17733 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
17734 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
17735 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
17736 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
17737 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
17738 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
17739 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
17740 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
17741 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
17742 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
17743 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
17744 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
17745 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
17746 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17747 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17748 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17749 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17750 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17751 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17752 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
17753 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
17754 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
17755 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
17756 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17757 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17758 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17759 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17760 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17761 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17762 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17763 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17764 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17765 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17766 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17767 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17770 #undef THUMB_VARIANT
17797 /* MD interface: bits in the object file. */
17799 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
17800 for use in the a.out file, and stores them in the array pointed to by buf.
17801 This knows about the endian-ness of the target machine and does
17802 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
17803 2 (short) and 4 (long) Floating numbers are put out as a series of
17804 LITTLENUMS (shorts, here at least). */
17807 md_number_to_chars (char * buf
, valueT val
, int n
)
17809 if (target_big_endian
)
17810 number_to_chars_bigendian (buf
, val
, n
);
17812 number_to_chars_littleendian (buf
, val
, n
);
17816 md_chars_to_number (char * buf
, int n
)
17819 unsigned char * where
= (unsigned char *) buf
;
17821 if (target_big_endian
)
17826 result
|= (*where
++ & 255);
17834 result
|= (where
[n
] & 255);
17841 /* MD interface: Sections. */
17843 /* Estimate the size of a frag before relaxing. Assume everything fits in
17847 md_estimate_size_before_relax (fragS
* fragp
,
17848 segT segtype ATTRIBUTE_UNUSED
)
17854 /* Convert a machine dependent frag. */
17857 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
17859 unsigned long insn
;
17860 unsigned long old_op
;
17868 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17870 old_op
= bfd_get_16(abfd
, buf
);
17871 if (fragp
->fr_symbol
)
17873 exp
.X_op
= O_symbol
;
17874 exp
.X_add_symbol
= fragp
->fr_symbol
;
17878 exp
.X_op
= O_constant
;
17880 exp
.X_add_number
= fragp
->fr_offset
;
17881 opcode
= fragp
->fr_subtype
;
17884 case T_MNEM_ldr_pc
:
17885 case T_MNEM_ldr_pc2
:
17886 case T_MNEM_ldr_sp
:
17887 case T_MNEM_str_sp
:
17894 if (fragp
->fr_var
== 4)
17896 insn
= THUMB_OP32 (opcode
);
17897 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
17899 insn
|= (old_op
& 0x700) << 4;
17903 insn
|= (old_op
& 7) << 12;
17904 insn
|= (old_op
& 0x38) << 13;
17906 insn
|= 0x00000c00;
17907 put_thumb32_insn (buf
, insn
);
17908 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
17912 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
17914 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
17917 if (fragp
->fr_var
== 4)
17919 insn
= THUMB_OP32 (opcode
);
17920 insn
|= (old_op
& 0xf0) << 4;
17921 put_thumb32_insn (buf
, insn
);
17922 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
17926 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
17927 exp
.X_add_number
-= 4;
17935 if (fragp
->fr_var
== 4)
17937 int r0off
= (opcode
== T_MNEM_mov
17938 || opcode
== T_MNEM_movs
) ? 0 : 8;
17939 insn
= THUMB_OP32 (opcode
);
17940 insn
= (insn
& 0xe1ffffff) | 0x10000000;
17941 insn
|= (old_op
& 0x700) << r0off
;
17942 put_thumb32_insn (buf
, insn
);
17943 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
17947 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
17952 if (fragp
->fr_var
== 4)
17954 insn
= THUMB_OP32(opcode
);
17955 put_thumb32_insn (buf
, insn
);
17956 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
17959 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
17963 if (fragp
->fr_var
== 4)
17965 insn
= THUMB_OP32(opcode
);
17966 insn
|= (old_op
& 0xf00) << 14;
17967 put_thumb32_insn (buf
, insn
);
17968 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
17971 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
17974 case T_MNEM_add_sp
:
17975 case T_MNEM_add_pc
:
17976 case T_MNEM_inc_sp
:
17977 case T_MNEM_dec_sp
:
17978 if (fragp
->fr_var
== 4)
17980 /* ??? Choose between add and addw. */
17981 insn
= THUMB_OP32 (opcode
);
17982 insn
|= (old_op
& 0xf0) << 4;
17983 put_thumb32_insn (buf
, insn
);
17984 if (opcode
== T_MNEM_add_pc
)
17985 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
17987 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
17990 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
17998 if (fragp
->fr_var
== 4)
18000 insn
= THUMB_OP32 (opcode
);
18001 insn
|= (old_op
& 0xf0) << 4;
18002 insn
|= (old_op
& 0xf) << 16;
18003 put_thumb32_insn (buf
, insn
);
18004 if (insn
& (1 << 20))
18005 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18007 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18010 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18016 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18018 fixp
->fx_file
= fragp
->fr_file
;
18019 fixp
->fx_line
= fragp
->fr_line
;
18020 fragp
->fr_fix
+= fragp
->fr_var
;
18023 /* Return the size of a relaxable immediate operand instruction.
18024 SHIFT and SIZE specify the form of the allowable immediate. */
18026 relax_immediate (fragS
*fragp
, int size
, int shift
)
18032 /* ??? Should be able to do better than this. */
18033 if (fragp
->fr_symbol
)
18036 low
= (1 << shift
) - 1;
18037 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18038 offset
= fragp
->fr_offset
;
18039 /* Force misaligned offsets to 32-bit variant. */
18042 if (offset
& ~mask
)
18047 /* Get the address of a symbol during relaxation. */
18049 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18055 sym
= fragp
->fr_symbol
;
18056 sym_frag
= symbol_get_frag (sym
);
18057 know (S_GET_SEGMENT (sym
) != absolute_section
18058 || sym_frag
== &zero_address_frag
);
18059 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18061 /* If frag has yet to be reached on this pass, assume it will
18062 move by STRETCH just as we did. If this is not so, it will
18063 be because some frag between grows, and that will force
18067 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18071 /* Adjust stretch for any alignment frag. Note that if have
18072 been expanding the earlier code, the symbol may be
18073 defined in what appears to be an earlier frag. FIXME:
18074 This doesn't handle the fr_subtype field, which specifies
18075 a maximum number of bytes to skip when doing an
18077 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18079 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18082 stretch
= - ((- stretch
)
18083 & ~ ((1 << (int) f
->fr_offset
) - 1));
18085 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18097 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18100 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18105 /* Assume worst case for symbols not known to be in the same section. */
18106 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18107 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18110 val
= relaxed_symbol_addr (fragp
, stretch
);
18111 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18112 addr
= (addr
+ 4) & ~3;
18113 /* Force misaligned targets to 32-bit variant. */
18117 if (val
< 0 || val
> 1020)
18122 /* Return the size of a relaxable add/sub immediate instruction. */
18124 relax_addsub (fragS
*fragp
, asection
*sec
)
18129 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18130 op
= bfd_get_16(sec
->owner
, buf
);
18131 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18132 return relax_immediate (fragp
, 8, 0);
18134 return relax_immediate (fragp
, 3, 0);
18138 /* Return the size of a relaxable branch instruction. BITS is the
18139 size of the offset field in the narrow instruction. */
18142 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18148 /* Assume worst case for symbols not known to be in the same section. */
18149 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18150 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18154 if (S_IS_DEFINED (fragp
->fr_symbol
)
18155 && ARM_IS_FUNC (fragp
->fr_symbol
))
18159 val
= relaxed_symbol_addr (fragp
, stretch
);
18160 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18163 /* Offset is a signed value *2 */
18165 if (val
>= limit
|| val
< -limit
)
18171 /* Relax a machine dependent frag. This returns the amount by which
18172 the current size of the frag should change. */
18175 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18180 oldsize
= fragp
->fr_var
;
18181 switch (fragp
->fr_subtype
)
18183 case T_MNEM_ldr_pc2
:
18184 newsize
= relax_adr (fragp
, sec
, stretch
);
18186 case T_MNEM_ldr_pc
:
18187 case T_MNEM_ldr_sp
:
18188 case T_MNEM_str_sp
:
18189 newsize
= relax_immediate (fragp
, 8, 2);
18193 newsize
= relax_immediate (fragp
, 5, 2);
18197 newsize
= relax_immediate (fragp
, 5, 1);
18201 newsize
= relax_immediate (fragp
, 5, 0);
18204 newsize
= relax_adr (fragp
, sec
, stretch
);
18210 newsize
= relax_immediate (fragp
, 8, 0);
18213 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18216 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18218 case T_MNEM_add_sp
:
18219 case T_MNEM_add_pc
:
18220 newsize
= relax_immediate (fragp
, 8, 2);
18222 case T_MNEM_inc_sp
:
18223 case T_MNEM_dec_sp
:
18224 newsize
= relax_immediate (fragp
, 7, 2);
18230 newsize
= relax_addsub (fragp
, sec
);
18236 fragp
->fr_var
= newsize
;
18237 /* Freeze wide instructions that are at or before the same location as
18238 in the previous pass. This avoids infinite loops.
18239 Don't freeze them unconditionally because targets may be artificially
18240 misaligned by the expansion of preceding frags. */
18241 if (stretch
<= 0 && newsize
> 2)
18243 md_convert_frag (sec
->owner
, sec
, fragp
);
18247 return newsize
- oldsize
;
18250 /* Round up a section size to the appropriate boundary. */
18253 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18256 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18257 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18259 /* For a.out, force the section size to be aligned. If we don't do
18260 this, BFD will align it for us, but it will not write out the
18261 final bytes of the section. This may be a bug in BFD, but it is
18262 easier to fix it here since that is how the other a.out targets
18266 align
= bfd_get_section_alignment (stdoutput
, segment
);
18267 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18274 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18275 of an rs_align_code fragment. */
18278 arm_handle_align (fragS
* fragP
)
18280 static char const arm_noop
[2][2][4] =
18283 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18284 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18287 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18288 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18291 static char const thumb_noop
[2][2][2] =
18294 {0xc0, 0x46}, /* LE */
18295 {0x46, 0xc0}, /* BE */
18298 {0x00, 0xbf}, /* LE */
18299 {0xbf, 0x00} /* BE */
18302 static char const wide_thumb_noop
[2][4] =
18303 { /* Wide Thumb-2 */
18304 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18305 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18308 unsigned bytes
, fix
, noop_size
;
18311 const char *narrow_noop
= NULL
;
18313 if (fragP
->fr_type
!= rs_align_code
)
18316 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18317 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18320 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18321 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18323 gas_assert ((fragP
->tc_frag_data
& MODE_RECORDED
) != 0);
18325 if (fragP
->tc_frag_data
& (~ MODE_RECORDED
))
18327 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18329 narrow_noop
= thumb_noop
[1][target_big_endian
];
18330 noop
= wide_thumb_noop
[target_big_endian
];
18333 noop
= thumb_noop
[0][target_big_endian
];
18338 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18339 [target_big_endian
];
18343 fragP
->fr_var
= noop_size
;
18345 if (bytes
& (noop_size
- 1))
18347 fix
= bytes
& (noop_size
- 1);
18348 memset (p
, 0, fix
);
18355 if (bytes
& noop_size
)
18357 /* Insert a narrow noop. */
18358 memcpy (p
, narrow_noop
, noop_size
);
18360 bytes
-= noop_size
;
18364 /* Use wide noops for the remainder */
18368 while (bytes
>= noop_size
)
18370 memcpy (p
, noop
, noop_size
);
18372 bytes
-= noop_size
;
18376 fragP
->fr_fix
+= fix
;
18379 /* Called from md_do_align. Used to create an alignment
18380 frag in a code section. */
18383 arm_frag_align_code (int n
, int max
)
18387 /* We assume that there will never be a requirement
18388 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18389 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18394 _("alignments greater than %d bytes not supported in .text sections."),
18395 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18396 as_fatal ("%s", err_msg
);
18399 p
= frag_var (rs_align_code
,
18400 MAX_MEM_FOR_RS_ALIGN_CODE
,
18402 (relax_substateT
) max
,
18409 /* Perform target specific initialisation of a frag.
18410 Note - despite the name this initialisation is not done when the frag
18411 is created, but only when its type is assigned. A frag can be created
18412 and used a long time before its type is set, so beware of assuming that
18413 this initialisationis performed first. */
18416 arm_init_frag (fragS
* fragP
)
18418 /* If the current ARM vs THUMB mode has not already
18419 been recorded into this frag then do so now. */
18420 if ((fragP
->tc_frag_data
& MODE_RECORDED
) == 0)
18421 fragP
->tc_frag_data
= thumb_mode
| MODE_RECORDED
;
18425 /* When we change sections we need to issue a new mapping symbol. */
18428 arm_elf_change_section (void)
18431 segment_info_type
*seginfo
;
18433 /* Link an unlinked unwind index table section to the .text section. */
18434 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
18435 && elf_linked_to_section (now_seg
) == NULL
)
18436 elf_linked_to_section (now_seg
) = text_section
;
18438 if (!SEG_NORMAL (now_seg
))
18441 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
18443 /* We can ignore sections that only contain debug info. */
18444 if ((flags
& SEC_ALLOC
) == 0)
18447 seginfo
= seg_info (now_seg
);
18448 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
18449 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
18453 arm_elf_section_type (const char * str
, size_t len
)
18455 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
18456 return SHT_ARM_EXIDX
;
18461 /* Code to deal with unwinding tables. */
18463 static void add_unwind_adjustsp (offsetT
);
18465 /* Generate any deferred unwind frame offset. */
18468 flush_pending_unwind (void)
18472 offset
= unwind
.pending_offset
;
18473 unwind
.pending_offset
= 0;
18475 add_unwind_adjustsp (offset
);
18478 /* Add an opcode to this list for this function. Two-byte opcodes should
18479 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
18483 add_unwind_opcode (valueT op
, int length
)
18485 /* Add any deferred stack adjustment. */
18486 if (unwind
.pending_offset
)
18487 flush_pending_unwind ();
18489 unwind
.sp_restored
= 0;
18491 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
18493 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
18494 if (unwind
.opcodes
)
18495 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
18496 unwind
.opcode_alloc
);
18498 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
18503 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
18505 unwind
.opcode_count
++;
18509 /* Add unwind opcodes to adjust the stack pointer. */
18512 add_unwind_adjustsp (offsetT offset
)
18516 if (offset
> 0x200)
18518 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
18523 /* Long form: 0xb2, uleb128. */
18524 /* This might not fit in a word so add the individual bytes,
18525 remembering the list is built in reverse order. */
18526 o
= (valueT
) ((offset
- 0x204) >> 2);
18528 add_unwind_opcode (0, 1);
18530 /* Calculate the uleb128 encoding of the offset. */
18534 bytes
[n
] = o
& 0x7f;
18540 /* Add the insn. */
18542 add_unwind_opcode (bytes
[n
- 1], 1);
18543 add_unwind_opcode (0xb2, 1);
18545 else if (offset
> 0x100)
18547 /* Two short opcodes. */
18548 add_unwind_opcode (0x3f, 1);
18549 op
= (offset
- 0x104) >> 2;
18550 add_unwind_opcode (op
, 1);
18552 else if (offset
> 0)
18554 /* Short opcode. */
18555 op
= (offset
- 4) >> 2;
18556 add_unwind_opcode (op
, 1);
18558 else if (offset
< 0)
18561 while (offset
> 0x100)
18563 add_unwind_opcode (0x7f, 1);
18566 op
= ((offset
- 4) >> 2) | 0x40;
18567 add_unwind_opcode (op
, 1);
18571 /* Finish the list of unwind opcodes for this function. */
18573 finish_unwind_opcodes (void)
18577 if (unwind
.fp_used
)
18579 /* Adjust sp as necessary. */
18580 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
18581 flush_pending_unwind ();
18583 /* After restoring sp from the frame pointer. */
18584 op
= 0x90 | unwind
.fp_reg
;
18585 add_unwind_opcode (op
, 1);
18588 flush_pending_unwind ();
18592 /* Start an exception table entry. If idx is nonzero this is an index table
18596 start_unwind_section (const segT text_seg
, int idx
)
18598 const char * text_name
;
18599 const char * prefix
;
18600 const char * prefix_once
;
18601 const char * group_name
;
18605 size_t sec_name_len
;
18612 prefix
= ELF_STRING_ARM_unwind
;
18613 prefix_once
= ELF_STRING_ARM_unwind_once
;
18614 type
= SHT_ARM_EXIDX
;
18618 prefix
= ELF_STRING_ARM_unwind_info
;
18619 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
18620 type
= SHT_PROGBITS
;
18623 text_name
= segment_name (text_seg
);
18624 if (streq (text_name
, ".text"))
18627 if (strncmp (text_name
, ".gnu.linkonce.t.",
18628 strlen (".gnu.linkonce.t.")) == 0)
18630 prefix
= prefix_once
;
18631 text_name
+= strlen (".gnu.linkonce.t.");
18634 prefix_len
= strlen (prefix
);
18635 text_len
= strlen (text_name
);
18636 sec_name_len
= prefix_len
+ text_len
;
18637 sec_name
= xmalloc (sec_name_len
+ 1);
18638 memcpy (sec_name
, prefix
, prefix_len
);
18639 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
18640 sec_name
[prefix_len
+ text_len
] = '\0';
18646 /* Handle COMDAT group. */
18647 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
18649 group_name
= elf_group_name (text_seg
);
18650 if (group_name
== NULL
)
18652 as_bad (_("Group section `%s' has no group signature"),
18653 segment_name (text_seg
));
18654 ignore_rest_of_line ();
18657 flags
|= SHF_GROUP
;
18661 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
18663 /* Set the section link for index tables. */
18665 elf_linked_to_section (now_seg
) = text_seg
;
18669 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
18670 personality routine data. Returns zero, or the index table value for
18671 and inline entry. */
18674 create_unwind_entry (int have_data
)
18679 /* The current word of data. */
18681 /* The number of bytes left in this word. */
18684 finish_unwind_opcodes ();
18686 /* Remember the current text section. */
18687 unwind
.saved_seg
= now_seg
;
18688 unwind
.saved_subseg
= now_subseg
;
18690 start_unwind_section (now_seg
, 0);
18692 if (unwind
.personality_routine
== NULL
)
18694 if (unwind
.personality_index
== -2)
18697 as_bad (_("handlerdata in cantunwind frame"));
18698 return 1; /* EXIDX_CANTUNWIND. */
18701 /* Use a default personality routine if none is specified. */
18702 if (unwind
.personality_index
== -1)
18704 if (unwind
.opcode_count
> 3)
18705 unwind
.personality_index
= 1;
18707 unwind
.personality_index
= 0;
18710 /* Space for the personality routine entry. */
18711 if (unwind
.personality_index
== 0)
18713 if (unwind
.opcode_count
> 3)
18714 as_bad (_("too many unwind opcodes for personality routine 0"));
18718 /* All the data is inline in the index table. */
18721 while (unwind
.opcode_count
> 0)
18723 unwind
.opcode_count
--;
18724 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
18728 /* Pad with "finish" opcodes. */
18730 data
= (data
<< 8) | 0xb0;
18737 /* We get two opcodes "free" in the first word. */
18738 size
= unwind
.opcode_count
- 2;
18741 /* An extra byte is required for the opcode count. */
18742 size
= unwind
.opcode_count
+ 1;
18744 size
= (size
+ 3) >> 2;
18746 as_bad (_("too many unwind opcodes"));
18748 frag_align (2, 0, 0);
18749 record_alignment (now_seg
, 2);
18750 unwind
.table_entry
= expr_build_dot ();
18752 /* Allocate the table entry. */
18753 ptr
= frag_more ((size
<< 2) + 4);
18754 where
= frag_now_fix () - ((size
<< 2) + 4);
18756 switch (unwind
.personality_index
)
18759 /* ??? Should this be a PLT generating relocation? */
18760 /* Custom personality routine. */
18761 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
18762 BFD_RELOC_ARM_PREL31
);
18767 /* Set the first byte to the number of additional words. */
18772 /* ABI defined personality routines. */
18774 /* Three opcodes bytes are packed into the first word. */
18781 /* The size and first two opcode bytes go in the first word. */
18782 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
18787 /* Should never happen. */
18791 /* Pack the opcodes into words (MSB first), reversing the list at the same
18793 while (unwind
.opcode_count
> 0)
18797 md_number_to_chars (ptr
, data
, 4);
18802 unwind
.opcode_count
--;
18804 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
18807 /* Finish off the last word. */
18810 /* Pad with "finish" opcodes. */
18812 data
= (data
<< 8) | 0xb0;
18814 md_number_to_chars (ptr
, data
, 4);
18819 /* Add an empty descriptor if there is no user-specified data. */
18820 ptr
= frag_more (4);
18821 md_number_to_chars (ptr
, 0, 4);
18828 /* Initialize the DWARF-2 unwind information for this procedure. */
18831 tc_arm_frame_initial_instructions (void)
18833 cfi_add_CFA_def_cfa (REG_SP
, 0);
18835 #endif /* OBJ_ELF */
18837 /* Convert REGNAME to a DWARF-2 register number. */
18840 tc_arm_regname_to_dw2regnum (char *regname
)
18842 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
18852 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
18856 expr
.X_op
= O_secrel
;
18857 expr
.X_add_symbol
= symbol
;
18858 expr
.X_add_number
= 0;
18859 emit_expr (&expr
, size
);
18863 /* MD interface: Symbol and relocation handling. */
18865 /* Return the address within the segment that a PC-relative fixup is
18866 relative to. For ARM, PC-relative fixups applied to instructions
18867 are generally relative to the location of the fixup plus 8 bytes.
18868 Thumb branches are offset by 4, and Thumb loads relative to PC
18869 require special handling. */
18872 md_pcrel_from_section (fixS
* fixP
, segT seg
)
18874 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
18876 /* If this is pc-relative and we are going to emit a relocation
18877 then we just want to put out any pipeline compensation that the linker
18878 will need. Otherwise we want to use the calculated base.
18879 For WinCE we skip the bias for externals as well, since this
18880 is how the MS ARM-CE assembler behaves and we want to be compatible. */
18882 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
18883 || (arm_force_relocation (fixP
)
18885 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
18891 switch (fixP
->fx_r_type
)
18893 /* PC relative addressing on the Thumb is slightly odd as the
18894 bottom two bits of the PC are forced to zero for the
18895 calculation. This happens *after* application of the
18896 pipeline offset. However, Thumb adrl already adjusts for
18897 this, so we need not do it again. */
18898 case BFD_RELOC_ARM_THUMB_ADD
:
18901 case BFD_RELOC_ARM_THUMB_OFFSET
:
18902 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18903 case BFD_RELOC_ARM_T32_ADD_PC12
:
18904 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18905 return (base
+ 4) & ~3;
18907 /* Thumb branches are simply offset by +4. */
18908 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
18909 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
18910 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
18911 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18912 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18915 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18917 && ARM_IS_FUNC (fixP
->fx_addsy
)
18918 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
18919 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
18922 /* BLX is like branches above, but forces the low two bits of PC to
18924 case BFD_RELOC_THUMB_PCREL_BLX
:
18926 && THUMB_IS_FUNC (fixP
->fx_addsy
)
18927 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
18928 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
18929 return (base
+ 4) & ~3;
18931 /* ARM mode branches are offset by +8. However, the Windows CE
18932 loader expects the relocation not to take this into account. */
18933 case BFD_RELOC_ARM_PCREL_BLX
:
18935 && ARM_IS_FUNC (fixP
->fx_addsy
)
18936 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
18937 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
18940 case BFD_RELOC_ARM_PCREL_CALL
:
18942 && THUMB_IS_FUNC (fixP
->fx_addsy
)
18943 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
18944 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
18947 case BFD_RELOC_ARM_PCREL_BRANCH
:
18948 case BFD_RELOC_ARM_PCREL_JUMP
:
18949 case BFD_RELOC_ARM_PLT32
:
18951 /* When handling fixups immediately, because we have already
18952 discovered the value of a symbol, or the address of the frag involved
18953 we must account for the offset by +8, as the OS loader will never see the reloc.
18954 see fixup_segment() in write.c
18955 The S_IS_EXTERNAL test handles the case of global symbols.
18956 Those need the calculated base, not just the pipe compensation the linker will need. */
18958 && fixP
->fx_addsy
!= NULL
18959 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
18960 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
18968 /* ARM mode loads relative to PC are also offset by +8. Unlike
18969 branches, the Windows CE loader *does* expect the relocation
18970 to take this into account. */
18971 case BFD_RELOC_ARM_OFFSET_IMM
:
18972 case BFD_RELOC_ARM_OFFSET_IMM8
:
18973 case BFD_RELOC_ARM_HWLITERAL
:
18974 case BFD_RELOC_ARM_LITERAL
:
18975 case BFD_RELOC_ARM_CP_OFF_IMM
:
18979 /* Other PC-relative relocations are un-offset. */
18985 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
18986 Otherwise we have no need to default values of symbols. */
18989 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
18992 if (name
[0] == '_' && name
[1] == 'G'
18993 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
18997 if (symbol_find (name
))
18998 as_bad (_("GOT already in the symbol table"));
19000 GOT_symbol
= symbol_new (name
, undefined_section
,
19001 (valueT
) 0, & zero_address_frag
);
19011 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19012 computed as two separate immediate values, added together. We
19013 already know that this value cannot be computed by just one ARM
19016 static unsigned int
19017 validate_immediate_twopart (unsigned int val
,
19018 unsigned int * highpart
)
19023 for (i
= 0; i
< 32; i
+= 2)
19024 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19030 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19032 else if (a
& 0xff0000)
19034 if (a
& 0xff000000)
19036 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19040 gas_assert (a
& 0xff000000);
19041 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19044 return (a
& 0xff) | (i
<< 7);
19051 validate_offset_imm (unsigned int val
, int hwse
)
19053 if ((hwse
&& val
> 255) || val
> 4095)
19058 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19059 negative immediate constant by altering the instruction. A bit of
19064 by inverting the second operand, and
19067 by negating the second operand. */
19070 negate_data_op (unsigned long * instruction
,
19071 unsigned long value
)
19074 unsigned long negated
, inverted
;
19076 negated
= encode_arm_immediate (-value
);
19077 inverted
= encode_arm_immediate (~value
);
19079 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19082 /* First negates. */
19083 case OPCODE_SUB
: /* ADD <-> SUB */
19084 new_inst
= OPCODE_ADD
;
19089 new_inst
= OPCODE_SUB
;
19093 case OPCODE_CMP
: /* CMP <-> CMN */
19094 new_inst
= OPCODE_CMN
;
19099 new_inst
= OPCODE_CMP
;
19103 /* Now Inverted ops. */
19104 case OPCODE_MOV
: /* MOV <-> MVN */
19105 new_inst
= OPCODE_MVN
;
19110 new_inst
= OPCODE_MOV
;
19114 case OPCODE_AND
: /* AND <-> BIC */
19115 new_inst
= OPCODE_BIC
;
19120 new_inst
= OPCODE_AND
;
19124 case OPCODE_ADC
: /* ADC <-> SBC */
19125 new_inst
= OPCODE_SBC
;
19130 new_inst
= OPCODE_ADC
;
19134 /* We cannot do anything. */
19139 if (value
== (unsigned) FAIL
)
19142 *instruction
&= OPCODE_MASK
;
19143 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19147 /* Like negate_data_op, but for Thumb-2. */
19149 static unsigned int
19150 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19154 unsigned int negated
, inverted
;
19156 negated
= encode_thumb32_immediate (-value
);
19157 inverted
= encode_thumb32_immediate (~value
);
19159 rd
= (*instruction
>> 8) & 0xf;
19160 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19163 /* ADD <-> SUB. Includes CMP <-> CMN. */
19164 case T2_OPCODE_SUB
:
19165 new_inst
= T2_OPCODE_ADD
;
19169 case T2_OPCODE_ADD
:
19170 new_inst
= T2_OPCODE_SUB
;
19174 /* ORR <-> ORN. Includes MOV <-> MVN. */
19175 case T2_OPCODE_ORR
:
19176 new_inst
= T2_OPCODE_ORN
;
19180 case T2_OPCODE_ORN
:
19181 new_inst
= T2_OPCODE_ORR
;
19185 /* AND <-> BIC. TST has no inverted equivalent. */
19186 case T2_OPCODE_AND
:
19187 new_inst
= T2_OPCODE_BIC
;
19194 case T2_OPCODE_BIC
:
19195 new_inst
= T2_OPCODE_AND
;
19200 case T2_OPCODE_ADC
:
19201 new_inst
= T2_OPCODE_SBC
;
19205 case T2_OPCODE_SBC
:
19206 new_inst
= T2_OPCODE_ADC
;
19210 /* We cannot do anything. */
19215 if (value
== (unsigned int)FAIL
)
19218 *instruction
&= T2_OPCODE_MASK
;
19219 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19223 /* Read a 32-bit thumb instruction from buf. */
19224 static unsigned long
19225 get_thumb32_insn (char * buf
)
19227 unsigned long insn
;
19228 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19229 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19235 /* We usually want to set the low bit on the address of thumb function
19236 symbols. In particular .word foo - . should have the low bit set.
19237 Generic code tries to fold the difference of two symbols to
19238 a constant. Prevent this and force a relocation when the first symbols
19239 is a thumb function. */
19242 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19244 if (op
== O_subtract
19245 && l
->X_op
== O_symbol
19246 && r
->X_op
== O_symbol
19247 && THUMB_IS_FUNC (l
->X_add_symbol
))
19249 l
->X_op
= O_subtract
;
19250 l
->X_op_symbol
= r
->X_add_symbol
;
19251 l
->X_add_number
-= r
->X_add_number
;
19255 /* Process as normal. */
19260 md_apply_fix (fixS
* fixP
,
19264 offsetT value
= * valP
;
19266 unsigned int newimm
;
19267 unsigned long temp
;
19269 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19271 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19273 /* Note whether this will delete the relocation. */
19275 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19278 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19279 consistency with the behaviour on 32-bit hosts. Remember value
19281 value
&= 0xffffffff;
19282 value
^= 0x80000000;
19283 value
-= 0x80000000;
19286 fixP
->fx_addnumber
= value
;
19288 /* Same treatment for fixP->fx_offset. */
19289 fixP
->fx_offset
&= 0xffffffff;
19290 fixP
->fx_offset
^= 0x80000000;
19291 fixP
->fx_offset
-= 0x80000000;
19293 switch (fixP
->fx_r_type
)
19295 case BFD_RELOC_NONE
:
19296 /* This will need to go in the object file. */
19300 case BFD_RELOC_ARM_IMMEDIATE
:
19301 /* We claim that this fixup has been processed here,
19302 even if in fact we generate an error because we do
19303 not have a reloc for it, so tc_gen_reloc will reject it. */
19307 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19309 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19310 _("undefined symbol %s used as an immediate value"),
19311 S_GET_NAME (fixP
->fx_addsy
));
19316 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19318 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19319 _("symbol %s is in a different section"),
19320 S_GET_NAME (fixP
->fx_addsy
));
19324 newimm
= encode_arm_immediate (value
);
19325 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19327 /* If the instruction will fail, see if we can fix things up by
19328 changing the opcode. */
19329 if (newimm
== (unsigned int) FAIL
19330 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19332 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19333 _("invalid constant (%lx) after fixup"),
19334 (unsigned long) value
);
19338 newimm
|= (temp
& 0xfffff000);
19339 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19342 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19344 unsigned int highpart
= 0;
19345 unsigned int newinsn
= 0xe1a00000; /* nop. */
19348 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19350 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19351 _("undefined symbol %s used as an immediate value"),
19352 S_GET_NAME (fixP
->fx_addsy
));
19357 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19359 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19360 _("symbol %s is in a different section"),
19361 S_GET_NAME (fixP
->fx_addsy
));
19365 newimm
= encode_arm_immediate (value
);
19366 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19368 /* If the instruction will fail, see if we can fix things up by
19369 changing the opcode. */
19370 if (newimm
== (unsigned int) FAIL
19371 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19373 /* No ? OK - try using two ADD instructions to generate
19375 newimm
= validate_immediate_twopart (value
, & highpart
);
19377 /* Yes - then make sure that the second instruction is
19379 if (newimm
!= (unsigned int) FAIL
)
19381 /* Still No ? Try using a negated value. */
19382 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19383 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19384 /* Otherwise - give up. */
19387 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19388 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19393 /* Replace the first operand in the 2nd instruction (which
19394 is the PC) with the destination register. We have
19395 already added in the PC in the first instruction and we
19396 do not want to do it again. */
19397 newinsn
&= ~ 0xf0000;
19398 newinsn
|= ((newinsn
& 0x0f000) << 4);
19401 newimm
|= (temp
& 0xfffff000);
19402 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19404 highpart
|= (newinsn
& 0xfffff000);
19405 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
19409 case BFD_RELOC_ARM_OFFSET_IMM
:
19410 if (!fixP
->fx_done
&& seg
->use_rela_p
)
19413 case BFD_RELOC_ARM_LITERAL
:
19419 if (validate_offset_imm (value
, 0) == FAIL
)
19421 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
19422 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19423 _("invalid literal constant: pool needs to be closer"));
19425 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19426 _("bad immediate value for offset (%ld)"),
19431 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19432 newval
&= 0xff7ff000;
19433 newval
|= value
| (sign
? INDEX_UP
: 0);
19434 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19437 case BFD_RELOC_ARM_OFFSET_IMM8
:
19438 case BFD_RELOC_ARM_HWLITERAL
:
19444 if (validate_offset_imm (value
, 1) == FAIL
)
19446 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
19447 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19448 _("invalid literal constant: pool needs to be closer"));
19450 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
19455 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19456 newval
&= 0xff7ff0f0;
19457 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
19458 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19461 case BFD_RELOC_ARM_T32_OFFSET_U8
:
19462 if (value
< 0 || value
> 1020 || value
% 4 != 0)
19463 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19464 _("bad immediate value for offset (%ld)"), (long) value
);
19467 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
19469 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
19472 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19473 /* This is a complicated relocation used for all varieties of Thumb32
19474 load/store instruction with immediate offset:
19476 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
19477 *4, optional writeback(W)
19478 (doubleword load/store)
19480 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
19481 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
19482 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
19483 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
19484 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
19486 Uppercase letters indicate bits that are already encoded at
19487 this point. Lowercase letters are our problem. For the
19488 second block of instructions, the secondary opcode nybble
19489 (bits 8..11) is present, and bit 23 is zero, even if this is
19490 a PC-relative operation. */
19491 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19493 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
19495 if ((newval
& 0xf0000000) == 0xe0000000)
19497 /* Doubleword load/store: 8-bit offset, scaled by 4. */
19499 newval
|= (1 << 23);
19502 if (value
% 4 != 0)
19504 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19505 _("offset not a multiple of 4"));
19511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19512 _("offset out of range"));
19517 else if ((newval
& 0x000f0000) == 0x000f0000)
19519 /* PC-relative, 12-bit offset. */
19521 newval
|= (1 << 23);
19526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19527 _("offset out of range"));
19532 else if ((newval
& 0x00000100) == 0x00000100)
19534 /* Writeback: 8-bit, +/- offset. */
19536 newval
|= (1 << 9);
19541 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19542 _("offset out of range"));
19547 else if ((newval
& 0x00000f00) == 0x00000e00)
19549 /* T-instruction: positive 8-bit offset. */
19550 if (value
< 0 || value
> 0xff)
19552 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19553 _("offset out of range"));
19561 /* Positive 12-bit or negative 8-bit offset. */
19565 newval
|= (1 << 23);
19575 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19576 _("offset out of range"));
19583 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
19584 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
19587 case BFD_RELOC_ARM_SHIFT_IMM
:
19588 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19589 if (((unsigned long) value
) > 32
19591 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
19593 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19594 _("shift expression is too large"));
19599 /* Shifts of zero must be done as lsl. */
19601 else if (value
== 32)
19603 newval
&= 0xfffff07f;
19604 newval
|= (value
& 0x1f) << 7;
19605 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19608 case BFD_RELOC_ARM_T32_IMMEDIATE
:
19609 case BFD_RELOC_ARM_T32_ADD_IMM
:
19610 case BFD_RELOC_ARM_T32_IMM12
:
19611 case BFD_RELOC_ARM_T32_ADD_PC12
:
19612 /* We claim that this fixup has been processed here,
19613 even if in fact we generate an error because we do
19614 not have a reloc for it, so tc_gen_reloc will reject it. */
19618 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19620 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19621 _("undefined symbol %s used as an immediate value"),
19622 S_GET_NAME (fixP
->fx_addsy
));
19626 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19628 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
19631 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19632 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19634 newimm
= encode_thumb32_immediate (value
);
19635 if (newimm
== (unsigned int) FAIL
)
19636 newimm
= thumb32_negate_data_op (&newval
, value
);
19638 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
19639 && newimm
== (unsigned int) FAIL
)
19641 /* Turn add/sum into addw/subw. */
19642 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19643 newval
= (newval
& 0xfeffffff) | 0x02000000;
19645 /* 12 bit immediate for addw/subw. */
19649 newval
^= 0x00a00000;
19652 newimm
= (unsigned int) FAIL
;
19657 if (newimm
== (unsigned int)FAIL
)
19659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19660 _("invalid constant (%lx) after fixup"),
19661 (unsigned long) value
);
19665 newval
|= (newimm
& 0x800) << 15;
19666 newval
|= (newimm
& 0x700) << 4;
19667 newval
|= (newimm
& 0x0ff);
19669 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
19670 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
19673 case BFD_RELOC_ARM_SMC
:
19674 if (((unsigned long) value
) > 0xffff)
19675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19676 _("invalid smc expression"));
19677 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19678 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
19679 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19682 case BFD_RELOC_ARM_SWI
:
19683 if (fixP
->tc_fix_data
!= 0)
19685 if (((unsigned long) value
) > 0xff)
19686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19687 _("invalid swi expression"));
19688 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19690 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19694 if (((unsigned long) value
) > 0x00ffffff)
19695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19696 _("invalid swi expression"));
19697 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19699 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19703 case BFD_RELOC_ARM_MULTI
:
19704 if (((unsigned long) value
) > 0xffff)
19705 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19706 _("invalid expression in load/store multiple"));
19707 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
19708 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19712 case BFD_RELOC_ARM_PCREL_CALL
:
19714 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19716 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19717 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19718 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19719 /* Flip the bl to blx. This is a simple flip
19720 bit here because we generate PCREL_CALL for
19721 unconditional bls. */
19723 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19724 newval
= newval
| 0x10000000;
19725 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19731 goto arm_branch_common
;
19733 case BFD_RELOC_ARM_PCREL_JUMP
:
19734 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19736 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19737 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19738 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19740 /* This would map to a bl<cond>, b<cond>,
19741 b<always> to a Thumb function. We
19742 need to force a relocation for this particular
19744 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19748 case BFD_RELOC_ARM_PLT32
:
19750 case BFD_RELOC_ARM_PCREL_BRANCH
:
19752 goto arm_branch_common
;
19754 case BFD_RELOC_ARM_PCREL_BLX
:
19757 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19759 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19760 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19761 && ARM_IS_FUNC (fixP
->fx_addsy
))
19763 /* Flip the blx to a bl and warn. */
19764 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
19765 newval
= 0xeb000000;
19766 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
19767 _("blx to '%s' an ARM ISA state function changed to bl"),
19769 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19775 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
19776 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
19780 /* We are going to store value (shifted right by two) in the
19781 instruction, in a 24 bit, signed field. Bits 26 through 32 either
19782 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
19783 also be be clear. */
19785 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19786 _("misaligned branch destination"));
19787 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
19788 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
19789 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19790 _("branch out of range"));
19792 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19794 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19795 newval
|= (value
>> 2) & 0x00ffffff;
19796 /* Set the H bit on BLX instructions. */
19800 newval
|= 0x01000000;
19802 newval
&= ~0x01000000;
19804 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19808 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
19809 /* CBZ can only branch forward. */
19811 /* Attempts to use CBZ to branch to the next instruction
19812 (which, strictly speaking, are prohibited) will be turned into
19815 FIXME: It may be better to remove the instruction completely and
19816 perform relaxation. */
19819 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19820 newval
= 0xbf00; /* NOP encoding T1 */
19821 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19826 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19827 _("branch out of range"));
19829 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19831 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19832 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
19833 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19838 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
19839 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
19840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19841 _("branch out of range"));
19843 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19845 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19846 newval
|= (value
& 0x1ff) >> 1;
19847 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19851 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
19852 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
19853 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19854 _("branch out of range"));
19856 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19858 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19859 newval
|= (value
& 0xfff) >> 1;
19860 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19864 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19866 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19867 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19868 && S_IS_DEFINED (fixP
->fx_addsy
)
19869 && ARM_IS_FUNC (fixP
->fx_addsy
)
19870 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19872 /* Force a relocation for a branch 20 bits wide. */
19875 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
19876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19877 _("conditional branch out of range"));
19879 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19882 addressT S
, J1
, J2
, lo
, hi
;
19884 S
= (value
& 0x00100000) >> 20;
19885 J2
= (value
& 0x00080000) >> 19;
19886 J1
= (value
& 0x00040000) >> 18;
19887 hi
= (value
& 0x0003f000) >> 12;
19888 lo
= (value
& 0x00000ffe) >> 1;
19890 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19891 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19892 newval
|= (S
<< 10) | hi
;
19893 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
19894 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19895 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19899 case BFD_RELOC_THUMB_PCREL_BLX
:
19901 /* If there is a blx from a thumb state function to
19902 another thumb function flip this to a bl and warn
19906 && S_IS_DEFINED (fixP
->fx_addsy
)
19907 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19908 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19909 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19911 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
19912 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
19913 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
19915 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19916 newval
= newval
| 0x1000;
19917 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
19918 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
19923 goto thumb_bl_common
;
19925 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19927 /* A bl from Thumb state ISA to an internal ARM state function
19928 is converted to a blx. */
19930 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19931 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19932 && S_IS_DEFINED (fixP
->fx_addsy
)
19933 && ARM_IS_FUNC (fixP
->fx_addsy
)
19934 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19936 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19937 newval
= newval
& ~0x1000;
19938 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
19939 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
19946 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
19947 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
19948 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
19951 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
19952 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19953 _("branch out of range"));
19955 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
19956 /* For a BLX instruction, make sure that the relocation is rounded up
19957 to a word boundary. This follows the semantics of the instruction
19958 which specifies that bit 1 of the target address will come from bit
19959 1 of the base address. */
19960 value
= (value
+ 1) & ~ 1;
19962 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19966 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19967 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19968 newval
|= (value
& 0x7fffff) >> 12;
19969 newval2
|= (value
& 0xfff) >> 1;
19970 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19971 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19975 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19976 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
19977 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19978 _("branch out of range"));
19980 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19983 addressT S
, I1
, I2
, lo
, hi
;
19985 S
= (value
& 0x01000000) >> 24;
19986 I1
= (value
& 0x00800000) >> 23;
19987 I2
= (value
& 0x00400000) >> 22;
19988 hi
= (value
& 0x003ff000) >> 12;
19989 lo
= (value
& 0x00000ffe) >> 1;
19994 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19995 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19996 newval
|= (S
<< 10) | hi
;
19997 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
19998 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19999 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20004 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20005 md_number_to_chars (buf
, value
, 1);
20009 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20010 md_number_to_chars (buf
, value
, 2);
20014 case BFD_RELOC_ARM_TLS_GD32
:
20015 case BFD_RELOC_ARM_TLS_LE32
:
20016 case BFD_RELOC_ARM_TLS_IE32
:
20017 case BFD_RELOC_ARM_TLS_LDM32
:
20018 case BFD_RELOC_ARM_TLS_LDO32
:
20019 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20022 case BFD_RELOC_ARM_GOT32
:
20023 case BFD_RELOC_ARM_GOTOFF
:
20024 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20025 md_number_to_chars (buf
, 0, 4);
20028 case BFD_RELOC_ARM_TARGET2
:
20029 /* TARGET2 is not partial-inplace, so we need to write the
20030 addend here for REL targets, because it won't be written out
20031 during reloc processing later. */
20032 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20033 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20037 case BFD_RELOC_RVA
:
20039 case BFD_RELOC_ARM_TARGET1
:
20040 case BFD_RELOC_ARM_ROSEGREL32
:
20041 case BFD_RELOC_ARM_SBREL32
:
20042 case BFD_RELOC_32_PCREL
:
20044 case BFD_RELOC_32_SECREL
:
20046 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20048 /* For WinCE we only do this for pcrel fixups. */
20049 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20051 md_number_to_chars (buf
, value
, 4);
20055 case BFD_RELOC_ARM_PREL31
:
20056 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20058 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20059 if ((value
^ (value
>> 1)) & 0x40000000)
20061 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20062 _("rel31 relocation overflow"));
20064 newval
|= value
& 0x7fffffff;
20065 md_number_to_chars (buf
, newval
, 4);
20070 case BFD_RELOC_ARM_CP_OFF_IMM
:
20071 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20072 if (value
< -1023 || value
> 1023 || (value
& 3))
20073 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20074 _("co-processor offset out of range"));
20079 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20080 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20081 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20083 newval
= get_thumb32_insn (buf
);
20084 newval
&= 0xff7fff00;
20085 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20086 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20087 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20088 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20090 put_thumb32_insn (buf
, newval
);
20093 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20094 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20095 if (value
< -255 || value
> 255)
20096 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20097 _("co-processor offset out of range"));
20099 goto cp_off_common
;
20101 case BFD_RELOC_ARM_THUMB_OFFSET
:
20102 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20103 /* Exactly what ranges, and where the offset is inserted depends
20104 on the type of instruction, we can establish this from the
20106 switch (newval
>> 12)
20108 case 4: /* PC load. */
20109 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20110 forced to zero for these loads; md_pcrel_from has already
20111 compensated for this. */
20113 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20114 _("invalid offset, target not word aligned (0x%08lX)"),
20115 (((unsigned long) fixP
->fx_frag
->fr_address
20116 + (unsigned long) fixP
->fx_where
) & ~3)
20117 + (unsigned long) value
);
20119 if (value
& ~0x3fc)
20120 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20121 _("invalid offset, value too big (0x%08lX)"),
20124 newval
|= value
>> 2;
20127 case 9: /* SP load/store. */
20128 if (value
& ~0x3fc)
20129 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20130 _("invalid offset, value too big (0x%08lX)"),
20132 newval
|= value
>> 2;
20135 case 6: /* Word load/store. */
20137 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20138 _("invalid offset, value too big (0x%08lX)"),
20140 newval
|= value
<< 4; /* 6 - 2. */
20143 case 7: /* Byte load/store. */
20145 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20146 _("invalid offset, value too big (0x%08lX)"),
20148 newval
|= value
<< 6;
20151 case 8: /* Halfword load/store. */
20153 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20154 _("invalid offset, value too big (0x%08lX)"),
20156 newval
|= value
<< 5; /* 6 - 1. */
20160 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20161 "Unable to process relocation for thumb opcode: %lx",
20162 (unsigned long) newval
);
20165 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20168 case BFD_RELOC_ARM_THUMB_ADD
:
20169 /* This is a complicated relocation, since we use it for all of
20170 the following immediate relocations:
20174 9bit ADD/SUB SP word-aligned
20175 10bit ADD PC/SP word-aligned
20177 The type of instruction being processed is encoded in the
20184 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20186 int rd
= (newval
>> 4) & 0xf;
20187 int rs
= newval
& 0xf;
20188 int subtract
= !!(newval
& 0x8000);
20190 /* Check for HI regs, only very restricted cases allowed:
20191 Adjusting SP, and using PC or SP to get an address. */
20192 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20193 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20194 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20195 _("invalid Hi register with immediate"));
20197 /* If value is negative, choose the opposite instruction. */
20201 subtract
= !subtract
;
20203 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20204 _("immediate value out of range"));
20209 if (value
& ~0x1fc)
20210 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20211 _("invalid immediate for stack address calculation"));
20212 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20213 newval
|= value
>> 2;
20215 else if (rs
== REG_PC
|| rs
== REG_SP
)
20217 if (subtract
|| value
& ~0x3fc)
20218 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20219 _("invalid immediate for address calculation (value = 0x%08lX)"),
20220 (unsigned long) value
);
20221 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20223 newval
|= value
>> 2;
20228 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20229 _("immediate value out of range"));
20230 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20231 newval
|= (rd
<< 8) | value
;
20236 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20237 _("immediate value out of range"));
20238 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20239 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20242 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20245 case BFD_RELOC_ARM_THUMB_IMM
:
20246 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20247 if (value
< 0 || value
> 255)
20248 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20249 _("invalid immediate: %ld is out of range"),
20252 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20255 case BFD_RELOC_ARM_THUMB_SHIFT
:
20256 /* 5bit shift value (0..32). LSL cannot take 32. */
20257 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20258 temp
= newval
& 0xf800;
20259 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20260 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20261 _("invalid shift value: %ld"), (long) value
);
20262 /* Shifts of zero must be encoded as LSL. */
20264 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20265 /* Shifts of 32 are encoded as zero. */
20266 else if (value
== 32)
20268 newval
|= value
<< 6;
20269 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20272 case BFD_RELOC_VTABLE_INHERIT
:
20273 case BFD_RELOC_VTABLE_ENTRY
:
20277 case BFD_RELOC_ARM_MOVW
:
20278 case BFD_RELOC_ARM_MOVT
:
20279 case BFD_RELOC_ARM_THUMB_MOVW
:
20280 case BFD_RELOC_ARM_THUMB_MOVT
:
20281 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20283 /* REL format relocations are limited to a 16-bit addend. */
20284 if (!fixP
->fx_done
)
20286 if (value
< -0x8000 || value
> 0x7fff)
20287 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20288 _("offset out of range"));
20290 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20291 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20296 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20297 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20299 newval
= get_thumb32_insn (buf
);
20300 newval
&= 0xfbf08f00;
20301 newval
|= (value
& 0xf000) << 4;
20302 newval
|= (value
& 0x0800) << 15;
20303 newval
|= (value
& 0x0700) << 4;
20304 newval
|= (value
& 0x00ff);
20305 put_thumb32_insn (buf
, newval
);
20309 newval
= md_chars_to_number (buf
, 4);
20310 newval
&= 0xfff0f000;
20311 newval
|= value
& 0x0fff;
20312 newval
|= (value
& 0xf000) << 4;
20313 md_number_to_chars (buf
, newval
, 4);
20318 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20319 case BFD_RELOC_ARM_ALU_PC_G0
:
20320 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20321 case BFD_RELOC_ARM_ALU_PC_G1
:
20322 case BFD_RELOC_ARM_ALU_PC_G2
:
20323 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20324 case BFD_RELOC_ARM_ALU_SB_G0
:
20325 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20326 case BFD_RELOC_ARM_ALU_SB_G1
:
20327 case BFD_RELOC_ARM_ALU_SB_G2
:
20328 gas_assert (!fixP
->fx_done
);
20329 if (!seg
->use_rela_p
)
20332 bfd_vma encoded_addend
;
20333 bfd_vma addend_abs
= abs (value
);
20335 /* Check that the absolute value of the addend can be
20336 expressed as an 8-bit constant plus a rotation. */
20337 encoded_addend
= encode_arm_immediate (addend_abs
);
20338 if (encoded_addend
== (unsigned int) FAIL
)
20339 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20340 _("the offset 0x%08lX is not representable"),
20341 (unsigned long) addend_abs
);
20343 /* Extract the instruction. */
20344 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20346 /* If the addend is positive, use an ADD instruction.
20347 Otherwise use a SUB. Take care not to destroy the S bit. */
20348 insn
&= 0xff1fffff;
20354 /* Place the encoded addend into the first 12 bits of the
20356 insn
&= 0xfffff000;
20357 insn
|= encoded_addend
;
20359 /* Update the instruction. */
20360 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20364 case BFD_RELOC_ARM_LDR_PC_G0
:
20365 case BFD_RELOC_ARM_LDR_PC_G1
:
20366 case BFD_RELOC_ARM_LDR_PC_G2
:
20367 case BFD_RELOC_ARM_LDR_SB_G0
:
20368 case BFD_RELOC_ARM_LDR_SB_G1
:
20369 case BFD_RELOC_ARM_LDR_SB_G2
:
20370 gas_assert (!fixP
->fx_done
);
20371 if (!seg
->use_rela_p
)
20374 bfd_vma addend_abs
= abs (value
);
20376 /* Check that the absolute value of the addend can be
20377 encoded in 12 bits. */
20378 if (addend_abs
>= 0x1000)
20379 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20380 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20381 (unsigned long) addend_abs
);
20383 /* Extract the instruction. */
20384 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20386 /* If the addend is negative, clear bit 23 of the instruction.
20387 Otherwise set it. */
20389 insn
&= ~(1 << 23);
20393 /* Place the absolute value of the addend into the first 12 bits
20394 of the instruction. */
20395 insn
&= 0xfffff000;
20396 insn
|= addend_abs
;
20398 /* Update the instruction. */
20399 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20403 case BFD_RELOC_ARM_LDRS_PC_G0
:
20404 case BFD_RELOC_ARM_LDRS_PC_G1
:
20405 case BFD_RELOC_ARM_LDRS_PC_G2
:
20406 case BFD_RELOC_ARM_LDRS_SB_G0
:
20407 case BFD_RELOC_ARM_LDRS_SB_G1
:
20408 case BFD_RELOC_ARM_LDRS_SB_G2
:
20409 gas_assert (!fixP
->fx_done
);
20410 if (!seg
->use_rela_p
)
20413 bfd_vma addend_abs
= abs (value
);
20415 /* Check that the absolute value of the addend can be
20416 encoded in 8 bits. */
20417 if (addend_abs
>= 0x100)
20418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20419 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
20420 (unsigned long) addend_abs
);
20422 /* Extract the instruction. */
20423 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20425 /* If the addend is negative, clear bit 23 of the instruction.
20426 Otherwise set it. */
20428 insn
&= ~(1 << 23);
20432 /* Place the first four bits of the absolute value of the addend
20433 into the first 4 bits of the instruction, and the remaining
20434 four into bits 8 .. 11. */
20435 insn
&= 0xfffff0f0;
20436 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
20438 /* Update the instruction. */
20439 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20443 case BFD_RELOC_ARM_LDC_PC_G0
:
20444 case BFD_RELOC_ARM_LDC_PC_G1
:
20445 case BFD_RELOC_ARM_LDC_PC_G2
:
20446 case BFD_RELOC_ARM_LDC_SB_G0
:
20447 case BFD_RELOC_ARM_LDC_SB_G1
:
20448 case BFD_RELOC_ARM_LDC_SB_G2
:
20449 gas_assert (!fixP
->fx_done
);
20450 if (!seg
->use_rela_p
)
20453 bfd_vma addend_abs
= abs (value
);
20455 /* Check that the absolute value of the addend is a multiple of
20456 four and, when divided by four, fits in 8 bits. */
20457 if (addend_abs
& 0x3)
20458 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20459 _("bad offset 0x%08lX (must be word-aligned)"),
20460 (unsigned long) addend_abs
);
20462 if ((addend_abs
>> 2) > 0xff)
20463 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20464 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
20465 (unsigned long) addend_abs
);
20467 /* Extract the instruction. */
20468 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20470 /* If the addend is negative, clear bit 23 of the instruction.
20471 Otherwise set it. */
20473 insn
&= ~(1 << 23);
20477 /* Place the addend (divided by four) into the first eight
20478 bits of the instruction. */
20479 insn
&= 0xfffffff0;
20480 insn
|= addend_abs
>> 2;
20482 /* Update the instruction. */
20483 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20487 case BFD_RELOC_ARM_V4BX
:
20488 /* This will need to go in the object file. */
20492 case BFD_RELOC_UNUSED
:
20494 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20495 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
20499 /* Translate internal representation of relocation info to BFD target
20503 tc_gen_reloc (asection
*section
, fixS
*fixp
)
20506 bfd_reloc_code_real_type code
;
20508 reloc
= xmalloc (sizeof (arelent
));
20510 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
20511 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
20512 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
20514 if (fixp
->fx_pcrel
)
20516 if (section
->use_rela_p
)
20517 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
20519 fixp
->fx_offset
= reloc
->address
;
20521 reloc
->addend
= fixp
->fx_offset
;
20523 switch (fixp
->fx_r_type
)
20526 if (fixp
->fx_pcrel
)
20528 code
= BFD_RELOC_8_PCREL
;
20533 if (fixp
->fx_pcrel
)
20535 code
= BFD_RELOC_16_PCREL
;
20540 if (fixp
->fx_pcrel
)
20542 code
= BFD_RELOC_32_PCREL
;
20546 case BFD_RELOC_ARM_MOVW
:
20547 if (fixp
->fx_pcrel
)
20549 code
= BFD_RELOC_ARM_MOVW_PCREL
;
20553 case BFD_RELOC_ARM_MOVT
:
20554 if (fixp
->fx_pcrel
)
20556 code
= BFD_RELOC_ARM_MOVT_PCREL
;
20560 case BFD_RELOC_ARM_THUMB_MOVW
:
20561 if (fixp
->fx_pcrel
)
20563 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
20567 case BFD_RELOC_ARM_THUMB_MOVT
:
20568 if (fixp
->fx_pcrel
)
20570 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
20574 case BFD_RELOC_NONE
:
20575 case BFD_RELOC_ARM_PCREL_BRANCH
:
20576 case BFD_RELOC_ARM_PCREL_BLX
:
20577 case BFD_RELOC_RVA
:
20578 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
20579 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
20580 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
20581 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20582 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20583 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20584 case BFD_RELOC_VTABLE_ENTRY
:
20585 case BFD_RELOC_VTABLE_INHERIT
:
20587 case BFD_RELOC_32_SECREL
:
20589 code
= fixp
->fx_r_type
;
20592 case BFD_RELOC_THUMB_PCREL_BLX
:
20594 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20595 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20598 code
= BFD_RELOC_THUMB_PCREL_BLX
;
20601 case BFD_RELOC_ARM_LITERAL
:
20602 case BFD_RELOC_ARM_HWLITERAL
:
20603 /* If this is called then the a literal has
20604 been referenced across a section boundary. */
20605 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20606 _("literal referenced across section boundary"));
20610 case BFD_RELOC_ARM_GOT32
:
20611 case BFD_RELOC_ARM_GOTOFF
:
20612 case BFD_RELOC_ARM_PLT32
:
20613 case BFD_RELOC_ARM_TARGET1
:
20614 case BFD_RELOC_ARM_ROSEGREL32
:
20615 case BFD_RELOC_ARM_SBREL32
:
20616 case BFD_RELOC_ARM_PREL31
:
20617 case BFD_RELOC_ARM_TARGET2
:
20618 case BFD_RELOC_ARM_TLS_LE32
:
20619 case BFD_RELOC_ARM_TLS_LDO32
:
20620 case BFD_RELOC_ARM_PCREL_CALL
:
20621 case BFD_RELOC_ARM_PCREL_JUMP
:
20622 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20623 case BFD_RELOC_ARM_ALU_PC_G0
:
20624 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20625 case BFD_RELOC_ARM_ALU_PC_G1
:
20626 case BFD_RELOC_ARM_ALU_PC_G2
:
20627 case BFD_RELOC_ARM_LDR_PC_G0
:
20628 case BFD_RELOC_ARM_LDR_PC_G1
:
20629 case BFD_RELOC_ARM_LDR_PC_G2
:
20630 case BFD_RELOC_ARM_LDRS_PC_G0
:
20631 case BFD_RELOC_ARM_LDRS_PC_G1
:
20632 case BFD_RELOC_ARM_LDRS_PC_G2
:
20633 case BFD_RELOC_ARM_LDC_PC_G0
:
20634 case BFD_RELOC_ARM_LDC_PC_G1
:
20635 case BFD_RELOC_ARM_LDC_PC_G2
:
20636 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20637 case BFD_RELOC_ARM_ALU_SB_G0
:
20638 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20639 case BFD_RELOC_ARM_ALU_SB_G1
:
20640 case BFD_RELOC_ARM_ALU_SB_G2
:
20641 case BFD_RELOC_ARM_LDR_SB_G0
:
20642 case BFD_RELOC_ARM_LDR_SB_G1
:
20643 case BFD_RELOC_ARM_LDR_SB_G2
:
20644 case BFD_RELOC_ARM_LDRS_SB_G0
:
20645 case BFD_RELOC_ARM_LDRS_SB_G1
:
20646 case BFD_RELOC_ARM_LDRS_SB_G2
:
20647 case BFD_RELOC_ARM_LDC_SB_G0
:
20648 case BFD_RELOC_ARM_LDC_SB_G1
:
20649 case BFD_RELOC_ARM_LDC_SB_G2
:
20650 case BFD_RELOC_ARM_V4BX
:
20651 code
= fixp
->fx_r_type
;
20654 case BFD_RELOC_ARM_TLS_GD32
:
20655 case BFD_RELOC_ARM_TLS_IE32
:
20656 case BFD_RELOC_ARM_TLS_LDM32
:
20657 /* BFD will include the symbol's address in the addend.
20658 But we don't want that, so subtract it out again here. */
20659 if (!S_IS_COMMON (fixp
->fx_addsy
))
20660 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
20661 code
= fixp
->fx_r_type
;
20665 case BFD_RELOC_ARM_IMMEDIATE
:
20666 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20667 _("internal relocation (type: IMMEDIATE) not fixed up"));
20670 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20671 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20672 _("ADRL used for a symbol not defined in the same file"));
20675 case BFD_RELOC_ARM_OFFSET_IMM
:
20676 if (section
->use_rela_p
)
20678 code
= fixp
->fx_r_type
;
20682 if (fixp
->fx_addsy
!= NULL
20683 && !S_IS_DEFINED (fixp
->fx_addsy
)
20684 && S_IS_LOCAL (fixp
->fx_addsy
))
20686 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20687 _("undefined local label `%s'"),
20688 S_GET_NAME (fixp
->fx_addsy
));
20692 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20693 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
20700 switch (fixp
->fx_r_type
)
20702 case BFD_RELOC_NONE
: type
= "NONE"; break;
20703 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
20704 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
20705 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
20706 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
20707 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
20708 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
20709 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
20710 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
20711 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
20712 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
20713 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
20714 default: type
= _("<unknown>"); break;
20716 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20717 _("cannot represent %s relocation in this object file format"),
20724 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
20726 && fixp
->fx_addsy
== GOT_symbol
)
20728 code
= BFD_RELOC_ARM_GOTPC
;
20729 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
20733 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
20735 if (reloc
->howto
== NULL
)
20737 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20738 _("cannot represent %s relocation in this object file format"),
20739 bfd_get_reloc_code_name (code
));
20743 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
20744 vtable entry to be used in the relocation's section offset. */
20745 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
20746 reloc
->address
= fixp
->fx_offset
;
20751 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
20754 cons_fix_new_arm (fragS
* frag
,
20759 bfd_reloc_code_real_type type
;
20763 FIXME: @@ Should look at CPU word size. */
20767 type
= BFD_RELOC_8
;
20770 type
= BFD_RELOC_16
;
20774 type
= BFD_RELOC_32
;
20777 type
= BFD_RELOC_64
;
20782 if (exp
->X_op
== O_secrel
)
20784 exp
->X_op
= O_symbol
;
20785 type
= BFD_RELOC_32_SECREL
;
20789 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
20792 #if defined (OBJ_COFF)
20794 arm_validate_fix (fixS
* fixP
)
20796 /* If the destination of the branch is a defined symbol which does not have
20797 the THUMB_FUNC attribute, then we must be calling a function which has
20798 the (interfacearm) attribute. We look for the Thumb entry point to that
20799 function and change the branch to refer to that function instead. */
20800 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
20801 && fixP
->fx_addsy
!= NULL
20802 && S_IS_DEFINED (fixP
->fx_addsy
)
20803 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
20805 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
20812 arm_force_relocation (struct fix
* fixp
)
20814 #if defined (OBJ_COFF) && defined (TE_PE)
20815 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
20819 /* In case we have a call or a branch to a function in ARM ISA mode from
20820 a thumb function or vice-versa force the relocation. These relocations
20821 are cleared off for some cores that might have blx and simple transformations
20825 switch (fixp
->fx_r_type
)
20827 case BFD_RELOC_ARM_PCREL_JUMP
:
20828 case BFD_RELOC_ARM_PCREL_CALL
:
20829 case BFD_RELOC_THUMB_PCREL_BLX
:
20830 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
20834 case BFD_RELOC_ARM_PCREL_BLX
:
20835 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20836 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20837 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20838 if (ARM_IS_FUNC (fixp
->fx_addsy
))
20847 /* Resolve these relocations even if the symbol is extern or weak. */
20848 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
20849 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
20850 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
20851 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
20852 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20853 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
20854 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
20857 /* Always leave these relocations for the linker. */
20858 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
20859 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
20860 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
20863 /* Always generate relocations against function symbols. */
20864 if (fixp
->fx_r_type
== BFD_RELOC_32
20866 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
20869 return generic_force_reloc (fixp
);
20872 #if defined (OBJ_ELF) || defined (OBJ_COFF)
20873 /* Relocations against function names must be left unadjusted,
20874 so that the linker can use this information to generate interworking
20875 stubs. The MIPS version of this function
20876 also prevents relocations that are mips-16 specific, but I do not
20877 know why it does this.
20880 There is one other problem that ought to be addressed here, but
20881 which currently is not: Taking the address of a label (rather
20882 than a function) and then later jumping to that address. Such
20883 addresses also ought to have their bottom bit set (assuming that
20884 they reside in Thumb code), but at the moment they will not. */
20887 arm_fix_adjustable (fixS
* fixP
)
20889 if (fixP
->fx_addsy
== NULL
)
20892 /* Preserve relocations against symbols with function type. */
20893 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
20896 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
20897 && fixP
->fx_subsy
== NULL
)
20900 /* We need the symbol name for the VTABLE entries. */
20901 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
20902 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
20905 /* Don't allow symbols to be discarded on GOT related relocs. */
20906 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
20907 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
20908 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
20909 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
20910 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
20911 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
20912 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
20913 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
20914 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
20917 /* Similarly for group relocations. */
20918 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
20919 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
20920 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
20923 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
20924 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
20925 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20926 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
20927 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
20928 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20929 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
20930 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
20931 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
20936 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
20941 elf32_arm_target_format (void)
20944 return (target_big_endian
20945 ? "elf32-bigarm-symbian"
20946 : "elf32-littlearm-symbian");
20947 #elif defined (TE_VXWORKS)
20948 return (target_big_endian
20949 ? "elf32-bigarm-vxworks"
20950 : "elf32-littlearm-vxworks");
20952 if (target_big_endian
)
20953 return "elf32-bigarm";
20955 return "elf32-littlearm";
20960 armelf_frob_symbol (symbolS
* symp
,
20963 elf_frob_symbol (symp
, puntp
);
20967 /* MD interface: Finalization. */
20972 literal_pool
* pool
;
20974 /* Ensure that all the IT blocks are properly closed. */
20975 check_it_blocks_finished ();
20977 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
20979 /* Put it at the end of the relevant section. */
20980 subseg_set (pool
->section
, pool
->sub_section
);
20982 arm_elf_change_section ();
20988 /* Adjust the symbol table. This marks Thumb symbols as distinct from
20992 arm_adjust_symtab (void)
20997 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
20999 if (ARM_IS_THUMB (sym
))
21001 if (THUMB_IS_FUNC (sym
))
21003 /* Mark the symbol as a Thumb function. */
21004 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21005 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21006 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21008 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21009 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21011 as_bad (_("%s: unexpected function type: %d"),
21012 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21014 else switch (S_GET_STORAGE_CLASS (sym
))
21017 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21020 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21023 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21031 if (ARM_IS_INTERWORK (sym
))
21032 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21039 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21041 if (ARM_IS_THUMB (sym
))
21043 elf_symbol_type
* elf_sym
;
21045 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21046 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21048 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21049 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21051 /* If it's a .thumb_func, declare it as so,
21052 otherwise tag label as .code 16. */
21053 if (THUMB_IS_FUNC (sym
))
21054 elf_sym
->internal_elf_sym
.st_info
=
21055 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21056 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21057 elf_sym
->internal_elf_sym
.st_info
=
21058 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21065 /* MD interface: Initialization. */
21068 set_constant_flonums (void)
21072 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21073 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21077 /* Auto-select Thumb mode if it's the only available instruction set for the
21078 given architecture. */
21081 autoselect_thumb_from_cpu_variant (void)
21083 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21084 opcode_select (16);
21093 if ( (arm_ops_hsh
= hash_new ()) == NULL
21094 || (arm_cond_hsh
= hash_new ()) == NULL
21095 || (arm_shift_hsh
= hash_new ()) == NULL
21096 || (arm_psr_hsh
= hash_new ()) == NULL
21097 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21098 || (arm_reg_hsh
= hash_new ()) == NULL
21099 || (arm_reloc_hsh
= hash_new ()) == NULL
21100 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21101 as_fatal (_("virtual memory exhausted"));
21103 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21104 hash_insert (arm_ops_hsh
, insns
[i
].template, (void *) (insns
+ i
));
21105 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21106 hash_insert (arm_cond_hsh
, conds
[i
].template, (void *) (conds
+ i
));
21107 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21108 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21109 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21110 hash_insert (arm_psr_hsh
, psrs
[i
].template, (void *) (psrs
+ i
));
21111 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21112 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (void *) (v7m_psrs
+ i
));
21113 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21114 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21116 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21118 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
21119 (void *) (barrier_opt_names
+ i
));
21121 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21122 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21125 set_constant_flonums ();
21127 /* Set the cpu variant based on the command-line options. We prefer
21128 -mcpu= over -march= if both are set (as for GCC); and we prefer
21129 -mfpu= over any other way of setting the floating point unit.
21130 Use of legacy options with new options are faulted. */
21133 if (mcpu_cpu_opt
|| march_cpu_opt
)
21134 as_bad (_("use of old and new-style options to set CPU type"));
21136 mcpu_cpu_opt
= legacy_cpu
;
21138 else if (!mcpu_cpu_opt
)
21139 mcpu_cpu_opt
= march_cpu_opt
;
21144 as_bad (_("use of old and new-style options to set FPU type"));
21146 mfpu_opt
= legacy_fpu
;
21148 else if (!mfpu_opt
)
21150 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21151 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21152 /* Some environments specify a default FPU. If they don't, infer it
21153 from the processor. */
21155 mfpu_opt
= mcpu_fpu_opt
;
21157 mfpu_opt
= march_fpu_opt
;
21159 mfpu_opt
= &fpu_default
;
21165 if (mcpu_cpu_opt
!= NULL
)
21166 mfpu_opt
= &fpu_default
;
21167 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21168 mfpu_opt
= &fpu_arch_vfp_v2
;
21170 mfpu_opt
= &fpu_arch_fpa
;
21176 mcpu_cpu_opt
= &cpu_default
;
21177 selected_cpu
= cpu_default
;
21181 selected_cpu
= *mcpu_cpu_opt
;
21183 mcpu_cpu_opt
= &arm_arch_any
;
21186 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21188 autoselect_thumb_from_cpu_variant ();
21190 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21192 #if defined OBJ_COFF || defined OBJ_ELF
21194 unsigned int flags
= 0;
21196 #if defined OBJ_ELF
21197 flags
= meabi_flags
;
21199 switch (meabi_flags
)
21201 case EF_ARM_EABI_UNKNOWN
:
21203 /* Set the flags in the private structure. */
21204 if (uses_apcs_26
) flags
|= F_APCS26
;
21205 if (support_interwork
) flags
|= F_INTERWORK
;
21206 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21207 if (pic_code
) flags
|= F_PIC
;
21208 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21209 flags
|= F_SOFT_FLOAT
;
21211 switch (mfloat_abi_opt
)
21213 case ARM_FLOAT_ABI_SOFT
:
21214 case ARM_FLOAT_ABI_SOFTFP
:
21215 flags
|= F_SOFT_FLOAT
;
21218 case ARM_FLOAT_ABI_HARD
:
21219 if (flags
& F_SOFT_FLOAT
)
21220 as_bad (_("hard-float conflicts with specified fpu"));
21224 /* Using pure-endian doubles (even if soft-float). */
21225 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21226 flags
|= F_VFP_FLOAT
;
21228 #if defined OBJ_ELF
21229 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21230 flags
|= EF_ARM_MAVERICK_FLOAT
;
21233 case EF_ARM_EABI_VER4
:
21234 case EF_ARM_EABI_VER5
:
21235 /* No additional flags to set. */
21242 bfd_set_private_flags (stdoutput
, flags
);
21244 /* We have run out flags in the COFF header to encode the
21245 status of ATPCS support, so instead we create a dummy,
21246 empty, debug section called .arm.atpcs. */
21251 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21255 bfd_set_section_flags
21256 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21257 bfd_set_section_size (stdoutput
, sec
, 0);
21258 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21264 /* Record the CPU type as well. */
21265 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21266 mach
= bfd_mach_arm_iWMMXt2
;
21267 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21268 mach
= bfd_mach_arm_iWMMXt
;
21269 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21270 mach
= bfd_mach_arm_XScale
;
21271 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21272 mach
= bfd_mach_arm_ep9312
;
21273 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21274 mach
= bfd_mach_arm_5TE
;
21275 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21277 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21278 mach
= bfd_mach_arm_5T
;
21280 mach
= bfd_mach_arm_5
;
21282 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21284 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21285 mach
= bfd_mach_arm_4T
;
21287 mach
= bfd_mach_arm_4
;
21289 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21290 mach
= bfd_mach_arm_3M
;
21291 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21292 mach
= bfd_mach_arm_3
;
21293 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21294 mach
= bfd_mach_arm_2a
;
21295 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21296 mach
= bfd_mach_arm_2
;
21298 mach
= bfd_mach_arm_unknown
;
21300 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21303 /* Command line processing. */
21306 Invocation line includes a switch not recognized by the base assembler.
21307 See if it's a processor-specific option.
21309 This routine is somewhat complicated by the need for backwards
21310 compatibility (since older releases of gcc can't be changed).
21311 The new options try to make the interface as compatible as
21314 New options (supported) are:
21316 -mcpu=<cpu name> Assemble for selected processor
21317 -march=<architecture name> Assemble for selected architecture
21318 -mfpu=<fpu architecture> Assemble for selected FPU.
21319 -EB/-mbig-endian Big-endian
21320 -EL/-mlittle-endian Little-endian
21321 -k Generate PIC code
21322 -mthumb Start in Thumb mode
21323 -mthumb-interwork Code supports ARM/Thumb interworking
21325 -m[no-]warn-deprecated Warn about deprecated features
21327 For now we will also provide support for:
21329 -mapcs-32 32-bit Program counter
21330 -mapcs-26 26-bit Program counter
21331 -macps-float Floats passed in FP registers
21332 -mapcs-reentrant Reentrant code
21334 (sometime these will probably be replaced with -mapcs=<list of options>
21335 and -matpcs=<list of options>)
21337 The remaining options are only supported for back-wards compatibility.
21338 Cpu variants, the arm part is optional:
21339 -m[arm]1 Currently not supported.
21340 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21341 -m[arm]3 Arm 3 processor
21342 -m[arm]6[xx], Arm 6 processors
21343 -m[arm]7[xx][t][[d]m] Arm 7 processors
21344 -m[arm]8[10] Arm 8 processors
21345 -m[arm]9[20][tdmi] Arm 9 processors
21346 -mstrongarm[110[0]] StrongARM processors
21347 -mxscale XScale processors
21348 -m[arm]v[2345[t[e]]] Arm architectures
21349 -mall All (except the ARM1)
21351 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
21352 -mfpe-old (No float load/store multiples)
21353 -mvfpxd VFP Single precision
21355 -mno-fpu Disable all floating point instructions
21357 The following CPU names are recognized:
21358 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
21359 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
21360 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
21361 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
21362 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
21363 arm10t arm10e, arm1020t, arm1020e, arm10200e,
21364 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
21368 const char * md_shortopts
= "m:k";
21370 #ifdef ARM_BI_ENDIAN
21371 #define OPTION_EB (OPTION_MD_BASE + 0)
21372 #define OPTION_EL (OPTION_MD_BASE + 1)
21374 #if TARGET_BYTES_BIG_ENDIAN
21375 #define OPTION_EB (OPTION_MD_BASE + 0)
21377 #define OPTION_EL (OPTION_MD_BASE + 1)
21380 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
21382 struct option md_longopts
[] =
21385 {"EB", no_argument
, NULL
, OPTION_EB
},
21388 {"EL", no_argument
, NULL
, OPTION_EL
},
21390 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
21391 {NULL
, no_argument
, NULL
, 0}
21394 size_t md_longopts_size
= sizeof (md_longopts
);
21396 struct arm_option_table
21398 char *option
; /* Option name to match. */
21399 char *help
; /* Help information. */
21400 int *var
; /* Variable to change. */
21401 int value
; /* What to change it to. */
21402 char *deprecated
; /* If non-null, print this message. */
21405 struct arm_option_table arm_opts
[] =
21407 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
21408 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
21409 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
21410 &support_interwork
, 1, NULL
},
21411 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
21412 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
21413 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
21415 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
21416 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
21417 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
21418 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
21421 /* These are recognized by the assembler, but have no affect on code. */
21422 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
21423 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
21425 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
21426 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
21427 &warn_on_deprecated
, 0, NULL
},
21428 {NULL
, NULL
, NULL
, 0, NULL
}
21431 struct arm_legacy_option_table
21433 char *option
; /* Option name to match. */
21434 const arm_feature_set
**var
; /* Variable to change. */
21435 const arm_feature_set value
; /* What to change it to. */
21436 char *deprecated
; /* If non-null, print this message. */
21439 const struct arm_legacy_option_table arm_legacy_opts
[] =
21441 /* DON'T add any new processors to this list -- we want the whole list
21442 to go away... Add them to the processors table instead. */
21443 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21444 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21445 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21446 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21447 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21448 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21449 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21450 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21451 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21452 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21453 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21454 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21455 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21456 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21457 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21458 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21459 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21460 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21461 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21462 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21463 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21464 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21465 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21466 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21467 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21468 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21469 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21470 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21471 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21472 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21473 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21474 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21475 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21476 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21477 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21478 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21479 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21480 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21481 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21482 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21483 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21484 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21485 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21486 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21487 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21488 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21489 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21490 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21491 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21492 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21493 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21494 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21495 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21496 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21497 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21498 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21499 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21500 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21501 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21502 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21503 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21504 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21505 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21506 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21507 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21508 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21509 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21510 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21511 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
21512 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
21513 N_("use -mcpu=strongarm110")},
21514 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
21515 N_("use -mcpu=strongarm1100")},
21516 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
21517 N_("use -mcpu=strongarm1110")},
21518 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
21519 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
21520 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
21522 /* Architecture variants -- don't add any more to this list either. */
21523 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21524 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21525 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21526 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21527 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21528 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21529 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21530 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21531 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21532 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21533 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21534 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21535 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21536 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21537 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21538 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21539 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21540 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21542 /* Floating point variants -- don't add any more to this list either. */
21543 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
21544 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
21545 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
21546 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
21547 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
21549 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
21552 struct arm_cpu_option_table
21555 const arm_feature_set value
;
21556 /* For some CPUs we assume an FPU unless the user explicitly sets
21558 const arm_feature_set default_fpu
;
21559 /* The canonical name of the CPU, or NULL to use NAME converted to upper
21561 const char *canonical_name
;
21564 /* This list should, at a minimum, contain all the cpu names
21565 recognized by GCC. */
21566 static const struct arm_cpu_option_table arm_cpus
[] =
21568 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
21569 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
21570 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
21571 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21572 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21573 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21574 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21575 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21576 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21577 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21578 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21579 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21580 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21581 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21582 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21583 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21584 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21585 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21586 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21587 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21588 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21589 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21590 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21591 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21592 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21593 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21594 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21595 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21596 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21597 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21598 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21599 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21600 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21601 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21602 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21603 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21604 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21605 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21606 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21607 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
21608 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21609 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21610 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21611 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21612 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21613 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21614 /* For V5 or later processors we default to using VFP; but the user
21615 should really set the FPU type explicitly. */
21616 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21617 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21618 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
21619 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
21620 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
21621 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21622 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
21623 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21624 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21625 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
21626 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21627 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21628 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21629 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21630 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21631 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
21632 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21633 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21634 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21635 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
21636 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
21637 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
21638 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21639 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
21640 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
21641 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
21642 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
21643 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
21644 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
21645 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
21646 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
21647 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
21648 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
21649 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
21650 | FPU_NEON_EXT_V1
),
21652 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
21653 | FPU_NEON_EXT_V1
),
21655 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
21656 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
21657 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
21658 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
21659 /* ??? XSCALE is really an architecture. */
21660 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
21661 /* ??? iwmmxt is not a processor. */
21662 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
21663 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
21664 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
21666 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
21667 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
21670 struct arm_arch_option_table
21673 const arm_feature_set value
;
21674 const arm_feature_set default_fpu
;
21677 /* This list should, at a minimum, contain all the architecture names
21678 recognized by GCC. */
21679 static const struct arm_arch_option_table arm_archs
[] =
21681 {"all", ARM_ANY
, FPU_ARCH_FPA
},
21682 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
21683 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
21684 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
21685 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
21686 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
21687 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
21688 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
21689 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
21690 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
21691 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
21692 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
21693 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
21694 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
21695 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
21696 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
21697 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
21698 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
21699 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
21700 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
21701 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
21702 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
21703 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
21704 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
21705 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
21706 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
21707 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
21708 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
21709 /* The official spelling of the ARMv7 profile variants is the dashed form.
21710 Accept the non-dashed form for compatibility with old toolchains. */
21711 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
21712 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
21713 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
21714 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
21715 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
21716 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
21717 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
21718 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
21719 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
21720 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
21723 /* ISA extensions in the co-processor space. */
21724 struct arm_option_cpu_value_table
21727 const arm_feature_set value
;
21730 static const struct arm_option_cpu_value_table arm_extensions
[] =
21732 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
21733 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
21734 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
21735 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
21736 {NULL
, ARM_ARCH_NONE
}
21739 /* This list should, at a minimum, contain all the fpu names
21740 recognized by GCC. */
21741 static const struct arm_option_cpu_value_table arm_fpus
[] =
21743 {"softfpa", FPU_NONE
},
21744 {"fpe", FPU_ARCH_FPE
},
21745 {"fpe2", FPU_ARCH_FPE
},
21746 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
21747 {"fpa", FPU_ARCH_FPA
},
21748 {"fpa10", FPU_ARCH_FPA
},
21749 {"fpa11", FPU_ARCH_FPA
},
21750 {"arm7500fe", FPU_ARCH_FPA
},
21751 {"softvfp", FPU_ARCH_VFP
},
21752 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
21753 {"vfp", FPU_ARCH_VFP_V2
},
21754 {"vfp9", FPU_ARCH_VFP_V2
},
21755 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
21756 {"vfp10", FPU_ARCH_VFP_V2
},
21757 {"vfp10-r0", FPU_ARCH_VFP_V1
},
21758 {"vfpxd", FPU_ARCH_VFP_V1xD
},
21759 {"vfpv2", FPU_ARCH_VFP_V2
},
21760 {"vfpv3", FPU_ARCH_VFP_V3
},
21761 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
21762 {"arm1020t", FPU_ARCH_VFP_V1
},
21763 {"arm1020e", FPU_ARCH_VFP_V2
},
21764 {"arm1136jfs", FPU_ARCH_VFP_V2
},
21765 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
21766 {"maverick", FPU_ARCH_MAVERICK
},
21767 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
21768 {"neon-fp16", FPU_ARCH_NEON_FP16
},
21769 {NULL
, ARM_ARCH_NONE
}
21772 struct arm_option_value_table
21778 static const struct arm_option_value_table arm_float_abis
[] =
21780 {"hard", ARM_FLOAT_ABI_HARD
},
21781 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
21782 {"soft", ARM_FLOAT_ABI_SOFT
},
21787 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
21788 static const struct arm_option_value_table arm_eabis
[] =
21790 {"gnu", EF_ARM_EABI_UNKNOWN
},
21791 {"4", EF_ARM_EABI_VER4
},
21792 {"5", EF_ARM_EABI_VER5
},
21797 struct arm_long_option_table
21799 char * option
; /* Substring to match. */
21800 char * help
; /* Help information. */
21801 int (* func
) (char * subopt
); /* Function to decode sub-option. */
21802 char * deprecated
; /* If non-null, print this message. */
21806 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
21808 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
21810 /* Copy the feature set, so that we can modify it. */
21811 *ext_set
= **opt_p
;
21814 while (str
!= NULL
&& *str
!= 0)
21816 const struct arm_option_cpu_value_table
* opt
;
21822 as_bad (_("invalid architectural extension"));
21827 ext
= strchr (str
, '+');
21830 optlen
= ext
- str
;
21832 optlen
= strlen (str
);
21836 as_bad (_("missing architectural extension"));
21840 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
21841 if (strncmp (opt
->name
, str
, optlen
) == 0)
21843 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
21847 if (opt
->name
== NULL
)
21849 as_bad (_("unknown architectural extension `%s'"), str
);
21860 arm_parse_cpu (char * str
)
21862 const struct arm_cpu_option_table
* opt
;
21863 char * ext
= strchr (str
, '+');
21867 optlen
= ext
- str
;
21869 optlen
= strlen (str
);
21873 as_bad (_("missing cpu name `%s'"), str
);
21877 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
21878 if (strncmp (opt
->name
, str
, optlen
) == 0)
21880 mcpu_cpu_opt
= &opt
->value
;
21881 mcpu_fpu_opt
= &opt
->default_fpu
;
21882 if (opt
->canonical_name
)
21883 strcpy (selected_cpu_name
, opt
->canonical_name
);
21888 for (i
= 0; i
< optlen
; i
++)
21889 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
21890 selected_cpu_name
[i
] = 0;
21894 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
21899 as_bad (_("unknown cpu `%s'"), str
);
21904 arm_parse_arch (char * str
)
21906 const struct arm_arch_option_table
*opt
;
21907 char *ext
= strchr (str
, '+');
21911 optlen
= ext
- str
;
21913 optlen
= strlen (str
);
21917 as_bad (_("missing architecture name `%s'"), str
);
21921 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
21922 if (streq (opt
->name
, str
))
21924 march_cpu_opt
= &opt
->value
;
21925 march_fpu_opt
= &opt
->default_fpu
;
21926 strcpy (selected_cpu_name
, opt
->name
);
21929 return arm_parse_extension (ext
, &march_cpu_opt
);
21934 as_bad (_("unknown architecture `%s'\n"), str
);
21939 arm_parse_fpu (char * str
)
21941 const struct arm_option_cpu_value_table
* opt
;
21943 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
21944 if (streq (opt
->name
, str
))
21946 mfpu_opt
= &opt
->value
;
21950 as_bad (_("unknown floating point format `%s'\n"), str
);
21955 arm_parse_float_abi (char * str
)
21957 const struct arm_option_value_table
* opt
;
21959 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
21960 if (streq (opt
->name
, str
))
21962 mfloat_abi_opt
= opt
->value
;
21966 as_bad (_("unknown floating point abi `%s'\n"), str
);
21972 arm_parse_eabi (char * str
)
21974 const struct arm_option_value_table
*opt
;
21976 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
21977 if (streq (opt
->name
, str
))
21979 meabi_flags
= opt
->value
;
21982 as_bad (_("unknown EABI `%s'\n"), str
);
21988 arm_parse_it_mode (char * str
)
21990 bfd_boolean ret
= TRUE
;
21992 if (streq ("arm", str
))
21993 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
21994 else if (streq ("thumb", str
))
21995 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
21996 else if (streq ("always", str
))
21997 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
21998 else if (streq ("never", str
))
21999 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22002 as_bad (_("unknown implicit IT mode `%s', should be "\
22003 "arm, thumb, always, or never."), str
);
22010 struct arm_long_option_table arm_long_opts
[] =
22012 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22013 arm_parse_cpu
, NULL
},
22014 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22015 arm_parse_arch
, NULL
},
22016 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22017 arm_parse_fpu
, NULL
},
22018 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22019 arm_parse_float_abi
, NULL
},
22021 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22022 arm_parse_eabi
, NULL
},
22024 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22025 arm_parse_it_mode
, NULL
},
22026 {NULL
, NULL
, 0, NULL
}
22030 md_parse_option (int c
, char * arg
)
22032 struct arm_option_table
*opt
;
22033 const struct arm_legacy_option_table
*fopt
;
22034 struct arm_long_option_table
*lopt
;
22040 target_big_endian
= 1;
22046 target_big_endian
= 0;
22050 case OPTION_FIX_V4BX
:
22055 /* Listing option. Just ignore these, we don't support additional
22060 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22062 if (c
== opt
->option
[0]
22063 && ((arg
== NULL
&& opt
->option
[1] == 0)
22064 || streq (arg
, opt
->option
+ 1)))
22066 /* If the option is deprecated, tell the user. */
22067 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22068 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22069 arg
? arg
: "", _(opt
->deprecated
));
22071 if (opt
->var
!= NULL
)
22072 *opt
->var
= opt
->value
;
22078 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22080 if (c
== fopt
->option
[0]
22081 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22082 || streq (arg
, fopt
->option
+ 1)))
22084 /* If the option is deprecated, tell the user. */
22085 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22086 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22087 arg
? arg
: "", _(fopt
->deprecated
));
22089 if (fopt
->var
!= NULL
)
22090 *fopt
->var
= &fopt
->value
;
22096 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22098 /* These options are expected to have an argument. */
22099 if (c
== lopt
->option
[0]
22101 && strncmp (arg
, lopt
->option
+ 1,
22102 strlen (lopt
->option
+ 1)) == 0)
22104 /* If the option is deprecated, tell the user. */
22105 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22106 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22107 _(lopt
->deprecated
));
22109 /* Call the sup-option parser. */
22110 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22121 md_show_usage (FILE * fp
)
22123 struct arm_option_table
*opt
;
22124 struct arm_long_option_table
*lopt
;
22126 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22128 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22129 if (opt
->help
!= NULL
)
22130 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22132 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22133 if (lopt
->help
!= NULL
)
22134 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22138 -EB assemble code for a big-endian cpu\n"));
22143 -EL assemble code for a little-endian cpu\n"));
22147 --fix-v4bx Allow BX in ARMv4 code\n"));
22155 arm_feature_set flags
;
22156 } cpu_arch_ver_table
;
22158 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22159 least features first. */
22160 static const cpu_arch_ver_table cpu_arch_ver
[] =
22166 {4, ARM_ARCH_V5TE
},
22167 {5, ARM_ARCH_V5TEJ
},
22171 {11, ARM_ARCH_V6M
},
22172 {8, ARM_ARCH_V6T2
},
22173 {10, ARM_ARCH_V7A
},
22174 {10, ARM_ARCH_V7R
},
22175 {10, ARM_ARCH_V7M
},
22179 /* Set an attribute if it has not already been set by the user. */
22181 aeabi_set_attribute_int (int tag
, int value
)
22184 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22185 || !attributes_set_explicitly
[tag
])
22186 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22190 aeabi_set_attribute_string (int tag
, const char *value
)
22193 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22194 || !attributes_set_explicitly
[tag
])
22195 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22198 /* Set the public EABI object attributes. */
22200 aeabi_set_public_attributes (void)
22203 arm_feature_set flags
;
22204 arm_feature_set tmp
;
22205 const cpu_arch_ver_table
*p
;
22207 /* Choose the architecture based on the capabilities of the requested cpu
22208 (if any) and/or the instructions actually used. */
22209 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22210 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22211 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22212 /*Allow the user to override the reported architecture. */
22215 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22216 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22221 for (p
= cpu_arch_ver
; p
->val
; p
++)
22223 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22226 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22230 /* Tag_CPU_name. */
22231 if (selected_cpu_name
[0])
22235 p
= selected_cpu_name
;
22236 if (strncmp (p
, "armv", 4) == 0)
22241 for (i
= 0; p
[i
]; i
++)
22242 p
[i
] = TOUPPER (p
[i
]);
22244 aeabi_set_attribute_string (Tag_CPU_name
, p
);
22246 /* Tag_CPU_arch. */
22247 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22248 /* Tag_CPU_arch_profile. */
22249 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22250 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22251 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22252 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22253 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22254 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22255 /* Tag_ARM_ISA_use. */
22256 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22258 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22259 /* Tag_THUMB_ISA_use. */
22260 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22262 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22263 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22264 /* Tag_VFP_arch. */
22265 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22266 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22267 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3
))
22268 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22269 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22270 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22271 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22272 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22273 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22274 /* Tag_WMMX_arch. */
22275 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22276 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22277 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22278 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22279 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22280 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22281 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
22282 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
22283 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_fp16
))
22284 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
22287 /* Add the default contents for the .ARM.attributes section. */
22291 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22294 aeabi_set_public_attributes ();
22296 #endif /* OBJ_ELF */
22299 /* Parse a .cpu directive. */
22302 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
22304 const struct arm_cpu_option_table
*opt
;
22308 name
= input_line_pointer
;
22309 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22310 input_line_pointer
++;
22311 saved_char
= *input_line_pointer
;
22312 *input_line_pointer
= 0;
22314 /* Skip the first "all" entry. */
22315 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
22316 if (streq (opt
->name
, name
))
22318 mcpu_cpu_opt
= &opt
->value
;
22319 selected_cpu
= opt
->value
;
22320 if (opt
->canonical_name
)
22321 strcpy (selected_cpu_name
, opt
->canonical_name
);
22325 for (i
= 0; opt
->name
[i
]; i
++)
22326 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22327 selected_cpu_name
[i
] = 0;
22329 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22330 *input_line_pointer
= saved_char
;
22331 demand_empty_rest_of_line ();
22334 as_bad (_("unknown cpu `%s'"), name
);
22335 *input_line_pointer
= saved_char
;
22336 ignore_rest_of_line ();
22340 /* Parse a .arch directive. */
22343 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
22345 const struct arm_arch_option_table
*opt
;
22349 name
= input_line_pointer
;
22350 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22351 input_line_pointer
++;
22352 saved_char
= *input_line_pointer
;
22353 *input_line_pointer
= 0;
22355 /* Skip the first "all" entry. */
22356 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22357 if (streq (opt
->name
, name
))
22359 mcpu_cpu_opt
= &opt
->value
;
22360 selected_cpu
= opt
->value
;
22361 strcpy (selected_cpu_name
, opt
->name
);
22362 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22363 *input_line_pointer
= saved_char
;
22364 demand_empty_rest_of_line ();
22368 as_bad (_("unknown architecture `%s'\n"), name
);
22369 *input_line_pointer
= saved_char
;
22370 ignore_rest_of_line ();
22374 /* Parse a .object_arch directive. */
22377 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
22379 const struct arm_arch_option_table
*opt
;
22383 name
= input_line_pointer
;
22384 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22385 input_line_pointer
++;
22386 saved_char
= *input_line_pointer
;
22387 *input_line_pointer
= 0;
22389 /* Skip the first "all" entry. */
22390 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22391 if (streq (opt
->name
, name
))
22393 object_arch
= &opt
->value
;
22394 *input_line_pointer
= saved_char
;
22395 demand_empty_rest_of_line ();
22399 as_bad (_("unknown architecture `%s'\n"), name
);
22400 *input_line_pointer
= saved_char
;
22401 ignore_rest_of_line ();
22404 /* Parse a .fpu directive. */
22407 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
22409 const struct arm_option_cpu_value_table
*opt
;
22413 name
= input_line_pointer
;
22414 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22415 input_line_pointer
++;
22416 saved_char
= *input_line_pointer
;
22417 *input_line_pointer
= 0;
22419 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22420 if (streq (opt
->name
, name
))
22422 mfpu_opt
= &opt
->value
;
22423 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22424 *input_line_pointer
= saved_char
;
22425 demand_empty_rest_of_line ();
22429 as_bad (_("unknown floating point format `%s'\n"), name
);
22430 *input_line_pointer
= saved_char
;
22431 ignore_rest_of_line ();
22434 /* Copy symbol information. */
22437 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
22439 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
22443 /* Given a symbolic attribute NAME, return the proper integer value.
22444 Returns -1 if the attribute is not known. */
22447 arm_convert_symbolic_attribute (const char *name
)
22449 static const struct
22454 attribute_table
[] =
22456 /* When you modify this table you should
22457 also modify the list in doc/c-arm.texi. */
22458 #define T(tag) {#tag, tag}
22459 T (Tag_CPU_raw_name
),
22462 T (Tag_CPU_arch_profile
),
22463 T (Tag_ARM_ISA_use
),
22464 T (Tag_THUMB_ISA_use
),
22467 T (Tag_Advanced_SIMD_arch
),
22468 T (Tag_PCS_config
),
22469 T (Tag_ABI_PCS_R9_use
),
22470 T (Tag_ABI_PCS_RW_data
),
22471 T (Tag_ABI_PCS_RO_data
),
22472 T (Tag_ABI_PCS_GOT_use
),
22473 T (Tag_ABI_PCS_wchar_t
),
22474 T (Tag_ABI_FP_rounding
),
22475 T (Tag_ABI_FP_denormal
),
22476 T (Tag_ABI_FP_exceptions
),
22477 T (Tag_ABI_FP_user_exceptions
),
22478 T (Tag_ABI_FP_number_model
),
22479 T (Tag_ABI_align8_needed
),
22480 T (Tag_ABI_align8_preserved
),
22481 T (Tag_ABI_enum_size
),
22482 T (Tag_ABI_HardFP_use
),
22483 T (Tag_ABI_VFP_args
),
22484 T (Tag_ABI_WMMX_args
),
22485 T (Tag_ABI_optimization_goals
),
22486 T (Tag_ABI_FP_optimization_goals
),
22487 T (Tag_compatibility
),
22488 T (Tag_CPU_unaligned_access
),
22489 T (Tag_VFP_HP_extension
),
22490 T (Tag_ABI_FP_16bit_format
),
22491 T (Tag_nodefaults
),
22492 T (Tag_also_compatible_with
),
22493 T (Tag_conformance
),
22495 T (Tag_Virtualization_use
),
22496 T (Tag_MPextension_use
)
22504 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
22505 if (streq (name
, attribute_table
[i
].name
))
22506 return attribute_table
[i
].tag
;
22512 /* Apply sym value for relocations only in the case that
22513 they are for local symbols and you have the respective
22514 architectural feature for blx and simple switches. */
22516 arm_apply_sym_value (struct fix
* fixP
)
22519 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22520 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
22522 switch (fixP
->fx_r_type
)
22524 case BFD_RELOC_ARM_PCREL_BLX
:
22525 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22526 if (ARM_IS_FUNC (fixP
->fx_addsy
))
22530 case BFD_RELOC_ARM_PCREL_CALL
:
22531 case BFD_RELOC_THUMB_PCREL_BLX
:
22532 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
22543 #endif /* OBJ_ELF */