1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1012 /* Toggle value[pos]. */
1013 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1017 /* This array holds the chars that always start a comment. If the
1018 pre-processor is disabled, these aren't very useful. */
1019 char arm_comment_chars
[] = "@";
1021 /* This array holds the chars that only start a comment at the beginning of
1022 a line. If the line seems to have the form '# 123 filename'
1023 .line and .file directives will appear in the pre-processed output. */
1024 /* Note that input_file.c hand checks for '#' at the beginning of the
1025 first line of the input file. This is because the compiler outputs
1026 #NO_APP at the beginning of its output. */
1027 /* Also note that comments like this one will always work. */
1028 const char line_comment_chars
[] = "#";
1030 char arm_line_separator_chars
[] = ";";
1032 /* Chars that can be used to separate mant
1033 from exp in floating point numbers. */
1034 const char EXP_CHARS
[] = "eE";
1036 /* Chars that mean this number is a floating point constant. */
1037 /* As in 0f12.456 */
1038 /* or 0d1.2345e12 */
1040 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1042 /* Prefix characters that indicate the start of an immediate
1044 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1046 /* Separator character handling. */
1048 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1050 enum fp_16bit_format
1052 ARM_FP16_FORMAT_IEEE
= 0x1,
1053 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1054 ARM_FP16_FORMAT_DEFAULT
= 0x3
1057 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1061 skip_past_char (char ** str
, char c
)
1063 /* PR gas/14987: Allow for whitespace before the expected character. */
1064 skip_whitespace (*str
);
1075 #define skip_past_comma(str) skip_past_char (str, ',')
1077 /* Arithmetic expressions (possibly involving symbols). */
1079 /* Return TRUE if anything in the expression is a bignum. */
1082 walk_no_bignums (symbolS
* sp
)
1084 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1087 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1089 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1090 || (symbol_get_value_expression (sp
)->X_op_symbol
1091 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1097 static bfd_boolean in_my_get_expression
= FALSE
;
1099 /* Third argument to my_get_expression. */
1100 #define GE_NO_PREFIX 0
1101 #define GE_IMM_PREFIX 1
1102 #define GE_OPT_PREFIX 2
1103 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1104 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1105 #define GE_OPT_PREFIX_BIG 3
1108 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1112 /* In unified syntax, all prefixes are optional. */
1114 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1117 switch (prefix_mode
)
1119 case GE_NO_PREFIX
: break;
1121 if (!is_immediate_prefix (**str
))
1123 inst
.error
= _("immediate expression requires a # prefix");
1129 case GE_OPT_PREFIX_BIG
:
1130 if (is_immediate_prefix (**str
))
1137 memset (ep
, 0, sizeof (expressionS
));
1139 save_in
= input_line_pointer
;
1140 input_line_pointer
= *str
;
1141 in_my_get_expression
= TRUE
;
1143 in_my_get_expression
= FALSE
;
1145 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1147 /* We found a bad or missing expression in md_operand(). */
1148 *str
= input_line_pointer
;
1149 input_line_pointer
= save_in
;
1150 if (inst
.error
== NULL
)
1151 inst
.error
= (ep
->X_op
== O_absent
1152 ? _("missing expression") :_("bad expression"));
1156 /* Get rid of any bignums now, so that we don't generate an error for which
1157 we can't establish a line number later on. Big numbers are never valid
1158 in instructions, which is where this routine is always called. */
1159 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1160 && (ep
->X_op
== O_big
1161 || (ep
->X_add_symbol
1162 && (walk_no_bignums (ep
->X_add_symbol
)
1164 && walk_no_bignums (ep
->X_op_symbol
))))))
1166 inst
.error
= _("invalid constant");
1167 *str
= input_line_pointer
;
1168 input_line_pointer
= save_in
;
1172 *str
= input_line_pointer
;
1173 input_line_pointer
= save_in
;
1177 /* Turn a string in input_line_pointer into a floating point constant
1178 of type TYPE, and store the appropriate bytes in *LITP. The number
1179 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1180 returned, or NULL on OK.
1182 Note that fp constants aren't represent in the normal way on the ARM.
1183 In big endian mode, things are as expected. However, in little endian
1184 mode fp constants are big-endian word-wise, and little-endian byte-wise
1185 within the words. For example, (double) 1.1 in big endian mode is
1186 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1187 the byte sequence 99 99 f1 3f 9a 99 99 99.
1189 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1192 md_atof (int type
, char * litP
, int * sizeP
)
1195 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1232 return _("Unrecognized or unsupported floating point constant");
1235 t
= atof_ieee (input_line_pointer
, type
, words
);
1237 input_line_pointer
= t
;
1238 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1240 if (target_big_endian
|| prec
== 1)
1241 for (i
= 0; i
< prec
; i
++)
1243 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1244 litP
+= sizeof (LITTLENUM_TYPE
);
1246 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1247 for (i
= prec
- 1; i
>= 0; i
--)
1249 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1250 litP
+= sizeof (LITTLENUM_TYPE
);
1253 /* For a 4 byte float the order of elements in `words' is 1 0.
1254 For an 8 byte float the order is 1 0 3 2. */
1255 for (i
= 0; i
< prec
; i
+= 2)
1257 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1258 sizeof (LITTLENUM_TYPE
));
1259 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1260 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1261 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1267 /* We handle all bad expressions here, so that we can report the faulty
1268 instruction in the error message. */
1271 md_operand (expressionS
* exp
)
1273 if (in_my_get_expression
)
1274 exp
->X_op
= O_illegal
;
1277 /* Immediate values. */
1280 /* Generic immediate-value read function for use in directives.
1281 Accepts anything that 'expression' can fold to a constant.
1282 *val receives the number. */
1285 immediate_for_directive (int *val
)
1288 exp
.X_op
= O_illegal
;
1290 if (is_immediate_prefix (*input_line_pointer
))
1292 input_line_pointer
++;
1296 if (exp
.X_op
!= O_constant
)
1298 as_bad (_("expected #constant"));
1299 ignore_rest_of_line ();
1302 *val
= exp
.X_add_number
;
1307 /* Register parsing. */
1309 /* Generic register parser. CCP points to what should be the
1310 beginning of a register name. If it is indeed a valid register
1311 name, advance CCP over it and return the reg_entry structure;
1312 otherwise return NULL. Does not issue diagnostics. */
1314 static struct reg_entry
*
1315 arm_reg_parse_multi (char **ccp
)
1319 struct reg_entry
*reg
;
1321 skip_whitespace (start
);
1323 #ifdef REGISTER_PREFIX
1324 if (*start
!= REGISTER_PREFIX
)
1328 #ifdef OPTIONAL_REGISTER_PREFIX
1329 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1334 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1339 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1341 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1351 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1352 enum arm_reg_type type
)
1354 /* Alternative syntaxes are accepted for a few register classes. */
1361 /* Generic coprocessor register names are allowed for these. */
1362 if (reg
&& reg
->type
== REG_TYPE_CN
)
1367 /* For backward compatibility, a bare number is valid here. */
1369 unsigned long processor
= strtoul (start
, ccp
, 10);
1370 if (*ccp
!= start
&& processor
<= 15)
1375 case REG_TYPE_MMXWC
:
1376 /* WC includes WCG. ??? I'm not sure this is true for all
1377 instructions that take WC registers. */
1378 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1389 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1390 return value is the register number or FAIL. */
1393 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1396 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1399 /* Do not allow a scalar (reg+index) to parse as a register. */
1400 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1403 if (reg
&& reg
->type
== type
)
1406 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1413 /* Parse a Neon type specifier. *STR should point at the leading '.'
1414 character. Does no verification at this stage that the type fits the opcode
1421 Can all be legally parsed by this function.
1423 Fills in neon_type struct pointer with parsed information, and updates STR
1424 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1425 type, FAIL if not. */
1428 parse_neon_type (struct neon_type
*type
, char **str
)
1435 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1437 enum neon_el_type thistype
= NT_untyped
;
1438 unsigned thissize
= -1u;
1445 /* Just a size without an explicit type. */
1449 switch (TOLOWER (*ptr
))
1451 case 'i': thistype
= NT_integer
; break;
1452 case 'f': thistype
= NT_float
; break;
1453 case 'p': thistype
= NT_poly
; break;
1454 case 's': thistype
= NT_signed
; break;
1455 case 'u': thistype
= NT_unsigned
; break;
1457 thistype
= NT_float
;
1462 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1468 /* .f is an abbreviation for .f32. */
1469 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1474 thissize
= strtoul (ptr
, &ptr
, 10);
1476 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1479 as_bad (_("bad size %d in type specifier"), thissize
);
1487 type
->el
[type
->elems
].type
= thistype
;
1488 type
->el
[type
->elems
].size
= thissize
;
1493 /* Empty/missing type is not a successful parse. */
1494 if (type
->elems
== 0)
1502 /* Errors may be set multiple times during parsing or bit encoding
1503 (particularly in the Neon bits), but usually the earliest error which is set
1504 will be the most meaningful. Avoid overwriting it with later (cascading)
1505 errors by calling this function. */
1508 first_error (const char *err
)
1514 /* Parse a single type, e.g. ".s32", leading period included. */
1516 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1519 struct neon_type optype
;
1523 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1525 if (optype
.elems
== 1)
1526 *vectype
= optype
.el
[0];
1529 first_error (_("only one type should be specified for operand"));
1535 first_error (_("vector type expected"));
1547 /* Special meanings for indices (which have a range of 0-7), which will fit into
1550 #define NEON_ALL_LANES 15
1551 #define NEON_INTERLEAVE_LANES 14
1553 /* Record a use of the given feature. */
1555 record_feature_use (const arm_feature_set
*feature
)
1558 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1560 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1563 /* If the given feature available in the selected CPU, mark it as used.
1564 Returns TRUE iff feature is available. */
1566 mark_feature_used (const arm_feature_set
*feature
)
1569 /* Do not support the use of MVE only instructions when in auto-detection or
1571 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1572 && ARM_CPU_IS_ANY (cpu_variant
))
1574 first_error (BAD_MVE_AUTO
);
1577 /* Ensure the option is valid on the current architecture. */
1578 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1581 /* Add the appropriate architecture feature for the barrier option used.
1583 record_feature_use (feature
);
1588 /* Parse either a register or a scalar, with an optional type. Return the
1589 register number, and optionally fill in the actual type of the register
1590 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1591 type/index information in *TYPEINFO. */
1594 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1595 enum arm_reg_type
*rtype
,
1596 struct neon_typed_alias
*typeinfo
)
1599 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1600 struct neon_typed_alias atype
;
1601 struct neon_type_el parsetype
;
1605 atype
.eltype
.type
= NT_invtype
;
1606 atype
.eltype
.size
= -1;
1608 /* Try alternate syntax for some types of register. Note these are mutually
1609 exclusive with the Neon syntax extensions. */
1612 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1620 /* Undo polymorphism when a set of register types may be accepted. */
1621 if ((type
== REG_TYPE_NDQ
1622 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1623 || (type
== REG_TYPE_VFSD
1624 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1625 || (type
== REG_TYPE_NSDQ
1626 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1627 || reg
->type
== REG_TYPE_NQ
))
1628 || (type
== REG_TYPE_NSD
1629 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1630 || (type
== REG_TYPE_MMXWC
1631 && (reg
->type
== REG_TYPE_MMXWCG
)))
1632 type
= (enum arm_reg_type
) reg
->type
;
1634 if (type
== REG_TYPE_MQ
)
1636 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1639 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1642 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1644 first_error (_("expected MVE register [q0..q7]"));
1649 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1650 && (type
== REG_TYPE_NQ
))
1654 if (type
!= reg
->type
)
1660 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1662 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1664 first_error (_("can't redefine type for operand"));
1667 atype
.defined
|= NTA_HASTYPE
;
1668 atype
.eltype
= parsetype
;
1671 if (skip_past_char (&str
, '[') == SUCCESS
)
1673 if (type
!= REG_TYPE_VFD
1674 && !(type
== REG_TYPE_VFS
1675 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1676 && !(type
== REG_TYPE_NQ
1677 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1679 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1680 first_error (_("only D and Q registers may be indexed"));
1682 first_error (_("only D registers may be indexed"));
1686 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1688 first_error (_("can't change index for operand"));
1692 atype
.defined
|= NTA_HASINDEX
;
1694 if (skip_past_char (&str
, ']') == SUCCESS
)
1695 atype
.index
= NEON_ALL_LANES
;
1700 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1702 if (exp
.X_op
!= O_constant
)
1704 first_error (_("constant expression required"));
1708 if (skip_past_char (&str
, ']') == FAIL
)
1711 atype
.index
= exp
.X_add_number
;
1726 /* Like arm_reg_parse, but also allow the following extra features:
1727 - If RTYPE is non-zero, return the (possibly restricted) type of the
1728 register (e.g. Neon double or quad reg when either has been requested).
1729 - If this is a Neon vector type with additional type information, fill
1730 in the struct pointed to by VECTYPE (if non-NULL).
1731 This function will fault on encountering a scalar. */
1734 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1735 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1737 struct neon_typed_alias atype
;
1739 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1744 /* Do not allow regname(... to parse as a register. */
1748 /* Do not allow a scalar (reg+index) to parse as a register. */
1749 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1751 first_error (_("register operand expected, but got scalar"));
1756 *vectype
= atype
.eltype
;
1763 #define NEON_SCALAR_REG(X) ((X) >> 4)
1764 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1766 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1767 have enough information to be able to do a good job bounds-checking. So, we
1768 just do easy checks here, and do further checks later. */
1771 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1772 arm_reg_type reg_type
)
1776 struct neon_typed_alias atype
;
1779 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1797 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1800 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1802 first_error (_("scalar must have an index"));
1805 else if (atype
.index
>= reg_size
/ elsize
)
1807 first_error (_("scalar index out of range"));
1812 *type
= atype
.eltype
;
1816 return reg
* 16 + atype
.index
;
1819 /* Types of registers in a list. */
1832 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1835 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1841 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1843 /* We come back here if we get ranges concatenated by '+' or '|'. */
1846 skip_whitespace (str
);
1859 const char apsr_str
[] = "apsr";
1860 int apsr_str_len
= strlen (apsr_str
);
1862 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1863 if (etype
== REGLIST_CLRM
)
1865 if (reg
== REG_SP
|| reg
== REG_PC
)
1867 else if (reg
== FAIL
1868 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1869 && !ISALPHA (*(str
+ apsr_str_len
)))
1872 str
+= apsr_str_len
;
1877 first_error (_("r0-r12, lr or APSR expected"));
1881 else /* etype == REGLIST_RN. */
1885 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1896 first_error (_("bad range in register list"));
1900 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1902 if (range
& (1 << i
))
1904 (_("Warning: duplicated register (r%d) in register list"),
1912 if (range
& (1 << reg
))
1913 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1915 else if (reg
<= cur_reg
)
1916 as_tsktsk (_("Warning: register range not in ascending order"));
1921 while (skip_past_comma (&str
) != FAIL
1922 || (in_range
= 1, *str
++ == '-'));
1925 if (skip_past_char (&str
, '}') == FAIL
)
1927 first_error (_("missing `}'"));
1931 else if (etype
== REGLIST_RN
)
1935 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1938 if (exp
.X_op
== O_constant
)
1940 if (exp
.X_add_number
1941 != (exp
.X_add_number
& 0x0000ffff))
1943 inst
.error
= _("invalid register mask");
1947 if ((range
& exp
.X_add_number
) != 0)
1949 int regno
= range
& exp
.X_add_number
;
1952 regno
= (1 << regno
) - 1;
1954 (_("Warning: duplicated register (r%d) in register list"),
1958 range
|= exp
.X_add_number
;
1962 if (inst
.relocs
[0].type
!= 0)
1964 inst
.error
= _("expression too complex");
1968 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1969 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1970 inst
.relocs
[0].pc_rel
= 0;
1974 if (*str
== '|' || *str
== '+')
1980 while (another_range
);
1986 /* Parse a VFP register list. If the string is invalid return FAIL.
1987 Otherwise return the number of registers, and set PBASE to the first
1988 register. Parses registers of type ETYPE.
1989 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1990 - Q registers can be used to specify pairs of D registers
1991 - { } can be omitted from around a singleton register list
1992 FIXME: This is not implemented, as it would require backtracking in
1995 This could be done (the meaning isn't really ambiguous), but doesn't
1996 fit in well with the current parsing framework.
1997 - 32 D registers may be used (also true for VFPv3).
1998 FIXME: Types are ignored in these register lists, which is probably a
2002 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2003 bfd_boolean
*partial_match
)
2008 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2012 unsigned long mask
= 0;
2014 bfd_boolean vpr_seen
= FALSE
;
2015 bfd_boolean expect_vpr
=
2016 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2018 if (skip_past_char (&str
, '{') == FAIL
)
2020 inst
.error
= _("expecting {");
2027 case REGLIST_VFP_S_VPR
:
2028 regtype
= REG_TYPE_VFS
;
2033 case REGLIST_VFP_D_VPR
:
2034 regtype
= REG_TYPE_VFD
;
2037 case REGLIST_NEON_D
:
2038 regtype
= REG_TYPE_NDQ
;
2045 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2047 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2048 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2052 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2055 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2062 base_reg
= max_regs
;
2063 *partial_match
= FALSE
;
2067 int setmask
= 1, addregs
= 1;
2068 const char vpr_str
[] = "vpr";
2069 int vpr_str_len
= strlen (vpr_str
);
2071 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2075 if (new_base
== FAIL
2076 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2077 && !ISALPHA (*(str
+ vpr_str_len
))
2083 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2087 first_error (_("VPR expected last"));
2090 else if (new_base
== FAIL
)
2092 if (regtype
== REG_TYPE_VFS
)
2093 first_error (_("VFP single precision register or VPR "
2095 else /* regtype == REG_TYPE_VFD. */
2096 first_error (_("VFP/Neon double precision register or VPR "
2101 else if (new_base
== FAIL
)
2103 first_error (_(reg_expected_msgs
[regtype
]));
2107 *partial_match
= TRUE
;
2111 if (new_base
>= max_regs
)
2113 first_error (_("register out of range in list"));
2117 /* Note: a value of 2 * n is returned for the register Q<n>. */
2118 if (regtype
== REG_TYPE_NQ
)
2124 if (new_base
< base_reg
)
2125 base_reg
= new_base
;
2127 if (mask
& (setmask
<< new_base
))
2129 first_error (_("invalid register list"));
2133 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2135 as_tsktsk (_("register list not in ascending order"));
2139 mask
|= setmask
<< new_base
;
2142 if (*str
== '-') /* We have the start of a range expression */
2148 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2151 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2155 if (high_range
>= max_regs
)
2157 first_error (_("register out of range in list"));
2161 if (regtype
== REG_TYPE_NQ
)
2162 high_range
= high_range
+ 1;
2164 if (high_range
<= new_base
)
2166 inst
.error
= _("register range not in ascending order");
2170 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2172 if (mask
& (setmask
<< new_base
))
2174 inst
.error
= _("invalid register list");
2178 mask
|= setmask
<< new_base
;
2183 while (skip_past_comma (&str
) != FAIL
);
2187 /* Sanity check -- should have raised a parse error above. */
2188 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2193 if (expect_vpr
&& !vpr_seen
)
2195 first_error (_("VPR expected last"));
2199 /* Final test -- the registers must be consecutive. */
2201 for (i
= 0; i
< count
; i
++)
2203 if ((mask
& (1u << i
)) == 0)
2205 inst
.error
= _("non-contiguous register range");
2215 /* True if two alias types are the same. */
2218 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2226 if (a
->defined
!= b
->defined
)
2229 if ((a
->defined
& NTA_HASTYPE
) != 0
2230 && (a
->eltype
.type
!= b
->eltype
.type
2231 || a
->eltype
.size
!= b
->eltype
.size
))
2234 if ((a
->defined
& NTA_HASINDEX
) != 0
2235 && (a
->index
!= b
->index
))
2241 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2242 The base register is put in *PBASE.
2243 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2245 The register stride (minus one) is put in bit 4 of the return value.
2246 Bits [6:5] encode the list length (minus one).
2247 The type of the list elements is put in *ELTYPE, if non-NULL. */
2249 #define NEON_LANE(X) ((X) & 0xf)
2250 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2251 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2254 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2256 struct neon_type_el
*eltype
)
2263 int leading_brace
= 0;
2264 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2265 const char *const incr_error
= mve
? _("register stride must be 1") :
2266 _("register stride must be 1 or 2");
2267 const char *const type_error
= _("mismatched element/structure types in list");
2268 struct neon_typed_alias firsttype
;
2269 firsttype
.defined
= 0;
2270 firsttype
.eltype
.type
= NT_invtype
;
2271 firsttype
.eltype
.size
= -1;
2272 firsttype
.index
= -1;
2274 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2279 struct neon_typed_alias atype
;
2281 rtype
= REG_TYPE_MQ
;
2282 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2286 first_error (_(reg_expected_msgs
[rtype
]));
2293 if (rtype
== REG_TYPE_NQ
)
2299 else if (reg_incr
== -1)
2301 reg_incr
= getreg
- base_reg
;
2302 if (reg_incr
< 1 || reg_incr
> 2)
2304 first_error (_(incr_error
));
2308 else if (getreg
!= base_reg
+ reg_incr
* count
)
2310 first_error (_(incr_error
));
2314 if (! neon_alias_types_same (&atype
, &firsttype
))
2316 first_error (_(type_error
));
2320 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2324 struct neon_typed_alias htype
;
2325 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2327 lane
= NEON_INTERLEAVE_LANES
;
2328 else if (lane
!= NEON_INTERLEAVE_LANES
)
2330 first_error (_(type_error
));
2335 else if (reg_incr
!= 1)
2337 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2341 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2344 first_error (_(reg_expected_msgs
[rtype
]));
2347 if (! neon_alias_types_same (&htype
, &firsttype
))
2349 first_error (_(type_error
));
2352 count
+= hireg
+ dregs
- getreg
;
2356 /* If we're using Q registers, we can't use [] or [n] syntax. */
2357 if (rtype
== REG_TYPE_NQ
)
2363 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2367 else if (lane
!= atype
.index
)
2369 first_error (_(type_error
));
2373 else if (lane
== -1)
2374 lane
= NEON_INTERLEAVE_LANES
;
2375 else if (lane
!= NEON_INTERLEAVE_LANES
)
2377 first_error (_(type_error
));
2382 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2384 /* No lane set by [x]. We must be interleaving structures. */
2386 lane
= NEON_INTERLEAVE_LANES
;
2389 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2390 || (count
> 1 && reg_incr
== -1))
2392 first_error (_("error parsing element/structure list"));
2396 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2398 first_error (_("expected }"));
2406 *eltype
= firsttype
.eltype
;
2411 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2414 /* Parse an explicit relocation suffix on an expression. This is
2415 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2416 arm_reloc_hsh contains no entries, so this function can only
2417 succeed if there is no () after the word. Returns -1 on error,
2418 BFD_RELOC_UNUSED if there wasn't any suffix. */
2421 parse_reloc (char **str
)
2423 struct reloc_entry
*r
;
2427 return BFD_RELOC_UNUSED
;
2432 while (*q
&& *q
!= ')' && *q
!= ',')
2437 if ((r
= (struct reloc_entry
*)
2438 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2445 /* Directives: register aliases. */
2447 static struct reg_entry
*
2448 insert_reg_alias (char *str
, unsigned number
, int type
)
2450 struct reg_entry
*new_reg
;
2453 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2455 if (new_reg
->builtin
)
2456 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2458 /* Only warn about a redefinition if it's not defined as the
2460 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2461 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2466 name
= xstrdup (str
);
2467 new_reg
= XNEW (struct reg_entry
);
2469 new_reg
->name
= name
;
2470 new_reg
->number
= number
;
2471 new_reg
->type
= type
;
2472 new_reg
->builtin
= FALSE
;
2473 new_reg
->neon
= NULL
;
2475 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2482 insert_neon_reg_alias (char *str
, int number
, int type
,
2483 struct neon_typed_alias
*atype
)
2485 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2489 first_error (_("attempt to redefine typed alias"));
2495 reg
->neon
= XNEW (struct neon_typed_alias
);
2496 *reg
->neon
= *atype
;
2500 /* Look for the .req directive. This is of the form:
2502 new_register_name .req existing_register_name
2504 If we find one, or if it looks sufficiently like one that we want to
2505 handle any error here, return TRUE. Otherwise return FALSE. */
2508 create_register_alias (char * newname
, char *p
)
2510 struct reg_entry
*old
;
2511 char *oldname
, *nbuf
;
2514 /* The input scrubber ensures that whitespace after the mnemonic is
2515 collapsed to single spaces. */
2517 if (strncmp (oldname
, " .req ", 6) != 0)
2521 if (*oldname
== '\0')
2524 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2527 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2531 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2532 the desired alias name, and p points to its end. If not, then
2533 the desired alias name is in the global original_case_string. */
2534 #ifdef TC_CASE_SENSITIVE
2537 newname
= original_case_string
;
2538 nlen
= strlen (newname
);
2541 nbuf
= xmemdup0 (newname
, nlen
);
2543 /* Create aliases under the new name as stated; an all-lowercase
2544 version of the new name; and an all-uppercase version of the new
2546 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2548 for (p
= nbuf
; *p
; p
++)
2551 if (strncmp (nbuf
, newname
, nlen
))
2553 /* If this attempt to create an additional alias fails, do not bother
2554 trying to create the all-lower case alias. We will fail and issue
2555 a second, duplicate error message. This situation arises when the
2556 programmer does something like:
2559 The second .req creates the "Foo" alias but then fails to create
2560 the artificial FOO alias because it has already been created by the
2562 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2569 for (p
= nbuf
; *p
; p
++)
2572 if (strncmp (nbuf
, newname
, nlen
))
2573 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2580 /* Create a Neon typed/indexed register alias using directives, e.g.:
2585 These typed registers can be used instead of the types specified after the
2586 Neon mnemonic, so long as all operands given have types. Types can also be
2587 specified directly, e.g.:
2588 vadd d0.s32, d1.s32, d2.s32 */
2591 create_neon_reg_alias (char *newname
, char *p
)
2593 enum arm_reg_type basetype
;
2594 struct reg_entry
*basereg
;
2595 struct reg_entry mybasereg
;
2596 struct neon_type ntype
;
2597 struct neon_typed_alias typeinfo
;
2598 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2601 typeinfo
.defined
= 0;
2602 typeinfo
.eltype
.type
= NT_invtype
;
2603 typeinfo
.eltype
.size
= -1;
2604 typeinfo
.index
= -1;
2608 if (strncmp (p
, " .dn ", 5) == 0)
2609 basetype
= REG_TYPE_VFD
;
2610 else if (strncmp (p
, " .qn ", 5) == 0)
2611 basetype
= REG_TYPE_NQ
;
2620 basereg
= arm_reg_parse_multi (&p
);
2622 if (basereg
&& basereg
->type
!= basetype
)
2624 as_bad (_("bad type for register"));
2628 if (basereg
== NULL
)
2631 /* Try parsing as an integer. */
2632 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2633 if (exp
.X_op
!= O_constant
)
2635 as_bad (_("expression must be constant"));
2638 basereg
= &mybasereg
;
2639 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2645 typeinfo
= *basereg
->neon
;
2647 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2649 /* We got a type. */
2650 if (typeinfo
.defined
& NTA_HASTYPE
)
2652 as_bad (_("can't redefine the type of a register alias"));
2656 typeinfo
.defined
|= NTA_HASTYPE
;
2657 if (ntype
.elems
!= 1)
2659 as_bad (_("you must specify a single type only"));
2662 typeinfo
.eltype
= ntype
.el
[0];
2665 if (skip_past_char (&p
, '[') == SUCCESS
)
2668 /* We got a scalar index. */
2670 if (typeinfo
.defined
& NTA_HASINDEX
)
2672 as_bad (_("can't redefine the index of a scalar alias"));
2676 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2678 if (exp
.X_op
!= O_constant
)
2680 as_bad (_("scalar index must be constant"));
2684 typeinfo
.defined
|= NTA_HASINDEX
;
2685 typeinfo
.index
= exp
.X_add_number
;
2687 if (skip_past_char (&p
, ']') == FAIL
)
2689 as_bad (_("expecting ]"));
2694 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2695 the desired alias name, and p points to its end. If not, then
2696 the desired alias name is in the global original_case_string. */
2697 #ifdef TC_CASE_SENSITIVE
2698 namelen
= nameend
- newname
;
2700 newname
= original_case_string
;
2701 namelen
= strlen (newname
);
2704 namebuf
= xmemdup0 (newname
, namelen
);
2706 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2707 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2709 /* Insert name in all uppercase. */
2710 for (p
= namebuf
; *p
; p
++)
2713 if (strncmp (namebuf
, newname
, namelen
))
2714 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2715 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2717 /* Insert name in all lowercase. */
2718 for (p
= namebuf
; *p
; p
++)
2721 if (strncmp (namebuf
, newname
, namelen
))
2722 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2723 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2729 /* Should never be called, as .req goes between the alias and the
2730 register name, not at the beginning of the line. */
2733 s_req (int a ATTRIBUTE_UNUSED
)
2735 as_bad (_("invalid syntax for .req directive"));
2739 s_dn (int a ATTRIBUTE_UNUSED
)
2741 as_bad (_("invalid syntax for .dn directive"));
2745 s_qn (int a ATTRIBUTE_UNUSED
)
2747 as_bad (_("invalid syntax for .qn directive"));
2750 /* The .unreq directive deletes an alias which was previously defined
2751 by .req. For example:
2757 s_unreq (int a ATTRIBUTE_UNUSED
)
2762 name
= input_line_pointer
;
2764 while (*input_line_pointer
!= 0
2765 && *input_line_pointer
!= ' '
2766 && *input_line_pointer
!= '\n')
2767 ++input_line_pointer
;
2769 saved_char
= *input_line_pointer
;
2770 *input_line_pointer
= 0;
2773 as_bad (_("invalid syntax for .unreq directive"));
2776 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2780 as_bad (_("unknown register alias '%s'"), name
);
2781 else if (reg
->builtin
)
2782 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2789 hash_delete (arm_reg_hsh
, name
, FALSE
);
2790 free ((char *) reg
->name
);
2795 /* Also locate the all upper case and all lower case versions.
2796 Do not complain if we cannot find one or the other as it
2797 was probably deleted above. */
2799 nbuf
= strdup (name
);
2800 for (p
= nbuf
; *p
; p
++)
2802 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2805 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2806 free ((char *) reg
->name
);
2812 for (p
= nbuf
; *p
; p
++)
2814 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2817 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2818 free ((char *) reg
->name
);
2828 *input_line_pointer
= saved_char
;
2829 demand_empty_rest_of_line ();
2832 /* Directives: Instruction set selection. */
2835 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2836 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2837 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2838 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2840 /* Create a new mapping symbol for the transition to STATE. */
2843 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2846 const char * symname
;
2853 type
= BSF_NO_FLAGS
;
2857 type
= BSF_NO_FLAGS
;
2861 type
= BSF_NO_FLAGS
;
2867 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2868 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2873 THUMB_SET_FUNC (symbolP
, 0);
2874 ARM_SET_THUMB (symbolP
, 0);
2875 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2879 THUMB_SET_FUNC (symbolP
, 1);
2880 ARM_SET_THUMB (symbolP
, 1);
2881 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2889 /* Save the mapping symbols for future reference. Also check that
2890 we do not place two mapping symbols at the same offset within a
2891 frag. We'll handle overlap between frags in
2892 check_mapping_symbols.
2894 If .fill or other data filling directive generates zero sized data,
2895 the mapping symbol for the following code will have the same value
2896 as the one generated for the data filling directive. In this case,
2897 we replace the old symbol with the new one at the same address. */
2900 if (frag
->tc_frag_data
.first_map
!= NULL
)
2902 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2903 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2905 frag
->tc_frag_data
.first_map
= symbolP
;
2907 if (frag
->tc_frag_data
.last_map
!= NULL
)
2909 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2910 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2911 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2913 frag
->tc_frag_data
.last_map
= symbolP
;
2916 /* We must sometimes convert a region marked as code to data during
2917 code alignment, if an odd number of bytes have to be padded. The
2918 code mapping symbol is pushed to an aligned address. */
2921 insert_data_mapping_symbol (enum mstate state
,
2922 valueT value
, fragS
*frag
, offsetT bytes
)
2924 /* If there was already a mapping symbol, remove it. */
2925 if (frag
->tc_frag_data
.last_map
!= NULL
2926 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2928 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2932 know (frag
->tc_frag_data
.first_map
== symp
);
2933 frag
->tc_frag_data
.first_map
= NULL
;
2935 frag
->tc_frag_data
.last_map
= NULL
;
2936 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2939 make_mapping_symbol (MAP_DATA
, value
, frag
);
2940 make_mapping_symbol (state
, value
+ bytes
, frag
);
2943 static void mapping_state_2 (enum mstate state
, int max_chars
);
2945 /* Set the mapping state to STATE. Only call this when about to
2946 emit some STATE bytes to the file. */
2948 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2950 mapping_state (enum mstate state
)
2952 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2954 if (mapstate
== state
)
2955 /* The mapping symbol has already been emitted.
2956 There is nothing else to do. */
2959 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2961 All ARM instructions require 4-byte alignment.
2962 (Almost) all Thumb instructions require 2-byte alignment.
2964 When emitting instructions into any section, mark the section
2967 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2968 but themselves require 2-byte alignment; this applies to some
2969 PC- relative forms. However, these cases will involve implicit
2970 literal pool generation or an explicit .align >=2, both of
2971 which will cause the section to me marked with sufficient
2972 alignment. Thus, we don't handle those cases here. */
2973 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2975 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2976 /* This case will be evaluated later. */
2979 mapping_state_2 (state
, 0);
2982 /* Same as mapping_state, but MAX_CHARS bytes have already been
2983 allocated. Put the mapping symbol that far back. */
2986 mapping_state_2 (enum mstate state
, int max_chars
)
2988 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2990 if (!SEG_NORMAL (now_seg
))
2993 if (mapstate
== state
)
2994 /* The mapping symbol has already been emitted.
2995 There is nothing else to do. */
2998 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2999 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3001 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3002 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3005 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3008 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3009 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3013 #define mapping_state(x) ((void)0)
3014 #define mapping_state_2(x, y) ((void)0)
3017 /* Find the real, Thumb encoded start of a Thumb function. */
3021 find_real_start (symbolS
* symbolP
)
3024 const char * name
= S_GET_NAME (symbolP
);
3025 symbolS
* new_target
;
3027 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3028 #define STUB_NAME ".real_start_of"
3033 /* The compiler may generate BL instructions to local labels because
3034 it needs to perform a branch to a far away location. These labels
3035 do not have a corresponding ".real_start_of" label. We check
3036 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3037 the ".real_start_of" convention for nonlocal branches. */
3038 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3041 real_start
= concat (STUB_NAME
, name
, NULL
);
3042 new_target
= symbol_find (real_start
);
3045 if (new_target
== NULL
)
3047 as_warn (_("Failed to find real start of function: %s\n"), name
);
3048 new_target
= symbolP
;
3056 opcode_select (int width
)
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3064 as_bad (_("selected processor does not support THUMB opcodes"));
3067 /* No need to force the alignment, since we will have been
3068 coming from ARM mode, which is word-aligned. */
3069 record_alignment (now_seg
, 1);
3076 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3077 as_bad (_("selected processor does not support ARM opcodes"));
3082 frag_align (2, 0, 0);
3084 record_alignment (now_seg
, 1);
3089 as_bad (_("invalid instruction size selected (%d)"), width
);
3094 s_arm (int ignore ATTRIBUTE_UNUSED
)
3097 demand_empty_rest_of_line ();
3101 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3104 demand_empty_rest_of_line ();
3108 s_code (int unused ATTRIBUTE_UNUSED
)
3112 temp
= get_absolute_expression ();
3117 opcode_select (temp
);
3121 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3126 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3128 /* If we are not already in thumb mode go into it, EVEN if
3129 the target processor does not support thumb instructions.
3130 This is used by gcc/config/arm/lib1funcs.asm for example
3131 to compile interworking support functions even if the
3132 target processor should not support interworking. */
3136 record_alignment (now_seg
, 1);
3139 demand_empty_rest_of_line ();
3143 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3147 /* The following label is the name/address of the start of a Thumb function.
3148 We need to know this for the interworking support. */
3149 label_is_thumb_function_name
= TRUE
;
3152 /* Perform a .set directive, but also mark the alias as
3153 being a thumb function. */
3156 s_thumb_set (int equiv
)
3158 /* XXX the following is a duplicate of the code for s_set() in read.c
3159 We cannot just call that code as we need to get at the symbol that
3166 /* Especial apologies for the random logic:
3167 This just grew, and could be parsed much more simply!
3169 delim
= get_symbol_name (& name
);
3170 end_name
= input_line_pointer
;
3171 (void) restore_line_pointer (delim
);
3173 if (*input_line_pointer
!= ',')
3176 as_bad (_("expected comma after name \"%s\""), name
);
3178 ignore_rest_of_line ();
3182 input_line_pointer
++;
3185 if (name
[0] == '.' && name
[1] == '\0')
3187 /* XXX - this should not happen to .thumb_set. */
3191 if ((symbolP
= symbol_find (name
)) == NULL
3192 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3195 /* When doing symbol listings, play games with dummy fragments living
3196 outside the normal fragment chain to record the file and line info
3198 if (listing
& LISTING_SYMBOLS
)
3200 extern struct list_info_struct
* listing_tail
;
3201 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3203 memset (dummy_frag
, 0, sizeof (fragS
));
3204 dummy_frag
->fr_type
= rs_fill
;
3205 dummy_frag
->line
= listing_tail
;
3206 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3207 dummy_frag
->fr_symbol
= symbolP
;
3211 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3214 /* "set" symbols are local unless otherwise specified. */
3215 SF_SET_LOCAL (symbolP
);
3216 #endif /* OBJ_COFF */
3217 } /* Make a new symbol. */
3219 symbol_table_insert (symbolP
);
3224 && S_IS_DEFINED (symbolP
)
3225 && S_GET_SEGMENT (symbolP
) != reg_section
)
3226 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3228 pseudo_set (symbolP
);
3230 demand_empty_rest_of_line ();
3232 /* XXX Now we come to the Thumb specific bit of code. */
3234 THUMB_SET_FUNC (symbolP
, 1);
3235 ARM_SET_THUMB (symbolP
, 1);
3236 #if defined OBJ_ELF || defined OBJ_COFF
3237 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3241 /* Directives: Mode selection. */
3243 /* .syntax [unified|divided] - choose the new unified syntax
3244 (same for Arm and Thumb encoding, modulo slight differences in what
3245 can be represented) or the old divergent syntax for each mode. */
3247 s_syntax (int unused ATTRIBUTE_UNUSED
)
3251 delim
= get_symbol_name (& name
);
3253 if (!strcasecmp (name
, "unified"))
3254 unified_syntax
= TRUE
;
3255 else if (!strcasecmp (name
, "divided"))
3256 unified_syntax
= FALSE
;
3259 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3262 (void) restore_line_pointer (delim
);
3263 demand_empty_rest_of_line ();
3266 /* Directives: sectioning and alignment. */
3269 s_bss (int ignore ATTRIBUTE_UNUSED
)
3271 /* We don't support putting frags in the BSS segment, we fake it by
3272 marking in_bss, then looking at s_skip for clues. */
3273 subseg_set (bss_section
, 0);
3274 demand_empty_rest_of_line ();
3276 #ifdef md_elf_section_change_hook
3277 md_elf_section_change_hook ();
3282 s_even (int ignore ATTRIBUTE_UNUSED
)
3284 /* Never make frag if expect extra pass. */
3286 frag_align (1, 0, 0);
3288 record_alignment (now_seg
, 1);
3290 demand_empty_rest_of_line ();
3293 /* Directives: CodeComposer Studio. */
3295 /* .ref (for CodeComposer Studio syntax only). */
3297 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3299 if (codecomposer_syntax
)
3300 ignore_rest_of_line ();
3302 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3305 /* If name is not NULL, then it is used for marking the beginning of a
3306 function, whereas if it is NULL then it means the function end. */
3308 asmfunc_debug (const char * name
)
3310 static const char * last_name
= NULL
;
3314 gas_assert (last_name
== NULL
);
3317 if (debug_type
== DEBUG_STABS
)
3318 stabs_generate_asm_func (name
, name
);
3322 gas_assert (last_name
!= NULL
);
3324 if (debug_type
== DEBUG_STABS
)
3325 stabs_generate_asm_endfunc (last_name
, last_name
);
3332 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3334 if (codecomposer_syntax
)
3336 switch (asmfunc_state
)
3338 case OUTSIDE_ASMFUNC
:
3339 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3342 case WAITING_ASMFUNC_NAME
:
3343 as_bad (_(".asmfunc repeated."));
3346 case WAITING_ENDASMFUNC
:
3347 as_bad (_(".asmfunc without function."));
3350 demand_empty_rest_of_line ();
3353 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3357 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3359 if (codecomposer_syntax
)
3361 switch (asmfunc_state
)
3363 case OUTSIDE_ASMFUNC
:
3364 as_bad (_(".endasmfunc without a .asmfunc."));
3367 case WAITING_ASMFUNC_NAME
:
3368 as_bad (_(".endasmfunc without function."));
3371 case WAITING_ENDASMFUNC
:
3372 asmfunc_state
= OUTSIDE_ASMFUNC
;
3373 asmfunc_debug (NULL
);
3376 demand_empty_rest_of_line ();
3379 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3383 s_ccs_def (int name
)
3385 if (codecomposer_syntax
)
3388 as_bad (_(".def pseudo-op only available with -mccs flag."));
3391 /* Directives: Literal pools. */
3393 static literal_pool
*
3394 find_literal_pool (void)
3396 literal_pool
* pool
;
3398 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3400 if (pool
->section
== now_seg
3401 && pool
->sub_section
== now_subseg
)
3408 static literal_pool
*
3409 find_or_make_literal_pool (void)
3411 /* Next literal pool ID number. */
3412 static unsigned int latest_pool_num
= 1;
3413 literal_pool
* pool
;
3415 pool
= find_literal_pool ();
3419 /* Create a new pool. */
3420 pool
= XNEW (literal_pool
);
3424 pool
->next_free_entry
= 0;
3425 pool
->section
= now_seg
;
3426 pool
->sub_section
= now_subseg
;
3427 pool
->next
= list_of_pools
;
3428 pool
->symbol
= NULL
;
3429 pool
->alignment
= 2;
3431 /* Add it to the list. */
3432 list_of_pools
= pool
;
3435 /* New pools, and emptied pools, will have a NULL symbol. */
3436 if (pool
->symbol
== NULL
)
3438 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3439 (valueT
) 0, &zero_address_frag
);
3440 pool
->id
= latest_pool_num
++;
3447 /* Add the literal in the global 'inst'
3448 structure to the relevant literal pool. */
3451 add_to_lit_pool (unsigned int nbytes
)
3453 #define PADDING_SLOT 0x1
3454 #define LIT_ENTRY_SIZE_MASK 0xFF
3455 literal_pool
* pool
;
3456 unsigned int entry
, pool_size
= 0;
3457 bfd_boolean padding_slot_p
= FALSE
;
3463 imm1
= inst
.operands
[1].imm
;
3464 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3465 : inst
.relocs
[0].exp
.X_unsigned
? 0
3466 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3467 if (target_big_endian
)
3470 imm2
= inst
.operands
[1].imm
;
3474 pool
= find_or_make_literal_pool ();
3476 /* Check if this literal value is already in the pool. */
3477 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3481 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3482 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3483 && (pool
->literals
[entry
].X_add_number
3484 == inst
.relocs
[0].exp
.X_add_number
)
3485 && (pool
->literals
[entry
].X_md
== nbytes
)
3486 && (pool
->literals
[entry
].X_unsigned
3487 == inst
.relocs
[0].exp
.X_unsigned
))
3490 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3491 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3492 && (pool
->literals
[entry
].X_add_number
3493 == inst
.relocs
[0].exp
.X_add_number
)
3494 && (pool
->literals
[entry
].X_add_symbol
3495 == inst
.relocs
[0].exp
.X_add_symbol
)
3496 && (pool
->literals
[entry
].X_op_symbol
3497 == inst
.relocs
[0].exp
.X_op_symbol
)
3498 && (pool
->literals
[entry
].X_md
== nbytes
))
3501 else if ((nbytes
== 8)
3502 && !(pool_size
& 0x7)
3503 && ((entry
+ 1) != pool
->next_free_entry
)
3504 && (pool
->literals
[entry
].X_op
== O_constant
)
3505 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3506 && (pool
->literals
[entry
].X_unsigned
3507 == inst
.relocs
[0].exp
.X_unsigned
)
3508 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3509 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3510 && (pool
->literals
[entry
+ 1].X_unsigned
3511 == inst
.relocs
[0].exp
.X_unsigned
))
3514 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3515 if (padding_slot_p
&& (nbytes
== 4))
3521 /* Do we need to create a new entry? */
3522 if (entry
== pool
->next_free_entry
)
3524 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3526 inst
.error
= _("literal pool overflow");
3532 /* For 8-byte entries, we align to an 8-byte boundary,
3533 and split it into two 4-byte entries, because on 32-bit
3534 host, 8-byte constants are treated as big num, thus
3535 saved in "generic_bignum" which will be overwritten
3536 by later assignments.
3538 We also need to make sure there is enough space for
3541 We also check to make sure the literal operand is a
3543 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3544 || inst
.relocs
[0].exp
.X_op
== O_big
))
3546 inst
.error
= _("invalid type for literal pool");
3549 else if (pool_size
& 0x7)
3551 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3553 inst
.error
= _("literal pool overflow");
3557 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3558 pool
->literals
[entry
].X_op
= O_constant
;
3559 pool
->literals
[entry
].X_add_number
= 0;
3560 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3561 pool
->next_free_entry
+= 1;
3564 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3566 inst
.error
= _("literal pool overflow");
3570 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3571 pool
->literals
[entry
].X_op
= O_constant
;
3572 pool
->literals
[entry
].X_add_number
= imm1
;
3573 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3574 pool
->literals
[entry
++].X_md
= 4;
3575 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3576 pool
->literals
[entry
].X_op
= O_constant
;
3577 pool
->literals
[entry
].X_add_number
= imm2
;
3578 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3579 pool
->literals
[entry
].X_md
= 4;
3580 pool
->alignment
= 3;
3581 pool
->next_free_entry
+= 1;
3585 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3586 pool
->literals
[entry
].X_md
= 4;
3590 /* PR ld/12974: Record the location of the first source line to reference
3591 this entry in the literal pool. If it turns out during linking that the
3592 symbol does not exist we will be able to give an accurate line number for
3593 the (first use of the) missing reference. */
3594 if (debug_type
== DEBUG_DWARF2
)
3595 dwarf2_where (pool
->locs
+ entry
);
3597 pool
->next_free_entry
+= 1;
3599 else if (padding_slot_p
)
3601 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3602 pool
->literals
[entry
].X_md
= nbytes
;
3605 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3606 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3607 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3613 tc_start_label_without_colon (void)
3615 bfd_boolean ret
= TRUE
;
3617 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3619 const char *label
= input_line_pointer
;
3621 while (!is_end_of_line
[(int) label
[-1]])
3626 as_bad (_("Invalid label '%s'"), label
);
3630 asmfunc_debug (label
);
3632 asmfunc_state
= WAITING_ENDASMFUNC
;
3638 /* Can't use symbol_new here, so have to create a symbol and then at
3639 a later date assign it a value. That's what these functions do. */
3642 symbol_locate (symbolS
* symbolP
,
3643 const char * name
, /* It is copied, the caller can modify. */
3644 segT segment
, /* Segment identifier (SEG_<something>). */
3645 valueT valu
, /* Symbol value. */
3646 fragS
* frag
) /* Associated fragment. */
3649 char * preserved_copy_of_name
;
3651 name_length
= strlen (name
) + 1; /* +1 for \0. */
3652 obstack_grow (¬es
, name
, name_length
);
3653 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3655 #ifdef tc_canonicalize_symbol_name
3656 preserved_copy_of_name
=
3657 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3660 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3662 S_SET_SEGMENT (symbolP
, segment
);
3663 S_SET_VALUE (symbolP
, valu
);
3664 symbol_clear_list_pointers (symbolP
);
3666 symbol_set_frag (symbolP
, frag
);
3668 /* Link to end of symbol chain. */
3670 extern int symbol_table_frozen
;
3672 if (symbol_table_frozen
)
3676 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3678 obj_symbol_new_hook (symbolP
);
3680 #ifdef tc_symbol_new_hook
3681 tc_symbol_new_hook (symbolP
);
3685 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3686 #endif /* DEBUG_SYMS */
3690 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3693 literal_pool
* pool
;
3696 pool
= find_literal_pool ();
3698 || pool
->symbol
== NULL
3699 || pool
->next_free_entry
== 0)
3702 /* Align pool as you have word accesses.
3703 Only make a frag if we have to. */
3705 frag_align (pool
->alignment
, 0, 0);
3707 record_alignment (now_seg
, 2);
3710 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3711 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3713 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3715 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3716 (valueT
) frag_now_fix (), frag_now
);
3717 symbol_table_insert (pool
->symbol
);
3719 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3721 #if defined OBJ_COFF || defined OBJ_ELF
3722 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3725 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3728 if (debug_type
== DEBUG_DWARF2
)
3729 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3731 /* First output the expression in the instruction to the pool. */
3732 emit_expr (&(pool
->literals
[entry
]),
3733 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3736 /* Mark the pool as empty. */
3737 pool
->next_free_entry
= 0;
3738 pool
->symbol
= NULL
;
3742 /* Forward declarations for functions below, in the MD interface
3744 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3745 static valueT
create_unwind_entry (int);
3746 static void start_unwind_section (const segT
, int);
3747 static void add_unwind_opcode (valueT
, int);
3748 static void flush_pending_unwind (void);
3750 /* Directives: Data. */
3753 s_arm_elf_cons (int nbytes
)
3757 #ifdef md_flush_pending_output
3758 md_flush_pending_output ();
3761 if (is_it_end_of_statement ())
3763 demand_empty_rest_of_line ();
3767 #ifdef md_cons_align
3768 md_cons_align (nbytes
);
3771 mapping_state (MAP_DATA
);
3775 char *base
= input_line_pointer
;
3779 if (exp
.X_op
!= O_symbol
)
3780 emit_expr (&exp
, (unsigned int) nbytes
);
3783 char *before_reloc
= input_line_pointer
;
3784 reloc
= parse_reloc (&input_line_pointer
);
3787 as_bad (_("unrecognized relocation suffix"));
3788 ignore_rest_of_line ();
3791 else if (reloc
== BFD_RELOC_UNUSED
)
3792 emit_expr (&exp
, (unsigned int) nbytes
);
3795 reloc_howto_type
*howto
= (reloc_howto_type
*)
3796 bfd_reloc_type_lookup (stdoutput
,
3797 (bfd_reloc_code_real_type
) reloc
);
3798 int size
= bfd_get_reloc_size (howto
);
3800 if (reloc
== BFD_RELOC_ARM_PLT32
)
3802 as_bad (_("(plt) is only valid on branch targets"));
3803 reloc
= BFD_RELOC_UNUSED
;
3808 as_bad (ngettext ("%s relocations do not fit in %d byte",
3809 "%s relocations do not fit in %d bytes",
3811 howto
->name
, nbytes
);
3814 /* We've parsed an expression stopping at O_symbol.
3815 But there may be more expression left now that we
3816 have parsed the relocation marker. Parse it again.
3817 XXX Surely there is a cleaner way to do this. */
3818 char *p
= input_line_pointer
;
3820 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3822 memcpy (save_buf
, base
, input_line_pointer
- base
);
3823 memmove (base
+ (input_line_pointer
- before_reloc
),
3824 base
, before_reloc
- base
);
3826 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3828 memcpy (base
, save_buf
, p
- base
);
3830 offset
= nbytes
- size
;
3831 p
= frag_more (nbytes
);
3832 memset (p
, 0, nbytes
);
3833 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3834 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3840 while (*input_line_pointer
++ == ',');
3842 /* Put terminator back into stream. */
3843 input_line_pointer
--;
3844 demand_empty_rest_of_line ();
3847 /* Emit an expression containing a 32-bit thumb instruction.
3848 Implementation based on put_thumb32_insn. */
3851 emit_thumb32_expr (expressionS
* exp
)
3853 expressionS exp_high
= *exp
;
3855 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3856 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3857 exp
->X_add_number
&= 0xffff;
3858 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3861 /* Guess the instruction size based on the opcode. */
3864 thumb_insn_size (int opcode
)
3866 if ((unsigned int) opcode
< 0xe800u
)
3868 else if ((unsigned int) opcode
>= 0xe8000000u
)
3875 emit_insn (expressionS
*exp
, int nbytes
)
3879 if (exp
->X_op
== O_constant
)
3884 size
= thumb_insn_size (exp
->X_add_number
);
3888 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3890 as_bad (_(".inst.n operand too big. "\
3891 "Use .inst.w instead"));
3896 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3897 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3899 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3901 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3902 emit_thumb32_expr (exp
);
3904 emit_expr (exp
, (unsigned int) size
);
3906 it_fsm_post_encode ();
3910 as_bad (_("cannot determine Thumb instruction size. " \
3911 "Use .inst.n/.inst.w instead"));
3914 as_bad (_("constant expression required"));
3919 /* Like s_arm_elf_cons but do not use md_cons_align and
3920 set the mapping state to MAP_ARM/MAP_THUMB. */
3923 s_arm_elf_inst (int nbytes
)
3925 if (is_it_end_of_statement ())
3927 demand_empty_rest_of_line ();
3931 /* Calling mapping_state () here will not change ARM/THUMB,
3932 but will ensure not to be in DATA state. */
3935 mapping_state (MAP_THUMB
);
3940 as_bad (_("width suffixes are invalid in ARM mode"));
3941 ignore_rest_of_line ();
3947 mapping_state (MAP_ARM
);
3956 if (! emit_insn (& exp
, nbytes
))
3958 ignore_rest_of_line ();
3962 while (*input_line_pointer
++ == ',');
3964 /* Put terminator back into stream. */
3965 input_line_pointer
--;
3966 demand_empty_rest_of_line ();
3969 /* Parse a .rel31 directive. */
3972 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3979 if (*input_line_pointer
== '1')
3980 highbit
= 0x80000000;
3981 else if (*input_line_pointer
!= '0')
3982 as_bad (_("expected 0 or 1"));
3984 input_line_pointer
++;
3985 if (*input_line_pointer
!= ',')
3986 as_bad (_("missing comma"));
3987 input_line_pointer
++;
3989 #ifdef md_flush_pending_output
3990 md_flush_pending_output ();
3993 #ifdef md_cons_align
3997 mapping_state (MAP_DATA
);
4002 md_number_to_chars (p
, highbit
, 4);
4003 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4004 BFD_RELOC_ARM_PREL31
);
4006 demand_empty_rest_of_line ();
4009 /* Directives: AEABI stack-unwind tables. */
4011 /* Parse an unwind_fnstart directive. Simply records the current location. */
4014 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4016 demand_empty_rest_of_line ();
4017 if (unwind
.proc_start
)
4019 as_bad (_("duplicate .fnstart directive"));
4023 /* Mark the start of the function. */
4024 unwind
.proc_start
= expr_build_dot ();
4026 /* Reset the rest of the unwind info. */
4027 unwind
.opcode_count
= 0;
4028 unwind
.table_entry
= NULL
;
4029 unwind
.personality_routine
= NULL
;
4030 unwind
.personality_index
= -1;
4031 unwind
.frame_size
= 0;
4032 unwind
.fp_offset
= 0;
4033 unwind
.fp_reg
= REG_SP
;
4035 unwind
.sp_restored
= 0;
4039 /* Parse a handlerdata directive. Creates the exception handling table entry
4040 for the function. */
4043 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4045 demand_empty_rest_of_line ();
4046 if (!unwind
.proc_start
)
4047 as_bad (MISSING_FNSTART
);
4049 if (unwind
.table_entry
)
4050 as_bad (_("duplicate .handlerdata directive"));
4052 create_unwind_entry (1);
4055 /* Parse an unwind_fnend directive. Generates the index table entry. */
4058 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4063 unsigned int marked_pr_dependency
;
4065 demand_empty_rest_of_line ();
4067 if (!unwind
.proc_start
)
4069 as_bad (_(".fnend directive without .fnstart"));
4073 /* Add eh table entry. */
4074 if (unwind
.table_entry
== NULL
)
4075 val
= create_unwind_entry (0);
4079 /* Add index table entry. This is two words. */
4080 start_unwind_section (unwind
.saved_seg
, 1);
4081 frag_align (2, 0, 0);
4082 record_alignment (now_seg
, 2);
4084 ptr
= frag_more (8);
4086 where
= frag_now_fix () - 8;
4088 /* Self relative offset of the function start. */
4089 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4090 BFD_RELOC_ARM_PREL31
);
4092 /* Indicate dependency on EHABI-defined personality routines to the
4093 linker, if it hasn't been done already. */
4094 marked_pr_dependency
4095 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4096 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4097 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4099 static const char *const name
[] =
4101 "__aeabi_unwind_cpp_pr0",
4102 "__aeabi_unwind_cpp_pr1",
4103 "__aeabi_unwind_cpp_pr2"
4105 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4106 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4107 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4108 |= 1 << unwind
.personality_index
;
4112 /* Inline exception table entry. */
4113 md_number_to_chars (ptr
+ 4, val
, 4);
4115 /* Self relative offset of the table entry. */
4116 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4117 BFD_RELOC_ARM_PREL31
);
4119 /* Restore the original section. */
4120 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4122 unwind
.proc_start
= NULL
;
4126 /* Parse an unwind_cantunwind directive. */
4129 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4131 demand_empty_rest_of_line ();
4132 if (!unwind
.proc_start
)
4133 as_bad (MISSING_FNSTART
);
4135 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4136 as_bad (_("personality routine specified for cantunwind frame"));
4138 unwind
.personality_index
= -2;
4142 /* Parse a personalityindex directive. */
4145 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4149 if (!unwind
.proc_start
)
4150 as_bad (MISSING_FNSTART
);
4152 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4153 as_bad (_("duplicate .personalityindex directive"));
4157 if (exp
.X_op
!= O_constant
4158 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4160 as_bad (_("bad personality routine number"));
4161 ignore_rest_of_line ();
4165 unwind
.personality_index
= exp
.X_add_number
;
4167 demand_empty_rest_of_line ();
4171 /* Parse a personality directive. */
4174 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4178 if (!unwind
.proc_start
)
4179 as_bad (MISSING_FNSTART
);
4181 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4182 as_bad (_("duplicate .personality directive"));
4184 c
= get_symbol_name (& name
);
4185 p
= input_line_pointer
;
4187 ++ input_line_pointer
;
4188 unwind
.personality_routine
= symbol_find_or_make (name
);
4190 demand_empty_rest_of_line ();
4194 /* Parse a directive saving core registers. */
4197 s_arm_unwind_save_core (void)
4203 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4206 as_bad (_("expected register list"));
4207 ignore_rest_of_line ();
4211 demand_empty_rest_of_line ();
4213 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4214 into .unwind_save {..., sp...}. We aren't bothered about the value of
4215 ip because it is clobbered by calls. */
4216 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4217 && (range
& 0x3000) == 0x1000)
4219 unwind
.opcode_count
--;
4220 unwind
.sp_restored
= 0;
4221 range
= (range
| 0x2000) & ~0x1000;
4222 unwind
.pending_offset
= 0;
4228 /* See if we can use the short opcodes. These pop a block of up to 8
4229 registers starting with r4, plus maybe r14. */
4230 for (n
= 0; n
< 8; n
++)
4232 /* Break at the first non-saved register. */
4233 if ((range
& (1 << (n
+ 4))) == 0)
4236 /* See if there are any other bits set. */
4237 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4239 /* Use the long form. */
4240 op
= 0x8000 | ((range
>> 4) & 0xfff);
4241 add_unwind_opcode (op
, 2);
4245 /* Use the short form. */
4247 op
= 0xa8; /* Pop r14. */
4249 op
= 0xa0; /* Do not pop r14. */
4251 add_unwind_opcode (op
, 1);
4258 op
= 0xb100 | (range
& 0xf);
4259 add_unwind_opcode (op
, 2);
4262 /* Record the number of bytes pushed. */
4263 for (n
= 0; n
< 16; n
++)
4265 if (range
& (1 << n
))
4266 unwind
.frame_size
+= 4;
4271 /* Parse a directive saving FPA registers. */
4274 s_arm_unwind_save_fpa (int reg
)
4280 /* Get Number of registers to transfer. */
4281 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4284 exp
.X_op
= O_illegal
;
4286 if (exp
.X_op
!= O_constant
)
4288 as_bad (_("expected , <constant>"));
4289 ignore_rest_of_line ();
4293 num_regs
= exp
.X_add_number
;
4295 if (num_regs
< 1 || num_regs
> 4)
4297 as_bad (_("number of registers must be in the range [1:4]"));
4298 ignore_rest_of_line ();
4302 demand_empty_rest_of_line ();
4307 op
= 0xb4 | (num_regs
- 1);
4308 add_unwind_opcode (op
, 1);
4313 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4314 add_unwind_opcode (op
, 2);
4316 unwind
.frame_size
+= num_regs
* 12;
4320 /* Parse a directive saving VFP registers for ARMv6 and above. */
4323 s_arm_unwind_save_vfp_armv6 (void)
4328 int num_vfpv3_regs
= 0;
4329 int num_regs_below_16
;
4330 bfd_boolean partial_match
;
4332 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4336 as_bad (_("expected register list"));
4337 ignore_rest_of_line ();
4341 demand_empty_rest_of_line ();
4343 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4344 than FSTMX/FLDMX-style ones). */
4346 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4348 num_vfpv3_regs
= count
;
4349 else if (start
+ count
> 16)
4350 num_vfpv3_regs
= start
+ count
- 16;
4352 if (num_vfpv3_regs
> 0)
4354 int start_offset
= start
> 16 ? start
- 16 : 0;
4355 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4356 add_unwind_opcode (op
, 2);
4359 /* Generate opcode for registers numbered in the range 0 .. 15. */
4360 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4361 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4362 if (num_regs_below_16
> 0)
4364 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4365 add_unwind_opcode (op
, 2);
4368 unwind
.frame_size
+= count
* 8;
4372 /* Parse a directive saving VFP registers for pre-ARMv6. */
4375 s_arm_unwind_save_vfp (void)
4380 bfd_boolean partial_match
;
4382 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4386 as_bad (_("expected register list"));
4387 ignore_rest_of_line ();
4391 demand_empty_rest_of_line ();
4396 op
= 0xb8 | (count
- 1);
4397 add_unwind_opcode (op
, 1);
4402 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4403 add_unwind_opcode (op
, 2);
4405 unwind
.frame_size
+= count
* 8 + 4;
4409 /* Parse a directive saving iWMMXt data registers. */
4412 s_arm_unwind_save_mmxwr (void)
4420 if (*input_line_pointer
== '{')
4421 input_line_pointer
++;
4425 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4429 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4434 as_tsktsk (_("register list not in ascending order"));
4437 if (*input_line_pointer
== '-')
4439 input_line_pointer
++;
4440 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4443 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4446 else if (reg
>= hi_reg
)
4448 as_bad (_("bad register range"));
4451 for (; reg
< hi_reg
; reg
++)
4455 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4457 skip_past_char (&input_line_pointer
, '}');
4459 demand_empty_rest_of_line ();
4461 /* Generate any deferred opcodes because we're going to be looking at
4463 flush_pending_unwind ();
4465 for (i
= 0; i
< 16; i
++)
4467 if (mask
& (1 << i
))
4468 unwind
.frame_size
+= 8;
4471 /* Attempt to combine with a previous opcode. We do this because gcc
4472 likes to output separate unwind directives for a single block of
4474 if (unwind
.opcode_count
> 0)
4476 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4477 if ((i
& 0xf8) == 0xc0)
4480 /* Only merge if the blocks are contiguous. */
4483 if ((mask
& 0xfe00) == (1 << 9))
4485 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4486 unwind
.opcode_count
--;
4489 else if (i
== 6 && unwind
.opcode_count
>= 2)
4491 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4495 op
= 0xffff << (reg
- 1);
4497 && ((mask
& op
) == (1u << (reg
- 1))))
4499 op
= (1 << (reg
+ i
+ 1)) - 1;
4500 op
&= ~((1 << reg
) - 1);
4502 unwind
.opcode_count
-= 2;
4509 /* We want to generate opcodes in the order the registers have been
4510 saved, ie. descending order. */
4511 for (reg
= 15; reg
>= -1; reg
--)
4513 /* Save registers in blocks. */
4515 || !(mask
& (1 << reg
)))
4517 /* We found an unsaved reg. Generate opcodes to save the
4524 op
= 0xc0 | (hi_reg
- 10);
4525 add_unwind_opcode (op
, 1);
4530 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4531 add_unwind_opcode (op
, 2);
4540 ignore_rest_of_line ();
4544 s_arm_unwind_save_mmxwcg (void)
4551 if (*input_line_pointer
== '{')
4552 input_line_pointer
++;
4554 skip_whitespace (input_line_pointer
);
4558 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4562 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4568 as_tsktsk (_("register list not in ascending order"));
4571 if (*input_line_pointer
== '-')
4573 input_line_pointer
++;
4574 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4577 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4580 else if (reg
>= hi_reg
)
4582 as_bad (_("bad register range"));
4585 for (; reg
< hi_reg
; reg
++)
4589 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4591 skip_past_char (&input_line_pointer
, '}');
4593 demand_empty_rest_of_line ();
4595 /* Generate any deferred opcodes because we're going to be looking at
4597 flush_pending_unwind ();
4599 for (reg
= 0; reg
< 16; reg
++)
4601 if (mask
& (1 << reg
))
4602 unwind
.frame_size
+= 4;
4605 add_unwind_opcode (op
, 2);
4608 ignore_rest_of_line ();
4612 /* Parse an unwind_save directive.
4613 If the argument is non-zero, this is a .vsave directive. */
4616 s_arm_unwind_save (int arch_v6
)
4619 struct reg_entry
*reg
;
4620 bfd_boolean had_brace
= FALSE
;
4622 if (!unwind
.proc_start
)
4623 as_bad (MISSING_FNSTART
);
4625 /* Figure out what sort of save we have. */
4626 peek
= input_line_pointer
;
4634 reg
= arm_reg_parse_multi (&peek
);
4638 as_bad (_("register expected"));
4639 ignore_rest_of_line ();
4648 as_bad (_("FPA .unwind_save does not take a register list"));
4649 ignore_rest_of_line ();
4652 input_line_pointer
= peek
;
4653 s_arm_unwind_save_fpa (reg
->number
);
4657 s_arm_unwind_save_core ();
4662 s_arm_unwind_save_vfp_armv6 ();
4664 s_arm_unwind_save_vfp ();
4667 case REG_TYPE_MMXWR
:
4668 s_arm_unwind_save_mmxwr ();
4671 case REG_TYPE_MMXWCG
:
4672 s_arm_unwind_save_mmxwcg ();
4676 as_bad (_(".unwind_save does not support this kind of register"));
4677 ignore_rest_of_line ();
4682 /* Parse an unwind_movsp directive. */
4685 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4691 if (!unwind
.proc_start
)
4692 as_bad (MISSING_FNSTART
);
4694 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4697 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4698 ignore_rest_of_line ();
4702 /* Optional constant. */
4703 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4705 if (immediate_for_directive (&offset
) == FAIL
)
4711 demand_empty_rest_of_line ();
4713 if (reg
== REG_SP
|| reg
== REG_PC
)
4715 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4719 if (unwind
.fp_reg
!= REG_SP
)
4720 as_bad (_("unexpected .unwind_movsp directive"));
4722 /* Generate opcode to restore the value. */
4724 add_unwind_opcode (op
, 1);
4726 /* Record the information for later. */
4727 unwind
.fp_reg
= reg
;
4728 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4729 unwind
.sp_restored
= 1;
4732 /* Parse an unwind_pad directive. */
4735 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4739 if (!unwind
.proc_start
)
4740 as_bad (MISSING_FNSTART
);
4742 if (immediate_for_directive (&offset
) == FAIL
)
4747 as_bad (_("stack increment must be multiple of 4"));
4748 ignore_rest_of_line ();
4752 /* Don't generate any opcodes, just record the details for later. */
4753 unwind
.frame_size
+= offset
;
4754 unwind
.pending_offset
+= offset
;
4756 demand_empty_rest_of_line ();
4759 /* Parse an unwind_setfp directive. */
4762 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4768 if (!unwind
.proc_start
)
4769 as_bad (MISSING_FNSTART
);
4771 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4772 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4775 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4777 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4779 as_bad (_("expected <reg>, <reg>"));
4780 ignore_rest_of_line ();
4784 /* Optional constant. */
4785 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4787 if (immediate_for_directive (&offset
) == FAIL
)
4793 demand_empty_rest_of_line ();
4795 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4797 as_bad (_("register must be either sp or set by a previous"
4798 "unwind_movsp directive"));
4802 /* Don't generate any opcodes, just record the information for later. */
4803 unwind
.fp_reg
= fp_reg
;
4805 if (sp_reg
== REG_SP
)
4806 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4808 unwind
.fp_offset
-= offset
;
4811 /* Parse an unwind_raw directive. */
4814 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4817 /* This is an arbitrary limit. */
4818 unsigned char op
[16];
4821 if (!unwind
.proc_start
)
4822 as_bad (MISSING_FNSTART
);
4825 if (exp
.X_op
== O_constant
4826 && skip_past_comma (&input_line_pointer
) != FAIL
)
4828 unwind
.frame_size
+= exp
.X_add_number
;
4832 exp
.X_op
= O_illegal
;
4834 if (exp
.X_op
!= O_constant
)
4836 as_bad (_("expected <offset>, <opcode>"));
4837 ignore_rest_of_line ();
4843 /* Parse the opcode. */
4848 as_bad (_("unwind opcode too long"));
4849 ignore_rest_of_line ();
4851 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4853 as_bad (_("invalid unwind opcode"));
4854 ignore_rest_of_line ();
4857 op
[count
++] = exp
.X_add_number
;
4859 /* Parse the next byte. */
4860 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4866 /* Add the opcode bytes in reverse order. */
4868 add_unwind_opcode (op
[count
], 1);
4870 demand_empty_rest_of_line ();
4874 /* Parse a .eabi_attribute directive. */
4877 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4879 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4881 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4882 attributes_set_explicitly
[tag
] = 1;
4885 /* Emit a tls fix for the symbol. */
4888 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4892 #ifdef md_flush_pending_output
4893 md_flush_pending_output ();
4896 #ifdef md_cons_align
4900 /* Since we're just labelling the code, there's no need to define a
4903 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4904 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4905 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4906 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4908 #endif /* OBJ_ELF */
4910 static void s_arm_arch (int);
4911 static void s_arm_object_arch (int);
4912 static void s_arm_cpu (int);
4913 static void s_arm_fpu (int);
4914 static void s_arm_arch_extension (int);
4919 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4926 if (exp
.X_op
== O_symbol
)
4927 exp
.X_op
= O_secrel
;
4929 emit_expr (&exp
, 4);
4931 while (*input_line_pointer
++ == ',');
4933 input_line_pointer
--;
4934 demand_empty_rest_of_line ();
4939 arm_is_largest_exponent_ok (int precision
)
4941 /* precision == 1 ensures that this will only return
4942 true for 16 bit floats. */
4943 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
4947 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
4951 enum fp_16bit_format new_format
;
4953 new_format
= ARM_FP16_FORMAT_DEFAULT
;
4955 name
= input_line_pointer
;
4956 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
4957 input_line_pointer
++;
4959 saved_char
= *input_line_pointer
;
4960 *input_line_pointer
= 0;
4962 if (strcasecmp (name
, "ieee") == 0)
4963 new_format
= ARM_FP16_FORMAT_IEEE
;
4964 else if (strcasecmp (name
, "alternative") == 0)
4965 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
4968 as_bad (_("unrecognised float16 format \"%s\""), name
);
4972 /* Only set fp16_format if it is still the default (aka not already
4974 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
4975 fp16_format
= new_format
;
4978 if (new_format
!= fp16_format
)
4979 as_warn (_("float16 format cannot be set more than once, ignoring."));
4983 *input_line_pointer
= saved_char
;
4984 ignore_rest_of_line ();
4987 /* This table describes all the machine specific pseudo-ops the assembler
4988 has to support. The fields are:
4989 pseudo-op name without dot
4990 function to call to execute this pseudo-op
4991 Integer arg to pass to the function. */
4993 const pseudo_typeS md_pseudo_table
[] =
4995 /* Never called because '.req' does not start a line. */
4996 { "req", s_req
, 0 },
4997 /* Following two are likewise never called. */
5000 { "unreq", s_unreq
, 0 },
5001 { "bss", s_bss
, 0 },
5002 { "align", s_align_ptwo
, 2 },
5003 { "arm", s_arm
, 0 },
5004 { "thumb", s_thumb
, 0 },
5005 { "code", s_code
, 0 },
5006 { "force_thumb", s_force_thumb
, 0 },
5007 { "thumb_func", s_thumb_func
, 0 },
5008 { "thumb_set", s_thumb_set
, 0 },
5009 { "even", s_even
, 0 },
5010 { "ltorg", s_ltorg
, 0 },
5011 { "pool", s_ltorg
, 0 },
5012 { "syntax", s_syntax
, 0 },
5013 { "cpu", s_arm_cpu
, 0 },
5014 { "arch", s_arm_arch
, 0 },
5015 { "object_arch", s_arm_object_arch
, 0 },
5016 { "fpu", s_arm_fpu
, 0 },
5017 { "arch_extension", s_arm_arch_extension
, 0 },
5019 { "word", s_arm_elf_cons
, 4 },
5020 { "long", s_arm_elf_cons
, 4 },
5021 { "inst.n", s_arm_elf_inst
, 2 },
5022 { "inst.w", s_arm_elf_inst
, 4 },
5023 { "inst", s_arm_elf_inst
, 0 },
5024 { "rel31", s_arm_rel31
, 0 },
5025 { "fnstart", s_arm_unwind_fnstart
, 0 },
5026 { "fnend", s_arm_unwind_fnend
, 0 },
5027 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5028 { "personality", s_arm_unwind_personality
, 0 },
5029 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5030 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5031 { "save", s_arm_unwind_save
, 0 },
5032 { "vsave", s_arm_unwind_save
, 1 },
5033 { "movsp", s_arm_unwind_movsp
, 0 },
5034 { "pad", s_arm_unwind_pad
, 0 },
5035 { "setfp", s_arm_unwind_setfp
, 0 },
5036 { "unwind_raw", s_arm_unwind_raw
, 0 },
5037 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5038 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5042 /* These are used for dwarf. */
5046 /* These are used for dwarf2. */
5047 { "file", dwarf2_directive_file
, 0 },
5048 { "loc", dwarf2_directive_loc
, 0 },
5049 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5051 { "extend", float_cons
, 'x' },
5052 { "ldouble", float_cons
, 'x' },
5053 { "packed", float_cons
, 'p' },
5055 {"secrel32", pe_directive_secrel
, 0},
5058 /* These are for compatibility with CodeComposer Studio. */
5059 {"ref", s_ccs_ref
, 0},
5060 {"def", s_ccs_def
, 0},
5061 {"asmfunc", s_ccs_asmfunc
, 0},
5062 {"endasmfunc", s_ccs_endasmfunc
, 0},
5064 {"float16", float_cons
, 'h' },
5065 {"float16_format", set_fp16_format
, 0 },
5070 /* Parser functions used exclusively in instruction operands. */
5072 /* Generic immediate-value read function for use in insn parsing.
5073 STR points to the beginning of the immediate (the leading #);
5074 VAL receives the value; if the value is outside [MIN, MAX]
5075 issue an error. PREFIX_OPT is true if the immediate prefix is
5079 parse_immediate (char **str
, int *val
, int min
, int max
,
5080 bfd_boolean prefix_opt
)
5084 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5085 if (exp
.X_op
!= O_constant
)
5087 inst
.error
= _("constant expression required");
5091 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5093 inst
.error
= _("immediate value out of range");
5097 *val
= exp
.X_add_number
;
5101 /* Less-generic immediate-value read function with the possibility of loading a
5102 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5103 instructions. Puts the result directly in inst.operands[i]. */
5106 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5107 bfd_boolean allow_symbol_p
)
5110 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5113 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5115 if (exp_p
->X_op
== O_constant
)
5117 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5118 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5119 O_constant. We have to be careful not to break compilation for
5120 32-bit X_add_number, though. */
5121 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5123 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5124 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5126 inst
.operands
[i
].regisimm
= 1;
5129 else if (exp_p
->X_op
== O_big
5130 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5132 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5134 /* Bignums have their least significant bits in
5135 generic_bignum[0]. Make sure we put 32 bits in imm and
5136 32 bits in reg, in a (hopefully) portable way. */
5137 gas_assert (parts
!= 0);
5139 /* Make sure that the number is not too big.
5140 PR 11972: Bignums can now be sign-extended to the
5141 size of a .octa so check that the out of range bits
5142 are all zero or all one. */
5143 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5145 LITTLENUM_TYPE m
= -1;
5147 if (generic_bignum
[parts
* 2] != 0
5148 && generic_bignum
[parts
* 2] != m
)
5151 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5152 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5156 inst
.operands
[i
].imm
= 0;
5157 for (j
= 0; j
< parts
; j
++, idx
++)
5158 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5159 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5160 inst
.operands
[i
].reg
= 0;
5161 for (j
= 0; j
< parts
; j
++, idx
++)
5162 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5163 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5164 inst
.operands
[i
].regisimm
= 1;
5166 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5174 /* Returns the pseudo-register number of an FPA immediate constant,
5175 or FAIL if there isn't a valid constant here. */
5178 parse_fpa_immediate (char ** str
)
5180 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5186 /* First try and match exact strings, this is to guarantee
5187 that some formats will work even for cross assembly. */
5189 for (i
= 0; fp_const
[i
]; i
++)
5191 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5195 *str
+= strlen (fp_const
[i
]);
5196 if (is_end_of_line
[(unsigned char) **str
])
5202 /* Just because we didn't get a match doesn't mean that the constant
5203 isn't valid, just that it is in a format that we don't
5204 automatically recognize. Try parsing it with the standard
5205 expression routines. */
5207 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5209 /* Look for a raw floating point number. */
5210 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5211 && is_end_of_line
[(unsigned char) *save_in
])
5213 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5215 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5217 if (words
[j
] != fp_values
[i
][j
])
5221 if (j
== MAX_LITTLENUMS
)
5229 /* Try and parse a more complex expression, this will probably fail
5230 unless the code uses a floating point prefix (eg "0f"). */
5231 save_in
= input_line_pointer
;
5232 input_line_pointer
= *str
;
5233 if (expression (&exp
) == absolute_section
5234 && exp
.X_op
== O_big
5235 && exp
.X_add_number
< 0)
5237 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5239 #define X_PRECISION 5
5240 #define E_PRECISION 15L
5241 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5243 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5245 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5247 if (words
[j
] != fp_values
[i
][j
])
5251 if (j
== MAX_LITTLENUMS
)
5253 *str
= input_line_pointer
;
5254 input_line_pointer
= save_in
;
5261 *str
= input_line_pointer
;
5262 input_line_pointer
= save_in
;
5263 inst
.error
= _("invalid FPA immediate expression");
5267 /* Returns 1 if a number has "quarter-precision" float format
5268 0baBbbbbbc defgh000 00000000 00000000. */
5271 is_quarter_float (unsigned imm
)
5273 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5274 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5278 /* Detect the presence of a floating point or integer zero constant,
5282 parse_ifimm_zero (char **in
)
5286 if (!is_immediate_prefix (**in
))
5288 /* In unified syntax, all prefixes are optional. */
5289 if (!unified_syntax
)
5295 /* Accept #0x0 as a synonym for #0. */
5296 if (strncmp (*in
, "0x", 2) == 0)
5299 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5304 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5305 &generic_floating_point_number
);
5308 && generic_floating_point_number
.sign
== '+'
5309 && (generic_floating_point_number
.low
5310 > generic_floating_point_number
.leader
))
5316 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5317 0baBbbbbbc defgh000 00000000 00000000.
5318 The zero and minus-zero cases need special handling, since they can't be
5319 encoded in the "quarter-precision" float format, but can nonetheless be
5320 loaded as integer constants. */
5323 parse_qfloat_immediate (char **ccp
, int *immed
)
5327 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5328 int found_fpchar
= 0;
5330 skip_past_char (&str
, '#');
5332 /* We must not accidentally parse an integer as a floating-point number. Make
5333 sure that the value we parse is not an integer by checking for special
5334 characters '.' or 'e'.
5335 FIXME: This is a horrible hack, but doing better is tricky because type
5336 information isn't in a very usable state at parse time. */
5338 skip_whitespace (fpnum
);
5340 if (strncmp (fpnum
, "0x", 2) == 0)
5344 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5345 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5355 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5357 unsigned fpword
= 0;
5360 /* Our FP word must be 32 bits (single-precision FP). */
5361 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5363 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5367 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5380 /* Shift operands. */
5383 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5386 struct asm_shift_name
5389 enum shift_kind kind
;
5392 /* Third argument to parse_shift. */
5393 enum parse_shift_mode
5395 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5396 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5397 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5398 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5399 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5400 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5403 /* Parse a <shift> specifier on an ARM data processing instruction.
5404 This has three forms:
5406 (LSL|LSR|ASL|ASR|ROR) Rs
5407 (LSL|LSR|ASL|ASR|ROR) #imm
5410 Note that ASL is assimilated to LSL in the instruction encoding, and
5411 RRX to ROR #0 (which cannot be written as such). */
5414 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5416 const struct asm_shift_name
*shift_name
;
5417 enum shift_kind shift
;
5422 for (p
= *str
; ISALPHA (*p
); p
++)
5427 inst
.error
= _("shift expression expected");
5431 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5434 if (shift_name
== NULL
)
5436 inst
.error
= _("shift expression expected");
5440 shift
= shift_name
->kind
;
5444 case NO_SHIFT_RESTRICT
:
5445 case SHIFT_IMMEDIATE
:
5446 if (shift
== SHIFT_UXTW
)
5448 inst
.error
= _("'UXTW' not allowed here");
5453 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5454 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5456 inst
.error
= _("'LSL' or 'ASR' required");
5461 case SHIFT_LSL_IMMEDIATE
:
5462 if (shift
!= SHIFT_LSL
)
5464 inst
.error
= _("'LSL' required");
5469 case SHIFT_ASR_IMMEDIATE
:
5470 if (shift
!= SHIFT_ASR
)
5472 inst
.error
= _("'ASR' required");
5476 case SHIFT_UXTW_IMMEDIATE
:
5477 if (shift
!= SHIFT_UXTW
)
5479 inst
.error
= _("'UXTW' required");
5487 if (shift
!= SHIFT_RRX
)
5489 /* Whitespace can appear here if the next thing is a bare digit. */
5490 skip_whitespace (p
);
5492 if (mode
== NO_SHIFT_RESTRICT
5493 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5495 inst
.operands
[i
].imm
= reg
;
5496 inst
.operands
[i
].immisreg
= 1;
5498 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5501 inst
.operands
[i
].shift_kind
= shift
;
5502 inst
.operands
[i
].shifted
= 1;
5507 /* Parse a <shifter_operand> for an ARM data processing instruction:
5510 #<immediate>, <rotate>
5514 where <shift> is defined by parse_shift above, and <rotate> is a
5515 multiple of 2 between 0 and 30. Validation of immediate operands
5516 is deferred to md_apply_fix. */
5519 parse_shifter_operand (char **str
, int i
)
5524 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5526 inst
.operands
[i
].reg
= value
;
5527 inst
.operands
[i
].isreg
= 1;
5529 /* parse_shift will override this if appropriate */
5530 inst
.relocs
[0].exp
.X_op
= O_constant
;
5531 inst
.relocs
[0].exp
.X_add_number
= 0;
5533 if (skip_past_comma (str
) == FAIL
)
5536 /* Shift operation on register. */
5537 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5540 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5543 if (skip_past_comma (str
) == SUCCESS
)
5545 /* #x, y -- ie explicit rotation by Y. */
5546 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5549 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5551 inst
.error
= _("constant expression expected");
5555 value
= exp
.X_add_number
;
5556 if (value
< 0 || value
> 30 || value
% 2 != 0)
5558 inst
.error
= _("invalid rotation");
5561 if (inst
.relocs
[0].exp
.X_add_number
< 0
5562 || inst
.relocs
[0].exp
.X_add_number
> 255)
5564 inst
.error
= _("invalid constant");
5568 /* Encode as specified. */
5569 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5573 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5574 inst
.relocs
[0].pc_rel
= 0;
5578 /* Group relocation information. Each entry in the table contains the
5579 textual name of the relocation as may appear in assembler source
5580 and must end with a colon.
5581 Along with this textual name are the relocation codes to be used if
5582 the corresponding instruction is an ALU instruction (ADD or SUB only),
5583 an LDR, an LDRS, or an LDC. */
5585 struct group_reloc_table_entry
5596 /* Varieties of non-ALU group relocation. */
5604 static struct group_reloc_table_entry group_reloc_table
[] =
5605 { /* Program counter relative: */
5607 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5612 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5613 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5614 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5615 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5617 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5622 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5623 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5624 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5625 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5627 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5628 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5629 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5630 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5631 /* Section base relative */
5633 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5638 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5639 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5640 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5641 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5643 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5648 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5649 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5650 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5651 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5653 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5654 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5655 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5656 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5657 /* Absolute thumb alu relocations. */
5659 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5664 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5669 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5674 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5679 /* Given the address of a pointer pointing to the textual name of a group
5680 relocation as may appear in assembler source, attempt to find its details
5681 in group_reloc_table. The pointer will be updated to the character after
5682 the trailing colon. On failure, FAIL will be returned; SUCCESS
5683 otherwise. On success, *entry will be updated to point at the relevant
5684 group_reloc_table entry. */
5687 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5690 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5692 int length
= strlen (group_reloc_table
[i
].name
);
5694 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5695 && (*str
)[length
] == ':')
5697 *out
= &group_reloc_table
[i
];
5698 *str
+= (length
+ 1);
5706 /* Parse a <shifter_operand> for an ARM data processing instruction
5707 (as for parse_shifter_operand) where group relocations are allowed:
5710 #<immediate>, <rotate>
5711 #:<group_reloc>:<expression>
5715 where <group_reloc> is one of the strings defined in group_reloc_table.
5716 The hashes are optional.
5718 Everything else is as for parse_shifter_operand. */
5720 static parse_operand_result
5721 parse_shifter_operand_group_reloc (char **str
, int i
)
5723 /* Determine if we have the sequence of characters #: or just :
5724 coming next. If we do, then we check for a group relocation.
5725 If we don't, punt the whole lot to parse_shifter_operand. */
5727 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5728 || (*str
)[0] == ':')
5730 struct group_reloc_table_entry
*entry
;
5732 if ((*str
)[0] == '#')
5737 /* Try to parse a group relocation. Anything else is an error. */
5738 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5740 inst
.error
= _("unknown group relocation");
5741 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5744 /* We now have the group relocation table entry corresponding to
5745 the name in the assembler source. Next, we parse the expression. */
5746 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5747 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5749 /* Record the relocation type (always the ALU variant here). */
5750 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5751 gas_assert (inst
.relocs
[0].type
!= 0);
5753 return PARSE_OPERAND_SUCCESS
;
5756 return parse_shifter_operand (str
, i
) == SUCCESS
5757 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5759 /* Never reached. */
5762 /* Parse a Neon alignment expression. Information is written to
5763 inst.operands[i]. We assume the initial ':' has been skipped.
5765 align .imm = align << 8, .immisalign=1, .preind=0 */
5766 static parse_operand_result
5767 parse_neon_alignment (char **str
, int i
)
5772 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5774 if (exp
.X_op
!= O_constant
)
5776 inst
.error
= _("alignment must be constant");
5777 return PARSE_OPERAND_FAIL
;
5780 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5781 inst
.operands
[i
].immisalign
= 1;
5782 /* Alignments are not pre-indexes. */
5783 inst
.operands
[i
].preind
= 0;
5786 return PARSE_OPERAND_SUCCESS
;
5789 /* Parse all forms of an ARM address expression. Information is written
5790 to inst.operands[i] and/or inst.relocs[0].
5792 Preindexed addressing (.preind=1):
5794 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5795 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5796 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5797 .shift_kind=shift .relocs[0].exp=shift_imm
5799 These three may have a trailing ! which causes .writeback to be set also.
5801 Postindexed addressing (.postind=1, .writeback=1):
5803 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5804 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5805 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5806 .shift_kind=shift .relocs[0].exp=shift_imm
5808 Unindexed addressing (.preind=0, .postind=0):
5810 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5814 [Rn]{!} shorthand for [Rn,#0]{!}
5815 =immediate .isreg=0 .relocs[0].exp=immediate
5816 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5818 It is the caller's responsibility to check for addressing modes not
5819 supported by the instruction, and to set inst.relocs[0].type. */
5821 static parse_operand_result
5822 parse_address_main (char **str
, int i
, int group_relocations
,
5823 group_reloc_type group_type
)
5828 if (skip_past_char (&p
, '[') == FAIL
)
5830 if (skip_past_char (&p
, '=') == FAIL
)
5832 /* Bare address - translate to PC-relative offset. */
5833 inst
.relocs
[0].pc_rel
= 1;
5834 inst
.operands
[i
].reg
= REG_PC
;
5835 inst
.operands
[i
].isreg
= 1;
5836 inst
.operands
[i
].preind
= 1;
5838 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5839 return PARSE_OPERAND_FAIL
;
5841 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5842 /*allow_symbol_p=*/TRUE
))
5843 return PARSE_OPERAND_FAIL
;
5846 return PARSE_OPERAND_SUCCESS
;
5849 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5850 skip_whitespace (p
);
5852 if (group_type
== GROUP_MVE
)
5854 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5855 struct neon_type_el et
;
5856 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5858 inst
.operands
[i
].isquad
= 1;
5860 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5862 inst
.error
= BAD_ADDR_MODE
;
5863 return PARSE_OPERAND_FAIL
;
5866 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5868 if (group_type
== GROUP_MVE
)
5869 inst
.error
= BAD_ADDR_MODE
;
5871 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5872 return PARSE_OPERAND_FAIL
;
5874 inst
.operands
[i
].reg
= reg
;
5875 inst
.operands
[i
].isreg
= 1;
5877 if (skip_past_comma (&p
) == SUCCESS
)
5879 inst
.operands
[i
].preind
= 1;
5882 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5884 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5885 struct neon_type_el et
;
5886 if (group_type
== GROUP_MVE
5887 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5889 inst
.operands
[i
].immisreg
= 2;
5890 inst
.operands
[i
].imm
= reg
;
5892 if (skip_past_comma (&p
) == SUCCESS
)
5894 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5896 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5897 inst
.relocs
[0].exp
.X_add_number
= 0;
5900 return PARSE_OPERAND_FAIL
;
5903 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5905 inst
.operands
[i
].imm
= reg
;
5906 inst
.operands
[i
].immisreg
= 1;
5908 if (skip_past_comma (&p
) == SUCCESS
)
5909 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5910 return PARSE_OPERAND_FAIL
;
5912 else if (skip_past_char (&p
, ':') == SUCCESS
)
5914 /* FIXME: '@' should be used here, but it's filtered out by generic
5915 code before we get to see it here. This may be subject to
5917 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5919 if (result
!= PARSE_OPERAND_SUCCESS
)
5924 if (inst
.operands
[i
].negative
)
5926 inst
.operands
[i
].negative
= 0;
5930 if (group_relocations
5931 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5933 struct group_reloc_table_entry
*entry
;
5935 /* Skip over the #: or : sequence. */
5941 /* Try to parse a group relocation. Anything else is an
5943 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5945 inst
.error
= _("unknown group relocation");
5946 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5949 /* We now have the group relocation table entry corresponding to
5950 the name in the assembler source. Next, we parse the
5952 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5953 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5955 /* Record the relocation type. */
5960 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5965 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5970 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5977 if (inst
.relocs
[0].type
== 0)
5979 inst
.error
= _("this group relocation is not allowed on this instruction");
5980 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5987 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5988 return PARSE_OPERAND_FAIL
;
5989 /* If the offset is 0, find out if it's a +0 or -0. */
5990 if (inst
.relocs
[0].exp
.X_op
== O_constant
5991 && inst
.relocs
[0].exp
.X_add_number
== 0)
5993 skip_whitespace (q
);
5997 skip_whitespace (q
);
6000 inst
.operands
[i
].negative
= 1;
6005 else if (skip_past_char (&p
, ':') == SUCCESS
)
6007 /* FIXME: '@' should be used here, but it's filtered out by generic code
6008 before we get to see it here. This may be subject to change. */
6009 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6011 if (result
!= PARSE_OPERAND_SUCCESS
)
6015 if (skip_past_char (&p
, ']') == FAIL
)
6017 inst
.error
= _("']' expected");
6018 return PARSE_OPERAND_FAIL
;
6021 if (skip_past_char (&p
, '!') == SUCCESS
)
6022 inst
.operands
[i
].writeback
= 1;
6024 else if (skip_past_comma (&p
) == SUCCESS
)
6026 if (skip_past_char (&p
, '{') == SUCCESS
)
6028 /* [Rn], {expr} - unindexed, with option */
6029 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6030 0, 255, TRUE
) == FAIL
)
6031 return PARSE_OPERAND_FAIL
;
6033 if (skip_past_char (&p
, '}') == FAIL
)
6035 inst
.error
= _("'}' expected at end of 'option' field");
6036 return PARSE_OPERAND_FAIL
;
6038 if (inst
.operands
[i
].preind
)
6040 inst
.error
= _("cannot combine index with option");
6041 return PARSE_OPERAND_FAIL
;
6044 return PARSE_OPERAND_SUCCESS
;
6048 inst
.operands
[i
].postind
= 1;
6049 inst
.operands
[i
].writeback
= 1;
6051 if (inst
.operands
[i
].preind
)
6053 inst
.error
= _("cannot combine pre- and post-indexing");
6054 return PARSE_OPERAND_FAIL
;
6058 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6060 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6061 struct neon_type_el et
;
6062 if (group_type
== GROUP_MVE
6063 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6065 inst
.operands
[i
].immisreg
= 2;
6066 inst
.operands
[i
].imm
= reg
;
6068 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6070 /* We might be using the immediate for alignment already. If we
6071 are, OR the register number into the low-order bits. */
6072 if (inst
.operands
[i
].immisalign
)
6073 inst
.operands
[i
].imm
|= reg
;
6075 inst
.operands
[i
].imm
= reg
;
6076 inst
.operands
[i
].immisreg
= 1;
6078 if (skip_past_comma (&p
) == SUCCESS
)
6079 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6080 return PARSE_OPERAND_FAIL
;
6086 if (inst
.operands
[i
].negative
)
6088 inst
.operands
[i
].negative
= 0;
6091 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6092 return PARSE_OPERAND_FAIL
;
6093 /* If the offset is 0, find out if it's a +0 or -0. */
6094 if (inst
.relocs
[0].exp
.X_op
== O_constant
6095 && inst
.relocs
[0].exp
.X_add_number
== 0)
6097 skip_whitespace (q
);
6101 skip_whitespace (q
);
6104 inst
.operands
[i
].negative
= 1;
6110 /* If at this point neither .preind nor .postind is set, we have a
6111 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6112 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6114 inst
.operands
[i
].preind
= 1;
6115 inst
.relocs
[0].exp
.X_op
= O_constant
;
6116 inst
.relocs
[0].exp
.X_add_number
= 0;
6119 return PARSE_OPERAND_SUCCESS
;
6123 parse_address (char **str
, int i
)
6125 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6129 static parse_operand_result
6130 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6132 return parse_address_main (str
, i
, 1, type
);
6135 /* Parse an operand for a MOVW or MOVT instruction. */
6137 parse_half (char **str
)
6142 skip_past_char (&p
, '#');
6143 if (strncasecmp (p
, ":lower16:", 9) == 0)
6144 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6145 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6146 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6148 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6151 skip_whitespace (p
);
6154 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6157 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6159 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6161 inst
.error
= _("constant expression expected");
6164 if (inst
.relocs
[0].exp
.X_add_number
< 0
6165 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6167 inst
.error
= _("immediate value out of range");
6175 /* Miscellaneous. */
6177 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6178 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6180 parse_psr (char **str
, bfd_boolean lhs
)
6183 unsigned long psr_field
;
6184 const struct asm_psr
*psr
;
6186 bfd_boolean is_apsr
= FALSE
;
6187 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6189 /* PR gas/12698: If the user has specified -march=all then m_profile will
6190 be TRUE, but we want to ignore it in this case as we are building for any
6191 CPU type, including non-m variants. */
6192 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6195 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6196 feature for ease of use and backwards compatibility. */
6198 if (strncasecmp (p
, "SPSR", 4) == 0)
6201 goto unsupported_psr
;
6203 psr_field
= SPSR_BIT
;
6205 else if (strncasecmp (p
, "CPSR", 4) == 0)
6208 goto unsupported_psr
;
6212 else if (strncasecmp (p
, "APSR", 4) == 0)
6214 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6215 and ARMv7-R architecture CPUs. */
6224 while (ISALNUM (*p
) || *p
== '_');
6226 if (strncasecmp (start
, "iapsr", 5) == 0
6227 || strncasecmp (start
, "eapsr", 5) == 0
6228 || strncasecmp (start
, "xpsr", 4) == 0
6229 || strncasecmp (start
, "psr", 3) == 0)
6230 p
= start
+ strcspn (start
, "rR") + 1;
6232 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6238 /* If APSR is being written, a bitfield may be specified. Note that
6239 APSR itself is handled above. */
6240 if (psr
->field
<= 3)
6242 psr_field
= psr
->field
;
6248 /* M-profile MSR instructions have the mask field set to "10", except
6249 *PSR variants which modify APSR, which may use a different mask (and
6250 have been handled already). Do that by setting the PSR_f field
6252 return psr
->field
| (lhs
? PSR_f
: 0);
6255 goto unsupported_psr
;
6261 /* A suffix follows. */
6267 while (ISALNUM (*p
) || *p
== '_');
6271 /* APSR uses a notation for bits, rather than fields. */
6272 unsigned int nzcvq_bits
= 0;
6273 unsigned int g_bit
= 0;
6276 for (bit
= start
; bit
!= p
; bit
++)
6278 switch (TOLOWER (*bit
))
6281 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6285 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6289 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6293 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6297 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6301 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6305 inst
.error
= _("unexpected bit specified after APSR");
6310 if (nzcvq_bits
== 0x1f)
6315 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6317 inst
.error
= _("selected processor does not "
6318 "support DSP extension");
6325 if ((nzcvq_bits
& 0x20) != 0
6326 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6327 || (g_bit
& 0x2) != 0)
6329 inst
.error
= _("bad bitmask specified after APSR");
6335 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6340 psr_field
|= psr
->field
;
6346 goto error
; /* Garbage after "[CS]PSR". */
6348 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6349 is deprecated, but allow it anyway. */
6353 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6356 else if (!m_profile
)
6357 /* These bits are never right for M-profile devices: don't set them
6358 (only code paths which read/write APSR reach here). */
6359 psr_field
|= (PSR_c
| PSR_f
);
6365 inst
.error
= _("selected processor does not support requested special "
6366 "purpose register");
6370 inst
.error
= _("flag for {c}psr instruction expected");
6375 parse_sys_vldr_vstr (char **str
)
6384 {"FPSCR", 0x1, 0x0},
6385 {"FPSCR_nzcvqc", 0x2, 0x0},
6388 {"FPCXTNS", 0x6, 0x1},
6389 {"FPCXTS", 0x7, 0x1}
6391 char *op_end
= strchr (*str
, ',');
6392 size_t op_strlen
= op_end
- *str
;
6394 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6396 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6398 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6407 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6408 value suitable for splatting into the AIF field of the instruction. */
6411 parse_cps_flags (char **str
)
6420 case '\0': case ',':
6423 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6424 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6425 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6428 inst
.error
= _("unrecognized CPS flag");
6433 if (saw_a_flag
== 0)
6435 inst
.error
= _("missing CPS flags");
6443 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6444 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6447 parse_endian_specifier (char **str
)
6452 if (strncasecmp (s
, "BE", 2))
6454 else if (strncasecmp (s
, "LE", 2))
6458 inst
.error
= _("valid endian specifiers are be or le");
6462 if (ISALNUM (s
[2]) || s
[2] == '_')
6464 inst
.error
= _("valid endian specifiers are be or le");
6469 return little_endian
;
6472 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6473 value suitable for poking into the rotate field of an sxt or sxta
6474 instruction, or FAIL on error. */
6477 parse_ror (char **str
)
6482 if (strncasecmp (s
, "ROR", 3) == 0)
6486 inst
.error
= _("missing rotation field after comma");
6490 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6495 case 0: *str
= s
; return 0x0;
6496 case 8: *str
= s
; return 0x1;
6497 case 16: *str
= s
; return 0x2;
6498 case 24: *str
= s
; return 0x3;
6501 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6506 /* Parse a conditional code (from conds[] below). The value returned is in the
6507 range 0 .. 14, or FAIL. */
6509 parse_cond (char **str
)
6512 const struct asm_cond
*c
;
6514 /* Condition codes are always 2 characters, so matching up to
6515 3 characters is sufficient. */
6520 while (ISALPHA (*q
) && n
< 3)
6522 cond
[n
] = TOLOWER (*q
);
6527 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6530 inst
.error
= _("condition required");
6538 /* Parse an option for a barrier instruction. Returns the encoding for the
6541 parse_barrier (char **str
)
6544 const struct asm_barrier_opt
*o
;
6547 while (ISALPHA (*q
))
6550 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6555 if (!mark_feature_used (&o
->arch
))
6562 /* Parse the operands of a table branch instruction. Similar to a memory
6565 parse_tb (char **str
)
6570 if (skip_past_char (&p
, '[') == FAIL
)
6572 inst
.error
= _("'[' expected");
6576 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6578 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6581 inst
.operands
[0].reg
= reg
;
6583 if (skip_past_comma (&p
) == FAIL
)
6585 inst
.error
= _("',' expected");
6589 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6591 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6594 inst
.operands
[0].imm
= reg
;
6596 if (skip_past_comma (&p
) == SUCCESS
)
6598 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6600 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6602 inst
.error
= _("invalid shift");
6605 inst
.operands
[0].shifted
= 1;
6608 if (skip_past_char (&p
, ']') == FAIL
)
6610 inst
.error
= _("']' expected");
6617 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6618 information on the types the operands can take and how they are encoded.
6619 Up to four operands may be read; this function handles setting the
6620 ".present" field for each read operand itself.
6621 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6622 else returns FAIL. */
6625 parse_neon_mov (char **str
, int *which_operand
)
6627 int i
= *which_operand
, val
;
6628 enum arm_reg_type rtype
;
6630 struct neon_type_el optype
;
6632 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6634 /* Cases 17 or 19. */
6635 inst
.operands
[i
].reg
= val
;
6636 inst
.operands
[i
].isvec
= 1;
6637 inst
.operands
[i
].isscalar
= 2;
6638 inst
.operands
[i
].vectype
= optype
;
6639 inst
.operands
[i
++].present
= 1;
6641 if (skip_past_comma (&ptr
) == FAIL
)
6644 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6646 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6647 inst
.operands
[i
].reg
= val
;
6648 inst
.operands
[i
].isreg
= 1;
6649 inst
.operands
[i
].present
= 1;
6651 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6653 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6654 inst
.operands
[i
].reg
= val
;
6655 inst
.operands
[i
].isvec
= 1;
6656 inst
.operands
[i
].isscalar
= 2;
6657 inst
.operands
[i
].vectype
= optype
;
6658 inst
.operands
[i
++].present
= 1;
6660 if (skip_past_comma (&ptr
) == FAIL
)
6663 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6666 inst
.operands
[i
].reg
= val
;
6667 inst
.operands
[i
].isreg
= 1;
6668 inst
.operands
[i
++].present
= 1;
6670 if (skip_past_comma (&ptr
) == FAIL
)
6673 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6676 inst
.operands
[i
].reg
= val
;
6677 inst
.operands
[i
].isreg
= 1;
6678 inst
.operands
[i
].present
= 1;
6682 first_error (_("expected ARM or MVE vector register"));
6686 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6688 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6689 inst
.operands
[i
].reg
= val
;
6690 inst
.operands
[i
].isscalar
= 1;
6691 inst
.operands
[i
].vectype
= optype
;
6692 inst
.operands
[i
++].present
= 1;
6694 if (skip_past_comma (&ptr
) == FAIL
)
6697 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6700 inst
.operands
[i
].reg
= val
;
6701 inst
.operands
[i
].isreg
= 1;
6702 inst
.operands
[i
].present
= 1;
6704 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6706 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6709 /* Cases 0, 1, 2, 3, 5 (D only). */
6710 if (skip_past_comma (&ptr
) == FAIL
)
6713 inst
.operands
[i
].reg
= val
;
6714 inst
.operands
[i
].isreg
= 1;
6715 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6716 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6717 inst
.operands
[i
].isvec
= 1;
6718 inst
.operands
[i
].vectype
= optype
;
6719 inst
.operands
[i
++].present
= 1;
6721 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6723 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6724 Case 13: VMOV <Sd>, <Rm> */
6725 inst
.operands
[i
].reg
= val
;
6726 inst
.operands
[i
].isreg
= 1;
6727 inst
.operands
[i
].present
= 1;
6729 if (rtype
== REG_TYPE_NQ
)
6731 first_error (_("can't use Neon quad register here"));
6734 else if (rtype
!= REG_TYPE_VFS
)
6737 if (skip_past_comma (&ptr
) == FAIL
)
6739 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6741 inst
.operands
[i
].reg
= val
;
6742 inst
.operands
[i
].isreg
= 1;
6743 inst
.operands
[i
].present
= 1;
6746 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6748 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
,
6751 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6752 Case 1: VMOV<c><q> <Dd>, <Dm>
6753 Case 8: VMOV.F32 <Sd>, <Sm>
6754 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6756 inst
.operands
[i
].reg
= val
;
6757 inst
.operands
[i
].isreg
= 1;
6758 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6759 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6760 inst
.operands
[i
].isvec
= 1;
6761 inst
.operands
[i
].vectype
= optype
;
6762 inst
.operands
[i
].present
= 1;
6764 if (skip_past_comma (&ptr
) == SUCCESS
)
6769 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6772 inst
.operands
[i
].reg
= val
;
6773 inst
.operands
[i
].isreg
= 1;
6774 inst
.operands
[i
++].present
= 1;
6776 if (skip_past_comma (&ptr
) == FAIL
)
6779 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6782 inst
.operands
[i
].reg
= val
;
6783 inst
.operands
[i
].isreg
= 1;
6784 inst
.operands
[i
].present
= 1;
6787 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6788 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6789 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6790 Case 10: VMOV.F32 <Sd>, #<imm>
6791 Case 11: VMOV.F64 <Dd>, #<imm> */
6792 inst
.operands
[i
].immisfloat
= 1;
6793 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6795 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6796 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6800 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6804 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6806 /* Cases 6, 7, 16, 18. */
6807 inst
.operands
[i
].reg
= val
;
6808 inst
.operands
[i
].isreg
= 1;
6809 inst
.operands
[i
++].present
= 1;
6811 if (skip_past_comma (&ptr
) == FAIL
)
6814 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6816 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6817 inst
.operands
[i
].reg
= val
;
6818 inst
.operands
[i
].isscalar
= 2;
6819 inst
.operands
[i
].present
= 1;
6820 inst
.operands
[i
].vectype
= optype
;
6822 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6824 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6825 inst
.operands
[i
].reg
= val
;
6826 inst
.operands
[i
].isscalar
= 1;
6827 inst
.operands
[i
].present
= 1;
6828 inst
.operands
[i
].vectype
= optype
;
6830 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6832 inst
.operands
[i
].reg
= val
;
6833 inst
.operands
[i
].isreg
= 1;
6834 inst
.operands
[i
++].present
= 1;
6836 if (skip_past_comma (&ptr
) == FAIL
)
6839 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6842 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6844 inst
.operands
[i
].reg
= val
;
6845 inst
.operands
[i
].isreg
= 1;
6846 inst
.operands
[i
].isvec
= 1;
6847 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6848 inst
.operands
[i
].vectype
= optype
;
6849 inst
.operands
[i
].present
= 1;
6851 if (rtype
== REG_TYPE_VFS
)
6855 if (skip_past_comma (&ptr
) == FAIL
)
6857 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6860 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6863 inst
.operands
[i
].reg
= val
;
6864 inst
.operands
[i
].isreg
= 1;
6865 inst
.operands
[i
].isvec
= 1;
6866 inst
.operands
[i
].issingle
= 1;
6867 inst
.operands
[i
].vectype
= optype
;
6868 inst
.operands
[i
].present
= 1;
6873 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6876 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6877 inst
.operands
[i
].reg
= val
;
6878 inst
.operands
[i
].isvec
= 1;
6879 inst
.operands
[i
].isscalar
= 2;
6880 inst
.operands
[i
].vectype
= optype
;
6881 inst
.operands
[i
++].present
= 1;
6883 if (skip_past_comma (&ptr
) == FAIL
)
6886 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6889 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6892 inst
.operands
[i
].reg
= val
;
6893 inst
.operands
[i
].isvec
= 1;
6894 inst
.operands
[i
].isscalar
= 2;
6895 inst
.operands
[i
].vectype
= optype
;
6896 inst
.operands
[i
].present
= 1;
6900 first_error (_("VFP single, double or MVE vector register"
6906 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6910 inst
.operands
[i
].reg
= val
;
6911 inst
.operands
[i
].isreg
= 1;
6912 inst
.operands
[i
].isvec
= 1;
6913 inst
.operands
[i
].issingle
= 1;
6914 inst
.operands
[i
].vectype
= optype
;
6915 inst
.operands
[i
].present
= 1;
6920 first_error (_("parse error"));
6924 /* Successfully parsed the operands. Update args. */
6930 first_error (_("expected comma"));
6934 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6938 /* Use this macro when the operand constraints are different
6939 for ARM and THUMB (e.g. ldrd). */
6940 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6941 ((arm_operand) | ((thumb_operand) << 16))
6943 /* Matcher codes for parse_operands. */
6944 enum operand_parse_code
6946 OP_stop
, /* end of line */
6948 OP_RR
, /* ARM register */
6949 OP_RRnpc
, /* ARM register, not r15 */
6950 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6951 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6952 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6953 optional trailing ! */
6954 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6955 OP_RCP
, /* Coprocessor number */
6956 OP_RCN
, /* Coprocessor register */
6957 OP_RF
, /* FPA register */
6958 OP_RVS
, /* VFP single precision register */
6959 OP_RVD
, /* VFP double precision register (0..15) */
6960 OP_RND
, /* Neon double precision register (0..31) */
6961 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6962 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6964 OP_RNQ
, /* Neon quad precision register */
6965 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6966 OP_RVSD
, /* VFP single or double precision register */
6967 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6968 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6969 OP_RNSD
, /* Neon single or double precision register */
6970 OP_RNDQ
, /* Neon double or quad precision register */
6971 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6972 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
6973 OP_RNSDQ
, /* Neon single, double or quad precision register */
6974 OP_RNSC
, /* Neon scalar D[X] */
6975 OP_RVC
, /* VFP control register */
6976 OP_RMF
, /* Maverick F register */
6977 OP_RMD
, /* Maverick D register */
6978 OP_RMFX
, /* Maverick FX register */
6979 OP_RMDX
, /* Maverick DX register */
6980 OP_RMAX
, /* Maverick AX register */
6981 OP_RMDS
, /* Maverick DSPSC register */
6982 OP_RIWR
, /* iWMMXt wR register */
6983 OP_RIWC
, /* iWMMXt wC register */
6984 OP_RIWG
, /* iWMMXt wCG register */
6985 OP_RXA
, /* XScale accumulator register */
6987 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6989 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6991 OP_RMQ
, /* MVE vector register. */
6992 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6993 OP_RMQRR
, /* MVE vector or ARM register. */
6995 /* New operands for Armv8.1-M Mainline. */
6996 OP_LR
, /* ARM LR register */
6997 OP_RRe
, /* ARM register, only even numbered. */
6998 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6999 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7000 OP_RR_ZR
, /* ARM register or ZR but no PC */
7002 OP_REGLST
, /* ARM register list */
7003 OP_CLRMLST
, /* CLRM register list */
7004 OP_VRSLST
, /* VFP single-precision register list */
7005 OP_VRDLST
, /* VFP double-precision register list */
7006 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7007 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7008 OP_NSTRLST
, /* Neon element/structure list */
7009 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7010 OP_MSTRLST2
, /* MVE vector list with two elements. */
7011 OP_MSTRLST4
, /* MVE vector list with four elements. */
7013 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7014 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7015 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7016 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7018 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7019 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7020 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7021 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7023 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7024 scalar, or ARM register. */
7025 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7026 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7027 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7029 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7030 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7031 OP_VMOV
, /* Neon VMOV operands. */
7032 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7033 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7035 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7036 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7038 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7039 OP_VLDR
, /* VLDR operand. */
7041 OP_I0
, /* immediate zero */
7042 OP_I7
, /* immediate value 0 .. 7 */
7043 OP_I15
, /* 0 .. 15 */
7044 OP_I16
, /* 1 .. 16 */
7045 OP_I16z
, /* 0 .. 16 */
7046 OP_I31
, /* 0 .. 31 */
7047 OP_I31w
, /* 0 .. 31, optional trailing ! */
7048 OP_I32
, /* 1 .. 32 */
7049 OP_I32z
, /* 0 .. 32 */
7050 OP_I48_I64
, /* 48 or 64 */
7051 OP_I63
, /* 0 .. 63 */
7052 OP_I63s
, /* -64 .. 63 */
7053 OP_I64
, /* 1 .. 64 */
7054 OP_I64z
, /* 0 .. 64 */
7055 OP_I255
, /* 0 .. 255 */
7057 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7058 OP_I7b
, /* 0 .. 7 */
7059 OP_I15b
, /* 0 .. 15 */
7060 OP_I31b
, /* 0 .. 31 */
7062 OP_SH
, /* shifter operand */
7063 OP_SHG
, /* shifter operand with possible group relocation */
7064 OP_ADDR
, /* Memory address expression (any mode) */
7065 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7066 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7067 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7068 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7069 OP_EXP
, /* arbitrary expression */
7070 OP_EXPi
, /* same, with optional immediate prefix */
7071 OP_EXPr
, /* same, with optional relocation suffix */
7072 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7073 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7074 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7075 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7077 OP_CPSF
, /* CPS flags */
7078 OP_ENDI
, /* Endianness specifier */
7079 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7080 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7081 OP_COND
, /* conditional code */
7082 OP_TB
, /* Table branch. */
7084 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7086 OP_RRnpc_I0
, /* ARM register or literal 0 */
7087 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7088 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7089 OP_RF_IF
, /* FPA register or immediate */
7090 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7091 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7093 /* Optional operands. */
7094 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7095 OP_oI31b
, /* 0 .. 31 */
7096 OP_oI32b
, /* 1 .. 32 */
7097 OP_oI32z
, /* 0 .. 32 */
7098 OP_oIffffb
, /* 0 .. 65535 */
7099 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7101 OP_oRR
, /* ARM register */
7102 OP_oLR
, /* ARM LR register */
7103 OP_oRRnpc
, /* ARM register, not the PC */
7104 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7105 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7106 OP_oRND
, /* Optional Neon double precision register */
7107 OP_oRNQ
, /* Optional Neon quad precision register */
7108 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7109 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7110 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7111 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7113 OP_oSHll
, /* LSL immediate */
7114 OP_oSHar
, /* ASR immediate */
7115 OP_oSHllar
, /* LSL or ASR immediate */
7116 OP_oROR
, /* ROR 0/8/16/24 */
7117 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7119 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7121 /* Some pre-defined mixed (ARM/THUMB) operands. */
7122 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7123 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7124 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7126 OP_FIRST_OPTIONAL
= OP_oI7b
7129 /* Generic instruction operand parser. This does no encoding and no
7130 semantic validation; it merely squirrels values away in the inst
7131 structure. Returns SUCCESS or FAIL depending on whether the
7132 specified grammar matched. */
7134 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7136 unsigned const int *upat
= pattern
;
7137 char *backtrack_pos
= 0;
7138 const char *backtrack_error
= 0;
7139 int i
, val
= 0, backtrack_index
= 0;
7140 enum arm_reg_type rtype
;
7141 parse_operand_result result
;
7142 unsigned int op_parse_code
;
7143 bfd_boolean partial_match
;
7145 #define po_char_or_fail(chr) \
7148 if (skip_past_char (&str, chr) == FAIL) \
7153 #define po_reg_or_fail(regtype) \
7156 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7157 & inst.operands[i].vectype); \
7160 first_error (_(reg_expected_msgs[regtype])); \
7163 inst.operands[i].reg = val; \
7164 inst.operands[i].isreg = 1; \
7165 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7166 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7167 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7168 || rtype == REG_TYPE_VFD \
7169 || rtype == REG_TYPE_NQ); \
7170 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7174 #define po_reg_or_goto(regtype, label) \
7177 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7178 & inst.operands[i].vectype); \
7182 inst.operands[i].reg = val; \
7183 inst.operands[i].isreg = 1; \
7184 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7185 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7186 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7187 || rtype == REG_TYPE_VFD \
7188 || rtype == REG_TYPE_NQ); \
7189 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7193 #define po_imm_or_fail(min, max, popt) \
7196 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7198 inst.operands[i].imm = val; \
7202 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7206 my_get_expression (&exp, &str, popt); \
7207 if (exp.X_op != O_constant) \
7209 inst.error = _("constant expression required"); \
7212 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7214 inst.error = _("immediate value 48 or 64 expected"); \
7217 inst.operands[i].imm = exp.X_add_number; \
7221 #define po_scalar_or_goto(elsz, label, reg_type) \
7224 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7228 inst.operands[i].reg = val; \
7229 inst.operands[i].isscalar = 1; \
7233 #define po_misc_or_fail(expr) \
7241 #define po_misc_or_fail_no_backtrack(expr) \
7245 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7246 backtrack_pos = 0; \
7247 if (result != PARSE_OPERAND_SUCCESS) \
7252 #define po_barrier_or_imm(str) \
7255 val = parse_barrier (&str); \
7256 if (val == FAIL && ! ISALPHA (*str)) \
7259 /* ISB can only take SY as an option. */ \
7260 || ((inst.instruction & 0xf0) == 0x60 \
7263 inst.error = _("invalid barrier type"); \
7264 backtrack_pos = 0; \
7270 skip_whitespace (str
);
7272 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7274 op_parse_code
= upat
[i
];
7275 if (op_parse_code
>= 1<<16)
7276 op_parse_code
= thumb
? (op_parse_code
>> 16)
7277 : (op_parse_code
& ((1<<16)-1));
7279 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7281 /* Remember where we are in case we need to backtrack. */
7282 backtrack_pos
= str
;
7283 backtrack_error
= inst
.error
;
7284 backtrack_index
= i
;
7287 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7288 po_char_or_fail (',');
7290 switch (op_parse_code
)
7302 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7303 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7304 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7305 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7306 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7307 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7310 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7314 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7317 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7319 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7321 /* Also accept generic coprocessor regs for unknown registers. */
7323 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7325 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7326 existing register with a value of 0, this seems like the
7327 best way to parse P0. */
7329 if (strncasecmp (str
, "P0", 2) == 0)
7332 inst
.operands
[i
].isreg
= 1;
7333 inst
.operands
[i
].reg
= 13;
7338 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7339 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7340 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7341 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7342 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7343 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7344 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7345 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7346 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7347 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7350 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7353 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7354 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7356 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7361 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7365 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7367 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7370 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7372 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7375 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7377 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7382 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7385 po_reg_or_fail (REG_TYPE_NSDQ
);
7389 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7393 po_reg_or_fail (REG_TYPE_MQ
);
7395 /* Neon scalar. Using an element size of 8 means that some invalid
7396 scalars are accepted here, so deal with those in later code. */
7397 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7401 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7404 po_imm_or_fail (0, 0, TRUE
);
7409 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7413 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7418 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7421 if (parse_ifimm_zero (&str
))
7422 inst
.operands
[i
].imm
= 0;
7426 = _("only floating point zero is allowed as immediate value");
7434 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7437 po_reg_or_fail (REG_TYPE_RN
);
7441 case OP_RNSDQ_RNSC_MQ_RR
:
7442 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7445 case OP_RNSDQ_RNSC_MQ
:
7446 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7451 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7455 po_reg_or_fail (REG_TYPE_NSDQ
);
7462 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7465 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7468 po_reg_or_fail (REG_TYPE_NSD
);
7472 case OP_RNDQMQ_RNSC_RR
:
7473 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7476 case OP_RNDQ_RNSC_RR
:
7477 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7479 case OP_RNDQMQ_RNSC
:
7480 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7485 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7488 po_reg_or_fail (REG_TYPE_NDQ
);
7494 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7497 po_reg_or_fail (REG_TYPE_VFD
);
7502 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7503 not careful then bad things might happen. */
7504 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7507 case OP_RNDQMQ_Ibig
:
7508 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7513 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7516 /* There's a possibility of getting a 64-bit immediate here, so
7517 we need special handling. */
7518 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7521 inst
.error
= _("immediate value is out of range");
7527 case OP_RNDQMQ_I63b_RR
:
7528 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7531 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7536 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7539 po_imm_or_fail (0, 63, TRUE
);
7544 po_char_or_fail ('[');
7545 po_reg_or_fail (REG_TYPE_RN
);
7546 po_char_or_fail (']');
7552 po_reg_or_fail (REG_TYPE_RN
);
7553 if (skip_past_char (&str
, '!') == SUCCESS
)
7554 inst
.operands
[i
].writeback
= 1;
7558 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7559 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7560 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7561 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7562 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7563 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7564 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7565 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, FALSE
); break;
7566 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7567 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7568 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7569 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7570 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7572 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7574 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7575 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7577 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7578 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7579 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7580 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7582 /* Immediate variants */
7584 po_char_or_fail ('{');
7585 po_imm_or_fail (0, 255, TRUE
);
7586 po_char_or_fail ('}');
7590 /* The expression parser chokes on a trailing !, so we have
7591 to find it first and zap it. */
7594 while (*s
&& *s
!= ',')
7599 inst
.operands
[i
].writeback
= 1;
7601 po_imm_or_fail (0, 31, TRUE
);
7609 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7614 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7619 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7621 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7623 val
= parse_reloc (&str
);
7626 inst
.error
= _("unrecognized relocation suffix");
7629 else if (val
!= BFD_RELOC_UNUSED
)
7631 inst
.operands
[i
].imm
= val
;
7632 inst
.operands
[i
].hasreloc
= 1;
7638 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7640 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7642 inst
.operands
[i
].hasreloc
= 1;
7644 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7646 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7647 inst
.operands
[i
].hasreloc
= 0;
7651 /* Operand for MOVW or MOVT. */
7653 po_misc_or_fail (parse_half (&str
));
7656 /* Register or expression. */
7657 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7658 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7660 /* Register or immediate. */
7661 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7662 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7664 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7665 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7667 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7669 if (!is_immediate_prefix (*str
))
7672 val
= parse_fpa_immediate (&str
);
7675 /* FPA immediates are encoded as registers 8-15.
7676 parse_fpa_immediate has already applied the offset. */
7677 inst
.operands
[i
].reg
= val
;
7678 inst
.operands
[i
].isreg
= 1;
7681 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7682 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7684 /* Two kinds of register. */
7687 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7689 || (rege
->type
!= REG_TYPE_MMXWR
7690 && rege
->type
!= REG_TYPE_MMXWC
7691 && rege
->type
!= REG_TYPE_MMXWCG
))
7693 inst
.error
= _("iWMMXt data or control register expected");
7696 inst
.operands
[i
].reg
= rege
->number
;
7697 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7703 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7705 || (rege
->type
!= REG_TYPE_MMXWC
7706 && rege
->type
!= REG_TYPE_MMXWCG
))
7708 inst
.error
= _("iWMMXt control register expected");
7711 inst
.operands
[i
].reg
= rege
->number
;
7712 inst
.operands
[i
].isreg
= 1;
7717 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7718 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7719 case OP_oROR
: val
= parse_ror (&str
); break;
7721 case OP_COND
: val
= parse_cond (&str
); break;
7722 case OP_oBARRIER_I15
:
7723 po_barrier_or_imm (str
); break;
7725 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7731 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7732 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7734 inst
.error
= _("Banked registers are not available with this "
7740 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7744 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7747 val
= parse_sys_vldr_vstr (&str
);
7751 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7754 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7756 if (strncasecmp (str
, "APSR_", 5) == 0)
7763 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7764 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7765 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7766 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7767 default: found
= 16;
7771 inst
.operands
[i
].isvec
= 1;
7772 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7773 inst
.operands
[i
].reg
= REG_PC
;
7780 po_misc_or_fail (parse_tb (&str
));
7783 /* Register lists. */
7785 val
= parse_reg_list (&str
, REGLIST_RN
);
7788 inst
.operands
[i
].writeback
= 1;
7794 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7798 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7803 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7808 /* Allow Q registers too. */
7809 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7810 REGLIST_NEON_D
, &partial_match
);
7814 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7815 REGLIST_VFP_S
, &partial_match
);
7816 inst
.operands
[i
].issingle
= 1;
7821 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7822 REGLIST_VFP_D_VPR
, &partial_match
);
7823 if (val
== FAIL
&& !partial_match
)
7826 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7827 REGLIST_VFP_S_VPR
, &partial_match
);
7828 inst
.operands
[i
].issingle
= 1;
7833 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7834 REGLIST_NEON_D
, &partial_match
);
7839 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7840 1, &inst
.operands
[i
].vectype
);
7841 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7845 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7846 0, &inst
.operands
[i
].vectype
);
7849 /* Addressing modes */
7851 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7855 po_misc_or_fail (parse_address (&str
, i
));
7859 po_misc_or_fail_no_backtrack (
7860 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7864 po_misc_or_fail_no_backtrack (
7865 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7869 po_misc_or_fail_no_backtrack (
7870 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7874 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7878 po_misc_or_fail_no_backtrack (
7879 parse_shifter_operand_group_reloc (&str
, i
));
7883 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7887 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7891 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7896 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7901 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7904 po_reg_or_fail (REG_TYPE_ZR
);
7908 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7911 /* Various value-based sanity checks and shared operations. We
7912 do not signal immediate failures for the register constraints;
7913 this allows a syntax error to take precedence. */
7914 switch (op_parse_code
)
7922 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7923 inst
.error
= BAD_PC
;
7928 case OP_RRnpcsp_I32
:
7929 if (inst
.operands
[i
].isreg
)
7931 if (inst
.operands
[i
].reg
== REG_PC
)
7932 inst
.error
= BAD_PC
;
7933 else if (inst
.operands
[i
].reg
== REG_SP
7934 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7935 relaxed since ARMv8-A. */
7936 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7939 inst
.error
= BAD_SP
;
7945 if (inst
.operands
[i
].isreg
7946 && inst
.operands
[i
].reg
== REG_PC
7947 && (inst
.operands
[i
].writeback
|| thumb
))
7948 inst
.error
= BAD_PC
;
7953 if (inst
.operands
[i
].isreg
)
7963 case OP_oBARRIER_I15
:
7976 inst
.operands
[i
].imm
= val
;
7981 if (inst
.operands
[i
].reg
!= REG_LR
)
7982 inst
.error
= _("operand must be LR register");
7988 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7989 inst
.error
= BAD_PC
;
7993 if (inst
.operands
[i
].isreg
7994 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7995 inst
.error
= BAD_ODD
;
7999 if (inst
.operands
[i
].isreg
)
8001 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8002 inst
.error
= BAD_EVEN
;
8003 else if (inst
.operands
[i
].reg
== REG_SP
)
8004 as_tsktsk (MVE_BAD_SP
);
8005 else if (inst
.operands
[i
].reg
== REG_PC
)
8006 inst
.error
= BAD_PC
;
8014 /* If we get here, this operand was successfully parsed. */
8015 inst
.operands
[i
].present
= 1;
8019 inst
.error
= BAD_ARGS
;
8024 /* The parse routine should already have set inst.error, but set a
8025 default here just in case. */
8027 inst
.error
= BAD_SYNTAX
;
8031 /* Do not backtrack over a trailing optional argument that
8032 absorbed some text. We will only fail again, with the
8033 'garbage following instruction' error message, which is
8034 probably less helpful than the current one. */
8035 if (backtrack_index
== i
&& backtrack_pos
!= str
8036 && upat
[i
+1] == OP_stop
)
8039 inst
.error
= BAD_SYNTAX
;
8043 /* Try again, skipping the optional argument at backtrack_pos. */
8044 str
= backtrack_pos
;
8045 inst
.error
= backtrack_error
;
8046 inst
.operands
[backtrack_index
].present
= 0;
8047 i
= backtrack_index
;
8051 /* Check that we have parsed all the arguments. */
8052 if (*str
!= '\0' && !inst
.error
)
8053 inst
.error
= _("garbage following instruction");
8055 return inst
.error
? FAIL
: SUCCESS
;
8058 #undef po_char_or_fail
8059 #undef po_reg_or_fail
8060 #undef po_reg_or_goto
8061 #undef po_imm_or_fail
8062 #undef po_scalar_or_fail
8063 #undef po_barrier_or_imm
8065 /* Shorthand macro for instruction encoding functions issuing errors. */
8066 #define constraint(expr, err) \
8077 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8078 instructions are unpredictable if these registers are used. This
8079 is the BadReg predicate in ARM's Thumb-2 documentation.
8081 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8082 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8083 #define reject_bad_reg(reg) \
8085 if (reg == REG_PC) \
8087 inst.error = BAD_PC; \
8090 else if (reg == REG_SP \
8091 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8093 inst.error = BAD_SP; \
8098 /* If REG is R13 (the stack pointer), warn that its use is
8100 #define warn_deprecated_sp(reg) \
8102 if (warn_on_deprecated && reg == REG_SP) \
8103 as_tsktsk (_("use of r13 is deprecated")); \
8106 /* Functions for operand encoding. ARM, then Thumb. */
8108 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8110 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8112 The only binary encoding difference is the Coprocessor number. Coprocessor
8113 9 is used for half-precision calculations or conversions. The format of the
8114 instruction is the same as the equivalent Coprocessor 10 instruction that
8115 exists for Single-Precision operation. */
8118 do_scalar_fp16_v82_encode (void)
8120 if (inst
.cond
< COND_ALWAYS
)
8121 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8122 " the behaviour is UNPREDICTABLE"));
8123 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8126 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8127 mark_feature_used (&arm_ext_fp16
);
8130 /* If VAL can be encoded in the immediate field of an ARM instruction,
8131 return the encoded form. Otherwise, return FAIL. */
8134 encode_arm_immediate (unsigned int val
)
8141 for (i
= 2; i
< 32; i
+= 2)
8142 if ((a
= rotate_left (val
, i
)) <= 0xff)
8143 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8148 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8149 return the encoded form. Otherwise, return FAIL. */
8151 encode_thumb32_immediate (unsigned int val
)
8158 for (i
= 1; i
<= 24; i
++)
8161 if ((val
& ~(0xff << i
)) == 0)
8162 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8166 if (val
== ((a
<< 16) | a
))
8168 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8172 if (val
== ((a
<< 16) | a
))
8173 return 0x200 | (a
>> 8);
8177 /* Encode a VFP SP or DP register number into inst.instruction. */
8180 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8182 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8185 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8188 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8191 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8196 first_error (_("D register out of range for selected VFP version"));
8204 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8208 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8212 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8216 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8220 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8224 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8232 /* Encode a <shift> in an ARM-format instruction. The immediate,
8233 if any, is handled by md_apply_fix. */
8235 encode_arm_shift (int i
)
8237 /* register-shifted register. */
8238 if (inst
.operands
[i
].immisreg
)
8241 for (op_index
= 0; op_index
<= i
; ++op_index
)
8243 /* Check the operand only when it's presented. In pre-UAL syntax,
8244 if the destination register is the same as the first operand, two
8245 register form of the instruction can be used. */
8246 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8247 && inst
.operands
[op_index
].reg
== REG_PC
)
8248 as_warn (UNPRED_REG ("r15"));
8251 if (inst
.operands
[i
].imm
== REG_PC
)
8252 as_warn (UNPRED_REG ("r15"));
8255 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8256 inst
.instruction
|= SHIFT_ROR
<< 5;
8259 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8260 if (inst
.operands
[i
].immisreg
)
8262 inst
.instruction
|= SHIFT_BY_REG
;
8263 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8266 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8271 encode_arm_shifter_operand (int i
)
8273 if (inst
.operands
[i
].isreg
)
8275 inst
.instruction
|= inst
.operands
[i
].reg
;
8276 encode_arm_shift (i
);
8280 inst
.instruction
|= INST_IMMEDIATE
;
8281 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8282 inst
.instruction
|= inst
.operands
[i
].imm
;
8286 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8288 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8291 Generate an error if the operand is not a register. */
8292 constraint (!inst
.operands
[i
].isreg
,
8293 _("Instruction does not support =N addresses"));
8295 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8297 if (inst
.operands
[i
].preind
)
8301 inst
.error
= _("instruction does not accept preindexed addressing");
8304 inst
.instruction
|= PRE_INDEX
;
8305 if (inst
.operands
[i
].writeback
)
8306 inst
.instruction
|= WRITE_BACK
;
8309 else if (inst
.operands
[i
].postind
)
8311 gas_assert (inst
.operands
[i
].writeback
);
8313 inst
.instruction
|= WRITE_BACK
;
8315 else /* unindexed - only for coprocessor */
8317 inst
.error
= _("instruction does not accept unindexed addressing");
8321 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8322 && (((inst
.instruction
& 0x000f0000) >> 16)
8323 == ((inst
.instruction
& 0x0000f000) >> 12)))
8324 as_warn ((inst
.instruction
& LOAD_BIT
)
8325 ? _("destination register same as write-back base")
8326 : _("source register same as write-back base"));
8329 /* inst.operands[i] was set up by parse_address. Encode it into an
8330 ARM-format mode 2 load or store instruction. If is_t is true,
8331 reject forms that cannot be used with a T instruction (i.e. not
8334 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8336 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8338 encode_arm_addr_mode_common (i
, is_t
);
8340 if (inst
.operands
[i
].immisreg
)
8342 constraint ((inst
.operands
[i
].imm
== REG_PC
8343 || (is_pc
&& inst
.operands
[i
].writeback
)),
8345 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8346 inst
.instruction
|= inst
.operands
[i
].imm
;
8347 if (!inst
.operands
[i
].negative
)
8348 inst
.instruction
|= INDEX_UP
;
8349 if (inst
.operands
[i
].shifted
)
8351 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8352 inst
.instruction
|= SHIFT_ROR
<< 5;
8355 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8356 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8360 else /* immediate offset in inst.relocs[0] */
8362 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8364 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8366 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8367 cannot use PC in addressing.
8368 PC cannot be used in writeback addressing, either. */
8369 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8372 /* Use of PC in str is deprecated for ARMv7. */
8373 if (warn_on_deprecated
8375 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8376 as_tsktsk (_("use of PC in this instruction is deprecated"));
8379 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8381 /* Prefer + for zero encoded value. */
8382 if (!inst
.operands
[i
].negative
)
8383 inst
.instruction
|= INDEX_UP
;
8384 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8389 /* inst.operands[i] was set up by parse_address. Encode it into an
8390 ARM-format mode 3 load or store instruction. Reject forms that
8391 cannot be used with such instructions. If is_t is true, reject
8392 forms that cannot be used with a T instruction (i.e. not
8395 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8397 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8399 inst
.error
= _("instruction does not accept scaled register index");
8403 encode_arm_addr_mode_common (i
, is_t
);
8405 if (inst
.operands
[i
].immisreg
)
8407 constraint ((inst
.operands
[i
].imm
== REG_PC
8408 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8410 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8412 inst
.instruction
|= inst
.operands
[i
].imm
;
8413 if (!inst
.operands
[i
].negative
)
8414 inst
.instruction
|= INDEX_UP
;
8416 else /* immediate offset in inst.relocs[0] */
8418 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8419 && inst
.operands
[i
].writeback
),
8421 inst
.instruction
|= HWOFFSET_IMM
;
8422 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8424 /* Prefer + for zero encoded value. */
8425 if (!inst
.operands
[i
].negative
)
8426 inst
.instruction
|= INDEX_UP
;
8428 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8433 /* Write immediate bits [7:0] to the following locations:
8435 |28/24|23 19|18 16|15 4|3 0|
8436 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8438 This function is used by VMOV/VMVN/VORR/VBIC. */
8441 neon_write_immbits (unsigned immbits
)
8443 inst
.instruction
|= immbits
& 0xf;
8444 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8445 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8448 /* Invert low-order SIZE bits of XHI:XLO. */
8451 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8453 unsigned immlo
= xlo
? *xlo
: 0;
8454 unsigned immhi
= xhi
? *xhi
: 0;
8459 immlo
= (~immlo
) & 0xff;
8463 immlo
= (~immlo
) & 0xffff;
8467 immhi
= (~immhi
) & 0xffffffff;
8471 immlo
= (~immlo
) & 0xffffffff;
8485 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8489 neon_bits_same_in_bytes (unsigned imm
)
8491 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8492 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8493 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8494 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8497 /* For immediate of above form, return 0bABCD. */
8500 neon_squash_bits (unsigned imm
)
8502 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8503 | ((imm
& 0x01000000) >> 21);
8506 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8509 neon_qfloat_bits (unsigned imm
)
8511 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8514 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8515 the instruction. *OP is passed as the initial value of the op field, and
8516 may be set to a different value depending on the constant (i.e.
8517 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8518 MVN). If the immediate looks like a repeated pattern then also
8519 try smaller element sizes. */
8522 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8523 unsigned *immbits
, int *op
, int size
,
8524 enum neon_el_type type
)
8526 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8528 if (type
== NT_float
&& !float_p
)
8531 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8533 if (size
!= 32 || *op
== 1)
8535 *immbits
= neon_qfloat_bits (immlo
);
8541 if (neon_bits_same_in_bytes (immhi
)
8542 && neon_bits_same_in_bytes (immlo
))
8546 *immbits
= (neon_squash_bits (immhi
) << 4)
8547 | neon_squash_bits (immlo
);
8558 if (immlo
== (immlo
& 0x000000ff))
8563 else if (immlo
== (immlo
& 0x0000ff00))
8565 *immbits
= immlo
>> 8;
8568 else if (immlo
== (immlo
& 0x00ff0000))
8570 *immbits
= immlo
>> 16;
8573 else if (immlo
== (immlo
& 0xff000000))
8575 *immbits
= immlo
>> 24;
8578 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8580 *immbits
= (immlo
>> 8) & 0xff;
8583 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8585 *immbits
= (immlo
>> 16) & 0xff;
8589 if ((immlo
& 0xffff) != (immlo
>> 16))
8596 if (immlo
== (immlo
& 0x000000ff))
8601 else if (immlo
== (immlo
& 0x0000ff00))
8603 *immbits
= immlo
>> 8;
8607 if ((immlo
& 0xff) != (immlo
>> 8))
8612 if (immlo
== (immlo
& 0x000000ff))
8614 /* Don't allow MVN with 8-bit immediate. */
8624 #if defined BFD_HOST_64_BIT
8625 /* Returns TRUE if double precision value V may be cast
8626 to single precision without loss of accuracy. */
8629 is_double_a_single (bfd_int64_t v
)
8631 int exp
= (int)((v
>> 52) & 0x7FF);
8632 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8634 return (exp
== 0 || exp
== 0x7FF
8635 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8636 && (mantissa
& 0x1FFFFFFFl
) == 0;
8639 /* Returns a double precision value casted to single precision
8640 (ignoring the least significant bits in exponent and mantissa). */
8643 double_to_single (bfd_int64_t v
)
8645 int sign
= (int) ((v
>> 63) & 1l);
8646 int exp
= (int) ((v
>> 52) & 0x7FF);
8647 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8653 exp
= exp
- 1023 + 127;
8662 /* No denormalized numbers. */
8668 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8670 #endif /* BFD_HOST_64_BIT */
8679 static void do_vfp_nsyn_opcode (const char *);
8681 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8682 Determine whether it can be performed with a move instruction; if
8683 it can, convert inst.instruction to that move instruction and
8684 return TRUE; if it can't, convert inst.instruction to a literal-pool
8685 load and return FALSE. If this is not a valid thing to do in the
8686 current context, set inst.error and return TRUE.
8688 inst.operands[i] describes the destination register. */
8691 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8694 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8695 bfd_boolean arm_p
= (t
== CONST_ARM
);
8698 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8702 if ((inst
.instruction
& tbit
) == 0)
8704 inst
.error
= _("invalid pseudo operation");
8708 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8709 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8710 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8712 inst
.error
= _("constant expression expected");
8716 if (inst
.relocs
[0].exp
.X_op
== O_constant
8717 || inst
.relocs
[0].exp
.X_op
== O_big
)
8719 #if defined BFD_HOST_64_BIT
8724 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8726 LITTLENUM_TYPE w
[X_PRECISION
];
8729 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8731 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8733 /* FIXME: Should we check words w[2..5] ? */
8738 #if defined BFD_HOST_64_BIT
8740 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8741 << LITTLENUM_NUMBER_OF_BITS
)
8742 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8743 << LITTLENUM_NUMBER_OF_BITS
)
8744 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8745 << LITTLENUM_NUMBER_OF_BITS
)
8746 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8748 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8749 | (l
[0] & LITTLENUM_MASK
);
8753 v
= inst
.relocs
[0].exp
.X_add_number
;
8755 if (!inst
.operands
[i
].issingle
)
8759 /* LDR should not use lead in a flag-setting instruction being
8760 chosen so we do not check whether movs can be used. */
8762 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8763 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8764 && inst
.operands
[i
].reg
!= 13
8765 && inst
.operands
[i
].reg
!= 15)
8767 /* Check if on thumb2 it can be done with a mov.w, mvn or
8768 movw instruction. */
8769 unsigned int newimm
;
8770 bfd_boolean isNegated
;
8772 newimm
= encode_thumb32_immediate (v
);
8773 if (newimm
!= (unsigned int) FAIL
)
8777 newimm
= encode_thumb32_immediate (~v
);
8778 if (newimm
!= (unsigned int) FAIL
)
8782 /* The number can be loaded with a mov.w or mvn
8784 if (newimm
!= (unsigned int) FAIL
8785 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8787 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8788 | (inst
.operands
[i
].reg
<< 8));
8789 /* Change to MOVN. */
8790 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8791 inst
.instruction
|= (newimm
& 0x800) << 15;
8792 inst
.instruction
|= (newimm
& 0x700) << 4;
8793 inst
.instruction
|= (newimm
& 0x0ff);
8796 /* The number can be loaded with a movw instruction. */
8797 else if ((v
& ~0xFFFF) == 0
8798 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8800 int imm
= v
& 0xFFFF;
8802 inst
.instruction
= 0xf2400000; /* MOVW. */
8803 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8804 inst
.instruction
|= (imm
& 0xf000) << 4;
8805 inst
.instruction
|= (imm
& 0x0800) << 15;
8806 inst
.instruction
|= (imm
& 0x0700) << 4;
8807 inst
.instruction
|= (imm
& 0x00ff);
8808 /* In case this replacement is being done on Armv8-M
8809 Baseline we need to make sure to disable the
8810 instruction size check, as otherwise GAS will reject
8811 the use of this T32 instruction. */
8819 int value
= encode_arm_immediate (v
);
8823 /* This can be done with a mov instruction. */
8824 inst
.instruction
&= LITERAL_MASK
;
8825 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8826 inst
.instruction
|= value
& 0xfff;
8830 value
= encode_arm_immediate (~ v
);
8833 /* This can be done with a mvn instruction. */
8834 inst
.instruction
&= LITERAL_MASK
;
8835 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8836 inst
.instruction
|= value
& 0xfff;
8840 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8843 unsigned immbits
= 0;
8844 unsigned immlo
= inst
.operands
[1].imm
;
8845 unsigned immhi
= inst
.operands
[1].regisimm
8846 ? inst
.operands
[1].reg
8847 : inst
.relocs
[0].exp
.X_unsigned
8849 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8850 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8851 &op
, 64, NT_invtype
);
8855 neon_invert_size (&immlo
, &immhi
, 64);
8857 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8858 &op
, 64, NT_invtype
);
8863 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8869 /* Fill other bits in vmov encoding for both thumb and arm. */
8871 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8873 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8874 neon_write_immbits (immbits
);
8882 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8883 if (inst
.operands
[i
].issingle
8884 && is_quarter_float (inst
.operands
[1].imm
)
8885 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8887 inst
.operands
[1].imm
=
8888 neon_qfloat_bits (v
);
8889 do_vfp_nsyn_opcode ("fconsts");
8893 /* If our host does not support a 64-bit type then we cannot perform
8894 the following optimization. This mean that there will be a
8895 discrepancy between the output produced by an assembler built for
8896 a 32-bit-only host and the output produced from a 64-bit host, but
8897 this cannot be helped. */
8898 #if defined BFD_HOST_64_BIT
8899 else if (!inst
.operands
[1].issingle
8900 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8902 if (is_double_a_single (v
)
8903 && is_quarter_float (double_to_single (v
)))
8905 inst
.operands
[1].imm
=
8906 neon_qfloat_bits (double_to_single (v
));
8907 do_vfp_nsyn_opcode ("fconstd");
8915 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8916 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8919 inst
.operands
[1].reg
= REG_PC
;
8920 inst
.operands
[1].isreg
= 1;
8921 inst
.operands
[1].preind
= 1;
8922 inst
.relocs
[0].pc_rel
= 1;
8923 inst
.relocs
[0].type
= (thumb_p
8924 ? BFD_RELOC_ARM_THUMB_OFFSET
8926 ? BFD_RELOC_ARM_HWLITERAL
8927 : BFD_RELOC_ARM_LITERAL
));
8931 /* inst.operands[i] was set up by parse_address. Encode it into an
8932 ARM-format instruction. Reject all forms which cannot be encoded
8933 into a coprocessor load/store instruction. If wb_ok is false,
8934 reject use of writeback; if unind_ok is false, reject use of
8935 unindexed addressing. If reloc_override is not 0, use it instead
8936 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8937 (in which case it is preserved). */
8940 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8942 if (!inst
.operands
[i
].isreg
)
8945 if (! inst
.operands
[0].isvec
)
8947 inst
.error
= _("invalid co-processor operand");
8950 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8954 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8956 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8958 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8960 gas_assert (!inst
.operands
[i
].writeback
);
8963 inst
.error
= _("instruction does not support unindexed addressing");
8966 inst
.instruction
|= inst
.operands
[i
].imm
;
8967 inst
.instruction
|= INDEX_UP
;
8971 if (inst
.operands
[i
].preind
)
8972 inst
.instruction
|= PRE_INDEX
;
8974 if (inst
.operands
[i
].writeback
)
8976 if (inst
.operands
[i
].reg
== REG_PC
)
8978 inst
.error
= _("pc may not be used with write-back");
8983 inst
.error
= _("instruction does not support writeback");
8986 inst
.instruction
|= WRITE_BACK
;
8990 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8991 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8992 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8993 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8996 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8998 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
9001 /* Prefer + for zero encoded value. */
9002 if (!inst
.operands
[i
].negative
)
9003 inst
.instruction
|= INDEX_UP
;
9008 /* Functions for instruction encoding, sorted by sub-architecture.
9009 First some generics; their names are taken from the conventional
9010 bit positions for register arguments in ARM format instructions. */
9020 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9026 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9032 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9033 inst
.instruction
|= inst
.operands
[1].reg
;
9039 inst
.instruction
|= inst
.operands
[0].reg
;
9040 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9046 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9047 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9053 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9054 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9060 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9061 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9065 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9067 if (ARM_CPU_IS_ANY (cpu_variant
))
9069 as_tsktsk ("%s", msg
);
9072 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9084 unsigned Rn
= inst
.operands
[2].reg
;
9085 /* Enforce restrictions on SWP instruction. */
9086 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9088 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9089 _("Rn must not overlap other operands"));
9091 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9093 if (!check_obsolete (&arm_ext_v8
,
9094 _("swp{b} use is obsoleted for ARMv8 and later"))
9095 && warn_on_deprecated
9096 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9097 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9101 inst
.instruction
|= inst
.operands
[1].reg
;
9102 inst
.instruction
|= Rn
<< 16;
9108 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9109 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9110 inst
.instruction
|= inst
.operands
[2].reg
;
9116 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9117 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9118 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9119 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9121 inst
.instruction
|= inst
.operands
[0].reg
;
9122 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9123 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9129 inst
.instruction
|= inst
.operands
[0].imm
;
9135 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9136 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9139 /* ARM instructions, in alphabetical order by function name (except
9140 that wrapper functions appear immediately after the function they
9143 /* This is a pseudo-op of the form "adr rd, label" to be converted
9144 into a relative address of the form "add rd, pc, #label-.-8". */
9149 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9151 /* Frag hacking will turn this into a sub instruction if the offset turns
9152 out to be negative. */
9153 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9154 inst
.relocs
[0].pc_rel
= 1;
9155 inst
.relocs
[0].exp
.X_add_number
-= 8;
9157 if (support_interwork
9158 && inst
.relocs
[0].exp
.X_op
== O_symbol
9159 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9160 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9161 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9162 inst
.relocs
[0].exp
.X_add_number
|= 1;
9165 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9166 into a relative address of the form:
9167 add rd, pc, #low(label-.-8)"
9168 add rd, rd, #high(label-.-8)" */
9173 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9175 /* Frag hacking will turn this into a sub instruction if the offset turns
9176 out to be negative. */
9177 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9178 inst
.relocs
[0].pc_rel
= 1;
9179 inst
.size
= INSN_SIZE
* 2;
9180 inst
.relocs
[0].exp
.X_add_number
-= 8;
9182 if (support_interwork
9183 && inst
.relocs
[0].exp
.X_op
== O_symbol
9184 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9185 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9186 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9187 inst
.relocs
[0].exp
.X_add_number
|= 1;
9193 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9194 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9196 if (!inst
.operands
[1].present
)
9197 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9198 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9199 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9200 encode_arm_shifter_operand (2);
9206 if (inst
.operands
[0].present
)
9207 inst
.instruction
|= inst
.operands
[0].imm
;
9209 inst
.instruction
|= 0xf;
9215 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9216 constraint (msb
> 32, _("bit-field extends past end of register"));
9217 /* The instruction encoding stores the LSB and MSB,
9218 not the LSB and width. */
9219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9220 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9221 inst
.instruction
|= (msb
- 1) << 16;
9229 /* #0 in second position is alternative syntax for bfc, which is
9230 the same instruction but with REG_PC in the Rm field. */
9231 if (!inst
.operands
[1].isreg
)
9232 inst
.operands
[1].reg
= REG_PC
;
9234 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9235 constraint (msb
> 32, _("bit-field extends past end of register"));
9236 /* The instruction encoding stores the LSB and MSB,
9237 not the LSB and width. */
9238 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9239 inst
.instruction
|= inst
.operands
[1].reg
;
9240 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9241 inst
.instruction
|= (msb
- 1) << 16;
9247 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9248 _("bit-field extends past end of register"));
9249 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9250 inst
.instruction
|= inst
.operands
[1].reg
;
9251 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9252 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9255 /* ARM V5 breakpoint instruction (argument parse)
9256 BKPT <16 bit unsigned immediate>
9257 Instruction is not conditional.
9258 The bit pattern given in insns[] has the COND_ALWAYS condition,
9259 and it is an error if the caller tried to override that. */
9264 /* Top 12 of 16 bits to bits 19:8. */
9265 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9267 /* Bottom 4 of 16 bits to bits 3:0. */
9268 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9272 encode_branch (int default_reloc
)
9274 if (inst
.operands
[0].hasreloc
)
9276 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9277 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9278 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9279 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9280 ? BFD_RELOC_ARM_PLT32
9281 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9284 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9285 inst
.relocs
[0].pc_rel
= 1;
9292 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9293 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9296 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9303 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9305 if (inst
.cond
== COND_ALWAYS
)
9306 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9308 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9312 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9315 /* ARM V5 branch-link-exchange instruction (argument parse)
9316 BLX <target_addr> ie BLX(1)
9317 BLX{<condition>} <Rm> ie BLX(2)
9318 Unfortunately, there are two different opcodes for this mnemonic.
9319 So, the insns[].value is not used, and the code here zaps values
9320 into inst.instruction.
9321 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9326 if (inst
.operands
[0].isreg
)
9328 /* Arg is a register; the opcode provided by insns[] is correct.
9329 It is not illegal to do "blx pc", just useless. */
9330 if (inst
.operands
[0].reg
== REG_PC
)
9331 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9333 inst
.instruction
|= inst
.operands
[0].reg
;
9337 /* Arg is an address; this instruction cannot be executed
9338 conditionally, and the opcode must be adjusted.
9339 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9340 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9341 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9342 inst
.instruction
= 0xfa000000;
9343 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9350 bfd_boolean want_reloc
;
9352 if (inst
.operands
[0].reg
== REG_PC
)
9353 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9355 inst
.instruction
|= inst
.operands
[0].reg
;
9356 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9357 it is for ARMv4t or earlier. */
9358 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9359 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9360 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9364 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9369 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9373 /* ARM v5TEJ. Jump to Jazelle code. */
9378 if (inst
.operands
[0].reg
== REG_PC
)
9379 as_tsktsk (_("use of r15 in bxj is not really useful"));
9381 inst
.instruction
|= inst
.operands
[0].reg
;
9384 /* Co-processor data operation:
9385 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9386 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9390 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9391 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9392 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9393 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9394 inst
.instruction
|= inst
.operands
[4].reg
;
9395 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9401 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9402 encode_arm_shifter_operand (1);
9405 /* Transfer between coprocessor and ARM registers.
9406 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9411 No special properties. */
9413 struct deprecated_coproc_regs_s
9420 arm_feature_set deprecated
;
9421 arm_feature_set obsoleted
;
9422 const char *dep_msg
;
9423 const char *obs_msg
;
9426 #define DEPR_ACCESS_V8 \
9427 N_("This coprocessor register access is deprecated in ARMv8")
9429 /* Table of all deprecated coprocessor registers. */
9430 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9432 {15, 0, 7, 10, 5, /* CP15DMB. */
9433 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9434 DEPR_ACCESS_V8
, NULL
},
9435 {15, 0, 7, 10, 4, /* CP15DSB. */
9436 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9437 DEPR_ACCESS_V8
, NULL
},
9438 {15, 0, 7, 5, 4, /* CP15ISB. */
9439 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9440 DEPR_ACCESS_V8
, NULL
},
9441 {14, 6, 1, 0, 0, /* TEEHBR. */
9442 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9443 DEPR_ACCESS_V8
, NULL
},
9444 {14, 6, 0, 0, 0, /* TEECR. */
9445 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9446 DEPR_ACCESS_V8
, NULL
},
9449 #undef DEPR_ACCESS_V8
9451 static const size_t deprecated_coproc_reg_count
=
9452 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9460 Rd
= inst
.operands
[2].reg
;
9463 if (inst
.instruction
== 0xee000010
9464 || inst
.instruction
== 0xfe000010)
9466 reject_bad_reg (Rd
);
9467 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9469 constraint (Rd
== REG_SP
, BAD_SP
);
9474 if (inst
.instruction
== 0xe000010)
9475 constraint (Rd
== REG_PC
, BAD_PC
);
9478 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9480 const struct deprecated_coproc_regs_s
*r
=
9481 deprecated_coproc_regs
+ i
;
9483 if (inst
.operands
[0].reg
== r
->cp
9484 && inst
.operands
[1].imm
== r
->opc1
9485 && inst
.operands
[3].reg
== r
->crn
9486 && inst
.operands
[4].reg
== r
->crm
9487 && inst
.operands
[5].imm
== r
->opc2
)
9489 if (! ARM_CPU_IS_ANY (cpu_variant
)
9490 && warn_on_deprecated
9491 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9492 as_tsktsk ("%s", r
->dep_msg
);
9496 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9497 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9498 inst
.instruction
|= Rd
<< 12;
9499 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9500 inst
.instruction
|= inst
.operands
[4].reg
;
9501 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9504 /* Transfer between coprocessor register and pair of ARM registers.
9505 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9510 Two XScale instructions are special cases of these:
9512 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9513 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9515 Result unpredictable if Rd or Rn is R15. */
9522 Rd
= inst
.operands
[2].reg
;
9523 Rn
= inst
.operands
[3].reg
;
9527 reject_bad_reg (Rd
);
9528 reject_bad_reg (Rn
);
9532 constraint (Rd
== REG_PC
, BAD_PC
);
9533 constraint (Rn
== REG_PC
, BAD_PC
);
9536 /* Only check the MRRC{2} variants. */
9537 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9539 /* If Rd == Rn, error that the operation is
9540 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9541 constraint (Rd
== Rn
, BAD_OVERLAP
);
9544 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9545 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9546 inst
.instruction
|= Rd
<< 12;
9547 inst
.instruction
|= Rn
<< 16;
9548 inst
.instruction
|= inst
.operands
[4].reg
;
9554 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9555 if (inst
.operands
[1].present
)
9557 inst
.instruction
|= CPSI_MMOD
;
9558 inst
.instruction
|= inst
.operands
[1].imm
;
9565 inst
.instruction
|= inst
.operands
[0].imm
;
9571 unsigned Rd
, Rn
, Rm
;
9573 Rd
= inst
.operands
[0].reg
;
9574 Rn
= (inst
.operands
[1].present
9575 ? inst
.operands
[1].reg
: Rd
);
9576 Rm
= inst
.operands
[2].reg
;
9578 constraint ((Rd
== REG_PC
), BAD_PC
);
9579 constraint ((Rn
== REG_PC
), BAD_PC
);
9580 constraint ((Rm
== REG_PC
), BAD_PC
);
9582 inst
.instruction
|= Rd
<< 16;
9583 inst
.instruction
|= Rn
<< 0;
9584 inst
.instruction
|= Rm
<< 8;
9590 /* There is no IT instruction in ARM mode. We
9591 process it to do the validation as if in
9592 thumb mode, just in case the code gets
9593 assembled for thumb using the unified syntax. */
9598 set_pred_insn_type (IT_INSN
);
9599 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9600 now_pred
.cc
= inst
.operands
[0].imm
;
9604 /* If there is only one register in the register list,
9605 then return its register number. Otherwise return -1. */
9607 only_one_reg_in_list (int range
)
9609 int i
= ffs (range
) - 1;
9610 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9614 encode_ldmstm(int from_push_pop_mnem
)
9616 int base_reg
= inst
.operands
[0].reg
;
9617 int range
= inst
.operands
[1].imm
;
9620 inst
.instruction
|= base_reg
<< 16;
9621 inst
.instruction
|= range
;
9623 if (inst
.operands
[1].writeback
)
9624 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9626 if (inst
.operands
[0].writeback
)
9628 inst
.instruction
|= WRITE_BACK
;
9629 /* Check for unpredictable uses of writeback. */
9630 if (inst
.instruction
& LOAD_BIT
)
9632 /* Not allowed in LDM type 2. */
9633 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9634 && ((range
& (1 << REG_PC
)) == 0))
9635 as_warn (_("writeback of base register is UNPREDICTABLE"));
9636 /* Only allowed if base reg not in list for other types. */
9637 else if (range
& (1 << base_reg
))
9638 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9642 /* Not allowed for type 2. */
9643 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9644 as_warn (_("writeback of base register is UNPREDICTABLE"));
9645 /* Only allowed if base reg not in list, or first in list. */
9646 else if ((range
& (1 << base_reg
))
9647 && (range
& ((1 << base_reg
) - 1)))
9648 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9652 /* If PUSH/POP has only one register, then use the A2 encoding. */
9653 one_reg
= only_one_reg_in_list (range
);
9654 if (from_push_pop_mnem
&& one_reg
>= 0)
9656 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9658 if (is_push
&& one_reg
== 13 /* SP */)
9659 /* PR 22483: The A2 encoding cannot be used when
9660 pushing the stack pointer as this is UNPREDICTABLE. */
9663 inst
.instruction
&= A_COND_MASK
;
9664 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9665 inst
.instruction
|= one_reg
<< 12;
9672 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9675 /* ARMv5TE load-consecutive (argument parse)
9684 constraint (inst
.operands
[0].reg
% 2 != 0,
9685 _("first transfer register must be even"));
9686 constraint (inst
.operands
[1].present
9687 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9688 _("can only transfer two consecutive registers"));
9689 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9690 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9692 if (!inst
.operands
[1].present
)
9693 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9695 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9696 register and the first register written; we have to diagnose
9697 overlap between the base and the second register written here. */
9699 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9700 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9701 as_warn (_("base register written back, and overlaps "
9702 "second transfer register"));
9704 if (!(inst
.instruction
& V4_STR_BIT
))
9706 /* For an index-register load, the index register must not overlap the
9707 destination (even if not write-back). */
9708 if (inst
.operands
[2].immisreg
9709 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9710 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9711 as_warn (_("index register overlaps transfer register"));
9713 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9714 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9720 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9721 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9722 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9723 || inst
.operands
[1].negative
9724 /* This can arise if the programmer has written
9726 or if they have mistakenly used a register name as the last
9729 It is very difficult to distinguish between these two cases
9730 because "rX" might actually be a label. ie the register
9731 name has been occluded by a symbol of the same name. So we
9732 just generate a general 'bad addressing mode' type error
9733 message and leave it up to the programmer to discover the
9734 true cause and fix their mistake. */
9735 || (inst
.operands
[1].reg
== REG_PC
),
9738 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9739 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9740 _("offset must be zero in ARM encoding"));
9742 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9744 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9745 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9746 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9752 constraint (inst
.operands
[0].reg
% 2 != 0,
9753 _("even register required"));
9754 constraint (inst
.operands
[1].present
9755 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9756 _("can only load two consecutive registers"));
9757 /* If op 1 were present and equal to PC, this function wouldn't
9758 have been called in the first place. */
9759 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9761 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9762 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9765 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9766 which is not a multiple of four is UNPREDICTABLE. */
9768 check_ldr_r15_aligned (void)
9770 constraint (!(inst
.operands
[1].immisreg
)
9771 && (inst
.operands
[0].reg
== REG_PC
9772 && inst
.operands
[1].reg
== REG_PC
9773 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9774 _("ldr to register 15 must be 4-byte aligned"));
9780 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9781 if (!inst
.operands
[1].isreg
)
9782 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9784 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9785 check_ldr_r15_aligned ();
9791 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9793 if (inst
.operands
[1].preind
)
9795 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9796 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9797 _("this instruction requires a post-indexed address"));
9799 inst
.operands
[1].preind
= 0;
9800 inst
.operands
[1].postind
= 1;
9801 inst
.operands
[1].writeback
= 1;
9803 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9804 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9807 /* Halfword and signed-byte load/store operations. */
9812 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9813 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9814 if (!inst
.operands
[1].isreg
)
9815 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9817 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9823 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9825 if (inst
.operands
[1].preind
)
9827 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9828 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9829 _("this instruction requires a post-indexed address"));
9831 inst
.operands
[1].preind
= 0;
9832 inst
.operands
[1].postind
= 1;
9833 inst
.operands
[1].writeback
= 1;
9835 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9836 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9839 /* Co-processor register load/store.
9840 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9844 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9845 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9846 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9852 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9853 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9854 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9855 && !(inst
.instruction
& 0x00400000))
9856 as_tsktsk (_("Rd and Rm should be different in mla"));
9858 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9859 inst
.instruction
|= inst
.operands
[1].reg
;
9860 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9861 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9867 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9868 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9870 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9871 encode_arm_shifter_operand (1);
9874 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9881 top
= (inst
.instruction
& 0x00400000) != 0;
9882 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9883 _(":lower16: not allowed in this instruction"));
9884 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9885 _(":upper16: not allowed in this instruction"));
9886 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9887 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9889 imm
= inst
.relocs
[0].exp
.X_add_number
;
9890 /* The value is in two pieces: 0:11, 16:19. */
9891 inst
.instruction
|= (imm
& 0x00000fff);
9892 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9897 do_vfp_nsyn_mrs (void)
9899 if (inst
.operands
[0].isvec
)
9901 if (inst
.operands
[1].reg
!= 1)
9902 first_error (_("operand 1 must be FPSCR"));
9903 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9904 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9905 do_vfp_nsyn_opcode ("fmstat");
9907 else if (inst
.operands
[1].isvec
)
9908 do_vfp_nsyn_opcode ("fmrx");
9916 do_vfp_nsyn_msr (void)
9918 if (inst
.operands
[0].isvec
)
9919 do_vfp_nsyn_opcode ("fmxr");
9929 unsigned Rt
= inst
.operands
[0].reg
;
9931 if (thumb_mode
&& Rt
== REG_SP
)
9933 inst
.error
= BAD_SP
;
9937 switch (inst
.operands
[1].reg
)
9939 /* MVFR2 is only valid for Armv8-A. */
9941 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9945 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
9946 case 1: /* fpscr. */
9947 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9948 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9952 case 14: /* fpcxt_ns. */
9953 case 15: /* fpcxt_s. */
9954 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
9955 _("selected processor does not support instruction"));
9958 case 2: /* fpscr_nzcvqc. */
9961 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
9962 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9963 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9964 _("selected processor does not support instruction"));
9965 if (inst
.operands
[0].reg
!= 2
9966 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
9967 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
9974 /* APSR_ sets isvec. All other refs to PC are illegal. */
9975 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9977 inst
.error
= BAD_PC
;
9981 /* If we get through parsing the register name, we just insert the number
9982 generated into the instruction without further validation. */
9983 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9984 inst
.instruction
|= (Rt
<< 12);
9990 unsigned Rt
= inst
.operands
[1].reg
;
9993 reject_bad_reg (Rt
);
9994 else if (Rt
== REG_PC
)
9996 inst
.error
= BAD_PC
;
10000 switch (inst
.operands
[0].reg
)
10002 /* MVFR2 is only valid for Armv8-A. */
10004 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10008 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10009 case 1: /* fpcr. */
10010 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10011 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10015 case 14: /* fpcxt_ns. */
10016 case 15: /* fpcxt_s. */
10017 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10018 _("selected processor does not support instruction"));
10021 case 2: /* fpscr_nzcvqc. */
10022 case 12: /* vpr. */
10024 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10025 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10026 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10027 _("selected processor does not support instruction"));
10028 if (inst
.operands
[0].reg
!= 2
10029 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10030 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10037 /* If we get through parsing the register name, we just insert the number
10038 generated into the instruction without further validation. */
10039 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10040 inst
.instruction
|= (Rt
<< 12);
10048 if (do_vfp_nsyn_mrs () == SUCCESS
)
10051 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10052 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10054 if (inst
.operands
[1].isreg
)
10056 br
= inst
.operands
[1].reg
;
10057 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10058 as_bad (_("bad register for mrs"));
10062 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10063 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10065 _("'APSR', 'CPSR' or 'SPSR' expected"));
10066 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10069 inst
.instruction
|= br
;
10072 /* Two possible forms:
10073 "{C|S}PSR_<field>, Rm",
10074 "{C|S}PSR_f, #expression". */
10079 if (do_vfp_nsyn_msr () == SUCCESS
)
10082 inst
.instruction
|= inst
.operands
[0].imm
;
10083 if (inst
.operands
[1].isreg
)
10084 inst
.instruction
|= inst
.operands
[1].reg
;
10087 inst
.instruction
|= INST_IMMEDIATE
;
10088 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10089 inst
.relocs
[0].pc_rel
= 0;
10096 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10098 if (!inst
.operands
[2].present
)
10099 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10100 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10101 inst
.instruction
|= inst
.operands
[1].reg
;
10102 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10104 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10105 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10106 as_tsktsk (_("Rd and Rm should be different in mul"));
10109 /* Long Multiply Parser
10110 UMULL RdLo, RdHi, Rm, Rs
10111 SMULL RdLo, RdHi, Rm, Rs
10112 UMLAL RdLo, RdHi, Rm, Rs
10113 SMLAL RdLo, RdHi, Rm, Rs. */
10118 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10119 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10120 inst
.instruction
|= inst
.operands
[2].reg
;
10121 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10123 /* rdhi and rdlo must be different. */
10124 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10125 as_tsktsk (_("rdhi and rdlo must be different"));
10127 /* rdhi, rdlo and rm must all be different before armv6. */
10128 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10129 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10130 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10131 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10137 if (inst
.operands
[0].present
10138 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10140 /* Architectural NOP hints are CPSR sets with no bits selected. */
10141 inst
.instruction
&= 0xf0000000;
10142 inst
.instruction
|= 0x0320f000;
10143 if (inst
.operands
[0].present
)
10144 inst
.instruction
|= inst
.operands
[0].imm
;
10148 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10149 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10150 Condition defaults to COND_ALWAYS.
10151 Error if Rd, Rn or Rm are R15. */
10156 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10157 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10158 inst
.instruction
|= inst
.operands
[2].reg
;
10159 if (inst
.operands
[3].present
)
10160 encode_arm_shift (3);
10163 /* ARM V6 PKHTB (Argument Parse). */
10168 if (!inst
.operands
[3].present
)
10170 /* If the shift specifier is omitted, turn the instruction
10171 into pkhbt rd, rm, rn. */
10172 inst
.instruction
&= 0xfff00010;
10173 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10174 inst
.instruction
|= inst
.operands
[1].reg
;
10175 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10179 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10180 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10181 inst
.instruction
|= inst
.operands
[2].reg
;
10182 encode_arm_shift (3);
10186 /* ARMv5TE: Preload-Cache
10187 MP Extensions: Preload for write
10191 Syntactically, like LDR with B=1, W=0, L=1. */
10196 constraint (!inst
.operands
[0].isreg
,
10197 _("'[' expected after PLD mnemonic"));
10198 constraint (inst
.operands
[0].postind
,
10199 _("post-indexed expression used in preload instruction"));
10200 constraint (inst
.operands
[0].writeback
,
10201 _("writeback used in preload instruction"));
10202 constraint (!inst
.operands
[0].preind
,
10203 _("unindexed addressing used in preload instruction"));
10204 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10207 /* ARMv7: PLI <addr_mode> */
10211 constraint (!inst
.operands
[0].isreg
,
10212 _("'[' expected after PLI mnemonic"));
10213 constraint (inst
.operands
[0].postind
,
10214 _("post-indexed expression used in preload instruction"));
10215 constraint (inst
.operands
[0].writeback
,
10216 _("writeback used in preload instruction"));
10217 constraint (!inst
.operands
[0].preind
,
10218 _("unindexed addressing used in preload instruction"));
10219 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10220 inst
.instruction
&= ~PRE_INDEX
;
10226 constraint (inst
.operands
[0].writeback
,
10227 _("push/pop do not support {reglist}^"));
10228 inst
.operands
[1] = inst
.operands
[0];
10229 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10230 inst
.operands
[0].isreg
= 1;
10231 inst
.operands
[0].writeback
= 1;
10232 inst
.operands
[0].reg
= REG_SP
;
10233 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10236 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10237 word at the specified address and the following word
10239 Unconditionally executed.
10240 Error if Rn is R15. */
10245 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10246 if (inst
.operands
[0].writeback
)
10247 inst
.instruction
|= WRITE_BACK
;
10250 /* ARM V6 ssat (argument parse). */
10255 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10256 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10257 inst
.instruction
|= inst
.operands
[2].reg
;
10259 if (inst
.operands
[3].present
)
10260 encode_arm_shift (3);
10263 /* ARM V6 usat (argument parse). */
10268 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10269 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10270 inst
.instruction
|= inst
.operands
[2].reg
;
10272 if (inst
.operands
[3].present
)
10273 encode_arm_shift (3);
10276 /* ARM V6 ssat16 (argument parse). */
10281 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10282 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10283 inst
.instruction
|= inst
.operands
[2].reg
;
10289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10290 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10291 inst
.instruction
|= inst
.operands
[2].reg
;
10294 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10295 preserving the other bits.
10297 setend <endian_specifier>, where <endian_specifier> is either
10303 if (warn_on_deprecated
10304 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10305 as_tsktsk (_("setend use is deprecated for ARMv8"));
10307 if (inst
.operands
[0].imm
)
10308 inst
.instruction
|= 0x200;
10314 unsigned int Rm
= (inst
.operands
[1].present
10315 ? inst
.operands
[1].reg
10316 : inst
.operands
[0].reg
);
10318 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10319 inst
.instruction
|= Rm
;
10320 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10322 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10323 inst
.instruction
|= SHIFT_BY_REG
;
10324 /* PR 12854: Error on extraneous shifts. */
10325 constraint (inst
.operands
[2].shifted
,
10326 _("extraneous shift as part of operand to shift insn"));
10329 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10335 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10336 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10338 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10339 inst
.relocs
[0].pc_rel
= 0;
10345 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10346 inst
.relocs
[0].pc_rel
= 0;
10352 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10353 inst
.relocs
[0].pc_rel
= 0;
10359 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10360 _("selected processor does not support SETPAN instruction"));
10362 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10368 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10369 _("selected processor does not support SETPAN instruction"));
10371 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10374 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10375 SMLAxy{cond} Rd,Rm,Rs,Rn
10376 SMLAWy{cond} Rd,Rm,Rs,Rn
10377 Error if any register is R15. */
10382 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10383 inst
.instruction
|= inst
.operands
[1].reg
;
10384 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10385 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10388 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10389 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10390 Error if any register is R15.
10391 Warning if Rdlo == Rdhi. */
10396 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10397 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10398 inst
.instruction
|= inst
.operands
[2].reg
;
10399 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10401 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10402 as_tsktsk (_("rdhi and rdlo must be different"));
10405 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10406 SMULxy{cond} Rd,Rm,Rs
10407 Error if any register is R15. */
10412 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10413 inst
.instruction
|= inst
.operands
[1].reg
;
10414 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10417 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10418 the same for both ARM and Thumb-2. */
10425 if (inst
.operands
[0].present
)
10427 reg
= inst
.operands
[0].reg
;
10428 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10433 inst
.instruction
|= reg
<< 16;
10434 inst
.instruction
|= inst
.operands
[1].imm
;
10435 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10436 inst
.instruction
|= WRITE_BACK
;
10439 /* ARM V6 strex (argument parse). */
10444 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10445 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10446 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10447 || inst
.operands
[2].negative
10448 /* See comment in do_ldrex(). */
10449 || (inst
.operands
[2].reg
== REG_PC
),
10452 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10453 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10455 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10456 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10457 _("offset must be zero in ARM encoding"));
10459 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10460 inst
.instruction
|= inst
.operands
[1].reg
;
10461 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10462 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10466 do_t_strexbh (void)
10468 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10469 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10470 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10471 || inst
.operands
[2].negative
,
10474 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10475 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10483 constraint (inst
.operands
[1].reg
% 2 != 0,
10484 _("even register required"));
10485 constraint (inst
.operands
[2].present
10486 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10487 _("can only store two consecutive registers"));
10488 /* If op 2 were present and equal to PC, this function wouldn't
10489 have been called in the first place. */
10490 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10492 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10493 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10494 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10497 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10498 inst
.instruction
|= inst
.operands
[1].reg
;
10499 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10506 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10507 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10515 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10516 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10521 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10522 extends it to 32-bits, and adds the result to a value in another
10523 register. You can specify a rotation by 0, 8, 16, or 24 bits
10524 before extracting the 16-bit value.
10525 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10526 Condition defaults to COND_ALWAYS.
10527 Error if any register uses R15. */
10532 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10533 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10534 inst
.instruction
|= inst
.operands
[2].reg
;
10535 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10540 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10541 Condition defaults to COND_ALWAYS.
10542 Error if any register uses R15. */
10547 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10548 inst
.instruction
|= inst
.operands
[1].reg
;
10549 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10552 /* VFP instructions. In a logical order: SP variant first, monad
10553 before dyad, arithmetic then move then load/store. */
10556 do_vfp_sp_monadic (void)
10558 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10559 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10562 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10563 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10567 do_vfp_sp_dyadic (void)
10569 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10570 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10571 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10575 do_vfp_sp_compare_z (void)
10577 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10581 do_vfp_dp_sp_cvt (void)
10583 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10584 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10588 do_vfp_sp_dp_cvt (void)
10590 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10591 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10595 do_vfp_reg_from_sp (void)
10597 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10598 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10601 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10602 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10606 do_vfp_reg2_from_sp2 (void)
10608 constraint (inst
.operands
[2].imm
!= 2,
10609 _("only two consecutive VFP SP registers allowed here"));
10610 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10611 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10612 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10616 do_vfp_sp_from_reg (void)
10618 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10619 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10622 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10623 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10627 do_vfp_sp2_from_reg2 (void)
10629 constraint (inst
.operands
[0].imm
!= 2,
10630 _("only two consecutive VFP SP registers allowed here"));
10631 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10632 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10633 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10637 do_vfp_sp_ldst (void)
10639 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10640 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10644 do_vfp_dp_ldst (void)
10646 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10647 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10652 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10654 if (inst
.operands
[0].writeback
)
10655 inst
.instruction
|= WRITE_BACK
;
10657 constraint (ldstm_type
!= VFP_LDSTMIA
,
10658 _("this addressing mode requires base-register writeback"));
10659 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10660 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10661 inst
.instruction
|= inst
.operands
[1].imm
;
10665 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10669 if (inst
.operands
[0].writeback
)
10670 inst
.instruction
|= WRITE_BACK
;
10672 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10673 _("this addressing mode requires base-register writeback"));
10675 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10676 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10678 count
= inst
.operands
[1].imm
<< 1;
10679 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10682 inst
.instruction
|= count
;
10686 do_vfp_sp_ldstmia (void)
10688 vfp_sp_ldstm (VFP_LDSTMIA
);
10692 do_vfp_sp_ldstmdb (void)
10694 vfp_sp_ldstm (VFP_LDSTMDB
);
10698 do_vfp_dp_ldstmia (void)
10700 vfp_dp_ldstm (VFP_LDSTMIA
);
10704 do_vfp_dp_ldstmdb (void)
10706 vfp_dp_ldstm (VFP_LDSTMDB
);
10710 do_vfp_xp_ldstmia (void)
10712 vfp_dp_ldstm (VFP_LDSTMIAX
);
10716 do_vfp_xp_ldstmdb (void)
10718 vfp_dp_ldstm (VFP_LDSTMDBX
);
10722 do_vfp_dp_rd_rm (void)
10724 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10725 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10728 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10729 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10733 do_vfp_dp_rn_rd (void)
10735 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10736 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10740 do_vfp_dp_rd_rn (void)
10742 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10743 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10747 do_vfp_dp_rd_rn_rm (void)
10749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10750 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10753 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10754 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10755 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10759 do_vfp_dp_rd (void)
10761 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10765 do_vfp_dp_rm_rd_rn (void)
10767 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10768 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10771 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10772 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10773 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10776 /* VFPv3 instructions. */
10778 do_vfp_sp_const (void)
10780 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10781 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10782 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10786 do_vfp_dp_const (void)
10788 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10789 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10790 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10794 vfp_conv (int srcsize
)
10796 int immbits
= srcsize
- inst
.operands
[1].imm
;
10798 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10800 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10801 i.e. immbits must be in range 0 - 16. */
10802 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10805 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10807 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10808 i.e. immbits must be in range 0 - 31. */
10809 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10813 inst
.instruction
|= (immbits
& 1) << 5;
10814 inst
.instruction
|= (immbits
>> 1);
10818 do_vfp_sp_conv_16 (void)
10820 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10825 do_vfp_dp_conv_16 (void)
10827 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10832 do_vfp_sp_conv_32 (void)
10834 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10839 do_vfp_dp_conv_32 (void)
10841 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10845 /* FPA instructions. Also in a logical order. */
10850 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10851 inst
.instruction
|= inst
.operands
[1].reg
;
10855 do_fpa_ldmstm (void)
10857 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10858 switch (inst
.operands
[1].imm
)
10860 case 1: inst
.instruction
|= CP_T_X
; break;
10861 case 2: inst
.instruction
|= CP_T_Y
; break;
10862 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10867 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10869 /* The instruction specified "ea" or "fd", so we can only accept
10870 [Rn]{!}. The instruction does not really support stacking or
10871 unstacking, so we have to emulate these by setting appropriate
10872 bits and offsets. */
10873 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10874 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10875 _("this instruction does not support indexing"));
10877 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10878 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10880 if (!(inst
.instruction
& INDEX_UP
))
10881 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10883 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10885 inst
.operands
[2].preind
= 0;
10886 inst
.operands
[2].postind
= 1;
10890 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10893 /* iWMMXt instructions: strictly in alphabetical order. */
10896 do_iwmmxt_tandorc (void)
10898 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10902 do_iwmmxt_textrc (void)
10904 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10905 inst
.instruction
|= inst
.operands
[1].imm
;
10909 do_iwmmxt_textrm (void)
10911 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10912 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10913 inst
.instruction
|= inst
.operands
[2].imm
;
10917 do_iwmmxt_tinsr (void)
10919 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10920 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10921 inst
.instruction
|= inst
.operands
[2].imm
;
10925 do_iwmmxt_tmia (void)
10927 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10928 inst
.instruction
|= inst
.operands
[1].reg
;
10929 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10933 do_iwmmxt_waligni (void)
10935 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10936 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10937 inst
.instruction
|= inst
.operands
[2].reg
;
10938 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10942 do_iwmmxt_wmerge (void)
10944 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10945 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10946 inst
.instruction
|= inst
.operands
[2].reg
;
10947 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10951 do_iwmmxt_wmov (void)
10953 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10955 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10956 inst
.instruction
|= inst
.operands
[1].reg
;
10960 do_iwmmxt_wldstbh (void)
10963 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10965 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10967 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10968 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10972 do_iwmmxt_wldstw (void)
10974 /* RIWR_RIWC clears .isreg for a control register. */
10975 if (!inst
.operands
[0].isreg
)
10977 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10978 inst
.instruction
|= 0xf0000000;
10981 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10982 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10986 do_iwmmxt_wldstd (void)
10988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10989 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10990 && inst
.operands
[1].immisreg
)
10992 inst
.instruction
&= ~0x1a000ff;
10993 inst
.instruction
|= (0xfU
<< 28);
10994 if (inst
.operands
[1].preind
)
10995 inst
.instruction
|= PRE_INDEX
;
10996 if (!inst
.operands
[1].negative
)
10997 inst
.instruction
|= INDEX_UP
;
10998 if (inst
.operands
[1].writeback
)
10999 inst
.instruction
|= WRITE_BACK
;
11000 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11001 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11002 inst
.instruction
|= inst
.operands
[1].imm
;
11005 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
11009 do_iwmmxt_wshufh (void)
11011 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11012 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11013 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11014 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11018 do_iwmmxt_wzero (void)
11020 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11021 inst
.instruction
|= inst
.operands
[0].reg
;
11022 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11023 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11027 do_iwmmxt_wrwrwr_or_imm5 (void)
11029 if (inst
.operands
[2].isreg
)
11032 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11033 _("immediate operand requires iWMMXt2"));
11035 if (inst
.operands
[2].imm
== 0)
11037 switch ((inst
.instruction
>> 20) & 0xf)
11043 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11044 inst
.operands
[2].imm
= 16;
11045 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11051 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11052 inst
.operands
[2].imm
= 32;
11053 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11060 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11062 wrn
= (inst
.instruction
>> 16) & 0xf;
11063 inst
.instruction
&= 0xff0fff0f;
11064 inst
.instruction
|= wrn
;
11065 /* Bail out here; the instruction is now assembled. */
11070 /* Map 32 -> 0, etc. */
11071 inst
.operands
[2].imm
&= 0x1f;
11072 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11076 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11077 operations first, then control, shift, and load/store. */
11079 /* Insns like "foo X,Y,Z". */
11082 do_mav_triple (void)
11084 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11085 inst
.instruction
|= inst
.operands
[1].reg
;
11086 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11089 /* Insns like "foo W,X,Y,Z".
11090 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11095 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11096 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11097 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11098 inst
.instruction
|= inst
.operands
[3].reg
;
11101 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11103 do_mav_dspsc (void)
11105 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11108 /* Maverick shift immediate instructions.
11109 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11110 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11113 do_mav_shift (void)
11115 int imm
= inst
.operands
[2].imm
;
11117 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11118 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11120 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11121 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11122 Bit 4 should be 0. */
11123 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11125 inst
.instruction
|= imm
;
11128 /* XScale instructions. Also sorted arithmetic before move. */
11130 /* Xscale multiply-accumulate (argument parse)
11133 MIAxycc acc0,Rm,Rs. */
11138 inst
.instruction
|= inst
.operands
[1].reg
;
11139 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11142 /* Xscale move-accumulator-register (argument parse)
11144 MARcc acc0,RdLo,RdHi. */
11149 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11150 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11153 /* Xscale move-register-accumulator (argument parse)
11155 MRAcc RdLo,RdHi,acc0. */
11160 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11161 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11162 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11165 /* Encoding functions relevant only to Thumb. */
11167 /* inst.operands[i] is a shifted-register operand; encode
11168 it into inst.instruction in the format used by Thumb32. */
11171 encode_thumb32_shifted_operand (int i
)
11173 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11174 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11176 constraint (inst
.operands
[i
].immisreg
,
11177 _("shift by register not allowed in thumb mode"));
11178 inst
.instruction
|= inst
.operands
[i
].reg
;
11179 if (shift
== SHIFT_RRX
)
11180 inst
.instruction
|= SHIFT_ROR
<< 4;
11183 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11184 _("expression too complex"));
11186 constraint (value
> 32
11187 || (value
== 32 && (shift
== SHIFT_LSL
11188 || shift
== SHIFT_ROR
)),
11189 _("shift expression is too large"));
11193 else if (value
== 32)
11196 inst
.instruction
|= shift
<< 4;
11197 inst
.instruction
|= (value
& 0x1c) << 10;
11198 inst
.instruction
|= (value
& 0x03) << 6;
11203 /* inst.operands[i] was set up by parse_address. Encode it into a
11204 Thumb32 format load or store instruction. Reject forms that cannot
11205 be used with such instructions. If is_t is true, reject forms that
11206 cannot be used with a T instruction; if is_d is true, reject forms
11207 that cannot be used with a D instruction. If it is a store insn,
11208 reject PC in Rn. */
11211 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11213 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11215 constraint (!inst
.operands
[i
].isreg
,
11216 _("Instruction does not support =N addresses"));
11218 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11219 if (inst
.operands
[i
].immisreg
)
11221 constraint (is_pc
, BAD_PC_ADDRESSING
);
11222 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11223 constraint (inst
.operands
[i
].negative
,
11224 _("Thumb does not support negative register indexing"));
11225 constraint (inst
.operands
[i
].postind
,
11226 _("Thumb does not support register post-indexing"));
11227 constraint (inst
.operands
[i
].writeback
,
11228 _("Thumb does not support register indexing with writeback"));
11229 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11230 _("Thumb supports only LSL in shifted register indexing"));
11232 inst
.instruction
|= inst
.operands
[i
].imm
;
11233 if (inst
.operands
[i
].shifted
)
11235 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11236 _("expression too complex"));
11237 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11238 || inst
.relocs
[0].exp
.X_add_number
> 3,
11239 _("shift out of range"));
11240 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11242 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11244 else if (inst
.operands
[i
].preind
)
11246 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11247 constraint (is_t
&& inst
.operands
[i
].writeback
,
11248 _("cannot use writeback with this instruction"));
11249 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11250 BAD_PC_ADDRESSING
);
11254 inst
.instruction
|= 0x01000000;
11255 if (inst
.operands
[i
].writeback
)
11256 inst
.instruction
|= 0x00200000;
11260 inst
.instruction
|= 0x00000c00;
11261 if (inst
.operands
[i
].writeback
)
11262 inst
.instruction
|= 0x00000100;
11264 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11266 else if (inst
.operands
[i
].postind
)
11268 gas_assert (inst
.operands
[i
].writeback
);
11269 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11270 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11273 inst
.instruction
|= 0x00200000;
11275 inst
.instruction
|= 0x00000900;
11276 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11278 else /* unindexed - only for coprocessor */
11279 inst
.error
= _("instruction does not accept unindexed addressing");
11282 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11283 encodings (the latter only in post-V6T2 cores). The index is the
11284 value used in the insns table below. When there is more than one
11285 possible 16-bit encoding for the instruction, this table always
11287 Also contains several pseudo-instructions used during relaxation. */
11288 #define T16_32_TAB \
11289 X(_adc, 4140, eb400000), \
11290 X(_adcs, 4140, eb500000), \
11291 X(_add, 1c00, eb000000), \
11292 X(_adds, 1c00, eb100000), \
11293 X(_addi, 0000, f1000000), \
11294 X(_addis, 0000, f1100000), \
11295 X(_add_pc,000f, f20f0000), \
11296 X(_add_sp,000d, f10d0000), \
11297 X(_adr, 000f, f20f0000), \
11298 X(_and, 4000, ea000000), \
11299 X(_ands, 4000, ea100000), \
11300 X(_asr, 1000, fa40f000), \
11301 X(_asrs, 1000, fa50f000), \
11302 X(_b, e000, f000b000), \
11303 X(_bcond, d000, f0008000), \
11304 X(_bf, 0000, f040e001), \
11305 X(_bfcsel,0000, f000e001), \
11306 X(_bfx, 0000, f060e001), \
11307 X(_bfl, 0000, f000c001), \
11308 X(_bflx, 0000, f070e001), \
11309 X(_bic, 4380, ea200000), \
11310 X(_bics, 4380, ea300000), \
11311 X(_cinc, 0000, ea509000), \
11312 X(_cinv, 0000, ea50a000), \
11313 X(_cmn, 42c0, eb100f00), \
11314 X(_cmp, 2800, ebb00f00), \
11315 X(_cneg, 0000, ea50b000), \
11316 X(_cpsie, b660, f3af8400), \
11317 X(_cpsid, b670, f3af8600), \
11318 X(_cpy, 4600, ea4f0000), \
11319 X(_csel, 0000, ea508000), \
11320 X(_cset, 0000, ea5f900f), \
11321 X(_csetm, 0000, ea5fa00f), \
11322 X(_csinc, 0000, ea509000), \
11323 X(_csinv, 0000, ea50a000), \
11324 X(_csneg, 0000, ea50b000), \
11325 X(_dec_sp,80dd, f1ad0d00), \
11326 X(_dls, 0000, f040e001), \
11327 X(_dlstp, 0000, f000e001), \
11328 X(_eor, 4040, ea800000), \
11329 X(_eors, 4040, ea900000), \
11330 X(_inc_sp,00dd, f10d0d00), \
11331 X(_lctp, 0000, f00fe001), \
11332 X(_ldmia, c800, e8900000), \
11333 X(_ldr, 6800, f8500000), \
11334 X(_ldrb, 7800, f8100000), \
11335 X(_ldrh, 8800, f8300000), \
11336 X(_ldrsb, 5600, f9100000), \
11337 X(_ldrsh, 5e00, f9300000), \
11338 X(_ldr_pc,4800, f85f0000), \
11339 X(_ldr_pc2,4800, f85f0000), \
11340 X(_ldr_sp,9800, f85d0000), \
11341 X(_le, 0000, f00fc001), \
11342 X(_letp, 0000, f01fc001), \
11343 X(_lsl, 0000, fa00f000), \
11344 X(_lsls, 0000, fa10f000), \
11345 X(_lsr, 0800, fa20f000), \
11346 X(_lsrs, 0800, fa30f000), \
11347 X(_mov, 2000, ea4f0000), \
11348 X(_movs, 2000, ea5f0000), \
11349 X(_mul, 4340, fb00f000), \
11350 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11351 X(_mvn, 43c0, ea6f0000), \
11352 X(_mvns, 43c0, ea7f0000), \
11353 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11354 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11355 X(_orr, 4300, ea400000), \
11356 X(_orrs, 4300, ea500000), \
11357 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11358 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11359 X(_rev, ba00, fa90f080), \
11360 X(_rev16, ba40, fa90f090), \
11361 X(_revsh, bac0, fa90f0b0), \
11362 X(_ror, 41c0, fa60f000), \
11363 X(_rors, 41c0, fa70f000), \
11364 X(_sbc, 4180, eb600000), \
11365 X(_sbcs, 4180, eb700000), \
11366 X(_stmia, c000, e8800000), \
11367 X(_str, 6000, f8400000), \
11368 X(_strb, 7000, f8000000), \
11369 X(_strh, 8000, f8200000), \
11370 X(_str_sp,9000, f84d0000), \
11371 X(_sub, 1e00, eba00000), \
11372 X(_subs, 1e00, ebb00000), \
11373 X(_subi, 8000, f1a00000), \
11374 X(_subis, 8000, f1b00000), \
11375 X(_sxtb, b240, fa4ff080), \
11376 X(_sxth, b200, fa0ff080), \
11377 X(_tst, 4200, ea100f00), \
11378 X(_uxtb, b2c0, fa5ff080), \
11379 X(_uxth, b280, fa1ff080), \
11380 X(_nop, bf00, f3af8000), \
11381 X(_yield, bf10, f3af8001), \
11382 X(_wfe, bf20, f3af8002), \
11383 X(_wfi, bf30, f3af8003), \
11384 X(_wls, 0000, f040c001), \
11385 X(_wlstp, 0000, f000c001), \
11386 X(_sev, bf40, f3af8004), \
11387 X(_sevl, bf50, f3af8005), \
11388 X(_udf, de00, f7f0a000)
11390 /* To catch errors in encoding functions, the codes are all offset by
11391 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11392 as 16-bit instructions. */
11393 #define X(a,b,c) T_MNEM##a
11394 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11397 #define X(a,b,c) 0x##b
11398 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11399 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11402 #define X(a,b,c) 0x##c
11403 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11404 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11405 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11409 /* Thumb instruction encoders, in alphabetical order. */
11411 /* ADDW or SUBW. */
11414 do_t_add_sub_w (void)
11418 Rd
= inst
.operands
[0].reg
;
11419 Rn
= inst
.operands
[1].reg
;
11421 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11422 is the SP-{plus,minus}-immediate form of the instruction. */
11424 constraint (Rd
== REG_PC
, BAD_PC
);
11426 reject_bad_reg (Rd
);
11428 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11429 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11432 /* Parse an add or subtract instruction. We get here with inst.instruction
11433 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11436 do_t_add_sub (void)
11440 Rd
= inst
.operands
[0].reg
;
11441 Rs
= (inst
.operands
[1].present
11442 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11443 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11446 set_pred_insn_type_last ();
11448 if (unified_syntax
)
11451 bfd_boolean narrow
;
11454 flags
= (inst
.instruction
== T_MNEM_adds
11455 || inst
.instruction
== T_MNEM_subs
);
11457 narrow
= !in_pred_block ();
11459 narrow
= in_pred_block ();
11460 if (!inst
.operands
[2].isreg
)
11464 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11465 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11467 add
= (inst
.instruction
== T_MNEM_add
11468 || inst
.instruction
== T_MNEM_adds
);
11470 if (inst
.size_req
!= 4)
11472 /* Attempt to use a narrow opcode, with relaxation if
11474 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11475 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11476 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11477 opcode
= T_MNEM_add_sp
;
11478 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11479 opcode
= T_MNEM_add_pc
;
11480 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11483 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11485 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11489 inst
.instruction
= THUMB_OP16(opcode
);
11490 inst
.instruction
|= (Rd
<< 4) | Rs
;
11491 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11492 || (inst
.relocs
[0].type
11493 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11495 if (inst
.size_req
== 2)
11496 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11498 inst
.relax
= opcode
;
11502 constraint (inst
.size_req
== 2, BAD_HIREG
);
11504 if (inst
.size_req
== 4
11505 || (inst
.size_req
!= 2 && !opcode
))
11507 constraint ((inst
.relocs
[0].type
11508 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11509 && (inst
.relocs
[0].type
11510 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11511 THUMB1_RELOC_ONLY
);
11514 constraint (add
, BAD_PC
);
11515 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11516 _("only SUBS PC, LR, #const allowed"));
11517 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11518 _("expression too complex"));
11519 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11520 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11521 _("immediate value out of range"));
11522 inst
.instruction
= T2_SUBS_PC_LR
11523 | inst
.relocs
[0].exp
.X_add_number
;
11524 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11527 else if (Rs
== REG_PC
)
11529 /* Always use addw/subw. */
11530 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11531 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11535 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11536 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11539 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11541 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11543 inst
.instruction
|= Rd
<< 8;
11544 inst
.instruction
|= Rs
<< 16;
11549 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11550 unsigned int shift
= inst
.operands
[2].shift_kind
;
11552 Rn
= inst
.operands
[2].reg
;
11553 /* See if we can do this with a 16-bit instruction. */
11554 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11556 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11561 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11562 || inst
.instruction
== T_MNEM_add
)
11564 : T_OPCODE_SUB_R3
);
11565 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11569 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11571 /* Thumb-1 cores (except v6-M) require at least one high
11572 register in a narrow non flag setting add. */
11573 if (Rd
> 7 || Rn
> 7
11574 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11575 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11582 inst
.instruction
= T_OPCODE_ADD_HI
;
11583 inst
.instruction
|= (Rd
& 8) << 4;
11584 inst
.instruction
|= (Rd
& 7);
11585 inst
.instruction
|= Rn
<< 3;
11591 constraint (Rd
== REG_PC
, BAD_PC
);
11592 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11593 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11594 constraint (Rs
== REG_PC
, BAD_PC
);
11595 reject_bad_reg (Rn
);
11597 /* If we get here, it can't be done in 16 bits. */
11598 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11599 _("shift must be constant"));
11600 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11601 inst
.instruction
|= Rd
<< 8;
11602 inst
.instruction
|= Rs
<< 16;
11603 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11604 _("shift value over 3 not allowed in thumb mode"));
11605 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11606 _("only LSL shift allowed in thumb mode"));
11607 encode_thumb32_shifted_operand (2);
11612 constraint (inst
.instruction
== T_MNEM_adds
11613 || inst
.instruction
== T_MNEM_subs
,
11616 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11618 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11619 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11622 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11623 ? 0x0000 : 0x8000);
11624 inst
.instruction
|= (Rd
<< 4) | Rs
;
11625 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11629 Rn
= inst
.operands
[2].reg
;
11630 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11632 /* We now have Rd, Rs, and Rn set to registers. */
11633 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11635 /* Can't do this for SUB. */
11636 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11637 inst
.instruction
= T_OPCODE_ADD_HI
;
11638 inst
.instruction
|= (Rd
& 8) << 4;
11639 inst
.instruction
|= (Rd
& 7);
11641 inst
.instruction
|= Rn
<< 3;
11643 inst
.instruction
|= Rs
<< 3;
11645 constraint (1, _("dest must overlap one source register"));
11649 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11650 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11651 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11661 Rd
= inst
.operands
[0].reg
;
11662 reject_bad_reg (Rd
);
11664 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11666 /* Defer to section relaxation. */
11667 inst
.relax
= inst
.instruction
;
11668 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11669 inst
.instruction
|= Rd
<< 4;
11671 else if (unified_syntax
&& inst
.size_req
!= 2)
11673 /* Generate a 32-bit opcode. */
11674 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11675 inst
.instruction
|= Rd
<< 8;
11676 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11677 inst
.relocs
[0].pc_rel
= 1;
11681 /* Generate a 16-bit opcode. */
11682 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11683 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11684 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11685 inst
.relocs
[0].pc_rel
= 1;
11686 inst
.instruction
|= Rd
<< 4;
11689 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11690 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11691 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11692 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11693 inst
.relocs
[0].exp
.X_add_number
+= 1;
11696 /* Arithmetic instructions for which there is just one 16-bit
11697 instruction encoding, and it allows only two low registers.
11698 For maximal compatibility with ARM syntax, we allow three register
11699 operands even when Thumb-32 instructions are not available, as long
11700 as the first two are identical. For instance, both "sbc r0,r1" and
11701 "sbc r0,r0,r1" are allowed. */
11707 Rd
= inst
.operands
[0].reg
;
11708 Rs
= (inst
.operands
[1].present
11709 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11710 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11711 Rn
= inst
.operands
[2].reg
;
11713 reject_bad_reg (Rd
);
11714 reject_bad_reg (Rs
);
11715 if (inst
.operands
[2].isreg
)
11716 reject_bad_reg (Rn
);
11718 if (unified_syntax
)
11720 if (!inst
.operands
[2].isreg
)
11722 /* For an immediate, we always generate a 32-bit opcode;
11723 section relaxation will shrink it later if possible. */
11724 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11725 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11726 inst
.instruction
|= Rd
<< 8;
11727 inst
.instruction
|= Rs
<< 16;
11728 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11732 bfd_boolean narrow
;
11734 /* See if we can do this with a 16-bit instruction. */
11735 if (THUMB_SETS_FLAGS (inst
.instruction
))
11736 narrow
= !in_pred_block ();
11738 narrow
= in_pred_block ();
11740 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11742 if (inst
.operands
[2].shifted
)
11744 if (inst
.size_req
== 4)
11750 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11751 inst
.instruction
|= Rd
;
11752 inst
.instruction
|= Rn
<< 3;
11756 /* If we get here, it can't be done in 16 bits. */
11757 constraint (inst
.operands
[2].shifted
11758 && inst
.operands
[2].immisreg
,
11759 _("shift must be constant"));
11760 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11761 inst
.instruction
|= Rd
<< 8;
11762 inst
.instruction
|= Rs
<< 16;
11763 encode_thumb32_shifted_operand (2);
11768 /* On its face this is a lie - the instruction does set the
11769 flags. However, the only supported mnemonic in this mode
11770 says it doesn't. */
11771 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11773 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11774 _("unshifted register required"));
11775 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11776 constraint (Rd
!= Rs
,
11777 _("dest and source1 must be the same register"));
11779 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11780 inst
.instruction
|= Rd
;
11781 inst
.instruction
|= Rn
<< 3;
11785 /* Similarly, but for instructions where the arithmetic operation is
11786 commutative, so we can allow either of them to be different from
11787 the destination operand in a 16-bit instruction. For instance, all
11788 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11795 Rd
= inst
.operands
[0].reg
;
11796 Rs
= (inst
.operands
[1].present
11797 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11798 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11799 Rn
= inst
.operands
[2].reg
;
11801 reject_bad_reg (Rd
);
11802 reject_bad_reg (Rs
);
11803 if (inst
.operands
[2].isreg
)
11804 reject_bad_reg (Rn
);
11806 if (unified_syntax
)
11808 if (!inst
.operands
[2].isreg
)
11810 /* For an immediate, we always generate a 32-bit opcode;
11811 section relaxation will shrink it later if possible. */
11812 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11813 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11814 inst
.instruction
|= Rd
<< 8;
11815 inst
.instruction
|= Rs
<< 16;
11816 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11820 bfd_boolean narrow
;
11822 /* See if we can do this with a 16-bit instruction. */
11823 if (THUMB_SETS_FLAGS (inst
.instruction
))
11824 narrow
= !in_pred_block ();
11826 narrow
= in_pred_block ();
11828 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11830 if (inst
.operands
[2].shifted
)
11832 if (inst
.size_req
== 4)
11839 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11840 inst
.instruction
|= Rd
;
11841 inst
.instruction
|= Rn
<< 3;
11846 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11847 inst
.instruction
|= Rd
;
11848 inst
.instruction
|= Rs
<< 3;
11853 /* If we get here, it can't be done in 16 bits. */
11854 constraint (inst
.operands
[2].shifted
11855 && inst
.operands
[2].immisreg
,
11856 _("shift must be constant"));
11857 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11858 inst
.instruction
|= Rd
<< 8;
11859 inst
.instruction
|= Rs
<< 16;
11860 encode_thumb32_shifted_operand (2);
11865 /* On its face this is a lie - the instruction does set the
11866 flags. However, the only supported mnemonic in this mode
11867 says it doesn't. */
11868 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11870 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11871 _("unshifted register required"));
11872 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11874 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11875 inst
.instruction
|= Rd
;
11878 inst
.instruction
|= Rn
<< 3;
11880 inst
.instruction
|= Rs
<< 3;
11882 constraint (1, _("dest must overlap one source register"));
11890 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11891 constraint (msb
> 32, _("bit-field extends past end of register"));
11892 /* The instruction encoding stores the LSB and MSB,
11893 not the LSB and width. */
11894 Rd
= inst
.operands
[0].reg
;
11895 reject_bad_reg (Rd
);
11896 inst
.instruction
|= Rd
<< 8;
11897 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11898 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11899 inst
.instruction
|= msb
- 1;
11908 Rd
= inst
.operands
[0].reg
;
11909 reject_bad_reg (Rd
);
11911 /* #0 in second position is alternative syntax for bfc, which is
11912 the same instruction but with REG_PC in the Rm field. */
11913 if (!inst
.operands
[1].isreg
)
11917 Rn
= inst
.operands
[1].reg
;
11918 reject_bad_reg (Rn
);
11921 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11922 constraint (msb
> 32, _("bit-field extends past end of register"));
11923 /* The instruction encoding stores the LSB and MSB,
11924 not the LSB and width. */
11925 inst
.instruction
|= Rd
<< 8;
11926 inst
.instruction
|= Rn
<< 16;
11927 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11928 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11929 inst
.instruction
|= msb
- 1;
11937 Rd
= inst
.operands
[0].reg
;
11938 Rn
= inst
.operands
[1].reg
;
11940 reject_bad_reg (Rd
);
11941 reject_bad_reg (Rn
);
11943 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11944 _("bit-field extends past end of register"));
11945 inst
.instruction
|= Rd
<< 8;
11946 inst
.instruction
|= Rn
<< 16;
11947 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11948 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11949 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11952 /* ARM V5 Thumb BLX (argument parse)
11953 BLX <target_addr> which is BLX(1)
11954 BLX <Rm> which is BLX(2)
11955 Unfortunately, there are two different opcodes for this mnemonic.
11956 So, the insns[].value is not used, and the code here zaps values
11957 into inst.instruction.
11959 ??? How to take advantage of the additional two bits of displacement
11960 available in Thumb32 mode? Need new relocation? */
11965 set_pred_insn_type_last ();
11967 if (inst
.operands
[0].isreg
)
11969 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11970 /* We have a register, so this is BLX(2). */
11971 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11975 /* No register. This must be BLX(1). */
11976 inst
.instruction
= 0xf000e800;
11977 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11986 bfd_reloc_code_real_type reloc
;
11989 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11991 if (in_pred_block ())
11993 /* Conditional branches inside IT blocks are encoded as unconditional
11995 cond
= COND_ALWAYS
;
12000 if (cond
!= COND_ALWAYS
)
12001 opcode
= T_MNEM_bcond
;
12003 opcode
= inst
.instruction
;
12006 && (inst
.size_req
== 4
12007 || (inst
.size_req
!= 2
12008 && (inst
.operands
[0].hasreloc
12009 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12011 inst
.instruction
= THUMB_OP32(opcode
);
12012 if (cond
== COND_ALWAYS
)
12013 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12016 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12017 _("selected architecture does not support "
12018 "wide conditional branch instruction"));
12020 gas_assert (cond
!= 0xF);
12021 inst
.instruction
|= cond
<< 22;
12022 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12027 inst
.instruction
= THUMB_OP16(opcode
);
12028 if (cond
== COND_ALWAYS
)
12029 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12032 inst
.instruction
|= cond
<< 8;
12033 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12035 /* Allow section relaxation. */
12036 if (unified_syntax
&& inst
.size_req
!= 2)
12037 inst
.relax
= opcode
;
12039 inst
.relocs
[0].type
= reloc
;
12040 inst
.relocs
[0].pc_rel
= 1;
12043 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12044 between the two is the maximum immediate allowed - which is passed in
12047 do_t_bkpt_hlt1 (int range
)
12049 constraint (inst
.cond
!= COND_ALWAYS
,
12050 _("instruction is always unconditional"));
12051 if (inst
.operands
[0].present
)
12053 constraint (inst
.operands
[0].imm
> range
,
12054 _("immediate value out of range"));
12055 inst
.instruction
|= inst
.operands
[0].imm
;
12058 set_pred_insn_type (NEUTRAL_IT_INSN
);
12064 do_t_bkpt_hlt1 (63);
12070 do_t_bkpt_hlt1 (255);
12074 do_t_branch23 (void)
12076 set_pred_insn_type_last ();
12077 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12079 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12080 this file. We used to simply ignore the PLT reloc type here --
12081 the branch encoding is now needed to deal with TLSCALL relocs.
12082 So if we see a PLT reloc now, put it back to how it used to be to
12083 keep the preexisting behaviour. */
12084 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12085 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12087 #if defined(OBJ_COFF)
12088 /* If the destination of the branch is a defined symbol which does not have
12089 the THUMB_FUNC attribute, then we must be calling a function which has
12090 the (interfacearm) attribute. We look for the Thumb entry point to that
12091 function and change the branch to refer to that function instead. */
12092 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12093 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12094 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12095 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12096 inst
.relocs
[0].exp
.X_add_symbol
12097 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12104 set_pred_insn_type_last ();
12105 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12106 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12107 should cause the alignment to be checked once it is known. This is
12108 because BX PC only works if the instruction is word aligned. */
12116 set_pred_insn_type_last ();
12117 Rm
= inst
.operands
[0].reg
;
12118 reject_bad_reg (Rm
);
12119 inst
.instruction
|= Rm
<< 16;
12128 Rd
= inst
.operands
[0].reg
;
12129 Rm
= inst
.operands
[1].reg
;
12131 reject_bad_reg (Rd
);
12132 reject_bad_reg (Rm
);
12134 inst
.instruction
|= Rd
<< 8;
12135 inst
.instruction
|= Rm
<< 16;
12136 inst
.instruction
|= Rm
;
12139 /* For the Armv8.1-M conditional instructions. */
12143 unsigned Rd
, Rn
, Rm
;
12146 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12148 Rd
= inst
.operands
[0].reg
;
12149 switch (inst
.instruction
)
12155 Rn
= inst
.operands
[1].reg
;
12156 Rm
= inst
.operands
[2].reg
;
12157 cond
= inst
.operands
[3].imm
;
12158 constraint (Rn
== REG_SP
, BAD_SP
);
12159 constraint (Rm
== REG_SP
, BAD_SP
);
12165 Rn
= inst
.operands
[1].reg
;
12166 cond
= inst
.operands
[2].imm
;
12167 /* Invert the last bit to invert the cond. */
12168 cond
= TOGGLE_BIT (cond
, 0);
12169 constraint (Rn
== REG_SP
, BAD_SP
);
12175 cond
= inst
.operands
[1].imm
;
12176 /* Invert the last bit to invert the cond. */
12177 cond
= TOGGLE_BIT (cond
, 0);
12185 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12186 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12187 inst
.instruction
|= Rd
<< 8;
12188 inst
.instruction
|= Rn
<< 16;
12189 inst
.instruction
|= Rm
;
12190 inst
.instruction
|= cond
<< 4;
12196 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12202 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12203 inst
.instruction
|= inst
.operands
[0].imm
;
12209 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12211 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12212 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12214 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12215 inst
.instruction
= 0xf3af8000;
12216 inst
.instruction
|= imod
<< 9;
12217 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12218 if (inst
.operands
[1].present
)
12219 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12223 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12224 && (inst
.operands
[0].imm
& 4),
12225 _("selected processor does not support 'A' form "
12226 "of this instruction"));
12227 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12228 _("Thumb does not support the 2-argument "
12229 "form of this instruction"));
12230 inst
.instruction
|= inst
.operands
[0].imm
;
12234 /* THUMB CPY instruction (argument parse). */
12239 if (inst
.size_req
== 4)
12241 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12242 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12243 inst
.instruction
|= inst
.operands
[1].reg
;
12247 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12248 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12249 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12256 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12257 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12258 inst
.instruction
|= inst
.operands
[0].reg
;
12259 inst
.relocs
[0].pc_rel
= 1;
12260 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12266 inst
.instruction
|= inst
.operands
[0].imm
;
12272 unsigned Rd
, Rn
, Rm
;
12274 Rd
= inst
.operands
[0].reg
;
12275 Rn
= (inst
.operands
[1].present
12276 ? inst
.operands
[1].reg
: Rd
);
12277 Rm
= inst
.operands
[2].reg
;
12279 reject_bad_reg (Rd
);
12280 reject_bad_reg (Rn
);
12281 reject_bad_reg (Rm
);
12283 inst
.instruction
|= Rd
<< 8;
12284 inst
.instruction
|= Rn
<< 16;
12285 inst
.instruction
|= Rm
;
12291 if (unified_syntax
&& inst
.size_req
== 4)
12292 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12294 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12300 unsigned int cond
= inst
.operands
[0].imm
;
12302 set_pred_insn_type (IT_INSN
);
12303 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12304 now_pred
.cc
= cond
;
12305 now_pred
.warn_deprecated
= FALSE
;
12306 now_pred
.type
= SCALAR_PRED
;
12308 /* If the condition is a negative condition, invert the mask. */
12309 if ((cond
& 0x1) == 0x0)
12311 unsigned int mask
= inst
.instruction
& 0x000f;
12313 if ((mask
& 0x7) == 0)
12315 /* No conversion needed. */
12316 now_pred
.block_length
= 1;
12318 else if ((mask
& 0x3) == 0)
12321 now_pred
.block_length
= 2;
12323 else if ((mask
& 0x1) == 0)
12326 now_pred
.block_length
= 3;
12331 now_pred
.block_length
= 4;
12334 inst
.instruction
&= 0xfff0;
12335 inst
.instruction
|= mask
;
12338 inst
.instruction
|= cond
<< 4;
12341 /* Helper function used for both push/pop and ldm/stm. */
12343 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12344 bfd_boolean writeback
)
12346 bfd_boolean load
, store
;
12348 gas_assert (base
!= -1 || !do_io
);
12349 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12350 store
= do_io
&& !load
;
12352 if (mask
& (1 << 13))
12353 inst
.error
= _("SP not allowed in register list");
12355 if (do_io
&& (mask
& (1 << base
)) != 0
12357 inst
.error
= _("having the base register in the register list when "
12358 "using write back is UNPREDICTABLE");
12362 if (mask
& (1 << 15))
12364 if (mask
& (1 << 14))
12365 inst
.error
= _("LR and PC should not both be in register list");
12367 set_pred_insn_type_last ();
12372 if (mask
& (1 << 15))
12373 inst
.error
= _("PC not allowed in register list");
12376 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12378 /* Single register transfers implemented as str/ldr. */
12381 if (inst
.instruction
& (1 << 23))
12382 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12384 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12388 if (inst
.instruction
& (1 << 23))
12389 inst
.instruction
= 0x00800000; /* ia -> [base] */
12391 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12394 inst
.instruction
|= 0xf8400000;
12396 inst
.instruction
|= 0x00100000;
12398 mask
= ffs (mask
) - 1;
12401 else if (writeback
)
12402 inst
.instruction
|= WRITE_BACK
;
12404 inst
.instruction
|= mask
;
12406 inst
.instruction
|= base
<< 16;
12412 /* This really doesn't seem worth it. */
12413 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12414 _("expression too complex"));
12415 constraint (inst
.operands
[1].writeback
,
12416 _("Thumb load/store multiple does not support {reglist}^"));
12418 if (unified_syntax
)
12420 bfd_boolean narrow
;
12424 /* See if we can use a 16-bit instruction. */
12425 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12426 && inst
.size_req
!= 4
12427 && !(inst
.operands
[1].imm
& ~0xff))
12429 mask
= 1 << inst
.operands
[0].reg
;
12431 if (inst
.operands
[0].reg
<= 7)
12433 if (inst
.instruction
== T_MNEM_stmia
12434 ? inst
.operands
[0].writeback
12435 : (inst
.operands
[0].writeback
12436 == !(inst
.operands
[1].imm
& mask
)))
12438 if (inst
.instruction
== T_MNEM_stmia
12439 && (inst
.operands
[1].imm
& mask
)
12440 && (inst
.operands
[1].imm
& (mask
- 1)))
12441 as_warn (_("value stored for r%d is UNKNOWN"),
12442 inst
.operands
[0].reg
);
12444 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12445 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12446 inst
.instruction
|= inst
.operands
[1].imm
;
12449 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12451 /* This means 1 register in reg list one of 3 situations:
12452 1. Instruction is stmia, but without writeback.
12453 2. lmdia without writeback, but with Rn not in
12455 3. ldmia with writeback, but with Rn in reglist.
12456 Case 3 is UNPREDICTABLE behaviour, so we handle
12457 case 1 and 2 which can be converted into a 16-bit
12458 str or ldr. The SP cases are handled below. */
12459 unsigned long opcode
;
12460 /* First, record an error for Case 3. */
12461 if (inst
.operands
[1].imm
& mask
12462 && inst
.operands
[0].writeback
)
12464 _("having the base register in the register list when "
12465 "using write back is UNPREDICTABLE");
12467 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12469 inst
.instruction
= THUMB_OP16 (opcode
);
12470 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12471 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12475 else if (inst
.operands
[0] .reg
== REG_SP
)
12477 if (inst
.operands
[0].writeback
)
12480 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12481 ? T_MNEM_push
: T_MNEM_pop
);
12482 inst
.instruction
|= inst
.operands
[1].imm
;
12485 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12488 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12489 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12490 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12498 if (inst
.instruction
< 0xffff)
12499 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12501 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12502 inst
.operands
[1].imm
,
12503 inst
.operands
[0].writeback
);
12508 constraint (inst
.operands
[0].reg
> 7
12509 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12510 constraint (inst
.instruction
!= T_MNEM_ldmia
12511 && inst
.instruction
!= T_MNEM_stmia
,
12512 _("Thumb-2 instruction only valid in unified syntax"));
12513 if (inst
.instruction
== T_MNEM_stmia
)
12515 if (!inst
.operands
[0].writeback
)
12516 as_warn (_("this instruction will write back the base register"));
12517 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12518 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12519 as_warn (_("value stored for r%d is UNKNOWN"),
12520 inst
.operands
[0].reg
);
12524 if (!inst
.operands
[0].writeback
12525 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12526 as_warn (_("this instruction will write back the base register"));
12527 else if (inst
.operands
[0].writeback
12528 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12529 as_warn (_("this instruction will not write back the base register"));
12532 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12533 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12534 inst
.instruction
|= inst
.operands
[1].imm
;
12541 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12542 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12543 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12544 || inst
.operands
[1].negative
,
12547 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12549 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12550 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12551 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12557 if (!inst
.operands
[1].present
)
12559 constraint (inst
.operands
[0].reg
== REG_LR
,
12560 _("r14 not allowed as first register "
12561 "when second register is omitted"));
12562 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12564 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12567 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12568 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12569 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12575 unsigned long opcode
;
12578 if (inst
.operands
[0].isreg
12579 && !inst
.operands
[0].preind
12580 && inst
.operands
[0].reg
== REG_PC
)
12581 set_pred_insn_type_last ();
12583 opcode
= inst
.instruction
;
12584 if (unified_syntax
)
12586 if (!inst
.operands
[1].isreg
)
12588 if (opcode
<= 0xffff)
12589 inst
.instruction
= THUMB_OP32 (opcode
);
12590 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12593 if (inst
.operands
[1].isreg
12594 && !inst
.operands
[1].writeback
12595 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12596 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12597 && opcode
<= 0xffff
12598 && inst
.size_req
!= 4)
12600 /* Insn may have a 16-bit form. */
12601 Rn
= inst
.operands
[1].reg
;
12602 if (inst
.operands
[1].immisreg
)
12604 inst
.instruction
= THUMB_OP16 (opcode
);
12606 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12608 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12609 reject_bad_reg (inst
.operands
[1].imm
);
12611 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12612 && opcode
!= T_MNEM_ldrsb
)
12613 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12614 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12621 if (inst
.relocs
[0].pc_rel
)
12622 opcode
= T_MNEM_ldr_pc2
;
12624 opcode
= T_MNEM_ldr_pc
;
12628 if (opcode
== T_MNEM_ldr
)
12629 opcode
= T_MNEM_ldr_sp
;
12631 opcode
= T_MNEM_str_sp
;
12633 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12637 inst
.instruction
= inst
.operands
[0].reg
;
12638 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12640 inst
.instruction
|= THUMB_OP16 (opcode
);
12641 if (inst
.size_req
== 2)
12642 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12644 inst
.relax
= opcode
;
12648 /* Definitely a 32-bit variant. */
12650 /* Warning for Erratum 752419. */
12651 if (opcode
== T_MNEM_ldr
12652 && inst
.operands
[0].reg
== REG_SP
12653 && inst
.operands
[1].writeback
== 1
12654 && !inst
.operands
[1].immisreg
)
12656 if (no_cpu_selected ()
12657 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12658 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12659 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12660 as_warn (_("This instruction may be unpredictable "
12661 "if executed on M-profile cores "
12662 "with interrupts enabled."));
12665 /* Do some validations regarding addressing modes. */
12666 if (inst
.operands
[1].immisreg
)
12667 reject_bad_reg (inst
.operands
[1].imm
);
12669 constraint (inst
.operands
[1].writeback
== 1
12670 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12673 inst
.instruction
= THUMB_OP32 (opcode
);
12674 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12675 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12676 check_ldr_r15_aligned ();
12680 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12682 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12684 /* Only [Rn,Rm] is acceptable. */
12685 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12686 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12687 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12688 || inst
.operands
[1].negative
,
12689 _("Thumb does not support this addressing mode"));
12690 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12694 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12695 if (!inst
.operands
[1].isreg
)
12696 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12699 constraint (!inst
.operands
[1].preind
12700 || inst
.operands
[1].shifted
12701 || inst
.operands
[1].writeback
,
12702 _("Thumb does not support this addressing mode"));
12703 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12705 constraint (inst
.instruction
& 0x0600,
12706 _("byte or halfword not valid for base register"));
12707 constraint (inst
.operands
[1].reg
== REG_PC
12708 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12709 _("r15 based store not allowed"));
12710 constraint (inst
.operands
[1].immisreg
,
12711 _("invalid base register for register offset"));
12713 if (inst
.operands
[1].reg
== REG_PC
)
12714 inst
.instruction
= T_OPCODE_LDR_PC
;
12715 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12716 inst
.instruction
= T_OPCODE_LDR_SP
;
12718 inst
.instruction
= T_OPCODE_STR_SP
;
12720 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12721 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12725 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12726 if (!inst
.operands
[1].immisreg
)
12728 /* Immediate offset. */
12729 inst
.instruction
|= inst
.operands
[0].reg
;
12730 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12731 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12735 /* Register offset. */
12736 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12737 constraint (inst
.operands
[1].negative
,
12738 _("Thumb does not support this addressing mode"));
12741 switch (inst
.instruction
)
12743 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12744 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12745 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12746 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12747 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12748 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12749 case 0x5600 /* ldrsb */:
12750 case 0x5e00 /* ldrsh */: break;
12754 inst
.instruction
|= inst
.operands
[0].reg
;
12755 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12756 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12762 if (!inst
.operands
[1].present
)
12764 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12765 constraint (inst
.operands
[0].reg
== REG_LR
,
12766 _("r14 not allowed here"));
12767 constraint (inst
.operands
[0].reg
== REG_R12
,
12768 _("r12 not allowed here"));
12771 if (inst
.operands
[2].writeback
12772 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12773 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12774 as_warn (_("base register written back, and overlaps "
12775 "one of transfer registers"));
12777 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12778 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12779 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12785 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12786 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12792 unsigned Rd
, Rn
, Rm
, Ra
;
12794 Rd
= inst
.operands
[0].reg
;
12795 Rn
= inst
.operands
[1].reg
;
12796 Rm
= inst
.operands
[2].reg
;
12797 Ra
= inst
.operands
[3].reg
;
12799 reject_bad_reg (Rd
);
12800 reject_bad_reg (Rn
);
12801 reject_bad_reg (Rm
);
12802 reject_bad_reg (Ra
);
12804 inst
.instruction
|= Rd
<< 8;
12805 inst
.instruction
|= Rn
<< 16;
12806 inst
.instruction
|= Rm
;
12807 inst
.instruction
|= Ra
<< 12;
12813 unsigned RdLo
, RdHi
, Rn
, Rm
;
12815 RdLo
= inst
.operands
[0].reg
;
12816 RdHi
= inst
.operands
[1].reg
;
12817 Rn
= inst
.operands
[2].reg
;
12818 Rm
= inst
.operands
[3].reg
;
12820 reject_bad_reg (RdLo
);
12821 reject_bad_reg (RdHi
);
12822 reject_bad_reg (Rn
);
12823 reject_bad_reg (Rm
);
12825 inst
.instruction
|= RdLo
<< 12;
12826 inst
.instruction
|= RdHi
<< 8;
12827 inst
.instruction
|= Rn
<< 16;
12828 inst
.instruction
|= Rm
;
12832 do_t_mov_cmp (void)
12836 Rn
= inst
.operands
[0].reg
;
12837 Rm
= inst
.operands
[1].reg
;
12840 set_pred_insn_type_last ();
12842 if (unified_syntax
)
12844 int r0off
= (inst
.instruction
== T_MNEM_mov
12845 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12846 unsigned long opcode
;
12847 bfd_boolean narrow
;
12848 bfd_boolean low_regs
;
12850 low_regs
= (Rn
<= 7 && Rm
<= 7);
12851 opcode
= inst
.instruction
;
12852 if (in_pred_block ())
12853 narrow
= opcode
!= T_MNEM_movs
;
12855 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12856 if (inst
.size_req
== 4
12857 || inst
.operands
[1].shifted
)
12860 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12861 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12862 && !inst
.operands
[1].shifted
12866 inst
.instruction
= T2_SUBS_PC_LR
;
12870 if (opcode
== T_MNEM_cmp
)
12872 constraint (Rn
== REG_PC
, BAD_PC
);
12875 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12877 warn_deprecated_sp (Rm
);
12878 /* R15 was documented as a valid choice for Rm in ARMv6,
12879 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12880 tools reject R15, so we do too. */
12881 constraint (Rm
== REG_PC
, BAD_PC
);
12884 reject_bad_reg (Rm
);
12886 else if (opcode
== T_MNEM_mov
12887 || opcode
== T_MNEM_movs
)
12889 if (inst
.operands
[1].isreg
)
12891 if (opcode
== T_MNEM_movs
)
12893 reject_bad_reg (Rn
);
12894 reject_bad_reg (Rm
);
12898 /* This is mov.n. */
12899 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12900 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12902 as_tsktsk (_("Use of r%u as a source register is "
12903 "deprecated when r%u is the destination "
12904 "register."), Rm
, Rn
);
12909 /* This is mov.w. */
12910 constraint (Rn
== REG_PC
, BAD_PC
);
12911 constraint (Rm
== REG_PC
, BAD_PC
);
12912 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12913 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12917 reject_bad_reg (Rn
);
12920 if (!inst
.operands
[1].isreg
)
12922 /* Immediate operand. */
12923 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12925 if (low_regs
&& narrow
)
12927 inst
.instruction
= THUMB_OP16 (opcode
);
12928 inst
.instruction
|= Rn
<< 8;
12929 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12930 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12932 if (inst
.size_req
== 2)
12933 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12935 inst
.relax
= opcode
;
12940 constraint ((inst
.relocs
[0].type
12941 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12942 && (inst
.relocs
[0].type
12943 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12944 THUMB1_RELOC_ONLY
);
12946 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12947 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12948 inst
.instruction
|= Rn
<< r0off
;
12949 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12952 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12953 && (inst
.instruction
== T_MNEM_mov
12954 || inst
.instruction
== T_MNEM_movs
))
12956 /* Register shifts are encoded as separate shift instructions. */
12957 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12959 if (in_pred_block ())
12964 if (inst
.size_req
== 4)
12967 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12973 switch (inst
.operands
[1].shift_kind
)
12976 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12979 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12982 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12985 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12991 inst
.instruction
= opcode
;
12994 inst
.instruction
|= Rn
;
12995 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
13000 inst
.instruction
|= CONDS_BIT
;
13002 inst
.instruction
|= Rn
<< 8;
13003 inst
.instruction
|= Rm
<< 16;
13004 inst
.instruction
|= inst
.operands
[1].imm
;
13009 /* Some mov with immediate shift have narrow variants.
13010 Register shifts are handled above. */
13011 if (low_regs
&& inst
.operands
[1].shifted
13012 && (inst
.instruction
== T_MNEM_mov
13013 || inst
.instruction
== T_MNEM_movs
))
13015 if (in_pred_block ())
13016 narrow
= (inst
.instruction
== T_MNEM_mov
);
13018 narrow
= (inst
.instruction
== T_MNEM_movs
);
13023 switch (inst
.operands
[1].shift_kind
)
13025 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13026 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13027 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13028 default: narrow
= FALSE
; break;
13034 inst
.instruction
|= Rn
;
13035 inst
.instruction
|= Rm
<< 3;
13036 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13040 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13041 inst
.instruction
|= Rn
<< r0off
;
13042 encode_thumb32_shifted_operand (1);
13046 switch (inst
.instruction
)
13049 /* In v4t or v5t a move of two lowregs produces unpredictable
13050 results. Don't allow this. */
13053 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13054 "MOV Rd, Rs with two low registers is not "
13055 "permitted on this architecture");
13056 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13060 inst
.instruction
= T_OPCODE_MOV_HR
;
13061 inst
.instruction
|= (Rn
& 0x8) << 4;
13062 inst
.instruction
|= (Rn
& 0x7);
13063 inst
.instruction
|= Rm
<< 3;
13067 /* We know we have low registers at this point.
13068 Generate LSLS Rd, Rs, #0. */
13069 inst
.instruction
= T_OPCODE_LSL_I
;
13070 inst
.instruction
|= Rn
;
13071 inst
.instruction
|= Rm
<< 3;
13077 inst
.instruction
= T_OPCODE_CMP_LR
;
13078 inst
.instruction
|= Rn
;
13079 inst
.instruction
|= Rm
<< 3;
13083 inst
.instruction
= T_OPCODE_CMP_HR
;
13084 inst
.instruction
|= (Rn
& 0x8) << 4;
13085 inst
.instruction
|= (Rn
& 0x7);
13086 inst
.instruction
|= Rm
<< 3;
13093 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13095 /* PR 10443: Do not silently ignore shifted operands. */
13096 constraint (inst
.operands
[1].shifted
,
13097 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13099 if (inst
.operands
[1].isreg
)
13101 if (Rn
< 8 && Rm
< 8)
13103 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13104 since a MOV instruction produces unpredictable results. */
13105 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13106 inst
.instruction
= T_OPCODE_ADD_I3
;
13108 inst
.instruction
= T_OPCODE_CMP_LR
;
13110 inst
.instruction
|= Rn
;
13111 inst
.instruction
|= Rm
<< 3;
13115 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13116 inst
.instruction
= T_OPCODE_MOV_HR
;
13118 inst
.instruction
= T_OPCODE_CMP_HR
;
13124 constraint (Rn
> 7,
13125 _("only lo regs allowed with immediate"));
13126 inst
.instruction
|= Rn
<< 8;
13127 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13138 top
= (inst
.instruction
& 0x00800000) != 0;
13139 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13141 constraint (top
, _(":lower16: not allowed in this instruction"));
13142 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13144 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13146 constraint (!top
, _(":upper16: not allowed in this instruction"));
13147 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13150 Rd
= inst
.operands
[0].reg
;
13151 reject_bad_reg (Rd
);
13153 inst
.instruction
|= Rd
<< 8;
13154 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13156 imm
= inst
.relocs
[0].exp
.X_add_number
;
13157 inst
.instruction
|= (imm
& 0xf000) << 4;
13158 inst
.instruction
|= (imm
& 0x0800) << 15;
13159 inst
.instruction
|= (imm
& 0x0700) << 4;
13160 inst
.instruction
|= (imm
& 0x00ff);
13165 do_t_mvn_tst (void)
13169 Rn
= inst
.operands
[0].reg
;
13170 Rm
= inst
.operands
[1].reg
;
13172 if (inst
.instruction
== T_MNEM_cmp
13173 || inst
.instruction
== T_MNEM_cmn
)
13174 constraint (Rn
== REG_PC
, BAD_PC
);
13176 reject_bad_reg (Rn
);
13177 reject_bad_reg (Rm
);
13179 if (unified_syntax
)
13181 int r0off
= (inst
.instruction
== T_MNEM_mvn
13182 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13183 bfd_boolean narrow
;
13185 if (inst
.size_req
== 4
13186 || inst
.instruction
> 0xffff
13187 || inst
.operands
[1].shifted
13188 || Rn
> 7 || Rm
> 7)
13190 else if (inst
.instruction
== T_MNEM_cmn
13191 || inst
.instruction
== T_MNEM_tst
)
13193 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13194 narrow
= !in_pred_block ();
13196 narrow
= in_pred_block ();
13198 if (!inst
.operands
[1].isreg
)
13200 /* For an immediate, we always generate a 32-bit opcode;
13201 section relaxation will shrink it later if possible. */
13202 if (inst
.instruction
< 0xffff)
13203 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13204 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13205 inst
.instruction
|= Rn
<< r0off
;
13206 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13210 /* See if we can do this with a 16-bit instruction. */
13213 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13214 inst
.instruction
|= Rn
;
13215 inst
.instruction
|= Rm
<< 3;
13219 constraint (inst
.operands
[1].shifted
13220 && inst
.operands
[1].immisreg
,
13221 _("shift must be constant"));
13222 if (inst
.instruction
< 0xffff)
13223 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13224 inst
.instruction
|= Rn
<< r0off
;
13225 encode_thumb32_shifted_operand (1);
13231 constraint (inst
.instruction
> 0xffff
13232 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13233 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13234 _("unshifted register required"));
13235 constraint (Rn
> 7 || Rm
> 7,
13238 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13239 inst
.instruction
|= Rn
;
13240 inst
.instruction
|= Rm
<< 3;
13249 if (do_vfp_nsyn_mrs () == SUCCESS
)
13252 Rd
= inst
.operands
[0].reg
;
13253 reject_bad_reg (Rd
);
13254 inst
.instruction
|= Rd
<< 8;
13256 if (inst
.operands
[1].isreg
)
13258 unsigned br
= inst
.operands
[1].reg
;
13259 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13260 as_bad (_("bad register for mrs"));
13262 inst
.instruction
|= br
& (0xf << 16);
13263 inst
.instruction
|= (br
& 0x300) >> 4;
13264 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13268 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13270 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13272 /* PR gas/12698: The constraint is only applied for m_profile.
13273 If the user has specified -march=all, we want to ignore it as
13274 we are building for any CPU type, including non-m variants. */
13275 bfd_boolean m_profile
=
13276 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13277 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13278 "not support requested special purpose register"));
13281 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13283 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13284 _("'APSR', 'CPSR' or 'SPSR' expected"));
13286 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13287 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13288 inst
.instruction
|= 0xf0000;
13298 if (do_vfp_nsyn_msr () == SUCCESS
)
13301 constraint (!inst
.operands
[1].isreg
,
13302 _("Thumb encoding does not support an immediate here"));
13304 if (inst
.operands
[0].isreg
)
13305 flags
= (int)(inst
.operands
[0].reg
);
13307 flags
= inst
.operands
[0].imm
;
13309 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13311 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13313 /* PR gas/12698: The constraint is only applied for m_profile.
13314 If the user has specified -march=all, we want to ignore it as
13315 we are building for any CPU type, including non-m variants. */
13316 bfd_boolean m_profile
=
13317 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13318 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13319 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13320 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13321 && bits
!= PSR_f
)) && m_profile
,
13322 _("selected processor does not support requested special "
13323 "purpose register"));
13326 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13327 "requested special purpose register"));
13329 Rn
= inst
.operands
[1].reg
;
13330 reject_bad_reg (Rn
);
13332 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13333 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13334 inst
.instruction
|= (flags
& 0x300) >> 4;
13335 inst
.instruction
|= (flags
& 0xff);
13336 inst
.instruction
|= Rn
<< 16;
13342 bfd_boolean narrow
;
13343 unsigned Rd
, Rn
, Rm
;
13345 if (!inst
.operands
[2].present
)
13346 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13348 Rd
= inst
.operands
[0].reg
;
13349 Rn
= inst
.operands
[1].reg
;
13350 Rm
= inst
.operands
[2].reg
;
13352 if (unified_syntax
)
13354 if (inst
.size_req
== 4
13360 else if (inst
.instruction
== T_MNEM_muls
)
13361 narrow
= !in_pred_block ();
13363 narrow
= in_pred_block ();
13367 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13368 constraint (Rn
> 7 || Rm
> 7,
13375 /* 16-bit MULS/Conditional MUL. */
13376 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13377 inst
.instruction
|= Rd
;
13380 inst
.instruction
|= Rm
<< 3;
13382 inst
.instruction
|= Rn
<< 3;
13384 constraint (1, _("dest must overlap one source register"));
13388 constraint (inst
.instruction
!= T_MNEM_mul
,
13389 _("Thumb-2 MUL must not set flags"));
13391 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13392 inst
.instruction
|= Rd
<< 8;
13393 inst
.instruction
|= Rn
<< 16;
13394 inst
.instruction
|= Rm
<< 0;
13396 reject_bad_reg (Rd
);
13397 reject_bad_reg (Rn
);
13398 reject_bad_reg (Rm
);
13405 unsigned RdLo
, RdHi
, Rn
, Rm
;
13407 RdLo
= inst
.operands
[0].reg
;
13408 RdHi
= inst
.operands
[1].reg
;
13409 Rn
= inst
.operands
[2].reg
;
13410 Rm
= inst
.operands
[3].reg
;
13412 reject_bad_reg (RdLo
);
13413 reject_bad_reg (RdHi
);
13414 reject_bad_reg (Rn
);
13415 reject_bad_reg (Rm
);
13417 inst
.instruction
|= RdLo
<< 12;
13418 inst
.instruction
|= RdHi
<< 8;
13419 inst
.instruction
|= Rn
<< 16;
13420 inst
.instruction
|= Rm
;
13423 as_tsktsk (_("rdhi and rdlo must be different"));
13429 set_pred_insn_type (NEUTRAL_IT_INSN
);
13431 if (unified_syntax
)
13433 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13435 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13436 inst
.instruction
|= inst
.operands
[0].imm
;
13440 /* PR9722: Check for Thumb2 availability before
13441 generating a thumb2 nop instruction. */
13442 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13444 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13445 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13448 inst
.instruction
= 0x46c0;
13453 constraint (inst
.operands
[0].present
,
13454 _("Thumb does not support NOP with hints"));
13455 inst
.instruction
= 0x46c0;
13462 if (unified_syntax
)
13464 bfd_boolean narrow
;
13466 if (THUMB_SETS_FLAGS (inst
.instruction
))
13467 narrow
= !in_pred_block ();
13469 narrow
= in_pred_block ();
13470 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13472 if (inst
.size_req
== 4)
13477 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13478 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13479 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13483 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13484 inst
.instruction
|= inst
.operands
[0].reg
;
13485 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13490 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13492 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13494 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13495 inst
.instruction
|= inst
.operands
[0].reg
;
13496 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13505 Rd
= inst
.operands
[0].reg
;
13506 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13508 reject_bad_reg (Rd
);
13509 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13510 reject_bad_reg (Rn
);
13512 inst
.instruction
|= Rd
<< 8;
13513 inst
.instruction
|= Rn
<< 16;
13515 if (!inst
.operands
[2].isreg
)
13517 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13518 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13524 Rm
= inst
.operands
[2].reg
;
13525 reject_bad_reg (Rm
);
13527 constraint (inst
.operands
[2].shifted
13528 && inst
.operands
[2].immisreg
,
13529 _("shift must be constant"));
13530 encode_thumb32_shifted_operand (2);
13537 unsigned Rd
, Rn
, Rm
;
13539 Rd
= inst
.operands
[0].reg
;
13540 Rn
= inst
.operands
[1].reg
;
13541 Rm
= inst
.operands
[2].reg
;
13543 reject_bad_reg (Rd
);
13544 reject_bad_reg (Rn
);
13545 reject_bad_reg (Rm
);
13547 inst
.instruction
|= Rd
<< 8;
13548 inst
.instruction
|= Rn
<< 16;
13549 inst
.instruction
|= Rm
;
13550 if (inst
.operands
[3].present
)
13552 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13553 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13554 _("expression too complex"));
13555 inst
.instruction
|= (val
& 0x1c) << 10;
13556 inst
.instruction
|= (val
& 0x03) << 6;
13563 if (!inst
.operands
[3].present
)
13567 inst
.instruction
&= ~0x00000020;
13569 /* PR 10168. Swap the Rm and Rn registers. */
13570 Rtmp
= inst
.operands
[1].reg
;
13571 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13572 inst
.operands
[2].reg
= Rtmp
;
13580 if (inst
.operands
[0].immisreg
)
13581 reject_bad_reg (inst
.operands
[0].imm
);
13583 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13587 do_t_push_pop (void)
13591 constraint (inst
.operands
[0].writeback
,
13592 _("push/pop do not support {reglist}^"));
13593 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13594 _("expression too complex"));
13596 mask
= inst
.operands
[0].imm
;
13597 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13598 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13599 else if (inst
.size_req
!= 4
13600 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13601 ? REG_LR
: REG_PC
)))
13603 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13604 inst
.instruction
|= THUMB_PP_PC_LR
;
13605 inst
.instruction
|= mask
& 0xff;
13607 else if (unified_syntax
)
13609 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13610 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13614 inst
.error
= _("invalid register list to push/pop instruction");
13622 if (unified_syntax
)
13623 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13626 inst
.error
= _("invalid register list to push/pop instruction");
13632 do_t_vscclrm (void)
13634 if (inst
.operands
[0].issingle
)
13636 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13637 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13638 inst
.instruction
|= inst
.operands
[0].imm
;
13642 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13643 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13644 inst
.instruction
|= 1 << 8;
13645 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13654 Rd
= inst
.operands
[0].reg
;
13655 Rm
= inst
.operands
[1].reg
;
13657 reject_bad_reg (Rd
);
13658 reject_bad_reg (Rm
);
13660 inst
.instruction
|= Rd
<< 8;
13661 inst
.instruction
|= Rm
<< 16;
13662 inst
.instruction
|= Rm
;
13670 Rd
= inst
.operands
[0].reg
;
13671 Rm
= inst
.operands
[1].reg
;
13673 reject_bad_reg (Rd
);
13674 reject_bad_reg (Rm
);
13676 if (Rd
<= 7 && Rm
<= 7
13677 && inst
.size_req
!= 4)
13679 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13680 inst
.instruction
|= Rd
;
13681 inst
.instruction
|= Rm
<< 3;
13683 else if (unified_syntax
)
13685 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13686 inst
.instruction
|= Rd
<< 8;
13687 inst
.instruction
|= Rm
<< 16;
13688 inst
.instruction
|= Rm
;
13691 inst
.error
= BAD_HIREG
;
13699 Rd
= inst
.operands
[0].reg
;
13700 Rm
= inst
.operands
[1].reg
;
13702 reject_bad_reg (Rd
);
13703 reject_bad_reg (Rm
);
13705 inst
.instruction
|= Rd
<< 8;
13706 inst
.instruction
|= Rm
;
13714 Rd
= inst
.operands
[0].reg
;
13715 Rs
= (inst
.operands
[1].present
13716 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13717 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13719 reject_bad_reg (Rd
);
13720 reject_bad_reg (Rs
);
13721 if (inst
.operands
[2].isreg
)
13722 reject_bad_reg (inst
.operands
[2].reg
);
13724 inst
.instruction
|= Rd
<< 8;
13725 inst
.instruction
|= Rs
<< 16;
13726 if (!inst
.operands
[2].isreg
)
13728 bfd_boolean narrow
;
13730 if ((inst
.instruction
& 0x00100000) != 0)
13731 narrow
= !in_pred_block ();
13733 narrow
= in_pred_block ();
13735 if (Rd
> 7 || Rs
> 7)
13738 if (inst
.size_req
== 4 || !unified_syntax
)
13741 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13742 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13745 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13746 relaxation, but it doesn't seem worth the hassle. */
13749 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13750 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13751 inst
.instruction
|= Rs
<< 3;
13752 inst
.instruction
|= Rd
;
13756 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13757 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13761 encode_thumb32_shifted_operand (2);
13767 if (warn_on_deprecated
13768 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13769 as_tsktsk (_("setend use is deprecated for ARMv8"));
13771 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13772 if (inst
.operands
[0].imm
)
13773 inst
.instruction
|= 0x8;
13779 if (!inst
.operands
[1].present
)
13780 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13782 if (unified_syntax
)
13784 bfd_boolean narrow
;
13787 switch (inst
.instruction
)
13790 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13792 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13794 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13796 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13800 if (THUMB_SETS_FLAGS (inst
.instruction
))
13801 narrow
= !in_pred_block ();
13803 narrow
= in_pred_block ();
13804 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13806 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13808 if (inst
.operands
[2].isreg
13809 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13810 || inst
.operands
[2].reg
> 7))
13812 if (inst
.size_req
== 4)
13815 reject_bad_reg (inst
.operands
[0].reg
);
13816 reject_bad_reg (inst
.operands
[1].reg
);
13820 if (inst
.operands
[2].isreg
)
13822 reject_bad_reg (inst
.operands
[2].reg
);
13823 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13824 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13825 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13826 inst
.instruction
|= inst
.operands
[2].reg
;
13828 /* PR 12854: Error on extraneous shifts. */
13829 constraint (inst
.operands
[2].shifted
,
13830 _("extraneous shift as part of operand to shift insn"));
13834 inst
.operands
[1].shifted
= 1;
13835 inst
.operands
[1].shift_kind
= shift_kind
;
13836 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13837 ? T_MNEM_movs
: T_MNEM_mov
);
13838 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13839 encode_thumb32_shifted_operand (1);
13840 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13841 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13846 if (inst
.operands
[2].isreg
)
13848 switch (shift_kind
)
13850 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13851 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13852 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13853 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13857 inst
.instruction
|= inst
.operands
[0].reg
;
13858 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13860 /* PR 12854: Error on extraneous shifts. */
13861 constraint (inst
.operands
[2].shifted
,
13862 _("extraneous shift as part of operand to shift insn"));
13866 switch (shift_kind
)
13868 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13869 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13870 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13873 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13874 inst
.instruction
|= inst
.operands
[0].reg
;
13875 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13881 constraint (inst
.operands
[0].reg
> 7
13882 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13883 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13885 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13887 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13888 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13889 _("source1 and dest must be same register"));
13891 switch (inst
.instruction
)
13893 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13894 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13895 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13896 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13900 inst
.instruction
|= inst
.operands
[0].reg
;
13901 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13903 /* PR 12854: Error on extraneous shifts. */
13904 constraint (inst
.operands
[2].shifted
,
13905 _("extraneous shift as part of operand to shift insn"));
13909 switch (inst
.instruction
)
13911 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13912 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13913 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13914 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13917 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13918 inst
.instruction
|= inst
.operands
[0].reg
;
13919 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13927 unsigned Rd
, Rn
, Rm
;
13929 Rd
= inst
.operands
[0].reg
;
13930 Rn
= inst
.operands
[1].reg
;
13931 Rm
= inst
.operands
[2].reg
;
13933 reject_bad_reg (Rd
);
13934 reject_bad_reg (Rn
);
13935 reject_bad_reg (Rm
);
13937 inst
.instruction
|= Rd
<< 8;
13938 inst
.instruction
|= Rn
<< 16;
13939 inst
.instruction
|= Rm
;
13945 unsigned Rd
, Rn
, Rm
;
13947 Rd
= inst
.operands
[0].reg
;
13948 Rm
= inst
.operands
[1].reg
;
13949 Rn
= inst
.operands
[2].reg
;
13951 reject_bad_reg (Rd
);
13952 reject_bad_reg (Rn
);
13953 reject_bad_reg (Rm
);
13955 inst
.instruction
|= Rd
<< 8;
13956 inst
.instruction
|= Rn
<< 16;
13957 inst
.instruction
|= Rm
;
13963 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13964 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13965 _("SMC is not permitted on this architecture"));
13966 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13967 _("expression too complex"));
13968 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
13970 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13971 inst
.instruction
|= (value
& 0x000f) << 16;
13973 /* PR gas/15623: SMC instructions must be last in an IT block. */
13974 set_pred_insn_type_last ();
13980 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13982 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13983 inst
.instruction
|= (value
& 0x0fff);
13984 inst
.instruction
|= (value
& 0xf000) << 4;
13988 do_t_ssat_usat (int bias
)
13992 Rd
= inst
.operands
[0].reg
;
13993 Rn
= inst
.operands
[2].reg
;
13995 reject_bad_reg (Rd
);
13996 reject_bad_reg (Rn
);
13998 inst
.instruction
|= Rd
<< 8;
13999 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
14000 inst
.instruction
|= Rn
<< 16;
14002 if (inst
.operands
[3].present
)
14004 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14006 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14008 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14009 _("expression too complex"));
14011 if (shift_amount
!= 0)
14013 constraint (shift_amount
> 31,
14014 _("shift expression is too large"));
14016 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14017 inst
.instruction
|= 0x00200000; /* sh bit. */
14019 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14020 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14028 do_t_ssat_usat (1);
14036 Rd
= inst
.operands
[0].reg
;
14037 Rn
= inst
.operands
[2].reg
;
14039 reject_bad_reg (Rd
);
14040 reject_bad_reg (Rn
);
14042 inst
.instruction
|= Rd
<< 8;
14043 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14044 inst
.instruction
|= Rn
<< 16;
14050 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14051 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14052 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14053 || inst
.operands
[2].negative
,
14056 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14058 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14059 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14060 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14061 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14067 if (!inst
.operands
[2].present
)
14068 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14070 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14071 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14072 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14075 inst
.instruction
|= inst
.operands
[0].reg
;
14076 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14077 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14078 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14084 unsigned Rd
, Rn
, Rm
;
14086 Rd
= inst
.operands
[0].reg
;
14087 Rn
= inst
.operands
[1].reg
;
14088 Rm
= inst
.operands
[2].reg
;
14090 reject_bad_reg (Rd
);
14091 reject_bad_reg (Rn
);
14092 reject_bad_reg (Rm
);
14094 inst
.instruction
|= Rd
<< 8;
14095 inst
.instruction
|= Rn
<< 16;
14096 inst
.instruction
|= Rm
;
14097 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14105 Rd
= inst
.operands
[0].reg
;
14106 Rm
= inst
.operands
[1].reg
;
14108 reject_bad_reg (Rd
);
14109 reject_bad_reg (Rm
);
14111 if (inst
.instruction
<= 0xffff
14112 && inst
.size_req
!= 4
14113 && Rd
<= 7 && Rm
<= 7
14114 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14116 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14117 inst
.instruction
|= Rd
;
14118 inst
.instruction
|= Rm
<< 3;
14120 else if (unified_syntax
)
14122 if (inst
.instruction
<= 0xffff)
14123 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14124 inst
.instruction
|= Rd
<< 8;
14125 inst
.instruction
|= Rm
;
14126 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14130 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14131 _("Thumb encoding does not support rotation"));
14132 constraint (1, BAD_HIREG
);
14139 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14148 half
= (inst
.instruction
& 0x10) != 0;
14149 set_pred_insn_type_last ();
14150 constraint (inst
.operands
[0].immisreg
,
14151 _("instruction requires register index"));
14153 Rn
= inst
.operands
[0].reg
;
14154 Rm
= inst
.operands
[0].imm
;
14156 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14157 constraint (Rn
== REG_SP
, BAD_SP
);
14158 reject_bad_reg (Rm
);
14160 constraint (!half
&& inst
.operands
[0].shifted
,
14161 _("instruction does not allow shifted index"));
14162 inst
.instruction
|= (Rn
<< 16) | Rm
;
14168 if (!inst
.operands
[0].present
)
14169 inst
.operands
[0].imm
= 0;
14171 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14173 constraint (inst
.size_req
== 2,
14174 _("immediate value out of range"));
14175 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14176 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14177 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14181 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14182 inst
.instruction
|= inst
.operands
[0].imm
;
14185 set_pred_insn_type (NEUTRAL_IT_INSN
);
14192 do_t_ssat_usat (0);
14200 Rd
= inst
.operands
[0].reg
;
14201 Rn
= inst
.operands
[2].reg
;
14203 reject_bad_reg (Rd
);
14204 reject_bad_reg (Rn
);
14206 inst
.instruction
|= Rd
<< 8;
14207 inst
.instruction
|= inst
.operands
[1].imm
;
14208 inst
.instruction
|= Rn
<< 16;
14211 /* Checking the range of the branch offset (VAL) with NBITS bits
14212 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14214 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14216 gas_assert (nbits
> 0 && nbits
<= 32);
14219 int cmp
= (1 << (nbits
- 1));
14220 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14225 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14231 /* For branches in Armv8.1-M Mainline. */
14233 do_t_branch_future (void)
14235 unsigned long insn
= inst
.instruction
;
14237 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14238 if (inst
.operands
[0].hasreloc
== 0)
14240 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14241 as_bad (BAD_BRANCH_OFF
);
14243 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14247 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14248 inst
.relocs
[0].pc_rel
= 1;
14254 if (inst
.operands
[1].hasreloc
== 0)
14256 int val
= inst
.operands
[1].imm
;
14257 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14258 as_bad (BAD_BRANCH_OFF
);
14260 int immA
= (val
& 0x0001f000) >> 12;
14261 int immB
= (val
& 0x00000ffc) >> 2;
14262 int immC
= (val
& 0x00000002) >> 1;
14263 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14267 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14268 inst
.relocs
[1].pc_rel
= 1;
14273 if (inst
.operands
[1].hasreloc
== 0)
14275 int val
= inst
.operands
[1].imm
;
14276 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14277 as_bad (BAD_BRANCH_OFF
);
14279 int immA
= (val
& 0x0007f000) >> 12;
14280 int immB
= (val
& 0x00000ffc) >> 2;
14281 int immC
= (val
& 0x00000002) >> 1;
14282 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14286 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14287 inst
.relocs
[1].pc_rel
= 1;
14291 case T_MNEM_bfcsel
:
14293 if (inst
.operands
[1].hasreloc
== 0)
14295 int val
= inst
.operands
[1].imm
;
14296 int immA
= (val
& 0x00001000) >> 12;
14297 int immB
= (val
& 0x00000ffc) >> 2;
14298 int immC
= (val
& 0x00000002) >> 1;
14299 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14303 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14304 inst
.relocs
[1].pc_rel
= 1;
14308 if (inst
.operands
[2].hasreloc
== 0)
14310 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14311 int val2
= inst
.operands
[2].imm
;
14312 int val0
= inst
.operands
[0].imm
& 0x1f;
14313 int diff
= val2
- val0
;
14315 inst
.instruction
|= 1 << 17; /* T bit. */
14316 else if (diff
!= 2)
14317 as_bad (_("out of range label-relative fixup value"));
14321 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14322 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14323 inst
.relocs
[2].pc_rel
= 1;
14327 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14328 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14333 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14340 /* Helper function for do_t_loloop to handle relocations. */
14342 v8_1_loop_reloc (int is_le
)
14344 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14346 int value
= inst
.relocs
[0].exp
.X_add_number
;
14347 value
= (is_le
) ? -value
: value
;
14349 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14350 as_bad (BAD_BRANCH_OFF
);
14354 immh
= (value
& 0x00000ffc) >> 2;
14355 imml
= (value
& 0x00000002) >> 1;
14357 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14361 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14362 inst
.relocs
[0].pc_rel
= 1;
14366 /* For shifts with four operands in MVE. */
14368 do_mve_scalar_shift1 (void)
14370 unsigned int value
= inst
.operands
[2].imm
;
14372 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14373 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14375 /* Setting the bit for saturation. */
14376 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14378 /* Assuming Rm is already checked not to be 11x1. */
14379 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14380 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14381 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14384 /* For shifts in MVE. */
14386 do_mve_scalar_shift (void)
14388 if (!inst
.operands
[2].present
)
14390 inst
.operands
[2] = inst
.operands
[1];
14391 inst
.operands
[1].reg
= 0xf;
14394 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14395 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14397 if (inst
.operands
[2].isreg
)
14399 /* Assuming Rm is already checked not to be 11x1. */
14400 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14401 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14402 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14406 /* Assuming imm is already checked as [1,32]. */
14407 unsigned int value
= inst
.operands
[2].imm
;
14408 inst
.instruction
|= (value
& 0x1c) << 10;
14409 inst
.instruction
|= (value
& 0x03) << 6;
14410 /* Change last 4 bits from 0xd to 0xf. */
14411 inst
.instruction
|= 0x2;
14415 /* MVE instruction encoder helpers. */
14416 #define M_MNEM_vabav 0xee800f01
14417 #define M_MNEM_vmladav 0xeef00e00
14418 #define M_MNEM_vmladava 0xeef00e20
14419 #define M_MNEM_vmladavx 0xeef01e00
14420 #define M_MNEM_vmladavax 0xeef01e20
14421 #define M_MNEM_vmlsdav 0xeef00e01
14422 #define M_MNEM_vmlsdava 0xeef00e21
14423 #define M_MNEM_vmlsdavx 0xeef01e01
14424 #define M_MNEM_vmlsdavax 0xeef01e21
14425 #define M_MNEM_vmullt 0xee011e00
14426 #define M_MNEM_vmullb 0xee010e00
14427 #define M_MNEM_vctp 0xf000e801
14428 #define M_MNEM_vst20 0xfc801e00
14429 #define M_MNEM_vst21 0xfc801e20
14430 #define M_MNEM_vst40 0xfc801e01
14431 #define M_MNEM_vst41 0xfc801e21
14432 #define M_MNEM_vst42 0xfc801e41
14433 #define M_MNEM_vst43 0xfc801e61
14434 #define M_MNEM_vld20 0xfc901e00
14435 #define M_MNEM_vld21 0xfc901e20
14436 #define M_MNEM_vld40 0xfc901e01
14437 #define M_MNEM_vld41 0xfc901e21
14438 #define M_MNEM_vld42 0xfc901e41
14439 #define M_MNEM_vld43 0xfc901e61
14440 #define M_MNEM_vstrb 0xec000e00
14441 #define M_MNEM_vstrh 0xec000e10
14442 #define M_MNEM_vstrw 0xec000e40
14443 #define M_MNEM_vstrd 0xec000e50
14444 #define M_MNEM_vldrb 0xec100e00
14445 #define M_MNEM_vldrh 0xec100e10
14446 #define M_MNEM_vldrw 0xec100e40
14447 #define M_MNEM_vldrd 0xec100e50
14448 #define M_MNEM_vmovlt 0xeea01f40
14449 #define M_MNEM_vmovlb 0xeea00f40
14450 #define M_MNEM_vmovnt 0xfe311e81
14451 #define M_MNEM_vmovnb 0xfe310e81
14452 #define M_MNEM_vadc 0xee300f00
14453 #define M_MNEM_vadci 0xee301f00
14454 #define M_MNEM_vbrsr 0xfe011e60
14455 #define M_MNEM_vaddlv 0xee890f00
14456 #define M_MNEM_vaddlva 0xee890f20
14457 #define M_MNEM_vaddv 0xeef10f00
14458 #define M_MNEM_vaddva 0xeef10f20
14459 #define M_MNEM_vddup 0xee011f6e
14460 #define M_MNEM_vdwdup 0xee011f60
14461 #define M_MNEM_vidup 0xee010f6e
14462 #define M_MNEM_viwdup 0xee010f60
14463 #define M_MNEM_vmaxv 0xeee20f00
14464 #define M_MNEM_vmaxav 0xeee00f00
14465 #define M_MNEM_vminv 0xeee20f80
14466 #define M_MNEM_vminav 0xeee00f80
14467 #define M_MNEM_vmlaldav 0xee800e00
14468 #define M_MNEM_vmlaldava 0xee800e20
14469 #define M_MNEM_vmlaldavx 0xee801e00
14470 #define M_MNEM_vmlaldavax 0xee801e20
14471 #define M_MNEM_vmlsldav 0xee800e01
14472 #define M_MNEM_vmlsldava 0xee800e21
14473 #define M_MNEM_vmlsldavx 0xee801e01
14474 #define M_MNEM_vmlsldavax 0xee801e21
14475 #define M_MNEM_vrmlaldavhx 0xee801f00
14476 #define M_MNEM_vrmlaldavhax 0xee801f20
14477 #define M_MNEM_vrmlsldavh 0xfe800e01
14478 #define M_MNEM_vrmlsldavha 0xfe800e21
14479 #define M_MNEM_vrmlsldavhx 0xfe801e01
14480 #define M_MNEM_vrmlsldavhax 0xfe801e21
14481 #define M_MNEM_vqmovnt 0xee331e01
14482 #define M_MNEM_vqmovnb 0xee330e01
14483 #define M_MNEM_vqmovunt 0xee311e81
14484 #define M_MNEM_vqmovunb 0xee310e81
14485 #define M_MNEM_vshrnt 0xee801fc1
14486 #define M_MNEM_vshrnb 0xee800fc1
14487 #define M_MNEM_vrshrnt 0xfe801fc1
14488 #define M_MNEM_vqshrnt 0xee801f40
14489 #define M_MNEM_vqshrnb 0xee800f40
14490 #define M_MNEM_vqshrunt 0xee801fc0
14491 #define M_MNEM_vqshrunb 0xee800fc0
14492 #define M_MNEM_vrshrnb 0xfe800fc1
14493 #define M_MNEM_vqrshrnt 0xee801f41
14494 #define M_MNEM_vqrshrnb 0xee800f41
14495 #define M_MNEM_vqrshrunt 0xfe801fc0
14496 #define M_MNEM_vqrshrunb 0xfe800fc0
14498 /* Neon instruction encoder helpers. */
14500 /* Encodings for the different types for various Neon opcodes. */
14502 /* An "invalid" code for the following tables. */
14505 struct neon_tab_entry
14508 unsigned float_or_poly
;
14509 unsigned scalar_or_imm
;
14512 /* Map overloaded Neon opcodes to their respective encodings. */
14513 #define NEON_ENC_TAB \
14514 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14515 X(vabdl, 0x0800700, N_INV, N_INV), \
14516 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14517 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14518 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14519 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14520 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14521 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14522 X(vaddl, 0x0800000, N_INV, N_INV), \
14523 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14524 X(vsubl, 0x0800200, N_INV, N_INV), \
14525 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14526 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14527 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14528 /* Register variants of the following two instructions are encoded as
14529 vcge / vcgt with the operands reversed. */ \
14530 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14531 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14532 X(vfma, N_INV, 0x0000c10, N_INV), \
14533 X(vfms, N_INV, 0x0200c10, N_INV), \
14534 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14535 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14536 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14537 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14538 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14539 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14540 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14541 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14542 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14543 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14544 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14545 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14546 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14547 X(vshl, 0x0000400, N_INV, 0x0800510), \
14548 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14549 X(vand, 0x0000110, N_INV, 0x0800030), \
14550 X(vbic, 0x0100110, N_INV, 0x0800030), \
14551 X(veor, 0x1000110, N_INV, N_INV), \
14552 X(vorn, 0x0300110, N_INV, 0x0800010), \
14553 X(vorr, 0x0200110, N_INV, 0x0800010), \
14554 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14555 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14556 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14557 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14558 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14559 X(vst1, 0x0000000, 0x0800000, N_INV), \
14560 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14561 X(vst2, 0x0000100, 0x0800100, N_INV), \
14562 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14563 X(vst3, 0x0000200, 0x0800200, N_INV), \
14564 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14565 X(vst4, 0x0000300, 0x0800300, N_INV), \
14566 X(vmovn, 0x1b20200, N_INV, N_INV), \
14567 X(vtrn, 0x1b20080, N_INV, N_INV), \
14568 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14569 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14570 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14571 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14572 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14573 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14574 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14575 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14576 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14577 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14578 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14579 X(vseleq, 0xe000a00, N_INV, N_INV), \
14580 X(vselvs, 0xe100a00, N_INV, N_INV), \
14581 X(vselge, 0xe200a00, N_INV, N_INV), \
14582 X(vselgt, 0xe300a00, N_INV, N_INV), \
14583 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14584 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14585 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14586 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14587 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14588 X(aes, 0x3b00300, N_INV, N_INV), \
14589 X(sha3op, 0x2000c00, N_INV, N_INV), \
14590 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14591 X(sha2op, 0x3ba0380, N_INV, N_INV)
14595 #define X(OPC,I,F,S) N_MNEM_##OPC
14600 static const struct neon_tab_entry neon_enc_tab
[] =
14602 #define X(OPC,I,F,S) { (I), (F), (S) }
14607 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14608 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14609 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14610 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14611 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14612 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14613 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14614 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14615 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14616 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14617 #define NEON_ENC_SINGLE_(X) \
14618 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14619 #define NEON_ENC_DOUBLE_(X) \
14620 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14621 #define NEON_ENC_FPV8_(X) \
14622 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14624 #define NEON_ENCODE(type, inst) \
14627 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14628 inst.is_neon = 1; \
14632 #define check_neon_suffixes \
14635 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14637 as_bad (_("invalid neon suffix for non neon instruction")); \
14643 /* Define shapes for instruction operands. The following mnemonic characters
14644 are used in this table:
14646 F - VFP S<n> register
14647 D - Neon D<n> register
14648 Q - Neon Q<n> register
14652 L - D<n> register list
14654 This table is used to generate various data:
14655 - enumerations of the form NS_DDR to be used as arguments to
14657 - a table classifying shapes into single, double, quad, mixed.
14658 - a table used to drive neon_select_shape. */
14660 #define NEON_SHAPE_DEF \
14661 X(4, (R, R, Q, Q), QUAD), \
14662 X(4, (Q, R, R, I), QUAD), \
14663 X(4, (R, R, S, S), QUAD), \
14664 X(4, (S, S, R, R), QUAD), \
14665 X(3, (Q, R, I), QUAD), \
14666 X(3, (I, Q, Q), QUAD), \
14667 X(3, (I, Q, R), QUAD), \
14668 X(3, (R, Q, Q), QUAD), \
14669 X(3, (D, D, D), DOUBLE), \
14670 X(3, (Q, Q, Q), QUAD), \
14671 X(3, (D, D, I), DOUBLE), \
14672 X(3, (Q, Q, I), QUAD), \
14673 X(3, (D, D, S), DOUBLE), \
14674 X(3, (Q, Q, S), QUAD), \
14675 X(3, (Q, Q, R), QUAD), \
14676 X(3, (R, R, Q), QUAD), \
14677 X(2, (R, Q), QUAD), \
14678 X(2, (D, D), DOUBLE), \
14679 X(2, (Q, Q), QUAD), \
14680 X(2, (D, S), DOUBLE), \
14681 X(2, (Q, S), QUAD), \
14682 X(2, (D, R), DOUBLE), \
14683 X(2, (Q, R), QUAD), \
14684 X(2, (D, I), DOUBLE), \
14685 X(2, (Q, I), QUAD), \
14686 X(3, (D, L, D), DOUBLE), \
14687 X(2, (D, Q), MIXED), \
14688 X(2, (Q, D), MIXED), \
14689 X(3, (D, Q, I), MIXED), \
14690 X(3, (Q, D, I), MIXED), \
14691 X(3, (Q, D, D), MIXED), \
14692 X(3, (D, Q, Q), MIXED), \
14693 X(3, (Q, Q, D), MIXED), \
14694 X(3, (Q, D, S), MIXED), \
14695 X(3, (D, Q, S), MIXED), \
14696 X(4, (D, D, D, I), DOUBLE), \
14697 X(4, (Q, Q, Q, I), QUAD), \
14698 X(4, (D, D, S, I), DOUBLE), \
14699 X(4, (Q, Q, S, I), QUAD), \
14700 X(2, (F, F), SINGLE), \
14701 X(3, (F, F, F), SINGLE), \
14702 X(2, (F, I), SINGLE), \
14703 X(2, (F, D), MIXED), \
14704 X(2, (D, F), MIXED), \
14705 X(3, (F, F, I), MIXED), \
14706 X(4, (R, R, F, F), SINGLE), \
14707 X(4, (F, F, R, R), SINGLE), \
14708 X(3, (D, R, R), DOUBLE), \
14709 X(3, (R, R, D), DOUBLE), \
14710 X(2, (S, R), SINGLE), \
14711 X(2, (R, S), SINGLE), \
14712 X(2, (F, R), SINGLE), \
14713 X(2, (R, F), SINGLE), \
14714 /* Used for MVE tail predicated loop instructions. */\
14715 X(2, (R, R), QUAD), \
14716 /* Half float shape supported so far. */\
14717 X (2, (H, D), MIXED), \
14718 X (2, (D, H), MIXED), \
14719 X (2, (H, F), MIXED), \
14720 X (2, (F, H), MIXED), \
14721 X (2, (H, H), HALF), \
14722 X (2, (H, R), HALF), \
14723 X (2, (R, H), HALF), \
14724 X (2, (H, I), HALF), \
14725 X (3, (H, H, H), HALF), \
14726 X (3, (H, F, I), MIXED), \
14727 X (3, (F, H, I), MIXED), \
14728 X (3, (D, H, H), MIXED), \
14729 X (3, (D, H, S), MIXED)
14731 #define S2(A,B) NS_##A##B
14732 #define S3(A,B,C) NS_##A##B##C
14733 #define S4(A,B,C,D) NS_##A##B##C##D
14735 #define X(N, L, C) S##N L
14748 enum neon_shape_class
14757 #define X(N, L, C) SC_##C
14759 static enum neon_shape_class neon_shape_class
[] =
14778 /* Register widths of above. */
14779 static unsigned neon_shape_el_size
[] =
14791 struct neon_shape_info
14794 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14797 #define S2(A,B) { SE_##A, SE_##B }
14798 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14799 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14801 #define X(N, L, C) { N, S##N L }
14803 static struct neon_shape_info neon_shape_tab
[] =
14813 /* Bit masks used in type checking given instructions.
14814 'N_EQK' means the type must be the same as (or based on in some way) the key
14815 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14816 set, various other bits can be set as well in order to modify the meaning of
14817 the type constraint. */
14819 enum neon_type_mask
14843 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14844 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14845 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14846 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14847 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14848 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14849 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14850 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14851 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14852 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14853 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14855 N_MAX_NONSPECIAL
= N_P64
14858 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14860 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14861 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14862 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14863 #define N_S_32 (N_S8 | N_S16 | N_S32)
14864 #define N_F_16_32 (N_F16 | N_F32)
14865 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14866 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14867 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14868 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14869 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14870 #define N_F_MVE (N_F16 | N_F32)
14871 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14873 /* Pass this as the first type argument to neon_check_type to ignore types
14875 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14877 /* Select a "shape" for the current instruction (describing register types or
14878 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14879 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14880 function of operand parsing, so this function doesn't need to be called.
14881 Shapes should be listed in order of decreasing length. */
14883 static enum neon_shape
14884 neon_select_shape (enum neon_shape shape
, ...)
14887 enum neon_shape first_shape
= shape
;
14889 /* Fix missing optional operands. FIXME: we don't know at this point how
14890 many arguments we should have, so this makes the assumption that we have
14891 > 1. This is true of all current Neon opcodes, I think, but may not be
14892 true in the future. */
14893 if (!inst
.operands
[1].present
)
14894 inst
.operands
[1] = inst
.operands
[0];
14896 va_start (ap
, shape
);
14898 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14903 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14905 if (!inst
.operands
[j
].present
)
14911 switch (neon_shape_tab
[shape
].el
[j
])
14913 /* If a .f16, .16, .u16, .s16 type specifier is given over
14914 a VFP single precision register operand, it's essentially
14915 means only half of the register is used.
14917 If the type specifier is given after the mnemonics, the
14918 information is stored in inst.vectype. If the type specifier
14919 is given after register operand, the information is stored
14920 in inst.operands[].vectype.
14922 When there is only one type specifier, and all the register
14923 operands are the same type of hardware register, the type
14924 specifier applies to all register operands.
14926 If no type specifier is given, the shape is inferred from
14927 operand information.
14930 vadd.f16 s0, s1, s2: NS_HHH
14931 vabs.f16 s0, s1: NS_HH
14932 vmov.f16 s0, r1: NS_HR
14933 vmov.f16 r0, s1: NS_RH
14934 vcvt.f16 r0, s1: NS_RH
14935 vcvt.f16.s32 s2, s2, #29: NS_HFI
14936 vcvt.f16.s32 s2, s2: NS_HF
14939 if (!(inst
.operands
[j
].isreg
14940 && inst
.operands
[j
].isvec
14941 && inst
.operands
[j
].issingle
14942 && !inst
.operands
[j
].isquad
14943 && ((inst
.vectype
.elems
== 1
14944 && inst
.vectype
.el
[0].size
== 16)
14945 || (inst
.vectype
.elems
> 1
14946 && inst
.vectype
.el
[j
].size
== 16)
14947 || (inst
.vectype
.elems
== 0
14948 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14949 && inst
.operands
[j
].vectype
.size
== 16))))
14954 if (!(inst
.operands
[j
].isreg
14955 && inst
.operands
[j
].isvec
14956 && inst
.operands
[j
].issingle
14957 && !inst
.operands
[j
].isquad
14958 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14959 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14960 || (inst
.vectype
.elems
== 0
14961 && (inst
.operands
[j
].vectype
.size
== 32
14962 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14967 if (!(inst
.operands
[j
].isreg
14968 && inst
.operands
[j
].isvec
14969 && !inst
.operands
[j
].isquad
14970 && !inst
.operands
[j
].issingle
))
14975 if (!(inst
.operands
[j
].isreg
14976 && !inst
.operands
[j
].isvec
))
14981 if (!(inst
.operands
[j
].isreg
14982 && inst
.operands
[j
].isvec
14983 && inst
.operands
[j
].isquad
14984 && !inst
.operands
[j
].issingle
))
14989 if (!(!inst
.operands
[j
].isreg
14990 && !inst
.operands
[j
].isscalar
))
14995 if (!(!inst
.operands
[j
].isreg
14996 && inst
.operands
[j
].isscalar
))
15006 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15007 /* We've matched all the entries in the shape table, and we don't
15008 have any left over operands which have not been matched. */
15014 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15015 first_error (_("invalid instruction shape"));
15020 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15021 means the Q bit should be set). */
15024 neon_quad (enum neon_shape shape
)
15026 return neon_shape_class
[shape
] == SC_QUAD
;
15030 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15033 /* Allow modification to be made to types which are constrained to be
15034 based on the key element, based on bits set alongside N_EQK. */
15035 if ((typebits
& N_EQK
) != 0)
15037 if ((typebits
& N_HLF
) != 0)
15039 else if ((typebits
& N_DBL
) != 0)
15041 if ((typebits
& N_SGN
) != 0)
15042 *g_type
= NT_signed
;
15043 else if ((typebits
& N_UNS
) != 0)
15044 *g_type
= NT_unsigned
;
15045 else if ((typebits
& N_INT
) != 0)
15046 *g_type
= NT_integer
;
15047 else if ((typebits
& N_FLT
) != 0)
15048 *g_type
= NT_float
;
15049 else if ((typebits
& N_SIZ
) != 0)
15050 *g_type
= NT_untyped
;
15054 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15055 operand type, i.e. the single type specified in a Neon instruction when it
15056 is the only one given. */
15058 static struct neon_type_el
15059 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15061 struct neon_type_el dest
= *key
;
15063 gas_assert ((thisarg
& N_EQK
) != 0);
15065 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15070 /* Convert Neon type and size into compact bitmask representation. */
15072 static enum neon_type_mask
15073 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15080 case 8: return N_8
;
15081 case 16: return N_16
;
15082 case 32: return N_32
;
15083 case 64: return N_64
;
15091 case 8: return N_I8
;
15092 case 16: return N_I16
;
15093 case 32: return N_I32
;
15094 case 64: return N_I64
;
15102 case 16: return N_F16
;
15103 case 32: return N_F32
;
15104 case 64: return N_F64
;
15112 case 8: return N_P8
;
15113 case 16: return N_P16
;
15114 case 64: return N_P64
;
15122 case 8: return N_S8
;
15123 case 16: return N_S16
;
15124 case 32: return N_S32
;
15125 case 64: return N_S64
;
15133 case 8: return N_U8
;
15134 case 16: return N_U16
;
15135 case 32: return N_U32
;
15136 case 64: return N_U64
;
15147 /* Convert compact Neon bitmask type representation to a type and size. Only
15148 handles the case where a single bit is set in the mask. */
15151 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15152 enum neon_type_mask mask
)
15154 if ((mask
& N_EQK
) != 0)
15157 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15159 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
15161 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15163 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15168 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15170 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15171 *type
= NT_unsigned
;
15172 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15173 *type
= NT_integer
;
15174 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15175 *type
= NT_untyped
;
15176 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15178 else if ((mask
& (N_F_ALL
)) != 0)
15186 /* Modify a bitmask of allowed types. This is only needed for type
15190 modify_types_allowed (unsigned allowed
, unsigned mods
)
15193 enum neon_el_type type
;
15199 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15201 if (el_type_of_type_chk (&type
, &size
,
15202 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15204 neon_modify_type_size (mods
, &type
, &size
);
15205 destmask
|= type_chk_of_el_type (type
, size
);
15212 /* Check type and return type classification.
15213 The manual states (paraphrase): If one datatype is given, it indicates the
15215 - the second operand, if there is one
15216 - the operand, if there is no second operand
15217 - the result, if there are no operands.
15218 This isn't quite good enough though, so we use a concept of a "key" datatype
15219 which is set on a per-instruction basis, which is the one which matters when
15220 only one data type is written.
15221 Note: this function has side-effects (e.g. filling in missing operands). All
15222 Neon instructions should call it before performing bit encoding. */
15224 static struct neon_type_el
15225 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15228 unsigned i
, pass
, key_el
= 0;
15229 unsigned types
[NEON_MAX_TYPE_ELS
];
15230 enum neon_el_type k_type
= NT_invtype
;
15231 unsigned k_size
= -1u;
15232 struct neon_type_el badtype
= {NT_invtype
, -1};
15233 unsigned key_allowed
= 0;
15235 /* Optional registers in Neon instructions are always (not) in operand 1.
15236 Fill in the missing operand here, if it was omitted. */
15237 if (els
> 1 && !inst
.operands
[1].present
)
15238 inst
.operands
[1] = inst
.operands
[0];
15240 /* Suck up all the varargs. */
15242 for (i
= 0; i
< els
; i
++)
15244 unsigned thisarg
= va_arg (ap
, unsigned);
15245 if (thisarg
== N_IGNORE_TYPE
)
15250 types
[i
] = thisarg
;
15251 if ((thisarg
& N_KEY
) != 0)
15256 if (inst
.vectype
.elems
> 0)
15257 for (i
= 0; i
< els
; i
++)
15258 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15260 first_error (_("types specified in both the mnemonic and operands"));
15264 /* Duplicate inst.vectype elements here as necessary.
15265 FIXME: No idea if this is exactly the same as the ARM assembler,
15266 particularly when an insn takes one register and one non-register
15268 if (inst
.vectype
.elems
== 1 && els
> 1)
15271 inst
.vectype
.elems
= els
;
15272 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15273 for (j
= 0; j
< els
; j
++)
15275 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15278 else if (inst
.vectype
.elems
== 0 && els
> 0)
15281 /* No types were given after the mnemonic, so look for types specified
15282 after each operand. We allow some flexibility here; as long as the
15283 "key" operand has a type, we can infer the others. */
15284 for (j
= 0; j
< els
; j
++)
15285 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15286 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15288 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15290 for (j
= 0; j
< els
; j
++)
15291 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15292 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15297 first_error (_("operand types can't be inferred"));
15301 else if (inst
.vectype
.elems
!= els
)
15303 first_error (_("type specifier has the wrong number of parts"));
15307 for (pass
= 0; pass
< 2; pass
++)
15309 for (i
= 0; i
< els
; i
++)
15311 unsigned thisarg
= types
[i
];
15312 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15313 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15314 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15315 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15317 /* Decay more-specific signed & unsigned types to sign-insensitive
15318 integer types if sign-specific variants are unavailable. */
15319 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15320 && (types_allowed
& N_SU_ALL
) == 0)
15321 g_type
= NT_integer
;
15323 /* If only untyped args are allowed, decay any more specific types to
15324 them. Some instructions only care about signs for some element
15325 sizes, so handle that properly. */
15326 if (((types_allowed
& N_UNT
) == 0)
15327 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15328 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15329 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15330 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15331 g_type
= NT_untyped
;
15335 if ((thisarg
& N_KEY
) != 0)
15339 key_allowed
= thisarg
& ~N_KEY
;
15341 /* Check architecture constraint on FP16 extension. */
15343 && k_type
== NT_float
15344 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15346 inst
.error
= _(BAD_FP16
);
15353 if ((thisarg
& N_VFP
) != 0)
15355 enum neon_shape_el regshape
;
15356 unsigned regwidth
, match
;
15358 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15361 first_error (_("invalid instruction shape"));
15364 regshape
= neon_shape_tab
[ns
].el
[i
];
15365 regwidth
= neon_shape_el_size
[regshape
];
15367 /* In VFP mode, operands must match register widths. If we
15368 have a key operand, use its width, else use the width of
15369 the current operand. */
15375 /* FP16 will use a single precision register. */
15376 if (regwidth
== 32 && match
== 16)
15378 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15382 inst
.error
= _(BAD_FP16
);
15387 if (regwidth
!= match
)
15389 first_error (_("operand size must match register width"));
15394 if ((thisarg
& N_EQK
) == 0)
15396 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15398 if ((given_type
& types_allowed
) == 0)
15400 first_error (BAD_SIMD_TYPE
);
15406 enum neon_el_type mod_k_type
= k_type
;
15407 unsigned mod_k_size
= k_size
;
15408 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15409 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15411 first_error (_("inconsistent types in Neon instruction"));
15419 return inst
.vectype
.el
[key_el
];
15422 /* Neon-style VFP instruction forwarding. */
15424 /* Thumb VFP instructions have 0xE in the condition field. */
15427 do_vfp_cond_or_thumb (void)
15432 inst
.instruction
|= 0xe0000000;
15434 inst
.instruction
|= inst
.cond
<< 28;
15437 /* Look up and encode a simple mnemonic, for use as a helper function for the
15438 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15439 etc. It is assumed that operand parsing has already been done, and that the
15440 operands are in the form expected by the given opcode (this isn't necessarily
15441 the same as the form in which they were parsed, hence some massaging must
15442 take place before this function is called).
15443 Checks current arch version against that in the looked-up opcode. */
15446 do_vfp_nsyn_opcode (const char *opname
)
15448 const struct asm_opcode
*opcode
;
15450 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15455 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15456 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15463 inst
.instruction
= opcode
->tvalue
;
15464 opcode
->tencode ();
15468 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15469 opcode
->aencode ();
15474 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15476 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15478 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15481 do_vfp_nsyn_opcode ("fadds");
15483 do_vfp_nsyn_opcode ("fsubs");
15485 /* ARMv8.2 fp16 instruction. */
15487 do_scalar_fp16_v82_encode ();
15492 do_vfp_nsyn_opcode ("faddd");
15494 do_vfp_nsyn_opcode ("fsubd");
15498 /* Check operand types to see if this is a VFP instruction, and if so call
15502 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15504 enum neon_shape rs
;
15505 struct neon_type_el et
;
15510 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15511 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15515 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15516 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15517 N_F_ALL
| N_KEY
| N_VFP
);
15524 if (et
.type
!= NT_invtype
)
15535 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15537 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15539 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15542 do_vfp_nsyn_opcode ("fmacs");
15544 do_vfp_nsyn_opcode ("fnmacs");
15546 /* ARMv8.2 fp16 instruction. */
15548 do_scalar_fp16_v82_encode ();
15553 do_vfp_nsyn_opcode ("fmacd");
15555 do_vfp_nsyn_opcode ("fnmacd");
15560 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15562 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15564 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15567 do_vfp_nsyn_opcode ("ffmas");
15569 do_vfp_nsyn_opcode ("ffnmas");
15571 /* ARMv8.2 fp16 instruction. */
15573 do_scalar_fp16_v82_encode ();
15578 do_vfp_nsyn_opcode ("ffmad");
15580 do_vfp_nsyn_opcode ("ffnmad");
15585 do_vfp_nsyn_mul (enum neon_shape rs
)
15587 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15589 do_vfp_nsyn_opcode ("fmuls");
15591 /* ARMv8.2 fp16 instruction. */
15593 do_scalar_fp16_v82_encode ();
15596 do_vfp_nsyn_opcode ("fmuld");
15600 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15602 int is_neg
= (inst
.instruction
& 0x80) != 0;
15603 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15605 if (rs
== NS_FF
|| rs
== NS_HH
)
15608 do_vfp_nsyn_opcode ("fnegs");
15610 do_vfp_nsyn_opcode ("fabss");
15612 /* ARMv8.2 fp16 instruction. */
15614 do_scalar_fp16_v82_encode ();
15619 do_vfp_nsyn_opcode ("fnegd");
15621 do_vfp_nsyn_opcode ("fabsd");
15625 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15626 insns belong to Neon, and are handled elsewhere. */
15629 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15631 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15635 do_vfp_nsyn_opcode ("fldmdbs");
15637 do_vfp_nsyn_opcode ("fldmias");
15642 do_vfp_nsyn_opcode ("fstmdbs");
15644 do_vfp_nsyn_opcode ("fstmias");
15649 do_vfp_nsyn_sqrt (void)
15651 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15652 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15654 if (rs
== NS_FF
|| rs
== NS_HH
)
15656 do_vfp_nsyn_opcode ("fsqrts");
15658 /* ARMv8.2 fp16 instruction. */
15660 do_scalar_fp16_v82_encode ();
15663 do_vfp_nsyn_opcode ("fsqrtd");
15667 do_vfp_nsyn_div (void)
15669 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15670 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15671 N_F_ALL
| N_KEY
| N_VFP
);
15673 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15675 do_vfp_nsyn_opcode ("fdivs");
15677 /* ARMv8.2 fp16 instruction. */
15679 do_scalar_fp16_v82_encode ();
15682 do_vfp_nsyn_opcode ("fdivd");
15686 do_vfp_nsyn_nmul (void)
15688 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15689 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15690 N_F_ALL
| N_KEY
| N_VFP
);
15692 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15694 NEON_ENCODE (SINGLE
, inst
);
15695 do_vfp_sp_dyadic ();
15697 /* ARMv8.2 fp16 instruction. */
15699 do_scalar_fp16_v82_encode ();
15703 NEON_ENCODE (DOUBLE
, inst
);
15704 do_vfp_dp_rd_rn_rm ();
15706 do_vfp_cond_or_thumb ();
15710 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15714 neon_logbits (unsigned x
)
15716 return ffs (x
) - 4;
15719 #define LOW4(R) ((R) & 0xf)
15720 #define HI1(R) (((R) >> 4) & 1)
15723 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15728 first_error (BAD_EL_TYPE
);
15731 switch (inst
.operands
[0].imm
)
15734 first_error (_("invalid condition"));
15756 /* only accept eq and ne. */
15757 if (inst
.operands
[0].imm
> 1)
15759 first_error (_("invalid condition"));
15762 return inst
.operands
[0].imm
;
15764 if (inst
.operands
[0].imm
== 0x2)
15766 else if (inst
.operands
[0].imm
== 0x8)
15770 first_error (_("invalid condition"));
15774 switch (inst
.operands
[0].imm
)
15777 first_error (_("invalid condition"));
15793 /* Should be unreachable. */
15797 /* For VCTP (create vector tail predicate) in MVE. */
15802 unsigned size
= 0x0;
15804 if (inst
.cond
> COND_ALWAYS
)
15805 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15807 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15809 /* This is a typical MVE instruction which has no type but have size 8, 16,
15810 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15811 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15812 if ((inst
.operands
[0].present
) && (inst
.vectype
.el
[0].type
== NT_untyped
))
15813 dt
= inst
.vectype
.el
[0].size
;
15815 /* Setting this does not indicate an actual NEON instruction, but only
15816 indicates that the mnemonic accepts neon-style type suffixes. */
15830 first_error (_("Type is not allowed for this instruction"));
15832 inst
.instruction
|= size
<< 20;
15833 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15839 /* We are dealing with a vector predicated block. */
15840 if (inst
.operands
[0].present
)
15842 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15843 struct neon_type_el et
15844 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15847 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15849 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15851 if (et
.type
== NT_invtype
)
15854 if (et
.type
== NT_float
)
15856 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15858 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15859 inst
.instruction
|= (et
.size
== 16) << 28;
15860 inst
.instruction
|= 0x3 << 20;
15864 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15866 inst
.instruction
|= 1 << 28;
15867 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15870 if (inst
.operands
[2].isquad
)
15872 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15873 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15874 inst
.instruction
|= (fcond
& 0x2) >> 1;
15878 if (inst
.operands
[2].reg
== REG_SP
)
15879 as_tsktsk (MVE_BAD_SP
);
15880 inst
.instruction
|= 1 << 6;
15881 inst
.instruction
|= (fcond
& 0x2) << 4;
15882 inst
.instruction
|= inst
.operands
[2].reg
;
15884 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15885 inst
.instruction
|= (fcond
& 0x4) << 10;
15886 inst
.instruction
|= (fcond
& 0x1) << 7;
15889 set_pred_insn_type (VPT_INSN
);
15891 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15892 | ((inst
.instruction
& 0xe000) >> 13);
15893 now_pred
.warn_deprecated
= FALSE
;
15894 now_pred
.type
= VECTOR_PRED
;
15901 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15902 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15903 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15904 if (!inst
.operands
[2].present
)
15905 first_error (_("MVE vector or ARM register expected"));
15906 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15908 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15909 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15910 && inst
.operands
[1].isquad
)
15912 inst
.instruction
= N_MNEM_vcmp
;
15916 if (inst
.cond
> COND_ALWAYS
)
15917 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15919 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15921 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15922 struct neon_type_el et
15923 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15926 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15927 && !inst
.operands
[2].iszr
, BAD_PC
);
15929 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15931 inst
.instruction
= 0xee010f00;
15932 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15933 inst
.instruction
|= (fcond
& 0x4) << 10;
15934 inst
.instruction
|= (fcond
& 0x1) << 7;
15935 if (et
.type
== NT_float
)
15937 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15939 inst
.instruction
|= (et
.size
== 16) << 28;
15940 inst
.instruction
|= 0x3 << 20;
15944 inst
.instruction
|= 1 << 28;
15945 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15947 if (inst
.operands
[2].isquad
)
15949 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15950 inst
.instruction
|= (fcond
& 0x2) >> 1;
15951 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15955 if (inst
.operands
[2].reg
== REG_SP
)
15956 as_tsktsk (MVE_BAD_SP
);
15957 inst
.instruction
|= 1 << 6;
15958 inst
.instruction
|= (fcond
& 0x2) << 4;
15959 inst
.instruction
|= inst
.operands
[2].reg
;
15967 do_mve_vmaxa_vmina (void)
15969 if (inst
.cond
> COND_ALWAYS
)
15970 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15972 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15974 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15975 struct neon_type_el et
15976 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
15978 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15979 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15980 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15981 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15982 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15987 do_mve_vfmas (void)
15989 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15990 struct neon_type_el et
15991 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
15993 if (inst
.cond
> COND_ALWAYS
)
15994 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15996 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15998 if (inst
.operands
[2].reg
== REG_SP
)
15999 as_tsktsk (MVE_BAD_SP
);
16000 else if (inst
.operands
[2].reg
== REG_PC
)
16001 as_tsktsk (MVE_BAD_PC
);
16003 inst
.instruction
|= (et
.size
== 16) << 28;
16004 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16005 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16006 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16007 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16008 inst
.instruction
|= inst
.operands
[2].reg
;
16013 do_mve_viddup (void)
16015 if (inst
.cond
> COND_ALWAYS
)
16016 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16018 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16020 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
16021 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
16022 _("immediate must be either 1, 2, 4 or 8"));
16024 enum neon_shape rs
;
16025 struct neon_type_el et
;
16027 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
16029 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
16030 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
16035 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
16036 if (inst
.operands
[2].reg
== REG_SP
)
16037 as_tsktsk (MVE_BAD_SP
);
16038 else if (inst
.operands
[2].reg
== REG_PC
)
16039 first_error (BAD_PC
);
16041 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16042 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16043 Rm
= inst
.operands
[2].reg
>> 1;
16045 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16046 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16047 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16048 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16049 inst
.instruction
|= (imm
> 2) << 7;
16050 inst
.instruction
|= Rm
<< 1;
16051 inst
.instruction
|= (imm
== 2 || imm
== 8);
16056 do_mve_vmlas (void)
16058 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16059 struct neon_type_el et
16060 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16062 if (inst
.operands
[2].reg
== REG_PC
)
16063 as_tsktsk (MVE_BAD_PC
);
16064 else if (inst
.operands
[2].reg
== REG_SP
)
16065 as_tsktsk (MVE_BAD_SP
);
16067 if (inst
.cond
> COND_ALWAYS
)
16068 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16070 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16072 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16073 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16074 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16075 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16076 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16077 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16078 inst
.instruction
|= inst
.operands
[2].reg
;
16083 do_mve_vshll (void)
16085 struct neon_type_el et
16086 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16088 if (inst
.cond
> COND_ALWAYS
)
16089 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16091 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16093 int imm
= inst
.operands
[2].imm
;
16094 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16095 _("immediate value out of range"));
16097 if ((unsigned)imm
== et
.size
)
16099 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16100 inst
.instruction
|= 0x110001;
16104 inst
.instruction
|= (et
.size
+ imm
) << 16;
16105 inst
.instruction
|= 0x800140;
16108 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16109 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16110 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16111 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16112 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16117 do_mve_vshlc (void)
16119 if (inst
.cond
> COND_ALWAYS
)
16120 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16122 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16124 if (inst
.operands
[1].reg
== REG_PC
)
16125 as_tsktsk (MVE_BAD_PC
);
16126 else if (inst
.operands
[1].reg
== REG_SP
)
16127 as_tsktsk (MVE_BAD_SP
);
16129 int imm
= inst
.operands
[2].imm
;
16130 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16132 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16133 inst
.instruction
|= (imm
& 0x1f) << 16;
16134 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16135 inst
.instruction
|= inst
.operands
[1].reg
;
16140 do_mve_vshrn (void)
16143 switch (inst
.instruction
)
16145 case M_MNEM_vshrnt
:
16146 case M_MNEM_vshrnb
:
16147 case M_MNEM_vrshrnt
:
16148 case M_MNEM_vrshrnb
:
16149 types
= N_I16
| N_I32
;
16151 case M_MNEM_vqshrnt
:
16152 case M_MNEM_vqshrnb
:
16153 case M_MNEM_vqrshrnt
:
16154 case M_MNEM_vqrshrnb
:
16155 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16157 case M_MNEM_vqshrunt
:
16158 case M_MNEM_vqshrunb
:
16159 case M_MNEM_vqrshrunt
:
16160 case M_MNEM_vqrshrunb
:
16161 types
= N_S16
| N_S32
;
16167 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16169 if (inst
.cond
> COND_ALWAYS
)
16170 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16172 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16174 unsigned Qd
= inst
.operands
[0].reg
;
16175 unsigned Qm
= inst
.operands
[1].reg
;
16176 unsigned imm
= inst
.operands
[2].imm
;
16177 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16179 ? _("immediate operand expected in the range [1,8]")
16180 : _("immediate operand expected in the range [1,16]"));
16182 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16183 inst
.instruction
|= HI1 (Qd
) << 22;
16184 inst
.instruction
|= (et
.size
- imm
) << 16;
16185 inst
.instruction
|= LOW4 (Qd
) << 12;
16186 inst
.instruction
|= HI1 (Qm
) << 5;
16187 inst
.instruction
|= LOW4 (Qm
);
16192 do_mve_vqmovn (void)
16194 struct neon_type_el et
;
16195 if (inst
.instruction
== M_MNEM_vqmovnt
16196 || inst
.instruction
== M_MNEM_vqmovnb
)
16197 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16198 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16200 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16202 if (inst
.cond
> COND_ALWAYS
)
16203 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16205 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16207 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16208 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16209 inst
.instruction
|= (et
.size
== 32) << 18;
16210 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16211 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16212 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16217 do_mve_vpsel (void)
16219 neon_select_shape (NS_QQQ
, NS_NULL
);
16221 if (inst
.cond
> COND_ALWAYS
)
16222 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16224 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16226 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16227 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16228 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16229 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16230 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16231 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16236 do_mve_vpnot (void)
16238 if (inst
.cond
> COND_ALWAYS
)
16239 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16241 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16245 do_mve_vmaxnma_vminnma (void)
16247 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16248 struct neon_type_el et
16249 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16251 if (inst
.cond
> COND_ALWAYS
)
16252 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16254 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16256 inst
.instruction
|= (et
.size
== 16) << 28;
16257 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16258 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16259 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16260 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16265 do_mve_vcmul (void)
16267 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16268 struct neon_type_el et
16269 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16271 if (inst
.cond
> COND_ALWAYS
)
16272 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16274 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16276 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16277 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16278 _("immediate out of range"));
16280 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16281 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16282 as_tsktsk (BAD_MVE_SRCDEST
);
16284 inst
.instruction
|= (et
.size
== 32) << 28;
16285 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16286 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16287 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16288 inst
.instruction
|= (rot
> 90) << 12;
16289 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16290 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16291 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16292 inst
.instruction
|= (rot
== 90 || rot
== 270);
16296 /* To handle the Low Overhead Loop instructions
16297 in Armv8.1-M Mainline and MVE. */
16301 unsigned long insn
= inst
.instruction
;
16303 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16305 if (insn
== T_MNEM_lctp
)
16308 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16310 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16312 struct neon_type_el et
16313 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16314 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16321 constraint (!inst
.operands
[0].present
,
16323 /* fall through. */
16326 if (!inst
.operands
[0].present
)
16327 inst
.instruction
|= 1 << 21;
16329 v8_1_loop_reloc (TRUE
);
16334 v8_1_loop_reloc (FALSE
);
16335 /* fall through. */
16338 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16340 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16341 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16342 else if (inst
.operands
[1].reg
== REG_PC
)
16343 as_tsktsk (MVE_BAD_PC
);
16344 if (inst
.operands
[1].reg
== REG_SP
)
16345 as_tsktsk (MVE_BAD_SP
);
16347 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16357 do_vfp_nsyn_cmp (void)
16359 enum neon_shape rs
;
16360 if (!inst
.operands
[0].isreg
)
16367 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16368 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16372 if (inst
.operands
[1].isreg
)
16374 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16375 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16377 if (rs
== NS_FF
|| rs
== NS_HH
)
16379 NEON_ENCODE (SINGLE
, inst
);
16380 do_vfp_sp_monadic ();
16384 NEON_ENCODE (DOUBLE
, inst
);
16385 do_vfp_dp_rd_rm ();
16390 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16391 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16393 switch (inst
.instruction
& 0x0fffffff)
16396 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16399 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16405 if (rs
== NS_FI
|| rs
== NS_HI
)
16407 NEON_ENCODE (SINGLE
, inst
);
16408 do_vfp_sp_compare_z ();
16412 NEON_ENCODE (DOUBLE
, inst
);
16416 do_vfp_cond_or_thumb ();
16418 /* ARMv8.2 fp16 instruction. */
16419 if (rs
== NS_HI
|| rs
== NS_HH
)
16420 do_scalar_fp16_v82_encode ();
16424 nsyn_insert_sp (void)
16426 inst
.operands
[1] = inst
.operands
[0];
16427 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16428 inst
.operands
[0].reg
= REG_SP
;
16429 inst
.operands
[0].isreg
= 1;
16430 inst
.operands
[0].writeback
= 1;
16431 inst
.operands
[0].present
= 1;
16435 do_vfp_nsyn_push (void)
16439 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16440 _("register list must contain at least 1 and at most 16 "
16443 if (inst
.operands
[1].issingle
)
16444 do_vfp_nsyn_opcode ("fstmdbs");
16446 do_vfp_nsyn_opcode ("fstmdbd");
16450 do_vfp_nsyn_pop (void)
16454 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16455 _("register list must contain at least 1 and at most 16 "
16458 if (inst
.operands
[1].issingle
)
16459 do_vfp_nsyn_opcode ("fldmias");
16461 do_vfp_nsyn_opcode ("fldmiad");
16464 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16465 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16468 neon_dp_fixup (struct arm_it
* insn
)
16470 unsigned int i
= insn
->instruction
;
16475 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16486 insn
->instruction
= i
;
16490 mve_encode_qqr (int size
, int U
, int fp
)
16492 if (inst
.operands
[2].reg
== REG_SP
)
16493 as_tsktsk (MVE_BAD_SP
);
16494 else if (inst
.operands
[2].reg
== REG_PC
)
16495 as_tsktsk (MVE_BAD_PC
);
16500 if (((unsigned)inst
.instruction
) == 0xd00)
16501 inst
.instruction
= 0xee300f40;
16503 else if (((unsigned)inst
.instruction
) == 0x200d00)
16504 inst
.instruction
= 0xee301f40;
16506 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16507 inst
.instruction
= 0xee310e60;
16509 /* Setting size which is 1 for F16 and 0 for F32. */
16510 inst
.instruction
|= (size
== 16) << 28;
16515 if (((unsigned)inst
.instruction
) == 0x800)
16516 inst
.instruction
= 0xee010f40;
16518 else if (((unsigned)inst
.instruction
) == 0x1000800)
16519 inst
.instruction
= 0xee011f40;
16521 else if (((unsigned)inst
.instruction
) == 0)
16522 inst
.instruction
= 0xee000f40;
16524 else if (((unsigned)inst
.instruction
) == 0x200)
16525 inst
.instruction
= 0xee001f40;
16527 else if (((unsigned)inst
.instruction
) == 0x900)
16528 inst
.instruction
= 0xee010e40;
16530 else if (((unsigned)inst
.instruction
) == 0x910)
16531 inst
.instruction
= 0xee011e60;
16533 else if (((unsigned)inst
.instruction
) == 0x10)
16534 inst
.instruction
= 0xee000f60;
16536 else if (((unsigned)inst
.instruction
) == 0x210)
16537 inst
.instruction
= 0xee001f60;
16539 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16540 inst
.instruction
= 0xee000e40;
16542 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16543 inst
.instruction
= 0xee010e60;
16545 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16546 inst
.instruction
= 0xfe010e60;
16549 inst
.instruction
|= U
<< 28;
16551 /* Setting bits for size. */
16552 inst
.instruction
|= neon_logbits (size
) << 20;
16554 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16555 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16556 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16557 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16558 inst
.instruction
|= inst
.operands
[2].reg
;
16563 mve_encode_rqq (unsigned bit28
, unsigned size
)
16565 inst
.instruction
|= bit28
<< 28;
16566 inst
.instruction
|= neon_logbits (size
) << 20;
16567 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16568 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16569 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16570 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16571 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16576 mve_encode_qqq (int ubit
, int size
)
16579 inst
.instruction
|= (ubit
!= 0) << 28;
16580 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16581 inst
.instruction
|= neon_logbits (size
) << 20;
16582 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16583 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16584 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16585 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16586 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16592 mve_encode_rq (unsigned bit28
, unsigned size
)
16594 inst
.instruction
|= bit28
<< 28;
16595 inst
.instruction
|= neon_logbits (size
) << 18;
16596 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16597 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16602 mve_encode_rrqq (unsigned U
, unsigned size
)
16604 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16606 inst
.instruction
|= U
<< 28;
16607 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16608 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16609 inst
.instruction
|= (size
== 32) << 16;
16610 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16611 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16612 inst
.instruction
|= inst
.operands
[3].reg
;
16616 /* Encode insns with bit pattern:
16618 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16619 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16621 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16622 different meaning for some instruction. */
16625 neon_three_same (int isquad
, int ubit
, int size
)
16627 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16628 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16629 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16630 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16631 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16632 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16633 inst
.instruction
|= (isquad
!= 0) << 6;
16634 inst
.instruction
|= (ubit
!= 0) << 24;
16636 inst
.instruction
|= neon_logbits (size
) << 20;
16638 neon_dp_fixup (&inst
);
16641 /* Encode instructions of the form:
16643 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16644 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16646 Don't write size if SIZE == -1. */
16649 neon_two_same (int qbit
, int ubit
, int size
)
16651 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16652 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16653 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16654 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16655 inst
.instruction
|= (qbit
!= 0) << 6;
16656 inst
.instruction
|= (ubit
!= 0) << 24;
16659 inst
.instruction
|= neon_logbits (size
) << 18;
16661 neon_dp_fixup (&inst
);
16664 enum vfp_or_neon_is_neon_bits
16667 NEON_CHECK_ARCH
= 2,
16668 NEON_CHECK_ARCH8
= 4
16671 /* Call this function if an instruction which may have belonged to the VFP or
16672 Neon instruction sets, but turned out to be a Neon instruction (due to the
16673 operand types involved, etc.). We have to check and/or fix-up a couple of
16676 - Make sure the user hasn't attempted to make a Neon instruction
16678 - Alter the value in the condition code field if necessary.
16679 - Make sure that the arch supports Neon instructions.
16681 Which of these operations take place depends on bits from enum
16682 vfp_or_neon_is_neon_bits.
16684 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16685 current instruction's condition is COND_ALWAYS, the condition field is
16686 changed to inst.uncond_value. This is necessary because instructions shared
16687 between VFP and Neon may be conditional for the VFP variants only, and the
16688 unconditional Neon version must have, e.g., 0xF in the condition field. */
16691 vfp_or_neon_is_neon (unsigned check
)
16693 /* Conditions are always legal in Thumb mode (IT blocks). */
16694 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16696 if (inst
.cond
!= COND_ALWAYS
)
16698 first_error (_(BAD_COND
));
16701 if (inst
.uncond_value
!= -1)
16702 inst
.instruction
|= inst
.uncond_value
<< 28;
16706 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16707 || ((check
& NEON_CHECK_ARCH8
)
16708 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16710 first_error (_(BAD_FPU
));
16718 /* Return TRUE if the SIMD instruction is available for the current
16719 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16720 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16721 vfp_or_neon_is_neon for the NEON specific checks. */
16724 check_simd_pred_availability (int fp
, unsigned check
)
16726 if (inst
.cond
> COND_ALWAYS
)
16728 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16730 inst
.error
= BAD_FPU
;
16733 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16735 else if (inst
.cond
< COND_ALWAYS
)
16737 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16738 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16739 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16744 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16745 && vfp_or_neon_is_neon (check
) == FAIL
)
16748 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16749 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16754 /* Neon instruction encoders, in approximate order of appearance. */
16757 do_neon_dyadic_i_su (void)
16759 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16762 enum neon_shape rs
;
16763 struct neon_type_el et
;
16764 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16765 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16767 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16769 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16773 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16775 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16779 do_neon_dyadic_i64_su (void)
16781 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16783 enum neon_shape rs
;
16784 struct neon_type_el et
;
16785 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16787 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16788 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16792 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16793 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16796 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16798 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16802 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16805 unsigned size
= et
.size
>> 3;
16806 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16807 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16808 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16809 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16810 inst
.instruction
|= (isquad
!= 0) << 6;
16811 inst
.instruction
|= immbits
<< 16;
16812 inst
.instruction
|= (size
>> 3) << 7;
16813 inst
.instruction
|= (size
& 0x7) << 19;
16815 inst
.instruction
|= (uval
!= 0) << 24;
16817 neon_dp_fixup (&inst
);
16823 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16826 if (!inst
.operands
[2].isreg
)
16828 enum neon_shape rs
;
16829 struct neon_type_el et
;
16830 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16832 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16833 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16837 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16838 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16840 int imm
= inst
.operands
[2].imm
;
16842 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16843 _("immediate out of range for shift"));
16844 NEON_ENCODE (IMMED
, inst
);
16845 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16849 enum neon_shape rs
;
16850 struct neon_type_el et
;
16851 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16853 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16854 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16858 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16859 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16865 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16866 _("invalid instruction shape"));
16867 if (inst
.operands
[2].reg
== REG_SP
)
16868 as_tsktsk (MVE_BAD_SP
);
16869 else if (inst
.operands
[2].reg
== REG_PC
)
16870 as_tsktsk (MVE_BAD_PC
);
16872 inst
.instruction
= 0xee311e60;
16873 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16874 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16875 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16876 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16877 inst
.instruction
|= inst
.operands
[2].reg
;
16884 /* VSHL/VQSHL 3-register variants have syntax such as:
16886 whereas other 3-register operations encoded by neon_three_same have
16889 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16890 operands[2].reg here. */
16891 tmp
= inst
.operands
[2].reg
;
16892 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16893 inst
.operands
[1].reg
= tmp
;
16894 NEON_ENCODE (INTEGER
, inst
);
16895 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16901 do_neon_qshl (void)
16903 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16906 if (!inst
.operands
[2].isreg
)
16908 enum neon_shape rs
;
16909 struct neon_type_el et
;
16910 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16912 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16913 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
16917 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16918 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16920 int imm
= inst
.operands
[2].imm
;
16922 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16923 _("immediate out of range for shift"));
16924 NEON_ENCODE (IMMED
, inst
);
16925 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16929 enum neon_shape rs
;
16930 struct neon_type_el et
;
16932 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16934 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16935 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16939 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16940 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16945 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16946 _("invalid instruction shape"));
16947 if (inst
.operands
[2].reg
== REG_SP
)
16948 as_tsktsk (MVE_BAD_SP
);
16949 else if (inst
.operands
[2].reg
== REG_PC
)
16950 as_tsktsk (MVE_BAD_PC
);
16952 inst
.instruction
= 0xee311ee0;
16953 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16954 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16955 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16956 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16957 inst
.instruction
|= inst
.operands
[2].reg
;
16964 /* See note in do_neon_shl. */
16965 tmp
= inst
.operands
[2].reg
;
16966 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16967 inst
.operands
[1].reg
= tmp
;
16968 NEON_ENCODE (INTEGER
, inst
);
16969 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16975 do_neon_rshl (void)
16977 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16980 enum neon_shape rs
;
16981 struct neon_type_el et
;
16982 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16984 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16985 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16989 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16990 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16997 if (inst
.operands
[2].reg
== REG_PC
)
16998 as_tsktsk (MVE_BAD_PC
);
16999 else if (inst
.operands
[2].reg
== REG_SP
)
17000 as_tsktsk (MVE_BAD_SP
);
17002 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17003 _("invalid instruction shape"));
17005 if (inst
.instruction
== 0x0000510)
17006 /* We are dealing with vqrshl. */
17007 inst
.instruction
= 0xee331ee0;
17009 /* We are dealing with vrshl. */
17010 inst
.instruction
= 0xee331e60;
17012 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17013 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17014 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17015 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17016 inst
.instruction
|= inst
.operands
[2].reg
;
17021 tmp
= inst
.operands
[2].reg
;
17022 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17023 inst
.operands
[1].reg
= tmp
;
17024 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17029 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
17031 /* Handle .I8 pseudo-instructions. */
17034 /* Unfortunately, this will make everything apart from zero out-of-range.
17035 FIXME is this the intended semantics? There doesn't seem much point in
17036 accepting .I8 if so. */
17037 immediate
|= immediate
<< 8;
17043 if (immediate
== (immediate
& 0x000000ff))
17045 *immbits
= immediate
;
17048 else if (immediate
== (immediate
& 0x0000ff00))
17050 *immbits
= immediate
>> 8;
17053 else if (immediate
== (immediate
& 0x00ff0000))
17055 *immbits
= immediate
>> 16;
17058 else if (immediate
== (immediate
& 0xff000000))
17060 *immbits
= immediate
>> 24;
17063 if ((immediate
& 0xffff) != (immediate
>> 16))
17064 goto bad_immediate
;
17065 immediate
&= 0xffff;
17068 if (immediate
== (immediate
& 0x000000ff))
17070 *immbits
= immediate
;
17073 else if (immediate
== (immediate
& 0x0000ff00))
17075 *immbits
= immediate
>> 8;
17080 first_error (_("immediate value out of range"));
17085 do_neon_logic (void)
17087 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17089 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17091 && !check_simd_pred_availability (FALSE
,
17092 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17094 else if (rs
!= NS_QQQ
17095 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17096 first_error (BAD_FPU
);
17098 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17099 /* U bit and size field were set as part of the bitmask. */
17100 NEON_ENCODE (INTEGER
, inst
);
17101 neon_three_same (neon_quad (rs
), 0, -1);
17105 const int three_ops_form
= (inst
.operands
[2].present
17106 && !inst
.operands
[2].isreg
);
17107 const int immoperand
= (three_ops_form
? 2 : 1);
17108 enum neon_shape rs
= (three_ops_form
17109 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17110 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17111 /* Because neon_select_shape makes the second operand a copy of the first
17112 if the second operand is not present. */
17114 && !check_simd_pred_availability (FALSE
,
17115 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17117 else if (rs
!= NS_QQI
17118 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17119 first_error (BAD_FPU
);
17121 struct neon_type_el et
;
17122 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17123 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17125 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17128 if (et
.type
== NT_invtype
)
17130 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17135 if (three_ops_form
)
17136 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17137 _("first and second operands shall be the same register"));
17139 NEON_ENCODE (IMMED
, inst
);
17141 immbits
= inst
.operands
[immoperand
].imm
;
17144 /* .i64 is a pseudo-op, so the immediate must be a repeating
17146 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17147 inst
.operands
[immoperand
].reg
: 0))
17149 /* Set immbits to an invalid constant. */
17150 immbits
= 0xdeadbeef;
17157 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17161 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17165 /* Pseudo-instruction for VBIC. */
17166 neon_invert_size (&immbits
, 0, et
.size
);
17167 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17171 /* Pseudo-instruction for VORR. */
17172 neon_invert_size (&immbits
, 0, et
.size
);
17173 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17183 inst
.instruction
|= neon_quad (rs
) << 6;
17184 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17185 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17186 inst
.instruction
|= cmode
<< 8;
17187 neon_write_immbits (immbits
);
17189 neon_dp_fixup (&inst
);
17194 do_neon_bitfield (void)
17196 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17197 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17198 neon_three_same (neon_quad (rs
), 0, -1);
17202 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17205 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17206 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17208 if (et
.type
== NT_float
)
17210 NEON_ENCODE (FLOAT
, inst
);
17212 mve_encode_qqr (et
.size
, 0, 1);
17214 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17218 NEON_ENCODE (INTEGER
, inst
);
17220 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17222 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17228 do_neon_dyadic_if_su_d (void)
17230 /* This version only allow D registers, but that constraint is enforced during
17231 operand parsing so we don't need to do anything extra here. */
17232 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17236 do_neon_dyadic_if_i_d (void)
17238 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17239 affected if we specify unsigned args. */
17240 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17244 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17246 constraint (size
< 32, BAD_ADDR_MODE
);
17247 constraint (size
!= elsize
, BAD_EL_TYPE
);
17248 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17249 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17250 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17251 _("destination register and offset register may not be the"
17254 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17261 constraint ((imm
% (size
/ 8) != 0)
17262 || imm
> (0x7f << neon_logbits (size
)),
17263 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17264 " range of +/-[0,508]")
17265 : _("immediate must be a multiple of 8 in the"
17266 " range of +/-[0,1016]"));
17267 inst
.instruction
|= 0x11 << 24;
17268 inst
.instruction
|= add
<< 23;
17269 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17270 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17271 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17272 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17273 inst
.instruction
|= 1 << 12;
17274 inst
.instruction
|= (size
== 64) << 8;
17275 inst
.instruction
&= 0xffffff00;
17276 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17277 inst
.instruction
|= imm
>> neon_logbits (size
);
17281 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17283 unsigned os
= inst
.operands
[1].imm
>> 5;
17284 constraint (os
!= 0 && size
== 8,
17285 _("can not shift offsets when accessing less than half-word"));
17286 constraint (os
&& os
!= neon_logbits (size
),
17287 _("shift immediate must be 1, 2 or 3 for half-word, word"
17288 " or double-word accesses respectively"));
17289 if (inst
.operands
[1].reg
== REG_PC
)
17290 as_tsktsk (MVE_BAD_PC
);
17295 constraint (elsize
>= 64, BAD_EL_TYPE
);
17298 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17302 constraint (elsize
!= size
, BAD_EL_TYPE
);
17307 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17311 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17312 _("destination register and offset register may not be"
17314 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
17316 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
17317 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
17318 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
17322 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
17325 inst
.instruction
|= 1 << 23;
17326 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17327 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17328 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17329 inst
.instruction
|= neon_logbits (elsize
) << 7;
17330 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17331 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17332 inst
.instruction
|= !!os
;
17336 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17338 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17340 constraint (size
>= 64, BAD_ADDR_MODE
);
17344 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17347 constraint (elsize
!= size
, BAD_EL_TYPE
);
17354 constraint (elsize
!= size
&& type
!= NT_unsigned
17355 && type
!= NT_signed
, BAD_EL_TYPE
);
17359 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17362 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17370 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17375 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17378 constraint (1, _("immediate must be a multiple of 2 in the"
17379 " range of +/-[0,254]"));
17382 constraint (1, _("immediate must be a multiple of 4 in the"
17383 " range of +/-[0,508]"));
17388 if (size
!= elsize
)
17390 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17391 constraint (inst
.operands
[0].reg
> 14,
17392 _("MVE vector register in the range [Q0..Q7] expected"));
17393 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17394 inst
.instruction
|= (size
== 16) << 19;
17395 inst
.instruction
|= neon_logbits (elsize
) << 7;
17399 if (inst
.operands
[1].reg
== REG_PC
)
17400 as_tsktsk (MVE_BAD_PC
);
17401 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17402 as_tsktsk (MVE_BAD_SP
);
17403 inst
.instruction
|= 1 << 12;
17404 inst
.instruction
|= neon_logbits (size
) << 7;
17406 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17407 inst
.instruction
|= add
<< 23;
17408 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17409 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17410 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17411 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17412 inst
.instruction
&= 0xffffff80;
17413 inst
.instruction
|= imm
>> neon_logbits (size
);
17418 do_mve_vstr_vldr (void)
17423 if (inst
.cond
> COND_ALWAYS
)
17424 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17426 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17428 switch (inst
.instruction
)
17435 /* fall through. */
17441 /* fall through. */
17447 /* fall through. */
17453 /* fall through. */
17458 unsigned elsize
= inst
.vectype
.el
[0].size
;
17460 if (inst
.operands
[1].isquad
)
17462 /* We are dealing with [Q, imm]{!} cases. */
17463 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17467 if (inst
.operands
[1].immisreg
== 2)
17469 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17470 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17472 else if (!inst
.operands
[1].immisreg
)
17474 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17475 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17478 constraint (1, BAD_ADDR_MODE
);
17485 do_mve_vst_vld (void)
17487 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17490 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17491 || inst
.relocs
[0].exp
.X_add_number
!= 0
17492 || inst
.operands
[1].immisreg
!= 0,
17494 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17495 if (inst
.operands
[1].reg
== REG_PC
)
17496 as_tsktsk (MVE_BAD_PC
);
17497 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17498 as_tsktsk (MVE_BAD_SP
);
17501 /* These instructions are one of the "exceptions" mentioned in
17502 handle_pred_state. They are MVE instructions that are not VPT compatible
17503 and do not accept a VPT code, thus appending such a code is a syntax
17505 if (inst
.cond
> COND_ALWAYS
)
17506 first_error (BAD_SYNTAX
);
17507 /* If we append a scalar condition code we can set this to
17508 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17509 else if (inst
.cond
< COND_ALWAYS
)
17510 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17512 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17514 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17515 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17516 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17517 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17518 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17523 do_mve_vaddlv (void)
17525 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17526 struct neon_type_el et
17527 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17529 if (et
.type
== NT_invtype
)
17530 first_error (BAD_EL_TYPE
);
17532 if (inst
.cond
> COND_ALWAYS
)
17533 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17535 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17537 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17539 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17540 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17541 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17542 inst
.instruction
|= inst
.operands
[2].reg
;
17547 do_neon_dyadic_if_su (void)
17549 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17550 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17553 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17554 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17555 && et
.type
== NT_float
17556 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17558 if (!check_simd_pred_availability (et
.type
== NT_float
,
17559 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17562 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17566 do_neon_addsub_if_i (void)
17568 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17569 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17572 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17573 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17574 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17576 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17577 /* If we are parsing Q registers and the element types match MVE, which NEON
17578 also supports, then we must check whether this is an instruction that can
17579 be used by both MVE/NEON. This distinction can be made based on whether
17580 they are predicated or not. */
17581 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17583 if (!check_simd_pred_availability (et
.type
== NT_float
,
17584 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17589 /* If they are either in a D register or are using an unsupported. */
17591 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17595 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17596 affected if we specify unsigned args. */
17597 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17600 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17602 V<op> A,B (A is operand 0, B is operand 2)
17607 so handle that case specially. */
17610 neon_exchange_operands (void)
17612 if (inst
.operands
[1].present
)
17614 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17616 /* Swap operands[1] and operands[2]. */
17617 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17618 inst
.operands
[1] = inst
.operands
[2];
17619 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17624 inst
.operands
[1] = inst
.operands
[2];
17625 inst
.operands
[2] = inst
.operands
[0];
17630 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17632 if (inst
.operands
[2].isreg
)
17635 neon_exchange_operands ();
17636 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17640 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17641 struct neon_type_el et
= neon_check_type (2, rs
,
17642 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17644 NEON_ENCODE (IMMED
, inst
);
17645 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17646 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17647 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17648 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17649 inst
.instruction
|= neon_quad (rs
) << 6;
17650 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17651 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17653 neon_dp_fixup (&inst
);
17660 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17664 do_neon_cmp_inv (void)
17666 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17672 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17675 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17676 scalars, which are encoded in 5 bits, M : Rm.
17677 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17678 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17681 Dot Product instructions are similar to multiply instructions except elsize
17682 should always be 32.
17684 This function translates SCALAR, which is GAS's internal encoding of indexed
17685 scalar register, to raw encoding. There is also register and index range
17686 check based on ELSIZE. */
17689 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17691 unsigned regno
= NEON_SCALAR_REG (scalar
);
17692 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17697 if (regno
> 7 || elno
> 3)
17699 return regno
| (elno
<< 3);
17702 if (regno
> 15 || elno
> 1)
17704 return regno
| (elno
<< 4);
17708 first_error (_("scalar out of range for multiply instruction"));
17714 /* Encode multiply / multiply-accumulate scalar instructions. */
17717 neon_mul_mac (struct neon_type_el et
, int ubit
)
17721 /* Give a more helpful error message if we have an invalid type. */
17722 if (et
.type
== NT_invtype
)
17725 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17726 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17727 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17728 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17729 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17730 inst
.instruction
|= LOW4 (scalar
);
17731 inst
.instruction
|= HI1 (scalar
) << 5;
17732 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17733 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17734 inst
.instruction
|= (ubit
!= 0) << 24;
17736 neon_dp_fixup (&inst
);
17740 do_neon_mac_maybe_scalar (void)
17742 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17745 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17748 if (inst
.operands
[2].isscalar
)
17750 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17751 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17752 struct neon_type_el et
= neon_check_type (3, rs
,
17753 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17754 NEON_ENCODE (SCALAR
, inst
);
17755 neon_mul_mac (et
, neon_quad (rs
));
17757 else if (!inst
.operands
[2].isvec
)
17759 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17761 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17762 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17764 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17768 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17769 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17770 affected if we specify unsigned args. */
17771 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17776 do_neon_fmac (void)
17778 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17779 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17782 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17785 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17787 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17788 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17793 if (inst
.operands
[2].reg
== REG_SP
)
17794 as_tsktsk (MVE_BAD_SP
);
17795 else if (inst
.operands
[2].reg
== REG_PC
)
17796 as_tsktsk (MVE_BAD_PC
);
17798 inst
.instruction
= 0xee310e40;
17799 inst
.instruction
|= (et
.size
== 16) << 28;
17800 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17801 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17802 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17803 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17804 inst
.instruction
|= inst
.operands
[2].reg
;
17811 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17814 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17820 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17821 struct neon_type_el et
= neon_check_type (3, rs
,
17822 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17823 neon_three_same (neon_quad (rs
), 0, et
.size
);
17826 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17827 same types as the MAC equivalents. The polynomial type for this instruction
17828 is encoded the same as the integer type. */
17833 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17836 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17839 if (inst
.operands
[2].isscalar
)
17841 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17842 do_neon_mac_maybe_scalar ();
17846 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17848 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17849 struct neon_type_el et
17850 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
17851 if (et
.type
== NT_float
)
17852 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
17855 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
17859 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17860 neon_dyadic_misc (NT_poly
,
17861 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17867 do_neon_qdmulh (void)
17869 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17872 if (inst
.operands
[2].isscalar
)
17874 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17875 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17876 struct neon_type_el et
= neon_check_type (3, rs
,
17877 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17878 NEON_ENCODE (SCALAR
, inst
);
17879 neon_mul_mac (et
, neon_quad (rs
));
17883 enum neon_shape rs
;
17884 struct neon_type_el et
;
17885 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17887 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17888 et
= neon_check_type (3, rs
,
17889 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17893 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17894 et
= neon_check_type (3, rs
,
17895 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17898 NEON_ENCODE (INTEGER
, inst
);
17900 mve_encode_qqr (et
.size
, 0, 0);
17902 /* The U bit (rounding) comes from bit mask. */
17903 neon_three_same (neon_quad (rs
), 0, et
.size
);
17908 do_mve_vaddv (void)
17910 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17911 struct neon_type_el et
17912 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17914 if (et
.type
== NT_invtype
)
17915 first_error (BAD_EL_TYPE
);
17917 if (inst
.cond
> COND_ALWAYS
)
17918 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17920 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17922 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17924 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17928 do_mve_vhcadd (void)
17930 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
17931 struct neon_type_el et
17932 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17934 if (inst
.cond
> COND_ALWAYS
)
17935 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17937 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17939 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17940 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17942 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
17943 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17944 "operand makes instruction UNPREDICTABLE"));
17946 mve_encode_qqq (0, et
.size
);
17947 inst
.instruction
|= (rot
== 270) << 12;
17952 do_mve_vqdmull (void)
17954 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17955 struct neon_type_el et
17956 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17959 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17960 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
17961 as_tsktsk (BAD_MVE_SRCDEST
);
17963 if (inst
.cond
> COND_ALWAYS
)
17964 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17966 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17970 mve_encode_qqq (et
.size
== 32, 64);
17971 inst
.instruction
|= 1;
17975 mve_encode_qqr (64, et
.size
== 32, 0);
17976 inst
.instruction
|= 0x3 << 5;
17983 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17984 struct neon_type_el et
17985 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
17987 if (et
.type
== NT_invtype
)
17988 first_error (BAD_EL_TYPE
);
17990 if (inst
.cond
> COND_ALWAYS
)
17991 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17993 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17995 mve_encode_qqq (0, 64);
17999 do_mve_vbrsr (void)
18001 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18002 struct neon_type_el et
18003 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18005 if (inst
.cond
> COND_ALWAYS
)
18006 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18008 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18010 mve_encode_qqr (et
.size
, 0, 0);
18016 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
18018 if (inst
.cond
> COND_ALWAYS
)
18019 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18021 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18023 mve_encode_qqq (1, 64);
18027 do_mve_vmulh (void)
18029 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18030 struct neon_type_el et
18031 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18033 if (inst
.cond
> COND_ALWAYS
)
18034 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18036 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18038 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18042 do_mve_vqdmlah (void)
18044 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18045 struct neon_type_el et
18046 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18048 if (inst
.cond
> COND_ALWAYS
)
18049 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18051 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18053 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18057 do_mve_vqdmladh (void)
18059 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18060 struct neon_type_el et
18061 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18063 if (inst
.cond
> COND_ALWAYS
)
18064 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18066 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18068 mve_encode_qqq (0, et
.size
);
18073 do_mve_vmull (void)
18076 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18077 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18078 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18079 && inst
.cond
== COND_ALWAYS
18080 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18085 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18086 N_SUF_32
| N_F64
| N_P8
18087 | N_P16
| N_I_MVE
| N_KEY
);
18088 if (((et
.type
== NT_poly
) && et
.size
== 8
18089 && ARM_CPU_IS_ANY (cpu_variant
))
18090 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
18097 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18098 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18099 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18101 /* We are dealing with MVE's vmullt. */
18103 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18104 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18105 as_tsktsk (BAD_MVE_SRCDEST
);
18107 if (inst
.cond
> COND_ALWAYS
)
18108 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18110 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18112 if (et
.type
== NT_poly
)
18113 mve_encode_qqq (neon_logbits (et
.size
), 64);
18115 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18120 inst
.instruction
= N_MNEM_vmul
;
18123 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18128 do_mve_vabav (void)
18130 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18135 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18138 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18139 | N_S16
| N_S32
| N_U8
| N_U16
18142 if (inst
.cond
> COND_ALWAYS
)
18143 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18145 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18147 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18151 do_mve_vmladav (void)
18153 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18154 struct neon_type_el et
= neon_check_type (3, rs
,
18155 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18157 if (et
.type
== NT_unsigned
18158 && (inst
.instruction
== M_MNEM_vmladavx
18159 || inst
.instruction
== M_MNEM_vmladavax
18160 || inst
.instruction
== M_MNEM_vmlsdav
18161 || inst
.instruction
== M_MNEM_vmlsdava
18162 || inst
.instruction
== M_MNEM_vmlsdavx
18163 || inst
.instruction
== M_MNEM_vmlsdavax
))
18164 first_error (BAD_SIMD_TYPE
);
18166 constraint (inst
.operands
[2].reg
> 14,
18167 _("MVE vector register in the range [Q0..Q7] expected"));
18169 if (inst
.cond
> COND_ALWAYS
)
18170 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18172 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18174 if (inst
.instruction
== M_MNEM_vmlsdav
18175 || inst
.instruction
== M_MNEM_vmlsdava
18176 || inst
.instruction
== M_MNEM_vmlsdavx
18177 || inst
.instruction
== M_MNEM_vmlsdavax
)
18178 inst
.instruction
|= (et
.size
== 8) << 28;
18180 inst
.instruction
|= (et
.size
== 8) << 8;
18182 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18183 inst
.instruction
|= (et
.size
== 32) << 16;
18187 do_mve_vmlaldav (void)
18189 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18190 struct neon_type_el et
18191 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18192 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18194 if (et
.type
== NT_unsigned
18195 && (inst
.instruction
== M_MNEM_vmlsldav
18196 || inst
.instruction
== M_MNEM_vmlsldava
18197 || inst
.instruction
== M_MNEM_vmlsldavx
18198 || inst
.instruction
== M_MNEM_vmlsldavax
))
18199 first_error (BAD_SIMD_TYPE
);
18201 if (inst
.cond
> COND_ALWAYS
)
18202 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18204 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18206 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18210 do_mve_vrmlaldavh (void)
18212 struct neon_type_el et
;
18213 if (inst
.instruction
== M_MNEM_vrmlsldavh
18214 || inst
.instruction
== M_MNEM_vrmlsldavha
18215 || inst
.instruction
== M_MNEM_vrmlsldavhx
18216 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18218 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18219 if (inst
.operands
[1].reg
== REG_SP
)
18220 as_tsktsk (MVE_BAD_SP
);
18224 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18225 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18226 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18228 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18229 N_U32
| N_S32
| N_KEY
);
18230 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18231 with vmax/min instructions, making the use of SP in assembly really
18232 nonsensical, so instead of issuing a warning like we do for other uses
18233 of SP for the odd register operand we error out. */
18234 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18237 /* Make sure we still check the second operand is an odd one and that PC is
18238 disallowed. This because we are parsing for any GPR operand, to be able
18239 to distinguish between giving a warning or an error for SP as described
18241 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18242 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18244 if (inst
.cond
> COND_ALWAYS
)
18245 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18247 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18249 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18254 do_mve_vmaxnmv (void)
18256 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18257 struct neon_type_el et
18258 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18260 if (inst
.cond
> COND_ALWAYS
)
18261 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18263 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18265 if (inst
.operands
[0].reg
== REG_SP
)
18266 as_tsktsk (MVE_BAD_SP
);
18267 else if (inst
.operands
[0].reg
== REG_PC
)
18268 as_tsktsk (MVE_BAD_PC
);
18270 mve_encode_rq (et
.size
== 16, 64);
18274 do_mve_vmaxv (void)
18276 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18277 struct neon_type_el et
;
18279 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18280 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18282 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18284 if (inst
.cond
> COND_ALWAYS
)
18285 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18287 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18289 if (inst
.operands
[0].reg
== REG_SP
)
18290 as_tsktsk (MVE_BAD_SP
);
18291 else if (inst
.operands
[0].reg
== REG_PC
)
18292 as_tsktsk (MVE_BAD_PC
);
18294 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18299 do_neon_qrdmlah (void)
18301 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18303 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18305 /* Check we're on the correct architecture. */
18306 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18308 = _("instruction form not available on this architecture.");
18309 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18311 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18312 record_feature_use (&fpu_neon_ext_v8_1
);
18314 if (inst
.operands
[2].isscalar
)
18316 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18317 struct neon_type_el et
= neon_check_type (3, rs
,
18318 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18319 NEON_ENCODE (SCALAR
, inst
);
18320 neon_mul_mac (et
, neon_quad (rs
));
18324 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18325 struct neon_type_el et
= neon_check_type (3, rs
,
18326 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18327 NEON_ENCODE (INTEGER
, inst
);
18328 /* The U bit (rounding) comes from bit mask. */
18329 neon_three_same (neon_quad (rs
), 0, et
.size
);
18334 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18335 struct neon_type_el et
18336 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18338 NEON_ENCODE (INTEGER
, inst
);
18339 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18344 do_neon_fcmp_absolute (void)
18346 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18347 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18348 N_F_16_32
| N_KEY
);
18349 /* Size field comes from bit mask. */
18350 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18354 do_neon_fcmp_absolute_inv (void)
18356 neon_exchange_operands ();
18357 do_neon_fcmp_absolute ();
18361 do_neon_step (void)
18363 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18364 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18365 N_F_16_32
| N_KEY
);
18366 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18370 do_neon_abs_neg (void)
18372 enum neon_shape rs
;
18373 struct neon_type_el et
;
18375 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18378 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18379 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18381 if (!check_simd_pred_availability (et
.type
== NT_float
,
18382 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18385 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18386 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18387 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18388 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18389 inst
.instruction
|= neon_quad (rs
) << 6;
18390 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18391 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18393 neon_dp_fixup (&inst
);
18399 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18402 enum neon_shape rs
;
18403 struct neon_type_el et
;
18404 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18406 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18407 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18411 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18412 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18416 int imm
= inst
.operands
[2].imm
;
18417 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18418 _("immediate out of range for insert"));
18419 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18425 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18428 enum neon_shape rs
;
18429 struct neon_type_el et
;
18430 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18432 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18433 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18437 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18438 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18441 int imm
= inst
.operands
[2].imm
;
18442 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18443 _("immediate out of range for insert"));
18444 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18448 do_neon_qshlu_imm (void)
18450 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18453 enum neon_shape rs
;
18454 struct neon_type_el et
;
18455 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18457 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18458 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18462 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18463 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18464 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18467 int imm
= inst
.operands
[2].imm
;
18468 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18469 _("immediate out of range for shift"));
18470 /* Only encodes the 'U present' variant of the instruction.
18471 In this case, signed types have OP (bit 8) set to 0.
18472 Unsigned types have OP set to 1. */
18473 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18474 /* The rest of the bits are the same as other immediate shifts. */
18475 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18479 do_neon_qmovn (void)
18481 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18482 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18483 /* Saturating move where operands can be signed or unsigned, and the
18484 destination has the same signedness. */
18485 NEON_ENCODE (INTEGER
, inst
);
18486 if (et
.type
== NT_unsigned
)
18487 inst
.instruction
|= 0xc0;
18489 inst
.instruction
|= 0x80;
18490 neon_two_same (0, 1, et
.size
/ 2);
18494 do_neon_qmovun (void)
18496 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18497 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18498 /* Saturating move with unsigned results. Operands must be signed. */
18499 NEON_ENCODE (INTEGER
, inst
);
18500 neon_two_same (0, 1, et
.size
/ 2);
18504 do_neon_rshift_sat_narrow (void)
18506 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18507 or unsigned. If operands are unsigned, results must also be unsigned. */
18508 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18509 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18510 int imm
= inst
.operands
[2].imm
;
18511 /* This gets the bounds check, size encoding and immediate bits calculation
18515 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18516 VQMOVN.I<size> <Dd>, <Qm>. */
18519 inst
.operands
[2].present
= 0;
18520 inst
.instruction
= N_MNEM_vqmovn
;
18525 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18526 _("immediate out of range"));
18527 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18531 do_neon_rshift_sat_narrow_u (void)
18533 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18534 or unsigned. If operands are unsigned, results must also be unsigned. */
18535 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18536 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18537 int imm
= inst
.operands
[2].imm
;
18538 /* This gets the bounds check, size encoding and immediate bits calculation
18542 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18543 VQMOVUN.I<size> <Dd>, <Qm>. */
18546 inst
.operands
[2].present
= 0;
18547 inst
.instruction
= N_MNEM_vqmovun
;
18552 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18553 _("immediate out of range"));
18554 /* FIXME: The manual is kind of unclear about what value U should have in
18555 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18557 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18561 do_neon_movn (void)
18563 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18564 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18565 NEON_ENCODE (INTEGER
, inst
);
18566 neon_two_same (0, 1, et
.size
/ 2);
18570 do_neon_rshift_narrow (void)
18572 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18573 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18574 int imm
= inst
.operands
[2].imm
;
18575 /* This gets the bounds check, size encoding and immediate bits calculation
18579 /* If immediate is zero then we are a pseudo-instruction for
18580 VMOVN.I<size> <Dd>, <Qm> */
18583 inst
.operands
[2].present
= 0;
18584 inst
.instruction
= N_MNEM_vmovn
;
18589 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18590 _("immediate out of range for narrowing operation"));
18591 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18595 do_neon_shll (void)
18597 /* FIXME: Type checking when lengthening. */
18598 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18599 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18600 unsigned imm
= inst
.operands
[2].imm
;
18602 if (imm
== et
.size
)
18604 /* Maximum shift variant. */
18605 NEON_ENCODE (INTEGER
, inst
);
18606 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18607 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18608 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18609 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18610 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18612 neon_dp_fixup (&inst
);
18616 /* A more-specific type check for non-max versions. */
18617 et
= neon_check_type (2, NS_QDI
,
18618 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18619 NEON_ENCODE (IMMED
, inst
);
18620 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18624 /* Check the various types for the VCVT instruction, and return which version
18625 the current instruction is. */
18627 #define CVT_FLAVOUR_VAR \
18628 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18629 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18630 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18631 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18632 /* Half-precision conversions. */ \
18633 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18634 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18635 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18636 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18637 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18638 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18639 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18640 Compared with single/double precision variants, only the co-processor \
18641 field is different, so the encoding flow is reused here. */ \
18642 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18643 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18644 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18645 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18646 /* VFP instructions. */ \
18647 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18648 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18649 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18650 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18651 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18652 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18653 /* VFP instructions with bitshift. */ \
18654 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18655 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18656 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18657 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18658 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18659 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18660 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18661 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18663 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18664 neon_cvt_flavour_##C,
18666 /* The different types of conversions we can do. */
18667 enum neon_cvt_flavour
18670 neon_cvt_flavour_invalid
,
18671 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18676 static enum neon_cvt_flavour
18677 get_neon_cvt_flavour (enum neon_shape rs
)
18679 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18680 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18681 if (et.type != NT_invtype) \
18683 inst.error = NULL; \
18684 return (neon_cvt_flavour_##C); \
18687 struct neon_type_el et
;
18688 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18689 || rs
== NS_FF
) ? N_VFP
: 0;
18690 /* The instruction versions which take an immediate take one register
18691 argument, which is extended to the width of the full register. Thus the
18692 "source" and "destination" registers must have the same width. Hack that
18693 here by making the size equal to the key (wider, in this case) operand. */
18694 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18698 return neon_cvt_flavour_invalid
;
18713 /* Neon-syntax VFP conversions. */
18716 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18718 const char *opname
= 0;
18720 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18721 || rs
== NS_FHI
|| rs
== NS_HFI
)
18723 /* Conversions with immediate bitshift. */
18724 const char *enc
[] =
18726 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18732 if (flavour
< (int) ARRAY_SIZE (enc
))
18734 opname
= enc
[flavour
];
18735 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18736 _("operands 0 and 1 must be the same register"));
18737 inst
.operands
[1] = inst
.operands
[2];
18738 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18743 /* Conversions without bitshift. */
18744 const char *enc
[] =
18746 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18752 if (flavour
< (int) ARRAY_SIZE (enc
))
18753 opname
= enc
[flavour
];
18757 do_vfp_nsyn_opcode (opname
);
18759 /* ARMv8.2 fp16 VCVT instruction. */
18760 if (flavour
== neon_cvt_flavour_s32_f16
18761 || flavour
== neon_cvt_flavour_u32_f16
18762 || flavour
== neon_cvt_flavour_f16_u32
18763 || flavour
== neon_cvt_flavour_f16_s32
)
18764 do_scalar_fp16_v82_encode ();
18768 do_vfp_nsyn_cvtz (void)
18770 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18771 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18772 const char *enc
[] =
18774 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18780 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18781 do_vfp_nsyn_opcode (enc
[flavour
]);
18785 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18786 enum neon_cvt_mode mode
)
18791 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18792 D register operands. */
18793 if (flavour
== neon_cvt_flavour_s32_f64
18794 || flavour
== neon_cvt_flavour_u32_f64
)
18795 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18798 if (flavour
== neon_cvt_flavour_s32_f16
18799 || flavour
== neon_cvt_flavour_u32_f16
)
18800 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18803 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18807 case neon_cvt_flavour_s32_f64
:
18811 case neon_cvt_flavour_s32_f32
:
18815 case neon_cvt_flavour_s32_f16
:
18819 case neon_cvt_flavour_u32_f64
:
18823 case neon_cvt_flavour_u32_f32
:
18827 case neon_cvt_flavour_u32_f16
:
18832 first_error (_("invalid instruction shape"));
18838 case neon_cvt_mode_a
: rm
= 0; break;
18839 case neon_cvt_mode_n
: rm
= 1; break;
18840 case neon_cvt_mode_p
: rm
= 2; break;
18841 case neon_cvt_mode_m
: rm
= 3; break;
18842 default: first_error (_("invalid rounding mode")); return;
18845 NEON_ENCODE (FPV8
, inst
);
18846 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
18847 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
18848 inst
.instruction
|= sz
<< 8;
18850 /* ARMv8.2 fp16 VCVT instruction. */
18851 if (flavour
== neon_cvt_flavour_s32_f16
18852 ||flavour
== neon_cvt_flavour_u32_f16
)
18853 do_scalar_fp16_v82_encode ();
18854 inst
.instruction
|= op
<< 7;
18855 inst
.instruction
|= rm
<< 16;
18856 inst
.instruction
|= 0xf0000000;
18857 inst
.is_neon
= TRUE
;
18861 do_neon_cvt_1 (enum neon_cvt_mode mode
)
18863 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
18864 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
18865 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
18867 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18869 if (flavour
== neon_cvt_flavour_invalid
)
18872 /* PR11109: Handle round-to-zero for VCVT conversions. */
18873 if (mode
== neon_cvt_mode_z
18874 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
18875 && (flavour
== neon_cvt_flavour_s16_f16
18876 || flavour
== neon_cvt_flavour_u16_f16
18877 || flavour
== neon_cvt_flavour_s32_f32
18878 || flavour
== neon_cvt_flavour_u32_f32
18879 || flavour
== neon_cvt_flavour_s32_f64
18880 || flavour
== neon_cvt_flavour_u32_f64
)
18881 && (rs
== NS_FD
|| rs
== NS_FF
))
18883 do_vfp_nsyn_cvtz ();
18887 /* ARMv8.2 fp16 VCVT conversions. */
18888 if (mode
== neon_cvt_mode_z
18889 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
18890 && (flavour
== neon_cvt_flavour_s32_f16
18891 || flavour
== neon_cvt_flavour_u32_f16
)
18894 do_vfp_nsyn_cvtz ();
18895 do_scalar_fp16_v82_encode ();
18899 /* VFP rather than Neon conversions. */
18900 if (flavour
>= neon_cvt_flavour_first_fp
)
18902 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18903 do_vfp_nsyn_cvt (rs
, flavour
);
18905 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18913 if (mode
== neon_cvt_mode_z
18914 && (flavour
== neon_cvt_flavour_f16_s16
18915 || flavour
== neon_cvt_flavour_f16_u16
18916 || flavour
== neon_cvt_flavour_s16_f16
18917 || flavour
== neon_cvt_flavour_u16_f16
18918 || flavour
== neon_cvt_flavour_f32_u32
18919 || flavour
== neon_cvt_flavour_f32_s32
18920 || flavour
== neon_cvt_flavour_s32_f32
18921 || flavour
== neon_cvt_flavour_u32_f32
))
18923 if (!check_simd_pred_availability (TRUE
,
18924 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18927 else if (mode
== neon_cvt_mode_n
)
18929 /* We are dealing with vcvt with the 'ne' condition. */
18931 inst
.instruction
= N_MNEM_vcvt
;
18932 do_neon_cvt_1 (neon_cvt_mode_z
);
18935 /* fall through. */
18939 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18940 0x0000100, 0x1000100, 0x0, 0x1000000};
18942 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18943 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18946 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18948 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
18949 _("immediate value out of range"));
18952 case neon_cvt_flavour_f16_s16
:
18953 case neon_cvt_flavour_f16_u16
:
18954 case neon_cvt_flavour_s16_f16
:
18955 case neon_cvt_flavour_u16_f16
:
18956 constraint (inst
.operands
[2].imm
> 16,
18957 _("immediate value out of range"));
18959 case neon_cvt_flavour_f32_u32
:
18960 case neon_cvt_flavour_f32_s32
:
18961 case neon_cvt_flavour_s32_f32
:
18962 case neon_cvt_flavour_u32_f32
:
18963 constraint (inst
.operands
[2].imm
> 32,
18964 _("immediate value out of range"));
18967 inst
.error
= BAD_FPU
;
18972 /* Fixed-point conversion with #0 immediate is encoded as an
18973 integer conversion. */
18974 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
18976 NEON_ENCODE (IMMED
, inst
);
18977 if (flavour
!= neon_cvt_flavour_invalid
)
18978 inst
.instruction
|= enctab
[flavour
];
18979 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18980 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18981 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18982 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18983 inst
.instruction
|= neon_quad (rs
) << 6;
18984 inst
.instruction
|= 1 << 21;
18985 if (flavour
< neon_cvt_flavour_s16_f16
)
18987 inst
.instruction
|= 1 << 21;
18988 immbits
= 32 - inst
.operands
[2].imm
;
18989 inst
.instruction
|= immbits
<< 16;
18993 inst
.instruction
|= 3 << 20;
18994 immbits
= 16 - inst
.operands
[2].imm
;
18995 inst
.instruction
|= immbits
<< 16;
18996 inst
.instruction
&= ~(1 << 9);
18999 neon_dp_fixup (&inst
);
19004 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19005 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
19006 && (flavour
== neon_cvt_flavour_s16_f16
19007 || flavour
== neon_cvt_flavour_u16_f16
19008 || flavour
== neon_cvt_flavour_s32_f32
19009 || flavour
== neon_cvt_flavour_u32_f32
))
19011 if (!check_simd_pred_availability (TRUE
,
19012 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19015 else if (mode
== neon_cvt_mode_z
19016 && (flavour
== neon_cvt_flavour_f16_s16
19017 || flavour
== neon_cvt_flavour_f16_u16
19018 || flavour
== neon_cvt_flavour_s16_f16
19019 || flavour
== neon_cvt_flavour_u16_f16
19020 || flavour
== neon_cvt_flavour_f32_u32
19021 || flavour
== neon_cvt_flavour_f32_s32
19022 || flavour
== neon_cvt_flavour_s32_f32
19023 || flavour
== neon_cvt_flavour_u32_f32
))
19025 if (!check_simd_pred_availability (TRUE
,
19026 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19029 /* fall through. */
19031 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
19034 NEON_ENCODE (FLOAT
, inst
);
19035 if (!check_simd_pred_availability (TRUE
,
19036 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19039 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19040 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19041 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19042 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19043 inst
.instruction
|= neon_quad (rs
) << 6;
19044 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19045 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19046 inst
.instruction
|= mode
<< 8;
19047 if (flavour
== neon_cvt_flavour_u16_f16
19048 || flavour
== neon_cvt_flavour_s16_f16
)
19049 /* Mask off the original size bits and reencode them. */
19050 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19053 inst
.instruction
|= 0xfc000000;
19055 inst
.instruction
|= 0xf0000000;
19061 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19062 0x100, 0x180, 0x0, 0x080};
19064 NEON_ENCODE (INTEGER
, inst
);
19066 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19068 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19072 if (flavour
!= neon_cvt_flavour_invalid
)
19073 inst
.instruction
|= enctab
[flavour
];
19075 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19076 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19077 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19078 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19079 inst
.instruction
|= neon_quad (rs
) << 6;
19080 if (flavour
>= neon_cvt_flavour_s16_f16
19081 && flavour
<= neon_cvt_flavour_f16_u16
)
19082 /* Half precision. */
19083 inst
.instruction
|= 1 << 18;
19085 inst
.instruction
|= 2 << 18;
19087 neon_dp_fixup (&inst
);
19092 /* Half-precision conversions for Advanced SIMD -- neon. */
19095 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19099 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19101 as_bad (_("operand size must match register width"));
19106 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19108 as_bad (_("operand size must match register width"));
19113 inst
.instruction
= 0x3b60600;
19115 inst
.instruction
= 0x3b60700;
19117 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19118 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19119 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19120 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19121 neon_dp_fixup (&inst
);
19125 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19126 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19127 do_vfp_nsyn_cvt (rs
, flavour
);
19129 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19134 do_neon_cvtr (void)
19136 do_neon_cvt_1 (neon_cvt_mode_x
);
19142 do_neon_cvt_1 (neon_cvt_mode_z
);
19146 do_neon_cvta (void)
19148 do_neon_cvt_1 (neon_cvt_mode_a
);
19152 do_neon_cvtn (void)
19154 do_neon_cvt_1 (neon_cvt_mode_n
);
19158 do_neon_cvtp (void)
19160 do_neon_cvt_1 (neon_cvt_mode_p
);
19164 do_neon_cvtm (void)
19166 do_neon_cvt_1 (neon_cvt_mode_m
);
19170 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19173 mark_feature_used (&fpu_vfp_ext_armv8
);
19175 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19176 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19177 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19178 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19179 inst
.instruction
|= to
? 0x10000 : 0;
19180 inst
.instruction
|= t
? 0x80 : 0;
19181 inst
.instruction
|= is_double
? 0x100 : 0;
19182 do_vfp_cond_or_thumb ();
19186 do_neon_cvttb_1 (bfd_boolean t
)
19188 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19189 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19193 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19195 int single_to_half
= 0;
19196 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19199 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19201 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19202 && (flavour
== neon_cvt_flavour_u16_f16
19203 || flavour
== neon_cvt_flavour_s16_f16
19204 || flavour
== neon_cvt_flavour_f16_s16
19205 || flavour
== neon_cvt_flavour_f16_u16
19206 || flavour
== neon_cvt_flavour_u32_f32
19207 || flavour
== neon_cvt_flavour_s32_f32
19208 || flavour
== neon_cvt_flavour_f32_s32
19209 || flavour
== neon_cvt_flavour_f32_u32
))
19212 inst
.instruction
= N_MNEM_vcvt
;
19213 set_pred_insn_type (INSIDE_VPT_INSN
);
19214 do_neon_cvt_1 (neon_cvt_mode_z
);
19217 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19218 single_to_half
= 1;
19219 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19221 first_error (BAD_FPU
);
19225 inst
.instruction
= 0xee3f0e01;
19226 inst
.instruction
|= single_to_half
<< 28;
19227 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19228 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19229 inst
.instruction
|= t
<< 12;
19230 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19231 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19234 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19237 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19239 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19242 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19244 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19246 /* The VCVTB and VCVTT instructions with D-register operands
19247 don't work for SP only targets. */
19248 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19252 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19254 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19256 /* The VCVTB and VCVTT instructions with D-register operands
19257 don't work for SP only targets. */
19258 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19262 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19269 do_neon_cvtb (void)
19271 do_neon_cvttb_1 (FALSE
);
19276 do_neon_cvtt (void)
19278 do_neon_cvttb_1 (TRUE
);
19282 neon_move_immediate (void)
19284 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19285 struct neon_type_el et
= neon_check_type (2, rs
,
19286 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19287 unsigned immlo
, immhi
= 0, immbits
;
19288 int op
, cmode
, float_p
;
19290 constraint (et
.type
== NT_invtype
,
19291 _("operand size must be specified for immediate VMOV"));
19293 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19294 op
= (inst
.instruction
& (1 << 5)) != 0;
19296 immlo
= inst
.operands
[1].imm
;
19297 if (inst
.operands
[1].regisimm
)
19298 immhi
= inst
.operands
[1].reg
;
19300 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19301 _("immediate has bits set outside the operand size"));
19303 float_p
= inst
.operands
[1].immisfloat
;
19305 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19306 et
.size
, et
.type
)) == FAIL
)
19308 /* Invert relevant bits only. */
19309 neon_invert_size (&immlo
, &immhi
, et
.size
);
19310 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19311 with one or the other; those cases are caught by
19312 neon_cmode_for_move_imm. */
19314 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19315 &op
, et
.size
, et
.type
)) == FAIL
)
19317 first_error (_("immediate out of range"));
19322 inst
.instruction
&= ~(1 << 5);
19323 inst
.instruction
|= op
<< 5;
19325 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19326 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19327 inst
.instruction
|= neon_quad (rs
) << 6;
19328 inst
.instruction
|= cmode
<< 8;
19330 neon_write_immbits (immbits
);
19336 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19339 if (inst
.operands
[1].isreg
)
19341 enum neon_shape rs
;
19342 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19343 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19345 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19347 NEON_ENCODE (INTEGER
, inst
);
19348 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19349 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19350 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19351 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19352 inst
.instruction
|= neon_quad (rs
) << 6;
19356 NEON_ENCODE (IMMED
, inst
);
19357 neon_move_immediate ();
19360 neon_dp_fixup (&inst
);
19362 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19364 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19365 constraint ((inst
.instruction
& 0xd00) == 0xd00,
19366 _("immediate value out of range"));
19370 /* Encode instructions of form:
19372 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19373 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19376 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19378 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19379 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19380 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19381 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19382 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19383 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19384 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19385 inst
.instruction
|= neon_logbits (size
) << 20;
19387 neon_dp_fixup (&inst
);
19391 do_neon_dyadic_long (void)
19393 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19396 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19399 NEON_ENCODE (INTEGER
, inst
);
19400 /* FIXME: Type checking for lengthening op. */
19401 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19402 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19403 neon_mixed_length (et
, et
.size
);
19405 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19406 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19408 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19409 in an IT block with le/lt conditions. */
19411 if (inst
.cond
== 0xf)
19413 else if (inst
.cond
== 0x10)
19416 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19418 if (inst
.instruction
== N_MNEM_vaddl
)
19420 inst
.instruction
= N_MNEM_vadd
;
19421 do_neon_addsub_if_i ();
19423 else if (inst
.instruction
== N_MNEM_vsubl
)
19425 inst
.instruction
= N_MNEM_vsub
;
19426 do_neon_addsub_if_i ();
19428 else if (inst
.instruction
== N_MNEM_vabdl
)
19430 inst
.instruction
= N_MNEM_vabd
;
19431 do_neon_dyadic_if_su ();
19435 first_error (BAD_FPU
);
19439 do_neon_abal (void)
19441 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19442 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19443 neon_mixed_length (et
, et
.size
);
19447 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19449 if (inst
.operands
[2].isscalar
)
19451 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19452 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19453 NEON_ENCODE (SCALAR
, inst
);
19454 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19458 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19459 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19460 NEON_ENCODE (INTEGER
, inst
);
19461 neon_mixed_length (et
, et
.size
);
19466 do_neon_mac_maybe_scalar_long (void)
19468 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19471 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19472 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19475 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19477 unsigned regno
= NEON_SCALAR_REG (scalar
);
19478 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19482 if (regno
> 7 || elno
> 3)
19485 return ((regno
& 0x7)
19486 | ((elno
& 0x1) << 3)
19487 | (((elno
>> 1) & 0x1) << 5));
19491 if (regno
> 15 || elno
> 1)
19494 return (((regno
& 0x1) << 5)
19495 | ((regno
>> 1) & 0x7)
19496 | ((elno
& 0x1) << 3));
19500 first_error (_("scalar out of range for multiply instruction"));
19505 do_neon_fmac_maybe_scalar_long (int subtype
)
19507 enum neon_shape rs
;
19509 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19510 field (bits[21:20]) has different meaning. For scalar index variant, it's
19511 used to differentiate add and subtract, otherwise it's with fixed value
19515 if (inst
.cond
!= COND_ALWAYS
)
19516 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19517 "behaviour is UNPREDICTABLE"));
19519 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19522 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19525 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19526 be a scalar index register. */
19527 if (inst
.operands
[2].isscalar
)
19529 high8
= 0xfe000000;
19532 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19536 high8
= 0xfc000000;
19539 inst
.instruction
|= (0x1 << 23);
19540 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19543 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
19545 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19546 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19547 so we simply pass -1 as size. */
19548 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19549 neon_three_same (quad_p
, 0, size
);
19551 /* Undo neon_dp_fixup. Redo the high eight bits. */
19552 inst
.instruction
&= 0x00ffffff;
19553 inst
.instruction
|= high8
;
19555 #define LOW1(R) ((R) & 0x1)
19556 #define HI4(R) (((R) >> 1) & 0xf)
19557 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19558 whether the instruction is in Q form and whether Vm is a scalar indexed
19560 if (inst
.operands
[2].isscalar
)
19563 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19564 inst
.instruction
&= 0xffffffd0;
19565 inst
.instruction
|= rm
;
19569 /* Redo Rn as well. */
19570 inst
.instruction
&= 0xfff0ff7f;
19571 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19572 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19577 /* Redo Rn and Rm. */
19578 inst
.instruction
&= 0xfff0ff50;
19579 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19580 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19581 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19582 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19587 do_neon_vfmal (void)
19589 return do_neon_fmac_maybe_scalar_long (0);
19593 do_neon_vfmsl (void)
19595 return do_neon_fmac_maybe_scalar_long (1);
19599 do_neon_dyadic_wide (void)
19601 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19602 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19603 neon_mixed_length (et
, et
.size
);
19607 do_neon_dyadic_narrow (void)
19609 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19610 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19611 /* Operand sign is unimportant, and the U bit is part of the opcode,
19612 so force the operand type to integer. */
19613 et
.type
= NT_integer
;
19614 neon_mixed_length (et
, et
.size
/ 2);
19618 do_neon_mul_sat_scalar_long (void)
19620 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19624 do_neon_vmull (void)
19626 if (inst
.operands
[2].isscalar
)
19627 do_neon_mac_maybe_scalar_long ();
19630 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19631 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19633 if (et
.type
== NT_poly
)
19634 NEON_ENCODE (POLY
, inst
);
19636 NEON_ENCODE (INTEGER
, inst
);
19638 /* For polynomial encoding the U bit must be zero, and the size must
19639 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19640 obviously, as 0b10). */
19643 /* Check we're on the correct architecture. */
19644 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19646 _("Instruction form not available on this architecture.");
19651 neon_mixed_length (et
, et
.size
);
19658 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19659 struct neon_type_el et
= neon_check_type (3, rs
,
19660 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19661 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19663 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19664 _("shift out of range"));
19665 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19666 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19667 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19668 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19669 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19670 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19671 inst
.instruction
|= neon_quad (rs
) << 6;
19672 inst
.instruction
|= imm
<< 8;
19674 neon_dp_fixup (&inst
);
19680 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19683 enum neon_shape rs
;
19684 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19685 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19687 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19689 struct neon_type_el et
= neon_check_type (2, rs
,
19690 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19692 unsigned op
= (inst
.instruction
>> 7) & 3;
19693 /* N (width of reversed regions) is encoded as part of the bitmask. We
19694 extract it here to check the elements to be reversed are smaller.
19695 Otherwise we'd get a reserved instruction. */
19696 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19698 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19699 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19700 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19701 " operands makes instruction UNPREDICTABLE"));
19703 gas_assert (elsize
!= 0);
19704 constraint (et
.size
>= elsize
,
19705 _("elements must be smaller than reversal region"));
19706 neon_two_same (neon_quad (rs
), 1, et
.size
);
19712 if (inst
.operands
[1].isscalar
)
19714 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19716 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19717 struct neon_type_el et
= neon_check_type (2, rs
,
19718 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19719 unsigned sizebits
= et
.size
>> 3;
19720 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19721 int logsize
= neon_logbits (et
.size
);
19722 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19724 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19727 NEON_ENCODE (SCALAR
, inst
);
19728 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19729 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19730 inst
.instruction
|= LOW4 (dm
);
19731 inst
.instruction
|= HI1 (dm
) << 5;
19732 inst
.instruction
|= neon_quad (rs
) << 6;
19733 inst
.instruction
|= x
<< 17;
19734 inst
.instruction
|= sizebits
<< 16;
19736 neon_dp_fixup (&inst
);
19740 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19741 struct neon_type_el et
= neon_check_type (2, rs
,
19742 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19745 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19752 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19754 if (inst
.operands
[1].reg
== REG_SP
)
19755 as_tsktsk (MVE_BAD_SP
);
19756 else if (inst
.operands
[1].reg
== REG_PC
)
19757 as_tsktsk (MVE_BAD_PC
);
19760 /* Duplicate ARM register to lanes of vector. */
19761 NEON_ENCODE (ARMREG
, inst
);
19764 case 8: inst
.instruction
|= 0x400000; break;
19765 case 16: inst
.instruction
|= 0x000020; break;
19766 case 32: inst
.instruction
|= 0x000000; break;
19769 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19770 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19771 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19772 inst
.instruction
|= neon_quad (rs
) << 21;
19773 /* The encoding for this instruction is identical for the ARM and Thumb
19774 variants, except for the condition field. */
19775 do_vfp_cond_or_thumb ();
19780 do_mve_mov (int toQ
)
19782 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19784 if (inst
.cond
> COND_ALWAYS
)
19785 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19787 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19796 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19797 _("Index one must be [2,3] and index two must be two less than"
19799 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19800 _("General purpose registers may not be the same"));
19801 constraint (inst
.operands
[Rt
].reg
== REG_SP
19802 || inst
.operands
[Rt2
].reg
== REG_SP
,
19804 constraint (inst
.operands
[Rt
].reg
== REG_PC
19805 || inst
.operands
[Rt2
].reg
== REG_PC
,
19808 inst
.instruction
= 0xec000f00;
19809 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19810 inst
.instruction
|= !!toQ
<< 20;
19811 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19812 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19813 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19814 inst
.instruction
|= inst
.operands
[Rt
].reg
;
19820 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19823 if (inst
.cond
> COND_ALWAYS
)
19824 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19826 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
19828 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
19831 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19832 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
19833 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19834 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19835 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19840 /* VMOV has particularly many variations. It can be one of:
19841 0. VMOV<c><q> <Qd>, <Qm>
19842 1. VMOV<c><q> <Dd>, <Dm>
19843 (Register operations, which are VORR with Rm = Rn.)
19844 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19845 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19847 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19848 (ARM register to scalar.)
19849 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19850 (Two ARM registers to vector.)
19851 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19852 (Scalar to ARM register.)
19853 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19854 (Vector to two ARM registers.)
19855 8. VMOV.F32 <Sd>, <Sm>
19856 9. VMOV.F64 <Dd>, <Dm>
19857 (VFP register moves.)
19858 10. VMOV.F32 <Sd>, #imm
19859 11. VMOV.F64 <Dd>, #imm
19860 (VFP float immediate load.)
19861 12. VMOV <Rd>, <Sm>
19862 (VFP single to ARM reg.)
19863 13. VMOV <Sd>, <Rm>
19864 (ARM reg to VFP single.)
19865 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19866 (Two ARM regs to two VFP singles.)
19867 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19868 (Two VFP singles to two ARM regs.)
19869 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19870 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19871 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19872 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
19874 These cases can be disambiguated using neon_select_shape, except cases 1/9
19875 and 3/11 which depend on the operand type too.
19877 All the encoded bits are hardcoded by this function.
19879 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19880 Cases 5, 7 may be used with VFPv2 and above.
19882 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
19883 can specify a type where it doesn't make sense to, and is ignored). */
19888 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
19889 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
19890 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
19891 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
19893 struct neon_type_el et
;
19894 const char *ldconst
= 0;
19898 case NS_DD
: /* case 1/9. */
19899 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19900 /* It is not an error here if no type is given. */
19903 /* In MVE we interpret the following instructions as same, so ignoring
19904 the following type (float) and size (64) checks.
19905 a: VMOV<c><q> <Dd>, <Dm>
19906 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
19907 if ((et
.type
== NT_float
&& et
.size
== 64)
19908 || (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
19910 do_vfp_nsyn_opcode ("fcpyd");
19913 /* fall through. */
19915 case NS_QQ
: /* case 0/1. */
19917 if (!check_simd_pred_availability (FALSE
,
19918 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19920 /* The architecture manual I have doesn't explicitly state which
19921 value the U bit should have for register->register moves, but
19922 the equivalent VORR instruction has U = 0, so do that. */
19923 inst
.instruction
= 0x0200110;
19924 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19925 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19926 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19927 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19928 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19929 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19930 inst
.instruction
|= neon_quad (rs
) << 6;
19932 neon_dp_fixup (&inst
);
19936 case NS_DI
: /* case 3/11. */
19937 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19939 if (et
.type
== NT_float
&& et
.size
== 64)
19941 /* case 11 (fconstd). */
19942 ldconst
= "fconstd";
19943 goto encode_fconstd
;
19945 /* fall through. */
19947 case NS_QI
: /* case 2/3. */
19948 if (!check_simd_pred_availability (FALSE
,
19949 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19951 inst
.instruction
= 0x0800010;
19952 neon_move_immediate ();
19953 neon_dp_fixup (&inst
);
19956 case NS_SR
: /* case 4. */
19958 unsigned bcdebits
= 0;
19960 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
19961 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
19963 /* .<size> is optional here, defaulting to .32. */
19964 if (inst
.vectype
.elems
== 0
19965 && inst
.operands
[0].vectype
.type
== NT_invtype
19966 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19968 inst
.vectype
.el
[0].type
= NT_untyped
;
19969 inst
.vectype
.el
[0].size
= 32;
19970 inst
.vectype
.elems
= 1;
19973 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19974 logsize
= neon_logbits (et
.size
);
19978 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19979 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
19984 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19985 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19989 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19991 if (inst
.operands
[1].reg
== REG_SP
)
19992 as_tsktsk (MVE_BAD_SP
);
19993 else if (inst
.operands
[1].reg
== REG_PC
)
19994 as_tsktsk (MVE_BAD_PC
);
19996 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
19998 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19999 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20004 case 8: bcdebits
= 0x8; break;
20005 case 16: bcdebits
= 0x1; break;
20006 case 32: bcdebits
= 0x0; break;
20010 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20012 inst
.instruction
= 0xe000b10;
20013 do_vfp_cond_or_thumb ();
20014 inst
.instruction
|= LOW4 (dn
) << 16;
20015 inst
.instruction
|= HI1 (dn
) << 7;
20016 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20017 inst
.instruction
|= (bcdebits
& 3) << 5;
20018 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
20019 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20023 case NS_DRR
: /* case 5 (fmdrr). */
20024 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20025 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20028 inst
.instruction
= 0xc400b10;
20029 do_vfp_cond_or_thumb ();
20030 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
20031 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
20032 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20033 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
20036 case NS_RS
: /* case 6. */
20039 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
20040 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
20041 unsigned abcdebits
= 0;
20043 /* .<dt> is optional here, defaulting to .32. */
20044 if (inst
.vectype
.elems
== 0
20045 && inst
.operands
[0].vectype
.type
== NT_invtype
20046 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20048 inst
.vectype
.el
[0].type
= NT_untyped
;
20049 inst
.vectype
.el
[0].size
= 32;
20050 inst
.vectype
.elems
= 1;
20053 et
= neon_check_type (2, NS_NULL
,
20054 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20055 logsize
= neon_logbits (et
.size
);
20059 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20060 && vfp_or_neon_is_neon (NEON_CHECK_CC
20061 | NEON_CHECK_ARCH
) == FAIL
)
20066 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20067 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20071 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20073 if (inst
.operands
[0].reg
== REG_SP
)
20074 as_tsktsk (MVE_BAD_SP
);
20075 else if (inst
.operands
[0].reg
== REG_PC
)
20076 as_tsktsk (MVE_BAD_PC
);
20079 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20081 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20082 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20086 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20087 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20088 case 32: abcdebits
= 0x00; break;
20092 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20093 inst
.instruction
= 0xe100b10;
20094 do_vfp_cond_or_thumb ();
20095 inst
.instruction
|= LOW4 (dn
) << 16;
20096 inst
.instruction
|= HI1 (dn
) << 7;
20097 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20098 inst
.instruction
|= (abcdebits
& 3) << 5;
20099 inst
.instruction
|= (abcdebits
>> 2) << 21;
20100 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20104 case NS_RRD
: /* case 7 (fmrrd). */
20105 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20106 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20109 inst
.instruction
= 0xc500b10;
20110 do_vfp_cond_or_thumb ();
20111 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20112 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20113 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20114 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20117 case NS_FF
: /* case 8 (fcpys). */
20118 do_vfp_nsyn_opcode ("fcpys");
20122 case NS_FI
: /* case 10 (fconsts). */
20123 ldconst
= "fconsts";
20125 if (!inst
.operands
[1].immisfloat
)
20128 /* Immediate has to fit in 8 bits so float is enough. */
20129 float imm
= (float) inst
.operands
[1].imm
;
20130 memcpy (&new_imm
, &imm
, sizeof (float));
20131 /* But the assembly may have been written to provide an integer
20132 bit pattern that equates to a float, so check that the
20133 conversion has worked. */
20134 if (is_quarter_float (new_imm
))
20136 if (is_quarter_float (inst
.operands
[1].imm
))
20137 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20139 inst
.operands
[1].imm
= new_imm
;
20140 inst
.operands
[1].immisfloat
= 1;
20144 if (is_quarter_float (inst
.operands
[1].imm
))
20146 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20147 do_vfp_nsyn_opcode (ldconst
);
20149 /* ARMv8.2 fp16 vmov.f16 instruction. */
20151 do_scalar_fp16_v82_encode ();
20154 first_error (_("immediate out of range"));
20158 case NS_RF
: /* case 12 (fmrs). */
20159 do_vfp_nsyn_opcode ("fmrs");
20160 /* ARMv8.2 fp16 vmov.f16 instruction. */
20162 do_scalar_fp16_v82_encode ();
20166 case NS_FR
: /* case 13 (fmsr). */
20167 do_vfp_nsyn_opcode ("fmsr");
20168 /* ARMv8.2 fp16 vmov.f16 instruction. */
20170 do_scalar_fp16_v82_encode ();
20180 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20181 (one of which is a list), but we have parsed four. Do some fiddling to
20182 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20184 case NS_RRFF
: /* case 14 (fmrrs). */
20185 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20186 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20188 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20189 _("VFP registers must be adjacent"));
20190 inst
.operands
[2].imm
= 2;
20191 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20192 do_vfp_nsyn_opcode ("fmrrs");
20195 case NS_FFRR
: /* case 15 (fmsrr). */
20196 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20197 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20199 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20200 _("VFP registers must be adjacent"));
20201 inst
.operands
[1] = inst
.operands
[2];
20202 inst
.operands
[2] = inst
.operands
[3];
20203 inst
.operands
[0].imm
= 2;
20204 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20205 do_vfp_nsyn_opcode ("fmsrr");
20209 /* neon_select_shape has determined that the instruction
20210 shape is wrong and has already set the error message. */
20221 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20222 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20223 && !inst
.operands
[2].present
))
20225 inst
.instruction
= 0;
20228 set_pred_insn_type (INSIDE_IT_INSN
);
20233 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20236 if (inst
.cond
!= COND_ALWAYS
)
20237 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20239 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20240 | N_S16
| N_U16
| N_KEY
);
20242 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20243 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20244 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20245 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20246 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20247 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20252 do_neon_rshift_round_imm (void)
20254 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20257 enum neon_shape rs
;
20258 struct neon_type_el et
;
20260 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20262 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20263 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20267 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20268 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20270 int imm
= inst
.operands
[2].imm
;
20272 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20275 inst
.operands
[2].present
= 0;
20280 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20281 _("immediate out of range for shift"));
20282 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20287 do_neon_movhf (void)
20289 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20290 constraint (rs
!= NS_HH
, _("invalid suffix"));
20292 if (inst
.cond
!= COND_ALWAYS
)
20296 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20297 " the behaviour is UNPREDICTABLE"));
20301 inst
.error
= BAD_COND
;
20306 do_vfp_sp_monadic ();
20309 inst
.instruction
|= 0xf0000000;
20313 do_neon_movl (void)
20315 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20316 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20317 unsigned sizebits
= et
.size
>> 3;
20318 inst
.instruction
|= sizebits
<< 19;
20319 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20325 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20326 struct neon_type_el et
= neon_check_type (2, rs
,
20327 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20328 NEON_ENCODE (INTEGER
, inst
);
20329 neon_two_same (neon_quad (rs
), 1, et
.size
);
20333 do_neon_zip_uzp (void)
20335 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20336 struct neon_type_el et
= neon_check_type (2, rs
,
20337 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20338 if (rs
== NS_DD
&& et
.size
== 32)
20340 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20341 inst
.instruction
= N_MNEM_vtrn
;
20345 neon_two_same (neon_quad (rs
), 1, et
.size
);
20349 do_neon_sat_abs_neg (void)
20351 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20354 enum neon_shape rs
;
20355 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20356 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20358 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20359 struct neon_type_el et
= neon_check_type (2, rs
,
20360 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20361 neon_two_same (neon_quad (rs
), 1, et
.size
);
20365 do_neon_pair_long (void)
20367 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20368 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20369 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20370 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20371 neon_two_same (neon_quad (rs
), 1, et
.size
);
20375 do_neon_recip_est (void)
20377 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20378 struct neon_type_el et
= neon_check_type (2, rs
,
20379 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20380 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20381 neon_two_same (neon_quad (rs
), 1, et
.size
);
20387 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20390 enum neon_shape rs
;
20391 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20392 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20394 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20396 struct neon_type_el et
= neon_check_type (2, rs
,
20397 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20398 neon_two_same (neon_quad (rs
), 1, et
.size
);
20404 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20407 enum neon_shape rs
;
20408 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20409 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20411 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20413 struct neon_type_el et
= neon_check_type (2, rs
,
20414 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20415 neon_two_same (neon_quad (rs
), 1, et
.size
);
20421 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20422 struct neon_type_el et
= neon_check_type (2, rs
,
20423 N_EQK
| N_INT
, N_8
| N_KEY
);
20424 neon_two_same (neon_quad (rs
), 1, et
.size
);
20430 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20431 neon_two_same (neon_quad (rs
), 1, -1);
20435 do_neon_tbl_tbx (void)
20437 unsigned listlenbits
;
20438 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20440 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20442 first_error (_("bad list length for table lookup"));
20446 listlenbits
= inst
.operands
[1].imm
- 1;
20447 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20448 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20449 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20450 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20451 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20452 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20453 inst
.instruction
|= listlenbits
<< 8;
20455 neon_dp_fixup (&inst
);
20459 do_neon_ldm_stm (void)
20461 /* P, U and L bits are part of bitmask. */
20462 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20463 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20465 if (inst
.operands
[1].issingle
)
20467 do_vfp_nsyn_ldm_stm (is_dbmode
);
20471 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20472 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20474 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20475 _("register list must contain at least 1 and at most 16 "
20478 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20479 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20480 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20481 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20483 inst
.instruction
|= offsetbits
;
20485 do_vfp_cond_or_thumb ();
20489 do_neon_ldr_str (void)
20491 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20493 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20494 And is UNPREDICTABLE in thumb mode. */
20496 && inst
.operands
[1].reg
== REG_PC
20497 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20500 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20501 else if (warn_on_deprecated
)
20502 as_tsktsk (_("Use of PC here is deprecated"));
20505 if (inst
.operands
[0].issingle
)
20508 do_vfp_nsyn_opcode ("flds");
20510 do_vfp_nsyn_opcode ("fsts");
20512 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20513 if (inst
.vectype
.el
[0].size
== 16)
20514 do_scalar_fp16_v82_encode ();
20519 do_vfp_nsyn_opcode ("fldd");
20521 do_vfp_nsyn_opcode ("fstd");
20526 do_t_vldr_vstr_sysreg (void)
20528 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20529 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20531 /* Use of PC is UNPREDICTABLE. */
20532 if (inst
.operands
[1].reg
== REG_PC
)
20533 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20535 if (inst
.operands
[1].immisreg
)
20536 inst
.error
= _("instruction does not accept register index");
20538 if (!inst
.operands
[1].isreg
)
20539 inst
.error
= _("instruction does not accept PC-relative addressing");
20541 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20542 inst
.error
= _("immediate value out of range");
20544 inst
.instruction
= 0xec000f80;
20546 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20547 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20548 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20549 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20553 do_vldr_vstr (void)
20555 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20557 /* VLDR/VSTR (System Register). */
20560 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20561 as_bad (_("Instruction not permitted on this architecture"));
20563 do_t_vldr_vstr_sysreg ();
20568 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20569 as_bad (_("Instruction not permitted on this architecture"));
20570 do_neon_ldr_str ();
20574 /* "interleave" version also handles non-interleaving register VLD1/VST1
20578 do_neon_ld_st_interleave (void)
20580 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20581 N_8
| N_16
| N_32
| N_64
);
20582 unsigned alignbits
= 0;
20584 /* The bits in this table go:
20585 0: register stride of one (0) or two (1)
20586 1,2: register list length, minus one (1, 2, 3, 4).
20587 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20588 We use -1 for invalid entries. */
20589 const int typetable
[] =
20591 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20592 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20593 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20594 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20598 if (et
.type
== NT_invtype
)
20601 if (inst
.operands
[1].immisalign
)
20602 switch (inst
.operands
[1].imm
>> 8)
20604 case 64: alignbits
= 1; break;
20606 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20607 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20608 goto bad_alignment
;
20612 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20613 goto bad_alignment
;
20618 first_error (_("bad alignment"));
20622 inst
.instruction
|= alignbits
<< 4;
20623 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20625 /* Bits [4:6] of the immediate in a list specifier encode register stride
20626 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20627 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20628 up the right value for "type" in a table based on this value and the given
20629 list style, then stick it back. */
20630 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20631 | (((inst
.instruction
>> 8) & 3) << 3);
20633 typebits
= typetable
[idx
];
20635 constraint (typebits
== -1, _("bad list type for instruction"));
20636 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20639 inst
.instruction
&= ~0xf00;
20640 inst
.instruction
|= typebits
<< 8;
20643 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20644 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20645 otherwise. The variable arguments are a list of pairs of legal (size, align)
20646 values, terminated with -1. */
20649 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20652 int result
= FAIL
, thissize
, thisalign
;
20654 if (!inst
.operands
[1].immisalign
)
20660 va_start (ap
, do_alignment
);
20664 thissize
= va_arg (ap
, int);
20665 if (thissize
== -1)
20667 thisalign
= va_arg (ap
, int);
20669 if (size
== thissize
&& align
== thisalign
)
20672 while (result
!= SUCCESS
);
20676 if (result
== SUCCESS
)
20679 first_error (_("unsupported alignment for instruction"));
20685 do_neon_ld_st_lane (void)
20687 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20688 int align_good
, do_alignment
= 0;
20689 int logsize
= neon_logbits (et
.size
);
20690 int align
= inst
.operands
[1].imm
>> 8;
20691 int n
= (inst
.instruction
>> 8) & 3;
20692 int max_el
= 64 / et
.size
;
20694 if (et
.type
== NT_invtype
)
20697 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20698 _("bad list length"));
20699 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20700 _("scalar index out of range"));
20701 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20703 _("stride of 2 unavailable when element size is 8"));
20707 case 0: /* VLD1 / VST1. */
20708 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20710 if (align_good
== FAIL
)
20714 unsigned alignbits
= 0;
20717 case 16: alignbits
= 0x1; break;
20718 case 32: alignbits
= 0x3; break;
20721 inst
.instruction
|= alignbits
<< 4;
20725 case 1: /* VLD2 / VST2. */
20726 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20727 16, 32, 32, 64, -1);
20728 if (align_good
== FAIL
)
20731 inst
.instruction
|= 1 << 4;
20734 case 2: /* VLD3 / VST3. */
20735 constraint (inst
.operands
[1].immisalign
,
20736 _("can't use alignment with this instruction"));
20739 case 3: /* VLD4 / VST4. */
20740 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20741 16, 64, 32, 64, 32, 128, -1);
20742 if (align_good
== FAIL
)
20746 unsigned alignbits
= 0;
20749 case 8: alignbits
= 0x1; break;
20750 case 16: alignbits
= 0x1; break;
20751 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20754 inst
.instruction
|= alignbits
<< 4;
20761 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20762 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20763 inst
.instruction
|= 1 << (4 + logsize
);
20765 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20766 inst
.instruction
|= logsize
<< 10;
20769 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20772 do_neon_ld_dup (void)
20774 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20775 int align_good
, do_alignment
= 0;
20777 if (et
.type
== NT_invtype
)
20780 switch ((inst
.instruction
>> 8) & 3)
20782 case 0: /* VLD1. */
20783 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20784 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20785 &do_alignment
, 16, 16, 32, 32, -1);
20786 if (align_good
== FAIL
)
20788 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20791 case 2: inst
.instruction
|= 1 << 5; break;
20792 default: first_error (_("bad list length")); return;
20794 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20797 case 1: /* VLD2. */
20798 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20799 &do_alignment
, 8, 16, 16, 32, 32, 64,
20801 if (align_good
== FAIL
)
20803 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20804 _("bad list length"));
20805 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20806 inst
.instruction
|= 1 << 5;
20807 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20810 case 2: /* VLD3. */
20811 constraint (inst
.operands
[1].immisalign
,
20812 _("can't use alignment with this instruction"));
20813 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20814 _("bad list length"));
20815 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20816 inst
.instruction
|= 1 << 5;
20817 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20820 case 3: /* VLD4. */
20822 int align
= inst
.operands
[1].imm
>> 8;
20823 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20824 16, 64, 32, 64, 32, 128, -1);
20825 if (align_good
== FAIL
)
20827 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
20828 _("bad list length"));
20829 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20830 inst
.instruction
|= 1 << 5;
20831 if (et
.size
== 32 && align
== 128)
20832 inst
.instruction
|= 0x3 << 6;
20834 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20841 inst
.instruction
|= do_alignment
<< 4;
20844 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20845 apart from bits [11:4]. */
20848 do_neon_ldx_stx (void)
20850 if (inst
.operands
[1].isreg
)
20851 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
20853 switch (NEON_LANE (inst
.operands
[0].imm
))
20855 case NEON_INTERLEAVE_LANES
:
20856 NEON_ENCODE (INTERLV
, inst
);
20857 do_neon_ld_st_interleave ();
20860 case NEON_ALL_LANES
:
20861 NEON_ENCODE (DUP
, inst
);
20862 if (inst
.instruction
== N_INV
)
20864 first_error ("only loads support such operands");
20871 NEON_ENCODE (LANE
, inst
);
20872 do_neon_ld_st_lane ();
20875 /* L bit comes from bit mask. */
20876 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20877 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20878 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20880 if (inst
.operands
[1].postind
)
20882 int postreg
= inst
.operands
[1].imm
& 0xf;
20883 constraint (!inst
.operands
[1].immisreg
,
20884 _("post-index must be a register"));
20885 constraint (postreg
== 0xd || postreg
== 0xf,
20886 _("bad register for post-index"));
20887 inst
.instruction
|= postreg
;
20891 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
20892 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
20893 || inst
.relocs
[0].exp
.X_add_number
!= 0,
20896 if (inst
.operands
[1].writeback
)
20898 inst
.instruction
|= 0xd;
20901 inst
.instruction
|= 0xf;
20905 inst
.instruction
|= 0xf9000000;
20907 inst
.instruction
|= 0xf4000000;
20912 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
20914 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20915 D register operands. */
20916 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20917 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20920 NEON_ENCODE (FPV8
, inst
);
20922 if (rs
== NS_FFF
|| rs
== NS_HHH
)
20924 do_vfp_sp_dyadic ();
20926 /* ARMv8.2 fp16 instruction. */
20928 do_scalar_fp16_v82_encode ();
20931 do_vfp_dp_rd_rn_rm ();
20934 inst
.instruction
|= 0x100;
20936 inst
.instruction
|= 0xf0000000;
20942 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20944 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
20945 first_error (_("invalid instruction shape"));
20951 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20952 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20954 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
20957 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20960 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
20964 do_vrint_1 (enum neon_cvt_mode mode
)
20966 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
20967 struct neon_type_el et
;
20972 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20973 D register operands. */
20974 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20975 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20978 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
20980 if (et
.type
!= NT_invtype
)
20982 /* VFP encodings. */
20983 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
20984 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
20985 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20987 NEON_ENCODE (FPV8
, inst
);
20988 if (rs
== NS_FF
|| rs
== NS_HH
)
20989 do_vfp_sp_monadic ();
20991 do_vfp_dp_rd_rm ();
20995 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
20996 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
20997 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
20998 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
20999 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
21000 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
21001 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
21005 inst
.instruction
|= (rs
== NS_DD
) << 8;
21006 do_vfp_cond_or_thumb ();
21008 /* ARMv8.2 fp16 vrint instruction. */
21010 do_scalar_fp16_v82_encode ();
21014 /* Neon encodings (or something broken...). */
21016 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
21018 if (et
.type
== NT_invtype
)
21021 if (!check_simd_pred_availability (TRUE
,
21022 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21025 NEON_ENCODE (FLOAT
, inst
);
21027 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21028 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21029 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21030 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21031 inst
.instruction
|= neon_quad (rs
) << 6;
21032 /* Mask off the original size bits and reencode them. */
21033 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
21034 | neon_logbits (et
.size
) << 18);
21038 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
21039 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
21040 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
21041 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
21042 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
21043 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
21044 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21049 inst
.instruction
|= 0xfc000000;
21051 inst
.instruction
|= 0xf0000000;
21058 do_vrint_1 (neon_cvt_mode_x
);
21064 do_vrint_1 (neon_cvt_mode_z
);
21070 do_vrint_1 (neon_cvt_mode_r
);
21076 do_vrint_1 (neon_cvt_mode_a
);
21082 do_vrint_1 (neon_cvt_mode_n
);
21088 do_vrint_1 (neon_cvt_mode_p
);
21094 do_vrint_1 (neon_cvt_mode_m
);
21098 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21100 unsigned regno
= NEON_SCALAR_REG (opnd
);
21101 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21103 if (elsize
== 16 && elno
< 2 && regno
< 16)
21104 return regno
| (elno
<< 4);
21105 else if (elsize
== 32 && elno
== 0)
21108 first_error (_("scalar out of range"));
21115 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21116 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21117 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21118 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21119 _("expression too complex"));
21120 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21121 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21122 _("immediate out of range"));
21125 if (!check_simd_pred_availability (TRUE
,
21126 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21129 if (inst
.operands
[2].isscalar
)
21131 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21132 first_error (_("invalid instruction shape"));
21133 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21134 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21135 N_KEY
| N_F16
| N_F32
).size
;
21136 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21138 inst
.instruction
= 0xfe000800;
21139 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21140 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21141 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21142 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21143 inst
.instruction
|= LOW4 (m
);
21144 inst
.instruction
|= HI1 (m
) << 5;
21145 inst
.instruction
|= neon_quad (rs
) << 6;
21146 inst
.instruction
|= rot
<< 20;
21147 inst
.instruction
|= (size
== 32) << 23;
21151 enum neon_shape rs
;
21152 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21153 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21155 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21157 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21158 N_KEY
| N_F16
| N_F32
).size
;
21159 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21160 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21161 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21162 as_tsktsk (BAD_MVE_SRCDEST
);
21164 neon_three_same (neon_quad (rs
), 0, -1);
21165 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21166 inst
.instruction
|= 0xfc200800;
21167 inst
.instruction
|= rot
<< 23;
21168 inst
.instruction
|= (size
== 32) << 20;
21175 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21176 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21177 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21178 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21179 _("expression too complex"));
21181 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21182 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21183 enum neon_shape rs
;
21184 struct neon_type_el et
;
21185 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21187 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21188 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21192 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21193 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21195 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21196 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21197 "operand makes instruction UNPREDICTABLE"));
21200 if (et
.type
== NT_invtype
)
21203 if (!check_simd_pred_availability (et
.type
== NT_float
,
21204 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21207 if (et
.type
== NT_float
)
21209 neon_three_same (neon_quad (rs
), 0, -1);
21210 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21211 inst
.instruction
|= 0xfc800800;
21212 inst
.instruction
|= (rot
== 270) << 24;
21213 inst
.instruction
|= (et
.size
== 32) << 20;
21217 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21218 inst
.instruction
= 0xfe000f00;
21219 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21220 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21221 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21222 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21223 inst
.instruction
|= (rot
== 270) << 12;
21224 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21225 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21226 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21231 /* Dot Product instructions encoding support. */
21234 do_neon_dotproduct (int unsigned_p
)
21236 enum neon_shape rs
;
21237 unsigned scalar_oprd2
= 0;
21240 if (inst
.cond
!= COND_ALWAYS
)
21241 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21242 "is UNPREDICTABLE"));
21244 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21247 /* Dot Product instructions are in three-same D/Q register format or the third
21248 operand can be a scalar index register. */
21249 if (inst
.operands
[2].isscalar
)
21251 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21252 high8
= 0xfe000000;
21253 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21257 high8
= 0xfc000000;
21258 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21262 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21264 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21266 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21267 Product instruction, so we pass 0 as the "ubit" parameter. And the
21268 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21269 neon_three_same (neon_quad (rs
), 0, 32);
21271 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21272 different NEON three-same encoding. */
21273 inst
.instruction
&= 0x00ffffff;
21274 inst
.instruction
|= high8
;
21275 /* Encode 'U' bit which indicates signedness. */
21276 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21277 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21278 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21279 the instruction encoding. */
21280 if (inst
.operands
[2].isscalar
)
21282 inst
.instruction
&= 0xffffffd0;
21283 inst
.instruction
|= LOW4 (scalar_oprd2
);
21284 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21288 /* Dot Product instructions for signed integer. */
21291 do_neon_dotproduct_s (void)
21293 return do_neon_dotproduct (0);
21296 /* Dot Product instructions for unsigned integer. */
21299 do_neon_dotproduct_u (void)
21301 return do_neon_dotproduct (1);
21304 /* Crypto v1 instructions. */
21306 do_crypto_2op_1 (unsigned elttype
, int op
)
21308 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21310 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
21316 NEON_ENCODE (INTEGER
, inst
);
21317 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21318 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21319 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21320 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21322 inst
.instruction
|= op
<< 6;
21325 inst
.instruction
|= 0xfc000000;
21327 inst
.instruction
|= 0xf0000000;
21331 do_crypto_3op_1 (int u
, int op
)
21333 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21335 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
21336 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
21341 NEON_ENCODE (INTEGER
, inst
);
21342 neon_three_same (1, u
, 8 << op
);
21348 do_crypto_2op_1 (N_8
, 0);
21354 do_crypto_2op_1 (N_8
, 1);
21360 do_crypto_2op_1 (N_8
, 2);
21366 do_crypto_2op_1 (N_8
, 3);
21372 do_crypto_3op_1 (0, 0);
21378 do_crypto_3op_1 (0, 1);
21384 do_crypto_3op_1 (0, 2);
21390 do_crypto_3op_1 (0, 3);
21396 do_crypto_3op_1 (1, 0);
21402 do_crypto_3op_1 (1, 1);
21406 do_sha256su1 (void)
21408 do_crypto_3op_1 (1, 2);
21414 do_crypto_2op_1 (N_32
, -1);
21420 do_crypto_2op_1 (N_32
, 0);
21424 do_sha256su0 (void)
21426 do_crypto_2op_1 (N_32
, 1);
21430 do_crc32_1 (unsigned int poly
, unsigned int sz
)
21432 unsigned int Rd
= inst
.operands
[0].reg
;
21433 unsigned int Rn
= inst
.operands
[1].reg
;
21434 unsigned int Rm
= inst
.operands
[2].reg
;
21436 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21437 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
21438 inst
.instruction
|= LOW4 (Rn
) << 16;
21439 inst
.instruction
|= LOW4 (Rm
);
21440 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
21441 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
21443 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
21444 as_warn (UNPRED_REG ("r15"));
21486 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21488 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
21489 do_vfp_sp_dp_cvt ();
21490 do_vfp_cond_or_thumb ();
21494 /* Overall per-instruction processing. */
21496 /* We need to be able to fix up arbitrary expressions in some statements.
21497 This is so that we can handle symbols that are an arbitrary distance from
21498 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21499 which returns part of an address in a form which will be valid for
21500 a data instruction. We do this by pushing the expression into a symbol
21501 in the expr_section, and creating a fix for that. */
21504 fix_new_arm (fragS
* frag
,
21518 /* Create an absolute valued symbol, so we have something to
21519 refer to in the object file. Unfortunately for us, gas's
21520 generic expression parsing will already have folded out
21521 any use of .set foo/.type foo %function that may have
21522 been used to set type information of the target location,
21523 that's being specified symbolically. We have to presume
21524 the user knows what they are doing. */
21528 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
21530 symbol
= symbol_find_or_make (name
);
21531 S_SET_SEGMENT (symbol
, absolute_section
);
21532 symbol_set_frag (symbol
, &zero_address_frag
);
21533 S_SET_VALUE (symbol
, exp
->X_add_number
);
21534 exp
->X_op
= O_symbol
;
21535 exp
->X_add_symbol
= symbol
;
21536 exp
->X_add_number
= 0;
21542 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
21543 (enum bfd_reloc_code_real
) reloc
);
21547 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21548 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21552 /* Mark whether the fix is to a THUMB instruction, or an ARM
21554 new_fix
->tc_fix_data
= thumb_mode
;
21557 /* Create a frg for an instruction requiring relaxation. */
21559 output_relax_insn (void)
21565 /* The size of the instruction is unknown, so tie the debug info to the
21566 start of the instruction. */
21567 dwarf2_emit_insn (0);
21569 switch (inst
.relocs
[0].exp
.X_op
)
21572 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21573 offset
= inst
.relocs
[0].exp
.X_add_number
;
21577 offset
= inst
.relocs
[0].exp
.X_add_number
;
21580 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21584 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21585 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21586 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21589 /* Write a 32-bit thumb instruction to buf. */
21591 put_thumb32_insn (char * buf
, unsigned long insn
)
21593 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21594 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21598 output_inst (const char * str
)
21604 as_bad ("%s -- `%s'", inst
.error
, str
);
21609 output_relax_insn ();
21612 if (inst
.size
== 0)
21615 to
= frag_more (inst
.size
);
21616 /* PR 9814: Record the thumb mode into the current frag so that we know
21617 what type of NOP padding to use, if necessary. We override any previous
21618 setting so that if the mode has changed then the NOPS that we use will
21619 match the encoding of the last instruction in the frag. */
21620 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21622 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21624 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21625 put_thumb32_insn (to
, inst
.instruction
);
21627 else if (inst
.size
> INSN_SIZE
)
21629 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21630 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21631 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21634 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21637 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21639 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21640 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21641 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21642 inst
.relocs
[r
].type
);
21645 dwarf2_emit_insn (inst
.size
);
21649 output_it_inst (int cond
, int mask
, char * to
)
21651 unsigned long instruction
= 0xbf00;
21654 instruction
|= mask
;
21655 instruction
|= cond
<< 4;
21659 to
= frag_more (2);
21661 dwarf2_emit_insn (2);
21665 md_number_to_chars (to
, instruction
, 2);
21670 /* Tag values used in struct asm_opcode's tag field. */
21673 OT_unconditional
, /* Instruction cannot be conditionalized.
21674 The ARM condition field is still 0xE. */
21675 OT_unconditionalF
, /* Instruction cannot be conditionalized
21676 and carries 0xF in its ARM condition field. */
21677 OT_csuffix
, /* Instruction takes a conditional suffix. */
21678 OT_csuffixF
, /* Some forms of the instruction take a scalar
21679 conditional suffix, others place 0xF where the
21680 condition field would be, others take a vector
21681 conditional suffix. */
21682 OT_cinfix3
, /* Instruction takes a conditional infix,
21683 beginning at character index 3. (In
21684 unified mode, it becomes a suffix.) */
21685 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21686 tsts, cmps, cmns, and teqs. */
21687 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21688 character index 3, even in unified mode. Used for
21689 legacy instructions where suffix and infix forms
21690 may be ambiguous. */
21691 OT_csuf_or_in3
, /* Instruction takes either a conditional
21692 suffix or an infix at character index 3. */
21693 OT_odd_infix_unc
, /* This is the unconditional variant of an
21694 instruction that takes a conditional infix
21695 at an unusual position. In unified mode,
21696 this variant will accept a suffix. */
21697 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21698 are the conditional variants of instructions that
21699 take conditional infixes in unusual positions.
21700 The infix appears at character index
21701 (tag - OT_odd_infix_0). These are not accepted
21702 in unified mode. */
21705 /* Subroutine of md_assemble, responsible for looking up the primary
21706 opcode from the mnemonic the user wrote. STR points to the
21707 beginning of the mnemonic.
21709 This is not simply a hash table lookup, because of conditional
21710 variants. Most instructions have conditional variants, which are
21711 expressed with a _conditional affix_ to the mnemonic. If we were
21712 to encode each conditional variant as a literal string in the opcode
21713 table, it would have approximately 20,000 entries.
21715 Most mnemonics take this affix as a suffix, and in unified syntax,
21716 'most' is upgraded to 'all'. However, in the divided syntax, some
21717 instructions take the affix as an infix, notably the s-variants of
21718 the arithmetic instructions. Of those instructions, all but six
21719 have the infix appear after the third character of the mnemonic.
21721 Accordingly, the algorithm for looking up primary opcodes given
21724 1. Look up the identifier in the opcode table.
21725 If we find a match, go to step U.
21727 2. Look up the last two characters of the identifier in the
21728 conditions table. If we find a match, look up the first N-2
21729 characters of the identifier in the opcode table. If we
21730 find a match, go to step CE.
21732 3. Look up the fourth and fifth characters of the identifier in
21733 the conditions table. If we find a match, extract those
21734 characters from the identifier, and look up the remaining
21735 characters in the opcode table. If we find a match, go
21740 U. Examine the tag field of the opcode structure, in case this is
21741 one of the six instructions with its conditional infix in an
21742 unusual place. If it is, the tag tells us where to find the
21743 infix; look it up in the conditions table and set inst.cond
21744 accordingly. Otherwise, this is an unconditional instruction.
21745 Again set inst.cond accordingly. Return the opcode structure.
21747 CE. Examine the tag field to make sure this is an instruction that
21748 should receive a conditional suffix. If it is not, fail.
21749 Otherwise, set inst.cond from the suffix we already looked up,
21750 and return the opcode structure.
21752 CM. Examine the tag field to make sure this is an instruction that
21753 should receive a conditional infix after the third character.
21754 If it is not, fail. Otherwise, undo the edits to the current
21755 line of input and proceed as for case CE. */
21757 static const struct asm_opcode
*
21758 opcode_lookup (char **str
)
21762 const struct asm_opcode
*opcode
;
21763 const struct asm_cond
*cond
;
21766 /* Scan up to the end of the mnemonic, which must end in white space,
21767 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
21768 for (base
= end
= *str
; *end
!= '\0'; end
++)
21769 if (*end
== ' ' || *end
== '.')
21775 /* Handle a possible width suffix and/or Neon type suffix. */
21780 /* The .w and .n suffixes are only valid if the unified syntax is in
21782 if (unified_syntax
&& end
[1] == 'w')
21784 else if (unified_syntax
&& end
[1] == 'n')
21789 inst
.vectype
.elems
= 0;
21791 *str
= end
+ offset
;
21793 if (end
[offset
] == '.')
21795 /* See if we have a Neon type suffix (possible in either unified or
21796 non-unified ARM syntax mode). */
21797 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
21800 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
21806 /* Look for unaffixed or special-case affixed mnemonic. */
21807 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21812 if (opcode
->tag
< OT_odd_infix_0
)
21814 inst
.cond
= COND_ALWAYS
;
21818 if (warn_on_deprecated
&& unified_syntax
)
21819 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21820 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
21821 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21824 inst
.cond
= cond
->value
;
21827 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21829 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21831 if (end
- base
< 2)
21834 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
21835 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21837 /* If this opcode can not be vector predicated then don't accept it with a
21838 vector predication code. */
21839 if (opcode
&& !opcode
->mayBeVecPred
)
21842 if (!opcode
|| !cond
)
21844 /* Cannot have a conditional suffix on a mnemonic of less than two
21846 if (end
- base
< 3)
21849 /* Look for suffixed mnemonic. */
21851 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21852 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21856 if (opcode
&& cond
)
21859 switch (opcode
->tag
)
21861 case OT_cinfix3_legacy
:
21862 /* Ignore conditional suffixes matched on infix only mnemonics. */
21866 case OT_cinfix3_deprecated
:
21867 case OT_odd_infix_unc
:
21868 if (!unified_syntax
)
21870 /* Fall through. */
21874 case OT_csuf_or_in3
:
21875 inst
.cond
= cond
->value
;
21878 case OT_unconditional
:
21879 case OT_unconditionalF
:
21881 inst
.cond
= cond
->value
;
21884 /* Delayed diagnostic. */
21885 inst
.error
= BAD_COND
;
21886 inst
.cond
= COND_ALWAYS
;
21895 /* Cannot have a usual-position infix on a mnemonic of less than
21896 six characters (five would be a suffix). */
21897 if (end
- base
< 6)
21900 /* Look for infixed mnemonic in the usual position. */
21902 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21906 memcpy (save
, affix
, 2);
21907 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
21908 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21910 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
21911 memcpy (affix
, save
, 2);
21914 && (opcode
->tag
== OT_cinfix3
21915 || opcode
->tag
== OT_cinfix3_deprecated
21916 || opcode
->tag
== OT_csuf_or_in3
21917 || opcode
->tag
== OT_cinfix3_legacy
))
21920 if (warn_on_deprecated
&& unified_syntax
21921 && (opcode
->tag
== OT_cinfix3
21922 || opcode
->tag
== OT_cinfix3_deprecated
))
21923 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21925 inst
.cond
= cond
->value
;
21932 /* This function generates an initial IT instruction, leaving its block
21933 virtually open for the new instructions. Eventually,
21934 the mask will be updated by now_pred_add_mask () each time
21935 a new instruction needs to be included in the IT block.
21936 Finally, the block is closed with close_automatic_it_block ().
21937 The block closure can be requested either from md_assemble (),
21938 a tencode (), or due to a label hook. */
21941 new_automatic_it_block (int cond
)
21943 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
21944 now_pred
.mask
= 0x18;
21945 now_pred
.cc
= cond
;
21946 now_pred
.block_length
= 1;
21947 mapping_state (MAP_THUMB
);
21948 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
21949 now_pred
.warn_deprecated
= FALSE
;
21950 now_pred
.insn_cond
= TRUE
;
21953 /* Close an automatic IT block.
21954 See comments in new_automatic_it_block (). */
21957 close_automatic_it_block (void)
21959 now_pred
.mask
= 0x10;
21960 now_pred
.block_length
= 0;
21963 /* Update the mask of the current automatically-generated IT
21964 instruction. See comments in new_automatic_it_block (). */
21967 now_pred_add_mask (int cond
)
21969 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21970 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21971 | ((bitvalue) << (nbit)))
21972 const int resulting_bit
= (cond
& 1);
21974 now_pred
.mask
&= 0xf;
21975 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21977 (5 - now_pred
.block_length
));
21978 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21980 ((5 - now_pred
.block_length
) - 1));
21981 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
21984 #undef SET_BIT_VALUE
21987 /* The IT blocks handling machinery is accessed through the these functions:
21988 it_fsm_pre_encode () from md_assemble ()
21989 set_pred_insn_type () optional, from the tencode functions
21990 set_pred_insn_type_last () ditto
21991 in_pred_block () ditto
21992 it_fsm_post_encode () from md_assemble ()
21993 force_automatic_it_block_close () from label handling functions
21996 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
21997 initializing the IT insn type with a generic initial value depending
21998 on the inst.condition.
21999 2) During the tencode function, two things may happen:
22000 a) The tencode function overrides the IT insn type by
22001 calling either set_pred_insn_type (type) or
22002 set_pred_insn_type_last ().
22003 b) The tencode function queries the IT block state by
22004 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22006 Both set_pred_insn_type and in_pred_block run the internal FSM state
22007 handling function (handle_pred_state), because: a) setting the IT insn
22008 type may incur in an invalid state (exiting the function),
22009 and b) querying the state requires the FSM to be updated.
22010 Specifically we want to avoid creating an IT block for conditional
22011 branches, so it_fsm_pre_encode is actually a guess and we can't
22012 determine whether an IT block is required until the tencode () routine
22013 has decided what type of instruction this actually it.
22014 Because of this, if set_pred_insn_type and in_pred_block have to be
22015 used, set_pred_insn_type has to be called first.
22017 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22018 that determines the insn IT type depending on the inst.cond code.
22019 When a tencode () routine encodes an instruction that can be
22020 either outside an IT block, or, in the case of being inside, has to be
22021 the last one, set_pred_insn_type_last () will determine the proper
22022 IT instruction type based on the inst.cond code. Otherwise,
22023 set_pred_insn_type can be called for overriding that logic or
22024 for covering other cases.
22026 Calling handle_pred_state () may not transition the IT block state to
22027 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22028 still queried. Instead, if the FSM determines that the state should
22029 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22030 after the tencode () function: that's what it_fsm_post_encode () does.
22032 Since in_pred_block () calls the state handling function to get an
22033 updated state, an error may occur (due to invalid insns combination).
22034 In that case, inst.error is set.
22035 Therefore, inst.error has to be checked after the execution of
22036 the tencode () routine.
22038 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22039 any pending state change (if any) that didn't take place in
22040 handle_pred_state () as explained above. */
22043 it_fsm_pre_encode (void)
22045 if (inst
.cond
!= COND_ALWAYS
)
22046 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22048 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22050 now_pred
.state_handled
= 0;
22053 /* IT state FSM handling function. */
22054 /* MVE instructions and non-MVE instructions are handled differently because of
22055 the introduction of VPT blocks.
22056 Specifications say that any non-MVE instruction inside a VPT block is
22057 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22058 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22059 few exceptions we have MVE_UNPREDICABLE_INSN.
22060 The error messages provided depending on the different combinations possible
22061 are described in the cases below:
22062 For 'most' MVE instructions:
22063 1) In an IT block, with an IT code: syntax error
22064 2) In an IT block, with a VPT code: error: must be in a VPT block
22065 3) In an IT block, with no code: warning: UNPREDICTABLE
22066 4) In a VPT block, with an IT code: syntax error
22067 5) In a VPT block, with a VPT code: OK!
22068 6) In a VPT block, with no code: error: missing code
22069 7) Outside a pred block, with an IT code: error: syntax error
22070 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22071 9) Outside a pred block, with no code: OK!
22072 For non-MVE instructions:
22073 10) In an IT block, with an IT code: OK!
22074 11) In an IT block, with a VPT code: syntax error
22075 12) In an IT block, with no code: error: missing code
22076 13) In a VPT block, with an IT code: error: should be in an IT block
22077 14) In a VPT block, with a VPT code: syntax error
22078 15) In a VPT block, with no code: UNPREDICTABLE
22079 16) Outside a pred block, with an IT code: error: should be in an IT block
22080 17) Outside a pred block, with a VPT code: syntax error
22081 18) Outside a pred block, with no code: OK!
22086 handle_pred_state (void)
22088 now_pred
.state_handled
= 1;
22089 now_pred
.insn_cond
= FALSE
;
22091 switch (now_pred
.state
)
22093 case OUTSIDE_PRED_BLOCK
:
22094 switch (inst
.pred_insn_type
)
22096 case MVE_UNPREDICABLE_INSN
:
22097 case MVE_OUTSIDE_PRED_INSN
:
22098 if (inst
.cond
< COND_ALWAYS
)
22100 /* Case 7: Outside a pred block, with an IT code: error: syntax
22102 inst
.error
= BAD_SYNTAX
;
22105 /* Case 9: Outside a pred block, with no code: OK! */
22107 case OUTSIDE_PRED_INSN
:
22108 if (inst
.cond
> COND_ALWAYS
)
22110 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22112 inst
.error
= BAD_SYNTAX
;
22115 /* Case 18: Outside a pred block, with no code: OK! */
22118 case INSIDE_VPT_INSN
:
22119 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22121 inst
.error
= BAD_OUT_VPT
;
22124 case INSIDE_IT_INSN
:
22125 case INSIDE_IT_LAST_INSN
:
22126 if (inst
.cond
< COND_ALWAYS
)
22128 /* Case 16: Outside a pred block, with an IT code: error: should
22129 be in an IT block. */
22130 if (thumb_mode
== 0)
22133 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22134 as_tsktsk (_("Warning: conditional outside an IT block"\
22139 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22140 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22142 /* Automatically generate the IT instruction. */
22143 new_automatic_it_block (inst
.cond
);
22144 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22145 close_automatic_it_block ();
22149 inst
.error
= BAD_OUT_IT
;
22155 else if (inst
.cond
> COND_ALWAYS
)
22157 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22159 inst
.error
= BAD_SYNTAX
;
22164 case IF_INSIDE_IT_LAST_INSN
:
22165 case NEUTRAL_IT_INSN
:
22169 if (inst
.cond
!= COND_ALWAYS
)
22170 first_error (BAD_SYNTAX
);
22171 now_pred
.state
= MANUAL_PRED_BLOCK
;
22172 now_pred
.block_length
= 0;
22173 now_pred
.type
= VECTOR_PRED
;
22177 now_pred
.state
= MANUAL_PRED_BLOCK
;
22178 now_pred
.block_length
= 0;
22179 now_pred
.type
= SCALAR_PRED
;
22184 case AUTOMATIC_PRED_BLOCK
:
22185 /* Three things may happen now:
22186 a) We should increment current it block size;
22187 b) We should close current it block (closing insn or 4 insns);
22188 c) We should close current it block and start a new one (due
22189 to incompatible conditions or
22190 4 insns-length block reached). */
22192 switch (inst
.pred_insn_type
)
22194 case INSIDE_VPT_INSN
:
22196 case MVE_UNPREDICABLE_INSN
:
22197 case MVE_OUTSIDE_PRED_INSN
:
22199 case OUTSIDE_PRED_INSN
:
22200 /* The closure of the block shall happen immediately,
22201 so any in_pred_block () call reports the block as closed. */
22202 force_automatic_it_block_close ();
22205 case INSIDE_IT_INSN
:
22206 case INSIDE_IT_LAST_INSN
:
22207 case IF_INSIDE_IT_LAST_INSN
:
22208 now_pred
.block_length
++;
22210 if (now_pred
.block_length
> 4
22211 || !now_pred_compatible (inst
.cond
))
22213 force_automatic_it_block_close ();
22214 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
22215 new_automatic_it_block (inst
.cond
);
22219 now_pred
.insn_cond
= TRUE
;
22220 now_pred_add_mask (inst
.cond
);
22223 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
22224 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
22225 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
22226 close_automatic_it_block ();
22229 case NEUTRAL_IT_INSN
:
22230 now_pred
.block_length
++;
22231 now_pred
.insn_cond
= TRUE
;
22233 if (now_pred
.block_length
> 4)
22234 force_automatic_it_block_close ();
22236 now_pred_add_mask (now_pred
.cc
& 1);
22240 close_automatic_it_block ();
22241 now_pred
.state
= MANUAL_PRED_BLOCK
;
22246 case MANUAL_PRED_BLOCK
:
22249 if (now_pred
.type
== SCALAR_PRED
)
22251 /* Check conditional suffixes. */
22252 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
22253 now_pred
.mask
<<= 1;
22254 now_pred
.mask
&= 0x1f;
22255 is_last
= (now_pred
.mask
== 0x10);
22259 now_pred
.cc
^= (now_pred
.mask
>> 4);
22260 cond
= now_pred
.cc
+ 0xf;
22261 now_pred
.mask
<<= 1;
22262 now_pred
.mask
&= 0x1f;
22263 is_last
= now_pred
.mask
== 0x10;
22265 now_pred
.insn_cond
= TRUE
;
22267 switch (inst
.pred_insn_type
)
22269 case OUTSIDE_PRED_INSN
:
22270 if (now_pred
.type
== SCALAR_PRED
)
22272 if (inst
.cond
== COND_ALWAYS
)
22274 /* Case 12: In an IT block, with no code: error: missing
22276 inst
.error
= BAD_NOT_IT
;
22279 else if (inst
.cond
> COND_ALWAYS
)
22281 /* Case 11: In an IT block, with a VPT code: syntax error.
22283 inst
.error
= BAD_SYNTAX
;
22286 else if (thumb_mode
)
22288 /* This is for some special cases where a non-MVE
22289 instruction is not allowed in an IT block, such as cbz,
22290 but are put into one with a condition code.
22291 You could argue this should be a syntax error, but we
22292 gave the 'not allowed in IT block' diagnostic in the
22293 past so we will keep doing so. */
22294 inst
.error
= BAD_NOT_IT
;
22301 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
22302 as_tsktsk (MVE_NOT_VPT
);
22305 case MVE_OUTSIDE_PRED_INSN
:
22306 if (now_pred
.type
== SCALAR_PRED
)
22308 if (inst
.cond
== COND_ALWAYS
)
22310 /* Case 3: In an IT block, with no code: warning:
22312 as_tsktsk (MVE_NOT_IT
);
22315 else if (inst
.cond
< COND_ALWAYS
)
22317 /* Case 1: In an IT block, with an IT code: syntax error.
22319 inst
.error
= BAD_SYNTAX
;
22327 if (inst
.cond
< COND_ALWAYS
)
22329 /* Case 4: In a VPT block, with an IT code: syntax error.
22331 inst
.error
= BAD_SYNTAX
;
22334 else if (inst
.cond
== COND_ALWAYS
)
22336 /* Case 6: In a VPT block, with no code: error: missing
22338 inst
.error
= BAD_NOT_VPT
;
22346 case MVE_UNPREDICABLE_INSN
:
22347 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
22349 case INSIDE_IT_INSN
:
22350 if (inst
.cond
> COND_ALWAYS
)
22352 /* Case 11: In an IT block, with a VPT code: syntax error. */
22353 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22354 inst
.error
= BAD_SYNTAX
;
22357 else if (now_pred
.type
== SCALAR_PRED
)
22359 /* Case 10: In an IT block, with an IT code: OK! */
22360 if (cond
!= inst
.cond
)
22362 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
22369 /* Case 13: In a VPT block, with an IT code: error: should be
22371 inst
.error
= BAD_OUT_IT
;
22376 case INSIDE_VPT_INSN
:
22377 if (now_pred
.type
== SCALAR_PRED
)
22379 /* Case 2: In an IT block, with a VPT code: error: must be in a
22381 inst
.error
= BAD_OUT_VPT
;
22384 /* Case 5: In a VPT block, with a VPT code: OK! */
22385 else if (cond
!= inst
.cond
)
22387 inst
.error
= BAD_VPT_COND
;
22391 case INSIDE_IT_LAST_INSN
:
22392 case IF_INSIDE_IT_LAST_INSN
:
22393 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
22395 /* Case 4: In a VPT block, with an IT code: syntax error. */
22396 /* Case 11: In an IT block, with a VPT code: syntax error. */
22397 inst
.error
= BAD_SYNTAX
;
22400 else if (cond
!= inst
.cond
)
22402 inst
.error
= BAD_IT_COND
;
22407 inst
.error
= BAD_BRANCH
;
22412 case NEUTRAL_IT_INSN
:
22413 /* The BKPT instruction is unconditional even in a IT or VPT
22418 if (now_pred
.type
== SCALAR_PRED
)
22420 inst
.error
= BAD_IT_IT
;
22423 /* fall through. */
22425 if (inst
.cond
== COND_ALWAYS
)
22427 /* Executing a VPT/VPST instruction inside an IT block or a
22428 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22430 if (now_pred
.type
== SCALAR_PRED
)
22431 as_tsktsk (MVE_NOT_IT
);
22433 as_tsktsk (MVE_NOT_VPT
);
22438 /* VPT/VPST do not accept condition codes. */
22439 inst
.error
= BAD_SYNTAX
;
22450 struct depr_insn_mask
22452 unsigned long pattern
;
22453 unsigned long mask
;
22454 const char* description
;
22457 /* List of 16-bit instruction patterns deprecated in an IT block in
22459 static const struct depr_insn_mask depr_it_insns
[] = {
22460 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22461 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22462 { 0xa000, 0xb800, N_("ADR") },
22463 { 0x4800, 0xf800, N_("Literal loads") },
22464 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22465 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22466 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22467 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22468 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22473 it_fsm_post_encode (void)
22477 if (!now_pred
.state_handled
)
22478 handle_pred_state ();
22480 if (now_pred
.insn_cond
22481 && !now_pred
.warn_deprecated
22482 && warn_on_deprecated
22483 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
22484 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
22486 if (inst
.instruction
>= 0x10000)
22488 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22489 "performance deprecated in ARMv8-A and ARMv8-R"));
22490 now_pred
.warn_deprecated
= TRUE
;
22494 const struct depr_insn_mask
*p
= depr_it_insns
;
22496 while (p
->mask
!= 0)
22498 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
22500 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22501 "instructions of the following class are "
22502 "performance deprecated in ARMv8-A and "
22503 "ARMv8-R: %s"), p
->description
);
22504 now_pred
.warn_deprecated
= TRUE
;
22512 if (now_pred
.block_length
> 1)
22514 as_tsktsk (_("IT blocks containing more than one conditional "
22515 "instruction are performance deprecated in ARMv8-A and "
22517 now_pred
.warn_deprecated
= TRUE
;
22521 is_last
= (now_pred
.mask
== 0x10);
22524 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22530 force_automatic_it_block_close (void)
22532 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
22534 close_automatic_it_block ();
22535 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22541 in_pred_block (void)
22543 if (!now_pred
.state_handled
)
22544 handle_pred_state ();
22546 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22549 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22550 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22551 here, hence the "known" in the function name. */
22554 known_t32_only_insn (const struct asm_opcode
*opcode
)
22556 /* Original Thumb-1 wide instruction. */
22557 if (opcode
->tencode
== do_t_blx
22558 || opcode
->tencode
== do_t_branch23
22559 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22560 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22563 /* Wide-only instruction added to ARMv8-M Baseline. */
22564 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22565 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22566 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22567 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22573 /* Whether wide instruction variant can be used if available for a valid OPCODE
22577 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22579 if (known_t32_only_insn (opcode
))
22582 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22583 of variant T3 of B.W is checked in do_t_branch. */
22584 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22585 && opcode
->tencode
== do_t_branch
)
22588 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22589 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22590 && opcode
->tencode
== do_t_mov_cmp
22591 /* Make sure CMP instruction is not affected. */
22592 && opcode
->aencode
== do_mov
)
22595 /* Wide instruction variants of all instructions with narrow *and* wide
22596 variants become available with ARMv6t2. Other opcodes are either
22597 narrow-only or wide-only and are thus available if OPCODE is valid. */
22598 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22601 /* OPCODE with narrow only instruction variant or wide variant not
22607 md_assemble (char *str
)
22610 const struct asm_opcode
* opcode
;
22612 /* Align the previous label if needed. */
22613 if (last_label_seen
!= NULL
)
22615 symbol_set_frag (last_label_seen
, frag_now
);
22616 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22617 S_SET_SEGMENT (last_label_seen
, now_seg
);
22620 memset (&inst
, '\0', sizeof (inst
));
22622 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22623 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22625 opcode
= opcode_lookup (&p
);
22628 /* It wasn't an instruction, but it might be a register alias of
22629 the form alias .req reg, or a Neon .dn/.qn directive. */
22630 if (! create_register_alias (str
, p
)
22631 && ! create_neon_reg_alias (str
, p
))
22632 as_bad (_("bad instruction `%s'"), str
);
22637 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22638 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22640 /* The value which unconditional instructions should have in place of the
22641 condition field. */
22642 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22646 arm_feature_set variant
;
22648 variant
= cpu_variant
;
22649 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22650 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22651 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22652 /* Check that this instruction is supported for this CPU. */
22653 if (!opcode
->tvariant
22654 || (thumb_mode
== 1
22655 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22657 if (opcode
->tencode
== do_t_swi
)
22658 as_bad (_("SVC is not permitted on this architecture"));
22660 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22663 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22664 && opcode
->tencode
!= do_t_branch
)
22666 as_bad (_("Thumb does not support conditional execution"));
22670 /* Two things are addressed here:
22671 1) Implicit require narrow instructions on Thumb-1.
22672 This avoids relaxation accidentally introducing Thumb-2
22674 2) Reject wide instructions in non Thumb-2 cores.
22676 Only instructions with narrow and wide variants need to be handled
22677 but selecting all non wide-only instructions is easier. */
22678 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22679 && !t32_insn_ok (variant
, opcode
))
22681 if (inst
.size_req
== 0)
22683 else if (inst
.size_req
== 4)
22685 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22686 as_bad (_("selected processor does not support 32bit wide "
22687 "variant of instruction `%s'"), str
);
22689 as_bad (_("selected processor does not support `%s' in "
22690 "Thumb-2 mode"), str
);
22695 inst
.instruction
= opcode
->tvalue
;
22697 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22699 /* Prepare the pred_insn_type for those encodings that don't set
22701 it_fsm_pre_encode ();
22703 opcode
->tencode ();
22705 it_fsm_post_encode ();
22708 if (!(inst
.error
|| inst
.relax
))
22710 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
22711 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
22712 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
22714 as_bad (_("cannot honor width suffix -- `%s'"), str
);
22719 /* Something has gone badly wrong if we try to relax a fixed size
22721 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
22723 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22724 *opcode
->tvariant
);
22725 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
22726 set those bits when Thumb-2 32-bit instructions are seen. The impact
22727 of relaxable instructions will be considered later after we finish all
22729 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
22730 variant
= arm_arch_none
;
22732 variant
= cpu_variant
;
22733 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
22734 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22737 check_neon_suffixes
;
22741 mapping_state (MAP_THUMB
);
22744 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22748 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22749 is_bx
= (opcode
->aencode
== do_bx
);
22751 /* Check that this instruction is supported for this CPU. */
22752 if (!(is_bx
&& fix_v4bx
)
22753 && !(opcode
->avariant
&&
22754 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
22756 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
22761 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
22765 inst
.instruction
= opcode
->avalue
;
22766 if (opcode
->tag
== OT_unconditionalF
)
22767 inst
.instruction
|= 0xFU
<< 28;
22769 inst
.instruction
|= inst
.cond
<< 28;
22770 inst
.size
= INSN_SIZE
;
22771 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
22773 it_fsm_pre_encode ();
22774 opcode
->aencode ();
22775 it_fsm_post_encode ();
22777 /* Arm mode bx is marked as both v4T and v5 because it's still required
22778 on a hypothetical non-thumb v5 core. */
22780 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
22782 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
22783 *opcode
->avariant
);
22785 check_neon_suffixes
;
22789 mapping_state (MAP_ARM
);
22794 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22802 check_pred_blocks_finished (void)
22807 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
22808 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
22809 == MANUAL_PRED_BLOCK
)
22811 if (now_pred
.type
== SCALAR_PRED
)
22812 as_warn (_("section '%s' finished with an open IT block."),
22815 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22819 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
22821 if (now_pred
.type
== SCALAR_PRED
)
22822 as_warn (_("file finished with an open IT block."));
22824 as_warn (_("file finished with an open VPT/VPST block."));
22829 /* Various frobbings of labels and their addresses. */
22832 arm_start_line_hook (void)
22834 last_label_seen
= NULL
;
22838 arm_frob_label (symbolS
* sym
)
22840 last_label_seen
= sym
;
22842 ARM_SET_THUMB (sym
, thumb_mode
);
22844 #if defined OBJ_COFF || defined OBJ_ELF
22845 ARM_SET_INTERWORK (sym
, support_interwork
);
22848 force_automatic_it_block_close ();
22850 /* Note - do not allow local symbols (.Lxxx) to be labelled
22851 as Thumb functions. This is because these labels, whilst
22852 they exist inside Thumb code, are not the entry points for
22853 possible ARM->Thumb calls. Also, these labels can be used
22854 as part of a computed goto or switch statement. eg gcc
22855 can generate code that looks like this:
22857 ldr r2, [pc, .Laaa]
22867 The first instruction loads the address of the jump table.
22868 The second instruction converts a table index into a byte offset.
22869 The third instruction gets the jump address out of the table.
22870 The fourth instruction performs the jump.
22872 If the address stored at .Laaa is that of a symbol which has the
22873 Thumb_Func bit set, then the linker will arrange for this address
22874 to have the bottom bit set, which in turn would mean that the
22875 address computation performed by the third instruction would end
22876 up with the bottom bit set. Since the ARM is capable of unaligned
22877 word loads, the instruction would then load the incorrect address
22878 out of the jump table, and chaos would ensue. */
22879 if (label_is_thumb_function_name
22880 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
22881 && (bfd_section_flags (now_seg
) & SEC_CODE
) != 0)
22883 /* When the address of a Thumb function is taken the bottom
22884 bit of that address should be set. This will allow
22885 interworking between Arm and Thumb functions to work
22888 THUMB_SET_FUNC (sym
, 1);
22890 label_is_thumb_function_name
= FALSE
;
22893 dwarf2_emit_label (sym
);
22897 arm_data_in_code (void)
22899 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
22901 *input_line_pointer
= '/';
22902 input_line_pointer
+= 5;
22903 *input_line_pointer
= 0;
22911 arm_canonicalize_symbol_name (char * name
)
22915 if (thumb_mode
&& (len
= strlen (name
)) > 5
22916 && streq (name
+ len
- 5, "/data"))
22917 *(name
+ len
- 5) = 0;
22922 /* Table of all register names defined by default. The user can
22923 define additional names with .req. Note that all register names
22924 should appear in both upper and lowercase variants. Some registers
22925 also have mixed-case names. */
22927 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
22928 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
22929 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
22930 #define REGSET(p,t) \
22931 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22932 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22933 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22934 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
22935 #define REGSETH(p,t) \
22936 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22937 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22938 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22939 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22940 #define REGSET2(p,t) \
22941 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22942 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22943 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22944 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
22945 #define SPLRBANK(base,bank,t) \
22946 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22947 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22948 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22949 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22950 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22951 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22953 static const struct reg_entry reg_names
[] =
22955 /* ARM integer registers. */
22956 REGSET(r
, RN
), REGSET(R
, RN
),
22958 /* ATPCS synonyms. */
22959 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
22960 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
22961 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
22963 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
22964 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
22965 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
22967 /* Well-known aliases. */
22968 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
22969 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
22971 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
22972 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
22974 /* Defining the new Zero register from ARMv8.1-M. */
22978 /* Coprocessor numbers. */
22979 REGSET(p
, CP
), REGSET(P
, CP
),
22981 /* Coprocessor register numbers. The "cr" variants are for backward
22983 REGSET(c
, CN
), REGSET(C
, CN
),
22984 REGSET(cr
, CN
), REGSET(CR
, CN
),
22986 /* ARM banked registers. */
22987 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
22988 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
22989 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
22990 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
22991 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
22992 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
22993 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
22995 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
22996 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
22997 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
22998 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
22999 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
23000 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
23001 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
23002 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
23004 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
23005 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
23006 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
23007 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
23008 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
23009 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
23010 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
23011 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23012 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23014 /* FPA registers. */
23015 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
23016 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
23018 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
23019 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
23021 /* VFP SP registers. */
23022 REGSET(s
,VFS
), REGSET(S
,VFS
),
23023 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
23025 /* VFP DP Registers. */
23026 REGSET(d
,VFD
), REGSET(D
,VFD
),
23027 /* Extra Neon DP registers. */
23028 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
23030 /* Neon QP registers. */
23031 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
23033 /* VFP control registers. */
23034 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
23035 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
23036 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
23037 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
23038 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
23039 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
23040 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
23041 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
23042 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
23043 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
23044 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
23046 /* Maverick DSP coprocessor registers. */
23047 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23048 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23050 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23051 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23052 REGDEF(dspsc
,0,DSPSC
),
23054 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23055 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23056 REGDEF(DSPSC
,0,DSPSC
),
23058 /* iWMMXt data registers - p0, c0-15. */
23059 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23061 /* iWMMXt control registers - p1, c0-3. */
23062 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23063 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23064 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23065 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23067 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23068 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23069 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23070 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23071 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23073 /* XScale accumulator registers. */
23074 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23080 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23081 within psr_required_here. */
23082 static const struct asm_psr psrs
[] =
23084 /* Backward compatibility notation. Note that "all" is no longer
23085 truly all possible PSR bits. */
23086 {"all", PSR_c
| PSR_f
},
23090 /* Individual flags. */
23096 /* Combinations of flags. */
23097 {"fs", PSR_f
| PSR_s
},
23098 {"fx", PSR_f
| PSR_x
},
23099 {"fc", PSR_f
| PSR_c
},
23100 {"sf", PSR_s
| PSR_f
},
23101 {"sx", PSR_s
| PSR_x
},
23102 {"sc", PSR_s
| PSR_c
},
23103 {"xf", PSR_x
| PSR_f
},
23104 {"xs", PSR_x
| PSR_s
},
23105 {"xc", PSR_x
| PSR_c
},
23106 {"cf", PSR_c
| PSR_f
},
23107 {"cs", PSR_c
| PSR_s
},
23108 {"cx", PSR_c
| PSR_x
},
23109 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23110 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23111 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23112 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23113 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23114 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23115 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23116 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23117 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23118 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23119 {"scf", PSR_s
| PSR_c
| PSR_f
},
23120 {"scx", PSR_s
| PSR_c
| PSR_x
},
23121 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23122 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23123 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23124 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23125 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23126 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23127 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23128 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23129 {"csf", PSR_c
| PSR_s
| PSR_f
},
23130 {"csx", PSR_c
| PSR_s
| PSR_x
},
23131 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23132 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23133 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23134 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23135 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23136 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23137 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23138 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23139 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23140 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23141 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23142 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23143 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23144 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23145 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23146 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23147 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23148 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23149 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23150 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23151 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23152 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23153 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23154 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23155 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23156 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23159 /* Table of V7M psr names. */
23160 static const struct asm_psr v7m_psrs
[] =
23162 {"apsr", 0x0 }, {"APSR", 0x0 },
23163 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23164 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23165 {"psr", 0x3 }, {"PSR", 0x3 },
23166 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23167 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23168 {"epsr", 0x6 }, {"EPSR", 0x6 },
23169 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23170 {"msp", 0x8 }, {"MSP", 0x8 },
23171 {"psp", 0x9 }, {"PSP", 0x9 },
23172 {"msplim", 0xa }, {"MSPLIM", 0xa },
23173 {"psplim", 0xb }, {"PSPLIM", 0xb },
23174 {"primask", 0x10}, {"PRIMASK", 0x10},
23175 {"basepri", 0x11}, {"BASEPRI", 0x11},
23176 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
23177 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23178 {"control", 0x14}, {"CONTROL", 0x14},
23179 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23180 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
23181 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
23182 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
23183 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
23184 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
23185 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
23186 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
23187 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
23190 /* Table of all shift-in-operand names. */
23191 static const struct asm_shift_name shift_names
[] =
23193 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
23194 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
23195 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
23196 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
23197 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
23198 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
23199 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
23202 /* Table of all explicit relocation names. */
23204 static struct reloc_entry reloc_names
[] =
23206 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
23207 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
23208 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
23209 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
23210 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
23211 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
23212 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
23213 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
23214 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
23215 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
23216 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
23217 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
23218 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
23219 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
23220 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
23221 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
23222 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
23223 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
23224 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
23225 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
23226 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23227 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23228 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
23229 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
23230 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
23231 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
23232 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
23236 /* Table of all conditional affixes. */
23237 static const struct asm_cond conds
[] =
23241 {"cs", 0x2}, {"hs", 0x2},
23242 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
23255 static const struct asm_cond vconds
[] =
23261 #define UL_BARRIER(L,U,CODE,FEAT) \
23262 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
23263 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
23265 static struct asm_barrier_opt barrier_opt_names
[] =
23267 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
23268 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
23269 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
23270 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
23271 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
23272 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
23273 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
23274 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
23275 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
23276 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
23277 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
23278 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
23279 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
23280 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
23281 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
23282 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
23287 /* Table of ARM-format instructions. */
23289 /* Macros for gluing together operand strings. N.B. In all cases
23290 other than OPS0, the trailing OP_stop comes from default
23291 zero-initialization of the unspecified elements of the array. */
23292 #define OPS0() { OP_stop, }
23293 #define OPS1(a) { OP_##a, }
23294 #define OPS2(a,b) { OP_##a,OP_##b, }
23295 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
23296 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
23297 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
23298 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
23300 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
23301 This is useful when mixing operands for ARM and THUMB, i.e. using the
23302 MIX_ARM_THUMB_OPERANDS macro.
23303 In order to use these macros, prefix the number of operands with _
23305 #define OPS_1(a) { a, }
23306 #define OPS_2(a,b) { a,b, }
23307 #define OPS_3(a,b,c) { a,b,c, }
23308 #define OPS_4(a,b,c,d) { a,b,c,d, }
23309 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
23310 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
23312 /* These macros abstract out the exact format of the mnemonic table and
23313 save some repeated characters. */
23315 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
23316 #define TxCE(mnem, op, top, nops, ops, ae, te) \
23317 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
23318 THUMB_VARIANT, do_##ae, do_##te, 0 }
23320 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
23321 a T_MNEM_xyz enumerator. */
23322 #define TCE(mnem, aop, top, nops, ops, ae, te) \
23323 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
23324 #define tCE(mnem, aop, top, nops, ops, ae, te) \
23325 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23327 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
23328 infix after the third character. */
23329 #define TxC3(mnem, op, top, nops, ops, ae, te) \
23330 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
23331 THUMB_VARIANT, do_##ae, do_##te, 0 }
23332 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
23333 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
23334 THUMB_VARIANT, do_##ae, do_##te, 0 }
23335 #define TC3(mnem, aop, top, nops, ops, ae, te) \
23336 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
23337 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
23338 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
23339 #define tC3(mnem, aop, top, nops, ops, ae, te) \
23340 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23341 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
23342 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23344 /* Mnemonic that cannot be conditionalized. The ARM condition-code
23345 field is still 0xE. Many of the Thumb variants can be executed
23346 conditionally, so this is checked separately. */
23347 #define TUE(mnem, op, top, nops, ops, ae, te) \
23348 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23349 THUMB_VARIANT, do_##ae, do_##te, 0 }
23351 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23352 Used by mnemonics that have very minimal differences in the encoding for
23353 ARM and Thumb variants and can be handled in a common function. */
23354 #define TUEc(mnem, op, top, nops, ops, en) \
23355 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23356 THUMB_VARIANT, do_##en, do_##en, 0 }
23358 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23359 condition code field. */
23360 #define TUF(mnem, op, top, nops, ops, ae, te) \
23361 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
23362 THUMB_VARIANT, do_##ae, do_##te, 0 }
23364 /* ARM-only variants of all the above. */
23365 #define CE(mnem, op, nops, ops, ae) \
23366 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23368 #define C3(mnem, op, nops, ops, ae) \
23369 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23371 /* Thumb-only variants of TCE and TUE. */
23372 #define ToC(mnem, top, nops, ops, te) \
23373 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23376 #define ToU(mnem, top, nops, ops, te) \
23377 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
23380 /* T_MNEM_xyz enumerator variants of ToC. */
23381 #define toC(mnem, top, nops, ops, te) \
23382 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
23385 /* T_MNEM_xyz enumerator variants of ToU. */
23386 #define toU(mnem, top, nops, ops, te) \
23387 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
23390 /* Legacy mnemonics that always have conditional infix after the third
23392 #define CL(mnem, op, nops, ops, ae) \
23393 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23394 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23396 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23397 #define cCE(mnem, op, nops, ops, ae) \
23398 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23400 /* mov instructions that are shared between coprocessor and MVE. */
23401 #define mcCE(mnem, op, nops, ops, ae) \
23402 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23404 /* Legacy coprocessor instructions where conditional infix and conditional
23405 suffix are ambiguous. For consistency this includes all FPA instructions,
23406 not just the potentially ambiguous ones. */
23407 #define cCL(mnem, op, nops, ops, ae) \
23408 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23409 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23411 /* Coprocessor, takes either a suffix or a position-3 infix
23412 (for an FPA corner case). */
23413 #define C3E(mnem, op, nops, ops, ae) \
23414 { mnem, OPS##nops ops, OT_csuf_or_in3, \
23415 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23417 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
23418 { m1 #m2 m3, OPS##nops ops, \
23419 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
23420 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23422 #define CM(m1, m2, op, nops, ops, ae) \
23423 xCM_ (m1, , m2, op, nops, ops, ae), \
23424 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23425 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23426 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23427 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23428 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23429 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23430 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23431 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23432 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23433 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23434 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23435 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23436 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23437 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23438 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23439 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23440 xCM_ (m1, le, m2, op, nops, ops, ae), \
23441 xCM_ (m1, al, m2, op, nops, ops, ae)
23443 #define UE(mnem, op, nops, ops, ae) \
23444 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23446 #define UF(mnem, op, nops, ops, ae) \
23447 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23449 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23450 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23451 use the same encoding function for each. */
23452 #define NUF(mnem, op, nops, ops, enc) \
23453 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23454 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23456 /* Neon data processing, version which indirects through neon_enc_tab for
23457 the various overloaded versions of opcodes. */
23458 #define nUF(mnem, op, nops, ops, enc) \
23459 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23460 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23462 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23464 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23465 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23466 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23468 #define NCE(mnem, op, nops, ops, enc) \
23469 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23471 #define NCEF(mnem, op, nops, ops, enc) \
23472 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23474 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23475 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23476 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23477 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23479 #define nCE(mnem, op, nops, ops, enc) \
23480 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23482 #define nCEF(mnem, op, nops, ops, enc) \
23483 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23486 #define mCEF(mnem, op, nops, ops, enc) \
23487 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23488 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23491 /* nCEF but for MVE predicated instructions. */
23492 #define mnCEF(mnem, op, nops, ops, enc) \
23493 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23495 /* nCE but for MVE predicated instructions. */
23496 #define mnCE(mnem, op, nops, ops, enc) \
23497 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23499 /* NUF but for potentially MVE predicated instructions. */
23500 #define MNUF(mnem, op, nops, ops, enc) \
23501 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23502 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23504 /* nUF but for potentially MVE predicated instructions. */
23505 #define mnUF(mnem, op, nops, ops, enc) \
23506 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23507 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23509 /* ToC but for potentially MVE predicated instructions. */
23510 #define mToC(mnem, top, nops, ops, te) \
23511 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23514 /* NCE but for MVE predicated instructions. */
23515 #define MNCE(mnem, op, nops, ops, enc) \
23516 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23518 /* NCEF but for MVE predicated instructions. */
23519 #define MNCEF(mnem, op, nops, ops, enc) \
23520 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23523 static const struct asm_opcode insns
[] =
23525 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23526 #define THUMB_VARIANT & arm_ext_v4t
23527 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23528 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23529 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23530 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23531 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23532 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23533 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23534 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23535 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23536 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23537 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23538 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23539 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23540 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23541 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23542 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23544 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23545 for setting PSR flag bits. They are obsolete in V6 and do not
23546 have Thumb equivalents. */
23547 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23548 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23549 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
23550 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23551 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23552 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23553 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23554 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23555 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23557 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23558 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23559 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23560 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23562 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23563 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23564 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23566 OP_ADDRGLDR
),ldst
, t_ldst
),
23567 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23569 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23570 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23571 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23572 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23573 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23574 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23576 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23577 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23580 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23581 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23582 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23583 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23585 /* Thumb-compatibility pseudo ops. */
23586 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23587 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23588 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23589 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23590 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23591 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23592 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23593 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23594 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23595 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23596 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23597 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23599 /* These may simplify to neg. */
23600 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23601 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23603 #undef THUMB_VARIANT
23604 #define THUMB_VARIANT & arm_ext_os
23606 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23607 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23609 #undef THUMB_VARIANT
23610 #define THUMB_VARIANT & arm_ext_v6
23612 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23614 /* V1 instructions with no Thumb analogue prior to V6T2. */
23615 #undef THUMB_VARIANT
23616 #define THUMB_VARIANT & arm_ext_v6t2
23618 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23619 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23620 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23622 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23623 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23624 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23625 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23627 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23628 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23630 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23631 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23633 /* V1 instructions with no Thumb analogue at all. */
23634 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23635 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23637 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23638 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23639 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23640 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23641 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23642 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23643 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23644 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23647 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23648 #undef THUMB_VARIANT
23649 #define THUMB_VARIANT & arm_ext_v4t
23651 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23652 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23654 #undef THUMB_VARIANT
23655 #define THUMB_VARIANT & arm_ext_v6t2
23657 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23658 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23660 /* Generic coprocessor instructions. */
23661 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23662 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23663 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23664 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23665 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23666 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23667 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23670 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23672 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23673 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23676 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23677 #undef THUMB_VARIANT
23678 #define THUMB_VARIANT & arm_ext_msr
23680 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23681 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23684 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23685 #undef THUMB_VARIANT
23686 #define THUMB_VARIANT & arm_ext_v6t2
23688 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23689 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23690 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23691 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23692 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23693 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23694 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23695 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23698 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23699 #undef THUMB_VARIANT
23700 #define THUMB_VARIANT & arm_ext_v4t
23702 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23703 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23704 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23705 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23706 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23707 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23710 #define ARM_VARIANT & arm_ext_v4t_5
23712 /* ARM Architecture 4T. */
23713 /* Note: bx (and blx) are required on V5, even if the processor does
23714 not support Thumb. */
23715 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
23718 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23719 #undef THUMB_VARIANT
23720 #define THUMB_VARIANT & arm_ext_v5t
23722 /* Note: blx has 2 variants; the .value coded here is for
23723 BLX(2). Only this variant has conditional execution. */
23724 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
23725 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
23727 #undef THUMB_VARIANT
23728 #define THUMB_VARIANT & arm_ext_v6t2
23730 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
23731 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23732 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23733 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23734 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23735 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23736 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23737 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23740 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23741 #undef THUMB_VARIANT
23742 #define THUMB_VARIANT & arm_ext_v5exp
23744 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23745 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23746 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23747 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23749 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23750 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23752 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23753 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23754 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23755 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23757 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23758 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23759 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23760 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23762 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23763 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23765 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23766 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23767 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23768 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23771 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23772 #undef THUMB_VARIANT
23773 #define THUMB_VARIANT & arm_ext_v6t2
23775 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
23776 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
23778 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
23779 ADDRGLDRS
), ldrd
, t_ldstd
),
23781 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23782 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23785 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23787 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
23790 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23791 #undef THUMB_VARIANT
23792 #define THUMB_VARIANT & arm_ext_v6
23794 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23795 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23796 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23797 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23798 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23799 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23800 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23801 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23802 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23803 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
23805 #undef THUMB_VARIANT
23806 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23808 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
23809 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23811 #undef THUMB_VARIANT
23812 #define THUMB_VARIANT & arm_ext_v6t2
23814 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23815 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23817 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
23818 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
23820 /* ARM V6 not included in V7M. */
23821 #undef THUMB_VARIANT
23822 #define THUMB_VARIANT & arm_ext_v6_notm
23823 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23824 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23825 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
23826 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
23827 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23828 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23829 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
23830 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23831 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
23832 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23833 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23834 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23835 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23836 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23837 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
23838 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
23839 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23840 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23841 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
23843 /* ARM V6 not included in V7M (eg. integer SIMD). */
23844 #undef THUMB_VARIANT
23845 #define THUMB_VARIANT & arm_ext_v6_dsp
23846 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
23847 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
23848 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23849 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23850 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23851 /* Old name for QASX. */
23852 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23853 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23854 /* Old name for QSAX. */
23855 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23856 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23857 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23858 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23859 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23860 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23861 /* Old name for SASX. */
23862 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23863 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23864 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23865 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23866 /* Old name for SHASX. */
23867 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23868 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23869 /* Old name for SHSAX. */
23870 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23871 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23872 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23873 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23874 /* Old name for SSAX. */
23875 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23876 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23877 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23878 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23879 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23880 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23881 /* Old name for UASX. */
23882 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23883 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23884 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23885 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23886 /* Old name for UHASX. */
23887 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23888 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23889 /* Old name for UHSAX. */
23890 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23891 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23892 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23893 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23894 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23895 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23896 /* Old name for UQASX. */
23897 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23898 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23899 /* Old name for UQSAX. */
23900 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23901 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23902 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23903 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23904 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23905 /* Old name for USAX. */
23906 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23907 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23908 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23909 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23910 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23911 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23912 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23913 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23914 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23915 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23916 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23917 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23918 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23919 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23920 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23921 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23922 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23923 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23924 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23925 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23926 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23927 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23928 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23929 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23930 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23931 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23932 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23933 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23934 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23935 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
23936 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
23937 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23938 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23939 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
23942 #define ARM_VARIANT & arm_ext_v6k_v6t2
23943 #undef THUMB_VARIANT
23944 #define THUMB_VARIANT & arm_ext_v6k_v6t2
23946 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
23947 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
23948 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
23949 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
23951 #undef THUMB_VARIANT
23952 #define THUMB_VARIANT & arm_ext_v6_notm
23953 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
23955 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
23956 RRnpcb
), strexd
, t_strexd
),
23958 #undef THUMB_VARIANT
23959 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23960 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
23962 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
23964 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23966 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23968 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
23971 #define ARM_VARIANT & arm_ext_sec
23972 #undef THUMB_VARIANT
23973 #define THUMB_VARIANT & arm_ext_sec
23975 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
23978 #define ARM_VARIANT & arm_ext_virt
23979 #undef THUMB_VARIANT
23980 #define THUMB_VARIANT & arm_ext_virt
23982 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
23983 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
23986 #define ARM_VARIANT & arm_ext_pan
23987 #undef THUMB_VARIANT
23988 #define THUMB_VARIANT & arm_ext_pan
23990 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
23993 #define ARM_VARIANT & arm_ext_v6t2
23994 #undef THUMB_VARIANT
23995 #define THUMB_VARIANT & arm_ext_v6t2
23997 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
23998 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
23999 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24000 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24002 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24003 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
24005 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24006 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24007 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24008 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24011 #define ARM_VARIANT & arm_ext_v3
24012 #undef THUMB_VARIANT
24013 #define THUMB_VARIANT & arm_ext_v6t2
24015 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
24016 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
24017 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
24020 #define ARM_VARIANT & arm_ext_v6t2
24021 #undef THUMB_VARIANT
24022 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24023 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24024 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24026 /* Thumb-only instructions. */
24028 #define ARM_VARIANT NULL
24029 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
24030 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
24032 /* ARM does not really have an IT instruction, so always allow it.
24033 The opcode is copied from Thumb in order to allow warnings in
24034 -mimplicit-it=[never | arm] modes. */
24036 #define ARM_VARIANT & arm_ext_v1
24037 #undef THUMB_VARIANT
24038 #define THUMB_VARIANT & arm_ext_v6t2
24040 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
24041 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
24042 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
24043 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
24044 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
24045 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
24046 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
24047 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24048 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24049 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24050 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24051 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24052 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24053 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24054 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24055 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24056 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24057 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24059 /* Thumb2 only instructions. */
24061 #define ARM_VARIANT NULL
24063 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24064 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24065 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24066 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24067 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24068 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24070 /* Hardware division instructions. */
24072 #define ARM_VARIANT & arm_ext_adiv
24073 #undef THUMB_VARIANT
24074 #define THUMB_VARIANT & arm_ext_div
24076 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24077 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24079 /* ARM V6M/V7 instructions. */
24081 #define ARM_VARIANT & arm_ext_barrier
24082 #undef THUMB_VARIANT
24083 #define THUMB_VARIANT & arm_ext_barrier
24085 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24086 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24087 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24089 /* ARM V7 instructions. */
24091 #define ARM_VARIANT & arm_ext_v7
24092 #undef THUMB_VARIANT
24093 #define THUMB_VARIANT & arm_ext_v7
24095 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24096 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24099 #define ARM_VARIANT & arm_ext_mp
24100 #undef THUMB_VARIANT
24101 #define THUMB_VARIANT & arm_ext_mp
24103 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24105 /* AArchv8 instructions. */
24107 #define ARM_VARIANT & arm_ext_v8
24109 /* Instructions shared between armv8-a and armv8-m. */
24110 #undef THUMB_VARIANT
24111 #define THUMB_VARIANT & arm_ext_atomics
24113 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24114 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24115 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24116 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24117 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24118 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24119 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24120 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24121 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24122 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24124 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24126 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24128 #undef THUMB_VARIANT
24129 #define THUMB_VARIANT & arm_ext_v8
24131 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24132 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24134 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24137 /* Defined in V8 but is in undefined encoding space for earlier
24138 architectures. However earlier architectures are required to treat
24139 this instuction as a semihosting trap as well. Hence while not explicitly
24140 defined as such, it is in fact correct to define the instruction for all
24142 #undef THUMB_VARIANT
24143 #define THUMB_VARIANT & arm_ext_v1
24145 #define ARM_VARIANT & arm_ext_v1
24146 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24148 /* ARMv8 T32 only. */
24150 #define ARM_VARIANT NULL
24151 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24152 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24153 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24155 /* FP for ARMv8. */
24157 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24158 #undef THUMB_VARIANT
24159 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24161 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24162 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24163 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24164 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24165 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24166 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
24167 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
24168 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
24169 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
24170 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
24171 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
24173 /* Crypto v1 extensions. */
24175 #define ARM_VARIANT & fpu_crypto_ext_armv8
24176 #undef THUMB_VARIANT
24177 #define THUMB_VARIANT & fpu_crypto_ext_armv8
24179 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
24180 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
24181 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
24182 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
24183 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
24184 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
24185 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
24186 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
24187 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
24188 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
24189 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
24190 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
24191 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
24192 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
24195 #define ARM_VARIANT & crc_ext_armv8
24196 #undef THUMB_VARIANT
24197 #define THUMB_VARIANT & crc_ext_armv8
24198 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
24199 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
24200 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
24201 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
24202 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
24203 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
24205 /* ARMv8.2 RAS extension. */
24207 #define ARM_VARIANT & arm_ext_ras
24208 #undef THUMB_VARIANT
24209 #define THUMB_VARIANT & arm_ext_ras
24210 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
24213 #define ARM_VARIANT & arm_ext_v8_3
24214 #undef THUMB_VARIANT
24215 #define THUMB_VARIANT & arm_ext_v8_3
24216 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
24219 #define ARM_VARIANT & fpu_neon_ext_dotprod
24220 #undef THUMB_VARIANT
24221 #define THUMB_VARIANT & fpu_neon_ext_dotprod
24222 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
24223 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
24226 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
24227 #undef THUMB_VARIANT
24228 #define THUMB_VARIANT NULL
24230 cCE("wfs", e200110
, 1, (RR
), rd
),
24231 cCE("rfs", e300110
, 1, (RR
), rd
),
24232 cCE("wfc", e400110
, 1, (RR
), rd
),
24233 cCE("rfc", e500110
, 1, (RR
), rd
),
24235 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24236 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24237 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24238 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24240 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24241 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24242 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24243 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24245 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
24246 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
24247 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
24248 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
24249 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
24250 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
24251 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
24252 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
24253 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
24254 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
24255 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
24256 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
24258 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
24259 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
24260 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
24261 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
24262 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
24263 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
24264 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
24265 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
24266 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
24267 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
24268 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
24269 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
24271 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
24272 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
24273 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
24274 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
24275 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
24276 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
24277 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
24278 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
24279 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
24280 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
24281 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
24282 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
24284 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
24285 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
24286 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
24287 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
24288 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
24289 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
24290 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
24291 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
24292 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
24293 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
24294 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
24295 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
24297 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
24298 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
24299 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
24300 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
24301 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
24302 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
24303 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
24304 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
24305 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
24306 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
24307 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
24308 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
24310 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
24311 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
24312 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
24313 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
24314 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
24315 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
24316 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
24317 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
24318 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
24319 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
24320 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
24321 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
24323 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
24324 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
24325 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
24326 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
24327 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
24328 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
24329 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
24330 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
24331 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
24332 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
24333 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
24334 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
24336 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
24337 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
24338 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
24339 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
24340 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
24341 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
24342 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
24343 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
24344 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
24345 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
24346 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
24347 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
24349 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
24350 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
24351 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
24352 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
24353 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
24354 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
24355 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
24356 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
24357 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
24358 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
24359 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
24360 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
24362 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
24363 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
24364 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
24365 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
24366 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
24367 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
24368 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
24369 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
24370 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
24371 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
24372 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
24373 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
24375 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
24376 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
24377 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
24378 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
24379 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
24380 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
24381 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
24382 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
24383 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
24384 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
24385 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
24386 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
24388 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
24389 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
24390 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
24391 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
24392 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
24393 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
24394 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
24395 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
24396 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
24397 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
24398 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
24399 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
24401 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
24402 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
24403 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
24404 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
24405 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
24406 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
24407 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
24408 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
24409 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
24410 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
24411 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
24412 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
24414 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
24415 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
24416 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
24417 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
24418 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
24419 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
24420 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
24421 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
24422 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
24423 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
24424 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
24425 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
24427 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
24428 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
24429 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
24430 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
24431 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
24432 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
24433 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
24434 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
24435 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
24436 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
24437 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
24438 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
24440 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
24441 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
24442 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
24443 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
24444 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
24445 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
24446 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
24447 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
24448 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
24449 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
24450 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
24451 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
24453 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24454 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24455 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24456 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24457 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24458 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24459 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24460 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24461 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24462 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24463 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24464 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24466 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24467 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24468 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24469 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24470 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24471 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24472 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24473 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24474 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24475 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24476 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24477 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24479 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24480 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24481 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24482 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24483 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24484 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24485 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24486 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24487 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24488 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24489 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24490 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24492 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24493 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24494 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24495 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24496 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24497 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24498 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24499 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24500 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24501 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24502 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24503 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24505 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24506 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24507 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24508 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24509 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24510 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24511 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24512 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24513 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24514 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24515 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24516 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24518 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24519 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24520 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24521 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24522 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24523 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24524 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24525 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24526 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24527 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24528 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24529 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24531 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24532 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24533 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24534 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24535 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24536 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24537 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24538 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24539 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24540 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24541 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24542 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24544 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24545 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24546 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24547 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24548 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24549 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24550 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24551 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24552 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24553 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24554 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24555 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24557 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24558 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24559 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24560 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24561 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24562 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24563 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24564 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24565 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24566 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24567 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24568 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24570 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24571 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24572 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24573 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24574 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24575 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24576 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24577 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24578 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24579 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24580 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24581 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24583 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24584 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24585 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24586 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24587 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24588 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24589 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24590 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24591 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24592 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24593 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24594 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24596 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24597 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24598 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24599 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24600 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24601 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24602 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24603 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24604 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24605 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24606 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24607 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24609 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24610 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24611 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24612 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24613 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24614 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24615 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24616 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24617 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24618 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24619 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24620 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24622 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24623 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24624 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24625 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24627 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24628 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24629 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24630 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24631 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24632 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24633 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24634 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24635 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24636 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24637 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24638 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24640 /* The implementation of the FIX instruction is broken on some
24641 assemblers, in that it accepts a precision specifier as well as a
24642 rounding specifier, despite the fact that this is meaningless.
24643 To be more compatible, we accept it as well, though of course it
24644 does not set any bits. */
24645 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24646 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24647 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24648 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24649 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24650 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24651 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24652 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24653 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24654 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24655 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24656 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24657 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24659 /* Instructions that were new with the real FPA, call them V2. */
24661 #define ARM_VARIANT & fpu_fpa_ext_v2
24663 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24664 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24665 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24666 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24667 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24668 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24671 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24672 #undef THUMB_VARIANT
24673 #define THUMB_VARIANT & arm_ext_v6t2
24674 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24675 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
24676 #undef THUMB_VARIANT
24678 /* Moves and type conversions. */
24679 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24680 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24681 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24682 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24683 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24684 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24685 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24686 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24687 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24689 /* Memory operations. */
24690 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24691 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24692 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24693 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24694 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24695 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24696 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24697 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24698 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24699 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24700 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24701 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24702 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24703 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24704 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24705 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24706 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24707 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24709 /* Monadic operations. */
24710 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24711 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24712 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24714 /* Dyadic operations. */
24715 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24716 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24717 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24718 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24719 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24720 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24721 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24722 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24723 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24726 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24727 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
24728 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24729 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
24731 /* Double precision load/store are still present on single precision
24732 implementations. */
24733 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24734 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24735 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24736 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24737 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24738 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24739 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24740 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24741 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24742 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24745 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24747 /* Moves and type conversions. */
24748 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24749 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24750 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24751 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24752 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24753 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24754 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24755 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24756 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24757 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24758 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24759 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24761 /* Monadic operations. */
24762 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24763 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24764 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24766 /* Dyadic operations. */
24767 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24768 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24769 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24770 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24771 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24772 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24773 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24774 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24775 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24778 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24779 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
24780 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24781 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
24783 /* Instructions which may belong to either the Neon or VFP instruction sets.
24784 Individual encoder functions perform additional architecture checks. */
24786 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24787 #undef THUMB_VARIANT
24788 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
24790 /* These mnemonics are unique to VFP. */
24791 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
24792 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
24793 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24794 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24795 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24796 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
24797 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
24798 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
24800 /* Mnemonics shared by Neon and VFP. */
24801 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
24803 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24804 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24805 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24806 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24807 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24808 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24810 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
24811 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
24812 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
24813 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
24816 /* NOTE: All VMOV encoding is special-cased! */
24817 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
24819 #undef THUMB_VARIANT
24820 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24821 by different feature bits. Since we are setting the Thumb guard, we can
24822 require Thumb-1 which makes it a nop guard and set the right feature bit in
24823 do_vldr_vstr (). */
24824 #define THUMB_VARIANT & arm_ext_v4t
24825 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24826 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24829 #define ARM_VARIANT & arm_ext_fp16
24830 #undef THUMB_VARIANT
24831 #define THUMB_VARIANT & arm_ext_fp16
24832 /* New instructions added from v8.2, allowing the extraction and insertion of
24833 the upper 16 bits of a 32-bit vector register. */
24834 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
24835 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
24837 /* New backported fma/fms instructions optional in v8.2. */
24838 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
24839 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
24841 #undef THUMB_VARIANT
24842 #define THUMB_VARIANT & fpu_neon_ext_v1
24844 #define ARM_VARIANT & fpu_neon_ext_v1
24846 /* Data processing with three registers of the same length. */
24847 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24848 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
24849 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
24850 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24851 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24852 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24853 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
24854 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24855 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24856 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24857 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24858 /* If not immediate, fall back to neon_dyadic_i64_su.
24859 shl should accept I8 I16 I32 I64,
24860 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24861 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
24862 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
24863 /* Logic ops, types optional & ignored. */
24864 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24865 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24866 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24867 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24868 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
24869 /* Bitfield ops, untyped. */
24870 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24871 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24872 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24873 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24874 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24875 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24876 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
24877 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24878 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24879 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24880 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24881 back to neon_dyadic_if_su. */
24882 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24883 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24884 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24885 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24886 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24887 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24888 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24889 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24890 /* Comparison. Type I8 I16 I32 F32. */
24891 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
24892 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
24893 /* As above, D registers only. */
24894 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24895 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24896 /* Int and float variants, signedness unimportant. */
24897 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24898 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24899 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
24900 /* Add/sub take types I8 I16 I32 I64 F32. */
24901 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24902 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24903 /* vtst takes sizes 8, 16, 32. */
24904 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
24905 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
24906 /* VMUL takes I8 I16 I32 F32 P8. */
24907 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
24908 /* VQD{R}MULH takes S16 S32. */
24909 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24910 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24911 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24912 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24913 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24914 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24915 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24916 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24917 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24918 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24919 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24920 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24921 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24922 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24923 /* ARM v8.1 extension. */
24924 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24925 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
24926 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24928 /* Two address, int/float. Types S8 S16 S32 F32. */
24929 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24930 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24932 /* Data processing with two registers and a shift amount. */
24933 /* Right shifts, and variants with rounding.
24934 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
24935 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24936 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24937 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24938 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24939 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24940 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24941 /* Shift and insert. Sizes accepted 8 16 32 64. */
24942 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
24943 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
24944 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24945 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
24946 /* Right shift immediate, saturating & narrowing, with rounding variants.
24947 Types accepted S16 S32 S64 U16 U32 U64. */
24948 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24949 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24950 /* As above, unsigned. Types accepted S16 S32 S64. */
24951 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24952 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24953 /* Right shift narrowing. Types accepted I16 I32 I64. */
24954 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24955 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24956 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24957 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
24958 /* CVT with optional immediate for fixed-point variant. */
24959 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
24961 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
24963 /* Data processing, three registers of different lengths. */
24964 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24965 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
24966 /* If not scalar, fall back to neon_dyadic_long.
24967 Vector types as above, scalar types S16 S32 U16 U32. */
24968 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24969 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24970 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24971 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24972 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24973 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24974 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24975 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24976 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24977 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24978 /* Saturating doubling multiplies. Types S16 S32. */
24979 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24980 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24981 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24982 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24983 S16 S32 U16 U32. */
24984 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
24986 /* Extract. Size 8. */
24987 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
24988 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
24990 /* Two registers, miscellaneous. */
24991 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
24992 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
24993 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
24994 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
24995 /* Vector replicate. Sizes 8 16 32. */
24996 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
24997 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24998 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
24999 /* VMOVN. Types I16 I32 I64. */
25000 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
25001 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
25002 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
25003 /* VQMOVUN. Types S16 S32 S64. */
25004 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
25005 /* VZIP / VUZP. Sizes 8 16 32. */
25006 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25007 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25008 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25009 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25010 /* VQABS / VQNEG. Types S8 S16 S32. */
25011 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25012 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25013 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25014 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25015 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
25016 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25017 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
25018 /* Reciprocal estimates. Types U32 F16 F32. */
25019 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25020 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
25021 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25022 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
25023 /* VCLS. Types S8 S16 S32. */
25024 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
25025 /* VCLZ. Types I8 I16 I32. */
25026 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
25027 /* VCNT. Size 8. */
25028 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
25029 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
25030 /* Two address, untyped. */
25031 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
25032 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
25033 /* VTRN. Sizes 8 16 32. */
25034 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
25035 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
25037 /* Table lookup. Size 8. */
25038 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25039 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25041 #undef THUMB_VARIANT
25042 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25044 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25046 /* Neon element/structure load/store. */
25047 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25048 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25049 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25050 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25051 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25052 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25053 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25054 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25056 #undef THUMB_VARIANT
25057 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25059 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25060 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25061 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25062 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25063 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25064 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25065 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25066 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25067 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25068 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25070 #undef THUMB_VARIANT
25071 #define THUMB_VARIANT & fpu_vfp_ext_v3
25073 #define ARM_VARIANT & fpu_vfp_ext_v3
25075 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25076 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25077 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25078 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25079 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25080 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25081 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25082 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25083 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25086 #define ARM_VARIANT & fpu_vfp_ext_fma
25087 #undef THUMB_VARIANT
25088 #define THUMB_VARIANT & fpu_vfp_ext_fma
25089 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
25090 VFP FMA variant; NEON and VFP FMA always includes the NEON
25091 FMA instructions. */
25092 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25093 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25095 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25096 the v form should always be used. */
25097 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25098 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25099 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25100 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25101 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25102 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25104 #undef THUMB_VARIANT
25106 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25108 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25109 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25110 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25111 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25112 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25113 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25114 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25115 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25118 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25120 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25121 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25122 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25123 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25124 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25125 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25126 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25127 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25128 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25129 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25130 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25131 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25132 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25133 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25134 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25135 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25136 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25137 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25138 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25139 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25140 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25141 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25142 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25143 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25144 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25145 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25146 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25147 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25148 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25149 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25150 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25151 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25152 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25153 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25154 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25155 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25156 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25157 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25158 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25159 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25160 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25161 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25162 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25163 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25164 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25165 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25166 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
25167 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25168 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25169 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25170 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25171 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25172 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25173 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25174 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25175 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25176 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25177 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25178 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25179 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25180 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25181 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25182 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25183 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25184 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25185 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25186 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25187 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25188 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25189 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25190 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25191 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25192 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25193 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25194 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25195 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25196 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25197 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25198 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25199 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25200 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25201 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25202 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25203 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25204 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25205 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25206 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25207 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25208 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
25209 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25210 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25211 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25212 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25213 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25214 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25215 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25216 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25217 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25218 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25219 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25220 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25221 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25222 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25223 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25224 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25225 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25226 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25227 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25228 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25229 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25230 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
25231 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25232 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25233 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25234 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25235 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25236 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25237 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25238 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25239 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25240 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25241 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25242 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25243 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25244 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25245 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25246 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25247 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25248 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25249 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25250 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25251 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25252 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25253 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25254 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25255 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25256 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25257 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25258 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25259 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25260 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25261 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25262 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25263 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25264 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25265 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25266 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25267 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25268 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25269 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25270 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25271 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25272 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25273 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25274 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25275 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25276 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25277 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25278 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25279 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25280 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25281 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
25284 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
25286 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
25287 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
25288 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
25289 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25290 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25291 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25292 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25293 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25294 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25295 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25296 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25297 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25298 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25299 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25300 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25301 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25302 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25303 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25304 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25305 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25306 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
25307 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25308 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25309 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25310 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25311 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25312 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25313 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25314 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25315 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25316 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25317 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25318 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25319 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25320 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25321 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25322 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25323 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25324 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25325 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25326 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25327 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25328 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25329 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25330 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25331 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25332 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25333 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25334 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25335 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25336 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25337 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25338 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25339 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25340 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25341 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25342 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25345 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25347 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25348 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25349 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25350 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25351 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25352 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25353 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25354 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25355 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
25356 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
25357 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
25358 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
25359 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
25360 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
25361 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
25362 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
25363 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
25364 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
25365 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
25366 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
25367 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
25368 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
25369 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
25370 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
25371 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
25372 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
25373 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
25374 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
25375 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
25376 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
25377 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
25378 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
25379 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
25380 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
25381 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
25382 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
25383 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
25384 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
25385 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
25386 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
25387 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
25388 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
25389 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
25390 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
25391 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
25392 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
25393 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
25394 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
25395 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
25396 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
25397 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
25398 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
25399 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
25400 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
25401 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25402 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25403 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25404 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25405 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25406 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25407 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
25408 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
25409 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
25410 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
25411 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25412 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25413 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25414 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25415 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25416 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25417 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25418 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25419 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25420 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25421 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25422 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25424 /* ARMv8.5-A instructions. */
25426 #define ARM_VARIANT & arm_ext_sb
25427 #undef THUMB_VARIANT
25428 #define THUMB_VARIANT & arm_ext_sb
25429 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
25432 #define ARM_VARIANT & arm_ext_predres
25433 #undef THUMB_VARIANT
25434 #define THUMB_VARIANT & arm_ext_predres
25435 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
25436 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
25437 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
25439 /* ARMv8-M instructions. */
25441 #define ARM_VARIANT NULL
25442 #undef THUMB_VARIANT
25443 #define THUMB_VARIANT & arm_ext_v8m
25444 ToU("sg", e97fe97f
, 0, (), noargs
),
25445 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
25446 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
25447 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
25448 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
25449 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
25450 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
25452 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25453 instructions behave as nop if no VFP is present. */
25454 #undef THUMB_VARIANT
25455 #define THUMB_VARIANT & arm_ext_v8m_main
25456 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
25457 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
25459 /* Armv8.1-M Mainline instructions. */
25460 #undef THUMB_VARIANT
25461 #define THUMB_VARIANT & arm_ext_v8_1m_main
25462 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25463 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25464 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25465 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25466 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
25467 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
25468 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25469 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25470 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25472 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
25473 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
25474 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25475 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
25476 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25478 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
25479 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
25480 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
25482 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
25483 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
25485 #undef THUMB_VARIANT
25486 #define THUMB_VARIANT & mve_ext
25487 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25488 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25489 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25490 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
25491 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
25492 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25493 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25494 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25495 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25496 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25497 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25498 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25499 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25500 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25501 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25503 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25504 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25505 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25506 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25507 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25508 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25509 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25510 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25511 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25512 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25513 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25514 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25515 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25516 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25517 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25519 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
25520 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
25521 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
25522 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
25523 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
25524 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
25525 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
25526 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
25527 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
25528 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
25529 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
25530 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
25531 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
25532 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
25533 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
25535 /* MVE and MVE FP only. */
25536 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
25537 mCEF(vctp
, _vctp
, 1, (RRnpc
), mve_vctp
),
25538 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25539 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25540 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25541 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25542 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
25543 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
25544 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25545 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25546 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25547 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25548 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25549 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25550 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25551 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25552 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25553 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25555 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25556 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25557 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25558 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25559 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25560 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25561 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25562 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25563 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25564 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25565 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25566 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25567 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25568 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25569 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25570 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25571 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25572 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25573 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25574 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25576 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
25577 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25578 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25579 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25580 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25581 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25582 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25583 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25584 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25585 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25586 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25587 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25588 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25589 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25590 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25591 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25592 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25594 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25595 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25596 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25597 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25598 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25599 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25600 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25601 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25602 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25603 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25604 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25605 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25606 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25607 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25608 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25609 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25610 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25611 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25612 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25613 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25615 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25616 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25617 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25618 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25619 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25621 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25622 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25623 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25624 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25625 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25626 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25627 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25628 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25629 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25630 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25631 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25632 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25633 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25634 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25635 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25636 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25637 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25639 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25640 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25641 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25642 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25643 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25644 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25645 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25646 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25647 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25648 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25649 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25650 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25652 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
25653 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25654 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25656 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
25657 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
25658 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
25659 toU("lctp", _lctp
, 0, (), t_loloop
),
25661 #undef THUMB_VARIANT
25662 #define THUMB_VARIANT & mve_fp_ext
25663 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25664 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25665 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25666 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25667 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25668 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25669 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25670 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25673 #define ARM_VARIANT & fpu_vfp_ext_v1
25674 #undef THUMB_VARIANT
25675 #define THUMB_VARIANT & arm_ext_v6t2
25676 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25677 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25679 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25682 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25684 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25685 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25686 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25687 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25689 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25690 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25691 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25693 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25694 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25696 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25697 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25699 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25700 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25703 #define ARM_VARIANT & fpu_vfp_ext_v2
25705 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
25706 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
25707 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
25708 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
25711 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25712 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
25713 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
25714 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
25715 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
25716 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25717 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25720 #define ARM_VARIANT & fpu_neon_ext_v1
25721 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25722 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
25723 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25724 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25725 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25726 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25727 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25728 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25729 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
25730 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
25731 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
25732 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
25733 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25734 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
25735 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25736 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25737 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25738 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25739 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25740 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
25741 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25742 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25743 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
25744 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25745 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25746 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25747 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25748 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25749 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25750 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
25751 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
25752 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25753 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25754 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25755 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
25756 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
25757 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
25760 #define ARM_VARIANT & arm_ext_v8_3
25761 #undef THUMB_VARIANT
25762 #define THUMB_VARIANT & arm_ext_v6t2_v8m
25763 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
25764 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
25767 #undef THUMB_VARIANT
25799 /* MD interface: bits in the object file. */
25801 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25802 for use in the a.out file, and stores them in the array pointed to by buf.
25803 This knows about the endian-ness of the target machine and does
25804 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25805 2 (short) and 4 (long) Floating numbers are put out as a series of
25806 LITTLENUMS (shorts, here at least). */
25809 md_number_to_chars (char * buf
, valueT val
, int n
)
25811 if (target_big_endian
)
25812 number_to_chars_bigendian (buf
, val
, n
);
25814 number_to_chars_littleendian (buf
, val
, n
);
25818 md_chars_to_number (char * buf
, int n
)
25821 unsigned char * where
= (unsigned char *) buf
;
25823 if (target_big_endian
)
25828 result
|= (*where
++ & 255);
25836 result
|= (where
[n
] & 255);
25843 /* MD interface: Sections. */
25845 /* Calculate the maximum variable size (i.e., excluding fr_fix)
25846 that an rs_machine_dependent frag may reach. */
25849 arm_frag_max_var (fragS
*fragp
)
25851 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25852 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25854 Note that we generate relaxable instructions even for cases that don't
25855 really need it, like an immediate that's a trivial constant. So we're
25856 overestimating the instruction size for some of those cases. Rather
25857 than putting more intelligence here, it would probably be better to
25858 avoid generating a relaxation frag in the first place when it can be
25859 determined up front that a short instruction will suffice. */
25861 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
25865 /* Estimate the size of a frag before relaxing. Assume everything fits in
25869 md_estimate_size_before_relax (fragS
* fragp
,
25870 segT segtype ATTRIBUTE_UNUSED
)
25876 /* Convert a machine dependent frag. */
25879 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
25881 unsigned long insn
;
25882 unsigned long old_op
;
25890 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25892 old_op
= bfd_get_16(abfd
, buf
);
25893 if (fragp
->fr_symbol
)
25895 exp
.X_op
= O_symbol
;
25896 exp
.X_add_symbol
= fragp
->fr_symbol
;
25900 exp
.X_op
= O_constant
;
25902 exp
.X_add_number
= fragp
->fr_offset
;
25903 opcode
= fragp
->fr_subtype
;
25906 case T_MNEM_ldr_pc
:
25907 case T_MNEM_ldr_pc2
:
25908 case T_MNEM_ldr_sp
:
25909 case T_MNEM_str_sp
:
25916 if (fragp
->fr_var
== 4)
25918 insn
= THUMB_OP32 (opcode
);
25919 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
25921 insn
|= (old_op
& 0x700) << 4;
25925 insn
|= (old_op
& 7) << 12;
25926 insn
|= (old_op
& 0x38) << 13;
25928 insn
|= 0x00000c00;
25929 put_thumb32_insn (buf
, insn
);
25930 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
25934 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
25936 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
25939 if (fragp
->fr_var
== 4)
25941 insn
= THUMB_OP32 (opcode
);
25942 insn
|= (old_op
& 0xf0) << 4;
25943 put_thumb32_insn (buf
, insn
);
25944 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
25948 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25949 exp
.X_add_number
-= 4;
25957 if (fragp
->fr_var
== 4)
25959 int r0off
= (opcode
== T_MNEM_mov
25960 || opcode
== T_MNEM_movs
) ? 0 : 8;
25961 insn
= THUMB_OP32 (opcode
);
25962 insn
= (insn
& 0xe1ffffff) | 0x10000000;
25963 insn
|= (old_op
& 0x700) << r0off
;
25964 put_thumb32_insn (buf
, insn
);
25965 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25969 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
25974 if (fragp
->fr_var
== 4)
25976 insn
= THUMB_OP32(opcode
);
25977 put_thumb32_insn (buf
, insn
);
25978 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
25981 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
25985 if (fragp
->fr_var
== 4)
25987 insn
= THUMB_OP32(opcode
);
25988 insn
|= (old_op
& 0xf00) << 14;
25989 put_thumb32_insn (buf
, insn
);
25990 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
25993 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
25996 case T_MNEM_add_sp
:
25997 case T_MNEM_add_pc
:
25998 case T_MNEM_inc_sp
:
25999 case T_MNEM_dec_sp
:
26000 if (fragp
->fr_var
== 4)
26002 /* ??? Choose between add and addw. */
26003 insn
= THUMB_OP32 (opcode
);
26004 insn
|= (old_op
& 0xf0) << 4;
26005 put_thumb32_insn (buf
, insn
);
26006 if (opcode
== T_MNEM_add_pc
)
26007 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
26009 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26012 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26020 if (fragp
->fr_var
== 4)
26022 insn
= THUMB_OP32 (opcode
);
26023 insn
|= (old_op
& 0xf0) << 4;
26024 insn
|= (old_op
& 0xf) << 16;
26025 put_thumb32_insn (buf
, insn
);
26026 if (insn
& (1 << 20))
26027 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26029 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26032 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26038 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
26039 (enum bfd_reloc_code_real
) reloc_type
);
26040 fixp
->fx_file
= fragp
->fr_file
;
26041 fixp
->fx_line
= fragp
->fr_line
;
26042 fragp
->fr_fix
+= fragp
->fr_var
;
26044 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26045 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
26046 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
26047 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26050 /* Return the size of a relaxable immediate operand instruction.
26051 SHIFT and SIZE specify the form of the allowable immediate. */
26053 relax_immediate (fragS
*fragp
, int size
, int shift
)
26059 /* ??? Should be able to do better than this. */
26060 if (fragp
->fr_symbol
)
26063 low
= (1 << shift
) - 1;
26064 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26065 offset
= fragp
->fr_offset
;
26066 /* Force misaligned offsets to 32-bit variant. */
26069 if (offset
& ~mask
)
26074 /* Get the address of a symbol during relaxation. */
26076 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
26082 sym
= fragp
->fr_symbol
;
26083 sym_frag
= symbol_get_frag (sym
);
26084 know (S_GET_SEGMENT (sym
) != absolute_section
26085 || sym_frag
== &zero_address_frag
);
26086 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26088 /* If frag has yet to be reached on this pass, assume it will
26089 move by STRETCH just as we did. If this is not so, it will
26090 be because some frag between grows, and that will force
26094 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26098 /* Adjust stretch for any alignment frag. Note that if have
26099 been expanding the earlier code, the symbol may be
26100 defined in what appears to be an earlier frag. FIXME:
26101 This doesn't handle the fr_subtype field, which specifies
26102 a maximum number of bytes to skip when doing an
26104 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26106 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
26109 stretch
= - ((- stretch
)
26110 & ~ ((1 << (int) f
->fr_offset
) - 1));
26112 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
26124 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
26127 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
26132 /* Assume worst case for symbols not known to be in the same section. */
26133 if (fragp
->fr_symbol
== NULL
26134 || !S_IS_DEFINED (fragp
->fr_symbol
)
26135 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26136 || S_IS_WEAK (fragp
->fr_symbol
))
26139 val
= relaxed_symbol_addr (fragp
, stretch
);
26140 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
26141 addr
= (addr
+ 4) & ~3;
26142 /* Force misaligned targets to 32-bit variant. */
26146 if (val
< 0 || val
> 1020)
26151 /* Return the size of a relaxable add/sub immediate instruction. */
26153 relax_addsub (fragS
*fragp
, asection
*sec
)
26158 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26159 op
= bfd_get_16(sec
->owner
, buf
);
26160 if ((op
& 0xf) == ((op
>> 4) & 0xf))
26161 return relax_immediate (fragp
, 8, 0);
26163 return relax_immediate (fragp
, 3, 0);
26166 /* Return TRUE iff the definition of symbol S could be pre-empted
26167 (overridden) at link or load time. */
26169 symbol_preemptible (symbolS
*s
)
26171 /* Weak symbols can always be pre-empted. */
26175 /* Non-global symbols cannot be pre-empted. */
26176 if (! S_IS_EXTERNAL (s
))
26180 /* In ELF, a global symbol can be marked protected, or private. In that
26181 case it can't be pre-empted (other definitions in the same link unit
26182 would violate the ODR). */
26183 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
26187 /* Other global symbols might be pre-empted. */
26191 /* Return the size of a relaxable branch instruction. BITS is the
26192 size of the offset field in the narrow instruction. */
26195 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
26201 /* Assume worst case for symbols not known to be in the same section. */
26202 if (!S_IS_DEFINED (fragp
->fr_symbol
)
26203 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26204 || S_IS_WEAK (fragp
->fr_symbol
))
26208 /* A branch to a function in ARM state will require interworking. */
26209 if (S_IS_DEFINED (fragp
->fr_symbol
)
26210 && ARM_IS_FUNC (fragp
->fr_symbol
))
26214 if (symbol_preemptible (fragp
->fr_symbol
))
26217 val
= relaxed_symbol_addr (fragp
, stretch
);
26218 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
26221 /* Offset is a signed value *2 */
26223 if (val
>= limit
|| val
< -limit
)
26229 /* Relax a machine dependent frag. This returns the amount by which
26230 the current size of the frag should change. */
26233 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
26238 oldsize
= fragp
->fr_var
;
26239 switch (fragp
->fr_subtype
)
26241 case T_MNEM_ldr_pc2
:
26242 newsize
= relax_adr (fragp
, sec
, stretch
);
26244 case T_MNEM_ldr_pc
:
26245 case T_MNEM_ldr_sp
:
26246 case T_MNEM_str_sp
:
26247 newsize
= relax_immediate (fragp
, 8, 2);
26251 newsize
= relax_immediate (fragp
, 5, 2);
26255 newsize
= relax_immediate (fragp
, 5, 1);
26259 newsize
= relax_immediate (fragp
, 5, 0);
26262 newsize
= relax_adr (fragp
, sec
, stretch
);
26268 newsize
= relax_immediate (fragp
, 8, 0);
26271 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
26274 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
26276 case T_MNEM_add_sp
:
26277 case T_MNEM_add_pc
:
26278 newsize
= relax_immediate (fragp
, 8, 2);
26280 case T_MNEM_inc_sp
:
26281 case T_MNEM_dec_sp
:
26282 newsize
= relax_immediate (fragp
, 7, 2);
26288 newsize
= relax_addsub (fragp
, sec
);
26294 fragp
->fr_var
= newsize
;
26295 /* Freeze wide instructions that are at or before the same location as
26296 in the previous pass. This avoids infinite loops.
26297 Don't freeze them unconditionally because targets may be artificially
26298 misaligned by the expansion of preceding frags. */
26299 if (stretch
<= 0 && newsize
> 2)
26301 md_convert_frag (sec
->owner
, sec
, fragp
);
26305 return newsize
- oldsize
;
26308 /* Round up a section size to the appropriate boundary. */
26311 md_section_align (segT segment ATTRIBUTE_UNUSED
,
26317 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
26318 of an rs_align_code fragment. */
26321 arm_handle_align (fragS
* fragP
)
26323 static unsigned char const arm_noop
[2][2][4] =
26326 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
26327 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
26330 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
26331 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
26334 static unsigned char const thumb_noop
[2][2][2] =
26337 {0xc0, 0x46}, /* LE */
26338 {0x46, 0xc0}, /* BE */
26341 {0x00, 0xbf}, /* LE */
26342 {0xbf, 0x00} /* BE */
26345 static unsigned char const wide_thumb_noop
[2][4] =
26346 { /* Wide Thumb-2 */
26347 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
26348 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
26351 unsigned bytes
, fix
, noop_size
;
26353 const unsigned char * noop
;
26354 const unsigned char *narrow_noop
= NULL
;
26359 if (fragP
->fr_type
!= rs_align_code
)
26362 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
26363 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
26366 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26367 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
26369 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
26371 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
26373 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26374 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
26376 narrow_noop
= thumb_noop
[1][target_big_endian
];
26377 noop
= wide_thumb_noop
[target_big_endian
];
26380 noop
= thumb_noop
[0][target_big_endian
];
26388 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26389 ? selected_cpu
: arm_arch_none
,
26391 [target_big_endian
];
26398 fragP
->fr_var
= noop_size
;
26400 if (bytes
& (noop_size
- 1))
26402 fix
= bytes
& (noop_size
- 1);
26404 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
26406 memset (p
, 0, fix
);
26413 if (bytes
& noop_size
)
26415 /* Insert a narrow noop. */
26416 memcpy (p
, narrow_noop
, noop_size
);
26418 bytes
-= noop_size
;
26422 /* Use wide noops for the remainder */
26426 while (bytes
>= noop_size
)
26428 memcpy (p
, noop
, noop_size
);
26430 bytes
-= noop_size
;
26434 fragP
->fr_fix
+= fix
;
26437 /* Called from md_do_align. Used to create an alignment
26438 frag in a code section. */
26441 arm_frag_align_code (int n
, int max
)
26445 /* We assume that there will never be a requirement
26446 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
26447 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26452 _("alignments greater than %d bytes not supported in .text sections."),
26453 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
26454 as_fatal ("%s", err_msg
);
26457 p
= frag_var (rs_align_code
,
26458 MAX_MEM_FOR_RS_ALIGN_CODE
,
26460 (relax_substateT
) max
,
26467 /* Perform target specific initialisation of a frag.
26468 Note - despite the name this initialisation is not done when the frag
26469 is created, but only when its type is assigned. A frag can be created
26470 and used a long time before its type is set, so beware of assuming that
26471 this initialisation is performed first. */
26475 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
26477 /* Record whether this frag is in an ARM or a THUMB area. */
26478 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26481 #else /* OBJ_ELF is defined. */
26483 arm_init_frag (fragS
* fragP
, int max_chars
)
26485 bfd_boolean frag_thumb_mode
;
26487 /* If the current ARM vs THUMB mode has not already
26488 been recorded into this frag then do so now. */
26489 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
26490 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26492 /* PR 21809: Do not set a mapping state for debug sections
26493 - it just confuses other tools. */
26494 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
26497 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
26499 /* Record a mapping symbol for alignment frags. We will delete this
26500 later if the alignment ends up empty. */
26501 switch (fragP
->fr_type
)
26504 case rs_align_test
:
26506 mapping_state_2 (MAP_DATA
, max_chars
);
26508 case rs_align_code
:
26509 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
26516 /* When we change sections we need to issue a new mapping symbol. */
26519 arm_elf_change_section (void)
26521 /* Link an unlinked unwind index table section to the .text section. */
26522 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
26523 && elf_linked_to_section (now_seg
) == NULL
)
26524 elf_linked_to_section (now_seg
) = text_section
;
26528 arm_elf_section_type (const char * str
, size_t len
)
26530 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
26531 return SHT_ARM_EXIDX
;
26536 /* Code to deal with unwinding tables. */
26538 static void add_unwind_adjustsp (offsetT
);
26540 /* Generate any deferred unwind frame offset. */
26543 flush_pending_unwind (void)
26547 offset
= unwind
.pending_offset
;
26548 unwind
.pending_offset
= 0;
26550 add_unwind_adjustsp (offset
);
26553 /* Add an opcode to this list for this function. Two-byte opcodes should
26554 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26558 add_unwind_opcode (valueT op
, int length
)
26560 /* Add any deferred stack adjustment. */
26561 if (unwind
.pending_offset
)
26562 flush_pending_unwind ();
26564 unwind
.sp_restored
= 0;
26566 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
26568 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
26569 if (unwind
.opcodes
)
26570 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
26571 unwind
.opcode_alloc
);
26573 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
26578 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
26580 unwind
.opcode_count
++;
26584 /* Add unwind opcodes to adjust the stack pointer. */
26587 add_unwind_adjustsp (offsetT offset
)
26591 if (offset
> 0x200)
26593 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26598 /* Long form: 0xb2, uleb128. */
26599 /* This might not fit in a word so add the individual bytes,
26600 remembering the list is built in reverse order. */
26601 o
= (valueT
) ((offset
- 0x204) >> 2);
26603 add_unwind_opcode (0, 1);
26605 /* Calculate the uleb128 encoding of the offset. */
26609 bytes
[n
] = o
& 0x7f;
26615 /* Add the insn. */
26617 add_unwind_opcode (bytes
[n
- 1], 1);
26618 add_unwind_opcode (0xb2, 1);
26620 else if (offset
> 0x100)
26622 /* Two short opcodes. */
26623 add_unwind_opcode (0x3f, 1);
26624 op
= (offset
- 0x104) >> 2;
26625 add_unwind_opcode (op
, 1);
26627 else if (offset
> 0)
26629 /* Short opcode. */
26630 op
= (offset
- 4) >> 2;
26631 add_unwind_opcode (op
, 1);
26633 else if (offset
< 0)
26636 while (offset
> 0x100)
26638 add_unwind_opcode (0x7f, 1);
26641 op
= ((offset
- 4) >> 2) | 0x40;
26642 add_unwind_opcode (op
, 1);
26646 /* Finish the list of unwind opcodes for this function. */
26649 finish_unwind_opcodes (void)
26653 if (unwind
.fp_used
)
26655 /* Adjust sp as necessary. */
26656 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26657 flush_pending_unwind ();
26659 /* After restoring sp from the frame pointer. */
26660 op
= 0x90 | unwind
.fp_reg
;
26661 add_unwind_opcode (op
, 1);
26664 flush_pending_unwind ();
26668 /* Start an exception table entry. If idx is nonzero this is an index table
26672 start_unwind_section (const segT text_seg
, int idx
)
26674 const char * text_name
;
26675 const char * prefix
;
26676 const char * prefix_once
;
26677 const char * group_name
;
26685 prefix
= ELF_STRING_ARM_unwind
;
26686 prefix_once
= ELF_STRING_ARM_unwind_once
;
26687 type
= SHT_ARM_EXIDX
;
26691 prefix
= ELF_STRING_ARM_unwind_info
;
26692 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
26693 type
= SHT_PROGBITS
;
26696 text_name
= segment_name (text_seg
);
26697 if (streq (text_name
, ".text"))
26700 if (strncmp (text_name
, ".gnu.linkonce.t.",
26701 strlen (".gnu.linkonce.t.")) == 0)
26703 prefix
= prefix_once
;
26704 text_name
+= strlen (".gnu.linkonce.t.");
26707 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
26713 /* Handle COMDAT group. */
26714 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
26716 group_name
= elf_group_name (text_seg
);
26717 if (group_name
== NULL
)
26719 as_bad (_("Group section `%s' has no group signature"),
26720 segment_name (text_seg
));
26721 ignore_rest_of_line ();
26724 flags
|= SHF_GROUP
;
26728 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
26731 /* Set the section link for index tables. */
26733 elf_linked_to_section (now_seg
) = text_seg
;
26737 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26738 personality routine data. Returns zero, or the index table value for
26739 an inline entry. */
26742 create_unwind_entry (int have_data
)
26747 /* The current word of data. */
26749 /* The number of bytes left in this word. */
26752 finish_unwind_opcodes ();
26754 /* Remember the current text section. */
26755 unwind
.saved_seg
= now_seg
;
26756 unwind
.saved_subseg
= now_subseg
;
26758 start_unwind_section (now_seg
, 0);
26760 if (unwind
.personality_routine
== NULL
)
26762 if (unwind
.personality_index
== -2)
26765 as_bad (_("handlerdata in cantunwind frame"));
26766 return 1; /* EXIDX_CANTUNWIND. */
26769 /* Use a default personality routine if none is specified. */
26770 if (unwind
.personality_index
== -1)
26772 if (unwind
.opcode_count
> 3)
26773 unwind
.personality_index
= 1;
26775 unwind
.personality_index
= 0;
26778 /* Space for the personality routine entry. */
26779 if (unwind
.personality_index
== 0)
26781 if (unwind
.opcode_count
> 3)
26782 as_bad (_("too many unwind opcodes for personality routine 0"));
26786 /* All the data is inline in the index table. */
26789 while (unwind
.opcode_count
> 0)
26791 unwind
.opcode_count
--;
26792 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26796 /* Pad with "finish" opcodes. */
26798 data
= (data
<< 8) | 0xb0;
26805 /* We get two opcodes "free" in the first word. */
26806 size
= unwind
.opcode_count
- 2;
26810 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26811 if (unwind
.personality_index
!= -1)
26813 as_bad (_("attempt to recreate an unwind entry"));
26817 /* An extra byte is required for the opcode count. */
26818 size
= unwind
.opcode_count
+ 1;
26821 size
= (size
+ 3) >> 2;
26823 as_bad (_("too many unwind opcodes"));
26825 frag_align (2, 0, 0);
26826 record_alignment (now_seg
, 2);
26827 unwind
.table_entry
= expr_build_dot ();
26829 /* Allocate the table entry. */
26830 ptr
= frag_more ((size
<< 2) + 4);
26831 /* PR 13449: Zero the table entries in case some of them are not used. */
26832 memset (ptr
, 0, (size
<< 2) + 4);
26833 where
= frag_now_fix () - ((size
<< 2) + 4);
26835 switch (unwind
.personality_index
)
26838 /* ??? Should this be a PLT generating relocation? */
26839 /* Custom personality routine. */
26840 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
26841 BFD_RELOC_ARM_PREL31
);
26846 /* Set the first byte to the number of additional words. */
26847 data
= size
> 0 ? size
- 1 : 0;
26851 /* ABI defined personality routines. */
26853 /* Three opcodes bytes are packed into the first word. */
26860 /* The size and first two opcode bytes go in the first word. */
26861 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
26866 /* Should never happen. */
26870 /* Pack the opcodes into words (MSB first), reversing the list at the same
26872 while (unwind
.opcode_count
> 0)
26876 md_number_to_chars (ptr
, data
, 4);
26881 unwind
.opcode_count
--;
26883 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26886 /* Finish off the last word. */
26889 /* Pad with "finish" opcodes. */
26891 data
= (data
<< 8) | 0xb0;
26893 md_number_to_chars (ptr
, data
, 4);
26898 /* Add an empty descriptor if there is no user-specified data. */
26899 ptr
= frag_more (4);
26900 md_number_to_chars (ptr
, 0, 4);
26907 /* Initialize the DWARF-2 unwind information for this procedure. */
26910 tc_arm_frame_initial_instructions (void)
26912 cfi_add_CFA_def_cfa (REG_SP
, 0);
26914 #endif /* OBJ_ELF */
26916 /* Convert REGNAME to a DWARF-2 register number. */
26919 tc_arm_regname_to_dw2regnum (char *regname
)
26921 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
26925 /* PR 16694: Allow VFP registers as well. */
26926 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
26930 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
26939 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
26943 exp
.X_op
= O_secrel
;
26944 exp
.X_add_symbol
= symbol
;
26945 exp
.X_add_number
= 0;
26946 emit_expr (&exp
, size
);
26950 /* MD interface: Symbol and relocation handling. */
26952 /* Return the address within the segment that a PC-relative fixup is
26953 relative to. For ARM, PC-relative fixups applied to instructions
26954 are generally relative to the location of the fixup plus 8 bytes.
26955 Thumb branches are offset by 4, and Thumb loads relative to PC
26956 require special handling. */
26959 md_pcrel_from_section (fixS
* fixP
, segT seg
)
26961 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26963 /* If this is pc-relative and we are going to emit a relocation
26964 then we just want to put out any pipeline compensation that the linker
26965 will need. Otherwise we want to use the calculated base.
26966 For WinCE we skip the bias for externals as well, since this
26967 is how the MS ARM-CE assembler behaves and we want to be compatible. */
26969 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26970 || (arm_force_relocation (fixP
)
26972 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
26978 switch (fixP
->fx_r_type
)
26980 /* PC relative addressing on the Thumb is slightly odd as the
26981 bottom two bits of the PC are forced to zero for the
26982 calculation. This happens *after* application of the
26983 pipeline offset. However, Thumb adrl already adjusts for
26984 this, so we need not do it again. */
26985 case BFD_RELOC_ARM_THUMB_ADD
:
26988 case BFD_RELOC_ARM_THUMB_OFFSET
:
26989 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26990 case BFD_RELOC_ARM_T32_ADD_PC12
:
26991 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26992 return (base
+ 4) & ~3;
26994 /* Thumb branches are simply offset by +4. */
26995 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
26996 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
26997 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
26998 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
26999 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27000 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27001 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27002 case BFD_RELOC_ARM_THUMB_BF17
:
27003 case BFD_RELOC_ARM_THUMB_BF19
:
27004 case BFD_RELOC_ARM_THUMB_BF13
:
27005 case BFD_RELOC_ARM_THUMB_LOOP12
:
27008 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27010 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27011 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27012 && ARM_IS_FUNC (fixP
->fx_addsy
)
27013 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27014 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27017 /* BLX is like branches above, but forces the low two bits of PC to
27019 case BFD_RELOC_THUMB_PCREL_BLX
:
27021 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27022 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27023 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27024 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27025 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27026 return (base
+ 4) & ~3;
27028 /* ARM mode branches are offset by +8. However, the Windows CE
27029 loader expects the relocation not to take this into account. */
27030 case BFD_RELOC_ARM_PCREL_BLX
:
27032 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27033 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27034 && ARM_IS_FUNC (fixP
->fx_addsy
)
27035 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27036 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27039 case BFD_RELOC_ARM_PCREL_CALL
:
27041 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27042 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27043 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27044 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27045 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27048 case BFD_RELOC_ARM_PCREL_BRANCH
:
27049 case BFD_RELOC_ARM_PCREL_JUMP
:
27050 case BFD_RELOC_ARM_PLT32
:
27052 /* When handling fixups immediately, because we have already
27053 discovered the value of a symbol, or the address of the frag involved
27054 we must account for the offset by +8, as the OS loader will never see the reloc.
27055 see fixup_segment() in write.c
27056 The S_IS_EXTERNAL test handles the case of global symbols.
27057 Those need the calculated base, not just the pipe compensation the linker will need. */
27059 && fixP
->fx_addsy
!= NULL
27060 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27061 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27069 /* ARM mode loads relative to PC are also offset by +8. Unlike
27070 branches, the Windows CE loader *does* expect the relocation
27071 to take this into account. */
27072 case BFD_RELOC_ARM_OFFSET_IMM
:
27073 case BFD_RELOC_ARM_OFFSET_IMM8
:
27074 case BFD_RELOC_ARM_HWLITERAL
:
27075 case BFD_RELOC_ARM_LITERAL
:
27076 case BFD_RELOC_ARM_CP_OFF_IMM
:
27080 /* Other PC-relative relocations are un-offset. */
27086 static bfd_boolean flag_warn_syms
= TRUE
;
27089 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27091 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27092 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27093 does mean that the resulting code might be very confusing to the reader.
27094 Also this warning can be triggered if the user omits an operand before
27095 an immediate address, eg:
27099 GAS treats this as an assignment of the value of the symbol foo to a
27100 symbol LDR, and so (without this code) it will not issue any kind of
27101 warning or error message.
27103 Note - ARM instructions are case-insensitive but the strings in the hash
27104 table are all stored in lower case, so we must first ensure that name is
27106 if (flag_warn_syms
&& arm_ops_hsh
)
27108 char * nbuf
= strdup (name
);
27111 for (p
= nbuf
; *p
; p
++)
27113 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
27115 static struct hash_control
* already_warned
= NULL
;
27117 if (already_warned
== NULL
)
27118 already_warned
= hash_new ();
27119 /* Only warn about the symbol once. To keep the code
27120 simple we let hash_insert do the lookup for us. */
27121 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
27122 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
27131 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
27132 Otherwise we have no need to default values of symbols. */
27135 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
27138 if (name
[0] == '_' && name
[1] == 'G'
27139 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
27143 if (symbol_find (name
))
27144 as_bad (_("GOT already in the symbol table"));
27146 GOT_symbol
= symbol_new (name
, undefined_section
,
27147 (valueT
) 0, & zero_address_frag
);
27157 /* Subroutine of md_apply_fix. Check to see if an immediate can be
27158 computed as two separate immediate values, added together. We
27159 already know that this value cannot be computed by just one ARM
27162 static unsigned int
27163 validate_immediate_twopart (unsigned int val
,
27164 unsigned int * highpart
)
27169 for (i
= 0; i
< 32; i
+= 2)
27170 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
27176 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
27178 else if (a
& 0xff0000)
27180 if (a
& 0xff000000)
27182 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
27186 gas_assert (a
& 0xff000000);
27187 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
27190 return (a
& 0xff) | (i
<< 7);
27197 validate_offset_imm (unsigned int val
, int hwse
)
27199 if ((hwse
&& val
> 255) || val
> 4095)
27204 /* Subroutine of md_apply_fix. Do those data_ops which can take a
27205 negative immediate constant by altering the instruction. A bit of
27210 by inverting the second operand, and
27213 by negating the second operand. */
27216 negate_data_op (unsigned long * instruction
,
27217 unsigned long value
)
27220 unsigned long negated
, inverted
;
27222 negated
= encode_arm_immediate (-value
);
27223 inverted
= encode_arm_immediate (~value
);
27225 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
27228 /* First negates. */
27229 case OPCODE_SUB
: /* ADD <-> SUB */
27230 new_inst
= OPCODE_ADD
;
27235 new_inst
= OPCODE_SUB
;
27239 case OPCODE_CMP
: /* CMP <-> CMN */
27240 new_inst
= OPCODE_CMN
;
27245 new_inst
= OPCODE_CMP
;
27249 /* Now Inverted ops. */
27250 case OPCODE_MOV
: /* MOV <-> MVN */
27251 new_inst
= OPCODE_MVN
;
27256 new_inst
= OPCODE_MOV
;
27260 case OPCODE_AND
: /* AND <-> BIC */
27261 new_inst
= OPCODE_BIC
;
27266 new_inst
= OPCODE_AND
;
27270 case OPCODE_ADC
: /* ADC <-> SBC */
27271 new_inst
= OPCODE_SBC
;
27276 new_inst
= OPCODE_ADC
;
27280 /* We cannot do anything. */
27285 if (value
== (unsigned) FAIL
)
27288 *instruction
&= OPCODE_MASK
;
27289 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
27293 /* Like negate_data_op, but for Thumb-2. */
27295 static unsigned int
27296 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
27300 unsigned int negated
, inverted
;
27302 negated
= encode_thumb32_immediate (-value
);
27303 inverted
= encode_thumb32_immediate (~value
);
27305 rd
= (*instruction
>> 8) & 0xf;
27306 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
27309 /* ADD <-> SUB. Includes CMP <-> CMN. */
27310 case T2_OPCODE_SUB
:
27311 new_inst
= T2_OPCODE_ADD
;
27315 case T2_OPCODE_ADD
:
27316 new_inst
= T2_OPCODE_SUB
;
27320 /* ORR <-> ORN. Includes MOV <-> MVN. */
27321 case T2_OPCODE_ORR
:
27322 new_inst
= T2_OPCODE_ORN
;
27326 case T2_OPCODE_ORN
:
27327 new_inst
= T2_OPCODE_ORR
;
27331 /* AND <-> BIC. TST has no inverted equivalent. */
27332 case T2_OPCODE_AND
:
27333 new_inst
= T2_OPCODE_BIC
;
27340 case T2_OPCODE_BIC
:
27341 new_inst
= T2_OPCODE_AND
;
27346 case T2_OPCODE_ADC
:
27347 new_inst
= T2_OPCODE_SBC
;
27351 case T2_OPCODE_SBC
:
27352 new_inst
= T2_OPCODE_ADC
;
27356 /* We cannot do anything. */
27361 if (value
== (unsigned int)FAIL
)
27364 *instruction
&= T2_OPCODE_MASK
;
27365 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
27369 /* Read a 32-bit thumb instruction from buf. */
27371 static unsigned long
27372 get_thumb32_insn (char * buf
)
27374 unsigned long insn
;
27375 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
27376 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27381 /* We usually want to set the low bit on the address of thumb function
27382 symbols. In particular .word foo - . should have the low bit set.
27383 Generic code tries to fold the difference of two symbols to
27384 a constant. Prevent this and force a relocation when the first symbols
27385 is a thumb function. */
27388 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
27390 if (op
== O_subtract
27391 && l
->X_op
== O_symbol
27392 && r
->X_op
== O_symbol
27393 && THUMB_IS_FUNC (l
->X_add_symbol
))
27395 l
->X_op
= O_subtract
;
27396 l
->X_op_symbol
= r
->X_add_symbol
;
27397 l
->X_add_number
-= r
->X_add_number
;
27401 /* Process as normal. */
27405 /* Encode Thumb2 unconditional branches and calls. The encoding
27406 for the 2 are identical for the immediate values. */
27409 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
27411 #define T2I1I2MASK ((1 << 13) | (1 << 11))
27414 addressT S
, I1
, I2
, lo
, hi
;
27416 S
= (value
>> 24) & 0x01;
27417 I1
= (value
>> 23) & 0x01;
27418 I2
= (value
>> 22) & 0x01;
27419 hi
= (value
>> 12) & 0x3ff;
27420 lo
= (value
>> 1) & 0x7ff;
27421 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27422 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27423 newval
|= (S
<< 10) | hi
;
27424 newval2
&= ~T2I1I2MASK
;
27425 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
27426 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27427 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27431 md_apply_fix (fixS
* fixP
,
27435 offsetT value
= * valP
;
27437 unsigned int newimm
;
27438 unsigned long temp
;
27440 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
27442 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
27444 /* Note whether this will delete the relocation. */
27446 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
27449 /* On a 64-bit host, silently truncate 'value' to 32 bits for
27450 consistency with the behaviour on 32-bit hosts. Remember value
27452 value
&= 0xffffffff;
27453 value
^= 0x80000000;
27454 value
-= 0x80000000;
27457 fixP
->fx_addnumber
= value
;
27459 /* Same treatment for fixP->fx_offset. */
27460 fixP
->fx_offset
&= 0xffffffff;
27461 fixP
->fx_offset
^= 0x80000000;
27462 fixP
->fx_offset
-= 0x80000000;
27464 switch (fixP
->fx_r_type
)
27466 case BFD_RELOC_NONE
:
27467 /* This will need to go in the object file. */
27471 case BFD_RELOC_ARM_IMMEDIATE
:
27472 /* We claim that this fixup has been processed here,
27473 even if in fact we generate an error because we do
27474 not have a reloc for it, so tc_gen_reloc will reject it. */
27477 if (fixP
->fx_addsy
)
27479 const char *msg
= 0;
27481 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27482 msg
= _("undefined symbol %s used as an immediate value");
27483 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27484 msg
= _("symbol %s is in a different section");
27485 else if (S_IS_WEAK (fixP
->fx_addsy
))
27486 msg
= _("symbol %s is weak and may be overridden later");
27490 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27491 msg
, S_GET_NAME (fixP
->fx_addsy
));
27496 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27498 /* If the offset is negative, we should use encoding A2 for ADR. */
27499 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
27500 newimm
= negate_data_op (&temp
, value
);
27503 newimm
= encode_arm_immediate (value
);
27505 /* If the instruction will fail, see if we can fix things up by
27506 changing the opcode. */
27507 if (newimm
== (unsigned int) FAIL
)
27508 newimm
= negate_data_op (&temp
, value
);
27509 /* MOV accepts both ARM modified immediate (A1 encoding) and
27510 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27511 When disassembling, MOV is preferred when there is no encoding
27513 if (newimm
== (unsigned int) FAIL
27514 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
27515 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
27516 && !((temp
>> SBIT_SHIFT
) & 0x1)
27517 && value
>= 0 && value
<= 0xffff)
27519 /* Clear bits[23:20] to change encoding from A1 to A2. */
27520 temp
&= 0xff0fffff;
27521 /* Encoding high 4bits imm. Code below will encode the remaining
27523 temp
|= (value
& 0x0000f000) << 4;
27524 newimm
= value
& 0x00000fff;
27528 if (newimm
== (unsigned int) FAIL
)
27530 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27531 _("invalid constant (%lx) after fixup"),
27532 (unsigned long) value
);
27536 newimm
|= (temp
& 0xfffff000);
27537 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27540 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27542 unsigned int highpart
= 0;
27543 unsigned int newinsn
= 0xe1a00000; /* nop. */
27545 if (fixP
->fx_addsy
)
27547 const char *msg
= 0;
27549 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27550 msg
= _("undefined symbol %s used as an immediate value");
27551 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27552 msg
= _("symbol %s is in a different section");
27553 else if (S_IS_WEAK (fixP
->fx_addsy
))
27554 msg
= _("symbol %s is weak and may be overridden later");
27558 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27559 msg
, S_GET_NAME (fixP
->fx_addsy
));
27564 newimm
= encode_arm_immediate (value
);
27565 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27567 /* If the instruction will fail, see if we can fix things up by
27568 changing the opcode. */
27569 if (newimm
== (unsigned int) FAIL
27570 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
27572 /* No ? OK - try using two ADD instructions to generate
27574 newimm
= validate_immediate_twopart (value
, & highpart
);
27576 /* Yes - then make sure that the second instruction is
27578 if (newimm
!= (unsigned int) FAIL
)
27580 /* Still No ? Try using a negated value. */
27581 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
27582 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
27583 /* Otherwise - give up. */
27586 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27587 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27592 /* Replace the first operand in the 2nd instruction (which
27593 is the PC) with the destination register. We have
27594 already added in the PC in the first instruction and we
27595 do not want to do it again. */
27596 newinsn
&= ~ 0xf0000;
27597 newinsn
|= ((newinsn
& 0x0f000) << 4);
27600 newimm
|= (temp
& 0xfffff000);
27601 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27603 highpart
|= (newinsn
& 0xfffff000);
27604 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27608 case BFD_RELOC_ARM_OFFSET_IMM
:
27609 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27611 /* Fall through. */
27613 case BFD_RELOC_ARM_LITERAL
:
27619 if (validate_offset_imm (value
, 0) == FAIL
)
27621 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27622 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27623 _("invalid literal constant: pool needs to be closer"));
27625 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27626 _("bad immediate value for offset (%ld)"),
27631 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27633 newval
&= 0xfffff000;
27636 newval
&= 0xff7ff000;
27637 newval
|= value
| (sign
? INDEX_UP
: 0);
27639 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27642 case BFD_RELOC_ARM_OFFSET_IMM8
:
27643 case BFD_RELOC_ARM_HWLITERAL
:
27649 if (validate_offset_imm (value
, 1) == FAIL
)
27651 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27652 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27653 _("invalid literal constant: pool needs to be closer"));
27655 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27656 _("bad immediate value for 8-bit offset (%ld)"),
27661 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27663 newval
&= 0xfffff0f0;
27666 newval
&= 0xff7ff0f0;
27667 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27669 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27672 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27673 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27674 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27675 _("bad immediate value for offset (%ld)"), (long) value
);
27678 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27680 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27683 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27684 /* This is a complicated relocation used for all varieties of Thumb32
27685 load/store instruction with immediate offset:
27687 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
27688 *4, optional writeback(W)
27689 (doubleword load/store)
27691 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27692 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27693 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27694 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27695 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27697 Uppercase letters indicate bits that are already encoded at
27698 this point. Lowercase letters are our problem. For the
27699 second block of instructions, the secondary opcode nybble
27700 (bits 8..11) is present, and bit 23 is zero, even if this is
27701 a PC-relative operation. */
27702 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27704 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
27706 if ((newval
& 0xf0000000) == 0xe0000000)
27708 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27710 newval
|= (1 << 23);
27713 if (value
% 4 != 0)
27715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27716 _("offset not a multiple of 4"));
27722 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27723 _("offset out of range"));
27728 else if ((newval
& 0x000f0000) == 0x000f0000)
27730 /* PC-relative, 12-bit offset. */
27732 newval
|= (1 << 23);
27737 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27738 _("offset out of range"));
27743 else if ((newval
& 0x00000100) == 0x00000100)
27745 /* Writeback: 8-bit, +/- offset. */
27747 newval
|= (1 << 9);
27752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27753 _("offset out of range"));
27758 else if ((newval
& 0x00000f00) == 0x00000e00)
27760 /* T-instruction: positive 8-bit offset. */
27761 if (value
< 0 || value
> 0xff)
27763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27764 _("offset out of range"));
27772 /* Positive 12-bit or negative 8-bit offset. */
27776 newval
|= (1 << 23);
27786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27787 _("offset out of range"));
27794 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
27795 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
27798 case BFD_RELOC_ARM_SHIFT_IMM
:
27799 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27800 if (((unsigned long) value
) > 32
27802 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
27804 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27805 _("shift expression is too large"));
27810 /* Shifts of zero must be done as lsl. */
27812 else if (value
== 32)
27814 newval
&= 0xfffff07f;
27815 newval
|= (value
& 0x1f) << 7;
27816 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27819 case BFD_RELOC_ARM_T32_IMMEDIATE
:
27820 case BFD_RELOC_ARM_T32_ADD_IMM
:
27821 case BFD_RELOC_ARM_T32_IMM12
:
27822 case BFD_RELOC_ARM_T32_ADD_PC12
:
27823 /* We claim that this fixup has been processed here,
27824 even if in fact we generate an error because we do
27825 not have a reloc for it, so tc_gen_reloc will reject it. */
27829 && ! S_IS_DEFINED (fixP
->fx_addsy
))
27831 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27832 _("undefined symbol %s used as an immediate value"),
27833 S_GET_NAME (fixP
->fx_addsy
));
27837 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27839 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
27842 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27843 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27844 Thumb2 modified immediate encoding (T2). */
27845 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
27846 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27848 newimm
= encode_thumb32_immediate (value
);
27849 if (newimm
== (unsigned int) FAIL
)
27850 newimm
= thumb32_negate_data_op (&newval
, value
);
27852 if (newimm
== (unsigned int) FAIL
)
27854 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
27856 /* Turn add/sum into addw/subw. */
27857 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27858 newval
= (newval
& 0xfeffffff) | 0x02000000;
27859 /* No flat 12-bit imm encoding for addsw/subsw. */
27860 if ((newval
& 0x00100000) == 0)
27862 /* 12 bit immediate for addw/subw. */
27866 newval
^= 0x00a00000;
27869 newimm
= (unsigned int) FAIL
;
27876 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27877 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27878 disassembling, MOV is preferred when there is no encoding
27880 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
27881 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27882 but with the Rn field [19:16] set to 1111. */
27883 && (((newval
>> 16) & 0xf) == 0xf)
27884 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
27885 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
27886 && value
>= 0 && value
<= 0xffff)
27888 /* Toggle bit[25] to change encoding from T2 to T3. */
27890 /* Clear bits[19:16]. */
27891 newval
&= 0xfff0ffff;
27892 /* Encoding high 4bits imm. Code below will encode the
27893 remaining low 12bits. */
27894 newval
|= (value
& 0x0000f000) << 4;
27895 newimm
= value
& 0x00000fff;
27900 if (newimm
== (unsigned int)FAIL
)
27902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27903 _("invalid constant (%lx) after fixup"),
27904 (unsigned long) value
);
27908 newval
|= (newimm
& 0x800) << 15;
27909 newval
|= (newimm
& 0x700) << 4;
27910 newval
|= (newimm
& 0x0ff);
27912 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
27913 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
27916 case BFD_RELOC_ARM_SMC
:
27917 if (((unsigned long) value
) > 0xf)
27918 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27919 _("invalid smc expression"));
27921 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27922 newval
|= (value
& 0xf);
27923 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27926 case BFD_RELOC_ARM_HVC
:
27927 if (((unsigned long) value
) > 0xffff)
27928 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27929 _("invalid hvc expression"));
27930 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27931 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27932 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27935 case BFD_RELOC_ARM_SWI
:
27936 if (fixP
->tc_fix_data
!= 0)
27938 if (((unsigned long) value
) > 0xff)
27939 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27940 _("invalid swi expression"));
27941 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27943 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27947 if (((unsigned long) value
) > 0x00ffffff)
27948 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27949 _("invalid swi expression"));
27950 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27952 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27956 case BFD_RELOC_ARM_MULTI
:
27957 if (((unsigned long) value
) > 0xffff)
27958 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27959 _("invalid expression in load/store multiple"));
27960 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
27961 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27965 case BFD_RELOC_ARM_PCREL_CALL
:
27967 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27969 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27970 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27971 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27972 /* Flip the bl to blx. This is a simple flip
27973 bit here because we generate PCREL_CALL for
27974 unconditional bls. */
27976 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27977 newval
= newval
| 0x10000000;
27978 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27984 goto arm_branch_common
;
27986 case BFD_RELOC_ARM_PCREL_JUMP
:
27987 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27989 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27990 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27991 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27993 /* This would map to a bl<cond>, b<cond>,
27994 b<always> to a Thumb function. We
27995 need to force a relocation for this particular
27997 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28000 /* Fall through. */
28002 case BFD_RELOC_ARM_PLT32
:
28004 case BFD_RELOC_ARM_PCREL_BRANCH
:
28006 goto arm_branch_common
;
28008 case BFD_RELOC_ARM_PCREL_BLX
:
28011 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28013 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28014 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28015 && ARM_IS_FUNC (fixP
->fx_addsy
))
28017 /* Flip the blx to a bl and warn. */
28018 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28019 newval
= 0xeb000000;
28020 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28021 _("blx to '%s' an ARM ISA state function changed to bl"),
28023 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28029 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28030 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
28034 /* We are going to store value (shifted right by two) in the
28035 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28036 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
28039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28040 _("misaligned branch destination"));
28041 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
28042 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
28043 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28045 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28047 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28048 newval
|= (value
>> 2) & 0x00ffffff;
28049 /* Set the H bit on BLX instructions. */
28053 newval
|= 0x01000000;
28055 newval
&= ~0x01000000;
28057 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28061 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28062 /* CBZ can only branch forward. */
28064 /* Attempts to use CBZ to branch to the next instruction
28065 (which, strictly speaking, are prohibited) will be turned into
28068 FIXME: It may be better to remove the instruction completely and
28069 perform relaxation. */
28072 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28073 newval
= 0xbf00; /* NOP encoding T1 */
28074 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28079 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28081 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28083 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28084 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28085 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28090 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28091 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
28092 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28094 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28096 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28097 newval
|= (value
& 0x1ff) >> 1;
28098 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28102 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28103 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
28104 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28106 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28108 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28109 newval
|= (value
& 0xfff) >> 1;
28110 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28114 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28116 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28117 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28118 && ARM_IS_FUNC (fixP
->fx_addsy
)
28119 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28121 /* Force a relocation for a branch 20 bits wide. */
28124 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
28125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28126 _("conditional branch out of range"));
28128 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28131 addressT S
, J1
, J2
, lo
, hi
;
28133 S
= (value
& 0x00100000) >> 20;
28134 J2
= (value
& 0x00080000) >> 19;
28135 J1
= (value
& 0x00040000) >> 18;
28136 hi
= (value
& 0x0003f000) >> 12;
28137 lo
= (value
& 0x00000ffe) >> 1;
28139 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28140 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28141 newval
|= (S
<< 10) | hi
;
28142 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
28143 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28144 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28148 case BFD_RELOC_THUMB_PCREL_BLX
:
28149 /* If there is a blx from a thumb state function to
28150 another thumb function flip this to a bl and warn
28154 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28155 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28156 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28158 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28159 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28160 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
28162 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28163 newval
= newval
| 0x1000;
28164 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28165 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28170 goto thumb_bl_common
;
28172 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28173 /* A bl from Thumb state ISA to an internal ARM state function
28174 is converted to a blx. */
28176 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28177 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28178 && ARM_IS_FUNC (fixP
->fx_addsy
)
28179 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28181 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28182 newval
= newval
& ~0x1000;
28183 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28184 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
28190 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28191 /* For a BLX instruction, make sure that the relocation is rounded up
28192 to a word boundary. This follows the semantics of the instruction
28193 which specifies that bit 1 of the target address will come from bit
28194 1 of the base address. */
28195 value
= (value
+ 3) & ~ 3;
28198 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
28199 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28200 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28203 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
28205 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
28206 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28207 else if ((value
& ~0x1ffffff)
28208 && ((value
& ~0x1ffffff) != ~0x1ffffff))
28209 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28210 _("Thumb2 branch out of range"));
28213 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28214 encode_thumb2_b_bl_offset (buf
, value
);
28218 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28219 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
28220 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28222 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28223 encode_thumb2_b_bl_offset (buf
, value
);
28228 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28233 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28234 md_number_to_chars (buf
, value
, 2);
28238 case BFD_RELOC_ARM_TLS_CALL
:
28239 case BFD_RELOC_ARM_THM_TLS_CALL
:
28240 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28241 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28242 case BFD_RELOC_ARM_TLS_GOTDESC
:
28243 case BFD_RELOC_ARM_TLS_GD32
:
28244 case BFD_RELOC_ARM_TLS_LE32
:
28245 case BFD_RELOC_ARM_TLS_IE32
:
28246 case BFD_RELOC_ARM_TLS_LDM32
:
28247 case BFD_RELOC_ARM_TLS_LDO32
:
28248 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28251 /* Same handling as above, but with the arm_fdpic guard. */
28252 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28253 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28254 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28257 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28262 _("Relocation supported only in FDPIC mode"));
28266 case BFD_RELOC_ARM_GOT32
:
28267 case BFD_RELOC_ARM_GOTOFF
:
28270 case BFD_RELOC_ARM_GOT_PREL
:
28271 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28272 md_number_to_chars (buf
, value
, 4);
28275 case BFD_RELOC_ARM_TARGET2
:
28276 /* TARGET2 is not partial-inplace, so we need to write the
28277 addend here for REL targets, because it won't be written out
28278 during reloc processing later. */
28279 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28280 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
28283 /* Relocations for FDPIC. */
28284 case BFD_RELOC_ARM_GOTFUNCDESC
:
28285 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28286 case BFD_RELOC_ARM_FUNCDESC
:
28289 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28290 md_number_to_chars (buf
, 0, 4);
28294 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28295 _("Relocation supported only in FDPIC mode"));
28300 case BFD_RELOC_RVA
:
28302 case BFD_RELOC_ARM_TARGET1
:
28303 case BFD_RELOC_ARM_ROSEGREL32
:
28304 case BFD_RELOC_ARM_SBREL32
:
28305 case BFD_RELOC_32_PCREL
:
28307 case BFD_RELOC_32_SECREL
:
28309 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28311 /* For WinCE we only do this for pcrel fixups. */
28312 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
28314 md_number_to_chars (buf
, value
, 4);
28318 case BFD_RELOC_ARM_PREL31
:
28319 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28321 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
28322 if ((value
^ (value
>> 1)) & 0x40000000)
28324 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28325 _("rel31 relocation overflow"));
28327 newval
|= value
& 0x7fffffff;
28328 md_number_to_chars (buf
, newval
, 4);
28333 case BFD_RELOC_ARM_CP_OFF_IMM
:
28334 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
28335 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
28336 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
28337 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28339 newval
= get_thumb32_insn (buf
);
28340 if ((newval
& 0x0f200f00) == 0x0d000900)
28342 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
28343 has permitted values that are multiples of 2, in the range 0
28345 if (value
< -510 || value
> 510 || (value
& 1))
28346 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28347 _("co-processor offset out of range"));
28349 else if ((newval
& 0xfe001f80) == 0xec000f80)
28351 if (value
< -511 || value
> 512 || (value
& 3))
28352 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28353 _("co-processor offset out of range"));
28355 else if (value
< -1023 || value
> 1023 || (value
& 3))
28356 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28357 _("co-processor offset out of range"));
28362 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28363 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28364 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28366 newval
= get_thumb32_insn (buf
);
28369 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28370 newval
&= 0xffffff80;
28372 newval
&= 0xffffff00;
28376 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28377 newval
&= 0xff7fff80;
28379 newval
&= 0xff7fff00;
28380 if ((newval
& 0x0f200f00) == 0x0d000900)
28382 /* This is a fp16 vstr/vldr.
28384 It requires the immediate offset in the instruction is shifted
28385 left by 1 to be a half-word offset.
28387 Here, left shift by 1 first, and later right shift by 2
28388 should get the right offset. */
28391 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
28393 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28394 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28395 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28397 put_thumb32_insn (buf
, newval
);
28400 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
28401 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
28402 if (value
< -255 || value
> 255)
28403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28404 _("co-processor offset out of range"));
28406 goto cp_off_common
;
28408 case BFD_RELOC_ARM_THUMB_OFFSET
:
28409 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28410 /* Exactly what ranges, and where the offset is inserted depends
28411 on the type of instruction, we can establish this from the
28413 switch (newval
>> 12)
28415 case 4: /* PC load. */
28416 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28417 forced to zero for these loads; md_pcrel_from has already
28418 compensated for this. */
28420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28421 _("invalid offset, target not word aligned (0x%08lX)"),
28422 (((unsigned long) fixP
->fx_frag
->fr_address
28423 + (unsigned long) fixP
->fx_where
) & ~3)
28424 + (unsigned long) value
);
28426 if (value
& ~0x3fc)
28427 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28428 _("invalid offset, value too big (0x%08lX)"),
28431 newval
|= value
>> 2;
28434 case 9: /* SP load/store. */
28435 if (value
& ~0x3fc)
28436 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28437 _("invalid offset, value too big (0x%08lX)"),
28439 newval
|= value
>> 2;
28442 case 6: /* Word load/store. */
28444 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28445 _("invalid offset, value too big (0x%08lX)"),
28447 newval
|= value
<< 4; /* 6 - 2. */
28450 case 7: /* Byte load/store. */
28452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28453 _("invalid offset, value too big (0x%08lX)"),
28455 newval
|= value
<< 6;
28458 case 8: /* Halfword load/store. */
28460 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28461 _("invalid offset, value too big (0x%08lX)"),
28463 newval
|= value
<< 5; /* 6 - 1. */
28467 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28468 "Unable to process relocation for thumb opcode: %lx",
28469 (unsigned long) newval
);
28472 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28475 case BFD_RELOC_ARM_THUMB_ADD
:
28476 /* This is a complicated relocation, since we use it for all of
28477 the following immediate relocations:
28481 9bit ADD/SUB SP word-aligned
28482 10bit ADD PC/SP word-aligned
28484 The type of instruction being processed is encoded in the
28491 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28493 int rd
= (newval
>> 4) & 0xf;
28494 int rs
= newval
& 0xf;
28495 int subtract
= !!(newval
& 0x8000);
28497 /* Check for HI regs, only very restricted cases allowed:
28498 Adjusting SP, and using PC or SP to get an address. */
28499 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
28500 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
28501 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28502 _("invalid Hi register with immediate"));
28504 /* If value is negative, choose the opposite instruction. */
28508 subtract
= !subtract
;
28510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28511 _("immediate value out of range"));
28516 if (value
& ~0x1fc)
28517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28518 _("invalid immediate for stack address calculation"));
28519 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
28520 newval
|= value
>> 2;
28522 else if (rs
== REG_PC
|| rs
== REG_SP
)
28524 /* PR gas/18541. If the addition is for a defined symbol
28525 within range of an ADR instruction then accept it. */
28528 && fixP
->fx_addsy
!= NULL
)
28532 if (! S_IS_DEFINED (fixP
->fx_addsy
)
28533 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
28534 || S_IS_WEAK (fixP
->fx_addsy
))
28536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28537 _("address calculation needs a strongly defined nearby symbol"));
28541 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
28543 /* Round up to the next 4-byte boundary. */
28548 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
28552 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28553 _("symbol too far away"));
28563 if (subtract
|| value
& ~0x3fc)
28564 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28565 _("invalid immediate for address calculation (value = 0x%08lX)"),
28566 (unsigned long) (subtract
? - value
: value
));
28567 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
28569 newval
|= value
>> 2;
28574 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28575 _("immediate value out of range"));
28576 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
28577 newval
|= (rd
<< 8) | value
;
28582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28583 _("immediate value out of range"));
28584 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
28585 newval
|= rd
| (rs
<< 3) | (value
<< 6);
28588 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28591 case BFD_RELOC_ARM_THUMB_IMM
:
28592 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28593 if (value
< 0 || value
> 255)
28594 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28595 _("invalid immediate: %ld is out of range"),
28598 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28601 case BFD_RELOC_ARM_THUMB_SHIFT
:
28602 /* 5bit shift value (0..32). LSL cannot take 32. */
28603 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28604 temp
= newval
& 0xf800;
28605 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28606 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28607 _("invalid shift value: %ld"), (long) value
);
28608 /* Shifts of zero must be encoded as LSL. */
28610 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28611 /* Shifts of 32 are encoded as zero. */
28612 else if (value
== 32)
28614 newval
|= value
<< 6;
28615 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28618 case BFD_RELOC_VTABLE_INHERIT
:
28619 case BFD_RELOC_VTABLE_ENTRY
:
28623 case BFD_RELOC_ARM_MOVW
:
28624 case BFD_RELOC_ARM_MOVT
:
28625 case BFD_RELOC_ARM_THUMB_MOVW
:
28626 case BFD_RELOC_ARM_THUMB_MOVT
:
28627 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28629 /* REL format relocations are limited to a 16-bit addend. */
28630 if (!fixP
->fx_done
)
28632 if (value
< -0x8000 || value
> 0x7fff)
28633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28634 _("offset out of range"));
28636 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28637 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28642 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28643 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28645 newval
= get_thumb32_insn (buf
);
28646 newval
&= 0xfbf08f00;
28647 newval
|= (value
& 0xf000) << 4;
28648 newval
|= (value
& 0x0800) << 15;
28649 newval
|= (value
& 0x0700) << 4;
28650 newval
|= (value
& 0x00ff);
28651 put_thumb32_insn (buf
, newval
);
28655 newval
= md_chars_to_number (buf
, 4);
28656 newval
&= 0xfff0f000;
28657 newval
|= value
& 0x0fff;
28658 newval
|= (value
& 0xf000) << 4;
28659 md_number_to_chars (buf
, newval
, 4);
28664 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28665 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28666 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28667 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28668 gas_assert (!fixP
->fx_done
);
28671 bfd_boolean is_mov
;
28672 bfd_vma encoded_addend
= value
;
28674 /* Check that addend can be encoded in instruction. */
28675 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28676 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28677 _("the offset 0x%08lX is not representable"),
28678 (unsigned long) encoded_addend
);
28680 /* Extract the instruction. */
28681 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28682 is_mov
= (insn
& 0xf800) == 0x2000;
28687 if (!seg
->use_rela_p
)
28688 insn
|= encoded_addend
;
28694 /* Extract the instruction. */
28695 /* Encoding is the following
28700 /* The following conditions must be true :
28705 rd
= (insn
>> 4) & 0xf;
28707 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
28708 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28709 _("Unable to process relocation for thumb opcode: %lx"),
28710 (unsigned long) insn
);
28712 /* Encode as ADD immediate8 thumb 1 code. */
28713 insn
= 0x3000 | (rd
<< 8);
28715 /* Place the encoded addend into the first 8 bits of the
28717 if (!seg
->use_rela_p
)
28718 insn
|= encoded_addend
;
28721 /* Update the instruction. */
28722 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
28726 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28727 case BFD_RELOC_ARM_ALU_PC_G0
:
28728 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28729 case BFD_RELOC_ARM_ALU_PC_G1
:
28730 case BFD_RELOC_ARM_ALU_PC_G2
:
28731 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28732 case BFD_RELOC_ARM_ALU_SB_G0
:
28733 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28734 case BFD_RELOC_ARM_ALU_SB_G1
:
28735 case BFD_RELOC_ARM_ALU_SB_G2
:
28736 gas_assert (!fixP
->fx_done
);
28737 if (!seg
->use_rela_p
)
28740 bfd_vma encoded_addend
;
28741 bfd_vma addend_abs
= llabs (value
);
28743 /* Check that the absolute value of the addend can be
28744 expressed as an 8-bit constant plus a rotation. */
28745 encoded_addend
= encode_arm_immediate (addend_abs
);
28746 if (encoded_addend
== (unsigned int) FAIL
)
28747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28748 _("the offset 0x%08lX is not representable"),
28749 (unsigned long) addend_abs
);
28751 /* Extract the instruction. */
28752 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28754 /* If the addend is positive, use an ADD instruction.
28755 Otherwise use a SUB. Take care not to destroy the S bit. */
28756 insn
&= 0xff1fffff;
28762 /* Place the encoded addend into the first 12 bits of the
28764 insn
&= 0xfffff000;
28765 insn
|= encoded_addend
;
28767 /* Update the instruction. */
28768 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28772 case BFD_RELOC_ARM_LDR_PC_G0
:
28773 case BFD_RELOC_ARM_LDR_PC_G1
:
28774 case BFD_RELOC_ARM_LDR_PC_G2
:
28775 case BFD_RELOC_ARM_LDR_SB_G0
:
28776 case BFD_RELOC_ARM_LDR_SB_G1
:
28777 case BFD_RELOC_ARM_LDR_SB_G2
:
28778 gas_assert (!fixP
->fx_done
);
28779 if (!seg
->use_rela_p
)
28782 bfd_vma addend_abs
= llabs (value
);
28784 /* Check that the absolute value of the addend can be
28785 encoded in 12 bits. */
28786 if (addend_abs
>= 0x1000)
28787 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28788 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28789 (unsigned long) addend_abs
);
28791 /* Extract the instruction. */
28792 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28794 /* If the addend is negative, clear bit 23 of the instruction.
28795 Otherwise set it. */
28797 insn
&= ~(1 << 23);
28801 /* Place the absolute value of the addend into the first 12 bits
28802 of the instruction. */
28803 insn
&= 0xfffff000;
28804 insn
|= addend_abs
;
28806 /* Update the instruction. */
28807 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28811 case BFD_RELOC_ARM_LDRS_PC_G0
:
28812 case BFD_RELOC_ARM_LDRS_PC_G1
:
28813 case BFD_RELOC_ARM_LDRS_PC_G2
:
28814 case BFD_RELOC_ARM_LDRS_SB_G0
:
28815 case BFD_RELOC_ARM_LDRS_SB_G1
:
28816 case BFD_RELOC_ARM_LDRS_SB_G2
:
28817 gas_assert (!fixP
->fx_done
);
28818 if (!seg
->use_rela_p
)
28821 bfd_vma addend_abs
= llabs (value
);
28823 /* Check that the absolute value of the addend can be
28824 encoded in 8 bits. */
28825 if (addend_abs
>= 0x100)
28826 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28827 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28828 (unsigned long) addend_abs
);
28830 /* Extract the instruction. */
28831 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28833 /* If the addend is negative, clear bit 23 of the instruction.
28834 Otherwise set it. */
28836 insn
&= ~(1 << 23);
28840 /* Place the first four bits of the absolute value of the addend
28841 into the first 4 bits of the instruction, and the remaining
28842 four into bits 8 .. 11. */
28843 insn
&= 0xfffff0f0;
28844 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
28846 /* Update the instruction. */
28847 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28851 case BFD_RELOC_ARM_LDC_PC_G0
:
28852 case BFD_RELOC_ARM_LDC_PC_G1
:
28853 case BFD_RELOC_ARM_LDC_PC_G2
:
28854 case BFD_RELOC_ARM_LDC_SB_G0
:
28855 case BFD_RELOC_ARM_LDC_SB_G1
:
28856 case BFD_RELOC_ARM_LDC_SB_G2
:
28857 gas_assert (!fixP
->fx_done
);
28858 if (!seg
->use_rela_p
)
28861 bfd_vma addend_abs
= llabs (value
);
28863 /* Check that the absolute value of the addend is a multiple of
28864 four and, when divided by four, fits in 8 bits. */
28865 if (addend_abs
& 0x3)
28866 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28867 _("bad offset 0x%08lX (must be word-aligned)"),
28868 (unsigned long) addend_abs
);
28870 if ((addend_abs
>> 2) > 0xff)
28871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28872 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28873 (unsigned long) addend_abs
);
28875 /* Extract the instruction. */
28876 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28878 /* If the addend is negative, clear bit 23 of the instruction.
28879 Otherwise set it. */
28881 insn
&= ~(1 << 23);
28885 /* Place the addend (divided by four) into the first eight
28886 bits of the instruction. */
28887 insn
&= 0xfffffff0;
28888 insn
|= addend_abs
>> 2;
28890 /* Update the instruction. */
28891 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28895 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28897 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28898 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28899 && ARM_IS_FUNC (fixP
->fx_addsy
)
28900 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28902 /* Force a relocation for a branch 5 bits wide. */
28905 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
28906 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28909 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28911 addressT boff
= value
>> 1;
28913 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28914 newval
|= (boff
<< 7);
28915 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28919 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28921 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28922 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28923 && ARM_IS_FUNC (fixP
->fx_addsy
)
28924 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28928 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
28929 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28930 _("branch out of range"));
28932 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28934 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28936 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
28937 addressT diff
= value
- boff
;
28941 newval
|= 1 << 1; /* T bit. */
28943 else if (diff
!= 2)
28945 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28946 _("out of range label-relative fixup value"));
28948 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28952 case BFD_RELOC_ARM_THUMB_BF17
:
28954 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28955 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28956 && ARM_IS_FUNC (fixP
->fx_addsy
)
28957 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28959 /* Force a relocation for a branch 17 bits wide. */
28963 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
28964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28967 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28970 addressT immA
, immB
, immC
;
28972 immA
= (value
& 0x0001f000) >> 12;
28973 immB
= (value
& 0x00000ffc) >> 2;
28974 immC
= (value
& 0x00000002) >> 1;
28976 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28977 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28979 newval2
|= (immC
<< 11) | (immB
<< 1);
28980 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28981 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28985 case BFD_RELOC_ARM_THUMB_BF19
:
28987 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28988 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28989 && ARM_IS_FUNC (fixP
->fx_addsy
)
28990 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28992 /* Force a relocation for a branch 19 bits wide. */
28996 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
28997 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29000 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29003 addressT immA
, immB
, immC
;
29005 immA
= (value
& 0x0007f000) >> 12;
29006 immB
= (value
& 0x00000ffc) >> 2;
29007 immC
= (value
& 0x00000002) >> 1;
29009 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29010 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29012 newval2
|= (immC
<< 11) | (immB
<< 1);
29013 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29014 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29018 case BFD_RELOC_ARM_THUMB_BF13
:
29020 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29021 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29022 && ARM_IS_FUNC (fixP
->fx_addsy
)
29023 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29025 /* Force a relocation for a branch 13 bits wide. */
29029 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
29030 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29033 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29036 addressT immA
, immB
, immC
;
29038 immA
= (value
& 0x00001000) >> 12;
29039 immB
= (value
& 0x00000ffc) >> 2;
29040 immC
= (value
& 0x00000002) >> 1;
29042 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29043 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29045 newval2
|= (immC
<< 11) | (immB
<< 1);
29046 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29047 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29051 case BFD_RELOC_ARM_THUMB_LOOP12
:
29053 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29054 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29055 && ARM_IS_FUNC (fixP
->fx_addsy
)
29056 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29058 /* Force a relocation for a branch 12 bits wide. */
29062 bfd_vma insn
= get_thumb32_insn (buf
);
29063 /* le lr, <label>, le <label> or letp lr, <label> */
29064 if (((insn
& 0xffffffff) == 0xf00fc001)
29065 || ((insn
& 0xffffffff) == 0xf02fc001)
29066 || ((insn
& 0xffffffff) == 0xf01fc001))
29069 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
29070 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29072 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29074 addressT imml
, immh
;
29076 immh
= (value
& 0x00000ffc) >> 2;
29077 imml
= (value
& 0x00000002) >> 1;
29079 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29080 newval
|= (imml
<< 11) | (immh
<< 1);
29081 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29085 case BFD_RELOC_ARM_V4BX
:
29086 /* This will need to go in the object file. */
29090 case BFD_RELOC_UNUSED
:
29092 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29093 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29097 /* Translate internal representation of relocation info to BFD target
29101 tc_gen_reloc (asection
*section
, fixS
*fixp
)
29104 bfd_reloc_code_real_type code
;
29106 reloc
= XNEW (arelent
);
29108 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
29109 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
29110 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
29112 if (fixp
->fx_pcrel
)
29114 if (section
->use_rela_p
)
29115 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
29117 fixp
->fx_offset
= reloc
->address
;
29119 reloc
->addend
= fixp
->fx_offset
;
29121 switch (fixp
->fx_r_type
)
29124 if (fixp
->fx_pcrel
)
29126 code
= BFD_RELOC_8_PCREL
;
29129 /* Fall through. */
29132 if (fixp
->fx_pcrel
)
29134 code
= BFD_RELOC_16_PCREL
;
29137 /* Fall through. */
29140 if (fixp
->fx_pcrel
)
29142 code
= BFD_RELOC_32_PCREL
;
29145 /* Fall through. */
29147 case BFD_RELOC_ARM_MOVW
:
29148 if (fixp
->fx_pcrel
)
29150 code
= BFD_RELOC_ARM_MOVW_PCREL
;
29153 /* Fall through. */
29155 case BFD_RELOC_ARM_MOVT
:
29156 if (fixp
->fx_pcrel
)
29158 code
= BFD_RELOC_ARM_MOVT_PCREL
;
29161 /* Fall through. */
29163 case BFD_RELOC_ARM_THUMB_MOVW
:
29164 if (fixp
->fx_pcrel
)
29166 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
29169 /* Fall through. */
29171 case BFD_RELOC_ARM_THUMB_MOVT
:
29172 if (fixp
->fx_pcrel
)
29174 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
29177 /* Fall through. */
29179 case BFD_RELOC_NONE
:
29180 case BFD_RELOC_ARM_PCREL_BRANCH
:
29181 case BFD_RELOC_ARM_PCREL_BLX
:
29182 case BFD_RELOC_RVA
:
29183 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
29184 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
29185 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
29186 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29187 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29188 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29189 case BFD_RELOC_VTABLE_ENTRY
:
29190 case BFD_RELOC_VTABLE_INHERIT
:
29192 case BFD_RELOC_32_SECREL
:
29194 code
= fixp
->fx_r_type
;
29197 case BFD_RELOC_THUMB_PCREL_BLX
:
29199 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
29200 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29203 code
= BFD_RELOC_THUMB_PCREL_BLX
;
29206 case BFD_RELOC_ARM_LITERAL
:
29207 case BFD_RELOC_ARM_HWLITERAL
:
29208 /* If this is called then the a literal has
29209 been referenced across a section boundary. */
29210 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29211 _("literal referenced across section boundary"));
29215 case BFD_RELOC_ARM_TLS_CALL
:
29216 case BFD_RELOC_ARM_THM_TLS_CALL
:
29217 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29218 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29219 case BFD_RELOC_ARM_GOT32
:
29220 case BFD_RELOC_ARM_GOTOFF
:
29221 case BFD_RELOC_ARM_GOT_PREL
:
29222 case BFD_RELOC_ARM_PLT32
:
29223 case BFD_RELOC_ARM_TARGET1
:
29224 case BFD_RELOC_ARM_ROSEGREL32
:
29225 case BFD_RELOC_ARM_SBREL32
:
29226 case BFD_RELOC_ARM_PREL31
:
29227 case BFD_RELOC_ARM_TARGET2
:
29228 case BFD_RELOC_ARM_TLS_LDO32
:
29229 case BFD_RELOC_ARM_PCREL_CALL
:
29230 case BFD_RELOC_ARM_PCREL_JUMP
:
29231 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29232 case BFD_RELOC_ARM_ALU_PC_G0
:
29233 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29234 case BFD_RELOC_ARM_ALU_PC_G1
:
29235 case BFD_RELOC_ARM_ALU_PC_G2
:
29236 case BFD_RELOC_ARM_LDR_PC_G0
:
29237 case BFD_RELOC_ARM_LDR_PC_G1
:
29238 case BFD_RELOC_ARM_LDR_PC_G2
:
29239 case BFD_RELOC_ARM_LDRS_PC_G0
:
29240 case BFD_RELOC_ARM_LDRS_PC_G1
:
29241 case BFD_RELOC_ARM_LDRS_PC_G2
:
29242 case BFD_RELOC_ARM_LDC_PC_G0
:
29243 case BFD_RELOC_ARM_LDC_PC_G1
:
29244 case BFD_RELOC_ARM_LDC_PC_G2
:
29245 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29246 case BFD_RELOC_ARM_ALU_SB_G0
:
29247 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29248 case BFD_RELOC_ARM_ALU_SB_G1
:
29249 case BFD_RELOC_ARM_ALU_SB_G2
:
29250 case BFD_RELOC_ARM_LDR_SB_G0
:
29251 case BFD_RELOC_ARM_LDR_SB_G1
:
29252 case BFD_RELOC_ARM_LDR_SB_G2
:
29253 case BFD_RELOC_ARM_LDRS_SB_G0
:
29254 case BFD_RELOC_ARM_LDRS_SB_G1
:
29255 case BFD_RELOC_ARM_LDRS_SB_G2
:
29256 case BFD_RELOC_ARM_LDC_SB_G0
:
29257 case BFD_RELOC_ARM_LDC_SB_G1
:
29258 case BFD_RELOC_ARM_LDC_SB_G2
:
29259 case BFD_RELOC_ARM_V4BX
:
29260 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29261 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29262 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29263 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29264 case BFD_RELOC_ARM_GOTFUNCDESC
:
29265 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29266 case BFD_RELOC_ARM_FUNCDESC
:
29267 case BFD_RELOC_ARM_THUMB_BF17
:
29268 case BFD_RELOC_ARM_THUMB_BF19
:
29269 case BFD_RELOC_ARM_THUMB_BF13
:
29270 code
= fixp
->fx_r_type
;
29273 case BFD_RELOC_ARM_TLS_GOTDESC
:
29274 case BFD_RELOC_ARM_TLS_GD32
:
29275 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29276 case BFD_RELOC_ARM_TLS_LE32
:
29277 case BFD_RELOC_ARM_TLS_IE32
:
29278 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29279 case BFD_RELOC_ARM_TLS_LDM32
:
29280 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29281 /* BFD will include the symbol's address in the addend.
29282 But we don't want that, so subtract it out again here. */
29283 if (!S_IS_COMMON (fixp
->fx_addsy
))
29284 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
29285 code
= fixp
->fx_r_type
;
29289 case BFD_RELOC_ARM_IMMEDIATE
:
29290 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29291 _("internal relocation (type: IMMEDIATE) not fixed up"));
29294 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
29295 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29296 _("ADRL used for a symbol not defined in the same file"));
29299 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29300 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29301 case BFD_RELOC_ARM_THUMB_LOOP12
:
29302 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29303 _("%s used for a symbol not defined in the same file"),
29304 bfd_get_reloc_code_name (fixp
->fx_r_type
));
29307 case BFD_RELOC_ARM_OFFSET_IMM
:
29308 if (section
->use_rela_p
)
29310 code
= fixp
->fx_r_type
;
29314 if (fixp
->fx_addsy
!= NULL
29315 && !S_IS_DEFINED (fixp
->fx_addsy
)
29316 && S_IS_LOCAL (fixp
->fx_addsy
))
29318 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29319 _("undefined local label `%s'"),
29320 S_GET_NAME (fixp
->fx_addsy
));
29324 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29325 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
29332 switch (fixp
->fx_r_type
)
29334 case BFD_RELOC_NONE
: type
= "NONE"; break;
29335 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
29336 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
29337 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
29338 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
29339 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
29340 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
29341 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
29342 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
29343 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
29344 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
29345 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
29346 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
29347 default: type
= _("<unknown>"); break;
29349 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29350 _("cannot represent %s relocation in this object file format"),
29357 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
29359 && fixp
->fx_addsy
== GOT_symbol
)
29361 code
= BFD_RELOC_ARM_GOTPC
;
29362 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
29366 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
29368 if (reloc
->howto
== NULL
)
29370 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29371 _("cannot represent %s relocation in this object file format"),
29372 bfd_get_reloc_code_name (code
));
29376 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29377 vtable entry to be used in the relocation's section offset. */
29378 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29379 reloc
->address
= fixp
->fx_offset
;
29384 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
29387 cons_fix_new_arm (fragS
* frag
,
29391 bfd_reloc_code_real_type reloc
)
29396 FIXME: @@ Should look at CPU word size. */
29400 reloc
= BFD_RELOC_8
;
29403 reloc
= BFD_RELOC_16
;
29407 reloc
= BFD_RELOC_32
;
29410 reloc
= BFD_RELOC_64
;
29415 if (exp
->X_op
== O_secrel
)
29417 exp
->X_op
= O_symbol
;
29418 reloc
= BFD_RELOC_32_SECREL
;
29422 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
29425 #if defined (OBJ_COFF)
29427 arm_validate_fix (fixS
* fixP
)
29429 /* If the destination of the branch is a defined symbol which does not have
29430 the THUMB_FUNC attribute, then we must be calling a function which has
29431 the (interfacearm) attribute. We look for the Thumb entry point to that
29432 function and change the branch to refer to that function instead. */
29433 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
29434 && fixP
->fx_addsy
!= NULL
29435 && S_IS_DEFINED (fixP
->fx_addsy
)
29436 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
29438 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
29445 arm_force_relocation (struct fix
* fixp
)
29447 #if defined (OBJ_COFF) && defined (TE_PE)
29448 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
29452 /* In case we have a call or a branch to a function in ARM ISA mode from
29453 a thumb function or vice-versa force the relocation. These relocations
29454 are cleared off for some cores that might have blx and simple transformations
29458 switch (fixp
->fx_r_type
)
29460 case BFD_RELOC_ARM_PCREL_JUMP
:
29461 case BFD_RELOC_ARM_PCREL_CALL
:
29462 case BFD_RELOC_THUMB_PCREL_BLX
:
29463 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
29467 case BFD_RELOC_ARM_PCREL_BLX
:
29468 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29469 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29470 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29471 if (ARM_IS_FUNC (fixp
->fx_addsy
))
29480 /* Resolve these relocations even if the symbol is extern or weak.
29481 Technically this is probably wrong due to symbol preemption.
29482 In practice these relocations do not have enough range to be useful
29483 at dynamic link time, and some code (e.g. in the Linux kernel)
29484 expects these references to be resolved. */
29485 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
29486 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
29487 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
29488 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
29489 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29490 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
29491 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
29492 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
29493 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
29494 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
29495 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
29496 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
29497 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
29498 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
29501 /* Always leave these relocations for the linker. */
29502 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29503 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29504 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29507 /* Always generate relocations against function symbols. */
29508 if (fixp
->fx_r_type
== BFD_RELOC_32
29510 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
29513 return generic_force_reloc (fixp
);
29516 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29517 /* Relocations against function names must be left unadjusted,
29518 so that the linker can use this information to generate interworking
29519 stubs. The MIPS version of this function
29520 also prevents relocations that are mips-16 specific, but I do not
29521 know why it does this.
29524 There is one other problem that ought to be addressed here, but
29525 which currently is not: Taking the address of a label (rather
29526 than a function) and then later jumping to that address. Such
29527 addresses also ought to have their bottom bit set (assuming that
29528 they reside in Thumb code), but at the moment they will not. */
29531 arm_fix_adjustable (fixS
* fixP
)
29533 if (fixP
->fx_addsy
== NULL
)
29536 /* Preserve relocations against symbols with function type. */
29537 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
29540 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
29541 && fixP
->fx_subsy
== NULL
)
29544 /* We need the symbol name for the VTABLE entries. */
29545 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
29546 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29549 /* Don't allow symbols to be discarded on GOT related relocs. */
29550 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
29551 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
29552 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
29553 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
29554 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
29555 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
29556 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
29557 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
29558 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
29559 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
29560 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
29561 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
29562 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
29563 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
29564 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
29565 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
29566 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
29569 /* Similarly for group relocations. */
29570 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29571 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29572 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29575 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29576 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
29577 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29578 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
29579 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
29580 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29581 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
29582 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
29583 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
29586 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29587 offsets, so keep these symbols. */
29588 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29589 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29594 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29598 elf32_arm_target_format (void)
29601 return (target_big_endian
29602 ? "elf32-bigarm-symbian"
29603 : "elf32-littlearm-symbian");
29604 #elif defined (TE_VXWORKS)
29605 return (target_big_endian
29606 ? "elf32-bigarm-vxworks"
29607 : "elf32-littlearm-vxworks");
29608 #elif defined (TE_NACL)
29609 return (target_big_endian
29610 ? "elf32-bigarm-nacl"
29611 : "elf32-littlearm-nacl");
29615 if (target_big_endian
)
29616 return "elf32-bigarm-fdpic";
29618 return "elf32-littlearm-fdpic";
29622 if (target_big_endian
)
29623 return "elf32-bigarm";
29625 return "elf32-littlearm";
29631 armelf_frob_symbol (symbolS
* symp
,
29634 elf_frob_symbol (symp
, puntp
);
29638 /* MD interface: Finalization. */
29643 literal_pool
* pool
;
29645 /* Ensure that all the predication blocks are properly closed. */
29646 check_pred_blocks_finished ();
29648 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29650 /* Put it at the end of the relevant section. */
29651 subseg_set (pool
->section
, pool
->sub_section
);
29653 arm_elf_change_section ();
29660 /* Remove any excess mapping symbols generated for alignment frags in
29661 SEC. We may have created a mapping symbol before a zero byte
29662 alignment; remove it if there's a mapping symbol after the
29665 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29666 void *dummy ATTRIBUTE_UNUSED
)
29668 segment_info_type
*seginfo
= seg_info (sec
);
29671 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29674 for (fragp
= seginfo
->frchainP
->frch_root
;
29676 fragp
= fragp
->fr_next
)
29678 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29679 fragS
*next
= fragp
->fr_next
;
29681 /* Variable-sized frags have been converted to fixed size by
29682 this point. But if this was variable-sized to start with,
29683 there will be a fixed-size frag after it. So don't handle
29685 if (sym
== NULL
|| next
== NULL
)
29688 if (S_GET_VALUE (sym
) < next
->fr_address
)
29689 /* Not at the end of this frag. */
29691 know (S_GET_VALUE (sym
) == next
->fr_address
);
29695 if (next
->tc_frag_data
.first_map
!= NULL
)
29697 /* Next frag starts with a mapping symbol. Discard this
29699 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29703 if (next
->fr_next
== NULL
)
29705 /* This mapping symbol is at the end of the section. Discard
29707 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
29708 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29712 /* As long as we have empty frags without any mapping symbols,
29714 /* If the next frag is non-empty and does not start with a
29715 mapping symbol, then this mapping symbol is required. */
29716 if (next
->fr_address
!= next
->fr_next
->fr_address
)
29719 next
= next
->fr_next
;
29721 while (next
!= NULL
);
29726 /* Adjust the symbol table. This marks Thumb symbols as distinct from
29730 arm_adjust_symtab (void)
29735 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29737 if (ARM_IS_THUMB (sym
))
29739 if (THUMB_IS_FUNC (sym
))
29741 /* Mark the symbol as a Thumb function. */
29742 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
29743 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
29744 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
29746 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
29747 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
29749 as_bad (_("%s: unexpected function type: %d"),
29750 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
29752 else switch (S_GET_STORAGE_CLASS (sym
))
29755 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
29758 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
29761 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
29769 if (ARM_IS_INTERWORK (sym
))
29770 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
29777 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29779 if (ARM_IS_THUMB (sym
))
29781 elf_symbol_type
* elf_sym
;
29783 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
29784 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
29786 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
29787 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
29789 /* If it's a .thumb_func, declare it as so,
29790 otherwise tag label as .code 16. */
29791 if (THUMB_IS_FUNC (sym
))
29792 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
29793 ST_BRANCH_TO_THUMB
);
29794 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
29795 elf_sym
->internal_elf_sym
.st_info
=
29796 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
29801 /* Remove any overlapping mapping symbols generated by alignment frags. */
29802 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
29803 /* Now do generic ELF adjustments. */
29804 elf_adjust_symtab ();
29808 /* MD interface: Initialization. */
29811 set_constant_flonums (void)
29815 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
29816 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
29820 /* Auto-select Thumb mode if it's the only available instruction set for the
29821 given architecture. */
29824 autoselect_thumb_from_cpu_variant (void)
29826 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
29827 opcode_select (16);
29836 if ( (arm_ops_hsh
= hash_new ()) == NULL
29837 || (arm_cond_hsh
= hash_new ()) == NULL
29838 || (arm_vcond_hsh
= hash_new ()) == NULL
29839 || (arm_shift_hsh
= hash_new ()) == NULL
29840 || (arm_psr_hsh
= hash_new ()) == NULL
29841 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
29842 || (arm_reg_hsh
= hash_new ()) == NULL
29843 || (arm_reloc_hsh
= hash_new ()) == NULL
29844 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
29845 as_fatal (_("virtual memory exhausted"));
29847 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
29848 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
29849 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
29850 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
29851 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
29852 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
29853 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
29854 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
29855 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
29856 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
29857 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
29858 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
29859 (void *) (v7m_psrs
+ i
));
29860 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
29861 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
29863 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
29865 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
29866 (void *) (barrier_opt_names
+ i
));
29868 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
29870 struct reloc_entry
* entry
= reloc_names
+ i
;
29872 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
29873 /* This makes encode_branch() use the EABI versions of this relocation. */
29874 entry
->reloc
= BFD_RELOC_UNUSED
;
29876 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
29880 set_constant_flonums ();
29882 /* Set the cpu variant based on the command-line options. We prefer
29883 -mcpu= over -march= if both are set (as for GCC); and we prefer
29884 -mfpu= over any other way of setting the floating point unit.
29885 Use of legacy options with new options are faulted. */
29888 if (mcpu_cpu_opt
|| march_cpu_opt
)
29889 as_bad (_("use of old and new-style options to set CPU type"));
29891 selected_arch
= *legacy_cpu
;
29893 else if (mcpu_cpu_opt
)
29895 selected_arch
= *mcpu_cpu_opt
;
29896 selected_ext
= *mcpu_ext_opt
;
29898 else if (march_cpu_opt
)
29900 selected_arch
= *march_cpu_opt
;
29901 selected_ext
= *march_ext_opt
;
29903 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
29908 as_bad (_("use of old and new-style options to set FPU type"));
29910 selected_fpu
= *legacy_fpu
;
29913 selected_fpu
= *mfpu_opt
;
29916 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29917 || defined (TE_NetBSD) || defined (TE_VXWORKS))
29918 /* Some environments specify a default FPU. If they don't, infer it
29919 from the processor. */
29921 selected_fpu
= *mcpu_fpu_opt
;
29922 else if (march_fpu_opt
)
29923 selected_fpu
= *march_fpu_opt
;
29925 selected_fpu
= fpu_default
;
29929 if (ARM_FEATURE_ZERO (selected_fpu
))
29931 if (!no_cpu_selected ())
29932 selected_fpu
= fpu_default
;
29934 selected_fpu
= fpu_arch_fpa
;
29938 if (ARM_FEATURE_ZERO (selected_arch
))
29940 selected_arch
= cpu_default
;
29941 selected_cpu
= selected_arch
;
29943 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29945 /* Autodection of feature mode: allow all features in cpu_variant but leave
29946 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29947 after all instruction have been processed and we can decide what CPU
29948 should be selected. */
29949 if (ARM_FEATURE_ZERO (selected_arch
))
29950 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
29952 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29955 autoselect_thumb_from_cpu_variant ();
29957 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
29959 #if defined OBJ_COFF || defined OBJ_ELF
29961 unsigned int flags
= 0;
29963 #if defined OBJ_ELF
29964 flags
= meabi_flags
;
29966 switch (meabi_flags
)
29968 case EF_ARM_EABI_UNKNOWN
:
29970 /* Set the flags in the private structure. */
29971 if (uses_apcs_26
) flags
|= F_APCS26
;
29972 if (support_interwork
) flags
|= F_INTERWORK
;
29973 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
29974 if (pic_code
) flags
|= F_PIC
;
29975 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
29976 flags
|= F_SOFT_FLOAT
;
29978 switch (mfloat_abi_opt
)
29980 case ARM_FLOAT_ABI_SOFT
:
29981 case ARM_FLOAT_ABI_SOFTFP
:
29982 flags
|= F_SOFT_FLOAT
;
29985 case ARM_FLOAT_ABI_HARD
:
29986 if (flags
& F_SOFT_FLOAT
)
29987 as_bad (_("hard-float conflicts with specified fpu"));
29991 /* Using pure-endian doubles (even if soft-float). */
29992 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
29993 flags
|= F_VFP_FLOAT
;
29995 #if defined OBJ_ELF
29996 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
29997 flags
|= EF_ARM_MAVERICK_FLOAT
;
30000 case EF_ARM_EABI_VER4
:
30001 case EF_ARM_EABI_VER5
:
30002 /* No additional flags to set. */
30009 bfd_set_private_flags (stdoutput
, flags
);
30011 /* We have run out flags in the COFF header to encode the
30012 status of ATPCS support, so instead we create a dummy,
30013 empty, debug section called .arm.atpcs. */
30018 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
30022 bfd_set_section_flags (sec
, SEC_READONLY
| SEC_DEBUGGING
);
30023 bfd_set_section_size (sec
, 0);
30024 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
30030 /* Record the CPU type as well. */
30031 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
30032 mach
= bfd_mach_arm_iWMMXt2
;
30033 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
30034 mach
= bfd_mach_arm_iWMMXt
;
30035 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
30036 mach
= bfd_mach_arm_XScale
;
30037 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
30038 mach
= bfd_mach_arm_ep9312
;
30039 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
30040 mach
= bfd_mach_arm_5TE
;
30041 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
30043 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30044 mach
= bfd_mach_arm_5T
;
30046 mach
= bfd_mach_arm_5
;
30048 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30050 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30051 mach
= bfd_mach_arm_4T
;
30053 mach
= bfd_mach_arm_4
;
30055 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30056 mach
= bfd_mach_arm_3M
;
30057 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30058 mach
= bfd_mach_arm_3
;
30059 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30060 mach
= bfd_mach_arm_2a
;
30061 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30062 mach
= bfd_mach_arm_2
;
30064 mach
= bfd_mach_arm_unknown
;
30066 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30069 /* Command line processing. */
30072 Invocation line includes a switch not recognized by the base assembler.
30073 See if it's a processor-specific option.
30075 This routine is somewhat complicated by the need for backwards
30076 compatibility (since older releases of gcc can't be changed).
30077 The new options try to make the interface as compatible as
30080 New options (supported) are:
30082 -mcpu=<cpu name> Assemble for selected processor
30083 -march=<architecture name> Assemble for selected architecture
30084 -mfpu=<fpu architecture> Assemble for selected FPU.
30085 -EB/-mbig-endian Big-endian
30086 -EL/-mlittle-endian Little-endian
30087 -k Generate PIC code
30088 -mthumb Start in Thumb mode
30089 -mthumb-interwork Code supports ARM/Thumb interworking
30091 -m[no-]warn-deprecated Warn about deprecated features
30092 -m[no-]warn-syms Warn when symbols match instructions
30094 For now we will also provide support for:
30096 -mapcs-32 32-bit Program counter
30097 -mapcs-26 26-bit Program counter
30098 -macps-float Floats passed in FP registers
30099 -mapcs-reentrant Reentrant code
30101 (sometime these will probably be replaced with -mapcs=<list of options>
30102 and -matpcs=<list of options>)
30104 The remaining options are only supported for back-wards compatibility.
30105 Cpu variants, the arm part is optional:
30106 -m[arm]1 Currently not supported.
30107 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30108 -m[arm]3 Arm 3 processor
30109 -m[arm]6[xx], Arm 6 processors
30110 -m[arm]7[xx][t][[d]m] Arm 7 processors
30111 -m[arm]8[10] Arm 8 processors
30112 -m[arm]9[20][tdmi] Arm 9 processors
30113 -mstrongarm[110[0]] StrongARM processors
30114 -mxscale XScale processors
30115 -m[arm]v[2345[t[e]]] Arm architectures
30116 -mall All (except the ARM1)
30118 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
30119 -mfpe-old (No float load/store multiples)
30120 -mvfpxd VFP Single precision
30122 -mno-fpu Disable all floating point instructions
30124 The following CPU names are recognized:
30125 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
30126 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
30127 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
30128 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
30129 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
30130 arm10t arm10e, arm1020t, arm1020e, arm10200e,
30131 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
30135 const char * md_shortopts
= "m:k";
30137 #ifdef ARM_BI_ENDIAN
30138 #define OPTION_EB (OPTION_MD_BASE + 0)
30139 #define OPTION_EL (OPTION_MD_BASE + 1)
30141 #if TARGET_BYTES_BIG_ENDIAN
30142 #define OPTION_EB (OPTION_MD_BASE + 0)
30144 #define OPTION_EL (OPTION_MD_BASE + 1)
30147 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
30148 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
30150 struct option md_longopts
[] =
30153 {"EB", no_argument
, NULL
, OPTION_EB
},
30156 {"EL", no_argument
, NULL
, OPTION_EL
},
30158 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
30160 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
30162 {NULL
, no_argument
, NULL
, 0}
30165 size_t md_longopts_size
= sizeof (md_longopts
);
30167 struct arm_option_table
30169 const char * option
; /* Option name to match. */
30170 const char * help
; /* Help information. */
30171 int * var
; /* Variable to change. */
30172 int value
; /* What to change it to. */
30173 const char * deprecated
; /* If non-null, print this message. */
30176 struct arm_option_table arm_opts
[] =
30178 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
30179 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
30180 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
30181 &support_interwork
, 1, NULL
},
30182 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
30183 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
30184 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
30186 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
30187 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
30188 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
30189 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
30192 /* These are recognized by the assembler, but have no affect on code. */
30193 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
30194 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
30196 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
30197 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
30198 &warn_on_deprecated
, 0, NULL
},
30199 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
30200 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
30201 {NULL
, NULL
, NULL
, 0, NULL
}
30204 struct arm_legacy_option_table
30206 const char * option
; /* Option name to match. */
30207 const arm_feature_set
** var
; /* Variable to change. */
30208 const arm_feature_set value
; /* What to change it to. */
30209 const char * deprecated
; /* If non-null, print this message. */
30212 const struct arm_legacy_option_table arm_legacy_opts
[] =
30214 /* DON'T add any new processors to this list -- we want the whole list
30215 to go away... Add them to the processors table instead. */
30216 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30217 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30218 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30219 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30220 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30221 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30222 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30223 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30224 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30225 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30226 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30227 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30228 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30229 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30230 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30231 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30232 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30233 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30234 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30235 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30236 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30237 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30238 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30239 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30240 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30241 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30242 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30243 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30244 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30245 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30246 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30247 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30248 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30249 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30250 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30251 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30252 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30253 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30254 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30255 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30256 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30257 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30258 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30259 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30260 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30261 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30262 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30263 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30264 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30265 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30266 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30267 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30268 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30269 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30270 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30271 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30272 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30273 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30274 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30275 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30276 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30277 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30278 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30279 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30280 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30281 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30282 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30283 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30284 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
30285 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
30286 N_("use -mcpu=strongarm110")},
30287 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
30288 N_("use -mcpu=strongarm1100")},
30289 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
30290 N_("use -mcpu=strongarm1110")},
30291 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
30292 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
30293 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
30295 /* Architecture variants -- don't add any more to this list either. */
30296 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30297 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30298 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30299 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30300 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30301 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30302 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30303 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30304 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30305 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30306 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30307 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30308 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30309 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30310 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30311 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30312 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30313 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30315 /* Floating point variants -- don't add any more to this list either. */
30316 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
30317 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
30318 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
30319 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
30320 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
30322 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
30325 struct arm_cpu_option_table
30329 const arm_feature_set value
;
30330 const arm_feature_set ext
;
30331 /* For some CPUs we assume an FPU unless the user explicitly sets
30333 const arm_feature_set default_fpu
;
30334 /* The canonical name of the CPU, or NULL to use NAME converted to upper
30336 const char * canonical_name
;
30339 /* This list should, at a minimum, contain all the cpu names
30340 recognized by GCC. */
30341 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
30343 static const struct arm_cpu_option_table arm_cpus
[] =
30345 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
30348 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
30351 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
30354 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
30357 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
30360 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
30363 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
30366 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
30369 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
30372 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
30375 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
30378 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
30381 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
30384 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
30387 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
30390 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
30393 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
30396 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
30399 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
30402 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
30405 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
30408 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
30411 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
30414 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
30417 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
30420 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
30423 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
30426 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
30429 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
30432 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
30435 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
30438 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
30441 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
30444 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
30447 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
30450 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
30453 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
30456 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
30459 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
30462 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
30465 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
30468 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
30471 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
30474 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
30477 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
30480 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
30484 /* For V5 or later processors we default to using VFP; but the user
30485 should really set the FPU type explicitly. */
30486 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
30489 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
30492 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30495 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30498 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
30501 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
30504 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
30507 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
30510 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
30513 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
30516 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
30519 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
30522 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
30525 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
30528 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
30531 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
30534 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
30537 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
30540 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
30543 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
30546 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
30549 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
30552 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
30555 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
30558 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
30561 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
30564 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
30567 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
30570 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
30573 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
30576 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
30579 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
30582 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
30585 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
30588 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30591 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30594 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30595 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30597 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30599 FPU_ARCH_NEON_VFP_V4
),
30600 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30601 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30602 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30603 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30604 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30605 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30606 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30608 FPU_ARCH_NEON_VFP_V4
),
30609 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30611 FPU_ARCH_NEON_VFP_V4
),
30612 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30614 FPU_ARCH_NEON_VFP_V4
),
30615 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30616 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30617 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30618 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30619 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30620 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30621 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30622 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30623 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30624 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30625 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30626 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30627 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30628 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30629 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30630 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30631 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30632 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30633 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30634 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30635 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30636 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30637 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30638 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30639 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30640 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30641 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30642 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A
,
30643 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30644 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30645 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A
,
30646 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30647 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30648 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30649 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30650 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30651 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30654 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30656 FPU_ARCH_VFP_V3D16
),
30657 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30658 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30660 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30661 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30662 FPU_ARCH_VFP_V3D16
),
30663 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30664 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30665 FPU_ARCH_VFP_V3D16
),
30666 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30667 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30668 FPU_ARCH_NEON_VFP_ARMV8
),
30669 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN
,
30670 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30672 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30673 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30675 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30678 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30681 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
30684 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
30687 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
30690 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
30693 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
30696 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
30697 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30698 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30699 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
30700 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30701 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30702 /* ??? XSCALE is really an architecture. */
30703 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
30707 /* ??? iwmmxt is not a processor. */
30708 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
30711 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
30714 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
30719 ARM_CPU_OPT ("ep9312", "ARM920T",
30720 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
30721 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
30723 /* Marvell processors. */
30724 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
30725 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30726 FPU_ARCH_VFP_V3D16
),
30727 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
30728 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30729 FPU_ARCH_NEON_VFP_V4
),
30731 /* APM X-Gene family. */
30732 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
30734 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30735 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
30736 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30737 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30739 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30743 struct arm_ext_table
30747 const arm_feature_set merge
;
30748 const arm_feature_set clear
;
30751 struct arm_arch_option_table
30755 const arm_feature_set value
;
30756 const arm_feature_set default_fpu
;
30757 const struct arm_ext_table
* ext_table
;
30760 /* Used to add support for +E and +noE extension. */
30761 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30762 /* Used to add support for a +E extension. */
30763 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30764 /* Used to add support for a +noE extension. */
30765 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30767 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30768 ~0 & ~FPU_ENDIAN_PURE)
30770 static const struct arm_ext_table armv5te_ext_table
[] =
30772 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
30773 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30776 static const struct arm_ext_table armv7_ext_table
[] =
30778 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30779 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30782 static const struct arm_ext_table armv7ve_ext_table
[] =
30784 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
30785 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
30786 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30787 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30788 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30789 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
30790 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30792 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
30793 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30795 /* Aliases for +simd. */
30796 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30798 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30799 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30800 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30802 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30805 static const struct arm_ext_table armv7a_ext_table
[] =
30807 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30808 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30809 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30810 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30811 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30812 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
30813 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30815 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
30816 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30818 /* Aliases for +simd. */
30819 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30820 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30822 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30823 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30825 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
30826 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
30827 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30830 static const struct arm_ext_table armv7r_ext_table
[] =
30832 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
30833 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
30834 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30835 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30836 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
30837 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30838 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30839 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
30840 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30843 static const struct arm_ext_table armv7em_ext_table
[] =
30845 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
30846 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30847 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
30848 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
30849 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30850 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
30851 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30854 static const struct arm_ext_table armv8a_ext_table
[] =
30856 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30857 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30858 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30859 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30861 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30862 should use the +simd option to turn on FP. */
30863 ARM_REMOVE ("fp", ALL_FP
),
30864 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30865 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30866 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30870 static const struct arm_ext_table armv81a_ext_table
[] =
30872 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30873 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30874 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30876 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30877 should use the +simd option to turn on FP. */
30878 ARM_REMOVE ("fp", ALL_FP
),
30879 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30880 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30881 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30884 static const struct arm_ext_table armv82a_ext_table
[] =
30886 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30887 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
30888 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
30889 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30890 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30891 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30893 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30894 should use the +simd option to turn on FP. */
30895 ARM_REMOVE ("fp", ALL_FP
),
30896 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30897 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30898 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30901 static const struct arm_ext_table armv84a_ext_table
[] =
30903 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30904 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30905 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30906 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30908 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30909 should use the +simd option to turn on FP. */
30910 ARM_REMOVE ("fp", ALL_FP
),
30911 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30912 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30913 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30916 static const struct arm_ext_table armv85a_ext_table
[] =
30918 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30919 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30920 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30921 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30923 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30924 should use the +simd option to turn on FP. */
30925 ARM_REMOVE ("fp", ALL_FP
),
30926 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30929 static const struct arm_ext_table armv8m_main_ext_table
[] =
30931 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30932 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30933 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
30934 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30935 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30938 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
30940 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30941 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30943 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30944 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
30947 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30948 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30949 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
30950 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
30952 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30953 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
30954 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30955 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30958 static const struct arm_ext_table armv8r_ext_table
[] =
30960 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30961 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30962 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30963 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30964 ARM_REMOVE ("fp", ALL_FP
),
30965 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
30966 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30969 /* This list should, at a minimum, contain all the architecture names
30970 recognized by GCC. */
30971 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30972 #define ARM_ARCH_OPT2(N, V, DF, ext) \
30973 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
30975 static const struct arm_arch_option_table arm_archs
[] =
30977 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
30978 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
30979 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
30980 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30981 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30982 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
30983 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
30984 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
30985 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
30986 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
30987 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
30988 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
30989 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
30990 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
30991 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
30992 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
30993 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
30994 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30995 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30996 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
30997 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
30998 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30999 kept to preserve existing behaviour. */
31000 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31001 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31002 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
31003 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
31004 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
31005 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31006 kept to preserve existing behaviour. */
31007 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31008 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31009 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
31010 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
31011 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
31012 /* The official spelling of the ARMv7 profile variants is the dashed form.
31013 Accept the non-dashed form for compatibility with old toolchains. */
31014 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31015 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
31016 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31017 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31018 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31019 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31020 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31021 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
31022 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
31023 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
31025 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
31027 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
31028 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
31029 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
31030 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
31031 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
31032 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
31033 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
31034 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
31035 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
31036 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
31037 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31039 #undef ARM_ARCH_OPT
31041 /* ISA extensions in the co-processor and main instruction set space. */
31043 struct arm_option_extension_value_table
31047 const arm_feature_set merge_value
;
31048 const arm_feature_set clear_value
;
31049 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31050 indicates that an extension is available for all architectures while
31051 ARM_ANY marks an empty entry. */
31052 const arm_feature_set allowed_archs
[2];
31055 /* The following table must be in alphabetical order with a NULL last entry. */
31057 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31058 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
31060 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
31061 use the context sensitive approach using arm_ext_table's. */
31062 static const struct arm_option_extension_value_table arm_extensions
[] =
31064 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
31065 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31066 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31067 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
31068 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31069 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
31070 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
31072 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31073 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31074 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
31075 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
31076 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31077 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31078 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31080 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31081 | ARM_EXT2_FP16_FML
),
31082 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31083 | ARM_EXT2_FP16_FML
),
31085 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31086 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31087 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31088 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31089 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
31090 Thumb divide instruction. Due to this having the same name as the
31091 previous entry, this will be ignored when doing command-line parsing and
31092 only considered by build attribute selection code. */
31093 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31094 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31095 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
31096 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
31097 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
31098 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
31099 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
31100 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
31101 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
31102 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31103 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31104 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31105 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31106 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31107 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31108 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
31109 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
31110 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
31111 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31112 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31113 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31115 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
31116 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
31117 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31118 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
31119 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
31120 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31121 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31122 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31124 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31125 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31126 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
31127 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31128 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
31129 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
31130 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31131 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
31133 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
31134 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31135 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
31136 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
31137 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
31141 /* ISA floating-point and Advanced SIMD extensions. */
31142 struct arm_option_fpu_value_table
31145 const arm_feature_set value
;
31148 /* This list should, at a minimum, contain all the fpu names
31149 recognized by GCC. */
31150 static const struct arm_option_fpu_value_table arm_fpus
[] =
31152 {"softfpa", FPU_NONE
},
31153 {"fpe", FPU_ARCH_FPE
},
31154 {"fpe2", FPU_ARCH_FPE
},
31155 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
31156 {"fpa", FPU_ARCH_FPA
},
31157 {"fpa10", FPU_ARCH_FPA
},
31158 {"fpa11", FPU_ARCH_FPA
},
31159 {"arm7500fe", FPU_ARCH_FPA
},
31160 {"softvfp", FPU_ARCH_VFP
},
31161 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
31162 {"vfp", FPU_ARCH_VFP_V2
},
31163 {"vfp9", FPU_ARCH_VFP_V2
},
31164 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
31165 {"vfp10", FPU_ARCH_VFP_V2
},
31166 {"vfp10-r0", FPU_ARCH_VFP_V1
},
31167 {"vfpxd", FPU_ARCH_VFP_V1xD
},
31168 {"vfpv2", FPU_ARCH_VFP_V2
},
31169 {"vfpv3", FPU_ARCH_VFP_V3
},
31170 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
31171 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
31172 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
31173 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
31174 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
31175 {"arm1020t", FPU_ARCH_VFP_V1
},
31176 {"arm1020e", FPU_ARCH_VFP_V2
},
31177 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
31178 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
31179 {"maverick", FPU_ARCH_MAVERICK
},
31180 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31181 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31182 {"neon-fp16", FPU_ARCH_NEON_FP16
},
31183 {"vfpv4", FPU_ARCH_VFP_V4
},
31184 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
31185 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
31186 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
31187 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
31188 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
31189 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
31190 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
31191 {"crypto-neon-fp-armv8",
31192 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
31193 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
31194 {"crypto-neon-fp-armv8.1",
31195 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
31196 {NULL
, ARM_ARCH_NONE
}
31199 struct arm_option_value_table
31205 static const struct arm_option_value_table arm_float_abis
[] =
31207 {"hard", ARM_FLOAT_ABI_HARD
},
31208 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
31209 {"soft", ARM_FLOAT_ABI_SOFT
},
31214 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
31215 static const struct arm_option_value_table arm_eabis
[] =
31217 {"gnu", EF_ARM_EABI_UNKNOWN
},
31218 {"4", EF_ARM_EABI_VER4
},
31219 {"5", EF_ARM_EABI_VER5
},
31224 struct arm_long_option_table
31226 const char * option
; /* Substring to match. */
31227 const char * help
; /* Help information. */
31228 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
31229 const char * deprecated
; /* If non-null, print this message. */
31233 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
31234 arm_feature_set
*ext_set
,
31235 const struct arm_ext_table
*ext_table
)
31237 /* We insist on extensions being specified in alphabetical order, and with
31238 extensions being added before being removed. We achieve this by having
31239 the global ARM_EXTENSIONS table in alphabetical order, and using the
31240 ADDING_VALUE variable to indicate whether we are adding an extension (1)
31241 or removing it (0) and only allowing it to change in the order
31243 const struct arm_option_extension_value_table
* opt
= NULL
;
31244 const arm_feature_set arm_any
= ARM_ANY
;
31245 int adding_value
= -1;
31247 while (str
!= NULL
&& *str
!= 0)
31254 as_bad (_("invalid architectural extension"));
31259 ext
= strchr (str
, '+');
31264 len
= strlen (str
);
31266 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
31268 if (adding_value
!= 0)
31271 opt
= arm_extensions
;
31279 if (adding_value
== -1)
31282 opt
= arm_extensions
;
31284 else if (adding_value
!= 1)
31286 as_bad (_("must specify extensions to add before specifying "
31287 "those to remove"));
31294 as_bad (_("missing architectural extension"));
31298 gas_assert (adding_value
!= -1);
31299 gas_assert (opt
!= NULL
);
31301 if (ext_table
!= NULL
)
31303 const struct arm_ext_table
* ext_opt
= ext_table
;
31304 bfd_boolean found
= FALSE
;
31305 for (; ext_opt
->name
!= NULL
; ext_opt
++)
31306 if (ext_opt
->name_len
== len
31307 && strncmp (ext_opt
->name
, str
, len
) == 0)
31311 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
31312 /* TODO: Option not supported. When we remove the
31313 legacy table this case should error out. */
31316 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
31320 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
31321 /* TODO: Option not supported. When we remove the
31322 legacy table this case should error out. */
31324 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
31336 /* Scan over the options table trying to find an exact match. */
31337 for (; opt
->name
!= NULL
; opt
++)
31338 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31340 int i
, nb_allowed_archs
=
31341 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31342 /* Check we can apply the extension to this architecture. */
31343 for (i
= 0; i
< nb_allowed_archs
; i
++)
31346 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
31348 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
31351 if (i
== nb_allowed_archs
)
31353 as_bad (_("extension does not apply to the base architecture"));
31357 /* Add or remove the extension. */
31359 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
31361 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
31363 /* Allowing Thumb division instructions for ARMv7 in autodetection
31364 rely on this break so that duplicate extensions (extensions
31365 with the same name as a previous extension in the list) are not
31366 considered for command-line parsing. */
31370 if (opt
->name
== NULL
)
31372 /* Did we fail to find an extension because it wasn't specified in
31373 alphabetical order, or because it does not exist? */
31375 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31376 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31379 if (opt
->name
== NULL
)
31380 as_bad (_("unknown architectural extension `%s'"), str
);
31382 as_bad (_("architectural extensions must be specified in "
31383 "alphabetical order"));
31389 /* We should skip the extension we've just matched the next time
31401 arm_parse_fp16_opt (const char *str
)
31403 if (strcasecmp (str
, "ieee") == 0)
31404 fp16_format
= ARM_FP16_FORMAT_IEEE
;
31405 else if (strcasecmp (str
, "alternative") == 0)
31406 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
31409 as_bad (_("unrecognised float16 format \"%s\""), str
);
31417 arm_parse_cpu (const char *str
)
31419 const struct arm_cpu_option_table
*opt
;
31420 const char *ext
= strchr (str
, '+');
31426 len
= strlen (str
);
31430 as_bad (_("missing cpu name `%s'"), str
);
31434 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
31435 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31437 mcpu_cpu_opt
= &opt
->value
;
31438 if (mcpu_ext_opt
== NULL
)
31439 mcpu_ext_opt
= XNEW (arm_feature_set
);
31440 *mcpu_ext_opt
= opt
->ext
;
31441 mcpu_fpu_opt
= &opt
->default_fpu
;
31442 if (opt
->canonical_name
)
31444 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
31445 strcpy (selected_cpu_name
, opt
->canonical_name
);
31451 if (len
>= sizeof selected_cpu_name
)
31452 len
= (sizeof selected_cpu_name
) - 1;
31454 for (i
= 0; i
< len
; i
++)
31455 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31456 selected_cpu_name
[i
] = 0;
31460 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
31465 as_bad (_("unknown cpu `%s'"), str
);
31470 arm_parse_arch (const char *str
)
31472 const struct arm_arch_option_table
*opt
;
31473 const char *ext
= strchr (str
, '+');
31479 len
= strlen (str
);
31483 as_bad (_("missing architecture name `%s'"), str
);
31487 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
31488 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31490 march_cpu_opt
= &opt
->value
;
31491 if (march_ext_opt
== NULL
)
31492 march_ext_opt
= XNEW (arm_feature_set
);
31493 *march_ext_opt
= arm_arch_none
;
31494 march_fpu_opt
= &opt
->default_fpu
;
31495 strcpy (selected_cpu_name
, opt
->name
);
31498 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
31504 as_bad (_("unknown architecture `%s'\n"), str
);
31509 arm_parse_fpu (const char * str
)
31511 const struct arm_option_fpu_value_table
* opt
;
31513 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31514 if (streq (opt
->name
, str
))
31516 mfpu_opt
= &opt
->value
;
31520 as_bad (_("unknown floating point format `%s'\n"), str
);
31525 arm_parse_float_abi (const char * str
)
31527 const struct arm_option_value_table
* opt
;
31529 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
31530 if (streq (opt
->name
, str
))
31532 mfloat_abi_opt
= opt
->value
;
31536 as_bad (_("unknown floating point abi `%s'\n"), str
);
31542 arm_parse_eabi (const char * str
)
31544 const struct arm_option_value_table
*opt
;
31546 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
31547 if (streq (opt
->name
, str
))
31549 meabi_flags
= opt
->value
;
31552 as_bad (_("unknown EABI `%s'\n"), str
);
31558 arm_parse_it_mode (const char * str
)
31560 bfd_boolean ret
= TRUE
;
31562 if (streq ("arm", str
))
31563 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
31564 else if (streq ("thumb", str
))
31565 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
31566 else if (streq ("always", str
))
31567 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
31568 else if (streq ("never", str
))
31569 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
31572 as_bad (_("unknown implicit IT mode `%s', should be "\
31573 "arm, thumb, always, or never."), str
);
31581 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
31583 codecomposer_syntax
= TRUE
;
31584 arm_comment_chars
[0] = ';';
31585 arm_line_separator_chars
[0] = 0;
31589 struct arm_long_option_table arm_long_opts
[] =
31591 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31592 arm_parse_cpu
, NULL
},
31593 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31594 arm_parse_arch
, NULL
},
31595 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31596 arm_parse_fpu
, NULL
},
31597 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31598 arm_parse_float_abi
, NULL
},
31600 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31601 arm_parse_eabi
, NULL
},
31603 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31604 arm_parse_it_mode
, NULL
},
31605 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31606 arm_ccs_mode
, NULL
},
31608 N_("[ieee|alternative]\n\
31609 set the encoding for half precision floating point "
31610 "numbers to IEEE\n\
31611 or Arm alternative format."),
31612 arm_parse_fp16_opt
, NULL
},
31613 {NULL
, NULL
, 0, NULL
}
31617 md_parse_option (int c
, const char * arg
)
31619 struct arm_option_table
*opt
;
31620 const struct arm_legacy_option_table
*fopt
;
31621 struct arm_long_option_table
*lopt
;
31627 target_big_endian
= 1;
31633 target_big_endian
= 0;
31637 case OPTION_FIX_V4BX
:
31645 #endif /* OBJ_ELF */
31648 /* Listing option. Just ignore these, we don't support additional
31653 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31655 if (c
== opt
->option
[0]
31656 && ((arg
== NULL
&& opt
->option
[1] == 0)
31657 || streq (arg
, opt
->option
+ 1)))
31659 /* If the option is deprecated, tell the user. */
31660 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31661 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31662 arg
? arg
: "", _(opt
->deprecated
));
31664 if (opt
->var
!= NULL
)
31665 *opt
->var
= opt
->value
;
31671 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
31673 if (c
== fopt
->option
[0]
31674 && ((arg
== NULL
&& fopt
->option
[1] == 0)
31675 || streq (arg
, fopt
->option
+ 1)))
31677 /* If the option is deprecated, tell the user. */
31678 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
31679 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31680 arg
? arg
: "", _(fopt
->deprecated
));
31682 if (fopt
->var
!= NULL
)
31683 *fopt
->var
= &fopt
->value
;
31689 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31691 /* These options are expected to have an argument. */
31692 if (c
== lopt
->option
[0]
31694 && strncmp (arg
, lopt
->option
+ 1,
31695 strlen (lopt
->option
+ 1)) == 0)
31697 /* If the option is deprecated, tell the user. */
31698 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
31699 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
31700 _(lopt
->deprecated
));
31702 /* Call the sup-option parser. */
31703 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
31714 md_show_usage (FILE * fp
)
31716 struct arm_option_table
*opt
;
31717 struct arm_long_option_table
*lopt
;
31719 fprintf (fp
, _(" ARM-specific assembler options:\n"));
31721 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31722 if (opt
->help
!= NULL
)
31723 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
31725 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31726 if (lopt
->help
!= NULL
)
31727 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
31731 -EB assemble code for a big-endian cpu\n"));
31736 -EL assemble code for a little-endian cpu\n"));
31740 --fix-v4bx Allow BX in ARMv4 code\n"));
31744 --fdpic generate an FDPIC object file\n"));
31745 #endif /* OBJ_ELF */
31753 arm_feature_set flags
;
31754 } cpu_arch_ver_table
;
31756 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31757 chronologically for architectures, with an exception for ARMv6-M and
31758 ARMv6S-M due to legacy reasons. No new architecture should have a
31759 special case. This allows for build attribute selection results to be
31760 stable when new architectures are added. */
31761 static const cpu_arch_ver_table cpu_arch_ver
[] =
31763 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
31764 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
31765 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
31766 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
31767 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
31768 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
31769 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
31770 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
31771 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
31772 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
31773 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
31774 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
31775 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
31776 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
31777 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
31778 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
31779 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
31780 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
31781 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
31782 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
31783 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
31784 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
31785 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
31786 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
31788 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31789 always selected build attributes to match those of ARMv6-M
31790 (resp. ARMv6S-M). However, due to these architectures being a strict
31791 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31792 would be selected when fully respecting chronology of architectures.
31793 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31794 move them before ARMv7 architectures. */
31795 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
31796 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
31798 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
31799 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
31800 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
31801 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
31802 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
31803 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
31804 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
31805 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
31806 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
31807 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
31808 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
31809 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
31810 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
31811 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
31812 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
31813 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
31814 {-1, ARM_ARCH_NONE
}
31817 /* Set an attribute if it has not already been set by the user. */
31820 aeabi_set_attribute_int (int tag
, int value
)
31823 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31824 || !attributes_set_explicitly
[tag
])
31825 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
31829 aeabi_set_attribute_string (int tag
, const char *value
)
31832 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31833 || !attributes_set_explicitly
[tag
])
31834 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
31837 /* Return whether features in the *NEEDED feature set are available via
31838 extensions for the architecture whose feature set is *ARCH_FSET. */
31841 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
31842 const arm_feature_set
*needed
)
31844 int i
, nb_allowed_archs
;
31845 arm_feature_set ext_fset
;
31846 const struct arm_option_extension_value_table
*opt
;
31848 ext_fset
= arm_arch_none
;
31849 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31851 /* Extension does not provide any feature we need. */
31852 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
31856 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31857 for (i
= 0; i
< nb_allowed_archs
; i
++)
31860 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
31863 /* Extension is available, add it. */
31864 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
31865 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
31869 /* Can we enable all features in *needed? */
31870 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
31873 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31874 a given architecture feature set *ARCH_EXT_FSET including extension feature
31875 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31876 - if true, check for an exact match of the architecture modulo extensions;
31877 - otherwise, select build attribute value of the first superset
31878 architecture released so that results remains stable when new architectures
31880 For -march/-mcpu=all the build attribute value of the most featureful
31881 architecture is returned. Tag_CPU_arch_profile result is returned in
31885 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
31886 const arm_feature_set
*ext_fset
,
31887 char *profile
, int exact_match
)
31889 arm_feature_set arch_fset
;
31890 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
31892 /* Select most featureful architecture with all its extensions if building
31893 for -march=all as the feature sets used to set build attributes. */
31894 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
31896 /* Force revisiting of decision for each new architecture. */
31897 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31899 return TAG_CPU_ARCH_V8
;
31902 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
31904 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
31906 arm_feature_set known_arch_fset
;
31908 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
31911 /* Base architecture match user-specified architecture and
31912 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31913 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
31918 /* Base architecture match user-specified architecture only
31919 (eg. ARMv6-M in the same case as above). Record it in case we
31920 find a match with above condition. */
31921 else if (p_ver_ret
== NULL
31922 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
31928 /* Architecture has all features wanted. */
31929 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
31931 arm_feature_set added_fset
;
31933 /* Compute features added by this architecture over the one
31934 recorded in p_ver_ret. */
31935 if (p_ver_ret
!= NULL
)
31936 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
31938 /* First architecture that match incl. with extensions, or the
31939 only difference in features over the recorded match is
31940 features that were optional and are now mandatory. */
31941 if (p_ver_ret
== NULL
31942 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
31948 else if (p_ver_ret
== NULL
)
31950 arm_feature_set needed_ext_fset
;
31952 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
31954 /* Architecture has all features needed when using some
31955 extensions. Record it and continue searching in case there
31956 exist an architecture providing all needed features without
31957 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31959 if (have_ext_for_needed_feat_p (&known_arch_fset
,
31966 if (p_ver_ret
== NULL
)
31970 /* Tag_CPU_arch_profile. */
31971 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
31972 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
31973 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
31974 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
31976 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
31978 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
31982 return p_ver_ret
->val
;
31985 /* Set the public EABI object attributes. */
31988 aeabi_set_public_attributes (void)
31990 char profile
= '\0';
31993 int fp16_optional
= 0;
31994 int skip_exact_match
= 0;
31995 arm_feature_set flags
, flags_arch
, flags_ext
;
31997 /* Autodetection mode, choose the architecture based the instructions
31999 if (no_cpu_selected ())
32001 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
32003 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
32004 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
32006 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
32007 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
32009 /* Code run during relaxation relies on selected_cpu being set. */
32010 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32011 flags_ext
= arm_arch_none
;
32012 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
32013 selected_ext
= flags_ext
;
32014 selected_cpu
= flags
;
32016 /* Otherwise, choose the architecture based on the capabilities of the
32020 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
32021 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
32022 flags_ext
= selected_ext
;
32023 flags
= selected_cpu
;
32025 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
32027 /* Allow the user to override the reported architecture. */
32028 if (!ARM_FEATURE_ZERO (selected_object_arch
))
32030 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
32031 flags_ext
= arm_arch_none
;
32034 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
32036 /* When this function is run again after relaxation has happened there is no
32037 way to determine whether an architecture or CPU was specified by the user:
32038 - selected_cpu is set above for relaxation to work;
32039 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32040 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32041 Therefore, if not in -march=all case we first try an exact match and fall
32042 back to autodetection. */
32043 if (!skip_exact_match
)
32044 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
32046 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
32048 as_bad (_("no architecture contains all the instructions used\n"));
32050 /* Tag_CPU_name. */
32051 if (selected_cpu_name
[0])
32055 q
= selected_cpu_name
;
32056 if (strncmp (q
, "armv", 4) == 0)
32061 for (i
= 0; q
[i
]; i
++)
32062 q
[i
] = TOUPPER (q
[i
]);
32064 aeabi_set_attribute_string (Tag_CPU_name
, q
);
32067 /* Tag_CPU_arch. */
32068 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
32070 /* Tag_CPU_arch_profile. */
32071 if (profile
!= '\0')
32072 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
32074 /* Tag_DSP_extension. */
32075 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
32076 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
32078 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32079 /* Tag_ARM_ISA_use. */
32080 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
32081 || ARM_FEATURE_ZERO (flags_arch
))
32082 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
32084 /* Tag_THUMB_ISA_use. */
32085 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
32086 || ARM_FEATURE_ZERO (flags_arch
))
32090 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32091 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
32093 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
32097 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
32100 /* Tag_VFP_arch. */
32101 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
32102 aeabi_set_attribute_int (Tag_VFP_arch
,
32103 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32105 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
32106 aeabi_set_attribute_int (Tag_VFP_arch
,
32107 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32109 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
32112 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
32114 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
32116 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
32119 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
32120 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
32121 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
32122 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
32123 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
32125 /* Tag_ABI_HardFP_use. */
32126 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
32127 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
32128 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
32130 /* Tag_WMMX_arch. */
32131 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
32132 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
32133 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
32134 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
32136 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
32137 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
32138 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
32139 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
32140 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
32141 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
32143 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
32145 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
32149 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
32154 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
32155 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
32156 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
32157 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
32159 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
32160 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
32161 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
32165 We set Tag_DIV_use to two when integer divide instructions have been used
32166 in ARM state, or when Thumb integer divide instructions have been used,
32167 but we have no architecture profile set, nor have we any ARM instructions.
32169 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
32170 by the base architecture.
32172 For new architectures we will have to check these tests. */
32173 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32174 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32175 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
32176 aeabi_set_attribute_int (Tag_DIV_use
, 0);
32177 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
32178 || (profile
== '\0'
32179 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
32180 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
32181 aeabi_set_attribute_int (Tag_DIV_use
, 2);
32183 /* Tag_MP_extension_use. */
32184 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
32185 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
32187 /* Tag Virtualization_use. */
32188 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
32190 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
32193 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
32195 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
32196 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
32199 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
32200 finished and free extension feature bits which will not be used anymore. */
32203 arm_md_post_relax (void)
32205 aeabi_set_public_attributes ();
32206 XDELETE (mcpu_ext_opt
);
32207 mcpu_ext_opt
= NULL
;
32208 XDELETE (march_ext_opt
);
32209 march_ext_opt
= NULL
;
32212 /* Add the default contents for the .ARM.attributes section. */
32217 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
32220 aeabi_set_public_attributes ();
32222 #endif /* OBJ_ELF */
32224 /* Parse a .cpu directive. */
32227 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
32229 const struct arm_cpu_option_table
*opt
;
32233 name
= input_line_pointer
;
32234 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32235 input_line_pointer
++;
32236 saved_char
= *input_line_pointer
;
32237 *input_line_pointer
= 0;
32239 /* Skip the first "all" entry. */
32240 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
32241 if (streq (opt
->name
, name
))
32243 selected_arch
= opt
->value
;
32244 selected_ext
= opt
->ext
;
32245 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32246 if (opt
->canonical_name
)
32247 strcpy (selected_cpu_name
, opt
->canonical_name
);
32251 for (i
= 0; opt
->name
[i
]; i
++)
32252 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32254 selected_cpu_name
[i
] = 0;
32256 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32258 *input_line_pointer
= saved_char
;
32259 demand_empty_rest_of_line ();
32262 as_bad (_("unknown cpu `%s'"), name
);
32263 *input_line_pointer
= saved_char
;
32264 ignore_rest_of_line ();
32267 /* Parse a .arch directive. */
32270 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
32272 const struct arm_arch_option_table
*opt
;
32276 name
= input_line_pointer
;
32277 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32278 input_line_pointer
++;
32279 saved_char
= *input_line_pointer
;
32280 *input_line_pointer
= 0;
32282 /* Skip the first "all" entry. */
32283 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32284 if (streq (opt
->name
, name
))
32286 selected_arch
= opt
->value
;
32287 selected_ext
= arm_arch_none
;
32288 selected_cpu
= selected_arch
;
32289 strcpy (selected_cpu_name
, opt
->name
);
32290 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32291 *input_line_pointer
= saved_char
;
32292 demand_empty_rest_of_line ();
32296 as_bad (_("unknown architecture `%s'\n"), name
);
32297 *input_line_pointer
= saved_char
;
32298 ignore_rest_of_line ();
32301 /* Parse a .object_arch directive. */
32304 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
32306 const struct arm_arch_option_table
*opt
;
32310 name
= input_line_pointer
;
32311 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32312 input_line_pointer
++;
32313 saved_char
= *input_line_pointer
;
32314 *input_line_pointer
= 0;
32316 /* Skip the first "all" entry. */
32317 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32318 if (streq (opt
->name
, name
))
32320 selected_object_arch
= opt
->value
;
32321 *input_line_pointer
= saved_char
;
32322 demand_empty_rest_of_line ();
32326 as_bad (_("unknown architecture `%s'\n"), name
);
32327 *input_line_pointer
= saved_char
;
32328 ignore_rest_of_line ();
32331 /* Parse a .arch_extension directive. */
32334 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
32336 const struct arm_option_extension_value_table
*opt
;
32339 int adding_value
= 1;
32341 name
= input_line_pointer
;
32342 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32343 input_line_pointer
++;
32344 saved_char
= *input_line_pointer
;
32345 *input_line_pointer
= 0;
32347 if (strlen (name
) >= 2
32348 && strncmp (name
, "no", 2) == 0)
32354 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32355 if (streq (opt
->name
, name
))
32357 int i
, nb_allowed_archs
=
32358 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
32359 for (i
= 0; i
< nb_allowed_archs
; i
++)
32362 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
32364 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
32368 if (i
== nb_allowed_archs
)
32370 as_bad (_("architectural extension `%s' is not allowed for the "
32371 "current base architecture"), name
);
32376 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
32379 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
32381 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32382 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32383 *input_line_pointer
= saved_char
;
32384 demand_empty_rest_of_line ();
32385 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
32386 on this return so that duplicate extensions (extensions with the
32387 same name as a previous extension in the list) are not considered
32388 for command-line parsing. */
32392 if (opt
->name
== NULL
)
32393 as_bad (_("unknown architecture extension `%s'\n"), name
);
32395 *input_line_pointer
= saved_char
;
32396 ignore_rest_of_line ();
32399 /* Parse a .fpu directive. */
32402 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
32404 const struct arm_option_fpu_value_table
*opt
;
32408 name
= input_line_pointer
;
32409 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32410 input_line_pointer
++;
32411 saved_char
= *input_line_pointer
;
32412 *input_line_pointer
= 0;
32414 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32415 if (streq (opt
->name
, name
))
32417 selected_fpu
= opt
->value
;
32418 #ifndef CPU_DEFAULT
32419 if (no_cpu_selected ())
32420 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
32423 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32424 *input_line_pointer
= saved_char
;
32425 demand_empty_rest_of_line ();
32429 as_bad (_("unknown floating point format `%s'\n"), name
);
32430 *input_line_pointer
= saved_char
;
32431 ignore_rest_of_line ();
32434 /* Copy symbol information. */
32437 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
32439 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
32443 /* Given a symbolic attribute NAME, return the proper integer value.
32444 Returns -1 if the attribute is not known. */
32447 arm_convert_symbolic_attribute (const char *name
)
32449 static const struct
32454 attribute_table
[] =
32456 /* When you modify this table you should
32457 also modify the list in doc/c-arm.texi. */
32458 #define T(tag) {#tag, tag}
32459 T (Tag_CPU_raw_name
),
32462 T (Tag_CPU_arch_profile
),
32463 T (Tag_ARM_ISA_use
),
32464 T (Tag_THUMB_ISA_use
),
32468 T (Tag_Advanced_SIMD_arch
),
32469 T (Tag_PCS_config
),
32470 T (Tag_ABI_PCS_R9_use
),
32471 T (Tag_ABI_PCS_RW_data
),
32472 T (Tag_ABI_PCS_RO_data
),
32473 T (Tag_ABI_PCS_GOT_use
),
32474 T (Tag_ABI_PCS_wchar_t
),
32475 T (Tag_ABI_FP_rounding
),
32476 T (Tag_ABI_FP_denormal
),
32477 T (Tag_ABI_FP_exceptions
),
32478 T (Tag_ABI_FP_user_exceptions
),
32479 T (Tag_ABI_FP_number_model
),
32480 T (Tag_ABI_align_needed
),
32481 T (Tag_ABI_align8_needed
),
32482 T (Tag_ABI_align_preserved
),
32483 T (Tag_ABI_align8_preserved
),
32484 T (Tag_ABI_enum_size
),
32485 T (Tag_ABI_HardFP_use
),
32486 T (Tag_ABI_VFP_args
),
32487 T (Tag_ABI_WMMX_args
),
32488 T (Tag_ABI_optimization_goals
),
32489 T (Tag_ABI_FP_optimization_goals
),
32490 T (Tag_compatibility
),
32491 T (Tag_CPU_unaligned_access
),
32492 T (Tag_FP_HP_extension
),
32493 T (Tag_VFP_HP_extension
),
32494 T (Tag_ABI_FP_16bit_format
),
32495 T (Tag_MPextension_use
),
32497 T (Tag_nodefaults
),
32498 T (Tag_also_compatible_with
),
32499 T (Tag_conformance
),
32501 T (Tag_Virtualization_use
),
32502 T (Tag_DSP_extension
),
32504 /* We deliberately do not include Tag_MPextension_use_legacy. */
32512 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
32513 if (streq (name
, attribute_table
[i
].name
))
32514 return attribute_table
[i
].tag
;
32519 /* Apply sym value for relocations only in the case that they are for
32520 local symbols in the same segment as the fixup and you have the
32521 respective architectural feature for blx and simple switches. */
32524 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
32527 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
32528 /* PR 17444: If the local symbol is in a different section then a reloc
32529 will always be generated for it, so applying the symbol value now
32530 will result in a double offset being stored in the relocation. */
32531 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
32532 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
32534 switch (fixP
->fx_r_type
)
32536 case BFD_RELOC_ARM_PCREL_BLX
:
32537 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
32538 if (ARM_IS_FUNC (fixP
->fx_addsy
))
32542 case BFD_RELOC_ARM_PCREL_CALL
:
32543 case BFD_RELOC_THUMB_PCREL_BLX
:
32544 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
32555 #endif /* OBJ_ELF */