1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
39 #include "dw2gencfi.h"
42 #include "dwarf2dbg.h"
45 /* Must be at least the size of the largest unwind opcode (currently two). */
46 #define ARM_OPCODE_CHUNK_SIZE 8
48 /* This structure holds the unwinding state. */
53 symbolS
* table_entry
;
54 symbolS
* personality_routine
;
55 int personality_index
;
56 /* The segment containing the function. */
59 /* Opcodes generated from this function. */
60 unsigned char * opcodes
;
63 /* The number of bytes pushed to the stack. */
65 /* We don't add stack adjustment opcodes immediately so that we can merge
66 multiple adjustments. We can also omit the final adjustment
67 when using a frame pointer. */
68 offsetT pending_offset
;
69 /* These two fields are set by both unwind_movsp and unwind_setfp. They
70 hold the reg+offset to use when restoring sp from a frame pointer. */
73 /* Nonzero if an unwind_setfp directive has been seen. */
75 /* Nonzero if the last opcode restores sp from fp_reg. */
76 unsigned sp_restored
:1;
79 /* Whether --fdpic was given. */
84 /* Results from operand parsing worker functions. */
88 PARSE_OPERAND_SUCCESS
,
90 PARSE_OPERAND_FAIL_NO_BACKTRACK
91 } parse_operand_result
;
100 /* Types of processor to assemble for. */
102 /* The code that was here used to select a default CPU depending on compiler
103 pre-defines which were only present when doing native builds, thus
104 changing gas' default behaviour depending upon the build host.
106 If you have a target that requires a default CPU option then the you
107 should define CPU_DEFAULT here. */
110 /* Perform range checks on positive and negative overflows by checking if the
111 VALUE given fits within the range of an BITS sized immediate. */
112 static bfd_boolean
out_of_range_p (offsetT value
, offsetT bits
)
114 gas_assert (bits
< (offsetT
)(sizeof (value
) * 8));
115 return (value
& ~((1 << bits
)-1))
116 && ((value
& ~((1 << bits
)-1)) != ~((1 << bits
)-1));
121 # define FPU_DEFAULT FPU_ARCH_FPA
122 # elif defined (TE_NetBSD)
124 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
126 /* Legacy a.out format. */
127 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
129 # elif defined (TE_VXWORKS)
130 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
132 /* For backwards compatibility, default to FPA. */
133 # define FPU_DEFAULT FPU_ARCH_FPA
135 #endif /* ifndef FPU_DEFAULT */
137 #define streq(a, b) (strcmp (a, b) == 0)
139 /* Current set of feature bits available (CPU+FPU). Different from
140 selected_cpu + selected_fpu in case of autodetection since the CPU
141 feature bits are then all set. */
142 static arm_feature_set cpu_variant
;
143 /* Feature bits used in each execution state. Used to set build attribute
144 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
145 static arm_feature_set arm_arch_used
;
146 static arm_feature_set thumb_arch_used
;
148 /* Flags stored in private area of BFD structure. */
149 static int uses_apcs_26
= FALSE
;
150 static int atpcs
= FALSE
;
151 static int support_interwork
= FALSE
;
152 static int uses_apcs_float
= FALSE
;
153 static int pic_code
= FALSE
;
154 static int fix_v4bx
= FALSE
;
155 /* Warn on using deprecated features. */
156 static int warn_on_deprecated
= TRUE
;
157 static int warn_on_restrict_it
= FALSE
;
159 /* Understand CodeComposer Studio assembly syntax. */
160 bfd_boolean codecomposer_syntax
= FALSE
;
162 /* Variables that we set while parsing command-line options. Once all
163 options have been read we re-process these values to set the real
166 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
167 instead of -mcpu=arm1). */
168 static const arm_feature_set
*legacy_cpu
= NULL
;
169 static const arm_feature_set
*legacy_fpu
= NULL
;
171 /* CPU, extension and FPU feature bits selected by -mcpu. */
172 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
173 static arm_feature_set
*mcpu_ext_opt
= NULL
;
174 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
176 /* CPU, extension and FPU feature bits selected by -march. */
177 static const arm_feature_set
*march_cpu_opt
= NULL
;
178 static arm_feature_set
*march_ext_opt
= NULL
;
179 static const arm_feature_set
*march_fpu_opt
= NULL
;
181 /* Feature bits selected by -mfpu. */
182 static const arm_feature_set
*mfpu_opt
= NULL
;
184 /* Constants for known architecture features. */
185 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
186 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
187 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
188 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
189 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
190 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
191 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
193 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
195 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
198 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
201 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
202 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
203 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
204 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
205 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
206 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
207 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
208 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
209 static const arm_feature_set arm_ext_v4t_5
=
210 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
211 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
212 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
213 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
214 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
215 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
216 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
217 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
218 /* Only for compatability of hint instructions. */
219 static const arm_feature_set arm_ext_v6k_v6t2
=
220 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
221 static const arm_feature_set arm_ext_v6_notm
=
222 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
223 static const arm_feature_set arm_ext_v6_dsp
=
224 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
225 static const arm_feature_set arm_ext_barrier
=
226 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
227 static const arm_feature_set arm_ext_msr
=
228 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
229 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
230 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
231 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
232 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
233 static const arm_feature_set arm_ext_v8r
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R
);
235 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
237 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
238 static const arm_feature_set arm_ext_m
=
239 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
240 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
241 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
242 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
243 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
244 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
245 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
246 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
247 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
248 static const arm_feature_set arm_ext_v8m_main
=
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
250 static const arm_feature_set arm_ext_v8_1m_main
=
251 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
252 /* Instructions in ARMv8-M only found in M profile architectures. */
253 static const arm_feature_set arm_ext_v8m_m_only
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
255 static const arm_feature_set arm_ext_v6t2_v8m
=
256 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
257 /* Instructions shared between ARMv8-A and ARMv8-M. */
258 static const arm_feature_set arm_ext_atomics
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
261 /* DSP instructions Tag_DSP_extension refers to. */
262 static const arm_feature_set arm_ext_dsp
=
263 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
265 static const arm_feature_set arm_ext_ras
=
266 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
267 /* FP16 instructions. */
268 static const arm_feature_set arm_ext_fp16
=
269 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
270 static const arm_feature_set arm_ext_fp16_fml
=
271 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
272 static const arm_feature_set arm_ext_v8_2
=
273 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
274 static const arm_feature_set arm_ext_v8_3
=
275 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
276 static const arm_feature_set arm_ext_sb
=
277 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
278 static const arm_feature_set arm_ext_predres
=
279 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
280 static const arm_feature_set arm_ext_bf16
=
281 ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
);
282 static const arm_feature_set arm_ext_i8mm
=
283 ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
);
284 static const arm_feature_set arm_ext_crc
=
285 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
);
286 static const arm_feature_set arm_ext_cde
=
287 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
);
288 static const arm_feature_set arm_ext_cde0
=
289 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE0
);
290 static const arm_feature_set arm_ext_cde1
=
291 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE1
);
292 static const arm_feature_set arm_ext_cde2
=
293 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE2
);
294 static const arm_feature_set arm_ext_cde3
=
295 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE3
);
296 static const arm_feature_set arm_ext_cde4
=
297 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE4
);
298 static const arm_feature_set arm_ext_cde5
=
299 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE5
);
300 static const arm_feature_set arm_ext_cde6
=
301 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE6
);
302 static const arm_feature_set arm_ext_cde7
=
303 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE7
);
305 static const arm_feature_set arm_arch_any
= ARM_ANY
;
306 static const arm_feature_set fpu_any
= FPU_ANY
;
307 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
308 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
309 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
311 static const arm_feature_set arm_cext_iwmmxt2
=
312 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
313 static const arm_feature_set arm_cext_iwmmxt
=
314 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
315 static const arm_feature_set arm_cext_xscale
=
316 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
317 static const arm_feature_set arm_cext_maverick
=
318 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
319 static const arm_feature_set fpu_fpa_ext_v1
=
320 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
321 static const arm_feature_set fpu_fpa_ext_v2
=
322 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
323 static const arm_feature_set fpu_vfp_ext_v1xd
=
324 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
325 static const arm_feature_set fpu_vfp_ext_v1
=
326 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
327 static const arm_feature_set fpu_vfp_ext_v2
=
328 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
329 static const arm_feature_set fpu_vfp_ext_v3xd
=
330 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
331 static const arm_feature_set fpu_vfp_ext_v3
=
332 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
333 static const arm_feature_set fpu_vfp_ext_d32
=
334 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
335 static const arm_feature_set fpu_neon_ext_v1
=
336 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
337 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
338 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
339 static const arm_feature_set mve_ext
=
340 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
);
341 static const arm_feature_set mve_fp_ext
=
342 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
);
343 /* Note: This has more than one bit set, which means using it with
344 mark_feature_used (which returns if *any* of the bits are set in the current
345 cpu variant) can give surprising results. */
346 static const arm_feature_set armv8m_fp
=
347 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16
);
349 static const arm_feature_set fpu_vfp_fp16
=
350 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
351 static const arm_feature_set fpu_neon_ext_fma
=
352 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
354 static const arm_feature_set fpu_vfp_ext_fma
=
355 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
356 static const arm_feature_set fpu_vfp_ext_armv8
=
357 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
358 static const arm_feature_set fpu_vfp_ext_armv8xd
=
359 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
360 static const arm_feature_set fpu_neon_ext_armv8
=
361 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
362 static const arm_feature_set fpu_crypto_ext_armv8
=
363 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
364 static const arm_feature_set fpu_neon_ext_v8_1
=
365 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
366 static const arm_feature_set fpu_neon_ext_dotprod
=
367 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
369 static int mfloat_abi_opt
= -1;
370 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
372 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
373 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
375 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
376 /* Feature bits selected by the last -mcpu/-march or by the combination of the
377 last .cpu/.arch directive .arch_extension directives since that
379 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
380 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
381 static arm_feature_set selected_fpu
= FPU_NONE
;
382 /* Feature bits selected by the last .object_arch directive. */
383 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
384 /* Must be long enough to hold any of the names in arm_cpus. */
385 static const struct arm_ext_table
* selected_ctx_ext_table
= NULL
;
386 static char selected_cpu_name
[20];
388 extern FLONUM_TYPE generic_floating_point_number
;
390 /* Return if no cpu was selected on command-line. */
392 no_cpu_selected (void)
394 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
399 static int meabi_flags
= EABI_DEFAULT
;
401 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
404 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
409 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
414 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
415 symbolS
* GOT_symbol
;
418 /* 0: assemble for ARM,
419 1: assemble for Thumb,
420 2: assemble for Thumb even though target CPU does not support thumb
422 static int thumb_mode
= 0;
423 /* A value distinct from the possible values for thumb_mode that we
424 can use to record whether thumb_mode has been copied into the
425 tc_frag_data field of a frag. */
426 #define MODE_RECORDED (1 << 4)
428 /* Specifies the intrinsic IT insn behavior mode. */
429 enum implicit_it_mode
431 IMPLICIT_IT_MODE_NEVER
= 0x00,
432 IMPLICIT_IT_MODE_ARM
= 0x01,
433 IMPLICIT_IT_MODE_THUMB
= 0x02,
434 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
436 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
438 /* If unified_syntax is true, we are processing the new unified
439 ARM/Thumb syntax. Important differences from the old ARM mode:
441 - Immediate operands do not require a # prefix.
442 - Conditional affixes always appear at the end of the
443 instruction. (For backward compatibility, those instructions
444 that formerly had them in the middle, continue to accept them
446 - The IT instruction may appear, and if it does is validated
447 against subsequent conditional affixes. It does not generate
450 Important differences from the old Thumb mode:
452 - Immediate operands do not require a # prefix.
453 - Most of the V6T2 instructions are only available in unified mode.
454 - The .N and .W suffixes are recognized and honored (it is an error
455 if they cannot be honored).
456 - All instructions set the flags if and only if they have an 's' affix.
457 - Conditional affixes may be used. They are validated against
458 preceding IT instructions. Unlike ARM mode, you cannot use a
459 conditional affix except in the scope of an IT instruction. */
461 static bfd_boolean unified_syntax
= FALSE
;
463 /* An immediate operand can start with #, and ld*, st*, pld operands
464 can contain [ and ]. We need to tell APP not to elide whitespace
465 before a [, which can appear as the first operand for pld.
466 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
467 const char arm_symbol_chars
[] = "#[]{}";
483 enum neon_el_type type
;
487 #define NEON_MAX_TYPE_ELS 5
491 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
495 enum pred_instruction_type
501 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
502 if inside, should be the last one. */
503 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
504 i.e. BKPT and NOP. */
505 IT_INSN
, /* The IT insn has been parsed. */
506 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
507 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
508 a predication code. */
509 MVE_UNPREDICABLE_INSN
, /* MVE instruction that is non-predicable. */
512 /* The maximum number of operands we need. */
513 #define ARM_IT_MAX_OPERANDS 6
514 #define ARM_IT_MAX_RELOCS 3
519 unsigned long instruction
;
523 /* "uncond_value" is set to the value in place of the conditional field in
524 unconditional versions of the instruction, or -1 if nothing is
527 struct neon_type vectype
;
528 /* This does not indicate an actual NEON instruction, only that
529 the mnemonic accepts neon-style type suffixes. */
531 /* Set to the opcode if the instruction needs relaxation.
532 Zero if the instruction is not relaxed. */
536 bfd_reloc_code_real_type type
;
539 } relocs
[ARM_IT_MAX_RELOCS
];
541 enum pred_instruction_type pred_insn_type
;
547 struct neon_type_el vectype
;
548 unsigned present
: 1; /* Operand present. */
549 unsigned isreg
: 1; /* Operand was a register. */
550 unsigned immisreg
: 2; /* .imm field is a second register.
551 0: imm, 1: gpr, 2: MVE Q-register. */
552 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
556 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
557 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
558 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
559 instructions. This allows us to disambiguate ARM <-> vector insns. */
560 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
561 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
562 unsigned isquad
: 1; /* Operand is SIMD quad register. */
563 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
564 unsigned iszr
: 1; /* Operand is ZR register. */
565 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
566 unsigned writeback
: 1; /* Operand has trailing ! */
567 unsigned preind
: 1; /* Preindexed address. */
568 unsigned postind
: 1; /* Postindexed address. */
569 unsigned negative
: 1; /* Index register was negated. */
570 unsigned shifted
: 1; /* Shift applied to operation. */
571 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
572 } operands
[ARM_IT_MAX_OPERANDS
];
575 static struct arm_it inst
;
577 #define NUM_FLOAT_VALS 8
579 const char * fp_const
[] =
581 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
584 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
594 #define CP_T_X 0x00008000
595 #define CP_T_Y 0x00400000
597 #define CONDS_BIT 0x00100000
598 #define LOAD_BIT 0x00100000
600 #define DOUBLE_LOAD_FLAG 0x00000001
604 const char * template_name
;
608 #define COND_ALWAYS 0xE
612 const char * template_name
;
616 struct asm_barrier_opt
618 const char * template_name
;
620 const arm_feature_set arch
;
623 /* The bit that distinguishes CPSR and SPSR. */
624 #define SPSR_BIT (1 << 22)
626 /* The individual PSR flag bits. */
627 #define PSR_c (1 << 16)
628 #define PSR_x (1 << 17)
629 #define PSR_s (1 << 18)
630 #define PSR_f (1 << 19)
635 bfd_reloc_code_real_type reloc
;
640 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
641 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
646 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
649 /* Bits for DEFINED field in neon_typed_alias. */
650 #define NTA_HASTYPE 1
651 #define NTA_HASINDEX 2
653 struct neon_typed_alias
655 unsigned char defined
;
657 struct neon_type_el eltype
;
660 /* ARM register categories. This includes coprocessor numbers and various
661 architecture extensions' registers. Each entry should have an error message
662 in reg_expected_msgs below. */
692 /* Structure for a hash table entry for a register.
693 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
694 information which states whether a vector type or index is specified (for a
695 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
701 unsigned char builtin
;
702 struct neon_typed_alias
* neon
;
705 /* Diagnostics used when we don't get a register of the expected type. */
706 const char * const reg_expected_msgs
[] =
708 [REG_TYPE_RN
] = N_("ARM register expected"),
709 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
710 [REG_TYPE_CN
] = N_("co-processor register expected"),
711 [REG_TYPE_FN
] = N_("FPA register expected"),
712 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
713 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
714 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
715 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
716 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
717 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
718 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
720 [REG_TYPE_VFC
] = N_("VFP system register expected"),
721 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
722 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
723 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
724 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
725 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
726 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
727 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
728 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
729 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
730 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
731 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
735 /* Some well known registers that we refer to directly elsewhere. */
741 /* ARM instructions take 4bytes in the object file, Thumb instructions
747 /* Basic string to match. */
748 const char * template_name
;
750 /* Parameters to instruction. */
751 unsigned int operands
[8];
753 /* Conditional tag - see opcode_lookup. */
754 unsigned int tag
: 4;
756 /* Basic instruction code. */
759 /* Thumb-format instruction code. */
762 /* Which architecture variant provides this instruction. */
763 const arm_feature_set
* avariant
;
764 const arm_feature_set
* tvariant
;
766 /* Function to call to encode instruction in ARM format. */
767 void (* aencode
) (void);
769 /* Function to call to encode instruction in Thumb format. */
770 void (* tencode
) (void);
772 /* Indicates whether this instruction may be vector predicated. */
773 unsigned int mayBeVecPred
: 1;
776 /* Defines for various bits that we will want to toggle. */
777 #define INST_IMMEDIATE 0x02000000
778 #define OFFSET_REG 0x02000000
779 #define HWOFFSET_IMM 0x00400000
780 #define SHIFT_BY_REG 0x00000010
781 #define PRE_INDEX 0x01000000
782 #define INDEX_UP 0x00800000
783 #define WRITE_BACK 0x00200000
784 #define LDM_TYPE_2_OR_3 0x00400000
785 #define CPSI_MMOD 0x00020000
787 #define LITERAL_MASK 0xf000f000
788 #define OPCODE_MASK 0xfe1fffff
789 #define V4_STR_BIT 0x00000020
790 #define VLDR_VMOV_SAME 0x0040f000
792 #define T2_SUBS_PC_LR 0xf3de8f00
794 #define DATA_OP_SHIFT 21
795 #define SBIT_SHIFT 20
797 #define T2_OPCODE_MASK 0xfe1fffff
798 #define T2_DATA_OP_SHIFT 21
799 #define T2_SBIT_SHIFT 20
801 #define A_COND_MASK 0xf0000000
802 #define A_PUSH_POP_OP_MASK 0x0fff0000
804 /* Opcodes for pushing/poping registers to/from the stack. */
805 #define A1_OPCODE_PUSH 0x092d0000
806 #define A2_OPCODE_PUSH 0x052d0004
807 #define A2_OPCODE_POP 0x049d0004
809 /* Codes to distinguish the arithmetic instructions. */
820 #define OPCODE_CMP 10
821 #define OPCODE_CMN 11
822 #define OPCODE_ORR 12
823 #define OPCODE_MOV 13
824 #define OPCODE_BIC 14
825 #define OPCODE_MVN 15
827 #define T2_OPCODE_AND 0
828 #define T2_OPCODE_BIC 1
829 #define T2_OPCODE_ORR 2
830 #define T2_OPCODE_ORN 3
831 #define T2_OPCODE_EOR 4
832 #define T2_OPCODE_ADD 8
833 #define T2_OPCODE_ADC 10
834 #define T2_OPCODE_SBC 11
835 #define T2_OPCODE_SUB 13
836 #define T2_OPCODE_RSB 14
838 #define T_OPCODE_MUL 0x4340
839 #define T_OPCODE_TST 0x4200
840 #define T_OPCODE_CMN 0x42c0
841 #define T_OPCODE_NEG 0x4240
842 #define T_OPCODE_MVN 0x43c0
844 #define T_OPCODE_ADD_R3 0x1800
845 #define T_OPCODE_SUB_R3 0x1a00
846 #define T_OPCODE_ADD_HI 0x4400
847 #define T_OPCODE_ADD_ST 0xb000
848 #define T_OPCODE_SUB_ST 0xb080
849 #define T_OPCODE_ADD_SP 0xa800
850 #define T_OPCODE_ADD_PC 0xa000
851 #define T_OPCODE_ADD_I8 0x3000
852 #define T_OPCODE_SUB_I8 0x3800
853 #define T_OPCODE_ADD_I3 0x1c00
854 #define T_OPCODE_SUB_I3 0x1e00
856 #define T_OPCODE_ASR_R 0x4100
857 #define T_OPCODE_LSL_R 0x4080
858 #define T_OPCODE_LSR_R 0x40c0
859 #define T_OPCODE_ROR_R 0x41c0
860 #define T_OPCODE_ASR_I 0x1000
861 #define T_OPCODE_LSL_I 0x0000
862 #define T_OPCODE_LSR_I 0x0800
864 #define T_OPCODE_MOV_I8 0x2000
865 #define T_OPCODE_CMP_I8 0x2800
866 #define T_OPCODE_CMP_LR 0x4280
867 #define T_OPCODE_MOV_HR 0x4600
868 #define T_OPCODE_CMP_HR 0x4500
870 #define T_OPCODE_LDR_PC 0x4800
871 #define T_OPCODE_LDR_SP 0x9800
872 #define T_OPCODE_STR_SP 0x9000
873 #define T_OPCODE_LDR_IW 0x6800
874 #define T_OPCODE_STR_IW 0x6000
875 #define T_OPCODE_LDR_IH 0x8800
876 #define T_OPCODE_STR_IH 0x8000
877 #define T_OPCODE_LDR_IB 0x7800
878 #define T_OPCODE_STR_IB 0x7000
879 #define T_OPCODE_LDR_RW 0x5800
880 #define T_OPCODE_STR_RW 0x5000
881 #define T_OPCODE_LDR_RH 0x5a00
882 #define T_OPCODE_STR_RH 0x5200
883 #define T_OPCODE_LDR_RB 0x5c00
884 #define T_OPCODE_STR_RB 0x5400
886 #define T_OPCODE_PUSH 0xb400
887 #define T_OPCODE_POP 0xbc00
889 #define T_OPCODE_BRANCH 0xe000
891 #define THUMB_SIZE 2 /* Size of thumb instruction. */
892 #define THUMB_PP_PC_LR 0x0100
893 #define THUMB_LOAD_BIT 0x0800
894 #define THUMB2_LOAD_BIT 0x00100000
896 #define BAD_SYNTAX _("syntax error")
897 #define BAD_ARGS _("bad arguments to instruction")
898 #define BAD_SP _("r13 not allowed here")
899 #define BAD_PC _("r15 not allowed here")
900 #define BAD_ODD _("Odd register not allowed here")
901 #define BAD_EVEN _("Even register not allowed here")
902 #define BAD_COND _("instruction cannot be conditional")
903 #define BAD_OVERLAP _("registers may not be the same")
904 #define BAD_HIREG _("lo register required")
905 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
906 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
907 #define BAD_BRANCH _("branch must be last instruction in IT block")
908 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
909 #define BAD_NO_VPT _("instruction not allowed in VPT block")
910 #define BAD_NOT_IT _("instruction not allowed in IT block")
911 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
912 #define BAD_FPU _("selected FPU does not support instruction")
913 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
914 #define BAD_OUT_VPT \
915 _("vector predicated instruction should be in VPT/VPST block")
916 #define BAD_IT_COND _("incorrect condition in IT block")
917 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
918 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
919 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
920 #define BAD_PC_ADDRESSING \
921 _("cannot use register index with PC-relative addressing")
922 #define BAD_PC_WRITEBACK \
923 _("cannot use writeback with PC-relative addressing")
924 #define BAD_RANGE _("branch out of range")
925 #define BAD_FP16 _("selected processor does not support fp16 instruction")
926 #define BAD_BF16 _("selected processor does not support bf16 instruction")
927 #define BAD_CDE _("selected processor does not support cde instruction")
928 #define BAD_CDE_COPROC _("coprocessor for insn is not enabled for cde")
929 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
930 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
931 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
933 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
935 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
937 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
939 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
940 #define BAD_MVE_AUTO \
941 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
942 " use a valid -march or -mcpu option.")
943 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
944 "and source operands makes instruction UNPREDICTABLE")
945 #define BAD_EL_TYPE _("bad element type for instruction")
946 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
948 static htab_t arm_ops_hsh
;
949 static htab_t arm_cond_hsh
;
950 static htab_t arm_vcond_hsh
;
951 static htab_t arm_shift_hsh
;
952 static htab_t arm_psr_hsh
;
953 static htab_t arm_v7m_psr_hsh
;
954 static htab_t arm_reg_hsh
;
955 static htab_t arm_reloc_hsh
;
956 static htab_t arm_barrier_opt_hsh
;
958 /* Stuff needed to resolve the label ambiguity
967 symbolS
* last_label_seen
;
968 static int label_is_thumb_function_name
= FALSE
;
970 /* Literal pool structure. Held on a per-section
971 and per-sub-section basis. */
973 #define MAX_LITERAL_POOL_SIZE 1024
974 typedef struct literal_pool
976 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
977 unsigned int next_free_entry
;
983 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
985 struct literal_pool
* next
;
986 unsigned int alignment
;
989 /* Pointer to a linked list of literal pools. */
990 literal_pool
* list_of_pools
= NULL
;
992 typedef enum asmfunc_states
995 WAITING_ASMFUNC_NAME
,
999 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
1002 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
1004 static struct current_pred now_pred
;
1008 now_pred_compatible (int cond
)
1010 return (cond
& ~1) == (now_pred
.cc
& ~1);
1014 conditional_insn (void)
1016 return inst
.cond
!= COND_ALWAYS
;
1019 static int in_pred_block (void);
1021 static int handle_pred_state (void);
1023 static void force_automatic_it_block_close (void);
1025 static void it_fsm_post_encode (void);
1027 #define set_pred_insn_type(type) \
1030 inst.pred_insn_type = type; \
1031 if (handle_pred_state () == FAIL) \
1036 #define set_pred_insn_type_nonvoid(type, failret) \
1039 inst.pred_insn_type = type; \
1040 if (handle_pred_state () == FAIL) \
1045 #define set_pred_insn_type_last() \
1048 if (inst.cond == COND_ALWAYS) \
1049 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1051 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1055 /* Toggle value[pos]. */
1056 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1060 /* This array holds the chars that always start a comment. If the
1061 pre-processor is disabled, these aren't very useful. */
1062 char arm_comment_chars
[] = "@";
1064 /* This array holds the chars that only start a comment at the beginning of
1065 a line. If the line seems to have the form '# 123 filename'
1066 .line and .file directives will appear in the pre-processed output. */
1067 /* Note that input_file.c hand checks for '#' at the beginning of the
1068 first line of the input file. This is because the compiler outputs
1069 #NO_APP at the beginning of its output. */
1070 /* Also note that comments like this one will always work. */
1071 const char line_comment_chars
[] = "#";
1073 char arm_line_separator_chars
[] = ";";
1075 /* Chars that can be used to separate mant
1076 from exp in floating point numbers. */
1077 const char EXP_CHARS
[] = "eE";
1079 /* Chars that mean this number is a floating point constant. */
1080 /* As in 0f12.456 */
1081 /* or 0d1.2345e12 */
1083 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1085 /* Prefix characters that indicate the start of an immediate
1087 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1089 /* Separator character handling. */
1091 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1093 enum fp_16bit_format
1095 ARM_FP16_FORMAT_IEEE
= 0x1,
1096 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1097 ARM_FP16_FORMAT_DEFAULT
= 0x3
1100 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1104 skip_past_char (char ** str
, char c
)
1106 /* PR gas/14987: Allow for whitespace before the expected character. */
1107 skip_whitespace (*str
);
1118 #define skip_past_comma(str) skip_past_char (str, ',')
1120 /* Arithmetic expressions (possibly involving symbols). */
1122 /* Return TRUE if anything in the expression is a bignum. */
1125 walk_no_bignums (symbolS
* sp
)
1127 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1130 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1132 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1133 || (symbol_get_value_expression (sp
)->X_op_symbol
1134 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1140 static bfd_boolean in_my_get_expression
= FALSE
;
1142 /* Third argument to my_get_expression. */
1143 #define GE_NO_PREFIX 0
1144 #define GE_IMM_PREFIX 1
1145 #define GE_OPT_PREFIX 2
1146 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1147 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1148 #define GE_OPT_PREFIX_BIG 3
1151 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1155 /* In unified syntax, all prefixes are optional. */
1157 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1160 switch (prefix_mode
)
1162 case GE_NO_PREFIX
: break;
1164 if (!is_immediate_prefix (**str
))
1166 inst
.error
= _("immediate expression requires a # prefix");
1172 case GE_OPT_PREFIX_BIG
:
1173 if (is_immediate_prefix (**str
))
1180 memset (ep
, 0, sizeof (expressionS
));
1182 save_in
= input_line_pointer
;
1183 input_line_pointer
= *str
;
1184 in_my_get_expression
= TRUE
;
1186 in_my_get_expression
= FALSE
;
1188 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1190 /* We found a bad or missing expression in md_operand(). */
1191 *str
= input_line_pointer
;
1192 input_line_pointer
= save_in
;
1193 if (inst
.error
== NULL
)
1194 inst
.error
= (ep
->X_op
== O_absent
1195 ? _("missing expression") :_("bad expression"));
1199 /* Get rid of any bignums now, so that we don't generate an error for which
1200 we can't establish a line number later on. Big numbers are never valid
1201 in instructions, which is where this routine is always called. */
1202 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1203 && (ep
->X_op
== O_big
1204 || (ep
->X_add_symbol
1205 && (walk_no_bignums (ep
->X_add_symbol
)
1207 && walk_no_bignums (ep
->X_op_symbol
))))))
1209 inst
.error
= _("invalid constant");
1210 *str
= input_line_pointer
;
1211 input_line_pointer
= save_in
;
1215 *str
= input_line_pointer
;
1216 input_line_pointer
= save_in
;
1220 /* Turn a string in input_line_pointer into a floating point constant
1221 of type TYPE, and store the appropriate bytes in *LITP. The number
1222 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1223 returned, or NULL on OK.
1225 Note that fp constants aren't represent in the normal way on the ARM.
1226 In big endian mode, things are as expected. However, in little endian
1227 mode fp constants are big-endian word-wise, and little-endian byte-wise
1228 within the words. For example, (double) 1.1 in big endian mode is
1229 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1230 the byte sequence 99 99 f1 3f 9a 99 99 99.
1232 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1235 md_atof (int type
, char * litP
, int * sizeP
)
1238 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1249 /* If this is a bfloat16, then parse it slightly differently, as it
1250 does not follow the IEEE specification for floating point numbers
1254 FLONUM_TYPE generic_float
;
1256 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
1259 input_line_pointer
= t
;
1261 return _("invalid floating point number");
1263 switch (generic_float
.sign
)
1276 /* bfloat16 has two types of NaN - quiet and signalling.
1277 Quiet NaN has bit[6] == 1 && faction != 0, whereas
1278 signalling NaN's have bit[0] == 0 && fraction != 0.
1279 Chosen this specific encoding as it is the same form
1280 as used by other IEEE 754 encodings in GAS. */
1291 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
1321 return _("Unrecognized or unsupported floating point constant");
1324 t
= atof_ieee (input_line_pointer
, type
, words
);
1326 input_line_pointer
= t
;
1327 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1329 if (target_big_endian
|| prec
== 1)
1330 for (i
= 0; i
< prec
; i
++)
1332 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1333 litP
+= sizeof (LITTLENUM_TYPE
);
1335 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1336 for (i
= prec
- 1; i
>= 0; i
--)
1338 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1339 litP
+= sizeof (LITTLENUM_TYPE
);
1342 /* For a 4 byte float the order of elements in `words' is 1 0.
1343 For an 8 byte float the order is 1 0 3 2. */
1344 for (i
= 0; i
< prec
; i
+= 2)
1346 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1347 sizeof (LITTLENUM_TYPE
));
1348 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1349 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1350 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1356 /* We handle all bad expressions here, so that we can report the faulty
1357 instruction in the error message. */
1360 md_operand (expressionS
* exp
)
1362 if (in_my_get_expression
)
1363 exp
->X_op
= O_illegal
;
1366 /* Immediate values. */
1369 /* Generic immediate-value read function for use in directives.
1370 Accepts anything that 'expression' can fold to a constant.
1371 *val receives the number. */
1374 immediate_for_directive (int *val
)
1377 exp
.X_op
= O_illegal
;
1379 if (is_immediate_prefix (*input_line_pointer
))
1381 input_line_pointer
++;
1385 if (exp
.X_op
!= O_constant
)
1387 as_bad (_("expected #constant"));
1388 ignore_rest_of_line ();
1391 *val
= exp
.X_add_number
;
1396 /* Register parsing. */
1398 /* Generic register parser. CCP points to what should be the
1399 beginning of a register name. If it is indeed a valid register
1400 name, advance CCP over it and return the reg_entry structure;
1401 otherwise return NULL. Does not issue diagnostics. */
1403 static struct reg_entry
*
1404 arm_reg_parse_multi (char **ccp
)
1408 struct reg_entry
*reg
;
1410 skip_whitespace (start
);
1412 #ifdef REGISTER_PREFIX
1413 if (*start
!= REGISTER_PREFIX
)
1417 #ifdef OPTIONAL_REGISTER_PREFIX
1418 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1423 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1428 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1430 reg
= (struct reg_entry
*) str_hash_find_n (arm_reg_hsh
, start
, p
- start
);
1440 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1441 enum arm_reg_type type
)
1443 /* Alternative syntaxes are accepted for a few register classes. */
1450 /* Generic coprocessor register names are allowed for these. */
1451 if (reg
&& reg
->type
== REG_TYPE_CN
)
1456 /* For backward compatibility, a bare number is valid here. */
1458 unsigned long processor
= strtoul (start
, ccp
, 10);
1459 if (*ccp
!= start
&& processor
<= 15)
1464 case REG_TYPE_MMXWC
:
1465 /* WC includes WCG. ??? I'm not sure this is true for all
1466 instructions that take WC registers. */
1467 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1478 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1479 return value is the register number or FAIL. */
1482 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1485 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1488 /* Do not allow a scalar (reg+index) to parse as a register. */
1489 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1492 if (reg
&& reg
->type
== type
)
1495 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1502 /* Parse a Neon type specifier. *STR should point at the leading '.'
1503 character. Does no verification at this stage that the type fits the opcode
1510 Can all be legally parsed by this function.
1512 Fills in neon_type struct pointer with parsed information, and updates STR
1513 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1514 type, FAIL if not. */
1517 parse_neon_type (struct neon_type
*type
, char **str
)
1524 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1526 enum neon_el_type thistype
= NT_untyped
;
1527 unsigned thissize
= -1u;
1534 /* Just a size without an explicit type. */
1538 switch (TOLOWER (*ptr
))
1540 case 'i': thistype
= NT_integer
; break;
1541 case 'f': thistype
= NT_float
; break;
1542 case 'p': thistype
= NT_poly
; break;
1543 case 's': thistype
= NT_signed
; break;
1544 case 'u': thistype
= NT_unsigned
; break;
1546 thistype
= NT_float
;
1551 thistype
= NT_bfloat
;
1552 switch (TOLOWER (*(++ptr
)))
1556 thissize
= strtoul (ptr
, &ptr
, 10);
1559 as_bad (_("bad size %d in type specifier"), thissize
);
1563 case '0': case '1': case '2': case '3': case '4':
1564 case '5': case '6': case '7': case '8': case '9':
1566 as_bad (_("unexpected type character `b' -- did you mean `bf'?"));
1573 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1579 /* .f is an abbreviation for .f32. */
1580 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1585 thissize
= strtoul (ptr
, &ptr
, 10);
1587 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1590 as_bad (_("bad size %d in type specifier"), thissize
);
1598 type
->el
[type
->elems
].type
= thistype
;
1599 type
->el
[type
->elems
].size
= thissize
;
1604 /* Empty/missing type is not a successful parse. */
1605 if (type
->elems
== 0)
1613 /* Errors may be set multiple times during parsing or bit encoding
1614 (particularly in the Neon bits), but usually the earliest error which is set
1615 will be the most meaningful. Avoid overwriting it with later (cascading)
1616 errors by calling this function. */
1619 first_error (const char *err
)
1625 /* Parse a single type, e.g. ".s32", leading period included. */
1627 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1630 struct neon_type optype
;
1634 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1636 if (optype
.elems
== 1)
1637 *vectype
= optype
.el
[0];
1640 first_error (_("only one type should be specified for operand"));
1646 first_error (_("vector type expected"));
1658 /* Special meanings for indices (which have a range of 0-7), which will fit into
1661 #define NEON_ALL_LANES 15
1662 #define NEON_INTERLEAVE_LANES 14
1664 /* Record a use of the given feature. */
1666 record_feature_use (const arm_feature_set
*feature
)
1669 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1671 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1674 /* If the given feature available in the selected CPU, mark it as used.
1675 Returns TRUE iff feature is available. */
1677 mark_feature_used (const arm_feature_set
*feature
)
1680 /* Do not support the use of MVE only instructions when in auto-detection or
1682 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1683 && ARM_CPU_IS_ANY (cpu_variant
))
1685 first_error (BAD_MVE_AUTO
);
1688 /* Ensure the option is valid on the current architecture. */
1689 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1692 /* Add the appropriate architecture feature for the barrier option used.
1694 record_feature_use (feature
);
1699 /* Parse either a register or a scalar, with an optional type. Return the
1700 register number, and optionally fill in the actual type of the register
1701 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1702 type/index information in *TYPEINFO. */
1705 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1706 enum arm_reg_type
*rtype
,
1707 struct neon_typed_alias
*typeinfo
)
1710 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1711 struct neon_typed_alias atype
;
1712 struct neon_type_el parsetype
;
1716 atype
.eltype
.type
= NT_invtype
;
1717 atype
.eltype
.size
= -1;
1719 /* Try alternate syntax for some types of register. Note these are mutually
1720 exclusive with the Neon syntax extensions. */
1723 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1731 /* Undo polymorphism when a set of register types may be accepted. */
1732 if ((type
== REG_TYPE_NDQ
1733 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1734 || (type
== REG_TYPE_VFSD
1735 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1736 || (type
== REG_TYPE_NSDQ
1737 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1738 || reg
->type
== REG_TYPE_NQ
))
1739 || (type
== REG_TYPE_NSD
1740 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1741 || (type
== REG_TYPE_MMXWC
1742 && (reg
->type
== REG_TYPE_MMXWCG
)))
1743 type
= (enum arm_reg_type
) reg
->type
;
1745 if (type
== REG_TYPE_MQ
)
1747 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1750 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1753 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1755 first_error (_("expected MVE register [q0..q7]"));
1760 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1761 && (type
== REG_TYPE_NQ
))
1765 if (type
!= reg
->type
)
1771 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1773 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1775 first_error (_("can't redefine type for operand"));
1778 atype
.defined
|= NTA_HASTYPE
;
1779 atype
.eltype
= parsetype
;
1782 if (skip_past_char (&str
, '[') == SUCCESS
)
1784 if (type
!= REG_TYPE_VFD
1785 && !(type
== REG_TYPE_VFS
1786 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1787 && !(type
== REG_TYPE_NQ
1788 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1790 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1791 first_error (_("only D and Q registers may be indexed"));
1793 first_error (_("only D registers may be indexed"));
1797 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1799 first_error (_("can't change index for operand"));
1803 atype
.defined
|= NTA_HASINDEX
;
1805 if (skip_past_char (&str
, ']') == SUCCESS
)
1806 atype
.index
= NEON_ALL_LANES
;
1811 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1813 if (exp
.X_op
!= O_constant
)
1815 first_error (_("constant expression required"));
1819 if (skip_past_char (&str
, ']') == FAIL
)
1822 atype
.index
= exp
.X_add_number
;
1837 /* Like arm_reg_parse, but also allow the following extra features:
1838 - If RTYPE is non-zero, return the (possibly restricted) type of the
1839 register (e.g. Neon double or quad reg when either has been requested).
1840 - If this is a Neon vector type with additional type information, fill
1841 in the struct pointed to by VECTYPE (if non-NULL).
1842 This function will fault on encountering a scalar. */
1845 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1846 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1848 struct neon_typed_alias atype
;
1850 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1855 /* Do not allow regname(... to parse as a register. */
1859 /* Do not allow a scalar (reg+index) to parse as a register. */
1860 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1862 first_error (_("register operand expected, but got scalar"));
1867 *vectype
= atype
.eltype
;
1874 #define NEON_SCALAR_REG(X) ((X) >> 4)
1875 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1877 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1878 have enough information to be able to do a good job bounds-checking. So, we
1879 just do easy checks here, and do further checks later. */
1882 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1883 arm_reg_type reg_type
)
1887 struct neon_typed_alias atype
;
1890 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1908 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1911 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1913 first_error (_("scalar must have an index"));
1916 else if (atype
.index
>= reg_size
/ elsize
)
1918 first_error (_("scalar index out of range"));
1923 *type
= atype
.eltype
;
1927 return reg
* 16 + atype
.index
;
1930 /* Types of registers in a list. */
1943 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1946 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1952 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1954 /* We come back here if we get ranges concatenated by '+' or '|'. */
1957 skip_whitespace (str
);
1970 const char apsr_str
[] = "apsr";
1971 int apsr_str_len
= strlen (apsr_str
);
1973 reg
= arm_reg_parse (&str
, REG_TYPE_RN
);
1974 if (etype
== REGLIST_CLRM
)
1976 if (reg
== REG_SP
|| reg
== REG_PC
)
1978 else if (reg
== FAIL
1979 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1980 && !ISALPHA (*(str
+ apsr_str_len
)))
1983 str
+= apsr_str_len
;
1988 first_error (_("r0-r12, lr or APSR expected"));
1992 else /* etype == REGLIST_RN. */
1996 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
2007 first_error (_("bad range in register list"));
2011 for (i
= cur_reg
+ 1; i
< reg
; i
++)
2013 if (range
& (1 << i
))
2015 (_("Warning: duplicated register (r%d) in register list"),
2023 if (range
& (1 << reg
))
2024 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
2026 else if (reg
<= cur_reg
)
2027 as_tsktsk (_("Warning: register range not in ascending order"));
2032 while (skip_past_comma (&str
) != FAIL
2033 || (in_range
= 1, *str
++ == '-'));
2036 if (skip_past_char (&str
, '}') == FAIL
)
2038 first_error (_("missing `}'"));
2042 else if (etype
== REGLIST_RN
)
2046 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
2049 if (exp
.X_op
== O_constant
)
2051 if (exp
.X_add_number
2052 != (exp
.X_add_number
& 0x0000ffff))
2054 inst
.error
= _("invalid register mask");
2058 if ((range
& exp
.X_add_number
) != 0)
2060 int regno
= range
& exp
.X_add_number
;
2063 regno
= (1 << regno
) - 1;
2065 (_("Warning: duplicated register (r%d) in register list"),
2069 range
|= exp
.X_add_number
;
2073 if (inst
.relocs
[0].type
!= 0)
2075 inst
.error
= _("expression too complex");
2079 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
2080 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
2081 inst
.relocs
[0].pc_rel
= 0;
2085 if (*str
== '|' || *str
== '+')
2091 while (another_range
);
2097 /* Parse a VFP register list. If the string is invalid return FAIL.
2098 Otherwise return the number of registers, and set PBASE to the first
2099 register. Parses registers of type ETYPE.
2100 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2101 - Q registers can be used to specify pairs of D registers
2102 - { } can be omitted from around a singleton register list
2103 FIXME: This is not implemented, as it would require backtracking in
2106 This could be done (the meaning isn't really ambiguous), but doesn't
2107 fit in well with the current parsing framework.
2108 - 32 D registers may be used (also true for VFPv3).
2109 FIXME: Types are ignored in these register lists, which is probably a
2113 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2114 bfd_boolean
*partial_match
)
2119 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2123 unsigned long mask
= 0;
2125 bfd_boolean vpr_seen
= FALSE
;
2126 bfd_boolean expect_vpr
=
2127 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2129 if (skip_past_char (&str
, '{') == FAIL
)
2131 inst
.error
= _("expecting {");
2138 case REGLIST_VFP_S_VPR
:
2139 regtype
= REG_TYPE_VFS
;
2144 case REGLIST_VFP_D_VPR
:
2145 regtype
= REG_TYPE_VFD
;
2148 case REGLIST_NEON_D
:
2149 regtype
= REG_TYPE_NDQ
;
2156 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2158 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2159 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2163 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2166 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2173 base_reg
= max_regs
;
2174 *partial_match
= FALSE
;
2178 int setmask
= 1, addregs
= 1;
2179 const char vpr_str
[] = "vpr";
2180 int vpr_str_len
= strlen (vpr_str
);
2182 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2186 if (new_base
== FAIL
2187 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2188 && !ISALPHA (*(str
+ vpr_str_len
))
2194 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2198 first_error (_("VPR expected last"));
2201 else if (new_base
== FAIL
)
2203 if (regtype
== REG_TYPE_VFS
)
2204 first_error (_("VFP single precision register or VPR "
2206 else /* regtype == REG_TYPE_VFD. */
2207 first_error (_("VFP/Neon double precision register or VPR "
2212 else if (new_base
== FAIL
)
2214 first_error (_(reg_expected_msgs
[regtype
]));
2218 *partial_match
= TRUE
;
2222 if (new_base
>= max_regs
)
2224 first_error (_("register out of range in list"));
2228 /* Note: a value of 2 * n is returned for the register Q<n>. */
2229 if (regtype
== REG_TYPE_NQ
)
2235 if (new_base
< base_reg
)
2236 base_reg
= new_base
;
2238 if (mask
& (setmask
<< new_base
))
2240 first_error (_("invalid register list"));
2244 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2246 as_tsktsk (_("register list not in ascending order"));
2250 mask
|= setmask
<< new_base
;
2253 if (*str
== '-') /* We have the start of a range expression */
2259 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2262 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2266 if (high_range
>= max_regs
)
2268 first_error (_("register out of range in list"));
2272 if (regtype
== REG_TYPE_NQ
)
2273 high_range
= high_range
+ 1;
2275 if (high_range
<= new_base
)
2277 inst
.error
= _("register range not in ascending order");
2281 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2283 if (mask
& (setmask
<< new_base
))
2285 inst
.error
= _("invalid register list");
2289 mask
|= setmask
<< new_base
;
2294 while (skip_past_comma (&str
) != FAIL
);
2298 /* Sanity check -- should have raised a parse error above. */
2299 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2304 if (expect_vpr
&& !vpr_seen
)
2306 first_error (_("VPR expected last"));
2310 /* Final test -- the registers must be consecutive. */
2312 for (i
= 0; i
< count
; i
++)
2314 if ((mask
& (1u << i
)) == 0)
2316 inst
.error
= _("non-contiguous register range");
2326 /* True if two alias types are the same. */
2329 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2337 if (a
->defined
!= b
->defined
)
2340 if ((a
->defined
& NTA_HASTYPE
) != 0
2341 && (a
->eltype
.type
!= b
->eltype
.type
2342 || a
->eltype
.size
!= b
->eltype
.size
))
2345 if ((a
->defined
& NTA_HASINDEX
) != 0
2346 && (a
->index
!= b
->index
))
2352 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2353 The base register is put in *PBASE.
2354 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2356 The register stride (minus one) is put in bit 4 of the return value.
2357 Bits [6:5] encode the list length (minus one).
2358 The type of the list elements is put in *ELTYPE, if non-NULL. */
2360 #define NEON_LANE(X) ((X) & 0xf)
2361 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2362 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2365 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2367 struct neon_type_el
*eltype
)
2374 int leading_brace
= 0;
2375 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2376 const char *const incr_error
= mve
? _("register stride must be 1") :
2377 _("register stride must be 1 or 2");
2378 const char *const type_error
= _("mismatched element/structure types in list");
2379 struct neon_typed_alias firsttype
;
2380 firsttype
.defined
= 0;
2381 firsttype
.eltype
.type
= NT_invtype
;
2382 firsttype
.eltype
.size
= -1;
2383 firsttype
.index
= -1;
2385 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2390 struct neon_typed_alias atype
;
2392 rtype
= REG_TYPE_MQ
;
2393 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2397 first_error (_(reg_expected_msgs
[rtype
]));
2404 if (rtype
== REG_TYPE_NQ
)
2410 else if (reg_incr
== -1)
2412 reg_incr
= getreg
- base_reg
;
2413 if (reg_incr
< 1 || reg_incr
> 2)
2415 first_error (_(incr_error
));
2419 else if (getreg
!= base_reg
+ reg_incr
* count
)
2421 first_error (_(incr_error
));
2425 if (! neon_alias_types_same (&atype
, &firsttype
))
2427 first_error (_(type_error
));
2431 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2435 struct neon_typed_alias htype
;
2436 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2438 lane
= NEON_INTERLEAVE_LANES
;
2439 else if (lane
!= NEON_INTERLEAVE_LANES
)
2441 first_error (_(type_error
));
2446 else if (reg_incr
!= 1)
2448 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2452 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2455 first_error (_(reg_expected_msgs
[rtype
]));
2458 if (! neon_alias_types_same (&htype
, &firsttype
))
2460 first_error (_(type_error
));
2463 count
+= hireg
+ dregs
- getreg
;
2467 /* If we're using Q registers, we can't use [] or [n] syntax. */
2468 if (rtype
== REG_TYPE_NQ
)
2474 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2478 else if (lane
!= atype
.index
)
2480 first_error (_(type_error
));
2484 else if (lane
== -1)
2485 lane
= NEON_INTERLEAVE_LANES
;
2486 else if (lane
!= NEON_INTERLEAVE_LANES
)
2488 first_error (_(type_error
));
2493 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2495 /* No lane set by [x]. We must be interleaving structures. */
2497 lane
= NEON_INTERLEAVE_LANES
;
2500 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2501 || (count
> 1 && reg_incr
== -1))
2503 first_error (_("error parsing element/structure list"));
2507 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2509 first_error (_("expected }"));
2517 *eltype
= firsttype
.eltype
;
2522 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2525 /* Parse an explicit relocation suffix on an expression. This is
2526 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2527 arm_reloc_hsh contains no entries, so this function can only
2528 succeed if there is no () after the word. Returns -1 on error,
2529 BFD_RELOC_UNUSED if there wasn't any suffix. */
2532 parse_reloc (char **str
)
2534 struct reloc_entry
*r
;
2538 return BFD_RELOC_UNUSED
;
2543 while (*q
&& *q
!= ')' && *q
!= ',')
2548 if ((r
= (struct reloc_entry
*)
2549 str_hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2556 /* Directives: register aliases. */
2558 static struct reg_entry
*
2559 insert_reg_alias (char *str
, unsigned number
, int type
)
2561 struct reg_entry
*new_reg
;
2564 if ((new_reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, str
)) != 0)
2566 if (new_reg
->builtin
)
2567 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2569 /* Only warn about a redefinition if it's not defined as the
2571 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2572 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2577 name
= xstrdup (str
);
2578 new_reg
= XNEW (struct reg_entry
);
2580 new_reg
->name
= name
;
2581 new_reg
->number
= number
;
2582 new_reg
->type
= type
;
2583 new_reg
->builtin
= FALSE
;
2584 new_reg
->neon
= NULL
;
2586 str_hash_insert (arm_reg_hsh
, name
, new_reg
, 0);
2592 insert_neon_reg_alias (char *str
, int number
, int type
,
2593 struct neon_typed_alias
*atype
)
2595 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2599 first_error (_("attempt to redefine typed alias"));
2605 reg
->neon
= XNEW (struct neon_typed_alias
);
2606 *reg
->neon
= *atype
;
2610 /* Look for the .req directive. This is of the form:
2612 new_register_name .req existing_register_name
2614 If we find one, or if it looks sufficiently like one that we want to
2615 handle any error here, return TRUE. Otherwise return FALSE. */
2618 create_register_alias (char * newname
, char *p
)
2620 struct reg_entry
*old
;
2621 char *oldname
, *nbuf
;
2624 /* The input scrubber ensures that whitespace after the mnemonic is
2625 collapsed to single spaces. */
2627 if (strncmp (oldname
, " .req ", 6) != 0)
2631 if (*oldname
== '\0')
2634 old
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, oldname
);
2637 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2641 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2642 the desired alias name, and p points to its end. If not, then
2643 the desired alias name is in the global original_case_string. */
2644 #ifdef TC_CASE_SENSITIVE
2647 newname
= original_case_string
;
2648 nlen
= strlen (newname
);
2651 nbuf
= xmemdup0 (newname
, nlen
);
2653 /* Create aliases under the new name as stated; an all-lowercase
2654 version of the new name; and an all-uppercase version of the new
2656 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2658 for (p
= nbuf
; *p
; p
++)
2661 if (strncmp (nbuf
, newname
, nlen
))
2663 /* If this attempt to create an additional alias fails, do not bother
2664 trying to create the all-lower case alias. We will fail and issue
2665 a second, duplicate error message. This situation arises when the
2666 programmer does something like:
2669 The second .req creates the "Foo" alias but then fails to create
2670 the artificial FOO alias because it has already been created by the
2672 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2679 for (p
= nbuf
; *p
; p
++)
2682 if (strncmp (nbuf
, newname
, nlen
))
2683 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2690 /* Create a Neon typed/indexed register alias using directives, e.g.:
2695 These typed registers can be used instead of the types specified after the
2696 Neon mnemonic, so long as all operands given have types. Types can also be
2697 specified directly, e.g.:
2698 vadd d0.s32, d1.s32, d2.s32 */
2701 create_neon_reg_alias (char *newname
, char *p
)
2703 enum arm_reg_type basetype
;
2704 struct reg_entry
*basereg
;
2705 struct reg_entry mybasereg
;
2706 struct neon_type ntype
;
2707 struct neon_typed_alias typeinfo
;
2708 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2711 typeinfo
.defined
= 0;
2712 typeinfo
.eltype
.type
= NT_invtype
;
2713 typeinfo
.eltype
.size
= -1;
2714 typeinfo
.index
= -1;
2718 if (strncmp (p
, " .dn ", 5) == 0)
2719 basetype
= REG_TYPE_VFD
;
2720 else if (strncmp (p
, " .qn ", 5) == 0)
2721 basetype
= REG_TYPE_NQ
;
2730 basereg
= arm_reg_parse_multi (&p
);
2732 if (basereg
&& basereg
->type
!= basetype
)
2734 as_bad (_("bad type for register"));
2738 if (basereg
== NULL
)
2741 /* Try parsing as an integer. */
2742 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2743 if (exp
.X_op
!= O_constant
)
2745 as_bad (_("expression must be constant"));
2748 basereg
= &mybasereg
;
2749 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2755 typeinfo
= *basereg
->neon
;
2757 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2759 /* We got a type. */
2760 if (typeinfo
.defined
& NTA_HASTYPE
)
2762 as_bad (_("can't redefine the type of a register alias"));
2766 typeinfo
.defined
|= NTA_HASTYPE
;
2767 if (ntype
.elems
!= 1)
2769 as_bad (_("you must specify a single type only"));
2772 typeinfo
.eltype
= ntype
.el
[0];
2775 if (skip_past_char (&p
, '[') == SUCCESS
)
2778 /* We got a scalar index. */
2780 if (typeinfo
.defined
& NTA_HASINDEX
)
2782 as_bad (_("can't redefine the index of a scalar alias"));
2786 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2788 if (exp
.X_op
!= O_constant
)
2790 as_bad (_("scalar index must be constant"));
2794 typeinfo
.defined
|= NTA_HASINDEX
;
2795 typeinfo
.index
= exp
.X_add_number
;
2797 if (skip_past_char (&p
, ']') == FAIL
)
2799 as_bad (_("expecting ]"));
2804 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2805 the desired alias name, and p points to its end. If not, then
2806 the desired alias name is in the global original_case_string. */
2807 #ifdef TC_CASE_SENSITIVE
2808 namelen
= nameend
- newname
;
2810 newname
= original_case_string
;
2811 namelen
= strlen (newname
);
2814 namebuf
= xmemdup0 (newname
, namelen
);
2816 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2817 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2819 /* Insert name in all uppercase. */
2820 for (p
= namebuf
; *p
; p
++)
2823 if (strncmp (namebuf
, newname
, namelen
))
2824 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2825 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2827 /* Insert name in all lowercase. */
2828 for (p
= namebuf
; *p
; p
++)
2831 if (strncmp (namebuf
, newname
, namelen
))
2832 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2833 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2839 /* Should never be called, as .req goes between the alias and the
2840 register name, not at the beginning of the line. */
2843 s_req (int a ATTRIBUTE_UNUSED
)
2845 as_bad (_("invalid syntax for .req directive"));
2849 s_dn (int a ATTRIBUTE_UNUSED
)
2851 as_bad (_("invalid syntax for .dn directive"));
2855 s_qn (int a ATTRIBUTE_UNUSED
)
2857 as_bad (_("invalid syntax for .qn directive"));
2860 /* The .unreq directive deletes an alias which was previously defined
2861 by .req. For example:
2867 s_unreq (int a ATTRIBUTE_UNUSED
)
2872 name
= input_line_pointer
;
2874 while (*input_line_pointer
!= 0
2875 && *input_line_pointer
!= ' '
2876 && *input_line_pointer
!= '\n')
2877 ++input_line_pointer
;
2879 saved_char
= *input_line_pointer
;
2880 *input_line_pointer
= 0;
2883 as_bad (_("invalid syntax for .unreq directive"));
2886 struct reg_entry
*reg
2887 = (struct reg_entry
*) str_hash_find (arm_reg_hsh
, name
);
2890 as_bad (_("unknown register alias '%s'"), name
);
2891 else if (reg
->builtin
)
2892 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2899 str_hash_delete (arm_reg_hsh
, name
);
2900 free ((char *) reg
->name
);
2904 /* Also locate the all upper case and all lower case versions.
2905 Do not complain if we cannot find one or the other as it
2906 was probably deleted above. */
2908 nbuf
= strdup (name
);
2909 for (p
= nbuf
; *p
; p
++)
2911 reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, nbuf
);
2914 str_hash_delete (arm_reg_hsh
, nbuf
);
2915 free ((char *) reg
->name
);
2920 for (p
= nbuf
; *p
; p
++)
2922 reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, nbuf
);
2925 str_hash_delete (arm_reg_hsh
, nbuf
);
2926 free ((char *) reg
->name
);
2935 *input_line_pointer
= saved_char
;
2936 demand_empty_rest_of_line ();
2939 /* Directives: Instruction set selection. */
2942 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2943 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2944 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2945 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2947 /* Create a new mapping symbol for the transition to STATE. */
2950 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2953 const char * symname
;
2960 type
= BSF_NO_FLAGS
;
2964 type
= BSF_NO_FLAGS
;
2968 type
= BSF_NO_FLAGS
;
2974 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
2975 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2980 THUMB_SET_FUNC (symbolP
, 0);
2981 ARM_SET_THUMB (symbolP
, 0);
2982 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2986 THUMB_SET_FUNC (symbolP
, 1);
2987 ARM_SET_THUMB (symbolP
, 1);
2988 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2996 /* Save the mapping symbols for future reference. Also check that
2997 we do not place two mapping symbols at the same offset within a
2998 frag. We'll handle overlap between frags in
2999 check_mapping_symbols.
3001 If .fill or other data filling directive generates zero sized data,
3002 the mapping symbol for the following code will have the same value
3003 as the one generated for the data filling directive. In this case,
3004 we replace the old symbol with the new one at the same address. */
3007 if (frag
->tc_frag_data
.first_map
!= NULL
)
3009 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
3010 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
3012 frag
->tc_frag_data
.first_map
= symbolP
;
3014 if (frag
->tc_frag_data
.last_map
!= NULL
)
3016 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
3017 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
3018 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
3020 frag
->tc_frag_data
.last_map
= symbolP
;
3023 /* We must sometimes convert a region marked as code to data during
3024 code alignment, if an odd number of bytes have to be padded. The
3025 code mapping symbol is pushed to an aligned address. */
3028 insert_data_mapping_symbol (enum mstate state
,
3029 valueT value
, fragS
*frag
, offsetT bytes
)
3031 /* If there was already a mapping symbol, remove it. */
3032 if (frag
->tc_frag_data
.last_map
!= NULL
3033 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
3035 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
3039 know (frag
->tc_frag_data
.first_map
== symp
);
3040 frag
->tc_frag_data
.first_map
= NULL
;
3042 frag
->tc_frag_data
.last_map
= NULL
;
3043 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
3046 make_mapping_symbol (MAP_DATA
, value
, frag
);
3047 make_mapping_symbol (state
, value
+ bytes
, frag
);
3050 static void mapping_state_2 (enum mstate state
, int max_chars
);
3052 /* Set the mapping state to STATE. Only call this when about to
3053 emit some STATE bytes to the file. */
3055 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
3057 mapping_state (enum mstate state
)
3059 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3061 if (mapstate
== state
)
3062 /* The mapping symbol has already been emitted.
3063 There is nothing else to do. */
3066 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
3068 All ARM instructions require 4-byte alignment.
3069 (Almost) all Thumb instructions require 2-byte alignment.
3071 When emitting instructions into any section, mark the section
3074 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
3075 but themselves require 2-byte alignment; this applies to some
3076 PC- relative forms. However, these cases will involve implicit
3077 literal pool generation or an explicit .align >=2, both of
3078 which will cause the section to me marked with sufficient
3079 alignment. Thus, we don't handle those cases here. */
3080 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
3082 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
3083 /* This case will be evaluated later. */
3086 mapping_state_2 (state
, 0);
3089 /* Same as mapping_state, but MAX_CHARS bytes have already been
3090 allocated. Put the mapping symbol that far back. */
3093 mapping_state_2 (enum mstate state
, int max_chars
)
3095 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3097 if (!SEG_NORMAL (now_seg
))
3100 if (mapstate
== state
)
3101 /* The mapping symbol has already been emitted.
3102 There is nothing else to do. */
3105 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
3106 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3108 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3109 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3112 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3115 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3116 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3120 #define mapping_state(x) ((void)0)
3121 #define mapping_state_2(x, y) ((void)0)
3124 /* Find the real, Thumb encoded start of a Thumb function. */
3128 find_real_start (symbolS
* symbolP
)
3131 const char * name
= S_GET_NAME (symbolP
);
3132 symbolS
* new_target
;
3134 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3135 #define STUB_NAME ".real_start_of"
3140 /* The compiler may generate BL instructions to local labels because
3141 it needs to perform a branch to a far away location. These labels
3142 do not have a corresponding ".real_start_of" label. We check
3143 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3144 the ".real_start_of" convention for nonlocal branches. */
3145 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3148 real_start
= concat (STUB_NAME
, name
, NULL
);
3149 new_target
= symbol_find (real_start
);
3152 if (new_target
== NULL
)
3154 as_warn (_("Failed to find real start of function: %s\n"), name
);
3155 new_target
= symbolP
;
3163 opcode_select (int width
)
3170 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3171 as_bad (_("selected processor does not support THUMB opcodes"));
3174 /* No need to force the alignment, since we will have been
3175 coming from ARM mode, which is word-aligned. */
3176 record_alignment (now_seg
, 1);
3183 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3184 as_bad (_("selected processor does not support ARM opcodes"));
3189 frag_align (2, 0, 0);
3191 record_alignment (now_seg
, 1);
3196 as_bad (_("invalid instruction size selected (%d)"), width
);
3201 s_arm (int ignore ATTRIBUTE_UNUSED
)
3204 demand_empty_rest_of_line ();
3208 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3211 demand_empty_rest_of_line ();
3215 s_code (int unused ATTRIBUTE_UNUSED
)
3219 temp
= get_absolute_expression ();
3224 opcode_select (temp
);
3228 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3233 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3235 /* If we are not already in thumb mode go into it, EVEN if
3236 the target processor does not support thumb instructions.
3237 This is used by gcc/config/arm/lib1funcs.asm for example
3238 to compile interworking support functions even if the
3239 target processor should not support interworking. */
3243 record_alignment (now_seg
, 1);
3246 demand_empty_rest_of_line ();
3250 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3254 /* The following label is the name/address of the start of a Thumb function.
3255 We need to know this for the interworking support. */
3256 label_is_thumb_function_name
= TRUE
;
3259 /* Perform a .set directive, but also mark the alias as
3260 being a thumb function. */
3263 s_thumb_set (int equiv
)
3265 /* XXX the following is a duplicate of the code for s_set() in read.c
3266 We cannot just call that code as we need to get at the symbol that
3273 /* Especial apologies for the random logic:
3274 This just grew, and could be parsed much more simply!
3276 delim
= get_symbol_name (& name
);
3277 end_name
= input_line_pointer
;
3278 (void) restore_line_pointer (delim
);
3280 if (*input_line_pointer
!= ',')
3283 as_bad (_("expected comma after name \"%s\""), name
);
3285 ignore_rest_of_line ();
3289 input_line_pointer
++;
3292 if (name
[0] == '.' && name
[1] == '\0')
3294 /* XXX - this should not happen to .thumb_set. */
3298 if ((symbolP
= symbol_find (name
)) == NULL
3299 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3302 /* When doing symbol listings, play games with dummy fragments living
3303 outside the normal fragment chain to record the file and line info
3305 if (listing
& LISTING_SYMBOLS
)
3307 extern struct list_info_struct
* listing_tail
;
3308 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3310 memset (dummy_frag
, 0, sizeof (fragS
));
3311 dummy_frag
->fr_type
= rs_fill
;
3312 dummy_frag
->line
= listing_tail
;
3313 symbolP
= symbol_new (name
, undefined_section
, dummy_frag
, 0);
3314 dummy_frag
->fr_symbol
= symbolP
;
3318 symbolP
= symbol_new (name
, undefined_section
, &zero_address_frag
, 0);
3321 /* "set" symbols are local unless otherwise specified. */
3322 SF_SET_LOCAL (symbolP
);
3323 #endif /* OBJ_COFF */
3324 } /* Make a new symbol. */
3326 symbol_table_insert (symbolP
);
3331 && S_IS_DEFINED (symbolP
)
3332 && S_GET_SEGMENT (symbolP
) != reg_section
)
3333 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3335 pseudo_set (symbolP
);
3337 demand_empty_rest_of_line ();
3339 /* XXX Now we come to the Thumb specific bit of code. */
3341 THUMB_SET_FUNC (symbolP
, 1);
3342 ARM_SET_THUMB (symbolP
, 1);
3343 #if defined OBJ_ELF || defined OBJ_COFF
3344 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3348 /* Directives: Mode selection. */
3350 /* .syntax [unified|divided] - choose the new unified syntax
3351 (same for Arm and Thumb encoding, modulo slight differences in what
3352 can be represented) or the old divergent syntax for each mode. */
3354 s_syntax (int unused ATTRIBUTE_UNUSED
)
3358 delim
= get_symbol_name (& name
);
3360 if (!strcasecmp (name
, "unified"))
3361 unified_syntax
= TRUE
;
3362 else if (!strcasecmp (name
, "divided"))
3363 unified_syntax
= FALSE
;
3366 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3369 (void) restore_line_pointer (delim
);
3370 demand_empty_rest_of_line ();
3373 /* Directives: sectioning and alignment. */
3376 s_bss (int ignore ATTRIBUTE_UNUSED
)
3378 /* We don't support putting frags in the BSS segment, we fake it by
3379 marking in_bss, then looking at s_skip for clues. */
3380 subseg_set (bss_section
, 0);
3381 demand_empty_rest_of_line ();
3383 #ifdef md_elf_section_change_hook
3384 md_elf_section_change_hook ();
3389 s_even (int ignore ATTRIBUTE_UNUSED
)
3391 /* Never make frag if expect extra pass. */
3393 frag_align (1, 0, 0);
3395 record_alignment (now_seg
, 1);
3397 demand_empty_rest_of_line ();
3400 /* Directives: CodeComposer Studio. */
3402 /* .ref (for CodeComposer Studio syntax only). */
3404 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3406 if (codecomposer_syntax
)
3407 ignore_rest_of_line ();
3409 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3412 /* If name is not NULL, then it is used for marking the beginning of a
3413 function, whereas if it is NULL then it means the function end. */
3415 asmfunc_debug (const char * name
)
3417 static const char * last_name
= NULL
;
3421 gas_assert (last_name
== NULL
);
3424 if (debug_type
== DEBUG_STABS
)
3425 stabs_generate_asm_func (name
, name
);
3429 gas_assert (last_name
!= NULL
);
3431 if (debug_type
== DEBUG_STABS
)
3432 stabs_generate_asm_endfunc (last_name
, last_name
);
3439 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3441 if (codecomposer_syntax
)
3443 switch (asmfunc_state
)
3445 case OUTSIDE_ASMFUNC
:
3446 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3449 case WAITING_ASMFUNC_NAME
:
3450 as_bad (_(".asmfunc repeated."));
3453 case WAITING_ENDASMFUNC
:
3454 as_bad (_(".asmfunc without function."));
3457 demand_empty_rest_of_line ();
3460 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3464 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3466 if (codecomposer_syntax
)
3468 switch (asmfunc_state
)
3470 case OUTSIDE_ASMFUNC
:
3471 as_bad (_(".endasmfunc without a .asmfunc."));
3474 case WAITING_ASMFUNC_NAME
:
3475 as_bad (_(".endasmfunc without function."));
3478 case WAITING_ENDASMFUNC
:
3479 asmfunc_state
= OUTSIDE_ASMFUNC
;
3480 asmfunc_debug (NULL
);
3483 demand_empty_rest_of_line ();
3486 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3490 s_ccs_def (int name
)
3492 if (codecomposer_syntax
)
3495 as_bad (_(".def pseudo-op only available with -mccs flag."));
3498 /* Directives: Literal pools. */
3500 static literal_pool
*
3501 find_literal_pool (void)
3503 literal_pool
* pool
;
3505 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3507 if (pool
->section
== now_seg
3508 && pool
->sub_section
== now_subseg
)
3515 static literal_pool
*
3516 find_or_make_literal_pool (void)
3518 /* Next literal pool ID number. */
3519 static unsigned int latest_pool_num
= 1;
3520 literal_pool
* pool
;
3522 pool
= find_literal_pool ();
3526 /* Create a new pool. */
3527 pool
= XNEW (literal_pool
);
3531 pool
->next_free_entry
= 0;
3532 pool
->section
= now_seg
;
3533 pool
->sub_section
= now_subseg
;
3534 pool
->next
= list_of_pools
;
3535 pool
->symbol
= NULL
;
3536 pool
->alignment
= 2;
3538 /* Add it to the list. */
3539 list_of_pools
= pool
;
3542 /* New pools, and emptied pools, will have a NULL symbol. */
3543 if (pool
->symbol
== NULL
)
3545 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3546 &zero_address_frag
, 0);
3547 pool
->id
= latest_pool_num
++;
3554 /* Add the literal in the global 'inst'
3555 structure to the relevant literal pool. */
3558 add_to_lit_pool (unsigned int nbytes
)
3560 #define PADDING_SLOT 0x1
3561 #define LIT_ENTRY_SIZE_MASK 0xFF
3562 literal_pool
* pool
;
3563 unsigned int entry
, pool_size
= 0;
3564 bfd_boolean padding_slot_p
= FALSE
;
3570 imm1
= inst
.operands
[1].imm
;
3571 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3572 : inst
.relocs
[0].exp
.X_unsigned
? 0
3573 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3574 if (target_big_endian
)
3577 imm2
= inst
.operands
[1].imm
;
3581 pool
= find_or_make_literal_pool ();
3583 /* Check if this literal value is already in the pool. */
3584 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3588 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3589 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3590 && (pool
->literals
[entry
].X_add_number
3591 == inst
.relocs
[0].exp
.X_add_number
)
3592 && (pool
->literals
[entry
].X_md
== nbytes
)
3593 && (pool
->literals
[entry
].X_unsigned
3594 == inst
.relocs
[0].exp
.X_unsigned
))
3597 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3598 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3599 && (pool
->literals
[entry
].X_add_number
3600 == inst
.relocs
[0].exp
.X_add_number
)
3601 && (pool
->literals
[entry
].X_add_symbol
3602 == inst
.relocs
[0].exp
.X_add_symbol
)
3603 && (pool
->literals
[entry
].X_op_symbol
3604 == inst
.relocs
[0].exp
.X_op_symbol
)
3605 && (pool
->literals
[entry
].X_md
== nbytes
))
3608 else if ((nbytes
== 8)
3609 && !(pool_size
& 0x7)
3610 && ((entry
+ 1) != pool
->next_free_entry
)
3611 && (pool
->literals
[entry
].X_op
== O_constant
)
3612 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3613 && (pool
->literals
[entry
].X_unsigned
3614 == inst
.relocs
[0].exp
.X_unsigned
)
3615 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3616 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3617 && (pool
->literals
[entry
+ 1].X_unsigned
3618 == inst
.relocs
[0].exp
.X_unsigned
))
3621 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3622 if (padding_slot_p
&& (nbytes
== 4))
3628 /* Do we need to create a new entry? */
3629 if (entry
== pool
->next_free_entry
)
3631 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3633 inst
.error
= _("literal pool overflow");
3639 /* For 8-byte entries, we align to an 8-byte boundary,
3640 and split it into two 4-byte entries, because on 32-bit
3641 host, 8-byte constants are treated as big num, thus
3642 saved in "generic_bignum" which will be overwritten
3643 by later assignments.
3645 We also need to make sure there is enough space for
3648 We also check to make sure the literal operand is a
3650 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3651 || inst
.relocs
[0].exp
.X_op
== O_big
))
3653 inst
.error
= _("invalid type for literal pool");
3656 else if (pool_size
& 0x7)
3658 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3660 inst
.error
= _("literal pool overflow");
3664 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3665 pool
->literals
[entry
].X_op
= O_constant
;
3666 pool
->literals
[entry
].X_add_number
= 0;
3667 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3668 pool
->next_free_entry
+= 1;
3671 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3673 inst
.error
= _("literal pool overflow");
3677 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3678 pool
->literals
[entry
].X_op
= O_constant
;
3679 pool
->literals
[entry
].X_add_number
= imm1
;
3680 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3681 pool
->literals
[entry
++].X_md
= 4;
3682 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3683 pool
->literals
[entry
].X_op
= O_constant
;
3684 pool
->literals
[entry
].X_add_number
= imm2
;
3685 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3686 pool
->literals
[entry
].X_md
= 4;
3687 pool
->alignment
= 3;
3688 pool
->next_free_entry
+= 1;
3692 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3693 pool
->literals
[entry
].X_md
= 4;
3697 /* PR ld/12974: Record the location of the first source line to reference
3698 this entry in the literal pool. If it turns out during linking that the
3699 symbol does not exist we will be able to give an accurate line number for
3700 the (first use of the) missing reference. */
3701 if (debug_type
== DEBUG_DWARF2
)
3702 dwarf2_where (pool
->locs
+ entry
);
3704 pool
->next_free_entry
+= 1;
3706 else if (padding_slot_p
)
3708 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3709 pool
->literals
[entry
].X_md
= nbytes
;
3712 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3713 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3714 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3720 tc_start_label_without_colon (void)
3722 bfd_boolean ret
= TRUE
;
3724 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3726 const char *label
= input_line_pointer
;
3728 while (!is_end_of_line
[(int) label
[-1]])
3733 as_bad (_("Invalid label '%s'"), label
);
3737 asmfunc_debug (label
);
3739 asmfunc_state
= WAITING_ENDASMFUNC
;
3745 /* Can't use symbol_new here, so have to create a symbol and then at
3746 a later date assign it a value. That's what these functions do. */
3749 symbol_locate (symbolS
* symbolP
,
3750 const char * name
, /* It is copied, the caller can modify. */
3751 segT segment
, /* Segment identifier (SEG_<something>). */
3752 valueT valu
, /* Symbol value. */
3753 fragS
* frag
) /* Associated fragment. */
3756 char * preserved_copy_of_name
;
3758 name_length
= strlen (name
) + 1; /* +1 for \0. */
3759 obstack_grow (¬es
, name
, name_length
);
3760 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3762 #ifdef tc_canonicalize_symbol_name
3763 preserved_copy_of_name
=
3764 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3767 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3769 S_SET_SEGMENT (symbolP
, segment
);
3770 S_SET_VALUE (symbolP
, valu
);
3771 symbol_clear_list_pointers (symbolP
);
3773 symbol_set_frag (symbolP
, frag
);
3775 /* Link to end of symbol chain. */
3777 extern int symbol_table_frozen
;
3779 if (symbol_table_frozen
)
3783 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3785 obj_symbol_new_hook (symbolP
);
3787 #ifdef tc_symbol_new_hook
3788 tc_symbol_new_hook (symbolP
);
3792 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3793 #endif /* DEBUG_SYMS */
3797 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3800 literal_pool
* pool
;
3803 pool
= find_literal_pool ();
3805 || pool
->symbol
== NULL
3806 || pool
->next_free_entry
== 0)
3809 /* Align pool as you have word accesses.
3810 Only make a frag if we have to. */
3812 frag_align (pool
->alignment
, 0, 0);
3814 record_alignment (now_seg
, 2);
3817 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3818 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3820 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3822 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3823 (valueT
) frag_now_fix (), frag_now
);
3824 symbol_table_insert (pool
->symbol
);
3826 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3828 #if defined OBJ_COFF || defined OBJ_ELF
3829 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3832 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3835 if (debug_type
== DEBUG_DWARF2
)
3836 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3838 /* First output the expression in the instruction to the pool. */
3839 emit_expr (&(pool
->literals
[entry
]),
3840 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3843 /* Mark the pool as empty. */
3844 pool
->next_free_entry
= 0;
3845 pool
->symbol
= NULL
;
3849 /* Forward declarations for functions below, in the MD interface
3851 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3852 static valueT
create_unwind_entry (int);
3853 static void start_unwind_section (const segT
, int);
3854 static void add_unwind_opcode (valueT
, int);
3855 static void flush_pending_unwind (void);
3857 /* Directives: Data. */
3860 s_arm_elf_cons (int nbytes
)
3864 #ifdef md_flush_pending_output
3865 md_flush_pending_output ();
3868 if (is_it_end_of_statement ())
3870 demand_empty_rest_of_line ();
3874 #ifdef md_cons_align
3875 md_cons_align (nbytes
);
3878 mapping_state (MAP_DATA
);
3882 char *base
= input_line_pointer
;
3886 if (exp
.X_op
!= O_symbol
)
3887 emit_expr (&exp
, (unsigned int) nbytes
);
3890 char *before_reloc
= input_line_pointer
;
3891 reloc
= parse_reloc (&input_line_pointer
);
3894 as_bad (_("unrecognized relocation suffix"));
3895 ignore_rest_of_line ();
3898 else if (reloc
== BFD_RELOC_UNUSED
)
3899 emit_expr (&exp
, (unsigned int) nbytes
);
3902 reloc_howto_type
*howto
= (reloc_howto_type
*)
3903 bfd_reloc_type_lookup (stdoutput
,
3904 (bfd_reloc_code_real_type
) reloc
);
3905 int size
= bfd_get_reloc_size (howto
);
3907 if (reloc
== BFD_RELOC_ARM_PLT32
)
3909 as_bad (_("(plt) is only valid on branch targets"));
3910 reloc
= BFD_RELOC_UNUSED
;
3915 as_bad (ngettext ("%s relocations do not fit in %d byte",
3916 "%s relocations do not fit in %d bytes",
3918 howto
->name
, nbytes
);
3921 /* We've parsed an expression stopping at O_symbol.
3922 But there may be more expression left now that we
3923 have parsed the relocation marker. Parse it again.
3924 XXX Surely there is a cleaner way to do this. */
3925 char *p
= input_line_pointer
;
3927 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3929 memcpy (save_buf
, base
, input_line_pointer
- base
);
3930 memmove (base
+ (input_line_pointer
- before_reloc
),
3931 base
, before_reloc
- base
);
3933 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3935 memcpy (base
, save_buf
, p
- base
);
3937 offset
= nbytes
- size
;
3938 p
= frag_more (nbytes
);
3939 memset (p
, 0, nbytes
);
3940 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3941 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3947 while (*input_line_pointer
++ == ',');
3949 /* Put terminator back into stream. */
3950 input_line_pointer
--;
3951 demand_empty_rest_of_line ();
3954 /* Emit an expression containing a 32-bit thumb instruction.
3955 Implementation based on put_thumb32_insn. */
3958 emit_thumb32_expr (expressionS
* exp
)
3960 expressionS exp_high
= *exp
;
3962 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3963 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3964 exp
->X_add_number
&= 0xffff;
3965 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3968 /* Guess the instruction size based on the opcode. */
3971 thumb_insn_size (int opcode
)
3973 if ((unsigned int) opcode
< 0xe800u
)
3975 else if ((unsigned int) opcode
>= 0xe8000000u
)
3982 emit_insn (expressionS
*exp
, int nbytes
)
3986 if (exp
->X_op
== O_constant
)
3991 size
= thumb_insn_size (exp
->X_add_number
);
3995 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3997 as_bad (_(".inst.n operand too big. "\
3998 "Use .inst.w instead"));
4003 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
4004 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
4006 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
4008 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
4009 emit_thumb32_expr (exp
);
4011 emit_expr (exp
, (unsigned int) size
);
4013 it_fsm_post_encode ();
4017 as_bad (_("cannot determine Thumb instruction size. " \
4018 "Use .inst.n/.inst.w instead"));
4021 as_bad (_("constant expression required"));
4026 /* Like s_arm_elf_cons but do not use md_cons_align and
4027 set the mapping state to MAP_ARM/MAP_THUMB. */
4030 s_arm_elf_inst (int nbytes
)
4032 if (is_it_end_of_statement ())
4034 demand_empty_rest_of_line ();
4038 /* Calling mapping_state () here will not change ARM/THUMB,
4039 but will ensure not to be in DATA state. */
4042 mapping_state (MAP_THUMB
);
4047 as_bad (_("width suffixes are invalid in ARM mode"));
4048 ignore_rest_of_line ();
4054 mapping_state (MAP_ARM
);
4063 if (! emit_insn (& exp
, nbytes
))
4065 ignore_rest_of_line ();
4069 while (*input_line_pointer
++ == ',');
4071 /* Put terminator back into stream. */
4072 input_line_pointer
--;
4073 demand_empty_rest_of_line ();
4076 /* Parse a .rel31 directive. */
4079 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
4086 if (*input_line_pointer
== '1')
4087 highbit
= 0x80000000;
4088 else if (*input_line_pointer
!= '0')
4089 as_bad (_("expected 0 or 1"));
4091 input_line_pointer
++;
4092 if (*input_line_pointer
!= ',')
4093 as_bad (_("missing comma"));
4094 input_line_pointer
++;
4096 #ifdef md_flush_pending_output
4097 md_flush_pending_output ();
4100 #ifdef md_cons_align
4104 mapping_state (MAP_DATA
);
4109 md_number_to_chars (p
, highbit
, 4);
4110 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4111 BFD_RELOC_ARM_PREL31
);
4113 demand_empty_rest_of_line ();
4116 /* Directives: AEABI stack-unwind tables. */
4118 /* Parse an unwind_fnstart directive. Simply records the current location. */
4121 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4123 demand_empty_rest_of_line ();
4124 if (unwind
.proc_start
)
4126 as_bad (_("duplicate .fnstart directive"));
4130 /* Mark the start of the function. */
4131 unwind
.proc_start
= expr_build_dot ();
4133 /* Reset the rest of the unwind info. */
4134 unwind
.opcode_count
= 0;
4135 unwind
.table_entry
= NULL
;
4136 unwind
.personality_routine
= NULL
;
4137 unwind
.personality_index
= -1;
4138 unwind
.frame_size
= 0;
4139 unwind
.fp_offset
= 0;
4140 unwind
.fp_reg
= REG_SP
;
4142 unwind
.sp_restored
= 0;
4146 /* Parse a handlerdata directive. Creates the exception handling table entry
4147 for the function. */
4150 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4152 demand_empty_rest_of_line ();
4153 if (!unwind
.proc_start
)
4154 as_bad (MISSING_FNSTART
);
4156 if (unwind
.table_entry
)
4157 as_bad (_("duplicate .handlerdata directive"));
4159 create_unwind_entry (1);
4162 /* Parse an unwind_fnend directive. Generates the index table entry. */
4165 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4170 unsigned int marked_pr_dependency
;
4172 demand_empty_rest_of_line ();
4174 if (!unwind
.proc_start
)
4176 as_bad (_(".fnend directive without .fnstart"));
4180 /* Add eh table entry. */
4181 if (unwind
.table_entry
== NULL
)
4182 val
= create_unwind_entry (0);
4186 /* Add index table entry. This is two words. */
4187 start_unwind_section (unwind
.saved_seg
, 1);
4188 frag_align (2, 0, 0);
4189 record_alignment (now_seg
, 2);
4191 ptr
= frag_more (8);
4193 where
= frag_now_fix () - 8;
4195 /* Self relative offset of the function start. */
4196 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4197 BFD_RELOC_ARM_PREL31
);
4199 /* Indicate dependency on EHABI-defined personality routines to the
4200 linker, if it hasn't been done already. */
4201 marked_pr_dependency
4202 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4203 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4204 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4206 static const char *const name
[] =
4208 "__aeabi_unwind_cpp_pr0",
4209 "__aeabi_unwind_cpp_pr1",
4210 "__aeabi_unwind_cpp_pr2"
4212 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4213 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4214 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4215 |= 1 << unwind
.personality_index
;
4219 /* Inline exception table entry. */
4220 md_number_to_chars (ptr
+ 4, val
, 4);
4222 /* Self relative offset of the table entry. */
4223 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4224 BFD_RELOC_ARM_PREL31
);
4226 /* Restore the original section. */
4227 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4229 unwind
.proc_start
= NULL
;
4233 /* Parse an unwind_cantunwind directive. */
4236 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4238 demand_empty_rest_of_line ();
4239 if (!unwind
.proc_start
)
4240 as_bad (MISSING_FNSTART
);
4242 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4243 as_bad (_("personality routine specified for cantunwind frame"));
4245 unwind
.personality_index
= -2;
4249 /* Parse a personalityindex directive. */
4252 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4256 if (!unwind
.proc_start
)
4257 as_bad (MISSING_FNSTART
);
4259 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4260 as_bad (_("duplicate .personalityindex directive"));
4264 if (exp
.X_op
!= O_constant
4265 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4267 as_bad (_("bad personality routine number"));
4268 ignore_rest_of_line ();
4272 unwind
.personality_index
= exp
.X_add_number
;
4274 demand_empty_rest_of_line ();
4278 /* Parse a personality directive. */
4281 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4285 if (!unwind
.proc_start
)
4286 as_bad (MISSING_FNSTART
);
4288 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4289 as_bad (_("duplicate .personality directive"));
4291 c
= get_symbol_name (& name
);
4292 p
= input_line_pointer
;
4294 ++ input_line_pointer
;
4295 unwind
.personality_routine
= symbol_find_or_make (name
);
4297 demand_empty_rest_of_line ();
4301 /* Parse a directive saving core registers. */
4304 s_arm_unwind_save_core (void)
4310 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4313 as_bad (_("expected register list"));
4314 ignore_rest_of_line ();
4318 demand_empty_rest_of_line ();
4320 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4321 into .unwind_save {..., sp...}. We aren't bothered about the value of
4322 ip because it is clobbered by calls. */
4323 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4324 && (range
& 0x3000) == 0x1000)
4326 unwind
.opcode_count
--;
4327 unwind
.sp_restored
= 0;
4328 range
= (range
| 0x2000) & ~0x1000;
4329 unwind
.pending_offset
= 0;
4335 /* See if we can use the short opcodes. These pop a block of up to 8
4336 registers starting with r4, plus maybe r14. */
4337 for (n
= 0; n
< 8; n
++)
4339 /* Break at the first non-saved register. */
4340 if ((range
& (1 << (n
+ 4))) == 0)
4343 /* See if there are any other bits set. */
4344 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4346 /* Use the long form. */
4347 op
= 0x8000 | ((range
>> 4) & 0xfff);
4348 add_unwind_opcode (op
, 2);
4352 /* Use the short form. */
4354 op
= 0xa8; /* Pop r14. */
4356 op
= 0xa0; /* Do not pop r14. */
4358 add_unwind_opcode (op
, 1);
4365 op
= 0xb100 | (range
& 0xf);
4366 add_unwind_opcode (op
, 2);
4369 /* Record the number of bytes pushed. */
4370 for (n
= 0; n
< 16; n
++)
4372 if (range
& (1 << n
))
4373 unwind
.frame_size
+= 4;
4378 /* Parse a directive saving FPA registers. */
4381 s_arm_unwind_save_fpa (int reg
)
4387 /* Get Number of registers to transfer. */
4388 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4391 exp
.X_op
= O_illegal
;
4393 if (exp
.X_op
!= O_constant
)
4395 as_bad (_("expected , <constant>"));
4396 ignore_rest_of_line ();
4400 num_regs
= exp
.X_add_number
;
4402 if (num_regs
< 1 || num_regs
> 4)
4404 as_bad (_("number of registers must be in the range [1:4]"));
4405 ignore_rest_of_line ();
4409 demand_empty_rest_of_line ();
4414 op
= 0xb4 | (num_regs
- 1);
4415 add_unwind_opcode (op
, 1);
4420 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4421 add_unwind_opcode (op
, 2);
4423 unwind
.frame_size
+= num_regs
* 12;
4427 /* Parse a directive saving VFP registers for ARMv6 and above. */
4430 s_arm_unwind_save_vfp_armv6 (void)
4435 int num_vfpv3_regs
= 0;
4436 int num_regs_below_16
;
4437 bfd_boolean partial_match
;
4439 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4443 as_bad (_("expected register list"));
4444 ignore_rest_of_line ();
4448 demand_empty_rest_of_line ();
4450 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4451 than FSTMX/FLDMX-style ones). */
4453 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4455 num_vfpv3_regs
= count
;
4456 else if (start
+ count
> 16)
4457 num_vfpv3_regs
= start
+ count
- 16;
4459 if (num_vfpv3_regs
> 0)
4461 int start_offset
= start
> 16 ? start
- 16 : 0;
4462 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4463 add_unwind_opcode (op
, 2);
4466 /* Generate opcode for registers numbered in the range 0 .. 15. */
4467 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4468 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4469 if (num_regs_below_16
> 0)
4471 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4472 add_unwind_opcode (op
, 2);
4475 unwind
.frame_size
+= count
* 8;
4479 /* Parse a directive saving VFP registers for pre-ARMv6. */
4482 s_arm_unwind_save_vfp (void)
4487 bfd_boolean partial_match
;
4489 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4493 as_bad (_("expected register list"));
4494 ignore_rest_of_line ();
4498 demand_empty_rest_of_line ();
4503 op
= 0xb8 | (count
- 1);
4504 add_unwind_opcode (op
, 1);
4509 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4510 add_unwind_opcode (op
, 2);
4512 unwind
.frame_size
+= count
* 8 + 4;
4516 /* Parse a directive saving iWMMXt data registers. */
4519 s_arm_unwind_save_mmxwr (void)
4527 if (*input_line_pointer
== '{')
4528 input_line_pointer
++;
4532 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4536 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4541 as_tsktsk (_("register list not in ascending order"));
4544 if (*input_line_pointer
== '-')
4546 input_line_pointer
++;
4547 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4550 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4553 else if (reg
>= hi_reg
)
4555 as_bad (_("bad register range"));
4558 for (; reg
< hi_reg
; reg
++)
4562 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4564 skip_past_char (&input_line_pointer
, '}');
4566 demand_empty_rest_of_line ();
4568 /* Generate any deferred opcodes because we're going to be looking at
4570 flush_pending_unwind ();
4572 for (i
= 0; i
< 16; i
++)
4574 if (mask
& (1 << i
))
4575 unwind
.frame_size
+= 8;
4578 /* Attempt to combine with a previous opcode. We do this because gcc
4579 likes to output separate unwind directives for a single block of
4581 if (unwind
.opcode_count
> 0)
4583 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4584 if ((i
& 0xf8) == 0xc0)
4587 /* Only merge if the blocks are contiguous. */
4590 if ((mask
& 0xfe00) == (1 << 9))
4592 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4593 unwind
.opcode_count
--;
4596 else if (i
== 6 && unwind
.opcode_count
>= 2)
4598 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4602 op
= 0xffff << (reg
- 1);
4604 && ((mask
& op
) == (1u << (reg
- 1))))
4606 op
= (1 << (reg
+ i
+ 1)) - 1;
4607 op
&= ~((1 << reg
) - 1);
4609 unwind
.opcode_count
-= 2;
4616 /* We want to generate opcodes in the order the registers have been
4617 saved, ie. descending order. */
4618 for (reg
= 15; reg
>= -1; reg
--)
4620 /* Save registers in blocks. */
4622 || !(mask
& (1 << reg
)))
4624 /* We found an unsaved reg. Generate opcodes to save the
4631 op
= 0xc0 | (hi_reg
- 10);
4632 add_unwind_opcode (op
, 1);
4637 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4638 add_unwind_opcode (op
, 2);
4647 ignore_rest_of_line ();
4651 s_arm_unwind_save_mmxwcg (void)
4658 if (*input_line_pointer
== '{')
4659 input_line_pointer
++;
4661 skip_whitespace (input_line_pointer
);
4665 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4669 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4675 as_tsktsk (_("register list not in ascending order"));
4678 if (*input_line_pointer
== '-')
4680 input_line_pointer
++;
4681 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4687 else if (reg
>= hi_reg
)
4689 as_bad (_("bad register range"));
4692 for (; reg
< hi_reg
; reg
++)
4696 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4698 skip_past_char (&input_line_pointer
, '}');
4700 demand_empty_rest_of_line ();
4702 /* Generate any deferred opcodes because we're going to be looking at
4704 flush_pending_unwind ();
4706 for (reg
= 0; reg
< 16; reg
++)
4708 if (mask
& (1 << reg
))
4709 unwind
.frame_size
+= 4;
4712 add_unwind_opcode (op
, 2);
4715 ignore_rest_of_line ();
4719 /* Parse an unwind_save directive.
4720 If the argument is non-zero, this is a .vsave directive. */
4723 s_arm_unwind_save (int arch_v6
)
4726 struct reg_entry
*reg
;
4727 bfd_boolean had_brace
= FALSE
;
4729 if (!unwind
.proc_start
)
4730 as_bad (MISSING_FNSTART
);
4732 /* Figure out what sort of save we have. */
4733 peek
= input_line_pointer
;
4741 reg
= arm_reg_parse_multi (&peek
);
4745 as_bad (_("register expected"));
4746 ignore_rest_of_line ();
4755 as_bad (_("FPA .unwind_save does not take a register list"));
4756 ignore_rest_of_line ();
4759 input_line_pointer
= peek
;
4760 s_arm_unwind_save_fpa (reg
->number
);
4764 s_arm_unwind_save_core ();
4769 s_arm_unwind_save_vfp_armv6 ();
4771 s_arm_unwind_save_vfp ();
4774 case REG_TYPE_MMXWR
:
4775 s_arm_unwind_save_mmxwr ();
4778 case REG_TYPE_MMXWCG
:
4779 s_arm_unwind_save_mmxwcg ();
4783 as_bad (_(".unwind_save does not support this kind of register"));
4784 ignore_rest_of_line ();
4789 /* Parse an unwind_movsp directive. */
4792 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4798 if (!unwind
.proc_start
)
4799 as_bad (MISSING_FNSTART
);
4801 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4804 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4805 ignore_rest_of_line ();
4809 /* Optional constant. */
4810 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4812 if (immediate_for_directive (&offset
) == FAIL
)
4818 demand_empty_rest_of_line ();
4820 if (reg
== REG_SP
|| reg
== REG_PC
)
4822 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4826 if (unwind
.fp_reg
!= REG_SP
)
4827 as_bad (_("unexpected .unwind_movsp directive"));
4829 /* Generate opcode to restore the value. */
4831 add_unwind_opcode (op
, 1);
4833 /* Record the information for later. */
4834 unwind
.fp_reg
= reg
;
4835 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4836 unwind
.sp_restored
= 1;
4839 /* Parse an unwind_pad directive. */
4842 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4846 if (!unwind
.proc_start
)
4847 as_bad (MISSING_FNSTART
);
4849 if (immediate_for_directive (&offset
) == FAIL
)
4854 as_bad (_("stack increment must be multiple of 4"));
4855 ignore_rest_of_line ();
4859 /* Don't generate any opcodes, just record the details for later. */
4860 unwind
.frame_size
+= offset
;
4861 unwind
.pending_offset
+= offset
;
4863 demand_empty_rest_of_line ();
4866 /* Parse an unwind_setfp directive. */
4869 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4875 if (!unwind
.proc_start
)
4876 as_bad (MISSING_FNSTART
);
4878 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4879 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4882 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4884 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4886 as_bad (_("expected <reg>, <reg>"));
4887 ignore_rest_of_line ();
4891 /* Optional constant. */
4892 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4894 if (immediate_for_directive (&offset
) == FAIL
)
4900 demand_empty_rest_of_line ();
4902 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4904 as_bad (_("register must be either sp or set by a previous"
4905 "unwind_movsp directive"));
4909 /* Don't generate any opcodes, just record the information for later. */
4910 unwind
.fp_reg
= fp_reg
;
4912 if (sp_reg
== REG_SP
)
4913 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4915 unwind
.fp_offset
-= offset
;
4918 /* Parse an unwind_raw directive. */
4921 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4924 /* This is an arbitrary limit. */
4925 unsigned char op
[16];
4928 if (!unwind
.proc_start
)
4929 as_bad (MISSING_FNSTART
);
4932 if (exp
.X_op
== O_constant
4933 && skip_past_comma (&input_line_pointer
) != FAIL
)
4935 unwind
.frame_size
+= exp
.X_add_number
;
4939 exp
.X_op
= O_illegal
;
4941 if (exp
.X_op
!= O_constant
)
4943 as_bad (_("expected <offset>, <opcode>"));
4944 ignore_rest_of_line ();
4950 /* Parse the opcode. */
4955 as_bad (_("unwind opcode too long"));
4956 ignore_rest_of_line ();
4958 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4960 as_bad (_("invalid unwind opcode"));
4961 ignore_rest_of_line ();
4964 op
[count
++] = exp
.X_add_number
;
4966 /* Parse the next byte. */
4967 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4973 /* Add the opcode bytes in reverse order. */
4975 add_unwind_opcode (op
[count
], 1);
4977 demand_empty_rest_of_line ();
4981 /* Parse a .eabi_attribute directive. */
4984 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4986 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4988 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4989 attributes_set_explicitly
[tag
] = 1;
4992 /* Emit a tls fix for the symbol. */
4995 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4999 #ifdef md_flush_pending_output
5000 md_flush_pending_output ();
5003 #ifdef md_cons_align
5007 /* Since we're just labelling the code, there's no need to define a
5010 p
= obstack_next_free (&frchain_now
->frch_obstack
);
5011 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
5012 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
5013 : BFD_RELOC_ARM_TLS_DESCSEQ
);
5015 #endif /* OBJ_ELF */
5017 static void s_arm_arch (int);
5018 static void s_arm_object_arch (int);
5019 static void s_arm_cpu (int);
5020 static void s_arm_fpu (int);
5021 static void s_arm_arch_extension (int);
5026 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
5033 if (exp
.X_op
== O_symbol
)
5034 exp
.X_op
= O_secrel
;
5036 emit_expr (&exp
, 4);
5038 while (*input_line_pointer
++ == ',');
5040 input_line_pointer
--;
5041 demand_empty_rest_of_line ();
5046 arm_is_largest_exponent_ok (int precision
)
5048 /* precision == 1 ensures that this will only return
5049 true for 16 bit floats. */
5050 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
5054 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
5058 enum fp_16bit_format new_format
;
5060 new_format
= ARM_FP16_FORMAT_DEFAULT
;
5062 name
= input_line_pointer
;
5063 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
5064 input_line_pointer
++;
5066 saved_char
= *input_line_pointer
;
5067 *input_line_pointer
= 0;
5069 if (strcasecmp (name
, "ieee") == 0)
5070 new_format
= ARM_FP16_FORMAT_IEEE
;
5071 else if (strcasecmp (name
, "alternative") == 0)
5072 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
5075 as_bad (_("unrecognised float16 format \"%s\""), name
);
5079 /* Only set fp16_format if it is still the default (aka not already
5081 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
5082 fp16_format
= new_format
;
5085 if (new_format
!= fp16_format
)
5086 as_warn (_("float16 format cannot be set more than once, ignoring."));
5090 *input_line_pointer
= saved_char
;
5091 ignore_rest_of_line ();
5094 /* This table describes all the machine specific pseudo-ops the assembler
5095 has to support. The fields are:
5096 pseudo-op name without dot
5097 function to call to execute this pseudo-op
5098 Integer arg to pass to the function. */
5100 const pseudo_typeS md_pseudo_table
[] =
5102 /* Never called because '.req' does not start a line. */
5103 { "req", s_req
, 0 },
5104 /* Following two are likewise never called. */
5107 { "unreq", s_unreq
, 0 },
5108 { "bss", s_bss
, 0 },
5109 { "align", s_align_ptwo
, 2 },
5110 { "arm", s_arm
, 0 },
5111 { "thumb", s_thumb
, 0 },
5112 { "code", s_code
, 0 },
5113 { "force_thumb", s_force_thumb
, 0 },
5114 { "thumb_func", s_thumb_func
, 0 },
5115 { "thumb_set", s_thumb_set
, 0 },
5116 { "even", s_even
, 0 },
5117 { "ltorg", s_ltorg
, 0 },
5118 { "pool", s_ltorg
, 0 },
5119 { "syntax", s_syntax
, 0 },
5120 { "cpu", s_arm_cpu
, 0 },
5121 { "arch", s_arm_arch
, 0 },
5122 { "object_arch", s_arm_object_arch
, 0 },
5123 { "fpu", s_arm_fpu
, 0 },
5124 { "arch_extension", s_arm_arch_extension
, 0 },
5126 { "word", s_arm_elf_cons
, 4 },
5127 { "long", s_arm_elf_cons
, 4 },
5128 { "inst.n", s_arm_elf_inst
, 2 },
5129 { "inst.w", s_arm_elf_inst
, 4 },
5130 { "inst", s_arm_elf_inst
, 0 },
5131 { "rel31", s_arm_rel31
, 0 },
5132 { "fnstart", s_arm_unwind_fnstart
, 0 },
5133 { "fnend", s_arm_unwind_fnend
, 0 },
5134 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5135 { "personality", s_arm_unwind_personality
, 0 },
5136 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5137 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5138 { "save", s_arm_unwind_save
, 0 },
5139 { "vsave", s_arm_unwind_save
, 1 },
5140 { "movsp", s_arm_unwind_movsp
, 0 },
5141 { "pad", s_arm_unwind_pad
, 0 },
5142 { "setfp", s_arm_unwind_setfp
, 0 },
5143 { "unwind_raw", s_arm_unwind_raw
, 0 },
5144 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5145 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5149 /* These are used for dwarf. */
5153 /* These are used for dwarf2. */
5154 { "file", dwarf2_directive_file
, 0 },
5155 { "loc", dwarf2_directive_loc
, 0 },
5156 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5158 { "extend", float_cons
, 'x' },
5159 { "ldouble", float_cons
, 'x' },
5160 { "packed", float_cons
, 'p' },
5161 { "bfloat16", float_cons
, 'b' },
5163 {"secrel32", pe_directive_secrel
, 0},
5166 /* These are for compatibility with CodeComposer Studio. */
5167 {"ref", s_ccs_ref
, 0},
5168 {"def", s_ccs_def
, 0},
5169 {"asmfunc", s_ccs_asmfunc
, 0},
5170 {"endasmfunc", s_ccs_endasmfunc
, 0},
5172 {"float16", float_cons
, 'h' },
5173 {"float16_format", set_fp16_format
, 0 },
5178 /* Parser functions used exclusively in instruction operands. */
5180 /* Generic immediate-value read function for use in insn parsing.
5181 STR points to the beginning of the immediate (the leading #);
5182 VAL receives the value; if the value is outside [MIN, MAX]
5183 issue an error. PREFIX_OPT is true if the immediate prefix is
5187 parse_immediate (char **str
, int *val
, int min
, int max
,
5188 bfd_boolean prefix_opt
)
5192 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5193 if (exp
.X_op
!= O_constant
)
5195 inst
.error
= _("constant expression required");
5199 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5201 inst
.error
= _("immediate value out of range");
5205 *val
= exp
.X_add_number
;
5209 /* Less-generic immediate-value read function with the possibility of loading a
5210 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5211 instructions. Puts the result directly in inst.operands[i]. */
5214 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5215 bfd_boolean allow_symbol_p
)
5218 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5221 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5223 if (exp_p
->X_op
== O_constant
)
5225 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5226 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5227 O_constant. We have to be careful not to break compilation for
5228 32-bit X_add_number, though. */
5229 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5231 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5232 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5234 inst
.operands
[i
].regisimm
= 1;
5237 else if (exp_p
->X_op
== O_big
5238 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5240 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5242 /* Bignums have their least significant bits in
5243 generic_bignum[0]. Make sure we put 32 bits in imm and
5244 32 bits in reg, in a (hopefully) portable way. */
5245 gas_assert (parts
!= 0);
5247 /* Make sure that the number is not too big.
5248 PR 11972: Bignums can now be sign-extended to the
5249 size of a .octa so check that the out of range bits
5250 are all zero or all one. */
5251 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5253 LITTLENUM_TYPE m
= -1;
5255 if (generic_bignum
[parts
* 2] != 0
5256 && generic_bignum
[parts
* 2] != m
)
5259 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5260 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5264 inst
.operands
[i
].imm
= 0;
5265 for (j
= 0; j
< parts
; j
++, idx
++)
5266 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5267 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5268 inst
.operands
[i
].reg
= 0;
5269 for (j
= 0; j
< parts
; j
++, idx
++)
5270 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5271 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5272 inst
.operands
[i
].regisimm
= 1;
5274 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5282 /* Returns the pseudo-register number of an FPA immediate constant,
5283 or FAIL if there isn't a valid constant here. */
5286 parse_fpa_immediate (char ** str
)
5288 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5294 /* First try and match exact strings, this is to guarantee
5295 that some formats will work even for cross assembly. */
5297 for (i
= 0; fp_const
[i
]; i
++)
5299 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5303 *str
+= strlen (fp_const
[i
]);
5304 if (is_end_of_line
[(unsigned char) **str
])
5310 /* Just because we didn't get a match doesn't mean that the constant
5311 isn't valid, just that it is in a format that we don't
5312 automatically recognize. Try parsing it with the standard
5313 expression routines. */
5315 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5317 /* Look for a raw floating point number. */
5318 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5319 && is_end_of_line
[(unsigned char) *save_in
])
5321 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5323 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5325 if (words
[j
] != fp_values
[i
][j
])
5329 if (j
== MAX_LITTLENUMS
)
5337 /* Try and parse a more complex expression, this will probably fail
5338 unless the code uses a floating point prefix (eg "0f"). */
5339 save_in
= input_line_pointer
;
5340 input_line_pointer
= *str
;
5341 if (expression (&exp
) == absolute_section
5342 && exp
.X_op
== O_big
5343 && exp
.X_add_number
< 0)
5345 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5347 #define X_PRECISION 5
5348 #define E_PRECISION 15L
5349 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5351 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5353 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5355 if (words
[j
] != fp_values
[i
][j
])
5359 if (j
== MAX_LITTLENUMS
)
5361 *str
= input_line_pointer
;
5362 input_line_pointer
= save_in
;
5369 *str
= input_line_pointer
;
5370 input_line_pointer
= save_in
;
5371 inst
.error
= _("invalid FPA immediate expression");
5375 /* Returns 1 if a number has "quarter-precision" float format
5376 0baBbbbbbc defgh000 00000000 00000000. */
5379 is_quarter_float (unsigned imm
)
5381 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5382 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5386 /* Detect the presence of a floating point or integer zero constant,
5390 parse_ifimm_zero (char **in
)
5394 if (!is_immediate_prefix (**in
))
5396 /* In unified syntax, all prefixes are optional. */
5397 if (!unified_syntax
)
5403 /* Accept #0x0 as a synonym for #0. */
5404 if (strncmp (*in
, "0x", 2) == 0)
5407 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5412 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5413 &generic_floating_point_number
);
5416 && generic_floating_point_number
.sign
== '+'
5417 && (generic_floating_point_number
.low
5418 > generic_floating_point_number
.leader
))
5424 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5425 0baBbbbbbc defgh000 00000000 00000000.
5426 The zero and minus-zero cases need special handling, since they can't be
5427 encoded in the "quarter-precision" float format, but can nonetheless be
5428 loaded as integer constants. */
5431 parse_qfloat_immediate (char **ccp
, int *immed
)
5435 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5436 int found_fpchar
= 0;
5438 skip_past_char (&str
, '#');
5440 /* We must not accidentally parse an integer as a floating-point number. Make
5441 sure that the value we parse is not an integer by checking for special
5442 characters '.' or 'e'.
5443 FIXME: This is a horrible hack, but doing better is tricky because type
5444 information isn't in a very usable state at parse time. */
5446 skip_whitespace (fpnum
);
5448 if (strncmp (fpnum
, "0x", 2) == 0)
5452 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5453 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5463 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5465 unsigned fpword
= 0;
5468 /* Our FP word must be 32 bits (single-precision FP). */
5469 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5471 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5475 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5488 /* Shift operands. */
5491 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5494 struct asm_shift_name
5497 enum shift_kind kind
;
5500 /* Third argument to parse_shift. */
5501 enum parse_shift_mode
5503 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5504 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5505 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5506 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5507 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5508 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5511 /* Parse a <shift> specifier on an ARM data processing instruction.
5512 This has three forms:
5514 (LSL|LSR|ASL|ASR|ROR) Rs
5515 (LSL|LSR|ASL|ASR|ROR) #imm
5518 Note that ASL is assimilated to LSL in the instruction encoding, and
5519 RRX to ROR #0 (which cannot be written as such). */
5522 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5524 const struct asm_shift_name
*shift_name
;
5525 enum shift_kind shift
;
5530 for (p
= *str
; ISALPHA (*p
); p
++)
5535 inst
.error
= _("shift expression expected");
5540 = (const struct asm_shift_name
*) str_hash_find_n (arm_shift_hsh
, *str
,
5543 if (shift_name
== NULL
)
5545 inst
.error
= _("shift expression expected");
5549 shift
= shift_name
->kind
;
5553 case NO_SHIFT_RESTRICT
:
5554 case SHIFT_IMMEDIATE
:
5555 if (shift
== SHIFT_UXTW
)
5557 inst
.error
= _("'UXTW' not allowed here");
5562 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5563 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5565 inst
.error
= _("'LSL' or 'ASR' required");
5570 case SHIFT_LSL_IMMEDIATE
:
5571 if (shift
!= SHIFT_LSL
)
5573 inst
.error
= _("'LSL' required");
5578 case SHIFT_ASR_IMMEDIATE
:
5579 if (shift
!= SHIFT_ASR
)
5581 inst
.error
= _("'ASR' required");
5585 case SHIFT_UXTW_IMMEDIATE
:
5586 if (shift
!= SHIFT_UXTW
)
5588 inst
.error
= _("'UXTW' required");
5596 if (shift
!= SHIFT_RRX
)
5598 /* Whitespace can appear here if the next thing is a bare digit. */
5599 skip_whitespace (p
);
5601 if (mode
== NO_SHIFT_RESTRICT
5602 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5604 inst
.operands
[i
].imm
= reg
;
5605 inst
.operands
[i
].immisreg
= 1;
5607 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5610 inst
.operands
[i
].shift_kind
= shift
;
5611 inst
.operands
[i
].shifted
= 1;
5616 /* Parse a <shifter_operand> for an ARM data processing instruction:
5619 #<immediate>, <rotate>
5623 where <shift> is defined by parse_shift above, and <rotate> is a
5624 multiple of 2 between 0 and 30. Validation of immediate operands
5625 is deferred to md_apply_fix. */
5628 parse_shifter_operand (char **str
, int i
)
5633 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5635 inst
.operands
[i
].reg
= value
;
5636 inst
.operands
[i
].isreg
= 1;
5638 /* parse_shift will override this if appropriate */
5639 inst
.relocs
[0].exp
.X_op
= O_constant
;
5640 inst
.relocs
[0].exp
.X_add_number
= 0;
5642 if (skip_past_comma (str
) == FAIL
)
5645 /* Shift operation on register. */
5646 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5649 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5652 if (skip_past_comma (str
) == SUCCESS
)
5654 /* #x, y -- ie explicit rotation by Y. */
5655 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5658 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5660 inst
.error
= _("constant expression expected");
5664 value
= exp
.X_add_number
;
5665 if (value
< 0 || value
> 30 || value
% 2 != 0)
5667 inst
.error
= _("invalid rotation");
5670 if (inst
.relocs
[0].exp
.X_add_number
< 0
5671 || inst
.relocs
[0].exp
.X_add_number
> 255)
5673 inst
.error
= _("invalid constant");
5677 /* Encode as specified. */
5678 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5682 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5683 inst
.relocs
[0].pc_rel
= 0;
5687 /* Group relocation information. Each entry in the table contains the
5688 textual name of the relocation as may appear in assembler source
5689 and must end with a colon.
5690 Along with this textual name are the relocation codes to be used if
5691 the corresponding instruction is an ALU instruction (ADD or SUB only),
5692 an LDR, an LDRS, or an LDC. */
5694 struct group_reloc_table_entry
5705 /* Varieties of non-ALU group relocation. */
5713 static struct group_reloc_table_entry group_reloc_table
[] =
5714 { /* Program counter relative: */
5716 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5721 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5722 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5723 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5724 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5726 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5731 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5732 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5733 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5734 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5736 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5737 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5738 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5739 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5740 /* Section base relative */
5742 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5747 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5748 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5749 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5750 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5752 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5757 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5758 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5759 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5760 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5762 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5763 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5764 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5765 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5766 /* Absolute thumb alu relocations. */
5768 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5773 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5778 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5783 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5788 /* Given the address of a pointer pointing to the textual name of a group
5789 relocation as may appear in assembler source, attempt to find its details
5790 in group_reloc_table. The pointer will be updated to the character after
5791 the trailing colon. On failure, FAIL will be returned; SUCCESS
5792 otherwise. On success, *entry will be updated to point at the relevant
5793 group_reloc_table entry. */
5796 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5799 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5801 int length
= strlen (group_reloc_table
[i
].name
);
5803 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5804 && (*str
)[length
] == ':')
5806 *out
= &group_reloc_table
[i
];
5807 *str
+= (length
+ 1);
5815 /* Parse a <shifter_operand> for an ARM data processing instruction
5816 (as for parse_shifter_operand) where group relocations are allowed:
5819 #<immediate>, <rotate>
5820 #:<group_reloc>:<expression>
5824 where <group_reloc> is one of the strings defined in group_reloc_table.
5825 The hashes are optional.
5827 Everything else is as for parse_shifter_operand. */
5829 static parse_operand_result
5830 parse_shifter_operand_group_reloc (char **str
, int i
)
5832 /* Determine if we have the sequence of characters #: or just :
5833 coming next. If we do, then we check for a group relocation.
5834 If we don't, punt the whole lot to parse_shifter_operand. */
5836 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5837 || (*str
)[0] == ':')
5839 struct group_reloc_table_entry
*entry
;
5841 if ((*str
)[0] == '#')
5846 /* Try to parse a group relocation. Anything else is an error. */
5847 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5849 inst
.error
= _("unknown group relocation");
5850 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5853 /* We now have the group relocation table entry corresponding to
5854 the name in the assembler source. Next, we parse the expression. */
5855 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5856 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5858 /* Record the relocation type (always the ALU variant here). */
5859 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5860 gas_assert (inst
.relocs
[0].type
!= 0);
5862 return PARSE_OPERAND_SUCCESS
;
5865 return parse_shifter_operand (str
, i
) == SUCCESS
5866 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5868 /* Never reached. */
5871 /* Parse a Neon alignment expression. Information is written to
5872 inst.operands[i]. We assume the initial ':' has been skipped.
5874 align .imm = align << 8, .immisalign=1, .preind=0 */
5875 static parse_operand_result
5876 parse_neon_alignment (char **str
, int i
)
5881 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5883 if (exp
.X_op
!= O_constant
)
5885 inst
.error
= _("alignment must be constant");
5886 return PARSE_OPERAND_FAIL
;
5889 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5890 inst
.operands
[i
].immisalign
= 1;
5891 /* Alignments are not pre-indexes. */
5892 inst
.operands
[i
].preind
= 0;
5895 return PARSE_OPERAND_SUCCESS
;
5898 /* Parse all forms of an ARM address expression. Information is written
5899 to inst.operands[i] and/or inst.relocs[0].
5901 Preindexed addressing (.preind=1):
5903 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5904 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5905 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5906 .shift_kind=shift .relocs[0].exp=shift_imm
5908 These three may have a trailing ! which causes .writeback to be set also.
5910 Postindexed addressing (.postind=1, .writeback=1):
5912 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5913 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5914 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5915 .shift_kind=shift .relocs[0].exp=shift_imm
5917 Unindexed addressing (.preind=0, .postind=0):
5919 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5923 [Rn]{!} shorthand for [Rn,#0]{!}
5924 =immediate .isreg=0 .relocs[0].exp=immediate
5925 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5927 It is the caller's responsibility to check for addressing modes not
5928 supported by the instruction, and to set inst.relocs[0].type. */
5930 static parse_operand_result
5931 parse_address_main (char **str
, int i
, int group_relocations
,
5932 group_reloc_type group_type
)
5937 if (skip_past_char (&p
, '[') == FAIL
)
5939 if (skip_past_char (&p
, '=') == FAIL
)
5941 /* Bare address - translate to PC-relative offset. */
5942 inst
.relocs
[0].pc_rel
= 1;
5943 inst
.operands
[i
].reg
= REG_PC
;
5944 inst
.operands
[i
].isreg
= 1;
5945 inst
.operands
[i
].preind
= 1;
5947 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5948 return PARSE_OPERAND_FAIL
;
5950 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5951 /*allow_symbol_p=*/TRUE
))
5952 return PARSE_OPERAND_FAIL
;
5955 return PARSE_OPERAND_SUCCESS
;
5958 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5959 skip_whitespace (p
);
5961 if (group_type
== GROUP_MVE
)
5963 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5964 struct neon_type_el et
;
5965 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5967 inst
.operands
[i
].isquad
= 1;
5969 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5971 inst
.error
= BAD_ADDR_MODE
;
5972 return PARSE_OPERAND_FAIL
;
5975 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5977 if (group_type
== GROUP_MVE
)
5978 inst
.error
= BAD_ADDR_MODE
;
5980 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5981 return PARSE_OPERAND_FAIL
;
5983 inst
.operands
[i
].reg
= reg
;
5984 inst
.operands
[i
].isreg
= 1;
5986 if (skip_past_comma (&p
) == SUCCESS
)
5988 inst
.operands
[i
].preind
= 1;
5991 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5993 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5994 struct neon_type_el et
;
5995 if (group_type
== GROUP_MVE
5996 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5998 inst
.operands
[i
].immisreg
= 2;
5999 inst
.operands
[i
].imm
= reg
;
6001 if (skip_past_comma (&p
) == SUCCESS
)
6003 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
6005 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
6006 inst
.relocs
[0].exp
.X_add_number
= 0;
6009 return PARSE_OPERAND_FAIL
;
6012 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6014 inst
.operands
[i
].imm
= reg
;
6015 inst
.operands
[i
].immisreg
= 1;
6017 if (skip_past_comma (&p
) == SUCCESS
)
6018 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6019 return PARSE_OPERAND_FAIL
;
6021 else if (skip_past_char (&p
, ':') == SUCCESS
)
6023 /* FIXME: '@' should be used here, but it's filtered out by generic
6024 code before we get to see it here. This may be subject to
6026 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6028 if (result
!= PARSE_OPERAND_SUCCESS
)
6033 if (inst
.operands
[i
].negative
)
6035 inst
.operands
[i
].negative
= 0;
6039 if (group_relocations
6040 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
6042 struct group_reloc_table_entry
*entry
;
6044 /* Skip over the #: or : sequence. */
6050 /* Try to parse a group relocation. Anything else is an
6052 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
6054 inst
.error
= _("unknown group relocation");
6055 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6058 /* We now have the group relocation table entry corresponding to
6059 the name in the assembler source. Next, we parse the
6061 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6062 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6064 /* Record the relocation type. */
6069 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
6074 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
6079 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
6086 if (inst
.relocs
[0].type
== 0)
6088 inst
.error
= _("this group relocation is not allowed on this instruction");
6089 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6096 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6097 return PARSE_OPERAND_FAIL
;
6098 /* If the offset is 0, find out if it's a +0 or -0. */
6099 if (inst
.relocs
[0].exp
.X_op
== O_constant
6100 && inst
.relocs
[0].exp
.X_add_number
== 0)
6102 skip_whitespace (q
);
6106 skip_whitespace (q
);
6109 inst
.operands
[i
].negative
= 1;
6114 else if (skip_past_char (&p
, ':') == SUCCESS
)
6116 /* FIXME: '@' should be used here, but it's filtered out by generic code
6117 before we get to see it here. This may be subject to change. */
6118 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6120 if (result
!= PARSE_OPERAND_SUCCESS
)
6124 if (skip_past_char (&p
, ']') == FAIL
)
6126 inst
.error
= _("']' expected");
6127 return PARSE_OPERAND_FAIL
;
6130 if (skip_past_char (&p
, '!') == SUCCESS
)
6131 inst
.operands
[i
].writeback
= 1;
6133 else if (skip_past_comma (&p
) == SUCCESS
)
6135 if (skip_past_char (&p
, '{') == SUCCESS
)
6137 /* [Rn], {expr} - unindexed, with option */
6138 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6139 0, 255, TRUE
) == FAIL
)
6140 return PARSE_OPERAND_FAIL
;
6142 if (skip_past_char (&p
, '}') == FAIL
)
6144 inst
.error
= _("'}' expected at end of 'option' field");
6145 return PARSE_OPERAND_FAIL
;
6147 if (inst
.operands
[i
].preind
)
6149 inst
.error
= _("cannot combine index with option");
6150 return PARSE_OPERAND_FAIL
;
6153 return PARSE_OPERAND_SUCCESS
;
6157 inst
.operands
[i
].postind
= 1;
6158 inst
.operands
[i
].writeback
= 1;
6160 if (inst
.operands
[i
].preind
)
6162 inst
.error
= _("cannot combine pre- and post-indexing");
6163 return PARSE_OPERAND_FAIL
;
6167 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6169 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6170 struct neon_type_el et
;
6171 if (group_type
== GROUP_MVE
6172 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6174 inst
.operands
[i
].immisreg
= 2;
6175 inst
.operands
[i
].imm
= reg
;
6177 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6179 /* We might be using the immediate for alignment already. If we
6180 are, OR the register number into the low-order bits. */
6181 if (inst
.operands
[i
].immisalign
)
6182 inst
.operands
[i
].imm
|= reg
;
6184 inst
.operands
[i
].imm
= reg
;
6185 inst
.operands
[i
].immisreg
= 1;
6187 if (skip_past_comma (&p
) == SUCCESS
)
6188 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6189 return PARSE_OPERAND_FAIL
;
6195 if (inst
.operands
[i
].negative
)
6197 inst
.operands
[i
].negative
= 0;
6200 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6201 return PARSE_OPERAND_FAIL
;
6202 /* If the offset is 0, find out if it's a +0 or -0. */
6203 if (inst
.relocs
[0].exp
.X_op
== O_constant
6204 && inst
.relocs
[0].exp
.X_add_number
== 0)
6206 skip_whitespace (q
);
6210 skip_whitespace (q
);
6213 inst
.operands
[i
].negative
= 1;
6219 /* If at this point neither .preind nor .postind is set, we have a
6220 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6221 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6223 inst
.operands
[i
].preind
= 1;
6224 inst
.relocs
[0].exp
.X_op
= O_constant
;
6225 inst
.relocs
[0].exp
.X_add_number
= 0;
6228 return PARSE_OPERAND_SUCCESS
;
6232 parse_address (char **str
, int i
)
6234 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6238 static parse_operand_result
6239 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6241 return parse_address_main (str
, i
, 1, type
);
6244 /* Parse an operand for a MOVW or MOVT instruction. */
6246 parse_half (char **str
)
6251 skip_past_char (&p
, '#');
6252 if (strncasecmp (p
, ":lower16:", 9) == 0)
6253 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6254 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6255 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6257 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6260 skip_whitespace (p
);
6263 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6266 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6268 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6270 inst
.error
= _("constant expression expected");
6273 if (inst
.relocs
[0].exp
.X_add_number
< 0
6274 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6276 inst
.error
= _("immediate value out of range");
6284 /* Miscellaneous. */
6286 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6287 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6289 parse_psr (char **str
, bfd_boolean lhs
)
6292 unsigned long psr_field
;
6293 const struct asm_psr
*psr
;
6295 bfd_boolean is_apsr
= FALSE
;
6296 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6298 /* PR gas/12698: If the user has specified -march=all then m_profile will
6299 be TRUE, but we want to ignore it in this case as we are building for any
6300 CPU type, including non-m variants. */
6301 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6304 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6305 feature for ease of use and backwards compatibility. */
6307 if (strncasecmp (p
, "SPSR", 4) == 0)
6310 goto unsupported_psr
;
6312 psr_field
= SPSR_BIT
;
6314 else if (strncasecmp (p
, "CPSR", 4) == 0)
6317 goto unsupported_psr
;
6321 else if (strncasecmp (p
, "APSR", 4) == 0)
6323 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6324 and ARMv7-R architecture CPUs. */
6333 while (ISALNUM (*p
) || *p
== '_');
6335 if (strncasecmp (start
, "iapsr", 5) == 0
6336 || strncasecmp (start
, "eapsr", 5) == 0
6337 || strncasecmp (start
, "xpsr", 4) == 0
6338 || strncasecmp (start
, "psr", 3) == 0)
6339 p
= start
+ strcspn (start
, "rR") + 1;
6341 psr
= (const struct asm_psr
*) str_hash_find_n (arm_v7m_psr_hsh
, start
,
6347 /* If APSR is being written, a bitfield may be specified. Note that
6348 APSR itself is handled above. */
6349 if (psr
->field
<= 3)
6351 psr_field
= psr
->field
;
6357 /* M-profile MSR instructions have the mask field set to "10", except
6358 *PSR variants which modify APSR, which may use a different mask (and
6359 have been handled already). Do that by setting the PSR_f field
6361 return psr
->field
| (lhs
? PSR_f
: 0);
6364 goto unsupported_psr
;
6370 /* A suffix follows. */
6376 while (ISALNUM (*p
) || *p
== '_');
6380 /* APSR uses a notation for bits, rather than fields. */
6381 unsigned int nzcvq_bits
= 0;
6382 unsigned int g_bit
= 0;
6385 for (bit
= start
; bit
!= p
; bit
++)
6387 switch (TOLOWER (*bit
))
6390 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6394 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6398 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6402 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6406 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6410 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6414 inst
.error
= _("unexpected bit specified after APSR");
6419 if (nzcvq_bits
== 0x1f)
6424 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6426 inst
.error
= _("selected processor does not "
6427 "support DSP extension");
6434 if ((nzcvq_bits
& 0x20) != 0
6435 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6436 || (g_bit
& 0x2) != 0)
6438 inst
.error
= _("bad bitmask specified after APSR");
6444 psr
= (const struct asm_psr
*) str_hash_find_n (arm_psr_hsh
, start
,
6449 psr_field
|= psr
->field
;
6455 goto error
; /* Garbage after "[CS]PSR". */
6457 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6458 is deprecated, but allow it anyway. */
6462 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6465 else if (!m_profile
)
6466 /* These bits are never right for M-profile devices: don't set them
6467 (only code paths which read/write APSR reach here). */
6468 psr_field
|= (PSR_c
| PSR_f
);
6474 inst
.error
= _("selected processor does not support requested special "
6475 "purpose register");
6479 inst
.error
= _("flag for {c}psr instruction expected");
6484 parse_sys_vldr_vstr (char **str
)
6493 {"FPSCR", 0x1, 0x0},
6494 {"FPSCR_nzcvqc", 0x2, 0x0},
6497 {"FPCXTNS", 0x6, 0x1},
6498 {"FPCXTS", 0x7, 0x1}
6500 char *op_end
= strchr (*str
, ',');
6501 size_t op_strlen
= op_end
- *str
;
6503 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6505 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6507 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6516 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6517 value suitable for splatting into the AIF field of the instruction. */
6520 parse_cps_flags (char **str
)
6529 case '\0': case ',':
6532 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6533 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6534 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6537 inst
.error
= _("unrecognized CPS flag");
6542 if (saw_a_flag
== 0)
6544 inst
.error
= _("missing CPS flags");
6552 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6553 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6556 parse_endian_specifier (char **str
)
6561 if (strncasecmp (s
, "BE", 2))
6563 else if (strncasecmp (s
, "LE", 2))
6567 inst
.error
= _("valid endian specifiers are be or le");
6571 if (ISALNUM (s
[2]) || s
[2] == '_')
6573 inst
.error
= _("valid endian specifiers are be or le");
6578 return little_endian
;
6581 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6582 value suitable for poking into the rotate field of an sxt or sxta
6583 instruction, or FAIL on error. */
6586 parse_ror (char **str
)
6591 if (strncasecmp (s
, "ROR", 3) == 0)
6595 inst
.error
= _("missing rotation field after comma");
6599 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6604 case 0: *str
= s
; return 0x0;
6605 case 8: *str
= s
; return 0x1;
6606 case 16: *str
= s
; return 0x2;
6607 case 24: *str
= s
; return 0x3;
6610 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6615 /* Parse a conditional code (from conds[] below). The value returned is in the
6616 range 0 .. 14, or FAIL. */
6618 parse_cond (char **str
)
6621 const struct asm_cond
*c
;
6623 /* Condition codes are always 2 characters, so matching up to
6624 3 characters is sufficient. */
6629 while (ISALPHA (*q
) && n
< 3)
6631 cond
[n
] = TOLOWER (*q
);
6636 c
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, cond
, n
);
6639 inst
.error
= _("condition required");
6647 /* Parse an option for a barrier instruction. Returns the encoding for the
6650 parse_barrier (char **str
)
6653 const struct asm_barrier_opt
*o
;
6656 while (ISALPHA (*q
))
6659 o
= (const struct asm_barrier_opt
*) str_hash_find_n (arm_barrier_opt_hsh
, p
,
6664 if (!mark_feature_used (&o
->arch
))
6671 /* Parse the operands of a table branch instruction. Similar to a memory
6674 parse_tb (char **str
)
6679 if (skip_past_char (&p
, '[') == FAIL
)
6681 inst
.error
= _("'[' expected");
6685 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6687 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6690 inst
.operands
[0].reg
= reg
;
6692 if (skip_past_comma (&p
) == FAIL
)
6694 inst
.error
= _("',' expected");
6698 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6700 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6703 inst
.operands
[0].imm
= reg
;
6705 if (skip_past_comma (&p
) == SUCCESS
)
6707 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6709 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6711 inst
.error
= _("invalid shift");
6714 inst
.operands
[0].shifted
= 1;
6717 if (skip_past_char (&p
, ']') == FAIL
)
6719 inst
.error
= _("']' expected");
6726 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6727 information on the types the operands can take and how they are encoded.
6728 Up to four operands may be read; this function handles setting the
6729 ".present" field for each read operand itself.
6730 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6731 else returns FAIL. */
6734 parse_neon_mov (char **str
, int *which_operand
)
6736 int i
= *which_operand
, val
;
6737 enum arm_reg_type rtype
;
6739 struct neon_type_el optype
;
6741 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6743 /* Cases 17 or 19. */
6744 inst
.operands
[i
].reg
= val
;
6745 inst
.operands
[i
].isvec
= 1;
6746 inst
.operands
[i
].isscalar
= 2;
6747 inst
.operands
[i
].vectype
= optype
;
6748 inst
.operands
[i
++].present
= 1;
6750 if (skip_past_comma (&ptr
) == FAIL
)
6753 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6755 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6756 inst
.operands
[i
].reg
= val
;
6757 inst
.operands
[i
].isreg
= 1;
6758 inst
.operands
[i
].present
= 1;
6760 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6762 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6763 inst
.operands
[i
].reg
= val
;
6764 inst
.operands
[i
].isvec
= 1;
6765 inst
.operands
[i
].isscalar
= 2;
6766 inst
.operands
[i
].vectype
= optype
;
6767 inst
.operands
[i
++].present
= 1;
6769 if (skip_past_comma (&ptr
) == FAIL
)
6772 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6775 inst
.operands
[i
].reg
= val
;
6776 inst
.operands
[i
].isreg
= 1;
6777 inst
.operands
[i
++].present
= 1;
6779 if (skip_past_comma (&ptr
) == FAIL
)
6782 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6785 inst
.operands
[i
].reg
= val
;
6786 inst
.operands
[i
].isreg
= 1;
6787 inst
.operands
[i
].present
= 1;
6791 first_error (_("expected ARM or MVE vector register"));
6795 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6797 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6798 inst
.operands
[i
].reg
= val
;
6799 inst
.operands
[i
].isscalar
= 1;
6800 inst
.operands
[i
].vectype
= optype
;
6801 inst
.operands
[i
++].present
= 1;
6803 if (skip_past_comma (&ptr
) == FAIL
)
6806 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6809 inst
.operands
[i
].reg
= val
;
6810 inst
.operands
[i
].isreg
= 1;
6811 inst
.operands
[i
].present
= 1;
6813 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6815 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6818 /* Cases 0, 1, 2, 3, 5 (D only). */
6819 if (skip_past_comma (&ptr
) == FAIL
)
6822 inst
.operands
[i
].reg
= val
;
6823 inst
.operands
[i
].isreg
= 1;
6824 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6825 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6826 inst
.operands
[i
].isvec
= 1;
6827 inst
.operands
[i
].vectype
= optype
;
6828 inst
.operands
[i
++].present
= 1;
6830 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6832 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6833 Case 13: VMOV <Sd>, <Rm> */
6834 inst
.operands
[i
].reg
= val
;
6835 inst
.operands
[i
].isreg
= 1;
6836 inst
.operands
[i
].present
= 1;
6838 if (rtype
== REG_TYPE_NQ
)
6840 first_error (_("can't use Neon quad register here"));
6843 else if (rtype
!= REG_TYPE_VFS
)
6846 if (skip_past_comma (&ptr
) == FAIL
)
6848 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6850 inst
.operands
[i
].reg
= val
;
6851 inst
.operands
[i
].isreg
= 1;
6852 inst
.operands
[i
].present
= 1;
6855 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6857 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
,
6860 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6861 Case 1: VMOV<c><q> <Dd>, <Dm>
6862 Case 8: VMOV.F32 <Sd>, <Sm>
6863 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6865 inst
.operands
[i
].reg
= val
;
6866 inst
.operands
[i
].isreg
= 1;
6867 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6868 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6869 inst
.operands
[i
].isvec
= 1;
6870 inst
.operands
[i
].vectype
= optype
;
6871 inst
.operands
[i
].present
= 1;
6873 if (skip_past_comma (&ptr
) == SUCCESS
)
6878 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6881 inst
.operands
[i
].reg
= val
;
6882 inst
.operands
[i
].isreg
= 1;
6883 inst
.operands
[i
++].present
= 1;
6885 if (skip_past_comma (&ptr
) == FAIL
)
6888 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6891 inst
.operands
[i
].reg
= val
;
6892 inst
.operands
[i
].isreg
= 1;
6893 inst
.operands
[i
].present
= 1;
6896 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6897 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6898 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6899 Case 10: VMOV.F32 <Sd>, #<imm>
6900 Case 11: VMOV.F64 <Dd>, #<imm> */
6901 inst
.operands
[i
].immisfloat
= 1;
6902 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6904 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6905 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6909 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6913 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6915 /* Cases 6, 7, 16, 18. */
6916 inst
.operands
[i
].reg
= val
;
6917 inst
.operands
[i
].isreg
= 1;
6918 inst
.operands
[i
++].present
= 1;
6920 if (skip_past_comma (&ptr
) == FAIL
)
6923 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6925 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6926 inst
.operands
[i
].reg
= val
;
6927 inst
.operands
[i
].isscalar
= 2;
6928 inst
.operands
[i
].present
= 1;
6929 inst
.operands
[i
].vectype
= optype
;
6931 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6933 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6934 inst
.operands
[i
].reg
= val
;
6935 inst
.operands
[i
].isscalar
= 1;
6936 inst
.operands
[i
].present
= 1;
6937 inst
.operands
[i
].vectype
= optype
;
6939 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6941 inst
.operands
[i
].reg
= val
;
6942 inst
.operands
[i
].isreg
= 1;
6943 inst
.operands
[i
++].present
= 1;
6945 if (skip_past_comma (&ptr
) == FAIL
)
6948 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6951 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6953 inst
.operands
[i
].reg
= val
;
6954 inst
.operands
[i
].isreg
= 1;
6955 inst
.operands
[i
].isvec
= 1;
6956 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6957 inst
.operands
[i
].vectype
= optype
;
6958 inst
.operands
[i
].present
= 1;
6960 if (rtype
== REG_TYPE_VFS
)
6964 if (skip_past_comma (&ptr
) == FAIL
)
6966 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6969 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6972 inst
.operands
[i
].reg
= val
;
6973 inst
.operands
[i
].isreg
= 1;
6974 inst
.operands
[i
].isvec
= 1;
6975 inst
.operands
[i
].issingle
= 1;
6976 inst
.operands
[i
].vectype
= optype
;
6977 inst
.operands
[i
].present
= 1;
6982 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6985 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6986 inst
.operands
[i
].reg
= val
;
6987 inst
.operands
[i
].isvec
= 1;
6988 inst
.operands
[i
].isscalar
= 2;
6989 inst
.operands
[i
].vectype
= optype
;
6990 inst
.operands
[i
++].present
= 1;
6992 if (skip_past_comma (&ptr
) == FAIL
)
6995 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6998 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
7001 inst
.operands
[i
].reg
= val
;
7002 inst
.operands
[i
].isvec
= 1;
7003 inst
.operands
[i
].isscalar
= 2;
7004 inst
.operands
[i
].vectype
= optype
;
7005 inst
.operands
[i
].present
= 1;
7009 first_error (_("VFP single, double or MVE vector register"
7015 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
7019 inst
.operands
[i
].reg
= val
;
7020 inst
.operands
[i
].isreg
= 1;
7021 inst
.operands
[i
].isvec
= 1;
7022 inst
.operands
[i
].issingle
= 1;
7023 inst
.operands
[i
].vectype
= optype
;
7024 inst
.operands
[i
].present
= 1;
7029 first_error (_("parse error"));
7033 /* Successfully parsed the operands. Update args. */
7039 first_error (_("expected comma"));
7043 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
7047 /* Use this macro when the operand constraints are different
7048 for ARM and THUMB (e.g. ldrd). */
7049 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
7050 ((arm_operand) | ((thumb_operand) << 16))
7052 /* Matcher codes for parse_operands. */
7053 enum operand_parse_code
7055 OP_stop
, /* end of line */
7057 OP_RR
, /* ARM register */
7058 OP_RRnpc
, /* ARM register, not r15 */
7059 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
7060 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
7061 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
7062 optional trailing ! */
7063 OP_RRw
, /* ARM register, not r15, optional trailing ! */
7064 OP_RCP
, /* Coprocessor number */
7065 OP_RCN
, /* Coprocessor register */
7066 OP_RF
, /* FPA register */
7067 OP_RVS
, /* VFP single precision register */
7068 OP_RVD
, /* VFP double precision register (0..15) */
7069 OP_RND
, /* Neon double precision register (0..31) */
7070 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
7071 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
7073 OP_RNSDMQR
, /* Neon single or double precision, MVE vector or ARM register.
7075 OP_RNQ
, /* Neon quad precision register */
7076 OP_RNQMQ
, /* Neon quad or MVE vector register. */
7077 OP_RVSD
, /* VFP single or double precision register */
7078 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
7079 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
7080 OP_RNSD
, /* Neon single or double precision register */
7081 OP_RNDQ
, /* Neon double or quad precision register */
7082 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
7083 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
7084 OP_RNSDQ
, /* Neon single, double or quad precision register */
7085 OP_RNSC
, /* Neon scalar D[X] */
7086 OP_RVC
, /* VFP control register */
7087 OP_RMF
, /* Maverick F register */
7088 OP_RMD
, /* Maverick D register */
7089 OP_RMFX
, /* Maverick FX register */
7090 OP_RMDX
, /* Maverick DX register */
7091 OP_RMAX
, /* Maverick AX register */
7092 OP_RMDS
, /* Maverick DSPSC register */
7093 OP_RIWR
, /* iWMMXt wR register */
7094 OP_RIWC
, /* iWMMXt wC register */
7095 OP_RIWG
, /* iWMMXt wCG register */
7096 OP_RXA
, /* XScale accumulator register */
7098 OP_RNSDMQ
, /* Neon single, double or MVE vector register */
7099 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
7101 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
7103 OP_RMQ
, /* MVE vector register. */
7104 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
7105 OP_RMQRR
, /* MVE vector or ARM register. */
7107 /* New operands for Armv8.1-M Mainline. */
7108 OP_LR
, /* ARM LR register */
7109 OP_RRe
, /* ARM register, only even numbered. */
7110 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
7111 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7112 OP_RR_ZR
, /* ARM register or ZR but no PC */
7114 OP_REGLST
, /* ARM register list */
7115 OP_CLRMLST
, /* CLRM register list */
7116 OP_VRSLST
, /* VFP single-precision register list */
7117 OP_VRDLST
, /* VFP double-precision register list */
7118 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7119 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7120 OP_NSTRLST
, /* Neon element/structure list */
7121 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7122 OP_MSTRLST2
, /* MVE vector list with two elements. */
7123 OP_MSTRLST4
, /* MVE vector list with four elements. */
7125 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7126 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7127 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7128 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7130 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7131 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7132 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7133 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7135 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7136 scalar, or ARM register. */
7137 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7138 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7139 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7141 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7142 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7143 OP_VMOV
, /* Neon VMOV operands. */
7144 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7145 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7147 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7148 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7150 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7151 OP_VLDR
, /* VLDR operand. */
7153 OP_I0
, /* immediate zero */
7154 OP_I7
, /* immediate value 0 .. 7 */
7155 OP_I15
, /* 0 .. 15 */
7156 OP_I16
, /* 1 .. 16 */
7157 OP_I16z
, /* 0 .. 16 */
7158 OP_I31
, /* 0 .. 31 */
7159 OP_I31w
, /* 0 .. 31, optional trailing ! */
7160 OP_I32
, /* 1 .. 32 */
7161 OP_I32z
, /* 0 .. 32 */
7162 OP_I48_I64
, /* 48 or 64 */
7163 OP_I63
, /* 0 .. 63 */
7164 OP_I63s
, /* -64 .. 63 */
7165 OP_I64
, /* 1 .. 64 */
7166 OP_I64z
, /* 0 .. 64 */
7167 OP_I127
, /* 0 .. 127 */
7168 OP_I255
, /* 0 .. 255 */
7169 OP_I511
, /* 0 .. 511 */
7170 OP_I4095
, /* 0 .. 4095 */
7171 OP_I8191
, /* 0 .. 8191 */
7172 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7173 OP_I7b
, /* 0 .. 7 */
7174 OP_I15b
, /* 0 .. 15 */
7175 OP_I31b
, /* 0 .. 31 */
7177 OP_SH
, /* shifter operand */
7178 OP_SHG
, /* shifter operand with possible group relocation */
7179 OP_ADDR
, /* Memory address expression (any mode) */
7180 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7181 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7182 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7183 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7184 OP_EXP
, /* arbitrary expression */
7185 OP_EXPi
, /* same, with optional immediate prefix */
7186 OP_EXPr
, /* same, with optional relocation suffix */
7187 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7188 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7189 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7190 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7192 OP_CPSF
, /* CPS flags */
7193 OP_ENDI
, /* Endianness specifier */
7194 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7195 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7196 OP_COND
, /* conditional code */
7197 OP_TB
, /* Table branch. */
7199 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7201 OP_RRnpc_I0
, /* ARM register or literal 0 */
7202 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7203 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7204 OP_RF_IF
, /* FPA register or immediate */
7205 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7206 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7208 /* Optional operands. */
7209 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7210 OP_oI31b
, /* 0 .. 31 */
7211 OP_oI32b
, /* 1 .. 32 */
7212 OP_oI32z
, /* 0 .. 32 */
7213 OP_oIffffb
, /* 0 .. 65535 */
7214 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7216 OP_oRR
, /* ARM register */
7217 OP_oLR
, /* ARM LR register */
7218 OP_oRRnpc
, /* ARM register, not the PC */
7219 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7220 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7221 OP_oRND
, /* Optional Neon double precision register */
7222 OP_oRNQ
, /* Optional Neon quad precision register */
7223 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7224 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7225 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7226 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7228 OP_oRNSDMQ
, /* Optional single, double register or MVE vector
7230 OP_oSHll
, /* LSL immediate */
7231 OP_oSHar
, /* ASR immediate */
7232 OP_oSHllar
, /* LSL or ASR immediate */
7233 OP_oROR
, /* ROR 0/8/16/24 */
7234 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7236 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7238 /* Some pre-defined mixed (ARM/THUMB) operands. */
7239 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7240 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7241 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7243 OP_FIRST_OPTIONAL
= OP_oI7b
7246 /* Generic instruction operand parser. This does no encoding and no
7247 semantic validation; it merely squirrels values away in the inst
7248 structure. Returns SUCCESS or FAIL depending on whether the
7249 specified grammar matched. */
7251 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7253 unsigned const int *upat
= pattern
;
7254 char *backtrack_pos
= 0;
7255 const char *backtrack_error
= 0;
7256 int i
, val
= 0, backtrack_index
= 0;
7257 enum arm_reg_type rtype
;
7258 parse_operand_result result
;
7259 unsigned int op_parse_code
;
7260 bfd_boolean partial_match
;
7262 #define po_char_or_fail(chr) \
7265 if (skip_past_char (&str, chr) == FAIL) \
7270 #define po_reg_or_fail(regtype) \
7273 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7274 & inst.operands[i].vectype); \
7277 first_error (_(reg_expected_msgs[regtype])); \
7280 inst.operands[i].reg = val; \
7281 inst.operands[i].isreg = 1; \
7282 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7283 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7284 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7285 || rtype == REG_TYPE_VFD \
7286 || rtype == REG_TYPE_NQ); \
7287 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7291 #define po_reg_or_goto(regtype, label) \
7294 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7295 & inst.operands[i].vectype); \
7299 inst.operands[i].reg = val; \
7300 inst.operands[i].isreg = 1; \
7301 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7302 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7303 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7304 || rtype == REG_TYPE_VFD \
7305 || rtype == REG_TYPE_NQ); \
7306 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7310 #define po_imm_or_fail(min, max, popt) \
7313 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7315 inst.operands[i].imm = val; \
7319 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7323 my_get_expression (&exp, &str, popt); \
7324 if (exp.X_op != O_constant) \
7326 inst.error = _("constant expression required"); \
7329 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7331 inst.error = _("immediate value 48 or 64 expected"); \
7334 inst.operands[i].imm = exp.X_add_number; \
7338 #define po_scalar_or_goto(elsz, label, reg_type) \
7341 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7345 inst.operands[i].reg = val; \
7346 inst.operands[i].isscalar = 1; \
7350 #define po_misc_or_fail(expr) \
7358 #define po_misc_or_fail_no_backtrack(expr) \
7362 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7363 backtrack_pos = 0; \
7364 if (result != PARSE_OPERAND_SUCCESS) \
7369 #define po_barrier_or_imm(str) \
7372 val = parse_barrier (&str); \
7373 if (val == FAIL && ! ISALPHA (*str)) \
7376 /* ISB can only take SY as an option. */ \
7377 || ((inst.instruction & 0xf0) == 0x60 \
7380 inst.error = _("invalid barrier type"); \
7381 backtrack_pos = 0; \
7387 skip_whitespace (str
);
7389 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7391 op_parse_code
= upat
[i
];
7392 if (op_parse_code
>= 1<<16)
7393 op_parse_code
= thumb
? (op_parse_code
>> 16)
7394 : (op_parse_code
& ((1<<16)-1));
7396 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7398 /* Remember where we are in case we need to backtrack. */
7399 backtrack_pos
= str
;
7400 backtrack_error
= inst
.error
;
7401 backtrack_index
= i
;
7404 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7405 po_char_or_fail (',');
7407 switch (op_parse_code
)
7419 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7420 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7421 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7422 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7423 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7424 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7427 po_reg_or_goto (REG_TYPE_VFS
, try_rndmqr
);
7431 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7435 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7438 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7440 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7442 /* Also accept generic coprocessor regs for unknown registers. */
7444 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7446 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7447 existing register with a value of 0, this seems like the
7448 best way to parse P0. */
7450 if (strncasecmp (str
, "P0", 2) == 0)
7453 inst
.operands
[i
].isreg
= 1;
7454 inst
.operands
[i
].reg
= 13;
7459 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7460 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7461 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7462 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7463 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7464 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7465 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7466 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7467 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7468 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7471 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7474 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7475 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7477 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7482 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7486 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7488 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7491 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7493 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7497 po_reg_or_goto (REG_TYPE_NSD
, try_mq2
);
7500 po_reg_or_fail (REG_TYPE_MQ
);
7503 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7505 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7510 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7513 po_reg_or_fail (REG_TYPE_NSDQ
);
7517 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7521 po_reg_or_fail (REG_TYPE_MQ
);
7523 /* Neon scalar. Using an element size of 8 means that some invalid
7524 scalars are accepted here, so deal with those in later code. */
7525 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7529 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7532 po_imm_or_fail (0, 0, TRUE
);
7537 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7541 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7546 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7549 if (parse_ifimm_zero (&str
))
7550 inst
.operands
[i
].imm
= 0;
7554 = _("only floating point zero is allowed as immediate value");
7562 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7565 po_reg_or_fail (REG_TYPE_RN
);
7569 case OP_RNSDQ_RNSC_MQ_RR
:
7570 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7573 case OP_RNSDQ_RNSC_MQ
:
7574 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7579 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7583 po_reg_or_fail (REG_TYPE_NSDQ
);
7590 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7593 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7596 po_reg_or_fail (REG_TYPE_NSD
);
7600 case OP_RNDQMQ_RNSC_RR
:
7601 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7604 case OP_RNDQ_RNSC_RR
:
7605 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7607 case OP_RNDQMQ_RNSC
:
7608 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7613 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7616 po_reg_or_fail (REG_TYPE_NDQ
);
7622 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7625 po_reg_or_fail (REG_TYPE_VFD
);
7630 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7631 not careful then bad things might happen. */
7632 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7635 case OP_RNDQMQ_Ibig
:
7636 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7641 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7644 /* There's a possibility of getting a 64-bit immediate here, so
7645 we need special handling. */
7646 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7649 inst
.error
= _("immediate value is out of range");
7655 case OP_RNDQMQ_I63b_RR
:
7656 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7659 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7664 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7667 po_imm_or_fail (0, 63, TRUE
);
7672 po_char_or_fail ('[');
7673 po_reg_or_fail (REG_TYPE_RN
);
7674 po_char_or_fail (']');
7680 po_reg_or_fail (REG_TYPE_RN
);
7681 if (skip_past_char (&str
, '!') == SUCCESS
)
7682 inst
.operands
[i
].writeback
= 1;
7686 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7687 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7688 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7689 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7690 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7691 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7692 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7693 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, FALSE
); break;
7694 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7695 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7696 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7697 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7698 case OP_I127
: po_imm_or_fail ( 0, 127, FALSE
); break;
7699 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7700 case OP_I511
: po_imm_or_fail ( 0, 511, FALSE
); break;
7701 case OP_I4095
: po_imm_or_fail ( 0, 4095, FALSE
); break;
7702 case OP_I8191
: po_imm_or_fail ( 0, 8191, FALSE
); break;
7703 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7705 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7706 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7708 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7709 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7710 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7711 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7713 /* Immediate variants */
7715 po_char_or_fail ('{');
7716 po_imm_or_fail (0, 255, TRUE
);
7717 po_char_or_fail ('}');
7721 /* The expression parser chokes on a trailing !, so we have
7722 to find it first and zap it. */
7725 while (*s
&& *s
!= ',')
7730 inst
.operands
[i
].writeback
= 1;
7732 po_imm_or_fail (0, 31, TRUE
);
7740 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7745 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7750 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7752 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7754 val
= parse_reloc (&str
);
7757 inst
.error
= _("unrecognized relocation suffix");
7760 else if (val
!= BFD_RELOC_UNUSED
)
7762 inst
.operands
[i
].imm
= val
;
7763 inst
.operands
[i
].hasreloc
= 1;
7769 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7771 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7773 inst
.operands
[i
].hasreloc
= 1;
7775 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7777 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7778 inst
.operands
[i
].hasreloc
= 0;
7782 /* Operand for MOVW or MOVT. */
7784 po_misc_or_fail (parse_half (&str
));
7787 /* Register or expression. */
7788 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7789 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7791 /* Register or immediate. */
7792 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7793 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7795 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7796 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7798 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7800 if (!is_immediate_prefix (*str
))
7803 val
= parse_fpa_immediate (&str
);
7806 /* FPA immediates are encoded as registers 8-15.
7807 parse_fpa_immediate has already applied the offset. */
7808 inst
.operands
[i
].reg
= val
;
7809 inst
.operands
[i
].isreg
= 1;
7812 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7813 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7815 /* Two kinds of register. */
7818 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7820 || (rege
->type
!= REG_TYPE_MMXWR
7821 && rege
->type
!= REG_TYPE_MMXWC
7822 && rege
->type
!= REG_TYPE_MMXWCG
))
7824 inst
.error
= _("iWMMXt data or control register expected");
7827 inst
.operands
[i
].reg
= rege
->number
;
7828 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7834 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7836 || (rege
->type
!= REG_TYPE_MMXWC
7837 && rege
->type
!= REG_TYPE_MMXWCG
))
7839 inst
.error
= _("iWMMXt control register expected");
7842 inst
.operands
[i
].reg
= rege
->number
;
7843 inst
.operands
[i
].isreg
= 1;
7848 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7849 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7850 case OP_oROR
: val
= parse_ror (&str
); break;
7852 case OP_COND
: val
= parse_cond (&str
); break;
7853 case OP_oBARRIER_I15
:
7854 po_barrier_or_imm (str
); break;
7856 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7862 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7863 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7865 inst
.error
= _("Banked registers are not available with this "
7871 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7875 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7878 val
= parse_sys_vldr_vstr (&str
);
7882 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7885 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7887 if (strncasecmp (str
, "APSR_", 5) == 0)
7894 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7895 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7896 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7897 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7898 default: found
= 16;
7902 inst
.operands
[i
].isvec
= 1;
7903 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7904 inst
.operands
[i
].reg
= REG_PC
;
7911 po_misc_or_fail (parse_tb (&str
));
7914 /* Register lists. */
7916 val
= parse_reg_list (&str
, REGLIST_RN
);
7919 inst
.operands
[i
].writeback
= 1;
7925 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7929 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7934 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7939 /* Allow Q registers too. */
7940 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7941 REGLIST_NEON_D
, &partial_match
);
7945 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7946 REGLIST_VFP_S
, &partial_match
);
7947 inst
.operands
[i
].issingle
= 1;
7952 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7953 REGLIST_VFP_D_VPR
, &partial_match
);
7954 if (val
== FAIL
&& !partial_match
)
7957 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7958 REGLIST_VFP_S_VPR
, &partial_match
);
7959 inst
.operands
[i
].issingle
= 1;
7964 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7965 REGLIST_NEON_D
, &partial_match
);
7970 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7971 1, &inst
.operands
[i
].vectype
);
7972 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7976 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7977 0, &inst
.operands
[i
].vectype
);
7980 /* Addressing modes */
7982 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7986 po_misc_or_fail (parse_address (&str
, i
));
7990 po_misc_or_fail_no_backtrack (
7991 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7995 po_misc_or_fail_no_backtrack (
7996 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
8000 po_misc_or_fail_no_backtrack (
8001 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
8005 po_misc_or_fail (parse_shifter_operand (&str
, i
));
8009 po_misc_or_fail_no_backtrack (
8010 parse_shifter_operand_group_reloc (&str
, i
));
8014 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
8018 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
8022 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
8027 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
8032 po_reg_or_goto (REG_TYPE_RN
, ZR
);
8035 po_reg_or_fail (REG_TYPE_ZR
);
8039 as_fatal (_("unhandled operand code %d"), op_parse_code
);
8042 /* Various value-based sanity checks and shared operations. We
8043 do not signal immediate failures for the register constraints;
8044 this allows a syntax error to take precedence. */
8045 switch (op_parse_code
)
8053 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
8054 inst
.error
= BAD_PC
;
8059 case OP_RRnpcsp_I32
:
8060 if (inst
.operands
[i
].isreg
)
8062 if (inst
.operands
[i
].reg
== REG_PC
)
8063 inst
.error
= BAD_PC
;
8064 else if (inst
.operands
[i
].reg
== REG_SP
8065 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
8066 relaxed since ARMv8-A. */
8067 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8070 inst
.error
= BAD_SP
;
8076 if (inst
.operands
[i
].isreg
8077 && inst
.operands
[i
].reg
== REG_PC
8078 && (inst
.operands
[i
].writeback
|| thumb
))
8079 inst
.error
= BAD_PC
;
8084 if (inst
.operands
[i
].isreg
)
8094 case OP_oBARRIER_I15
:
8107 inst
.operands
[i
].imm
= val
;
8112 if (inst
.operands
[i
].reg
!= REG_LR
)
8113 inst
.error
= _("operand must be LR register");
8119 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
8120 inst
.error
= BAD_PC
;
8124 if (inst
.operands
[i
].isreg
8125 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
8126 inst
.error
= BAD_ODD
;
8130 if (inst
.operands
[i
].isreg
)
8132 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8133 inst
.error
= BAD_EVEN
;
8134 else if (inst
.operands
[i
].reg
== REG_SP
)
8135 as_tsktsk (MVE_BAD_SP
);
8136 else if (inst
.operands
[i
].reg
== REG_PC
)
8137 inst
.error
= BAD_PC
;
8145 /* If we get here, this operand was successfully parsed. */
8146 inst
.operands
[i
].present
= 1;
8150 inst
.error
= BAD_ARGS
;
8155 /* The parse routine should already have set inst.error, but set a
8156 default here just in case. */
8158 inst
.error
= BAD_SYNTAX
;
8162 /* Do not backtrack over a trailing optional argument that
8163 absorbed some text. We will only fail again, with the
8164 'garbage following instruction' error message, which is
8165 probably less helpful than the current one. */
8166 if (backtrack_index
== i
&& backtrack_pos
!= str
8167 && upat
[i
+1] == OP_stop
)
8170 inst
.error
= BAD_SYNTAX
;
8174 /* Try again, skipping the optional argument at backtrack_pos. */
8175 str
= backtrack_pos
;
8176 inst
.error
= backtrack_error
;
8177 inst
.operands
[backtrack_index
].present
= 0;
8178 i
= backtrack_index
;
8182 /* Check that we have parsed all the arguments. */
8183 if (*str
!= '\0' && !inst
.error
)
8184 inst
.error
= _("garbage following instruction");
8186 return inst
.error
? FAIL
: SUCCESS
;
8189 #undef po_char_or_fail
8190 #undef po_reg_or_fail
8191 #undef po_reg_or_goto
8192 #undef po_imm_or_fail
8193 #undef po_scalar_or_fail
8194 #undef po_barrier_or_imm
8196 /* Shorthand macro for instruction encoding functions issuing errors. */
8197 #define constraint(expr, err) \
8208 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8209 instructions are unpredictable if these registers are used. This
8210 is the BadReg predicate in ARM's Thumb-2 documentation.
8212 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8213 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8214 #define reject_bad_reg(reg) \
8216 if (reg == REG_PC) \
8218 inst.error = BAD_PC; \
8221 else if (reg == REG_SP \
8222 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8224 inst.error = BAD_SP; \
8229 /* If REG is R13 (the stack pointer), warn that its use is
8231 #define warn_deprecated_sp(reg) \
8233 if (warn_on_deprecated && reg == REG_SP) \
8234 as_tsktsk (_("use of r13 is deprecated")); \
8237 /* Functions for operand encoding. ARM, then Thumb. */
8239 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8241 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8243 The only binary encoding difference is the Coprocessor number. Coprocessor
8244 9 is used for half-precision calculations or conversions. The format of the
8245 instruction is the same as the equivalent Coprocessor 10 instruction that
8246 exists for Single-Precision operation. */
8249 do_scalar_fp16_v82_encode (void)
8251 if (inst
.cond
< COND_ALWAYS
)
8252 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8253 " the behaviour is UNPREDICTABLE"));
8254 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8257 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8258 mark_feature_used (&arm_ext_fp16
);
8261 /* If VAL can be encoded in the immediate field of an ARM instruction,
8262 return the encoded form. Otherwise, return FAIL. */
8265 encode_arm_immediate (unsigned int val
)
8272 for (i
= 2; i
< 32; i
+= 2)
8273 if ((a
= rotate_left (val
, i
)) <= 0xff)
8274 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8279 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8280 return the encoded form. Otherwise, return FAIL. */
8282 encode_thumb32_immediate (unsigned int val
)
8289 for (i
= 1; i
<= 24; i
++)
8292 if ((val
& ~(0xff << i
)) == 0)
8293 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8297 if (val
== ((a
<< 16) | a
))
8299 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8303 if (val
== ((a
<< 16) | a
))
8304 return 0x200 | (a
>> 8);
8308 /* Encode a VFP SP or DP register number into inst.instruction. */
8311 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8313 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8316 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8319 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8322 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8327 first_error (_("D register out of range for selected VFP version"));
8335 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8339 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8343 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8347 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8351 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8355 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8363 /* Encode a <shift> in an ARM-format instruction. The immediate,
8364 if any, is handled by md_apply_fix. */
8366 encode_arm_shift (int i
)
8368 /* register-shifted register. */
8369 if (inst
.operands
[i
].immisreg
)
8372 for (op_index
= 0; op_index
<= i
; ++op_index
)
8374 /* Check the operand only when it's presented. In pre-UAL syntax,
8375 if the destination register is the same as the first operand, two
8376 register form of the instruction can be used. */
8377 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8378 && inst
.operands
[op_index
].reg
== REG_PC
)
8379 as_warn (UNPRED_REG ("r15"));
8382 if (inst
.operands
[i
].imm
== REG_PC
)
8383 as_warn (UNPRED_REG ("r15"));
8386 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8387 inst
.instruction
|= SHIFT_ROR
<< 5;
8390 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8391 if (inst
.operands
[i
].immisreg
)
8393 inst
.instruction
|= SHIFT_BY_REG
;
8394 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8397 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8402 encode_arm_shifter_operand (int i
)
8404 if (inst
.operands
[i
].isreg
)
8406 inst
.instruction
|= inst
.operands
[i
].reg
;
8407 encode_arm_shift (i
);
8411 inst
.instruction
|= INST_IMMEDIATE
;
8412 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8413 inst
.instruction
|= inst
.operands
[i
].imm
;
8417 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8419 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8422 Generate an error if the operand is not a register. */
8423 constraint (!inst
.operands
[i
].isreg
,
8424 _("Instruction does not support =N addresses"));
8426 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8428 if (inst
.operands
[i
].preind
)
8432 inst
.error
= _("instruction does not accept preindexed addressing");
8435 inst
.instruction
|= PRE_INDEX
;
8436 if (inst
.operands
[i
].writeback
)
8437 inst
.instruction
|= WRITE_BACK
;
8440 else if (inst
.operands
[i
].postind
)
8442 gas_assert (inst
.operands
[i
].writeback
);
8444 inst
.instruction
|= WRITE_BACK
;
8446 else /* unindexed - only for coprocessor */
8448 inst
.error
= _("instruction does not accept unindexed addressing");
8452 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8453 && (((inst
.instruction
& 0x000f0000) >> 16)
8454 == ((inst
.instruction
& 0x0000f000) >> 12)))
8455 as_warn ((inst
.instruction
& LOAD_BIT
)
8456 ? _("destination register same as write-back base")
8457 : _("source register same as write-back base"));
8460 /* inst.operands[i] was set up by parse_address. Encode it into an
8461 ARM-format mode 2 load or store instruction. If is_t is true,
8462 reject forms that cannot be used with a T instruction (i.e. not
8465 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8467 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8469 encode_arm_addr_mode_common (i
, is_t
);
8471 if (inst
.operands
[i
].immisreg
)
8473 constraint ((inst
.operands
[i
].imm
== REG_PC
8474 || (is_pc
&& inst
.operands
[i
].writeback
)),
8476 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8477 inst
.instruction
|= inst
.operands
[i
].imm
;
8478 if (!inst
.operands
[i
].negative
)
8479 inst
.instruction
|= INDEX_UP
;
8480 if (inst
.operands
[i
].shifted
)
8482 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8483 inst
.instruction
|= SHIFT_ROR
<< 5;
8486 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8487 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8491 else /* immediate offset in inst.relocs[0] */
8493 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8495 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8497 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8498 cannot use PC in addressing.
8499 PC cannot be used in writeback addressing, either. */
8500 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8503 /* Use of PC in str is deprecated for ARMv7. */
8504 if (warn_on_deprecated
8506 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8507 as_tsktsk (_("use of PC in this instruction is deprecated"));
8510 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8512 /* Prefer + for zero encoded value. */
8513 if (!inst
.operands
[i
].negative
)
8514 inst
.instruction
|= INDEX_UP
;
8515 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8520 /* inst.operands[i] was set up by parse_address. Encode it into an
8521 ARM-format mode 3 load or store instruction. Reject forms that
8522 cannot be used with such instructions. If is_t is true, reject
8523 forms that cannot be used with a T instruction (i.e. not
8526 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8528 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8530 inst
.error
= _("instruction does not accept scaled register index");
8534 encode_arm_addr_mode_common (i
, is_t
);
8536 if (inst
.operands
[i
].immisreg
)
8538 constraint ((inst
.operands
[i
].imm
== REG_PC
8539 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8541 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8543 inst
.instruction
|= inst
.operands
[i
].imm
;
8544 if (!inst
.operands
[i
].negative
)
8545 inst
.instruction
|= INDEX_UP
;
8547 else /* immediate offset in inst.relocs[0] */
8549 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8550 && inst
.operands
[i
].writeback
),
8552 inst
.instruction
|= HWOFFSET_IMM
;
8553 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8555 /* Prefer + for zero encoded value. */
8556 if (!inst
.operands
[i
].negative
)
8557 inst
.instruction
|= INDEX_UP
;
8559 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8564 /* Write immediate bits [7:0] to the following locations:
8566 |28/24|23 19|18 16|15 4|3 0|
8567 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8569 This function is used by VMOV/VMVN/VORR/VBIC. */
8572 neon_write_immbits (unsigned immbits
)
8574 inst
.instruction
|= immbits
& 0xf;
8575 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8576 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8579 /* Invert low-order SIZE bits of XHI:XLO. */
8582 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8584 unsigned immlo
= xlo
? *xlo
: 0;
8585 unsigned immhi
= xhi
? *xhi
: 0;
8590 immlo
= (~immlo
) & 0xff;
8594 immlo
= (~immlo
) & 0xffff;
8598 immhi
= (~immhi
) & 0xffffffff;
8602 immlo
= (~immlo
) & 0xffffffff;
8616 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8620 neon_bits_same_in_bytes (unsigned imm
)
8622 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8623 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8624 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8625 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8628 /* For immediate of above form, return 0bABCD. */
8631 neon_squash_bits (unsigned imm
)
8633 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8634 | ((imm
& 0x01000000) >> 21);
8637 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8640 neon_qfloat_bits (unsigned imm
)
8642 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8645 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8646 the instruction. *OP is passed as the initial value of the op field, and
8647 may be set to a different value depending on the constant (i.e.
8648 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8649 MVN). If the immediate looks like a repeated pattern then also
8650 try smaller element sizes. */
8653 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8654 unsigned *immbits
, int *op
, int size
,
8655 enum neon_el_type type
)
8657 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8659 if (type
== NT_float
&& !float_p
)
8662 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8664 if (size
!= 32 || *op
== 1)
8666 *immbits
= neon_qfloat_bits (immlo
);
8672 if (neon_bits_same_in_bytes (immhi
)
8673 && neon_bits_same_in_bytes (immlo
))
8677 *immbits
= (neon_squash_bits (immhi
) << 4)
8678 | neon_squash_bits (immlo
);
8689 if (immlo
== (immlo
& 0x000000ff))
8694 else if (immlo
== (immlo
& 0x0000ff00))
8696 *immbits
= immlo
>> 8;
8699 else if (immlo
== (immlo
& 0x00ff0000))
8701 *immbits
= immlo
>> 16;
8704 else if (immlo
== (immlo
& 0xff000000))
8706 *immbits
= immlo
>> 24;
8709 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8711 *immbits
= (immlo
>> 8) & 0xff;
8714 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8716 *immbits
= (immlo
>> 16) & 0xff;
8720 if ((immlo
& 0xffff) != (immlo
>> 16))
8727 if (immlo
== (immlo
& 0x000000ff))
8732 else if (immlo
== (immlo
& 0x0000ff00))
8734 *immbits
= immlo
>> 8;
8738 if ((immlo
& 0xff) != (immlo
>> 8))
8743 if (immlo
== (immlo
& 0x000000ff))
8745 /* Don't allow MVN with 8-bit immediate. */
8755 #if defined BFD_HOST_64_BIT
8756 /* Returns TRUE if double precision value V may be cast
8757 to single precision without loss of accuracy. */
8760 is_double_a_single (bfd_int64_t v
)
8762 int exp
= (int)((v
>> 52) & 0x7FF);
8763 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8765 return (exp
== 0 || exp
== 0x7FF
8766 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8767 && (mantissa
& 0x1FFFFFFFl
) == 0;
8770 /* Returns a double precision value casted to single precision
8771 (ignoring the least significant bits in exponent and mantissa). */
8774 double_to_single (bfd_int64_t v
)
8776 int sign
= (int) ((v
>> 63) & 1l);
8777 int exp
= (int) ((v
>> 52) & 0x7FF);
8778 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8784 exp
= exp
- 1023 + 127;
8793 /* No denormalized numbers. */
8799 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8801 #endif /* BFD_HOST_64_BIT */
8810 static void do_vfp_nsyn_opcode (const char *);
8812 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8813 Determine whether it can be performed with a move instruction; if
8814 it can, convert inst.instruction to that move instruction and
8815 return TRUE; if it can't, convert inst.instruction to a literal-pool
8816 load and return FALSE. If this is not a valid thing to do in the
8817 current context, set inst.error and return TRUE.
8819 inst.operands[i] describes the destination register. */
8822 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8825 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8826 bfd_boolean arm_p
= (t
== CONST_ARM
);
8829 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8833 if ((inst
.instruction
& tbit
) == 0)
8835 inst
.error
= _("invalid pseudo operation");
8839 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8840 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8841 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8843 inst
.error
= _("constant expression expected");
8847 if (inst
.relocs
[0].exp
.X_op
== O_constant
8848 || inst
.relocs
[0].exp
.X_op
== O_big
)
8850 #if defined BFD_HOST_64_BIT
8855 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8857 LITTLENUM_TYPE w
[X_PRECISION
];
8860 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8862 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8864 /* FIXME: Should we check words w[2..5] ? */
8869 #if defined BFD_HOST_64_BIT
8871 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8872 << LITTLENUM_NUMBER_OF_BITS
)
8873 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8874 << LITTLENUM_NUMBER_OF_BITS
)
8875 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8876 << LITTLENUM_NUMBER_OF_BITS
)
8877 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8879 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8880 | (l
[0] & LITTLENUM_MASK
);
8884 v
= inst
.relocs
[0].exp
.X_add_number
;
8886 if (!inst
.operands
[i
].issingle
)
8890 /* LDR should not use lead in a flag-setting instruction being
8891 chosen so we do not check whether movs can be used. */
8893 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8894 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8895 && inst
.operands
[i
].reg
!= 13
8896 && inst
.operands
[i
].reg
!= 15)
8898 /* Check if on thumb2 it can be done with a mov.w, mvn or
8899 movw instruction. */
8900 unsigned int newimm
;
8901 bfd_boolean isNegated
;
8903 newimm
= encode_thumb32_immediate (v
);
8904 if (newimm
!= (unsigned int) FAIL
)
8908 newimm
= encode_thumb32_immediate (~v
);
8909 if (newimm
!= (unsigned int) FAIL
)
8913 /* The number can be loaded with a mov.w or mvn
8915 if (newimm
!= (unsigned int) FAIL
8916 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8918 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8919 | (inst
.operands
[i
].reg
<< 8));
8920 /* Change to MOVN. */
8921 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8922 inst
.instruction
|= (newimm
& 0x800) << 15;
8923 inst
.instruction
|= (newimm
& 0x700) << 4;
8924 inst
.instruction
|= (newimm
& 0x0ff);
8927 /* The number can be loaded with a movw instruction. */
8928 else if ((v
& ~0xFFFF) == 0
8929 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8931 int imm
= v
& 0xFFFF;
8933 inst
.instruction
= 0xf2400000; /* MOVW. */
8934 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8935 inst
.instruction
|= (imm
& 0xf000) << 4;
8936 inst
.instruction
|= (imm
& 0x0800) << 15;
8937 inst
.instruction
|= (imm
& 0x0700) << 4;
8938 inst
.instruction
|= (imm
& 0x00ff);
8939 /* In case this replacement is being done on Armv8-M
8940 Baseline we need to make sure to disable the
8941 instruction size check, as otherwise GAS will reject
8942 the use of this T32 instruction. */
8950 int value
= encode_arm_immediate (v
);
8954 /* This can be done with a mov instruction. */
8955 inst
.instruction
&= LITERAL_MASK
;
8956 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8957 inst
.instruction
|= value
& 0xfff;
8961 value
= encode_arm_immediate (~ v
);
8964 /* This can be done with a mvn instruction. */
8965 inst
.instruction
&= LITERAL_MASK
;
8966 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8967 inst
.instruction
|= value
& 0xfff;
8971 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8974 unsigned immbits
= 0;
8975 unsigned immlo
= inst
.operands
[1].imm
;
8976 unsigned immhi
= inst
.operands
[1].regisimm
8977 ? inst
.operands
[1].reg
8978 : inst
.relocs
[0].exp
.X_unsigned
8980 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8981 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8982 &op
, 64, NT_invtype
);
8986 neon_invert_size (&immlo
, &immhi
, 64);
8988 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8989 &op
, 64, NT_invtype
);
8994 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
9000 /* Fill other bits in vmov encoding for both thumb and arm. */
9002 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
9004 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
9005 neon_write_immbits (immbits
);
9013 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
9014 if (inst
.operands
[i
].issingle
9015 && is_quarter_float (inst
.operands
[1].imm
)
9016 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
9018 inst
.operands
[1].imm
=
9019 neon_qfloat_bits (v
);
9020 do_vfp_nsyn_opcode ("fconsts");
9024 /* If our host does not support a 64-bit type then we cannot perform
9025 the following optimization. This mean that there will be a
9026 discrepancy between the output produced by an assembler built for
9027 a 32-bit-only host and the output produced from a 64-bit host, but
9028 this cannot be helped. */
9029 #if defined BFD_HOST_64_BIT
9030 else if (!inst
.operands
[1].issingle
9031 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
9033 if (is_double_a_single (v
)
9034 && is_quarter_float (double_to_single (v
)))
9036 inst
.operands
[1].imm
=
9037 neon_qfloat_bits (double_to_single (v
));
9038 do_vfp_nsyn_opcode ("fconstd");
9046 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
9047 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
9050 inst
.operands
[1].reg
= REG_PC
;
9051 inst
.operands
[1].isreg
= 1;
9052 inst
.operands
[1].preind
= 1;
9053 inst
.relocs
[0].pc_rel
= 1;
9054 inst
.relocs
[0].type
= (thumb_p
9055 ? BFD_RELOC_ARM_THUMB_OFFSET
9057 ? BFD_RELOC_ARM_HWLITERAL
9058 : BFD_RELOC_ARM_LITERAL
));
9062 /* inst.operands[i] was set up by parse_address. Encode it into an
9063 ARM-format instruction. Reject all forms which cannot be encoded
9064 into a coprocessor load/store instruction. If wb_ok is false,
9065 reject use of writeback; if unind_ok is false, reject use of
9066 unindexed addressing. If reloc_override is not 0, use it instead
9067 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
9068 (in which case it is preserved). */
9071 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
9073 if (!inst
.operands
[i
].isreg
)
9076 if (! inst
.operands
[0].isvec
)
9078 inst
.error
= _("invalid co-processor operand");
9081 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
9085 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9087 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
9089 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
9091 gas_assert (!inst
.operands
[i
].writeback
);
9094 inst
.error
= _("instruction does not support unindexed addressing");
9097 inst
.instruction
|= inst
.operands
[i
].imm
;
9098 inst
.instruction
|= INDEX_UP
;
9102 if (inst
.operands
[i
].preind
)
9103 inst
.instruction
|= PRE_INDEX
;
9105 if (inst
.operands
[i
].writeback
)
9107 if (inst
.operands
[i
].reg
== REG_PC
)
9109 inst
.error
= _("pc may not be used with write-back");
9114 inst
.error
= _("instruction does not support writeback");
9117 inst
.instruction
|= WRITE_BACK
;
9121 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
9122 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
9123 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
9124 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
9127 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
9129 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
9132 /* Prefer + for zero encoded value. */
9133 if (!inst
.operands
[i
].negative
)
9134 inst
.instruction
|= INDEX_UP
;
9139 /* Functions for instruction encoding, sorted by sub-architecture.
9140 First some generics; their names are taken from the conventional
9141 bit positions for register arguments in ARM format instructions. */
9151 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9157 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9163 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9164 inst
.instruction
|= inst
.operands
[1].reg
;
9170 inst
.instruction
|= inst
.operands
[0].reg
;
9171 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9177 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9178 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9184 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9185 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9191 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9192 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9196 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9198 if (ARM_CPU_IS_ANY (cpu_variant
))
9200 as_tsktsk ("%s", msg
);
9203 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9215 unsigned Rn
= inst
.operands
[2].reg
;
9216 /* Enforce restrictions on SWP instruction. */
9217 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9219 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9220 _("Rn must not overlap other operands"));
9222 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9224 if (!check_obsolete (&arm_ext_v8
,
9225 _("swp{b} use is obsoleted for ARMv8 and later"))
9226 && warn_on_deprecated
9227 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9228 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9232 inst
.instruction
|= inst
.operands
[1].reg
;
9233 inst
.instruction
|= Rn
<< 16;
9239 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9240 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9241 inst
.instruction
|= inst
.operands
[2].reg
;
9247 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9248 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9249 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9250 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9252 inst
.instruction
|= inst
.operands
[0].reg
;
9253 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9254 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9260 inst
.instruction
|= inst
.operands
[0].imm
;
9266 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9267 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9270 /* ARM instructions, in alphabetical order by function name (except
9271 that wrapper functions appear immediately after the function they
9274 /* This is a pseudo-op of the form "adr rd, label" to be converted
9275 into a relative address of the form "add rd, pc, #label-.-8". */
9280 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9282 /* Frag hacking will turn this into a sub instruction if the offset turns
9283 out to be negative. */
9284 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9285 inst
.relocs
[0].pc_rel
= 1;
9286 inst
.relocs
[0].exp
.X_add_number
-= 8;
9288 if (support_interwork
9289 && inst
.relocs
[0].exp
.X_op
== O_symbol
9290 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9291 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9292 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9293 inst
.relocs
[0].exp
.X_add_number
|= 1;
9296 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9297 into a relative address of the form:
9298 add rd, pc, #low(label-.-8)"
9299 add rd, rd, #high(label-.-8)" */
9304 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9306 /* Frag hacking will turn this into a sub instruction if the offset turns
9307 out to be negative. */
9308 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9309 inst
.relocs
[0].pc_rel
= 1;
9310 inst
.size
= INSN_SIZE
* 2;
9311 inst
.relocs
[0].exp
.X_add_number
-= 8;
9313 if (support_interwork
9314 && inst
.relocs
[0].exp
.X_op
== O_symbol
9315 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9316 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9317 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9318 inst
.relocs
[0].exp
.X_add_number
|= 1;
9324 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9325 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9327 if (!inst
.operands
[1].present
)
9328 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9329 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9330 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9331 encode_arm_shifter_operand (2);
9337 if (inst
.operands
[0].present
)
9338 inst
.instruction
|= inst
.operands
[0].imm
;
9340 inst
.instruction
|= 0xf;
9346 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9347 constraint (msb
> 32, _("bit-field extends past end of register"));
9348 /* The instruction encoding stores the LSB and MSB,
9349 not the LSB and width. */
9350 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9351 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9352 inst
.instruction
|= (msb
- 1) << 16;
9360 /* #0 in second position is alternative syntax for bfc, which is
9361 the same instruction but with REG_PC in the Rm field. */
9362 if (!inst
.operands
[1].isreg
)
9363 inst
.operands
[1].reg
= REG_PC
;
9365 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9366 constraint (msb
> 32, _("bit-field extends past end of register"));
9367 /* The instruction encoding stores the LSB and MSB,
9368 not the LSB and width. */
9369 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9370 inst
.instruction
|= inst
.operands
[1].reg
;
9371 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9372 inst
.instruction
|= (msb
- 1) << 16;
9378 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9379 _("bit-field extends past end of register"));
9380 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9381 inst
.instruction
|= inst
.operands
[1].reg
;
9382 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9383 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9386 /* ARM V5 breakpoint instruction (argument parse)
9387 BKPT <16 bit unsigned immediate>
9388 Instruction is not conditional.
9389 The bit pattern given in insns[] has the COND_ALWAYS condition,
9390 and it is an error if the caller tried to override that. */
9395 /* Top 12 of 16 bits to bits 19:8. */
9396 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9398 /* Bottom 4 of 16 bits to bits 3:0. */
9399 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9403 encode_branch (int default_reloc
)
9405 if (inst
.operands
[0].hasreloc
)
9407 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9408 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9409 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9410 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9411 ? BFD_RELOC_ARM_PLT32
9412 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9415 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9416 inst
.relocs
[0].pc_rel
= 1;
9423 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9424 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9427 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9434 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9436 if (inst
.cond
== COND_ALWAYS
)
9437 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9439 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9443 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9446 /* ARM V5 branch-link-exchange instruction (argument parse)
9447 BLX <target_addr> ie BLX(1)
9448 BLX{<condition>} <Rm> ie BLX(2)
9449 Unfortunately, there are two different opcodes for this mnemonic.
9450 So, the insns[].value is not used, and the code here zaps values
9451 into inst.instruction.
9452 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9457 if (inst
.operands
[0].isreg
)
9459 /* Arg is a register; the opcode provided by insns[] is correct.
9460 It is not illegal to do "blx pc", just useless. */
9461 if (inst
.operands
[0].reg
== REG_PC
)
9462 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9464 inst
.instruction
|= inst
.operands
[0].reg
;
9468 /* Arg is an address; this instruction cannot be executed
9469 conditionally, and the opcode must be adjusted.
9470 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9471 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9472 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9473 inst
.instruction
= 0xfa000000;
9474 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9481 bfd_boolean want_reloc
;
9483 if (inst
.operands
[0].reg
== REG_PC
)
9484 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9486 inst
.instruction
|= inst
.operands
[0].reg
;
9487 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9488 it is for ARMv4t or earlier. */
9489 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9490 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9491 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9495 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9500 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9504 /* ARM v5TEJ. Jump to Jazelle code. */
9509 if (inst
.operands
[0].reg
== REG_PC
)
9510 as_tsktsk (_("use of r15 in bxj is not really useful"));
9512 inst
.instruction
|= inst
.operands
[0].reg
;
9515 /* Co-processor data operation:
9516 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9517 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9521 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9522 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9523 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9524 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9525 inst
.instruction
|= inst
.operands
[4].reg
;
9526 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9532 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9533 encode_arm_shifter_operand (1);
9536 /* Transfer between coprocessor and ARM registers.
9537 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9542 No special properties. */
9544 struct deprecated_coproc_regs_s
9551 arm_feature_set deprecated
;
9552 arm_feature_set obsoleted
;
9553 const char *dep_msg
;
9554 const char *obs_msg
;
9557 #define DEPR_ACCESS_V8 \
9558 N_("This coprocessor register access is deprecated in ARMv8")
9560 /* Table of all deprecated coprocessor registers. */
9561 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9563 {15, 0, 7, 10, 5, /* CP15DMB. */
9564 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9565 DEPR_ACCESS_V8
, NULL
},
9566 {15, 0, 7, 10, 4, /* CP15DSB. */
9567 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9568 DEPR_ACCESS_V8
, NULL
},
9569 {15, 0, 7, 5, 4, /* CP15ISB. */
9570 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9571 DEPR_ACCESS_V8
, NULL
},
9572 {14, 6, 1, 0, 0, /* TEEHBR. */
9573 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9574 DEPR_ACCESS_V8
, NULL
},
9575 {14, 6, 0, 0, 0, /* TEECR. */
9576 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9577 DEPR_ACCESS_V8
, NULL
},
9580 #undef DEPR_ACCESS_V8
9582 static const size_t deprecated_coproc_reg_count
=
9583 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9591 Rd
= inst
.operands
[2].reg
;
9594 if (inst
.instruction
== 0xee000010
9595 || inst
.instruction
== 0xfe000010)
9597 reject_bad_reg (Rd
);
9598 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9600 constraint (Rd
== REG_SP
, BAD_SP
);
9605 if (inst
.instruction
== 0xe000010)
9606 constraint (Rd
== REG_PC
, BAD_PC
);
9609 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9611 const struct deprecated_coproc_regs_s
*r
=
9612 deprecated_coproc_regs
+ i
;
9614 if (inst
.operands
[0].reg
== r
->cp
9615 && inst
.operands
[1].imm
== r
->opc1
9616 && inst
.operands
[3].reg
== r
->crn
9617 && inst
.operands
[4].reg
== r
->crm
9618 && inst
.operands
[5].imm
== r
->opc2
)
9620 if (! ARM_CPU_IS_ANY (cpu_variant
)
9621 && warn_on_deprecated
9622 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9623 as_tsktsk ("%s", r
->dep_msg
);
9627 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9628 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9629 inst
.instruction
|= Rd
<< 12;
9630 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9631 inst
.instruction
|= inst
.operands
[4].reg
;
9632 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9635 /* Transfer between coprocessor register and pair of ARM registers.
9636 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9641 Two XScale instructions are special cases of these:
9643 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9644 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9646 Result unpredictable if Rd or Rn is R15. */
9653 Rd
= inst
.operands
[2].reg
;
9654 Rn
= inst
.operands
[3].reg
;
9658 reject_bad_reg (Rd
);
9659 reject_bad_reg (Rn
);
9663 constraint (Rd
== REG_PC
, BAD_PC
);
9664 constraint (Rn
== REG_PC
, BAD_PC
);
9667 /* Only check the MRRC{2} variants. */
9668 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9670 /* If Rd == Rn, error that the operation is
9671 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9672 constraint (Rd
== Rn
, BAD_OVERLAP
);
9675 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9676 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9677 inst
.instruction
|= Rd
<< 12;
9678 inst
.instruction
|= Rn
<< 16;
9679 inst
.instruction
|= inst
.operands
[4].reg
;
9685 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9686 if (inst
.operands
[1].present
)
9688 inst
.instruction
|= CPSI_MMOD
;
9689 inst
.instruction
|= inst
.operands
[1].imm
;
9696 inst
.instruction
|= inst
.operands
[0].imm
;
9702 unsigned Rd
, Rn
, Rm
;
9704 Rd
= inst
.operands
[0].reg
;
9705 Rn
= (inst
.operands
[1].present
9706 ? inst
.operands
[1].reg
: Rd
);
9707 Rm
= inst
.operands
[2].reg
;
9709 constraint ((Rd
== REG_PC
), BAD_PC
);
9710 constraint ((Rn
== REG_PC
), BAD_PC
);
9711 constraint ((Rm
== REG_PC
), BAD_PC
);
9713 inst
.instruction
|= Rd
<< 16;
9714 inst
.instruction
|= Rn
<< 0;
9715 inst
.instruction
|= Rm
<< 8;
9721 /* There is no IT instruction in ARM mode. We
9722 process it to do the validation as if in
9723 thumb mode, just in case the code gets
9724 assembled for thumb using the unified syntax. */
9729 set_pred_insn_type (IT_INSN
);
9730 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9731 now_pred
.cc
= inst
.operands
[0].imm
;
9735 /* If there is only one register in the register list,
9736 then return its register number. Otherwise return -1. */
9738 only_one_reg_in_list (int range
)
9740 int i
= ffs (range
) - 1;
9741 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9745 encode_ldmstm(int from_push_pop_mnem
)
9747 int base_reg
= inst
.operands
[0].reg
;
9748 int range
= inst
.operands
[1].imm
;
9751 inst
.instruction
|= base_reg
<< 16;
9752 inst
.instruction
|= range
;
9754 if (inst
.operands
[1].writeback
)
9755 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9757 if (inst
.operands
[0].writeback
)
9759 inst
.instruction
|= WRITE_BACK
;
9760 /* Check for unpredictable uses of writeback. */
9761 if (inst
.instruction
& LOAD_BIT
)
9763 /* Not allowed in LDM type 2. */
9764 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9765 && ((range
& (1 << REG_PC
)) == 0))
9766 as_warn (_("writeback of base register is UNPREDICTABLE"));
9767 /* Only allowed if base reg not in list for other types. */
9768 else if (range
& (1 << base_reg
))
9769 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9773 /* Not allowed for type 2. */
9774 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9775 as_warn (_("writeback of base register is UNPREDICTABLE"));
9776 /* Only allowed if base reg not in list, or first in list. */
9777 else if ((range
& (1 << base_reg
))
9778 && (range
& ((1 << base_reg
) - 1)))
9779 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9783 /* If PUSH/POP has only one register, then use the A2 encoding. */
9784 one_reg
= only_one_reg_in_list (range
);
9785 if (from_push_pop_mnem
&& one_reg
>= 0)
9787 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9789 if (is_push
&& one_reg
== 13 /* SP */)
9790 /* PR 22483: The A2 encoding cannot be used when
9791 pushing the stack pointer as this is UNPREDICTABLE. */
9794 inst
.instruction
&= A_COND_MASK
;
9795 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9796 inst
.instruction
|= one_reg
<< 12;
9803 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9806 /* ARMv5TE load-consecutive (argument parse)
9815 constraint (inst
.operands
[0].reg
% 2 != 0,
9816 _("first transfer register must be even"));
9817 constraint (inst
.operands
[1].present
9818 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9819 _("can only transfer two consecutive registers"));
9820 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9821 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9823 if (!inst
.operands
[1].present
)
9824 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9826 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9827 register and the first register written; we have to diagnose
9828 overlap between the base and the second register written here. */
9830 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9831 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9832 as_warn (_("base register written back, and overlaps "
9833 "second transfer register"));
9835 if (!(inst
.instruction
& V4_STR_BIT
))
9837 /* For an index-register load, the index register must not overlap the
9838 destination (even if not write-back). */
9839 if (inst
.operands
[2].immisreg
9840 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9841 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9842 as_warn (_("index register overlaps transfer register"));
9844 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9845 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9851 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9852 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9853 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9854 || inst
.operands
[1].negative
9855 /* This can arise if the programmer has written
9857 or if they have mistakenly used a register name as the last
9860 It is very difficult to distinguish between these two cases
9861 because "rX" might actually be a label. ie the register
9862 name has been occluded by a symbol of the same name. So we
9863 just generate a general 'bad addressing mode' type error
9864 message and leave it up to the programmer to discover the
9865 true cause and fix their mistake. */
9866 || (inst
.operands
[1].reg
== REG_PC
),
9869 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9870 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9871 _("offset must be zero in ARM encoding"));
9873 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9875 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9876 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9877 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9883 constraint (inst
.operands
[0].reg
% 2 != 0,
9884 _("even register required"));
9885 constraint (inst
.operands
[1].present
9886 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9887 _("can only load two consecutive registers"));
9888 /* If op 1 were present and equal to PC, this function wouldn't
9889 have been called in the first place. */
9890 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9892 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9893 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9896 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9897 which is not a multiple of four is UNPREDICTABLE. */
9899 check_ldr_r15_aligned (void)
9901 constraint (!(inst
.operands
[1].immisreg
)
9902 && (inst
.operands
[0].reg
== REG_PC
9903 && inst
.operands
[1].reg
== REG_PC
9904 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9905 _("ldr to register 15 must be 4-byte aligned"));
9911 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9912 if (!inst
.operands
[1].isreg
)
9913 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9915 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9916 check_ldr_r15_aligned ();
9922 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9924 if (inst
.operands
[1].preind
)
9926 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9927 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9928 _("this instruction requires a post-indexed address"));
9930 inst
.operands
[1].preind
= 0;
9931 inst
.operands
[1].postind
= 1;
9932 inst
.operands
[1].writeback
= 1;
9934 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9935 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9938 /* Halfword and signed-byte load/store operations. */
9943 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9944 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9945 if (!inst
.operands
[1].isreg
)
9946 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9948 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9954 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9956 if (inst
.operands
[1].preind
)
9958 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9959 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9960 _("this instruction requires a post-indexed address"));
9962 inst
.operands
[1].preind
= 0;
9963 inst
.operands
[1].postind
= 1;
9964 inst
.operands
[1].writeback
= 1;
9966 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9967 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9970 /* Co-processor register load/store.
9971 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9975 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9976 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9977 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9983 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9984 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9985 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9986 && !(inst
.instruction
& 0x00400000))
9987 as_tsktsk (_("Rd and Rm should be different in mla"));
9989 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9990 inst
.instruction
|= inst
.operands
[1].reg
;
9991 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9992 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9998 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9999 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10000 THUMB1_RELOC_ONLY
);
10001 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10002 encode_arm_shifter_operand (1);
10005 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
10012 top
= (inst
.instruction
& 0x00400000) != 0;
10013 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
10014 _(":lower16: not allowed in this instruction"));
10015 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
10016 _(":upper16: not allowed in this instruction"));
10017 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10018 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
10020 imm
= inst
.relocs
[0].exp
.X_add_number
;
10021 /* The value is in two pieces: 0:11, 16:19. */
10022 inst
.instruction
|= (imm
& 0x00000fff);
10023 inst
.instruction
|= (imm
& 0x0000f000) << 4;
10028 do_vfp_nsyn_mrs (void)
10030 if (inst
.operands
[0].isvec
)
10032 if (inst
.operands
[1].reg
!= 1)
10033 first_error (_("operand 1 must be FPSCR"));
10034 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
10035 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
10036 do_vfp_nsyn_opcode ("fmstat");
10038 else if (inst
.operands
[1].isvec
)
10039 do_vfp_nsyn_opcode ("fmrx");
10047 do_vfp_nsyn_msr (void)
10049 if (inst
.operands
[0].isvec
)
10050 do_vfp_nsyn_opcode ("fmxr");
10060 unsigned Rt
= inst
.operands
[0].reg
;
10062 if (thumb_mode
&& Rt
== REG_SP
)
10064 inst
.error
= BAD_SP
;
10068 switch (inst
.operands
[1].reg
)
10070 /* MVFR2 is only valid for Armv8-A. */
10072 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10076 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10077 case 1: /* fpscr. */
10078 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10079 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10083 case 14: /* fpcxt_ns. */
10084 case 15: /* fpcxt_s. */
10085 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10086 _("selected processor does not support instruction"));
10089 case 2: /* fpscr_nzcvqc. */
10090 case 12: /* vpr. */
10092 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10093 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10094 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10095 _("selected processor does not support instruction"));
10096 if (inst
.operands
[0].reg
!= 2
10097 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10098 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10105 /* APSR_ sets isvec. All other refs to PC are illegal. */
10106 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
10108 inst
.error
= BAD_PC
;
10112 /* If we get through parsing the register name, we just insert the number
10113 generated into the instruction without further validation. */
10114 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
10115 inst
.instruction
|= (Rt
<< 12);
10121 unsigned Rt
= inst
.operands
[1].reg
;
10124 reject_bad_reg (Rt
);
10125 else if (Rt
== REG_PC
)
10127 inst
.error
= BAD_PC
;
10131 switch (inst
.operands
[0].reg
)
10133 /* MVFR2 is only valid for Armv8-A. */
10135 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10139 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10140 case 1: /* fpcr. */
10141 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10142 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10146 case 14: /* fpcxt_ns. */
10147 case 15: /* fpcxt_s. */
10148 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10149 _("selected processor does not support instruction"));
10152 case 2: /* fpscr_nzcvqc. */
10153 case 12: /* vpr. */
10155 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10156 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10157 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10158 _("selected processor does not support instruction"));
10159 if (inst
.operands
[0].reg
!= 2
10160 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10161 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10168 /* If we get through parsing the register name, we just insert the number
10169 generated into the instruction without further validation. */
10170 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10171 inst
.instruction
|= (Rt
<< 12);
10179 if (do_vfp_nsyn_mrs () == SUCCESS
)
10182 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10183 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10185 if (inst
.operands
[1].isreg
)
10187 br
= inst
.operands
[1].reg
;
10188 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10189 as_bad (_("bad register for mrs"));
10193 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10194 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10196 _("'APSR', 'CPSR' or 'SPSR' expected"));
10197 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10200 inst
.instruction
|= br
;
10203 /* Two possible forms:
10204 "{C|S}PSR_<field>, Rm",
10205 "{C|S}PSR_f, #expression". */
10210 if (do_vfp_nsyn_msr () == SUCCESS
)
10213 inst
.instruction
|= inst
.operands
[0].imm
;
10214 if (inst
.operands
[1].isreg
)
10215 inst
.instruction
|= inst
.operands
[1].reg
;
10218 inst
.instruction
|= INST_IMMEDIATE
;
10219 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10220 inst
.relocs
[0].pc_rel
= 0;
10227 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10229 if (!inst
.operands
[2].present
)
10230 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10231 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10232 inst
.instruction
|= inst
.operands
[1].reg
;
10233 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10235 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10236 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10237 as_tsktsk (_("Rd and Rm should be different in mul"));
10240 /* Long Multiply Parser
10241 UMULL RdLo, RdHi, Rm, Rs
10242 SMULL RdLo, RdHi, Rm, Rs
10243 UMLAL RdLo, RdHi, Rm, Rs
10244 SMLAL RdLo, RdHi, Rm, Rs. */
10249 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10250 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10251 inst
.instruction
|= inst
.operands
[2].reg
;
10252 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10254 /* rdhi and rdlo must be different. */
10255 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10256 as_tsktsk (_("rdhi and rdlo must be different"));
10258 /* rdhi, rdlo and rm must all be different before armv6. */
10259 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10260 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10261 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10262 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10268 if (inst
.operands
[0].present
10269 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10271 /* Architectural NOP hints are CPSR sets with no bits selected. */
10272 inst
.instruction
&= 0xf0000000;
10273 inst
.instruction
|= 0x0320f000;
10274 if (inst
.operands
[0].present
)
10275 inst
.instruction
|= inst
.operands
[0].imm
;
10279 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10280 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10281 Condition defaults to COND_ALWAYS.
10282 Error if Rd, Rn or Rm are R15. */
10287 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10288 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10289 inst
.instruction
|= inst
.operands
[2].reg
;
10290 if (inst
.operands
[3].present
)
10291 encode_arm_shift (3);
10294 /* ARM V6 PKHTB (Argument Parse). */
10299 if (!inst
.operands
[3].present
)
10301 /* If the shift specifier is omitted, turn the instruction
10302 into pkhbt rd, rm, rn. */
10303 inst
.instruction
&= 0xfff00010;
10304 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10305 inst
.instruction
|= inst
.operands
[1].reg
;
10306 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10310 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10311 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10312 inst
.instruction
|= inst
.operands
[2].reg
;
10313 encode_arm_shift (3);
10317 /* ARMv5TE: Preload-Cache
10318 MP Extensions: Preload for write
10322 Syntactically, like LDR with B=1, W=0, L=1. */
10327 constraint (!inst
.operands
[0].isreg
,
10328 _("'[' expected after PLD mnemonic"));
10329 constraint (inst
.operands
[0].postind
,
10330 _("post-indexed expression used in preload instruction"));
10331 constraint (inst
.operands
[0].writeback
,
10332 _("writeback used in preload instruction"));
10333 constraint (!inst
.operands
[0].preind
,
10334 _("unindexed addressing used in preload instruction"));
10335 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10338 /* ARMv7: PLI <addr_mode> */
10342 constraint (!inst
.operands
[0].isreg
,
10343 _("'[' expected after PLI mnemonic"));
10344 constraint (inst
.operands
[0].postind
,
10345 _("post-indexed expression used in preload instruction"));
10346 constraint (inst
.operands
[0].writeback
,
10347 _("writeback used in preload instruction"));
10348 constraint (!inst
.operands
[0].preind
,
10349 _("unindexed addressing used in preload instruction"));
10350 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10351 inst
.instruction
&= ~PRE_INDEX
;
10357 constraint (inst
.operands
[0].writeback
,
10358 _("push/pop do not support {reglist}^"));
10359 inst
.operands
[1] = inst
.operands
[0];
10360 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10361 inst
.operands
[0].isreg
= 1;
10362 inst
.operands
[0].writeback
= 1;
10363 inst
.operands
[0].reg
= REG_SP
;
10364 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10367 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10368 word at the specified address and the following word
10370 Unconditionally executed.
10371 Error if Rn is R15. */
10376 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10377 if (inst
.operands
[0].writeback
)
10378 inst
.instruction
|= WRITE_BACK
;
10381 /* ARM V6 ssat (argument parse). */
10386 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10387 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10388 inst
.instruction
|= inst
.operands
[2].reg
;
10390 if (inst
.operands
[3].present
)
10391 encode_arm_shift (3);
10394 /* ARM V6 usat (argument parse). */
10399 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10400 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10401 inst
.instruction
|= inst
.operands
[2].reg
;
10403 if (inst
.operands
[3].present
)
10404 encode_arm_shift (3);
10407 /* ARM V6 ssat16 (argument parse). */
10412 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10413 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10414 inst
.instruction
|= inst
.operands
[2].reg
;
10420 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10421 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10422 inst
.instruction
|= inst
.operands
[2].reg
;
10425 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10426 preserving the other bits.
10428 setend <endian_specifier>, where <endian_specifier> is either
10434 if (warn_on_deprecated
10435 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10436 as_tsktsk (_("setend use is deprecated for ARMv8"));
10438 if (inst
.operands
[0].imm
)
10439 inst
.instruction
|= 0x200;
10445 unsigned int Rm
= (inst
.operands
[1].present
10446 ? inst
.operands
[1].reg
10447 : inst
.operands
[0].reg
);
10449 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10450 inst
.instruction
|= Rm
;
10451 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10453 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10454 inst
.instruction
|= SHIFT_BY_REG
;
10455 /* PR 12854: Error on extraneous shifts. */
10456 constraint (inst
.operands
[2].shifted
,
10457 _("extraneous shift as part of operand to shift insn"));
10460 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10466 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10467 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10469 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10470 inst
.relocs
[0].pc_rel
= 0;
10476 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10477 inst
.relocs
[0].pc_rel
= 0;
10483 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10484 inst
.relocs
[0].pc_rel
= 0;
10490 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10491 _("selected processor does not support SETPAN instruction"));
10493 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10499 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10500 _("selected processor does not support SETPAN instruction"));
10502 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10505 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10506 SMLAxy{cond} Rd,Rm,Rs,Rn
10507 SMLAWy{cond} Rd,Rm,Rs,Rn
10508 Error if any register is R15. */
10513 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10514 inst
.instruction
|= inst
.operands
[1].reg
;
10515 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10516 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10519 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10520 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10521 Error if any register is R15.
10522 Warning if Rdlo == Rdhi. */
10527 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10528 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10529 inst
.instruction
|= inst
.operands
[2].reg
;
10530 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10532 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10533 as_tsktsk (_("rdhi and rdlo must be different"));
10536 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10537 SMULxy{cond} Rd,Rm,Rs
10538 Error if any register is R15. */
10543 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10544 inst
.instruction
|= inst
.operands
[1].reg
;
10545 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10548 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10549 the same for both ARM and Thumb-2. */
10556 if (inst
.operands
[0].present
)
10558 reg
= inst
.operands
[0].reg
;
10559 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10564 inst
.instruction
|= reg
<< 16;
10565 inst
.instruction
|= inst
.operands
[1].imm
;
10566 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10567 inst
.instruction
|= WRITE_BACK
;
10570 /* ARM V6 strex (argument parse). */
10575 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10576 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10577 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10578 || inst
.operands
[2].negative
10579 /* See comment in do_ldrex(). */
10580 || (inst
.operands
[2].reg
== REG_PC
),
10583 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10584 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10586 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10587 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10588 _("offset must be zero in ARM encoding"));
10590 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10591 inst
.instruction
|= inst
.operands
[1].reg
;
10592 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10593 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10597 do_t_strexbh (void)
10599 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10600 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10601 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10602 || inst
.operands
[2].negative
,
10605 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10606 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10614 constraint (inst
.operands
[1].reg
% 2 != 0,
10615 _("even register required"));
10616 constraint (inst
.operands
[2].present
10617 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10618 _("can only store two consecutive registers"));
10619 /* If op 2 were present and equal to PC, this function wouldn't
10620 have been called in the first place. */
10621 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10623 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10624 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10625 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10628 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10629 inst
.instruction
|= inst
.operands
[1].reg
;
10630 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10637 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10638 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10646 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10647 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10652 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10653 extends it to 32-bits, and adds the result to a value in another
10654 register. You can specify a rotation by 0, 8, 16, or 24 bits
10655 before extracting the 16-bit value.
10656 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10657 Condition defaults to COND_ALWAYS.
10658 Error if any register uses R15. */
10663 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10664 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10665 inst
.instruction
|= inst
.operands
[2].reg
;
10666 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10671 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10672 Condition defaults to COND_ALWAYS.
10673 Error if any register uses R15. */
10678 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10679 inst
.instruction
|= inst
.operands
[1].reg
;
10680 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10683 /* VFP instructions. In a logical order: SP variant first, monad
10684 before dyad, arithmetic then move then load/store. */
10687 do_vfp_sp_monadic (void)
10689 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10690 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10693 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10694 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10698 do_vfp_sp_dyadic (void)
10700 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10701 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10702 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10706 do_vfp_sp_compare_z (void)
10708 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10712 do_vfp_dp_sp_cvt (void)
10714 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10715 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10719 do_vfp_sp_dp_cvt (void)
10721 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10722 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10726 do_vfp_reg_from_sp (void)
10728 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10729 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10732 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10733 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10737 do_vfp_reg2_from_sp2 (void)
10739 constraint (inst
.operands
[2].imm
!= 2,
10740 _("only two consecutive VFP SP registers allowed here"));
10741 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10742 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10743 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10747 do_vfp_sp_from_reg (void)
10749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10750 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10753 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10754 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10758 do_vfp_sp2_from_reg2 (void)
10760 constraint (inst
.operands
[0].imm
!= 2,
10761 _("only two consecutive VFP SP registers allowed here"));
10762 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10763 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10764 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10768 do_vfp_sp_ldst (void)
10770 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10771 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10775 do_vfp_dp_ldst (void)
10777 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10778 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10783 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10785 if (inst
.operands
[0].writeback
)
10786 inst
.instruction
|= WRITE_BACK
;
10788 constraint (ldstm_type
!= VFP_LDSTMIA
,
10789 _("this addressing mode requires base-register writeback"));
10790 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10791 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10792 inst
.instruction
|= inst
.operands
[1].imm
;
10796 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10800 if (inst
.operands
[0].writeback
)
10801 inst
.instruction
|= WRITE_BACK
;
10803 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10804 _("this addressing mode requires base-register writeback"));
10806 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10807 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10809 count
= inst
.operands
[1].imm
<< 1;
10810 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10813 inst
.instruction
|= count
;
10817 do_vfp_sp_ldstmia (void)
10819 vfp_sp_ldstm (VFP_LDSTMIA
);
10823 do_vfp_sp_ldstmdb (void)
10825 vfp_sp_ldstm (VFP_LDSTMDB
);
10829 do_vfp_dp_ldstmia (void)
10831 vfp_dp_ldstm (VFP_LDSTMIA
);
10835 do_vfp_dp_ldstmdb (void)
10837 vfp_dp_ldstm (VFP_LDSTMDB
);
10841 do_vfp_xp_ldstmia (void)
10843 vfp_dp_ldstm (VFP_LDSTMIAX
);
10847 do_vfp_xp_ldstmdb (void)
10849 vfp_dp_ldstm (VFP_LDSTMDBX
);
10853 do_vfp_dp_rd_rm (void)
10855 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10856 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10859 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10860 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10864 do_vfp_dp_rn_rd (void)
10866 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10867 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10871 do_vfp_dp_rd_rn (void)
10873 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10874 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10878 do_vfp_dp_rd_rn_rm (void)
10880 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10881 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10884 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10885 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10886 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10890 do_vfp_dp_rd (void)
10892 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10896 do_vfp_dp_rm_rd_rn (void)
10898 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10899 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10902 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10903 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10904 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10907 /* VFPv3 instructions. */
10909 do_vfp_sp_const (void)
10911 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10912 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10913 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10917 do_vfp_dp_const (void)
10919 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10920 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10921 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10925 vfp_conv (int srcsize
)
10927 int immbits
= srcsize
- inst
.operands
[1].imm
;
10929 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10931 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10932 i.e. immbits must be in range 0 - 16. */
10933 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10936 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10938 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10939 i.e. immbits must be in range 0 - 31. */
10940 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10944 inst
.instruction
|= (immbits
& 1) << 5;
10945 inst
.instruction
|= (immbits
>> 1);
10949 do_vfp_sp_conv_16 (void)
10951 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10956 do_vfp_dp_conv_16 (void)
10958 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10963 do_vfp_sp_conv_32 (void)
10965 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10970 do_vfp_dp_conv_32 (void)
10972 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10976 /* FPA instructions. Also in a logical order. */
10981 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10982 inst
.instruction
|= inst
.operands
[1].reg
;
10986 do_fpa_ldmstm (void)
10988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10989 switch (inst
.operands
[1].imm
)
10991 case 1: inst
.instruction
|= CP_T_X
; break;
10992 case 2: inst
.instruction
|= CP_T_Y
; break;
10993 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10998 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
11000 /* The instruction specified "ea" or "fd", so we can only accept
11001 [Rn]{!}. The instruction does not really support stacking or
11002 unstacking, so we have to emulate these by setting appropriate
11003 bits and offsets. */
11004 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
11005 || inst
.relocs
[0].exp
.X_add_number
!= 0,
11006 _("this instruction does not support indexing"));
11008 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
11009 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
11011 if (!(inst
.instruction
& INDEX_UP
))
11012 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
11014 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
11016 inst
.operands
[2].preind
= 0;
11017 inst
.operands
[2].postind
= 1;
11021 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
11024 /* iWMMXt instructions: strictly in alphabetical order. */
11027 do_iwmmxt_tandorc (void)
11029 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
11033 do_iwmmxt_textrc (void)
11035 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11036 inst
.instruction
|= inst
.operands
[1].imm
;
11040 do_iwmmxt_textrm (void)
11042 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11043 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11044 inst
.instruction
|= inst
.operands
[2].imm
;
11048 do_iwmmxt_tinsr (void)
11050 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11051 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11052 inst
.instruction
|= inst
.operands
[2].imm
;
11056 do_iwmmxt_tmia (void)
11058 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11059 inst
.instruction
|= inst
.operands
[1].reg
;
11060 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11064 do_iwmmxt_waligni (void)
11066 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11067 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11068 inst
.instruction
|= inst
.operands
[2].reg
;
11069 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
11073 do_iwmmxt_wmerge (void)
11075 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11076 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11077 inst
.instruction
|= inst
.operands
[2].reg
;
11078 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
11082 do_iwmmxt_wmov (void)
11084 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
11085 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11086 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11087 inst
.instruction
|= inst
.operands
[1].reg
;
11091 do_iwmmxt_wldstbh (void)
11094 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11096 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
11098 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
11099 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
11103 do_iwmmxt_wldstw (void)
11105 /* RIWR_RIWC clears .isreg for a control register. */
11106 if (!inst
.operands
[0].isreg
)
11108 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
11109 inst
.instruction
|= 0xf0000000;
11112 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11113 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
11117 do_iwmmxt_wldstd (void)
11119 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11120 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
11121 && inst
.operands
[1].immisreg
)
11123 inst
.instruction
&= ~0x1a000ff;
11124 inst
.instruction
|= (0xfU
<< 28);
11125 if (inst
.operands
[1].preind
)
11126 inst
.instruction
|= PRE_INDEX
;
11127 if (!inst
.operands
[1].negative
)
11128 inst
.instruction
|= INDEX_UP
;
11129 if (inst
.operands
[1].writeback
)
11130 inst
.instruction
|= WRITE_BACK
;
11131 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11132 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11133 inst
.instruction
|= inst
.operands
[1].imm
;
11136 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
11140 do_iwmmxt_wshufh (void)
11142 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11143 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11144 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11145 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11149 do_iwmmxt_wzero (void)
11151 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11152 inst
.instruction
|= inst
.operands
[0].reg
;
11153 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11154 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11158 do_iwmmxt_wrwrwr_or_imm5 (void)
11160 if (inst
.operands
[2].isreg
)
11163 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11164 _("immediate operand requires iWMMXt2"));
11166 if (inst
.operands
[2].imm
== 0)
11168 switch ((inst
.instruction
>> 20) & 0xf)
11174 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11175 inst
.operands
[2].imm
= 16;
11176 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11182 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11183 inst
.operands
[2].imm
= 32;
11184 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11191 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11193 wrn
= (inst
.instruction
>> 16) & 0xf;
11194 inst
.instruction
&= 0xff0fff0f;
11195 inst
.instruction
|= wrn
;
11196 /* Bail out here; the instruction is now assembled. */
11201 /* Map 32 -> 0, etc. */
11202 inst
.operands
[2].imm
&= 0x1f;
11203 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11207 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11208 operations first, then control, shift, and load/store. */
11210 /* Insns like "foo X,Y,Z". */
11213 do_mav_triple (void)
11215 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11216 inst
.instruction
|= inst
.operands
[1].reg
;
11217 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11220 /* Insns like "foo W,X,Y,Z".
11221 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11226 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11227 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11228 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11229 inst
.instruction
|= inst
.operands
[3].reg
;
11232 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11234 do_mav_dspsc (void)
11236 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11239 /* Maverick shift immediate instructions.
11240 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11241 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11244 do_mav_shift (void)
11246 int imm
= inst
.operands
[2].imm
;
11248 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11249 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11251 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11252 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11253 Bit 4 should be 0. */
11254 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11256 inst
.instruction
|= imm
;
11259 /* XScale instructions. Also sorted arithmetic before move. */
11261 /* Xscale multiply-accumulate (argument parse)
11264 MIAxycc acc0,Rm,Rs. */
11269 inst
.instruction
|= inst
.operands
[1].reg
;
11270 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11273 /* Xscale move-accumulator-register (argument parse)
11275 MARcc acc0,RdLo,RdHi. */
11280 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11281 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11284 /* Xscale move-register-accumulator (argument parse)
11286 MRAcc RdLo,RdHi,acc0. */
11291 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11292 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11293 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11296 /* Encoding functions relevant only to Thumb. */
11298 /* inst.operands[i] is a shifted-register operand; encode
11299 it into inst.instruction in the format used by Thumb32. */
11302 encode_thumb32_shifted_operand (int i
)
11304 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11305 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11307 constraint (inst
.operands
[i
].immisreg
,
11308 _("shift by register not allowed in thumb mode"));
11309 inst
.instruction
|= inst
.operands
[i
].reg
;
11310 if (shift
== SHIFT_RRX
)
11311 inst
.instruction
|= SHIFT_ROR
<< 4;
11314 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11315 _("expression too complex"));
11317 constraint (value
> 32
11318 || (value
== 32 && (shift
== SHIFT_LSL
11319 || shift
== SHIFT_ROR
)),
11320 _("shift expression is too large"));
11324 else if (value
== 32)
11327 inst
.instruction
|= shift
<< 4;
11328 inst
.instruction
|= (value
& 0x1c) << 10;
11329 inst
.instruction
|= (value
& 0x03) << 6;
11334 /* inst.operands[i] was set up by parse_address. Encode it into a
11335 Thumb32 format load or store instruction. Reject forms that cannot
11336 be used with such instructions. If is_t is true, reject forms that
11337 cannot be used with a T instruction; if is_d is true, reject forms
11338 that cannot be used with a D instruction. If it is a store insn,
11339 reject PC in Rn. */
11342 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11344 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11346 constraint (!inst
.operands
[i
].isreg
,
11347 _("Instruction does not support =N addresses"));
11349 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11350 if (inst
.operands
[i
].immisreg
)
11352 constraint (is_pc
, BAD_PC_ADDRESSING
);
11353 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11354 constraint (inst
.operands
[i
].negative
,
11355 _("Thumb does not support negative register indexing"));
11356 constraint (inst
.operands
[i
].postind
,
11357 _("Thumb does not support register post-indexing"));
11358 constraint (inst
.operands
[i
].writeback
,
11359 _("Thumb does not support register indexing with writeback"));
11360 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11361 _("Thumb supports only LSL in shifted register indexing"));
11363 inst
.instruction
|= inst
.operands
[i
].imm
;
11364 if (inst
.operands
[i
].shifted
)
11366 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11367 _("expression too complex"));
11368 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11369 || inst
.relocs
[0].exp
.X_add_number
> 3,
11370 _("shift out of range"));
11371 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11373 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11375 else if (inst
.operands
[i
].preind
)
11377 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11378 constraint (is_t
&& inst
.operands
[i
].writeback
,
11379 _("cannot use writeback with this instruction"));
11380 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11381 BAD_PC_ADDRESSING
);
11385 inst
.instruction
|= 0x01000000;
11386 if (inst
.operands
[i
].writeback
)
11387 inst
.instruction
|= 0x00200000;
11391 inst
.instruction
|= 0x00000c00;
11392 if (inst
.operands
[i
].writeback
)
11393 inst
.instruction
|= 0x00000100;
11395 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11397 else if (inst
.operands
[i
].postind
)
11399 gas_assert (inst
.operands
[i
].writeback
);
11400 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11401 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11404 inst
.instruction
|= 0x00200000;
11406 inst
.instruction
|= 0x00000900;
11407 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11409 else /* unindexed - only for coprocessor */
11410 inst
.error
= _("instruction does not accept unindexed addressing");
11413 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11414 encodings (the latter only in post-V6T2 cores). The index is the
11415 value used in the insns table below. When there is more than one
11416 possible 16-bit encoding for the instruction, this table always
11418 Also contains several pseudo-instructions used during relaxation. */
11419 #define T16_32_TAB \
11420 X(_adc, 4140, eb400000), \
11421 X(_adcs, 4140, eb500000), \
11422 X(_add, 1c00, eb000000), \
11423 X(_adds, 1c00, eb100000), \
11424 X(_addi, 0000, f1000000), \
11425 X(_addis, 0000, f1100000), \
11426 X(_add_pc,000f, f20f0000), \
11427 X(_add_sp,000d, f10d0000), \
11428 X(_adr, 000f, f20f0000), \
11429 X(_and, 4000, ea000000), \
11430 X(_ands, 4000, ea100000), \
11431 X(_asr, 1000, fa40f000), \
11432 X(_asrs, 1000, fa50f000), \
11433 X(_b, e000, f000b000), \
11434 X(_bcond, d000, f0008000), \
11435 X(_bf, 0000, f040e001), \
11436 X(_bfcsel,0000, f000e001), \
11437 X(_bfx, 0000, f060e001), \
11438 X(_bfl, 0000, f000c001), \
11439 X(_bflx, 0000, f070e001), \
11440 X(_bic, 4380, ea200000), \
11441 X(_bics, 4380, ea300000), \
11442 X(_cinc, 0000, ea509000), \
11443 X(_cinv, 0000, ea50a000), \
11444 X(_cmn, 42c0, eb100f00), \
11445 X(_cmp, 2800, ebb00f00), \
11446 X(_cneg, 0000, ea50b000), \
11447 X(_cpsie, b660, f3af8400), \
11448 X(_cpsid, b670, f3af8600), \
11449 X(_cpy, 4600, ea4f0000), \
11450 X(_csel, 0000, ea508000), \
11451 X(_cset, 0000, ea5f900f), \
11452 X(_csetm, 0000, ea5fa00f), \
11453 X(_csinc, 0000, ea509000), \
11454 X(_csinv, 0000, ea50a000), \
11455 X(_csneg, 0000, ea50b000), \
11456 X(_dec_sp,80dd, f1ad0d00), \
11457 X(_dls, 0000, f040e001), \
11458 X(_dlstp, 0000, f000e001), \
11459 X(_eor, 4040, ea800000), \
11460 X(_eors, 4040, ea900000), \
11461 X(_inc_sp,00dd, f10d0d00), \
11462 X(_lctp, 0000, f00fe001), \
11463 X(_ldmia, c800, e8900000), \
11464 X(_ldr, 6800, f8500000), \
11465 X(_ldrb, 7800, f8100000), \
11466 X(_ldrh, 8800, f8300000), \
11467 X(_ldrsb, 5600, f9100000), \
11468 X(_ldrsh, 5e00, f9300000), \
11469 X(_ldr_pc,4800, f85f0000), \
11470 X(_ldr_pc2,4800, f85f0000), \
11471 X(_ldr_sp,9800, f85d0000), \
11472 X(_le, 0000, f00fc001), \
11473 X(_letp, 0000, f01fc001), \
11474 X(_lsl, 0000, fa00f000), \
11475 X(_lsls, 0000, fa10f000), \
11476 X(_lsr, 0800, fa20f000), \
11477 X(_lsrs, 0800, fa30f000), \
11478 X(_mov, 2000, ea4f0000), \
11479 X(_movs, 2000, ea5f0000), \
11480 X(_mul, 4340, fb00f000), \
11481 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11482 X(_mvn, 43c0, ea6f0000), \
11483 X(_mvns, 43c0, ea7f0000), \
11484 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11485 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11486 X(_orr, 4300, ea400000), \
11487 X(_orrs, 4300, ea500000), \
11488 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11489 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11490 X(_rev, ba00, fa90f080), \
11491 X(_rev16, ba40, fa90f090), \
11492 X(_revsh, bac0, fa90f0b0), \
11493 X(_ror, 41c0, fa60f000), \
11494 X(_rors, 41c0, fa70f000), \
11495 X(_sbc, 4180, eb600000), \
11496 X(_sbcs, 4180, eb700000), \
11497 X(_stmia, c000, e8800000), \
11498 X(_str, 6000, f8400000), \
11499 X(_strb, 7000, f8000000), \
11500 X(_strh, 8000, f8200000), \
11501 X(_str_sp,9000, f84d0000), \
11502 X(_sub, 1e00, eba00000), \
11503 X(_subs, 1e00, ebb00000), \
11504 X(_subi, 8000, f1a00000), \
11505 X(_subis, 8000, f1b00000), \
11506 X(_sxtb, b240, fa4ff080), \
11507 X(_sxth, b200, fa0ff080), \
11508 X(_tst, 4200, ea100f00), \
11509 X(_uxtb, b2c0, fa5ff080), \
11510 X(_uxth, b280, fa1ff080), \
11511 X(_nop, bf00, f3af8000), \
11512 X(_yield, bf10, f3af8001), \
11513 X(_wfe, bf20, f3af8002), \
11514 X(_wfi, bf30, f3af8003), \
11515 X(_wls, 0000, f040c001), \
11516 X(_wlstp, 0000, f000c001), \
11517 X(_sev, bf40, f3af8004), \
11518 X(_sevl, bf50, f3af8005), \
11519 X(_udf, de00, f7f0a000)
11521 /* To catch errors in encoding functions, the codes are all offset by
11522 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11523 as 16-bit instructions. */
11524 #define X(a,b,c) T_MNEM##a
11525 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11528 #define X(a,b,c) 0x##b
11529 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11530 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11533 #define X(a,b,c) 0x##c
11534 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11535 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11536 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11540 /* Thumb instruction encoders, in alphabetical order. */
11542 /* ADDW or SUBW. */
11545 do_t_add_sub_w (void)
11549 Rd
= inst
.operands
[0].reg
;
11550 Rn
= inst
.operands
[1].reg
;
11552 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11553 is the SP-{plus,minus}-immediate form of the instruction. */
11555 constraint (Rd
== REG_PC
, BAD_PC
);
11557 reject_bad_reg (Rd
);
11559 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11560 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11563 /* Parse an add or subtract instruction. We get here with inst.instruction
11564 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11567 do_t_add_sub (void)
11571 Rd
= inst
.operands
[0].reg
;
11572 Rs
= (inst
.operands
[1].present
11573 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11574 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11577 set_pred_insn_type_last ();
11579 if (unified_syntax
)
11582 bfd_boolean narrow
;
11585 flags
= (inst
.instruction
== T_MNEM_adds
11586 || inst
.instruction
== T_MNEM_subs
);
11588 narrow
= !in_pred_block ();
11590 narrow
= in_pred_block ();
11591 if (!inst
.operands
[2].isreg
)
11595 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11596 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11598 add
= (inst
.instruction
== T_MNEM_add
11599 || inst
.instruction
== T_MNEM_adds
);
11601 if (inst
.size_req
!= 4)
11603 /* Attempt to use a narrow opcode, with relaxation if
11605 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11606 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11607 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11608 opcode
= T_MNEM_add_sp
;
11609 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11610 opcode
= T_MNEM_add_pc
;
11611 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11614 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11616 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11620 inst
.instruction
= THUMB_OP16(opcode
);
11621 inst
.instruction
|= (Rd
<< 4) | Rs
;
11622 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11623 || (inst
.relocs
[0].type
11624 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11626 if (inst
.size_req
== 2)
11627 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11629 inst
.relax
= opcode
;
11633 constraint (inst
.size_req
== 2, BAD_HIREG
);
11635 if (inst
.size_req
== 4
11636 || (inst
.size_req
!= 2 && !opcode
))
11638 constraint ((inst
.relocs
[0].type
11639 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11640 && (inst
.relocs
[0].type
11641 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11642 THUMB1_RELOC_ONLY
);
11645 constraint (add
, BAD_PC
);
11646 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11647 _("only SUBS PC, LR, #const allowed"));
11648 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11649 _("expression too complex"));
11650 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11651 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11652 _("immediate value out of range"));
11653 inst
.instruction
= T2_SUBS_PC_LR
11654 | inst
.relocs
[0].exp
.X_add_number
;
11655 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11658 else if (Rs
== REG_PC
)
11660 /* Always use addw/subw. */
11661 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11662 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11666 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11667 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11670 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11672 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11674 inst
.instruction
|= Rd
<< 8;
11675 inst
.instruction
|= Rs
<< 16;
11680 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11681 unsigned int shift
= inst
.operands
[2].shift_kind
;
11683 Rn
= inst
.operands
[2].reg
;
11684 /* See if we can do this with a 16-bit instruction. */
11685 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11687 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11692 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11693 || inst
.instruction
== T_MNEM_add
)
11695 : T_OPCODE_SUB_R3
);
11696 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11700 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11702 /* Thumb-1 cores (except v6-M) require at least one high
11703 register in a narrow non flag setting add. */
11704 if (Rd
> 7 || Rn
> 7
11705 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11706 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11713 inst
.instruction
= T_OPCODE_ADD_HI
;
11714 inst
.instruction
|= (Rd
& 8) << 4;
11715 inst
.instruction
|= (Rd
& 7);
11716 inst
.instruction
|= Rn
<< 3;
11722 constraint (Rd
== REG_PC
, BAD_PC
);
11723 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11724 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11725 constraint (Rs
== REG_PC
, BAD_PC
);
11726 reject_bad_reg (Rn
);
11728 /* If we get here, it can't be done in 16 bits. */
11729 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11730 _("shift must be constant"));
11731 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11732 inst
.instruction
|= Rd
<< 8;
11733 inst
.instruction
|= Rs
<< 16;
11734 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11735 _("shift value over 3 not allowed in thumb mode"));
11736 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11737 _("only LSL shift allowed in thumb mode"));
11738 encode_thumb32_shifted_operand (2);
11743 constraint (inst
.instruction
== T_MNEM_adds
11744 || inst
.instruction
== T_MNEM_subs
,
11747 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11749 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11750 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11753 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11754 ? 0x0000 : 0x8000);
11755 inst
.instruction
|= (Rd
<< 4) | Rs
;
11756 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11760 Rn
= inst
.operands
[2].reg
;
11761 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11763 /* We now have Rd, Rs, and Rn set to registers. */
11764 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11766 /* Can't do this for SUB. */
11767 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11768 inst
.instruction
= T_OPCODE_ADD_HI
;
11769 inst
.instruction
|= (Rd
& 8) << 4;
11770 inst
.instruction
|= (Rd
& 7);
11772 inst
.instruction
|= Rn
<< 3;
11774 inst
.instruction
|= Rs
<< 3;
11776 constraint (1, _("dest must overlap one source register"));
11780 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11781 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11782 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11792 Rd
= inst
.operands
[0].reg
;
11793 reject_bad_reg (Rd
);
11795 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11797 /* Defer to section relaxation. */
11798 inst
.relax
= inst
.instruction
;
11799 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11800 inst
.instruction
|= Rd
<< 4;
11802 else if (unified_syntax
&& inst
.size_req
!= 2)
11804 /* Generate a 32-bit opcode. */
11805 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11806 inst
.instruction
|= Rd
<< 8;
11807 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11808 inst
.relocs
[0].pc_rel
= 1;
11812 /* Generate a 16-bit opcode. */
11813 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11814 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11815 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11816 inst
.relocs
[0].pc_rel
= 1;
11817 inst
.instruction
|= Rd
<< 4;
11820 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11821 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11822 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11823 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11824 inst
.relocs
[0].exp
.X_add_number
+= 1;
11827 /* Arithmetic instructions for which there is just one 16-bit
11828 instruction encoding, and it allows only two low registers.
11829 For maximal compatibility with ARM syntax, we allow three register
11830 operands even when Thumb-32 instructions are not available, as long
11831 as the first two are identical. For instance, both "sbc r0,r1" and
11832 "sbc r0,r0,r1" are allowed. */
11838 Rd
= inst
.operands
[0].reg
;
11839 Rs
= (inst
.operands
[1].present
11840 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11841 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11842 Rn
= inst
.operands
[2].reg
;
11844 reject_bad_reg (Rd
);
11845 reject_bad_reg (Rs
);
11846 if (inst
.operands
[2].isreg
)
11847 reject_bad_reg (Rn
);
11849 if (unified_syntax
)
11851 if (!inst
.operands
[2].isreg
)
11853 /* For an immediate, we always generate a 32-bit opcode;
11854 section relaxation will shrink it later if possible. */
11855 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11856 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11857 inst
.instruction
|= Rd
<< 8;
11858 inst
.instruction
|= Rs
<< 16;
11859 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11863 bfd_boolean narrow
;
11865 /* See if we can do this with a 16-bit instruction. */
11866 if (THUMB_SETS_FLAGS (inst
.instruction
))
11867 narrow
= !in_pred_block ();
11869 narrow
= in_pred_block ();
11871 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11873 if (inst
.operands
[2].shifted
)
11875 if (inst
.size_req
== 4)
11881 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11882 inst
.instruction
|= Rd
;
11883 inst
.instruction
|= Rn
<< 3;
11887 /* If we get here, it can't be done in 16 bits. */
11888 constraint (inst
.operands
[2].shifted
11889 && inst
.operands
[2].immisreg
,
11890 _("shift must be constant"));
11891 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11892 inst
.instruction
|= Rd
<< 8;
11893 inst
.instruction
|= Rs
<< 16;
11894 encode_thumb32_shifted_operand (2);
11899 /* On its face this is a lie - the instruction does set the
11900 flags. However, the only supported mnemonic in this mode
11901 says it doesn't. */
11902 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11904 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11905 _("unshifted register required"));
11906 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11907 constraint (Rd
!= Rs
,
11908 _("dest and source1 must be the same register"));
11910 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11911 inst
.instruction
|= Rd
;
11912 inst
.instruction
|= Rn
<< 3;
11916 /* Similarly, but for instructions where the arithmetic operation is
11917 commutative, so we can allow either of them to be different from
11918 the destination operand in a 16-bit instruction. For instance, all
11919 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11926 Rd
= inst
.operands
[0].reg
;
11927 Rs
= (inst
.operands
[1].present
11928 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11929 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11930 Rn
= inst
.operands
[2].reg
;
11932 reject_bad_reg (Rd
);
11933 reject_bad_reg (Rs
);
11934 if (inst
.operands
[2].isreg
)
11935 reject_bad_reg (Rn
);
11937 if (unified_syntax
)
11939 if (!inst
.operands
[2].isreg
)
11941 /* For an immediate, we always generate a 32-bit opcode;
11942 section relaxation will shrink it later if possible. */
11943 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11944 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11945 inst
.instruction
|= Rd
<< 8;
11946 inst
.instruction
|= Rs
<< 16;
11947 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11951 bfd_boolean narrow
;
11953 /* See if we can do this with a 16-bit instruction. */
11954 if (THUMB_SETS_FLAGS (inst
.instruction
))
11955 narrow
= !in_pred_block ();
11957 narrow
= in_pred_block ();
11959 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11961 if (inst
.operands
[2].shifted
)
11963 if (inst
.size_req
== 4)
11970 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11971 inst
.instruction
|= Rd
;
11972 inst
.instruction
|= Rn
<< 3;
11977 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11978 inst
.instruction
|= Rd
;
11979 inst
.instruction
|= Rs
<< 3;
11984 /* If we get here, it can't be done in 16 bits. */
11985 constraint (inst
.operands
[2].shifted
11986 && inst
.operands
[2].immisreg
,
11987 _("shift must be constant"));
11988 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11989 inst
.instruction
|= Rd
<< 8;
11990 inst
.instruction
|= Rs
<< 16;
11991 encode_thumb32_shifted_operand (2);
11996 /* On its face this is a lie - the instruction does set the
11997 flags. However, the only supported mnemonic in this mode
11998 says it doesn't. */
11999 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12001 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
12002 _("unshifted register required"));
12003 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
12005 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12006 inst
.instruction
|= Rd
;
12009 inst
.instruction
|= Rn
<< 3;
12011 inst
.instruction
|= Rs
<< 3;
12013 constraint (1, _("dest must overlap one source register"));
12021 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
12022 constraint (msb
> 32, _("bit-field extends past end of register"));
12023 /* The instruction encoding stores the LSB and MSB,
12024 not the LSB and width. */
12025 Rd
= inst
.operands
[0].reg
;
12026 reject_bad_reg (Rd
);
12027 inst
.instruction
|= Rd
<< 8;
12028 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
12029 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
12030 inst
.instruction
|= msb
- 1;
12039 Rd
= inst
.operands
[0].reg
;
12040 reject_bad_reg (Rd
);
12042 /* #0 in second position is alternative syntax for bfc, which is
12043 the same instruction but with REG_PC in the Rm field. */
12044 if (!inst
.operands
[1].isreg
)
12048 Rn
= inst
.operands
[1].reg
;
12049 reject_bad_reg (Rn
);
12052 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
12053 constraint (msb
> 32, _("bit-field extends past end of register"));
12054 /* The instruction encoding stores the LSB and MSB,
12055 not the LSB and width. */
12056 inst
.instruction
|= Rd
<< 8;
12057 inst
.instruction
|= Rn
<< 16;
12058 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12059 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12060 inst
.instruction
|= msb
- 1;
12068 Rd
= inst
.operands
[0].reg
;
12069 Rn
= inst
.operands
[1].reg
;
12071 reject_bad_reg (Rd
);
12072 reject_bad_reg (Rn
);
12074 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
12075 _("bit-field extends past end of register"));
12076 inst
.instruction
|= Rd
<< 8;
12077 inst
.instruction
|= Rn
<< 16;
12078 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12079 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12080 inst
.instruction
|= inst
.operands
[3].imm
- 1;
12083 /* ARM V5 Thumb BLX (argument parse)
12084 BLX <target_addr> which is BLX(1)
12085 BLX <Rm> which is BLX(2)
12086 Unfortunately, there are two different opcodes for this mnemonic.
12087 So, the insns[].value is not used, and the code here zaps values
12088 into inst.instruction.
12090 ??? How to take advantage of the additional two bits of displacement
12091 available in Thumb32 mode? Need new relocation? */
12096 set_pred_insn_type_last ();
12098 if (inst
.operands
[0].isreg
)
12100 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
12101 /* We have a register, so this is BLX(2). */
12102 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12106 /* No register. This must be BLX(1). */
12107 inst
.instruction
= 0xf000e800;
12108 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
12117 bfd_reloc_code_real_type reloc
;
12120 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
12122 if (in_pred_block ())
12124 /* Conditional branches inside IT blocks are encoded as unconditional
12126 cond
= COND_ALWAYS
;
12131 if (cond
!= COND_ALWAYS
)
12132 opcode
= T_MNEM_bcond
;
12134 opcode
= inst
.instruction
;
12137 && (inst
.size_req
== 4
12138 || (inst
.size_req
!= 2
12139 && (inst
.operands
[0].hasreloc
12140 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12142 inst
.instruction
= THUMB_OP32(opcode
);
12143 if (cond
== COND_ALWAYS
)
12144 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12147 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12148 _("selected architecture does not support "
12149 "wide conditional branch instruction"));
12151 gas_assert (cond
!= 0xF);
12152 inst
.instruction
|= cond
<< 22;
12153 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12158 inst
.instruction
= THUMB_OP16(opcode
);
12159 if (cond
== COND_ALWAYS
)
12160 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12163 inst
.instruction
|= cond
<< 8;
12164 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12166 /* Allow section relaxation. */
12167 if (unified_syntax
&& inst
.size_req
!= 2)
12168 inst
.relax
= opcode
;
12170 inst
.relocs
[0].type
= reloc
;
12171 inst
.relocs
[0].pc_rel
= 1;
12174 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12175 between the two is the maximum immediate allowed - which is passed in
12178 do_t_bkpt_hlt1 (int range
)
12180 constraint (inst
.cond
!= COND_ALWAYS
,
12181 _("instruction is always unconditional"));
12182 if (inst
.operands
[0].present
)
12184 constraint (inst
.operands
[0].imm
> range
,
12185 _("immediate value out of range"));
12186 inst
.instruction
|= inst
.operands
[0].imm
;
12189 set_pred_insn_type (NEUTRAL_IT_INSN
);
12195 do_t_bkpt_hlt1 (63);
12201 do_t_bkpt_hlt1 (255);
12205 do_t_branch23 (void)
12207 set_pred_insn_type_last ();
12208 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12210 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12211 this file. We used to simply ignore the PLT reloc type here --
12212 the branch encoding is now needed to deal with TLSCALL relocs.
12213 So if we see a PLT reloc now, put it back to how it used to be to
12214 keep the preexisting behaviour. */
12215 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12216 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12218 #if defined(OBJ_COFF)
12219 /* If the destination of the branch is a defined symbol which does not have
12220 the THUMB_FUNC attribute, then we must be calling a function which has
12221 the (interfacearm) attribute. We look for the Thumb entry point to that
12222 function and change the branch to refer to that function instead. */
12223 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12224 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12225 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12226 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12227 inst
.relocs
[0].exp
.X_add_symbol
12228 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12235 set_pred_insn_type_last ();
12236 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12237 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12238 should cause the alignment to be checked once it is known. This is
12239 because BX PC only works if the instruction is word aligned. */
12247 set_pred_insn_type_last ();
12248 Rm
= inst
.operands
[0].reg
;
12249 reject_bad_reg (Rm
);
12250 inst
.instruction
|= Rm
<< 16;
12259 Rd
= inst
.operands
[0].reg
;
12260 Rm
= inst
.operands
[1].reg
;
12262 reject_bad_reg (Rd
);
12263 reject_bad_reg (Rm
);
12265 inst
.instruction
|= Rd
<< 8;
12266 inst
.instruction
|= Rm
<< 16;
12267 inst
.instruction
|= Rm
;
12270 /* For the Armv8.1-M conditional instructions. */
12274 unsigned Rd
, Rn
, Rm
;
12277 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12279 Rd
= inst
.operands
[0].reg
;
12280 switch (inst
.instruction
)
12286 Rn
= inst
.operands
[1].reg
;
12287 Rm
= inst
.operands
[2].reg
;
12288 cond
= inst
.operands
[3].imm
;
12289 constraint (Rn
== REG_SP
, BAD_SP
);
12290 constraint (Rm
== REG_SP
, BAD_SP
);
12296 Rn
= inst
.operands
[1].reg
;
12297 cond
= inst
.operands
[2].imm
;
12298 /* Invert the last bit to invert the cond. */
12299 cond
= TOGGLE_BIT (cond
, 0);
12300 constraint (Rn
== REG_SP
, BAD_SP
);
12306 cond
= inst
.operands
[1].imm
;
12307 /* Invert the last bit to invert the cond. */
12308 cond
= TOGGLE_BIT (cond
, 0);
12316 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12317 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12318 inst
.instruction
|= Rd
<< 8;
12319 inst
.instruction
|= Rn
<< 16;
12320 inst
.instruction
|= Rm
;
12321 inst
.instruction
|= cond
<< 4;
12327 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12333 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12334 inst
.instruction
|= inst
.operands
[0].imm
;
12340 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12342 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12343 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12345 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12346 inst
.instruction
= 0xf3af8000;
12347 inst
.instruction
|= imod
<< 9;
12348 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12349 if (inst
.operands
[1].present
)
12350 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12354 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12355 && (inst
.operands
[0].imm
& 4),
12356 _("selected processor does not support 'A' form "
12357 "of this instruction"));
12358 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12359 _("Thumb does not support the 2-argument "
12360 "form of this instruction"));
12361 inst
.instruction
|= inst
.operands
[0].imm
;
12365 /* THUMB CPY instruction (argument parse). */
12370 if (inst
.size_req
== 4)
12372 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12373 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12374 inst
.instruction
|= inst
.operands
[1].reg
;
12378 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12379 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12380 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12387 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12388 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12389 inst
.instruction
|= inst
.operands
[0].reg
;
12390 inst
.relocs
[0].pc_rel
= 1;
12391 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12397 inst
.instruction
|= inst
.operands
[0].imm
;
12403 unsigned Rd
, Rn
, Rm
;
12405 Rd
= inst
.operands
[0].reg
;
12406 Rn
= (inst
.operands
[1].present
12407 ? inst
.operands
[1].reg
: Rd
);
12408 Rm
= inst
.operands
[2].reg
;
12410 reject_bad_reg (Rd
);
12411 reject_bad_reg (Rn
);
12412 reject_bad_reg (Rm
);
12414 inst
.instruction
|= Rd
<< 8;
12415 inst
.instruction
|= Rn
<< 16;
12416 inst
.instruction
|= Rm
;
12422 if (unified_syntax
&& inst
.size_req
== 4)
12423 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12425 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12431 unsigned int cond
= inst
.operands
[0].imm
;
12433 set_pred_insn_type (IT_INSN
);
12434 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12435 now_pred
.cc
= cond
;
12436 now_pred
.warn_deprecated
= FALSE
;
12437 now_pred
.type
= SCALAR_PRED
;
12439 /* If the condition is a negative condition, invert the mask. */
12440 if ((cond
& 0x1) == 0x0)
12442 unsigned int mask
= inst
.instruction
& 0x000f;
12444 if ((mask
& 0x7) == 0)
12446 /* No conversion needed. */
12447 now_pred
.block_length
= 1;
12449 else if ((mask
& 0x3) == 0)
12452 now_pred
.block_length
= 2;
12454 else if ((mask
& 0x1) == 0)
12457 now_pred
.block_length
= 3;
12462 now_pred
.block_length
= 4;
12465 inst
.instruction
&= 0xfff0;
12466 inst
.instruction
|= mask
;
12469 inst
.instruction
|= cond
<< 4;
12472 /* Helper function used for both push/pop and ldm/stm. */
12474 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12475 bfd_boolean writeback
)
12477 bfd_boolean load
, store
;
12479 gas_assert (base
!= -1 || !do_io
);
12480 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12481 store
= do_io
&& !load
;
12483 if (mask
& (1 << 13))
12484 inst
.error
= _("SP not allowed in register list");
12486 if (do_io
&& (mask
& (1 << base
)) != 0
12488 inst
.error
= _("having the base register in the register list when "
12489 "using write back is UNPREDICTABLE");
12493 if (mask
& (1 << 15))
12495 if (mask
& (1 << 14))
12496 inst
.error
= _("LR and PC should not both be in register list");
12498 set_pred_insn_type_last ();
12503 if (mask
& (1 << 15))
12504 inst
.error
= _("PC not allowed in register list");
12507 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12509 /* Single register transfers implemented as str/ldr. */
12512 if (inst
.instruction
& (1 << 23))
12513 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12515 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12519 if (inst
.instruction
& (1 << 23))
12520 inst
.instruction
= 0x00800000; /* ia -> [base] */
12522 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12525 inst
.instruction
|= 0xf8400000;
12527 inst
.instruction
|= 0x00100000;
12529 mask
= ffs (mask
) - 1;
12532 else if (writeback
)
12533 inst
.instruction
|= WRITE_BACK
;
12535 inst
.instruction
|= mask
;
12537 inst
.instruction
|= base
<< 16;
12543 /* This really doesn't seem worth it. */
12544 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12545 _("expression too complex"));
12546 constraint (inst
.operands
[1].writeback
,
12547 _("Thumb load/store multiple does not support {reglist}^"));
12549 if (unified_syntax
)
12551 bfd_boolean narrow
;
12555 /* See if we can use a 16-bit instruction. */
12556 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12557 && inst
.size_req
!= 4
12558 && !(inst
.operands
[1].imm
& ~0xff))
12560 mask
= 1 << inst
.operands
[0].reg
;
12562 if (inst
.operands
[0].reg
<= 7)
12564 if (inst
.instruction
== T_MNEM_stmia
12565 ? inst
.operands
[0].writeback
12566 : (inst
.operands
[0].writeback
12567 == !(inst
.operands
[1].imm
& mask
)))
12569 if (inst
.instruction
== T_MNEM_stmia
12570 && (inst
.operands
[1].imm
& mask
)
12571 && (inst
.operands
[1].imm
& (mask
- 1)))
12572 as_warn (_("value stored for r%d is UNKNOWN"),
12573 inst
.operands
[0].reg
);
12575 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12576 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12577 inst
.instruction
|= inst
.operands
[1].imm
;
12580 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12582 /* This means 1 register in reg list one of 3 situations:
12583 1. Instruction is stmia, but without writeback.
12584 2. lmdia without writeback, but with Rn not in
12586 3. ldmia with writeback, but with Rn in reglist.
12587 Case 3 is UNPREDICTABLE behaviour, so we handle
12588 case 1 and 2 which can be converted into a 16-bit
12589 str or ldr. The SP cases are handled below. */
12590 unsigned long opcode
;
12591 /* First, record an error for Case 3. */
12592 if (inst
.operands
[1].imm
& mask
12593 && inst
.operands
[0].writeback
)
12595 _("having the base register in the register list when "
12596 "using write back is UNPREDICTABLE");
12598 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12600 inst
.instruction
= THUMB_OP16 (opcode
);
12601 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12602 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12606 else if (inst
.operands
[0] .reg
== REG_SP
)
12608 if (inst
.operands
[0].writeback
)
12611 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12612 ? T_MNEM_push
: T_MNEM_pop
);
12613 inst
.instruction
|= inst
.operands
[1].imm
;
12616 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12619 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12620 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12621 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12629 if (inst
.instruction
< 0xffff)
12630 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12632 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12633 inst
.operands
[1].imm
,
12634 inst
.operands
[0].writeback
);
12639 constraint (inst
.operands
[0].reg
> 7
12640 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12641 constraint (inst
.instruction
!= T_MNEM_ldmia
12642 && inst
.instruction
!= T_MNEM_stmia
,
12643 _("Thumb-2 instruction only valid in unified syntax"));
12644 if (inst
.instruction
== T_MNEM_stmia
)
12646 if (!inst
.operands
[0].writeback
)
12647 as_warn (_("this instruction will write back the base register"));
12648 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12649 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12650 as_warn (_("value stored for r%d is UNKNOWN"),
12651 inst
.operands
[0].reg
);
12655 if (!inst
.operands
[0].writeback
12656 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12657 as_warn (_("this instruction will write back the base register"));
12658 else if (inst
.operands
[0].writeback
12659 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12660 as_warn (_("this instruction will not write back the base register"));
12663 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12664 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12665 inst
.instruction
|= inst
.operands
[1].imm
;
12672 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12673 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12674 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12675 || inst
.operands
[1].negative
,
12678 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12680 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12681 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12682 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12688 if (!inst
.operands
[1].present
)
12690 constraint (inst
.operands
[0].reg
== REG_LR
,
12691 _("r14 not allowed as first register "
12692 "when second register is omitted"));
12693 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12695 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12698 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12699 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12700 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12706 unsigned long opcode
;
12709 if (inst
.operands
[0].isreg
12710 && !inst
.operands
[0].preind
12711 && inst
.operands
[0].reg
== REG_PC
)
12712 set_pred_insn_type_last ();
12714 opcode
= inst
.instruction
;
12715 if (unified_syntax
)
12717 if (!inst
.operands
[1].isreg
)
12719 if (opcode
<= 0xffff)
12720 inst
.instruction
= THUMB_OP32 (opcode
);
12721 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12724 if (inst
.operands
[1].isreg
12725 && !inst
.operands
[1].writeback
12726 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12727 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12728 && opcode
<= 0xffff
12729 && inst
.size_req
!= 4)
12731 /* Insn may have a 16-bit form. */
12732 Rn
= inst
.operands
[1].reg
;
12733 if (inst
.operands
[1].immisreg
)
12735 inst
.instruction
= THUMB_OP16 (opcode
);
12737 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12739 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12740 reject_bad_reg (inst
.operands
[1].imm
);
12742 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12743 && opcode
!= T_MNEM_ldrsb
)
12744 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12745 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12752 if (inst
.relocs
[0].pc_rel
)
12753 opcode
= T_MNEM_ldr_pc2
;
12755 opcode
= T_MNEM_ldr_pc
;
12759 if (opcode
== T_MNEM_ldr
)
12760 opcode
= T_MNEM_ldr_sp
;
12762 opcode
= T_MNEM_str_sp
;
12764 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12768 inst
.instruction
= inst
.operands
[0].reg
;
12769 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12771 inst
.instruction
|= THUMB_OP16 (opcode
);
12772 if (inst
.size_req
== 2)
12773 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12775 inst
.relax
= opcode
;
12779 /* Definitely a 32-bit variant. */
12781 /* Warning for Erratum 752419. */
12782 if (opcode
== T_MNEM_ldr
12783 && inst
.operands
[0].reg
== REG_SP
12784 && inst
.operands
[1].writeback
== 1
12785 && !inst
.operands
[1].immisreg
)
12787 if (no_cpu_selected ()
12788 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12789 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12790 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12791 as_warn (_("This instruction may be unpredictable "
12792 "if executed on M-profile cores "
12793 "with interrupts enabled."));
12796 /* Do some validations regarding addressing modes. */
12797 if (inst
.operands
[1].immisreg
)
12798 reject_bad_reg (inst
.operands
[1].imm
);
12800 constraint (inst
.operands
[1].writeback
== 1
12801 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12804 inst
.instruction
= THUMB_OP32 (opcode
);
12805 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12806 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12807 check_ldr_r15_aligned ();
12811 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12813 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12815 /* Only [Rn,Rm] is acceptable. */
12816 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12817 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12818 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12819 || inst
.operands
[1].negative
,
12820 _("Thumb does not support this addressing mode"));
12821 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12825 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12826 if (!inst
.operands
[1].isreg
)
12827 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12830 constraint (!inst
.operands
[1].preind
12831 || inst
.operands
[1].shifted
12832 || inst
.operands
[1].writeback
,
12833 _("Thumb does not support this addressing mode"));
12834 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12836 constraint (inst
.instruction
& 0x0600,
12837 _("byte or halfword not valid for base register"));
12838 constraint (inst
.operands
[1].reg
== REG_PC
12839 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12840 _("r15 based store not allowed"));
12841 constraint (inst
.operands
[1].immisreg
,
12842 _("invalid base register for register offset"));
12844 if (inst
.operands
[1].reg
== REG_PC
)
12845 inst
.instruction
= T_OPCODE_LDR_PC
;
12846 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12847 inst
.instruction
= T_OPCODE_LDR_SP
;
12849 inst
.instruction
= T_OPCODE_STR_SP
;
12851 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12852 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12856 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12857 if (!inst
.operands
[1].immisreg
)
12859 /* Immediate offset. */
12860 inst
.instruction
|= inst
.operands
[0].reg
;
12861 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12862 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12866 /* Register offset. */
12867 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12868 constraint (inst
.operands
[1].negative
,
12869 _("Thumb does not support this addressing mode"));
12872 switch (inst
.instruction
)
12874 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12875 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12876 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12877 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12878 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12879 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12880 case 0x5600 /* ldrsb */:
12881 case 0x5e00 /* ldrsh */: break;
12885 inst
.instruction
|= inst
.operands
[0].reg
;
12886 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12887 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12893 if (!inst
.operands
[1].present
)
12895 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12896 constraint (inst
.operands
[0].reg
== REG_LR
,
12897 _("r14 not allowed here"));
12898 constraint (inst
.operands
[0].reg
== REG_R12
,
12899 _("r12 not allowed here"));
12902 if (inst
.operands
[2].writeback
12903 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12904 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12905 as_warn (_("base register written back, and overlaps "
12906 "one of transfer registers"));
12908 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12909 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12910 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12916 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12917 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12923 unsigned Rd
, Rn
, Rm
, Ra
;
12925 Rd
= inst
.operands
[0].reg
;
12926 Rn
= inst
.operands
[1].reg
;
12927 Rm
= inst
.operands
[2].reg
;
12928 Ra
= inst
.operands
[3].reg
;
12930 reject_bad_reg (Rd
);
12931 reject_bad_reg (Rn
);
12932 reject_bad_reg (Rm
);
12933 reject_bad_reg (Ra
);
12935 inst
.instruction
|= Rd
<< 8;
12936 inst
.instruction
|= Rn
<< 16;
12937 inst
.instruction
|= Rm
;
12938 inst
.instruction
|= Ra
<< 12;
12944 unsigned RdLo
, RdHi
, Rn
, Rm
;
12946 RdLo
= inst
.operands
[0].reg
;
12947 RdHi
= inst
.operands
[1].reg
;
12948 Rn
= inst
.operands
[2].reg
;
12949 Rm
= inst
.operands
[3].reg
;
12951 reject_bad_reg (RdLo
);
12952 reject_bad_reg (RdHi
);
12953 reject_bad_reg (Rn
);
12954 reject_bad_reg (Rm
);
12956 inst
.instruction
|= RdLo
<< 12;
12957 inst
.instruction
|= RdHi
<< 8;
12958 inst
.instruction
|= Rn
<< 16;
12959 inst
.instruction
|= Rm
;
12963 do_t_mov_cmp (void)
12967 Rn
= inst
.operands
[0].reg
;
12968 Rm
= inst
.operands
[1].reg
;
12971 set_pred_insn_type_last ();
12973 if (unified_syntax
)
12975 int r0off
= (inst
.instruction
== T_MNEM_mov
12976 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12977 unsigned long opcode
;
12978 bfd_boolean narrow
;
12979 bfd_boolean low_regs
;
12981 low_regs
= (Rn
<= 7 && Rm
<= 7);
12982 opcode
= inst
.instruction
;
12983 if (in_pred_block ())
12984 narrow
= opcode
!= T_MNEM_movs
;
12986 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12987 if (inst
.size_req
== 4
12988 || inst
.operands
[1].shifted
)
12991 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12992 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12993 && !inst
.operands
[1].shifted
12997 inst
.instruction
= T2_SUBS_PC_LR
;
13001 if (opcode
== T_MNEM_cmp
)
13003 constraint (Rn
== REG_PC
, BAD_PC
);
13006 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
13008 warn_deprecated_sp (Rm
);
13009 /* R15 was documented as a valid choice for Rm in ARMv6,
13010 but as UNPREDICTABLE in ARMv7. ARM's proprietary
13011 tools reject R15, so we do too. */
13012 constraint (Rm
== REG_PC
, BAD_PC
);
13015 reject_bad_reg (Rm
);
13017 else if (opcode
== T_MNEM_mov
13018 || opcode
== T_MNEM_movs
)
13020 if (inst
.operands
[1].isreg
)
13022 if (opcode
== T_MNEM_movs
)
13024 reject_bad_reg (Rn
);
13025 reject_bad_reg (Rm
);
13029 /* This is mov.n. */
13030 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
13031 && (Rm
== REG_SP
|| Rm
== REG_PC
))
13033 as_tsktsk (_("Use of r%u as a source register is "
13034 "deprecated when r%u is the destination "
13035 "register."), Rm
, Rn
);
13040 /* This is mov.w. */
13041 constraint (Rn
== REG_PC
, BAD_PC
);
13042 constraint (Rm
== REG_PC
, BAD_PC
);
13043 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13044 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
13048 reject_bad_reg (Rn
);
13051 if (!inst
.operands
[1].isreg
)
13053 /* Immediate operand. */
13054 if (!in_pred_block () && opcode
== T_MNEM_mov
)
13056 if (low_regs
&& narrow
)
13058 inst
.instruction
= THUMB_OP16 (opcode
);
13059 inst
.instruction
|= Rn
<< 8;
13060 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
13061 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
13063 if (inst
.size_req
== 2)
13064 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13066 inst
.relax
= opcode
;
13071 constraint ((inst
.relocs
[0].type
13072 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
13073 && (inst
.relocs
[0].type
13074 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
13075 THUMB1_RELOC_ONLY
);
13077 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13078 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13079 inst
.instruction
|= Rn
<< r0off
;
13080 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13083 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
13084 && (inst
.instruction
== T_MNEM_mov
13085 || inst
.instruction
== T_MNEM_movs
))
13087 /* Register shifts are encoded as separate shift instructions. */
13088 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
13090 if (in_pred_block ())
13095 if (inst
.size_req
== 4)
13098 if (!low_regs
|| inst
.operands
[1].imm
> 7)
13104 switch (inst
.operands
[1].shift_kind
)
13107 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
13110 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
13113 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
13116 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
13122 inst
.instruction
= opcode
;
13125 inst
.instruction
|= Rn
;
13126 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
13131 inst
.instruction
|= CONDS_BIT
;
13133 inst
.instruction
|= Rn
<< 8;
13134 inst
.instruction
|= Rm
<< 16;
13135 inst
.instruction
|= inst
.operands
[1].imm
;
13140 /* Some mov with immediate shift have narrow variants.
13141 Register shifts are handled above. */
13142 if (low_regs
&& inst
.operands
[1].shifted
13143 && (inst
.instruction
== T_MNEM_mov
13144 || inst
.instruction
== T_MNEM_movs
))
13146 if (in_pred_block ())
13147 narrow
= (inst
.instruction
== T_MNEM_mov
);
13149 narrow
= (inst
.instruction
== T_MNEM_movs
);
13154 switch (inst
.operands
[1].shift_kind
)
13156 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13157 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13158 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13159 default: narrow
= FALSE
; break;
13165 inst
.instruction
|= Rn
;
13166 inst
.instruction
|= Rm
<< 3;
13167 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13171 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13172 inst
.instruction
|= Rn
<< r0off
;
13173 encode_thumb32_shifted_operand (1);
13177 switch (inst
.instruction
)
13180 /* In v4t or v5t a move of two lowregs produces unpredictable
13181 results. Don't allow this. */
13184 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13185 "MOV Rd, Rs with two low registers is not "
13186 "permitted on this architecture");
13187 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13191 inst
.instruction
= T_OPCODE_MOV_HR
;
13192 inst
.instruction
|= (Rn
& 0x8) << 4;
13193 inst
.instruction
|= (Rn
& 0x7);
13194 inst
.instruction
|= Rm
<< 3;
13198 /* We know we have low registers at this point.
13199 Generate LSLS Rd, Rs, #0. */
13200 inst
.instruction
= T_OPCODE_LSL_I
;
13201 inst
.instruction
|= Rn
;
13202 inst
.instruction
|= Rm
<< 3;
13208 inst
.instruction
= T_OPCODE_CMP_LR
;
13209 inst
.instruction
|= Rn
;
13210 inst
.instruction
|= Rm
<< 3;
13214 inst
.instruction
= T_OPCODE_CMP_HR
;
13215 inst
.instruction
|= (Rn
& 0x8) << 4;
13216 inst
.instruction
|= (Rn
& 0x7);
13217 inst
.instruction
|= Rm
<< 3;
13224 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13226 /* PR 10443: Do not silently ignore shifted operands. */
13227 constraint (inst
.operands
[1].shifted
,
13228 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13230 if (inst
.operands
[1].isreg
)
13232 if (Rn
< 8 && Rm
< 8)
13234 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13235 since a MOV instruction produces unpredictable results. */
13236 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13237 inst
.instruction
= T_OPCODE_ADD_I3
;
13239 inst
.instruction
= T_OPCODE_CMP_LR
;
13241 inst
.instruction
|= Rn
;
13242 inst
.instruction
|= Rm
<< 3;
13246 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13247 inst
.instruction
= T_OPCODE_MOV_HR
;
13249 inst
.instruction
= T_OPCODE_CMP_HR
;
13255 constraint (Rn
> 7,
13256 _("only lo regs allowed with immediate"));
13257 inst
.instruction
|= Rn
<< 8;
13258 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13269 top
= (inst
.instruction
& 0x00800000) != 0;
13270 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13272 constraint (top
, _(":lower16: not allowed in this instruction"));
13273 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13275 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13277 constraint (!top
, _(":upper16: not allowed in this instruction"));
13278 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13281 Rd
= inst
.operands
[0].reg
;
13282 reject_bad_reg (Rd
);
13284 inst
.instruction
|= Rd
<< 8;
13285 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13287 imm
= inst
.relocs
[0].exp
.X_add_number
;
13288 inst
.instruction
|= (imm
& 0xf000) << 4;
13289 inst
.instruction
|= (imm
& 0x0800) << 15;
13290 inst
.instruction
|= (imm
& 0x0700) << 4;
13291 inst
.instruction
|= (imm
& 0x00ff);
13296 do_t_mvn_tst (void)
13300 Rn
= inst
.operands
[0].reg
;
13301 Rm
= inst
.operands
[1].reg
;
13303 if (inst
.instruction
== T_MNEM_cmp
13304 || inst
.instruction
== T_MNEM_cmn
)
13305 constraint (Rn
== REG_PC
, BAD_PC
);
13307 reject_bad_reg (Rn
);
13308 reject_bad_reg (Rm
);
13310 if (unified_syntax
)
13312 int r0off
= (inst
.instruction
== T_MNEM_mvn
13313 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13314 bfd_boolean narrow
;
13316 if (inst
.size_req
== 4
13317 || inst
.instruction
> 0xffff
13318 || inst
.operands
[1].shifted
13319 || Rn
> 7 || Rm
> 7)
13321 else if (inst
.instruction
== T_MNEM_cmn
13322 || inst
.instruction
== T_MNEM_tst
)
13324 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13325 narrow
= !in_pred_block ();
13327 narrow
= in_pred_block ();
13329 if (!inst
.operands
[1].isreg
)
13331 /* For an immediate, we always generate a 32-bit opcode;
13332 section relaxation will shrink it later if possible. */
13333 if (inst
.instruction
< 0xffff)
13334 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13335 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13336 inst
.instruction
|= Rn
<< r0off
;
13337 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13341 /* See if we can do this with a 16-bit instruction. */
13344 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13345 inst
.instruction
|= Rn
;
13346 inst
.instruction
|= Rm
<< 3;
13350 constraint (inst
.operands
[1].shifted
13351 && inst
.operands
[1].immisreg
,
13352 _("shift must be constant"));
13353 if (inst
.instruction
< 0xffff)
13354 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13355 inst
.instruction
|= Rn
<< r0off
;
13356 encode_thumb32_shifted_operand (1);
13362 constraint (inst
.instruction
> 0xffff
13363 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13364 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13365 _("unshifted register required"));
13366 constraint (Rn
> 7 || Rm
> 7,
13369 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13370 inst
.instruction
|= Rn
;
13371 inst
.instruction
|= Rm
<< 3;
13380 if (do_vfp_nsyn_mrs () == SUCCESS
)
13383 Rd
= inst
.operands
[0].reg
;
13384 reject_bad_reg (Rd
);
13385 inst
.instruction
|= Rd
<< 8;
13387 if (inst
.operands
[1].isreg
)
13389 unsigned br
= inst
.operands
[1].reg
;
13390 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13391 as_bad (_("bad register for mrs"));
13393 inst
.instruction
|= br
& (0xf << 16);
13394 inst
.instruction
|= (br
& 0x300) >> 4;
13395 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13399 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13401 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13403 /* PR gas/12698: The constraint is only applied for m_profile.
13404 If the user has specified -march=all, we want to ignore it as
13405 we are building for any CPU type, including non-m variants. */
13406 bfd_boolean m_profile
=
13407 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13408 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13409 "not support requested special purpose register"));
13412 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13414 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13415 _("'APSR', 'CPSR' or 'SPSR' expected"));
13417 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13418 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13419 inst
.instruction
|= 0xf0000;
13429 if (do_vfp_nsyn_msr () == SUCCESS
)
13432 constraint (!inst
.operands
[1].isreg
,
13433 _("Thumb encoding does not support an immediate here"));
13435 if (inst
.operands
[0].isreg
)
13436 flags
= (int)(inst
.operands
[0].reg
);
13438 flags
= inst
.operands
[0].imm
;
13440 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13442 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13444 /* PR gas/12698: The constraint is only applied for m_profile.
13445 If the user has specified -march=all, we want to ignore it as
13446 we are building for any CPU type, including non-m variants. */
13447 bfd_boolean m_profile
=
13448 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13449 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13450 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13451 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13452 && bits
!= PSR_f
)) && m_profile
,
13453 _("selected processor does not support requested special "
13454 "purpose register"));
13457 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13458 "requested special purpose register"));
13460 Rn
= inst
.operands
[1].reg
;
13461 reject_bad_reg (Rn
);
13463 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13464 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13465 inst
.instruction
|= (flags
& 0x300) >> 4;
13466 inst
.instruction
|= (flags
& 0xff);
13467 inst
.instruction
|= Rn
<< 16;
13473 bfd_boolean narrow
;
13474 unsigned Rd
, Rn
, Rm
;
13476 if (!inst
.operands
[2].present
)
13477 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13479 Rd
= inst
.operands
[0].reg
;
13480 Rn
= inst
.operands
[1].reg
;
13481 Rm
= inst
.operands
[2].reg
;
13483 if (unified_syntax
)
13485 if (inst
.size_req
== 4
13491 else if (inst
.instruction
== T_MNEM_muls
)
13492 narrow
= !in_pred_block ();
13494 narrow
= in_pred_block ();
13498 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13499 constraint (Rn
> 7 || Rm
> 7,
13506 /* 16-bit MULS/Conditional MUL. */
13507 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13508 inst
.instruction
|= Rd
;
13511 inst
.instruction
|= Rm
<< 3;
13513 inst
.instruction
|= Rn
<< 3;
13515 constraint (1, _("dest must overlap one source register"));
13519 constraint (inst
.instruction
!= T_MNEM_mul
,
13520 _("Thumb-2 MUL must not set flags"));
13522 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13523 inst
.instruction
|= Rd
<< 8;
13524 inst
.instruction
|= Rn
<< 16;
13525 inst
.instruction
|= Rm
<< 0;
13527 reject_bad_reg (Rd
);
13528 reject_bad_reg (Rn
);
13529 reject_bad_reg (Rm
);
13536 unsigned RdLo
, RdHi
, Rn
, Rm
;
13538 RdLo
= inst
.operands
[0].reg
;
13539 RdHi
= inst
.operands
[1].reg
;
13540 Rn
= inst
.operands
[2].reg
;
13541 Rm
= inst
.operands
[3].reg
;
13543 reject_bad_reg (RdLo
);
13544 reject_bad_reg (RdHi
);
13545 reject_bad_reg (Rn
);
13546 reject_bad_reg (Rm
);
13548 inst
.instruction
|= RdLo
<< 12;
13549 inst
.instruction
|= RdHi
<< 8;
13550 inst
.instruction
|= Rn
<< 16;
13551 inst
.instruction
|= Rm
;
13554 as_tsktsk (_("rdhi and rdlo must be different"));
13560 set_pred_insn_type (NEUTRAL_IT_INSN
);
13562 if (unified_syntax
)
13564 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13566 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13567 inst
.instruction
|= inst
.operands
[0].imm
;
13571 /* PR9722: Check for Thumb2 availability before
13572 generating a thumb2 nop instruction. */
13573 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13575 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13576 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13579 inst
.instruction
= 0x46c0;
13584 constraint (inst
.operands
[0].present
,
13585 _("Thumb does not support NOP with hints"));
13586 inst
.instruction
= 0x46c0;
13593 if (unified_syntax
)
13595 bfd_boolean narrow
;
13597 if (THUMB_SETS_FLAGS (inst
.instruction
))
13598 narrow
= !in_pred_block ();
13600 narrow
= in_pred_block ();
13601 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13603 if (inst
.size_req
== 4)
13608 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13609 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13610 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13614 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13615 inst
.instruction
|= inst
.operands
[0].reg
;
13616 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13621 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13623 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13625 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13626 inst
.instruction
|= inst
.operands
[0].reg
;
13627 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13636 Rd
= inst
.operands
[0].reg
;
13637 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13639 reject_bad_reg (Rd
);
13640 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13641 reject_bad_reg (Rn
);
13643 inst
.instruction
|= Rd
<< 8;
13644 inst
.instruction
|= Rn
<< 16;
13646 if (!inst
.operands
[2].isreg
)
13648 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13649 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13655 Rm
= inst
.operands
[2].reg
;
13656 reject_bad_reg (Rm
);
13658 constraint (inst
.operands
[2].shifted
13659 && inst
.operands
[2].immisreg
,
13660 _("shift must be constant"));
13661 encode_thumb32_shifted_operand (2);
13668 unsigned Rd
, Rn
, Rm
;
13670 Rd
= inst
.operands
[0].reg
;
13671 Rn
= inst
.operands
[1].reg
;
13672 Rm
= inst
.operands
[2].reg
;
13674 reject_bad_reg (Rd
);
13675 reject_bad_reg (Rn
);
13676 reject_bad_reg (Rm
);
13678 inst
.instruction
|= Rd
<< 8;
13679 inst
.instruction
|= Rn
<< 16;
13680 inst
.instruction
|= Rm
;
13681 if (inst
.operands
[3].present
)
13683 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13684 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13685 _("expression too complex"));
13686 inst
.instruction
|= (val
& 0x1c) << 10;
13687 inst
.instruction
|= (val
& 0x03) << 6;
13694 if (!inst
.operands
[3].present
)
13698 inst
.instruction
&= ~0x00000020;
13700 /* PR 10168. Swap the Rm and Rn registers. */
13701 Rtmp
= inst
.operands
[1].reg
;
13702 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13703 inst
.operands
[2].reg
= Rtmp
;
13711 if (inst
.operands
[0].immisreg
)
13712 reject_bad_reg (inst
.operands
[0].imm
);
13714 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13718 do_t_push_pop (void)
13722 constraint (inst
.operands
[0].writeback
,
13723 _("push/pop do not support {reglist}^"));
13724 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13725 _("expression too complex"));
13727 mask
= inst
.operands
[0].imm
;
13728 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13729 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13730 else if (inst
.size_req
!= 4
13731 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13732 ? REG_LR
: REG_PC
)))
13734 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13735 inst
.instruction
|= THUMB_PP_PC_LR
;
13736 inst
.instruction
|= mask
& 0xff;
13738 else if (unified_syntax
)
13740 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13741 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13745 inst
.error
= _("invalid register list to push/pop instruction");
13753 if (unified_syntax
)
13754 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13757 inst
.error
= _("invalid register list to push/pop instruction");
13763 do_t_vscclrm (void)
13765 if (inst
.operands
[0].issingle
)
13767 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13768 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13769 inst
.instruction
|= inst
.operands
[0].imm
;
13773 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13774 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13775 inst
.instruction
|= 1 << 8;
13776 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13785 Rd
= inst
.operands
[0].reg
;
13786 Rm
= inst
.operands
[1].reg
;
13788 reject_bad_reg (Rd
);
13789 reject_bad_reg (Rm
);
13791 inst
.instruction
|= Rd
<< 8;
13792 inst
.instruction
|= Rm
<< 16;
13793 inst
.instruction
|= Rm
;
13801 Rd
= inst
.operands
[0].reg
;
13802 Rm
= inst
.operands
[1].reg
;
13804 reject_bad_reg (Rd
);
13805 reject_bad_reg (Rm
);
13807 if (Rd
<= 7 && Rm
<= 7
13808 && inst
.size_req
!= 4)
13810 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13811 inst
.instruction
|= Rd
;
13812 inst
.instruction
|= Rm
<< 3;
13814 else if (unified_syntax
)
13816 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13817 inst
.instruction
|= Rd
<< 8;
13818 inst
.instruction
|= Rm
<< 16;
13819 inst
.instruction
|= Rm
;
13822 inst
.error
= BAD_HIREG
;
13830 Rd
= inst
.operands
[0].reg
;
13831 Rm
= inst
.operands
[1].reg
;
13833 reject_bad_reg (Rd
);
13834 reject_bad_reg (Rm
);
13836 inst
.instruction
|= Rd
<< 8;
13837 inst
.instruction
|= Rm
;
13845 Rd
= inst
.operands
[0].reg
;
13846 Rs
= (inst
.operands
[1].present
13847 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13848 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13850 reject_bad_reg (Rd
);
13851 reject_bad_reg (Rs
);
13852 if (inst
.operands
[2].isreg
)
13853 reject_bad_reg (inst
.operands
[2].reg
);
13855 inst
.instruction
|= Rd
<< 8;
13856 inst
.instruction
|= Rs
<< 16;
13857 if (!inst
.operands
[2].isreg
)
13859 bfd_boolean narrow
;
13861 if ((inst
.instruction
& 0x00100000) != 0)
13862 narrow
= !in_pred_block ();
13864 narrow
= in_pred_block ();
13866 if (Rd
> 7 || Rs
> 7)
13869 if (inst
.size_req
== 4 || !unified_syntax
)
13872 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13873 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13876 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13877 relaxation, but it doesn't seem worth the hassle. */
13880 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13881 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13882 inst
.instruction
|= Rs
<< 3;
13883 inst
.instruction
|= Rd
;
13887 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13888 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13892 encode_thumb32_shifted_operand (2);
13898 if (warn_on_deprecated
13899 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13900 as_tsktsk (_("setend use is deprecated for ARMv8"));
13902 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13903 if (inst
.operands
[0].imm
)
13904 inst
.instruction
|= 0x8;
13910 if (!inst
.operands
[1].present
)
13911 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13913 if (unified_syntax
)
13915 bfd_boolean narrow
;
13918 switch (inst
.instruction
)
13921 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13923 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13925 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13927 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13931 if (THUMB_SETS_FLAGS (inst
.instruction
))
13932 narrow
= !in_pred_block ();
13934 narrow
= in_pred_block ();
13935 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13937 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13939 if (inst
.operands
[2].isreg
13940 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13941 || inst
.operands
[2].reg
> 7))
13943 if (inst
.size_req
== 4)
13946 reject_bad_reg (inst
.operands
[0].reg
);
13947 reject_bad_reg (inst
.operands
[1].reg
);
13951 if (inst
.operands
[2].isreg
)
13953 reject_bad_reg (inst
.operands
[2].reg
);
13954 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13955 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13956 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13957 inst
.instruction
|= inst
.operands
[2].reg
;
13959 /* PR 12854: Error on extraneous shifts. */
13960 constraint (inst
.operands
[2].shifted
,
13961 _("extraneous shift as part of operand to shift insn"));
13965 inst
.operands
[1].shifted
= 1;
13966 inst
.operands
[1].shift_kind
= shift_kind
;
13967 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13968 ? T_MNEM_movs
: T_MNEM_mov
);
13969 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13970 encode_thumb32_shifted_operand (1);
13971 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13972 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13977 if (inst
.operands
[2].isreg
)
13979 switch (shift_kind
)
13981 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13982 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13983 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13984 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13988 inst
.instruction
|= inst
.operands
[0].reg
;
13989 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13991 /* PR 12854: Error on extraneous shifts. */
13992 constraint (inst
.operands
[2].shifted
,
13993 _("extraneous shift as part of operand to shift insn"));
13997 switch (shift_kind
)
13999 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
14000 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
14001 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14004 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14005 inst
.instruction
|= inst
.operands
[0].reg
;
14006 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14012 constraint (inst
.operands
[0].reg
> 7
14013 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
14014 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
14016 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
14018 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
14019 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14020 _("source1 and dest must be same register"));
14022 switch (inst
.instruction
)
14024 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
14025 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
14026 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
14027 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
14031 inst
.instruction
|= inst
.operands
[0].reg
;
14032 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
14034 /* PR 12854: Error on extraneous shifts. */
14035 constraint (inst
.operands
[2].shifted
,
14036 _("extraneous shift as part of operand to shift insn"));
14040 switch (inst
.instruction
)
14042 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
14043 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
14044 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14045 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
14048 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14049 inst
.instruction
|= inst
.operands
[0].reg
;
14050 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14058 unsigned Rd
, Rn
, Rm
;
14060 Rd
= inst
.operands
[0].reg
;
14061 Rn
= inst
.operands
[1].reg
;
14062 Rm
= inst
.operands
[2].reg
;
14064 reject_bad_reg (Rd
);
14065 reject_bad_reg (Rn
);
14066 reject_bad_reg (Rm
);
14068 inst
.instruction
|= Rd
<< 8;
14069 inst
.instruction
|= Rn
<< 16;
14070 inst
.instruction
|= Rm
;
14076 unsigned Rd
, Rn
, Rm
;
14078 Rd
= inst
.operands
[0].reg
;
14079 Rm
= inst
.operands
[1].reg
;
14080 Rn
= inst
.operands
[2].reg
;
14082 reject_bad_reg (Rd
);
14083 reject_bad_reg (Rn
);
14084 reject_bad_reg (Rm
);
14086 inst
.instruction
|= Rd
<< 8;
14087 inst
.instruction
|= Rn
<< 16;
14088 inst
.instruction
|= Rm
;
14094 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14095 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
14096 _("SMC is not permitted on this architecture"));
14097 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14098 _("expression too complex"));
14099 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
14101 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14102 inst
.instruction
|= (value
& 0x000f) << 16;
14104 /* PR gas/15623: SMC instructions must be last in an IT block. */
14105 set_pred_insn_type_last ();
14111 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14113 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14114 inst
.instruction
|= (value
& 0x0fff);
14115 inst
.instruction
|= (value
& 0xf000) << 4;
14119 do_t_ssat_usat (int bias
)
14123 Rd
= inst
.operands
[0].reg
;
14124 Rn
= inst
.operands
[2].reg
;
14126 reject_bad_reg (Rd
);
14127 reject_bad_reg (Rn
);
14129 inst
.instruction
|= Rd
<< 8;
14130 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
14131 inst
.instruction
|= Rn
<< 16;
14133 if (inst
.operands
[3].present
)
14135 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14137 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14139 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14140 _("expression too complex"));
14142 if (shift_amount
!= 0)
14144 constraint (shift_amount
> 31,
14145 _("shift expression is too large"));
14147 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14148 inst
.instruction
|= 0x00200000; /* sh bit. */
14150 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14151 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14159 do_t_ssat_usat (1);
14167 Rd
= inst
.operands
[0].reg
;
14168 Rn
= inst
.operands
[2].reg
;
14170 reject_bad_reg (Rd
);
14171 reject_bad_reg (Rn
);
14173 inst
.instruction
|= Rd
<< 8;
14174 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14175 inst
.instruction
|= Rn
<< 16;
14181 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14182 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14183 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14184 || inst
.operands
[2].negative
,
14187 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14189 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14190 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14191 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14192 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14198 if (!inst
.operands
[2].present
)
14199 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14201 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14202 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14203 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14206 inst
.instruction
|= inst
.operands
[0].reg
;
14207 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14208 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14209 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14215 unsigned Rd
, Rn
, Rm
;
14217 Rd
= inst
.operands
[0].reg
;
14218 Rn
= inst
.operands
[1].reg
;
14219 Rm
= inst
.operands
[2].reg
;
14221 reject_bad_reg (Rd
);
14222 reject_bad_reg (Rn
);
14223 reject_bad_reg (Rm
);
14225 inst
.instruction
|= Rd
<< 8;
14226 inst
.instruction
|= Rn
<< 16;
14227 inst
.instruction
|= Rm
;
14228 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14236 Rd
= inst
.operands
[0].reg
;
14237 Rm
= inst
.operands
[1].reg
;
14239 reject_bad_reg (Rd
);
14240 reject_bad_reg (Rm
);
14242 if (inst
.instruction
<= 0xffff
14243 && inst
.size_req
!= 4
14244 && Rd
<= 7 && Rm
<= 7
14245 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14247 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14248 inst
.instruction
|= Rd
;
14249 inst
.instruction
|= Rm
<< 3;
14251 else if (unified_syntax
)
14253 if (inst
.instruction
<= 0xffff)
14254 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14255 inst
.instruction
|= Rd
<< 8;
14256 inst
.instruction
|= Rm
;
14257 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14261 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14262 _("Thumb encoding does not support rotation"));
14263 constraint (1, BAD_HIREG
);
14270 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14279 half
= (inst
.instruction
& 0x10) != 0;
14280 set_pred_insn_type_last ();
14281 constraint (inst
.operands
[0].immisreg
,
14282 _("instruction requires register index"));
14284 Rn
= inst
.operands
[0].reg
;
14285 Rm
= inst
.operands
[0].imm
;
14287 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14288 constraint (Rn
== REG_SP
, BAD_SP
);
14289 reject_bad_reg (Rm
);
14291 constraint (!half
&& inst
.operands
[0].shifted
,
14292 _("instruction does not allow shifted index"));
14293 inst
.instruction
|= (Rn
<< 16) | Rm
;
14299 if (!inst
.operands
[0].present
)
14300 inst
.operands
[0].imm
= 0;
14302 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14304 constraint (inst
.size_req
== 2,
14305 _("immediate value out of range"));
14306 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14307 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14308 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14312 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14313 inst
.instruction
|= inst
.operands
[0].imm
;
14316 set_pred_insn_type (NEUTRAL_IT_INSN
);
14323 do_t_ssat_usat (0);
14331 Rd
= inst
.operands
[0].reg
;
14332 Rn
= inst
.operands
[2].reg
;
14334 reject_bad_reg (Rd
);
14335 reject_bad_reg (Rn
);
14337 inst
.instruction
|= Rd
<< 8;
14338 inst
.instruction
|= inst
.operands
[1].imm
;
14339 inst
.instruction
|= Rn
<< 16;
14342 /* Checking the range of the branch offset (VAL) with NBITS bits
14343 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14345 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14347 gas_assert (nbits
> 0 && nbits
<= 32);
14350 int cmp
= (1 << (nbits
- 1));
14351 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14356 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14362 /* For branches in Armv8.1-M Mainline. */
14364 do_t_branch_future (void)
14366 unsigned long insn
= inst
.instruction
;
14368 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14369 if (inst
.operands
[0].hasreloc
== 0)
14371 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14372 as_bad (BAD_BRANCH_OFF
);
14374 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14378 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14379 inst
.relocs
[0].pc_rel
= 1;
14385 if (inst
.operands
[1].hasreloc
== 0)
14387 int val
= inst
.operands
[1].imm
;
14388 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14389 as_bad (BAD_BRANCH_OFF
);
14391 int immA
= (val
& 0x0001f000) >> 12;
14392 int immB
= (val
& 0x00000ffc) >> 2;
14393 int immC
= (val
& 0x00000002) >> 1;
14394 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14398 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14399 inst
.relocs
[1].pc_rel
= 1;
14404 if (inst
.operands
[1].hasreloc
== 0)
14406 int val
= inst
.operands
[1].imm
;
14407 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14408 as_bad (BAD_BRANCH_OFF
);
14410 int immA
= (val
& 0x0007f000) >> 12;
14411 int immB
= (val
& 0x00000ffc) >> 2;
14412 int immC
= (val
& 0x00000002) >> 1;
14413 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14417 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14418 inst
.relocs
[1].pc_rel
= 1;
14422 case T_MNEM_bfcsel
:
14424 if (inst
.operands
[1].hasreloc
== 0)
14426 int val
= inst
.operands
[1].imm
;
14427 int immA
= (val
& 0x00001000) >> 12;
14428 int immB
= (val
& 0x00000ffc) >> 2;
14429 int immC
= (val
& 0x00000002) >> 1;
14430 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14434 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14435 inst
.relocs
[1].pc_rel
= 1;
14439 if (inst
.operands
[2].hasreloc
== 0)
14441 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14442 int val2
= inst
.operands
[2].imm
;
14443 int val0
= inst
.operands
[0].imm
& 0x1f;
14444 int diff
= val2
- val0
;
14446 inst
.instruction
|= 1 << 17; /* T bit. */
14447 else if (diff
!= 2)
14448 as_bad (_("out of range label-relative fixup value"));
14452 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14453 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14454 inst
.relocs
[2].pc_rel
= 1;
14458 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14459 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14464 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14471 /* Helper function for do_t_loloop to handle relocations. */
14473 v8_1_loop_reloc (int is_le
)
14475 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14477 int value
= inst
.relocs
[0].exp
.X_add_number
;
14478 value
= (is_le
) ? -value
: value
;
14480 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14481 as_bad (BAD_BRANCH_OFF
);
14485 immh
= (value
& 0x00000ffc) >> 2;
14486 imml
= (value
& 0x00000002) >> 1;
14488 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14492 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14493 inst
.relocs
[0].pc_rel
= 1;
14497 /* For shifts with four operands in MVE. */
14499 do_mve_scalar_shift1 (void)
14501 unsigned int value
= inst
.operands
[2].imm
;
14503 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14504 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14506 /* Setting the bit for saturation. */
14507 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14509 /* Assuming Rm is already checked not to be 11x1. */
14510 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14511 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14512 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14515 /* For shifts in MVE. */
14517 do_mve_scalar_shift (void)
14519 if (!inst
.operands
[2].present
)
14521 inst
.operands
[2] = inst
.operands
[1];
14522 inst
.operands
[1].reg
= 0xf;
14525 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14526 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14528 if (inst
.operands
[2].isreg
)
14530 /* Assuming Rm is already checked not to be 11x1. */
14531 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14532 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14533 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14537 /* Assuming imm is already checked as [1,32]. */
14538 unsigned int value
= inst
.operands
[2].imm
;
14539 inst
.instruction
|= (value
& 0x1c) << 10;
14540 inst
.instruction
|= (value
& 0x03) << 6;
14541 /* Change last 4 bits from 0xd to 0xf. */
14542 inst
.instruction
|= 0x2;
14546 /* MVE instruction encoder helpers. */
14547 #define M_MNEM_vabav 0xee800f01
14548 #define M_MNEM_vmladav 0xeef00e00
14549 #define M_MNEM_vmladava 0xeef00e20
14550 #define M_MNEM_vmladavx 0xeef01e00
14551 #define M_MNEM_vmladavax 0xeef01e20
14552 #define M_MNEM_vmlsdav 0xeef00e01
14553 #define M_MNEM_vmlsdava 0xeef00e21
14554 #define M_MNEM_vmlsdavx 0xeef01e01
14555 #define M_MNEM_vmlsdavax 0xeef01e21
14556 #define M_MNEM_vmullt 0xee011e00
14557 #define M_MNEM_vmullb 0xee010e00
14558 #define M_MNEM_vctp 0xf000e801
14559 #define M_MNEM_vst20 0xfc801e00
14560 #define M_MNEM_vst21 0xfc801e20
14561 #define M_MNEM_vst40 0xfc801e01
14562 #define M_MNEM_vst41 0xfc801e21
14563 #define M_MNEM_vst42 0xfc801e41
14564 #define M_MNEM_vst43 0xfc801e61
14565 #define M_MNEM_vld20 0xfc901e00
14566 #define M_MNEM_vld21 0xfc901e20
14567 #define M_MNEM_vld40 0xfc901e01
14568 #define M_MNEM_vld41 0xfc901e21
14569 #define M_MNEM_vld42 0xfc901e41
14570 #define M_MNEM_vld43 0xfc901e61
14571 #define M_MNEM_vstrb 0xec000e00
14572 #define M_MNEM_vstrh 0xec000e10
14573 #define M_MNEM_vstrw 0xec000e40
14574 #define M_MNEM_vstrd 0xec000e50
14575 #define M_MNEM_vldrb 0xec100e00
14576 #define M_MNEM_vldrh 0xec100e10
14577 #define M_MNEM_vldrw 0xec100e40
14578 #define M_MNEM_vldrd 0xec100e50
14579 #define M_MNEM_vmovlt 0xeea01f40
14580 #define M_MNEM_vmovlb 0xeea00f40
14581 #define M_MNEM_vmovnt 0xfe311e81
14582 #define M_MNEM_vmovnb 0xfe310e81
14583 #define M_MNEM_vadc 0xee300f00
14584 #define M_MNEM_vadci 0xee301f00
14585 #define M_MNEM_vbrsr 0xfe011e60
14586 #define M_MNEM_vaddlv 0xee890f00
14587 #define M_MNEM_vaddlva 0xee890f20
14588 #define M_MNEM_vaddv 0xeef10f00
14589 #define M_MNEM_vaddva 0xeef10f20
14590 #define M_MNEM_vddup 0xee011f6e
14591 #define M_MNEM_vdwdup 0xee011f60
14592 #define M_MNEM_vidup 0xee010f6e
14593 #define M_MNEM_viwdup 0xee010f60
14594 #define M_MNEM_vmaxv 0xeee20f00
14595 #define M_MNEM_vmaxav 0xeee00f00
14596 #define M_MNEM_vminv 0xeee20f80
14597 #define M_MNEM_vminav 0xeee00f80
14598 #define M_MNEM_vmlaldav 0xee800e00
14599 #define M_MNEM_vmlaldava 0xee800e20
14600 #define M_MNEM_vmlaldavx 0xee801e00
14601 #define M_MNEM_vmlaldavax 0xee801e20
14602 #define M_MNEM_vmlsldav 0xee800e01
14603 #define M_MNEM_vmlsldava 0xee800e21
14604 #define M_MNEM_vmlsldavx 0xee801e01
14605 #define M_MNEM_vmlsldavax 0xee801e21
14606 #define M_MNEM_vrmlaldavhx 0xee801f00
14607 #define M_MNEM_vrmlaldavhax 0xee801f20
14608 #define M_MNEM_vrmlsldavh 0xfe800e01
14609 #define M_MNEM_vrmlsldavha 0xfe800e21
14610 #define M_MNEM_vrmlsldavhx 0xfe801e01
14611 #define M_MNEM_vrmlsldavhax 0xfe801e21
14612 #define M_MNEM_vqmovnt 0xee331e01
14613 #define M_MNEM_vqmovnb 0xee330e01
14614 #define M_MNEM_vqmovunt 0xee311e81
14615 #define M_MNEM_vqmovunb 0xee310e81
14616 #define M_MNEM_vshrnt 0xee801fc1
14617 #define M_MNEM_vshrnb 0xee800fc1
14618 #define M_MNEM_vrshrnt 0xfe801fc1
14619 #define M_MNEM_vqshrnt 0xee801f40
14620 #define M_MNEM_vqshrnb 0xee800f40
14621 #define M_MNEM_vqshrunt 0xee801fc0
14622 #define M_MNEM_vqshrunb 0xee800fc0
14623 #define M_MNEM_vrshrnb 0xfe800fc1
14624 #define M_MNEM_vqrshrnt 0xee801f41
14625 #define M_MNEM_vqrshrnb 0xee800f41
14626 #define M_MNEM_vqrshrunt 0xfe801fc0
14627 #define M_MNEM_vqrshrunb 0xfe800fc0
14629 /* Bfloat16 instruction encoder helpers. */
14630 #define B_MNEM_vfmat 0xfc300850
14631 #define B_MNEM_vfmab 0xfc300810
14633 /* Neon instruction encoder helpers. */
14635 /* Encodings for the different types for various Neon opcodes. */
14637 /* An "invalid" code for the following tables. */
14640 struct neon_tab_entry
14643 unsigned float_or_poly
;
14644 unsigned scalar_or_imm
;
14647 /* Map overloaded Neon opcodes to their respective encodings. */
14648 #define NEON_ENC_TAB \
14649 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14650 X(vabdl, 0x0800700, N_INV, N_INV), \
14651 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14652 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14653 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14654 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14655 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14656 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14657 X(vaddl, 0x0800000, N_INV, N_INV), \
14658 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14659 X(vsubl, 0x0800200, N_INV, N_INV), \
14660 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14661 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14662 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14663 /* Register variants of the following two instructions are encoded as
14664 vcge / vcgt with the operands reversed. */ \
14665 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14666 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14667 X(vfma, N_INV, 0x0000c10, N_INV), \
14668 X(vfms, N_INV, 0x0200c10, N_INV), \
14669 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14670 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14671 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14672 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14673 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14674 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14675 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14676 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14677 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14678 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14679 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14680 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14681 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14682 X(vshl, 0x0000400, N_INV, 0x0800510), \
14683 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14684 X(vand, 0x0000110, N_INV, 0x0800030), \
14685 X(vbic, 0x0100110, N_INV, 0x0800030), \
14686 X(veor, 0x1000110, N_INV, N_INV), \
14687 X(vorn, 0x0300110, N_INV, 0x0800010), \
14688 X(vorr, 0x0200110, N_INV, 0x0800010), \
14689 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14690 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14691 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14692 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14693 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14694 X(vst1, 0x0000000, 0x0800000, N_INV), \
14695 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14696 X(vst2, 0x0000100, 0x0800100, N_INV), \
14697 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14698 X(vst3, 0x0000200, 0x0800200, N_INV), \
14699 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14700 X(vst4, 0x0000300, 0x0800300, N_INV), \
14701 X(vmovn, 0x1b20200, N_INV, N_INV), \
14702 X(vtrn, 0x1b20080, N_INV, N_INV), \
14703 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14704 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14705 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14706 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14707 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14708 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14709 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14710 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14711 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14712 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14713 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14714 X(vseleq, 0xe000a00, N_INV, N_INV), \
14715 X(vselvs, 0xe100a00, N_INV, N_INV), \
14716 X(vselge, 0xe200a00, N_INV, N_INV), \
14717 X(vselgt, 0xe300a00, N_INV, N_INV), \
14718 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14719 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14720 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14721 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14722 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14723 X(aes, 0x3b00300, N_INV, N_INV), \
14724 X(sha3op, 0x2000c00, N_INV, N_INV), \
14725 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14726 X(sha2op, 0x3ba0380, N_INV, N_INV)
14730 #define X(OPC,I,F,S) N_MNEM_##OPC
14735 static const struct neon_tab_entry neon_enc_tab
[] =
14737 #define X(OPC,I,F,S) { (I), (F), (S) }
14742 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14743 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14744 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14745 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14746 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14747 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14748 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14749 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14750 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14751 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14752 #define NEON_ENC_SINGLE_(X) \
14753 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14754 #define NEON_ENC_DOUBLE_(X) \
14755 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14756 #define NEON_ENC_FPV8_(X) \
14757 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14759 #define NEON_ENCODE(type, inst) \
14762 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14763 inst.is_neon = 1; \
14767 #define check_neon_suffixes \
14770 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14772 as_bad (_("invalid neon suffix for non neon instruction")); \
14778 /* Define shapes for instruction operands. The following mnemonic characters
14779 are used in this table:
14781 F - VFP S<n> register
14782 D - Neon D<n> register
14783 Q - Neon Q<n> register
14787 L - D<n> register list
14789 This table is used to generate various data:
14790 - enumerations of the form NS_DDR to be used as arguments to
14792 - a table classifying shapes into single, double, quad, mixed.
14793 - a table used to drive neon_select_shape. */
14795 #define NEON_SHAPE_DEF \
14796 X(4, (R, R, Q, Q), QUAD), \
14797 X(4, (Q, R, R, I), QUAD), \
14798 X(4, (R, R, S, S), QUAD), \
14799 X(4, (S, S, R, R), QUAD), \
14800 X(3, (Q, R, I), QUAD), \
14801 X(3, (I, Q, Q), QUAD), \
14802 X(3, (I, Q, R), QUAD), \
14803 X(3, (R, Q, Q), QUAD), \
14804 X(3, (D, D, D), DOUBLE), \
14805 X(3, (Q, Q, Q), QUAD), \
14806 X(3, (D, D, I), DOUBLE), \
14807 X(3, (Q, Q, I), QUAD), \
14808 X(3, (D, D, S), DOUBLE), \
14809 X(3, (Q, Q, S), QUAD), \
14810 X(3, (Q, Q, R), QUAD), \
14811 X(3, (R, R, Q), QUAD), \
14812 X(2, (R, Q), QUAD), \
14813 X(2, (D, D), DOUBLE), \
14814 X(2, (Q, Q), QUAD), \
14815 X(2, (D, S), DOUBLE), \
14816 X(2, (Q, S), QUAD), \
14817 X(2, (D, R), DOUBLE), \
14818 X(2, (Q, R), QUAD), \
14819 X(2, (D, I), DOUBLE), \
14820 X(2, (Q, I), QUAD), \
14821 X(3, (P, F, I), SINGLE), \
14822 X(3, (P, D, I), DOUBLE), \
14823 X(3, (P, Q, I), QUAD), \
14824 X(4, (P, F, F, I), SINGLE), \
14825 X(4, (P, D, D, I), DOUBLE), \
14826 X(4, (P, Q, Q, I), QUAD), \
14827 X(5, (P, F, F, F, I), SINGLE), \
14828 X(5, (P, D, D, D, I), DOUBLE), \
14829 X(5, (P, Q, Q, Q, I), QUAD), \
14830 X(3, (D, L, D), DOUBLE), \
14831 X(2, (D, Q), MIXED), \
14832 X(2, (Q, D), MIXED), \
14833 X(3, (D, Q, I), MIXED), \
14834 X(3, (Q, D, I), MIXED), \
14835 X(3, (Q, D, D), MIXED), \
14836 X(3, (D, Q, Q), MIXED), \
14837 X(3, (Q, Q, D), MIXED), \
14838 X(3, (Q, D, S), MIXED), \
14839 X(3, (D, Q, S), MIXED), \
14840 X(4, (D, D, D, I), DOUBLE), \
14841 X(4, (Q, Q, Q, I), QUAD), \
14842 X(4, (D, D, S, I), DOUBLE), \
14843 X(4, (Q, Q, S, I), QUAD), \
14844 X(2, (F, F), SINGLE), \
14845 X(3, (F, F, F), SINGLE), \
14846 X(2, (F, I), SINGLE), \
14847 X(2, (F, D), MIXED), \
14848 X(2, (D, F), MIXED), \
14849 X(3, (F, F, I), MIXED), \
14850 X(4, (R, R, F, F), SINGLE), \
14851 X(4, (F, F, R, R), SINGLE), \
14852 X(3, (D, R, R), DOUBLE), \
14853 X(3, (R, R, D), DOUBLE), \
14854 X(2, (S, R), SINGLE), \
14855 X(2, (R, S), SINGLE), \
14856 X(2, (F, R), SINGLE), \
14857 X(2, (R, F), SINGLE), \
14858 /* Used for MVE tail predicated loop instructions. */\
14859 X(2, (R, R), QUAD), \
14860 /* Half float shape supported so far. */\
14861 X (2, (H, D), MIXED), \
14862 X (2, (D, H), MIXED), \
14863 X (2, (H, F), MIXED), \
14864 X (2, (F, H), MIXED), \
14865 X (2, (H, H), HALF), \
14866 X (2, (H, R), HALF), \
14867 X (2, (R, H), HALF), \
14868 X (2, (H, I), HALF), \
14869 X (3, (H, H, H), HALF), \
14870 X (3, (H, F, I), MIXED), \
14871 X (3, (F, H, I), MIXED), \
14872 X (3, (D, H, H), MIXED), \
14873 X (3, (D, H, S), MIXED)
14875 #define S2(A,B) NS_##A##B
14876 #define S3(A,B,C) NS_##A##B##C
14877 #define S4(A,B,C,D) NS_##A##B##C##D
14878 #define S5(A,B,C,D,E) NS_##A##B##C##D##E
14880 #define X(N, L, C) S##N L
14894 enum neon_shape_class
14903 #define X(N, L, C) SC_##C
14905 static enum neon_shape_class neon_shape_class
[] =
14925 /* Register widths of above. */
14926 static unsigned neon_shape_el_size
[] =
14939 struct neon_shape_info
14942 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14945 #define S2(A,B) { SE_##A, SE_##B }
14946 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14947 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14948 #define S5(A,B,C,D,E) { SE_##A, SE_##B, SE_##C, SE_##D, SE_##E }
14950 #define X(N, L, C) { N, S##N L }
14952 static struct neon_shape_info neon_shape_tab
[] =
14963 /* Bit masks used in type checking given instructions.
14964 'N_EQK' means the type must be the same as (or based on in some way) the key
14965 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14966 set, various other bits can be set as well in order to modify the meaning of
14967 the type constraint. */
14969 enum neon_type_mask
14993 N_BF16
= 0x0400000,
14994 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14995 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14996 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14997 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14998 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14999 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
15000 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
15001 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
15002 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
15003 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
15004 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
15006 N_MAX_NONSPECIAL
= N_P64
15009 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
15011 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
15012 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15013 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
15014 #define N_S_32 (N_S8 | N_S16 | N_S32)
15015 #define N_F_16_32 (N_F16 | N_F32)
15016 #define N_SUF_32 (N_SU_32 | N_F_16_32)
15017 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
15018 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
15019 #define N_F_ALL (N_F16 | N_F32 | N_F64)
15020 #define N_I_MVE (N_I8 | N_I16 | N_I32)
15021 #define N_F_MVE (N_F16 | N_F32)
15022 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15024 /* Pass this as the first type argument to neon_check_type to ignore types
15026 #define N_IGNORE_TYPE (N_KEY | N_EQK)
15028 /* Select a "shape" for the current instruction (describing register types or
15029 sizes) from a list of alternatives. Return NS_NULL if the current instruction
15030 doesn't fit. For non-polymorphic shapes, checking is usually done as a
15031 function of operand parsing, so this function doesn't need to be called.
15032 Shapes should be listed in order of decreasing length. */
15034 static enum neon_shape
15035 neon_select_shape (enum neon_shape shape
, ...)
15038 enum neon_shape first_shape
= shape
;
15040 /* Fix missing optional operands. FIXME: we don't know at this point how
15041 many arguments we should have, so this makes the assumption that we have
15042 > 1. This is true of all current Neon opcodes, I think, but may not be
15043 true in the future. */
15044 if (!inst
.operands
[1].present
)
15045 inst
.operands
[1] = inst
.operands
[0];
15047 va_start (ap
, shape
);
15049 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
15054 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
15056 if (!inst
.operands
[j
].present
)
15062 switch (neon_shape_tab
[shape
].el
[j
])
15064 /* If a .f16, .16, .u16, .s16 type specifier is given over
15065 a VFP single precision register operand, it's essentially
15066 means only half of the register is used.
15068 If the type specifier is given after the mnemonics, the
15069 information is stored in inst.vectype. If the type specifier
15070 is given after register operand, the information is stored
15071 in inst.operands[].vectype.
15073 When there is only one type specifier, and all the register
15074 operands are the same type of hardware register, the type
15075 specifier applies to all register operands.
15077 If no type specifier is given, the shape is inferred from
15078 operand information.
15081 vadd.f16 s0, s1, s2: NS_HHH
15082 vabs.f16 s0, s1: NS_HH
15083 vmov.f16 s0, r1: NS_HR
15084 vmov.f16 r0, s1: NS_RH
15085 vcvt.f16 r0, s1: NS_RH
15086 vcvt.f16.s32 s2, s2, #29: NS_HFI
15087 vcvt.f16.s32 s2, s2: NS_HF
15090 if (!(inst
.operands
[j
].isreg
15091 && inst
.operands
[j
].isvec
15092 && inst
.operands
[j
].issingle
15093 && !inst
.operands
[j
].isquad
15094 && ((inst
.vectype
.elems
== 1
15095 && inst
.vectype
.el
[0].size
== 16)
15096 || (inst
.vectype
.elems
> 1
15097 && inst
.vectype
.el
[j
].size
== 16)
15098 || (inst
.vectype
.elems
== 0
15099 && inst
.operands
[j
].vectype
.type
!= NT_invtype
15100 && inst
.operands
[j
].vectype
.size
== 16))))
15105 if (!(inst
.operands
[j
].isreg
15106 && inst
.operands
[j
].isvec
15107 && inst
.operands
[j
].issingle
15108 && !inst
.operands
[j
].isquad
15109 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
15110 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
15111 || (inst
.vectype
.elems
== 0
15112 && (inst
.operands
[j
].vectype
.size
== 32
15113 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
15118 if (!(inst
.operands
[j
].isreg
15119 && inst
.operands
[j
].isvec
15120 && !inst
.operands
[j
].isquad
15121 && !inst
.operands
[j
].issingle
))
15126 if (!(inst
.operands
[j
].isreg
15127 && !inst
.operands
[j
].isvec
))
15132 if (!(inst
.operands
[j
].isreg
15133 && inst
.operands
[j
].isvec
15134 && inst
.operands
[j
].isquad
15135 && !inst
.operands
[j
].issingle
))
15140 if (!(!inst
.operands
[j
].isreg
15141 && !inst
.operands
[j
].isscalar
))
15146 if (!(!inst
.operands
[j
].isreg
15147 && inst
.operands
[j
].isscalar
))
15158 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15159 /* We've matched all the entries in the shape table, and we don't
15160 have any left over operands which have not been matched. */
15166 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15167 first_error (_("invalid instruction shape"));
15172 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15173 means the Q bit should be set). */
15176 neon_quad (enum neon_shape shape
)
15178 return neon_shape_class
[shape
] == SC_QUAD
;
15182 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15185 /* Allow modification to be made to types which are constrained to be
15186 based on the key element, based on bits set alongside N_EQK. */
15187 if ((typebits
& N_EQK
) != 0)
15189 if ((typebits
& N_HLF
) != 0)
15191 else if ((typebits
& N_DBL
) != 0)
15193 if ((typebits
& N_SGN
) != 0)
15194 *g_type
= NT_signed
;
15195 else if ((typebits
& N_UNS
) != 0)
15196 *g_type
= NT_unsigned
;
15197 else if ((typebits
& N_INT
) != 0)
15198 *g_type
= NT_integer
;
15199 else if ((typebits
& N_FLT
) != 0)
15200 *g_type
= NT_float
;
15201 else if ((typebits
& N_SIZ
) != 0)
15202 *g_type
= NT_untyped
;
15206 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15207 operand type, i.e. the single type specified in a Neon instruction when it
15208 is the only one given. */
15210 static struct neon_type_el
15211 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15213 struct neon_type_el dest
= *key
;
15215 gas_assert ((thisarg
& N_EQK
) != 0);
15217 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15222 /* Convert Neon type and size into compact bitmask representation. */
15224 static enum neon_type_mask
15225 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15232 case 8: return N_8
;
15233 case 16: return N_16
;
15234 case 32: return N_32
;
15235 case 64: return N_64
;
15243 case 8: return N_I8
;
15244 case 16: return N_I16
;
15245 case 32: return N_I32
;
15246 case 64: return N_I64
;
15254 case 16: return N_F16
;
15255 case 32: return N_F32
;
15256 case 64: return N_F64
;
15264 case 8: return N_P8
;
15265 case 16: return N_P16
;
15266 case 64: return N_P64
;
15274 case 8: return N_S8
;
15275 case 16: return N_S16
;
15276 case 32: return N_S32
;
15277 case 64: return N_S64
;
15285 case 8: return N_U8
;
15286 case 16: return N_U16
;
15287 case 32: return N_U32
;
15288 case 64: return N_U64
;
15294 if (size
== 16) return N_BF16
;
15303 /* Convert compact Neon bitmask type representation to a type and size. Only
15304 handles the case where a single bit is set in the mask. */
15307 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15308 enum neon_type_mask mask
)
15310 if ((mask
& N_EQK
) != 0)
15313 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15315 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
| N_BF16
))
15318 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15320 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15325 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15327 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15328 *type
= NT_unsigned
;
15329 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15330 *type
= NT_integer
;
15331 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15332 *type
= NT_untyped
;
15333 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15335 else if ((mask
& (N_F_ALL
)) != 0)
15337 else if ((mask
& (N_BF16
)) != 0)
15345 /* Modify a bitmask of allowed types. This is only needed for type
15349 modify_types_allowed (unsigned allowed
, unsigned mods
)
15352 enum neon_el_type type
;
15358 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15360 if (el_type_of_type_chk (&type
, &size
,
15361 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15363 neon_modify_type_size (mods
, &type
, &size
);
15364 destmask
|= type_chk_of_el_type (type
, size
);
15371 /* Check type and return type classification.
15372 The manual states (paraphrase): If one datatype is given, it indicates the
15374 - the second operand, if there is one
15375 - the operand, if there is no second operand
15376 - the result, if there are no operands.
15377 This isn't quite good enough though, so we use a concept of a "key" datatype
15378 which is set on a per-instruction basis, which is the one which matters when
15379 only one data type is written.
15380 Note: this function has side-effects (e.g. filling in missing operands). All
15381 Neon instructions should call it before performing bit encoding. */
15383 static struct neon_type_el
15384 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15387 unsigned i
, pass
, key_el
= 0;
15388 unsigned types
[NEON_MAX_TYPE_ELS
];
15389 enum neon_el_type k_type
= NT_invtype
;
15390 unsigned k_size
= -1u;
15391 struct neon_type_el badtype
= {NT_invtype
, -1};
15392 unsigned key_allowed
= 0;
15394 /* Optional registers in Neon instructions are always (not) in operand 1.
15395 Fill in the missing operand here, if it was omitted. */
15396 if (els
> 1 && !inst
.operands
[1].present
)
15397 inst
.operands
[1] = inst
.operands
[0];
15399 /* Suck up all the varargs. */
15401 for (i
= 0; i
< els
; i
++)
15403 unsigned thisarg
= va_arg (ap
, unsigned);
15404 if (thisarg
== N_IGNORE_TYPE
)
15409 types
[i
] = thisarg
;
15410 if ((thisarg
& N_KEY
) != 0)
15415 if (inst
.vectype
.elems
> 0)
15416 for (i
= 0; i
< els
; i
++)
15417 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15419 first_error (_("types specified in both the mnemonic and operands"));
15423 /* Duplicate inst.vectype elements here as necessary.
15424 FIXME: No idea if this is exactly the same as the ARM assembler,
15425 particularly when an insn takes one register and one non-register
15427 if (inst
.vectype
.elems
== 1 && els
> 1)
15430 inst
.vectype
.elems
= els
;
15431 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15432 for (j
= 0; j
< els
; j
++)
15434 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15437 else if (inst
.vectype
.elems
== 0 && els
> 0)
15440 /* No types were given after the mnemonic, so look for types specified
15441 after each operand. We allow some flexibility here; as long as the
15442 "key" operand has a type, we can infer the others. */
15443 for (j
= 0; j
< els
; j
++)
15444 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15445 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15447 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15449 for (j
= 0; j
< els
; j
++)
15450 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15451 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15456 first_error (_("operand types can't be inferred"));
15460 else if (inst
.vectype
.elems
!= els
)
15462 first_error (_("type specifier has the wrong number of parts"));
15466 for (pass
= 0; pass
< 2; pass
++)
15468 for (i
= 0; i
< els
; i
++)
15470 unsigned thisarg
= types
[i
];
15471 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15472 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15473 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15474 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15476 /* Decay more-specific signed & unsigned types to sign-insensitive
15477 integer types if sign-specific variants are unavailable. */
15478 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15479 && (types_allowed
& N_SU_ALL
) == 0)
15480 g_type
= NT_integer
;
15482 /* If only untyped args are allowed, decay any more specific types to
15483 them. Some instructions only care about signs for some element
15484 sizes, so handle that properly. */
15485 if (((types_allowed
& N_UNT
) == 0)
15486 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15487 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15488 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15489 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15490 g_type
= NT_untyped
;
15494 if ((thisarg
& N_KEY
) != 0)
15498 key_allowed
= thisarg
& ~N_KEY
;
15500 /* Check architecture constraint on FP16 extension. */
15502 && k_type
== NT_float
15503 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15505 inst
.error
= _(BAD_FP16
);
15512 if ((thisarg
& N_VFP
) != 0)
15514 enum neon_shape_el regshape
;
15515 unsigned regwidth
, match
;
15517 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15520 first_error (_("invalid instruction shape"));
15523 regshape
= neon_shape_tab
[ns
].el
[i
];
15524 regwidth
= neon_shape_el_size
[regshape
];
15526 /* In VFP mode, operands must match register widths. If we
15527 have a key operand, use its width, else use the width of
15528 the current operand. */
15534 /* FP16 will use a single precision register. */
15535 if (regwidth
== 32 && match
== 16)
15537 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15541 inst
.error
= _(BAD_FP16
);
15546 if (regwidth
!= match
)
15548 first_error (_("operand size must match register width"));
15553 if ((thisarg
& N_EQK
) == 0)
15555 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15557 if ((given_type
& types_allowed
) == 0)
15559 first_error (BAD_SIMD_TYPE
);
15565 enum neon_el_type mod_k_type
= k_type
;
15566 unsigned mod_k_size
= k_size
;
15567 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15568 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15570 first_error (_("inconsistent types in Neon instruction"));
15578 return inst
.vectype
.el
[key_el
];
15581 /* Neon-style VFP instruction forwarding. */
15583 /* Thumb VFP instructions have 0xE in the condition field. */
15586 do_vfp_cond_or_thumb (void)
15591 inst
.instruction
|= 0xe0000000;
15593 inst
.instruction
|= inst
.cond
<< 28;
15596 /* Look up and encode a simple mnemonic, for use as a helper function for the
15597 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15598 etc. It is assumed that operand parsing has already been done, and that the
15599 operands are in the form expected by the given opcode (this isn't necessarily
15600 the same as the form in which they were parsed, hence some massaging must
15601 take place before this function is called).
15602 Checks current arch version against that in the looked-up opcode. */
15605 do_vfp_nsyn_opcode (const char *opname
)
15607 const struct asm_opcode
*opcode
;
15609 opcode
= (const struct asm_opcode
*) str_hash_find (arm_ops_hsh
, opname
);
15614 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15615 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15622 inst
.instruction
= opcode
->tvalue
;
15623 opcode
->tencode ();
15627 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15628 opcode
->aencode ();
15633 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15635 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15637 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15640 do_vfp_nsyn_opcode ("fadds");
15642 do_vfp_nsyn_opcode ("fsubs");
15644 /* ARMv8.2 fp16 instruction. */
15646 do_scalar_fp16_v82_encode ();
15651 do_vfp_nsyn_opcode ("faddd");
15653 do_vfp_nsyn_opcode ("fsubd");
15657 /* Check operand types to see if this is a VFP instruction, and if so call
15661 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15663 enum neon_shape rs
;
15664 struct neon_type_el et
;
15669 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15670 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15674 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15675 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15676 N_F_ALL
| N_KEY
| N_VFP
);
15683 if (et
.type
!= NT_invtype
)
15694 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15696 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15698 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15701 do_vfp_nsyn_opcode ("fmacs");
15703 do_vfp_nsyn_opcode ("fnmacs");
15705 /* ARMv8.2 fp16 instruction. */
15707 do_scalar_fp16_v82_encode ();
15712 do_vfp_nsyn_opcode ("fmacd");
15714 do_vfp_nsyn_opcode ("fnmacd");
15719 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15721 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15723 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15726 do_vfp_nsyn_opcode ("ffmas");
15728 do_vfp_nsyn_opcode ("ffnmas");
15730 /* ARMv8.2 fp16 instruction. */
15732 do_scalar_fp16_v82_encode ();
15737 do_vfp_nsyn_opcode ("ffmad");
15739 do_vfp_nsyn_opcode ("ffnmad");
15744 do_vfp_nsyn_mul (enum neon_shape rs
)
15746 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15748 do_vfp_nsyn_opcode ("fmuls");
15750 /* ARMv8.2 fp16 instruction. */
15752 do_scalar_fp16_v82_encode ();
15755 do_vfp_nsyn_opcode ("fmuld");
15759 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15761 int is_neg
= (inst
.instruction
& 0x80) != 0;
15762 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15764 if (rs
== NS_FF
|| rs
== NS_HH
)
15767 do_vfp_nsyn_opcode ("fnegs");
15769 do_vfp_nsyn_opcode ("fabss");
15771 /* ARMv8.2 fp16 instruction. */
15773 do_scalar_fp16_v82_encode ();
15778 do_vfp_nsyn_opcode ("fnegd");
15780 do_vfp_nsyn_opcode ("fabsd");
15784 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15785 insns belong to Neon, and are handled elsewhere. */
15788 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15790 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15794 do_vfp_nsyn_opcode ("fldmdbs");
15796 do_vfp_nsyn_opcode ("fldmias");
15801 do_vfp_nsyn_opcode ("fstmdbs");
15803 do_vfp_nsyn_opcode ("fstmias");
15808 do_vfp_nsyn_sqrt (void)
15810 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15811 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15813 if (rs
== NS_FF
|| rs
== NS_HH
)
15815 do_vfp_nsyn_opcode ("fsqrts");
15817 /* ARMv8.2 fp16 instruction. */
15819 do_scalar_fp16_v82_encode ();
15822 do_vfp_nsyn_opcode ("fsqrtd");
15826 do_vfp_nsyn_div (void)
15828 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15829 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15830 N_F_ALL
| N_KEY
| N_VFP
);
15832 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15834 do_vfp_nsyn_opcode ("fdivs");
15836 /* ARMv8.2 fp16 instruction. */
15838 do_scalar_fp16_v82_encode ();
15841 do_vfp_nsyn_opcode ("fdivd");
15845 do_vfp_nsyn_nmul (void)
15847 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15848 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15849 N_F_ALL
| N_KEY
| N_VFP
);
15851 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15853 NEON_ENCODE (SINGLE
, inst
);
15854 do_vfp_sp_dyadic ();
15856 /* ARMv8.2 fp16 instruction. */
15858 do_scalar_fp16_v82_encode ();
15862 NEON_ENCODE (DOUBLE
, inst
);
15863 do_vfp_dp_rd_rn_rm ();
15865 do_vfp_cond_or_thumb ();
15869 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15873 neon_logbits (unsigned x
)
15875 return ffs (x
) - 4;
15878 #define LOW4(R) ((R) & 0xf)
15879 #define HI1(R) (((R) >> 4) & 1)
15880 #define LOW1(R) ((R) & 0x1)
15881 #define HI4(R) (((R) >> 1) & 0xf)
15884 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15889 first_error (BAD_EL_TYPE
);
15892 switch (inst
.operands
[0].imm
)
15895 first_error (_("invalid condition"));
15917 /* only accept eq and ne. */
15918 if (inst
.operands
[0].imm
> 1)
15920 first_error (_("invalid condition"));
15923 return inst
.operands
[0].imm
;
15925 if (inst
.operands
[0].imm
== 0x2)
15927 else if (inst
.operands
[0].imm
== 0x8)
15931 first_error (_("invalid condition"));
15935 switch (inst
.operands
[0].imm
)
15938 first_error (_("invalid condition"));
15954 /* Should be unreachable. */
15958 /* For VCTP (create vector tail predicate) in MVE. */
15963 unsigned size
= 0x0;
15965 if (inst
.cond
> COND_ALWAYS
)
15966 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15968 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15970 /* This is a typical MVE instruction which has no type but have size 8, 16,
15971 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15972 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15973 if ((inst
.operands
[0].present
) && (inst
.vectype
.el
[0].type
== NT_untyped
))
15974 dt
= inst
.vectype
.el
[0].size
;
15976 /* Setting this does not indicate an actual NEON instruction, but only
15977 indicates that the mnemonic accepts neon-style type suffixes. */
15991 first_error (_("Type is not allowed for this instruction"));
15993 inst
.instruction
|= size
<< 20;
15994 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16000 /* We are dealing with a vector predicated block. */
16001 if (inst
.operands
[0].present
)
16003 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16004 struct neon_type_el et
16005 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16008 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16010 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16012 if (et
.type
== NT_invtype
)
16015 if (et
.type
== NT_float
)
16017 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16019 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
16020 inst
.instruction
|= (et
.size
== 16) << 28;
16021 inst
.instruction
|= 0x3 << 20;
16025 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
16027 inst
.instruction
|= 1 << 28;
16028 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16031 if (inst
.operands
[2].isquad
)
16033 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16034 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16035 inst
.instruction
|= (fcond
& 0x2) >> 1;
16039 if (inst
.operands
[2].reg
== REG_SP
)
16040 as_tsktsk (MVE_BAD_SP
);
16041 inst
.instruction
|= 1 << 6;
16042 inst
.instruction
|= (fcond
& 0x2) << 4;
16043 inst
.instruction
|= inst
.operands
[2].reg
;
16045 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16046 inst
.instruction
|= (fcond
& 0x4) << 10;
16047 inst
.instruction
|= (fcond
& 0x1) << 7;
16050 set_pred_insn_type (VPT_INSN
);
16052 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
16053 | ((inst
.instruction
& 0xe000) >> 13);
16054 now_pred
.warn_deprecated
= FALSE
;
16055 now_pred
.type
= VECTOR_PRED
;
16062 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
16063 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
16064 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
16065 if (!inst
.operands
[2].present
)
16066 first_error (_("MVE vector or ARM register expected"));
16067 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16069 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
16070 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
16071 && inst
.operands
[1].isquad
)
16073 inst
.instruction
= N_MNEM_vcmp
;
16077 if (inst
.cond
> COND_ALWAYS
)
16078 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16080 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16082 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16083 struct neon_type_el et
16084 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16087 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
16088 && !inst
.operands
[2].iszr
, BAD_PC
);
16090 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16092 inst
.instruction
= 0xee010f00;
16093 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16094 inst
.instruction
|= (fcond
& 0x4) << 10;
16095 inst
.instruction
|= (fcond
& 0x1) << 7;
16096 if (et
.type
== NT_float
)
16098 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16100 inst
.instruction
|= (et
.size
== 16) << 28;
16101 inst
.instruction
|= 0x3 << 20;
16105 inst
.instruction
|= 1 << 28;
16106 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16108 if (inst
.operands
[2].isquad
)
16110 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16111 inst
.instruction
|= (fcond
& 0x2) >> 1;
16112 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16116 if (inst
.operands
[2].reg
== REG_SP
)
16117 as_tsktsk (MVE_BAD_SP
);
16118 inst
.instruction
|= 1 << 6;
16119 inst
.instruction
|= (fcond
& 0x2) << 4;
16120 inst
.instruction
|= inst
.operands
[2].reg
;
16128 do_mve_vmaxa_vmina (void)
16130 if (inst
.cond
> COND_ALWAYS
)
16131 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16133 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16135 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16136 struct neon_type_el et
16137 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
16139 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16140 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16141 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16142 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16143 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16148 do_mve_vfmas (void)
16150 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16151 struct neon_type_el et
16152 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
16154 if (inst
.cond
> COND_ALWAYS
)
16155 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16157 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16159 if (inst
.operands
[2].reg
== REG_SP
)
16160 as_tsktsk (MVE_BAD_SP
);
16161 else if (inst
.operands
[2].reg
== REG_PC
)
16162 as_tsktsk (MVE_BAD_PC
);
16164 inst
.instruction
|= (et
.size
== 16) << 28;
16165 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16166 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16167 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16168 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16169 inst
.instruction
|= inst
.operands
[2].reg
;
16174 do_mve_viddup (void)
16176 if (inst
.cond
> COND_ALWAYS
)
16177 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16179 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16181 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
16182 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
16183 _("immediate must be either 1, 2, 4 or 8"));
16185 enum neon_shape rs
;
16186 struct neon_type_el et
;
16188 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
16190 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
16191 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
16196 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
16197 if (inst
.operands
[2].reg
== REG_SP
)
16198 as_tsktsk (MVE_BAD_SP
);
16199 else if (inst
.operands
[2].reg
== REG_PC
)
16200 first_error (BAD_PC
);
16202 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16203 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16204 Rm
= inst
.operands
[2].reg
>> 1;
16206 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16207 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16208 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16209 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16210 inst
.instruction
|= (imm
> 2) << 7;
16211 inst
.instruction
|= Rm
<< 1;
16212 inst
.instruction
|= (imm
== 2 || imm
== 8);
16217 do_mve_vmlas (void)
16219 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16220 struct neon_type_el et
16221 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16223 if (inst
.operands
[2].reg
== REG_PC
)
16224 as_tsktsk (MVE_BAD_PC
);
16225 else if (inst
.operands
[2].reg
== REG_SP
)
16226 as_tsktsk (MVE_BAD_SP
);
16228 if (inst
.cond
> COND_ALWAYS
)
16229 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16231 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16233 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16234 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16235 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16236 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16237 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16238 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16239 inst
.instruction
|= inst
.operands
[2].reg
;
16244 do_mve_vshll (void)
16246 struct neon_type_el et
16247 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16249 if (inst
.cond
> COND_ALWAYS
)
16250 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16252 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16254 int imm
= inst
.operands
[2].imm
;
16255 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16256 _("immediate value out of range"));
16258 if ((unsigned)imm
== et
.size
)
16260 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16261 inst
.instruction
|= 0x110001;
16265 inst
.instruction
|= (et
.size
+ imm
) << 16;
16266 inst
.instruction
|= 0x800140;
16269 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16270 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16271 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16272 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16273 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16278 do_mve_vshlc (void)
16280 if (inst
.cond
> COND_ALWAYS
)
16281 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16283 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16285 if (inst
.operands
[1].reg
== REG_PC
)
16286 as_tsktsk (MVE_BAD_PC
);
16287 else if (inst
.operands
[1].reg
== REG_SP
)
16288 as_tsktsk (MVE_BAD_SP
);
16290 int imm
= inst
.operands
[2].imm
;
16291 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16293 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16294 inst
.instruction
|= (imm
& 0x1f) << 16;
16295 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16296 inst
.instruction
|= inst
.operands
[1].reg
;
16301 do_mve_vshrn (void)
16304 switch (inst
.instruction
)
16306 case M_MNEM_vshrnt
:
16307 case M_MNEM_vshrnb
:
16308 case M_MNEM_vrshrnt
:
16309 case M_MNEM_vrshrnb
:
16310 types
= N_I16
| N_I32
;
16312 case M_MNEM_vqshrnt
:
16313 case M_MNEM_vqshrnb
:
16314 case M_MNEM_vqrshrnt
:
16315 case M_MNEM_vqrshrnb
:
16316 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16318 case M_MNEM_vqshrunt
:
16319 case M_MNEM_vqshrunb
:
16320 case M_MNEM_vqrshrunt
:
16321 case M_MNEM_vqrshrunb
:
16322 types
= N_S16
| N_S32
;
16328 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16330 if (inst
.cond
> COND_ALWAYS
)
16331 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16333 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16335 unsigned Qd
= inst
.operands
[0].reg
;
16336 unsigned Qm
= inst
.operands
[1].reg
;
16337 unsigned imm
= inst
.operands
[2].imm
;
16338 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16340 ? _("immediate operand expected in the range [1,8]")
16341 : _("immediate operand expected in the range [1,16]"));
16343 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16344 inst
.instruction
|= HI1 (Qd
) << 22;
16345 inst
.instruction
|= (et
.size
- imm
) << 16;
16346 inst
.instruction
|= LOW4 (Qd
) << 12;
16347 inst
.instruction
|= HI1 (Qm
) << 5;
16348 inst
.instruction
|= LOW4 (Qm
);
16353 do_mve_vqmovn (void)
16355 struct neon_type_el et
;
16356 if (inst
.instruction
== M_MNEM_vqmovnt
16357 || inst
.instruction
== M_MNEM_vqmovnb
)
16358 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16359 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16361 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16363 if (inst
.cond
> COND_ALWAYS
)
16364 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16366 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16368 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16369 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16370 inst
.instruction
|= (et
.size
== 32) << 18;
16371 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16372 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16373 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16378 do_mve_vpsel (void)
16380 neon_select_shape (NS_QQQ
, NS_NULL
);
16382 if (inst
.cond
> COND_ALWAYS
)
16383 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16385 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16387 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16388 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16389 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16390 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16391 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16392 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16397 do_mve_vpnot (void)
16399 if (inst
.cond
> COND_ALWAYS
)
16400 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16402 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16406 do_mve_vmaxnma_vminnma (void)
16408 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16409 struct neon_type_el et
16410 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16412 if (inst
.cond
> COND_ALWAYS
)
16413 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16415 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16417 inst
.instruction
|= (et
.size
== 16) << 28;
16418 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16419 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16420 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16421 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16426 do_mve_vcmul (void)
16428 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16429 struct neon_type_el et
16430 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16432 if (inst
.cond
> COND_ALWAYS
)
16433 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16435 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16437 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16438 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16439 _("immediate out of range"));
16441 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16442 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16443 as_tsktsk (BAD_MVE_SRCDEST
);
16445 inst
.instruction
|= (et
.size
== 32) << 28;
16446 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16447 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16448 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16449 inst
.instruction
|= (rot
> 90) << 12;
16450 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16451 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16452 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16453 inst
.instruction
|= (rot
== 90 || rot
== 270);
16457 /* To handle the Low Overhead Loop instructions
16458 in Armv8.1-M Mainline and MVE. */
16462 unsigned long insn
= inst
.instruction
;
16464 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16466 if (insn
== T_MNEM_lctp
)
16469 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16471 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16473 struct neon_type_el et
16474 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16475 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16482 constraint (!inst
.operands
[0].present
,
16484 /* fall through. */
16487 if (!inst
.operands
[0].present
)
16488 inst
.instruction
|= 1 << 21;
16490 v8_1_loop_reloc (TRUE
);
16495 v8_1_loop_reloc (FALSE
);
16496 /* fall through. */
16499 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16501 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16502 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16503 else if (inst
.operands
[1].reg
== REG_PC
)
16504 as_tsktsk (MVE_BAD_PC
);
16505 if (inst
.operands
[1].reg
== REG_SP
)
16506 as_tsktsk (MVE_BAD_SP
);
16508 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16518 do_vfp_nsyn_cmp (void)
16520 enum neon_shape rs
;
16521 if (!inst
.operands
[0].isreg
)
16528 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16529 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16533 if (inst
.operands
[1].isreg
)
16535 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16536 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16538 if (rs
== NS_FF
|| rs
== NS_HH
)
16540 NEON_ENCODE (SINGLE
, inst
);
16541 do_vfp_sp_monadic ();
16545 NEON_ENCODE (DOUBLE
, inst
);
16546 do_vfp_dp_rd_rm ();
16551 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16552 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16554 switch (inst
.instruction
& 0x0fffffff)
16557 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16560 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16566 if (rs
== NS_FI
|| rs
== NS_HI
)
16568 NEON_ENCODE (SINGLE
, inst
);
16569 do_vfp_sp_compare_z ();
16573 NEON_ENCODE (DOUBLE
, inst
);
16577 do_vfp_cond_or_thumb ();
16579 /* ARMv8.2 fp16 instruction. */
16580 if (rs
== NS_HI
|| rs
== NS_HH
)
16581 do_scalar_fp16_v82_encode ();
16585 nsyn_insert_sp (void)
16587 inst
.operands
[1] = inst
.operands
[0];
16588 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16589 inst
.operands
[0].reg
= REG_SP
;
16590 inst
.operands
[0].isreg
= 1;
16591 inst
.operands
[0].writeback
= 1;
16592 inst
.operands
[0].present
= 1;
16595 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16596 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16599 neon_dp_fixup (struct arm_it
* insn
)
16601 unsigned int i
= insn
->instruction
;
16606 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16617 insn
->instruction
= i
;
16621 mve_encode_qqr (int size
, int U
, int fp
)
16623 if (inst
.operands
[2].reg
== REG_SP
)
16624 as_tsktsk (MVE_BAD_SP
);
16625 else if (inst
.operands
[2].reg
== REG_PC
)
16626 as_tsktsk (MVE_BAD_PC
);
16631 if (((unsigned)inst
.instruction
) == 0xd00)
16632 inst
.instruction
= 0xee300f40;
16634 else if (((unsigned)inst
.instruction
) == 0x200d00)
16635 inst
.instruction
= 0xee301f40;
16637 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16638 inst
.instruction
= 0xee310e60;
16640 /* Setting size which is 1 for F16 and 0 for F32. */
16641 inst
.instruction
|= (size
== 16) << 28;
16646 if (((unsigned)inst
.instruction
) == 0x800)
16647 inst
.instruction
= 0xee010f40;
16649 else if (((unsigned)inst
.instruction
) == 0x1000800)
16650 inst
.instruction
= 0xee011f40;
16652 else if (((unsigned)inst
.instruction
) == 0)
16653 inst
.instruction
= 0xee000f40;
16655 else if (((unsigned)inst
.instruction
) == 0x200)
16656 inst
.instruction
= 0xee001f40;
16658 else if (((unsigned)inst
.instruction
) == 0x900)
16659 inst
.instruction
= 0xee010e40;
16661 else if (((unsigned)inst
.instruction
) == 0x910)
16662 inst
.instruction
= 0xee011e60;
16664 else if (((unsigned)inst
.instruction
) == 0x10)
16665 inst
.instruction
= 0xee000f60;
16667 else if (((unsigned)inst
.instruction
) == 0x210)
16668 inst
.instruction
= 0xee001f60;
16670 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16671 inst
.instruction
= 0xee000e40;
16673 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16674 inst
.instruction
= 0xee010e60;
16676 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16677 inst
.instruction
= 0xfe010e60;
16680 inst
.instruction
|= U
<< 28;
16682 /* Setting bits for size. */
16683 inst
.instruction
|= neon_logbits (size
) << 20;
16685 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16686 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16687 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16688 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16689 inst
.instruction
|= inst
.operands
[2].reg
;
16694 mve_encode_rqq (unsigned bit28
, unsigned size
)
16696 inst
.instruction
|= bit28
<< 28;
16697 inst
.instruction
|= neon_logbits (size
) << 20;
16698 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16699 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16700 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16701 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16702 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16707 mve_encode_qqq (int ubit
, int size
)
16710 inst
.instruction
|= (ubit
!= 0) << 28;
16711 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16712 inst
.instruction
|= neon_logbits (size
) << 20;
16713 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16714 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16715 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16716 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16717 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16723 mve_encode_rq (unsigned bit28
, unsigned size
)
16725 inst
.instruction
|= bit28
<< 28;
16726 inst
.instruction
|= neon_logbits (size
) << 18;
16727 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16728 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16733 mve_encode_rrqq (unsigned U
, unsigned size
)
16735 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16737 inst
.instruction
|= U
<< 28;
16738 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16739 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16740 inst
.instruction
|= (size
== 32) << 16;
16741 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16742 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16743 inst
.instruction
|= inst
.operands
[3].reg
;
16747 /* Helper function for neon_three_same handling the operands. */
16749 neon_three_args (int isquad
)
16751 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16752 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16753 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16754 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16755 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16756 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16757 inst
.instruction
|= (isquad
!= 0) << 6;
16761 /* Encode insns with bit pattern:
16763 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16764 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16766 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16767 different meaning for some instruction. */
16770 neon_three_same (int isquad
, int ubit
, int size
)
16772 neon_three_args (isquad
);
16773 inst
.instruction
|= (ubit
!= 0) << 24;
16775 inst
.instruction
|= neon_logbits (size
) << 20;
16777 neon_dp_fixup (&inst
);
16780 /* Encode instructions of the form:
16782 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16783 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16785 Don't write size if SIZE == -1. */
16788 neon_two_same (int qbit
, int ubit
, int size
)
16790 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16791 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16792 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16793 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16794 inst
.instruction
|= (qbit
!= 0) << 6;
16795 inst
.instruction
|= (ubit
!= 0) << 24;
16798 inst
.instruction
|= neon_logbits (size
) << 18;
16800 neon_dp_fixup (&inst
);
16803 enum vfp_or_neon_is_neon_bits
16806 NEON_CHECK_ARCH
= 2,
16807 NEON_CHECK_ARCH8
= 4
16810 /* Call this function if an instruction which may have belonged to the VFP or
16811 Neon instruction sets, but turned out to be a Neon instruction (due to the
16812 operand types involved, etc.). We have to check and/or fix-up a couple of
16815 - Make sure the user hasn't attempted to make a Neon instruction
16817 - Alter the value in the condition code field if necessary.
16818 - Make sure that the arch supports Neon instructions.
16820 Which of these operations take place depends on bits from enum
16821 vfp_or_neon_is_neon_bits.
16823 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16824 current instruction's condition is COND_ALWAYS, the condition field is
16825 changed to inst.uncond_value. This is necessary because instructions shared
16826 between VFP and Neon may be conditional for the VFP variants only, and the
16827 unconditional Neon version must have, e.g., 0xF in the condition field. */
16830 vfp_or_neon_is_neon (unsigned check
)
16832 /* Conditions are always legal in Thumb mode (IT blocks). */
16833 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16835 if (inst
.cond
!= COND_ALWAYS
)
16837 first_error (_(BAD_COND
));
16840 if (inst
.uncond_value
!= -1)
16841 inst
.instruction
|= inst
.uncond_value
<< 28;
16845 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16846 || ((check
& NEON_CHECK_ARCH8
)
16847 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16849 first_error (_(BAD_FPU
));
16857 /* Return TRUE if the SIMD instruction is available for the current
16858 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16859 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16860 vfp_or_neon_is_neon for the NEON specific checks. */
16863 check_simd_pred_availability (int fp
, unsigned check
)
16865 if (inst
.cond
> COND_ALWAYS
)
16867 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16869 inst
.error
= BAD_FPU
;
16872 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16874 else if (inst
.cond
< COND_ALWAYS
)
16876 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16877 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16878 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16883 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16884 && vfp_or_neon_is_neon (check
) == FAIL
)
16887 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16888 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16893 /* Neon instruction encoders, in approximate order of appearance. */
16896 do_neon_dyadic_i_su (void)
16898 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16901 enum neon_shape rs
;
16902 struct neon_type_el et
;
16903 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16904 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16906 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16908 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16912 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16914 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16918 do_neon_dyadic_i64_su (void)
16920 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16922 enum neon_shape rs
;
16923 struct neon_type_el et
;
16924 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16926 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16927 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16931 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16932 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16935 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16937 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16941 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16944 unsigned size
= et
.size
>> 3;
16945 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16946 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16947 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16948 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16949 inst
.instruction
|= (isquad
!= 0) << 6;
16950 inst
.instruction
|= immbits
<< 16;
16951 inst
.instruction
|= (size
>> 3) << 7;
16952 inst
.instruction
|= (size
& 0x7) << 19;
16954 inst
.instruction
|= (uval
!= 0) << 24;
16956 neon_dp_fixup (&inst
);
16962 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16965 if (!inst
.operands
[2].isreg
)
16967 enum neon_shape rs
;
16968 struct neon_type_el et
;
16969 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16971 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16972 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16976 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16977 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16979 int imm
= inst
.operands
[2].imm
;
16981 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16982 _("immediate out of range for shift"));
16983 NEON_ENCODE (IMMED
, inst
);
16984 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16988 enum neon_shape rs
;
16989 struct neon_type_el et
;
16990 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16992 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16993 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16997 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16998 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17004 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17005 _("invalid instruction shape"));
17006 if (inst
.operands
[2].reg
== REG_SP
)
17007 as_tsktsk (MVE_BAD_SP
);
17008 else if (inst
.operands
[2].reg
== REG_PC
)
17009 as_tsktsk (MVE_BAD_PC
);
17011 inst
.instruction
= 0xee311e60;
17012 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17013 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17014 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17015 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17016 inst
.instruction
|= inst
.operands
[2].reg
;
17023 /* VSHL/VQSHL 3-register variants have syntax such as:
17025 whereas other 3-register operations encoded by neon_three_same have
17028 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
17029 operands[2].reg here. */
17030 tmp
= inst
.operands
[2].reg
;
17031 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17032 inst
.operands
[1].reg
= tmp
;
17033 NEON_ENCODE (INTEGER
, inst
);
17034 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17040 do_neon_qshl (void)
17042 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17045 if (!inst
.operands
[2].isreg
)
17047 enum neon_shape rs
;
17048 struct neon_type_el et
;
17049 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17051 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
17052 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
17056 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17057 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
17059 int imm
= inst
.operands
[2].imm
;
17061 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17062 _("immediate out of range for shift"));
17063 NEON_ENCODE (IMMED
, inst
);
17064 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
17068 enum neon_shape rs
;
17069 struct neon_type_el et
;
17071 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17073 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17074 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
17078 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17079 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17084 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17085 _("invalid instruction shape"));
17086 if (inst
.operands
[2].reg
== REG_SP
)
17087 as_tsktsk (MVE_BAD_SP
);
17088 else if (inst
.operands
[2].reg
== REG_PC
)
17089 as_tsktsk (MVE_BAD_PC
);
17091 inst
.instruction
= 0xee311ee0;
17092 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17093 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17094 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17095 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17096 inst
.instruction
|= inst
.operands
[2].reg
;
17103 /* See note in do_neon_shl. */
17104 tmp
= inst
.operands
[2].reg
;
17105 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17106 inst
.operands
[1].reg
= tmp
;
17107 NEON_ENCODE (INTEGER
, inst
);
17108 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17114 do_neon_rshl (void)
17116 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17119 enum neon_shape rs
;
17120 struct neon_type_el et
;
17121 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17123 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17124 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17128 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17129 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
17136 if (inst
.operands
[2].reg
== REG_PC
)
17137 as_tsktsk (MVE_BAD_PC
);
17138 else if (inst
.operands
[2].reg
== REG_SP
)
17139 as_tsktsk (MVE_BAD_SP
);
17141 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17142 _("invalid instruction shape"));
17144 if (inst
.instruction
== 0x0000510)
17145 /* We are dealing with vqrshl. */
17146 inst
.instruction
= 0xee331ee0;
17148 /* We are dealing with vrshl. */
17149 inst
.instruction
= 0xee331e60;
17151 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17152 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17153 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17154 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17155 inst
.instruction
|= inst
.operands
[2].reg
;
17160 tmp
= inst
.operands
[2].reg
;
17161 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17162 inst
.operands
[1].reg
= tmp
;
17163 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17168 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
17170 /* Handle .I8 pseudo-instructions. */
17173 /* Unfortunately, this will make everything apart from zero out-of-range.
17174 FIXME is this the intended semantics? There doesn't seem much point in
17175 accepting .I8 if so. */
17176 immediate
|= immediate
<< 8;
17182 if (immediate
== (immediate
& 0x000000ff))
17184 *immbits
= immediate
;
17187 else if (immediate
== (immediate
& 0x0000ff00))
17189 *immbits
= immediate
>> 8;
17192 else if (immediate
== (immediate
& 0x00ff0000))
17194 *immbits
= immediate
>> 16;
17197 else if (immediate
== (immediate
& 0xff000000))
17199 *immbits
= immediate
>> 24;
17202 if ((immediate
& 0xffff) != (immediate
>> 16))
17203 goto bad_immediate
;
17204 immediate
&= 0xffff;
17207 if (immediate
== (immediate
& 0x000000ff))
17209 *immbits
= immediate
;
17212 else if (immediate
== (immediate
& 0x0000ff00))
17214 *immbits
= immediate
>> 8;
17219 first_error (_("immediate value out of range"));
17224 do_neon_logic (void)
17226 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17228 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17230 && !check_simd_pred_availability (FALSE
,
17231 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17233 else if (rs
!= NS_QQQ
17234 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17235 first_error (BAD_FPU
);
17237 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17238 /* U bit and size field were set as part of the bitmask. */
17239 NEON_ENCODE (INTEGER
, inst
);
17240 neon_three_same (neon_quad (rs
), 0, -1);
17244 const int three_ops_form
= (inst
.operands
[2].present
17245 && !inst
.operands
[2].isreg
);
17246 const int immoperand
= (three_ops_form
? 2 : 1);
17247 enum neon_shape rs
= (three_ops_form
17248 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17249 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17250 /* Because neon_select_shape makes the second operand a copy of the first
17251 if the second operand is not present. */
17253 && !check_simd_pred_availability (FALSE
,
17254 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17256 else if (rs
!= NS_QQI
17257 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17258 first_error (BAD_FPU
);
17260 struct neon_type_el et
;
17261 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17262 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17264 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17267 if (et
.type
== NT_invtype
)
17269 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17274 if (three_ops_form
)
17275 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17276 _("first and second operands shall be the same register"));
17278 NEON_ENCODE (IMMED
, inst
);
17280 immbits
= inst
.operands
[immoperand
].imm
;
17283 /* .i64 is a pseudo-op, so the immediate must be a repeating
17285 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17286 inst
.operands
[immoperand
].reg
: 0))
17288 /* Set immbits to an invalid constant. */
17289 immbits
= 0xdeadbeef;
17296 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17300 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17304 /* Pseudo-instruction for VBIC. */
17305 neon_invert_size (&immbits
, 0, et
.size
);
17306 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17310 /* Pseudo-instruction for VORR. */
17311 neon_invert_size (&immbits
, 0, et
.size
);
17312 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17322 inst
.instruction
|= neon_quad (rs
) << 6;
17323 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17324 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17325 inst
.instruction
|= cmode
<< 8;
17326 neon_write_immbits (immbits
);
17328 neon_dp_fixup (&inst
);
17333 do_neon_bitfield (void)
17335 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17336 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17337 neon_three_same (neon_quad (rs
), 0, -1);
17341 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17344 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17345 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17347 if (et
.type
== NT_float
)
17349 NEON_ENCODE (FLOAT
, inst
);
17351 mve_encode_qqr (et
.size
, 0, 1);
17353 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17357 NEON_ENCODE (INTEGER
, inst
);
17359 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17361 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17367 do_neon_dyadic_if_su_d (void)
17369 /* This version only allow D registers, but that constraint is enforced during
17370 operand parsing so we don't need to do anything extra here. */
17371 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17375 do_neon_dyadic_if_i_d (void)
17377 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17378 affected if we specify unsigned args. */
17379 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17383 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17385 constraint (size
< 32, BAD_ADDR_MODE
);
17386 constraint (size
!= elsize
, BAD_EL_TYPE
);
17387 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17388 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17389 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17390 _("destination register and offset register may not be the"
17393 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17400 constraint ((imm
% (size
/ 8) != 0)
17401 || imm
> (0x7f << neon_logbits (size
)),
17402 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17403 " range of +/-[0,508]")
17404 : _("immediate must be a multiple of 8 in the"
17405 " range of +/-[0,1016]"));
17406 inst
.instruction
|= 0x11 << 24;
17407 inst
.instruction
|= add
<< 23;
17408 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17409 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17410 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17411 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17412 inst
.instruction
|= 1 << 12;
17413 inst
.instruction
|= (size
== 64) << 8;
17414 inst
.instruction
&= 0xffffff00;
17415 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17416 inst
.instruction
|= imm
>> neon_logbits (size
);
17420 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17422 unsigned os
= inst
.operands
[1].imm
>> 5;
17423 unsigned type
= inst
.vectype
.el
[0].type
;
17424 constraint (os
!= 0 && size
== 8,
17425 _("can not shift offsets when accessing less than half-word"));
17426 constraint (os
&& os
!= neon_logbits (size
),
17427 _("shift immediate must be 1, 2 or 3 for half-word, word"
17428 " or double-word accesses respectively"));
17429 if (inst
.operands
[1].reg
== REG_PC
)
17430 as_tsktsk (MVE_BAD_PC
);
17435 constraint (elsize
>= 64, BAD_EL_TYPE
);
17438 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17442 constraint (elsize
!= size
, BAD_EL_TYPE
);
17447 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17451 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17452 _("destination register and offset register may not be"
17454 constraint (size
== elsize
&& type
== NT_signed
, BAD_EL_TYPE
);
17455 constraint (size
!= elsize
&& type
!= NT_unsigned
&& type
!= NT_signed
,
17457 inst
.instruction
|= ((size
== elsize
) || (type
== NT_unsigned
)) << 28;
17461 constraint (type
!= NT_untyped
, BAD_EL_TYPE
);
17464 inst
.instruction
|= 1 << 23;
17465 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17466 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17467 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17468 inst
.instruction
|= neon_logbits (elsize
) << 7;
17469 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17470 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17471 inst
.instruction
|= !!os
;
17475 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17477 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17479 constraint (size
>= 64, BAD_ADDR_MODE
);
17483 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17486 constraint (elsize
!= size
, BAD_EL_TYPE
);
17493 constraint (elsize
!= size
&& type
!= NT_unsigned
17494 && type
!= NT_signed
, BAD_EL_TYPE
);
17498 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17501 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17509 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17514 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17517 constraint (1, _("immediate must be a multiple of 2 in the"
17518 " range of +/-[0,254]"));
17521 constraint (1, _("immediate must be a multiple of 4 in the"
17522 " range of +/-[0,508]"));
17527 if (size
!= elsize
)
17529 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17530 constraint (inst
.operands
[0].reg
> 14,
17531 _("MVE vector register in the range [Q0..Q7] expected"));
17532 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17533 inst
.instruction
|= (size
== 16) << 19;
17534 inst
.instruction
|= neon_logbits (elsize
) << 7;
17538 if (inst
.operands
[1].reg
== REG_PC
)
17539 as_tsktsk (MVE_BAD_PC
);
17540 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17541 as_tsktsk (MVE_BAD_SP
);
17542 inst
.instruction
|= 1 << 12;
17543 inst
.instruction
|= neon_logbits (size
) << 7;
17545 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17546 inst
.instruction
|= add
<< 23;
17547 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17548 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17549 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17550 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17551 inst
.instruction
&= 0xffffff80;
17552 inst
.instruction
|= imm
>> neon_logbits (size
);
17557 do_mve_vstr_vldr (void)
17562 if (inst
.cond
> COND_ALWAYS
)
17563 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17565 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17567 switch (inst
.instruction
)
17574 /* fall through. */
17580 /* fall through. */
17586 /* fall through. */
17592 /* fall through. */
17597 unsigned elsize
= inst
.vectype
.el
[0].size
;
17599 if (inst
.operands
[1].isquad
)
17601 /* We are dealing with [Q, imm]{!} cases. */
17602 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17606 if (inst
.operands
[1].immisreg
== 2)
17608 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17609 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17611 else if (!inst
.operands
[1].immisreg
)
17613 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17614 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17617 constraint (1, BAD_ADDR_MODE
);
17624 do_mve_vst_vld (void)
17626 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17629 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17630 || inst
.relocs
[0].exp
.X_add_number
!= 0
17631 || inst
.operands
[1].immisreg
!= 0,
17633 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17634 if (inst
.operands
[1].reg
== REG_PC
)
17635 as_tsktsk (MVE_BAD_PC
);
17636 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17637 as_tsktsk (MVE_BAD_SP
);
17640 /* These instructions are one of the "exceptions" mentioned in
17641 handle_pred_state. They are MVE instructions that are not VPT compatible
17642 and do not accept a VPT code, thus appending such a code is a syntax
17644 if (inst
.cond
> COND_ALWAYS
)
17645 first_error (BAD_SYNTAX
);
17646 /* If we append a scalar condition code we can set this to
17647 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17648 else if (inst
.cond
< COND_ALWAYS
)
17649 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17651 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17653 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17654 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17655 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17656 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17657 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17662 do_mve_vaddlv (void)
17664 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17665 struct neon_type_el et
17666 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17668 if (et
.type
== NT_invtype
)
17669 first_error (BAD_EL_TYPE
);
17671 if (inst
.cond
> COND_ALWAYS
)
17672 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17674 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17676 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17678 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17679 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17680 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17681 inst
.instruction
|= inst
.operands
[2].reg
;
17686 do_neon_dyadic_if_su (void)
17688 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17689 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17692 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17693 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17694 && et
.type
== NT_float
17695 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17697 if (!check_simd_pred_availability (et
.type
== NT_float
,
17698 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17701 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17705 do_neon_addsub_if_i (void)
17707 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17708 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17711 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17712 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17713 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17715 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17716 /* If we are parsing Q registers and the element types match MVE, which NEON
17717 also supports, then we must check whether this is an instruction that can
17718 be used by both MVE/NEON. This distinction can be made based on whether
17719 they are predicated or not. */
17720 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17722 if (!check_simd_pred_availability (et
.type
== NT_float
,
17723 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17728 /* If they are either in a D register or are using an unsupported. */
17730 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17734 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17735 affected if we specify unsigned args. */
17736 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17739 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17741 V<op> A,B (A is operand 0, B is operand 2)
17746 so handle that case specially. */
17749 neon_exchange_operands (void)
17751 if (inst
.operands
[1].present
)
17753 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17755 /* Swap operands[1] and operands[2]. */
17756 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17757 inst
.operands
[1] = inst
.operands
[2];
17758 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17763 inst
.operands
[1] = inst
.operands
[2];
17764 inst
.operands
[2] = inst
.operands
[0];
17769 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17771 if (inst
.operands
[2].isreg
)
17774 neon_exchange_operands ();
17775 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17779 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17780 struct neon_type_el et
= neon_check_type (2, rs
,
17781 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17783 NEON_ENCODE (IMMED
, inst
);
17784 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17785 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17786 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17787 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17788 inst
.instruction
|= neon_quad (rs
) << 6;
17789 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17790 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17792 neon_dp_fixup (&inst
);
17799 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17803 do_neon_cmp_inv (void)
17805 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17811 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17814 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17815 scalars, which are encoded in 5 bits, M : Rm.
17816 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17817 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17820 Dot Product instructions are similar to multiply instructions except elsize
17821 should always be 32.
17823 This function translates SCALAR, which is GAS's internal encoding of indexed
17824 scalar register, to raw encoding. There is also register and index range
17825 check based on ELSIZE. */
17828 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17830 unsigned regno
= NEON_SCALAR_REG (scalar
);
17831 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17836 if (regno
> 7 || elno
> 3)
17838 return regno
| (elno
<< 3);
17841 if (regno
> 15 || elno
> 1)
17843 return regno
| (elno
<< 4);
17847 first_error (_("scalar out of range for multiply instruction"));
17853 /* Encode multiply / multiply-accumulate scalar instructions. */
17856 neon_mul_mac (struct neon_type_el et
, int ubit
)
17860 /* Give a more helpful error message if we have an invalid type. */
17861 if (et
.type
== NT_invtype
)
17864 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17865 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17866 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17867 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17868 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17869 inst
.instruction
|= LOW4 (scalar
);
17870 inst
.instruction
|= HI1 (scalar
) << 5;
17871 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17872 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17873 inst
.instruction
|= (ubit
!= 0) << 24;
17875 neon_dp_fixup (&inst
);
17879 do_neon_mac_maybe_scalar (void)
17881 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17884 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17887 if (inst
.operands
[2].isscalar
)
17889 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17890 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17891 struct neon_type_el et
= neon_check_type (3, rs
,
17892 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17893 NEON_ENCODE (SCALAR
, inst
);
17894 neon_mul_mac (et
, neon_quad (rs
));
17896 else if (!inst
.operands
[2].isvec
)
17898 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17900 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17901 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17903 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17907 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17908 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17909 affected if we specify unsigned args. */
17910 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17915 do_bfloat_vfma (void)
17917 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
17918 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
17919 enum neon_shape rs
;
17922 if (inst
.instruction
!= B_MNEM_vfmab
)
17925 inst
.instruction
= B_MNEM_vfmat
;
17928 if (inst
.operands
[2].isscalar
)
17930 rs
= neon_select_shape (NS_QQS
, NS_NULL
);
17931 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17933 inst
.instruction
|= (1 << 25);
17934 int index
= inst
.operands
[2].reg
& 0xf;
17935 constraint (!(index
< 4), _("index must be in the range 0 to 3"));
17936 inst
.operands
[2].reg
>>= 4;
17937 constraint (!(inst
.operands
[2].reg
< 8),
17938 _("indexed register must be less than 8"));
17939 neon_three_args (t_bit
);
17940 inst
.instruction
|= ((index
& 1) << 3);
17941 inst
.instruction
|= ((index
& 2) << 4);
17945 rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17946 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17947 neon_three_args (t_bit
);
17953 do_neon_fmac (void)
17955 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17956 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17959 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17962 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17964 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17965 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17971 if (inst
.operands
[2].reg
== REG_SP
)
17972 as_tsktsk (MVE_BAD_SP
);
17973 else if (inst
.operands
[2].reg
== REG_PC
)
17974 as_tsktsk (MVE_BAD_PC
);
17976 inst
.instruction
= 0xee310e40;
17977 inst
.instruction
|= (et
.size
== 16) << 28;
17978 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17979 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17980 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17981 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17982 inst
.instruction
|= inst
.operands
[2].reg
;
17989 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17992 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17998 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_bf16
) &&
17999 inst
.cond
== COND_ALWAYS
)
18001 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18002 inst
.instruction
= N_MNEM_vfma
;
18003 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18005 return do_neon_fmac();
18016 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18017 struct neon_type_el et
= neon_check_type (3, rs
,
18018 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18019 neon_three_same (neon_quad (rs
), 0, et
.size
);
18022 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
18023 same types as the MAC equivalents. The polynomial type for this instruction
18024 is encoded the same as the integer type. */
18029 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
18032 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18035 if (inst
.operands
[2].isscalar
)
18037 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18038 do_neon_mac_maybe_scalar ();
18042 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18044 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18045 struct neon_type_el et
18046 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
18047 if (et
.type
== NT_float
)
18048 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
18051 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
18055 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
18056 neon_dyadic_misc (NT_poly
,
18057 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
18063 do_neon_qdmulh (void)
18065 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18068 if (inst
.operands
[2].isscalar
)
18070 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18071 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18072 struct neon_type_el et
= neon_check_type (3, rs
,
18073 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18074 NEON_ENCODE (SCALAR
, inst
);
18075 neon_mul_mac (et
, neon_quad (rs
));
18079 enum neon_shape rs
;
18080 struct neon_type_el et
;
18081 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18083 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18084 et
= neon_check_type (3, rs
,
18085 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18089 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18090 et
= neon_check_type (3, rs
,
18091 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18094 NEON_ENCODE (INTEGER
, inst
);
18096 mve_encode_qqr (et
.size
, 0, 0);
18098 /* The U bit (rounding) comes from bit mask. */
18099 neon_three_same (neon_quad (rs
), 0, et
.size
);
18104 do_mve_vaddv (void)
18106 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18107 struct neon_type_el et
18108 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18110 if (et
.type
== NT_invtype
)
18111 first_error (BAD_EL_TYPE
);
18113 if (inst
.cond
> COND_ALWAYS
)
18114 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18116 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18118 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
18120 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18124 do_mve_vhcadd (void)
18126 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
18127 struct neon_type_el et
18128 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18130 if (inst
.cond
> COND_ALWAYS
)
18131 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18133 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18135 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
18136 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
18138 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
18139 as_tsktsk (_("Warning: 32-bit element size and same first and third "
18140 "operand makes instruction UNPREDICTABLE"));
18142 mve_encode_qqq (0, et
.size
);
18143 inst
.instruction
|= (rot
== 270) << 12;
18148 do_mve_vqdmull (void)
18150 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
18151 struct neon_type_el et
18152 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18155 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18156 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
18157 as_tsktsk (BAD_MVE_SRCDEST
);
18159 if (inst
.cond
> COND_ALWAYS
)
18160 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18162 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18166 mve_encode_qqq (et
.size
== 32, 64);
18167 inst
.instruction
|= 1;
18171 mve_encode_qqr (64, et
.size
== 32, 0);
18172 inst
.instruction
|= 0x3 << 5;
18179 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18180 struct neon_type_el et
18181 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
18183 if (et
.type
== NT_invtype
)
18184 first_error (BAD_EL_TYPE
);
18186 if (inst
.cond
> COND_ALWAYS
)
18187 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18189 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18191 mve_encode_qqq (0, 64);
18195 do_mve_vbrsr (void)
18197 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18198 struct neon_type_el et
18199 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18201 if (inst
.cond
> COND_ALWAYS
)
18202 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18204 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18206 mve_encode_qqr (et
.size
, 0, 0);
18212 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
18214 if (inst
.cond
> COND_ALWAYS
)
18215 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18217 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18219 mve_encode_qqq (1, 64);
18223 do_mve_vmulh (void)
18225 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18226 struct neon_type_el et
18227 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18229 if (inst
.cond
> COND_ALWAYS
)
18230 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18232 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18234 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18238 do_mve_vqdmlah (void)
18240 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18241 struct neon_type_el et
18242 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18244 if (inst
.cond
> COND_ALWAYS
)
18245 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18247 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18249 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18253 do_mve_vqdmladh (void)
18255 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18256 struct neon_type_el et
18257 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18259 if (inst
.cond
> COND_ALWAYS
)
18260 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18262 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18264 mve_encode_qqq (0, et
.size
);
18269 do_mve_vmull (void)
18272 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18273 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18274 if (inst
.cond
== COND_ALWAYS
18275 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18280 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18287 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18288 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18289 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18291 /* We are dealing with MVE's vmullt. */
18293 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18294 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18295 as_tsktsk (BAD_MVE_SRCDEST
);
18297 if (inst
.cond
> COND_ALWAYS
)
18298 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18300 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18302 if (et
.type
== NT_poly
)
18303 mve_encode_qqq (neon_logbits (et
.size
), 64);
18305 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18310 inst
.instruction
= N_MNEM_vmul
;
18313 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18318 do_mve_vabav (void)
18320 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18325 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18328 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18329 | N_S16
| N_S32
| N_U8
| N_U16
18332 if (inst
.cond
> COND_ALWAYS
)
18333 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18335 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18337 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18341 do_mve_vmladav (void)
18343 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18344 struct neon_type_el et
= neon_check_type (3, rs
,
18345 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18347 if (et
.type
== NT_unsigned
18348 && (inst
.instruction
== M_MNEM_vmladavx
18349 || inst
.instruction
== M_MNEM_vmladavax
18350 || inst
.instruction
== M_MNEM_vmlsdav
18351 || inst
.instruction
== M_MNEM_vmlsdava
18352 || inst
.instruction
== M_MNEM_vmlsdavx
18353 || inst
.instruction
== M_MNEM_vmlsdavax
))
18354 first_error (BAD_SIMD_TYPE
);
18356 constraint (inst
.operands
[2].reg
> 14,
18357 _("MVE vector register in the range [Q0..Q7] expected"));
18359 if (inst
.cond
> COND_ALWAYS
)
18360 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18362 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18364 if (inst
.instruction
== M_MNEM_vmlsdav
18365 || inst
.instruction
== M_MNEM_vmlsdava
18366 || inst
.instruction
== M_MNEM_vmlsdavx
18367 || inst
.instruction
== M_MNEM_vmlsdavax
)
18368 inst
.instruction
|= (et
.size
== 8) << 28;
18370 inst
.instruction
|= (et
.size
== 8) << 8;
18372 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18373 inst
.instruction
|= (et
.size
== 32) << 16;
18377 do_mve_vmlaldav (void)
18379 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18380 struct neon_type_el et
18381 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18382 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18384 if (et
.type
== NT_unsigned
18385 && (inst
.instruction
== M_MNEM_vmlsldav
18386 || inst
.instruction
== M_MNEM_vmlsldava
18387 || inst
.instruction
== M_MNEM_vmlsldavx
18388 || inst
.instruction
== M_MNEM_vmlsldavax
))
18389 first_error (BAD_SIMD_TYPE
);
18391 if (inst
.cond
> COND_ALWAYS
)
18392 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18394 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18396 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18400 do_mve_vrmlaldavh (void)
18402 struct neon_type_el et
;
18403 if (inst
.instruction
== M_MNEM_vrmlsldavh
18404 || inst
.instruction
== M_MNEM_vrmlsldavha
18405 || inst
.instruction
== M_MNEM_vrmlsldavhx
18406 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18408 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18409 if (inst
.operands
[1].reg
== REG_SP
)
18410 as_tsktsk (MVE_BAD_SP
);
18414 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18415 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18416 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18418 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18419 N_U32
| N_S32
| N_KEY
);
18420 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18421 with vmax/min instructions, making the use of SP in assembly really
18422 nonsensical, so instead of issuing a warning like we do for other uses
18423 of SP for the odd register operand we error out. */
18424 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18427 /* Make sure we still check the second operand is an odd one and that PC is
18428 disallowed. This because we are parsing for any GPR operand, to be able
18429 to distinguish between giving a warning or an error for SP as described
18431 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18432 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18434 if (inst
.cond
> COND_ALWAYS
)
18435 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18437 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18439 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18444 do_mve_vmaxnmv (void)
18446 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18447 struct neon_type_el et
18448 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18450 if (inst
.cond
> COND_ALWAYS
)
18451 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18453 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18455 if (inst
.operands
[0].reg
== REG_SP
)
18456 as_tsktsk (MVE_BAD_SP
);
18457 else if (inst
.operands
[0].reg
== REG_PC
)
18458 as_tsktsk (MVE_BAD_PC
);
18460 mve_encode_rq (et
.size
== 16, 64);
18464 do_mve_vmaxv (void)
18466 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18467 struct neon_type_el et
;
18469 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18470 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18472 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18474 if (inst
.cond
> COND_ALWAYS
)
18475 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18477 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18479 if (inst
.operands
[0].reg
== REG_SP
)
18480 as_tsktsk (MVE_BAD_SP
);
18481 else if (inst
.operands
[0].reg
== REG_PC
)
18482 as_tsktsk (MVE_BAD_PC
);
18484 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18489 do_neon_qrdmlah (void)
18491 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18493 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18495 /* Check we're on the correct architecture. */
18496 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18498 = _("instruction form not available on this architecture.");
18499 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18501 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18502 record_feature_use (&fpu_neon_ext_v8_1
);
18504 if (inst
.operands
[2].isscalar
)
18506 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18507 struct neon_type_el et
= neon_check_type (3, rs
,
18508 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18509 NEON_ENCODE (SCALAR
, inst
);
18510 neon_mul_mac (et
, neon_quad (rs
));
18514 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18515 struct neon_type_el et
= neon_check_type (3, rs
,
18516 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18517 NEON_ENCODE (INTEGER
, inst
);
18518 /* The U bit (rounding) comes from bit mask. */
18519 neon_three_same (neon_quad (rs
), 0, et
.size
);
18524 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18525 struct neon_type_el et
18526 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18528 NEON_ENCODE (INTEGER
, inst
);
18529 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18534 do_neon_fcmp_absolute (void)
18536 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18537 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18538 N_F_16_32
| N_KEY
);
18539 /* Size field comes from bit mask. */
18540 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18544 do_neon_fcmp_absolute_inv (void)
18546 neon_exchange_operands ();
18547 do_neon_fcmp_absolute ();
18551 do_neon_step (void)
18553 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18554 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18555 N_F_16_32
| N_KEY
);
18556 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18560 do_neon_abs_neg (void)
18562 enum neon_shape rs
;
18563 struct neon_type_el et
;
18565 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18568 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18569 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18571 if (!check_simd_pred_availability (et
.type
== NT_float
,
18572 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18575 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18576 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18577 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18578 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18579 inst
.instruction
|= neon_quad (rs
) << 6;
18580 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18581 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18583 neon_dp_fixup (&inst
);
18589 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18592 enum neon_shape rs
;
18593 struct neon_type_el et
;
18594 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18596 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18597 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18601 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18602 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18606 int imm
= inst
.operands
[2].imm
;
18607 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18608 _("immediate out of range for insert"));
18609 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18615 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18618 enum neon_shape rs
;
18619 struct neon_type_el et
;
18620 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18622 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18623 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18627 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18628 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18631 int imm
= inst
.operands
[2].imm
;
18632 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18633 _("immediate out of range for insert"));
18634 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18638 do_neon_qshlu_imm (void)
18640 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18643 enum neon_shape rs
;
18644 struct neon_type_el et
;
18645 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18647 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18648 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18652 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18653 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18654 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18657 int imm
= inst
.operands
[2].imm
;
18658 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18659 _("immediate out of range for shift"));
18660 /* Only encodes the 'U present' variant of the instruction.
18661 In this case, signed types have OP (bit 8) set to 0.
18662 Unsigned types have OP set to 1. */
18663 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18664 /* The rest of the bits are the same as other immediate shifts. */
18665 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18669 do_neon_qmovn (void)
18671 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18672 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18673 /* Saturating move where operands can be signed or unsigned, and the
18674 destination has the same signedness. */
18675 NEON_ENCODE (INTEGER
, inst
);
18676 if (et
.type
== NT_unsigned
)
18677 inst
.instruction
|= 0xc0;
18679 inst
.instruction
|= 0x80;
18680 neon_two_same (0, 1, et
.size
/ 2);
18684 do_neon_qmovun (void)
18686 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18687 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18688 /* Saturating move with unsigned results. Operands must be signed. */
18689 NEON_ENCODE (INTEGER
, inst
);
18690 neon_two_same (0, 1, et
.size
/ 2);
18694 do_neon_rshift_sat_narrow (void)
18696 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18697 or unsigned. If operands are unsigned, results must also be unsigned. */
18698 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18699 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18700 int imm
= inst
.operands
[2].imm
;
18701 /* This gets the bounds check, size encoding and immediate bits calculation
18705 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18706 VQMOVN.I<size> <Dd>, <Qm>. */
18709 inst
.operands
[2].present
= 0;
18710 inst
.instruction
= N_MNEM_vqmovn
;
18715 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18716 _("immediate out of range"));
18717 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18721 do_neon_rshift_sat_narrow_u (void)
18723 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18724 or unsigned. If operands are unsigned, results must also be unsigned. */
18725 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18726 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18727 int imm
= inst
.operands
[2].imm
;
18728 /* This gets the bounds check, size encoding and immediate bits calculation
18732 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18733 VQMOVUN.I<size> <Dd>, <Qm>. */
18736 inst
.operands
[2].present
= 0;
18737 inst
.instruction
= N_MNEM_vqmovun
;
18742 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18743 _("immediate out of range"));
18744 /* FIXME: The manual is kind of unclear about what value U should have in
18745 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18747 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18751 do_neon_movn (void)
18753 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18754 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18755 NEON_ENCODE (INTEGER
, inst
);
18756 neon_two_same (0, 1, et
.size
/ 2);
18760 do_neon_rshift_narrow (void)
18762 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18763 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18764 int imm
= inst
.operands
[2].imm
;
18765 /* This gets the bounds check, size encoding and immediate bits calculation
18769 /* If immediate is zero then we are a pseudo-instruction for
18770 VMOVN.I<size> <Dd>, <Qm> */
18773 inst
.operands
[2].present
= 0;
18774 inst
.instruction
= N_MNEM_vmovn
;
18779 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18780 _("immediate out of range for narrowing operation"));
18781 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18785 do_neon_shll (void)
18787 /* FIXME: Type checking when lengthening. */
18788 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18789 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18790 unsigned imm
= inst
.operands
[2].imm
;
18792 if (imm
== et
.size
)
18794 /* Maximum shift variant. */
18795 NEON_ENCODE (INTEGER
, inst
);
18796 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18797 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18798 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18799 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18800 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18802 neon_dp_fixup (&inst
);
18806 /* A more-specific type check for non-max versions. */
18807 et
= neon_check_type (2, NS_QDI
,
18808 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18809 NEON_ENCODE (IMMED
, inst
);
18810 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18814 /* Check the various types for the VCVT instruction, and return which version
18815 the current instruction is. */
18817 #define CVT_FLAVOUR_VAR \
18818 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18819 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18820 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18821 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18822 /* Half-precision conversions. */ \
18823 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18824 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18825 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18826 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18827 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18828 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18829 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18830 Compared with single/double precision variants, only the co-processor \
18831 field is different, so the encoding flow is reused here. */ \
18832 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18833 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18834 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18835 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18836 CVT_VAR (bf16_f32, N_BF16, N_F32, whole_reg, NULL, NULL, NULL) \
18837 /* VFP instructions. */ \
18838 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18839 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18840 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18841 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18842 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18843 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18844 /* VFP instructions with bitshift. */ \
18845 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18846 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18847 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18848 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18849 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18850 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18851 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18852 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18854 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18855 neon_cvt_flavour_##C,
18857 /* The different types of conversions we can do. */
18858 enum neon_cvt_flavour
18861 neon_cvt_flavour_invalid
,
18862 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18867 static enum neon_cvt_flavour
18868 get_neon_cvt_flavour (enum neon_shape rs
)
18870 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18871 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18872 if (et.type != NT_invtype) \
18874 inst.error = NULL; \
18875 return (neon_cvt_flavour_##C); \
18878 struct neon_type_el et
;
18879 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18880 || rs
== NS_FF
) ? N_VFP
: 0;
18881 /* The instruction versions which take an immediate take one register
18882 argument, which is extended to the width of the full register. Thus the
18883 "source" and "destination" registers must have the same width. Hack that
18884 here by making the size equal to the key (wider, in this case) operand. */
18885 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18889 return neon_cvt_flavour_invalid
;
18904 /* Neon-syntax VFP conversions. */
18907 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18909 const char *opname
= 0;
18911 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18912 || rs
== NS_FHI
|| rs
== NS_HFI
)
18914 /* Conversions with immediate bitshift. */
18915 const char *enc
[] =
18917 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18923 if (flavour
< (int) ARRAY_SIZE (enc
))
18925 opname
= enc
[flavour
];
18926 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18927 _("operands 0 and 1 must be the same register"));
18928 inst
.operands
[1] = inst
.operands
[2];
18929 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18934 /* Conversions without bitshift. */
18935 const char *enc
[] =
18937 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18943 if (flavour
< (int) ARRAY_SIZE (enc
))
18944 opname
= enc
[flavour
];
18948 do_vfp_nsyn_opcode (opname
);
18950 /* ARMv8.2 fp16 VCVT instruction. */
18951 if (flavour
== neon_cvt_flavour_s32_f16
18952 || flavour
== neon_cvt_flavour_u32_f16
18953 || flavour
== neon_cvt_flavour_f16_u32
18954 || flavour
== neon_cvt_flavour_f16_s32
)
18955 do_scalar_fp16_v82_encode ();
18959 do_vfp_nsyn_cvtz (void)
18961 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18962 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18963 const char *enc
[] =
18965 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18971 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18972 do_vfp_nsyn_opcode (enc
[flavour
]);
18976 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18977 enum neon_cvt_mode mode
)
18982 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18983 D register operands. */
18984 if (flavour
== neon_cvt_flavour_s32_f64
18985 || flavour
== neon_cvt_flavour_u32_f64
)
18986 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18989 if (flavour
== neon_cvt_flavour_s32_f16
18990 || flavour
== neon_cvt_flavour_u32_f16
)
18991 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18994 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18998 case neon_cvt_flavour_s32_f64
:
19002 case neon_cvt_flavour_s32_f32
:
19006 case neon_cvt_flavour_s32_f16
:
19010 case neon_cvt_flavour_u32_f64
:
19014 case neon_cvt_flavour_u32_f32
:
19018 case neon_cvt_flavour_u32_f16
:
19023 first_error (_("invalid instruction shape"));
19029 case neon_cvt_mode_a
: rm
= 0; break;
19030 case neon_cvt_mode_n
: rm
= 1; break;
19031 case neon_cvt_mode_p
: rm
= 2; break;
19032 case neon_cvt_mode_m
: rm
= 3; break;
19033 default: first_error (_("invalid rounding mode")); return;
19036 NEON_ENCODE (FPV8
, inst
);
19037 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
19038 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
19039 inst
.instruction
|= sz
<< 8;
19041 /* ARMv8.2 fp16 VCVT instruction. */
19042 if (flavour
== neon_cvt_flavour_s32_f16
19043 ||flavour
== neon_cvt_flavour_u32_f16
)
19044 do_scalar_fp16_v82_encode ();
19045 inst
.instruction
|= op
<< 7;
19046 inst
.instruction
|= rm
<< 16;
19047 inst
.instruction
|= 0xf0000000;
19048 inst
.is_neon
= TRUE
;
19052 do_neon_cvt_1 (enum neon_cvt_mode mode
)
19054 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
19055 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
19056 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
19058 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19060 if (flavour
== neon_cvt_flavour_invalid
)
19063 /* PR11109: Handle round-to-zero for VCVT conversions. */
19064 if (mode
== neon_cvt_mode_z
19065 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
19066 && (flavour
== neon_cvt_flavour_s16_f16
19067 || flavour
== neon_cvt_flavour_u16_f16
19068 || flavour
== neon_cvt_flavour_s32_f32
19069 || flavour
== neon_cvt_flavour_u32_f32
19070 || flavour
== neon_cvt_flavour_s32_f64
19071 || flavour
== neon_cvt_flavour_u32_f64
)
19072 && (rs
== NS_FD
|| rs
== NS_FF
))
19074 do_vfp_nsyn_cvtz ();
19078 /* ARMv8.2 fp16 VCVT conversions. */
19079 if (mode
== neon_cvt_mode_z
19080 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
19081 && (flavour
== neon_cvt_flavour_s32_f16
19082 || flavour
== neon_cvt_flavour_u32_f16
)
19085 do_vfp_nsyn_cvtz ();
19086 do_scalar_fp16_v82_encode ();
19090 if ((rs
== NS_FD
|| rs
== NS_QQI
) && mode
== neon_cvt_mode_n
19091 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19093 /* We are dealing with vcvt with the 'ne' condition. */
19095 inst
.instruction
= N_MNEM_vcvt
;
19096 do_neon_cvt_1 (neon_cvt_mode_z
);
19100 /* VFP rather than Neon conversions. */
19101 if (flavour
>= neon_cvt_flavour_first_fp
)
19103 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19104 do_vfp_nsyn_cvt (rs
, flavour
);
19106 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19114 if (mode
== neon_cvt_mode_z
19115 && (flavour
== neon_cvt_flavour_f16_s16
19116 || flavour
== neon_cvt_flavour_f16_u16
19117 || flavour
== neon_cvt_flavour_s16_f16
19118 || flavour
== neon_cvt_flavour_u16_f16
19119 || flavour
== neon_cvt_flavour_f32_u32
19120 || flavour
== neon_cvt_flavour_f32_s32
19121 || flavour
== neon_cvt_flavour_s32_f32
19122 || flavour
== neon_cvt_flavour_u32_f32
))
19124 if (!check_simd_pred_availability (TRUE
,
19125 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19128 /* fall through. */
19132 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
19133 0x0000100, 0x1000100, 0x0, 0x1000000};
19135 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19136 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19139 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19141 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
19142 _("immediate value out of range"));
19145 case neon_cvt_flavour_f16_s16
:
19146 case neon_cvt_flavour_f16_u16
:
19147 case neon_cvt_flavour_s16_f16
:
19148 case neon_cvt_flavour_u16_f16
:
19149 constraint (inst
.operands
[2].imm
> 16,
19150 _("immediate value out of range"));
19152 case neon_cvt_flavour_f32_u32
:
19153 case neon_cvt_flavour_f32_s32
:
19154 case neon_cvt_flavour_s32_f32
:
19155 case neon_cvt_flavour_u32_f32
:
19156 constraint (inst
.operands
[2].imm
> 32,
19157 _("immediate value out of range"));
19160 inst
.error
= BAD_FPU
;
19165 /* Fixed-point conversion with #0 immediate is encoded as an
19166 integer conversion. */
19167 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
19169 NEON_ENCODE (IMMED
, inst
);
19170 if (flavour
!= neon_cvt_flavour_invalid
)
19171 inst
.instruction
|= enctab
[flavour
];
19172 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19173 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19174 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19175 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19176 inst
.instruction
|= neon_quad (rs
) << 6;
19177 inst
.instruction
|= 1 << 21;
19178 if (flavour
< neon_cvt_flavour_s16_f16
)
19180 inst
.instruction
|= 1 << 21;
19181 immbits
= 32 - inst
.operands
[2].imm
;
19182 inst
.instruction
|= immbits
<< 16;
19186 inst
.instruction
|= 3 << 20;
19187 immbits
= 16 - inst
.operands
[2].imm
;
19188 inst
.instruction
|= immbits
<< 16;
19189 inst
.instruction
&= ~(1 << 9);
19192 neon_dp_fixup (&inst
);
19197 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19198 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
19199 && (flavour
== neon_cvt_flavour_s16_f16
19200 || flavour
== neon_cvt_flavour_u16_f16
19201 || flavour
== neon_cvt_flavour_s32_f32
19202 || flavour
== neon_cvt_flavour_u32_f32
))
19204 if (!check_simd_pred_availability (TRUE
,
19205 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19208 else if (mode
== neon_cvt_mode_z
19209 && (flavour
== neon_cvt_flavour_f16_s16
19210 || flavour
== neon_cvt_flavour_f16_u16
19211 || flavour
== neon_cvt_flavour_s16_f16
19212 || flavour
== neon_cvt_flavour_u16_f16
19213 || flavour
== neon_cvt_flavour_f32_u32
19214 || flavour
== neon_cvt_flavour_f32_s32
19215 || flavour
== neon_cvt_flavour_s32_f32
19216 || flavour
== neon_cvt_flavour_u32_f32
))
19218 if (!check_simd_pred_availability (TRUE
,
19219 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19222 /* fall through. */
19224 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
19227 NEON_ENCODE (FLOAT
, inst
);
19228 if (!check_simd_pred_availability (TRUE
,
19229 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19232 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19233 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19234 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19235 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19236 inst
.instruction
|= neon_quad (rs
) << 6;
19237 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19238 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19239 inst
.instruction
|= mode
<< 8;
19240 if (flavour
== neon_cvt_flavour_u16_f16
19241 || flavour
== neon_cvt_flavour_s16_f16
)
19242 /* Mask off the original size bits and reencode them. */
19243 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19246 inst
.instruction
|= 0xfc000000;
19248 inst
.instruction
|= 0xf0000000;
19254 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19255 0x100, 0x180, 0x0, 0x080};
19257 NEON_ENCODE (INTEGER
, inst
);
19259 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19261 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19265 if (flavour
!= neon_cvt_flavour_invalid
)
19266 inst
.instruction
|= enctab
[flavour
];
19268 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19269 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19270 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19271 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19272 inst
.instruction
|= neon_quad (rs
) << 6;
19273 if (flavour
>= neon_cvt_flavour_s16_f16
19274 && flavour
<= neon_cvt_flavour_f16_u16
)
19275 /* Half precision. */
19276 inst
.instruction
|= 1 << 18;
19278 inst
.instruction
|= 2 << 18;
19280 neon_dp_fixup (&inst
);
19285 /* Half-precision conversions for Advanced SIMD -- neon. */
19288 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19292 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19294 as_bad (_("operand size must match register width"));
19299 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19301 as_bad (_("operand size must match register width"));
19307 if (flavour
== neon_cvt_flavour_bf16_f32
)
19309 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH8
) == FAIL
)
19311 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19312 /* VCVT.bf16.f32. */
19313 inst
.instruction
= 0x11b60640;
19316 /* VCVT.f16.f32. */
19317 inst
.instruction
= 0x3b60600;
19320 /* VCVT.f32.f16. */
19321 inst
.instruction
= 0x3b60700;
19323 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19324 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19325 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19326 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19327 neon_dp_fixup (&inst
);
19331 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19332 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19333 do_vfp_nsyn_cvt (rs
, flavour
);
19335 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19340 do_neon_cvtr (void)
19342 do_neon_cvt_1 (neon_cvt_mode_x
);
19348 do_neon_cvt_1 (neon_cvt_mode_z
);
19352 do_neon_cvta (void)
19354 do_neon_cvt_1 (neon_cvt_mode_a
);
19358 do_neon_cvtn (void)
19360 do_neon_cvt_1 (neon_cvt_mode_n
);
19364 do_neon_cvtp (void)
19366 do_neon_cvt_1 (neon_cvt_mode_p
);
19370 do_neon_cvtm (void)
19372 do_neon_cvt_1 (neon_cvt_mode_m
);
19376 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19379 mark_feature_used (&fpu_vfp_ext_armv8
);
19381 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19382 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19383 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19384 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19385 inst
.instruction
|= to
? 0x10000 : 0;
19386 inst
.instruction
|= t
? 0x80 : 0;
19387 inst
.instruction
|= is_double
? 0x100 : 0;
19388 do_vfp_cond_or_thumb ();
19392 do_neon_cvttb_1 (bfd_boolean t
)
19394 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19395 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19399 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19401 int single_to_half
= 0;
19402 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19405 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19407 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19408 && (flavour
== neon_cvt_flavour_u16_f16
19409 || flavour
== neon_cvt_flavour_s16_f16
19410 || flavour
== neon_cvt_flavour_f16_s16
19411 || flavour
== neon_cvt_flavour_f16_u16
19412 || flavour
== neon_cvt_flavour_u32_f32
19413 || flavour
== neon_cvt_flavour_s32_f32
19414 || flavour
== neon_cvt_flavour_f32_s32
19415 || flavour
== neon_cvt_flavour_f32_u32
))
19418 inst
.instruction
= N_MNEM_vcvt
;
19419 set_pred_insn_type (INSIDE_VPT_INSN
);
19420 do_neon_cvt_1 (neon_cvt_mode_z
);
19423 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19424 single_to_half
= 1;
19425 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19427 first_error (BAD_FPU
);
19431 inst
.instruction
= 0xee3f0e01;
19432 inst
.instruction
|= single_to_half
<< 28;
19433 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19434 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19435 inst
.instruction
|= t
<< 12;
19436 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19437 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19440 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19443 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19445 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19448 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19450 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19452 /* The VCVTB and VCVTT instructions with D-register operands
19453 don't work for SP only targets. */
19454 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19458 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19460 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19462 /* The VCVTB and VCVTT instructions with D-register operands
19463 don't work for SP only targets. */
19464 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19468 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19470 else if (neon_check_type (2, rs
, N_BF16
| N_VFP
, N_F32
).type
!= NT_invtype
)
19472 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19474 inst
.instruction
|= (1 << 8);
19475 inst
.instruction
&= ~(1 << 9);
19476 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19483 do_neon_cvtb (void)
19485 do_neon_cvttb_1 (FALSE
);
19490 do_neon_cvtt (void)
19492 do_neon_cvttb_1 (TRUE
);
19496 neon_move_immediate (void)
19498 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19499 struct neon_type_el et
= neon_check_type (2, rs
,
19500 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19501 unsigned immlo
, immhi
= 0, immbits
;
19502 int op
, cmode
, float_p
;
19504 constraint (et
.type
== NT_invtype
,
19505 _("operand size must be specified for immediate VMOV"));
19507 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19508 op
= (inst
.instruction
& (1 << 5)) != 0;
19510 immlo
= inst
.operands
[1].imm
;
19511 if (inst
.operands
[1].regisimm
)
19512 immhi
= inst
.operands
[1].reg
;
19514 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19515 _("immediate has bits set outside the operand size"));
19517 float_p
= inst
.operands
[1].immisfloat
;
19519 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19520 et
.size
, et
.type
)) == FAIL
)
19522 /* Invert relevant bits only. */
19523 neon_invert_size (&immlo
, &immhi
, et
.size
);
19524 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19525 with one or the other; those cases are caught by
19526 neon_cmode_for_move_imm. */
19528 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19529 &op
, et
.size
, et
.type
)) == FAIL
)
19531 first_error (_("immediate out of range"));
19536 inst
.instruction
&= ~(1 << 5);
19537 inst
.instruction
|= op
<< 5;
19539 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19540 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19541 inst
.instruction
|= neon_quad (rs
) << 6;
19542 inst
.instruction
|= cmode
<< 8;
19544 neon_write_immbits (immbits
);
19550 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19553 if (inst
.operands
[1].isreg
)
19555 enum neon_shape rs
;
19556 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19557 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19559 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19561 NEON_ENCODE (INTEGER
, inst
);
19562 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19563 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19564 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19565 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19566 inst
.instruction
|= neon_quad (rs
) << 6;
19570 NEON_ENCODE (IMMED
, inst
);
19571 neon_move_immediate ();
19574 neon_dp_fixup (&inst
);
19576 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19578 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19582 /* Encode instructions of form:
19584 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19585 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19588 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19590 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19591 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19592 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19593 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19594 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19595 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19596 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19597 inst
.instruction
|= neon_logbits (size
) << 20;
19599 neon_dp_fixup (&inst
);
19603 do_neon_dyadic_long (void)
19605 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
19608 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19611 NEON_ENCODE (INTEGER
, inst
);
19612 /* FIXME: Type checking for lengthening op. */
19613 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19614 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19615 neon_mixed_length (et
, et
.size
);
19617 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19618 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19620 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19621 in an IT block with le/lt conditions. */
19623 if (inst
.cond
== 0xf)
19625 else if (inst
.cond
== 0x10)
19628 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19630 if (inst
.instruction
== N_MNEM_vaddl
)
19632 inst
.instruction
= N_MNEM_vadd
;
19633 do_neon_addsub_if_i ();
19635 else if (inst
.instruction
== N_MNEM_vsubl
)
19637 inst
.instruction
= N_MNEM_vsub
;
19638 do_neon_addsub_if_i ();
19640 else if (inst
.instruction
== N_MNEM_vabdl
)
19642 inst
.instruction
= N_MNEM_vabd
;
19643 do_neon_dyadic_if_su ();
19647 first_error (BAD_FPU
);
19651 do_neon_abal (void)
19653 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19654 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19655 neon_mixed_length (et
, et
.size
);
19659 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19661 if (inst
.operands
[2].isscalar
)
19663 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19664 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19665 NEON_ENCODE (SCALAR
, inst
);
19666 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19670 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19671 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19672 NEON_ENCODE (INTEGER
, inst
);
19673 neon_mixed_length (et
, et
.size
);
19678 do_neon_mac_maybe_scalar_long (void)
19680 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19683 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19684 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19687 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19689 unsigned regno
= NEON_SCALAR_REG (scalar
);
19690 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19694 if (regno
> 7 || elno
> 3)
19697 return ((regno
& 0x7)
19698 | ((elno
& 0x1) << 3)
19699 | (((elno
>> 1) & 0x1) << 5));
19703 if (regno
> 15 || elno
> 1)
19706 return (((regno
& 0x1) << 5)
19707 | ((regno
>> 1) & 0x7)
19708 | ((elno
& 0x1) << 3));
19712 first_error (_("scalar out of range for multiply instruction"));
19717 do_neon_fmac_maybe_scalar_long (int subtype
)
19719 enum neon_shape rs
;
19721 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19722 field (bits[21:20]) has different meaning. For scalar index variant, it's
19723 used to differentiate add and subtract, otherwise it's with fixed value
19727 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19728 be a scalar index register. */
19729 if (inst
.operands
[2].isscalar
)
19731 high8
= 0xfe000000;
19734 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19738 high8
= 0xfc000000;
19741 inst
.instruction
|= (0x1 << 23);
19742 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19746 if (inst
.cond
!= COND_ALWAYS
)
19747 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19748 "behaviour is UNPREDICTABLE"));
19750 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19753 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19756 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19757 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19758 so we simply pass -1 as size. */
19759 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19760 neon_three_same (quad_p
, 0, size
);
19762 /* Undo neon_dp_fixup. Redo the high eight bits. */
19763 inst
.instruction
&= 0x00ffffff;
19764 inst
.instruction
|= high8
;
19766 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19767 whether the instruction is in Q form and whether Vm is a scalar indexed
19769 if (inst
.operands
[2].isscalar
)
19772 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19773 inst
.instruction
&= 0xffffffd0;
19774 inst
.instruction
|= rm
;
19778 /* Redo Rn as well. */
19779 inst
.instruction
&= 0xfff0ff7f;
19780 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19781 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19786 /* Redo Rn and Rm. */
19787 inst
.instruction
&= 0xfff0ff50;
19788 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19789 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19790 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19791 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19796 do_neon_vfmal (void)
19798 return do_neon_fmac_maybe_scalar_long (0);
19802 do_neon_vfmsl (void)
19804 return do_neon_fmac_maybe_scalar_long (1);
19808 do_neon_dyadic_wide (void)
19810 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19811 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19812 neon_mixed_length (et
, et
.size
);
19816 do_neon_dyadic_narrow (void)
19818 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19819 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19820 /* Operand sign is unimportant, and the U bit is part of the opcode,
19821 so force the operand type to integer. */
19822 et
.type
= NT_integer
;
19823 neon_mixed_length (et
, et
.size
/ 2);
19827 do_neon_mul_sat_scalar_long (void)
19829 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19833 do_neon_vmull (void)
19835 if (inst
.operands
[2].isscalar
)
19836 do_neon_mac_maybe_scalar_long ();
19839 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19840 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19842 if (et
.type
== NT_poly
)
19843 NEON_ENCODE (POLY
, inst
);
19845 NEON_ENCODE (INTEGER
, inst
);
19847 /* For polynomial encoding the U bit must be zero, and the size must
19848 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19849 obviously, as 0b10). */
19852 /* Check we're on the correct architecture. */
19853 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19855 _("Instruction form not available on this architecture.");
19860 neon_mixed_length (et
, et
.size
);
19867 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19868 struct neon_type_el et
= neon_check_type (3, rs
,
19869 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19870 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19872 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19873 _("shift out of range"));
19874 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19875 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19876 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19877 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19878 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19879 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19880 inst
.instruction
|= neon_quad (rs
) << 6;
19881 inst
.instruction
|= imm
<< 8;
19883 neon_dp_fixup (&inst
);
19889 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19892 enum neon_shape rs
;
19893 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19894 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19896 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19898 struct neon_type_el et
= neon_check_type (2, rs
,
19899 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19901 unsigned op
= (inst
.instruction
>> 7) & 3;
19902 /* N (width of reversed regions) is encoded as part of the bitmask. We
19903 extract it here to check the elements to be reversed are smaller.
19904 Otherwise we'd get a reserved instruction. */
19905 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19907 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19908 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19909 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19910 " operands makes instruction UNPREDICTABLE"));
19912 gas_assert (elsize
!= 0);
19913 constraint (et
.size
>= elsize
,
19914 _("elements must be smaller than reversal region"));
19915 neon_two_same (neon_quad (rs
), 1, et
.size
);
19921 if (inst
.operands
[1].isscalar
)
19923 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19925 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19926 struct neon_type_el et
= neon_check_type (2, rs
,
19927 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19928 unsigned sizebits
= et
.size
>> 3;
19929 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19930 int logsize
= neon_logbits (et
.size
);
19931 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19933 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19936 NEON_ENCODE (SCALAR
, inst
);
19937 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19938 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19939 inst
.instruction
|= LOW4 (dm
);
19940 inst
.instruction
|= HI1 (dm
) << 5;
19941 inst
.instruction
|= neon_quad (rs
) << 6;
19942 inst
.instruction
|= x
<< 17;
19943 inst
.instruction
|= sizebits
<< 16;
19945 neon_dp_fixup (&inst
);
19949 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19950 struct neon_type_el et
= neon_check_type (2, rs
,
19951 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19954 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19958 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19961 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19963 if (inst
.operands
[1].reg
== REG_SP
)
19964 as_tsktsk (MVE_BAD_SP
);
19965 else if (inst
.operands
[1].reg
== REG_PC
)
19966 as_tsktsk (MVE_BAD_PC
);
19969 /* Duplicate ARM register to lanes of vector. */
19970 NEON_ENCODE (ARMREG
, inst
);
19973 case 8: inst
.instruction
|= 0x400000; break;
19974 case 16: inst
.instruction
|= 0x000020; break;
19975 case 32: inst
.instruction
|= 0x000000; break;
19978 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19979 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19980 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19981 inst
.instruction
|= neon_quad (rs
) << 21;
19982 /* The encoding for this instruction is identical for the ARM and Thumb
19983 variants, except for the condition field. */
19984 do_vfp_cond_or_thumb ();
19989 do_mve_mov (int toQ
)
19991 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19993 if (inst
.cond
> COND_ALWAYS
)
19994 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19996 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
20005 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
20006 _("Index one must be [2,3] and index two must be two less than"
20008 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
20009 _("General purpose registers may not be the same"));
20010 constraint (inst
.operands
[Rt
].reg
== REG_SP
20011 || inst
.operands
[Rt2
].reg
== REG_SP
,
20013 constraint (inst
.operands
[Rt
].reg
== REG_PC
20014 || inst
.operands
[Rt2
].reg
== REG_PC
,
20017 inst
.instruction
= 0xec000f00;
20018 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
20019 inst
.instruction
|= !!toQ
<< 20;
20020 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
20021 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
20022 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
20023 inst
.instruction
|= inst
.operands
[Rt
].reg
;
20029 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20032 if (inst
.cond
> COND_ALWAYS
)
20033 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20035 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
20037 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
20040 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20041 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
20042 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20043 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20044 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20049 /* VMOV has particularly many variations. It can be one of:
20050 0. VMOV<c><q> <Qd>, <Qm>
20051 1. VMOV<c><q> <Dd>, <Dm>
20052 (Register operations, which are VORR with Rm = Rn.)
20053 2. VMOV<c><q>.<dt> <Qd>, #<imm>
20054 3. VMOV<c><q>.<dt> <Dd>, #<imm>
20056 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
20057 (ARM register to scalar.)
20058 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
20059 (Two ARM registers to vector.)
20060 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
20061 (Scalar to ARM register.)
20062 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
20063 (Vector to two ARM registers.)
20064 8. VMOV.F32 <Sd>, <Sm>
20065 9. VMOV.F64 <Dd>, <Dm>
20066 (VFP register moves.)
20067 10. VMOV.F32 <Sd>, #imm
20068 11. VMOV.F64 <Dd>, #imm
20069 (VFP float immediate load.)
20070 12. VMOV <Rd>, <Sm>
20071 (VFP single to ARM reg.)
20072 13. VMOV <Sd>, <Rm>
20073 (ARM reg to VFP single.)
20074 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
20075 (Two ARM regs to two VFP singles.)
20076 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
20077 (Two VFP singles to two ARM regs.)
20078 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
20079 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
20080 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
20081 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
20083 These cases can be disambiguated using neon_select_shape, except cases 1/9
20084 and 3/11 which depend on the operand type too.
20086 All the encoded bits are hardcoded by this function.
20088 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
20089 Cases 5, 7 may be used with VFPv2 and above.
20091 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
20092 can specify a type where it doesn't make sense to, and is ignored). */
20097 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
20098 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
20099 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
20100 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
20102 struct neon_type_el et
;
20103 const char *ldconst
= 0;
20107 case NS_DD
: /* case 1/9. */
20108 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20109 /* It is not an error here if no type is given. */
20112 /* In MVE we interpret the following instructions as same, so ignoring
20113 the following type (float) and size (64) checks.
20114 a: VMOV<c><q> <Dd>, <Dm>
20115 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
20116 if ((et
.type
== NT_float
&& et
.size
== 64)
20117 || (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
20119 do_vfp_nsyn_opcode ("fcpyd");
20122 /* fall through. */
20124 case NS_QQ
: /* case 0/1. */
20126 if (!check_simd_pred_availability (FALSE
,
20127 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20129 /* The architecture manual I have doesn't explicitly state which
20130 value the U bit should have for register->register moves, but
20131 the equivalent VORR instruction has U = 0, so do that. */
20132 inst
.instruction
= 0x0200110;
20133 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20134 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20135 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20136 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20137 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20138 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20139 inst
.instruction
|= neon_quad (rs
) << 6;
20141 neon_dp_fixup (&inst
);
20145 case NS_DI
: /* case 3/11. */
20146 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20148 if (et
.type
== NT_float
&& et
.size
== 64)
20150 /* case 11 (fconstd). */
20151 ldconst
= "fconstd";
20152 goto encode_fconstd
;
20154 /* fall through. */
20156 case NS_QI
: /* case 2/3. */
20157 if (!check_simd_pred_availability (FALSE
,
20158 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20160 inst
.instruction
= 0x0800010;
20161 neon_move_immediate ();
20162 neon_dp_fixup (&inst
);
20165 case NS_SR
: /* case 4. */
20167 unsigned bcdebits
= 0;
20169 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
20170 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
20172 /* .<size> is optional here, defaulting to .32. */
20173 if (inst
.vectype
.elems
== 0
20174 && inst
.operands
[0].vectype
.type
== NT_invtype
20175 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20177 inst
.vectype
.el
[0].type
= NT_untyped
;
20178 inst
.vectype
.el
[0].size
= 32;
20179 inst
.vectype
.elems
= 1;
20182 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
20183 logsize
= neon_logbits (et
.size
);
20187 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20188 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
20193 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20194 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20198 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20200 if (inst
.operands
[1].reg
== REG_SP
)
20201 as_tsktsk (MVE_BAD_SP
);
20202 else if (inst
.operands
[1].reg
== REG_PC
)
20203 as_tsktsk (MVE_BAD_PC
);
20205 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
20207 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20208 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20213 case 8: bcdebits
= 0x8; break;
20214 case 16: bcdebits
= 0x1; break;
20215 case 32: bcdebits
= 0x0; break;
20219 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20221 inst
.instruction
= 0xe000b10;
20222 do_vfp_cond_or_thumb ();
20223 inst
.instruction
|= LOW4 (dn
) << 16;
20224 inst
.instruction
|= HI1 (dn
) << 7;
20225 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20226 inst
.instruction
|= (bcdebits
& 3) << 5;
20227 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
20228 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20232 case NS_DRR
: /* case 5 (fmdrr). */
20233 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20234 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20237 inst
.instruction
= 0xc400b10;
20238 do_vfp_cond_or_thumb ();
20239 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
20240 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
20241 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20242 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
20245 case NS_RS
: /* case 6. */
20248 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
20249 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
20250 unsigned abcdebits
= 0;
20252 /* .<dt> is optional here, defaulting to .32. */
20253 if (inst
.vectype
.elems
== 0
20254 && inst
.operands
[0].vectype
.type
== NT_invtype
20255 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20257 inst
.vectype
.el
[0].type
= NT_untyped
;
20258 inst
.vectype
.el
[0].size
= 32;
20259 inst
.vectype
.elems
= 1;
20262 et
= neon_check_type (2, NS_NULL
,
20263 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20264 logsize
= neon_logbits (et
.size
);
20268 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20269 && vfp_or_neon_is_neon (NEON_CHECK_CC
20270 | NEON_CHECK_ARCH
) == FAIL
)
20275 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20276 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20280 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20282 if (inst
.operands
[0].reg
== REG_SP
)
20283 as_tsktsk (MVE_BAD_SP
);
20284 else if (inst
.operands
[0].reg
== REG_PC
)
20285 as_tsktsk (MVE_BAD_PC
);
20288 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20290 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20291 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20295 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20296 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20297 case 32: abcdebits
= 0x00; break;
20301 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20302 inst
.instruction
= 0xe100b10;
20303 do_vfp_cond_or_thumb ();
20304 inst
.instruction
|= LOW4 (dn
) << 16;
20305 inst
.instruction
|= HI1 (dn
) << 7;
20306 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20307 inst
.instruction
|= (abcdebits
& 3) << 5;
20308 inst
.instruction
|= (abcdebits
>> 2) << 21;
20309 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20313 case NS_RRD
: /* case 7 (fmrrd). */
20314 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20315 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20318 inst
.instruction
= 0xc500b10;
20319 do_vfp_cond_or_thumb ();
20320 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20321 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20322 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20323 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20326 case NS_FF
: /* case 8 (fcpys). */
20327 do_vfp_nsyn_opcode ("fcpys");
20331 case NS_FI
: /* case 10 (fconsts). */
20332 ldconst
= "fconsts";
20334 if (!inst
.operands
[1].immisfloat
)
20337 /* Immediate has to fit in 8 bits so float is enough. */
20338 float imm
= (float) inst
.operands
[1].imm
;
20339 memcpy (&new_imm
, &imm
, sizeof (float));
20340 /* But the assembly may have been written to provide an integer
20341 bit pattern that equates to a float, so check that the
20342 conversion has worked. */
20343 if (is_quarter_float (new_imm
))
20345 if (is_quarter_float (inst
.operands
[1].imm
))
20346 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20348 inst
.operands
[1].imm
= new_imm
;
20349 inst
.operands
[1].immisfloat
= 1;
20353 if (is_quarter_float (inst
.operands
[1].imm
))
20355 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20356 do_vfp_nsyn_opcode (ldconst
);
20358 /* ARMv8.2 fp16 vmov.f16 instruction. */
20360 do_scalar_fp16_v82_encode ();
20363 first_error (_("immediate out of range"));
20367 case NS_RF
: /* case 12 (fmrs). */
20368 do_vfp_nsyn_opcode ("fmrs");
20369 /* ARMv8.2 fp16 vmov.f16 instruction. */
20371 do_scalar_fp16_v82_encode ();
20375 case NS_FR
: /* case 13 (fmsr). */
20376 do_vfp_nsyn_opcode ("fmsr");
20377 /* ARMv8.2 fp16 vmov.f16 instruction. */
20379 do_scalar_fp16_v82_encode ();
20389 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20390 (one of which is a list), but we have parsed four. Do some fiddling to
20391 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20393 case NS_RRFF
: /* case 14 (fmrrs). */
20394 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20395 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20397 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20398 _("VFP registers must be adjacent"));
20399 inst
.operands
[2].imm
= 2;
20400 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20401 do_vfp_nsyn_opcode ("fmrrs");
20404 case NS_FFRR
: /* case 15 (fmsrr). */
20405 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20406 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20408 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20409 _("VFP registers must be adjacent"));
20410 inst
.operands
[1] = inst
.operands
[2];
20411 inst
.operands
[2] = inst
.operands
[3];
20412 inst
.operands
[0].imm
= 2;
20413 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20414 do_vfp_nsyn_opcode ("fmsrr");
20418 /* neon_select_shape has determined that the instruction
20419 shape is wrong and has already set the error message. */
20430 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20431 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20432 && !inst
.operands
[2].present
))
20434 inst
.instruction
= 0;
20437 set_pred_insn_type (INSIDE_IT_INSN
);
20442 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20445 if (inst
.cond
!= COND_ALWAYS
)
20446 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20448 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20449 | N_S16
| N_U16
| N_KEY
);
20451 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20452 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20453 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20454 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20455 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20456 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20461 do_neon_rshift_round_imm (void)
20463 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20466 enum neon_shape rs
;
20467 struct neon_type_el et
;
20469 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20471 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20472 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20476 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20477 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20479 int imm
= inst
.operands
[2].imm
;
20481 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20484 inst
.operands
[2].present
= 0;
20489 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20490 _("immediate out of range for shift"));
20491 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20496 do_neon_movhf (void)
20498 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20499 constraint (rs
!= NS_HH
, _("invalid suffix"));
20501 if (inst
.cond
!= COND_ALWAYS
)
20505 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20506 " the behaviour is UNPREDICTABLE"));
20510 inst
.error
= BAD_COND
;
20515 do_vfp_sp_monadic ();
20518 inst
.instruction
|= 0xf0000000;
20522 do_neon_movl (void)
20524 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20525 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20526 unsigned sizebits
= et
.size
>> 3;
20527 inst
.instruction
|= sizebits
<< 19;
20528 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20534 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20535 struct neon_type_el et
= neon_check_type (2, rs
,
20536 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20537 NEON_ENCODE (INTEGER
, inst
);
20538 neon_two_same (neon_quad (rs
), 1, et
.size
);
20542 do_neon_zip_uzp (void)
20544 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20545 struct neon_type_el et
= neon_check_type (2, rs
,
20546 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20547 if (rs
== NS_DD
&& et
.size
== 32)
20549 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20550 inst
.instruction
= N_MNEM_vtrn
;
20554 neon_two_same (neon_quad (rs
), 1, et
.size
);
20558 do_neon_sat_abs_neg (void)
20560 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20563 enum neon_shape rs
;
20564 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20565 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20567 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20568 struct neon_type_el et
= neon_check_type (2, rs
,
20569 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20570 neon_two_same (neon_quad (rs
), 1, et
.size
);
20574 do_neon_pair_long (void)
20576 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20577 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20578 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20579 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20580 neon_two_same (neon_quad (rs
), 1, et
.size
);
20584 do_neon_recip_est (void)
20586 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20587 struct neon_type_el et
= neon_check_type (2, rs
,
20588 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20589 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20590 neon_two_same (neon_quad (rs
), 1, et
.size
);
20596 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20599 enum neon_shape rs
;
20600 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20601 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20603 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20605 struct neon_type_el et
= neon_check_type (2, rs
,
20606 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20607 neon_two_same (neon_quad (rs
), 1, et
.size
);
20613 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20616 enum neon_shape rs
;
20617 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20618 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20620 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20622 struct neon_type_el et
= neon_check_type (2, rs
,
20623 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20624 neon_two_same (neon_quad (rs
), 1, et
.size
);
20630 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20631 struct neon_type_el et
= neon_check_type (2, rs
,
20632 N_EQK
| N_INT
, N_8
| N_KEY
);
20633 neon_two_same (neon_quad (rs
), 1, et
.size
);
20639 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20640 neon_two_same (neon_quad (rs
), 1, -1);
20644 do_neon_tbl_tbx (void)
20646 unsigned listlenbits
;
20647 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20649 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20651 first_error (_("bad list length for table lookup"));
20655 listlenbits
= inst
.operands
[1].imm
- 1;
20656 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20657 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20658 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20659 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20660 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20661 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20662 inst
.instruction
|= listlenbits
<< 8;
20664 neon_dp_fixup (&inst
);
20668 do_neon_ldm_stm (void)
20670 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
20671 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20673 /* P, U and L bits are part of bitmask. */
20674 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20675 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20677 if (inst
.operands
[1].issingle
)
20679 do_vfp_nsyn_ldm_stm (is_dbmode
);
20683 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20684 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20686 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20687 _("register list must contain at least 1 and at most 16 "
20690 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20691 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20692 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20693 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20695 inst
.instruction
|= offsetbits
;
20697 do_vfp_cond_or_thumb ();
20701 do_vfp_nsyn_pop (void)
20704 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20705 return do_vfp_nsyn_opcode ("vldm");
20708 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20711 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20712 _("register list must contain at least 1 and at most 16 "
20715 if (inst
.operands
[1].issingle
)
20716 do_vfp_nsyn_opcode ("fldmias");
20718 do_vfp_nsyn_opcode ("fldmiad");
20722 do_vfp_nsyn_push (void)
20725 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20726 return do_vfp_nsyn_opcode ("vstmdb");
20729 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20732 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20733 _("register list must contain at least 1 and at most 16 "
20736 if (inst
.operands
[1].issingle
)
20737 do_vfp_nsyn_opcode ("fstmdbs");
20739 do_vfp_nsyn_opcode ("fstmdbd");
20744 do_neon_ldr_str (void)
20746 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20748 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20749 And is UNPREDICTABLE in thumb mode. */
20751 && inst
.operands
[1].reg
== REG_PC
20752 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20755 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20756 else if (warn_on_deprecated
)
20757 as_tsktsk (_("Use of PC here is deprecated"));
20760 if (inst
.operands
[0].issingle
)
20763 do_vfp_nsyn_opcode ("flds");
20765 do_vfp_nsyn_opcode ("fsts");
20767 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20768 if (inst
.vectype
.el
[0].size
== 16)
20769 do_scalar_fp16_v82_encode ();
20774 do_vfp_nsyn_opcode ("fldd");
20776 do_vfp_nsyn_opcode ("fstd");
20781 do_t_vldr_vstr_sysreg (void)
20783 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20784 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20786 /* Use of PC is UNPREDICTABLE. */
20787 if (inst
.operands
[1].reg
== REG_PC
)
20788 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20790 if (inst
.operands
[1].immisreg
)
20791 inst
.error
= _("instruction does not accept register index");
20793 if (!inst
.operands
[1].isreg
)
20794 inst
.error
= _("instruction does not accept PC-relative addressing");
20796 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20797 inst
.error
= _("immediate value out of range");
20799 inst
.instruction
= 0xec000f80;
20801 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20802 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20803 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20804 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20808 do_vldr_vstr (void)
20810 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20812 /* VLDR/VSTR (System Register). */
20815 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20816 as_bad (_("Instruction not permitted on this architecture"));
20818 do_t_vldr_vstr_sysreg ();
20823 if (!mark_feature_used (&fpu_vfp_ext_v1xd
)
20824 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20825 as_bad (_("Instruction not permitted on this architecture"));
20826 do_neon_ldr_str ();
20830 /* "interleave" version also handles non-interleaving register VLD1/VST1
20834 do_neon_ld_st_interleave (void)
20836 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20837 N_8
| N_16
| N_32
| N_64
);
20838 unsigned alignbits
= 0;
20840 /* The bits in this table go:
20841 0: register stride of one (0) or two (1)
20842 1,2: register list length, minus one (1, 2, 3, 4).
20843 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20844 We use -1 for invalid entries. */
20845 const int typetable
[] =
20847 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20848 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20849 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20850 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20854 if (et
.type
== NT_invtype
)
20857 if (inst
.operands
[1].immisalign
)
20858 switch (inst
.operands
[1].imm
>> 8)
20860 case 64: alignbits
= 1; break;
20862 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20863 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20864 goto bad_alignment
;
20868 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20869 goto bad_alignment
;
20874 first_error (_("bad alignment"));
20878 inst
.instruction
|= alignbits
<< 4;
20879 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20881 /* Bits [4:6] of the immediate in a list specifier encode register stride
20882 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20883 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20884 up the right value for "type" in a table based on this value and the given
20885 list style, then stick it back. */
20886 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20887 | (((inst
.instruction
>> 8) & 3) << 3);
20889 typebits
= typetable
[idx
];
20891 constraint (typebits
== -1, _("bad list type for instruction"));
20892 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20895 inst
.instruction
&= ~0xf00;
20896 inst
.instruction
|= typebits
<< 8;
20899 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20900 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20901 otherwise. The variable arguments are a list of pairs of legal (size, align)
20902 values, terminated with -1. */
20905 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20908 int result
= FAIL
, thissize
, thisalign
;
20910 if (!inst
.operands
[1].immisalign
)
20916 va_start (ap
, do_alignment
);
20920 thissize
= va_arg (ap
, int);
20921 if (thissize
== -1)
20923 thisalign
= va_arg (ap
, int);
20925 if (size
== thissize
&& align
== thisalign
)
20928 while (result
!= SUCCESS
);
20932 if (result
== SUCCESS
)
20935 first_error (_("unsupported alignment for instruction"));
20941 do_neon_ld_st_lane (void)
20943 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20944 int align_good
, do_alignment
= 0;
20945 int logsize
= neon_logbits (et
.size
);
20946 int align
= inst
.operands
[1].imm
>> 8;
20947 int n
= (inst
.instruction
>> 8) & 3;
20948 int max_el
= 64 / et
.size
;
20950 if (et
.type
== NT_invtype
)
20953 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20954 _("bad list length"));
20955 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20956 _("scalar index out of range"));
20957 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20959 _("stride of 2 unavailable when element size is 8"));
20963 case 0: /* VLD1 / VST1. */
20964 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20966 if (align_good
== FAIL
)
20970 unsigned alignbits
= 0;
20973 case 16: alignbits
= 0x1; break;
20974 case 32: alignbits
= 0x3; break;
20977 inst
.instruction
|= alignbits
<< 4;
20981 case 1: /* VLD2 / VST2. */
20982 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20983 16, 32, 32, 64, -1);
20984 if (align_good
== FAIL
)
20987 inst
.instruction
|= 1 << 4;
20990 case 2: /* VLD3 / VST3. */
20991 constraint (inst
.operands
[1].immisalign
,
20992 _("can't use alignment with this instruction"));
20995 case 3: /* VLD4 / VST4. */
20996 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20997 16, 64, 32, 64, 32, 128, -1);
20998 if (align_good
== FAIL
)
21002 unsigned alignbits
= 0;
21005 case 8: alignbits
= 0x1; break;
21006 case 16: alignbits
= 0x1; break;
21007 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
21010 inst
.instruction
|= alignbits
<< 4;
21017 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
21018 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21019 inst
.instruction
|= 1 << (4 + logsize
);
21021 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
21022 inst
.instruction
|= logsize
<< 10;
21025 /* Encode single n-element structure to all lanes VLD<n> instructions. */
21028 do_neon_ld_dup (void)
21030 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
21031 int align_good
, do_alignment
= 0;
21033 if (et
.type
== NT_invtype
)
21036 switch ((inst
.instruction
>> 8) & 3)
21038 case 0: /* VLD1. */
21039 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
21040 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21041 &do_alignment
, 16, 16, 32, 32, -1);
21042 if (align_good
== FAIL
)
21044 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
21047 case 2: inst
.instruction
|= 1 << 5; break;
21048 default: first_error (_("bad list length")); return;
21050 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21053 case 1: /* VLD2. */
21054 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21055 &do_alignment
, 8, 16, 16, 32, 32, 64,
21057 if (align_good
== FAIL
)
21059 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
21060 _("bad list length"));
21061 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21062 inst
.instruction
|= 1 << 5;
21063 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21066 case 2: /* VLD3. */
21067 constraint (inst
.operands
[1].immisalign
,
21068 _("can't use alignment with this instruction"));
21069 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
21070 _("bad list length"));
21071 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21072 inst
.instruction
|= 1 << 5;
21073 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21076 case 3: /* VLD4. */
21078 int align
= inst
.operands
[1].imm
>> 8;
21079 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
21080 16, 64, 32, 64, 32, 128, -1);
21081 if (align_good
== FAIL
)
21083 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
21084 _("bad list length"));
21085 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21086 inst
.instruction
|= 1 << 5;
21087 if (et
.size
== 32 && align
== 128)
21088 inst
.instruction
|= 0x3 << 6;
21090 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21097 inst
.instruction
|= do_alignment
<< 4;
21100 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
21101 apart from bits [11:4]. */
21104 do_neon_ldx_stx (void)
21106 if (inst
.operands
[1].isreg
)
21107 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
21109 switch (NEON_LANE (inst
.operands
[0].imm
))
21111 case NEON_INTERLEAVE_LANES
:
21112 NEON_ENCODE (INTERLV
, inst
);
21113 do_neon_ld_st_interleave ();
21116 case NEON_ALL_LANES
:
21117 NEON_ENCODE (DUP
, inst
);
21118 if (inst
.instruction
== N_INV
)
21120 first_error ("only loads support such operands");
21127 NEON_ENCODE (LANE
, inst
);
21128 do_neon_ld_st_lane ();
21131 /* L bit comes from bit mask. */
21132 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21133 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21134 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
21136 if (inst
.operands
[1].postind
)
21138 int postreg
= inst
.operands
[1].imm
& 0xf;
21139 constraint (!inst
.operands
[1].immisreg
,
21140 _("post-index must be a register"));
21141 constraint (postreg
== 0xd || postreg
== 0xf,
21142 _("bad register for post-index"));
21143 inst
.instruction
|= postreg
;
21147 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
21148 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
21149 || inst
.relocs
[0].exp
.X_add_number
!= 0,
21152 if (inst
.operands
[1].writeback
)
21154 inst
.instruction
|= 0xd;
21157 inst
.instruction
|= 0xf;
21161 inst
.instruction
|= 0xf9000000;
21163 inst
.instruction
|= 0xf4000000;
21168 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
21170 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21171 D register operands. */
21172 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21173 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21176 NEON_ENCODE (FPV8
, inst
);
21178 if (rs
== NS_FFF
|| rs
== NS_HHH
)
21180 do_vfp_sp_dyadic ();
21182 /* ARMv8.2 fp16 instruction. */
21184 do_scalar_fp16_v82_encode ();
21187 do_vfp_dp_rd_rn_rm ();
21190 inst
.instruction
|= 0x100;
21192 inst
.instruction
|= 0xf0000000;
21198 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21200 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
21201 first_error (_("invalid instruction shape"));
21207 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21208 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21210 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
21213 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21216 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
21220 do_vrint_1 (enum neon_cvt_mode mode
)
21222 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
21223 struct neon_type_el et
;
21228 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21229 D register operands. */
21230 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21231 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21234 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
21236 if (et
.type
!= NT_invtype
)
21238 /* VFP encodings. */
21239 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
21240 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
21241 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21243 NEON_ENCODE (FPV8
, inst
);
21244 if (rs
== NS_FF
|| rs
== NS_HH
)
21245 do_vfp_sp_monadic ();
21247 do_vfp_dp_rd_rm ();
21251 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
21252 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
21253 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
21254 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
21255 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
21256 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
21257 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
21261 inst
.instruction
|= (rs
== NS_DD
) << 8;
21262 do_vfp_cond_or_thumb ();
21264 /* ARMv8.2 fp16 vrint instruction. */
21266 do_scalar_fp16_v82_encode ();
21270 /* Neon encodings (or something broken...). */
21272 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
21274 if (et
.type
== NT_invtype
)
21277 if (!check_simd_pred_availability (TRUE
,
21278 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21281 NEON_ENCODE (FLOAT
, inst
);
21283 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21284 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21285 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21286 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21287 inst
.instruction
|= neon_quad (rs
) << 6;
21288 /* Mask off the original size bits and reencode them. */
21289 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
21290 | neon_logbits (et
.size
) << 18);
21294 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
21295 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
21296 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
21297 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
21298 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
21299 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
21300 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21305 inst
.instruction
|= 0xfc000000;
21307 inst
.instruction
|= 0xf0000000;
21314 do_vrint_1 (neon_cvt_mode_x
);
21320 do_vrint_1 (neon_cvt_mode_z
);
21326 do_vrint_1 (neon_cvt_mode_r
);
21332 do_vrint_1 (neon_cvt_mode_a
);
21338 do_vrint_1 (neon_cvt_mode_n
);
21344 do_vrint_1 (neon_cvt_mode_p
);
21350 do_vrint_1 (neon_cvt_mode_m
);
21354 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21356 unsigned regno
= NEON_SCALAR_REG (opnd
);
21357 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21359 if (elsize
== 16 && elno
< 2 && regno
< 16)
21360 return regno
| (elno
<< 4);
21361 else if (elsize
== 32 && elno
== 0)
21364 first_error (_("scalar out of range"));
21371 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21372 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21373 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21374 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21375 _("expression too complex"));
21376 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21377 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21378 _("immediate out of range"));
21381 if (!check_simd_pred_availability (TRUE
,
21382 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21385 if (inst
.operands
[2].isscalar
)
21387 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21388 first_error (_("invalid instruction shape"));
21389 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21390 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21391 N_KEY
| N_F16
| N_F32
).size
;
21392 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21394 inst
.instruction
= 0xfe000800;
21395 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21396 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21397 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21398 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21399 inst
.instruction
|= LOW4 (m
);
21400 inst
.instruction
|= HI1 (m
) << 5;
21401 inst
.instruction
|= neon_quad (rs
) << 6;
21402 inst
.instruction
|= rot
<< 20;
21403 inst
.instruction
|= (size
== 32) << 23;
21407 enum neon_shape rs
;
21408 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21409 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21411 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21413 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21414 N_KEY
| N_F16
| N_F32
).size
;
21415 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21416 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21417 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21418 as_tsktsk (BAD_MVE_SRCDEST
);
21420 neon_three_same (neon_quad (rs
), 0, -1);
21421 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21422 inst
.instruction
|= 0xfc200800;
21423 inst
.instruction
|= rot
<< 23;
21424 inst
.instruction
|= (size
== 32) << 20;
21431 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21432 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21433 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21434 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21435 _("expression too complex"));
21437 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21438 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21439 enum neon_shape rs
;
21440 struct neon_type_el et
;
21441 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21443 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21444 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21448 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21449 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21451 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21452 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21453 "operand makes instruction UNPREDICTABLE"));
21456 if (et
.type
== NT_invtype
)
21459 if (!check_simd_pred_availability (et
.type
== NT_float
,
21460 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21463 if (et
.type
== NT_float
)
21465 neon_three_same (neon_quad (rs
), 0, -1);
21466 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21467 inst
.instruction
|= 0xfc800800;
21468 inst
.instruction
|= (rot
== 270) << 24;
21469 inst
.instruction
|= (et
.size
== 32) << 20;
21473 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21474 inst
.instruction
= 0xfe000f00;
21475 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21476 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21477 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21478 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21479 inst
.instruction
|= (rot
== 270) << 12;
21480 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21481 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21482 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21487 /* Dot Product instructions encoding support. */
21490 do_neon_dotproduct (int unsigned_p
)
21492 enum neon_shape rs
;
21493 unsigned scalar_oprd2
= 0;
21496 if (inst
.cond
!= COND_ALWAYS
)
21497 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21498 "is UNPREDICTABLE"));
21500 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21503 /* Dot Product instructions are in three-same D/Q register format or the third
21504 operand can be a scalar index register. */
21505 if (inst
.operands
[2].isscalar
)
21507 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21508 high8
= 0xfe000000;
21509 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21513 high8
= 0xfc000000;
21514 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21518 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21520 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21522 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21523 Product instruction, so we pass 0 as the "ubit" parameter. And the
21524 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21525 neon_three_same (neon_quad (rs
), 0, 32);
21527 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21528 different NEON three-same encoding. */
21529 inst
.instruction
&= 0x00ffffff;
21530 inst
.instruction
|= high8
;
21531 /* Encode 'U' bit which indicates signedness. */
21532 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21533 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21534 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21535 the instruction encoding. */
21536 if (inst
.operands
[2].isscalar
)
21538 inst
.instruction
&= 0xffffffd0;
21539 inst
.instruction
|= LOW4 (scalar_oprd2
);
21540 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21544 /* Dot Product instructions for signed integer. */
21547 do_neon_dotproduct_s (void)
21549 return do_neon_dotproduct (0);
21552 /* Dot Product instructions for unsigned integer. */
21555 do_neon_dotproduct_u (void)
21557 return do_neon_dotproduct (1);
21563 enum neon_shape rs
;
21564 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21565 if (inst
.operands
[2].isscalar
)
21567 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21568 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21570 inst
.instruction
|= (1 << 25);
21571 int index
= inst
.operands
[2].reg
& 0xf;
21572 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21573 inst
.operands
[2].reg
>>= 4;
21574 constraint (!(inst
.operands
[2].reg
< 16),
21575 _("indexed register must be less than 16"));
21576 neon_three_args (rs
== NS_QQS
);
21577 inst
.instruction
|= (index
<< 5);
21581 inst
.instruction
|= (1 << 21);
21582 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21583 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21584 neon_three_args (rs
== NS_QQQ
);
21591 enum neon_shape rs
;
21592 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21593 if (inst
.operands
[2].isscalar
)
21595 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21596 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21598 inst
.instruction
|= (1 << 25);
21599 int index
= inst
.operands
[2].reg
& 0xf;
21600 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21601 inst
.operands
[2].reg
>>= 4;
21602 constraint (!(inst
.operands
[2].reg
< 16),
21603 _("indexed register must be less than 16"));
21604 neon_three_args (rs
== NS_QQS
);
21605 inst
.instruction
|= (index
<< 5);
21612 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21613 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21615 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21617 neon_three_args (1);
21624 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21625 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21627 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21629 neon_three_args (1);
21634 check_cde_operand (size_t index
, int is_dual
)
21636 unsigned Rx
= inst
.operands
[index
].reg
;
21637 bfd_boolean isvec
= inst
.operands
[index
].isvec
;
21638 if (is_dual
== 0 && thumb_mode
)
21640 !((Rx
<= 14 && Rx
!= 13) || (Rx
== REG_PC
&& isvec
)),
21641 _("Register must be r0-r14 except r13, or APSR_nzcv."));
21643 constraint ( !((Rx
<= 10 && Rx
% 2 == 0 )),
21644 _("Register must be an even register between r0-r10."));
21648 cde_coproc_enabled (unsigned coproc
)
21652 case 0: return mark_feature_used (&arm_ext_cde0
);
21653 case 1: return mark_feature_used (&arm_ext_cde1
);
21654 case 2: return mark_feature_used (&arm_ext_cde2
);
21655 case 3: return mark_feature_used (&arm_ext_cde3
);
21656 case 4: return mark_feature_used (&arm_ext_cde4
);
21657 case 5: return mark_feature_used (&arm_ext_cde5
);
21658 case 6: return mark_feature_used (&arm_ext_cde6
);
21659 case 7: return mark_feature_used (&arm_ext_cde7
);
21660 default: return FALSE
;
21664 #define cde_coproc_pos 8
21666 cde_handle_coproc (void)
21668 unsigned coproc
= inst
.operands
[0].reg
;
21669 constraint (coproc
> 7, _("CDE Coprocessor must be in range 0-7"));
21670 constraint (!(cde_coproc_enabled (coproc
)), BAD_CDE_COPROC
);
21671 inst
.instruction
|= coproc
<< cde_coproc_pos
;
21673 #undef cde_coproc_pos
21676 cxn_handle_predication (bfd_boolean is_accum
)
21678 if (is_accum
&& conditional_insn ())
21679 set_pred_insn_type (INSIDE_IT_INSN
);
21680 else if (conditional_insn ())
21681 /* conditional_insn essentially checks for a suffix, not whether the
21682 instruction is inside an IT block or not.
21683 The non-accumulator versions should not have suffixes. */
21684 inst
.error
= BAD_SYNTAX
;
21686 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21690 do_custom_instruction_1 (int is_dual
, bfd_boolean is_accum
)
21693 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21697 Rd
= inst
.operands
[1].reg
;
21698 check_cde_operand (1, is_dual
);
21702 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21703 _("cx1d requires consecutive destination registers."));
21704 imm
= inst
.operands
[3].imm
;
21706 else if (is_dual
== 0)
21707 imm
= inst
.operands
[2].imm
;
21711 inst
.instruction
|= Rd
<< 12;
21712 inst
.instruction
|= (imm
& 0x1F80) << 9;
21713 inst
.instruction
|= (imm
& 0x0040) << 1;
21714 inst
.instruction
|= (imm
& 0x003f);
21716 cde_handle_coproc ();
21717 cxn_handle_predication (is_accum
);
21721 do_custom_instruction_2 (int is_dual
, bfd_boolean is_accum
)
21724 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21726 unsigned imm
, Rd
, Rn
;
21728 Rd
= inst
.operands
[1].reg
;
21732 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21733 _("cx2d requires consecutive destination registers."));
21734 imm
= inst
.operands
[4].imm
;
21735 Rn
= inst
.operands
[3].reg
;
21737 else if (is_dual
== 0)
21739 imm
= inst
.operands
[3].imm
;
21740 Rn
= inst
.operands
[2].reg
;
21745 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21746 check_cde_operand (1, is_dual
);
21748 inst
.instruction
|= Rd
<< 12;
21749 inst
.instruction
|= Rn
<< 16;
21751 inst
.instruction
|= (imm
& 0x0380) << 13;
21752 inst
.instruction
|= (imm
& 0x0040) << 1;
21753 inst
.instruction
|= (imm
& 0x003f);
21755 cde_handle_coproc ();
21756 cxn_handle_predication (is_accum
);
21760 do_custom_instruction_3 (int is_dual
, bfd_boolean is_accum
)
21763 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21765 unsigned imm
, Rd
, Rn
, Rm
;
21767 Rd
= inst
.operands
[1].reg
;
21771 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21772 _("cx3d requires consecutive destination registers."));
21773 imm
= inst
.operands
[5].imm
;
21774 Rn
= inst
.operands
[3].reg
;
21775 Rm
= inst
.operands
[4].reg
;
21777 else if (is_dual
== 0)
21779 imm
= inst
.operands
[4].imm
;
21780 Rn
= inst
.operands
[2].reg
;
21781 Rm
= inst
.operands
[3].reg
;
21786 check_cde_operand (1, is_dual
);
21787 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21788 check_cde_operand (3 + is_dual
, /* is_dual = */0);
21790 inst
.instruction
|= Rd
;
21791 inst
.instruction
|= Rn
<< 16;
21792 inst
.instruction
|= Rm
<< 12;
21794 inst
.instruction
|= (imm
& 0x0038) << 17;
21795 inst
.instruction
|= (imm
& 0x0004) << 5;
21796 inst
.instruction
|= (imm
& 0x0003) << 4;
21798 cde_handle_coproc ();
21799 cxn_handle_predication (is_accum
);
21805 return do_custom_instruction_1 (0, 0);
21811 return do_custom_instruction_1 (0, 1);
21817 return do_custom_instruction_1 (1, 0);
21823 return do_custom_instruction_1 (1, 1);
21829 return do_custom_instruction_2 (0, 0);
21835 return do_custom_instruction_2 (0, 1);
21841 return do_custom_instruction_2 (1, 0);
21847 return do_custom_instruction_2 (1, 1);
21853 return do_custom_instruction_3 (0, 0);
21859 return do_custom_instruction_3 (0, 1);
21865 return do_custom_instruction_3 (1, 0);
21871 return do_custom_instruction_3 (1, 1);
21875 vcx_assign_vec_d (unsigned regnum
)
21877 inst
.instruction
|= HI4 (regnum
) << 12;
21878 inst
.instruction
|= LOW1 (regnum
) << 22;
21882 vcx_assign_vec_m (unsigned regnum
)
21884 inst
.instruction
|= HI4 (regnum
);
21885 inst
.instruction
|= LOW1 (regnum
) << 5;
21889 vcx_assign_vec_n (unsigned regnum
)
21891 inst
.instruction
|= HI4 (regnum
) << 16;
21892 inst
.instruction
|= LOW1 (regnum
) << 7;
21895 enum vcx_reg_type
{
21901 static enum vcx_reg_type
21902 vcx_get_reg_type (enum neon_shape ns
)
21904 gas_assert (ns
== NS_PQI
21912 || ns
== NS_PFFFI
);
21913 if (ns
== NS_PQI
|| ns
== NS_PQQI
|| ns
== NS_PQQQI
)
21915 if (ns
== NS_PDI
|| ns
== NS_PDDI
|| ns
== NS_PDDDI
)
21920 #define vcx_size_pos 24
21921 #define vcx_vec_pos 6
21923 vcx_handle_shape (enum vcx_reg_type reg_type
)
21926 if (reg_type
== q_reg
)
21927 inst
.instruction
|= 1 << vcx_vec_pos
;
21928 else if (reg_type
== d_reg
)
21929 inst
.instruction
|= 1 << vcx_size_pos
;
21933 The documentation says that the Q registers are encoded as 2*N in the D:Vd
21934 bits (or equivalent for N and M registers).
21935 Similarly the D registers are encoded as N in D:Vd bits.
21936 While the S registers are encoded as N in the Vd:D bits.
21938 Taking into account the maximum values of these registers we can see a
21939 nicer pattern for calculation:
21940 Q -> 7, D -> 15, S -> 31
21942 If we say that everything is encoded in the Vd:D bits, then we can say
21943 that Q is encoded as 4*N, and D is encoded as 2*N.
21944 This way the bits will end up the same, and calculation is simpler.
21945 (calculation is now:
21946 1. Multiply by a number determined by the register letter.
21947 2. Encode resulting number in Vd:D bits.)
21949 This is made a little more complicated by automatic handling of 'Q'
21950 registers elsewhere, which means the register number is already 2*N where
21951 N is the number the user wrote after the register letter.
21956 #undef vcx_size_pos
21959 vcx_ensure_register_in_range (unsigned R
, enum vcx_reg_type reg_type
)
21961 if (reg_type
== q_reg
)
21963 gas_assert (R
% 2 == 0);
21964 constraint (R
>= 16, _("'q' register must be in range 0-7"));
21966 else if (reg_type
== d_reg
)
21967 constraint (R
>= 16, _("'d' register must be in range 0-15"));
21969 constraint (R
>= 32, _("'s' register must be in range 0-31"));
21972 static void (*vcx_assign_vec
[3]) (unsigned) = {
21979 vcx_handle_register_arguments (unsigned num_registers
,
21980 enum vcx_reg_type reg_type
)
21983 unsigned reg_mult
= vcx_handle_shape (reg_type
);
21984 for (i
= 0; i
< num_registers
; i
++)
21986 R
= inst
.operands
[i
+1].reg
;
21987 vcx_ensure_register_in_range (R
, reg_type
);
21988 if (num_registers
== 3 && i
> 0)
21991 vcx_assign_vec
[1] (R
* reg_mult
);
21993 vcx_assign_vec
[2] (R
* reg_mult
);
21996 vcx_assign_vec
[i
](R
* reg_mult
);
22001 vcx_handle_insn_block (enum vcx_reg_type reg_type
)
22003 if (reg_type
== q_reg
)
22004 if (inst
.cond
> COND_ALWAYS
)
22005 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
22007 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
22008 else if (inst
.cond
== COND_ALWAYS
)
22009 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22011 inst
.error
= BAD_NOT_IT
;
22015 vcx_handle_common_checks (unsigned num_args
, enum neon_shape rs
)
22017 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
22018 cde_handle_coproc ();
22019 enum vcx_reg_type reg_type
= vcx_get_reg_type (rs
);
22020 vcx_handle_register_arguments (num_args
, reg_type
);
22021 vcx_handle_insn_block (reg_type
);
22022 if (reg_type
== q_reg
)
22023 constraint (!mark_feature_used (&mve_ext
),
22024 _("vcx instructions with Q registers require MVE"));
22026 constraint (!(ARM_FSET_CPU_SUBSET (armv8m_fp
, cpu_variant
)
22027 && mark_feature_used (&armv8m_fp
))
22028 && !mark_feature_used (&mve_ext
),
22029 _("vcx instructions with S or D registers require either MVE"
22030 " or Armv8-M floating point extension."));
22036 enum neon_shape rs
= neon_select_shape (NS_PQI
, NS_PDI
, NS_PFI
, NS_NULL
);
22037 vcx_handle_common_checks (1, rs
);
22039 unsigned imm
= inst
.operands
[2].imm
;
22040 inst
.instruction
|= (imm
& 0x03f);
22041 inst
.instruction
|= (imm
& 0x040) << 1;
22042 inst
.instruction
|= (imm
& 0x780) << 9;
22044 constraint (imm
>= 2048,
22045 _("vcx1 with S or D registers takes immediate within 0-2047"));
22046 inst
.instruction
|= (imm
& 0x800) << 13;
22052 enum neon_shape rs
= neon_select_shape (NS_PQQI
, NS_PDDI
, NS_PFFI
, NS_NULL
);
22053 vcx_handle_common_checks (2, rs
);
22055 unsigned imm
= inst
.operands
[3].imm
;
22056 inst
.instruction
|= (imm
& 0x01) << 4;
22057 inst
.instruction
|= (imm
& 0x02) << 6;
22058 inst
.instruction
|= (imm
& 0x3c) << 14;
22060 constraint (imm
>= 64,
22061 _("vcx2 with S or D registers takes immediate within 0-63"));
22062 inst
.instruction
|= (imm
& 0x40) << 18;
22068 enum neon_shape rs
= neon_select_shape (NS_PQQQI
, NS_PDDDI
, NS_PFFFI
, NS_NULL
);
22069 vcx_handle_common_checks (3, rs
);
22071 unsigned imm
= inst
.operands
[4].imm
;
22072 inst
.instruction
|= (imm
& 0x1) << 4;
22073 inst
.instruction
|= (imm
& 0x6) << 19;
22074 if (rs
!= NS_PQQQI
)
22075 constraint (imm
>= 8,
22076 _("vcx2 with S or D registers takes immediate within 0-7"));
22077 inst
.instruction
|= (imm
& 0x8) << 21;
22080 /* Crypto v1 instructions. */
22082 do_crypto_2op_1 (unsigned elttype
, int op
)
22084 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22086 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
22092 NEON_ENCODE (INTEGER
, inst
);
22093 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
22094 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
22095 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
22096 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
22098 inst
.instruction
|= op
<< 6;
22101 inst
.instruction
|= 0xfc000000;
22103 inst
.instruction
|= 0xf0000000;
22107 do_crypto_3op_1 (int u
, int op
)
22109 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22111 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
22112 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
22117 NEON_ENCODE (INTEGER
, inst
);
22118 neon_three_same (1, u
, 8 << op
);
22124 do_crypto_2op_1 (N_8
, 0);
22130 do_crypto_2op_1 (N_8
, 1);
22136 do_crypto_2op_1 (N_8
, 2);
22142 do_crypto_2op_1 (N_8
, 3);
22148 do_crypto_3op_1 (0, 0);
22154 do_crypto_3op_1 (0, 1);
22160 do_crypto_3op_1 (0, 2);
22166 do_crypto_3op_1 (0, 3);
22172 do_crypto_3op_1 (1, 0);
22178 do_crypto_3op_1 (1, 1);
22182 do_sha256su1 (void)
22184 do_crypto_3op_1 (1, 2);
22190 do_crypto_2op_1 (N_32
, -1);
22196 do_crypto_2op_1 (N_32
, 0);
22200 do_sha256su0 (void)
22202 do_crypto_2op_1 (N_32
, 1);
22206 do_crc32_1 (unsigned int poly
, unsigned int sz
)
22208 unsigned int Rd
= inst
.operands
[0].reg
;
22209 unsigned int Rn
= inst
.operands
[1].reg
;
22210 unsigned int Rm
= inst
.operands
[2].reg
;
22212 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22213 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
22214 inst
.instruction
|= LOW4 (Rn
) << 16;
22215 inst
.instruction
|= LOW4 (Rm
);
22216 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
22217 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
22219 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
22220 as_warn (UNPRED_REG ("r15"));
22262 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
22264 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
22265 do_vfp_sp_dp_cvt ();
22266 do_vfp_cond_or_thumb ();
22272 enum neon_shape rs
;
22273 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22274 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22275 if (inst
.operands
[2].isscalar
)
22277 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
22278 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22280 inst
.instruction
|= (1 << 25);
22281 int index
= inst
.operands
[2].reg
& 0xf;
22282 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
22283 inst
.operands
[2].reg
>>= 4;
22284 constraint (!(inst
.operands
[2].reg
< 16),
22285 _("indexed register must be less than 16"));
22286 neon_three_args (rs
== NS_QQS
);
22287 inst
.instruction
|= (index
<< 5);
22291 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
22292 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22293 neon_three_args (rs
== NS_QQQ
);
22300 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
22301 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22303 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22304 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22306 neon_three_args (1);
22310 /* Overall per-instruction processing. */
22312 /* We need to be able to fix up arbitrary expressions in some statements.
22313 This is so that we can handle symbols that are an arbitrary distance from
22314 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
22315 which returns part of an address in a form which will be valid for
22316 a data instruction. We do this by pushing the expression into a symbol
22317 in the expr_section, and creating a fix for that. */
22320 fix_new_arm (fragS
* frag
,
22334 /* Create an absolute valued symbol, so we have something to
22335 refer to in the object file. Unfortunately for us, gas's
22336 generic expression parsing will already have folded out
22337 any use of .set foo/.type foo %function that may have
22338 been used to set type information of the target location,
22339 that's being specified symbolically. We have to presume
22340 the user knows what they are doing. */
22344 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
22346 symbol
= symbol_find_or_make (name
);
22347 S_SET_SEGMENT (symbol
, absolute_section
);
22348 symbol_set_frag (symbol
, &zero_address_frag
);
22349 S_SET_VALUE (symbol
, exp
->X_add_number
);
22350 exp
->X_op
= O_symbol
;
22351 exp
->X_add_symbol
= symbol
;
22352 exp
->X_add_number
= 0;
22358 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
22359 (enum bfd_reloc_code_real
) reloc
);
22363 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
22364 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
22368 /* Mark whether the fix is to a THUMB instruction, or an ARM
22370 new_fix
->tc_fix_data
= thumb_mode
;
22373 /* Create a frg for an instruction requiring relaxation. */
22375 output_relax_insn (void)
22381 /* The size of the instruction is unknown, so tie the debug info to the
22382 start of the instruction. */
22383 dwarf2_emit_insn (0);
22385 switch (inst
.relocs
[0].exp
.X_op
)
22388 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
22389 offset
= inst
.relocs
[0].exp
.X_add_number
;
22393 offset
= inst
.relocs
[0].exp
.X_add_number
;
22396 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
22400 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
22401 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
22402 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
22405 /* Write a 32-bit thumb instruction to buf. */
22407 put_thumb32_insn (char * buf
, unsigned long insn
)
22409 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
22410 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
22414 output_inst (const char * str
)
22420 as_bad ("%s -- `%s'", inst
.error
, str
);
22425 output_relax_insn ();
22428 if (inst
.size
== 0)
22431 to
= frag_more (inst
.size
);
22432 /* PR 9814: Record the thumb mode into the current frag so that we know
22433 what type of NOP padding to use, if necessary. We override any previous
22434 setting so that if the mode has changed then the NOPS that we use will
22435 match the encoding of the last instruction in the frag. */
22436 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22438 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
22440 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
22441 put_thumb32_insn (to
, inst
.instruction
);
22443 else if (inst
.size
> INSN_SIZE
)
22445 gas_assert (inst
.size
== (2 * INSN_SIZE
));
22446 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
22447 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
22450 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
22453 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22455 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
22456 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
22457 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
22458 inst
.relocs
[r
].type
);
22461 dwarf2_emit_insn (inst
.size
);
22465 output_it_inst (int cond
, int mask
, char * to
)
22467 unsigned long instruction
= 0xbf00;
22470 instruction
|= mask
;
22471 instruction
|= cond
<< 4;
22475 to
= frag_more (2);
22477 dwarf2_emit_insn (2);
22481 md_number_to_chars (to
, instruction
, 2);
22486 /* Tag values used in struct asm_opcode's tag field. */
22489 OT_unconditional
, /* Instruction cannot be conditionalized.
22490 The ARM condition field is still 0xE. */
22491 OT_unconditionalF
, /* Instruction cannot be conditionalized
22492 and carries 0xF in its ARM condition field. */
22493 OT_csuffix
, /* Instruction takes a conditional suffix. */
22494 OT_csuffixF
, /* Some forms of the instruction take a scalar
22495 conditional suffix, others place 0xF where the
22496 condition field would be, others take a vector
22497 conditional suffix. */
22498 OT_cinfix3
, /* Instruction takes a conditional infix,
22499 beginning at character index 3. (In
22500 unified mode, it becomes a suffix.) */
22501 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
22502 tsts, cmps, cmns, and teqs. */
22503 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
22504 character index 3, even in unified mode. Used for
22505 legacy instructions where suffix and infix forms
22506 may be ambiguous. */
22507 OT_csuf_or_in3
, /* Instruction takes either a conditional
22508 suffix or an infix at character index 3. */
22509 OT_odd_infix_unc
, /* This is the unconditional variant of an
22510 instruction that takes a conditional infix
22511 at an unusual position. In unified mode,
22512 this variant will accept a suffix. */
22513 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
22514 are the conditional variants of instructions that
22515 take conditional infixes in unusual positions.
22516 The infix appears at character index
22517 (tag - OT_odd_infix_0). These are not accepted
22518 in unified mode. */
22521 /* Subroutine of md_assemble, responsible for looking up the primary
22522 opcode from the mnemonic the user wrote. STR points to the
22523 beginning of the mnemonic.
22525 This is not simply a hash table lookup, because of conditional
22526 variants. Most instructions have conditional variants, which are
22527 expressed with a _conditional affix_ to the mnemonic. If we were
22528 to encode each conditional variant as a literal string in the opcode
22529 table, it would have approximately 20,000 entries.
22531 Most mnemonics take this affix as a suffix, and in unified syntax,
22532 'most' is upgraded to 'all'. However, in the divided syntax, some
22533 instructions take the affix as an infix, notably the s-variants of
22534 the arithmetic instructions. Of those instructions, all but six
22535 have the infix appear after the third character of the mnemonic.
22537 Accordingly, the algorithm for looking up primary opcodes given
22540 1. Look up the identifier in the opcode table.
22541 If we find a match, go to step U.
22543 2. Look up the last two characters of the identifier in the
22544 conditions table. If we find a match, look up the first N-2
22545 characters of the identifier in the opcode table. If we
22546 find a match, go to step CE.
22548 3. Look up the fourth and fifth characters of the identifier in
22549 the conditions table. If we find a match, extract those
22550 characters from the identifier, and look up the remaining
22551 characters in the opcode table. If we find a match, go
22556 U. Examine the tag field of the opcode structure, in case this is
22557 one of the six instructions with its conditional infix in an
22558 unusual place. If it is, the tag tells us where to find the
22559 infix; look it up in the conditions table and set inst.cond
22560 accordingly. Otherwise, this is an unconditional instruction.
22561 Again set inst.cond accordingly. Return the opcode structure.
22563 CE. Examine the tag field to make sure this is an instruction that
22564 should receive a conditional suffix. If it is not, fail.
22565 Otherwise, set inst.cond from the suffix we already looked up,
22566 and return the opcode structure.
22568 CM. Examine the tag field to make sure this is an instruction that
22569 should receive a conditional infix after the third character.
22570 If it is not, fail. Otherwise, undo the edits to the current
22571 line of input and proceed as for case CE. */
22573 static const struct asm_opcode
*
22574 opcode_lookup (char **str
)
22578 const struct asm_opcode
*opcode
;
22579 const struct asm_cond
*cond
;
22582 /* Scan up to the end of the mnemonic, which must end in white space,
22583 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
22584 for (base
= end
= *str
; *end
!= '\0'; end
++)
22585 if (*end
== ' ' || *end
== '.')
22591 /* Handle a possible width suffix and/or Neon type suffix. */
22596 /* The .w and .n suffixes are only valid if the unified syntax is in
22598 if (unified_syntax
&& end
[1] == 'w')
22600 else if (unified_syntax
&& end
[1] == 'n')
22605 inst
.vectype
.elems
= 0;
22607 *str
= end
+ offset
;
22609 if (end
[offset
] == '.')
22611 /* See if we have a Neon type suffix (possible in either unified or
22612 non-unified ARM syntax mode). */
22613 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
22616 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
22622 /* Look for unaffixed or special-case affixed mnemonic. */
22623 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22628 if (opcode
->tag
< OT_odd_infix_0
)
22630 inst
.cond
= COND_ALWAYS
;
22634 if (warn_on_deprecated
&& unified_syntax
)
22635 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22636 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
22637 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22640 inst
.cond
= cond
->value
;
22643 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
22645 /* Cannot have a conditional suffix on a mnemonic of less than a character.
22647 if (end
- base
< 2)
22650 cond
= (const struct asm_cond
*) str_hash_find_n (arm_vcond_hsh
, affix
, 1);
22651 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22653 /* If this opcode can not be vector predicated then don't accept it with a
22654 vector predication code. */
22655 if (opcode
&& !opcode
->mayBeVecPred
)
22658 if (!opcode
|| !cond
)
22660 /* Cannot have a conditional suffix on a mnemonic of less than two
22662 if (end
- base
< 3)
22665 /* Look for suffixed mnemonic. */
22667 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22668 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22672 if (opcode
&& cond
)
22675 switch (opcode
->tag
)
22677 case OT_cinfix3_legacy
:
22678 /* Ignore conditional suffixes matched on infix only mnemonics. */
22682 case OT_cinfix3_deprecated
:
22683 case OT_odd_infix_unc
:
22684 if (!unified_syntax
)
22686 /* Fall through. */
22690 case OT_csuf_or_in3
:
22691 inst
.cond
= cond
->value
;
22694 case OT_unconditional
:
22695 case OT_unconditionalF
:
22697 inst
.cond
= cond
->value
;
22700 /* Delayed diagnostic. */
22701 inst
.error
= BAD_COND
;
22702 inst
.cond
= COND_ALWAYS
;
22711 /* Cannot have a usual-position infix on a mnemonic of less than
22712 six characters (five would be a suffix). */
22713 if (end
- base
< 6)
22716 /* Look for infixed mnemonic in the usual position. */
22718 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22722 memcpy (save
, affix
, 2);
22723 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
22724 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22726 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
22727 memcpy (affix
, save
, 2);
22730 && (opcode
->tag
== OT_cinfix3
22731 || opcode
->tag
== OT_cinfix3_deprecated
22732 || opcode
->tag
== OT_csuf_or_in3
22733 || opcode
->tag
== OT_cinfix3_legacy
))
22736 if (warn_on_deprecated
&& unified_syntax
22737 && (opcode
->tag
== OT_cinfix3
22738 || opcode
->tag
== OT_cinfix3_deprecated
))
22739 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22741 inst
.cond
= cond
->value
;
22748 /* This function generates an initial IT instruction, leaving its block
22749 virtually open for the new instructions. Eventually,
22750 the mask will be updated by now_pred_add_mask () each time
22751 a new instruction needs to be included in the IT block.
22752 Finally, the block is closed with close_automatic_it_block ().
22753 The block closure can be requested either from md_assemble (),
22754 a tencode (), or due to a label hook. */
22757 new_automatic_it_block (int cond
)
22759 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
22760 now_pred
.mask
= 0x18;
22761 now_pred
.cc
= cond
;
22762 now_pred
.block_length
= 1;
22763 mapping_state (MAP_THUMB
);
22764 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
22765 now_pred
.warn_deprecated
= FALSE
;
22766 now_pred
.insn_cond
= TRUE
;
22769 /* Close an automatic IT block.
22770 See comments in new_automatic_it_block (). */
22773 close_automatic_it_block (void)
22775 now_pred
.mask
= 0x10;
22776 now_pred
.block_length
= 0;
22779 /* Update the mask of the current automatically-generated IT
22780 instruction. See comments in new_automatic_it_block (). */
22783 now_pred_add_mask (int cond
)
22785 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
22786 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
22787 | ((bitvalue) << (nbit)))
22788 const int resulting_bit
= (cond
& 1);
22790 now_pred
.mask
&= 0xf;
22791 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22793 (5 - now_pred
.block_length
));
22794 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22796 ((5 - now_pred
.block_length
) - 1));
22797 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
22800 #undef SET_BIT_VALUE
22803 /* The IT blocks handling machinery is accessed through the these functions:
22804 it_fsm_pre_encode () from md_assemble ()
22805 set_pred_insn_type () optional, from the tencode functions
22806 set_pred_insn_type_last () ditto
22807 in_pred_block () ditto
22808 it_fsm_post_encode () from md_assemble ()
22809 force_automatic_it_block_close () from label handling functions
22812 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
22813 initializing the IT insn type with a generic initial value depending
22814 on the inst.condition.
22815 2) During the tencode function, two things may happen:
22816 a) The tencode function overrides the IT insn type by
22817 calling either set_pred_insn_type (type) or
22818 set_pred_insn_type_last ().
22819 b) The tencode function queries the IT block state by
22820 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22822 Both set_pred_insn_type and in_pred_block run the internal FSM state
22823 handling function (handle_pred_state), because: a) setting the IT insn
22824 type may incur in an invalid state (exiting the function),
22825 and b) querying the state requires the FSM to be updated.
22826 Specifically we want to avoid creating an IT block for conditional
22827 branches, so it_fsm_pre_encode is actually a guess and we can't
22828 determine whether an IT block is required until the tencode () routine
22829 has decided what type of instruction this actually it.
22830 Because of this, if set_pred_insn_type and in_pred_block have to be
22831 used, set_pred_insn_type has to be called first.
22833 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22834 that determines the insn IT type depending on the inst.cond code.
22835 When a tencode () routine encodes an instruction that can be
22836 either outside an IT block, or, in the case of being inside, has to be
22837 the last one, set_pred_insn_type_last () will determine the proper
22838 IT instruction type based on the inst.cond code. Otherwise,
22839 set_pred_insn_type can be called for overriding that logic or
22840 for covering other cases.
22842 Calling handle_pred_state () may not transition the IT block state to
22843 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22844 still queried. Instead, if the FSM determines that the state should
22845 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22846 after the tencode () function: that's what it_fsm_post_encode () does.
22848 Since in_pred_block () calls the state handling function to get an
22849 updated state, an error may occur (due to invalid insns combination).
22850 In that case, inst.error is set.
22851 Therefore, inst.error has to be checked after the execution of
22852 the tencode () routine.
22854 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22855 any pending state change (if any) that didn't take place in
22856 handle_pred_state () as explained above. */
22859 it_fsm_pre_encode (void)
22861 if (inst
.cond
!= COND_ALWAYS
)
22862 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22864 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22866 now_pred
.state_handled
= 0;
22869 /* IT state FSM handling function. */
22870 /* MVE instructions and non-MVE instructions are handled differently because of
22871 the introduction of VPT blocks.
22872 Specifications say that any non-MVE instruction inside a VPT block is
22873 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22874 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22875 few exceptions we have MVE_UNPREDICABLE_INSN.
22876 The error messages provided depending on the different combinations possible
22877 are described in the cases below:
22878 For 'most' MVE instructions:
22879 1) In an IT block, with an IT code: syntax error
22880 2) In an IT block, with a VPT code: error: must be in a VPT block
22881 3) In an IT block, with no code: warning: UNPREDICTABLE
22882 4) In a VPT block, with an IT code: syntax error
22883 5) In a VPT block, with a VPT code: OK!
22884 6) In a VPT block, with no code: error: missing code
22885 7) Outside a pred block, with an IT code: error: syntax error
22886 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22887 9) Outside a pred block, with no code: OK!
22888 For non-MVE instructions:
22889 10) In an IT block, with an IT code: OK!
22890 11) In an IT block, with a VPT code: syntax error
22891 12) In an IT block, with no code: error: missing code
22892 13) In a VPT block, with an IT code: error: should be in an IT block
22893 14) In a VPT block, with a VPT code: syntax error
22894 15) In a VPT block, with no code: UNPREDICTABLE
22895 16) Outside a pred block, with an IT code: error: should be in an IT block
22896 17) Outside a pred block, with a VPT code: syntax error
22897 18) Outside a pred block, with no code: OK!
22902 handle_pred_state (void)
22904 now_pred
.state_handled
= 1;
22905 now_pred
.insn_cond
= FALSE
;
22907 switch (now_pred
.state
)
22909 case OUTSIDE_PRED_BLOCK
:
22910 switch (inst
.pred_insn_type
)
22912 case MVE_UNPREDICABLE_INSN
:
22913 case MVE_OUTSIDE_PRED_INSN
:
22914 if (inst
.cond
< COND_ALWAYS
)
22916 /* Case 7: Outside a pred block, with an IT code: error: syntax
22918 inst
.error
= BAD_SYNTAX
;
22921 /* Case 9: Outside a pred block, with no code: OK! */
22923 case OUTSIDE_PRED_INSN
:
22924 if (inst
.cond
> COND_ALWAYS
)
22926 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22928 inst
.error
= BAD_SYNTAX
;
22931 /* Case 18: Outside a pred block, with no code: OK! */
22934 case INSIDE_VPT_INSN
:
22935 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22937 inst
.error
= BAD_OUT_VPT
;
22940 case INSIDE_IT_INSN
:
22941 case INSIDE_IT_LAST_INSN
:
22942 if (inst
.cond
< COND_ALWAYS
)
22944 /* Case 16: Outside a pred block, with an IT code: error: should
22945 be in an IT block. */
22946 if (thumb_mode
== 0)
22949 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22950 as_tsktsk (_("Warning: conditional outside an IT block"\
22955 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22956 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22958 /* Automatically generate the IT instruction. */
22959 new_automatic_it_block (inst
.cond
);
22960 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22961 close_automatic_it_block ();
22965 inst
.error
= BAD_OUT_IT
;
22971 else if (inst
.cond
> COND_ALWAYS
)
22973 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22975 inst
.error
= BAD_SYNTAX
;
22980 case IF_INSIDE_IT_LAST_INSN
:
22981 case NEUTRAL_IT_INSN
:
22985 if (inst
.cond
!= COND_ALWAYS
)
22986 first_error (BAD_SYNTAX
);
22987 now_pred
.state
= MANUAL_PRED_BLOCK
;
22988 now_pred
.block_length
= 0;
22989 now_pred
.type
= VECTOR_PRED
;
22993 now_pred
.state
= MANUAL_PRED_BLOCK
;
22994 now_pred
.block_length
= 0;
22995 now_pred
.type
= SCALAR_PRED
;
23000 case AUTOMATIC_PRED_BLOCK
:
23001 /* Three things may happen now:
23002 a) We should increment current it block size;
23003 b) We should close current it block (closing insn or 4 insns);
23004 c) We should close current it block and start a new one (due
23005 to incompatible conditions or
23006 4 insns-length block reached). */
23008 switch (inst
.pred_insn_type
)
23010 case INSIDE_VPT_INSN
:
23012 case MVE_UNPREDICABLE_INSN
:
23013 case MVE_OUTSIDE_PRED_INSN
:
23015 case OUTSIDE_PRED_INSN
:
23016 /* The closure of the block shall happen immediately,
23017 so any in_pred_block () call reports the block as closed. */
23018 force_automatic_it_block_close ();
23021 case INSIDE_IT_INSN
:
23022 case INSIDE_IT_LAST_INSN
:
23023 case IF_INSIDE_IT_LAST_INSN
:
23024 now_pred
.block_length
++;
23026 if (now_pred
.block_length
> 4
23027 || !now_pred_compatible (inst
.cond
))
23029 force_automatic_it_block_close ();
23030 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
23031 new_automatic_it_block (inst
.cond
);
23035 now_pred
.insn_cond
= TRUE
;
23036 now_pred_add_mask (inst
.cond
);
23039 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
23040 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
23041 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
23042 close_automatic_it_block ();
23046 case NEUTRAL_IT_INSN
:
23047 now_pred
.block_length
++;
23048 now_pred
.insn_cond
= TRUE
;
23050 if (now_pred
.block_length
> 4)
23051 force_automatic_it_block_close ();
23053 now_pred_add_mask (now_pred
.cc
& 1);
23057 close_automatic_it_block ();
23058 now_pred
.state
= MANUAL_PRED_BLOCK
;
23063 case MANUAL_PRED_BLOCK
:
23066 if (now_pred
.type
== SCALAR_PRED
)
23068 /* Check conditional suffixes. */
23069 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
23070 now_pred
.mask
<<= 1;
23071 now_pred
.mask
&= 0x1f;
23072 is_last
= (now_pred
.mask
== 0x10);
23076 now_pred
.cc
^= (now_pred
.mask
>> 4);
23077 cond
= now_pred
.cc
+ 0xf;
23078 now_pred
.mask
<<= 1;
23079 now_pred
.mask
&= 0x1f;
23080 is_last
= now_pred
.mask
== 0x10;
23082 now_pred
.insn_cond
= TRUE
;
23084 switch (inst
.pred_insn_type
)
23086 case OUTSIDE_PRED_INSN
:
23087 if (now_pred
.type
== SCALAR_PRED
)
23089 if (inst
.cond
== COND_ALWAYS
)
23091 /* Case 12: In an IT block, with no code: error: missing
23093 inst
.error
= BAD_NOT_IT
;
23096 else if (inst
.cond
> COND_ALWAYS
)
23098 /* Case 11: In an IT block, with a VPT code: syntax error.
23100 inst
.error
= BAD_SYNTAX
;
23103 else if (thumb_mode
)
23105 /* This is for some special cases where a non-MVE
23106 instruction is not allowed in an IT block, such as cbz,
23107 but are put into one with a condition code.
23108 You could argue this should be a syntax error, but we
23109 gave the 'not allowed in IT block' diagnostic in the
23110 past so we will keep doing so. */
23111 inst
.error
= BAD_NOT_IT
;
23118 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
23119 as_tsktsk (MVE_NOT_VPT
);
23122 case MVE_OUTSIDE_PRED_INSN
:
23123 if (now_pred
.type
== SCALAR_PRED
)
23125 if (inst
.cond
== COND_ALWAYS
)
23127 /* Case 3: In an IT block, with no code: warning:
23129 as_tsktsk (MVE_NOT_IT
);
23132 else if (inst
.cond
< COND_ALWAYS
)
23134 /* Case 1: In an IT block, with an IT code: syntax error.
23136 inst
.error
= BAD_SYNTAX
;
23144 if (inst
.cond
< COND_ALWAYS
)
23146 /* Case 4: In a VPT block, with an IT code: syntax error.
23148 inst
.error
= BAD_SYNTAX
;
23151 else if (inst
.cond
== COND_ALWAYS
)
23153 /* Case 6: In a VPT block, with no code: error: missing
23155 inst
.error
= BAD_NOT_VPT
;
23163 case MVE_UNPREDICABLE_INSN
:
23164 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
23166 case INSIDE_IT_INSN
:
23167 if (inst
.cond
> COND_ALWAYS
)
23169 /* Case 11: In an IT block, with a VPT code: syntax error. */
23170 /* Case 14: In a VPT block, with a VPT code: syntax error. */
23171 inst
.error
= BAD_SYNTAX
;
23174 else if (now_pred
.type
== SCALAR_PRED
)
23176 /* Case 10: In an IT block, with an IT code: OK! */
23177 if (cond
!= inst
.cond
)
23179 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
23186 /* Case 13: In a VPT block, with an IT code: error: should be
23188 inst
.error
= BAD_OUT_IT
;
23193 case INSIDE_VPT_INSN
:
23194 if (now_pred
.type
== SCALAR_PRED
)
23196 /* Case 2: In an IT block, with a VPT code: error: must be in a
23198 inst
.error
= BAD_OUT_VPT
;
23201 /* Case 5: In a VPT block, with a VPT code: OK! */
23202 else if (cond
!= inst
.cond
)
23204 inst
.error
= BAD_VPT_COND
;
23208 case INSIDE_IT_LAST_INSN
:
23209 case IF_INSIDE_IT_LAST_INSN
:
23210 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
23212 /* Case 4: In a VPT block, with an IT code: syntax error. */
23213 /* Case 11: In an IT block, with a VPT code: syntax error. */
23214 inst
.error
= BAD_SYNTAX
;
23217 else if (cond
!= inst
.cond
)
23219 inst
.error
= BAD_IT_COND
;
23224 inst
.error
= BAD_BRANCH
;
23229 case NEUTRAL_IT_INSN
:
23230 /* The BKPT instruction is unconditional even in a IT or VPT
23235 if (now_pred
.type
== SCALAR_PRED
)
23237 inst
.error
= BAD_IT_IT
;
23240 /* fall through. */
23242 if (inst
.cond
== COND_ALWAYS
)
23244 /* Executing a VPT/VPST instruction inside an IT block or a
23245 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
23247 if (now_pred
.type
== SCALAR_PRED
)
23248 as_tsktsk (MVE_NOT_IT
);
23250 as_tsktsk (MVE_NOT_VPT
);
23255 /* VPT/VPST do not accept condition codes. */
23256 inst
.error
= BAD_SYNTAX
;
23267 struct depr_insn_mask
23269 unsigned long pattern
;
23270 unsigned long mask
;
23271 const char* description
;
23274 /* List of 16-bit instruction patterns deprecated in an IT block in
23276 static const struct depr_insn_mask depr_it_insns
[] = {
23277 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
23278 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
23279 { 0xa000, 0xb800, N_("ADR") },
23280 { 0x4800, 0xf800, N_("Literal loads") },
23281 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
23282 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
23283 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
23284 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
23285 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
23290 it_fsm_post_encode (void)
23294 if (!now_pred
.state_handled
)
23295 handle_pred_state ();
23297 if (now_pred
.insn_cond
23298 && warn_on_restrict_it
23299 && !now_pred
.warn_deprecated
23300 && warn_on_deprecated
23301 && (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
23302 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8r
))
23303 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
23305 if (inst
.instruction
>= 0x10000)
23307 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
23308 "performance deprecated in ARMv8-A and ARMv8-R"));
23309 now_pred
.warn_deprecated
= TRUE
;
23313 const struct depr_insn_mask
*p
= depr_it_insns
;
23315 while (p
->mask
!= 0)
23317 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
23319 as_tsktsk (_("IT blocks containing 16-bit Thumb "
23320 "instructions of the following class are "
23321 "performance deprecated in ARMv8-A and "
23322 "ARMv8-R: %s"), p
->description
);
23323 now_pred
.warn_deprecated
= TRUE
;
23331 if (now_pred
.block_length
> 1)
23333 as_tsktsk (_("IT blocks containing more than one conditional "
23334 "instruction are performance deprecated in ARMv8-A and "
23336 now_pred
.warn_deprecated
= TRUE
;
23340 is_last
= (now_pred
.mask
== 0x10);
23343 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23349 force_automatic_it_block_close (void)
23351 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
23353 close_automatic_it_block ();
23354 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23360 in_pred_block (void)
23362 if (!now_pred
.state_handled
)
23363 handle_pred_state ();
23365 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
23368 /* Whether OPCODE only has T32 encoding. Since this function is only used by
23369 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
23370 here, hence the "known" in the function name. */
23373 known_t32_only_insn (const struct asm_opcode
*opcode
)
23375 /* Original Thumb-1 wide instruction. */
23376 if (opcode
->tencode
== do_t_blx
23377 || opcode
->tencode
== do_t_branch23
23378 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
23379 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
23382 /* Wide-only instruction added to ARMv8-M Baseline. */
23383 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
23384 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
23385 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
23386 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
23392 /* Whether wide instruction variant can be used if available for a valid OPCODE
23396 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
23398 if (known_t32_only_insn (opcode
))
23401 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
23402 of variant T3 of B.W is checked in do_t_branch. */
23403 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23404 && opcode
->tencode
== do_t_branch
)
23407 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
23408 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23409 && opcode
->tencode
== do_t_mov_cmp
23410 /* Make sure CMP instruction is not affected. */
23411 && opcode
->aencode
== do_mov
)
23414 /* Wide instruction variants of all instructions with narrow *and* wide
23415 variants become available with ARMv6t2. Other opcodes are either
23416 narrow-only or wide-only and are thus available if OPCODE is valid. */
23417 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
23420 /* OPCODE with narrow only instruction variant or wide variant not
23426 md_assemble (char *str
)
23429 const struct asm_opcode
* opcode
;
23431 /* Align the previous label if needed. */
23432 if (last_label_seen
!= NULL
)
23434 symbol_set_frag (last_label_seen
, frag_now
);
23435 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
23436 S_SET_SEGMENT (last_label_seen
, now_seg
);
23439 memset (&inst
, '\0', sizeof (inst
));
23441 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
23442 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
23444 opcode
= opcode_lookup (&p
);
23447 /* It wasn't an instruction, but it might be a register alias of
23448 the form alias .req reg, or a Neon .dn/.qn directive. */
23449 if (! create_register_alias (str
, p
)
23450 && ! create_neon_reg_alias (str
, p
))
23451 as_bad (_("bad instruction `%s'"), str
);
23456 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
23457 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
23459 /* The value which unconditional instructions should have in place of the
23460 condition field. */
23461 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
23465 arm_feature_set variant
;
23467 variant
= cpu_variant
;
23468 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
23469 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
23470 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
23471 /* Check that this instruction is supported for this CPU. */
23472 if (!opcode
->tvariant
23473 || (thumb_mode
== 1
23474 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
23476 if (opcode
->tencode
== do_t_swi
)
23477 as_bad (_("SVC is not permitted on this architecture"));
23479 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
23482 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
23483 && opcode
->tencode
!= do_t_branch
)
23485 as_bad (_("Thumb does not support conditional execution"));
23489 /* Two things are addressed here:
23490 1) Implicit require narrow instructions on Thumb-1.
23491 This avoids relaxation accidentally introducing Thumb-2
23493 2) Reject wide instructions in non Thumb-2 cores.
23495 Only instructions with narrow and wide variants need to be handled
23496 but selecting all non wide-only instructions is easier. */
23497 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
23498 && !t32_insn_ok (variant
, opcode
))
23500 if (inst
.size_req
== 0)
23502 else if (inst
.size_req
== 4)
23504 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
23505 as_bad (_("selected processor does not support 32bit wide "
23506 "variant of instruction `%s'"), str
);
23508 as_bad (_("selected processor does not support `%s' in "
23509 "Thumb-2 mode"), str
);
23514 inst
.instruction
= opcode
->tvalue
;
23516 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
23518 /* Prepare the pred_insn_type for those encodings that don't set
23520 it_fsm_pre_encode ();
23522 opcode
->tencode ();
23524 it_fsm_post_encode ();
23527 if (!(inst
.error
|| inst
.relax
))
23529 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
23530 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
23531 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
23533 as_bad (_("cannot honor width suffix -- `%s'"), str
);
23538 /* Something has gone badly wrong if we try to relax a fixed size
23540 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
23542 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23543 *opcode
->tvariant
);
23544 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
23545 set those bits when Thumb-2 32-bit instructions are seen. The impact
23546 of relaxable instructions will be considered later after we finish all
23548 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
23549 variant
= arm_arch_none
;
23551 variant
= cpu_variant
;
23552 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
23553 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23556 check_neon_suffixes
;
23560 mapping_state (MAP_THUMB
);
23563 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23567 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
23568 is_bx
= (opcode
->aencode
== do_bx
);
23570 /* Check that this instruction is supported for this CPU. */
23571 if (!(is_bx
&& fix_v4bx
)
23572 && !(opcode
->avariant
&&
23573 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
23575 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
23580 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
23584 inst
.instruction
= opcode
->avalue
;
23585 if (opcode
->tag
== OT_unconditionalF
)
23586 inst
.instruction
|= 0xFU
<< 28;
23588 inst
.instruction
|= inst
.cond
<< 28;
23589 inst
.size
= INSN_SIZE
;
23590 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
23592 it_fsm_pre_encode ();
23593 opcode
->aencode ();
23594 it_fsm_post_encode ();
23596 /* Arm mode bx is marked as both v4T and v5 because it's still required
23597 on a hypothetical non-thumb v5 core. */
23599 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
23601 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
23602 *opcode
->avariant
);
23604 check_neon_suffixes
;
23608 mapping_state (MAP_ARM
);
23613 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
23621 check_pred_blocks_finished (void)
23626 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
23627 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
23628 == MANUAL_PRED_BLOCK
)
23630 if (now_pred
.type
== SCALAR_PRED
)
23631 as_warn (_("section '%s' finished with an open IT block."),
23634 as_warn (_("section '%s' finished with an open VPT/VPST block."),
23638 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
23640 if (now_pred
.type
== SCALAR_PRED
)
23641 as_warn (_("file finished with an open IT block."));
23643 as_warn (_("file finished with an open VPT/VPST block."));
23648 /* Various frobbings of labels and their addresses. */
23651 arm_start_line_hook (void)
23653 last_label_seen
= NULL
;
23657 arm_frob_label (symbolS
* sym
)
23659 last_label_seen
= sym
;
23661 ARM_SET_THUMB (sym
, thumb_mode
);
23663 #if defined OBJ_COFF || defined OBJ_ELF
23664 ARM_SET_INTERWORK (sym
, support_interwork
);
23667 force_automatic_it_block_close ();
23669 /* Note - do not allow local symbols (.Lxxx) to be labelled
23670 as Thumb functions. This is because these labels, whilst
23671 they exist inside Thumb code, are not the entry points for
23672 possible ARM->Thumb calls. Also, these labels can be used
23673 as part of a computed goto or switch statement. eg gcc
23674 can generate code that looks like this:
23676 ldr r2, [pc, .Laaa]
23686 The first instruction loads the address of the jump table.
23687 The second instruction converts a table index into a byte offset.
23688 The third instruction gets the jump address out of the table.
23689 The fourth instruction performs the jump.
23691 If the address stored at .Laaa is that of a symbol which has the
23692 Thumb_Func bit set, then the linker will arrange for this address
23693 to have the bottom bit set, which in turn would mean that the
23694 address computation performed by the third instruction would end
23695 up with the bottom bit set. Since the ARM is capable of unaligned
23696 word loads, the instruction would then load the incorrect address
23697 out of the jump table, and chaos would ensue. */
23698 if (label_is_thumb_function_name
23699 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
23700 && (bfd_section_flags (now_seg
) & SEC_CODE
) != 0)
23702 /* When the address of a Thumb function is taken the bottom
23703 bit of that address should be set. This will allow
23704 interworking between Arm and Thumb functions to work
23707 THUMB_SET_FUNC (sym
, 1);
23709 label_is_thumb_function_name
= FALSE
;
23712 dwarf2_emit_label (sym
);
23716 arm_data_in_code (void)
23718 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
23720 *input_line_pointer
= '/';
23721 input_line_pointer
+= 5;
23722 *input_line_pointer
= 0;
23730 arm_canonicalize_symbol_name (char * name
)
23734 if (thumb_mode
&& (len
= strlen (name
)) > 5
23735 && streq (name
+ len
- 5, "/data"))
23736 *(name
+ len
- 5) = 0;
23741 /* Table of all register names defined by default. The user can
23742 define additional names with .req. Note that all register names
23743 should appear in both upper and lowercase variants. Some registers
23744 also have mixed-case names. */
23746 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
23747 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
23748 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
23749 #define REGSET(p,t) \
23750 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
23751 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
23752 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
23753 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
23754 #define REGSETH(p,t) \
23755 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
23756 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
23757 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
23758 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
23759 #define REGSET2(p,t) \
23760 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
23761 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
23762 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
23763 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
23764 #define SPLRBANK(base,bank,t) \
23765 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
23766 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
23767 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
23768 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
23769 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
23770 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
23772 static const struct reg_entry reg_names
[] =
23774 /* ARM integer registers. */
23775 REGSET(r
, RN
), REGSET(R
, RN
),
23777 /* ATPCS synonyms. */
23778 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
23779 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
23780 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
23782 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
23783 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
23784 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
23786 /* Well-known aliases. */
23787 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
23788 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
23790 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
23791 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
23793 /* Defining the new Zero register from ARMv8.1-M. */
23797 /* Coprocessor numbers. */
23798 REGSET(p
, CP
), REGSET(P
, CP
),
23800 /* Coprocessor register numbers. The "cr" variants are for backward
23802 REGSET(c
, CN
), REGSET(C
, CN
),
23803 REGSET(cr
, CN
), REGSET(CR
, CN
),
23805 /* ARM banked registers. */
23806 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
23807 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
23808 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
23809 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
23810 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
23811 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
23812 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
23814 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
23815 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
23816 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
23817 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
23818 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
23819 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
23820 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
23821 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
23823 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
23824 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
23825 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
23826 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
23827 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
23828 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
23829 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
23830 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23831 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23833 /* FPA registers. */
23834 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
23835 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
23837 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
23838 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
23840 /* VFP SP registers. */
23841 REGSET(s
,VFS
), REGSET(S
,VFS
),
23842 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
23844 /* VFP DP Registers. */
23845 REGSET(d
,VFD
), REGSET(D
,VFD
),
23846 /* Extra Neon DP registers. */
23847 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
23849 /* Neon QP registers. */
23850 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
23852 /* VFP control registers. */
23853 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
23854 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
23855 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
23856 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
23857 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
23858 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
23859 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
23860 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
23861 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
23862 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
23863 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
23865 /* Maverick DSP coprocessor registers. */
23866 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23867 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23869 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23870 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23871 REGDEF(dspsc
,0,DSPSC
),
23873 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23874 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23875 REGDEF(DSPSC
,0,DSPSC
),
23877 /* iWMMXt data registers - p0, c0-15. */
23878 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23880 /* iWMMXt control registers - p1, c0-3. */
23881 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23882 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23883 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23884 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23886 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23887 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23888 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23889 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23890 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23892 /* XScale accumulator registers. */
23893 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23899 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23900 within psr_required_here. */
23901 static const struct asm_psr psrs
[] =
23903 /* Backward compatibility notation. Note that "all" is no longer
23904 truly all possible PSR bits. */
23905 {"all", PSR_c
| PSR_f
},
23909 /* Individual flags. */
23915 /* Combinations of flags. */
23916 {"fs", PSR_f
| PSR_s
},
23917 {"fx", PSR_f
| PSR_x
},
23918 {"fc", PSR_f
| PSR_c
},
23919 {"sf", PSR_s
| PSR_f
},
23920 {"sx", PSR_s
| PSR_x
},
23921 {"sc", PSR_s
| PSR_c
},
23922 {"xf", PSR_x
| PSR_f
},
23923 {"xs", PSR_x
| PSR_s
},
23924 {"xc", PSR_x
| PSR_c
},
23925 {"cf", PSR_c
| PSR_f
},
23926 {"cs", PSR_c
| PSR_s
},
23927 {"cx", PSR_c
| PSR_x
},
23928 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23929 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23930 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23931 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23932 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23933 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23934 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23935 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23936 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23937 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23938 {"scf", PSR_s
| PSR_c
| PSR_f
},
23939 {"scx", PSR_s
| PSR_c
| PSR_x
},
23940 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23941 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23942 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23943 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23944 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23945 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23946 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23947 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23948 {"csf", PSR_c
| PSR_s
| PSR_f
},
23949 {"csx", PSR_c
| PSR_s
| PSR_x
},
23950 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23951 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23952 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23953 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23954 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23955 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23956 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23957 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23958 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23959 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23960 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23961 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23962 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23963 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23964 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23965 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23966 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23967 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23968 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23969 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23970 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23971 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23972 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23973 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23974 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23975 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23978 /* Table of V7M psr names. */
23979 static const struct asm_psr v7m_psrs
[] =
23981 {"apsr", 0x0 }, {"APSR", 0x0 },
23982 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23983 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23984 {"psr", 0x3 }, {"PSR", 0x3 },
23985 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23986 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23987 {"epsr", 0x6 }, {"EPSR", 0x6 },
23988 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23989 {"msp", 0x8 }, {"MSP", 0x8 },
23990 {"psp", 0x9 }, {"PSP", 0x9 },
23991 {"msplim", 0xa }, {"MSPLIM", 0xa },
23992 {"psplim", 0xb }, {"PSPLIM", 0xb },
23993 {"primask", 0x10}, {"PRIMASK", 0x10},
23994 {"basepri", 0x11}, {"BASEPRI", 0x11},
23995 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
23996 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23997 {"control", 0x14}, {"CONTROL", 0x14},
23998 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23999 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
24000 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
24001 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
24002 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
24003 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
24004 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
24005 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
24006 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
24009 /* Table of all shift-in-operand names. */
24010 static const struct asm_shift_name shift_names
[] =
24012 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
24013 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
24014 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
24015 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
24016 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
24017 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
24018 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
24021 /* Table of all explicit relocation names. */
24023 static struct reloc_entry reloc_names
[] =
24025 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
24026 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
24027 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
24028 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
24029 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
24030 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
24031 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
24032 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
24033 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
24034 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
24035 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
24036 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
24037 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
24038 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
24039 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
24040 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
24041 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
24042 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
24043 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
24044 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
24045 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24046 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24047 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
24048 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
24049 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
24050 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
24051 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
24055 /* Table of all conditional affixes. */
24056 static const struct asm_cond conds
[] =
24060 {"cs", 0x2}, {"hs", 0x2},
24061 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
24074 static const struct asm_cond vconds
[] =
24080 #define UL_BARRIER(L,U,CODE,FEAT) \
24081 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
24082 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
24084 static struct asm_barrier_opt barrier_opt_names
[] =
24086 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
24087 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
24088 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
24089 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
24090 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
24091 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
24092 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
24093 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
24094 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
24095 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
24096 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
24097 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
24098 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
24099 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
24100 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
24101 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
24106 /* Table of ARM-format instructions. */
24108 /* Macros for gluing together operand strings. N.B. In all cases
24109 other than OPS0, the trailing OP_stop comes from default
24110 zero-initialization of the unspecified elements of the array. */
24111 #define OPS0() { OP_stop, }
24112 #define OPS1(a) { OP_##a, }
24113 #define OPS2(a,b) { OP_##a,OP_##b, }
24114 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
24115 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
24116 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
24117 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
24119 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
24120 This is useful when mixing operands for ARM and THUMB, i.e. using the
24121 MIX_ARM_THUMB_OPERANDS macro.
24122 In order to use these macros, prefix the number of operands with _
24124 #define OPS_1(a) { a, }
24125 #define OPS_2(a,b) { a,b, }
24126 #define OPS_3(a,b,c) { a,b,c, }
24127 #define OPS_4(a,b,c,d) { a,b,c,d, }
24128 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
24129 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
24131 /* These macros abstract out the exact format of the mnemonic table and
24132 save some repeated characters. */
24134 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
24135 #define TxCE(mnem, op, top, nops, ops, ae, te) \
24136 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
24137 THUMB_VARIANT, do_##ae, do_##te, 0 }
24139 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
24140 a T_MNEM_xyz enumerator. */
24141 #define TCE(mnem, aop, top, nops, ops, ae, te) \
24142 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
24143 #define tCE(mnem, aop, top, nops, ops, ae, te) \
24144 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24146 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
24147 infix after the third character. */
24148 #define TxC3(mnem, op, top, nops, ops, ae, te) \
24149 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
24150 THUMB_VARIANT, do_##ae, do_##te, 0 }
24151 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
24152 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
24153 THUMB_VARIANT, do_##ae, do_##te, 0 }
24154 #define TC3(mnem, aop, top, nops, ops, ae, te) \
24155 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
24156 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
24157 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
24158 #define tC3(mnem, aop, top, nops, ops, ae, te) \
24159 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24160 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
24161 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24163 /* Mnemonic that cannot be conditionalized. The ARM condition-code
24164 field is still 0xE. Many of the Thumb variants can be executed
24165 conditionally, so this is checked separately. */
24166 #define TUE(mnem, op, top, nops, ops, ae, te) \
24167 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24168 THUMB_VARIANT, do_##ae, do_##te, 0 }
24170 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
24171 Used by mnemonics that have very minimal differences in the encoding for
24172 ARM and Thumb variants and can be handled in a common function. */
24173 #define TUEc(mnem, op, top, nops, ops, en) \
24174 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24175 THUMB_VARIANT, do_##en, do_##en, 0 }
24177 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
24178 condition code field. */
24179 #define TUF(mnem, op, top, nops, ops, ae, te) \
24180 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
24181 THUMB_VARIANT, do_##ae, do_##te, 0 }
24183 /* ARM-only variants of all the above. */
24184 #define CE(mnem, op, nops, ops, ae) \
24185 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24187 #define C3(mnem, op, nops, ops, ae) \
24188 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24190 /* Thumb-only variants of TCE and TUE. */
24191 #define ToC(mnem, top, nops, ops, te) \
24192 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24195 #define ToU(mnem, top, nops, ops, te) \
24196 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
24199 /* T_MNEM_xyz enumerator variants of ToC. */
24200 #define toC(mnem, top, nops, ops, te) \
24201 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
24204 /* T_MNEM_xyz enumerator variants of ToU. */
24205 #define toU(mnem, top, nops, ops, te) \
24206 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
24209 /* Legacy mnemonics that always have conditional infix after the third
24211 #define CL(mnem, op, nops, ops, ae) \
24212 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24213 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24215 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
24216 #define cCE(mnem, op, nops, ops, ae) \
24217 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24219 /* mov instructions that are shared between coprocessor and MVE. */
24220 #define mcCE(mnem, op, nops, ops, ae) \
24221 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
24223 /* Legacy coprocessor instructions where conditional infix and conditional
24224 suffix are ambiguous. For consistency this includes all FPA instructions,
24225 not just the potentially ambiguous ones. */
24226 #define cCL(mnem, op, nops, ops, ae) \
24227 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24228 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24230 /* Coprocessor, takes either a suffix or a position-3 infix
24231 (for an FPA corner case). */
24232 #define C3E(mnem, op, nops, ops, ae) \
24233 { mnem, OPS##nops ops, OT_csuf_or_in3, \
24234 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24236 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
24237 { m1 #m2 m3, OPS##nops ops, \
24238 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
24239 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24241 #define CM(m1, m2, op, nops, ops, ae) \
24242 xCM_ (m1, , m2, op, nops, ops, ae), \
24243 xCM_ (m1, eq, m2, op, nops, ops, ae), \
24244 xCM_ (m1, ne, m2, op, nops, ops, ae), \
24245 xCM_ (m1, cs, m2, op, nops, ops, ae), \
24246 xCM_ (m1, hs, m2, op, nops, ops, ae), \
24247 xCM_ (m1, cc, m2, op, nops, ops, ae), \
24248 xCM_ (m1, ul, m2, op, nops, ops, ae), \
24249 xCM_ (m1, lo, m2, op, nops, ops, ae), \
24250 xCM_ (m1, mi, m2, op, nops, ops, ae), \
24251 xCM_ (m1, pl, m2, op, nops, ops, ae), \
24252 xCM_ (m1, vs, m2, op, nops, ops, ae), \
24253 xCM_ (m1, vc, m2, op, nops, ops, ae), \
24254 xCM_ (m1, hi, m2, op, nops, ops, ae), \
24255 xCM_ (m1, ls, m2, op, nops, ops, ae), \
24256 xCM_ (m1, ge, m2, op, nops, ops, ae), \
24257 xCM_ (m1, lt, m2, op, nops, ops, ae), \
24258 xCM_ (m1, gt, m2, op, nops, ops, ae), \
24259 xCM_ (m1, le, m2, op, nops, ops, ae), \
24260 xCM_ (m1, al, m2, op, nops, ops, ae)
24262 #define UE(mnem, op, nops, ops, ae) \
24263 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24265 #define UF(mnem, op, nops, ops, ae) \
24266 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24268 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
24269 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
24270 use the same encoding function for each. */
24271 #define NUF(mnem, op, nops, ops, enc) \
24272 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24273 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24275 /* Neon data processing, version which indirects through neon_enc_tab for
24276 the various overloaded versions of opcodes. */
24277 #define nUF(mnem, op, nops, ops, enc) \
24278 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24279 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24281 /* Neon insn with conditional suffix for the ARM version, non-overloaded
24283 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24284 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
24285 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24287 #define NCE(mnem, op, nops, ops, enc) \
24288 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24290 #define NCEF(mnem, op, nops, ops, enc) \
24291 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24293 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
24294 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24295 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
24296 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24298 #define nCE(mnem, op, nops, ops, enc) \
24299 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24301 #define nCEF(mnem, op, nops, ops, enc) \
24302 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24305 #define mCEF(mnem, op, nops, ops, enc) \
24306 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
24307 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24310 /* nCEF but for MVE predicated instructions. */
24311 #define mnCEF(mnem, op, nops, ops, enc) \
24312 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24314 /* nCE but for MVE predicated instructions. */
24315 #define mnCE(mnem, op, nops, ops, enc) \
24316 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24318 /* NUF but for potentially MVE predicated instructions. */
24319 #define MNUF(mnem, op, nops, ops, enc) \
24320 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24321 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24323 /* nUF but for potentially MVE predicated instructions. */
24324 #define mnUF(mnem, op, nops, ops, enc) \
24325 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24326 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24328 /* ToC but for potentially MVE predicated instructions. */
24329 #define mToC(mnem, top, nops, ops, te) \
24330 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24333 /* NCE but for MVE predicated instructions. */
24334 #define MNCE(mnem, op, nops, ops, enc) \
24335 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24337 /* NCEF but for MVE predicated instructions. */
24338 #define MNCEF(mnem, op, nops, ops, enc) \
24339 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24342 static const struct asm_opcode insns
[] =
24344 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
24345 #define THUMB_VARIANT & arm_ext_v4t
24346 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24347 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24348 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24349 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24350 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24351 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24352 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24353 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24354 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24355 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24356 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24357 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24358 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24359 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24360 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24361 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24363 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
24364 for setting PSR flag bits. They are obsolete in V6 and do not
24365 have Thumb equivalents. */
24366 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24367 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24368 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
24369 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24370 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24371 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
24372 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24373 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24374 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
24376 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
24377 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
24378 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24379 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24381 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
24382 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24383 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
24385 OP_ADDRGLDR
),ldst
, t_ldst
),
24386 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24388 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24389 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24390 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24391 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24392 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24393 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24395 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
24396 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
24399 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
24400 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
24401 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
24402 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
24404 /* Thumb-compatibility pseudo ops. */
24405 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24406 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24407 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24408 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24409 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24410 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24411 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24412 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24413 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
24414 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
24415 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
24416 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
24418 /* These may simplify to neg. */
24419 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24420 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24422 #undef THUMB_VARIANT
24423 #define THUMB_VARIANT & arm_ext_os
24425 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24426 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24428 #undef THUMB_VARIANT
24429 #define THUMB_VARIANT & arm_ext_v6
24431 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
24433 /* V1 instructions with no Thumb analogue prior to V6T2. */
24434 #undef THUMB_VARIANT
24435 #define THUMB_VARIANT & arm_ext_v6t2
24437 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24438 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24439 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
24441 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24442 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24443 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
24444 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24446 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24447 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24449 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24450 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24452 /* V1 instructions with no Thumb analogue at all. */
24453 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
24454 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
24456 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24457 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24458 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24459 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24460 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24461 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24462 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24463 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24466 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
24467 #undef THUMB_VARIANT
24468 #define THUMB_VARIANT & arm_ext_v4t
24470 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24471 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24473 #undef THUMB_VARIANT
24474 #define THUMB_VARIANT & arm_ext_v6t2
24476 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24477 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
24479 /* Generic coprocessor instructions. */
24480 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24481 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24482 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24483 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24484 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24485 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24486 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24489 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
24491 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24492 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24495 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
24496 #undef THUMB_VARIANT
24497 #define THUMB_VARIANT & arm_ext_msr
24499 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
24500 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
24503 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
24504 #undef THUMB_VARIANT
24505 #define THUMB_VARIANT & arm_ext_v6t2
24507 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24508 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24509 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24510 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24511 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24512 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24513 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24514 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24517 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
24518 #undef THUMB_VARIANT
24519 #define THUMB_VARIANT & arm_ext_v4t
24521 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24522 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24523 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24524 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24525 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24526 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24529 #define ARM_VARIANT & arm_ext_v4t_5
24531 /* ARM Architecture 4T. */
24532 /* Note: bx (and blx) are required on V5, even if the processor does
24533 not support Thumb. */
24534 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
24537 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
24538 #undef THUMB_VARIANT
24539 #define THUMB_VARIANT & arm_ext_v5t
24541 /* Note: blx has 2 variants; the .value coded here is for
24542 BLX(2). Only this variant has conditional execution. */
24543 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
24544 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
24546 #undef THUMB_VARIANT
24547 #define THUMB_VARIANT & arm_ext_v6t2
24549 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
24550 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24551 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24552 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24553 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24554 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24555 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24556 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24559 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
24560 #undef THUMB_VARIANT
24561 #define THUMB_VARIANT & arm_ext_v5exp
24563 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24564 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24565 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24566 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24568 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24569 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24571 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24572 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24573 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24574 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24576 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24577 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24578 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24579 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24581 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24582 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24584 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24585 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24586 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24587 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24590 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
24591 #undef THUMB_VARIANT
24592 #define THUMB_VARIANT & arm_ext_v6t2
24594 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
24595 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
24597 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
24598 ADDRGLDRS
), ldrd
, t_ldstd
),
24600 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24601 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24604 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
24606 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
24609 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
24610 #undef THUMB_VARIANT
24611 #define THUMB_VARIANT & arm_ext_v6
24613 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24614 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24615 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24616 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24617 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24618 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24619 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24620 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24621 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24622 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
24624 #undef THUMB_VARIANT
24625 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24627 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
24628 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24630 #undef THUMB_VARIANT
24631 #define THUMB_VARIANT & arm_ext_v6t2
24633 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24634 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24636 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
24637 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
24639 /* ARM V6 not included in V7M. */
24640 #undef THUMB_VARIANT
24641 #define THUMB_VARIANT & arm_ext_v6_notm
24642 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24643 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24644 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
24645 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
24646 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24647 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24648 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
24649 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24650 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
24651 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24652 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24653 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24654 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24655 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24656 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
24657 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
24658 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24659 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24660 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
24662 /* ARM V6 not included in V7M (eg. integer SIMD). */
24663 #undef THUMB_VARIANT
24664 #define THUMB_VARIANT & arm_ext_v6_dsp
24665 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
24666 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
24667 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24668 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24669 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24670 /* Old name for QASX. */
24671 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24672 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24673 /* Old name for QSAX. */
24674 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24675 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24676 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24677 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24678 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24679 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24680 /* Old name for SASX. */
24681 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24682 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24683 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24684 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24685 /* Old name for SHASX. */
24686 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24687 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24688 /* Old name for SHSAX. */
24689 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24690 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24691 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24692 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24693 /* Old name for SSAX. */
24694 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24695 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24696 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24697 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24698 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24699 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24700 /* Old name for UASX. */
24701 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24702 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24703 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24704 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24705 /* Old name for UHASX. */
24706 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24707 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24708 /* Old name for UHSAX. */
24709 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24710 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24711 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24712 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24713 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24714 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24715 /* Old name for UQASX. */
24716 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24717 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24718 /* Old name for UQSAX. */
24719 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24720 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24721 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24722 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24723 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24724 /* Old name for USAX. */
24725 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24726 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24727 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24728 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24729 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24730 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24731 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24732 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24733 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24734 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24735 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24736 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24737 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24738 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24739 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24740 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24741 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24742 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24743 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24744 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24745 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24746 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24747 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24748 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24749 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24750 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24751 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24752 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24753 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24754 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
24755 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
24756 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24757 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24758 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
24761 #define ARM_VARIANT & arm_ext_v6k_v6t2
24762 #undef THUMB_VARIANT
24763 #define THUMB_VARIANT & arm_ext_v6k_v6t2
24765 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
24766 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
24767 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
24768 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
24770 #undef THUMB_VARIANT
24771 #define THUMB_VARIANT & arm_ext_v6_notm
24772 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
24774 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
24775 RRnpcb
), strexd
, t_strexd
),
24777 #undef THUMB_VARIANT
24778 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24779 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
24781 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
24783 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24785 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24787 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
24790 #define ARM_VARIANT & arm_ext_sec
24791 #undef THUMB_VARIANT
24792 #define THUMB_VARIANT & arm_ext_sec
24794 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
24797 #define ARM_VARIANT & arm_ext_virt
24798 #undef THUMB_VARIANT
24799 #define THUMB_VARIANT & arm_ext_virt
24801 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
24802 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
24805 #define ARM_VARIANT & arm_ext_pan
24806 #undef THUMB_VARIANT
24807 #define THUMB_VARIANT & arm_ext_pan
24809 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
24812 #define ARM_VARIANT & arm_ext_v6t2
24813 #undef THUMB_VARIANT
24814 #define THUMB_VARIANT & arm_ext_v6t2
24816 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
24817 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
24818 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24819 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24821 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24822 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
24824 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24825 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24826 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24827 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24830 #define ARM_VARIANT & arm_ext_v3
24831 #undef THUMB_VARIANT
24832 #define THUMB_VARIANT & arm_ext_v6t2
24834 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
24835 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
24836 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
24839 #define ARM_VARIANT & arm_ext_v6t2
24840 #undef THUMB_VARIANT
24841 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24842 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24843 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24845 /* Thumb-only instructions. */
24847 #define ARM_VARIANT NULL
24848 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
24849 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
24851 /* ARM does not really have an IT instruction, so always allow it.
24852 The opcode is copied from Thumb in order to allow warnings in
24853 -mimplicit-it=[never | arm] modes. */
24855 #define ARM_VARIANT & arm_ext_v1
24856 #undef THUMB_VARIANT
24857 #define THUMB_VARIANT & arm_ext_v6t2
24859 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
24860 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
24861 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
24862 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
24863 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
24864 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
24865 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
24866 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24867 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24868 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24869 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24870 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24871 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24872 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24873 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24874 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24875 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24876 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24878 /* Thumb2 only instructions. */
24880 #define ARM_VARIANT NULL
24882 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24883 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24884 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24885 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24886 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24887 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24889 /* Hardware division instructions. */
24891 #define ARM_VARIANT & arm_ext_adiv
24892 #undef THUMB_VARIANT
24893 #define THUMB_VARIANT & arm_ext_div
24895 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24896 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24898 /* ARM V6M/V7 instructions. */
24900 #define ARM_VARIANT & arm_ext_barrier
24901 #undef THUMB_VARIANT
24902 #define THUMB_VARIANT & arm_ext_barrier
24904 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24905 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24906 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24908 /* ARM V7 instructions. */
24910 #define ARM_VARIANT & arm_ext_v7
24911 #undef THUMB_VARIANT
24912 #define THUMB_VARIANT & arm_ext_v7
24914 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24915 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24918 #define ARM_VARIANT & arm_ext_mp
24919 #undef THUMB_VARIANT
24920 #define THUMB_VARIANT & arm_ext_mp
24922 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24924 /* AArchv8 instructions. */
24926 #define ARM_VARIANT & arm_ext_v8
24928 /* Instructions shared between armv8-a and armv8-m. */
24929 #undef THUMB_VARIANT
24930 #define THUMB_VARIANT & arm_ext_atomics
24932 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24933 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24934 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24935 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24936 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24937 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24938 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24939 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24940 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24941 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24943 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24945 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24947 #undef THUMB_VARIANT
24948 #define THUMB_VARIANT & arm_ext_v8
24950 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24951 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24953 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24955 #undef THUMB_VARIANT
24956 #define THUMB_VARIANT & arm_ext_v8r
24958 #define ARM_VARIANT & arm_ext_v8r
24960 /* ARMv8-R instructions. */
24961 TUF("dfb", 57ff04c
, f3bf8f4c
, 0, (), noargs
, noargs
),
24963 /* Defined in V8 but is in undefined encoding space for earlier
24964 architectures. However earlier architectures are required to treat
24965 this instuction as a semihosting trap as well. Hence while not explicitly
24966 defined as such, it is in fact correct to define the instruction for all
24968 #undef THUMB_VARIANT
24969 #define THUMB_VARIANT & arm_ext_v1
24971 #define ARM_VARIANT & arm_ext_v1
24972 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24974 /* ARMv8 T32 only. */
24976 #define ARM_VARIANT NULL
24977 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24978 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24979 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24981 /* FP for ARMv8. */
24983 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24984 #undef THUMB_VARIANT
24985 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24987 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24988 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24989 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24990 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24991 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24992 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
24993 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
24994 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
24995 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
24996 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
24997 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
24999 /* Crypto v1 extensions. */
25001 #define ARM_VARIANT & fpu_crypto_ext_armv8
25002 #undef THUMB_VARIANT
25003 #define THUMB_VARIANT & fpu_crypto_ext_armv8
25005 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
25006 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
25007 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
25008 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
25009 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
25010 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
25011 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
25012 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
25013 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
25014 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
25015 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
25016 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
25017 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
25018 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
25021 #define ARM_VARIANT & arm_ext_crc
25022 #undef THUMB_VARIANT
25023 #define THUMB_VARIANT & arm_ext_crc
25024 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
25025 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
25026 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
25027 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
25028 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
25029 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
25031 /* ARMv8.2 RAS extension. */
25033 #define ARM_VARIANT & arm_ext_ras
25034 #undef THUMB_VARIANT
25035 #define THUMB_VARIANT & arm_ext_ras
25036 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
25039 #define ARM_VARIANT & arm_ext_v8_3
25040 #undef THUMB_VARIANT
25041 #define THUMB_VARIANT & arm_ext_v8_3
25042 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
25045 #define ARM_VARIANT & fpu_neon_ext_dotprod
25046 #undef THUMB_VARIANT
25047 #define THUMB_VARIANT & fpu_neon_ext_dotprod
25048 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
25049 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
25052 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
25053 #undef THUMB_VARIANT
25054 #define THUMB_VARIANT NULL
25056 cCE("wfs", e200110
, 1, (RR
), rd
),
25057 cCE("rfs", e300110
, 1, (RR
), rd
),
25058 cCE("wfc", e400110
, 1, (RR
), rd
),
25059 cCE("rfc", e500110
, 1, (RR
), rd
),
25061 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25062 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25063 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25064 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25066 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25067 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25068 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25069 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25071 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
25072 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
25073 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
25074 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
25075 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
25076 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
25077 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
25078 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
25079 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
25080 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
25081 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
25082 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
25084 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
25085 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
25086 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
25087 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
25088 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
25089 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
25090 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
25091 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
25092 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
25093 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
25094 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
25095 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
25097 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
25098 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
25099 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
25100 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
25101 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
25102 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
25103 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
25104 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
25105 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
25106 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
25107 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
25108 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
25110 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
25111 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
25112 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
25113 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
25114 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
25115 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
25116 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
25117 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
25118 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
25119 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
25120 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
25121 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
25123 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
25124 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
25125 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
25126 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
25127 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
25128 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
25129 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
25130 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
25131 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
25132 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
25133 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
25134 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
25136 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
25137 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
25138 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
25139 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
25140 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
25141 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
25142 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
25143 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
25144 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
25145 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
25146 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
25147 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
25149 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
25150 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
25151 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
25152 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
25153 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
25154 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
25155 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
25156 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
25157 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
25158 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
25159 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
25160 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
25162 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
25163 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
25164 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
25165 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
25166 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
25167 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
25168 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
25169 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
25170 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
25171 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
25172 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
25173 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
25175 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
25176 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
25177 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
25178 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
25179 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
25180 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
25181 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
25182 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
25183 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
25184 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
25185 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
25186 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
25188 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
25189 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
25190 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
25191 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
25192 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
25193 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
25194 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
25195 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
25196 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
25197 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
25198 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
25199 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
25201 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
25202 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
25203 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
25204 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
25205 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
25206 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
25207 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
25208 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
25209 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
25210 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
25211 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
25212 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
25214 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
25215 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
25216 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
25217 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
25218 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
25219 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
25220 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
25221 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
25222 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
25223 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
25224 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
25225 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
25227 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
25228 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
25229 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
25230 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
25231 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
25232 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
25233 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
25234 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
25235 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
25236 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
25237 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
25238 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
25240 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
25241 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
25242 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
25243 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
25244 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
25245 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
25246 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
25247 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
25248 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
25249 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
25250 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
25251 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
25253 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
25254 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
25255 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
25256 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
25257 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
25258 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
25259 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
25260 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
25261 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
25262 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
25263 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
25264 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
25266 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
25267 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
25268 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
25269 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
25270 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
25271 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
25272 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
25273 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
25274 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
25275 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
25276 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
25277 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
25279 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25280 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25281 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25282 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25283 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25284 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25285 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25286 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25287 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25288 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25289 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25290 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25292 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25293 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25294 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25295 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25296 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25297 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25298 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25299 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25300 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25301 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25302 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25303 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25305 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25306 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25307 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25308 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25309 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25310 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25311 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25312 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25313 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25314 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25315 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25316 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25318 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25319 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25320 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25321 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25322 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25323 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25324 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25325 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25326 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25327 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25328 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25329 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25331 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25332 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25333 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25334 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25335 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25336 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25337 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25338 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25339 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25340 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25341 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25342 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25344 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25345 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25346 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25347 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25348 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25349 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25350 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25351 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25352 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25353 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25354 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25355 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25357 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25358 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25359 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25360 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25361 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25362 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25363 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25364 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25365 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25366 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25367 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25368 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25370 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25371 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25372 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25373 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25374 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25375 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25376 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25377 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25378 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25379 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25380 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25381 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25383 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25384 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25385 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25386 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25387 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25388 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25389 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25390 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25391 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25392 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25393 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25394 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25396 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25397 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25398 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25399 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25400 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25401 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25402 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25403 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25404 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25405 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25406 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25407 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25409 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25410 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25411 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25412 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25413 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25414 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25415 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25416 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25417 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25418 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25419 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25420 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25422 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25423 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25424 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25425 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25426 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25427 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25428 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25429 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25430 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25431 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25432 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25433 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25435 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25436 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25437 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25438 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25439 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25440 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25441 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25442 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25443 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25444 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25445 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25446 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25448 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25449 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25450 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25451 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25453 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
25454 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
25455 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
25456 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
25457 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
25458 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
25459 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
25460 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
25461 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
25462 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
25463 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
25464 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
25466 /* The implementation of the FIX instruction is broken on some
25467 assemblers, in that it accepts a precision specifier as well as a
25468 rounding specifier, despite the fact that this is meaningless.
25469 To be more compatible, we accept it as well, though of course it
25470 does not set any bits. */
25471 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
25472 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
25473 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
25474 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
25475 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
25476 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
25477 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
25478 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
25479 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
25480 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
25481 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
25482 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
25483 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
25485 /* Instructions that were new with the real FPA, call them V2. */
25487 #define ARM_VARIANT & fpu_fpa_ext_v2
25489 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25490 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25491 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25492 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25493 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25494 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25497 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
25498 #undef THUMB_VARIANT
25499 #define THUMB_VARIANT & arm_ext_v6t2
25500 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
25501 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
25502 mcCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25503 mcCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25504 mcCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25505 mcCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25507 /* Memory operations. */
25508 mcCE(fldmias
, c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25509 mcCE(fldmdbs
, d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25510 mcCE(fstmias
, c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25511 mcCE(fstmdbs
, d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25512 #undef THUMB_VARIANT
25514 /* Moves and type conversions. */
25515 cCE("fmstat", ef1fa10
, 0, (), noargs
),
25516 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25517 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25518 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25519 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25520 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25521 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25522 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
25523 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
25525 /* Memory operations. */
25526 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25527 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25528 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25529 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25530 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25531 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25532 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25533 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25534 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25535 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25536 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25537 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25539 /* Monadic operations. */
25540 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25541 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25542 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25544 /* Dyadic operations. */
25545 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25546 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25547 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25548 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25549 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25550 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25551 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25552 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25553 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25556 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25557 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
25558 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25559 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
25561 /* Double precision load/store are still present on single precision
25562 implementations. */
25563 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25564 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25565 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25566 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25567 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25568 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25569 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25570 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25573 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
25575 /* Moves and type conversions. */
25576 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25577 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25578 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25579 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25580 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25581 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25582 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25583 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25584 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25585 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25586 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25587 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25589 /* Monadic operations. */
25590 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25591 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25592 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25594 /* Dyadic operations. */
25595 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25596 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25597 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25598 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25599 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25600 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25601 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25602 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25603 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25606 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25607 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
25608 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25609 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
25611 /* Instructions which may belong to either the Neon or VFP instruction sets.
25612 Individual encoder functions perform additional architecture checks. */
25614 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25615 #undef THUMB_VARIANT
25616 #define THUMB_VARIANT & arm_ext_v6t2
25618 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25619 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25620 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25621 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25622 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25623 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25625 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
25626 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
25628 #undef THUMB_VARIANT
25629 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
25631 /* These mnemonics are unique to VFP. */
25632 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
25633 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
25634 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25635 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25636 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25637 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
25639 /* Mnemonics shared by Neon and VFP. */
25640 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
25642 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
25643 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
25644 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
25645 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
25648 /* NOTE: All VMOV encoding is special-cased! */
25649 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
25651 #undef THUMB_VARIANT
25652 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
25653 by different feature bits. Since we are setting the Thumb guard, we can
25654 require Thumb-1 which makes it a nop guard and set the right feature bit in
25655 do_vldr_vstr (). */
25656 #define THUMB_VARIANT & arm_ext_v4t
25657 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25658 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25661 #define ARM_VARIANT & arm_ext_fp16
25662 #undef THUMB_VARIANT
25663 #define THUMB_VARIANT & arm_ext_fp16
25664 /* New instructions added from v8.2, allowing the extraction and insertion of
25665 the upper 16 bits of a 32-bit vector register. */
25666 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
25667 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
25669 /* New backported fma/fms instructions optional in v8.2. */
25670 NUF (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
25671 NUF (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
25673 #undef THUMB_VARIANT
25674 #define THUMB_VARIANT & fpu_neon_ext_v1
25676 #define ARM_VARIANT & fpu_neon_ext_v1
25678 /* Data processing with three registers of the same length. */
25679 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
25680 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
25681 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
25682 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25683 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25684 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25685 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
25686 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25687 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25688 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25689 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25690 /* If not immediate, fall back to neon_dyadic_i64_su.
25691 shl should accept I8 I16 I32 I64,
25692 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
25693 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
25694 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
25695 /* Logic ops, types optional & ignored. */
25696 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25697 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25698 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25699 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25700 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
25701 /* Bitfield ops, untyped. */
25702 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25703 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25704 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25705 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25706 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25707 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25708 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
25709 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25710 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25711 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25712 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
25713 back to neon_dyadic_if_su. */
25714 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25715 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25716 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25717 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25718 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25719 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25720 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25721 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25722 /* Comparison. Type I8 I16 I32 F32. */
25723 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
25724 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
25725 /* As above, D registers only. */
25726 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25727 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25728 /* Int and float variants, signedness unimportant. */
25729 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25730 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25731 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
25732 /* Add/sub take types I8 I16 I32 I64 F32. */
25733 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25734 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25735 /* vtst takes sizes 8, 16, 32. */
25736 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
25737 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
25738 /* VMUL takes I8 I16 I32 F32 P8. */
25739 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
25740 /* VQD{R}MULH takes S16 S32. */
25741 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25742 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25743 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25744 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25745 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25746 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25747 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25748 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25749 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25750 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25751 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25752 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25753 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25754 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25755 /* ARM v8.1 extension. */
25756 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25757 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
25758 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25760 /* Two address, int/float. Types S8 S16 S32 F32. */
25761 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25762 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25764 /* Data processing with two registers and a shift amount. */
25765 /* Right shifts, and variants with rounding.
25766 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
25767 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25768 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25769 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25770 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25771 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25772 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25773 /* Shift and insert. Sizes accepted 8 16 32 64. */
25774 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
25775 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
25776 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
25777 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
25778 /* Right shift immediate, saturating & narrowing, with rounding variants.
25779 Types accepted S16 S32 S64 U16 U32 U64. */
25780 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25781 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25782 /* As above, unsigned. Types accepted S16 S32 S64. */
25783 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25784 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25785 /* Right shift narrowing. Types accepted I16 I32 I64. */
25786 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25787 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25788 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
25789 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
25790 /* CVT with optional immediate for fixed-point variant. */
25791 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
25793 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
25795 /* Data processing, three registers of different lengths. */
25796 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
25797 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
25798 /* If not scalar, fall back to neon_dyadic_long.
25799 Vector types as above, scalar types S16 S32 U16 U32. */
25800 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25801 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25802 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
25803 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25804 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25805 /* Dyadic, narrowing insns. Types I16 I32 I64. */
25806 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25807 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25808 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25809 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25810 /* Saturating doubling multiplies. Types S16 S32. */
25811 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25812 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25813 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25814 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
25815 S16 S32 U16 U32. */
25816 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
25818 /* Extract. Size 8. */
25819 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
25820 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
25822 /* Two registers, miscellaneous. */
25823 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
25824 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
25825 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
25826 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
25827 /* Vector replicate. Sizes 8 16 32. */
25828 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
25829 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
25830 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
25831 /* VMOVN. Types I16 I32 I64. */
25832 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
25833 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
25834 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
25835 /* VQMOVUN. Types S16 S32 S64. */
25836 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
25837 /* VZIP / VUZP. Sizes 8 16 32. */
25838 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25839 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25840 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25841 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25842 /* VQABS / VQNEG. Types S8 S16 S32. */
25843 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25844 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25845 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25846 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25847 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
25848 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25849 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
25850 /* Reciprocal estimates. Types U32 F16 F32. */
25851 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25852 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
25853 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25854 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
25855 /* VCLS. Types S8 S16 S32. */
25856 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
25857 /* VCLZ. Types I8 I16 I32. */
25858 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
25859 /* VCNT. Size 8. */
25860 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
25861 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
25862 /* Two address, untyped. */
25863 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
25864 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
25865 /* VTRN. Sizes 8 16 32. */
25866 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
25867 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
25869 /* Table lookup. Size 8. */
25870 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25871 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25873 #undef THUMB_VARIANT
25874 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25876 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25878 /* Neon element/structure load/store. */
25879 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25880 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25881 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25882 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25883 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25884 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25885 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25886 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25888 #undef THUMB_VARIANT
25889 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25891 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25892 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25893 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25894 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25895 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25896 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25897 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25898 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25899 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25900 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25902 #undef THUMB_VARIANT
25903 #define THUMB_VARIANT & fpu_vfp_ext_v3
25905 #define ARM_VARIANT & fpu_vfp_ext_v3
25907 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25908 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25909 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25910 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25911 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25912 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25913 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25914 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25915 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25918 #define ARM_VARIANT & fpu_vfp_ext_fma
25919 #undef THUMB_VARIANT
25920 #define THUMB_VARIANT & fpu_vfp_ext_fma
25921 /* Mnemonics shared by Neon, VFP, MVE and BF16. These are included in the
25922 VFP FMA variant; NEON and VFP FMA always includes the NEON
25923 FMA instructions. */
25924 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25925 TUF ("vfmat", c300850
, fc300850
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), mve_vfma
, mve_vfma
),
25926 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25928 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25929 the v form should always be used. */
25930 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25931 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25932 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25933 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25934 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25935 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25937 #undef THUMB_VARIANT
25939 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25941 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25942 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25943 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25944 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25945 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25946 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25947 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25948 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25951 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25953 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25954 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25955 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25956 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25957 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25958 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25959 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25960 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25961 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25962 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25963 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25964 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25965 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25966 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25967 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25968 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25969 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25970 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25971 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25972 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25973 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25974 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25975 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25976 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25977 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25978 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25979 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25980 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25981 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25982 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25983 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25984 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25985 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25986 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25987 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25988 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25989 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25990 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25991 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25992 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25993 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25994 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25995 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25996 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25997 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25998 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25999 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
26000 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26001 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26002 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26003 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26004 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26005 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26006 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26007 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26008 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26009 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26010 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26011 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26012 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26013 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26014 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26015 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26016 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26017 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26018 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26019 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26020 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26021 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26022 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26023 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26024 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26025 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26026 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26027 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26028 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26029 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26030 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26031 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26032 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26033 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26034 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26035 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26036 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26037 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26038 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26039 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26040 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26041 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
26042 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26043 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26044 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26045 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26046 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26047 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26048 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26049 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26050 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26051 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26052 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26053 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26054 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26055 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26056 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26057 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26058 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26059 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26060 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26061 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26062 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26063 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
26064 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26065 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26066 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26067 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26068 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26069 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26070 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26071 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26072 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26073 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26074 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26075 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26076 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26077 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26078 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26079 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26080 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26081 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26082 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26083 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26084 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26085 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26086 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26087 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26088 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26089 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26090 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26091 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26092 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26093 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26094 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26095 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26096 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26097 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26098 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26099 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26100 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26101 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26102 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26103 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26104 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26105 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26106 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26107 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26108 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26109 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26110 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26111 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26112 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26113 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26114 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
26117 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
26119 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
26120 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
26121 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
26122 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26123 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26124 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26125 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26126 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26127 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26128 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26129 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26130 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26131 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26132 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26133 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26134 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26135 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26136 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26137 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26138 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26139 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
26140 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26141 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26142 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26143 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26144 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26145 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26146 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26147 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26148 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26149 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26150 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26151 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26152 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26153 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26154 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26155 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26156 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26157 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26158 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26159 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26160 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26161 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26162 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26163 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26164 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26165 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26166 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26167 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26168 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26169 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26170 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26171 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26172 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26173 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26174 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26175 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26178 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
26180 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26181 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26182 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26183 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26184 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26185 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26186 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26187 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26188 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
26189 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
26190 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
26191 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
26192 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
26193 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
26194 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
26195 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
26196 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
26197 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
26198 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
26199 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
26200 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
26201 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
26202 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
26203 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
26204 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
26205 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
26206 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
26207 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
26208 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
26209 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
26210 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
26211 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
26212 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
26213 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
26214 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
26215 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
26216 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
26217 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
26218 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
26219 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
26220 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
26221 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
26222 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
26223 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
26224 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
26225 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
26226 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
26227 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
26228 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
26229 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
26230 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
26231 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
26232 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
26233 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
26234 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26235 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26236 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26237 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26238 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26239 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26240 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
26241 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
26242 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
26243 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
26244 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26245 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26246 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26247 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26248 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26249 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26250 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26251 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26252 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26253 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26254 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26255 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26257 /* ARMv8.5-A instructions. */
26259 #define ARM_VARIANT & arm_ext_sb
26260 #undef THUMB_VARIANT
26261 #define THUMB_VARIANT & arm_ext_sb
26262 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
26265 #define ARM_VARIANT & arm_ext_predres
26266 #undef THUMB_VARIANT
26267 #define THUMB_VARIANT & arm_ext_predres
26268 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
26269 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
26270 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
26272 /* ARMv8-M instructions. */
26274 #define ARM_VARIANT NULL
26275 #undef THUMB_VARIANT
26276 #define THUMB_VARIANT & arm_ext_v8m
26277 ToU("sg", e97fe97f
, 0, (), noargs
),
26278 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
26279 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
26280 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
26281 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
26282 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
26283 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
26285 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
26286 instructions behave as nop if no VFP is present. */
26287 #undef THUMB_VARIANT
26288 #define THUMB_VARIANT & arm_ext_v8m_main
26289 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
26290 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
26292 /* Armv8.1-M Mainline instructions. */
26293 #undef THUMB_VARIANT
26294 #define THUMB_VARIANT & arm_ext_v8_1m_main
26295 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26296 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26297 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26298 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26299 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
26300 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
26301 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26302 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26303 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26305 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
26306 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
26307 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26308 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
26309 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26311 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
26312 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
26313 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
26315 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
26316 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
26318 #undef THUMB_VARIANT
26319 #define THUMB_VARIANT & mve_ext
26320 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26321 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26322 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26323 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26324 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26325 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26326 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26327 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26328 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26329 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26330 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26331 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26332 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26333 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26334 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26336 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26337 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26338 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26339 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26340 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26341 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26342 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26343 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26344 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26345 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26346 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26347 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26348 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26349 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26350 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26352 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
26353 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
26354 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
26355 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
26356 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
26357 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
26358 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
26359 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
26360 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
26361 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
26362 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
26363 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
26364 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
26365 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
26366 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
26368 /* MVE and MVE FP only. */
26369 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
26370 mCEF(vctp
, _vctp
, 1, (RRnpc
), mve_vctp
),
26371 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26372 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26373 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26374 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26375 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
26376 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
26377 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26378 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26379 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26380 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26381 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26382 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26383 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26384 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26385 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26386 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26388 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26389 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26390 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26391 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26392 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26393 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26394 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26395 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26396 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26397 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26398 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26399 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26400 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26401 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26402 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26403 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26404 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26405 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26406 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26407 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26409 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
26410 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
26411 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
26412 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26413 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26414 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
26415 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
26416 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26417 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26418 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26419 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26420 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26421 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26422 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
26423 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
26424 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
26425 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
26427 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26428 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26429 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26430 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26431 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26432 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26433 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26434 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26435 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26436 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26437 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26438 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26439 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26440 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26441 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26442 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26443 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26444 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26445 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26446 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26448 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
26449 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26450 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26451 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
26452 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
26454 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26455 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26456 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26457 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26458 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26459 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26460 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26461 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26462 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26463 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26464 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26465 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26466 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26467 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26468 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26469 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26470 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26472 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26473 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26474 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26475 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26476 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26477 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26478 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26479 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26480 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26481 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26482 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26483 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26485 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
26486 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26487 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26489 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
26490 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
26491 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
26492 toU("lctp", _lctp
, 0, (), t_loloop
),
26494 #undef THUMB_VARIANT
26495 #define THUMB_VARIANT & mve_fp_ext
26496 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
26497 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
26498 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26499 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26500 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26501 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26502 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26503 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26506 #define ARM_VARIANT & fpu_vfp_ext_v1
26507 #undef THUMB_VARIANT
26508 #define THUMB_VARIANT & arm_ext_v6t2
26509 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
26510 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
26512 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
26515 #define ARM_VARIANT & fpu_vfp_ext_v1xd
26517 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
26518 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
26519 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
26520 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
26522 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
26523 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26524 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26526 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26527 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26529 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
26530 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
26532 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26533 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26536 #define ARM_VARIANT & fpu_vfp_ext_v2
26538 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
26539 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
26540 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
26541 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
26544 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
26545 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
26546 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
26547 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
26548 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
26549 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26550 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26553 #define ARM_VARIANT & fpu_neon_ext_v1
26554 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26555 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
26556 mnUF(vaddl
, _vaddl
, 3, (RNSDQMQ
, oRNSDMQ
, RNSDMQR
), neon_dyadic_long
),
26557 mnUF(vsubl
, _vsubl
, 3, (RNSDQMQ
, oRNSDMQ
, RNSDMQR
), neon_dyadic_long
),
26558 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26559 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26560 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26561 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26562 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
26563 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
26564 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
26565 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
26566 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26567 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
26568 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26569 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26570 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26571 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26572 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26573 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
26574 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26575 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26576 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
26577 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26578 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26579 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26580 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26581 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26582 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26583 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
26584 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
26585 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26586 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26587 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26588 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
26589 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
26590 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
26593 #define ARM_VARIANT & arm_ext_v8_3
26594 #undef THUMB_VARIANT
26595 #define THUMB_VARIANT & arm_ext_v6t2_v8m
26596 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
26597 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
26600 #define ARM_VARIANT &arm_ext_bf16
26601 #undef THUMB_VARIANT
26602 #define THUMB_VARIANT &arm_ext_bf16
26603 TUF ("vdot", c000d00
, fc000d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vdot
, vdot
),
26604 TUF ("vmmla", c000c40
, fc000c40
, 3, (RNQ
, RNQ
, RNQ
), vmmla
, vmmla
),
26605 TUF ("vfmab", c300810
, fc300810
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), bfloat_vfma
, bfloat_vfma
),
26608 #define ARM_VARIANT &arm_ext_i8mm
26609 #undef THUMB_VARIANT
26610 #define THUMB_VARIANT &arm_ext_i8mm
26611 TUF ("vsmmla", c200c40
, fc200c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26612 TUF ("vummla", c200c50
, fc200c50
, 3, (RNQ
, RNQ
, RNQ
), vummla
, vummla
),
26613 TUF ("vusmmla", ca00c40
, fca00c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26614 TUF ("vusdot", c800d00
, fc800d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vusdot
, vusdot
),
26615 TUF ("vsudot", c800d10
, fc800d10
, 3, (RNDQ
, RNDQ
, RNSC
), vsudot
, vsudot
),
26618 #undef THUMB_VARIANT
26619 #define THUMB_VARIANT &arm_ext_cde
26620 ToC ("cx1", ee000000
, 3, (RCP
, APSR_RR
, I8191
), cx1
),
26621 ToC ("cx1a", fe000000
, 3, (RCP
, APSR_RR
, I8191
), cx1a
),
26622 ToC ("cx1d", ee000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1d
),
26623 ToC ("cx1da", fe000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1da
),
26625 ToC ("cx2", ee400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2
),
26626 ToC ("cx2a", fe400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2a
),
26627 ToC ("cx2d", ee400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2d
),
26628 ToC ("cx2da", fe400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2da
),
26630 ToC ("cx3", ee800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3
),
26631 ToC ("cx3a", fe800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3a
),
26632 ToC ("cx3d", ee800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3d
),
26633 ToC ("cx3da", fe800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3da
),
26635 mToC ("vcx1", ec200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26636 mToC ("vcx1a", fc200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26638 mToC ("vcx2", ec300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26639 mToC ("vcx2a", fc300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26641 mToC ("vcx3", ec800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26642 mToC ("vcx3a", fc800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26646 #undef THUMB_VARIANT
26678 /* MD interface: bits in the object file. */
26680 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
26681 for use in the a.out file, and stores them in the array pointed to by buf.
26682 This knows about the endian-ness of the target machine and does
26683 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
26684 2 (short) and 4 (long) Floating numbers are put out as a series of
26685 LITTLENUMS (shorts, here at least). */
26688 md_number_to_chars (char * buf
, valueT val
, int n
)
26690 if (target_big_endian
)
26691 number_to_chars_bigendian (buf
, val
, n
);
26693 number_to_chars_littleendian (buf
, val
, n
);
26697 md_chars_to_number (char * buf
, int n
)
26700 unsigned char * where
= (unsigned char *) buf
;
26702 if (target_big_endian
)
26707 result
|= (*where
++ & 255);
26715 result
|= (where
[n
] & 255);
26722 /* MD interface: Sections. */
26724 /* Calculate the maximum variable size (i.e., excluding fr_fix)
26725 that an rs_machine_dependent frag may reach. */
26728 arm_frag_max_var (fragS
*fragp
)
26730 /* We only use rs_machine_dependent for variable-size Thumb instructions,
26731 which are either THUMB_SIZE (2) or INSN_SIZE (4).
26733 Note that we generate relaxable instructions even for cases that don't
26734 really need it, like an immediate that's a trivial constant. So we're
26735 overestimating the instruction size for some of those cases. Rather
26736 than putting more intelligence here, it would probably be better to
26737 avoid generating a relaxation frag in the first place when it can be
26738 determined up front that a short instruction will suffice. */
26740 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
26744 /* Estimate the size of a frag before relaxing. Assume everything fits in
26748 md_estimate_size_before_relax (fragS
* fragp
,
26749 segT segtype ATTRIBUTE_UNUSED
)
26755 /* Convert a machine dependent frag. */
26758 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
26760 unsigned long insn
;
26761 unsigned long old_op
;
26769 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26771 old_op
= bfd_get_16(abfd
, buf
);
26772 if (fragp
->fr_symbol
)
26774 exp
.X_op
= O_symbol
;
26775 exp
.X_add_symbol
= fragp
->fr_symbol
;
26779 exp
.X_op
= O_constant
;
26781 exp
.X_add_number
= fragp
->fr_offset
;
26782 opcode
= fragp
->fr_subtype
;
26785 case T_MNEM_ldr_pc
:
26786 case T_MNEM_ldr_pc2
:
26787 case T_MNEM_ldr_sp
:
26788 case T_MNEM_str_sp
:
26795 if (fragp
->fr_var
== 4)
26797 insn
= THUMB_OP32 (opcode
);
26798 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
26800 insn
|= (old_op
& 0x700) << 4;
26804 insn
|= (old_op
& 7) << 12;
26805 insn
|= (old_op
& 0x38) << 13;
26807 insn
|= 0x00000c00;
26808 put_thumb32_insn (buf
, insn
);
26809 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
26813 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
26815 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
26818 if (fragp
->fr_var
== 4)
26820 insn
= THUMB_OP32 (opcode
);
26821 insn
|= (old_op
& 0xf0) << 4;
26822 put_thumb32_insn (buf
, insn
);
26823 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
26827 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26828 exp
.X_add_number
-= 4;
26836 if (fragp
->fr_var
== 4)
26838 int r0off
= (opcode
== T_MNEM_mov
26839 || opcode
== T_MNEM_movs
) ? 0 : 8;
26840 insn
= THUMB_OP32 (opcode
);
26841 insn
= (insn
& 0xe1ffffff) | 0x10000000;
26842 insn
|= (old_op
& 0x700) << r0off
;
26843 put_thumb32_insn (buf
, insn
);
26844 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26848 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
26853 if (fragp
->fr_var
== 4)
26855 insn
= THUMB_OP32(opcode
);
26856 put_thumb32_insn (buf
, insn
);
26857 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
26860 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
26864 if (fragp
->fr_var
== 4)
26866 insn
= THUMB_OP32(opcode
);
26867 insn
|= (old_op
& 0xf00) << 14;
26868 put_thumb32_insn (buf
, insn
);
26869 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
26872 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
26875 case T_MNEM_add_sp
:
26876 case T_MNEM_add_pc
:
26877 case T_MNEM_inc_sp
:
26878 case T_MNEM_dec_sp
:
26879 if (fragp
->fr_var
== 4)
26881 /* ??? Choose between add and addw. */
26882 insn
= THUMB_OP32 (opcode
);
26883 insn
|= (old_op
& 0xf0) << 4;
26884 put_thumb32_insn (buf
, insn
);
26885 if (opcode
== T_MNEM_add_pc
)
26886 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
26888 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26891 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26899 if (fragp
->fr_var
== 4)
26901 insn
= THUMB_OP32 (opcode
);
26902 insn
|= (old_op
& 0xf0) << 4;
26903 insn
|= (old_op
& 0xf) << 16;
26904 put_thumb32_insn (buf
, insn
);
26905 if (insn
& (1 << 20))
26906 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26908 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26911 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26917 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
26918 (enum bfd_reloc_code_real
) reloc_type
);
26919 fixp
->fx_file
= fragp
->fr_file
;
26920 fixp
->fx_line
= fragp
->fr_line
;
26921 fragp
->fr_fix
+= fragp
->fr_var
;
26923 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26924 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
26925 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
26926 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26929 /* Return the size of a relaxable immediate operand instruction.
26930 SHIFT and SIZE specify the form of the allowable immediate. */
26932 relax_immediate (fragS
*fragp
, int size
, int shift
)
26938 /* ??? Should be able to do better than this. */
26939 if (fragp
->fr_symbol
)
26942 low
= (1 << shift
) - 1;
26943 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26944 offset
= fragp
->fr_offset
;
26945 /* Force misaligned offsets to 32-bit variant. */
26948 if (offset
& ~mask
)
26953 /* Get the address of a symbol during relaxation. */
26955 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
26961 sym
= fragp
->fr_symbol
;
26962 sym_frag
= symbol_get_frag (sym
);
26963 know (S_GET_SEGMENT (sym
) != absolute_section
26964 || sym_frag
== &zero_address_frag
);
26965 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26967 /* If frag has yet to be reached on this pass, assume it will
26968 move by STRETCH just as we did. If this is not so, it will
26969 be because some frag between grows, and that will force
26973 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26977 /* Adjust stretch for any alignment frag. Note that if have
26978 been expanding the earlier code, the symbol may be
26979 defined in what appears to be an earlier frag. FIXME:
26980 This doesn't handle the fr_subtype field, which specifies
26981 a maximum number of bytes to skip when doing an
26983 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26985 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
26988 stretch
= - ((- stretch
)
26989 & ~ ((1 << (int) f
->fr_offset
) - 1));
26991 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
27003 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
27006 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
27011 /* Assume worst case for symbols not known to be in the same section. */
27012 if (fragp
->fr_symbol
== NULL
27013 || !S_IS_DEFINED (fragp
->fr_symbol
)
27014 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27015 || S_IS_WEAK (fragp
->fr_symbol
))
27018 val
= relaxed_symbol_addr (fragp
, stretch
);
27019 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
27020 addr
= (addr
+ 4) & ~3;
27021 /* Force misaligned targets to 32-bit variant. */
27025 if (val
< 0 || val
> 1020)
27030 /* Return the size of a relaxable add/sub immediate instruction. */
27032 relax_addsub (fragS
*fragp
, asection
*sec
)
27037 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
27038 op
= bfd_get_16(sec
->owner
, buf
);
27039 if ((op
& 0xf) == ((op
>> 4) & 0xf))
27040 return relax_immediate (fragp
, 8, 0);
27042 return relax_immediate (fragp
, 3, 0);
27045 /* Return TRUE iff the definition of symbol S could be pre-empted
27046 (overridden) at link or load time. */
27048 symbol_preemptible (symbolS
*s
)
27050 /* Weak symbols can always be pre-empted. */
27054 /* Non-global symbols cannot be pre-empted. */
27055 if (! S_IS_EXTERNAL (s
))
27059 /* In ELF, a global symbol can be marked protected, or private. In that
27060 case it can't be pre-empted (other definitions in the same link unit
27061 would violate the ODR). */
27062 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
27066 /* Other global symbols might be pre-empted. */
27070 /* Return the size of a relaxable branch instruction. BITS is the
27071 size of the offset field in the narrow instruction. */
27074 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
27080 /* Assume worst case for symbols not known to be in the same section. */
27081 if (!S_IS_DEFINED (fragp
->fr_symbol
)
27082 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27083 || S_IS_WEAK (fragp
->fr_symbol
))
27087 /* A branch to a function in ARM state will require interworking. */
27088 if (S_IS_DEFINED (fragp
->fr_symbol
)
27089 && ARM_IS_FUNC (fragp
->fr_symbol
))
27093 if (symbol_preemptible (fragp
->fr_symbol
))
27096 val
= relaxed_symbol_addr (fragp
, stretch
);
27097 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
27100 /* Offset is a signed value *2 */
27102 if (val
>= limit
|| val
< -limit
)
27108 /* Relax a machine dependent frag. This returns the amount by which
27109 the current size of the frag should change. */
27112 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
27117 oldsize
= fragp
->fr_var
;
27118 switch (fragp
->fr_subtype
)
27120 case T_MNEM_ldr_pc2
:
27121 newsize
= relax_adr (fragp
, sec
, stretch
);
27123 case T_MNEM_ldr_pc
:
27124 case T_MNEM_ldr_sp
:
27125 case T_MNEM_str_sp
:
27126 newsize
= relax_immediate (fragp
, 8, 2);
27130 newsize
= relax_immediate (fragp
, 5, 2);
27134 newsize
= relax_immediate (fragp
, 5, 1);
27138 newsize
= relax_immediate (fragp
, 5, 0);
27141 newsize
= relax_adr (fragp
, sec
, stretch
);
27147 newsize
= relax_immediate (fragp
, 8, 0);
27150 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
27153 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
27155 case T_MNEM_add_sp
:
27156 case T_MNEM_add_pc
:
27157 newsize
= relax_immediate (fragp
, 8, 2);
27159 case T_MNEM_inc_sp
:
27160 case T_MNEM_dec_sp
:
27161 newsize
= relax_immediate (fragp
, 7, 2);
27167 newsize
= relax_addsub (fragp
, sec
);
27173 fragp
->fr_var
= newsize
;
27174 /* Freeze wide instructions that are at or before the same location as
27175 in the previous pass. This avoids infinite loops.
27176 Don't freeze them unconditionally because targets may be artificially
27177 misaligned by the expansion of preceding frags. */
27178 if (stretch
<= 0 && newsize
> 2)
27180 md_convert_frag (sec
->owner
, sec
, fragp
);
27184 return newsize
- oldsize
;
27187 /* Round up a section size to the appropriate boundary. */
27190 md_section_align (segT segment ATTRIBUTE_UNUSED
,
27196 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
27197 of an rs_align_code fragment. */
27200 arm_handle_align (fragS
* fragP
)
27202 static unsigned char const arm_noop
[2][2][4] =
27205 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
27206 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
27209 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
27210 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
27213 static unsigned char const thumb_noop
[2][2][2] =
27216 {0xc0, 0x46}, /* LE */
27217 {0x46, 0xc0}, /* BE */
27220 {0x00, 0xbf}, /* LE */
27221 {0xbf, 0x00} /* BE */
27224 static unsigned char const wide_thumb_noop
[2][4] =
27225 { /* Wide Thumb-2 */
27226 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
27227 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
27230 unsigned bytes
, fix
, noop_size
;
27232 const unsigned char * noop
;
27233 const unsigned char *narrow_noop
= NULL
;
27238 if (fragP
->fr_type
!= rs_align_code
)
27241 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
27242 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
27245 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27246 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
27248 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
27250 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
27252 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27253 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
27255 narrow_noop
= thumb_noop
[1][target_big_endian
];
27256 noop
= wide_thumb_noop
[target_big_endian
];
27259 noop
= thumb_noop
[0][target_big_endian
];
27267 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27268 ? selected_cpu
: arm_arch_none
,
27270 [target_big_endian
];
27277 fragP
->fr_var
= noop_size
;
27279 if (bytes
& (noop_size
- 1))
27281 fix
= bytes
& (noop_size
- 1);
27283 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
27285 memset (p
, 0, fix
);
27292 if (bytes
& noop_size
)
27294 /* Insert a narrow noop. */
27295 memcpy (p
, narrow_noop
, noop_size
);
27297 bytes
-= noop_size
;
27301 /* Use wide noops for the remainder */
27305 while (bytes
>= noop_size
)
27307 memcpy (p
, noop
, noop_size
);
27309 bytes
-= noop_size
;
27313 fragP
->fr_fix
+= fix
;
27316 /* Called from md_do_align. Used to create an alignment
27317 frag in a code section. */
27320 arm_frag_align_code (int n
, int max
)
27324 /* We assume that there will never be a requirement
27325 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
27326 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27331 _("alignments greater than %d bytes not supported in .text sections."),
27332 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
27333 as_fatal ("%s", err_msg
);
27336 p
= frag_var (rs_align_code
,
27337 MAX_MEM_FOR_RS_ALIGN_CODE
,
27339 (relax_substateT
) max
,
27346 /* Perform target specific initialisation of a frag.
27347 Note - despite the name this initialisation is not done when the frag
27348 is created, but only when its type is assigned. A frag can be created
27349 and used a long time before its type is set, so beware of assuming that
27350 this initialisation is performed first. */
27354 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
27356 /* Record whether this frag is in an ARM or a THUMB area. */
27357 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27360 #else /* OBJ_ELF is defined. */
27362 arm_init_frag (fragS
* fragP
, int max_chars
)
27364 bfd_boolean frag_thumb_mode
;
27366 /* If the current ARM vs THUMB mode has not already
27367 been recorded into this frag then do so now. */
27368 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
27369 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27371 /* PR 21809: Do not set a mapping state for debug sections
27372 - it just confuses other tools. */
27373 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
27376 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
27378 /* Record a mapping symbol for alignment frags. We will delete this
27379 later if the alignment ends up empty. */
27380 switch (fragP
->fr_type
)
27383 case rs_align_test
:
27385 mapping_state_2 (MAP_DATA
, max_chars
);
27387 case rs_align_code
:
27388 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
27395 /* When we change sections we need to issue a new mapping symbol. */
27398 arm_elf_change_section (void)
27400 /* Link an unlinked unwind index table section to the .text section. */
27401 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
27402 && elf_linked_to_section (now_seg
) == NULL
)
27403 elf_linked_to_section (now_seg
) = text_section
;
27407 arm_elf_section_type (const char * str
, size_t len
)
27409 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
27410 return SHT_ARM_EXIDX
;
27415 /* Code to deal with unwinding tables. */
27417 static void add_unwind_adjustsp (offsetT
);
27419 /* Generate any deferred unwind frame offset. */
27422 flush_pending_unwind (void)
27426 offset
= unwind
.pending_offset
;
27427 unwind
.pending_offset
= 0;
27429 add_unwind_adjustsp (offset
);
27432 /* Add an opcode to this list for this function. Two-byte opcodes should
27433 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
27437 add_unwind_opcode (valueT op
, int length
)
27439 /* Add any deferred stack adjustment. */
27440 if (unwind
.pending_offset
)
27441 flush_pending_unwind ();
27443 unwind
.sp_restored
= 0;
27445 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
27447 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
27448 if (unwind
.opcodes
)
27449 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
27450 unwind
.opcode_alloc
);
27452 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
27457 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
27459 unwind
.opcode_count
++;
27463 /* Add unwind opcodes to adjust the stack pointer. */
27466 add_unwind_adjustsp (offsetT offset
)
27470 if (offset
> 0x200)
27472 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
27477 /* Long form: 0xb2, uleb128. */
27478 /* This might not fit in a word so add the individual bytes,
27479 remembering the list is built in reverse order. */
27480 o
= (valueT
) ((offset
- 0x204) >> 2);
27482 add_unwind_opcode (0, 1);
27484 /* Calculate the uleb128 encoding of the offset. */
27488 bytes
[n
] = o
& 0x7f;
27494 /* Add the insn. */
27496 add_unwind_opcode (bytes
[n
- 1], 1);
27497 add_unwind_opcode (0xb2, 1);
27499 else if (offset
> 0x100)
27501 /* Two short opcodes. */
27502 add_unwind_opcode (0x3f, 1);
27503 op
= (offset
- 0x104) >> 2;
27504 add_unwind_opcode (op
, 1);
27506 else if (offset
> 0)
27508 /* Short opcode. */
27509 op
= (offset
- 4) >> 2;
27510 add_unwind_opcode (op
, 1);
27512 else if (offset
< 0)
27515 while (offset
> 0x100)
27517 add_unwind_opcode (0x7f, 1);
27520 op
= ((offset
- 4) >> 2) | 0x40;
27521 add_unwind_opcode (op
, 1);
27525 /* Finish the list of unwind opcodes for this function. */
27528 finish_unwind_opcodes (void)
27532 if (unwind
.fp_used
)
27534 /* Adjust sp as necessary. */
27535 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
27536 flush_pending_unwind ();
27538 /* After restoring sp from the frame pointer. */
27539 op
= 0x90 | unwind
.fp_reg
;
27540 add_unwind_opcode (op
, 1);
27543 flush_pending_unwind ();
27547 /* Start an exception table entry. If idx is nonzero this is an index table
27551 start_unwind_section (const segT text_seg
, int idx
)
27553 const char * text_name
;
27554 const char * prefix
;
27555 const char * prefix_once
;
27556 struct elf_section_match match
;
27564 prefix
= ELF_STRING_ARM_unwind
;
27565 prefix_once
= ELF_STRING_ARM_unwind_once
;
27566 type
= SHT_ARM_EXIDX
;
27570 prefix
= ELF_STRING_ARM_unwind_info
;
27571 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
27572 type
= SHT_PROGBITS
;
27575 text_name
= segment_name (text_seg
);
27576 if (streq (text_name
, ".text"))
27579 if (strncmp (text_name
, ".gnu.linkonce.t.",
27580 strlen (".gnu.linkonce.t.")) == 0)
27582 prefix
= prefix_once
;
27583 text_name
+= strlen (".gnu.linkonce.t.");
27586 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
27590 memset (&match
, 0, sizeof (match
));
27592 /* Handle COMDAT group. */
27593 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
27595 match
.group_name
= elf_group_name (text_seg
);
27596 if (match
.group_name
== NULL
)
27598 as_bad (_("Group section `%s' has no group signature"),
27599 segment_name (text_seg
));
27600 ignore_rest_of_line ();
27603 flags
|= SHF_GROUP
;
27607 obj_elf_change_section (sec_name
, type
, flags
, 0, &match
,
27610 /* Set the section link for index tables. */
27612 elf_linked_to_section (now_seg
) = text_seg
;
27616 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
27617 personality routine data. Returns zero, or the index table value for
27618 an inline entry. */
27621 create_unwind_entry (int have_data
)
27626 /* The current word of data. */
27628 /* The number of bytes left in this word. */
27631 finish_unwind_opcodes ();
27633 /* Remember the current text section. */
27634 unwind
.saved_seg
= now_seg
;
27635 unwind
.saved_subseg
= now_subseg
;
27637 start_unwind_section (now_seg
, 0);
27639 if (unwind
.personality_routine
== NULL
)
27641 if (unwind
.personality_index
== -2)
27644 as_bad (_("handlerdata in cantunwind frame"));
27645 return 1; /* EXIDX_CANTUNWIND. */
27648 /* Use a default personality routine if none is specified. */
27649 if (unwind
.personality_index
== -1)
27651 if (unwind
.opcode_count
> 3)
27652 unwind
.personality_index
= 1;
27654 unwind
.personality_index
= 0;
27657 /* Space for the personality routine entry. */
27658 if (unwind
.personality_index
== 0)
27660 if (unwind
.opcode_count
> 3)
27661 as_bad (_("too many unwind opcodes for personality routine 0"));
27665 /* All the data is inline in the index table. */
27668 while (unwind
.opcode_count
> 0)
27670 unwind
.opcode_count
--;
27671 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27675 /* Pad with "finish" opcodes. */
27677 data
= (data
<< 8) | 0xb0;
27684 /* We get two opcodes "free" in the first word. */
27685 size
= unwind
.opcode_count
- 2;
27689 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
27690 if (unwind
.personality_index
!= -1)
27692 as_bad (_("attempt to recreate an unwind entry"));
27696 /* An extra byte is required for the opcode count. */
27697 size
= unwind
.opcode_count
+ 1;
27700 size
= (size
+ 3) >> 2;
27702 as_bad (_("too many unwind opcodes"));
27704 frag_align (2, 0, 0);
27705 record_alignment (now_seg
, 2);
27706 unwind
.table_entry
= expr_build_dot ();
27708 /* Allocate the table entry. */
27709 ptr
= frag_more ((size
<< 2) + 4);
27710 /* PR 13449: Zero the table entries in case some of them are not used. */
27711 memset (ptr
, 0, (size
<< 2) + 4);
27712 where
= frag_now_fix () - ((size
<< 2) + 4);
27714 switch (unwind
.personality_index
)
27717 /* ??? Should this be a PLT generating relocation? */
27718 /* Custom personality routine. */
27719 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
27720 BFD_RELOC_ARM_PREL31
);
27725 /* Set the first byte to the number of additional words. */
27726 data
= size
> 0 ? size
- 1 : 0;
27730 /* ABI defined personality routines. */
27732 /* Three opcodes bytes are packed into the first word. */
27739 /* The size and first two opcode bytes go in the first word. */
27740 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
27745 /* Should never happen. */
27749 /* Pack the opcodes into words (MSB first), reversing the list at the same
27751 while (unwind
.opcode_count
> 0)
27755 md_number_to_chars (ptr
, data
, 4);
27760 unwind
.opcode_count
--;
27762 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27765 /* Finish off the last word. */
27768 /* Pad with "finish" opcodes. */
27770 data
= (data
<< 8) | 0xb0;
27772 md_number_to_chars (ptr
, data
, 4);
27777 /* Add an empty descriptor if there is no user-specified data. */
27778 ptr
= frag_more (4);
27779 md_number_to_chars (ptr
, 0, 4);
27786 /* Initialize the DWARF-2 unwind information for this procedure. */
27789 tc_arm_frame_initial_instructions (void)
27791 cfi_add_CFA_def_cfa (REG_SP
, 0);
27793 #endif /* OBJ_ELF */
27795 /* Convert REGNAME to a DWARF-2 register number. */
27798 tc_arm_regname_to_dw2regnum (char *regname
)
27800 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
27804 /* PR 16694: Allow VFP registers as well. */
27805 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
27809 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
27818 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
27822 exp
.X_op
= O_secrel
;
27823 exp
.X_add_symbol
= symbol
;
27824 exp
.X_add_number
= 0;
27825 emit_expr (&exp
, size
);
27829 /* MD interface: Symbol and relocation handling. */
27831 /* Return the address within the segment that a PC-relative fixup is
27832 relative to. For ARM, PC-relative fixups applied to instructions
27833 are generally relative to the location of the fixup plus 8 bytes.
27834 Thumb branches are offset by 4, and Thumb loads relative to PC
27835 require special handling. */
27838 md_pcrel_from_section (fixS
* fixP
, segT seg
)
27840 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27842 /* If this is pc-relative and we are going to emit a relocation
27843 then we just want to put out any pipeline compensation that the linker
27844 will need. Otherwise we want to use the calculated base.
27845 For WinCE we skip the bias for externals as well, since this
27846 is how the MS ARM-CE assembler behaves and we want to be compatible. */
27848 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27849 || (arm_force_relocation (fixP
)
27851 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
27857 switch (fixP
->fx_r_type
)
27859 /* PC relative addressing on the Thumb is slightly odd as the
27860 bottom two bits of the PC are forced to zero for the
27861 calculation. This happens *after* application of the
27862 pipeline offset. However, Thumb adrl already adjusts for
27863 this, so we need not do it again. */
27864 case BFD_RELOC_ARM_THUMB_ADD
:
27867 case BFD_RELOC_ARM_THUMB_OFFSET
:
27868 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27869 case BFD_RELOC_ARM_T32_ADD_PC12
:
27870 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27871 return (base
+ 4) & ~3;
27873 /* Thumb branches are simply offset by +4. */
27874 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27875 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27876 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27877 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27878 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27879 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27880 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27881 case BFD_RELOC_ARM_THUMB_BF17
:
27882 case BFD_RELOC_ARM_THUMB_BF19
:
27883 case BFD_RELOC_ARM_THUMB_BF13
:
27884 case BFD_RELOC_ARM_THUMB_LOOP12
:
27887 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27889 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27890 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27891 && ARM_IS_FUNC (fixP
->fx_addsy
)
27892 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27893 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27896 /* BLX is like branches above, but forces the low two bits of PC to
27898 case BFD_RELOC_THUMB_PCREL_BLX
:
27900 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27901 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27902 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27903 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27904 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27905 return (base
+ 4) & ~3;
27907 /* ARM mode branches are offset by +8. However, the Windows CE
27908 loader expects the relocation not to take this into account. */
27909 case BFD_RELOC_ARM_PCREL_BLX
:
27911 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27912 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27913 && ARM_IS_FUNC (fixP
->fx_addsy
)
27914 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27915 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27918 case BFD_RELOC_ARM_PCREL_CALL
:
27920 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27921 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27922 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27923 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27924 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27927 case BFD_RELOC_ARM_PCREL_BRANCH
:
27928 case BFD_RELOC_ARM_PCREL_JUMP
:
27929 case BFD_RELOC_ARM_PLT32
:
27931 /* When handling fixups immediately, because we have already
27932 discovered the value of a symbol, or the address of the frag involved
27933 we must account for the offset by +8, as the OS loader will never see the reloc.
27934 see fixup_segment() in write.c
27935 The S_IS_EXTERNAL test handles the case of global symbols.
27936 Those need the calculated base, not just the pipe compensation the linker will need. */
27938 && fixP
->fx_addsy
!= NULL
27939 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27940 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27948 /* ARM mode loads relative to PC are also offset by +8. Unlike
27949 branches, the Windows CE loader *does* expect the relocation
27950 to take this into account. */
27951 case BFD_RELOC_ARM_OFFSET_IMM
:
27952 case BFD_RELOC_ARM_OFFSET_IMM8
:
27953 case BFD_RELOC_ARM_HWLITERAL
:
27954 case BFD_RELOC_ARM_LITERAL
:
27955 case BFD_RELOC_ARM_CP_OFF_IMM
:
27959 /* Other PC-relative relocations are un-offset. */
27965 static bfd_boolean flag_warn_syms
= TRUE
;
27968 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27970 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27971 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27972 does mean that the resulting code might be very confusing to the reader.
27973 Also this warning can be triggered if the user omits an operand before
27974 an immediate address, eg:
27978 GAS treats this as an assignment of the value of the symbol foo to a
27979 symbol LDR, and so (without this code) it will not issue any kind of
27980 warning or error message.
27982 Note - ARM instructions are case-insensitive but the strings in the hash
27983 table are all stored in lower case, so we must first ensure that name is
27985 if (flag_warn_syms
&& arm_ops_hsh
)
27987 char * nbuf
= strdup (name
);
27990 for (p
= nbuf
; *p
; p
++)
27992 if (str_hash_find (arm_ops_hsh
, nbuf
) != NULL
)
27994 static htab_t already_warned
= NULL
;
27996 if (already_warned
== NULL
)
27997 already_warned
= str_htab_create ();
27998 /* Only warn about the symbol once. To keep the code
27999 simple we let str_hash_insert do the lookup for us. */
28000 if (str_hash_find (already_warned
, nbuf
) == NULL
)
28002 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
28003 str_hash_insert (already_warned
, nbuf
, NULL
, 0);
28013 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
28014 Otherwise we have no need to default values of symbols. */
28017 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
28020 if (name
[0] == '_' && name
[1] == 'G'
28021 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
28025 if (symbol_find (name
))
28026 as_bad (_("GOT already in the symbol table"));
28028 GOT_symbol
= symbol_new (name
, undefined_section
,
28029 &zero_address_frag
, 0);
28039 /* Subroutine of md_apply_fix. Check to see if an immediate can be
28040 computed as two separate immediate values, added together. We
28041 already know that this value cannot be computed by just one ARM
28044 static unsigned int
28045 validate_immediate_twopart (unsigned int val
,
28046 unsigned int * highpart
)
28051 for (i
= 0; i
< 32; i
+= 2)
28052 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
28058 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
28060 else if (a
& 0xff0000)
28062 if (a
& 0xff000000)
28064 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
28068 gas_assert (a
& 0xff000000);
28069 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
28072 return (a
& 0xff) | (i
<< 7);
28079 validate_offset_imm (unsigned int val
, int hwse
)
28081 if ((hwse
&& val
> 255) || val
> 4095)
28086 /* Subroutine of md_apply_fix. Do those data_ops which can take a
28087 negative immediate constant by altering the instruction. A bit of
28092 by inverting the second operand, and
28095 by negating the second operand. */
28098 negate_data_op (unsigned long * instruction
,
28099 unsigned long value
)
28102 unsigned long negated
, inverted
;
28104 negated
= encode_arm_immediate (-value
);
28105 inverted
= encode_arm_immediate (~value
);
28107 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
28110 /* First negates. */
28111 case OPCODE_SUB
: /* ADD <-> SUB */
28112 new_inst
= OPCODE_ADD
;
28117 new_inst
= OPCODE_SUB
;
28121 case OPCODE_CMP
: /* CMP <-> CMN */
28122 new_inst
= OPCODE_CMN
;
28127 new_inst
= OPCODE_CMP
;
28131 /* Now Inverted ops. */
28132 case OPCODE_MOV
: /* MOV <-> MVN */
28133 new_inst
= OPCODE_MVN
;
28138 new_inst
= OPCODE_MOV
;
28142 case OPCODE_AND
: /* AND <-> BIC */
28143 new_inst
= OPCODE_BIC
;
28148 new_inst
= OPCODE_AND
;
28152 case OPCODE_ADC
: /* ADC <-> SBC */
28153 new_inst
= OPCODE_SBC
;
28158 new_inst
= OPCODE_ADC
;
28162 /* We cannot do anything. */
28167 if (value
== (unsigned) FAIL
)
28170 *instruction
&= OPCODE_MASK
;
28171 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
28175 /* Like negate_data_op, but for Thumb-2. */
28177 static unsigned int
28178 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
28182 unsigned int negated
, inverted
;
28184 negated
= encode_thumb32_immediate (-value
);
28185 inverted
= encode_thumb32_immediate (~value
);
28187 rd
= (*instruction
>> 8) & 0xf;
28188 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
28191 /* ADD <-> SUB. Includes CMP <-> CMN. */
28192 case T2_OPCODE_SUB
:
28193 new_inst
= T2_OPCODE_ADD
;
28197 case T2_OPCODE_ADD
:
28198 new_inst
= T2_OPCODE_SUB
;
28202 /* ORR <-> ORN. Includes MOV <-> MVN. */
28203 case T2_OPCODE_ORR
:
28204 new_inst
= T2_OPCODE_ORN
;
28208 case T2_OPCODE_ORN
:
28209 new_inst
= T2_OPCODE_ORR
;
28213 /* AND <-> BIC. TST has no inverted equivalent. */
28214 case T2_OPCODE_AND
:
28215 new_inst
= T2_OPCODE_BIC
;
28222 case T2_OPCODE_BIC
:
28223 new_inst
= T2_OPCODE_AND
;
28228 case T2_OPCODE_ADC
:
28229 new_inst
= T2_OPCODE_SBC
;
28233 case T2_OPCODE_SBC
:
28234 new_inst
= T2_OPCODE_ADC
;
28238 /* We cannot do anything. */
28243 if (value
== (unsigned int)FAIL
)
28246 *instruction
&= T2_OPCODE_MASK
;
28247 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
28251 /* Read a 32-bit thumb instruction from buf. */
28253 static unsigned long
28254 get_thumb32_insn (char * buf
)
28256 unsigned long insn
;
28257 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
28258 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28263 /* We usually want to set the low bit on the address of thumb function
28264 symbols. In particular .word foo - . should have the low bit set.
28265 Generic code tries to fold the difference of two symbols to
28266 a constant. Prevent this and force a relocation when the first symbols
28267 is a thumb function. */
28270 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
28272 if (op
== O_subtract
28273 && l
->X_op
== O_symbol
28274 && r
->X_op
== O_symbol
28275 && THUMB_IS_FUNC (l
->X_add_symbol
))
28277 l
->X_op
= O_subtract
;
28278 l
->X_op_symbol
= r
->X_add_symbol
;
28279 l
->X_add_number
-= r
->X_add_number
;
28283 /* Process as normal. */
28287 /* Encode Thumb2 unconditional branches and calls. The encoding
28288 for the 2 are identical for the immediate values. */
28291 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
28293 #define T2I1I2MASK ((1 << 13) | (1 << 11))
28296 addressT S
, I1
, I2
, lo
, hi
;
28298 S
= (value
>> 24) & 0x01;
28299 I1
= (value
>> 23) & 0x01;
28300 I2
= (value
>> 22) & 0x01;
28301 hi
= (value
>> 12) & 0x3ff;
28302 lo
= (value
>> 1) & 0x7ff;
28303 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28304 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28305 newval
|= (S
<< 10) | hi
;
28306 newval2
&= ~T2I1I2MASK
;
28307 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
28308 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28309 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28313 md_apply_fix (fixS
* fixP
,
28317 offsetT value
= * valP
;
28319 unsigned int newimm
;
28320 unsigned long temp
;
28322 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
28324 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
28326 /* Note whether this will delete the relocation. */
28328 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
28331 /* On a 64-bit host, silently truncate 'value' to 32 bits for
28332 consistency with the behaviour on 32-bit hosts. Remember value
28334 value
&= 0xffffffff;
28335 value
^= 0x80000000;
28336 value
-= 0x80000000;
28339 fixP
->fx_addnumber
= value
;
28341 /* Same treatment for fixP->fx_offset. */
28342 fixP
->fx_offset
&= 0xffffffff;
28343 fixP
->fx_offset
^= 0x80000000;
28344 fixP
->fx_offset
-= 0x80000000;
28346 switch (fixP
->fx_r_type
)
28348 case BFD_RELOC_NONE
:
28349 /* This will need to go in the object file. */
28353 case BFD_RELOC_ARM_IMMEDIATE
:
28354 /* We claim that this fixup has been processed here,
28355 even if in fact we generate an error because we do
28356 not have a reloc for it, so tc_gen_reloc will reject it. */
28359 if (fixP
->fx_addsy
)
28361 const char *msg
= 0;
28363 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28364 msg
= _("undefined symbol %s used as an immediate value");
28365 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28366 msg
= _("symbol %s is in a different section");
28367 else if (S_IS_WEAK (fixP
->fx_addsy
))
28368 msg
= _("symbol %s is weak and may be overridden later");
28372 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28373 msg
, S_GET_NAME (fixP
->fx_addsy
));
28378 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28380 /* If the offset is negative, we should use encoding A2 for ADR. */
28381 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
28382 newimm
= negate_data_op (&temp
, value
);
28385 newimm
= encode_arm_immediate (value
);
28387 /* If the instruction will fail, see if we can fix things up by
28388 changing the opcode. */
28389 if (newimm
== (unsigned int) FAIL
)
28390 newimm
= negate_data_op (&temp
, value
);
28391 /* MOV accepts both ARM modified immediate (A1 encoding) and
28392 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
28393 When disassembling, MOV is preferred when there is no encoding
28395 if (newimm
== (unsigned int) FAIL
28396 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
28397 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
28398 && !((temp
>> SBIT_SHIFT
) & 0x1)
28399 && value
>= 0 && value
<= 0xffff)
28401 /* Clear bits[23:20] to change encoding from A1 to A2. */
28402 temp
&= 0xff0fffff;
28403 /* Encoding high 4bits imm. Code below will encode the remaining
28405 temp
|= (value
& 0x0000f000) << 4;
28406 newimm
= value
& 0x00000fff;
28410 if (newimm
== (unsigned int) FAIL
)
28412 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28413 _("invalid constant (%lx) after fixup"),
28414 (unsigned long) value
);
28418 newimm
|= (temp
& 0xfffff000);
28419 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28422 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28424 unsigned int highpart
= 0;
28425 unsigned int newinsn
= 0xe1a00000; /* nop. */
28427 if (fixP
->fx_addsy
)
28429 const char *msg
= 0;
28431 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28432 msg
= _("undefined symbol %s used as an immediate value");
28433 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28434 msg
= _("symbol %s is in a different section");
28435 else if (S_IS_WEAK (fixP
->fx_addsy
))
28436 msg
= _("symbol %s is weak and may be overridden later");
28440 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28441 msg
, S_GET_NAME (fixP
->fx_addsy
));
28446 newimm
= encode_arm_immediate (value
);
28447 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28449 /* If the instruction will fail, see if we can fix things up by
28450 changing the opcode. */
28451 if (newimm
== (unsigned int) FAIL
28452 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
28454 /* No ? OK - try using two ADD instructions to generate
28456 newimm
= validate_immediate_twopart (value
, & highpart
);
28458 /* Yes - then make sure that the second instruction is
28460 if (newimm
!= (unsigned int) FAIL
)
28462 /* Still No ? Try using a negated value. */
28463 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
28464 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
28465 /* Otherwise - give up. */
28468 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28469 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
28474 /* Replace the first operand in the 2nd instruction (which
28475 is the PC) with the destination register. We have
28476 already added in the PC in the first instruction and we
28477 do not want to do it again. */
28478 newinsn
&= ~ 0xf0000;
28479 newinsn
|= ((newinsn
& 0x0f000) << 4);
28482 newimm
|= (temp
& 0xfffff000);
28483 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28485 highpart
|= (newinsn
& 0xfffff000);
28486 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
28490 case BFD_RELOC_ARM_OFFSET_IMM
:
28491 if (!fixP
->fx_done
&& seg
->use_rela_p
)
28493 /* Fall through. */
28495 case BFD_RELOC_ARM_LITERAL
:
28501 if (validate_offset_imm (value
, 0) == FAIL
)
28503 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
28504 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28505 _("invalid literal constant: pool needs to be closer"));
28507 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28508 _("bad immediate value for offset (%ld)"),
28513 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28515 newval
&= 0xfffff000;
28518 newval
&= 0xff7ff000;
28519 newval
|= value
| (sign
? INDEX_UP
: 0);
28521 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28524 case BFD_RELOC_ARM_OFFSET_IMM8
:
28525 case BFD_RELOC_ARM_HWLITERAL
:
28531 if (validate_offset_imm (value
, 1) == FAIL
)
28533 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
28534 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28535 _("invalid literal constant: pool needs to be closer"));
28537 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28538 _("bad immediate value for 8-bit offset (%ld)"),
28543 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28545 newval
&= 0xfffff0f0;
28548 newval
&= 0xff7ff0f0;
28549 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
28551 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28554 case BFD_RELOC_ARM_T32_OFFSET_U8
:
28555 if (value
< 0 || value
> 1020 || value
% 4 != 0)
28556 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28557 _("bad immediate value for offset (%ld)"), (long) value
);
28560 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
28562 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
28565 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
28566 /* This is a complicated relocation used for all varieties of Thumb32
28567 load/store instruction with immediate offset:
28569 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
28570 *4, optional writeback(W)
28571 (doubleword load/store)
28573 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
28574 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
28575 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
28576 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
28577 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
28579 Uppercase letters indicate bits that are already encoded at
28580 this point. Lowercase letters are our problem. For the
28581 second block of instructions, the secondary opcode nybble
28582 (bits 8..11) is present, and bit 23 is zero, even if this is
28583 a PC-relative operation. */
28584 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28586 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
28588 if ((newval
& 0xf0000000) == 0xe0000000)
28590 /* Doubleword load/store: 8-bit offset, scaled by 4. */
28592 newval
|= (1 << 23);
28595 if (value
% 4 != 0)
28597 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28598 _("offset not a multiple of 4"));
28604 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28605 _("offset out of range"));
28610 else if ((newval
& 0x000f0000) == 0x000f0000)
28612 /* PC-relative, 12-bit offset. */
28614 newval
|= (1 << 23);
28619 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28620 _("offset out of range"));
28625 else if ((newval
& 0x00000100) == 0x00000100)
28627 /* Writeback: 8-bit, +/- offset. */
28629 newval
|= (1 << 9);
28634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28635 _("offset out of range"));
28640 else if ((newval
& 0x00000f00) == 0x00000e00)
28642 /* T-instruction: positive 8-bit offset. */
28643 if (value
< 0 || value
> 0xff)
28645 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28646 _("offset out of range"));
28654 /* Positive 12-bit or negative 8-bit offset. */
28658 newval
|= (1 << 23);
28668 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28669 _("offset out of range"));
28676 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
28677 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
28680 case BFD_RELOC_ARM_SHIFT_IMM
:
28681 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28682 if (((unsigned long) value
) > 32
28684 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
28686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28687 _("shift expression is too large"));
28692 /* Shifts of zero must be done as lsl. */
28694 else if (value
== 32)
28696 newval
&= 0xfffff07f;
28697 newval
|= (value
& 0x1f) << 7;
28698 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28701 case BFD_RELOC_ARM_T32_IMMEDIATE
:
28702 case BFD_RELOC_ARM_T32_ADD_IMM
:
28703 case BFD_RELOC_ARM_T32_IMM12
:
28704 case BFD_RELOC_ARM_T32_ADD_PC12
:
28705 /* We claim that this fixup has been processed here,
28706 even if in fact we generate an error because we do
28707 not have a reloc for it, so tc_gen_reloc will reject it. */
28711 && ! S_IS_DEFINED (fixP
->fx_addsy
))
28713 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28714 _("undefined symbol %s used as an immediate value"),
28715 S_GET_NAME (fixP
->fx_addsy
));
28719 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28721 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
28724 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
28725 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
28726 Thumb2 modified immediate encoding (T2). */
28727 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
28728 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28730 newimm
= encode_thumb32_immediate (value
);
28731 if (newimm
== (unsigned int) FAIL
)
28732 newimm
= thumb32_negate_data_op (&newval
, value
);
28734 if (newimm
== (unsigned int) FAIL
)
28736 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
28738 /* Turn add/sum into addw/subw. */
28739 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28740 newval
= (newval
& 0xfeffffff) | 0x02000000;
28741 /* No flat 12-bit imm encoding for addsw/subsw. */
28742 if ((newval
& 0x00100000) == 0)
28744 /* 12 bit immediate for addw/subw. */
28748 newval
^= 0x00a00000;
28751 newimm
= (unsigned int) FAIL
;
28758 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
28759 UINT16 (T3 encoding), MOVW only accepts UINT16. When
28760 disassembling, MOV is preferred when there is no encoding
28762 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
28763 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
28764 but with the Rn field [19:16] set to 1111. */
28765 && (((newval
>> 16) & 0xf) == 0xf)
28766 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
28767 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
28768 && value
>= 0 && value
<= 0xffff)
28770 /* Toggle bit[25] to change encoding from T2 to T3. */
28772 /* Clear bits[19:16]. */
28773 newval
&= 0xfff0ffff;
28774 /* Encoding high 4bits imm. Code below will encode the
28775 remaining low 12bits. */
28776 newval
|= (value
& 0x0000f000) << 4;
28777 newimm
= value
& 0x00000fff;
28782 if (newimm
== (unsigned int)FAIL
)
28784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28785 _("invalid constant (%lx) after fixup"),
28786 (unsigned long) value
);
28790 newval
|= (newimm
& 0x800) << 15;
28791 newval
|= (newimm
& 0x700) << 4;
28792 newval
|= (newimm
& 0x0ff);
28794 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
28795 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
28798 case BFD_RELOC_ARM_SMC
:
28799 if (((unsigned long) value
) > 0xf)
28800 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28801 _("invalid smc expression"));
28803 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28804 newval
|= (value
& 0xf);
28805 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28808 case BFD_RELOC_ARM_HVC
:
28809 if (((unsigned long) value
) > 0xffff)
28810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28811 _("invalid hvc expression"));
28812 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28813 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
28814 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28817 case BFD_RELOC_ARM_SWI
:
28818 if (fixP
->tc_fix_data
!= 0)
28820 if (((unsigned long) value
) > 0xff)
28821 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28822 _("invalid swi expression"));
28823 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28825 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28829 if (((unsigned long) value
) > 0x00ffffff)
28830 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28831 _("invalid swi expression"));
28832 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28834 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28838 case BFD_RELOC_ARM_MULTI
:
28839 if (((unsigned long) value
) > 0xffff)
28840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28841 _("invalid expression in load/store multiple"));
28842 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
28843 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28847 case BFD_RELOC_ARM_PCREL_CALL
:
28849 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28851 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28852 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28853 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28854 /* Flip the bl to blx. This is a simple flip
28855 bit here because we generate PCREL_CALL for
28856 unconditional bls. */
28858 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28859 newval
= newval
| 0x10000000;
28860 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28866 goto arm_branch_common
;
28868 case BFD_RELOC_ARM_PCREL_JUMP
:
28869 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28871 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28872 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28873 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28875 /* This would map to a bl<cond>, b<cond>,
28876 b<always> to a Thumb function. We
28877 need to force a relocation for this particular
28879 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28882 /* Fall through. */
28884 case BFD_RELOC_ARM_PLT32
:
28886 case BFD_RELOC_ARM_PCREL_BRANCH
:
28888 goto arm_branch_common
;
28890 case BFD_RELOC_ARM_PCREL_BLX
:
28893 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28895 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28896 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28897 && ARM_IS_FUNC (fixP
->fx_addsy
))
28899 /* Flip the blx to a bl and warn. */
28900 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28901 newval
= 0xeb000000;
28902 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28903 _("blx to '%s' an ARM ISA state function changed to bl"),
28905 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28911 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28912 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
28916 /* We are going to store value (shifted right by two) in the
28917 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28918 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
28921 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28922 _("misaligned branch destination"));
28923 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
28924 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
28925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28927 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28929 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28930 newval
|= (value
>> 2) & 0x00ffffff;
28931 /* Set the H bit on BLX instructions. */
28935 newval
|= 0x01000000;
28937 newval
&= ~0x01000000;
28939 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28943 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28944 /* CBZ can only branch forward. */
28946 /* Attempts to use CBZ to branch to the next instruction
28947 (which, strictly speaking, are prohibited) will be turned into
28950 FIXME: It may be better to remove the instruction completely and
28951 perform relaxation. */
28954 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28955 newval
= 0xbf00; /* NOP encoding T1 */
28956 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28963 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28965 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28966 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28967 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28972 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28973 if (out_of_range_p (value
, 8))
28974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28976 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28978 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28979 newval
|= (value
& 0x1ff) >> 1;
28980 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28984 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28985 if (out_of_range_p (value
, 11))
28986 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28988 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28990 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28991 newval
|= (value
& 0xfff) >> 1;
28992 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28996 /* This relocation is misnamed, it should be BRANCH21. */
28997 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28999 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29000 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29001 && ARM_IS_FUNC (fixP
->fx_addsy
)
29002 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29004 /* Force a relocation for a branch 20 bits wide. */
29007 if (out_of_range_p (value
, 20))
29008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29009 _("conditional branch out of range"));
29011 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29014 addressT S
, J1
, J2
, lo
, hi
;
29016 S
= (value
& 0x00100000) >> 20;
29017 J2
= (value
& 0x00080000) >> 19;
29018 J1
= (value
& 0x00040000) >> 18;
29019 hi
= (value
& 0x0003f000) >> 12;
29020 lo
= (value
& 0x00000ffe) >> 1;
29022 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29023 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29024 newval
|= (S
<< 10) | hi
;
29025 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
29026 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29027 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29031 case BFD_RELOC_THUMB_PCREL_BLX
:
29032 /* If there is a blx from a thumb state function to
29033 another thumb function flip this to a bl and warn
29037 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29038 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29039 && THUMB_IS_FUNC (fixP
->fx_addsy
))
29041 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
29042 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29043 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
29045 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29046 newval
= newval
| 0x1000;
29047 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29048 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29053 goto thumb_bl_common
;
29055 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29056 /* A bl from Thumb state ISA to an internal ARM state function
29057 is converted to a blx. */
29059 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29060 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29061 && ARM_IS_FUNC (fixP
->fx_addsy
)
29062 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29064 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29065 newval
= newval
& ~0x1000;
29066 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29067 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
29073 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29074 /* For a BLX instruction, make sure that the relocation is rounded up
29075 to a word boundary. This follows the semantics of the instruction
29076 which specifies that bit 1 of the target address will come from bit
29077 1 of the base address. */
29078 value
= (value
+ 3) & ~ 3;
29081 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
29082 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29083 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29086 if (out_of_range_p (value
, 22))
29088 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
29089 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29090 else if (out_of_range_p (value
, 24))
29091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29092 _("Thumb2 branch out of range"));
29095 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29096 encode_thumb2_b_bl_offset (buf
, value
);
29100 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29101 if (out_of_range_p (value
, 24))
29102 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29104 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29105 encode_thumb2_b_bl_offset (buf
, value
);
29110 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29115 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29116 md_number_to_chars (buf
, value
, 2);
29120 case BFD_RELOC_ARM_TLS_CALL
:
29121 case BFD_RELOC_ARM_THM_TLS_CALL
:
29122 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29123 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29124 case BFD_RELOC_ARM_TLS_GOTDESC
:
29125 case BFD_RELOC_ARM_TLS_GD32
:
29126 case BFD_RELOC_ARM_TLS_LE32
:
29127 case BFD_RELOC_ARM_TLS_IE32
:
29128 case BFD_RELOC_ARM_TLS_LDM32
:
29129 case BFD_RELOC_ARM_TLS_LDO32
:
29130 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29133 /* Same handling as above, but with the arm_fdpic guard. */
29134 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29135 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29136 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29139 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29143 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29144 _("Relocation supported only in FDPIC mode"));
29148 case BFD_RELOC_ARM_GOT32
:
29149 case BFD_RELOC_ARM_GOTOFF
:
29152 case BFD_RELOC_ARM_GOT_PREL
:
29153 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29154 md_number_to_chars (buf
, value
, 4);
29157 case BFD_RELOC_ARM_TARGET2
:
29158 /* TARGET2 is not partial-inplace, so we need to write the
29159 addend here for REL targets, because it won't be written out
29160 during reloc processing later. */
29161 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29162 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
29165 /* Relocations for FDPIC. */
29166 case BFD_RELOC_ARM_GOTFUNCDESC
:
29167 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29168 case BFD_RELOC_ARM_FUNCDESC
:
29171 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29172 md_number_to_chars (buf
, 0, 4);
29176 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29177 _("Relocation supported only in FDPIC mode"));
29182 case BFD_RELOC_RVA
:
29184 case BFD_RELOC_ARM_TARGET1
:
29185 case BFD_RELOC_ARM_ROSEGREL32
:
29186 case BFD_RELOC_ARM_SBREL32
:
29187 case BFD_RELOC_32_PCREL
:
29189 case BFD_RELOC_32_SECREL
:
29191 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29193 /* For WinCE we only do this for pcrel fixups. */
29194 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
29196 md_number_to_chars (buf
, value
, 4);
29200 case BFD_RELOC_ARM_PREL31
:
29201 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29203 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
29204 if ((value
^ (value
>> 1)) & 0x40000000)
29206 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29207 _("rel31 relocation overflow"));
29209 newval
|= value
& 0x7fffffff;
29210 md_number_to_chars (buf
, newval
, 4);
29215 case BFD_RELOC_ARM_CP_OFF_IMM
:
29216 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
29217 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
29218 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
29219 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29221 newval
= get_thumb32_insn (buf
);
29222 if ((newval
& 0x0f200f00) == 0x0d000900)
29224 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
29225 has permitted values that are multiples of 2, in the range 0
29227 if (value
< -510 || value
> 510 || (value
& 1))
29228 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29229 _("co-processor offset out of range"));
29231 else if ((newval
& 0xfe001f80) == 0xec000f80)
29233 if (value
< -511 || value
> 512 || (value
& 3))
29234 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29235 _("co-processor offset out of range"));
29237 else if (value
< -1023 || value
> 1023 || (value
& 3))
29238 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29239 _("co-processor offset out of range"));
29244 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29245 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29246 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29248 newval
= get_thumb32_insn (buf
);
29251 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29252 newval
&= 0xffffff80;
29254 newval
&= 0xffffff00;
29258 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29259 newval
&= 0xff7fff80;
29261 newval
&= 0xff7fff00;
29262 if ((newval
& 0x0f200f00) == 0x0d000900)
29264 /* This is a fp16 vstr/vldr.
29266 It requires the immediate offset in the instruction is shifted
29267 left by 1 to be a half-word offset.
29269 Here, left shift by 1 first, and later right shift by 2
29270 should get the right offset. */
29273 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
29275 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29276 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29277 md_number_to_chars (buf
, newval
, INSN_SIZE
);
29279 put_thumb32_insn (buf
, newval
);
29282 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
29283 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
29284 if (value
< -255 || value
> 255)
29285 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29286 _("co-processor offset out of range"));
29288 goto cp_off_common
;
29290 case BFD_RELOC_ARM_THUMB_OFFSET
:
29291 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29292 /* Exactly what ranges, and where the offset is inserted depends
29293 on the type of instruction, we can establish this from the
29295 switch (newval
>> 12)
29297 case 4: /* PC load. */
29298 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
29299 forced to zero for these loads; md_pcrel_from has already
29300 compensated for this. */
29302 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29303 _("invalid offset, target not word aligned (0x%08lX)"),
29304 (((unsigned long) fixP
->fx_frag
->fr_address
29305 + (unsigned long) fixP
->fx_where
) & ~3)
29306 + (unsigned long) value
);
29307 else if (get_recorded_alignment (seg
) < 2)
29308 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29309 _("section does not have enough alignment to ensure safe PC-relative loads"));
29311 if (value
& ~0x3fc)
29312 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29313 _("invalid offset, value too big (0x%08lX)"),
29316 newval
|= value
>> 2;
29319 case 9: /* SP load/store. */
29320 if (value
& ~0x3fc)
29321 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29322 _("invalid offset, value too big (0x%08lX)"),
29324 newval
|= value
>> 2;
29327 case 6: /* Word load/store. */
29329 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29330 _("invalid offset, value too big (0x%08lX)"),
29332 newval
|= value
<< 4; /* 6 - 2. */
29335 case 7: /* Byte load/store. */
29337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29338 _("invalid offset, value too big (0x%08lX)"),
29340 newval
|= value
<< 6;
29343 case 8: /* Halfword load/store. */
29345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29346 _("invalid offset, value too big (0x%08lX)"),
29348 newval
|= value
<< 5; /* 6 - 1. */
29352 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29353 "Unable to process relocation for thumb opcode: %lx",
29354 (unsigned long) newval
);
29357 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29360 case BFD_RELOC_ARM_THUMB_ADD
:
29361 /* This is a complicated relocation, since we use it for all of
29362 the following immediate relocations:
29366 9bit ADD/SUB SP word-aligned
29367 10bit ADD PC/SP word-aligned
29369 The type of instruction being processed is encoded in the
29376 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29378 int rd
= (newval
>> 4) & 0xf;
29379 int rs
= newval
& 0xf;
29380 int subtract
= !!(newval
& 0x8000);
29382 /* Check for HI regs, only very restricted cases allowed:
29383 Adjusting SP, and using PC or SP to get an address. */
29384 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
29385 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
29386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29387 _("invalid Hi register with immediate"));
29389 /* If value is negative, choose the opposite instruction. */
29393 subtract
= !subtract
;
29395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29396 _("immediate value out of range"));
29401 if (value
& ~0x1fc)
29402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29403 _("invalid immediate for stack address calculation"));
29404 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
29405 newval
|= value
>> 2;
29407 else if (rs
== REG_PC
|| rs
== REG_SP
)
29409 /* PR gas/18541. If the addition is for a defined symbol
29410 within range of an ADR instruction then accept it. */
29413 && fixP
->fx_addsy
!= NULL
)
29417 if (! S_IS_DEFINED (fixP
->fx_addsy
)
29418 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
29419 || S_IS_WEAK (fixP
->fx_addsy
))
29421 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29422 _("address calculation needs a strongly defined nearby symbol"));
29426 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
29428 /* Round up to the next 4-byte boundary. */
29433 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
29437 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29438 _("symbol too far away"));
29448 if (subtract
|| value
& ~0x3fc)
29449 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29450 _("invalid immediate for address calculation (value = 0x%08lX)"),
29451 (unsigned long) (subtract
? - value
: value
));
29452 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
29454 newval
|= value
>> 2;
29459 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29460 _("immediate value out of range"));
29461 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
29462 newval
|= (rd
<< 8) | value
;
29467 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29468 _("immediate value out of range"));
29469 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
29470 newval
|= rd
| (rs
<< 3) | (value
<< 6);
29473 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29476 case BFD_RELOC_ARM_THUMB_IMM
:
29477 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29478 if (value
< 0 || value
> 255)
29479 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29480 _("invalid immediate: %ld is out of range"),
29483 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29486 case BFD_RELOC_ARM_THUMB_SHIFT
:
29487 /* 5bit shift value (0..32). LSL cannot take 32. */
29488 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
29489 temp
= newval
& 0xf800;
29490 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
29491 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29492 _("invalid shift value: %ld"), (long) value
);
29493 /* Shifts of zero must be encoded as LSL. */
29495 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
29496 /* Shifts of 32 are encoded as zero. */
29497 else if (value
== 32)
29499 newval
|= value
<< 6;
29500 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29503 case BFD_RELOC_VTABLE_INHERIT
:
29504 case BFD_RELOC_VTABLE_ENTRY
:
29508 case BFD_RELOC_ARM_MOVW
:
29509 case BFD_RELOC_ARM_MOVT
:
29510 case BFD_RELOC_ARM_THUMB_MOVW
:
29511 case BFD_RELOC_ARM_THUMB_MOVT
:
29512 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29514 /* REL format relocations are limited to a 16-bit addend. */
29515 if (!fixP
->fx_done
)
29517 if (value
< -0x8000 || value
> 0x7fff)
29518 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29519 _("offset out of range"));
29521 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29522 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29527 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29528 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29530 newval
= get_thumb32_insn (buf
);
29531 newval
&= 0xfbf08f00;
29532 newval
|= (value
& 0xf000) << 4;
29533 newval
|= (value
& 0x0800) << 15;
29534 newval
|= (value
& 0x0700) << 4;
29535 newval
|= (value
& 0x00ff);
29536 put_thumb32_insn (buf
, newval
);
29540 newval
= md_chars_to_number (buf
, 4);
29541 newval
&= 0xfff0f000;
29542 newval
|= value
& 0x0fff;
29543 newval
|= (value
& 0xf000) << 4;
29544 md_number_to_chars (buf
, newval
, 4);
29549 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29550 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29551 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29552 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29553 gas_assert (!fixP
->fx_done
);
29556 bfd_boolean is_mov
;
29557 bfd_vma encoded_addend
= value
;
29559 /* Check that addend can be encoded in instruction. */
29560 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
29561 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29562 _("the offset 0x%08lX is not representable"),
29563 (unsigned long) encoded_addend
);
29565 /* Extract the instruction. */
29566 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
29567 is_mov
= (insn
& 0xf800) == 0x2000;
29572 if (!seg
->use_rela_p
)
29573 insn
|= encoded_addend
;
29579 /* Extract the instruction. */
29580 /* Encoding is the following
29585 /* The following conditions must be true :
29590 rd
= (insn
>> 4) & 0xf;
29592 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
29593 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29594 _("Unable to process relocation for thumb opcode: %lx"),
29595 (unsigned long) insn
);
29597 /* Encode as ADD immediate8 thumb 1 code. */
29598 insn
= 0x3000 | (rd
<< 8);
29600 /* Place the encoded addend into the first 8 bits of the
29602 if (!seg
->use_rela_p
)
29603 insn
|= encoded_addend
;
29606 /* Update the instruction. */
29607 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
29611 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29612 case BFD_RELOC_ARM_ALU_PC_G0
:
29613 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29614 case BFD_RELOC_ARM_ALU_PC_G1
:
29615 case BFD_RELOC_ARM_ALU_PC_G2
:
29616 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29617 case BFD_RELOC_ARM_ALU_SB_G0
:
29618 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29619 case BFD_RELOC_ARM_ALU_SB_G1
:
29620 case BFD_RELOC_ARM_ALU_SB_G2
:
29621 gas_assert (!fixP
->fx_done
);
29622 if (!seg
->use_rela_p
)
29625 bfd_vma encoded_addend
;
29626 bfd_vma addend_abs
= llabs (value
);
29628 /* Check that the absolute value of the addend can be
29629 expressed as an 8-bit constant plus a rotation. */
29630 encoded_addend
= encode_arm_immediate (addend_abs
);
29631 if (encoded_addend
== (unsigned int) FAIL
)
29632 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29633 _("the offset 0x%08lX is not representable"),
29634 (unsigned long) addend_abs
);
29636 /* Extract the instruction. */
29637 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29639 /* If the addend is positive, use an ADD instruction.
29640 Otherwise use a SUB. Take care not to destroy the S bit. */
29641 insn
&= 0xff1fffff;
29647 /* Place the encoded addend into the first 12 bits of the
29649 insn
&= 0xfffff000;
29650 insn
|= encoded_addend
;
29652 /* Update the instruction. */
29653 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29657 case BFD_RELOC_ARM_LDR_PC_G0
:
29658 case BFD_RELOC_ARM_LDR_PC_G1
:
29659 case BFD_RELOC_ARM_LDR_PC_G2
:
29660 case BFD_RELOC_ARM_LDR_SB_G0
:
29661 case BFD_RELOC_ARM_LDR_SB_G1
:
29662 case BFD_RELOC_ARM_LDR_SB_G2
:
29663 gas_assert (!fixP
->fx_done
);
29664 if (!seg
->use_rela_p
)
29667 bfd_vma addend_abs
= llabs (value
);
29669 /* Check that the absolute value of the addend can be
29670 encoded in 12 bits. */
29671 if (addend_abs
>= 0x1000)
29672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29673 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
29674 (unsigned long) addend_abs
);
29676 /* Extract the instruction. */
29677 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29679 /* If the addend is negative, clear bit 23 of the instruction.
29680 Otherwise set it. */
29682 insn
&= ~(1 << 23);
29686 /* Place the absolute value of the addend into the first 12 bits
29687 of the instruction. */
29688 insn
&= 0xfffff000;
29689 insn
|= addend_abs
;
29691 /* Update the instruction. */
29692 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29696 case BFD_RELOC_ARM_LDRS_PC_G0
:
29697 case BFD_RELOC_ARM_LDRS_PC_G1
:
29698 case BFD_RELOC_ARM_LDRS_PC_G2
:
29699 case BFD_RELOC_ARM_LDRS_SB_G0
:
29700 case BFD_RELOC_ARM_LDRS_SB_G1
:
29701 case BFD_RELOC_ARM_LDRS_SB_G2
:
29702 gas_assert (!fixP
->fx_done
);
29703 if (!seg
->use_rela_p
)
29706 bfd_vma addend_abs
= llabs (value
);
29708 /* Check that the absolute value of the addend can be
29709 encoded in 8 bits. */
29710 if (addend_abs
>= 0x100)
29711 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29712 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
29713 (unsigned long) addend_abs
);
29715 /* Extract the instruction. */
29716 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29718 /* If the addend is negative, clear bit 23 of the instruction.
29719 Otherwise set it. */
29721 insn
&= ~(1 << 23);
29725 /* Place the first four bits of the absolute value of the addend
29726 into the first 4 bits of the instruction, and the remaining
29727 four into bits 8 .. 11. */
29728 insn
&= 0xfffff0f0;
29729 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
29731 /* Update the instruction. */
29732 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29736 case BFD_RELOC_ARM_LDC_PC_G0
:
29737 case BFD_RELOC_ARM_LDC_PC_G1
:
29738 case BFD_RELOC_ARM_LDC_PC_G2
:
29739 case BFD_RELOC_ARM_LDC_SB_G0
:
29740 case BFD_RELOC_ARM_LDC_SB_G1
:
29741 case BFD_RELOC_ARM_LDC_SB_G2
:
29742 gas_assert (!fixP
->fx_done
);
29743 if (!seg
->use_rela_p
)
29746 bfd_vma addend_abs
= llabs (value
);
29748 /* Check that the absolute value of the addend is a multiple of
29749 four and, when divided by four, fits in 8 bits. */
29750 if (addend_abs
& 0x3)
29751 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29752 _("bad offset 0x%08lX (must be word-aligned)"),
29753 (unsigned long) addend_abs
);
29755 if ((addend_abs
>> 2) > 0xff)
29756 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29757 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
29758 (unsigned long) addend_abs
);
29760 /* Extract the instruction. */
29761 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29763 /* If the addend is negative, clear bit 23 of the instruction.
29764 Otherwise set it. */
29766 insn
&= ~(1 << 23);
29770 /* Place the addend (divided by four) into the first eight
29771 bits of the instruction. */
29772 insn
&= 0xfffffff0;
29773 insn
|= addend_abs
>> 2;
29775 /* Update the instruction. */
29776 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29780 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29782 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29783 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29784 && ARM_IS_FUNC (fixP
->fx_addsy
)
29785 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29787 /* Force a relocation for a branch 5 bits wide. */
29790 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
29791 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29794 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29796 addressT boff
= value
>> 1;
29798 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29799 newval
|= (boff
<< 7);
29800 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29804 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29806 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29807 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29808 && ARM_IS_FUNC (fixP
->fx_addsy
)
29809 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29813 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
29814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29815 _("branch out of range"));
29817 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29819 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29821 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
29822 addressT diff
= value
- boff
;
29826 newval
|= 1 << 1; /* T bit. */
29828 else if (diff
!= 2)
29830 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29831 _("out of range label-relative fixup value"));
29833 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29837 case BFD_RELOC_ARM_THUMB_BF17
:
29839 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29840 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29841 && ARM_IS_FUNC (fixP
->fx_addsy
)
29842 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29844 /* Force a relocation for a branch 17 bits wide. */
29848 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
29849 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29852 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29855 addressT immA
, immB
, immC
;
29857 immA
= (value
& 0x0001f000) >> 12;
29858 immB
= (value
& 0x00000ffc) >> 2;
29859 immC
= (value
& 0x00000002) >> 1;
29861 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29862 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29864 newval2
|= (immC
<< 11) | (immB
<< 1);
29865 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29866 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29870 case BFD_RELOC_ARM_THUMB_BF19
:
29872 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29873 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29874 && ARM_IS_FUNC (fixP
->fx_addsy
)
29875 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29877 /* Force a relocation for a branch 19 bits wide. */
29881 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
29882 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29885 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29888 addressT immA
, immB
, immC
;
29890 immA
= (value
& 0x0007f000) >> 12;
29891 immB
= (value
& 0x00000ffc) >> 2;
29892 immC
= (value
& 0x00000002) >> 1;
29894 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29895 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29897 newval2
|= (immC
<< 11) | (immB
<< 1);
29898 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29899 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29903 case BFD_RELOC_ARM_THUMB_BF13
:
29905 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29906 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29907 && ARM_IS_FUNC (fixP
->fx_addsy
)
29908 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29910 /* Force a relocation for a branch 13 bits wide. */
29914 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
29915 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29918 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29921 addressT immA
, immB
, immC
;
29923 immA
= (value
& 0x00001000) >> 12;
29924 immB
= (value
& 0x00000ffc) >> 2;
29925 immC
= (value
& 0x00000002) >> 1;
29927 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29928 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29930 newval2
|= (immC
<< 11) | (immB
<< 1);
29931 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29932 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29936 case BFD_RELOC_ARM_THUMB_LOOP12
:
29938 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29939 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29940 && ARM_IS_FUNC (fixP
->fx_addsy
)
29941 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29943 /* Force a relocation for a branch 12 bits wide. */
29947 bfd_vma insn
= get_thumb32_insn (buf
);
29948 /* le lr, <label>, le <label> or letp lr, <label> */
29949 if (((insn
& 0xffffffff) == 0xf00fc001)
29950 || ((insn
& 0xffffffff) == 0xf02fc001)
29951 || ((insn
& 0xffffffff) == 0xf01fc001))
29954 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
29955 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29957 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29959 addressT imml
, immh
;
29961 immh
= (value
& 0x00000ffc) >> 2;
29962 imml
= (value
& 0x00000002) >> 1;
29964 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29965 newval
|= (imml
<< 11) | (immh
<< 1);
29966 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29970 case BFD_RELOC_ARM_V4BX
:
29971 /* This will need to go in the object file. */
29975 case BFD_RELOC_UNUSED
:
29977 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29978 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29982 /* Translate internal representation of relocation info to BFD target
29986 tc_gen_reloc (asection
*section
, fixS
*fixp
)
29989 bfd_reloc_code_real_type code
;
29991 reloc
= XNEW (arelent
);
29993 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
29994 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
29995 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
29997 if (fixp
->fx_pcrel
)
29999 if (section
->use_rela_p
)
30000 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
30002 fixp
->fx_offset
= reloc
->address
;
30004 reloc
->addend
= fixp
->fx_offset
;
30006 switch (fixp
->fx_r_type
)
30009 if (fixp
->fx_pcrel
)
30011 code
= BFD_RELOC_8_PCREL
;
30014 /* Fall through. */
30017 if (fixp
->fx_pcrel
)
30019 code
= BFD_RELOC_16_PCREL
;
30022 /* Fall through. */
30025 if (fixp
->fx_pcrel
)
30027 code
= BFD_RELOC_32_PCREL
;
30030 /* Fall through. */
30032 case BFD_RELOC_ARM_MOVW
:
30033 if (fixp
->fx_pcrel
)
30035 code
= BFD_RELOC_ARM_MOVW_PCREL
;
30038 /* Fall through. */
30040 case BFD_RELOC_ARM_MOVT
:
30041 if (fixp
->fx_pcrel
)
30043 code
= BFD_RELOC_ARM_MOVT_PCREL
;
30046 /* Fall through. */
30048 case BFD_RELOC_ARM_THUMB_MOVW
:
30049 if (fixp
->fx_pcrel
)
30051 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
30054 /* Fall through. */
30056 case BFD_RELOC_ARM_THUMB_MOVT
:
30057 if (fixp
->fx_pcrel
)
30059 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
30062 /* Fall through. */
30064 case BFD_RELOC_NONE
:
30065 case BFD_RELOC_ARM_PCREL_BRANCH
:
30066 case BFD_RELOC_ARM_PCREL_BLX
:
30067 case BFD_RELOC_RVA
:
30068 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
30069 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
30070 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
30071 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30072 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30073 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30074 case BFD_RELOC_VTABLE_ENTRY
:
30075 case BFD_RELOC_VTABLE_INHERIT
:
30077 case BFD_RELOC_32_SECREL
:
30079 code
= fixp
->fx_r_type
;
30082 case BFD_RELOC_THUMB_PCREL_BLX
:
30084 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
30085 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
30088 code
= BFD_RELOC_THUMB_PCREL_BLX
;
30091 case BFD_RELOC_ARM_LITERAL
:
30092 case BFD_RELOC_ARM_HWLITERAL
:
30093 /* If this is called then the a literal has
30094 been referenced across a section boundary. */
30095 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30096 _("literal referenced across section boundary"));
30100 case BFD_RELOC_ARM_TLS_CALL
:
30101 case BFD_RELOC_ARM_THM_TLS_CALL
:
30102 case BFD_RELOC_ARM_TLS_DESCSEQ
:
30103 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
30104 case BFD_RELOC_ARM_GOT32
:
30105 case BFD_RELOC_ARM_GOTOFF
:
30106 case BFD_RELOC_ARM_GOT_PREL
:
30107 case BFD_RELOC_ARM_PLT32
:
30108 case BFD_RELOC_ARM_TARGET1
:
30109 case BFD_RELOC_ARM_ROSEGREL32
:
30110 case BFD_RELOC_ARM_SBREL32
:
30111 case BFD_RELOC_ARM_PREL31
:
30112 case BFD_RELOC_ARM_TARGET2
:
30113 case BFD_RELOC_ARM_TLS_LDO32
:
30114 case BFD_RELOC_ARM_PCREL_CALL
:
30115 case BFD_RELOC_ARM_PCREL_JUMP
:
30116 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
30117 case BFD_RELOC_ARM_ALU_PC_G0
:
30118 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
30119 case BFD_RELOC_ARM_ALU_PC_G1
:
30120 case BFD_RELOC_ARM_ALU_PC_G2
:
30121 case BFD_RELOC_ARM_LDR_PC_G0
:
30122 case BFD_RELOC_ARM_LDR_PC_G1
:
30123 case BFD_RELOC_ARM_LDR_PC_G2
:
30124 case BFD_RELOC_ARM_LDRS_PC_G0
:
30125 case BFD_RELOC_ARM_LDRS_PC_G1
:
30126 case BFD_RELOC_ARM_LDRS_PC_G2
:
30127 case BFD_RELOC_ARM_LDC_PC_G0
:
30128 case BFD_RELOC_ARM_LDC_PC_G1
:
30129 case BFD_RELOC_ARM_LDC_PC_G2
:
30130 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
30131 case BFD_RELOC_ARM_ALU_SB_G0
:
30132 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
30133 case BFD_RELOC_ARM_ALU_SB_G1
:
30134 case BFD_RELOC_ARM_ALU_SB_G2
:
30135 case BFD_RELOC_ARM_LDR_SB_G0
:
30136 case BFD_RELOC_ARM_LDR_SB_G1
:
30137 case BFD_RELOC_ARM_LDR_SB_G2
:
30138 case BFD_RELOC_ARM_LDRS_SB_G0
:
30139 case BFD_RELOC_ARM_LDRS_SB_G1
:
30140 case BFD_RELOC_ARM_LDRS_SB_G2
:
30141 case BFD_RELOC_ARM_LDC_SB_G0
:
30142 case BFD_RELOC_ARM_LDC_SB_G1
:
30143 case BFD_RELOC_ARM_LDC_SB_G2
:
30144 case BFD_RELOC_ARM_V4BX
:
30145 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
30146 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
30147 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
30148 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
30149 case BFD_RELOC_ARM_GOTFUNCDESC
:
30150 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
30151 case BFD_RELOC_ARM_FUNCDESC
:
30152 case BFD_RELOC_ARM_THUMB_BF17
:
30153 case BFD_RELOC_ARM_THUMB_BF19
:
30154 case BFD_RELOC_ARM_THUMB_BF13
:
30155 code
= fixp
->fx_r_type
;
30158 case BFD_RELOC_ARM_TLS_GOTDESC
:
30159 case BFD_RELOC_ARM_TLS_GD32
:
30160 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
30161 case BFD_RELOC_ARM_TLS_LE32
:
30162 case BFD_RELOC_ARM_TLS_IE32
:
30163 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
30164 case BFD_RELOC_ARM_TLS_LDM32
:
30165 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
30166 /* BFD will include the symbol's address in the addend.
30167 But we don't want that, so subtract it out again here. */
30168 if (!S_IS_COMMON (fixp
->fx_addsy
))
30169 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
30170 code
= fixp
->fx_r_type
;
30174 case BFD_RELOC_ARM_IMMEDIATE
:
30175 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30176 _("internal relocation (type: IMMEDIATE) not fixed up"));
30179 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
30180 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30181 _("ADRL used for a symbol not defined in the same file"));
30184 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
30185 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
30186 case BFD_RELOC_ARM_THUMB_LOOP12
:
30187 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30188 _("%s used for a symbol not defined in the same file"),
30189 bfd_get_reloc_code_name (fixp
->fx_r_type
));
30192 case BFD_RELOC_ARM_OFFSET_IMM
:
30193 if (section
->use_rela_p
)
30195 code
= fixp
->fx_r_type
;
30199 if (fixp
->fx_addsy
!= NULL
30200 && !S_IS_DEFINED (fixp
->fx_addsy
)
30201 && S_IS_LOCAL (fixp
->fx_addsy
))
30203 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30204 _("undefined local label `%s'"),
30205 S_GET_NAME (fixp
->fx_addsy
));
30209 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30210 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
30217 switch (fixp
->fx_r_type
)
30219 case BFD_RELOC_NONE
: type
= "NONE"; break;
30220 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
30221 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
30222 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
30223 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
30224 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
30225 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
30226 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
30227 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
30228 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
30229 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
30230 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
30231 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
30232 default: type
= _("<unknown>"); break;
30234 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30235 _("cannot represent %s relocation in this object file format"),
30242 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
30244 && fixp
->fx_addsy
== GOT_symbol
)
30246 code
= BFD_RELOC_ARM_GOTPC
;
30247 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
30251 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
30253 if (reloc
->howto
== NULL
)
30255 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30256 _("cannot represent %s relocation in this object file format"),
30257 bfd_get_reloc_code_name (code
));
30261 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
30262 vtable entry to be used in the relocation's section offset. */
30263 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30264 reloc
->address
= fixp
->fx_offset
;
30269 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
30272 cons_fix_new_arm (fragS
* frag
,
30276 bfd_reloc_code_real_type reloc
)
30281 FIXME: @@ Should look at CPU word size. */
30285 reloc
= BFD_RELOC_8
;
30288 reloc
= BFD_RELOC_16
;
30292 reloc
= BFD_RELOC_32
;
30295 reloc
= BFD_RELOC_64
;
30300 if (exp
->X_op
== O_secrel
)
30302 exp
->X_op
= O_symbol
;
30303 reloc
= BFD_RELOC_32_SECREL
;
30307 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
30310 #if defined (OBJ_COFF)
30312 arm_validate_fix (fixS
* fixP
)
30314 /* If the destination of the branch is a defined symbol which does not have
30315 the THUMB_FUNC attribute, then we must be calling a function which has
30316 the (interfacearm) attribute. We look for the Thumb entry point to that
30317 function and change the branch to refer to that function instead. */
30318 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
30319 && fixP
->fx_addsy
!= NULL
30320 && S_IS_DEFINED (fixP
->fx_addsy
)
30321 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
30323 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
30330 arm_force_relocation (struct fix
* fixp
)
30332 #if defined (OBJ_COFF) && defined (TE_PE)
30333 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
30337 /* In case we have a call or a branch to a function in ARM ISA mode from
30338 a thumb function or vice-versa force the relocation. These relocations
30339 are cleared off for some cores that might have blx and simple transformations
30343 switch (fixp
->fx_r_type
)
30345 case BFD_RELOC_ARM_PCREL_JUMP
:
30346 case BFD_RELOC_ARM_PCREL_CALL
:
30347 case BFD_RELOC_THUMB_PCREL_BLX
:
30348 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
30352 case BFD_RELOC_ARM_PCREL_BLX
:
30353 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30354 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30355 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30356 if (ARM_IS_FUNC (fixp
->fx_addsy
))
30365 /* Resolve these relocations even if the symbol is extern or weak.
30366 Technically this is probably wrong due to symbol preemption.
30367 In practice these relocations do not have enough range to be useful
30368 at dynamic link time, and some code (e.g. in the Linux kernel)
30369 expects these references to be resolved. */
30370 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
30371 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
30372 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
30373 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
30374 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
30375 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
30376 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
30377 || fixp
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH12
30378 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
30379 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
30380 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
30381 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
30382 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
30383 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
30384 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
30387 /* Always leave these relocations for the linker. */
30388 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30389 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30390 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30393 /* Always generate relocations against function symbols. */
30394 if (fixp
->fx_r_type
== BFD_RELOC_32
30396 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
30399 return generic_force_reloc (fixp
);
30402 #if defined (OBJ_ELF) || defined (OBJ_COFF)
30403 /* Relocations against function names must be left unadjusted,
30404 so that the linker can use this information to generate interworking
30405 stubs. The MIPS version of this function
30406 also prevents relocations that are mips-16 specific, but I do not
30407 know why it does this.
30410 There is one other problem that ought to be addressed here, but
30411 which currently is not: Taking the address of a label (rather
30412 than a function) and then later jumping to that address. Such
30413 addresses also ought to have their bottom bit set (assuming that
30414 they reside in Thumb code), but at the moment they will not. */
30417 arm_fix_adjustable (fixS
* fixP
)
30419 if (fixP
->fx_addsy
== NULL
)
30422 /* Preserve relocations against symbols with function type. */
30423 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
30426 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
30427 && fixP
->fx_subsy
== NULL
)
30430 /* We need the symbol name for the VTABLE entries. */
30431 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
30432 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30435 /* Don't allow symbols to be discarded on GOT related relocs. */
30436 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
30437 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
30438 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
30439 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
30440 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
30441 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
30442 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
30443 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
30444 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
30445 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
30446 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
30447 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
30448 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
30449 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
30450 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
30451 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
30452 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
30455 /* Similarly for group relocations. */
30456 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30457 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30458 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30461 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
30462 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
30463 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
30464 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
30465 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
30466 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
30467 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
30468 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
30469 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
30472 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
30473 offsets, so keep these symbols. */
30474 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
30475 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
30480 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
30484 elf32_arm_target_format (void)
30487 return (target_big_endian
30488 ? "elf32-bigarm-symbian"
30489 : "elf32-littlearm-symbian");
30490 #elif defined (TE_VXWORKS)
30491 return (target_big_endian
30492 ? "elf32-bigarm-vxworks"
30493 : "elf32-littlearm-vxworks");
30494 #elif defined (TE_NACL)
30495 return (target_big_endian
30496 ? "elf32-bigarm-nacl"
30497 : "elf32-littlearm-nacl");
30501 if (target_big_endian
)
30502 return "elf32-bigarm-fdpic";
30504 return "elf32-littlearm-fdpic";
30508 if (target_big_endian
)
30509 return "elf32-bigarm";
30511 return "elf32-littlearm";
30517 armelf_frob_symbol (symbolS
* symp
,
30520 elf_frob_symbol (symp
, puntp
);
30524 /* MD interface: Finalization. */
30529 literal_pool
* pool
;
30531 /* Ensure that all the predication blocks are properly closed. */
30532 check_pred_blocks_finished ();
30534 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
30536 /* Put it at the end of the relevant section. */
30537 subseg_set (pool
->section
, pool
->sub_section
);
30539 arm_elf_change_section ();
30546 /* Remove any excess mapping symbols generated for alignment frags in
30547 SEC. We may have created a mapping symbol before a zero byte
30548 alignment; remove it if there's a mapping symbol after the
30551 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
30552 void *dummy ATTRIBUTE_UNUSED
)
30554 segment_info_type
*seginfo
= seg_info (sec
);
30557 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
30560 for (fragp
= seginfo
->frchainP
->frch_root
;
30562 fragp
= fragp
->fr_next
)
30564 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
30565 fragS
*next
= fragp
->fr_next
;
30567 /* Variable-sized frags have been converted to fixed size by
30568 this point. But if this was variable-sized to start with,
30569 there will be a fixed-size frag after it. So don't handle
30571 if (sym
== NULL
|| next
== NULL
)
30574 if (S_GET_VALUE (sym
) < next
->fr_address
)
30575 /* Not at the end of this frag. */
30577 know (S_GET_VALUE (sym
) == next
->fr_address
);
30581 if (next
->tc_frag_data
.first_map
!= NULL
)
30583 /* Next frag starts with a mapping symbol. Discard this
30585 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30589 if (next
->fr_next
== NULL
)
30591 /* This mapping symbol is at the end of the section. Discard
30593 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
30594 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30598 /* As long as we have empty frags without any mapping symbols,
30600 /* If the next frag is non-empty and does not start with a
30601 mapping symbol, then this mapping symbol is required. */
30602 if (next
->fr_address
!= next
->fr_next
->fr_address
)
30605 next
= next
->fr_next
;
30607 while (next
!= NULL
);
30612 /* Adjust the symbol table. This marks Thumb symbols as distinct from
30616 arm_adjust_symtab (void)
30621 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30623 if (ARM_IS_THUMB (sym
))
30625 if (THUMB_IS_FUNC (sym
))
30627 /* Mark the symbol as a Thumb function. */
30628 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
30629 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
30630 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
30632 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
30633 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
30635 as_bad (_("%s: unexpected function type: %d"),
30636 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
30638 else switch (S_GET_STORAGE_CLASS (sym
))
30641 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
30644 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
30647 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
30655 if (ARM_IS_INTERWORK (sym
))
30656 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
30663 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30665 if (ARM_IS_THUMB (sym
))
30667 elf_symbol_type
* elf_sym
;
30669 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
30670 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
30672 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
30673 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
30675 /* If it's a .thumb_func, declare it as so,
30676 otherwise tag label as .code 16. */
30677 if (THUMB_IS_FUNC (sym
))
30678 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
30679 ST_BRANCH_TO_THUMB
);
30680 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30681 elf_sym
->internal_elf_sym
.st_info
=
30682 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
30687 /* Remove any overlapping mapping symbols generated by alignment frags. */
30688 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
30689 /* Now do generic ELF adjustments. */
30690 elf_adjust_symtab ();
30694 /* MD interface: Initialization. */
30697 set_constant_flonums (void)
30701 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
30702 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
30706 /* Auto-select Thumb mode if it's the only available instruction set for the
30707 given architecture. */
30710 autoselect_thumb_from_cpu_variant (void)
30712 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
30713 opcode_select (16);
30722 if ( (arm_ops_hsh
= str_htab_create ()) == NULL
30723 || (arm_cond_hsh
= str_htab_create ()) == NULL
30724 || (arm_vcond_hsh
= str_htab_create ()) == NULL
30725 || (arm_shift_hsh
= str_htab_create ()) == NULL
30726 || (arm_psr_hsh
= str_htab_create ()) == NULL
30727 || (arm_v7m_psr_hsh
= str_htab_create ()) == NULL
30728 || (arm_reg_hsh
= str_htab_create ()) == NULL
30729 || (arm_reloc_hsh
= str_htab_create ()) == NULL
30730 || (arm_barrier_opt_hsh
= str_htab_create ()) == NULL
)
30731 as_fatal (_("virtual memory exhausted"));
30733 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
30734 if (str_hash_find (arm_ops_hsh
, insns
[i
].template_name
) == NULL
)
30735 str_hash_insert (arm_ops_hsh
, insns
[i
].template_name
, insns
+ i
, 0);
30736 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
30737 str_hash_insert (arm_cond_hsh
, conds
[i
].template_name
, conds
+ i
, 0);
30738 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
30739 str_hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, vconds
+ i
, 0);
30740 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
30741 str_hash_insert (arm_shift_hsh
, shift_names
[i
].name
, shift_names
+ i
, 0);
30742 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
30743 str_hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, psrs
+ i
, 0);
30744 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
30745 str_hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
30747 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
30748 str_hash_insert (arm_reg_hsh
, reg_names
[i
].name
, reg_names
+ i
, 0);
30750 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
30752 str_hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
30753 barrier_opt_names
+ i
, 0);
30755 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
30757 struct reloc_entry
* entry
= reloc_names
+ i
;
30759 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
30760 /* This makes encode_branch() use the EABI versions of this relocation. */
30761 entry
->reloc
= BFD_RELOC_UNUSED
;
30763 str_hash_insert (arm_reloc_hsh
, entry
->name
, entry
, 0);
30767 set_constant_flonums ();
30769 /* Set the cpu variant based on the command-line options. We prefer
30770 -mcpu= over -march= if both are set (as for GCC); and we prefer
30771 -mfpu= over any other way of setting the floating point unit.
30772 Use of legacy options with new options are faulted. */
30775 if (mcpu_cpu_opt
|| march_cpu_opt
)
30776 as_bad (_("use of old and new-style options to set CPU type"));
30778 selected_arch
= *legacy_cpu
;
30780 else if (mcpu_cpu_opt
)
30782 selected_arch
= *mcpu_cpu_opt
;
30783 selected_ext
= *mcpu_ext_opt
;
30785 else if (march_cpu_opt
)
30787 selected_arch
= *march_cpu_opt
;
30788 selected_ext
= *march_ext_opt
;
30790 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30795 as_bad (_("use of old and new-style options to set FPU type"));
30797 selected_fpu
= *legacy_fpu
;
30800 selected_fpu
= *mfpu_opt
;
30803 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
30804 || defined (TE_NetBSD) || defined (TE_VXWORKS))
30805 /* Some environments specify a default FPU. If they don't, infer it
30806 from the processor. */
30808 selected_fpu
= *mcpu_fpu_opt
;
30809 else if (march_fpu_opt
)
30810 selected_fpu
= *march_fpu_opt
;
30812 selected_fpu
= fpu_default
;
30816 if (ARM_FEATURE_ZERO (selected_fpu
))
30818 if (!no_cpu_selected ())
30819 selected_fpu
= fpu_default
;
30821 selected_fpu
= fpu_arch_fpa
;
30825 if (ARM_FEATURE_ZERO (selected_arch
))
30827 selected_arch
= cpu_default
;
30828 selected_cpu
= selected_arch
;
30830 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30832 /* Autodection of feature mode: allow all features in cpu_variant but leave
30833 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
30834 after all instruction have been processed and we can decide what CPU
30835 should be selected. */
30836 if (ARM_FEATURE_ZERO (selected_arch
))
30837 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30839 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30842 autoselect_thumb_from_cpu_variant ();
30844 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
30846 #if defined OBJ_COFF || defined OBJ_ELF
30848 unsigned int flags
= 0;
30850 #if defined OBJ_ELF
30851 flags
= meabi_flags
;
30853 switch (meabi_flags
)
30855 case EF_ARM_EABI_UNKNOWN
:
30857 /* Set the flags in the private structure. */
30858 if (uses_apcs_26
) flags
|= F_APCS26
;
30859 if (support_interwork
) flags
|= F_INTERWORK
;
30860 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
30861 if (pic_code
) flags
|= F_PIC
;
30862 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
30863 flags
|= F_SOFT_FLOAT
;
30865 switch (mfloat_abi_opt
)
30867 case ARM_FLOAT_ABI_SOFT
:
30868 case ARM_FLOAT_ABI_SOFTFP
:
30869 flags
|= F_SOFT_FLOAT
;
30872 case ARM_FLOAT_ABI_HARD
:
30873 if (flags
& F_SOFT_FLOAT
)
30874 as_bad (_("hard-float conflicts with specified fpu"));
30878 /* Using pure-endian doubles (even if soft-float). */
30879 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
30880 flags
|= F_VFP_FLOAT
;
30882 #if defined OBJ_ELF
30883 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
30884 flags
|= EF_ARM_MAVERICK_FLOAT
;
30887 case EF_ARM_EABI_VER4
:
30888 case EF_ARM_EABI_VER5
:
30889 /* No additional flags to set. */
30896 bfd_set_private_flags (stdoutput
, flags
);
30898 /* We have run out flags in the COFF header to encode the
30899 status of ATPCS support, so instead we create a dummy,
30900 empty, debug section called .arm.atpcs. */
30905 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
30909 bfd_set_section_flags (sec
, SEC_READONLY
| SEC_DEBUGGING
);
30910 bfd_set_section_size (sec
, 0);
30911 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
30917 /* Record the CPU type as well. */
30918 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
30919 mach
= bfd_mach_arm_iWMMXt2
;
30920 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
30921 mach
= bfd_mach_arm_iWMMXt
;
30922 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
30923 mach
= bfd_mach_arm_XScale
;
30924 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
30925 mach
= bfd_mach_arm_ep9312
;
30926 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
30927 mach
= bfd_mach_arm_5TE
;
30928 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
30930 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30931 mach
= bfd_mach_arm_5T
;
30933 mach
= bfd_mach_arm_5
;
30935 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30937 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30938 mach
= bfd_mach_arm_4T
;
30940 mach
= bfd_mach_arm_4
;
30942 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30943 mach
= bfd_mach_arm_3M
;
30944 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30945 mach
= bfd_mach_arm_3
;
30946 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30947 mach
= bfd_mach_arm_2a
;
30948 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30949 mach
= bfd_mach_arm_2
;
30951 mach
= bfd_mach_arm_unknown
;
30953 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30956 /* Command line processing. */
30959 Invocation line includes a switch not recognized by the base assembler.
30960 See if it's a processor-specific option.
30962 This routine is somewhat complicated by the need for backwards
30963 compatibility (since older releases of gcc can't be changed).
30964 The new options try to make the interface as compatible as
30967 New options (supported) are:
30969 -mcpu=<cpu name> Assemble for selected processor
30970 -march=<architecture name> Assemble for selected architecture
30971 -mfpu=<fpu architecture> Assemble for selected FPU.
30972 -EB/-mbig-endian Big-endian
30973 -EL/-mlittle-endian Little-endian
30974 -k Generate PIC code
30975 -mthumb Start in Thumb mode
30976 -mthumb-interwork Code supports ARM/Thumb interworking
30978 -m[no-]warn-deprecated Warn about deprecated features
30979 -m[no-]warn-syms Warn when symbols match instructions
30981 For now we will also provide support for:
30983 -mapcs-32 32-bit Program counter
30984 -mapcs-26 26-bit Program counter
30985 -macps-float Floats passed in FP registers
30986 -mapcs-reentrant Reentrant code
30988 (sometime these will probably be replaced with -mapcs=<list of options>
30989 and -matpcs=<list of options>)
30991 The remaining options are only supported for back-wards compatibility.
30992 Cpu variants, the arm part is optional:
30993 -m[arm]1 Currently not supported.
30994 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30995 -m[arm]3 Arm 3 processor
30996 -m[arm]6[xx], Arm 6 processors
30997 -m[arm]7[xx][t][[d]m] Arm 7 processors
30998 -m[arm]8[10] Arm 8 processors
30999 -m[arm]9[20][tdmi] Arm 9 processors
31000 -mstrongarm[110[0]] StrongARM processors
31001 -mxscale XScale processors
31002 -m[arm]v[2345[t[e]]] Arm architectures
31003 -mall All (except the ARM1)
31005 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
31006 -mfpe-old (No float load/store multiples)
31007 -mvfpxd VFP Single precision
31009 -mno-fpu Disable all floating point instructions
31011 The following CPU names are recognized:
31012 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
31013 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
31014 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
31015 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
31016 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
31017 arm10t arm10e, arm1020t, arm1020e, arm10200e,
31018 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
31022 const char * md_shortopts
= "m:k";
31024 #ifdef ARM_BI_ENDIAN
31025 #define OPTION_EB (OPTION_MD_BASE + 0)
31026 #define OPTION_EL (OPTION_MD_BASE + 1)
31028 #if TARGET_BYTES_BIG_ENDIAN
31029 #define OPTION_EB (OPTION_MD_BASE + 0)
31031 #define OPTION_EL (OPTION_MD_BASE + 1)
31034 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
31035 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
31037 struct option md_longopts
[] =
31040 {"EB", no_argument
, NULL
, OPTION_EB
},
31043 {"EL", no_argument
, NULL
, OPTION_EL
},
31045 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
31047 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
31049 {NULL
, no_argument
, NULL
, 0}
31052 size_t md_longopts_size
= sizeof (md_longopts
);
31054 struct arm_option_table
31056 const char * option
; /* Option name to match. */
31057 const char * help
; /* Help information. */
31058 int * var
; /* Variable to change. */
31059 int value
; /* What to change it to. */
31060 const char * deprecated
; /* If non-null, print this message. */
31063 struct arm_option_table arm_opts
[] =
31065 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
31066 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
31067 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
31068 &support_interwork
, 1, NULL
},
31069 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
31070 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
31071 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
31073 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
31074 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
31075 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
31076 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
31079 /* These are recognized by the assembler, but have no affect on code. */
31080 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
31081 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
31083 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
31084 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
31085 &warn_on_deprecated
, 0, NULL
},
31087 {"mwarn-restrict-it", N_("warn about performance deprecated IT instructions"
31088 " in ARMv8-A and ARMv8-R"), &warn_on_restrict_it
, 1, NULL
},
31089 {"mno-warn-restrict-it", NULL
, &warn_on_restrict_it
, 0, NULL
},
31091 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
31092 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
31093 {NULL
, NULL
, NULL
, 0, NULL
}
31096 struct arm_legacy_option_table
31098 const char * option
; /* Option name to match. */
31099 const arm_feature_set
** var
; /* Variable to change. */
31100 const arm_feature_set value
; /* What to change it to. */
31101 const char * deprecated
; /* If non-null, print this message. */
31104 const struct arm_legacy_option_table arm_legacy_opts
[] =
31106 /* DON'T add any new processors to this list -- we want the whole list
31107 to go away... Add them to the processors table instead. */
31108 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31109 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31110 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31111 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31112 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31113 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31114 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31115 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31116 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31117 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31118 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31119 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31120 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31121 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31122 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31123 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31124 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31125 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31126 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31127 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31128 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31129 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31130 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31131 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31132 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31133 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31134 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31135 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31136 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31137 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31138 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31139 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31140 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31141 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31142 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31143 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31144 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31145 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31146 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31147 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31148 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31149 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31150 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31151 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31152 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31153 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31154 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31155 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31156 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31157 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31158 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31159 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31160 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31161 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31162 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31163 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31164 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31165 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31166 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31167 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31168 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31169 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31170 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31171 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31172 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31173 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31174 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31175 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31176 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
31177 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
31178 N_("use -mcpu=strongarm110")},
31179 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
31180 N_("use -mcpu=strongarm1100")},
31181 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
31182 N_("use -mcpu=strongarm1110")},
31183 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
31184 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
31185 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
31187 /* Architecture variants -- don't add any more to this list either. */
31188 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31189 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31190 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31191 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31192 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31193 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31194 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31195 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31196 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31197 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31198 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31199 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31200 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31201 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31202 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31203 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31204 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31205 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31207 /* Floating point variants -- don't add any more to this list either. */
31208 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
31209 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
31210 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
31211 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
31212 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
31214 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
31217 struct arm_cpu_option_table
31221 const arm_feature_set value
;
31222 const arm_feature_set ext
;
31223 /* For some CPUs we assume an FPU unless the user explicitly sets
31225 const arm_feature_set default_fpu
;
31226 /* The canonical name of the CPU, or NULL to use NAME converted to upper
31228 const char * canonical_name
;
31231 /* This list should, at a minimum, contain all the cpu names
31232 recognized by GCC. */
31233 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
31235 static const struct arm_cpu_option_table arm_cpus
[] =
31237 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
31240 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
31243 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
31246 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
31249 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
31252 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
31255 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
31258 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
31261 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
31264 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
31267 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
31270 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
31273 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
31276 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
31279 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
31282 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
31285 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
31288 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
31291 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
31294 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
31297 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
31300 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
31303 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
31306 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
31309 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
31312 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
31315 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
31318 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
31321 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
31324 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
31327 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
31330 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
31333 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
31336 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
31339 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
31342 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
31345 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
31348 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
31351 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
31354 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
31357 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
31360 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
31363 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
31366 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
31369 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
31372 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
31376 /* For V5 or later processors we default to using VFP; but the user
31377 should really set the FPU type explicitly. */
31378 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
31381 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
31384 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31387 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31390 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
31393 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
31396 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
31399 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
31402 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
31405 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
31408 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
31411 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
31414 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
31417 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
31420 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
31423 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
31426 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
31429 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
31432 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
31435 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
31438 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
31441 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
31444 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
31447 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
31450 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
31453 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
31456 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
31459 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
31462 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
31465 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
31468 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
31471 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
31474 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
31477 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
31480 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
31483 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
31486 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
31487 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31489 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
31491 FPU_ARCH_NEON_VFP_V4
),
31492 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
31493 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31494 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31495 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
31496 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31497 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31498 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
31500 FPU_ARCH_NEON_VFP_V4
),
31501 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
31503 FPU_ARCH_NEON_VFP_V4
),
31504 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
31506 FPU_ARCH_NEON_VFP_V4
),
31507 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
31508 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31509 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31510 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
31511 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31512 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31513 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
31514 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31515 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31516 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
31517 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31518 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31519 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
31520 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31521 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31522 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
31523 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31524 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31525 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
31526 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31527 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31528 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
31529 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31530 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31531 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
31532 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31533 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31534 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A
,
31535 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31536 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31537 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A
,
31538 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31539 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31540 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
31541 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31542 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31543 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
31546 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
31548 FPU_ARCH_VFP_V3D16
),
31549 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
31550 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31552 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
31553 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31554 FPU_ARCH_VFP_V3D16
),
31555 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
31556 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31557 FPU_ARCH_VFP_V3D16
),
31558 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
31559 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31560 FPU_ARCH_NEON_VFP_ARMV8
),
31561 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN
,
31562 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31564 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
31565 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31567 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
31570 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
31573 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
31576 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
31579 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
31582 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
31585 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
31588 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
31589 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31590 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31591 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
31592 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31593 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31594 /* ??? XSCALE is really an architecture. */
31595 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
31599 /* ??? iwmmxt is not a processor. */
31600 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
31603 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
31606 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
31611 ARM_CPU_OPT ("ep9312", "ARM920T",
31612 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
31613 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
31615 /* Marvell processors. */
31616 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
31617 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31618 FPU_ARCH_VFP_V3D16
),
31619 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
31620 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31621 FPU_ARCH_NEON_VFP_V4
),
31623 /* APM X-Gene family. */
31624 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
31626 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31627 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
31628 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31629 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31631 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31635 struct arm_ext_table
31639 const arm_feature_set merge
;
31640 const arm_feature_set clear
;
31643 struct arm_arch_option_table
31647 const arm_feature_set value
;
31648 const arm_feature_set default_fpu
;
31649 const struct arm_ext_table
* ext_table
;
31652 /* Used to add support for +E and +noE extension. */
31653 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
31654 /* Used to add support for a +E extension. */
31655 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
31656 /* Used to add support for a +noE extension. */
31657 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
31659 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
31660 ~0 & ~FPU_ENDIAN_PURE)
31662 static const struct arm_ext_table armv5te_ext_table
[] =
31664 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
31665 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31668 static const struct arm_ext_table armv7_ext_table
[] =
31670 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31671 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31674 static const struct arm_ext_table armv7ve_ext_table
[] =
31676 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
31677 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
31678 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31679 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31680 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31681 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
31682 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31684 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
31685 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31687 /* Aliases for +simd. */
31688 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31690 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31691 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31692 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31694 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31697 static const struct arm_ext_table armv7a_ext_table
[] =
31699 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31700 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31701 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31702 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31703 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31704 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
31705 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31707 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
31708 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31710 /* Aliases for +simd. */
31711 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31712 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31714 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31715 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31717 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
31718 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
31719 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31722 static const struct arm_ext_table armv7r_ext_table
[] =
31724 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
31725 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
31726 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31727 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31728 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
31729 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31730 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31731 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
31732 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31735 static const struct arm_ext_table armv7em_ext_table
[] =
31737 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
31738 /* Alias for +fp, used to be known as fpv4-sp-d16. */
31739 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
31740 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
31741 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31742 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
31743 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31746 static const struct arm_ext_table armv8a_ext_table
[] =
31748 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31749 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31750 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31751 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31753 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31754 should use the +simd option to turn on FP. */
31755 ARM_REMOVE ("fp", ALL_FP
),
31756 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31757 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31758 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31762 static const struct arm_ext_table armv81a_ext_table
[] =
31764 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31765 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31766 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31768 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31769 should use the +simd option to turn on FP. */
31770 ARM_REMOVE ("fp", ALL_FP
),
31771 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31772 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31773 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31776 static const struct arm_ext_table armv82a_ext_table
[] =
31778 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31779 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
31780 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
31781 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31782 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31783 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31784 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31785 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31787 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31788 should use the +simd option to turn on FP. */
31789 ARM_REMOVE ("fp", ALL_FP
),
31790 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31791 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31792 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31795 static const struct arm_ext_table armv84a_ext_table
[] =
31797 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31798 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31799 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31800 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31801 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31802 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31804 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31805 should use the +simd option to turn on FP. */
31806 ARM_REMOVE ("fp", ALL_FP
),
31807 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31808 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31809 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31812 static const struct arm_ext_table armv85a_ext_table
[] =
31814 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31815 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31816 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31817 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31818 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31819 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31821 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31822 should use the +simd option to turn on FP. */
31823 ARM_REMOVE ("fp", ALL_FP
),
31824 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31827 static const struct arm_ext_table armv86a_ext_table
[] =
31829 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31830 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31833 #define CDE_EXTENSIONS \
31834 ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
31835 ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
31836 ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
31837 ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
31838 ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
31839 ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
31840 ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
31841 ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
31843 static const struct arm_ext_table armv8m_main_ext_table
[] =
31845 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31846 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31847 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
31848 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31850 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31854 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
31856 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31857 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31859 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31860 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
31863 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31864 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31865 ARM_EXT ("mve", ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
, ARM_EXT2_MVE
, 0),
31866 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
)),
31868 ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
,
31869 ARM_EXT2_FP16_INST
| ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
,
31870 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31872 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31875 #undef CDE_EXTENSIONS
31877 static const struct arm_ext_table armv8r_ext_table
[] =
31879 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31880 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31881 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31882 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31883 ARM_REMOVE ("fp", ALL_FP
),
31884 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
31885 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31888 /* This list should, at a minimum, contain all the architecture names
31889 recognized by GCC. */
31890 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
31891 #define ARM_ARCH_OPT2(N, V, DF, ext) \
31892 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
31894 static const struct arm_arch_option_table arm_archs
[] =
31896 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
31897 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
31898 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
31899 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31900 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31901 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
31902 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
31903 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
31904 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
31905 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
31906 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
31907 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
31908 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
31909 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
31910 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
31911 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
31912 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
31913 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31914 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31915 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
31916 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
31917 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31918 kept to preserve existing behaviour. */
31919 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31920 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31921 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
31922 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
31923 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
31924 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31925 kept to preserve existing behaviour. */
31926 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31927 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31928 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
31929 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
31930 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
31931 /* The official spelling of the ARMv7 profile variants is the dashed form.
31932 Accept the non-dashed form for compatibility with old toolchains. */
31933 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31934 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
31935 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31936 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31937 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31938 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31939 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31940 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
31941 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
31942 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
31944 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
31946 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
31947 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
31948 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
31949 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
31950 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
31951 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
31952 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
31953 ARM_ARCH_OPT2 ("armv8.6-a", ARM_ARCH_V8_6A
, FPU_ARCH_VFP
, armv86a
),
31954 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
31955 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
31956 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
31957 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31959 #undef ARM_ARCH_OPT
31961 /* ISA extensions in the co-processor and main instruction set space. */
31963 struct arm_option_extension_value_table
31967 const arm_feature_set merge_value
;
31968 const arm_feature_set clear_value
;
31969 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31970 indicates that an extension is available for all architectures while
31971 ARM_ANY marks an empty entry. */
31972 const arm_feature_set allowed_archs
[2];
31975 /* The following table must be in alphabetical order with a NULL last entry. */
31977 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31978 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
31980 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
31981 use the context sensitive approach using arm_ext_table's. */
31982 static const struct arm_option_extension_value_table arm_extensions
[] =
31984 ARM_EXT_OPT ("crc", ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
31985 ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
31986 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31987 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31988 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
31989 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31990 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
31991 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
31993 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31994 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31995 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
31996 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
31997 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31998 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31999 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
32001 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32002 | ARM_EXT2_FP16_FML
),
32003 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32004 | ARM_EXT2_FP16_FML
),
32006 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
32007 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
32008 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32009 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32010 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
32011 Thumb divide instruction. Due to this having the same name as the
32012 previous entry, this will be ignored when doing command-line parsing and
32013 only considered by build attribute selection code. */
32014 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32015 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32016 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
32017 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
32018 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
32019 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
32020 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
32021 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
32022 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
32023 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32024 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32025 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32026 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32027 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32028 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32029 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
32030 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
32031 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
32032 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32033 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32034 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32036 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
32037 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
32038 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32039 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
32040 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
32041 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32042 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32043 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32045 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32046 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32047 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
32048 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32049 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
32050 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
32051 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32052 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
32054 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
32055 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32056 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
32057 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
32058 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
32062 /* ISA floating-point and Advanced SIMD extensions. */
32063 struct arm_option_fpu_value_table
32066 const arm_feature_set value
;
32069 /* This list should, at a minimum, contain all the fpu names
32070 recognized by GCC. */
32071 static const struct arm_option_fpu_value_table arm_fpus
[] =
32073 {"softfpa", FPU_NONE
},
32074 {"fpe", FPU_ARCH_FPE
},
32075 {"fpe2", FPU_ARCH_FPE
},
32076 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
32077 {"fpa", FPU_ARCH_FPA
},
32078 {"fpa10", FPU_ARCH_FPA
},
32079 {"fpa11", FPU_ARCH_FPA
},
32080 {"arm7500fe", FPU_ARCH_FPA
},
32081 {"softvfp", FPU_ARCH_VFP
},
32082 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
32083 {"vfp", FPU_ARCH_VFP_V2
},
32084 {"vfp9", FPU_ARCH_VFP_V2
},
32085 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
32086 {"vfp10", FPU_ARCH_VFP_V2
},
32087 {"vfp10-r0", FPU_ARCH_VFP_V1
},
32088 {"vfpxd", FPU_ARCH_VFP_V1xD
},
32089 {"vfpv2", FPU_ARCH_VFP_V2
},
32090 {"vfpv3", FPU_ARCH_VFP_V3
},
32091 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
32092 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
32093 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
32094 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
32095 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
32096 {"arm1020t", FPU_ARCH_VFP_V1
},
32097 {"arm1020e", FPU_ARCH_VFP_V2
},
32098 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
32099 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
32100 {"maverick", FPU_ARCH_MAVERICK
},
32101 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32102 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32103 {"neon-fp16", FPU_ARCH_NEON_FP16
},
32104 {"vfpv4", FPU_ARCH_VFP_V4
},
32105 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
32106 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
32107 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
32108 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
32109 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
32110 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
32111 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
32112 {"crypto-neon-fp-armv8",
32113 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
32114 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
32115 {"crypto-neon-fp-armv8.1",
32116 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
32117 {NULL
, ARM_ARCH_NONE
}
32120 struct arm_option_value_table
32126 static const struct arm_option_value_table arm_float_abis
[] =
32128 {"hard", ARM_FLOAT_ABI_HARD
},
32129 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
32130 {"soft", ARM_FLOAT_ABI_SOFT
},
32135 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
32136 static const struct arm_option_value_table arm_eabis
[] =
32138 {"gnu", EF_ARM_EABI_UNKNOWN
},
32139 {"4", EF_ARM_EABI_VER4
},
32140 {"5", EF_ARM_EABI_VER5
},
32145 struct arm_long_option_table
32147 const char * option
; /* Substring to match. */
32148 const char * help
; /* Help information. */
32149 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
32150 const char * deprecated
; /* If non-null, print this message. */
32154 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
32155 arm_feature_set
*ext_set
,
32156 const struct arm_ext_table
*ext_table
)
32158 /* We insist on extensions being specified in alphabetical order, and with
32159 extensions being added before being removed. We achieve this by having
32160 the global ARM_EXTENSIONS table in alphabetical order, and using the
32161 ADDING_VALUE variable to indicate whether we are adding an extension (1)
32162 or removing it (0) and only allowing it to change in the order
32164 const struct arm_option_extension_value_table
* opt
= NULL
;
32165 const arm_feature_set arm_any
= ARM_ANY
;
32166 int adding_value
= -1;
32168 while (str
!= NULL
&& *str
!= 0)
32175 as_bad (_("invalid architectural extension"));
32180 ext
= strchr (str
, '+');
32185 len
= strlen (str
);
32187 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
32189 if (adding_value
!= 0)
32192 opt
= arm_extensions
;
32200 if (adding_value
== -1)
32203 opt
= arm_extensions
;
32205 else if (adding_value
!= 1)
32207 as_bad (_("must specify extensions to add before specifying "
32208 "those to remove"));
32215 as_bad (_("missing architectural extension"));
32219 gas_assert (adding_value
!= -1);
32220 gas_assert (opt
!= NULL
);
32222 if (ext_table
!= NULL
)
32224 const struct arm_ext_table
* ext_opt
= ext_table
;
32225 bfd_boolean found
= FALSE
;
32226 for (; ext_opt
->name
!= NULL
; ext_opt
++)
32227 if (ext_opt
->name_len
== len
32228 && strncmp (ext_opt
->name
, str
, len
) == 0)
32232 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
32233 /* TODO: Option not supported. When we remove the
32234 legacy table this case should error out. */
32237 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
32241 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
32242 /* TODO: Option not supported. When we remove the
32243 legacy table this case should error out. */
32245 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
32257 /* Scan over the options table trying to find an exact match. */
32258 for (; opt
->name
!= NULL
; opt
++)
32259 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32261 int i
, nb_allowed_archs
=
32262 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32263 /* Check we can apply the extension to this architecture. */
32264 for (i
= 0; i
< nb_allowed_archs
; i
++)
32267 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
32269 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
32272 if (i
== nb_allowed_archs
)
32274 as_bad (_("extension does not apply to the base architecture"));
32278 /* Add or remove the extension. */
32280 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
32282 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
32284 /* Allowing Thumb division instructions for ARMv7 in autodetection
32285 rely on this break so that duplicate extensions (extensions
32286 with the same name as a previous extension in the list) are not
32287 considered for command-line parsing. */
32291 if (opt
->name
== NULL
)
32293 /* Did we fail to find an extension because it wasn't specified in
32294 alphabetical order, or because it does not exist? */
32296 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32297 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32300 if (opt
->name
== NULL
)
32301 as_bad (_("unknown architectural extension `%s'"), str
);
32303 as_bad (_("architectural extensions must be specified in "
32304 "alphabetical order"));
32310 /* We should skip the extension we've just matched the next time
32322 arm_parse_fp16_opt (const char *str
)
32324 if (strcasecmp (str
, "ieee") == 0)
32325 fp16_format
= ARM_FP16_FORMAT_IEEE
;
32326 else if (strcasecmp (str
, "alternative") == 0)
32327 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
32330 as_bad (_("unrecognised float16 format \"%s\""), str
);
32338 arm_parse_cpu (const char *str
)
32340 const struct arm_cpu_option_table
*opt
;
32341 const char *ext
= strchr (str
, '+');
32347 len
= strlen (str
);
32351 as_bad (_("missing cpu name `%s'"), str
);
32355 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
32356 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32358 mcpu_cpu_opt
= &opt
->value
;
32359 if (mcpu_ext_opt
== NULL
)
32360 mcpu_ext_opt
= XNEW (arm_feature_set
);
32361 *mcpu_ext_opt
= opt
->ext
;
32362 mcpu_fpu_opt
= &opt
->default_fpu
;
32363 if (opt
->canonical_name
)
32365 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
32366 strcpy (selected_cpu_name
, opt
->canonical_name
);
32372 if (len
>= sizeof selected_cpu_name
)
32373 len
= (sizeof selected_cpu_name
) - 1;
32375 for (i
= 0; i
< len
; i
++)
32376 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32377 selected_cpu_name
[i
] = 0;
32381 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
32386 as_bad (_("unknown cpu `%s'"), str
);
32391 arm_parse_arch (const char *str
)
32393 const struct arm_arch_option_table
*opt
;
32394 const char *ext
= strchr (str
, '+');
32400 len
= strlen (str
);
32404 as_bad (_("missing architecture name `%s'"), str
);
32408 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
32409 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32411 march_cpu_opt
= &opt
->value
;
32412 if (march_ext_opt
== NULL
)
32413 march_ext_opt
= XNEW (arm_feature_set
);
32414 *march_ext_opt
= arm_arch_none
;
32415 march_fpu_opt
= &opt
->default_fpu
;
32416 selected_ctx_ext_table
= opt
->ext_table
;
32417 strcpy (selected_cpu_name
, opt
->name
);
32420 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
32426 as_bad (_("unknown architecture `%s'\n"), str
);
32431 arm_parse_fpu (const char * str
)
32433 const struct arm_option_fpu_value_table
* opt
;
32435 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32436 if (streq (opt
->name
, str
))
32438 mfpu_opt
= &opt
->value
;
32442 as_bad (_("unknown floating point format `%s'\n"), str
);
32447 arm_parse_float_abi (const char * str
)
32449 const struct arm_option_value_table
* opt
;
32451 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
32452 if (streq (opt
->name
, str
))
32454 mfloat_abi_opt
= opt
->value
;
32458 as_bad (_("unknown floating point abi `%s'\n"), str
);
32464 arm_parse_eabi (const char * str
)
32466 const struct arm_option_value_table
*opt
;
32468 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
32469 if (streq (opt
->name
, str
))
32471 meabi_flags
= opt
->value
;
32474 as_bad (_("unknown EABI `%s'\n"), str
);
32480 arm_parse_it_mode (const char * str
)
32482 bfd_boolean ret
= TRUE
;
32484 if (streq ("arm", str
))
32485 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
32486 else if (streq ("thumb", str
))
32487 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
32488 else if (streq ("always", str
))
32489 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
32490 else if (streq ("never", str
))
32491 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
32494 as_bad (_("unknown implicit IT mode `%s', should be "\
32495 "arm, thumb, always, or never."), str
);
32503 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
32505 codecomposer_syntax
= TRUE
;
32506 arm_comment_chars
[0] = ';';
32507 arm_line_separator_chars
[0] = 0;
32511 struct arm_long_option_table arm_long_opts
[] =
32513 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
32514 arm_parse_cpu
, NULL
},
32515 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
32516 arm_parse_arch
, NULL
},
32517 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
32518 arm_parse_fpu
, NULL
},
32519 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
32520 arm_parse_float_abi
, NULL
},
32522 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
32523 arm_parse_eabi
, NULL
},
32525 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
32526 arm_parse_it_mode
, NULL
},
32527 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
32528 arm_ccs_mode
, NULL
},
32530 N_("[ieee|alternative]\n\
32531 set the encoding for half precision floating point "
32532 "numbers to IEEE\n\
32533 or Arm alternative format."),
32534 arm_parse_fp16_opt
, NULL
},
32535 {NULL
, NULL
, 0, NULL
}
32539 md_parse_option (int c
, const char * arg
)
32541 struct arm_option_table
*opt
;
32542 const struct arm_legacy_option_table
*fopt
;
32543 struct arm_long_option_table
*lopt
;
32549 target_big_endian
= 1;
32555 target_big_endian
= 0;
32559 case OPTION_FIX_V4BX
:
32567 #endif /* OBJ_ELF */
32570 /* Listing option. Just ignore these, we don't support additional
32575 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32577 if (c
== opt
->option
[0]
32578 && ((arg
== NULL
&& opt
->option
[1] == 0)
32579 || streq (arg
, opt
->option
+ 1)))
32581 /* If the option is deprecated, tell the user. */
32582 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
32583 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32584 arg
? arg
: "", _(opt
->deprecated
));
32586 if (opt
->var
!= NULL
)
32587 *opt
->var
= opt
->value
;
32593 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
32595 if (c
== fopt
->option
[0]
32596 && ((arg
== NULL
&& fopt
->option
[1] == 0)
32597 || streq (arg
, fopt
->option
+ 1)))
32599 /* If the option is deprecated, tell the user. */
32600 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
32601 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32602 arg
? arg
: "", _(fopt
->deprecated
));
32604 if (fopt
->var
!= NULL
)
32605 *fopt
->var
= &fopt
->value
;
32611 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32613 /* These options are expected to have an argument. */
32614 if (c
== lopt
->option
[0]
32616 && strncmp (arg
, lopt
->option
+ 1,
32617 strlen (lopt
->option
+ 1)) == 0)
32619 /* If the option is deprecated, tell the user. */
32620 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
32621 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
32622 _(lopt
->deprecated
));
32624 /* Call the sup-option parser. */
32625 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
32636 md_show_usage (FILE * fp
)
32638 struct arm_option_table
*opt
;
32639 struct arm_long_option_table
*lopt
;
32641 fprintf (fp
, _(" ARM-specific assembler options:\n"));
32643 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32644 if (opt
->help
!= NULL
)
32645 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
32647 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32648 if (lopt
->help
!= NULL
)
32649 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
32653 -EB assemble code for a big-endian cpu\n"));
32658 -EL assemble code for a little-endian cpu\n"));
32662 --fix-v4bx Allow BX in ARMv4 code\n"));
32666 --fdpic generate an FDPIC object file\n"));
32667 #endif /* OBJ_ELF */
32675 arm_feature_set flags
;
32676 } cpu_arch_ver_table
;
32678 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
32679 chronologically for architectures, with an exception for ARMv6-M and
32680 ARMv6S-M due to legacy reasons. No new architecture should have a
32681 special case. This allows for build attribute selection results to be
32682 stable when new architectures are added. */
32683 static const cpu_arch_ver_table cpu_arch_ver
[] =
32685 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
32686 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
32687 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
32688 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
32689 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
32690 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
32691 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
32692 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
32693 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
32694 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
32695 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
32696 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
32697 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
32698 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
32699 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
32700 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
32701 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
32702 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
32703 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
32704 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
32705 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
32706 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
32707 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
32708 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
32710 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
32711 always selected build attributes to match those of ARMv6-M
32712 (resp. ARMv6S-M). However, due to these architectures being a strict
32713 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
32714 would be selected when fully respecting chronology of architectures.
32715 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
32716 move them before ARMv7 architectures. */
32717 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
32718 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
32720 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
32721 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
32722 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
32723 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
32724 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
32725 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
32726 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
32727 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
32728 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
32729 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
32730 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
32731 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
32732 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
32733 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
32734 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
32735 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
32736 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_6A
},
32737 {-1, ARM_ARCH_NONE
}
32740 /* Set an attribute if it has not already been set by the user. */
32743 aeabi_set_attribute_int (int tag
, int value
)
32746 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32747 || !attributes_set_explicitly
[tag
])
32748 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
32752 aeabi_set_attribute_string (int tag
, const char *value
)
32755 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32756 || !attributes_set_explicitly
[tag
])
32757 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
32760 /* Return whether features in the *NEEDED feature set are available via
32761 extensions for the architecture whose feature set is *ARCH_FSET. */
32764 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
32765 const arm_feature_set
*needed
)
32767 int i
, nb_allowed_archs
;
32768 arm_feature_set ext_fset
;
32769 const struct arm_option_extension_value_table
*opt
;
32771 ext_fset
= arm_arch_none
;
32772 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32774 /* Extension does not provide any feature we need. */
32775 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
32779 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32780 for (i
= 0; i
< nb_allowed_archs
; i
++)
32783 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
32786 /* Extension is available, add it. */
32787 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
32788 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
32792 /* Can we enable all features in *needed? */
32793 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
32796 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
32797 a given architecture feature set *ARCH_EXT_FSET including extension feature
32798 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
32799 - if true, check for an exact match of the architecture modulo extensions;
32800 - otherwise, select build attribute value of the first superset
32801 architecture released so that results remains stable when new architectures
32803 For -march/-mcpu=all the build attribute value of the most featureful
32804 architecture is returned. Tag_CPU_arch_profile result is returned in
32808 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
32809 const arm_feature_set
*ext_fset
,
32810 char *profile
, int exact_match
)
32812 arm_feature_set arch_fset
;
32813 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
32815 /* Select most featureful architecture with all its extensions if building
32816 for -march=all as the feature sets used to set build attributes. */
32817 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
32819 /* Force revisiting of decision for each new architecture. */
32820 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32822 return TAG_CPU_ARCH_V8
;
32825 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
32827 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
32829 arm_feature_set known_arch_fset
;
32831 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
32834 /* Base architecture match user-specified architecture and
32835 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
32836 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
32841 /* Base architecture match user-specified architecture only
32842 (eg. ARMv6-M in the same case as above). Record it in case we
32843 find a match with above condition. */
32844 else if (p_ver_ret
== NULL
32845 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
32851 /* Architecture has all features wanted. */
32852 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
32854 arm_feature_set added_fset
;
32856 /* Compute features added by this architecture over the one
32857 recorded in p_ver_ret. */
32858 if (p_ver_ret
!= NULL
)
32859 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
32861 /* First architecture that match incl. with extensions, or the
32862 only difference in features over the recorded match is
32863 features that were optional and are now mandatory. */
32864 if (p_ver_ret
== NULL
32865 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
32871 else if (p_ver_ret
== NULL
)
32873 arm_feature_set needed_ext_fset
;
32875 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
32877 /* Architecture has all features needed when using some
32878 extensions. Record it and continue searching in case there
32879 exist an architecture providing all needed features without
32880 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
32882 if (have_ext_for_needed_feat_p (&known_arch_fset
,
32889 if (p_ver_ret
== NULL
)
32893 /* Tag_CPU_arch_profile. */
32894 if (!ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8r
)
32895 && (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
32896 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
32897 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
32898 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
))))
32900 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
)
32901 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8r
))
32903 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
32907 return p_ver_ret
->val
;
32910 /* Set the public EABI object attributes. */
32913 aeabi_set_public_attributes (void)
32915 char profile
= '\0';
32918 int fp16_optional
= 0;
32919 int skip_exact_match
= 0;
32920 arm_feature_set flags
, flags_arch
, flags_ext
;
32922 /* Autodetection mode, choose the architecture based the instructions
32924 if (no_cpu_selected ())
32926 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
32928 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
32929 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
32931 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
32932 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
32934 /* Code run during relaxation relies on selected_cpu being set. */
32935 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32936 flags_ext
= arm_arch_none
;
32937 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
32938 selected_ext
= flags_ext
;
32939 selected_cpu
= flags
;
32941 /* Otherwise, choose the architecture based on the capabilities of the
32945 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
32946 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
32947 flags_ext
= selected_ext
;
32948 flags
= selected_cpu
;
32950 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
32952 /* Allow the user to override the reported architecture. */
32953 if (!ARM_FEATURE_ZERO (selected_object_arch
))
32955 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
32956 flags_ext
= arm_arch_none
;
32959 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
32961 /* When this function is run again after relaxation has happened there is no
32962 way to determine whether an architecture or CPU was specified by the user:
32963 - selected_cpu is set above for relaxation to work;
32964 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32965 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32966 Therefore, if not in -march=all case we first try an exact match and fall
32967 back to autodetection. */
32968 if (!skip_exact_match
)
32969 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
32971 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
32973 as_bad (_("no architecture contains all the instructions used\n"));
32975 /* Tag_CPU_name. */
32976 if (selected_cpu_name
[0])
32980 q
= selected_cpu_name
;
32981 if (strncmp (q
, "armv", 4) == 0)
32986 for (i
= 0; q
[i
]; i
++)
32987 q
[i
] = TOUPPER (q
[i
]);
32989 aeabi_set_attribute_string (Tag_CPU_name
, q
);
32992 /* Tag_CPU_arch. */
32993 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
32995 /* Tag_CPU_arch_profile. */
32996 if (profile
!= '\0')
32997 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
32999 /* Tag_DSP_extension. */
33000 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
33001 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
33003 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
33004 /* Tag_ARM_ISA_use. */
33005 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
33006 || ARM_FEATURE_ZERO (flags_arch
))
33007 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
33009 /* Tag_THUMB_ISA_use. */
33010 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
33011 || ARM_FEATURE_ZERO (flags_arch
))
33015 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33016 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
33018 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
33022 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
33025 /* Tag_VFP_arch. */
33026 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
33027 aeabi_set_attribute_int (Tag_VFP_arch
,
33028 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33030 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
33031 aeabi_set_attribute_int (Tag_VFP_arch
,
33032 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33034 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
33037 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
33039 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
33041 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
33044 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
33045 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
33046 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
33047 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
33048 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
33050 /* Tag_ABI_HardFP_use. */
33051 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
33052 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
33053 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
33055 /* Tag_WMMX_arch. */
33056 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
33057 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
33058 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
33059 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
33061 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
33062 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
33063 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
33064 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
33065 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
33066 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
33068 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
33070 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
33074 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
33079 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
33080 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
33081 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
33082 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
33084 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
33085 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
33086 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
33090 We set Tag_DIV_use to two when integer divide instructions have been used
33091 in ARM state, or when Thumb integer divide instructions have been used,
33092 but we have no architecture profile set, nor have we any ARM instructions.
33094 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
33095 by the base architecture.
33097 For new architectures we will have to check these tests. */
33098 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
33099 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33100 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
33101 aeabi_set_attribute_int (Tag_DIV_use
, 0);
33102 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
33103 || (profile
== '\0'
33104 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
33105 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
33106 aeabi_set_attribute_int (Tag_DIV_use
, 2);
33108 /* Tag_MP_extension_use. */
33109 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
33110 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
33112 /* Tag Virtualization_use. */
33113 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
33115 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
33118 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
33120 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
33121 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
33124 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
33125 finished and free extension feature bits which will not be used anymore. */
33128 arm_md_post_relax (void)
33130 aeabi_set_public_attributes ();
33131 XDELETE (mcpu_ext_opt
);
33132 mcpu_ext_opt
= NULL
;
33133 XDELETE (march_ext_opt
);
33134 march_ext_opt
= NULL
;
33137 /* Add the default contents for the .ARM.attributes section. */
33142 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
33145 aeabi_set_public_attributes ();
33147 #endif /* OBJ_ELF */
33149 /* Parse a .cpu directive. */
33152 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
33154 const struct arm_cpu_option_table
*opt
;
33158 name
= input_line_pointer
;
33159 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33160 input_line_pointer
++;
33161 saved_char
= *input_line_pointer
;
33162 *input_line_pointer
= 0;
33164 /* Skip the first "all" entry. */
33165 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
33166 if (streq (opt
->name
, name
))
33168 selected_arch
= opt
->value
;
33169 selected_ext
= opt
->ext
;
33170 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33171 if (opt
->canonical_name
)
33172 strcpy (selected_cpu_name
, opt
->canonical_name
);
33176 for (i
= 0; opt
->name
[i
]; i
++)
33177 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
33179 selected_cpu_name
[i
] = 0;
33181 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33183 *input_line_pointer
= saved_char
;
33184 demand_empty_rest_of_line ();
33187 as_bad (_("unknown cpu `%s'"), name
);
33188 *input_line_pointer
= saved_char
;
33189 ignore_rest_of_line ();
33192 /* Parse a .arch directive. */
33195 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
33197 const struct arm_arch_option_table
*opt
;
33201 name
= input_line_pointer
;
33202 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33203 input_line_pointer
++;
33204 saved_char
= *input_line_pointer
;
33205 *input_line_pointer
= 0;
33207 /* Skip the first "all" entry. */
33208 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33209 if (streq (opt
->name
, name
))
33211 selected_arch
= opt
->value
;
33212 selected_ctx_ext_table
= opt
->ext_table
;
33213 selected_ext
= arm_arch_none
;
33214 selected_cpu
= selected_arch
;
33215 strcpy (selected_cpu_name
, opt
->name
);
33216 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33217 *input_line_pointer
= saved_char
;
33218 demand_empty_rest_of_line ();
33222 as_bad (_("unknown architecture `%s'\n"), name
);
33223 *input_line_pointer
= saved_char
;
33224 ignore_rest_of_line ();
33227 /* Parse a .object_arch directive. */
33230 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
33232 const struct arm_arch_option_table
*opt
;
33236 name
= input_line_pointer
;
33237 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33238 input_line_pointer
++;
33239 saved_char
= *input_line_pointer
;
33240 *input_line_pointer
= 0;
33242 /* Skip the first "all" entry. */
33243 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33244 if (streq (opt
->name
, name
))
33246 selected_object_arch
= opt
->value
;
33247 *input_line_pointer
= saved_char
;
33248 demand_empty_rest_of_line ();
33252 as_bad (_("unknown architecture `%s'\n"), name
);
33253 *input_line_pointer
= saved_char
;
33254 ignore_rest_of_line ();
33257 /* Parse a .arch_extension directive. */
33260 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
33262 const struct arm_option_extension_value_table
*opt
;
33265 int adding_value
= 1;
33267 name
= input_line_pointer
;
33268 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33269 input_line_pointer
++;
33270 saved_char
= *input_line_pointer
;
33271 *input_line_pointer
= 0;
33273 if (strlen (name
) >= 2
33274 && strncmp (name
, "no", 2) == 0)
33280 /* Check the context specific extension table */
33281 if (selected_ctx_ext_table
)
33283 const struct arm_ext_table
* ext_opt
;
33284 for (ext_opt
= selected_ctx_ext_table
; ext_opt
->name
!= NULL
; ext_opt
++)
33286 if (streq (ext_opt
->name
, name
))
33290 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
33291 /* TODO: Option not supported. When we remove the
33292 legacy table this case should error out. */
33294 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33298 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, ext_opt
->clear
);
33300 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33301 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33302 *input_line_pointer
= saved_char
;
33303 demand_empty_rest_of_line ();
33309 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
33310 if (streq (opt
->name
, name
))
33312 int i
, nb_allowed_archs
=
33313 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
33314 for (i
= 0; i
< nb_allowed_archs
; i
++)
33317 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
33319 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
33323 if (i
== nb_allowed_archs
)
33325 as_bad (_("architectural extension `%s' is not allowed for the "
33326 "current base architecture"), name
);
33331 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33334 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
33336 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33337 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33338 *input_line_pointer
= saved_char
;
33339 demand_empty_rest_of_line ();
33340 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
33341 on this return so that duplicate extensions (extensions with the
33342 same name as a previous extension in the list) are not considered
33343 for command-line parsing. */
33347 if (opt
->name
== NULL
)
33348 as_bad (_("unknown architecture extension `%s'\n"), name
);
33350 *input_line_pointer
= saved_char
;
33351 ignore_rest_of_line ();
33354 /* Parse a .fpu directive. */
33357 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
33359 const struct arm_option_fpu_value_table
*opt
;
33363 name
= input_line_pointer
;
33364 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33365 input_line_pointer
++;
33366 saved_char
= *input_line_pointer
;
33367 *input_line_pointer
= 0;
33369 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
33370 if (streq (opt
->name
, name
))
33372 selected_fpu
= opt
->value
;
33373 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, fpu_any
);
33374 #ifndef CPU_DEFAULT
33375 if (no_cpu_selected ())
33376 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
33379 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33380 *input_line_pointer
= saved_char
;
33381 demand_empty_rest_of_line ();
33385 as_bad (_("unknown floating point format `%s'\n"), name
);
33386 *input_line_pointer
= saved_char
;
33387 ignore_rest_of_line ();
33390 /* Copy symbol information. */
33393 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
33395 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
33399 /* Given a symbolic attribute NAME, return the proper integer value.
33400 Returns -1 if the attribute is not known. */
33403 arm_convert_symbolic_attribute (const char *name
)
33405 static const struct
33410 attribute_table
[] =
33412 /* When you modify this table you should
33413 also modify the list in doc/c-arm.texi. */
33414 #define T(tag) {#tag, tag}
33415 T (Tag_CPU_raw_name
),
33418 T (Tag_CPU_arch_profile
),
33419 T (Tag_ARM_ISA_use
),
33420 T (Tag_THUMB_ISA_use
),
33424 T (Tag_Advanced_SIMD_arch
),
33425 T (Tag_PCS_config
),
33426 T (Tag_ABI_PCS_R9_use
),
33427 T (Tag_ABI_PCS_RW_data
),
33428 T (Tag_ABI_PCS_RO_data
),
33429 T (Tag_ABI_PCS_GOT_use
),
33430 T (Tag_ABI_PCS_wchar_t
),
33431 T (Tag_ABI_FP_rounding
),
33432 T (Tag_ABI_FP_denormal
),
33433 T (Tag_ABI_FP_exceptions
),
33434 T (Tag_ABI_FP_user_exceptions
),
33435 T (Tag_ABI_FP_number_model
),
33436 T (Tag_ABI_align_needed
),
33437 T (Tag_ABI_align8_needed
),
33438 T (Tag_ABI_align_preserved
),
33439 T (Tag_ABI_align8_preserved
),
33440 T (Tag_ABI_enum_size
),
33441 T (Tag_ABI_HardFP_use
),
33442 T (Tag_ABI_VFP_args
),
33443 T (Tag_ABI_WMMX_args
),
33444 T (Tag_ABI_optimization_goals
),
33445 T (Tag_ABI_FP_optimization_goals
),
33446 T (Tag_compatibility
),
33447 T (Tag_CPU_unaligned_access
),
33448 T (Tag_FP_HP_extension
),
33449 T (Tag_VFP_HP_extension
),
33450 T (Tag_ABI_FP_16bit_format
),
33451 T (Tag_MPextension_use
),
33453 T (Tag_nodefaults
),
33454 T (Tag_also_compatible_with
),
33455 T (Tag_conformance
),
33457 T (Tag_Virtualization_use
),
33458 T (Tag_DSP_extension
),
33460 /* We deliberately do not include Tag_MPextension_use_legacy. */
33468 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
33469 if (streq (name
, attribute_table
[i
].name
))
33470 return attribute_table
[i
].tag
;
33475 /* Apply sym value for relocations only in the case that they are for
33476 local symbols in the same segment as the fixup and you have the
33477 respective architectural feature for blx and simple switches. */
33480 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
33483 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
33484 /* PR 17444: If the local symbol is in a different section then a reloc
33485 will always be generated for it, so applying the symbol value now
33486 will result in a double offset being stored in the relocation. */
33487 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
33488 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
33490 switch (fixP
->fx_r_type
)
33492 case BFD_RELOC_ARM_PCREL_BLX
:
33493 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
33494 if (ARM_IS_FUNC (fixP
->fx_addsy
))
33498 case BFD_RELOC_ARM_PCREL_CALL
:
33499 case BFD_RELOC_THUMB_PCREL_BLX
:
33500 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
33511 #endif /* OBJ_ELF */