1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 #if defined __XSCALE__
101 #define CPU_DEFAULT ARM_ARCH_XSCALE
103 #if defined __thumb__
104 #define CPU_DEFAULT ARM_ARCH_V5T
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 static arm_feature_set cpu_variant
;
130 static arm_feature_set arm_arch_used
;
131 static arm_feature_set thumb_arch_used
;
133 /* Flags stored in private area of BFD structure. */
134 static int uses_apcs_26
= FALSE
;
135 static int atpcs
= FALSE
;
136 static int support_interwork
= FALSE
;
137 static int uses_apcs_float
= FALSE
;
138 static int pic_code
= FALSE
;
139 static int fix_v4bx
= FALSE
;
140 /* Warn on using deprecated features. */
141 static int warn_on_deprecated
= TRUE
;
144 /* Variables that we set while parsing command-line options. Once all
145 options have been read we re-process these values to set the real
147 static const arm_feature_set
*legacy_cpu
= NULL
;
148 static const arm_feature_set
*legacy_fpu
= NULL
;
150 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
151 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
152 static const arm_feature_set
*march_cpu_opt
= NULL
;
153 static const arm_feature_set
*march_fpu_opt
= NULL
;
154 static const arm_feature_set
*mfpu_opt
= NULL
;
155 static const arm_feature_set
*object_arch
= NULL
;
157 /* Constants for known architecture features. */
158 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
159 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
160 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
161 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
162 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
163 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
164 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
165 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
166 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
169 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
172 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
174 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
175 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
176 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
177 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
178 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
179 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
180 static const arm_feature_set arm_ext_v4t_5
=
181 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
182 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
183 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
184 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
185 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
186 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
187 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
188 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
189 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
190 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_m
=
198 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_arch_any
= ARM_ANY
;
201 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
202 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
203 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
205 static const arm_feature_set arm_cext_iwmmxt2
=
206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
207 static const arm_feature_set arm_cext_iwmmxt
=
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
209 static const arm_feature_set arm_cext_xscale
=
210 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
211 static const arm_feature_set arm_cext_maverick
=
212 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
213 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
214 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
215 static const arm_feature_set fpu_vfp_ext_v1xd
=
216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
217 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
218 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
219 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
220 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
221 static const arm_feature_set fpu_vfp_ext_d32
=
222 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
223 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
224 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
225 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
226 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
227 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
228 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
230 static int mfloat_abi_opt
= -1;
231 /* Record user cpu selection for object attributes. */
232 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
233 /* Must be long enough to hold any of the names in arm_cpus. */
234 static char selected_cpu_name
[16];
237 static int meabi_flags
= EABI_DEFAULT
;
239 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
242 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
247 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
252 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
253 symbolS
* GOT_symbol
;
256 /* 0: assemble for ARM,
257 1: assemble for Thumb,
258 2: assemble for Thumb even though target CPU does not support thumb
260 static int thumb_mode
= 0;
261 /* A value distinct from the possible values for thumb_mode that we
262 can use to record whether thumb_mode has been copied into the
263 tc_frag_data field of a frag. */
264 #define MODE_RECORDED (1 << 4)
266 /* Specifies the intrinsic IT insn behavior mode. */
267 enum implicit_it_mode
269 IMPLICIT_IT_MODE_NEVER
= 0x00,
270 IMPLICIT_IT_MODE_ARM
= 0x01,
271 IMPLICIT_IT_MODE_THUMB
= 0x02,
272 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
274 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
276 /* If unified_syntax is true, we are processing the new unified
277 ARM/Thumb syntax. Important differences from the old ARM mode:
279 - Immediate operands do not require a # prefix.
280 - Conditional affixes always appear at the end of the
281 instruction. (For backward compatibility, those instructions
282 that formerly had them in the middle, continue to accept them
284 - The IT instruction may appear, and if it does is validated
285 against subsequent conditional affixes. It does not generate
288 Important differences from the old Thumb mode:
290 - Immediate operands do not require a # prefix.
291 - Most of the V6T2 instructions are only available in unified mode.
292 - The .N and .W suffixes are recognized and honored (it is an error
293 if they cannot be honored).
294 - All instructions set the flags if and only if they have an 's' affix.
295 - Conditional affixes may be used. They are validated against
296 preceding IT instructions. Unlike ARM mode, you cannot use a
297 conditional affix except in the scope of an IT instruction. */
299 static bfd_boolean unified_syntax
= FALSE
;
314 enum neon_el_type type
;
318 #define NEON_MAX_TYPE_ELS 4
322 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
326 enum it_instruction_type
331 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
332 if inside, should be the last one. */
333 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
334 i.e. BKPT and NOP. */
335 IT_INSN
/* The IT insn has been parsed. */
341 unsigned long instruction
;
345 /* "uncond_value" is set to the value in place of the conditional field in
346 unconditional versions of the instruction, or -1 if nothing is
349 struct neon_type vectype
;
350 /* Set to the opcode if the instruction needs relaxation.
351 Zero if the instruction is not relaxed. */
355 bfd_reloc_code_real_type type
;
360 enum it_instruction_type it_insn_type
;
366 struct neon_type_el vectype
;
367 unsigned present
: 1; /* Operand present. */
368 unsigned isreg
: 1; /* Operand was a register. */
369 unsigned immisreg
: 1; /* .imm field is a second register. */
370 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
371 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
372 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
373 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
374 instructions. This allows us to disambiguate ARM <-> vector insns. */
375 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
376 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
377 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
378 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
379 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
380 unsigned writeback
: 1; /* Operand has trailing ! */
381 unsigned preind
: 1; /* Preindexed address. */
382 unsigned postind
: 1; /* Postindexed address. */
383 unsigned negative
: 1; /* Index register was negated. */
384 unsigned shifted
: 1; /* Shift applied to operation. */
385 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
389 static struct arm_it inst
;
391 #define NUM_FLOAT_VALS 8
393 const char * fp_const
[] =
395 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
398 /* Number of littlenums required to hold an extended precision number. */
399 #define MAX_LITTLENUMS 6
401 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
411 #define CP_T_X 0x00008000
412 #define CP_T_Y 0x00400000
414 #define CONDS_BIT 0x00100000
415 #define LOAD_BIT 0x00100000
417 #define DOUBLE_LOAD_FLAG 0x00000001
421 const char * template_name
;
425 #define COND_ALWAYS 0xE
429 const char * template_name
;
433 struct asm_barrier_opt
435 const char * template_name
;
439 /* The bit that distinguishes CPSR and SPSR. */
440 #define SPSR_BIT (1 << 22)
442 /* The individual PSR flag bits. */
443 #define PSR_c (1 << 16)
444 #define PSR_x (1 << 17)
445 #define PSR_s (1 << 18)
446 #define PSR_f (1 << 19)
451 bfd_reloc_code_real_type reloc
;
456 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
457 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
462 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
465 /* Bits for DEFINED field in neon_typed_alias. */
466 #define NTA_HASTYPE 1
467 #define NTA_HASINDEX 2
469 struct neon_typed_alias
471 unsigned char defined
;
473 struct neon_type_el eltype
;
476 /* ARM register categories. This includes coprocessor numbers and various
477 architecture extensions' registers. */
503 /* Structure for a hash table entry for a register.
504 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
505 information which states whether a vector type or index is specified (for a
506 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
510 unsigned char number
;
512 unsigned char builtin
;
513 struct neon_typed_alias
* neon
;
516 /* Diagnostics used when we don't get a register of the expected type. */
517 const char * const reg_expected_msgs
[] =
519 N_("ARM register expected"),
520 N_("bad or missing co-processor number"),
521 N_("co-processor register expected"),
522 N_("FPA register expected"),
523 N_("VFP single precision register expected"),
524 N_("VFP/Neon double precision register expected"),
525 N_("Neon quad precision register expected"),
526 N_("VFP single or double precision register expected"),
527 N_("Neon double or quad precision register expected"),
528 N_("VFP single, double or Neon quad precision register expected"),
529 N_("VFP system register expected"),
530 N_("Maverick MVF register expected"),
531 N_("Maverick MVD register expected"),
532 N_("Maverick MVFX register expected"),
533 N_("Maverick MVDX register expected"),
534 N_("Maverick MVAX register expected"),
535 N_("Maverick DSPSC register expected"),
536 N_("iWMMXt data register expected"),
537 N_("iWMMXt control register expected"),
538 N_("iWMMXt scalar register expected"),
539 N_("XScale accumulator register expected"),
542 /* Some well known registers that we refer to directly elsewhere. */
547 /* ARM instructions take 4bytes in the object file, Thumb instructions
553 /* Basic string to match. */
554 const char * template_name
;
556 /* Parameters to instruction. */
557 unsigned char operands
[8];
559 /* Conditional tag - see opcode_lookup. */
560 unsigned int tag
: 4;
562 /* Basic instruction code. */
563 unsigned int avalue
: 28;
565 /* Thumb-format instruction code. */
568 /* Which architecture variant provides this instruction. */
569 const arm_feature_set
* avariant
;
570 const arm_feature_set
* tvariant
;
572 /* Function to call to encode instruction in ARM format. */
573 void (* aencode
) (void);
575 /* Function to call to encode instruction in Thumb format. */
576 void (* tencode
) (void);
579 /* Defines for various bits that we will want to toggle. */
580 #define INST_IMMEDIATE 0x02000000
581 #define OFFSET_REG 0x02000000
582 #define HWOFFSET_IMM 0x00400000
583 #define SHIFT_BY_REG 0x00000010
584 #define PRE_INDEX 0x01000000
585 #define INDEX_UP 0x00800000
586 #define WRITE_BACK 0x00200000
587 #define LDM_TYPE_2_OR_3 0x00400000
588 #define CPSI_MMOD 0x00020000
590 #define LITERAL_MASK 0xf000f000
591 #define OPCODE_MASK 0xfe1fffff
592 #define V4_STR_BIT 0x00000020
594 #define T2_SUBS_PC_LR 0xf3de8f00
596 #define DATA_OP_SHIFT 21
598 #define T2_OPCODE_MASK 0xfe1fffff
599 #define T2_DATA_OP_SHIFT 21
601 /* Codes to distinguish the arithmetic instructions. */
612 #define OPCODE_CMP 10
613 #define OPCODE_CMN 11
614 #define OPCODE_ORR 12
615 #define OPCODE_MOV 13
616 #define OPCODE_BIC 14
617 #define OPCODE_MVN 15
619 #define T2_OPCODE_AND 0
620 #define T2_OPCODE_BIC 1
621 #define T2_OPCODE_ORR 2
622 #define T2_OPCODE_ORN 3
623 #define T2_OPCODE_EOR 4
624 #define T2_OPCODE_ADD 8
625 #define T2_OPCODE_ADC 10
626 #define T2_OPCODE_SBC 11
627 #define T2_OPCODE_SUB 13
628 #define T2_OPCODE_RSB 14
630 #define T_OPCODE_MUL 0x4340
631 #define T_OPCODE_TST 0x4200
632 #define T_OPCODE_CMN 0x42c0
633 #define T_OPCODE_NEG 0x4240
634 #define T_OPCODE_MVN 0x43c0
636 #define T_OPCODE_ADD_R3 0x1800
637 #define T_OPCODE_SUB_R3 0x1a00
638 #define T_OPCODE_ADD_HI 0x4400
639 #define T_OPCODE_ADD_ST 0xb000
640 #define T_OPCODE_SUB_ST 0xb080
641 #define T_OPCODE_ADD_SP 0xa800
642 #define T_OPCODE_ADD_PC 0xa000
643 #define T_OPCODE_ADD_I8 0x3000
644 #define T_OPCODE_SUB_I8 0x3800
645 #define T_OPCODE_ADD_I3 0x1c00
646 #define T_OPCODE_SUB_I3 0x1e00
648 #define T_OPCODE_ASR_R 0x4100
649 #define T_OPCODE_LSL_R 0x4080
650 #define T_OPCODE_LSR_R 0x40c0
651 #define T_OPCODE_ROR_R 0x41c0
652 #define T_OPCODE_ASR_I 0x1000
653 #define T_OPCODE_LSL_I 0x0000
654 #define T_OPCODE_LSR_I 0x0800
656 #define T_OPCODE_MOV_I8 0x2000
657 #define T_OPCODE_CMP_I8 0x2800
658 #define T_OPCODE_CMP_LR 0x4280
659 #define T_OPCODE_MOV_HR 0x4600
660 #define T_OPCODE_CMP_HR 0x4500
662 #define T_OPCODE_LDR_PC 0x4800
663 #define T_OPCODE_LDR_SP 0x9800
664 #define T_OPCODE_STR_SP 0x9000
665 #define T_OPCODE_LDR_IW 0x6800
666 #define T_OPCODE_STR_IW 0x6000
667 #define T_OPCODE_LDR_IH 0x8800
668 #define T_OPCODE_STR_IH 0x8000
669 #define T_OPCODE_LDR_IB 0x7800
670 #define T_OPCODE_STR_IB 0x7000
671 #define T_OPCODE_LDR_RW 0x5800
672 #define T_OPCODE_STR_RW 0x5000
673 #define T_OPCODE_LDR_RH 0x5a00
674 #define T_OPCODE_STR_RH 0x5200
675 #define T_OPCODE_LDR_RB 0x5c00
676 #define T_OPCODE_STR_RB 0x5400
678 #define T_OPCODE_PUSH 0xb400
679 #define T_OPCODE_POP 0xbc00
681 #define T_OPCODE_BRANCH 0xe000
683 #define THUMB_SIZE 2 /* Size of thumb instruction. */
684 #define THUMB_PP_PC_LR 0x0100
685 #define THUMB_LOAD_BIT 0x0800
686 #define THUMB2_LOAD_BIT 0x00100000
688 #define BAD_ARGS _("bad arguments to instruction")
689 #define BAD_SP _("r13 not allowed here")
690 #define BAD_PC _("r15 not allowed here")
691 #define BAD_COND _("instruction cannot be conditional")
692 #define BAD_OVERLAP _("registers may not be the same")
693 #define BAD_HIREG _("lo register required")
694 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
695 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
696 #define BAD_BRANCH _("branch must be last instruction in IT block")
697 #define BAD_NOT_IT _("instruction not allowed in IT block")
698 #define BAD_FPU _("selected FPU does not support instruction")
699 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
700 #define BAD_IT_COND _("incorrect condition in IT block")
701 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
702 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
704 static struct hash_control
* arm_ops_hsh
;
705 static struct hash_control
* arm_cond_hsh
;
706 static struct hash_control
* arm_shift_hsh
;
707 static struct hash_control
* arm_psr_hsh
;
708 static struct hash_control
* arm_v7m_psr_hsh
;
709 static struct hash_control
* arm_reg_hsh
;
710 static struct hash_control
* arm_reloc_hsh
;
711 static struct hash_control
* arm_barrier_opt_hsh
;
713 /* Stuff needed to resolve the label ambiguity
722 symbolS
* last_label_seen
;
723 static int label_is_thumb_function_name
= FALSE
;
725 /* Literal pool structure. Held on a per-section
726 and per-sub-section basis. */
728 #define MAX_LITERAL_POOL_SIZE 1024
729 typedef struct literal_pool
731 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
732 unsigned int next_free_entry
;
737 struct literal_pool
* next
;
740 /* Pointer to a linked list of literal pools. */
741 literal_pool
* list_of_pools
= NULL
;
744 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
746 static struct current_it now_it
;
750 now_it_compatible (int cond
)
752 return (cond
& ~1) == (now_it
.cc
& ~1);
756 conditional_insn (void)
758 return inst
.cond
!= COND_ALWAYS
;
761 static int in_it_block (void);
763 static int handle_it_state (void);
765 static void force_automatic_it_block_close (void);
767 static void it_fsm_post_encode (void);
769 #define set_it_insn_type(type) \
772 inst.it_insn_type = type; \
773 if (handle_it_state () == FAIL) \
778 #define set_it_insn_type_nonvoid(type, failret) \
781 inst.it_insn_type = type; \
782 if (handle_it_state () == FAIL) \
787 #define set_it_insn_type_last() \
790 if (inst.cond == COND_ALWAYS) \
791 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
793 set_it_insn_type (INSIDE_IT_LAST_INSN); \
799 /* This array holds the chars that always start a comment. If the
800 pre-processor is disabled, these aren't very useful. */
801 const char comment_chars
[] = "@";
803 /* This array holds the chars that only start a comment at the beginning of
804 a line. If the line seems to have the form '# 123 filename'
805 .line and .file directives will appear in the pre-processed output. */
806 /* Note that input_file.c hand checks for '#' at the beginning of the
807 first line of the input file. This is because the compiler outputs
808 #NO_APP at the beginning of its output. */
809 /* Also note that comments like this one will always work. */
810 const char line_comment_chars
[] = "#";
812 const char line_separator_chars
[] = ";";
814 /* Chars that can be used to separate mant
815 from exp in floating point numbers. */
816 const char EXP_CHARS
[] = "eE";
818 /* Chars that mean this number is a floating point constant. */
822 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
824 /* Prefix characters that indicate the start of an immediate
826 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
828 /* Separator character handling. */
830 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
833 skip_past_char (char ** str
, char c
)
844 #define skip_past_comma(str) skip_past_char (str, ',')
846 /* Arithmetic expressions (possibly involving symbols). */
848 /* Return TRUE if anything in the expression is a bignum. */
851 walk_no_bignums (symbolS
* sp
)
853 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
856 if (symbol_get_value_expression (sp
)->X_add_symbol
)
858 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
859 || (symbol_get_value_expression (sp
)->X_op_symbol
860 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
866 static int in_my_get_expression
= 0;
868 /* Third argument to my_get_expression. */
869 #define GE_NO_PREFIX 0
870 #define GE_IMM_PREFIX 1
871 #define GE_OPT_PREFIX 2
872 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
873 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
874 #define GE_OPT_PREFIX_BIG 3
877 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
882 /* In unified syntax, all prefixes are optional. */
884 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
889 case GE_NO_PREFIX
: break;
891 if (!is_immediate_prefix (**str
))
893 inst
.error
= _("immediate expression requires a # prefix");
899 case GE_OPT_PREFIX_BIG
:
900 if (is_immediate_prefix (**str
))
906 memset (ep
, 0, sizeof (expressionS
));
908 save_in
= input_line_pointer
;
909 input_line_pointer
= *str
;
910 in_my_get_expression
= 1;
911 seg
= expression (ep
);
912 in_my_get_expression
= 0;
914 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
916 /* We found a bad or missing expression in md_operand(). */
917 *str
= input_line_pointer
;
918 input_line_pointer
= save_in
;
919 if (inst
.error
== NULL
)
920 inst
.error
= (ep
->X_op
== O_absent
921 ? _("missing expression") :_("bad expression"));
926 if (seg
!= absolute_section
927 && seg
!= text_section
928 && seg
!= data_section
929 && seg
!= bss_section
930 && seg
!= undefined_section
)
932 inst
.error
= _("bad segment");
933 *str
= input_line_pointer
;
934 input_line_pointer
= save_in
;
939 /* Get rid of any bignums now, so that we don't generate an error for which
940 we can't establish a line number later on. Big numbers are never valid
941 in instructions, which is where this routine is always called. */
942 if (prefix_mode
!= GE_OPT_PREFIX_BIG
943 && (ep
->X_op
== O_big
945 && (walk_no_bignums (ep
->X_add_symbol
)
947 && walk_no_bignums (ep
->X_op_symbol
))))))
949 inst
.error
= _("invalid constant");
950 *str
= input_line_pointer
;
951 input_line_pointer
= save_in
;
955 *str
= input_line_pointer
;
956 input_line_pointer
= save_in
;
960 /* Turn a string in input_line_pointer into a floating point constant
961 of type TYPE, and store the appropriate bytes in *LITP. The number
962 of LITTLENUMS emitted is stored in *SIZEP. An error message is
963 returned, or NULL on OK.
965 Note that fp constants aren't represent in the normal way on the ARM.
966 In big endian mode, things are as expected. However, in little endian
967 mode fp constants are big-endian word-wise, and little-endian byte-wise
968 within the words. For example, (double) 1.1 in big endian mode is
969 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
970 the byte sequence 99 99 f1 3f 9a 99 99 99.
972 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
975 md_atof (int type
, char * litP
, int * sizeP
)
978 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1010 return _("Unrecognized or unsupported floating point constant");
1013 t
= atof_ieee (input_line_pointer
, type
, words
);
1015 input_line_pointer
= t
;
1016 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1018 if (target_big_endian
)
1020 for (i
= 0; i
< prec
; i
++)
1022 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1023 litP
+= sizeof (LITTLENUM_TYPE
);
1028 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1029 for (i
= prec
- 1; i
>= 0; i
--)
1031 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1032 litP
+= sizeof (LITTLENUM_TYPE
);
1035 /* For a 4 byte float the order of elements in `words' is 1 0.
1036 For an 8 byte float the order is 1 0 3 2. */
1037 for (i
= 0; i
< prec
; i
+= 2)
1039 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1040 sizeof (LITTLENUM_TYPE
));
1041 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1042 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1043 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1050 /* We handle all bad expressions here, so that we can report the faulty
1051 instruction in the error message. */
1053 md_operand (expressionS
* expr
)
1055 if (in_my_get_expression
)
1056 expr
->X_op
= O_illegal
;
1059 /* Immediate values. */
1061 /* Generic immediate-value read function for use in directives.
1062 Accepts anything that 'expression' can fold to a constant.
1063 *val receives the number. */
1066 immediate_for_directive (int *val
)
1069 exp
.X_op
= O_illegal
;
1071 if (is_immediate_prefix (*input_line_pointer
))
1073 input_line_pointer
++;
1077 if (exp
.X_op
!= O_constant
)
1079 as_bad (_("expected #constant"));
1080 ignore_rest_of_line ();
1083 *val
= exp
.X_add_number
;
1088 /* Register parsing. */
1090 /* Generic register parser. CCP points to what should be the
1091 beginning of a register name. If it is indeed a valid register
1092 name, advance CCP over it and return the reg_entry structure;
1093 otherwise return NULL. Does not issue diagnostics. */
1095 static struct reg_entry
*
1096 arm_reg_parse_multi (char **ccp
)
1100 struct reg_entry
*reg
;
1102 #ifdef REGISTER_PREFIX
1103 if (*start
!= REGISTER_PREFIX
)
1107 #ifdef OPTIONAL_REGISTER_PREFIX
1108 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1113 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1118 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1120 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1130 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1131 enum arm_reg_type type
)
1133 /* Alternative syntaxes are accepted for a few register classes. */
1140 /* Generic coprocessor register names are allowed for these. */
1141 if (reg
&& reg
->type
== REG_TYPE_CN
)
1146 /* For backward compatibility, a bare number is valid here. */
1148 unsigned long processor
= strtoul (start
, ccp
, 10);
1149 if (*ccp
!= start
&& processor
<= 15)
1153 case REG_TYPE_MMXWC
:
1154 /* WC includes WCG. ??? I'm not sure this is true for all
1155 instructions that take WC registers. */
1156 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1167 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1168 return value is the register number or FAIL. */
1171 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1174 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1177 /* Do not allow a scalar (reg+index) to parse as a register. */
1178 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1181 if (reg
&& reg
->type
== type
)
1184 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1191 /* Parse a Neon type specifier. *STR should point at the leading '.'
1192 character. Does no verification at this stage that the type fits the opcode
1199 Can all be legally parsed by this function.
1201 Fills in neon_type struct pointer with parsed information, and updates STR
1202 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1203 type, FAIL if not. */
1206 parse_neon_type (struct neon_type
*type
, char **str
)
1213 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1215 enum neon_el_type thistype
= NT_untyped
;
1216 unsigned thissize
= -1u;
1223 /* Just a size without an explicit type. */
1227 switch (TOLOWER (*ptr
))
1229 case 'i': thistype
= NT_integer
; break;
1230 case 'f': thistype
= NT_float
; break;
1231 case 'p': thistype
= NT_poly
; break;
1232 case 's': thistype
= NT_signed
; break;
1233 case 'u': thistype
= NT_unsigned
; break;
1235 thistype
= NT_float
;
1240 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1246 /* .f is an abbreviation for .f32. */
1247 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1252 thissize
= strtoul (ptr
, &ptr
, 10);
1254 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1257 as_bad (_("bad size %d in type specifier"), thissize
);
1265 type
->el
[type
->elems
].type
= thistype
;
1266 type
->el
[type
->elems
].size
= thissize
;
1271 /* Empty/missing type is not a successful parse. */
1272 if (type
->elems
== 0)
1280 /* Errors may be set multiple times during parsing or bit encoding
1281 (particularly in the Neon bits), but usually the earliest error which is set
1282 will be the most meaningful. Avoid overwriting it with later (cascading)
1283 errors by calling this function. */
1286 first_error (const char *err
)
1292 /* Parse a single type, e.g. ".s32", leading period included. */
1294 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1297 struct neon_type optype
;
1301 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1303 if (optype
.elems
== 1)
1304 *vectype
= optype
.el
[0];
1307 first_error (_("only one type should be specified for operand"));
1313 first_error (_("vector type expected"));
1325 /* Special meanings for indices (which have a range of 0-7), which will fit into
1328 #define NEON_ALL_LANES 15
1329 #define NEON_INTERLEAVE_LANES 14
1331 /* Parse either a register or a scalar, with an optional type. Return the
1332 register number, and optionally fill in the actual type of the register
1333 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1334 type/index information in *TYPEINFO. */
1337 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1338 enum arm_reg_type
*rtype
,
1339 struct neon_typed_alias
*typeinfo
)
1342 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1343 struct neon_typed_alias atype
;
1344 struct neon_type_el parsetype
;
1348 atype
.eltype
.type
= NT_invtype
;
1349 atype
.eltype
.size
= -1;
1351 /* Try alternate syntax for some types of register. Note these are mutually
1352 exclusive with the Neon syntax extensions. */
1355 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1363 /* Undo polymorphism when a set of register types may be accepted. */
1364 if ((type
== REG_TYPE_NDQ
1365 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1366 || (type
== REG_TYPE_VFSD
1367 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1368 || (type
== REG_TYPE_NSDQ
1369 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1370 || reg
->type
== REG_TYPE_NQ
))
1371 || (type
== REG_TYPE_MMXWC
1372 && (reg
->type
== REG_TYPE_MMXWCG
)))
1373 type
= (enum arm_reg_type
) reg
->type
;
1375 if (type
!= reg
->type
)
1381 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1383 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1385 first_error (_("can't redefine type for operand"));
1388 atype
.defined
|= NTA_HASTYPE
;
1389 atype
.eltype
= parsetype
;
1392 if (skip_past_char (&str
, '[') == SUCCESS
)
1394 if (type
!= REG_TYPE_VFD
)
1396 first_error (_("only D registers may be indexed"));
1400 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1402 first_error (_("can't change index for operand"));
1406 atype
.defined
|= NTA_HASINDEX
;
1408 if (skip_past_char (&str
, ']') == SUCCESS
)
1409 atype
.index
= NEON_ALL_LANES
;
1414 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1416 if (exp
.X_op
!= O_constant
)
1418 first_error (_("constant expression required"));
1422 if (skip_past_char (&str
, ']') == FAIL
)
1425 atype
.index
= exp
.X_add_number
;
1440 /* Like arm_reg_parse, but allow allow the following extra features:
1441 - If RTYPE is non-zero, return the (possibly restricted) type of the
1442 register (e.g. Neon double or quad reg when either has been requested).
1443 - If this is a Neon vector type with additional type information, fill
1444 in the struct pointed to by VECTYPE (if non-NULL).
1445 This function will fault on encountering a scalar. */
1448 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1449 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1451 struct neon_typed_alias atype
;
1453 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1458 /* Do not allow a scalar (reg+index) to parse as a register. */
1459 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1461 first_error (_("register operand expected, but got scalar"));
1466 *vectype
= atype
.eltype
;
1473 #define NEON_SCALAR_REG(X) ((X) >> 4)
1474 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1476 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1477 have enough information to be able to do a good job bounds-checking. So, we
1478 just do easy checks here, and do further checks later. */
1481 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1485 struct neon_typed_alias atype
;
1487 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1489 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1492 if (atype
.index
== NEON_ALL_LANES
)
1494 first_error (_("scalar must have an index"));
1497 else if (atype
.index
>= 64 / elsize
)
1499 first_error (_("scalar index out of range"));
1504 *type
= atype
.eltype
;
1508 return reg
* 16 + atype
.index
;
1511 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1514 parse_reg_list (char ** strp
)
1516 char * str
= * strp
;
1520 /* We come back here if we get ranges concatenated by '+' or '|'. */
1535 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1537 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1547 first_error (_("bad range in register list"));
1551 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1553 if (range
& (1 << i
))
1555 (_("Warning: duplicated register (r%d) in register list"),
1563 if (range
& (1 << reg
))
1564 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1566 else if (reg
<= cur_reg
)
1567 as_tsktsk (_("Warning: register range not in ascending order"));
1572 while (skip_past_comma (&str
) != FAIL
1573 || (in_range
= 1, *str
++ == '-'));
1578 first_error (_("missing `}'"));
1586 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1589 if (expr
.X_op
== O_constant
)
1591 if (expr
.X_add_number
1592 != (expr
.X_add_number
& 0x0000ffff))
1594 inst
.error
= _("invalid register mask");
1598 if ((range
& expr
.X_add_number
) != 0)
1600 int regno
= range
& expr
.X_add_number
;
1603 regno
= (1 << regno
) - 1;
1605 (_("Warning: duplicated register (r%d) in register list"),
1609 range
|= expr
.X_add_number
;
1613 if (inst
.reloc
.type
!= 0)
1615 inst
.error
= _("expression too complex");
1619 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1620 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1621 inst
.reloc
.pc_rel
= 0;
1625 if (*str
== '|' || *str
== '+')
1631 while (another_range
);
1637 /* Types of registers in a list. */
1646 /* Parse a VFP register list. If the string is invalid return FAIL.
1647 Otherwise return the number of registers, and set PBASE to the first
1648 register. Parses registers of type ETYPE.
1649 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1650 - Q registers can be used to specify pairs of D registers
1651 - { } can be omitted from around a singleton register list
1652 FIXME: This is not implemented, as it would require backtracking in
1655 This could be done (the meaning isn't really ambiguous), but doesn't
1656 fit in well with the current parsing framework.
1657 - 32 D registers may be used (also true for VFPv3).
1658 FIXME: Types are ignored in these register lists, which is probably a
1662 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1667 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1671 unsigned long mask
= 0;
1676 inst
.error
= _("expecting {");
1685 regtype
= REG_TYPE_VFS
;
1690 regtype
= REG_TYPE_VFD
;
1693 case REGLIST_NEON_D
:
1694 regtype
= REG_TYPE_NDQ
;
1698 if (etype
!= REGLIST_VFP_S
)
1700 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1701 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1705 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1708 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1715 base_reg
= max_regs
;
1719 int setmask
= 1, addregs
= 1;
1721 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1723 if (new_base
== FAIL
)
1725 first_error (_(reg_expected_msgs
[regtype
]));
1729 if (new_base
>= max_regs
)
1731 first_error (_("register out of range in list"));
1735 /* Note: a value of 2 * n is returned for the register Q<n>. */
1736 if (regtype
== REG_TYPE_NQ
)
1742 if (new_base
< base_reg
)
1743 base_reg
= new_base
;
1745 if (mask
& (setmask
<< new_base
))
1747 first_error (_("invalid register list"));
1751 if ((mask
>> new_base
) != 0 && ! warned
)
1753 as_tsktsk (_("register list not in ascending order"));
1757 mask
|= setmask
<< new_base
;
1760 if (*str
== '-') /* We have the start of a range expression */
1766 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1769 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1773 if (high_range
>= max_regs
)
1775 first_error (_("register out of range in list"));
1779 if (regtype
== REG_TYPE_NQ
)
1780 high_range
= high_range
+ 1;
1782 if (high_range
<= new_base
)
1784 inst
.error
= _("register range not in ascending order");
1788 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1790 if (mask
& (setmask
<< new_base
))
1792 inst
.error
= _("invalid register list");
1796 mask
|= setmask
<< new_base
;
1801 while (skip_past_comma (&str
) != FAIL
);
1805 /* Sanity check -- should have raised a parse error above. */
1806 if (count
== 0 || count
> max_regs
)
1811 /* Final test -- the registers must be consecutive. */
1813 for (i
= 0; i
< count
; i
++)
1815 if ((mask
& (1u << i
)) == 0)
1817 inst
.error
= _("non-contiguous register range");
1827 /* True if two alias types are the same. */
1830 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1838 if (a
->defined
!= b
->defined
)
1841 if ((a
->defined
& NTA_HASTYPE
) != 0
1842 && (a
->eltype
.type
!= b
->eltype
.type
1843 || a
->eltype
.size
!= b
->eltype
.size
))
1846 if ((a
->defined
& NTA_HASINDEX
) != 0
1847 && (a
->index
!= b
->index
))
1853 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1854 The base register is put in *PBASE.
1855 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1857 The register stride (minus one) is put in bit 4 of the return value.
1858 Bits [6:5] encode the list length (minus one).
1859 The type of the list elements is put in *ELTYPE, if non-NULL. */
1861 #define NEON_LANE(X) ((X) & 0xf)
1862 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1863 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1866 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1867 struct neon_type_el
*eltype
)
1874 int leading_brace
= 0;
1875 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1877 const char *const incr_error
= _("register stride must be 1 or 2");
1878 const char *const type_error
= _("mismatched element/structure types in list");
1879 struct neon_typed_alias firsttype
;
1881 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1886 struct neon_typed_alias atype
;
1887 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1891 first_error (_(reg_expected_msgs
[rtype
]));
1898 if (rtype
== REG_TYPE_NQ
)
1905 else if (reg_incr
== -1)
1907 reg_incr
= getreg
- base_reg
;
1908 if (reg_incr
< 1 || reg_incr
> 2)
1910 first_error (_(incr_error
));
1914 else if (getreg
!= base_reg
+ reg_incr
* count
)
1916 first_error (_(incr_error
));
1920 if (! neon_alias_types_same (&atype
, &firsttype
))
1922 first_error (_(type_error
));
1926 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1930 struct neon_typed_alias htype
;
1931 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1933 lane
= NEON_INTERLEAVE_LANES
;
1934 else if (lane
!= NEON_INTERLEAVE_LANES
)
1936 first_error (_(type_error
));
1941 else if (reg_incr
!= 1)
1943 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1947 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1950 first_error (_(reg_expected_msgs
[rtype
]));
1953 if (! neon_alias_types_same (&htype
, &firsttype
))
1955 first_error (_(type_error
));
1958 count
+= hireg
+ dregs
- getreg
;
1962 /* If we're using Q registers, we can't use [] or [n] syntax. */
1963 if (rtype
== REG_TYPE_NQ
)
1969 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1973 else if (lane
!= atype
.index
)
1975 first_error (_(type_error
));
1979 else if (lane
== -1)
1980 lane
= NEON_INTERLEAVE_LANES
;
1981 else if (lane
!= NEON_INTERLEAVE_LANES
)
1983 first_error (_(type_error
));
1988 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1990 /* No lane set by [x]. We must be interleaving structures. */
1992 lane
= NEON_INTERLEAVE_LANES
;
1995 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1996 || (count
> 1 && reg_incr
== -1))
1998 first_error (_("error parsing element/structure list"));
2002 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2004 first_error (_("expected }"));
2012 *eltype
= firsttype
.eltype
;
2017 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2020 /* Parse an explicit relocation suffix on an expression. This is
2021 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2022 arm_reloc_hsh contains no entries, so this function can only
2023 succeed if there is no () after the word. Returns -1 on error,
2024 BFD_RELOC_UNUSED if there wasn't any suffix. */
2026 parse_reloc (char **str
)
2028 struct reloc_entry
*r
;
2032 return BFD_RELOC_UNUSED
;
2037 while (*q
&& *q
!= ')' && *q
!= ',')
2042 if ((r
= (struct reloc_entry
*)
2043 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2050 /* Directives: register aliases. */
2052 static struct reg_entry
*
2053 insert_reg_alias (char *str
, int number
, int type
)
2055 struct reg_entry
*new_reg
;
2058 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2060 if (new_reg
->builtin
)
2061 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2063 /* Only warn about a redefinition if it's not defined as the
2065 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2066 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2071 name
= xstrdup (str
);
2072 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2074 new_reg
->name
= name
;
2075 new_reg
->number
= number
;
2076 new_reg
->type
= type
;
2077 new_reg
->builtin
= FALSE
;
2078 new_reg
->neon
= NULL
;
2080 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2087 insert_neon_reg_alias (char *str
, int number
, int type
,
2088 struct neon_typed_alias
*atype
)
2090 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2094 first_error (_("attempt to redefine typed alias"));
2100 reg
->neon
= (struct neon_typed_alias
*)
2101 xmalloc (sizeof (struct neon_typed_alias
));
2102 *reg
->neon
= *atype
;
2106 /* Look for the .req directive. This is of the form:
2108 new_register_name .req existing_register_name
2110 If we find one, or if it looks sufficiently like one that we want to
2111 handle any error here, return TRUE. Otherwise return FALSE. */
2114 create_register_alias (char * newname
, char *p
)
2116 struct reg_entry
*old
;
2117 char *oldname
, *nbuf
;
2120 /* The input scrubber ensures that whitespace after the mnemonic is
2121 collapsed to single spaces. */
2123 if (strncmp (oldname
, " .req ", 6) != 0)
2127 if (*oldname
== '\0')
2130 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2133 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2137 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2138 the desired alias name, and p points to its end. If not, then
2139 the desired alias name is in the global original_case_string. */
2140 #ifdef TC_CASE_SENSITIVE
2143 newname
= original_case_string
;
2144 nlen
= strlen (newname
);
2147 nbuf
= (char *) alloca (nlen
+ 1);
2148 memcpy (nbuf
, newname
, nlen
);
2151 /* Create aliases under the new name as stated; an all-lowercase
2152 version of the new name; and an all-uppercase version of the new
2154 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2156 for (p
= nbuf
; *p
; p
++)
2159 if (strncmp (nbuf
, newname
, nlen
))
2161 /* If this attempt to create an additional alias fails, do not bother
2162 trying to create the all-lower case alias. We will fail and issue
2163 a second, duplicate error message. This situation arises when the
2164 programmer does something like:
2167 The second .req creates the "Foo" alias but then fails to create
2168 the artificial FOO alias because it has already been created by the
2170 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2174 for (p
= nbuf
; *p
; p
++)
2177 if (strncmp (nbuf
, newname
, nlen
))
2178 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2184 /* Create a Neon typed/indexed register alias using directives, e.g.:
2189 These typed registers can be used instead of the types specified after the
2190 Neon mnemonic, so long as all operands given have types. Types can also be
2191 specified directly, e.g.:
2192 vadd d0.s32, d1.s32, d2.s32 */
2195 create_neon_reg_alias (char *newname
, char *p
)
2197 enum arm_reg_type basetype
;
2198 struct reg_entry
*basereg
;
2199 struct reg_entry mybasereg
;
2200 struct neon_type ntype
;
2201 struct neon_typed_alias typeinfo
;
2202 char *namebuf
, *nameend
;
2205 typeinfo
.defined
= 0;
2206 typeinfo
.eltype
.type
= NT_invtype
;
2207 typeinfo
.eltype
.size
= -1;
2208 typeinfo
.index
= -1;
2212 if (strncmp (p
, " .dn ", 5) == 0)
2213 basetype
= REG_TYPE_VFD
;
2214 else if (strncmp (p
, " .qn ", 5) == 0)
2215 basetype
= REG_TYPE_NQ
;
2224 basereg
= arm_reg_parse_multi (&p
);
2226 if (basereg
&& basereg
->type
!= basetype
)
2228 as_bad (_("bad type for register"));
2232 if (basereg
== NULL
)
2235 /* Try parsing as an integer. */
2236 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2237 if (exp
.X_op
!= O_constant
)
2239 as_bad (_("expression must be constant"));
2242 basereg
= &mybasereg
;
2243 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2249 typeinfo
= *basereg
->neon
;
2251 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2253 /* We got a type. */
2254 if (typeinfo
.defined
& NTA_HASTYPE
)
2256 as_bad (_("can't redefine the type of a register alias"));
2260 typeinfo
.defined
|= NTA_HASTYPE
;
2261 if (ntype
.elems
!= 1)
2263 as_bad (_("you must specify a single type only"));
2266 typeinfo
.eltype
= ntype
.el
[0];
2269 if (skip_past_char (&p
, '[') == SUCCESS
)
2272 /* We got a scalar index. */
2274 if (typeinfo
.defined
& NTA_HASINDEX
)
2276 as_bad (_("can't redefine the index of a scalar alias"));
2280 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2282 if (exp
.X_op
!= O_constant
)
2284 as_bad (_("scalar index must be constant"));
2288 typeinfo
.defined
|= NTA_HASINDEX
;
2289 typeinfo
.index
= exp
.X_add_number
;
2291 if (skip_past_char (&p
, ']') == FAIL
)
2293 as_bad (_("expecting ]"));
2298 namelen
= nameend
- newname
;
2299 namebuf
= (char *) alloca (namelen
+ 1);
2300 strncpy (namebuf
, newname
, namelen
);
2301 namebuf
[namelen
] = '\0';
2303 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2304 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2306 /* Insert name in all uppercase. */
2307 for (p
= namebuf
; *p
; p
++)
2310 if (strncmp (namebuf
, newname
, namelen
))
2311 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2312 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2314 /* Insert name in all lowercase. */
2315 for (p
= namebuf
; *p
; p
++)
2318 if (strncmp (namebuf
, newname
, namelen
))
2319 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2320 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2325 /* Should never be called, as .req goes between the alias and the
2326 register name, not at the beginning of the line. */
2329 s_req (int a ATTRIBUTE_UNUSED
)
2331 as_bad (_("invalid syntax for .req directive"));
2335 s_dn (int a ATTRIBUTE_UNUSED
)
2337 as_bad (_("invalid syntax for .dn directive"));
2341 s_qn (int a ATTRIBUTE_UNUSED
)
2343 as_bad (_("invalid syntax for .qn directive"));
2346 /* The .unreq directive deletes an alias which was previously defined
2347 by .req. For example:
2353 s_unreq (int a ATTRIBUTE_UNUSED
)
2358 name
= input_line_pointer
;
2360 while (*input_line_pointer
!= 0
2361 && *input_line_pointer
!= ' '
2362 && *input_line_pointer
!= '\n')
2363 ++input_line_pointer
;
2365 saved_char
= *input_line_pointer
;
2366 *input_line_pointer
= 0;
2369 as_bad (_("invalid syntax for .unreq directive"));
2372 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2376 as_bad (_("unknown register alias '%s'"), name
);
2377 else if (reg
->builtin
)
2378 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2385 hash_delete (arm_reg_hsh
, name
, FALSE
);
2386 free ((char *) reg
->name
);
2391 /* Also locate the all upper case and all lower case versions.
2392 Do not complain if we cannot find one or the other as it
2393 was probably deleted above. */
2395 nbuf
= strdup (name
);
2396 for (p
= nbuf
; *p
; p
++)
2398 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2401 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2402 free ((char *) reg
->name
);
2408 for (p
= nbuf
; *p
; p
++)
2410 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2413 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2414 free ((char *) reg
->name
);
2424 *input_line_pointer
= saved_char
;
2425 demand_empty_rest_of_line ();
2428 /* Directives: Instruction set selection. */
2431 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2432 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2433 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2434 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2436 /* Create a new mapping symbol for the transition to STATE. */
2439 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2442 const char * symname
;
2449 type
= BSF_NO_FLAGS
;
2453 type
= BSF_NO_FLAGS
;
2457 type
= BSF_NO_FLAGS
;
2463 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2464 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2469 THUMB_SET_FUNC (symbolP
, 0);
2470 ARM_SET_THUMB (symbolP
, 0);
2471 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2475 THUMB_SET_FUNC (symbolP
, 1);
2476 ARM_SET_THUMB (symbolP
, 1);
2477 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2485 /* Save the mapping symbols for future reference. Also check that
2486 we do not place two mapping symbols at the same offset within a
2487 frag. We'll handle overlap between frags in
2488 check_mapping_symbols. */
2491 know (frag
->tc_frag_data
.first_map
== NULL
);
2492 frag
->tc_frag_data
.first_map
= symbolP
;
2494 if (frag
->tc_frag_data
.last_map
!= NULL
)
2495 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) < S_GET_VALUE (symbolP
));
2496 frag
->tc_frag_data
.last_map
= symbolP
;
2499 /* We must sometimes convert a region marked as code to data during
2500 code alignment, if an odd number of bytes have to be padded. The
2501 code mapping symbol is pushed to an aligned address. */
2504 insert_data_mapping_symbol (enum mstate state
,
2505 valueT value
, fragS
*frag
, offsetT bytes
)
2507 /* If there was already a mapping symbol, remove it. */
2508 if (frag
->tc_frag_data
.last_map
!= NULL
2509 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2511 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2515 know (frag
->tc_frag_data
.first_map
== symp
);
2516 frag
->tc_frag_data
.first_map
= NULL
;
2518 frag
->tc_frag_data
.last_map
= NULL
;
2519 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2522 make_mapping_symbol (MAP_DATA
, value
, frag
);
2523 make_mapping_symbol (state
, value
+ bytes
, frag
);
2526 static void mapping_state_2 (enum mstate state
, int max_chars
);
2528 /* Set the mapping state to STATE. Only call this when about to
2529 emit some STATE bytes to the file. */
2532 mapping_state (enum mstate state
)
2534 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2536 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2538 if (mapstate
== state
)
2539 /* The mapping symbol has already been emitted.
2540 There is nothing else to do. */
2542 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2543 /* This case will be evaluated later in the next else. */
2545 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2546 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2548 /* Only add the symbol if the offset is > 0:
2549 if we're at the first frag, check it's size > 0;
2550 if we're not at the first frag, then for sure
2551 the offset is > 0. */
2552 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2553 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2556 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2559 mapping_state_2 (state
, 0);
2563 /* Same as mapping_state, but MAX_CHARS bytes have already been
2564 allocated. Put the mapping symbol that far back. */
2567 mapping_state_2 (enum mstate state
, int max_chars
)
2569 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2571 if (!SEG_NORMAL (now_seg
))
2574 if (mapstate
== state
)
2575 /* The mapping symbol has already been emitted.
2576 There is nothing else to do. */
2579 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2580 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2583 #define mapping_state(x) ((void)0)
2584 #define mapping_state_2(x, y) ((void)0)
2587 /* Find the real, Thumb encoded start of a Thumb function. */
2591 find_real_start (symbolS
* symbolP
)
2594 const char * name
= S_GET_NAME (symbolP
);
2595 symbolS
* new_target
;
2597 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2598 #define STUB_NAME ".real_start_of"
2603 /* The compiler may generate BL instructions to local labels because
2604 it needs to perform a branch to a far away location. These labels
2605 do not have a corresponding ".real_start_of" label. We check
2606 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2607 the ".real_start_of" convention for nonlocal branches. */
2608 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2611 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2612 new_target
= symbol_find (real_start
);
2614 if (new_target
== NULL
)
2616 as_warn (_("Failed to find real start of function: %s\n"), name
);
2617 new_target
= symbolP
;
2625 opcode_select (int width
)
2632 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2633 as_bad (_("selected processor does not support THUMB opcodes"));
2636 /* No need to force the alignment, since we will have been
2637 coming from ARM mode, which is word-aligned. */
2638 record_alignment (now_seg
, 1);
2645 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2646 as_bad (_("selected processor does not support ARM opcodes"));
2651 frag_align (2, 0, 0);
2653 record_alignment (now_seg
, 1);
2658 as_bad (_("invalid instruction size selected (%d)"), width
);
2663 s_arm (int ignore ATTRIBUTE_UNUSED
)
2666 demand_empty_rest_of_line ();
2670 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2673 demand_empty_rest_of_line ();
2677 s_code (int unused ATTRIBUTE_UNUSED
)
2681 temp
= get_absolute_expression ();
2686 opcode_select (temp
);
2690 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2695 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2697 /* If we are not already in thumb mode go into it, EVEN if
2698 the target processor does not support thumb instructions.
2699 This is used by gcc/config/arm/lib1funcs.asm for example
2700 to compile interworking support functions even if the
2701 target processor should not support interworking. */
2705 record_alignment (now_seg
, 1);
2708 demand_empty_rest_of_line ();
2712 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2716 /* The following label is the name/address of the start of a Thumb function.
2717 We need to know this for the interworking support. */
2718 label_is_thumb_function_name
= TRUE
;
2721 /* Perform a .set directive, but also mark the alias as
2722 being a thumb function. */
2725 s_thumb_set (int equiv
)
2727 /* XXX the following is a duplicate of the code for s_set() in read.c
2728 We cannot just call that code as we need to get at the symbol that
2735 /* Especial apologies for the random logic:
2736 This just grew, and could be parsed much more simply!
2738 name
= input_line_pointer
;
2739 delim
= get_symbol_end ();
2740 end_name
= input_line_pointer
;
2743 if (*input_line_pointer
!= ',')
2746 as_bad (_("expected comma after name \"%s\""), name
);
2748 ignore_rest_of_line ();
2752 input_line_pointer
++;
2755 if (name
[0] == '.' && name
[1] == '\0')
2757 /* XXX - this should not happen to .thumb_set. */
2761 if ((symbolP
= symbol_find (name
)) == NULL
2762 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2765 /* When doing symbol listings, play games with dummy fragments living
2766 outside the normal fragment chain to record the file and line info
2768 if (listing
& LISTING_SYMBOLS
)
2770 extern struct list_info_struct
* listing_tail
;
2771 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2773 memset (dummy_frag
, 0, sizeof (fragS
));
2774 dummy_frag
->fr_type
= rs_fill
;
2775 dummy_frag
->line
= listing_tail
;
2776 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2777 dummy_frag
->fr_symbol
= symbolP
;
2781 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2784 /* "set" symbols are local unless otherwise specified. */
2785 SF_SET_LOCAL (symbolP
);
2786 #endif /* OBJ_COFF */
2787 } /* Make a new symbol. */
2789 symbol_table_insert (symbolP
);
2794 && S_IS_DEFINED (symbolP
)
2795 && S_GET_SEGMENT (symbolP
) != reg_section
)
2796 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2798 pseudo_set (symbolP
);
2800 demand_empty_rest_of_line ();
2802 /* XXX Now we come to the Thumb specific bit of code. */
2804 THUMB_SET_FUNC (symbolP
, 1);
2805 ARM_SET_THUMB (symbolP
, 1);
2806 #if defined OBJ_ELF || defined OBJ_COFF
2807 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2811 /* Directives: Mode selection. */
2813 /* .syntax [unified|divided] - choose the new unified syntax
2814 (same for Arm and Thumb encoding, modulo slight differences in what
2815 can be represented) or the old divergent syntax for each mode. */
2817 s_syntax (int unused ATTRIBUTE_UNUSED
)
2821 name
= input_line_pointer
;
2822 delim
= get_symbol_end ();
2824 if (!strcasecmp (name
, "unified"))
2825 unified_syntax
= TRUE
;
2826 else if (!strcasecmp (name
, "divided"))
2827 unified_syntax
= FALSE
;
2830 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2833 *input_line_pointer
= delim
;
2834 demand_empty_rest_of_line ();
2837 /* Directives: sectioning and alignment. */
2839 /* Same as s_align_ptwo but align 0 => align 2. */
2842 s_align (int unused ATTRIBUTE_UNUSED
)
2847 long max_alignment
= 15;
2849 temp
= get_absolute_expression ();
2850 if (temp
> max_alignment
)
2851 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2854 as_bad (_("alignment negative. 0 assumed."));
2858 if (*input_line_pointer
== ',')
2860 input_line_pointer
++;
2861 temp_fill
= get_absolute_expression ();
2873 /* Only make a frag if we HAVE to. */
2874 if (temp
&& !need_pass_2
)
2876 if (!fill_p
&& subseg_text_p (now_seg
))
2877 frag_align_code (temp
, 0);
2879 frag_align (temp
, (int) temp_fill
, 0);
2881 demand_empty_rest_of_line ();
2883 record_alignment (now_seg
, temp
);
2887 s_bss (int ignore ATTRIBUTE_UNUSED
)
2889 /* We don't support putting frags in the BSS segment, we fake it by
2890 marking in_bss, then looking at s_skip for clues. */
2891 subseg_set (bss_section
, 0);
2892 demand_empty_rest_of_line ();
2894 #ifdef md_elf_section_change_hook
2895 md_elf_section_change_hook ();
2900 s_even (int ignore ATTRIBUTE_UNUSED
)
2902 /* Never make frag if expect extra pass. */
2904 frag_align (1, 0, 0);
2906 record_alignment (now_seg
, 1);
2908 demand_empty_rest_of_line ();
2911 /* Directives: Literal pools. */
2913 static literal_pool
*
2914 find_literal_pool (void)
2916 literal_pool
* pool
;
2918 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2920 if (pool
->section
== now_seg
2921 && pool
->sub_section
== now_subseg
)
2928 static literal_pool
*
2929 find_or_make_literal_pool (void)
2931 /* Next literal pool ID number. */
2932 static unsigned int latest_pool_num
= 1;
2933 literal_pool
* pool
;
2935 pool
= find_literal_pool ();
2939 /* Create a new pool. */
2940 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2944 pool
->next_free_entry
= 0;
2945 pool
->section
= now_seg
;
2946 pool
->sub_section
= now_subseg
;
2947 pool
->next
= list_of_pools
;
2948 pool
->symbol
= NULL
;
2950 /* Add it to the list. */
2951 list_of_pools
= pool
;
2954 /* New pools, and emptied pools, will have a NULL symbol. */
2955 if (pool
->symbol
== NULL
)
2957 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2958 (valueT
) 0, &zero_address_frag
);
2959 pool
->id
= latest_pool_num
++;
2966 /* Add the literal in the global 'inst'
2967 structure to the relevant literal pool. */
2970 add_to_lit_pool (void)
2972 literal_pool
* pool
;
2975 pool
= find_or_make_literal_pool ();
2977 /* Check if this literal value is already in the pool. */
2978 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2980 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2981 && (inst
.reloc
.exp
.X_op
== O_constant
)
2982 && (pool
->literals
[entry
].X_add_number
2983 == inst
.reloc
.exp
.X_add_number
)
2984 && (pool
->literals
[entry
].X_unsigned
2985 == inst
.reloc
.exp
.X_unsigned
))
2988 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2989 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2990 && (pool
->literals
[entry
].X_add_number
2991 == inst
.reloc
.exp
.X_add_number
)
2992 && (pool
->literals
[entry
].X_add_symbol
2993 == inst
.reloc
.exp
.X_add_symbol
)
2994 && (pool
->literals
[entry
].X_op_symbol
2995 == inst
.reloc
.exp
.X_op_symbol
))
2999 /* Do we need to create a new entry? */
3000 if (entry
== pool
->next_free_entry
)
3002 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3004 inst
.error
= _("literal pool overflow");
3008 pool
->literals
[entry
] = inst
.reloc
.exp
;
3009 pool
->next_free_entry
+= 1;
3012 inst
.reloc
.exp
.X_op
= O_symbol
;
3013 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3014 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3019 /* Can't use symbol_new here, so have to create a symbol and then at
3020 a later date assign it a value. Thats what these functions do. */
3023 symbol_locate (symbolS
* symbolP
,
3024 const char * name
, /* It is copied, the caller can modify. */
3025 segT segment
, /* Segment identifier (SEG_<something>). */
3026 valueT valu
, /* Symbol value. */
3027 fragS
* frag
) /* Associated fragment. */
3029 unsigned int name_length
;
3030 char * preserved_copy_of_name
;
3032 name_length
= strlen (name
) + 1; /* +1 for \0. */
3033 obstack_grow (¬es
, name
, name_length
);
3034 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3036 #ifdef tc_canonicalize_symbol_name
3037 preserved_copy_of_name
=
3038 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3041 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3043 S_SET_SEGMENT (symbolP
, segment
);
3044 S_SET_VALUE (symbolP
, valu
);
3045 symbol_clear_list_pointers (symbolP
);
3047 symbol_set_frag (symbolP
, frag
);
3049 /* Link to end of symbol chain. */
3051 extern int symbol_table_frozen
;
3053 if (symbol_table_frozen
)
3057 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3059 obj_symbol_new_hook (symbolP
);
3061 #ifdef tc_symbol_new_hook
3062 tc_symbol_new_hook (symbolP
);
3066 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3067 #endif /* DEBUG_SYMS */
3072 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3075 literal_pool
* pool
;
3078 pool
= find_literal_pool ();
3080 || pool
->symbol
== NULL
3081 || pool
->next_free_entry
== 0)
3084 mapping_state (MAP_DATA
);
3086 /* Align pool as you have word accesses.
3087 Only make a frag if we have to. */
3089 frag_align (2, 0, 0);
3091 record_alignment (now_seg
, 2);
3093 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3095 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3096 (valueT
) frag_now_fix (), frag_now
);
3097 symbol_table_insert (pool
->symbol
);
3099 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3101 #if defined OBJ_COFF || defined OBJ_ELF
3102 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3105 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3106 /* First output the expression in the instruction to the pool. */
3107 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3109 /* Mark the pool as empty. */
3110 pool
->next_free_entry
= 0;
3111 pool
->symbol
= NULL
;
3115 /* Forward declarations for functions below, in the MD interface
3117 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3118 static valueT
create_unwind_entry (int);
3119 static void start_unwind_section (const segT
, int);
3120 static void add_unwind_opcode (valueT
, int);
3121 static void flush_pending_unwind (void);
3123 /* Directives: Data. */
3126 s_arm_elf_cons (int nbytes
)
3130 #ifdef md_flush_pending_output
3131 md_flush_pending_output ();
3134 if (is_it_end_of_statement ())
3136 demand_empty_rest_of_line ();
3140 #ifdef md_cons_align
3141 md_cons_align (nbytes
);
3144 mapping_state (MAP_DATA
);
3148 char *base
= input_line_pointer
;
3152 if (exp
.X_op
!= O_symbol
)
3153 emit_expr (&exp
, (unsigned int) nbytes
);
3156 char *before_reloc
= input_line_pointer
;
3157 reloc
= parse_reloc (&input_line_pointer
);
3160 as_bad (_("unrecognized relocation suffix"));
3161 ignore_rest_of_line ();
3164 else if (reloc
== BFD_RELOC_UNUSED
)
3165 emit_expr (&exp
, (unsigned int) nbytes
);
3168 reloc_howto_type
*howto
= (reloc_howto_type
*)
3169 bfd_reloc_type_lookup (stdoutput
,
3170 (bfd_reloc_code_real_type
) reloc
);
3171 int size
= bfd_get_reloc_size (howto
);
3173 if (reloc
== BFD_RELOC_ARM_PLT32
)
3175 as_bad (_("(plt) is only valid on branch targets"));
3176 reloc
= BFD_RELOC_UNUSED
;
3181 as_bad (_("%s relocations do not fit in %d bytes"),
3182 howto
->name
, nbytes
);
3185 /* We've parsed an expression stopping at O_symbol.
3186 But there may be more expression left now that we
3187 have parsed the relocation marker. Parse it again.
3188 XXX Surely there is a cleaner way to do this. */
3189 char *p
= input_line_pointer
;
3191 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3192 memcpy (save_buf
, base
, input_line_pointer
- base
);
3193 memmove (base
+ (input_line_pointer
- before_reloc
),
3194 base
, before_reloc
- base
);
3196 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3198 memcpy (base
, save_buf
, p
- base
);
3200 offset
= nbytes
- size
;
3201 p
= frag_more ((int) nbytes
);
3202 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3203 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3208 while (*input_line_pointer
++ == ',');
3210 /* Put terminator back into stream. */
3211 input_line_pointer
--;
3212 demand_empty_rest_of_line ();
3215 /* Emit an expression containing a 32-bit thumb instruction.
3216 Implementation based on put_thumb32_insn. */
3219 emit_thumb32_expr (expressionS
* exp
)
3221 expressionS exp_high
= *exp
;
3223 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3224 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3225 exp
->X_add_number
&= 0xffff;
3226 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3229 /* Guess the instruction size based on the opcode. */
3232 thumb_insn_size (int opcode
)
3234 if ((unsigned int) opcode
< 0xe800u
)
3236 else if ((unsigned int) opcode
>= 0xe8000000u
)
3243 emit_insn (expressionS
*exp
, int nbytes
)
3247 if (exp
->X_op
== O_constant
)
3252 size
= thumb_insn_size (exp
->X_add_number
);
3256 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3258 as_bad (_(".inst.n operand too big. "\
3259 "Use .inst.w instead"));
3264 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3265 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3267 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3269 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3270 emit_thumb32_expr (exp
);
3272 emit_expr (exp
, (unsigned int) size
);
3274 it_fsm_post_encode ();
3278 as_bad (_("cannot determine Thumb instruction size. " \
3279 "Use .inst.n/.inst.w instead"));
3282 as_bad (_("constant expression required"));
3287 /* Like s_arm_elf_cons but do not use md_cons_align and
3288 set the mapping state to MAP_ARM/MAP_THUMB. */
3291 s_arm_elf_inst (int nbytes
)
3293 if (is_it_end_of_statement ())
3295 demand_empty_rest_of_line ();
3299 /* Calling mapping_state () here will not change ARM/THUMB,
3300 but will ensure not to be in DATA state. */
3303 mapping_state (MAP_THUMB
);
3308 as_bad (_("width suffixes are invalid in ARM mode"));
3309 ignore_rest_of_line ();
3315 mapping_state (MAP_ARM
);
3324 if (! emit_insn (& exp
, nbytes
))
3326 ignore_rest_of_line ();
3330 while (*input_line_pointer
++ == ',');
3332 /* Put terminator back into stream. */
3333 input_line_pointer
--;
3334 demand_empty_rest_of_line ();
3337 /* Parse a .rel31 directive. */
3340 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3347 if (*input_line_pointer
== '1')
3348 highbit
= 0x80000000;
3349 else if (*input_line_pointer
!= '0')
3350 as_bad (_("expected 0 or 1"));
3352 input_line_pointer
++;
3353 if (*input_line_pointer
!= ',')
3354 as_bad (_("missing comma"));
3355 input_line_pointer
++;
3357 #ifdef md_flush_pending_output
3358 md_flush_pending_output ();
3361 #ifdef md_cons_align
3365 mapping_state (MAP_DATA
);
3370 md_number_to_chars (p
, highbit
, 4);
3371 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3372 BFD_RELOC_ARM_PREL31
);
3374 demand_empty_rest_of_line ();
3377 /* Directives: AEABI stack-unwind tables. */
3379 /* Parse an unwind_fnstart directive. Simply records the current location. */
3382 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3384 demand_empty_rest_of_line ();
3385 if (unwind
.proc_start
)
3387 as_bad (_("duplicate .fnstart directive"));
3391 /* Mark the start of the function. */
3392 unwind
.proc_start
= expr_build_dot ();
3394 /* Reset the rest of the unwind info. */
3395 unwind
.opcode_count
= 0;
3396 unwind
.table_entry
= NULL
;
3397 unwind
.personality_routine
= NULL
;
3398 unwind
.personality_index
= -1;
3399 unwind
.frame_size
= 0;
3400 unwind
.fp_offset
= 0;
3401 unwind
.fp_reg
= REG_SP
;
3403 unwind
.sp_restored
= 0;
3407 /* Parse a handlerdata directive. Creates the exception handling table entry
3408 for the function. */
3411 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3413 demand_empty_rest_of_line ();
3414 if (!unwind
.proc_start
)
3415 as_bad (MISSING_FNSTART
);
3417 if (unwind
.table_entry
)
3418 as_bad (_("duplicate .handlerdata directive"));
3420 create_unwind_entry (1);
3423 /* Parse an unwind_fnend directive. Generates the index table entry. */
3426 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3431 unsigned int marked_pr_dependency
;
3433 demand_empty_rest_of_line ();
3435 if (!unwind
.proc_start
)
3437 as_bad (_(".fnend directive without .fnstart"));
3441 /* Add eh table entry. */
3442 if (unwind
.table_entry
== NULL
)
3443 val
= create_unwind_entry (0);
3447 /* Add index table entry. This is two words. */
3448 start_unwind_section (unwind
.saved_seg
, 1);
3449 frag_align (2, 0, 0);
3450 record_alignment (now_seg
, 2);
3452 ptr
= frag_more (8);
3453 where
= frag_now_fix () - 8;
3455 /* Self relative offset of the function start. */
3456 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3457 BFD_RELOC_ARM_PREL31
);
3459 /* Indicate dependency on EHABI-defined personality routines to the
3460 linker, if it hasn't been done already. */
3461 marked_pr_dependency
3462 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3463 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3464 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3466 static const char *const name
[] =
3468 "__aeabi_unwind_cpp_pr0",
3469 "__aeabi_unwind_cpp_pr1",
3470 "__aeabi_unwind_cpp_pr2"
3472 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3473 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3474 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3475 |= 1 << unwind
.personality_index
;
3479 /* Inline exception table entry. */
3480 md_number_to_chars (ptr
+ 4, val
, 4);
3482 /* Self relative offset of the table entry. */
3483 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3484 BFD_RELOC_ARM_PREL31
);
3486 /* Restore the original section. */
3487 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3489 unwind
.proc_start
= NULL
;
3493 /* Parse an unwind_cantunwind directive. */
3496 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3498 demand_empty_rest_of_line ();
3499 if (!unwind
.proc_start
)
3500 as_bad (MISSING_FNSTART
);
3502 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3503 as_bad (_("personality routine specified for cantunwind frame"));
3505 unwind
.personality_index
= -2;
3509 /* Parse a personalityindex directive. */
3512 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3516 if (!unwind
.proc_start
)
3517 as_bad (MISSING_FNSTART
);
3519 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3520 as_bad (_("duplicate .personalityindex directive"));
3524 if (exp
.X_op
!= O_constant
3525 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3527 as_bad (_("bad personality routine number"));
3528 ignore_rest_of_line ();
3532 unwind
.personality_index
= exp
.X_add_number
;
3534 demand_empty_rest_of_line ();
3538 /* Parse a personality directive. */
3541 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3545 if (!unwind
.proc_start
)
3546 as_bad (MISSING_FNSTART
);
3548 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3549 as_bad (_("duplicate .personality directive"));
3551 name
= input_line_pointer
;
3552 c
= get_symbol_end ();
3553 p
= input_line_pointer
;
3554 unwind
.personality_routine
= symbol_find_or_make (name
);
3556 demand_empty_rest_of_line ();
3560 /* Parse a directive saving core registers. */
3563 s_arm_unwind_save_core (void)
3569 range
= parse_reg_list (&input_line_pointer
);
3572 as_bad (_("expected register list"));
3573 ignore_rest_of_line ();
3577 demand_empty_rest_of_line ();
3579 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3580 into .unwind_save {..., sp...}. We aren't bothered about the value of
3581 ip because it is clobbered by calls. */
3582 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3583 && (range
& 0x3000) == 0x1000)
3585 unwind
.opcode_count
--;
3586 unwind
.sp_restored
= 0;
3587 range
= (range
| 0x2000) & ~0x1000;
3588 unwind
.pending_offset
= 0;
3594 /* See if we can use the short opcodes. These pop a block of up to 8
3595 registers starting with r4, plus maybe r14. */
3596 for (n
= 0; n
< 8; n
++)
3598 /* Break at the first non-saved register. */
3599 if ((range
& (1 << (n
+ 4))) == 0)
3602 /* See if there are any other bits set. */
3603 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3605 /* Use the long form. */
3606 op
= 0x8000 | ((range
>> 4) & 0xfff);
3607 add_unwind_opcode (op
, 2);
3611 /* Use the short form. */
3613 op
= 0xa8; /* Pop r14. */
3615 op
= 0xa0; /* Do not pop r14. */
3617 add_unwind_opcode (op
, 1);
3624 op
= 0xb100 | (range
& 0xf);
3625 add_unwind_opcode (op
, 2);
3628 /* Record the number of bytes pushed. */
3629 for (n
= 0; n
< 16; n
++)
3631 if (range
& (1 << n
))
3632 unwind
.frame_size
+= 4;
3637 /* Parse a directive saving FPA registers. */
3640 s_arm_unwind_save_fpa (int reg
)
3646 /* Get Number of registers to transfer. */
3647 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3650 exp
.X_op
= O_illegal
;
3652 if (exp
.X_op
!= O_constant
)
3654 as_bad (_("expected , <constant>"));
3655 ignore_rest_of_line ();
3659 num_regs
= exp
.X_add_number
;
3661 if (num_regs
< 1 || num_regs
> 4)
3663 as_bad (_("number of registers must be in the range [1:4]"));
3664 ignore_rest_of_line ();
3668 demand_empty_rest_of_line ();
3673 op
= 0xb4 | (num_regs
- 1);
3674 add_unwind_opcode (op
, 1);
3679 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3680 add_unwind_opcode (op
, 2);
3682 unwind
.frame_size
+= num_regs
* 12;
3686 /* Parse a directive saving VFP registers for ARMv6 and above. */
3689 s_arm_unwind_save_vfp_armv6 (void)
3694 int num_vfpv3_regs
= 0;
3695 int num_regs_below_16
;
3697 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3700 as_bad (_("expected register list"));
3701 ignore_rest_of_line ();
3705 demand_empty_rest_of_line ();
3707 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3708 than FSTMX/FLDMX-style ones). */
3710 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3712 num_vfpv3_regs
= count
;
3713 else if (start
+ count
> 16)
3714 num_vfpv3_regs
= start
+ count
- 16;
3716 if (num_vfpv3_regs
> 0)
3718 int start_offset
= start
> 16 ? start
- 16 : 0;
3719 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3720 add_unwind_opcode (op
, 2);
3723 /* Generate opcode for registers numbered in the range 0 .. 15. */
3724 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3725 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3726 if (num_regs_below_16
> 0)
3728 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3729 add_unwind_opcode (op
, 2);
3732 unwind
.frame_size
+= count
* 8;
3736 /* Parse a directive saving VFP registers for pre-ARMv6. */
3739 s_arm_unwind_save_vfp (void)
3745 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3748 as_bad (_("expected register list"));
3749 ignore_rest_of_line ();
3753 demand_empty_rest_of_line ();
3758 op
= 0xb8 | (count
- 1);
3759 add_unwind_opcode (op
, 1);
3764 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3765 add_unwind_opcode (op
, 2);
3767 unwind
.frame_size
+= count
* 8 + 4;
3771 /* Parse a directive saving iWMMXt data registers. */
3774 s_arm_unwind_save_mmxwr (void)
3782 if (*input_line_pointer
== '{')
3783 input_line_pointer
++;
3787 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3791 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3796 as_tsktsk (_("register list not in ascending order"));
3799 if (*input_line_pointer
== '-')
3801 input_line_pointer
++;
3802 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3805 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3808 else if (reg
>= hi_reg
)
3810 as_bad (_("bad register range"));
3813 for (; reg
< hi_reg
; reg
++)
3817 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3819 if (*input_line_pointer
== '}')
3820 input_line_pointer
++;
3822 demand_empty_rest_of_line ();
3824 /* Generate any deferred opcodes because we're going to be looking at
3826 flush_pending_unwind ();
3828 for (i
= 0; i
< 16; i
++)
3830 if (mask
& (1 << i
))
3831 unwind
.frame_size
+= 8;
3834 /* Attempt to combine with a previous opcode. We do this because gcc
3835 likes to output separate unwind directives for a single block of
3837 if (unwind
.opcode_count
> 0)
3839 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3840 if ((i
& 0xf8) == 0xc0)
3843 /* Only merge if the blocks are contiguous. */
3846 if ((mask
& 0xfe00) == (1 << 9))
3848 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3849 unwind
.opcode_count
--;
3852 else if (i
== 6 && unwind
.opcode_count
>= 2)
3854 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3858 op
= 0xffff << (reg
- 1);
3860 && ((mask
& op
) == (1u << (reg
- 1))))
3862 op
= (1 << (reg
+ i
+ 1)) - 1;
3863 op
&= ~((1 << reg
) - 1);
3865 unwind
.opcode_count
-= 2;
3872 /* We want to generate opcodes in the order the registers have been
3873 saved, ie. descending order. */
3874 for (reg
= 15; reg
>= -1; reg
--)
3876 /* Save registers in blocks. */
3878 || !(mask
& (1 << reg
)))
3880 /* We found an unsaved reg. Generate opcodes to save the
3887 op
= 0xc0 | (hi_reg
- 10);
3888 add_unwind_opcode (op
, 1);
3893 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3894 add_unwind_opcode (op
, 2);
3903 ignore_rest_of_line ();
3907 s_arm_unwind_save_mmxwcg (void)
3914 if (*input_line_pointer
== '{')
3915 input_line_pointer
++;
3919 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3923 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3929 as_tsktsk (_("register list not in ascending order"));
3932 if (*input_line_pointer
== '-')
3934 input_line_pointer
++;
3935 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3938 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3941 else if (reg
>= hi_reg
)
3943 as_bad (_("bad register range"));
3946 for (; reg
< hi_reg
; reg
++)
3950 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3952 if (*input_line_pointer
== '}')
3953 input_line_pointer
++;
3955 demand_empty_rest_of_line ();
3957 /* Generate any deferred opcodes because we're going to be looking at
3959 flush_pending_unwind ();
3961 for (reg
= 0; reg
< 16; reg
++)
3963 if (mask
& (1 << reg
))
3964 unwind
.frame_size
+= 4;
3967 add_unwind_opcode (op
, 2);
3970 ignore_rest_of_line ();
3974 /* Parse an unwind_save directive.
3975 If the argument is non-zero, this is a .vsave directive. */
3978 s_arm_unwind_save (int arch_v6
)
3981 struct reg_entry
*reg
;
3982 bfd_boolean had_brace
= FALSE
;
3984 if (!unwind
.proc_start
)
3985 as_bad (MISSING_FNSTART
);
3987 /* Figure out what sort of save we have. */
3988 peek
= input_line_pointer
;
3996 reg
= arm_reg_parse_multi (&peek
);
4000 as_bad (_("register expected"));
4001 ignore_rest_of_line ();
4010 as_bad (_("FPA .unwind_save does not take a register list"));
4011 ignore_rest_of_line ();
4014 input_line_pointer
= peek
;
4015 s_arm_unwind_save_fpa (reg
->number
);
4018 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4021 s_arm_unwind_save_vfp_armv6 ();
4023 s_arm_unwind_save_vfp ();
4025 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4026 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4029 as_bad (_(".unwind_save does not support this kind of register"));
4030 ignore_rest_of_line ();
4035 /* Parse an unwind_movsp directive. */
4038 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4044 if (!unwind
.proc_start
)
4045 as_bad (MISSING_FNSTART
);
4047 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4050 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4051 ignore_rest_of_line ();
4055 /* Optional constant. */
4056 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4058 if (immediate_for_directive (&offset
) == FAIL
)
4064 demand_empty_rest_of_line ();
4066 if (reg
== REG_SP
|| reg
== REG_PC
)
4068 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4072 if (unwind
.fp_reg
!= REG_SP
)
4073 as_bad (_("unexpected .unwind_movsp directive"));
4075 /* Generate opcode to restore the value. */
4077 add_unwind_opcode (op
, 1);
4079 /* Record the information for later. */
4080 unwind
.fp_reg
= reg
;
4081 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4082 unwind
.sp_restored
= 1;
4085 /* Parse an unwind_pad directive. */
4088 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4092 if (!unwind
.proc_start
)
4093 as_bad (MISSING_FNSTART
);
4095 if (immediate_for_directive (&offset
) == FAIL
)
4100 as_bad (_("stack increment must be multiple of 4"));
4101 ignore_rest_of_line ();
4105 /* Don't generate any opcodes, just record the details for later. */
4106 unwind
.frame_size
+= offset
;
4107 unwind
.pending_offset
+= offset
;
4109 demand_empty_rest_of_line ();
4112 /* Parse an unwind_setfp directive. */
4115 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4121 if (!unwind
.proc_start
)
4122 as_bad (MISSING_FNSTART
);
4124 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4125 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4128 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4130 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4132 as_bad (_("expected <reg>, <reg>"));
4133 ignore_rest_of_line ();
4137 /* Optional constant. */
4138 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4140 if (immediate_for_directive (&offset
) == FAIL
)
4146 demand_empty_rest_of_line ();
4148 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4150 as_bad (_("register must be either sp or set by a previous"
4151 "unwind_movsp directive"));
4155 /* Don't generate any opcodes, just record the information for later. */
4156 unwind
.fp_reg
= fp_reg
;
4158 if (sp_reg
== REG_SP
)
4159 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4161 unwind
.fp_offset
-= offset
;
4164 /* Parse an unwind_raw directive. */
4167 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4170 /* This is an arbitrary limit. */
4171 unsigned char op
[16];
4174 if (!unwind
.proc_start
)
4175 as_bad (MISSING_FNSTART
);
4178 if (exp
.X_op
== O_constant
4179 && skip_past_comma (&input_line_pointer
) != FAIL
)
4181 unwind
.frame_size
+= exp
.X_add_number
;
4185 exp
.X_op
= O_illegal
;
4187 if (exp
.X_op
!= O_constant
)
4189 as_bad (_("expected <offset>, <opcode>"));
4190 ignore_rest_of_line ();
4196 /* Parse the opcode. */
4201 as_bad (_("unwind opcode too long"));
4202 ignore_rest_of_line ();
4204 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4206 as_bad (_("invalid unwind opcode"));
4207 ignore_rest_of_line ();
4210 op
[count
++] = exp
.X_add_number
;
4212 /* Parse the next byte. */
4213 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4219 /* Add the opcode bytes in reverse order. */
4221 add_unwind_opcode (op
[count
], 1);
4223 demand_empty_rest_of_line ();
4227 /* Parse a .eabi_attribute directive. */
4230 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4232 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4234 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4235 attributes_set_explicitly
[tag
] = 1;
4237 #endif /* OBJ_ELF */
4239 static void s_arm_arch (int);
4240 static void s_arm_object_arch (int);
4241 static void s_arm_cpu (int);
4242 static void s_arm_fpu (int);
4247 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4254 if (exp
.X_op
== O_symbol
)
4255 exp
.X_op
= O_secrel
;
4257 emit_expr (&exp
, 4);
4259 while (*input_line_pointer
++ == ',');
4261 input_line_pointer
--;
4262 demand_empty_rest_of_line ();
4266 /* This table describes all the machine specific pseudo-ops the assembler
4267 has to support. The fields are:
4268 pseudo-op name without dot
4269 function to call to execute this pseudo-op
4270 Integer arg to pass to the function. */
4272 const pseudo_typeS md_pseudo_table
[] =
4274 /* Never called because '.req' does not start a line. */
4275 { "req", s_req
, 0 },
4276 /* Following two are likewise never called. */
4279 { "unreq", s_unreq
, 0 },
4280 { "bss", s_bss
, 0 },
4281 { "align", s_align
, 0 },
4282 { "arm", s_arm
, 0 },
4283 { "thumb", s_thumb
, 0 },
4284 { "code", s_code
, 0 },
4285 { "force_thumb", s_force_thumb
, 0 },
4286 { "thumb_func", s_thumb_func
, 0 },
4287 { "thumb_set", s_thumb_set
, 0 },
4288 { "even", s_even
, 0 },
4289 { "ltorg", s_ltorg
, 0 },
4290 { "pool", s_ltorg
, 0 },
4291 { "syntax", s_syntax
, 0 },
4292 { "cpu", s_arm_cpu
, 0 },
4293 { "arch", s_arm_arch
, 0 },
4294 { "object_arch", s_arm_object_arch
, 0 },
4295 { "fpu", s_arm_fpu
, 0 },
4297 { "word", s_arm_elf_cons
, 4 },
4298 { "long", s_arm_elf_cons
, 4 },
4299 { "inst.n", s_arm_elf_inst
, 2 },
4300 { "inst.w", s_arm_elf_inst
, 4 },
4301 { "inst", s_arm_elf_inst
, 0 },
4302 { "rel31", s_arm_rel31
, 0 },
4303 { "fnstart", s_arm_unwind_fnstart
, 0 },
4304 { "fnend", s_arm_unwind_fnend
, 0 },
4305 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4306 { "personality", s_arm_unwind_personality
, 0 },
4307 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4308 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4309 { "save", s_arm_unwind_save
, 0 },
4310 { "vsave", s_arm_unwind_save
, 1 },
4311 { "movsp", s_arm_unwind_movsp
, 0 },
4312 { "pad", s_arm_unwind_pad
, 0 },
4313 { "setfp", s_arm_unwind_setfp
, 0 },
4314 { "unwind_raw", s_arm_unwind_raw
, 0 },
4315 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4319 /* These are used for dwarf. */
4323 /* These are used for dwarf2. */
4324 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4325 { "loc", dwarf2_directive_loc
, 0 },
4326 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4328 { "extend", float_cons
, 'x' },
4329 { "ldouble", float_cons
, 'x' },
4330 { "packed", float_cons
, 'p' },
4332 {"secrel32", pe_directive_secrel
, 0},
4337 /* Parser functions used exclusively in instruction operands. */
4339 /* Generic immediate-value read function for use in insn parsing.
4340 STR points to the beginning of the immediate (the leading #);
4341 VAL receives the value; if the value is outside [MIN, MAX]
4342 issue an error. PREFIX_OPT is true if the immediate prefix is
4346 parse_immediate (char **str
, int *val
, int min
, int max
,
4347 bfd_boolean prefix_opt
)
4350 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4351 if (exp
.X_op
!= O_constant
)
4353 inst
.error
= _("constant expression required");
4357 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4359 inst
.error
= _("immediate value out of range");
4363 *val
= exp
.X_add_number
;
4367 /* Less-generic immediate-value read function with the possibility of loading a
4368 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4369 instructions. Puts the result directly in inst.operands[i]. */
4372 parse_big_immediate (char **str
, int i
)
4377 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4379 if (exp
.X_op
== O_constant
)
4381 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4382 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4383 O_constant. We have to be careful not to break compilation for
4384 32-bit X_add_number, though. */
4385 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4387 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4388 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4389 inst
.operands
[i
].regisimm
= 1;
4392 else if (exp
.X_op
== O_big
4393 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4394 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4396 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4397 /* Bignums have their least significant bits in
4398 generic_bignum[0]. Make sure we put 32 bits in imm and
4399 32 bits in reg, in a (hopefully) portable way. */
4400 gas_assert (parts
!= 0);
4401 inst
.operands
[i
].imm
= 0;
4402 for (j
= 0; j
< parts
; j
++, idx
++)
4403 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4404 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4405 inst
.operands
[i
].reg
= 0;
4406 for (j
= 0; j
< parts
; j
++, idx
++)
4407 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4408 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4409 inst
.operands
[i
].regisimm
= 1;
4419 /* Returns the pseudo-register number of an FPA immediate constant,
4420 or FAIL if there isn't a valid constant here. */
4423 parse_fpa_immediate (char ** str
)
4425 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4431 /* First try and match exact strings, this is to guarantee
4432 that some formats will work even for cross assembly. */
4434 for (i
= 0; fp_const
[i
]; i
++)
4436 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4440 *str
+= strlen (fp_const
[i
]);
4441 if (is_end_of_line
[(unsigned char) **str
])
4447 /* Just because we didn't get a match doesn't mean that the constant
4448 isn't valid, just that it is in a format that we don't
4449 automatically recognize. Try parsing it with the standard
4450 expression routines. */
4452 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4454 /* Look for a raw floating point number. */
4455 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4456 && is_end_of_line
[(unsigned char) *save_in
])
4458 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4460 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4462 if (words
[j
] != fp_values
[i
][j
])
4466 if (j
== MAX_LITTLENUMS
)
4474 /* Try and parse a more complex expression, this will probably fail
4475 unless the code uses a floating point prefix (eg "0f"). */
4476 save_in
= input_line_pointer
;
4477 input_line_pointer
= *str
;
4478 if (expression (&exp
) == absolute_section
4479 && exp
.X_op
== O_big
4480 && exp
.X_add_number
< 0)
4482 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4484 if (gen_to_words (words
, 5, (long) 15) == 0)
4486 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4488 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4490 if (words
[j
] != fp_values
[i
][j
])
4494 if (j
== MAX_LITTLENUMS
)
4496 *str
= input_line_pointer
;
4497 input_line_pointer
= save_in
;
4504 *str
= input_line_pointer
;
4505 input_line_pointer
= save_in
;
4506 inst
.error
= _("invalid FPA immediate expression");
4510 /* Returns 1 if a number has "quarter-precision" float format
4511 0baBbbbbbc defgh000 00000000 00000000. */
4514 is_quarter_float (unsigned imm
)
4516 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4517 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4520 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4521 0baBbbbbbc defgh000 00000000 00000000.
4522 The zero and minus-zero cases need special handling, since they can't be
4523 encoded in the "quarter-precision" float format, but can nonetheless be
4524 loaded as integer constants. */
4527 parse_qfloat_immediate (char **ccp
, int *immed
)
4531 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4532 int found_fpchar
= 0;
4534 skip_past_char (&str
, '#');
4536 /* We must not accidentally parse an integer as a floating-point number. Make
4537 sure that the value we parse is not an integer by checking for special
4538 characters '.' or 'e'.
4539 FIXME: This is a horrible hack, but doing better is tricky because type
4540 information isn't in a very usable state at parse time. */
4542 skip_whitespace (fpnum
);
4544 if (strncmp (fpnum
, "0x", 2) == 0)
4548 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4549 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4559 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4561 unsigned fpword
= 0;
4564 /* Our FP word must be 32 bits (single-precision FP). */
4565 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4567 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4571 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4584 /* Shift operands. */
4587 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4590 struct asm_shift_name
4593 enum shift_kind kind
;
4596 /* Third argument to parse_shift. */
4597 enum parse_shift_mode
4599 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4600 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4601 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4602 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4603 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4606 /* Parse a <shift> specifier on an ARM data processing instruction.
4607 This has three forms:
4609 (LSL|LSR|ASL|ASR|ROR) Rs
4610 (LSL|LSR|ASL|ASR|ROR) #imm
4613 Note that ASL is assimilated to LSL in the instruction encoding, and
4614 RRX to ROR #0 (which cannot be written as such). */
4617 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4619 const struct asm_shift_name
*shift_name
;
4620 enum shift_kind shift
;
4625 for (p
= *str
; ISALPHA (*p
); p
++)
4630 inst
.error
= _("shift expression expected");
4634 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4637 if (shift_name
== NULL
)
4639 inst
.error
= _("shift expression expected");
4643 shift
= shift_name
->kind
;
4647 case NO_SHIFT_RESTRICT
:
4648 case SHIFT_IMMEDIATE
: break;
4650 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4651 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4653 inst
.error
= _("'LSL' or 'ASR' required");
4658 case SHIFT_LSL_IMMEDIATE
:
4659 if (shift
!= SHIFT_LSL
)
4661 inst
.error
= _("'LSL' required");
4666 case SHIFT_ASR_IMMEDIATE
:
4667 if (shift
!= SHIFT_ASR
)
4669 inst
.error
= _("'ASR' required");
4677 if (shift
!= SHIFT_RRX
)
4679 /* Whitespace can appear here if the next thing is a bare digit. */
4680 skip_whitespace (p
);
4682 if (mode
== NO_SHIFT_RESTRICT
4683 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4685 inst
.operands
[i
].imm
= reg
;
4686 inst
.operands
[i
].immisreg
= 1;
4688 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4691 inst
.operands
[i
].shift_kind
= shift
;
4692 inst
.operands
[i
].shifted
= 1;
4697 /* Parse a <shifter_operand> for an ARM data processing instruction:
4700 #<immediate>, <rotate>
4704 where <shift> is defined by parse_shift above, and <rotate> is a
4705 multiple of 2 between 0 and 30. Validation of immediate operands
4706 is deferred to md_apply_fix. */
4709 parse_shifter_operand (char **str
, int i
)
4714 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4716 inst
.operands
[i
].reg
= value
;
4717 inst
.operands
[i
].isreg
= 1;
4719 /* parse_shift will override this if appropriate */
4720 inst
.reloc
.exp
.X_op
= O_constant
;
4721 inst
.reloc
.exp
.X_add_number
= 0;
4723 if (skip_past_comma (str
) == FAIL
)
4726 /* Shift operation on register. */
4727 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4730 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4733 if (skip_past_comma (str
) == SUCCESS
)
4735 /* #x, y -- ie explicit rotation by Y. */
4736 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4739 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4741 inst
.error
= _("constant expression expected");
4745 value
= expr
.X_add_number
;
4746 if (value
< 0 || value
> 30 || value
% 2 != 0)
4748 inst
.error
= _("invalid rotation");
4751 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4753 inst
.error
= _("invalid constant");
4757 /* Convert to decoded value. md_apply_fix will put it back. */
4758 inst
.reloc
.exp
.X_add_number
4759 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4760 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4763 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4764 inst
.reloc
.pc_rel
= 0;
4768 /* Group relocation information. Each entry in the table contains the
4769 textual name of the relocation as may appear in assembler source
4770 and must end with a colon.
4771 Along with this textual name are the relocation codes to be used if
4772 the corresponding instruction is an ALU instruction (ADD or SUB only),
4773 an LDR, an LDRS, or an LDC. */
4775 struct group_reloc_table_entry
4786 /* Varieties of non-ALU group relocation. */
4793 static struct group_reloc_table_entry group_reloc_table
[] =
4794 { /* Program counter relative: */
4796 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4801 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4802 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4803 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4804 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4806 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4811 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4812 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4813 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4814 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4816 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4817 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4818 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4819 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4820 /* Section base relative */
4822 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4827 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4828 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4829 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4830 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4832 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4837 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4838 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4839 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4840 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4842 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4843 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4844 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4845 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4847 /* Given the address of a pointer pointing to the textual name of a group
4848 relocation as may appear in assembler source, attempt to find its details
4849 in group_reloc_table. The pointer will be updated to the character after
4850 the trailing colon. On failure, FAIL will be returned; SUCCESS
4851 otherwise. On success, *entry will be updated to point at the relevant
4852 group_reloc_table entry. */
4855 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4858 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4860 int length
= strlen (group_reloc_table
[i
].name
);
4862 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4863 && (*str
)[length
] == ':')
4865 *out
= &group_reloc_table
[i
];
4866 *str
+= (length
+ 1);
4874 /* Parse a <shifter_operand> for an ARM data processing instruction
4875 (as for parse_shifter_operand) where group relocations are allowed:
4878 #<immediate>, <rotate>
4879 #:<group_reloc>:<expression>
4883 where <group_reloc> is one of the strings defined in group_reloc_table.
4884 The hashes are optional.
4886 Everything else is as for parse_shifter_operand. */
4888 static parse_operand_result
4889 parse_shifter_operand_group_reloc (char **str
, int i
)
4891 /* Determine if we have the sequence of characters #: or just :
4892 coming next. If we do, then we check for a group relocation.
4893 If we don't, punt the whole lot to parse_shifter_operand. */
4895 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4896 || (*str
)[0] == ':')
4898 struct group_reloc_table_entry
*entry
;
4900 if ((*str
)[0] == '#')
4905 /* Try to parse a group relocation. Anything else is an error. */
4906 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4908 inst
.error
= _("unknown group relocation");
4909 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4912 /* We now have the group relocation table entry corresponding to
4913 the name in the assembler source. Next, we parse the expression. */
4914 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4915 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4917 /* Record the relocation type (always the ALU variant here). */
4918 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4919 gas_assert (inst
.reloc
.type
!= 0);
4921 return PARSE_OPERAND_SUCCESS
;
4924 return parse_shifter_operand (str
, i
) == SUCCESS
4925 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4927 /* Never reached. */
4930 /* Parse all forms of an ARM address expression. Information is written
4931 to inst.operands[i] and/or inst.reloc.
4933 Preindexed addressing (.preind=1):
4935 [Rn, #offset] .reg=Rn .reloc.exp=offset
4936 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4937 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4938 .shift_kind=shift .reloc.exp=shift_imm
4940 These three may have a trailing ! which causes .writeback to be set also.
4942 Postindexed addressing (.postind=1, .writeback=1):
4944 [Rn], #offset .reg=Rn .reloc.exp=offset
4945 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4946 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4947 .shift_kind=shift .reloc.exp=shift_imm
4949 Unindexed addressing (.preind=0, .postind=0):
4951 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4955 [Rn]{!} shorthand for [Rn,#0]{!}
4956 =immediate .isreg=0 .reloc.exp=immediate
4957 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4959 It is the caller's responsibility to check for addressing modes not
4960 supported by the instruction, and to set inst.reloc.type. */
4962 static parse_operand_result
4963 parse_address_main (char **str
, int i
, int group_relocations
,
4964 group_reloc_type group_type
)
4969 if (skip_past_char (&p
, '[') == FAIL
)
4971 if (skip_past_char (&p
, '=') == FAIL
)
4973 /* bare address - translate to PC-relative offset */
4974 inst
.reloc
.pc_rel
= 1;
4975 inst
.operands
[i
].reg
= REG_PC
;
4976 inst
.operands
[i
].isreg
= 1;
4977 inst
.operands
[i
].preind
= 1;
4979 /* else a load-constant pseudo op, no special treatment needed here */
4981 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4982 return PARSE_OPERAND_FAIL
;
4985 return PARSE_OPERAND_SUCCESS
;
4988 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4990 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4991 return PARSE_OPERAND_FAIL
;
4993 inst
.operands
[i
].reg
= reg
;
4994 inst
.operands
[i
].isreg
= 1;
4996 if (skip_past_comma (&p
) == SUCCESS
)
4998 inst
.operands
[i
].preind
= 1;
5001 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5003 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5005 inst
.operands
[i
].imm
= reg
;
5006 inst
.operands
[i
].immisreg
= 1;
5008 if (skip_past_comma (&p
) == SUCCESS
)
5009 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5010 return PARSE_OPERAND_FAIL
;
5012 else if (skip_past_char (&p
, ':') == SUCCESS
)
5014 /* FIXME: '@' should be used here, but it's filtered out by generic
5015 code before we get to see it here. This may be subject to
5018 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5019 if (exp
.X_op
!= O_constant
)
5021 inst
.error
= _("alignment must be constant");
5022 return PARSE_OPERAND_FAIL
;
5024 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5025 inst
.operands
[i
].immisalign
= 1;
5026 /* Alignments are not pre-indexes. */
5027 inst
.operands
[i
].preind
= 0;
5031 if (inst
.operands
[i
].negative
)
5033 inst
.operands
[i
].negative
= 0;
5037 if (group_relocations
5038 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5040 struct group_reloc_table_entry
*entry
;
5042 /* Skip over the #: or : sequence. */
5048 /* Try to parse a group relocation. Anything else is an
5050 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5052 inst
.error
= _("unknown group relocation");
5053 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5056 /* We now have the group relocation table entry corresponding to
5057 the name in the assembler source. Next, we parse the
5059 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5060 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5062 /* Record the relocation type. */
5066 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5070 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5074 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5081 if (inst
.reloc
.type
== 0)
5083 inst
.error
= _("this group relocation is not allowed on this instruction");
5084 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5088 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5089 return PARSE_OPERAND_FAIL
;
5093 if (skip_past_char (&p
, ']') == FAIL
)
5095 inst
.error
= _("']' expected");
5096 return PARSE_OPERAND_FAIL
;
5099 if (skip_past_char (&p
, '!') == SUCCESS
)
5100 inst
.operands
[i
].writeback
= 1;
5102 else if (skip_past_comma (&p
) == SUCCESS
)
5104 if (skip_past_char (&p
, '{') == SUCCESS
)
5106 /* [Rn], {expr} - unindexed, with option */
5107 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5108 0, 255, TRUE
) == FAIL
)
5109 return PARSE_OPERAND_FAIL
;
5111 if (skip_past_char (&p
, '}') == FAIL
)
5113 inst
.error
= _("'}' expected at end of 'option' field");
5114 return PARSE_OPERAND_FAIL
;
5116 if (inst
.operands
[i
].preind
)
5118 inst
.error
= _("cannot combine index with option");
5119 return PARSE_OPERAND_FAIL
;
5122 return PARSE_OPERAND_SUCCESS
;
5126 inst
.operands
[i
].postind
= 1;
5127 inst
.operands
[i
].writeback
= 1;
5129 if (inst
.operands
[i
].preind
)
5131 inst
.error
= _("cannot combine pre- and post-indexing");
5132 return PARSE_OPERAND_FAIL
;
5136 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5138 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5140 /* We might be using the immediate for alignment already. If we
5141 are, OR the register number into the low-order bits. */
5142 if (inst
.operands
[i
].immisalign
)
5143 inst
.operands
[i
].imm
|= reg
;
5145 inst
.operands
[i
].imm
= reg
;
5146 inst
.operands
[i
].immisreg
= 1;
5148 if (skip_past_comma (&p
) == SUCCESS
)
5149 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5150 return PARSE_OPERAND_FAIL
;
5154 if (inst
.operands
[i
].negative
)
5156 inst
.operands
[i
].negative
= 0;
5159 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5160 return PARSE_OPERAND_FAIL
;
5165 /* If at this point neither .preind nor .postind is set, we have a
5166 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5167 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5169 inst
.operands
[i
].preind
= 1;
5170 inst
.reloc
.exp
.X_op
= O_constant
;
5171 inst
.reloc
.exp
.X_add_number
= 0;
5174 return PARSE_OPERAND_SUCCESS
;
5178 parse_address (char **str
, int i
)
5180 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5184 static parse_operand_result
5185 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5187 return parse_address_main (str
, i
, 1, type
);
5190 /* Parse an operand for a MOVW or MOVT instruction. */
5192 parse_half (char **str
)
5197 skip_past_char (&p
, '#');
5198 if (strncasecmp (p
, ":lower16:", 9) == 0)
5199 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5200 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5201 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5203 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5206 skip_whitespace (p
);
5209 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5212 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5214 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5216 inst
.error
= _("constant expression expected");
5219 if (inst
.reloc
.exp
.X_add_number
< 0
5220 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5222 inst
.error
= _("immediate value out of range");
5230 /* Miscellaneous. */
5232 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5233 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5235 parse_psr (char **str
)
5238 unsigned long psr_field
;
5239 const struct asm_psr
*psr
;
5242 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5243 feature for ease of use and backwards compatibility. */
5245 if (strncasecmp (p
, "SPSR", 4) == 0)
5246 psr_field
= SPSR_BIT
;
5247 else if (strncasecmp (p
, "CPSR", 4) == 0)
5254 while (ISALNUM (*p
) || *p
== '_');
5256 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5268 /* A suffix follows. */
5274 while (ISALNUM (*p
) || *p
== '_');
5276 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5281 psr_field
|= psr
->field
;
5286 goto error
; /* Garbage after "[CS]PSR". */
5288 psr_field
|= (PSR_c
| PSR_f
);
5294 inst
.error
= _("flag for {c}psr instruction expected");
5298 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5299 value suitable for splatting into the AIF field of the instruction. */
5302 parse_cps_flags (char **str
)
5311 case '\0': case ',':
5314 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5315 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5316 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5319 inst
.error
= _("unrecognized CPS flag");
5324 if (saw_a_flag
== 0)
5326 inst
.error
= _("missing CPS flags");
5334 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5335 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5338 parse_endian_specifier (char **str
)
5343 if (strncasecmp (s
, "BE", 2))
5345 else if (strncasecmp (s
, "LE", 2))
5349 inst
.error
= _("valid endian specifiers are be or le");
5353 if (ISALNUM (s
[2]) || s
[2] == '_')
5355 inst
.error
= _("valid endian specifiers are be or le");
5360 return little_endian
;
5363 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5364 value suitable for poking into the rotate field of an sxt or sxta
5365 instruction, or FAIL on error. */
5368 parse_ror (char **str
)
5373 if (strncasecmp (s
, "ROR", 3) == 0)
5377 inst
.error
= _("missing rotation field after comma");
5381 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5386 case 0: *str
= s
; return 0x0;
5387 case 8: *str
= s
; return 0x1;
5388 case 16: *str
= s
; return 0x2;
5389 case 24: *str
= s
; return 0x3;
5392 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5397 /* Parse a conditional code (from conds[] below). The value returned is in the
5398 range 0 .. 14, or FAIL. */
5400 parse_cond (char **str
)
5403 const struct asm_cond
*c
;
5405 /* Condition codes are always 2 characters, so matching up to
5406 3 characters is sufficient. */
5411 while (ISALPHA (*q
) && n
< 3)
5413 cond
[n
] = TOLOWER (*q
);
5418 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5421 inst
.error
= _("condition required");
5429 /* Parse an option for a barrier instruction. Returns the encoding for the
5432 parse_barrier (char **str
)
5435 const struct asm_barrier_opt
*o
;
5438 while (ISALPHA (*q
))
5441 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5450 /* Parse the operands of a table branch instruction. Similar to a memory
5453 parse_tb (char **str
)
5458 if (skip_past_char (&p
, '[') == FAIL
)
5460 inst
.error
= _("'[' expected");
5464 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5466 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5469 inst
.operands
[0].reg
= reg
;
5471 if (skip_past_comma (&p
) == FAIL
)
5473 inst
.error
= _("',' expected");
5477 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5479 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5482 inst
.operands
[0].imm
= reg
;
5484 if (skip_past_comma (&p
) == SUCCESS
)
5486 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5488 if (inst
.reloc
.exp
.X_add_number
!= 1)
5490 inst
.error
= _("invalid shift");
5493 inst
.operands
[0].shifted
= 1;
5496 if (skip_past_char (&p
, ']') == FAIL
)
5498 inst
.error
= _("']' expected");
5505 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5506 information on the types the operands can take and how they are encoded.
5507 Up to four operands may be read; this function handles setting the
5508 ".present" field for each read operand itself.
5509 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5510 else returns FAIL. */
5513 parse_neon_mov (char **str
, int *which_operand
)
5515 int i
= *which_operand
, val
;
5516 enum arm_reg_type rtype
;
5518 struct neon_type_el optype
;
5520 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5522 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5523 inst
.operands
[i
].reg
= val
;
5524 inst
.operands
[i
].isscalar
= 1;
5525 inst
.operands
[i
].vectype
= optype
;
5526 inst
.operands
[i
++].present
= 1;
5528 if (skip_past_comma (&ptr
) == FAIL
)
5531 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5534 inst
.operands
[i
].reg
= val
;
5535 inst
.operands
[i
].isreg
= 1;
5536 inst
.operands
[i
].present
= 1;
5538 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5541 /* Cases 0, 1, 2, 3, 5 (D only). */
5542 if (skip_past_comma (&ptr
) == FAIL
)
5545 inst
.operands
[i
].reg
= val
;
5546 inst
.operands
[i
].isreg
= 1;
5547 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5548 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5549 inst
.operands
[i
].isvec
= 1;
5550 inst
.operands
[i
].vectype
= optype
;
5551 inst
.operands
[i
++].present
= 1;
5553 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5555 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5556 Case 13: VMOV <Sd>, <Rm> */
5557 inst
.operands
[i
].reg
= val
;
5558 inst
.operands
[i
].isreg
= 1;
5559 inst
.operands
[i
].present
= 1;
5561 if (rtype
== REG_TYPE_NQ
)
5563 first_error (_("can't use Neon quad register here"));
5566 else if (rtype
!= REG_TYPE_VFS
)
5569 if (skip_past_comma (&ptr
) == FAIL
)
5571 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5573 inst
.operands
[i
].reg
= val
;
5574 inst
.operands
[i
].isreg
= 1;
5575 inst
.operands
[i
].present
= 1;
5578 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5581 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5582 Case 1: VMOV<c><q> <Dd>, <Dm>
5583 Case 8: VMOV.F32 <Sd>, <Sm>
5584 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5586 inst
.operands
[i
].reg
= val
;
5587 inst
.operands
[i
].isreg
= 1;
5588 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5589 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5590 inst
.operands
[i
].isvec
= 1;
5591 inst
.operands
[i
].vectype
= optype
;
5592 inst
.operands
[i
].present
= 1;
5594 if (skip_past_comma (&ptr
) == SUCCESS
)
5599 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5602 inst
.operands
[i
].reg
= val
;
5603 inst
.operands
[i
].isreg
= 1;
5604 inst
.operands
[i
++].present
= 1;
5606 if (skip_past_comma (&ptr
) == FAIL
)
5609 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5612 inst
.operands
[i
].reg
= val
;
5613 inst
.operands
[i
].isreg
= 1;
5614 inst
.operands
[i
++].present
= 1;
5617 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5618 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5619 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5620 Case 10: VMOV.F32 <Sd>, #<imm>
5621 Case 11: VMOV.F64 <Dd>, #<imm> */
5622 inst
.operands
[i
].immisfloat
= 1;
5623 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5624 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5625 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5629 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5633 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5636 inst
.operands
[i
].reg
= val
;
5637 inst
.operands
[i
].isreg
= 1;
5638 inst
.operands
[i
++].present
= 1;
5640 if (skip_past_comma (&ptr
) == FAIL
)
5643 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5645 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5646 inst
.operands
[i
].reg
= val
;
5647 inst
.operands
[i
].isscalar
= 1;
5648 inst
.operands
[i
].present
= 1;
5649 inst
.operands
[i
].vectype
= optype
;
5651 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5653 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5654 inst
.operands
[i
].reg
= val
;
5655 inst
.operands
[i
].isreg
= 1;
5656 inst
.operands
[i
++].present
= 1;
5658 if (skip_past_comma (&ptr
) == FAIL
)
5661 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5664 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5668 inst
.operands
[i
].reg
= val
;
5669 inst
.operands
[i
].isreg
= 1;
5670 inst
.operands
[i
].isvec
= 1;
5671 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5672 inst
.operands
[i
].vectype
= optype
;
5673 inst
.operands
[i
].present
= 1;
5675 if (rtype
== REG_TYPE_VFS
)
5679 if (skip_past_comma (&ptr
) == FAIL
)
5681 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5684 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5687 inst
.operands
[i
].reg
= val
;
5688 inst
.operands
[i
].isreg
= 1;
5689 inst
.operands
[i
].isvec
= 1;
5690 inst
.operands
[i
].issingle
= 1;
5691 inst
.operands
[i
].vectype
= optype
;
5692 inst
.operands
[i
].present
= 1;
5695 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5699 inst
.operands
[i
].reg
= val
;
5700 inst
.operands
[i
].isreg
= 1;
5701 inst
.operands
[i
].isvec
= 1;
5702 inst
.operands
[i
].issingle
= 1;
5703 inst
.operands
[i
].vectype
= optype
;
5704 inst
.operands
[i
++].present
= 1;
5709 first_error (_("parse error"));
5713 /* Successfully parsed the operands. Update args. */
5719 first_error (_("expected comma"));
5723 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5727 /* Matcher codes for parse_operands. */
5728 enum operand_parse_code
5730 OP_stop
, /* end of line */
5732 OP_RR
, /* ARM register */
5733 OP_RRnpc
, /* ARM register, not r15 */
5734 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5735 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5736 OP_RCP
, /* Coprocessor number */
5737 OP_RCN
, /* Coprocessor register */
5738 OP_RF
, /* FPA register */
5739 OP_RVS
, /* VFP single precision register */
5740 OP_RVD
, /* VFP double precision register (0..15) */
5741 OP_RND
, /* Neon double precision register (0..31) */
5742 OP_RNQ
, /* Neon quad precision register */
5743 OP_RVSD
, /* VFP single or double precision register */
5744 OP_RNDQ
, /* Neon double or quad precision register */
5745 OP_RNSDQ
, /* Neon single, double or quad precision register */
5746 OP_RNSC
, /* Neon scalar D[X] */
5747 OP_RVC
, /* VFP control register */
5748 OP_RMF
, /* Maverick F register */
5749 OP_RMD
, /* Maverick D register */
5750 OP_RMFX
, /* Maverick FX register */
5751 OP_RMDX
, /* Maverick DX register */
5752 OP_RMAX
, /* Maverick AX register */
5753 OP_RMDS
, /* Maverick DSPSC register */
5754 OP_RIWR
, /* iWMMXt wR register */
5755 OP_RIWC
, /* iWMMXt wC register */
5756 OP_RIWG
, /* iWMMXt wCG register */
5757 OP_RXA
, /* XScale accumulator register */
5759 OP_REGLST
, /* ARM register list */
5760 OP_VRSLST
, /* VFP single-precision register list */
5761 OP_VRDLST
, /* VFP double-precision register list */
5762 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5763 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5764 OP_NSTRLST
, /* Neon element/structure list */
5766 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5767 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5768 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5769 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5770 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5771 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5772 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5773 OP_VMOV
, /* Neon VMOV operands. */
5774 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5775 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5776 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5778 OP_I0
, /* immediate zero */
5779 OP_I7
, /* immediate value 0 .. 7 */
5780 OP_I15
, /* 0 .. 15 */
5781 OP_I16
, /* 1 .. 16 */
5782 OP_I16z
, /* 0 .. 16 */
5783 OP_I31
, /* 0 .. 31 */
5784 OP_I31w
, /* 0 .. 31, optional trailing ! */
5785 OP_I32
, /* 1 .. 32 */
5786 OP_I32z
, /* 0 .. 32 */
5787 OP_I63
, /* 0 .. 63 */
5788 OP_I63s
, /* -64 .. 63 */
5789 OP_I64
, /* 1 .. 64 */
5790 OP_I64z
, /* 0 .. 64 */
5791 OP_I255
, /* 0 .. 255 */
5793 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5794 OP_I7b
, /* 0 .. 7 */
5795 OP_I15b
, /* 0 .. 15 */
5796 OP_I31b
, /* 0 .. 31 */
5798 OP_SH
, /* shifter operand */
5799 OP_SHG
, /* shifter operand with possible group relocation */
5800 OP_ADDR
, /* Memory address expression (any mode) */
5801 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5802 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5803 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5804 OP_EXP
, /* arbitrary expression */
5805 OP_EXPi
, /* same, with optional immediate prefix */
5806 OP_EXPr
, /* same, with optional relocation suffix */
5807 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5809 OP_CPSF
, /* CPS flags */
5810 OP_ENDI
, /* Endianness specifier */
5811 OP_PSR
, /* CPSR/SPSR mask for msr */
5812 OP_COND
, /* conditional code */
5813 OP_TB
, /* Table branch. */
5815 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5816 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5818 OP_RRnpc_I0
, /* ARM register or literal 0 */
5819 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5820 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5821 OP_RF_IF
, /* FPA register or immediate */
5822 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5823 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5825 /* Optional operands. */
5826 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5827 OP_oI31b
, /* 0 .. 31 */
5828 OP_oI32b
, /* 1 .. 32 */
5829 OP_oIffffb
, /* 0 .. 65535 */
5830 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5832 OP_oRR
, /* ARM register */
5833 OP_oRRnpc
, /* ARM register, not the PC */
5834 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5835 OP_oRND
, /* Optional Neon double precision register */
5836 OP_oRNQ
, /* Optional Neon quad precision register */
5837 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5838 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5839 OP_oSHll
, /* LSL immediate */
5840 OP_oSHar
, /* ASR immediate */
5841 OP_oSHllar
, /* LSL or ASR immediate */
5842 OP_oROR
, /* ROR 0/8/16/24 */
5843 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5845 OP_FIRST_OPTIONAL
= OP_oI7b
5848 /* Generic instruction operand parser. This does no encoding and no
5849 semantic validation; it merely squirrels values away in the inst
5850 structure. Returns SUCCESS or FAIL depending on whether the
5851 specified grammar matched. */
5853 parse_operands (char *str
, const unsigned char *pattern
)
5855 unsigned const char *upat
= pattern
;
5856 char *backtrack_pos
= 0;
5857 const char *backtrack_error
= 0;
5858 int i
, val
, backtrack_index
= 0;
5859 enum arm_reg_type rtype
;
5860 parse_operand_result result
;
5862 #define po_char_or_fail(chr) \
5865 if (skip_past_char (&str, chr) == FAIL) \
5870 #define po_reg_or_fail(regtype) \
5873 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5874 & inst.operands[i].vectype); \
5877 first_error (_(reg_expected_msgs[regtype])); \
5880 inst.operands[i].reg = val; \
5881 inst.operands[i].isreg = 1; \
5882 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5883 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5884 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5885 || rtype == REG_TYPE_VFD \
5886 || rtype == REG_TYPE_NQ); \
5890 #define po_reg_or_goto(regtype, label) \
5893 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5894 & inst.operands[i].vectype); \
5898 inst.operands[i].reg = val; \
5899 inst.operands[i].isreg = 1; \
5900 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5901 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5902 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5903 || rtype == REG_TYPE_VFD \
5904 || rtype == REG_TYPE_NQ); \
5908 #define po_imm_or_fail(min, max, popt) \
5911 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5913 inst.operands[i].imm = val; \
5917 #define po_scalar_or_goto(elsz, label) \
5920 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5923 inst.operands[i].reg = val; \
5924 inst.operands[i].isscalar = 1; \
5928 #define po_misc_or_fail(expr) \
5936 #define po_misc_or_fail_no_backtrack(expr) \
5940 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
5941 backtrack_pos = 0; \
5942 if (result != PARSE_OPERAND_SUCCESS) \
5947 skip_whitespace (str
);
5949 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5951 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5953 /* Remember where we are in case we need to backtrack. */
5954 gas_assert (!backtrack_pos
);
5955 backtrack_pos
= str
;
5956 backtrack_error
= inst
.error
;
5957 backtrack_index
= i
;
5960 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5961 po_char_or_fail (',');
5969 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5970 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5971 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5972 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5973 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5974 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5976 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5978 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5980 /* Also accept generic coprocessor regs for unknown registers. */
5982 po_reg_or_fail (REG_TYPE_CN
);
5984 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5985 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5986 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5987 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5988 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5989 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5990 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5991 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5992 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5993 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5995 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5997 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5998 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6000 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6002 /* Neon scalar. Using an element size of 8 means that some invalid
6003 scalars are accepted here, so deal with those in later code. */
6004 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6006 /* WARNING: We can expand to two operands here. This has the potential
6007 to totally confuse the backtracking mechanism! It will be OK at
6008 least as long as we don't try to use optional args as well,
6012 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
6013 inst
.operands
[i
].present
= 1;
6015 skip_past_comma (&str
);
6016 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
6019 /* Optional register operand was omitted. Unfortunately, it's in
6020 operands[i-1] and we need it to be in inst.operands[i]. Fix that
6021 here (this is a bit grotty). */
6022 inst
.operands
[i
] = inst
.operands
[i
-1];
6023 inst
.operands
[i
-1].present
= 0;
6026 /* There's a possibility of getting a 64-bit immediate here, so
6027 we need special handling. */
6028 if (parse_big_immediate (&str
, i
) == FAIL
)
6030 inst
.error
= _("immediate value is out of range");
6038 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6041 po_imm_or_fail (0, 0, TRUE
);
6046 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6051 po_scalar_or_goto (8, try_rr
);
6054 po_reg_or_fail (REG_TYPE_RN
);
6060 po_scalar_or_goto (8, try_nsdq
);
6063 po_reg_or_fail (REG_TYPE_NSDQ
);
6069 po_scalar_or_goto (8, try_ndq
);
6072 po_reg_or_fail (REG_TYPE_NDQ
);
6078 po_scalar_or_goto (8, try_vfd
);
6081 po_reg_or_fail (REG_TYPE_VFD
);
6086 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6087 not careful then bad things might happen. */
6088 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6093 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
6096 /* There's a possibility of getting a 64-bit immediate here, so
6097 we need special handling. */
6098 if (parse_big_immediate (&str
, i
) == FAIL
)
6100 inst
.error
= _("immediate value is out of range");
6108 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6111 po_imm_or_fail (0, 63, TRUE
);
6116 po_char_or_fail ('[');
6117 po_reg_or_fail (REG_TYPE_RN
);
6118 po_char_or_fail (']');
6123 po_reg_or_fail (REG_TYPE_RN
);
6124 if (skip_past_char (&str
, '!') == SUCCESS
)
6125 inst
.operands
[i
].writeback
= 1;
6129 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6130 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6131 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6132 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6133 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6134 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6135 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6136 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6137 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6138 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6139 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6140 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6142 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6144 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6145 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6147 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6148 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6149 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6151 /* Immediate variants */
6153 po_char_or_fail ('{');
6154 po_imm_or_fail (0, 255, TRUE
);
6155 po_char_or_fail ('}');
6159 /* The expression parser chokes on a trailing !, so we have
6160 to find it first and zap it. */
6163 while (*s
&& *s
!= ',')
6168 inst
.operands
[i
].writeback
= 1;
6170 po_imm_or_fail (0, 31, TRUE
);
6178 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6183 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6188 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6190 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6192 val
= parse_reloc (&str
);
6195 inst
.error
= _("unrecognized relocation suffix");
6198 else if (val
!= BFD_RELOC_UNUSED
)
6200 inst
.operands
[i
].imm
= val
;
6201 inst
.operands
[i
].hasreloc
= 1;
6206 /* Operand for MOVW or MOVT. */
6208 po_misc_or_fail (parse_half (&str
));
6211 /* Register or expression. */
6212 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6213 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6215 /* Register or immediate. */
6216 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6217 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6219 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6221 if (!is_immediate_prefix (*str
))
6224 val
= parse_fpa_immediate (&str
);
6227 /* FPA immediates are encoded as registers 8-15.
6228 parse_fpa_immediate has already applied the offset. */
6229 inst
.operands
[i
].reg
= val
;
6230 inst
.operands
[i
].isreg
= 1;
6233 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6234 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6236 /* Two kinds of register. */
6239 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6241 || (rege
->type
!= REG_TYPE_MMXWR
6242 && rege
->type
!= REG_TYPE_MMXWC
6243 && rege
->type
!= REG_TYPE_MMXWCG
))
6245 inst
.error
= _("iWMMXt data or control register expected");
6248 inst
.operands
[i
].reg
= rege
->number
;
6249 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6255 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6257 || (rege
->type
!= REG_TYPE_MMXWC
6258 && rege
->type
!= REG_TYPE_MMXWCG
))
6260 inst
.error
= _("iWMMXt control register expected");
6263 inst
.operands
[i
].reg
= rege
->number
;
6264 inst
.operands
[i
].isreg
= 1;
6269 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6270 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6271 case OP_oROR
: val
= parse_ror (&str
); break;
6272 case OP_PSR
: val
= parse_psr (&str
); break;
6273 case OP_COND
: val
= parse_cond (&str
); break;
6274 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
6277 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6278 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6281 val
= parse_psr (&str
);
6285 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6288 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6290 if (strncasecmp (str
, "APSR_", 5) == 0)
6297 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6298 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6299 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6300 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6301 default: found
= 16;
6305 inst
.operands
[i
].isvec
= 1;
6306 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6307 inst
.operands
[i
].reg
= REG_PC
;
6314 po_misc_or_fail (parse_tb (&str
));
6317 /* Register lists. */
6319 val
= parse_reg_list (&str
);
6322 inst
.operands
[1].writeback
= 1;
6328 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6332 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6336 /* Allow Q registers too. */
6337 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6342 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6344 inst
.operands
[i
].issingle
= 1;
6349 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6354 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6355 &inst
.operands
[i
].vectype
);
6358 /* Addressing modes */
6360 po_misc_or_fail (parse_address (&str
, i
));
6364 po_misc_or_fail_no_backtrack (
6365 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6369 po_misc_or_fail_no_backtrack (
6370 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6374 po_misc_or_fail_no_backtrack (
6375 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6379 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6383 po_misc_or_fail_no_backtrack (
6384 parse_shifter_operand_group_reloc (&str
, i
));
6388 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6392 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6396 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6400 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6403 /* Various value-based sanity checks and shared operations. We
6404 do not signal immediate failures for the register constraints;
6405 this allows a syntax error to take precedence. */
6414 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6415 inst
.error
= BAD_PC
;
6433 inst
.operands
[i
].imm
= val
;
6440 /* If we get here, this operand was successfully parsed. */
6441 inst
.operands
[i
].present
= 1;
6445 inst
.error
= BAD_ARGS
;
6450 /* The parse routine should already have set inst.error, but set a
6451 default here just in case. */
6453 inst
.error
= _("syntax error");
6457 /* Do not backtrack over a trailing optional argument that
6458 absorbed some text. We will only fail again, with the
6459 'garbage following instruction' error message, which is
6460 probably less helpful than the current one. */
6461 if (backtrack_index
== i
&& backtrack_pos
!= str
6462 && upat
[i
+1] == OP_stop
)
6465 inst
.error
= _("syntax error");
6469 /* Try again, skipping the optional argument at backtrack_pos. */
6470 str
= backtrack_pos
;
6471 inst
.error
= backtrack_error
;
6472 inst
.operands
[backtrack_index
].present
= 0;
6473 i
= backtrack_index
;
6477 /* Check that we have parsed all the arguments. */
6478 if (*str
!= '\0' && !inst
.error
)
6479 inst
.error
= _("garbage following instruction");
6481 return inst
.error
? FAIL
: SUCCESS
;
6484 #undef po_char_or_fail
6485 #undef po_reg_or_fail
6486 #undef po_reg_or_goto
6487 #undef po_imm_or_fail
6488 #undef po_scalar_or_fail
6490 /* Shorthand macro for instruction encoding functions issuing errors. */
6491 #define constraint(expr, err) \
6502 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6503 instructions are unpredictable if these registers are used. This
6504 is the BadReg predicate in ARM's Thumb-2 documentation. */
6505 #define reject_bad_reg(reg) \
6507 if (reg == REG_SP || reg == REG_PC) \
6509 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6514 /* If REG is R13 (the stack pointer), warn that its use is
6516 #define warn_deprecated_sp(reg) \
6518 if (warn_on_deprecated && reg == REG_SP) \
6519 as_warn (_("use of r13 is deprecated")); \
6522 /* Functions for operand encoding. ARM, then Thumb. */
6524 #define rotate_left(v, n) (v << n | v >> (32 - n))
6526 /* If VAL can be encoded in the immediate field of an ARM instruction,
6527 return the encoded form. Otherwise, return FAIL. */
6530 encode_arm_immediate (unsigned int val
)
6534 for (i
= 0; i
< 32; i
+= 2)
6535 if ((a
= rotate_left (val
, i
)) <= 0xff)
6536 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6541 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6542 return the encoded form. Otherwise, return FAIL. */
6544 encode_thumb32_immediate (unsigned int val
)
6551 for (i
= 1; i
<= 24; i
++)
6554 if ((val
& ~(0xff << i
)) == 0)
6555 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6559 if (val
== ((a
<< 16) | a
))
6561 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6565 if (val
== ((a
<< 16) | a
))
6566 return 0x200 | (a
>> 8);
6570 /* Encode a VFP SP or DP register number into inst.instruction. */
6573 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6575 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6578 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6581 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6584 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6589 first_error (_("D register out of range for selected VFP version"));
6597 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6601 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6605 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6609 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6613 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6617 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6625 /* Encode a <shift> in an ARM-format instruction. The immediate,
6626 if any, is handled by md_apply_fix. */
6628 encode_arm_shift (int i
)
6630 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6631 inst
.instruction
|= SHIFT_ROR
<< 5;
6634 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6635 if (inst
.operands
[i
].immisreg
)
6637 inst
.instruction
|= SHIFT_BY_REG
;
6638 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6641 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6646 encode_arm_shifter_operand (int i
)
6648 if (inst
.operands
[i
].isreg
)
6650 inst
.instruction
|= inst
.operands
[i
].reg
;
6651 encode_arm_shift (i
);
6654 inst
.instruction
|= INST_IMMEDIATE
;
6657 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6659 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6661 gas_assert (inst
.operands
[i
].isreg
);
6662 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6664 if (inst
.operands
[i
].preind
)
6668 inst
.error
= _("instruction does not accept preindexed addressing");
6671 inst
.instruction
|= PRE_INDEX
;
6672 if (inst
.operands
[i
].writeback
)
6673 inst
.instruction
|= WRITE_BACK
;
6676 else if (inst
.operands
[i
].postind
)
6678 gas_assert (inst
.operands
[i
].writeback
);
6680 inst
.instruction
|= WRITE_BACK
;
6682 else /* unindexed - only for coprocessor */
6684 inst
.error
= _("instruction does not accept unindexed addressing");
6688 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6689 && (((inst
.instruction
& 0x000f0000) >> 16)
6690 == ((inst
.instruction
& 0x0000f000) >> 12)))
6691 as_warn ((inst
.instruction
& LOAD_BIT
)
6692 ? _("destination register same as write-back base")
6693 : _("source register same as write-back base"));
6696 /* inst.operands[i] was set up by parse_address. Encode it into an
6697 ARM-format mode 2 load or store instruction. If is_t is true,
6698 reject forms that cannot be used with a T instruction (i.e. not
6701 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6703 encode_arm_addr_mode_common (i
, is_t
);
6705 if (inst
.operands
[i
].immisreg
)
6707 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6708 inst
.instruction
|= inst
.operands
[i
].imm
;
6709 if (!inst
.operands
[i
].negative
)
6710 inst
.instruction
|= INDEX_UP
;
6711 if (inst
.operands
[i
].shifted
)
6713 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6714 inst
.instruction
|= SHIFT_ROR
<< 5;
6717 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6718 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6722 else /* immediate offset in inst.reloc */
6724 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6725 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6729 /* inst.operands[i] was set up by parse_address. Encode it into an
6730 ARM-format mode 3 load or store instruction. Reject forms that
6731 cannot be used with such instructions. If is_t is true, reject
6732 forms that cannot be used with a T instruction (i.e. not
6735 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6737 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6739 inst
.error
= _("instruction does not accept scaled register index");
6743 encode_arm_addr_mode_common (i
, is_t
);
6745 if (inst
.operands
[i
].immisreg
)
6747 inst
.instruction
|= inst
.operands
[i
].imm
;
6748 if (!inst
.operands
[i
].negative
)
6749 inst
.instruction
|= INDEX_UP
;
6751 else /* immediate offset in inst.reloc */
6753 inst
.instruction
|= HWOFFSET_IMM
;
6754 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6755 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6759 /* inst.operands[i] was set up by parse_address. Encode it into an
6760 ARM-format instruction. Reject all forms which cannot be encoded
6761 into a coprocessor load/store instruction. If wb_ok is false,
6762 reject use of writeback; if unind_ok is false, reject use of
6763 unindexed addressing. If reloc_override is not 0, use it instead
6764 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6765 (in which case it is preserved). */
6768 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6770 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6772 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6774 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6776 gas_assert (!inst
.operands
[i
].writeback
);
6779 inst
.error
= _("instruction does not support unindexed addressing");
6782 inst
.instruction
|= inst
.operands
[i
].imm
;
6783 inst
.instruction
|= INDEX_UP
;
6787 if (inst
.operands
[i
].preind
)
6788 inst
.instruction
|= PRE_INDEX
;
6790 if (inst
.operands
[i
].writeback
)
6792 if (inst
.operands
[i
].reg
== REG_PC
)
6794 inst
.error
= _("pc may not be used with write-back");
6799 inst
.error
= _("instruction does not support writeback");
6802 inst
.instruction
|= WRITE_BACK
;
6806 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6807 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6808 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6809 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6812 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6814 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6820 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6821 Determine whether it can be performed with a move instruction; if
6822 it can, convert inst.instruction to that move instruction and
6823 return TRUE; if it can't, convert inst.instruction to a literal-pool
6824 load and return FALSE. If this is not a valid thing to do in the
6825 current context, set inst.error and return TRUE.
6827 inst.operands[i] describes the destination register. */
6830 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6835 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6839 if ((inst
.instruction
& tbit
) == 0)
6841 inst
.error
= _("invalid pseudo operation");
6844 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6846 inst
.error
= _("constant expression expected");
6849 if (inst
.reloc
.exp
.X_op
== O_constant
)
6853 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6855 /* This can be done with a mov(1) instruction. */
6856 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6857 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6863 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6866 /* This can be done with a mov instruction. */
6867 inst
.instruction
&= LITERAL_MASK
;
6868 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6869 inst
.instruction
|= value
& 0xfff;
6873 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6876 /* This can be done with a mvn instruction. */
6877 inst
.instruction
&= LITERAL_MASK
;
6878 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6879 inst
.instruction
|= value
& 0xfff;
6885 if (add_to_lit_pool () == FAIL
)
6887 inst
.error
= _("literal pool insertion failed");
6890 inst
.operands
[1].reg
= REG_PC
;
6891 inst
.operands
[1].isreg
= 1;
6892 inst
.operands
[1].preind
= 1;
6893 inst
.reloc
.pc_rel
= 1;
6894 inst
.reloc
.type
= (thumb_p
6895 ? BFD_RELOC_ARM_THUMB_OFFSET
6897 ? BFD_RELOC_ARM_HWLITERAL
6898 : BFD_RELOC_ARM_LITERAL
));
6902 /* Functions for instruction encoding, sorted by sub-architecture.
6903 First some generics; their names are taken from the conventional
6904 bit positions for register arguments in ARM format instructions. */
6914 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6920 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6921 inst
.instruction
|= inst
.operands
[1].reg
;
6927 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6928 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6934 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6935 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6941 unsigned Rn
= inst
.operands
[2].reg
;
6942 /* Enforce restrictions on SWP instruction. */
6943 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6944 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6945 _("Rn must not overlap other operands"));
6946 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6947 inst
.instruction
|= inst
.operands
[1].reg
;
6948 inst
.instruction
|= Rn
<< 16;
6954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6955 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6956 inst
.instruction
|= inst
.operands
[2].reg
;
6962 inst
.instruction
|= inst
.operands
[0].reg
;
6963 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6964 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6970 inst
.instruction
|= inst
.operands
[0].imm
;
6976 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6977 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6980 /* ARM instructions, in alphabetical order by function name (except
6981 that wrapper functions appear immediately after the function they
6984 /* This is a pseudo-op of the form "adr rd, label" to be converted
6985 into a relative address of the form "add rd, pc, #label-.-8". */
6990 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6992 /* Frag hacking will turn this into a sub instruction if the offset turns
6993 out to be negative. */
6994 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6995 inst
.reloc
.pc_rel
= 1;
6996 inst
.reloc
.exp
.X_add_number
-= 8;
6999 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7000 into a relative address of the form:
7001 add rd, pc, #low(label-.-8)"
7002 add rd, rd, #high(label-.-8)" */
7007 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7009 /* Frag hacking will turn this into a sub instruction if the offset turns
7010 out to be negative. */
7011 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7012 inst
.reloc
.pc_rel
= 1;
7013 inst
.size
= INSN_SIZE
* 2;
7014 inst
.reloc
.exp
.X_add_number
-= 8;
7020 if (!inst
.operands
[1].present
)
7021 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7022 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7023 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7024 encode_arm_shifter_operand (2);
7030 if (inst
.operands
[0].present
)
7032 constraint ((inst
.instruction
& 0xf0) != 0x40
7033 && inst
.operands
[0].imm
!= 0xf,
7034 _("bad barrier type"));
7035 inst
.instruction
|= inst
.operands
[0].imm
;
7038 inst
.instruction
|= 0xf;
7044 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7045 constraint (msb
> 32, _("bit-field extends past end of register"));
7046 /* The instruction encoding stores the LSB and MSB,
7047 not the LSB and width. */
7048 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7049 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7050 inst
.instruction
|= (msb
- 1) << 16;
7058 /* #0 in second position is alternative syntax for bfc, which is
7059 the same instruction but with REG_PC in the Rm field. */
7060 if (!inst
.operands
[1].isreg
)
7061 inst
.operands
[1].reg
= REG_PC
;
7063 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7064 constraint (msb
> 32, _("bit-field extends past end of register"));
7065 /* The instruction encoding stores the LSB and MSB,
7066 not the LSB and width. */
7067 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7068 inst
.instruction
|= inst
.operands
[1].reg
;
7069 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7070 inst
.instruction
|= (msb
- 1) << 16;
7076 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7077 _("bit-field extends past end of register"));
7078 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7079 inst
.instruction
|= inst
.operands
[1].reg
;
7080 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7081 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7084 /* ARM V5 breakpoint instruction (argument parse)
7085 BKPT <16 bit unsigned immediate>
7086 Instruction is not conditional.
7087 The bit pattern given in insns[] has the COND_ALWAYS condition,
7088 and it is an error if the caller tried to override that. */
7093 /* Top 12 of 16 bits to bits 19:8. */
7094 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7096 /* Bottom 4 of 16 bits to bits 3:0. */
7097 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7101 encode_branch (int default_reloc
)
7103 if (inst
.operands
[0].hasreloc
)
7105 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7106 _("the only suffix valid here is '(plt)'"));
7107 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7111 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7113 inst
.reloc
.pc_rel
= 1;
7120 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7121 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7124 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7131 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7133 if (inst
.cond
== COND_ALWAYS
)
7134 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7136 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7140 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7143 /* ARM V5 branch-link-exchange instruction (argument parse)
7144 BLX <target_addr> ie BLX(1)
7145 BLX{<condition>} <Rm> ie BLX(2)
7146 Unfortunately, there are two different opcodes for this mnemonic.
7147 So, the insns[].value is not used, and the code here zaps values
7148 into inst.instruction.
7149 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7154 if (inst
.operands
[0].isreg
)
7156 /* Arg is a register; the opcode provided by insns[] is correct.
7157 It is not illegal to do "blx pc", just useless. */
7158 if (inst
.operands
[0].reg
== REG_PC
)
7159 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7161 inst
.instruction
|= inst
.operands
[0].reg
;
7165 /* Arg is an address; this instruction cannot be executed
7166 conditionally, and the opcode must be adjusted.
7167 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7168 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7169 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7170 inst
.instruction
= 0xfa000000;
7171 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7178 bfd_boolean want_reloc
;
7180 if (inst
.operands
[0].reg
== REG_PC
)
7181 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7183 inst
.instruction
|= inst
.operands
[0].reg
;
7184 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7185 it is for ARMv4t or earlier. */
7186 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7187 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7191 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7196 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7200 /* ARM v5TEJ. Jump to Jazelle code. */
7205 if (inst
.operands
[0].reg
== REG_PC
)
7206 as_tsktsk (_("use of r15 in bxj is not really useful"));
7208 inst
.instruction
|= inst
.operands
[0].reg
;
7211 /* Co-processor data operation:
7212 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7213 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7217 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7218 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7219 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7220 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7221 inst
.instruction
|= inst
.operands
[4].reg
;
7222 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7228 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7229 encode_arm_shifter_operand (1);
7232 /* Transfer between coprocessor and ARM registers.
7233 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7238 No special properties. */
7245 Rd
= inst
.operands
[2].reg
;
7248 if (inst
.instruction
== 0xee000010
7249 || inst
.instruction
== 0xfe000010)
7251 reject_bad_reg (Rd
);
7254 constraint (Rd
== REG_SP
, BAD_SP
);
7259 if (inst
.instruction
== 0xe000010)
7260 constraint (Rd
== REG_PC
, BAD_PC
);
7264 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7265 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7266 inst
.instruction
|= Rd
<< 12;
7267 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7268 inst
.instruction
|= inst
.operands
[4].reg
;
7269 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7272 /* Transfer between coprocessor register and pair of ARM registers.
7273 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7278 Two XScale instructions are special cases of these:
7280 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7281 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7283 Result unpredictable if Rd or Rn is R15. */
7290 Rd
= inst
.operands
[2].reg
;
7291 Rn
= inst
.operands
[3].reg
;
7295 reject_bad_reg (Rd
);
7296 reject_bad_reg (Rn
);
7300 constraint (Rd
== REG_PC
, BAD_PC
);
7301 constraint (Rn
== REG_PC
, BAD_PC
);
7304 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7305 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7306 inst
.instruction
|= Rd
<< 12;
7307 inst
.instruction
|= Rn
<< 16;
7308 inst
.instruction
|= inst
.operands
[4].reg
;
7314 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7315 if (inst
.operands
[1].present
)
7317 inst
.instruction
|= CPSI_MMOD
;
7318 inst
.instruction
|= inst
.operands
[1].imm
;
7325 inst
.instruction
|= inst
.operands
[0].imm
;
7331 /* There is no IT instruction in ARM mode. We
7332 process it to do the validation as if in
7333 thumb mode, just in case the code gets
7334 assembled for thumb using the unified syntax. */
7339 set_it_insn_type (IT_INSN
);
7340 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7341 now_it
.cc
= inst
.operands
[0].imm
;
7348 int base_reg
= inst
.operands
[0].reg
;
7349 int range
= inst
.operands
[1].imm
;
7351 inst
.instruction
|= base_reg
<< 16;
7352 inst
.instruction
|= range
;
7354 if (inst
.operands
[1].writeback
)
7355 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7357 if (inst
.operands
[0].writeback
)
7359 inst
.instruction
|= WRITE_BACK
;
7360 /* Check for unpredictable uses of writeback. */
7361 if (inst
.instruction
& LOAD_BIT
)
7363 /* Not allowed in LDM type 2. */
7364 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7365 && ((range
& (1 << REG_PC
)) == 0))
7366 as_warn (_("writeback of base register is UNPREDICTABLE"));
7367 /* Only allowed if base reg not in list for other types. */
7368 else if (range
& (1 << base_reg
))
7369 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7373 /* Not allowed for type 2. */
7374 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7375 as_warn (_("writeback of base register is UNPREDICTABLE"));
7376 /* Only allowed if base reg not in list, or first in list. */
7377 else if ((range
& (1 << base_reg
))
7378 && (range
& ((1 << base_reg
) - 1)))
7379 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7384 /* ARMv5TE load-consecutive (argument parse)
7393 constraint (inst
.operands
[0].reg
% 2 != 0,
7394 _("first destination register must be even"));
7395 constraint (inst
.operands
[1].present
7396 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7397 _("can only load two consecutive registers"));
7398 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7399 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7401 if (!inst
.operands
[1].present
)
7402 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7404 if (inst
.instruction
& LOAD_BIT
)
7406 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7407 register and the first register written; we have to diagnose
7408 overlap between the base and the second register written here. */
7410 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7411 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7412 as_warn (_("base register written back, and overlaps "
7413 "second destination register"));
7415 /* For an index-register load, the index register must not overlap the
7416 destination (even if not write-back). */
7417 else if (inst
.operands
[2].immisreg
7418 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7419 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7420 as_warn (_("index register overlaps destination register"));
7423 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7424 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7430 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7431 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7432 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7433 || inst
.operands
[1].negative
7434 /* This can arise if the programmer has written
7436 or if they have mistakenly used a register name as the last
7439 It is very difficult to distinguish between these two cases
7440 because "rX" might actually be a label. ie the register
7441 name has been occluded by a symbol of the same name. So we
7442 just generate a general 'bad addressing mode' type error
7443 message and leave it up to the programmer to discover the
7444 true cause and fix their mistake. */
7445 || (inst
.operands
[1].reg
== REG_PC
),
7448 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7449 || inst
.reloc
.exp
.X_add_number
!= 0,
7450 _("offset must be zero in ARM encoding"));
7452 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7453 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7454 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7460 constraint (inst
.operands
[0].reg
% 2 != 0,
7461 _("even register required"));
7462 constraint (inst
.operands
[1].present
7463 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7464 _("can only load two consecutive registers"));
7465 /* If op 1 were present and equal to PC, this function wouldn't
7466 have been called in the first place. */
7467 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7469 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7470 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7476 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7477 if (!inst
.operands
[1].isreg
)
7478 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7480 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7486 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7488 if (inst
.operands
[1].preind
)
7490 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7491 || inst
.reloc
.exp
.X_add_number
!= 0,
7492 _("this instruction requires a post-indexed address"));
7494 inst
.operands
[1].preind
= 0;
7495 inst
.operands
[1].postind
= 1;
7496 inst
.operands
[1].writeback
= 1;
7498 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7499 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7502 /* Halfword and signed-byte load/store operations. */
7507 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7508 if (!inst
.operands
[1].isreg
)
7509 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7511 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7517 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7519 if (inst
.operands
[1].preind
)
7521 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7522 || inst
.reloc
.exp
.X_add_number
!= 0,
7523 _("this instruction requires a post-indexed address"));
7525 inst
.operands
[1].preind
= 0;
7526 inst
.operands
[1].postind
= 1;
7527 inst
.operands
[1].writeback
= 1;
7529 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7530 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7533 /* Co-processor register load/store.
7534 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7538 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7539 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7540 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7546 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7547 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7548 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7549 && !(inst
.instruction
& 0x00400000))
7550 as_tsktsk (_("Rd and Rm should be different in mla"));
7552 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7553 inst
.instruction
|= inst
.operands
[1].reg
;
7554 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7555 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7561 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7562 encode_arm_shifter_operand (1);
7565 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7572 top
= (inst
.instruction
& 0x00400000) != 0;
7573 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7574 _(":lower16: not allowed this instruction"));
7575 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7576 _(":upper16: not allowed instruction"));
7577 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7578 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7580 imm
= inst
.reloc
.exp
.X_add_number
;
7581 /* The value is in two pieces: 0:11, 16:19. */
7582 inst
.instruction
|= (imm
& 0x00000fff);
7583 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7587 static void do_vfp_nsyn_opcode (const char *);
7590 do_vfp_nsyn_mrs (void)
7592 if (inst
.operands
[0].isvec
)
7594 if (inst
.operands
[1].reg
!= 1)
7595 first_error (_("operand 1 must be FPSCR"));
7596 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7597 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7598 do_vfp_nsyn_opcode ("fmstat");
7600 else if (inst
.operands
[1].isvec
)
7601 do_vfp_nsyn_opcode ("fmrx");
7609 do_vfp_nsyn_msr (void)
7611 if (inst
.operands
[0].isvec
)
7612 do_vfp_nsyn_opcode ("fmxr");
7622 unsigned Rt
= inst
.operands
[0].reg
;
7624 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7626 inst
.error
= BAD_SP
;
7630 /* APSR_ sets isvec. All other refs to PC are illegal. */
7631 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7633 inst
.error
= BAD_PC
;
7637 if (inst
.operands
[1].reg
!= 1)
7638 first_error (_("operand 1 must be FPSCR"));
7640 inst
.instruction
|= (Rt
<< 12);
7646 unsigned Rt
= inst
.operands
[1].reg
;
7649 reject_bad_reg (Rt
);
7650 else if (Rt
== REG_PC
)
7652 inst
.error
= BAD_PC
;
7656 if (inst
.operands
[0].reg
!= 1)
7657 first_error (_("operand 0 must be FPSCR"));
7659 inst
.instruction
|= (Rt
<< 12);
7665 if (do_vfp_nsyn_mrs () == SUCCESS
)
7668 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7669 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7671 _("'CPSR' or 'SPSR' expected"));
7672 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7673 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7676 /* Two possible forms:
7677 "{C|S}PSR_<field>, Rm",
7678 "{C|S}PSR_f, #expression". */
7683 if (do_vfp_nsyn_msr () == SUCCESS
)
7686 inst
.instruction
|= inst
.operands
[0].imm
;
7687 if (inst
.operands
[1].isreg
)
7688 inst
.instruction
|= inst
.operands
[1].reg
;
7691 inst
.instruction
|= INST_IMMEDIATE
;
7692 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7693 inst
.reloc
.pc_rel
= 0;
7700 if (!inst
.operands
[2].present
)
7701 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7702 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7703 inst
.instruction
|= inst
.operands
[1].reg
;
7704 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7706 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7707 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7708 as_tsktsk (_("Rd and Rm should be different in mul"));
7711 /* Long Multiply Parser
7712 UMULL RdLo, RdHi, Rm, Rs
7713 SMULL RdLo, RdHi, Rm, Rs
7714 UMLAL RdLo, RdHi, Rm, Rs
7715 SMLAL RdLo, RdHi, Rm, Rs. */
7720 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7721 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7722 inst
.instruction
|= inst
.operands
[2].reg
;
7723 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7725 /* rdhi and rdlo must be different. */
7726 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7727 as_tsktsk (_("rdhi and rdlo must be different"));
7729 /* rdhi, rdlo and rm must all be different before armv6. */
7730 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7731 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7732 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7733 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7739 if (inst
.operands
[0].present
7740 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7742 /* Architectural NOP hints are CPSR sets with no bits selected. */
7743 inst
.instruction
&= 0xf0000000;
7744 inst
.instruction
|= 0x0320f000;
7745 if (inst
.operands
[0].present
)
7746 inst
.instruction
|= inst
.operands
[0].imm
;
7750 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7751 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7752 Condition defaults to COND_ALWAYS.
7753 Error if Rd, Rn or Rm are R15. */
7758 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7759 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7760 inst
.instruction
|= inst
.operands
[2].reg
;
7761 if (inst
.operands
[3].present
)
7762 encode_arm_shift (3);
7765 /* ARM V6 PKHTB (Argument Parse). */
7770 if (!inst
.operands
[3].present
)
7772 /* If the shift specifier is omitted, turn the instruction
7773 into pkhbt rd, rm, rn. */
7774 inst
.instruction
&= 0xfff00010;
7775 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7776 inst
.instruction
|= inst
.operands
[1].reg
;
7777 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7781 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7782 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7783 inst
.instruction
|= inst
.operands
[2].reg
;
7784 encode_arm_shift (3);
7788 /* ARMv5TE: Preload-Cache
7792 Syntactically, like LDR with B=1, W=0, L=1. */
7797 constraint (!inst
.operands
[0].isreg
,
7798 _("'[' expected after PLD mnemonic"));
7799 constraint (inst
.operands
[0].postind
,
7800 _("post-indexed expression used in preload instruction"));
7801 constraint (inst
.operands
[0].writeback
,
7802 _("writeback used in preload instruction"));
7803 constraint (!inst
.operands
[0].preind
,
7804 _("unindexed addressing used in preload instruction"));
7805 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7808 /* ARMv7: PLI <addr_mode> */
7812 constraint (!inst
.operands
[0].isreg
,
7813 _("'[' expected after PLI mnemonic"));
7814 constraint (inst
.operands
[0].postind
,
7815 _("post-indexed expression used in preload instruction"));
7816 constraint (inst
.operands
[0].writeback
,
7817 _("writeback used in preload instruction"));
7818 constraint (!inst
.operands
[0].preind
,
7819 _("unindexed addressing used in preload instruction"));
7820 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7821 inst
.instruction
&= ~PRE_INDEX
;
7827 inst
.operands
[1] = inst
.operands
[0];
7828 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7829 inst
.operands
[0].isreg
= 1;
7830 inst
.operands
[0].writeback
= 1;
7831 inst
.operands
[0].reg
= REG_SP
;
7835 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7836 word at the specified address and the following word
7838 Unconditionally executed.
7839 Error if Rn is R15. */
7844 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7845 if (inst
.operands
[0].writeback
)
7846 inst
.instruction
|= WRITE_BACK
;
7849 /* ARM V6 ssat (argument parse). */
7854 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7855 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7856 inst
.instruction
|= inst
.operands
[2].reg
;
7858 if (inst
.operands
[3].present
)
7859 encode_arm_shift (3);
7862 /* ARM V6 usat (argument parse). */
7867 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7868 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7869 inst
.instruction
|= inst
.operands
[2].reg
;
7871 if (inst
.operands
[3].present
)
7872 encode_arm_shift (3);
7875 /* ARM V6 ssat16 (argument parse). */
7880 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7881 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7882 inst
.instruction
|= inst
.operands
[2].reg
;
7888 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7889 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7890 inst
.instruction
|= inst
.operands
[2].reg
;
7893 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7894 preserving the other bits.
7896 setend <endian_specifier>, where <endian_specifier> is either
7902 if (inst
.operands
[0].imm
)
7903 inst
.instruction
|= 0x200;
7909 unsigned int Rm
= (inst
.operands
[1].present
7910 ? inst
.operands
[1].reg
7911 : inst
.operands
[0].reg
);
7913 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7914 inst
.instruction
|= Rm
;
7915 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7917 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7918 inst
.instruction
|= SHIFT_BY_REG
;
7921 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7927 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7928 inst
.reloc
.pc_rel
= 0;
7934 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7935 inst
.reloc
.pc_rel
= 0;
7938 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7939 SMLAxy{cond} Rd,Rm,Rs,Rn
7940 SMLAWy{cond} Rd,Rm,Rs,Rn
7941 Error if any register is R15. */
7946 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7947 inst
.instruction
|= inst
.operands
[1].reg
;
7948 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7949 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7952 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7953 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7954 Error if any register is R15.
7955 Warning if Rdlo == Rdhi. */
7960 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7961 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7962 inst
.instruction
|= inst
.operands
[2].reg
;
7963 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7965 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7966 as_tsktsk (_("rdhi and rdlo must be different"));
7969 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7970 SMULxy{cond} Rd,Rm,Rs
7971 Error if any register is R15. */
7976 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7977 inst
.instruction
|= inst
.operands
[1].reg
;
7978 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7981 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7982 the same for both ARM and Thumb-2. */
7989 if (inst
.operands
[0].present
)
7991 reg
= inst
.operands
[0].reg
;
7992 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
7997 inst
.instruction
|= reg
<< 16;
7998 inst
.instruction
|= inst
.operands
[1].imm
;
7999 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8000 inst
.instruction
|= WRITE_BACK
;
8003 /* ARM V6 strex (argument parse). */
8008 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8009 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8010 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8011 || inst
.operands
[2].negative
8012 /* See comment in do_ldrex(). */
8013 || (inst
.operands
[2].reg
== REG_PC
),
8016 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8017 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8019 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8020 || inst
.reloc
.exp
.X_add_number
!= 0,
8021 _("offset must be zero in ARM encoding"));
8023 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8024 inst
.instruction
|= inst
.operands
[1].reg
;
8025 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8026 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8032 constraint (inst
.operands
[1].reg
% 2 != 0,
8033 _("even register required"));
8034 constraint (inst
.operands
[2].present
8035 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8036 _("can only store two consecutive registers"));
8037 /* If op 2 were present and equal to PC, this function wouldn't
8038 have been called in the first place. */
8039 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8041 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8042 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8043 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8046 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8047 inst
.instruction
|= inst
.operands
[1].reg
;
8048 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8051 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8052 extends it to 32-bits, and adds the result to a value in another
8053 register. You can specify a rotation by 0, 8, 16, or 24 bits
8054 before extracting the 16-bit value.
8055 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8056 Condition defaults to COND_ALWAYS.
8057 Error if any register uses R15. */
8062 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8063 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8064 inst
.instruction
|= inst
.operands
[2].reg
;
8065 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8070 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8071 Condition defaults to COND_ALWAYS.
8072 Error if any register uses R15. */
8077 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8078 inst
.instruction
|= inst
.operands
[1].reg
;
8079 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8082 /* VFP instructions. In a logical order: SP variant first, monad
8083 before dyad, arithmetic then move then load/store. */
8086 do_vfp_sp_monadic (void)
8088 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8089 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8093 do_vfp_sp_dyadic (void)
8095 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8096 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8097 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8101 do_vfp_sp_compare_z (void)
8103 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8107 do_vfp_dp_sp_cvt (void)
8109 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8110 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8114 do_vfp_sp_dp_cvt (void)
8116 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8117 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8121 do_vfp_reg_from_sp (void)
8123 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8124 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8128 do_vfp_reg2_from_sp2 (void)
8130 constraint (inst
.operands
[2].imm
!= 2,
8131 _("only two consecutive VFP SP registers allowed here"));
8132 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8133 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8134 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8138 do_vfp_sp_from_reg (void)
8140 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8141 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8145 do_vfp_sp2_from_reg2 (void)
8147 constraint (inst
.operands
[0].imm
!= 2,
8148 _("only two consecutive VFP SP registers allowed here"));
8149 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8150 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8151 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8155 do_vfp_sp_ldst (void)
8157 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8158 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8162 do_vfp_dp_ldst (void)
8164 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8165 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8170 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8172 if (inst
.operands
[0].writeback
)
8173 inst
.instruction
|= WRITE_BACK
;
8175 constraint (ldstm_type
!= VFP_LDSTMIA
,
8176 _("this addressing mode requires base-register writeback"));
8177 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8178 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8179 inst
.instruction
|= inst
.operands
[1].imm
;
8183 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8187 if (inst
.operands
[0].writeback
)
8188 inst
.instruction
|= WRITE_BACK
;
8190 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8191 _("this addressing mode requires base-register writeback"));
8193 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8194 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8196 count
= inst
.operands
[1].imm
<< 1;
8197 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8200 inst
.instruction
|= count
;
8204 do_vfp_sp_ldstmia (void)
8206 vfp_sp_ldstm (VFP_LDSTMIA
);
8210 do_vfp_sp_ldstmdb (void)
8212 vfp_sp_ldstm (VFP_LDSTMDB
);
8216 do_vfp_dp_ldstmia (void)
8218 vfp_dp_ldstm (VFP_LDSTMIA
);
8222 do_vfp_dp_ldstmdb (void)
8224 vfp_dp_ldstm (VFP_LDSTMDB
);
8228 do_vfp_xp_ldstmia (void)
8230 vfp_dp_ldstm (VFP_LDSTMIAX
);
8234 do_vfp_xp_ldstmdb (void)
8236 vfp_dp_ldstm (VFP_LDSTMDBX
);
8240 do_vfp_dp_rd_rm (void)
8242 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8243 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8247 do_vfp_dp_rn_rd (void)
8249 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8250 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8254 do_vfp_dp_rd_rn (void)
8256 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8257 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8261 do_vfp_dp_rd_rn_rm (void)
8263 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8264 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8265 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8271 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8275 do_vfp_dp_rm_rd_rn (void)
8277 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8278 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8279 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8282 /* VFPv3 instructions. */
8284 do_vfp_sp_const (void)
8286 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8287 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8288 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8292 do_vfp_dp_const (void)
8294 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8295 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8296 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8300 vfp_conv (int srcsize
)
8302 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8303 inst
.instruction
|= (immbits
& 1) << 5;
8304 inst
.instruction
|= (immbits
>> 1);
8308 do_vfp_sp_conv_16 (void)
8310 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8315 do_vfp_dp_conv_16 (void)
8317 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8322 do_vfp_sp_conv_32 (void)
8324 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8329 do_vfp_dp_conv_32 (void)
8331 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8335 /* FPA instructions. Also in a logical order. */
8340 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8341 inst
.instruction
|= inst
.operands
[1].reg
;
8345 do_fpa_ldmstm (void)
8347 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8348 switch (inst
.operands
[1].imm
)
8350 case 1: inst
.instruction
|= CP_T_X
; break;
8351 case 2: inst
.instruction
|= CP_T_Y
; break;
8352 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8357 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8359 /* The instruction specified "ea" or "fd", so we can only accept
8360 [Rn]{!}. The instruction does not really support stacking or
8361 unstacking, so we have to emulate these by setting appropriate
8362 bits and offsets. */
8363 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8364 || inst
.reloc
.exp
.X_add_number
!= 0,
8365 _("this instruction does not support indexing"));
8367 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8368 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8370 if (!(inst
.instruction
& INDEX_UP
))
8371 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8373 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8375 inst
.operands
[2].preind
= 0;
8376 inst
.operands
[2].postind
= 1;
8380 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8383 /* iWMMXt instructions: strictly in alphabetical order. */
8386 do_iwmmxt_tandorc (void)
8388 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8392 do_iwmmxt_textrc (void)
8394 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8395 inst
.instruction
|= inst
.operands
[1].imm
;
8399 do_iwmmxt_textrm (void)
8401 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8402 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8403 inst
.instruction
|= inst
.operands
[2].imm
;
8407 do_iwmmxt_tinsr (void)
8409 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8410 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8411 inst
.instruction
|= inst
.operands
[2].imm
;
8415 do_iwmmxt_tmia (void)
8417 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8418 inst
.instruction
|= inst
.operands
[1].reg
;
8419 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8423 do_iwmmxt_waligni (void)
8425 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8426 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8427 inst
.instruction
|= inst
.operands
[2].reg
;
8428 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8432 do_iwmmxt_wmerge (void)
8434 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8435 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8436 inst
.instruction
|= inst
.operands
[2].reg
;
8437 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8441 do_iwmmxt_wmov (void)
8443 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8444 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8445 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8446 inst
.instruction
|= inst
.operands
[1].reg
;
8450 do_iwmmxt_wldstbh (void)
8453 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8455 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8457 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8458 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8462 do_iwmmxt_wldstw (void)
8464 /* RIWR_RIWC clears .isreg for a control register. */
8465 if (!inst
.operands
[0].isreg
)
8467 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8468 inst
.instruction
|= 0xf0000000;
8471 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8472 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8476 do_iwmmxt_wldstd (void)
8478 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8479 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8480 && inst
.operands
[1].immisreg
)
8482 inst
.instruction
&= ~0x1a000ff;
8483 inst
.instruction
|= (0xf << 28);
8484 if (inst
.operands
[1].preind
)
8485 inst
.instruction
|= PRE_INDEX
;
8486 if (!inst
.operands
[1].negative
)
8487 inst
.instruction
|= INDEX_UP
;
8488 if (inst
.operands
[1].writeback
)
8489 inst
.instruction
|= WRITE_BACK
;
8490 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8491 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8492 inst
.instruction
|= inst
.operands
[1].imm
;
8495 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8499 do_iwmmxt_wshufh (void)
8501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8502 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8503 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8504 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8508 do_iwmmxt_wzero (void)
8510 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8511 inst
.instruction
|= inst
.operands
[0].reg
;
8512 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8513 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8517 do_iwmmxt_wrwrwr_or_imm5 (void)
8519 if (inst
.operands
[2].isreg
)
8522 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8523 _("immediate operand requires iWMMXt2"));
8525 if (inst
.operands
[2].imm
== 0)
8527 switch ((inst
.instruction
>> 20) & 0xf)
8533 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8534 inst
.operands
[2].imm
= 16;
8535 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8541 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8542 inst
.operands
[2].imm
= 32;
8543 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8550 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8552 wrn
= (inst
.instruction
>> 16) & 0xf;
8553 inst
.instruction
&= 0xff0fff0f;
8554 inst
.instruction
|= wrn
;
8555 /* Bail out here; the instruction is now assembled. */
8560 /* Map 32 -> 0, etc. */
8561 inst
.operands
[2].imm
&= 0x1f;
8562 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8566 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8567 operations first, then control, shift, and load/store. */
8569 /* Insns like "foo X,Y,Z". */
8572 do_mav_triple (void)
8574 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8575 inst
.instruction
|= inst
.operands
[1].reg
;
8576 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8579 /* Insns like "foo W,X,Y,Z".
8580 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8585 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8586 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8587 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8588 inst
.instruction
|= inst
.operands
[3].reg
;
8591 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8595 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8598 /* Maverick shift immediate instructions.
8599 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8600 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8605 int imm
= inst
.operands
[2].imm
;
8607 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8608 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8610 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8611 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8612 Bit 4 should be 0. */
8613 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8615 inst
.instruction
|= imm
;
8618 /* XScale instructions. Also sorted arithmetic before move. */
8620 /* Xscale multiply-accumulate (argument parse)
8623 MIAxycc acc0,Rm,Rs. */
8628 inst
.instruction
|= inst
.operands
[1].reg
;
8629 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8632 /* Xscale move-accumulator-register (argument parse)
8634 MARcc acc0,RdLo,RdHi. */
8639 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8640 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8643 /* Xscale move-register-accumulator (argument parse)
8645 MRAcc RdLo,RdHi,acc0. */
8650 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8651 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8652 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8655 /* Encoding functions relevant only to Thumb. */
8657 /* inst.operands[i] is a shifted-register operand; encode
8658 it into inst.instruction in the format used by Thumb32. */
8661 encode_thumb32_shifted_operand (int i
)
8663 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8664 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8666 constraint (inst
.operands
[i
].immisreg
,
8667 _("shift by register not allowed in thumb mode"));
8668 inst
.instruction
|= inst
.operands
[i
].reg
;
8669 if (shift
== SHIFT_RRX
)
8670 inst
.instruction
|= SHIFT_ROR
<< 4;
8673 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8674 _("expression too complex"));
8676 constraint (value
> 32
8677 || (value
== 32 && (shift
== SHIFT_LSL
8678 || shift
== SHIFT_ROR
)),
8679 _("shift expression is too large"));
8683 else if (value
== 32)
8686 inst
.instruction
|= shift
<< 4;
8687 inst
.instruction
|= (value
& 0x1c) << 10;
8688 inst
.instruction
|= (value
& 0x03) << 6;
8693 /* inst.operands[i] was set up by parse_address. Encode it into a
8694 Thumb32 format load or store instruction. Reject forms that cannot
8695 be used with such instructions. If is_t is true, reject forms that
8696 cannot be used with a T instruction; if is_d is true, reject forms
8697 that cannot be used with a D instruction. */
8700 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8702 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8704 constraint (!inst
.operands
[i
].isreg
,
8705 _("Instruction does not support =N addresses"));
8707 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8708 if (inst
.operands
[i
].immisreg
)
8710 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8711 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8712 constraint (inst
.operands
[i
].negative
,
8713 _("Thumb does not support negative register indexing"));
8714 constraint (inst
.operands
[i
].postind
,
8715 _("Thumb does not support register post-indexing"));
8716 constraint (inst
.operands
[i
].writeback
,
8717 _("Thumb does not support register indexing with writeback"));
8718 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8719 _("Thumb supports only LSL in shifted register indexing"));
8721 inst
.instruction
|= inst
.operands
[i
].imm
;
8722 if (inst
.operands
[i
].shifted
)
8724 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8725 _("expression too complex"));
8726 constraint (inst
.reloc
.exp
.X_add_number
< 0
8727 || inst
.reloc
.exp
.X_add_number
> 3,
8728 _("shift out of range"));
8729 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8731 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8733 else if (inst
.operands
[i
].preind
)
8735 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8736 _("cannot use writeback with PC-relative addressing"));
8737 constraint (is_t
&& inst
.operands
[i
].writeback
,
8738 _("cannot use writeback with this instruction"));
8742 inst
.instruction
|= 0x01000000;
8743 if (inst
.operands
[i
].writeback
)
8744 inst
.instruction
|= 0x00200000;
8748 inst
.instruction
|= 0x00000c00;
8749 if (inst
.operands
[i
].writeback
)
8750 inst
.instruction
|= 0x00000100;
8752 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8754 else if (inst
.operands
[i
].postind
)
8756 gas_assert (inst
.operands
[i
].writeback
);
8757 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8758 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8761 inst
.instruction
|= 0x00200000;
8763 inst
.instruction
|= 0x00000900;
8764 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8766 else /* unindexed - only for coprocessor */
8767 inst
.error
= _("instruction does not accept unindexed addressing");
8770 /* Table of Thumb instructions which exist in both 16- and 32-bit
8771 encodings (the latter only in post-V6T2 cores). The index is the
8772 value used in the insns table below. When there is more than one
8773 possible 16-bit encoding for the instruction, this table always
8775 Also contains several pseudo-instructions used during relaxation. */
8776 #define T16_32_TAB \
8777 X(_adc, 4140, eb400000), \
8778 X(_adcs, 4140, eb500000), \
8779 X(_add, 1c00, eb000000), \
8780 X(_adds, 1c00, eb100000), \
8781 X(_addi, 0000, f1000000), \
8782 X(_addis, 0000, f1100000), \
8783 X(_add_pc,000f, f20f0000), \
8784 X(_add_sp,000d, f10d0000), \
8785 X(_adr, 000f, f20f0000), \
8786 X(_and, 4000, ea000000), \
8787 X(_ands, 4000, ea100000), \
8788 X(_asr, 1000, fa40f000), \
8789 X(_asrs, 1000, fa50f000), \
8790 X(_b, e000, f000b000), \
8791 X(_bcond, d000, f0008000), \
8792 X(_bic, 4380, ea200000), \
8793 X(_bics, 4380, ea300000), \
8794 X(_cmn, 42c0, eb100f00), \
8795 X(_cmp, 2800, ebb00f00), \
8796 X(_cpsie, b660, f3af8400), \
8797 X(_cpsid, b670, f3af8600), \
8798 X(_cpy, 4600, ea4f0000), \
8799 X(_dec_sp,80dd, f1ad0d00), \
8800 X(_eor, 4040, ea800000), \
8801 X(_eors, 4040, ea900000), \
8802 X(_inc_sp,00dd, f10d0d00), \
8803 X(_ldmia, c800, e8900000), \
8804 X(_ldr, 6800, f8500000), \
8805 X(_ldrb, 7800, f8100000), \
8806 X(_ldrh, 8800, f8300000), \
8807 X(_ldrsb, 5600, f9100000), \
8808 X(_ldrsh, 5e00, f9300000), \
8809 X(_ldr_pc,4800, f85f0000), \
8810 X(_ldr_pc2,4800, f85f0000), \
8811 X(_ldr_sp,9800, f85d0000), \
8812 X(_lsl, 0000, fa00f000), \
8813 X(_lsls, 0000, fa10f000), \
8814 X(_lsr, 0800, fa20f000), \
8815 X(_lsrs, 0800, fa30f000), \
8816 X(_mov, 2000, ea4f0000), \
8817 X(_movs, 2000, ea5f0000), \
8818 X(_mul, 4340, fb00f000), \
8819 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8820 X(_mvn, 43c0, ea6f0000), \
8821 X(_mvns, 43c0, ea7f0000), \
8822 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8823 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8824 X(_orr, 4300, ea400000), \
8825 X(_orrs, 4300, ea500000), \
8826 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8827 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8828 X(_rev, ba00, fa90f080), \
8829 X(_rev16, ba40, fa90f090), \
8830 X(_revsh, bac0, fa90f0b0), \
8831 X(_ror, 41c0, fa60f000), \
8832 X(_rors, 41c0, fa70f000), \
8833 X(_sbc, 4180, eb600000), \
8834 X(_sbcs, 4180, eb700000), \
8835 X(_stmia, c000, e8800000), \
8836 X(_str, 6000, f8400000), \
8837 X(_strb, 7000, f8000000), \
8838 X(_strh, 8000, f8200000), \
8839 X(_str_sp,9000, f84d0000), \
8840 X(_sub, 1e00, eba00000), \
8841 X(_subs, 1e00, ebb00000), \
8842 X(_subi, 8000, f1a00000), \
8843 X(_subis, 8000, f1b00000), \
8844 X(_sxtb, b240, fa4ff080), \
8845 X(_sxth, b200, fa0ff080), \
8846 X(_tst, 4200, ea100f00), \
8847 X(_uxtb, b2c0, fa5ff080), \
8848 X(_uxth, b280, fa1ff080), \
8849 X(_nop, bf00, f3af8000), \
8850 X(_yield, bf10, f3af8001), \
8851 X(_wfe, bf20, f3af8002), \
8852 X(_wfi, bf30, f3af8003), \
8853 X(_sev, bf40, f3af8004),
8855 /* To catch errors in encoding functions, the codes are all offset by
8856 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8857 as 16-bit instructions. */
8858 #define X(a,b,c) T_MNEM##a
8859 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8862 #define X(a,b,c) 0x##b
8863 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8864 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8867 #define X(a,b,c) 0x##c
8868 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8869 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8870 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8874 /* Thumb instruction encoders, in alphabetical order. */
8879 do_t_add_sub_w (void)
8883 Rd
= inst
.operands
[0].reg
;
8884 Rn
= inst
.operands
[1].reg
;
8886 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
8887 is the SP-{plus,minus}-immediate form of the instruction. */
8889 constraint (Rd
== REG_PC
, BAD_PC
);
8891 reject_bad_reg (Rd
);
8893 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8894 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8897 /* Parse an add or subtract instruction. We get here with inst.instruction
8898 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8905 Rd
= inst
.operands
[0].reg
;
8906 Rs
= (inst
.operands
[1].present
8907 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8908 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8911 set_it_insn_type_last ();
8919 flags
= (inst
.instruction
== T_MNEM_adds
8920 || inst
.instruction
== T_MNEM_subs
);
8922 narrow
= !in_it_block ();
8924 narrow
= in_it_block ();
8925 if (!inst
.operands
[2].isreg
)
8929 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8931 add
= (inst
.instruction
== T_MNEM_add
8932 || inst
.instruction
== T_MNEM_adds
);
8934 if (inst
.size_req
!= 4)
8936 /* Attempt to use a narrow opcode, with relaxation if
8938 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8939 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8940 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8941 opcode
= T_MNEM_add_sp
;
8942 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8943 opcode
= T_MNEM_add_pc
;
8944 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8947 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8949 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8953 inst
.instruction
= THUMB_OP16(opcode
);
8954 inst
.instruction
|= (Rd
<< 4) | Rs
;
8955 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8956 if (inst
.size_req
!= 2)
8957 inst
.relax
= opcode
;
8960 constraint (inst
.size_req
== 2, BAD_HIREG
);
8962 if (inst
.size_req
== 4
8963 || (inst
.size_req
!= 2 && !opcode
))
8967 constraint (add
, BAD_PC
);
8968 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8969 _("only SUBS PC, LR, #const allowed"));
8970 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8971 _("expression too complex"));
8972 constraint (inst
.reloc
.exp
.X_add_number
< 0
8973 || inst
.reloc
.exp
.X_add_number
> 0xff,
8974 _("immediate value out of range"));
8975 inst
.instruction
= T2_SUBS_PC_LR
8976 | inst
.reloc
.exp
.X_add_number
;
8977 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8980 else if (Rs
== REG_PC
)
8982 /* Always use addw/subw. */
8983 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8984 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8988 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8989 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8992 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8994 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8996 inst
.instruction
|= Rd
<< 8;
8997 inst
.instruction
|= Rs
<< 16;
9002 Rn
= inst
.operands
[2].reg
;
9003 /* See if we can do this with a 16-bit instruction. */
9004 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9006 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9011 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9012 || inst
.instruction
== T_MNEM_add
)
9015 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9019 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9021 /* Thumb-1 cores (except v6-M) require at least one high
9022 register in a narrow non flag setting add. */
9023 if (Rd
> 7 || Rn
> 7
9024 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9025 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9032 inst
.instruction
= T_OPCODE_ADD_HI
;
9033 inst
.instruction
|= (Rd
& 8) << 4;
9034 inst
.instruction
|= (Rd
& 7);
9035 inst
.instruction
|= Rn
<< 3;
9041 constraint (Rd
== REG_PC
, BAD_PC
);
9042 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9043 constraint (Rs
== REG_PC
, BAD_PC
);
9044 reject_bad_reg (Rn
);
9046 /* If we get here, it can't be done in 16 bits. */
9047 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9048 _("shift must be constant"));
9049 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9050 inst
.instruction
|= Rd
<< 8;
9051 inst
.instruction
|= Rs
<< 16;
9052 encode_thumb32_shifted_operand (2);
9057 constraint (inst
.instruction
== T_MNEM_adds
9058 || inst
.instruction
== T_MNEM_subs
,
9061 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9063 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9064 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9067 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9069 inst
.instruction
|= (Rd
<< 4) | Rs
;
9070 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9074 Rn
= inst
.operands
[2].reg
;
9075 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9077 /* We now have Rd, Rs, and Rn set to registers. */
9078 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9080 /* Can't do this for SUB. */
9081 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9082 inst
.instruction
= T_OPCODE_ADD_HI
;
9083 inst
.instruction
|= (Rd
& 8) << 4;
9084 inst
.instruction
|= (Rd
& 7);
9086 inst
.instruction
|= Rn
<< 3;
9088 inst
.instruction
|= Rs
<< 3;
9090 constraint (1, _("dest must overlap one source register"));
9094 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9095 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9096 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9106 Rd
= inst
.operands
[0].reg
;
9107 reject_bad_reg (Rd
);
9109 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9111 /* Defer to section relaxation. */
9112 inst
.relax
= inst
.instruction
;
9113 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9114 inst
.instruction
|= Rd
<< 4;
9116 else if (unified_syntax
&& inst
.size_req
!= 2)
9118 /* Generate a 32-bit opcode. */
9119 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9120 inst
.instruction
|= Rd
<< 8;
9121 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9122 inst
.reloc
.pc_rel
= 1;
9126 /* Generate a 16-bit opcode. */
9127 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9128 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9129 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9130 inst
.reloc
.pc_rel
= 1;
9132 inst
.instruction
|= Rd
<< 4;
9136 /* Arithmetic instructions for which there is just one 16-bit
9137 instruction encoding, and it allows only two low registers.
9138 For maximal compatibility with ARM syntax, we allow three register
9139 operands even when Thumb-32 instructions are not available, as long
9140 as the first two are identical. For instance, both "sbc r0,r1" and
9141 "sbc r0,r0,r1" are allowed. */
9147 Rd
= inst
.operands
[0].reg
;
9148 Rs
= (inst
.operands
[1].present
9149 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9150 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9151 Rn
= inst
.operands
[2].reg
;
9153 reject_bad_reg (Rd
);
9154 reject_bad_reg (Rs
);
9155 if (inst
.operands
[2].isreg
)
9156 reject_bad_reg (Rn
);
9160 if (!inst
.operands
[2].isreg
)
9162 /* For an immediate, we always generate a 32-bit opcode;
9163 section relaxation will shrink it later if possible. */
9164 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9165 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9166 inst
.instruction
|= Rd
<< 8;
9167 inst
.instruction
|= Rs
<< 16;
9168 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9174 /* See if we can do this with a 16-bit instruction. */
9175 if (THUMB_SETS_FLAGS (inst
.instruction
))
9176 narrow
= !in_it_block ();
9178 narrow
= in_it_block ();
9180 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9182 if (inst
.operands
[2].shifted
)
9184 if (inst
.size_req
== 4)
9190 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9191 inst
.instruction
|= Rd
;
9192 inst
.instruction
|= Rn
<< 3;
9196 /* If we get here, it can't be done in 16 bits. */
9197 constraint (inst
.operands
[2].shifted
9198 && inst
.operands
[2].immisreg
,
9199 _("shift must be constant"));
9200 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9201 inst
.instruction
|= Rd
<< 8;
9202 inst
.instruction
|= Rs
<< 16;
9203 encode_thumb32_shifted_operand (2);
9208 /* On its face this is a lie - the instruction does set the
9209 flags. However, the only supported mnemonic in this mode
9211 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9213 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9214 _("unshifted register required"));
9215 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9216 constraint (Rd
!= Rs
,
9217 _("dest and source1 must be the same register"));
9219 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9220 inst
.instruction
|= Rd
;
9221 inst
.instruction
|= Rn
<< 3;
9225 /* Similarly, but for instructions where the arithmetic operation is
9226 commutative, so we can allow either of them to be different from
9227 the destination operand in a 16-bit instruction. For instance, all
9228 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9235 Rd
= inst
.operands
[0].reg
;
9236 Rs
= (inst
.operands
[1].present
9237 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9238 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9239 Rn
= inst
.operands
[2].reg
;
9241 reject_bad_reg (Rd
);
9242 reject_bad_reg (Rs
);
9243 if (inst
.operands
[2].isreg
)
9244 reject_bad_reg (Rn
);
9248 if (!inst
.operands
[2].isreg
)
9250 /* For an immediate, we always generate a 32-bit opcode;
9251 section relaxation will shrink it later if possible. */
9252 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9253 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9254 inst
.instruction
|= Rd
<< 8;
9255 inst
.instruction
|= Rs
<< 16;
9256 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9262 /* See if we can do this with a 16-bit instruction. */
9263 if (THUMB_SETS_FLAGS (inst
.instruction
))
9264 narrow
= !in_it_block ();
9266 narrow
= in_it_block ();
9268 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9270 if (inst
.operands
[2].shifted
)
9272 if (inst
.size_req
== 4)
9279 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9280 inst
.instruction
|= Rd
;
9281 inst
.instruction
|= Rn
<< 3;
9286 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9287 inst
.instruction
|= Rd
;
9288 inst
.instruction
|= Rs
<< 3;
9293 /* If we get here, it can't be done in 16 bits. */
9294 constraint (inst
.operands
[2].shifted
9295 && inst
.operands
[2].immisreg
,
9296 _("shift must be constant"));
9297 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9298 inst
.instruction
|= Rd
<< 8;
9299 inst
.instruction
|= Rs
<< 16;
9300 encode_thumb32_shifted_operand (2);
9305 /* On its face this is a lie - the instruction does set the
9306 flags. However, the only supported mnemonic in this mode
9308 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9310 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9311 _("unshifted register required"));
9312 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9314 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9315 inst
.instruction
|= Rd
;
9318 inst
.instruction
|= Rn
<< 3;
9320 inst
.instruction
|= Rs
<< 3;
9322 constraint (1, _("dest must overlap one source register"));
9329 if (inst
.operands
[0].present
)
9331 constraint ((inst
.instruction
& 0xf0) != 0x40
9332 && inst
.operands
[0].imm
!= 0xf,
9333 _("bad barrier type"));
9334 inst
.instruction
|= inst
.operands
[0].imm
;
9337 inst
.instruction
|= 0xf;
9344 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9345 constraint (msb
> 32, _("bit-field extends past end of register"));
9346 /* The instruction encoding stores the LSB and MSB,
9347 not the LSB and width. */
9348 Rd
= inst
.operands
[0].reg
;
9349 reject_bad_reg (Rd
);
9350 inst
.instruction
|= Rd
<< 8;
9351 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9352 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9353 inst
.instruction
|= msb
- 1;
9362 Rd
= inst
.operands
[0].reg
;
9363 reject_bad_reg (Rd
);
9365 /* #0 in second position is alternative syntax for bfc, which is
9366 the same instruction but with REG_PC in the Rm field. */
9367 if (!inst
.operands
[1].isreg
)
9371 Rn
= inst
.operands
[1].reg
;
9372 reject_bad_reg (Rn
);
9375 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9376 constraint (msb
> 32, _("bit-field extends past end of register"));
9377 /* The instruction encoding stores the LSB and MSB,
9378 not the LSB and width. */
9379 inst
.instruction
|= Rd
<< 8;
9380 inst
.instruction
|= Rn
<< 16;
9381 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9382 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9383 inst
.instruction
|= msb
- 1;
9391 Rd
= inst
.operands
[0].reg
;
9392 Rn
= inst
.operands
[1].reg
;
9394 reject_bad_reg (Rd
);
9395 reject_bad_reg (Rn
);
9397 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9398 _("bit-field extends past end of register"));
9399 inst
.instruction
|= Rd
<< 8;
9400 inst
.instruction
|= Rn
<< 16;
9401 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9402 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9403 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9406 /* ARM V5 Thumb BLX (argument parse)
9407 BLX <target_addr> which is BLX(1)
9408 BLX <Rm> which is BLX(2)
9409 Unfortunately, there are two different opcodes for this mnemonic.
9410 So, the insns[].value is not used, and the code here zaps values
9411 into inst.instruction.
9413 ??? How to take advantage of the additional two bits of displacement
9414 available in Thumb32 mode? Need new relocation? */
9419 set_it_insn_type_last ();
9421 if (inst
.operands
[0].isreg
)
9423 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9424 /* We have a register, so this is BLX(2). */
9425 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9429 /* No register. This must be BLX(1). */
9430 inst
.instruction
= 0xf000e800;
9431 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9432 inst
.reloc
.pc_rel
= 1;
9443 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9447 /* Conditional branches inside IT blocks are encoded as unconditional
9454 if (cond
!= COND_ALWAYS
)
9455 opcode
= T_MNEM_bcond
;
9457 opcode
= inst
.instruction
;
9459 if (unified_syntax
&& inst
.size_req
== 4)
9461 inst
.instruction
= THUMB_OP32(opcode
);
9462 if (cond
== COND_ALWAYS
)
9463 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9466 gas_assert (cond
!= 0xF);
9467 inst
.instruction
|= cond
<< 22;
9468 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9473 inst
.instruction
= THUMB_OP16(opcode
);
9474 if (cond
== COND_ALWAYS
)
9475 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9478 inst
.instruction
|= cond
<< 8;
9479 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9481 /* Allow section relaxation. */
9482 if (unified_syntax
&& inst
.size_req
!= 2)
9483 inst
.relax
= opcode
;
9486 inst
.reloc
.pc_rel
= 1;
9492 constraint (inst
.cond
!= COND_ALWAYS
,
9493 _("instruction is always unconditional"));
9494 if (inst
.operands
[0].present
)
9496 constraint (inst
.operands
[0].imm
> 255,
9497 _("immediate value out of range"));
9498 inst
.instruction
|= inst
.operands
[0].imm
;
9499 set_it_insn_type (NEUTRAL_IT_INSN
);
9504 do_t_branch23 (void)
9506 set_it_insn_type_last ();
9507 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9508 inst
.reloc
.pc_rel
= 1;
9510 #if defined(OBJ_COFF)
9511 /* If the destination of the branch is a defined symbol which does not have
9512 the THUMB_FUNC attribute, then we must be calling a function which has
9513 the (interfacearm) attribute. We look for the Thumb entry point to that
9514 function and change the branch to refer to that function instead. */
9515 if ( inst
.reloc
.exp
.X_op
== O_symbol
9516 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9517 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9518 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9519 inst
.reloc
.exp
.X_add_symbol
=
9520 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9527 set_it_insn_type_last ();
9528 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9529 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9530 should cause the alignment to be checked once it is known. This is
9531 because BX PC only works if the instruction is word aligned. */
9539 set_it_insn_type_last ();
9540 Rm
= inst
.operands
[0].reg
;
9541 reject_bad_reg (Rm
);
9542 inst
.instruction
|= Rm
<< 16;
9551 Rd
= inst
.operands
[0].reg
;
9552 Rm
= inst
.operands
[1].reg
;
9554 reject_bad_reg (Rd
);
9555 reject_bad_reg (Rm
);
9557 inst
.instruction
|= Rd
<< 8;
9558 inst
.instruction
|= Rm
<< 16;
9559 inst
.instruction
|= Rm
;
9565 set_it_insn_type (OUTSIDE_IT_INSN
);
9566 inst
.instruction
|= inst
.operands
[0].imm
;
9572 set_it_insn_type (OUTSIDE_IT_INSN
);
9574 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9575 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9577 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9578 inst
.instruction
= 0xf3af8000;
9579 inst
.instruction
|= imod
<< 9;
9580 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9581 if (inst
.operands
[1].present
)
9582 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9586 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9587 && (inst
.operands
[0].imm
& 4),
9588 _("selected processor does not support 'A' form "
9589 "of this instruction"));
9590 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9591 _("Thumb does not support the 2-argument "
9592 "form of this instruction"));
9593 inst
.instruction
|= inst
.operands
[0].imm
;
9597 /* THUMB CPY instruction (argument parse). */
9602 if (inst
.size_req
== 4)
9604 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9605 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9606 inst
.instruction
|= inst
.operands
[1].reg
;
9610 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9611 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9612 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9619 set_it_insn_type (OUTSIDE_IT_INSN
);
9620 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9621 inst
.instruction
|= inst
.operands
[0].reg
;
9622 inst
.reloc
.pc_rel
= 1;
9623 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9629 inst
.instruction
|= inst
.operands
[0].imm
;
9635 unsigned Rd
, Rn
, Rm
;
9637 Rd
= inst
.operands
[0].reg
;
9638 Rn
= (inst
.operands
[1].present
9639 ? inst
.operands
[1].reg
: Rd
);
9640 Rm
= inst
.operands
[2].reg
;
9642 reject_bad_reg (Rd
);
9643 reject_bad_reg (Rn
);
9644 reject_bad_reg (Rm
);
9646 inst
.instruction
|= Rd
<< 8;
9647 inst
.instruction
|= Rn
<< 16;
9648 inst
.instruction
|= Rm
;
9654 if (unified_syntax
&& inst
.size_req
== 4)
9655 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9657 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9663 unsigned int cond
= inst
.operands
[0].imm
;
9665 set_it_insn_type (IT_INSN
);
9666 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9669 /* If the condition is a negative condition, invert the mask. */
9670 if ((cond
& 0x1) == 0x0)
9672 unsigned int mask
= inst
.instruction
& 0x000f;
9674 if ((mask
& 0x7) == 0)
9675 /* no conversion needed */;
9676 else if ((mask
& 0x3) == 0)
9678 else if ((mask
& 0x1) == 0)
9683 inst
.instruction
&= 0xfff0;
9684 inst
.instruction
|= mask
;
9687 inst
.instruction
|= cond
<< 4;
9690 /* Helper function used for both push/pop and ldm/stm. */
9692 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9696 load
= (inst
.instruction
& (1 << 20)) != 0;
9698 if (mask
& (1 << 13))
9699 inst
.error
= _("SP not allowed in register list");
9702 if (mask
& (1 << 15))
9704 if (mask
& (1 << 14))
9705 inst
.error
= _("LR and PC should not both be in register list");
9707 set_it_insn_type_last ();
9710 if ((mask
& (1 << base
)) != 0
9712 as_warn (_("base register should not be in register list "
9713 "when written back"));
9717 if (mask
& (1 << 15))
9718 inst
.error
= _("PC not allowed in register list");
9720 if (mask
& (1 << base
))
9721 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9724 if ((mask
& (mask
- 1)) == 0)
9726 /* Single register transfers implemented as str/ldr. */
9729 if (inst
.instruction
& (1 << 23))
9730 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9732 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9736 if (inst
.instruction
& (1 << 23))
9737 inst
.instruction
= 0x00800000; /* ia -> [base] */
9739 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9742 inst
.instruction
|= 0xf8400000;
9744 inst
.instruction
|= 0x00100000;
9746 mask
= ffs (mask
) - 1;
9750 inst
.instruction
|= WRITE_BACK
;
9752 inst
.instruction
|= mask
;
9753 inst
.instruction
|= base
<< 16;
9759 /* This really doesn't seem worth it. */
9760 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9761 _("expression too complex"));
9762 constraint (inst
.operands
[1].writeback
,
9763 _("Thumb load/store multiple does not support {reglist}^"));
9771 /* See if we can use a 16-bit instruction. */
9772 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9773 && inst
.size_req
!= 4
9774 && !(inst
.operands
[1].imm
& ~0xff))
9776 mask
= 1 << inst
.operands
[0].reg
;
9778 if (inst
.operands
[0].reg
<= 7
9779 && (inst
.instruction
== T_MNEM_stmia
9780 ? inst
.operands
[0].writeback
9781 : (inst
.operands
[0].writeback
9782 == !(inst
.operands
[1].imm
& mask
))))
9784 if (inst
.instruction
== T_MNEM_stmia
9785 && (inst
.operands
[1].imm
& mask
)
9786 && (inst
.operands
[1].imm
& (mask
- 1)))
9787 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9788 inst
.operands
[0].reg
);
9790 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9791 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9792 inst
.instruction
|= inst
.operands
[1].imm
;
9795 else if (inst
.operands
[0] .reg
== REG_SP
9796 && inst
.operands
[0].writeback
)
9798 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9799 ? T_MNEM_push
: T_MNEM_pop
);
9800 inst
.instruction
|= inst
.operands
[1].imm
;
9807 if (inst
.instruction
< 0xffff)
9808 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9810 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9811 inst
.operands
[0].writeback
);
9816 constraint (inst
.operands
[0].reg
> 7
9817 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9818 constraint (inst
.instruction
!= T_MNEM_ldmia
9819 && inst
.instruction
!= T_MNEM_stmia
,
9820 _("Thumb-2 instruction only valid in unified syntax"));
9821 if (inst
.instruction
== T_MNEM_stmia
)
9823 if (!inst
.operands
[0].writeback
)
9824 as_warn (_("this instruction will write back the base register"));
9825 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9826 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9827 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9828 inst
.operands
[0].reg
);
9832 if (!inst
.operands
[0].writeback
9833 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9834 as_warn (_("this instruction will write back the base register"));
9835 else if (inst
.operands
[0].writeback
9836 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9837 as_warn (_("this instruction will not write back the base register"));
9840 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9841 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9842 inst
.instruction
|= inst
.operands
[1].imm
;
9849 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9850 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9851 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9852 || inst
.operands
[1].negative
,
9855 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9856 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9857 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9863 if (!inst
.operands
[1].present
)
9865 constraint (inst
.operands
[0].reg
== REG_LR
,
9866 _("r14 not allowed as first register "
9867 "when second register is omitted"));
9868 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9870 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9873 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9874 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9875 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9881 unsigned long opcode
;
9884 if (inst
.operands
[0].isreg
9885 && !inst
.operands
[0].preind
9886 && inst
.operands
[0].reg
== REG_PC
)
9887 set_it_insn_type_last ();
9889 opcode
= inst
.instruction
;
9892 if (!inst
.operands
[1].isreg
)
9894 if (opcode
<= 0xffff)
9895 inst
.instruction
= THUMB_OP32 (opcode
);
9896 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9899 if (inst
.operands
[1].isreg
9900 && !inst
.operands
[1].writeback
9901 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9902 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9904 && inst
.size_req
!= 4)
9906 /* Insn may have a 16-bit form. */
9907 Rn
= inst
.operands
[1].reg
;
9908 if (inst
.operands
[1].immisreg
)
9910 inst
.instruction
= THUMB_OP16 (opcode
);
9912 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9915 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9916 && opcode
!= T_MNEM_ldrsb
)
9917 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9918 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9925 if (inst
.reloc
.pc_rel
)
9926 opcode
= T_MNEM_ldr_pc2
;
9928 opcode
= T_MNEM_ldr_pc
;
9932 if (opcode
== T_MNEM_ldr
)
9933 opcode
= T_MNEM_ldr_sp
;
9935 opcode
= T_MNEM_str_sp
;
9937 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9941 inst
.instruction
= inst
.operands
[0].reg
;
9942 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9944 inst
.instruction
|= THUMB_OP16 (opcode
);
9945 if (inst
.size_req
== 2)
9946 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9948 inst
.relax
= opcode
;
9952 /* Definitely a 32-bit variant. */
9953 inst
.instruction
= THUMB_OP32 (opcode
);
9954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9955 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9959 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9961 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9963 /* Only [Rn,Rm] is acceptable. */
9964 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9965 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9966 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9967 || inst
.operands
[1].negative
,
9968 _("Thumb does not support this addressing mode"));
9969 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9973 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9974 if (!inst
.operands
[1].isreg
)
9975 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9978 constraint (!inst
.operands
[1].preind
9979 || inst
.operands
[1].shifted
9980 || inst
.operands
[1].writeback
,
9981 _("Thumb does not support this addressing mode"));
9982 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9984 constraint (inst
.instruction
& 0x0600,
9985 _("byte or halfword not valid for base register"));
9986 constraint (inst
.operands
[1].reg
== REG_PC
9987 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9988 _("r15 based store not allowed"));
9989 constraint (inst
.operands
[1].immisreg
,
9990 _("invalid base register for register offset"));
9992 if (inst
.operands
[1].reg
== REG_PC
)
9993 inst
.instruction
= T_OPCODE_LDR_PC
;
9994 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9995 inst
.instruction
= T_OPCODE_LDR_SP
;
9997 inst
.instruction
= T_OPCODE_STR_SP
;
9999 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10000 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10004 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10005 if (!inst
.operands
[1].immisreg
)
10007 /* Immediate offset. */
10008 inst
.instruction
|= inst
.operands
[0].reg
;
10009 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10010 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10014 /* Register offset. */
10015 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10016 constraint (inst
.operands
[1].negative
,
10017 _("Thumb does not support this addressing mode"));
10020 switch (inst
.instruction
)
10022 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10023 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10024 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10025 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10026 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10027 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10028 case 0x5600 /* ldrsb */:
10029 case 0x5e00 /* ldrsh */: break;
10033 inst
.instruction
|= inst
.operands
[0].reg
;
10034 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10035 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10041 if (!inst
.operands
[1].present
)
10043 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10044 constraint (inst
.operands
[0].reg
== REG_LR
,
10045 _("r14 not allowed here"));
10047 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10048 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10049 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10055 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10056 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10062 unsigned Rd
, Rn
, Rm
, Ra
;
10064 Rd
= inst
.operands
[0].reg
;
10065 Rn
= inst
.operands
[1].reg
;
10066 Rm
= inst
.operands
[2].reg
;
10067 Ra
= inst
.operands
[3].reg
;
10069 reject_bad_reg (Rd
);
10070 reject_bad_reg (Rn
);
10071 reject_bad_reg (Rm
);
10072 reject_bad_reg (Ra
);
10074 inst
.instruction
|= Rd
<< 8;
10075 inst
.instruction
|= Rn
<< 16;
10076 inst
.instruction
|= Rm
;
10077 inst
.instruction
|= Ra
<< 12;
10083 unsigned RdLo
, RdHi
, Rn
, Rm
;
10085 RdLo
= inst
.operands
[0].reg
;
10086 RdHi
= inst
.operands
[1].reg
;
10087 Rn
= inst
.operands
[2].reg
;
10088 Rm
= inst
.operands
[3].reg
;
10090 reject_bad_reg (RdLo
);
10091 reject_bad_reg (RdHi
);
10092 reject_bad_reg (Rn
);
10093 reject_bad_reg (Rm
);
10095 inst
.instruction
|= RdLo
<< 12;
10096 inst
.instruction
|= RdHi
<< 8;
10097 inst
.instruction
|= Rn
<< 16;
10098 inst
.instruction
|= Rm
;
10102 do_t_mov_cmp (void)
10106 Rn
= inst
.operands
[0].reg
;
10107 Rm
= inst
.operands
[1].reg
;
10110 set_it_insn_type_last ();
10112 if (unified_syntax
)
10114 int r0off
= (inst
.instruction
== T_MNEM_mov
10115 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10116 unsigned long opcode
;
10117 bfd_boolean narrow
;
10118 bfd_boolean low_regs
;
10120 low_regs
= (Rn
<= 7 && Rm
<= 7);
10121 opcode
= inst
.instruction
;
10122 if (in_it_block ())
10123 narrow
= opcode
!= T_MNEM_movs
;
10125 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10126 if (inst
.size_req
== 4
10127 || inst
.operands
[1].shifted
)
10130 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10131 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10132 && !inst
.operands
[1].shifted
10136 inst
.instruction
= T2_SUBS_PC_LR
;
10140 if (opcode
== T_MNEM_cmp
)
10142 constraint (Rn
== REG_PC
, BAD_PC
);
10145 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10147 warn_deprecated_sp (Rm
);
10148 /* R15 was documented as a valid choice for Rm in ARMv6,
10149 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10150 tools reject R15, so we do too. */
10151 constraint (Rm
== REG_PC
, BAD_PC
);
10154 reject_bad_reg (Rm
);
10156 else if (opcode
== T_MNEM_mov
10157 || opcode
== T_MNEM_movs
)
10159 if (inst
.operands
[1].isreg
)
10161 if (opcode
== T_MNEM_movs
)
10163 reject_bad_reg (Rn
);
10164 reject_bad_reg (Rm
);
10166 else if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10167 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10168 reject_bad_reg (Rm
);
10171 reject_bad_reg (Rn
);
10174 if (!inst
.operands
[1].isreg
)
10176 /* Immediate operand. */
10177 if (!in_it_block () && opcode
== T_MNEM_mov
)
10179 if (low_regs
&& narrow
)
10181 inst
.instruction
= THUMB_OP16 (opcode
);
10182 inst
.instruction
|= Rn
<< 8;
10183 if (inst
.size_req
== 2)
10184 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10186 inst
.relax
= opcode
;
10190 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10191 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10192 inst
.instruction
|= Rn
<< r0off
;
10193 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10196 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10197 && (inst
.instruction
== T_MNEM_mov
10198 || inst
.instruction
== T_MNEM_movs
))
10200 /* Register shifts are encoded as separate shift instructions. */
10201 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10203 if (in_it_block ())
10208 if (inst
.size_req
== 4)
10211 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10217 switch (inst
.operands
[1].shift_kind
)
10220 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10223 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10226 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10229 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10235 inst
.instruction
= opcode
;
10238 inst
.instruction
|= Rn
;
10239 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10244 inst
.instruction
|= CONDS_BIT
;
10246 inst
.instruction
|= Rn
<< 8;
10247 inst
.instruction
|= Rm
<< 16;
10248 inst
.instruction
|= inst
.operands
[1].imm
;
10253 /* Some mov with immediate shift have narrow variants.
10254 Register shifts are handled above. */
10255 if (low_regs
&& inst
.operands
[1].shifted
10256 && (inst
.instruction
== T_MNEM_mov
10257 || inst
.instruction
== T_MNEM_movs
))
10259 if (in_it_block ())
10260 narrow
= (inst
.instruction
== T_MNEM_mov
);
10262 narrow
= (inst
.instruction
== T_MNEM_movs
);
10267 switch (inst
.operands
[1].shift_kind
)
10269 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10270 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10271 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10272 default: narrow
= FALSE
; break;
10278 inst
.instruction
|= Rn
;
10279 inst
.instruction
|= Rm
<< 3;
10280 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10284 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10285 inst
.instruction
|= Rn
<< r0off
;
10286 encode_thumb32_shifted_operand (1);
10290 switch (inst
.instruction
)
10293 inst
.instruction
= T_OPCODE_MOV_HR
;
10294 inst
.instruction
|= (Rn
& 0x8) << 4;
10295 inst
.instruction
|= (Rn
& 0x7);
10296 inst
.instruction
|= Rm
<< 3;
10300 /* We know we have low registers at this point.
10301 Generate ADD Rd, Rs, #0. */
10302 inst
.instruction
= T_OPCODE_ADD_I3
;
10303 inst
.instruction
|= Rn
;
10304 inst
.instruction
|= Rm
<< 3;
10310 inst
.instruction
= T_OPCODE_CMP_LR
;
10311 inst
.instruction
|= Rn
;
10312 inst
.instruction
|= Rm
<< 3;
10316 inst
.instruction
= T_OPCODE_CMP_HR
;
10317 inst
.instruction
|= (Rn
& 0x8) << 4;
10318 inst
.instruction
|= (Rn
& 0x7);
10319 inst
.instruction
|= Rm
<< 3;
10326 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10328 /* PR 10443: Do not silently ignore shifted operands. */
10329 constraint (inst
.operands
[1].shifted
,
10330 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10332 if (inst
.operands
[1].isreg
)
10334 if (Rn
< 8 && Rm
< 8)
10336 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10337 since a MOV instruction produces unpredictable results. */
10338 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10339 inst
.instruction
= T_OPCODE_ADD_I3
;
10341 inst
.instruction
= T_OPCODE_CMP_LR
;
10343 inst
.instruction
|= Rn
;
10344 inst
.instruction
|= Rm
<< 3;
10348 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10349 inst
.instruction
= T_OPCODE_MOV_HR
;
10351 inst
.instruction
= T_OPCODE_CMP_HR
;
10357 constraint (Rn
> 7,
10358 _("only lo regs allowed with immediate"));
10359 inst
.instruction
|= Rn
<< 8;
10360 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10371 top
= (inst
.instruction
& 0x00800000) != 0;
10372 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10374 constraint (top
, _(":lower16: not allowed this instruction"));
10375 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10377 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10379 constraint (!top
, _(":upper16: not allowed this instruction"));
10380 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10383 Rd
= inst
.operands
[0].reg
;
10384 reject_bad_reg (Rd
);
10386 inst
.instruction
|= Rd
<< 8;
10387 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10389 imm
= inst
.reloc
.exp
.X_add_number
;
10390 inst
.instruction
|= (imm
& 0xf000) << 4;
10391 inst
.instruction
|= (imm
& 0x0800) << 15;
10392 inst
.instruction
|= (imm
& 0x0700) << 4;
10393 inst
.instruction
|= (imm
& 0x00ff);
10398 do_t_mvn_tst (void)
10402 Rn
= inst
.operands
[0].reg
;
10403 Rm
= inst
.operands
[1].reg
;
10405 if (inst
.instruction
== T_MNEM_cmp
10406 || inst
.instruction
== T_MNEM_cmn
)
10407 constraint (Rn
== REG_PC
, BAD_PC
);
10409 reject_bad_reg (Rn
);
10410 reject_bad_reg (Rm
);
10412 if (unified_syntax
)
10414 int r0off
= (inst
.instruction
== T_MNEM_mvn
10415 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10416 bfd_boolean narrow
;
10418 if (inst
.size_req
== 4
10419 || inst
.instruction
> 0xffff
10420 || inst
.operands
[1].shifted
10421 || Rn
> 7 || Rm
> 7)
10423 else if (inst
.instruction
== T_MNEM_cmn
)
10425 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10426 narrow
= !in_it_block ();
10428 narrow
= in_it_block ();
10430 if (!inst
.operands
[1].isreg
)
10432 /* For an immediate, we always generate a 32-bit opcode;
10433 section relaxation will shrink it later if possible. */
10434 if (inst
.instruction
< 0xffff)
10435 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10436 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10437 inst
.instruction
|= Rn
<< r0off
;
10438 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10442 /* See if we can do this with a 16-bit instruction. */
10445 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10446 inst
.instruction
|= Rn
;
10447 inst
.instruction
|= Rm
<< 3;
10451 constraint (inst
.operands
[1].shifted
10452 && inst
.operands
[1].immisreg
,
10453 _("shift must be constant"));
10454 if (inst
.instruction
< 0xffff)
10455 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10456 inst
.instruction
|= Rn
<< r0off
;
10457 encode_thumb32_shifted_operand (1);
10463 constraint (inst
.instruction
> 0xffff
10464 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10465 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10466 _("unshifted register required"));
10467 constraint (Rn
> 7 || Rm
> 7,
10470 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10471 inst
.instruction
|= Rn
;
10472 inst
.instruction
|= Rm
<< 3;
10482 if (do_vfp_nsyn_mrs () == SUCCESS
)
10485 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10488 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10489 _("selected processor does not support "
10490 "requested special purpose register"));
10494 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10495 _("selected processor does not support "
10496 "requested special purpose register"));
10497 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10498 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10499 _("'CPSR' or 'SPSR' expected"));
10502 Rd
= inst
.operands
[0].reg
;
10503 reject_bad_reg (Rd
);
10505 inst
.instruction
|= Rd
<< 8;
10506 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10507 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10516 if (do_vfp_nsyn_msr () == SUCCESS
)
10519 constraint (!inst
.operands
[1].isreg
,
10520 _("Thumb encoding does not support an immediate here"));
10521 flags
= inst
.operands
[0].imm
;
10524 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10525 _("selected processor does not support "
10526 "requested special purpose register"));
10530 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10531 _("selected processor does not support "
10532 "requested special purpose register"));
10536 Rn
= inst
.operands
[1].reg
;
10537 reject_bad_reg (Rn
);
10539 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10540 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10541 inst
.instruction
|= (flags
& 0xff);
10542 inst
.instruction
|= Rn
<< 16;
10548 bfd_boolean narrow
;
10549 unsigned Rd
, Rn
, Rm
;
10551 if (!inst
.operands
[2].present
)
10552 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10554 Rd
= inst
.operands
[0].reg
;
10555 Rn
= inst
.operands
[1].reg
;
10556 Rm
= inst
.operands
[2].reg
;
10558 if (unified_syntax
)
10560 if (inst
.size_req
== 4
10566 else if (inst
.instruction
== T_MNEM_muls
)
10567 narrow
= !in_it_block ();
10569 narrow
= in_it_block ();
10573 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10574 constraint (Rn
> 7 || Rm
> 7,
10581 /* 16-bit MULS/Conditional MUL. */
10582 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10583 inst
.instruction
|= Rd
;
10586 inst
.instruction
|= Rm
<< 3;
10588 inst
.instruction
|= Rn
<< 3;
10590 constraint (1, _("dest must overlap one source register"));
10594 constraint (inst
.instruction
!= T_MNEM_mul
,
10595 _("Thumb-2 MUL must not set flags"));
10597 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10598 inst
.instruction
|= Rd
<< 8;
10599 inst
.instruction
|= Rn
<< 16;
10600 inst
.instruction
|= Rm
<< 0;
10602 reject_bad_reg (Rd
);
10603 reject_bad_reg (Rn
);
10604 reject_bad_reg (Rm
);
10611 unsigned RdLo
, RdHi
, Rn
, Rm
;
10613 RdLo
= inst
.operands
[0].reg
;
10614 RdHi
= inst
.operands
[1].reg
;
10615 Rn
= inst
.operands
[2].reg
;
10616 Rm
= inst
.operands
[3].reg
;
10618 reject_bad_reg (RdLo
);
10619 reject_bad_reg (RdHi
);
10620 reject_bad_reg (Rn
);
10621 reject_bad_reg (Rm
);
10623 inst
.instruction
|= RdLo
<< 12;
10624 inst
.instruction
|= RdHi
<< 8;
10625 inst
.instruction
|= Rn
<< 16;
10626 inst
.instruction
|= Rm
;
10629 as_tsktsk (_("rdhi and rdlo must be different"));
10635 set_it_insn_type (NEUTRAL_IT_INSN
);
10637 if (unified_syntax
)
10639 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10641 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10642 inst
.instruction
|= inst
.operands
[0].imm
;
10646 /* PR9722: Check for Thumb2 availability before
10647 generating a thumb2 nop instruction. */
10648 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
10650 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10651 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10654 inst
.instruction
= 0x46c0;
10659 constraint (inst
.operands
[0].present
,
10660 _("Thumb does not support NOP with hints"));
10661 inst
.instruction
= 0x46c0;
10668 if (unified_syntax
)
10670 bfd_boolean narrow
;
10672 if (THUMB_SETS_FLAGS (inst
.instruction
))
10673 narrow
= !in_it_block ();
10675 narrow
= in_it_block ();
10676 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10678 if (inst
.size_req
== 4)
10683 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10684 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10685 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10689 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10690 inst
.instruction
|= inst
.operands
[0].reg
;
10691 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10696 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10698 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10700 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10701 inst
.instruction
|= inst
.operands
[0].reg
;
10702 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10711 Rd
= inst
.operands
[0].reg
;
10712 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10714 reject_bad_reg (Rd
);
10715 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10716 reject_bad_reg (Rn
);
10718 inst
.instruction
|= Rd
<< 8;
10719 inst
.instruction
|= Rn
<< 16;
10721 if (!inst
.operands
[2].isreg
)
10723 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10724 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10730 Rm
= inst
.operands
[2].reg
;
10731 reject_bad_reg (Rm
);
10733 constraint (inst
.operands
[2].shifted
10734 && inst
.operands
[2].immisreg
,
10735 _("shift must be constant"));
10736 encode_thumb32_shifted_operand (2);
10743 unsigned Rd
, Rn
, Rm
;
10745 Rd
= inst
.operands
[0].reg
;
10746 Rn
= inst
.operands
[1].reg
;
10747 Rm
= inst
.operands
[2].reg
;
10749 reject_bad_reg (Rd
);
10750 reject_bad_reg (Rn
);
10751 reject_bad_reg (Rm
);
10753 inst
.instruction
|= Rd
<< 8;
10754 inst
.instruction
|= Rn
<< 16;
10755 inst
.instruction
|= Rm
;
10756 if (inst
.operands
[3].present
)
10758 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10759 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10760 _("expression too complex"));
10761 inst
.instruction
|= (val
& 0x1c) << 10;
10762 inst
.instruction
|= (val
& 0x03) << 6;
10769 if (!inst
.operands
[3].present
)
10773 inst
.instruction
&= ~0x00000020;
10775 /* PR 10168. Swap the Rm and Rn registers. */
10776 Rtmp
= inst
.operands
[1].reg
;
10777 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10778 inst
.operands
[2].reg
= Rtmp
;
10786 if (inst
.operands
[0].immisreg
)
10787 reject_bad_reg (inst
.operands
[0].imm
);
10789 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10793 do_t_push_pop (void)
10797 constraint (inst
.operands
[0].writeback
,
10798 _("push/pop do not support {reglist}^"));
10799 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10800 _("expression too complex"));
10802 mask
= inst
.operands
[0].imm
;
10803 if ((mask
& ~0xff) == 0)
10804 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10805 else if ((inst
.instruction
== T_MNEM_push
10806 && (mask
& ~0xff) == 1 << REG_LR
)
10807 || (inst
.instruction
== T_MNEM_pop
10808 && (mask
& ~0xff) == 1 << REG_PC
))
10810 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10811 inst
.instruction
|= THUMB_PP_PC_LR
;
10812 inst
.instruction
|= mask
& 0xff;
10814 else if (unified_syntax
)
10816 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10817 encode_thumb2_ldmstm (13, mask
, TRUE
);
10821 inst
.error
= _("invalid register list to push/pop instruction");
10831 Rd
= inst
.operands
[0].reg
;
10832 Rm
= inst
.operands
[1].reg
;
10834 reject_bad_reg (Rd
);
10835 reject_bad_reg (Rm
);
10837 inst
.instruction
|= Rd
<< 8;
10838 inst
.instruction
|= Rm
<< 16;
10839 inst
.instruction
|= Rm
;
10847 Rd
= inst
.operands
[0].reg
;
10848 Rm
= inst
.operands
[1].reg
;
10850 reject_bad_reg (Rd
);
10851 reject_bad_reg (Rm
);
10853 if (Rd
<= 7 && Rm
<= 7
10854 && inst
.size_req
!= 4)
10856 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10857 inst
.instruction
|= Rd
;
10858 inst
.instruction
|= Rm
<< 3;
10860 else if (unified_syntax
)
10862 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10863 inst
.instruction
|= Rd
<< 8;
10864 inst
.instruction
|= Rm
<< 16;
10865 inst
.instruction
|= Rm
;
10868 inst
.error
= BAD_HIREG
;
10876 Rd
= inst
.operands
[0].reg
;
10877 Rm
= inst
.operands
[1].reg
;
10879 reject_bad_reg (Rd
);
10880 reject_bad_reg (Rm
);
10882 inst
.instruction
|= Rd
<< 8;
10883 inst
.instruction
|= Rm
;
10891 Rd
= inst
.operands
[0].reg
;
10892 Rs
= (inst
.operands
[1].present
10893 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10894 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10896 reject_bad_reg (Rd
);
10897 reject_bad_reg (Rs
);
10898 if (inst
.operands
[2].isreg
)
10899 reject_bad_reg (inst
.operands
[2].reg
);
10901 inst
.instruction
|= Rd
<< 8;
10902 inst
.instruction
|= Rs
<< 16;
10903 if (!inst
.operands
[2].isreg
)
10905 bfd_boolean narrow
;
10907 if ((inst
.instruction
& 0x00100000) != 0)
10908 narrow
= !in_it_block ();
10910 narrow
= in_it_block ();
10912 if (Rd
> 7 || Rs
> 7)
10915 if (inst
.size_req
== 4 || !unified_syntax
)
10918 if (inst
.reloc
.exp
.X_op
!= O_constant
10919 || inst
.reloc
.exp
.X_add_number
!= 0)
10922 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10923 relaxation, but it doesn't seem worth the hassle. */
10926 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10927 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10928 inst
.instruction
|= Rs
<< 3;
10929 inst
.instruction
|= Rd
;
10933 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10934 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10938 encode_thumb32_shifted_operand (2);
10944 set_it_insn_type (OUTSIDE_IT_INSN
);
10945 if (inst
.operands
[0].imm
)
10946 inst
.instruction
|= 0x8;
10952 if (!inst
.operands
[1].present
)
10953 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10955 if (unified_syntax
)
10957 bfd_boolean narrow
;
10960 switch (inst
.instruction
)
10963 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10965 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10967 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10969 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10973 if (THUMB_SETS_FLAGS (inst
.instruction
))
10974 narrow
= !in_it_block ();
10976 narrow
= in_it_block ();
10977 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10979 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10981 if (inst
.operands
[2].isreg
10982 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10983 || inst
.operands
[2].reg
> 7))
10985 if (inst
.size_req
== 4)
10988 reject_bad_reg (inst
.operands
[0].reg
);
10989 reject_bad_reg (inst
.operands
[1].reg
);
10993 if (inst
.operands
[2].isreg
)
10995 reject_bad_reg (inst
.operands
[2].reg
);
10996 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10997 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10998 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10999 inst
.instruction
|= inst
.operands
[2].reg
;
11003 inst
.operands
[1].shifted
= 1;
11004 inst
.operands
[1].shift_kind
= shift_kind
;
11005 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11006 ? T_MNEM_movs
: T_MNEM_mov
);
11007 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11008 encode_thumb32_shifted_operand (1);
11009 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11010 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11015 if (inst
.operands
[2].isreg
)
11017 switch (shift_kind
)
11019 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11020 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11021 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11022 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11026 inst
.instruction
|= inst
.operands
[0].reg
;
11027 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11031 switch (shift_kind
)
11033 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11034 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11035 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11038 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11039 inst
.instruction
|= inst
.operands
[0].reg
;
11040 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11046 constraint (inst
.operands
[0].reg
> 7
11047 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11048 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11050 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11052 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11053 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11054 _("source1 and dest must be same register"));
11056 switch (inst
.instruction
)
11058 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11059 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11060 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11061 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11065 inst
.instruction
|= inst
.operands
[0].reg
;
11066 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11070 switch (inst
.instruction
)
11072 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11073 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11074 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11075 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11078 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11079 inst
.instruction
|= inst
.operands
[0].reg
;
11080 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11088 unsigned Rd
, Rn
, Rm
;
11090 Rd
= inst
.operands
[0].reg
;
11091 Rn
= inst
.operands
[1].reg
;
11092 Rm
= inst
.operands
[2].reg
;
11094 reject_bad_reg (Rd
);
11095 reject_bad_reg (Rn
);
11096 reject_bad_reg (Rm
);
11098 inst
.instruction
|= Rd
<< 8;
11099 inst
.instruction
|= Rn
<< 16;
11100 inst
.instruction
|= Rm
;
11106 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11107 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11108 _("expression too complex"));
11109 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11110 inst
.instruction
|= (value
& 0xf000) >> 12;
11111 inst
.instruction
|= (value
& 0x0ff0);
11112 inst
.instruction
|= (value
& 0x000f) << 16;
11116 do_t_ssat_usat (int bias
)
11120 Rd
= inst
.operands
[0].reg
;
11121 Rn
= inst
.operands
[2].reg
;
11123 reject_bad_reg (Rd
);
11124 reject_bad_reg (Rn
);
11126 inst
.instruction
|= Rd
<< 8;
11127 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11128 inst
.instruction
|= Rn
<< 16;
11130 if (inst
.operands
[3].present
)
11132 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11134 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11136 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11137 _("expression too complex"));
11139 if (shift_amount
!= 0)
11141 constraint (shift_amount
> 31,
11142 _("shift expression is too large"));
11144 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11145 inst
.instruction
|= 0x00200000; /* sh bit. */
11147 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11148 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11156 do_t_ssat_usat (1);
11164 Rd
= inst
.operands
[0].reg
;
11165 Rn
= inst
.operands
[2].reg
;
11167 reject_bad_reg (Rd
);
11168 reject_bad_reg (Rn
);
11170 inst
.instruction
|= Rd
<< 8;
11171 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11172 inst
.instruction
|= Rn
<< 16;
11178 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11179 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11180 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11181 || inst
.operands
[2].negative
,
11184 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11185 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11186 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11187 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11193 if (!inst
.operands
[2].present
)
11194 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11196 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11197 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11198 || inst
.operands
[0].reg
== inst
.operands
[3].reg
11199 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
11202 inst
.instruction
|= inst
.operands
[0].reg
;
11203 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11204 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11205 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11211 unsigned Rd
, Rn
, Rm
;
11213 Rd
= inst
.operands
[0].reg
;
11214 Rn
= inst
.operands
[1].reg
;
11215 Rm
= inst
.operands
[2].reg
;
11217 reject_bad_reg (Rd
);
11218 reject_bad_reg (Rn
);
11219 reject_bad_reg (Rm
);
11221 inst
.instruction
|= Rd
<< 8;
11222 inst
.instruction
|= Rn
<< 16;
11223 inst
.instruction
|= Rm
;
11224 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11232 Rd
= inst
.operands
[0].reg
;
11233 Rm
= inst
.operands
[1].reg
;
11235 reject_bad_reg (Rd
);
11236 reject_bad_reg (Rm
);
11238 if (inst
.instruction
<= 0xffff
11239 && inst
.size_req
!= 4
11240 && Rd
<= 7 && Rm
<= 7
11241 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11243 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11244 inst
.instruction
|= Rd
;
11245 inst
.instruction
|= Rm
<< 3;
11247 else if (unified_syntax
)
11249 if (inst
.instruction
<= 0xffff)
11250 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11251 inst
.instruction
|= Rd
<< 8;
11252 inst
.instruction
|= Rm
;
11253 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11257 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11258 _("Thumb encoding does not support rotation"));
11259 constraint (1, BAD_HIREG
);
11266 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11275 half
= (inst
.instruction
& 0x10) != 0;
11276 set_it_insn_type_last ();
11277 constraint (inst
.operands
[0].immisreg
,
11278 _("instruction requires register index"));
11280 Rn
= inst
.operands
[0].reg
;
11281 Rm
= inst
.operands
[0].imm
;
11283 constraint (Rn
== REG_SP
, BAD_SP
);
11284 reject_bad_reg (Rm
);
11286 constraint (!half
&& inst
.operands
[0].shifted
,
11287 _("instruction does not allow shifted index"));
11288 inst
.instruction
|= (Rn
<< 16) | Rm
;
11294 do_t_ssat_usat (0);
11302 Rd
= inst
.operands
[0].reg
;
11303 Rn
= inst
.operands
[2].reg
;
11305 reject_bad_reg (Rd
);
11306 reject_bad_reg (Rn
);
11308 inst
.instruction
|= Rd
<< 8;
11309 inst
.instruction
|= inst
.operands
[1].imm
;
11310 inst
.instruction
|= Rn
<< 16;
11313 /* Neon instruction encoder helpers. */
11315 /* Encodings for the different types for various Neon opcodes. */
11317 /* An "invalid" code for the following tables. */
11320 struct neon_tab_entry
11323 unsigned float_or_poly
;
11324 unsigned scalar_or_imm
;
11327 /* Map overloaded Neon opcodes to their respective encodings. */
11328 #define NEON_ENC_TAB \
11329 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11330 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11331 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11332 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11333 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11334 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11335 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11336 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11337 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11338 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11339 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11340 /* Register variants of the following two instructions are encoded as
11341 vcge / vcgt with the operands reversed. */ \
11342 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11343 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11344 X(vfma, N_INV, 0x0000c10, N_INV), \
11345 X(vfms, N_INV, 0x0200c10, N_INV), \
11346 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11347 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11348 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11349 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11350 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11351 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11352 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11353 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11354 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11355 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11356 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11357 X(vshl, 0x0000400, N_INV, 0x0800510), \
11358 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11359 X(vand, 0x0000110, N_INV, 0x0800030), \
11360 X(vbic, 0x0100110, N_INV, 0x0800030), \
11361 X(veor, 0x1000110, N_INV, N_INV), \
11362 X(vorn, 0x0300110, N_INV, 0x0800010), \
11363 X(vorr, 0x0200110, N_INV, 0x0800010), \
11364 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11365 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11366 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11367 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11368 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11369 X(vst1, 0x0000000, 0x0800000, N_INV), \
11370 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11371 X(vst2, 0x0000100, 0x0800100, N_INV), \
11372 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11373 X(vst3, 0x0000200, 0x0800200, N_INV), \
11374 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11375 X(vst4, 0x0000300, 0x0800300, N_INV), \
11376 X(vmovn, 0x1b20200, N_INV, N_INV), \
11377 X(vtrn, 0x1b20080, N_INV, N_INV), \
11378 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11379 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11380 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11381 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11382 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11383 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11384 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11385 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11386 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11387 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11388 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11392 #define X(OPC,I,F,S) N_MNEM_##OPC
11397 static const struct neon_tab_entry neon_enc_tab
[] =
11399 #define X(OPC,I,F,S) { (I), (F), (S) }
11404 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11405 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11406 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11407 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11408 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11409 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11410 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11411 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11412 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11413 #define NEON_ENC_SINGLE(X) \
11414 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11415 #define NEON_ENC_DOUBLE(X) \
11416 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11418 /* Define shapes for instruction operands. The following mnemonic characters
11419 are used in this table:
11421 F - VFP S<n> register
11422 D - Neon D<n> register
11423 Q - Neon Q<n> register
11427 L - D<n> register list
11429 This table is used to generate various data:
11430 - enumerations of the form NS_DDR to be used as arguments to
11432 - a table classifying shapes into single, double, quad, mixed.
11433 - a table used to drive neon_select_shape. */
11435 #define NEON_SHAPE_DEF \
11436 X(3, (D, D, D), DOUBLE), \
11437 X(3, (Q, Q, Q), QUAD), \
11438 X(3, (D, D, I), DOUBLE), \
11439 X(3, (Q, Q, I), QUAD), \
11440 X(3, (D, D, S), DOUBLE), \
11441 X(3, (Q, Q, S), QUAD), \
11442 X(2, (D, D), DOUBLE), \
11443 X(2, (Q, Q), QUAD), \
11444 X(2, (D, S), DOUBLE), \
11445 X(2, (Q, S), QUAD), \
11446 X(2, (D, R), DOUBLE), \
11447 X(2, (Q, R), QUAD), \
11448 X(2, (D, I), DOUBLE), \
11449 X(2, (Q, I), QUAD), \
11450 X(3, (D, L, D), DOUBLE), \
11451 X(2, (D, Q), MIXED), \
11452 X(2, (Q, D), MIXED), \
11453 X(3, (D, Q, I), MIXED), \
11454 X(3, (Q, D, I), MIXED), \
11455 X(3, (Q, D, D), MIXED), \
11456 X(3, (D, Q, Q), MIXED), \
11457 X(3, (Q, Q, D), MIXED), \
11458 X(3, (Q, D, S), MIXED), \
11459 X(3, (D, Q, S), MIXED), \
11460 X(4, (D, D, D, I), DOUBLE), \
11461 X(4, (Q, Q, Q, I), QUAD), \
11462 X(2, (F, F), SINGLE), \
11463 X(3, (F, F, F), SINGLE), \
11464 X(2, (F, I), SINGLE), \
11465 X(2, (F, D), MIXED), \
11466 X(2, (D, F), MIXED), \
11467 X(3, (F, F, I), MIXED), \
11468 X(4, (R, R, F, F), SINGLE), \
11469 X(4, (F, F, R, R), SINGLE), \
11470 X(3, (D, R, R), DOUBLE), \
11471 X(3, (R, R, D), DOUBLE), \
11472 X(2, (S, R), SINGLE), \
11473 X(2, (R, S), SINGLE), \
11474 X(2, (F, R), SINGLE), \
11475 X(2, (R, F), SINGLE)
11477 #define S2(A,B) NS_##A##B
11478 #define S3(A,B,C) NS_##A##B##C
11479 #define S4(A,B,C,D) NS_##A##B##C##D
11481 #define X(N, L, C) S##N L
11494 enum neon_shape_class
11502 #define X(N, L, C) SC_##C
11504 static enum neon_shape_class neon_shape_class
[] =
11522 /* Register widths of above. */
11523 static unsigned neon_shape_el_size
[] =
11534 struct neon_shape_info
11537 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11540 #define S2(A,B) { SE_##A, SE_##B }
11541 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11542 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11544 #define X(N, L, C) { N, S##N L }
11546 static struct neon_shape_info neon_shape_tab
[] =
11556 /* Bit masks used in type checking given instructions.
11557 'N_EQK' means the type must be the same as (or based on in some way) the key
11558 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11559 set, various other bits can be set as well in order to modify the meaning of
11560 the type constraint. */
11562 enum neon_type_mask
11585 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11586 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11587 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11588 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11589 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11590 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11591 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11592 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11593 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11594 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11596 N_MAX_NONSPECIAL
= N_F64
11599 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11601 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11602 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11603 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11604 #define N_SUF_32 (N_SU_32 | N_F32)
11605 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11606 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11608 /* Pass this as the first type argument to neon_check_type to ignore types
11610 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11612 /* Select a "shape" for the current instruction (describing register types or
11613 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11614 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11615 function of operand parsing, so this function doesn't need to be called.
11616 Shapes should be listed in order of decreasing length. */
11618 static enum neon_shape
11619 neon_select_shape (enum neon_shape shape
, ...)
11622 enum neon_shape first_shape
= shape
;
11624 /* Fix missing optional operands. FIXME: we don't know at this point how
11625 many arguments we should have, so this makes the assumption that we have
11626 > 1. This is true of all current Neon opcodes, I think, but may not be
11627 true in the future. */
11628 if (!inst
.operands
[1].present
)
11629 inst
.operands
[1] = inst
.operands
[0];
11631 va_start (ap
, shape
);
11633 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11638 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11640 if (!inst
.operands
[j
].present
)
11646 switch (neon_shape_tab
[shape
].el
[j
])
11649 if (!(inst
.operands
[j
].isreg
11650 && inst
.operands
[j
].isvec
11651 && inst
.operands
[j
].issingle
11652 && !inst
.operands
[j
].isquad
))
11657 if (!(inst
.operands
[j
].isreg
11658 && inst
.operands
[j
].isvec
11659 && !inst
.operands
[j
].isquad
11660 && !inst
.operands
[j
].issingle
))
11665 if (!(inst
.operands
[j
].isreg
11666 && !inst
.operands
[j
].isvec
))
11671 if (!(inst
.operands
[j
].isreg
11672 && inst
.operands
[j
].isvec
11673 && inst
.operands
[j
].isquad
11674 && !inst
.operands
[j
].issingle
))
11679 if (!(!inst
.operands
[j
].isreg
11680 && !inst
.operands
[j
].isscalar
))
11685 if (!(!inst
.operands
[j
].isreg
11686 && inst
.operands
[j
].isscalar
))
11700 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11701 first_error (_("invalid instruction shape"));
11706 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11707 means the Q bit should be set). */
11710 neon_quad (enum neon_shape shape
)
11712 return neon_shape_class
[shape
] == SC_QUAD
;
11716 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11719 /* Allow modification to be made to types which are constrained to be
11720 based on the key element, based on bits set alongside N_EQK. */
11721 if ((typebits
& N_EQK
) != 0)
11723 if ((typebits
& N_HLF
) != 0)
11725 else if ((typebits
& N_DBL
) != 0)
11727 if ((typebits
& N_SGN
) != 0)
11728 *g_type
= NT_signed
;
11729 else if ((typebits
& N_UNS
) != 0)
11730 *g_type
= NT_unsigned
;
11731 else if ((typebits
& N_INT
) != 0)
11732 *g_type
= NT_integer
;
11733 else if ((typebits
& N_FLT
) != 0)
11734 *g_type
= NT_float
;
11735 else if ((typebits
& N_SIZ
) != 0)
11736 *g_type
= NT_untyped
;
11740 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11741 operand type, i.e. the single type specified in a Neon instruction when it
11742 is the only one given. */
11744 static struct neon_type_el
11745 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11747 struct neon_type_el dest
= *key
;
11749 gas_assert ((thisarg
& N_EQK
) != 0);
11751 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11756 /* Convert Neon type and size into compact bitmask representation. */
11758 static enum neon_type_mask
11759 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11766 case 8: return N_8
;
11767 case 16: return N_16
;
11768 case 32: return N_32
;
11769 case 64: return N_64
;
11777 case 8: return N_I8
;
11778 case 16: return N_I16
;
11779 case 32: return N_I32
;
11780 case 64: return N_I64
;
11788 case 16: return N_F16
;
11789 case 32: return N_F32
;
11790 case 64: return N_F64
;
11798 case 8: return N_P8
;
11799 case 16: return N_P16
;
11807 case 8: return N_S8
;
11808 case 16: return N_S16
;
11809 case 32: return N_S32
;
11810 case 64: return N_S64
;
11818 case 8: return N_U8
;
11819 case 16: return N_U16
;
11820 case 32: return N_U32
;
11821 case 64: return N_U64
;
11832 /* Convert compact Neon bitmask type representation to a type and size. Only
11833 handles the case where a single bit is set in the mask. */
11836 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11837 enum neon_type_mask mask
)
11839 if ((mask
& N_EQK
) != 0)
11842 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11844 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11846 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11848 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
11853 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
11855 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
11856 *type
= NT_unsigned
;
11857 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
11858 *type
= NT_integer
;
11859 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
11860 *type
= NT_untyped
;
11861 else if ((mask
& (N_P8
| N_P16
)) != 0)
11863 else if ((mask
& (N_F32
| N_F64
)) != 0)
11871 /* Modify a bitmask of allowed types. This is only needed for type
11875 modify_types_allowed (unsigned allowed
, unsigned mods
)
11878 enum neon_el_type type
;
11884 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11886 if (el_type_of_type_chk (&type
, &size
,
11887 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
11889 neon_modify_type_size (mods
, &type
, &size
);
11890 destmask
|= type_chk_of_el_type (type
, size
);
11897 /* Check type and return type classification.
11898 The manual states (paraphrase): If one datatype is given, it indicates the
11900 - the second operand, if there is one
11901 - the operand, if there is no second operand
11902 - the result, if there are no operands.
11903 This isn't quite good enough though, so we use a concept of a "key" datatype
11904 which is set on a per-instruction basis, which is the one which matters when
11905 only one data type is written.
11906 Note: this function has side-effects (e.g. filling in missing operands). All
11907 Neon instructions should call it before performing bit encoding. */
11909 static struct neon_type_el
11910 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11913 unsigned i
, pass
, key_el
= 0;
11914 unsigned types
[NEON_MAX_TYPE_ELS
];
11915 enum neon_el_type k_type
= NT_invtype
;
11916 unsigned k_size
= -1u;
11917 struct neon_type_el badtype
= {NT_invtype
, -1};
11918 unsigned key_allowed
= 0;
11920 /* Optional registers in Neon instructions are always (not) in operand 1.
11921 Fill in the missing operand here, if it was omitted. */
11922 if (els
> 1 && !inst
.operands
[1].present
)
11923 inst
.operands
[1] = inst
.operands
[0];
11925 /* Suck up all the varargs. */
11927 for (i
= 0; i
< els
; i
++)
11929 unsigned thisarg
= va_arg (ap
, unsigned);
11930 if (thisarg
== N_IGNORE_TYPE
)
11935 types
[i
] = thisarg
;
11936 if ((thisarg
& N_KEY
) != 0)
11941 if (inst
.vectype
.elems
> 0)
11942 for (i
= 0; i
< els
; i
++)
11943 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11945 first_error (_("types specified in both the mnemonic and operands"));
11949 /* Duplicate inst.vectype elements here as necessary.
11950 FIXME: No idea if this is exactly the same as the ARM assembler,
11951 particularly when an insn takes one register and one non-register
11953 if (inst
.vectype
.elems
== 1 && els
> 1)
11956 inst
.vectype
.elems
= els
;
11957 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11958 for (j
= 0; j
< els
; j
++)
11960 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11963 else if (inst
.vectype
.elems
== 0 && els
> 0)
11966 /* No types were given after the mnemonic, so look for types specified
11967 after each operand. We allow some flexibility here; as long as the
11968 "key" operand has a type, we can infer the others. */
11969 for (j
= 0; j
< els
; j
++)
11970 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11971 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11973 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11975 for (j
= 0; j
< els
; j
++)
11976 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11977 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11982 first_error (_("operand types can't be inferred"));
11986 else if (inst
.vectype
.elems
!= els
)
11988 first_error (_("type specifier has the wrong number of parts"));
11992 for (pass
= 0; pass
< 2; pass
++)
11994 for (i
= 0; i
< els
; i
++)
11996 unsigned thisarg
= types
[i
];
11997 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11998 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11999 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12000 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12002 /* Decay more-specific signed & unsigned types to sign-insensitive
12003 integer types if sign-specific variants are unavailable. */
12004 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12005 && (types_allowed
& N_SU_ALL
) == 0)
12006 g_type
= NT_integer
;
12008 /* If only untyped args are allowed, decay any more specific types to
12009 them. Some instructions only care about signs for some element
12010 sizes, so handle that properly. */
12011 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12012 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12013 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12014 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12015 g_type
= NT_untyped
;
12019 if ((thisarg
& N_KEY
) != 0)
12023 key_allowed
= thisarg
& ~N_KEY
;
12028 if ((thisarg
& N_VFP
) != 0)
12030 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
12031 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
12033 /* In VFP mode, operands must match register widths. If we
12034 have a key operand, use its width, else use the width of
12035 the current operand. */
12041 if (regwidth
!= match
)
12043 first_error (_("operand size must match register width"));
12048 if ((thisarg
& N_EQK
) == 0)
12050 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12052 if ((given_type
& types_allowed
) == 0)
12054 first_error (_("bad type in Neon instruction"));
12060 enum neon_el_type mod_k_type
= k_type
;
12061 unsigned mod_k_size
= k_size
;
12062 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12063 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12065 first_error (_("inconsistent types in Neon instruction"));
12073 return inst
.vectype
.el
[key_el
];
12076 /* Neon-style VFP instruction forwarding. */
12078 /* Thumb VFP instructions have 0xE in the condition field. */
12081 do_vfp_cond_or_thumb (void)
12084 inst
.instruction
|= 0xe0000000;
12086 inst
.instruction
|= inst
.cond
<< 28;
12089 /* Look up and encode a simple mnemonic, for use as a helper function for the
12090 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12091 etc. It is assumed that operand parsing has already been done, and that the
12092 operands are in the form expected by the given opcode (this isn't necessarily
12093 the same as the form in which they were parsed, hence some massaging must
12094 take place before this function is called).
12095 Checks current arch version against that in the looked-up opcode. */
12098 do_vfp_nsyn_opcode (const char *opname
)
12100 const struct asm_opcode
*opcode
;
12102 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12107 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12108 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12113 inst
.instruction
= opcode
->tvalue
;
12114 opcode
->tencode ();
12118 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12119 opcode
->aencode ();
12124 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12126 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12131 do_vfp_nsyn_opcode ("fadds");
12133 do_vfp_nsyn_opcode ("fsubs");
12138 do_vfp_nsyn_opcode ("faddd");
12140 do_vfp_nsyn_opcode ("fsubd");
12144 /* Check operand types to see if this is a VFP instruction, and if so call
12148 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12150 enum neon_shape rs
;
12151 struct neon_type_el et
;
12156 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12157 et
= neon_check_type (2, rs
,
12158 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12162 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12163 et
= neon_check_type (3, rs
,
12164 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12171 if (et
.type
!= NT_invtype
)
12183 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12185 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12190 do_vfp_nsyn_opcode ("fmacs");
12192 do_vfp_nsyn_opcode ("fnmacs");
12197 do_vfp_nsyn_opcode ("fmacd");
12199 do_vfp_nsyn_opcode ("fnmacd");
12204 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12206 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12211 do_vfp_nsyn_opcode ("ffmas");
12213 do_vfp_nsyn_opcode ("ffnmas");
12218 do_vfp_nsyn_opcode ("ffmad");
12220 do_vfp_nsyn_opcode ("ffnmad");
12225 do_vfp_nsyn_mul (enum neon_shape rs
)
12228 do_vfp_nsyn_opcode ("fmuls");
12230 do_vfp_nsyn_opcode ("fmuld");
12234 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12236 int is_neg
= (inst
.instruction
& 0x80) != 0;
12237 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12242 do_vfp_nsyn_opcode ("fnegs");
12244 do_vfp_nsyn_opcode ("fabss");
12249 do_vfp_nsyn_opcode ("fnegd");
12251 do_vfp_nsyn_opcode ("fabsd");
12255 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12256 insns belong to Neon, and are handled elsewhere. */
12259 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12261 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12265 do_vfp_nsyn_opcode ("fldmdbs");
12267 do_vfp_nsyn_opcode ("fldmias");
12272 do_vfp_nsyn_opcode ("fstmdbs");
12274 do_vfp_nsyn_opcode ("fstmias");
12279 do_vfp_nsyn_sqrt (void)
12281 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12282 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12285 do_vfp_nsyn_opcode ("fsqrts");
12287 do_vfp_nsyn_opcode ("fsqrtd");
12291 do_vfp_nsyn_div (void)
12293 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12294 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12295 N_F32
| N_F64
| N_KEY
| N_VFP
);
12298 do_vfp_nsyn_opcode ("fdivs");
12300 do_vfp_nsyn_opcode ("fdivd");
12304 do_vfp_nsyn_nmul (void)
12306 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12307 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12308 N_F32
| N_F64
| N_KEY
| N_VFP
);
12312 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12313 do_vfp_sp_dyadic ();
12317 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12318 do_vfp_dp_rd_rn_rm ();
12320 do_vfp_cond_or_thumb ();
12324 do_vfp_nsyn_cmp (void)
12326 if (inst
.operands
[1].isreg
)
12328 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12329 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12333 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12334 do_vfp_sp_monadic ();
12338 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12339 do_vfp_dp_rd_rm ();
12344 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12345 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12347 switch (inst
.instruction
& 0x0fffffff)
12350 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12353 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12361 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12362 do_vfp_sp_compare_z ();
12366 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12370 do_vfp_cond_or_thumb ();
12374 nsyn_insert_sp (void)
12376 inst
.operands
[1] = inst
.operands
[0];
12377 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12378 inst
.operands
[0].reg
= REG_SP
;
12379 inst
.operands
[0].isreg
= 1;
12380 inst
.operands
[0].writeback
= 1;
12381 inst
.operands
[0].present
= 1;
12385 do_vfp_nsyn_push (void)
12388 if (inst
.operands
[1].issingle
)
12389 do_vfp_nsyn_opcode ("fstmdbs");
12391 do_vfp_nsyn_opcode ("fstmdbd");
12395 do_vfp_nsyn_pop (void)
12398 if (inst
.operands
[1].issingle
)
12399 do_vfp_nsyn_opcode ("fldmias");
12401 do_vfp_nsyn_opcode ("fldmiad");
12404 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12405 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12408 neon_dp_fixup (unsigned i
)
12412 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12426 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12430 neon_logbits (unsigned x
)
12432 return ffs (x
) - 4;
12435 #define LOW4(R) ((R) & 0xf)
12436 #define HI1(R) (((R) >> 4) & 1)
12438 /* Encode insns with bit pattern:
12440 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12441 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12443 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12444 different meaning for some instruction. */
12447 neon_three_same (int isquad
, int ubit
, int size
)
12449 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12450 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12451 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12452 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12453 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12454 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12455 inst
.instruction
|= (isquad
!= 0) << 6;
12456 inst
.instruction
|= (ubit
!= 0) << 24;
12458 inst
.instruction
|= neon_logbits (size
) << 20;
12460 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12463 /* Encode instructions of the form:
12465 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12466 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12468 Don't write size if SIZE == -1. */
12471 neon_two_same (int qbit
, int ubit
, int size
)
12473 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12474 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12475 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12476 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12477 inst
.instruction
|= (qbit
!= 0) << 6;
12478 inst
.instruction
|= (ubit
!= 0) << 24;
12481 inst
.instruction
|= neon_logbits (size
) << 18;
12483 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12486 /* Neon instruction encoders, in approximate order of appearance. */
12489 do_neon_dyadic_i_su (void)
12491 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12492 struct neon_type_el et
= neon_check_type (3, rs
,
12493 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12494 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12498 do_neon_dyadic_i64_su (void)
12500 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12501 struct neon_type_el et
= neon_check_type (3, rs
,
12502 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12503 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12507 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12510 unsigned size
= et
.size
>> 3;
12511 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12512 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12513 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12514 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12515 inst
.instruction
|= (isquad
!= 0) << 6;
12516 inst
.instruction
|= immbits
<< 16;
12517 inst
.instruction
|= (size
>> 3) << 7;
12518 inst
.instruction
|= (size
& 0x7) << 19;
12520 inst
.instruction
|= (uval
!= 0) << 24;
12522 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12526 do_neon_shl_imm (void)
12528 if (!inst
.operands
[2].isreg
)
12530 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12531 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12532 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12533 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12537 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12538 struct neon_type_el et
= neon_check_type (3, rs
,
12539 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12542 /* VSHL/VQSHL 3-register variants have syntax such as:
12544 whereas other 3-register operations encoded by neon_three_same have
12547 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12549 tmp
= inst
.operands
[2].reg
;
12550 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12551 inst
.operands
[1].reg
= tmp
;
12552 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12553 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12558 do_neon_qshl_imm (void)
12560 if (!inst
.operands
[2].isreg
)
12562 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12563 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12565 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12566 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12567 inst
.operands
[2].imm
);
12571 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12572 struct neon_type_el et
= neon_check_type (3, rs
,
12573 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12576 /* See note in do_neon_shl_imm. */
12577 tmp
= inst
.operands
[2].reg
;
12578 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12579 inst
.operands
[1].reg
= tmp
;
12580 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12581 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12586 do_neon_rshl (void)
12588 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12589 struct neon_type_el et
= neon_check_type (3, rs
,
12590 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12593 tmp
= inst
.operands
[2].reg
;
12594 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12595 inst
.operands
[1].reg
= tmp
;
12596 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12600 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12602 /* Handle .I8 pseudo-instructions. */
12605 /* Unfortunately, this will make everything apart from zero out-of-range.
12606 FIXME is this the intended semantics? There doesn't seem much point in
12607 accepting .I8 if so. */
12608 immediate
|= immediate
<< 8;
12614 if (immediate
== (immediate
& 0x000000ff))
12616 *immbits
= immediate
;
12619 else if (immediate
== (immediate
& 0x0000ff00))
12621 *immbits
= immediate
>> 8;
12624 else if (immediate
== (immediate
& 0x00ff0000))
12626 *immbits
= immediate
>> 16;
12629 else if (immediate
== (immediate
& 0xff000000))
12631 *immbits
= immediate
>> 24;
12634 if ((immediate
& 0xffff) != (immediate
>> 16))
12635 goto bad_immediate
;
12636 immediate
&= 0xffff;
12639 if (immediate
== (immediate
& 0x000000ff))
12641 *immbits
= immediate
;
12644 else if (immediate
== (immediate
& 0x0000ff00))
12646 *immbits
= immediate
>> 8;
12651 first_error (_("immediate value out of range"));
12655 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12659 neon_bits_same_in_bytes (unsigned imm
)
12661 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12662 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12663 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12664 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12667 /* For immediate of above form, return 0bABCD. */
12670 neon_squash_bits (unsigned imm
)
12672 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12673 | ((imm
& 0x01000000) >> 21);
12676 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12679 neon_qfloat_bits (unsigned imm
)
12681 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12684 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12685 the instruction. *OP is passed as the initial value of the op field, and
12686 may be set to a different value depending on the constant (i.e.
12687 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12688 MVN). If the immediate looks like a repeated pattern then also
12689 try smaller element sizes. */
12692 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12693 unsigned *immbits
, int *op
, int size
,
12694 enum neon_el_type type
)
12696 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12698 if (type
== NT_float
&& !float_p
)
12701 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12703 if (size
!= 32 || *op
== 1)
12705 *immbits
= neon_qfloat_bits (immlo
);
12711 if (neon_bits_same_in_bytes (immhi
)
12712 && neon_bits_same_in_bytes (immlo
))
12716 *immbits
= (neon_squash_bits (immhi
) << 4)
12717 | neon_squash_bits (immlo
);
12722 if (immhi
!= immlo
)
12728 if (immlo
== (immlo
& 0x000000ff))
12733 else if (immlo
== (immlo
& 0x0000ff00))
12735 *immbits
= immlo
>> 8;
12738 else if (immlo
== (immlo
& 0x00ff0000))
12740 *immbits
= immlo
>> 16;
12743 else if (immlo
== (immlo
& 0xff000000))
12745 *immbits
= immlo
>> 24;
12748 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12750 *immbits
= (immlo
>> 8) & 0xff;
12753 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12755 *immbits
= (immlo
>> 16) & 0xff;
12759 if ((immlo
& 0xffff) != (immlo
>> 16))
12766 if (immlo
== (immlo
& 0x000000ff))
12771 else if (immlo
== (immlo
& 0x0000ff00))
12773 *immbits
= immlo
>> 8;
12777 if ((immlo
& 0xff) != (immlo
>> 8))
12782 if (immlo
== (immlo
& 0x000000ff))
12784 /* Don't allow MVN with 8-bit immediate. */
12794 /* Write immediate bits [7:0] to the following locations:
12796 |28/24|23 19|18 16|15 4|3 0|
12797 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12799 This function is used by VMOV/VMVN/VORR/VBIC. */
12802 neon_write_immbits (unsigned immbits
)
12804 inst
.instruction
|= immbits
& 0xf;
12805 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12806 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12809 /* Invert low-order SIZE bits of XHI:XLO. */
12812 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12814 unsigned immlo
= xlo
? *xlo
: 0;
12815 unsigned immhi
= xhi
? *xhi
: 0;
12820 immlo
= (~immlo
) & 0xff;
12824 immlo
= (~immlo
) & 0xffff;
12828 immhi
= (~immhi
) & 0xffffffff;
12829 /* fall through. */
12832 immlo
= (~immlo
) & 0xffffffff;
12847 do_neon_logic (void)
12849 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
12851 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12852 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12853 /* U bit and size field were set as part of the bitmask. */
12854 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12855 neon_three_same (neon_quad (rs
), 0, -1);
12859 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12860 struct neon_type_el et
= neon_check_type (2, rs
,
12861 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12862 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
12866 if (et
.type
== NT_invtype
)
12869 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12871 immbits
= inst
.operands
[1].imm
;
12874 /* .i64 is a pseudo-op, so the immediate must be a repeating
12876 if (immbits
!= (inst
.operands
[1].regisimm
?
12877 inst
.operands
[1].reg
: 0))
12879 /* Set immbits to an invalid constant. */
12880 immbits
= 0xdeadbeef;
12887 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12891 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12895 /* Pseudo-instruction for VBIC. */
12896 neon_invert_size (&immbits
, 0, et
.size
);
12897 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12901 /* Pseudo-instruction for VORR. */
12902 neon_invert_size (&immbits
, 0, et
.size
);
12903 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12913 inst
.instruction
|= neon_quad (rs
) << 6;
12914 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12915 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12916 inst
.instruction
|= cmode
<< 8;
12917 neon_write_immbits (immbits
);
12919 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12924 do_neon_bitfield (void)
12926 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12927 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12928 neon_three_same (neon_quad (rs
), 0, -1);
12932 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12935 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12936 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12938 if (et
.type
== NT_float
)
12940 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12941 neon_three_same (neon_quad (rs
), 0, -1);
12945 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12946 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12951 do_neon_dyadic_if_su (void)
12953 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12957 do_neon_dyadic_if_su_d (void)
12959 /* This version only allow D registers, but that constraint is enforced during
12960 operand parsing so we don't need to do anything extra here. */
12961 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12965 do_neon_dyadic_if_i_d (void)
12967 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12968 affected if we specify unsigned args. */
12969 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12972 enum vfp_or_neon_is_neon_bits
12975 NEON_CHECK_ARCH
= 2
12978 /* Call this function if an instruction which may have belonged to the VFP or
12979 Neon instruction sets, but turned out to be a Neon instruction (due to the
12980 operand types involved, etc.). We have to check and/or fix-up a couple of
12983 - Make sure the user hasn't attempted to make a Neon instruction
12985 - Alter the value in the condition code field if necessary.
12986 - Make sure that the arch supports Neon instructions.
12988 Which of these operations take place depends on bits from enum
12989 vfp_or_neon_is_neon_bits.
12991 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12992 current instruction's condition is COND_ALWAYS, the condition field is
12993 changed to inst.uncond_value. This is necessary because instructions shared
12994 between VFP and Neon may be conditional for the VFP variants only, and the
12995 unconditional Neon version must have, e.g., 0xF in the condition field. */
12998 vfp_or_neon_is_neon (unsigned check
)
13000 /* Conditions are always legal in Thumb mode (IT blocks). */
13001 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13003 if (inst
.cond
!= COND_ALWAYS
)
13005 first_error (_(BAD_COND
));
13008 if (inst
.uncond_value
!= -1)
13009 inst
.instruction
|= inst
.uncond_value
<< 28;
13012 if ((check
& NEON_CHECK_ARCH
)
13013 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13015 first_error (_(BAD_FPU
));
13023 do_neon_addsub_if_i (void)
13025 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13028 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13031 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13032 affected if we specify unsigned args. */
13033 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13036 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13038 V<op> A,B (A is operand 0, B is operand 2)
13043 so handle that case specially. */
13046 neon_exchange_operands (void)
13048 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13049 if (inst
.operands
[1].present
)
13051 /* Swap operands[1] and operands[2]. */
13052 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13053 inst
.operands
[1] = inst
.operands
[2];
13054 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13058 inst
.operands
[1] = inst
.operands
[2];
13059 inst
.operands
[2] = inst
.operands
[0];
13064 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13066 if (inst
.operands
[2].isreg
)
13069 neon_exchange_operands ();
13070 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13074 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13075 struct neon_type_el et
= neon_check_type (2, rs
,
13076 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13078 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13079 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13080 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13081 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13082 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13083 inst
.instruction
|= neon_quad (rs
) << 6;
13084 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13085 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13087 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13094 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13098 do_neon_cmp_inv (void)
13100 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13106 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13109 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13110 scalars, which are encoded in 5 bits, M : Rm.
13111 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13112 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13116 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13118 unsigned regno
= NEON_SCALAR_REG (scalar
);
13119 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13124 if (regno
> 7 || elno
> 3)
13126 return regno
| (elno
<< 3);
13129 if (regno
> 15 || elno
> 1)
13131 return regno
| (elno
<< 4);
13135 first_error (_("scalar out of range for multiply instruction"));
13141 /* Encode multiply / multiply-accumulate scalar instructions. */
13144 neon_mul_mac (struct neon_type_el et
, int ubit
)
13148 /* Give a more helpful error message if we have an invalid type. */
13149 if (et
.type
== NT_invtype
)
13152 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13153 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13154 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13155 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13156 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13157 inst
.instruction
|= LOW4 (scalar
);
13158 inst
.instruction
|= HI1 (scalar
) << 5;
13159 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13160 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13161 inst
.instruction
|= (ubit
!= 0) << 24;
13163 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13167 do_neon_mac_maybe_scalar (void)
13169 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13172 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13175 if (inst
.operands
[2].isscalar
)
13177 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13178 struct neon_type_el et
= neon_check_type (3, rs
,
13179 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13180 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13181 neon_mul_mac (et
, neon_quad (rs
));
13185 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13186 affected if we specify unsigned args. */
13187 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13192 do_neon_fmac (void)
13194 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13197 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13200 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13206 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13207 struct neon_type_el et
= neon_check_type (3, rs
,
13208 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13209 neon_three_same (neon_quad (rs
), 0, et
.size
);
13212 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13213 same types as the MAC equivalents. The polynomial type for this instruction
13214 is encoded the same as the integer type. */
13219 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13222 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13225 if (inst
.operands
[2].isscalar
)
13226 do_neon_mac_maybe_scalar ();
13228 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13232 do_neon_qdmulh (void)
13234 if (inst
.operands
[2].isscalar
)
13236 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13237 struct neon_type_el et
= neon_check_type (3, rs
,
13238 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13239 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13240 neon_mul_mac (et
, neon_quad (rs
));
13244 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13245 struct neon_type_el et
= neon_check_type (3, rs
,
13246 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13247 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13248 /* The U bit (rounding) comes from bit mask. */
13249 neon_three_same (neon_quad (rs
), 0, et
.size
);
13254 do_neon_fcmp_absolute (void)
13256 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13257 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13258 /* Size field comes from bit mask. */
13259 neon_three_same (neon_quad (rs
), 1, -1);
13263 do_neon_fcmp_absolute_inv (void)
13265 neon_exchange_operands ();
13266 do_neon_fcmp_absolute ();
13270 do_neon_step (void)
13272 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13273 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13274 neon_three_same (neon_quad (rs
), 0, -1);
13278 do_neon_abs_neg (void)
13280 enum neon_shape rs
;
13281 struct neon_type_el et
;
13283 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13286 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13289 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13290 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13292 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13293 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13294 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13295 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13296 inst
.instruction
|= neon_quad (rs
) << 6;
13297 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13298 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13300 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13306 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13307 struct neon_type_el et
= neon_check_type (2, rs
,
13308 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13309 int imm
= inst
.operands
[2].imm
;
13310 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13311 _("immediate out of range for insert"));
13312 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13318 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13319 struct neon_type_el et
= neon_check_type (2, rs
,
13320 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13321 int imm
= inst
.operands
[2].imm
;
13322 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13323 _("immediate out of range for insert"));
13324 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13328 do_neon_qshlu_imm (void)
13330 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13331 struct neon_type_el et
= neon_check_type (2, rs
,
13332 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13333 int imm
= inst
.operands
[2].imm
;
13334 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13335 _("immediate out of range for shift"));
13336 /* Only encodes the 'U present' variant of the instruction.
13337 In this case, signed types have OP (bit 8) set to 0.
13338 Unsigned types have OP set to 1. */
13339 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13340 /* The rest of the bits are the same as other immediate shifts. */
13341 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13345 do_neon_qmovn (void)
13347 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13348 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13349 /* Saturating move where operands can be signed or unsigned, and the
13350 destination has the same signedness. */
13351 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13352 if (et
.type
== NT_unsigned
)
13353 inst
.instruction
|= 0xc0;
13355 inst
.instruction
|= 0x80;
13356 neon_two_same (0, 1, et
.size
/ 2);
13360 do_neon_qmovun (void)
13362 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13363 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13364 /* Saturating move with unsigned results. Operands must be signed. */
13365 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13366 neon_two_same (0, 1, et
.size
/ 2);
13370 do_neon_rshift_sat_narrow (void)
13372 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13373 or unsigned. If operands are unsigned, results must also be unsigned. */
13374 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13375 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13376 int imm
= inst
.operands
[2].imm
;
13377 /* This gets the bounds check, size encoding and immediate bits calculation
13381 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13382 VQMOVN.I<size> <Dd>, <Qm>. */
13385 inst
.operands
[2].present
= 0;
13386 inst
.instruction
= N_MNEM_vqmovn
;
13391 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13392 _("immediate out of range"));
13393 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13397 do_neon_rshift_sat_narrow_u (void)
13399 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13400 or unsigned. If operands are unsigned, results must also be unsigned. */
13401 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13402 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13403 int imm
= inst
.operands
[2].imm
;
13404 /* This gets the bounds check, size encoding and immediate bits calculation
13408 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13409 VQMOVUN.I<size> <Dd>, <Qm>. */
13412 inst
.operands
[2].present
= 0;
13413 inst
.instruction
= N_MNEM_vqmovun
;
13418 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13419 _("immediate out of range"));
13420 /* FIXME: The manual is kind of unclear about what value U should have in
13421 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13423 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13427 do_neon_movn (void)
13429 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13430 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13431 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13432 neon_two_same (0, 1, et
.size
/ 2);
13436 do_neon_rshift_narrow (void)
13438 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13439 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13440 int imm
= inst
.operands
[2].imm
;
13441 /* This gets the bounds check, size encoding and immediate bits calculation
13445 /* If immediate is zero then we are a pseudo-instruction for
13446 VMOVN.I<size> <Dd>, <Qm> */
13449 inst
.operands
[2].present
= 0;
13450 inst
.instruction
= N_MNEM_vmovn
;
13455 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13456 _("immediate out of range for narrowing operation"));
13457 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13461 do_neon_shll (void)
13463 /* FIXME: Type checking when lengthening. */
13464 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13465 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13466 unsigned imm
= inst
.operands
[2].imm
;
13468 if (imm
== et
.size
)
13470 /* Maximum shift variant. */
13471 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13472 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13473 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13474 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13475 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13476 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13478 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13482 /* A more-specific type check for non-max versions. */
13483 et
= neon_check_type (2, NS_QDI
,
13484 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13485 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13486 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13490 /* Check the various types for the VCVT instruction, and return which version
13491 the current instruction is. */
13494 neon_cvt_flavour (enum neon_shape rs
)
13496 #define CVT_VAR(C,X,Y) \
13497 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13498 if (et.type != NT_invtype) \
13500 inst.error = NULL; \
13503 struct neon_type_el et
;
13504 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13505 || rs
== NS_FF
) ? N_VFP
: 0;
13506 /* The instruction versions which take an immediate take one register
13507 argument, which is extended to the width of the full register. Thus the
13508 "source" and "destination" registers must have the same width. Hack that
13509 here by making the size equal to the key (wider, in this case) operand. */
13510 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13512 CVT_VAR (0, N_S32
, N_F32
);
13513 CVT_VAR (1, N_U32
, N_F32
);
13514 CVT_VAR (2, N_F32
, N_S32
);
13515 CVT_VAR (3, N_F32
, N_U32
);
13516 /* Half-precision conversions. */
13517 CVT_VAR (4, N_F32
, N_F16
);
13518 CVT_VAR (5, N_F16
, N_F32
);
13522 /* VFP instructions. */
13523 CVT_VAR (6, N_F32
, N_F64
);
13524 CVT_VAR (7, N_F64
, N_F32
);
13525 CVT_VAR (8, N_S32
, N_F64
| key
);
13526 CVT_VAR (9, N_U32
, N_F64
| key
);
13527 CVT_VAR (10, N_F64
| key
, N_S32
);
13528 CVT_VAR (11, N_F64
| key
, N_U32
);
13529 /* VFP instructions with bitshift. */
13530 CVT_VAR (12, N_F32
| key
, N_S16
);
13531 CVT_VAR (13, N_F32
| key
, N_U16
);
13532 CVT_VAR (14, N_F64
| key
, N_S16
);
13533 CVT_VAR (15, N_F64
| key
, N_U16
);
13534 CVT_VAR (16, N_S16
, N_F32
| key
);
13535 CVT_VAR (17, N_U16
, N_F32
| key
);
13536 CVT_VAR (18, N_S16
, N_F64
| key
);
13537 CVT_VAR (19, N_U16
, N_F64
| key
);
13543 /* Neon-syntax VFP conversions. */
13546 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13548 const char *opname
= 0;
13550 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13552 /* Conversions with immediate bitshift. */
13553 const char *enc
[] =
13577 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13579 opname
= enc
[flavour
];
13580 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13581 _("operands 0 and 1 must be the same register"));
13582 inst
.operands
[1] = inst
.operands
[2];
13583 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13588 /* Conversions without bitshift. */
13589 const char *enc
[] =
13605 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13606 opname
= enc
[flavour
];
13610 do_vfp_nsyn_opcode (opname
);
13614 do_vfp_nsyn_cvtz (void)
13616 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13617 int flavour
= neon_cvt_flavour (rs
);
13618 const char *enc
[] =
13632 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13633 do_vfp_nsyn_opcode (enc
[flavour
]);
13639 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13640 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13641 int flavour
= neon_cvt_flavour (rs
);
13643 /* VFP rather than Neon conversions. */
13646 do_vfp_nsyn_cvt (rs
, flavour
);
13656 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13658 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13661 /* Fixed-point conversion with #0 immediate is encoded as an
13662 integer conversion. */
13663 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13665 immbits
= 32 - inst
.operands
[2].imm
;
13666 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13668 inst
.instruction
|= enctab
[flavour
];
13669 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13670 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13671 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13672 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13673 inst
.instruction
|= neon_quad (rs
) << 6;
13674 inst
.instruction
|= 1 << 21;
13675 inst
.instruction
|= immbits
<< 16;
13677 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13685 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13687 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13689 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13693 inst
.instruction
|= enctab
[flavour
];
13695 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13696 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13697 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13698 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13699 inst
.instruction
|= neon_quad (rs
) << 6;
13700 inst
.instruction
|= 2 << 18;
13702 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13706 /* Half-precision conversions for Advanced SIMD -- neon. */
13711 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13713 as_bad (_("operand size must match register width"));
13718 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13720 as_bad (_("operand size must match register width"));
13725 inst
.instruction
= 0x3b60600;
13727 inst
.instruction
= 0x3b60700;
13729 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13730 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13731 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13732 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13733 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13737 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13738 do_vfp_nsyn_cvt (rs
, flavour
);
13743 do_neon_cvtb (void)
13745 inst
.instruction
= 0xeb20a40;
13747 /* The sizes are attached to the mnemonic. */
13748 if (inst
.vectype
.el
[0].type
!= NT_invtype
13749 && inst
.vectype
.el
[0].size
== 16)
13750 inst
.instruction
|= 0x00010000;
13752 /* Programmer's syntax: the sizes are attached to the operands. */
13753 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13754 && inst
.operands
[0].vectype
.size
== 16)
13755 inst
.instruction
|= 0x00010000;
13757 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13758 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13759 do_vfp_cond_or_thumb ();
13764 do_neon_cvtt (void)
13767 inst
.instruction
|= 0x80;
13771 neon_move_immediate (void)
13773 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13774 struct neon_type_el et
= neon_check_type (2, rs
,
13775 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13776 unsigned immlo
, immhi
= 0, immbits
;
13777 int op
, cmode
, float_p
;
13779 constraint (et
.type
== NT_invtype
,
13780 _("operand size must be specified for immediate VMOV"));
13782 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13783 op
= (inst
.instruction
& (1 << 5)) != 0;
13785 immlo
= inst
.operands
[1].imm
;
13786 if (inst
.operands
[1].regisimm
)
13787 immhi
= inst
.operands
[1].reg
;
13789 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
13790 _("immediate has bits set outside the operand size"));
13792 float_p
= inst
.operands
[1].immisfloat
;
13794 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
13795 et
.size
, et
.type
)) == FAIL
)
13797 /* Invert relevant bits only. */
13798 neon_invert_size (&immlo
, &immhi
, et
.size
);
13799 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13800 with one or the other; those cases are caught by
13801 neon_cmode_for_move_imm. */
13803 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
13804 &op
, et
.size
, et
.type
)) == FAIL
)
13806 first_error (_("immediate out of range"));
13811 inst
.instruction
&= ~(1 << 5);
13812 inst
.instruction
|= op
<< 5;
13814 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13815 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13816 inst
.instruction
|= neon_quad (rs
) << 6;
13817 inst
.instruction
|= cmode
<< 8;
13819 neon_write_immbits (immbits
);
13825 if (inst
.operands
[1].isreg
)
13827 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13829 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13830 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13831 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13832 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13833 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13834 inst
.instruction
|= neon_quad (rs
) << 6;
13838 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13839 neon_move_immediate ();
13842 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13845 /* Encode instructions of form:
13847 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13848 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
13851 neon_mixed_length (struct neon_type_el et
, unsigned size
)
13853 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13854 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13855 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13856 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13857 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13858 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13859 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
13860 inst
.instruction
|= neon_logbits (size
) << 20;
13862 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13866 do_neon_dyadic_long (void)
13868 /* FIXME: Type checking for lengthening op. */
13869 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13870 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13871 neon_mixed_length (et
, et
.size
);
13875 do_neon_abal (void)
13877 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13878 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13879 neon_mixed_length (et
, et
.size
);
13883 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
13885 if (inst
.operands
[2].isscalar
)
13887 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
13888 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
13889 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13890 neon_mul_mac (et
, et
.type
== NT_unsigned
);
13894 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13895 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
13896 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13897 neon_mixed_length (et
, et
.size
);
13902 do_neon_mac_maybe_scalar_long (void)
13904 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
13908 do_neon_dyadic_wide (void)
13910 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
13911 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13912 neon_mixed_length (et
, et
.size
);
13916 do_neon_dyadic_narrow (void)
13918 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13919 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
13920 /* Operand sign is unimportant, and the U bit is part of the opcode,
13921 so force the operand type to integer. */
13922 et
.type
= NT_integer
;
13923 neon_mixed_length (et
, et
.size
/ 2);
13927 do_neon_mul_sat_scalar_long (void)
13929 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
13933 do_neon_vmull (void)
13935 if (inst
.operands
[2].isscalar
)
13936 do_neon_mac_maybe_scalar_long ();
13939 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13940 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
13941 if (et
.type
== NT_poly
)
13942 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
13944 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13945 /* For polynomial encoding, size field must be 0b00 and the U bit must be
13946 zero. Should be OK as-is. */
13947 neon_mixed_length (et
, et
.size
);
13954 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
13955 struct neon_type_el et
= neon_check_type (3, rs
,
13956 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13957 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
13959 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
13960 _("shift out of range"));
13961 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13962 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13963 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13964 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13965 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13966 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13967 inst
.instruction
|= neon_quad (rs
) << 6;
13968 inst
.instruction
|= imm
<< 8;
13970 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13976 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13977 struct neon_type_el et
= neon_check_type (2, rs
,
13978 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13979 unsigned op
= (inst
.instruction
>> 7) & 3;
13980 /* N (width of reversed regions) is encoded as part of the bitmask. We
13981 extract it here to check the elements to be reversed are smaller.
13982 Otherwise we'd get a reserved instruction. */
13983 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
13984 gas_assert (elsize
!= 0);
13985 constraint (et
.size
>= elsize
,
13986 _("elements must be smaller than reversal region"));
13987 neon_two_same (neon_quad (rs
), 1, et
.size
);
13993 if (inst
.operands
[1].isscalar
)
13995 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
13996 struct neon_type_el et
= neon_check_type (2, rs
,
13997 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13998 unsigned sizebits
= et
.size
>> 3;
13999 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14000 int logsize
= neon_logbits (et
.size
);
14001 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14003 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14006 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
14007 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14008 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14009 inst
.instruction
|= LOW4 (dm
);
14010 inst
.instruction
|= HI1 (dm
) << 5;
14011 inst
.instruction
|= neon_quad (rs
) << 6;
14012 inst
.instruction
|= x
<< 17;
14013 inst
.instruction
|= sizebits
<< 16;
14015 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14019 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14020 struct neon_type_el et
= neon_check_type (2, rs
,
14021 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14022 /* Duplicate ARM register to lanes of vector. */
14023 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
14026 case 8: inst
.instruction
|= 0x400000; break;
14027 case 16: inst
.instruction
|= 0x000020; break;
14028 case 32: inst
.instruction
|= 0x000000; break;
14031 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14032 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14033 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14034 inst
.instruction
|= neon_quad (rs
) << 21;
14035 /* The encoding for this instruction is identical for the ARM and Thumb
14036 variants, except for the condition field. */
14037 do_vfp_cond_or_thumb ();
14041 /* VMOV has particularly many variations. It can be one of:
14042 0. VMOV<c><q> <Qd>, <Qm>
14043 1. VMOV<c><q> <Dd>, <Dm>
14044 (Register operations, which are VORR with Rm = Rn.)
14045 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14046 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14048 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14049 (ARM register to scalar.)
14050 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14051 (Two ARM registers to vector.)
14052 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14053 (Scalar to ARM register.)
14054 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14055 (Vector to two ARM registers.)
14056 8. VMOV.F32 <Sd>, <Sm>
14057 9. VMOV.F64 <Dd>, <Dm>
14058 (VFP register moves.)
14059 10. VMOV.F32 <Sd>, #imm
14060 11. VMOV.F64 <Dd>, #imm
14061 (VFP float immediate load.)
14062 12. VMOV <Rd>, <Sm>
14063 (VFP single to ARM reg.)
14064 13. VMOV <Sd>, <Rm>
14065 (ARM reg to VFP single.)
14066 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14067 (Two ARM regs to two VFP singles.)
14068 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14069 (Two VFP singles to two ARM regs.)
14071 These cases can be disambiguated using neon_select_shape, except cases 1/9
14072 and 3/11 which depend on the operand type too.
14074 All the encoded bits are hardcoded by this function.
14076 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14077 Cases 5, 7 may be used with VFPv2 and above.
14079 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14080 can specify a type where it doesn't make sense to, and is ignored). */
14085 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14086 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14088 struct neon_type_el et
;
14089 const char *ldconst
= 0;
14093 case NS_DD
: /* case 1/9. */
14094 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14095 /* It is not an error here if no type is given. */
14097 if (et
.type
== NT_float
&& et
.size
== 64)
14099 do_vfp_nsyn_opcode ("fcpyd");
14102 /* fall through. */
14104 case NS_QQ
: /* case 0/1. */
14106 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14108 /* The architecture manual I have doesn't explicitly state which
14109 value the U bit should have for register->register moves, but
14110 the equivalent VORR instruction has U = 0, so do that. */
14111 inst
.instruction
= 0x0200110;
14112 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14113 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14114 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14115 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14116 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14117 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14118 inst
.instruction
|= neon_quad (rs
) << 6;
14120 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14124 case NS_DI
: /* case 3/11. */
14125 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14127 if (et
.type
== NT_float
&& et
.size
== 64)
14129 /* case 11 (fconstd). */
14130 ldconst
= "fconstd";
14131 goto encode_fconstd
;
14133 /* fall through. */
14135 case NS_QI
: /* case 2/3. */
14136 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14138 inst
.instruction
= 0x0800010;
14139 neon_move_immediate ();
14140 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14143 case NS_SR
: /* case 4. */
14145 unsigned bcdebits
= 0;
14146 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
14147 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14148 int logsize
= neon_logbits (et
.size
);
14149 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14150 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14152 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14154 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14155 && et
.size
!= 32, _(BAD_FPU
));
14156 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14157 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14161 case 8: bcdebits
= 0x8; break;
14162 case 16: bcdebits
= 0x1; break;
14163 case 32: bcdebits
= 0x0; break;
14167 bcdebits
|= x
<< logsize
;
14169 inst
.instruction
= 0xe000b10;
14170 do_vfp_cond_or_thumb ();
14171 inst
.instruction
|= LOW4 (dn
) << 16;
14172 inst
.instruction
|= HI1 (dn
) << 7;
14173 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14174 inst
.instruction
|= (bcdebits
& 3) << 5;
14175 inst
.instruction
|= (bcdebits
>> 2) << 21;
14179 case NS_DRR
: /* case 5 (fmdrr). */
14180 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14183 inst
.instruction
= 0xc400b10;
14184 do_vfp_cond_or_thumb ();
14185 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14186 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14187 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14188 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14191 case NS_RS
: /* case 6. */
14193 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
14194 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14195 unsigned logsize
= neon_logbits (et
.size
);
14196 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14197 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14198 unsigned abcdebits
= 0;
14200 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14202 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14203 && et
.size
!= 32, _(BAD_FPU
));
14204 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14205 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14209 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14210 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14211 case 32: abcdebits
= 0x00; break;
14215 abcdebits
|= x
<< logsize
;
14216 inst
.instruction
= 0xe100b10;
14217 do_vfp_cond_or_thumb ();
14218 inst
.instruction
|= LOW4 (dn
) << 16;
14219 inst
.instruction
|= HI1 (dn
) << 7;
14220 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14221 inst
.instruction
|= (abcdebits
& 3) << 5;
14222 inst
.instruction
|= (abcdebits
>> 2) << 21;
14226 case NS_RRD
: /* case 7 (fmrrd). */
14227 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14230 inst
.instruction
= 0xc500b10;
14231 do_vfp_cond_or_thumb ();
14232 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14233 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14234 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14235 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14238 case NS_FF
: /* case 8 (fcpys). */
14239 do_vfp_nsyn_opcode ("fcpys");
14242 case NS_FI
: /* case 10 (fconsts). */
14243 ldconst
= "fconsts";
14245 if (is_quarter_float (inst
.operands
[1].imm
))
14247 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14248 do_vfp_nsyn_opcode (ldconst
);
14251 first_error (_("immediate out of range"));
14254 case NS_RF
: /* case 12 (fmrs). */
14255 do_vfp_nsyn_opcode ("fmrs");
14258 case NS_FR
: /* case 13 (fmsr). */
14259 do_vfp_nsyn_opcode ("fmsr");
14262 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14263 (one of which is a list), but we have parsed four. Do some fiddling to
14264 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14266 case NS_RRFF
: /* case 14 (fmrrs). */
14267 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14268 _("VFP registers must be adjacent"));
14269 inst
.operands
[2].imm
= 2;
14270 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14271 do_vfp_nsyn_opcode ("fmrrs");
14274 case NS_FFRR
: /* case 15 (fmsrr). */
14275 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14276 _("VFP registers must be adjacent"));
14277 inst
.operands
[1] = inst
.operands
[2];
14278 inst
.operands
[2] = inst
.operands
[3];
14279 inst
.operands
[0].imm
= 2;
14280 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14281 do_vfp_nsyn_opcode ("fmsrr");
14290 do_neon_rshift_round_imm (void)
14292 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14293 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14294 int imm
= inst
.operands
[2].imm
;
14296 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14299 inst
.operands
[2].present
= 0;
14304 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14305 _("immediate out of range for shift"));
14306 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14311 do_neon_movl (void)
14313 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14314 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14315 unsigned sizebits
= et
.size
>> 3;
14316 inst
.instruction
|= sizebits
<< 19;
14317 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14323 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14324 struct neon_type_el et
= neon_check_type (2, rs
,
14325 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14326 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
14327 neon_two_same (neon_quad (rs
), 1, et
.size
);
14331 do_neon_zip_uzp (void)
14333 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14334 struct neon_type_el et
= neon_check_type (2, rs
,
14335 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14336 if (rs
== NS_DD
&& et
.size
== 32)
14338 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14339 inst
.instruction
= N_MNEM_vtrn
;
14343 neon_two_same (neon_quad (rs
), 1, et
.size
);
14347 do_neon_sat_abs_neg (void)
14349 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14350 struct neon_type_el et
= neon_check_type (2, rs
,
14351 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14352 neon_two_same (neon_quad (rs
), 1, et
.size
);
14356 do_neon_pair_long (void)
14358 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14359 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14360 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14361 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14362 neon_two_same (neon_quad (rs
), 1, et
.size
);
14366 do_neon_recip_est (void)
14368 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14369 struct neon_type_el et
= neon_check_type (2, rs
,
14370 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14371 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14372 neon_two_same (neon_quad (rs
), 1, et
.size
);
14378 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14379 struct neon_type_el et
= neon_check_type (2, rs
,
14380 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14381 neon_two_same (neon_quad (rs
), 1, et
.size
);
14387 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14388 struct neon_type_el et
= neon_check_type (2, rs
,
14389 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14390 neon_two_same (neon_quad (rs
), 1, et
.size
);
14396 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14397 struct neon_type_el et
= neon_check_type (2, rs
,
14398 N_EQK
| N_INT
, N_8
| N_KEY
);
14399 neon_two_same (neon_quad (rs
), 1, et
.size
);
14405 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14406 neon_two_same (neon_quad (rs
), 1, -1);
14410 do_neon_tbl_tbx (void)
14412 unsigned listlenbits
;
14413 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14415 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14417 first_error (_("bad list length for table lookup"));
14421 listlenbits
= inst
.operands
[1].imm
- 1;
14422 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14423 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14424 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14425 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14426 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14427 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14428 inst
.instruction
|= listlenbits
<< 8;
14430 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14434 do_neon_ldm_stm (void)
14436 /* P, U and L bits are part of bitmask. */
14437 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14438 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14440 if (inst
.operands
[1].issingle
)
14442 do_vfp_nsyn_ldm_stm (is_dbmode
);
14446 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14447 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14449 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14450 _("register list must contain at least 1 and at most 16 "
14453 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14454 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14455 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14456 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14458 inst
.instruction
|= offsetbits
;
14460 do_vfp_cond_or_thumb ();
14464 do_neon_ldr_str (void)
14466 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14468 if (inst
.operands
[0].issingle
)
14471 do_vfp_nsyn_opcode ("flds");
14473 do_vfp_nsyn_opcode ("fsts");
14478 do_vfp_nsyn_opcode ("fldd");
14480 do_vfp_nsyn_opcode ("fstd");
14484 /* "interleave" version also handles non-interleaving register VLD1/VST1
14488 do_neon_ld_st_interleave (void)
14490 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14491 N_8
| N_16
| N_32
| N_64
);
14492 unsigned alignbits
= 0;
14494 /* The bits in this table go:
14495 0: register stride of one (0) or two (1)
14496 1,2: register list length, minus one (1, 2, 3, 4).
14497 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14498 We use -1 for invalid entries. */
14499 const int typetable
[] =
14501 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14502 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14503 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14504 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14508 if (et
.type
== NT_invtype
)
14511 if (inst
.operands
[1].immisalign
)
14512 switch (inst
.operands
[1].imm
>> 8)
14514 case 64: alignbits
= 1; break;
14516 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14517 goto bad_alignment
;
14521 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14522 goto bad_alignment
;
14527 first_error (_("bad alignment"));
14531 inst
.instruction
|= alignbits
<< 4;
14532 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14534 /* Bits [4:6] of the immediate in a list specifier encode register stride
14535 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14536 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14537 up the right value for "type" in a table based on this value and the given
14538 list style, then stick it back. */
14539 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14540 | (((inst
.instruction
>> 8) & 3) << 3);
14542 typebits
= typetable
[idx
];
14544 constraint (typebits
== -1, _("bad list type for instruction"));
14546 inst
.instruction
&= ~0xf00;
14547 inst
.instruction
|= typebits
<< 8;
14550 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14551 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14552 otherwise. The variable arguments are a list of pairs of legal (size, align)
14553 values, terminated with -1. */
14556 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14559 int result
= FAIL
, thissize
, thisalign
;
14561 if (!inst
.operands
[1].immisalign
)
14567 va_start (ap
, do_align
);
14571 thissize
= va_arg (ap
, int);
14572 if (thissize
== -1)
14574 thisalign
= va_arg (ap
, int);
14576 if (size
== thissize
&& align
== thisalign
)
14579 while (result
!= SUCCESS
);
14583 if (result
== SUCCESS
)
14586 first_error (_("unsupported alignment for instruction"));
14592 do_neon_ld_st_lane (void)
14594 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14595 int align_good
, do_align
= 0;
14596 int logsize
= neon_logbits (et
.size
);
14597 int align
= inst
.operands
[1].imm
>> 8;
14598 int n
= (inst
.instruction
>> 8) & 3;
14599 int max_el
= 64 / et
.size
;
14601 if (et
.type
== NT_invtype
)
14604 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14605 _("bad list length"));
14606 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14607 _("scalar index out of range"));
14608 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14610 _("stride of 2 unavailable when element size is 8"));
14614 case 0: /* VLD1 / VST1. */
14615 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14617 if (align_good
== FAIL
)
14621 unsigned alignbits
= 0;
14624 case 16: alignbits
= 0x1; break;
14625 case 32: alignbits
= 0x3; break;
14628 inst
.instruction
|= alignbits
<< 4;
14632 case 1: /* VLD2 / VST2. */
14633 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14635 if (align_good
== FAIL
)
14638 inst
.instruction
|= 1 << 4;
14641 case 2: /* VLD3 / VST3. */
14642 constraint (inst
.operands
[1].immisalign
,
14643 _("can't use alignment with this instruction"));
14646 case 3: /* VLD4 / VST4. */
14647 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14648 16, 64, 32, 64, 32, 128, -1);
14649 if (align_good
== FAIL
)
14653 unsigned alignbits
= 0;
14656 case 8: alignbits
= 0x1; break;
14657 case 16: alignbits
= 0x1; break;
14658 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14661 inst
.instruction
|= alignbits
<< 4;
14668 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14669 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14670 inst
.instruction
|= 1 << (4 + logsize
);
14672 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14673 inst
.instruction
|= logsize
<< 10;
14676 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14679 do_neon_ld_dup (void)
14681 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14682 int align_good
, do_align
= 0;
14684 if (et
.type
== NT_invtype
)
14687 switch ((inst
.instruction
>> 8) & 3)
14689 case 0: /* VLD1. */
14690 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14691 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14692 &do_align
, 16, 16, 32, 32, -1);
14693 if (align_good
== FAIL
)
14695 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14698 case 2: inst
.instruction
|= 1 << 5; break;
14699 default: first_error (_("bad list length")); return;
14701 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14704 case 1: /* VLD2. */
14705 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14706 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14707 if (align_good
== FAIL
)
14709 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14710 _("bad list length"));
14711 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14712 inst
.instruction
|= 1 << 5;
14713 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14716 case 2: /* VLD3. */
14717 constraint (inst
.operands
[1].immisalign
,
14718 _("can't use alignment with this instruction"));
14719 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14720 _("bad list length"));
14721 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14722 inst
.instruction
|= 1 << 5;
14723 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14726 case 3: /* VLD4. */
14728 int align
= inst
.operands
[1].imm
>> 8;
14729 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14730 16, 64, 32, 64, 32, 128, -1);
14731 if (align_good
== FAIL
)
14733 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14734 _("bad list length"));
14735 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14736 inst
.instruction
|= 1 << 5;
14737 if (et
.size
== 32 && align
== 128)
14738 inst
.instruction
|= 0x3 << 6;
14740 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14747 inst
.instruction
|= do_align
<< 4;
14750 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14751 apart from bits [11:4]. */
14754 do_neon_ldx_stx (void)
14756 switch (NEON_LANE (inst
.operands
[0].imm
))
14758 case NEON_INTERLEAVE_LANES
:
14759 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
14760 do_neon_ld_st_interleave ();
14763 case NEON_ALL_LANES
:
14764 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
14769 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
14770 do_neon_ld_st_lane ();
14773 /* L bit comes from bit mask. */
14774 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14775 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14776 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14778 if (inst
.operands
[1].postind
)
14780 int postreg
= inst
.operands
[1].imm
& 0xf;
14781 constraint (!inst
.operands
[1].immisreg
,
14782 _("post-index must be a register"));
14783 constraint (postreg
== 0xd || postreg
== 0xf,
14784 _("bad register for post-index"));
14785 inst
.instruction
|= postreg
;
14787 else if (inst
.operands
[1].writeback
)
14789 inst
.instruction
|= 0xd;
14792 inst
.instruction
|= 0xf;
14795 inst
.instruction
|= 0xf9000000;
14797 inst
.instruction
|= 0xf4000000;
14800 /* Overall per-instruction processing. */
14802 /* We need to be able to fix up arbitrary expressions in some statements.
14803 This is so that we can handle symbols that are an arbitrary distance from
14804 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
14805 which returns part of an address in a form which will be valid for
14806 a data instruction. We do this by pushing the expression into a symbol
14807 in the expr_section, and creating a fix for that. */
14810 fix_new_arm (fragS
* frag
,
14825 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
14826 (enum bfd_reloc_code_real
) reloc
);
14830 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
14831 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
14835 /* Mark whether the fix is to a THUMB instruction, or an ARM
14837 new_fix
->tc_fix_data
= thumb_mode
;
14840 /* Create a frg for an instruction requiring relaxation. */
14842 output_relax_insn (void)
14848 /* The size of the instruction is unknown, so tie the debug info to the
14849 start of the instruction. */
14850 dwarf2_emit_insn (0);
14852 switch (inst
.reloc
.exp
.X_op
)
14855 sym
= inst
.reloc
.exp
.X_add_symbol
;
14856 offset
= inst
.reloc
.exp
.X_add_number
;
14860 offset
= inst
.reloc
.exp
.X_add_number
;
14863 sym
= make_expr_symbol (&inst
.reloc
.exp
);
14867 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
14868 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
14869 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
14872 /* Write a 32-bit thumb instruction to buf. */
14874 put_thumb32_insn (char * buf
, unsigned long insn
)
14876 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
14877 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
14881 output_inst (const char * str
)
14887 as_bad ("%s -- `%s'", inst
.error
, str
);
14892 output_relax_insn ();
14895 if (inst
.size
== 0)
14898 to
= frag_more (inst
.size
);
14899 /* PR 9814: Record the thumb mode into the current frag so that we know
14900 what type of NOP padding to use, if necessary. We override any previous
14901 setting so that if the mode has changed then the NOPS that we use will
14902 match the encoding of the last instruction in the frag. */
14903 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
14905 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
14907 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
14908 put_thumb32_insn (to
, inst
.instruction
);
14910 else if (inst
.size
> INSN_SIZE
)
14912 gas_assert (inst
.size
== (2 * INSN_SIZE
));
14913 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
14914 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
14917 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
14919 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
14920 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
14921 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
14924 dwarf2_emit_insn (inst
.size
);
14928 output_it_inst (int cond
, int mask
, char * to
)
14930 unsigned long instruction
= 0xbf00;
14933 instruction
|= mask
;
14934 instruction
|= cond
<< 4;
14938 to
= frag_more (2);
14940 dwarf2_emit_insn (2);
14944 md_number_to_chars (to
, instruction
, 2);
14949 /* Tag values used in struct asm_opcode's tag field. */
14952 OT_unconditional
, /* Instruction cannot be conditionalized.
14953 The ARM condition field is still 0xE. */
14954 OT_unconditionalF
, /* Instruction cannot be conditionalized
14955 and carries 0xF in its ARM condition field. */
14956 OT_csuffix
, /* Instruction takes a conditional suffix. */
14957 OT_csuffixF
, /* Some forms of the instruction take a conditional
14958 suffix, others place 0xF where the condition field
14960 OT_cinfix3
, /* Instruction takes a conditional infix,
14961 beginning at character index 3. (In
14962 unified mode, it becomes a suffix.) */
14963 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
14964 tsts, cmps, cmns, and teqs. */
14965 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
14966 character index 3, even in unified mode. Used for
14967 legacy instructions where suffix and infix forms
14968 may be ambiguous. */
14969 OT_csuf_or_in3
, /* Instruction takes either a conditional
14970 suffix or an infix at character index 3. */
14971 OT_odd_infix_unc
, /* This is the unconditional variant of an
14972 instruction that takes a conditional infix
14973 at an unusual position. In unified mode,
14974 this variant will accept a suffix. */
14975 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
14976 are the conditional variants of instructions that
14977 take conditional infixes in unusual positions.
14978 The infix appears at character index
14979 (tag - OT_odd_infix_0). These are not accepted
14980 in unified mode. */
14983 /* Subroutine of md_assemble, responsible for looking up the primary
14984 opcode from the mnemonic the user wrote. STR points to the
14985 beginning of the mnemonic.
14987 This is not simply a hash table lookup, because of conditional
14988 variants. Most instructions have conditional variants, which are
14989 expressed with a _conditional affix_ to the mnemonic. If we were
14990 to encode each conditional variant as a literal string in the opcode
14991 table, it would have approximately 20,000 entries.
14993 Most mnemonics take this affix as a suffix, and in unified syntax,
14994 'most' is upgraded to 'all'. However, in the divided syntax, some
14995 instructions take the affix as an infix, notably the s-variants of
14996 the arithmetic instructions. Of those instructions, all but six
14997 have the infix appear after the third character of the mnemonic.
14999 Accordingly, the algorithm for looking up primary opcodes given
15002 1. Look up the identifier in the opcode table.
15003 If we find a match, go to step U.
15005 2. Look up the last two characters of the identifier in the
15006 conditions table. If we find a match, look up the first N-2
15007 characters of the identifier in the opcode table. If we
15008 find a match, go to step CE.
15010 3. Look up the fourth and fifth characters of the identifier in
15011 the conditions table. If we find a match, extract those
15012 characters from the identifier, and look up the remaining
15013 characters in the opcode table. If we find a match, go
15018 U. Examine the tag field of the opcode structure, in case this is
15019 one of the six instructions with its conditional infix in an
15020 unusual place. If it is, the tag tells us where to find the
15021 infix; look it up in the conditions table and set inst.cond
15022 accordingly. Otherwise, this is an unconditional instruction.
15023 Again set inst.cond accordingly. Return the opcode structure.
15025 CE. Examine the tag field to make sure this is an instruction that
15026 should receive a conditional suffix. If it is not, fail.
15027 Otherwise, set inst.cond from the suffix we already looked up,
15028 and return the opcode structure.
15030 CM. Examine the tag field to make sure this is an instruction that
15031 should receive a conditional infix after the third character.
15032 If it is not, fail. Otherwise, undo the edits to the current
15033 line of input and proceed as for case CE. */
15035 static const struct asm_opcode
*
15036 opcode_lookup (char **str
)
15040 const struct asm_opcode
*opcode
;
15041 const struct asm_cond
*cond
;
15044 /* Scan up to the end of the mnemonic, which must end in white space,
15045 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15046 for (base
= end
= *str
; *end
!= '\0'; end
++)
15047 if (*end
== ' ' || *end
== '.')
15053 /* Handle a possible width suffix and/or Neon type suffix. */
15058 /* The .w and .n suffixes are only valid if the unified syntax is in
15060 if (unified_syntax
&& end
[1] == 'w')
15062 else if (unified_syntax
&& end
[1] == 'n')
15067 inst
.vectype
.elems
= 0;
15069 *str
= end
+ offset
;
15071 if (end
[offset
] == '.')
15073 /* See if we have a Neon type suffix (possible in either unified or
15074 non-unified ARM syntax mode). */
15075 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15078 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15084 /* Look for unaffixed or special-case affixed mnemonic. */
15085 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15090 if (opcode
->tag
< OT_odd_infix_0
)
15092 inst
.cond
= COND_ALWAYS
;
15096 if (warn_on_deprecated
&& unified_syntax
)
15097 as_warn (_("conditional infixes are deprecated in unified syntax"));
15098 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15099 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15102 inst
.cond
= cond
->value
;
15106 /* Cannot have a conditional suffix on a mnemonic of less than two
15108 if (end
- base
< 3)
15111 /* Look for suffixed mnemonic. */
15113 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15114 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15116 if (opcode
&& cond
)
15119 switch (opcode
->tag
)
15121 case OT_cinfix3_legacy
:
15122 /* Ignore conditional suffixes matched on infix only mnemonics. */
15126 case OT_cinfix3_deprecated
:
15127 case OT_odd_infix_unc
:
15128 if (!unified_syntax
)
15130 /* else fall through */
15134 case OT_csuf_or_in3
:
15135 inst
.cond
= cond
->value
;
15138 case OT_unconditional
:
15139 case OT_unconditionalF
:
15141 inst
.cond
= cond
->value
;
15144 /* Delayed diagnostic. */
15145 inst
.error
= BAD_COND
;
15146 inst
.cond
= COND_ALWAYS
;
15155 /* Cannot have a usual-position infix on a mnemonic of less than
15156 six characters (five would be a suffix). */
15157 if (end
- base
< 6)
15160 /* Look for infixed mnemonic in the usual position. */
15162 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15166 memcpy (save
, affix
, 2);
15167 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15168 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15170 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15171 memcpy (affix
, save
, 2);
15174 && (opcode
->tag
== OT_cinfix3
15175 || opcode
->tag
== OT_cinfix3_deprecated
15176 || opcode
->tag
== OT_csuf_or_in3
15177 || opcode
->tag
== OT_cinfix3_legacy
))
15180 if (warn_on_deprecated
&& unified_syntax
15181 && (opcode
->tag
== OT_cinfix3
15182 || opcode
->tag
== OT_cinfix3_deprecated
))
15183 as_warn (_("conditional infixes are deprecated in unified syntax"));
15185 inst
.cond
= cond
->value
;
15192 /* This function generates an initial IT instruction, leaving its block
15193 virtually open for the new instructions. Eventually,
15194 the mask will be updated by now_it_add_mask () each time
15195 a new instruction needs to be included in the IT block.
15196 Finally, the block is closed with close_automatic_it_block ().
15197 The block closure can be requested either from md_assemble (),
15198 a tencode (), or due to a label hook. */
15201 new_automatic_it_block (int cond
)
15203 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15204 now_it
.mask
= 0x18;
15206 now_it
.block_length
= 1;
15207 mapping_state (MAP_THUMB
);
15208 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15211 /* Close an automatic IT block.
15212 See comments in new_automatic_it_block (). */
15215 close_automatic_it_block (void)
15217 now_it
.mask
= 0x10;
15218 now_it
.block_length
= 0;
15221 /* Update the mask of the current automatically-generated IT
15222 instruction. See comments in new_automatic_it_block (). */
15225 now_it_add_mask (int cond
)
15227 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15228 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15229 | ((bitvalue) << (nbit)))
15230 const int resulting_bit
= (cond
& 1);
15232 now_it
.mask
&= 0xf;
15233 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15235 (5 - now_it
.block_length
));
15236 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15238 ((5 - now_it
.block_length
) - 1) );
15239 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15242 #undef SET_BIT_VALUE
15245 /* The IT blocks handling machinery is accessed through the these functions:
15246 it_fsm_pre_encode () from md_assemble ()
15247 set_it_insn_type () optional, from the tencode functions
15248 set_it_insn_type_last () ditto
15249 in_it_block () ditto
15250 it_fsm_post_encode () from md_assemble ()
15251 force_automatic_it_block_close () from label habdling functions
15254 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15255 initializing the IT insn type with a generic initial value depending
15256 on the inst.condition.
15257 2) During the tencode function, two things may happen:
15258 a) The tencode function overrides the IT insn type by
15259 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15260 b) The tencode function queries the IT block state by
15261 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15263 Both set_it_insn_type and in_it_block run the internal FSM state
15264 handling function (handle_it_state), because: a) setting the IT insn
15265 type may incur in an invalid state (exiting the function),
15266 and b) querying the state requires the FSM to be updated.
15267 Specifically we want to avoid creating an IT block for conditional
15268 branches, so it_fsm_pre_encode is actually a guess and we can't
15269 determine whether an IT block is required until the tencode () routine
15270 has decided what type of instruction this actually it.
15271 Because of this, if set_it_insn_type and in_it_block have to be used,
15272 set_it_insn_type has to be called first.
15274 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15275 determines the insn IT type depending on the inst.cond code.
15276 When a tencode () routine encodes an instruction that can be
15277 either outside an IT block, or, in the case of being inside, has to be
15278 the last one, set_it_insn_type_last () will determine the proper
15279 IT instruction type based on the inst.cond code. Otherwise,
15280 set_it_insn_type can be called for overriding that logic or
15281 for covering other cases.
15283 Calling handle_it_state () may not transition the IT block state to
15284 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15285 still queried. Instead, if the FSM determines that the state should
15286 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15287 after the tencode () function: that's what it_fsm_post_encode () does.
15289 Since in_it_block () calls the state handling function to get an
15290 updated state, an error may occur (due to invalid insns combination).
15291 In that case, inst.error is set.
15292 Therefore, inst.error has to be checked after the execution of
15293 the tencode () routine.
15295 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15296 any pending state change (if any) that didn't take place in
15297 handle_it_state () as explained above. */
15300 it_fsm_pre_encode (void)
15302 if (inst
.cond
!= COND_ALWAYS
)
15303 inst
.it_insn_type
= INSIDE_IT_INSN
;
15305 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15307 now_it
.state_handled
= 0;
15310 /* IT state FSM handling function. */
15313 handle_it_state (void)
15315 now_it
.state_handled
= 1;
15317 switch (now_it
.state
)
15319 case OUTSIDE_IT_BLOCK
:
15320 switch (inst
.it_insn_type
)
15322 case OUTSIDE_IT_INSN
:
15325 case INSIDE_IT_INSN
:
15326 case INSIDE_IT_LAST_INSN
:
15327 if (thumb_mode
== 0)
15330 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15331 as_tsktsk (_("Warning: conditional outside an IT block"\
15336 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15337 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15339 /* Automatically generate the IT instruction. */
15340 new_automatic_it_block (inst
.cond
);
15341 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15342 close_automatic_it_block ();
15346 inst
.error
= BAD_OUT_IT
;
15352 case IF_INSIDE_IT_LAST_INSN
:
15353 case NEUTRAL_IT_INSN
:
15357 now_it
.state
= MANUAL_IT_BLOCK
;
15358 now_it
.block_length
= 0;
15363 case AUTOMATIC_IT_BLOCK
:
15364 /* Three things may happen now:
15365 a) We should increment current it block size;
15366 b) We should close current it block (closing insn or 4 insns);
15367 c) We should close current it block and start a new one (due
15368 to incompatible conditions or
15369 4 insns-length block reached). */
15371 switch (inst
.it_insn_type
)
15373 case OUTSIDE_IT_INSN
:
15374 /* The closure of the block shall happen immediatelly,
15375 so any in_it_block () call reports the block as closed. */
15376 force_automatic_it_block_close ();
15379 case INSIDE_IT_INSN
:
15380 case INSIDE_IT_LAST_INSN
:
15381 case IF_INSIDE_IT_LAST_INSN
:
15382 now_it
.block_length
++;
15384 if (now_it
.block_length
> 4
15385 || !now_it_compatible (inst
.cond
))
15387 force_automatic_it_block_close ();
15388 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15389 new_automatic_it_block (inst
.cond
);
15393 now_it_add_mask (inst
.cond
);
15396 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15397 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15398 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15399 close_automatic_it_block ();
15402 case NEUTRAL_IT_INSN
:
15403 now_it
.block_length
++;
15405 if (now_it
.block_length
> 4)
15406 force_automatic_it_block_close ();
15408 now_it_add_mask (now_it
.cc
& 1);
15412 close_automatic_it_block ();
15413 now_it
.state
= MANUAL_IT_BLOCK
;
15418 case MANUAL_IT_BLOCK
:
15420 /* Check conditional suffixes. */
15421 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15424 now_it
.mask
&= 0x1f;
15425 is_last
= (now_it
.mask
== 0x10);
15427 switch (inst
.it_insn_type
)
15429 case OUTSIDE_IT_INSN
:
15430 inst
.error
= BAD_NOT_IT
;
15433 case INSIDE_IT_INSN
:
15434 if (cond
!= inst
.cond
)
15436 inst
.error
= BAD_IT_COND
;
15441 case INSIDE_IT_LAST_INSN
:
15442 case IF_INSIDE_IT_LAST_INSN
:
15443 if (cond
!= inst
.cond
)
15445 inst
.error
= BAD_IT_COND
;
15450 inst
.error
= BAD_BRANCH
;
15455 case NEUTRAL_IT_INSN
:
15456 /* The BKPT instruction is unconditional even in an IT block. */
15460 inst
.error
= BAD_IT_IT
;
15471 it_fsm_post_encode (void)
15475 if (!now_it
.state_handled
)
15476 handle_it_state ();
15478 is_last
= (now_it
.mask
== 0x10);
15481 now_it
.state
= OUTSIDE_IT_BLOCK
;
15487 force_automatic_it_block_close (void)
15489 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15491 close_automatic_it_block ();
15492 now_it
.state
= OUTSIDE_IT_BLOCK
;
15500 if (!now_it
.state_handled
)
15501 handle_it_state ();
15503 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15507 md_assemble (char *str
)
15510 const struct asm_opcode
* opcode
;
15512 /* Align the previous label if needed. */
15513 if (last_label_seen
!= NULL
)
15515 symbol_set_frag (last_label_seen
, frag_now
);
15516 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15517 S_SET_SEGMENT (last_label_seen
, now_seg
);
15520 memset (&inst
, '\0', sizeof (inst
));
15521 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15523 opcode
= opcode_lookup (&p
);
15526 /* It wasn't an instruction, but it might be a register alias of
15527 the form alias .req reg, or a Neon .dn/.qn directive. */
15528 if (! create_register_alias (str
, p
)
15529 && ! create_neon_reg_alias (str
, p
))
15530 as_bad (_("bad instruction `%s'"), str
);
15535 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15536 as_warn (_("s suffix on comparison instruction is deprecated"));
15538 /* The value which unconditional instructions should have in place of the
15539 condition field. */
15540 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15544 arm_feature_set variant
;
15546 variant
= cpu_variant
;
15547 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15548 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15549 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15550 /* Check that this instruction is supported for this CPU. */
15551 if (!opcode
->tvariant
15552 || (thumb_mode
== 1
15553 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15555 as_bad (_("selected processor does not support `%s'"), str
);
15558 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15559 && opcode
->tencode
!= do_t_branch
)
15561 as_bad (_("Thumb does not support conditional execution"));
15565 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15567 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15568 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15569 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15571 /* Two things are addressed here.
15572 1) Implicit require narrow instructions on Thumb-1.
15573 This avoids relaxation accidentally introducing Thumb-2
15575 2) Reject wide instructions in non Thumb-2 cores. */
15576 if (inst
.size_req
== 0)
15578 else if (inst
.size_req
== 4)
15580 as_bad (_("selected processor does not support `%s'"), str
);
15586 inst
.instruction
= opcode
->tvalue
;
15588 if (!parse_operands (p
, opcode
->operands
))
15590 /* Prepare the it_insn_type for those encodings that don't set
15592 it_fsm_pre_encode ();
15594 opcode
->tencode ();
15596 it_fsm_post_encode ();
15599 if (!(inst
.error
|| inst
.relax
))
15601 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15602 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15603 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15605 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15610 /* Something has gone badly wrong if we try to relax a fixed size
15612 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15614 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15615 *opcode
->tvariant
);
15616 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15617 set those bits when Thumb-2 32-bit instructions are seen. ie.
15618 anything other than bl/blx and v6-M instructions.
15619 This is overly pessimistic for relaxable instructions. */
15620 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15622 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15623 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15624 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15629 mapping_state (MAP_THUMB
);
15632 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15636 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15637 is_bx
= (opcode
->aencode
== do_bx
);
15639 /* Check that this instruction is supported for this CPU. */
15640 if (!(is_bx
&& fix_v4bx
)
15641 && !(opcode
->avariant
&&
15642 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15644 as_bad (_("selected processor does not support `%s'"), str
);
15649 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15653 inst
.instruction
= opcode
->avalue
;
15654 if (opcode
->tag
== OT_unconditionalF
)
15655 inst
.instruction
|= 0xF << 28;
15657 inst
.instruction
|= inst
.cond
<< 28;
15658 inst
.size
= INSN_SIZE
;
15659 if (!parse_operands (p
, opcode
->operands
))
15661 it_fsm_pre_encode ();
15662 opcode
->aencode ();
15663 it_fsm_post_encode ();
15665 /* Arm mode bx is marked as both v4T and v5 because it's still required
15666 on a hypothetical non-thumb v5 core. */
15668 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15670 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15671 *opcode
->avariant
);
15674 mapping_state (MAP_ARM
);
15679 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15687 check_it_blocks_finished (void)
15692 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15693 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15694 == MANUAL_IT_BLOCK
)
15696 as_warn (_("section '%s' finished with an open IT block."),
15700 if (now_it
.state
== MANUAL_IT_BLOCK
)
15701 as_warn (_("file finished with an open IT block."));
15705 /* Various frobbings of labels and their addresses. */
15708 arm_start_line_hook (void)
15710 last_label_seen
= NULL
;
15714 arm_frob_label (symbolS
* sym
)
15716 last_label_seen
= sym
;
15718 ARM_SET_THUMB (sym
, thumb_mode
);
15720 #if defined OBJ_COFF || defined OBJ_ELF
15721 ARM_SET_INTERWORK (sym
, support_interwork
);
15724 force_automatic_it_block_close ();
15726 /* Note - do not allow local symbols (.Lxxx) to be labelled
15727 as Thumb functions. This is because these labels, whilst
15728 they exist inside Thumb code, are not the entry points for
15729 possible ARM->Thumb calls. Also, these labels can be used
15730 as part of a computed goto or switch statement. eg gcc
15731 can generate code that looks like this:
15733 ldr r2, [pc, .Laaa]
15743 The first instruction loads the address of the jump table.
15744 The second instruction converts a table index into a byte offset.
15745 The third instruction gets the jump address out of the table.
15746 The fourth instruction performs the jump.
15748 If the address stored at .Laaa is that of a symbol which has the
15749 Thumb_Func bit set, then the linker will arrange for this address
15750 to have the bottom bit set, which in turn would mean that the
15751 address computation performed by the third instruction would end
15752 up with the bottom bit set. Since the ARM is capable of unaligned
15753 word loads, the instruction would then load the incorrect address
15754 out of the jump table, and chaos would ensue. */
15755 if (label_is_thumb_function_name
15756 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
15757 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
15759 /* When the address of a Thumb function is taken the bottom
15760 bit of that address should be set. This will allow
15761 interworking between Arm and Thumb functions to work
15764 THUMB_SET_FUNC (sym
, 1);
15766 label_is_thumb_function_name
= FALSE
;
15769 dwarf2_emit_label (sym
);
15773 arm_data_in_code (void)
15775 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
15777 *input_line_pointer
= '/';
15778 input_line_pointer
+= 5;
15779 *input_line_pointer
= 0;
15787 arm_canonicalize_symbol_name (char * name
)
15791 if (thumb_mode
&& (len
= strlen (name
)) > 5
15792 && streq (name
+ len
- 5, "/data"))
15793 *(name
+ len
- 5) = 0;
15798 /* Table of all register names defined by default. The user can
15799 define additional names with .req. Note that all register names
15800 should appear in both upper and lowercase variants. Some registers
15801 also have mixed-case names. */
15803 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
15804 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
15805 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
15806 #define REGSET(p,t) \
15807 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
15808 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
15809 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
15810 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
15811 #define REGSETH(p,t) \
15812 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
15813 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
15814 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
15815 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
15816 #define REGSET2(p,t) \
15817 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
15818 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
15819 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
15820 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
15822 static const struct reg_entry reg_names
[] =
15824 /* ARM integer registers. */
15825 REGSET(r
, RN
), REGSET(R
, RN
),
15827 /* ATPCS synonyms. */
15828 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
15829 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
15830 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
15832 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
15833 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
15834 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
15836 /* Well-known aliases. */
15837 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
15838 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
15840 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
15841 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
15843 /* Coprocessor numbers. */
15844 REGSET(p
, CP
), REGSET(P
, CP
),
15846 /* Coprocessor register numbers. The "cr" variants are for backward
15848 REGSET(c
, CN
), REGSET(C
, CN
),
15849 REGSET(cr
, CN
), REGSET(CR
, CN
),
15851 /* FPA registers. */
15852 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
15853 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
15855 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
15856 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
15858 /* VFP SP registers. */
15859 REGSET(s
,VFS
), REGSET(S
,VFS
),
15860 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
15862 /* VFP DP Registers. */
15863 REGSET(d
,VFD
), REGSET(D
,VFD
),
15864 /* Extra Neon DP registers. */
15865 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
15867 /* Neon QP registers. */
15868 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
15870 /* VFP control registers. */
15871 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
15872 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
15873 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
15874 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
15875 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
15876 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
15878 /* Maverick DSP coprocessor registers. */
15879 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
15880 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
15882 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
15883 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
15884 REGDEF(dspsc
,0,DSPSC
),
15886 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
15887 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
15888 REGDEF(DSPSC
,0,DSPSC
),
15890 /* iWMMXt data registers - p0, c0-15. */
15891 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
15893 /* iWMMXt control registers - p1, c0-3. */
15894 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
15895 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
15896 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
15897 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
15899 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
15900 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
15901 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
15902 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
15903 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
15905 /* XScale accumulator registers. */
15906 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
15912 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
15913 within psr_required_here. */
15914 static const struct asm_psr psrs
[] =
15916 /* Backward compatibility notation. Note that "all" is no longer
15917 truly all possible PSR bits. */
15918 {"all", PSR_c
| PSR_f
},
15922 /* Individual flags. */
15927 /* Combinations of flags. */
15928 {"fs", PSR_f
| PSR_s
},
15929 {"fx", PSR_f
| PSR_x
},
15930 {"fc", PSR_f
| PSR_c
},
15931 {"sf", PSR_s
| PSR_f
},
15932 {"sx", PSR_s
| PSR_x
},
15933 {"sc", PSR_s
| PSR_c
},
15934 {"xf", PSR_x
| PSR_f
},
15935 {"xs", PSR_x
| PSR_s
},
15936 {"xc", PSR_x
| PSR_c
},
15937 {"cf", PSR_c
| PSR_f
},
15938 {"cs", PSR_c
| PSR_s
},
15939 {"cx", PSR_c
| PSR_x
},
15940 {"fsx", PSR_f
| PSR_s
| PSR_x
},
15941 {"fsc", PSR_f
| PSR_s
| PSR_c
},
15942 {"fxs", PSR_f
| PSR_x
| PSR_s
},
15943 {"fxc", PSR_f
| PSR_x
| PSR_c
},
15944 {"fcs", PSR_f
| PSR_c
| PSR_s
},
15945 {"fcx", PSR_f
| PSR_c
| PSR_x
},
15946 {"sfx", PSR_s
| PSR_f
| PSR_x
},
15947 {"sfc", PSR_s
| PSR_f
| PSR_c
},
15948 {"sxf", PSR_s
| PSR_x
| PSR_f
},
15949 {"sxc", PSR_s
| PSR_x
| PSR_c
},
15950 {"scf", PSR_s
| PSR_c
| PSR_f
},
15951 {"scx", PSR_s
| PSR_c
| PSR_x
},
15952 {"xfs", PSR_x
| PSR_f
| PSR_s
},
15953 {"xfc", PSR_x
| PSR_f
| PSR_c
},
15954 {"xsf", PSR_x
| PSR_s
| PSR_f
},
15955 {"xsc", PSR_x
| PSR_s
| PSR_c
},
15956 {"xcf", PSR_x
| PSR_c
| PSR_f
},
15957 {"xcs", PSR_x
| PSR_c
| PSR_s
},
15958 {"cfs", PSR_c
| PSR_f
| PSR_s
},
15959 {"cfx", PSR_c
| PSR_f
| PSR_x
},
15960 {"csf", PSR_c
| PSR_s
| PSR_f
},
15961 {"csx", PSR_c
| PSR_s
| PSR_x
},
15962 {"cxf", PSR_c
| PSR_x
| PSR_f
},
15963 {"cxs", PSR_c
| PSR_x
| PSR_s
},
15964 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
15965 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
15966 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
15967 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
15968 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
15969 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
15970 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
15971 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
15972 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
15973 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
15974 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
15975 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
15976 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
15977 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
15978 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
15979 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
15980 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
15981 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
15982 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
15983 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
15984 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
15985 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
15986 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
15987 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
15990 /* Table of V7M psr names. */
15991 static const struct asm_psr v7m_psrs
[] =
15993 {"apsr", 0 }, {"APSR", 0 },
15994 {"iapsr", 1 }, {"IAPSR", 1 },
15995 {"eapsr", 2 }, {"EAPSR", 2 },
15996 {"psr", 3 }, {"PSR", 3 },
15997 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
15998 {"ipsr", 5 }, {"IPSR", 5 },
15999 {"epsr", 6 }, {"EPSR", 6 },
16000 {"iepsr", 7 }, {"IEPSR", 7 },
16001 {"msp", 8 }, {"MSP", 8 },
16002 {"psp", 9 }, {"PSP", 9 },
16003 {"primask", 16}, {"PRIMASK", 16},
16004 {"basepri", 17}, {"BASEPRI", 17},
16005 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16006 {"faultmask", 19}, {"FAULTMASK", 19},
16007 {"control", 20}, {"CONTROL", 20}
16010 /* Table of all shift-in-operand names. */
16011 static const struct asm_shift_name shift_names
[] =
16013 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16014 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16015 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16016 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16017 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16018 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16021 /* Table of all explicit relocation names. */
16023 static struct reloc_entry reloc_names
[] =
16025 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16026 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16027 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16028 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16029 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16030 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16031 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16032 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16033 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16034 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16035 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
16039 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16040 static const struct asm_cond conds
[] =
16044 {"cs", 0x2}, {"hs", 0x2},
16045 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16059 static struct asm_barrier_opt barrier_opt_names
[] =
16067 /* Table of ARM-format instructions. */
16069 /* Macros for gluing together operand strings. N.B. In all cases
16070 other than OPS0, the trailing OP_stop comes from default
16071 zero-initialization of the unspecified elements of the array. */
16072 #define OPS0() { OP_stop, }
16073 #define OPS1(a) { OP_##a, }
16074 #define OPS2(a,b) { OP_##a,OP_##b, }
16075 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16076 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16077 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16078 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16080 /* These macros abstract out the exact format of the mnemonic table and
16081 save some repeated characters. */
16083 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16084 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16085 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16086 THUMB_VARIANT, do_##ae, do_##te }
16088 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16089 a T_MNEM_xyz enumerator. */
16090 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16091 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16092 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16093 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16095 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16096 infix after the third character. */
16097 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16098 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16099 THUMB_VARIANT, do_##ae, do_##te }
16100 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16101 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16102 THUMB_VARIANT, do_##ae, do_##te }
16103 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16104 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16105 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16106 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16107 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16108 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16109 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16110 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16112 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16113 appear in the condition table. */
16114 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16115 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16116 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16118 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16119 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16120 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16121 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16122 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16123 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16124 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16125 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16126 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16127 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16128 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16129 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16130 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16131 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16132 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16133 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16134 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16135 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16136 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16137 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16139 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16140 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16141 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16142 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16144 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16145 field is still 0xE. Many of the Thumb variants can be executed
16146 conditionally, so this is checked separately. */
16147 #define TUE(mnem, op, top, nops, ops, ae, te) \
16148 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16149 THUMB_VARIANT, do_##ae, do_##te }
16151 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16152 condition code field. */
16153 #define TUF(mnem, op, top, nops, ops, ae, te) \
16154 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16155 THUMB_VARIANT, do_##ae, do_##te }
16157 /* ARM-only variants of all the above. */
16158 #define CE(mnem, op, nops, ops, ae) \
16159 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16161 #define C3(mnem, op, nops, ops, ae) \
16162 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16164 /* Legacy mnemonics that always have conditional infix after the third
16166 #define CL(mnem, op, nops, ops, ae) \
16167 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16168 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16170 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16171 #define cCE(mnem, op, nops, ops, ae) \
16172 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16174 /* Legacy coprocessor instructions where conditional infix and conditional
16175 suffix are ambiguous. For consistency this includes all FPA instructions,
16176 not just the potentially ambiguous ones. */
16177 #define cCL(mnem, op, nops, ops, ae) \
16178 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16179 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16181 /* Coprocessor, takes either a suffix or a position-3 infix
16182 (for an FPA corner case). */
16183 #define C3E(mnem, op, nops, ops, ae) \
16184 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16185 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16187 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16188 { m1 #m2 m3, OPS##nops ops, \
16189 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16190 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16192 #define CM(m1, m2, op, nops, ops, ae) \
16193 xCM_ (m1, , m2, op, nops, ops, ae), \
16194 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16195 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16196 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16197 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16198 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16199 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16200 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16201 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16202 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16203 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16204 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16205 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16206 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16207 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16208 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16209 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16210 xCM_ (m1, le, m2, op, nops, ops, ae), \
16211 xCM_ (m1, al, m2, op, nops, ops, ae)
16213 #define UE(mnem, op, nops, ops, ae) \
16214 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16216 #define UF(mnem, op, nops, ops, ae) \
16217 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16219 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16220 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16221 use the same encoding function for each. */
16222 #define NUF(mnem, op, nops, ops, enc) \
16223 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16224 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16226 /* Neon data processing, version which indirects through neon_enc_tab for
16227 the various overloaded versions of opcodes. */
16228 #define nUF(mnem, op, nops, ops, enc) \
16229 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16230 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16232 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16234 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16235 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16236 THUMB_VARIANT, do_##enc, do_##enc }
16238 #define NCE(mnem, op, nops, ops, enc) \
16239 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16241 #define NCEF(mnem, op, nops, ops, enc) \
16242 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16244 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16245 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16246 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16247 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16249 #define nCE(mnem, op, nops, ops, enc) \
16250 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16252 #define nCEF(mnem, op, nops, ops, enc) \
16253 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16257 /* Thumb-only, unconditional. */
16258 #define UT(mnem, op, nops, ops, te) TUE (mnem, 0, op, nops, ops, 0, te)
16260 static const struct asm_opcode insns
[] =
16262 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16263 #define THUMB_VARIANT &arm_ext_v4t
16264 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16265 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16266 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16267 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16268 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16269 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16270 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16271 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16272 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16273 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16274 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16275 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16276 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16277 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16278 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16279 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16281 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16282 for setting PSR flag bits. They are obsolete in V6 and do not
16283 have Thumb equivalents. */
16284 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16285 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16286 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16287 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16288 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16289 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16290 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16291 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16292 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16294 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16295 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16296 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16297 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16299 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16300 tC3("ldrb", 4500000, _ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16301 tCE("str", 4000000, _str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16302 tC3("strb", 4400000, _strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16304 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16305 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16306 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16307 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16308 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16309 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16311 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16312 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16313 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16314 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16317 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16318 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16319 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16321 /* Thumb-compatibility pseudo ops. */
16322 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16323 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16324 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16325 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16326 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16327 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16328 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16329 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16330 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16331 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16332 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16333 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16335 /* These may simplify to neg. */
16336 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16337 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16339 #undef THUMB_VARIANT
16340 #define THUMB_VARIANT & arm_ext_v6
16342 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16344 /* V1 instructions with no Thumb analogue prior to V6T2. */
16345 #undef THUMB_VARIANT
16346 #define THUMB_VARIANT & arm_ext_v6t2
16348 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16349 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16350 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16352 TC3("ldrt", 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16353 TC3("ldrbt", 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16354 TC3("strt", 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16355 TC3("strbt", 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16357 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16358 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16360 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16361 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16363 /* V1 instructions with no Thumb analogue at all. */
16364 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16365 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16367 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16368 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16369 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16370 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16371 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16372 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16373 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16374 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16377 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16378 #undef THUMB_VARIANT
16379 #define THUMB_VARIANT & arm_ext_v4t
16381 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16382 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16384 #undef THUMB_VARIANT
16385 #define THUMB_VARIANT & arm_ext_v6t2
16387 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16388 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16390 /* Generic coprocessor instructions. */
16391 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16392 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16393 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16394 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16395 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16396 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16397 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16400 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16402 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16403 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16406 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16407 #undef THUMB_VARIANT
16408 #define THUMB_VARIANT & arm_ext_msr
16410 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16411 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16414 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16415 #undef THUMB_VARIANT
16416 #define THUMB_VARIANT & arm_ext_v6t2
16418 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16419 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16420 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16421 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16422 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16423 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16424 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16425 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16428 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16429 #undef THUMB_VARIANT
16430 #define THUMB_VARIANT & arm_ext_v4t
16432 tC3("ldrh", 01000b0
, _ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16433 tC3("strh", 00000b0
, _strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16434 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16435 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16436 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16437 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16440 #define ARM_VARIANT & arm_ext_v4t_5
16442 /* ARM Architecture 4T. */
16443 /* Note: bx (and blx) are required on V5, even if the processor does
16444 not support Thumb. */
16445 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16448 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16449 #undef THUMB_VARIANT
16450 #define THUMB_VARIANT & arm_ext_v5t
16452 /* Note: blx has 2 variants; the .value coded here is for
16453 BLX(2). Only this variant has conditional execution. */
16454 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16455 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16457 #undef THUMB_VARIANT
16458 #define THUMB_VARIANT & arm_ext_v6t2
16460 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16461 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16462 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16463 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16464 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16465 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16466 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16467 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16470 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16472 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16473 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16474 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16475 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16477 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16478 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16480 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16481 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16482 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16483 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16485 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16486 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16487 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16488 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16490 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16491 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16493 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16494 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16495 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16496 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16499 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16501 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16502 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16503 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16505 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16506 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16509 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16511 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16514 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16515 #undef THUMB_VARIANT
16516 #define THUMB_VARIANT & arm_ext_v6
16518 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16519 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16520 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16521 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16522 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16523 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16524 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16525 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16526 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16527 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16529 #undef THUMB_VARIANT
16530 #define THUMB_VARIANT & arm_ext_v6t2
16532 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
16533 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
16534 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16535 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16537 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16538 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16540 /* ARM V6 not included in V7M (eg. integer SIMD). */
16541 #undef THUMB_VARIANT
16542 #define THUMB_VARIANT & arm_ext_v6_notm
16544 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16545 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16546 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16547 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16548 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16549 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16550 /* Old name for QASX. */
16551 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16552 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16553 /* Old name for QSAX. */
16554 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16555 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16556 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16557 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16558 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16559 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16560 /* Old name for SASX. */
16561 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16562 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16563 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16564 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16565 /* Old name for SHASX. */
16566 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16567 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16568 /* Old name for SHSAX. */
16569 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16570 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16571 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16572 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16573 /* Old name for SSAX. */
16574 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16575 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16576 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16577 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16578 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16579 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16580 /* Old name for UASX. */
16581 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16582 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16583 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16584 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16585 /* Old name for UHASX. */
16586 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16587 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16588 /* Old name for UHSAX. */
16589 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16590 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16591 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16592 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16593 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16594 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16595 /* Old name for UQASX. */
16596 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16597 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16598 /* Old name for UQSAX. */
16599 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16600 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16601 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16602 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16603 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16604 /* Old name for USAX. */
16605 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16606 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16607 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16608 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16609 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16610 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16611 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16612 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16613 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16614 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16615 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16616 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16617 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16618 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16619 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16620 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16621 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16622 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16623 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16624 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16625 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16626 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16627 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16628 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16629 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16630 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16631 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16632 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16633 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16634 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16635 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16636 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16637 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16638 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16639 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16640 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16641 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16642 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16643 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16644 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16645 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16646 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16647 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16648 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16649 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16650 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16653 #define ARM_VARIANT & arm_ext_v6k
16654 #undef THUMB_VARIANT
16655 #define THUMB_VARIANT & arm_ext_v6k
16657 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
16658 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
16659 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
16660 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
16662 #undef THUMB_VARIANT
16663 #define THUMB_VARIANT & arm_ext_v6_notm
16665 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
16666 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
16668 #undef THUMB_VARIANT
16669 #define THUMB_VARIANT & arm_ext_v6t2
16671 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16672 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16673 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16674 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16675 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
16678 #define ARM_VARIANT & arm_ext_v6z
16680 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
16683 #define ARM_VARIANT & arm_ext_v6t2
16685 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
16686 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
16687 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16688 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16690 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16691 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16692 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16693 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
16695 TC3("ldrht", 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16696 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16697 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16698 TC3("strht", 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16700 UT("cbnz", b900
, 2, (RR
, EXP
), t_cbz
),
16701 UT("cbz", b100
, 2, (RR
, EXP
), t_cbz
),
16703 /* ARM does not really have an IT instruction, so always allow it.
16704 The opcode is copied from Thumb in order to allow warnings in
16705 -mimplicit-it=[never | arm] modes. */
16707 #define ARM_VARIANT & arm_ext_v1
16709 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
16710 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
16711 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
16712 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
16713 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
16714 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
16715 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
16716 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
16717 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
16718 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
16719 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
16720 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
16721 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
16722 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
16723 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
16724 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
16725 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16726 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16728 /* Thumb2 only instructions. */
16730 #define ARM_VARIANT NULL
16732 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16733 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16734 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16735 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16736 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
16737 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
16739 /* Thumb-2 hardware division instructions (R and M profiles only). */
16740 #undef THUMB_VARIANT
16741 #define THUMB_VARIANT & arm_ext_div
16743 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16744 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16746 /* ARM V6M/V7 instructions. */
16748 #define ARM_VARIANT & arm_ext_barrier
16749 #undef THUMB_VARIANT
16750 #define THUMB_VARIANT & arm_ext_barrier
16752 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
16753 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
16754 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
16756 /* ARM V7 instructions. */
16758 #define ARM_VARIANT & arm_ext_v7
16759 #undef THUMB_VARIANT
16760 #define THUMB_VARIANT & arm_ext_v7
16762 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
16763 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
16766 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
16768 cCE("wfs", e200110
, 1, (RR
), rd
),
16769 cCE("rfs", e300110
, 1, (RR
), rd
),
16770 cCE("wfc", e400110
, 1, (RR
), rd
),
16771 cCE("rfc", e500110
, 1, (RR
), rd
),
16773 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16774 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16775 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16776 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16778 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16779 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16780 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16781 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16783 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
16784 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
16785 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
16786 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
16787 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
16788 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
16789 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
16790 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
16791 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
16792 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
16793 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
16794 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
16796 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
16797 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
16798 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
16799 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
16800 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
16801 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
16802 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
16803 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
16804 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
16805 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
16806 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
16807 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
16809 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
16810 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
16811 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
16812 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
16813 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
16814 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
16815 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
16816 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
16817 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
16818 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
16819 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
16820 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
16822 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
16823 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
16824 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
16825 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
16826 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
16827 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
16828 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
16829 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
16830 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
16831 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
16832 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
16833 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
16835 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
16836 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
16837 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
16838 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
16839 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
16840 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
16841 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
16842 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
16843 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
16844 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
16845 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
16846 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
16848 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
16849 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
16850 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
16851 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
16852 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
16853 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
16854 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
16855 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
16856 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
16857 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
16858 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
16859 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
16861 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
16862 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
16863 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
16864 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
16865 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
16866 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
16867 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
16868 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
16869 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
16870 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
16871 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
16872 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
16874 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
16875 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
16876 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
16877 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
16878 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
16879 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
16880 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
16881 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
16882 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
16883 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
16884 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
16885 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
16887 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
16888 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
16889 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
16890 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
16891 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
16892 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
16893 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
16894 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
16895 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
16896 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
16897 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
16898 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
16900 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
16901 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
16902 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
16903 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
16904 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
16905 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
16906 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
16907 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
16908 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
16909 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
16910 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
16911 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
16913 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
16914 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
16915 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
16916 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
16917 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
16918 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
16919 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
16920 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
16921 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
16922 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
16923 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
16924 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
16926 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
16927 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
16928 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
16929 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
16930 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
16931 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
16932 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
16933 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
16934 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
16935 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
16936 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
16937 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
16939 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
16940 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
16941 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
16942 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
16943 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
16944 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
16945 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
16946 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
16947 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
16948 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
16949 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
16950 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
16952 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
16953 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
16954 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
16955 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
16956 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
16957 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
16958 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
16959 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
16960 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
16961 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
16962 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
16963 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
16965 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
16966 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
16967 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
16968 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
16969 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
16970 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
16971 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
16972 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
16973 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
16974 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
16975 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
16976 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
16978 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
16979 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
16980 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
16981 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
16982 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
16983 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
16984 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
16985 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
16986 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
16987 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
16988 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
16989 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
16991 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16992 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16993 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16994 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16995 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16996 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16997 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16998 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16999 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17000 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17001 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17002 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17004 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17005 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17006 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17007 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17008 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17009 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17010 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17011 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17012 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17013 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17014 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17015 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17017 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17018 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17019 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17020 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17021 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17022 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17023 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17024 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17025 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17026 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17027 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17028 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17030 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17031 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17032 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17033 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17034 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17035 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17036 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17037 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17038 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17039 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17040 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17041 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17043 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17044 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17045 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17046 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17047 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17048 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17049 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17050 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17051 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17052 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17053 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17054 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17056 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17057 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17058 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17059 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17060 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17061 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17062 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17063 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17064 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17065 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17066 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17067 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17069 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17070 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17071 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17072 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17073 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17074 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17075 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17076 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17077 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17078 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17079 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17080 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17082 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17083 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17084 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17085 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17086 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17087 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17088 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17089 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17090 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17091 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17092 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17093 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17095 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17096 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17097 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17098 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17099 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17100 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17101 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17102 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17103 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17104 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17105 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17106 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17108 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17109 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17110 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17111 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17112 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17113 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17114 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17115 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17116 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17117 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17118 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17119 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17121 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17122 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17123 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17124 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17125 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17126 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17127 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17128 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17129 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17130 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17131 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17132 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17134 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17135 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17136 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17137 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17138 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17139 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17140 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17141 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17142 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17143 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17144 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17145 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17147 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17148 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17149 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17150 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17151 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17152 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17153 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17154 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17155 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17156 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17157 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17158 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17160 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17161 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17162 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17163 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17165 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17166 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17167 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17168 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17169 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17170 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17171 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17172 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17173 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17174 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17175 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17176 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17178 /* The implementation of the FIX instruction is broken on some
17179 assemblers, in that it accepts a precision specifier as well as a
17180 rounding specifier, despite the fact that this is meaningless.
17181 To be more compatible, we accept it as well, though of course it
17182 does not set any bits. */
17183 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17184 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17185 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17186 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17187 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17188 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17189 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17190 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17191 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17192 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17193 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17194 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17195 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17197 /* Instructions that were new with the real FPA, call them V2. */
17199 #define ARM_VARIANT & fpu_fpa_ext_v2
17201 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17202 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17203 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17204 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17205 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17206 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17209 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17211 /* Moves and type conversions. */
17212 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17213 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17214 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17215 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17216 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17217 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17218 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17219 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17220 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17221 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17222 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17223 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17224 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17225 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17227 /* Memory operations. */
17228 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17229 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17230 cCE("fldmias", c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17231 cCE("fldmfds", c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17232 cCE("fldmdbs", d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17233 cCE("fldmeas", d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17234 cCE("fldmiax", c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17235 cCE("fldmfdx", c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17236 cCE("fldmdbx", d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17237 cCE("fldmeax", d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17238 cCE("fstmias", c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17239 cCE("fstmeas", c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17240 cCE("fstmdbs", d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17241 cCE("fstmfds", d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17242 cCE("fstmiax", c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17243 cCE("fstmeax", c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17244 cCE("fstmdbx", d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17245 cCE("fstmfdx", d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17247 /* Monadic operations. */
17248 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17249 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17250 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17252 /* Dyadic operations. */
17253 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17254 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17255 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17256 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17257 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17258 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17259 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17260 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17261 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17264 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17265 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17266 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17267 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17269 /* Double precision load/store are still present on single precision
17270 implementations. */
17271 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17272 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17273 cCE("fldmiad", c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17274 cCE("fldmfdd", c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17275 cCE("fldmdbd", d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17276 cCE("fldmead", d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17277 cCE("fstmiad", c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17278 cCE("fstmead", c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17279 cCE("fstmdbd", d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17280 cCE("fstmfdd", d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17283 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17285 /* Moves and type conversions. */
17286 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17287 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17288 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17289 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17290 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17291 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17292 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17293 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17294 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17295 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17296 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17297 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17298 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17300 /* Monadic operations. */
17301 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17302 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17303 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17305 /* Dyadic operations. */
17306 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17307 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17308 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17309 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17310 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17311 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17312 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17313 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17314 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17317 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17318 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17319 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17320 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17323 #define ARM_VARIANT & fpu_vfp_ext_v2
17325 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17326 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17327 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17328 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17330 /* Instructions which may belong to either the Neon or VFP instruction sets.
17331 Individual encoder functions perform additional architecture checks. */
17333 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17334 #undef THUMB_VARIANT
17335 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17337 /* These mnemonics are unique to VFP. */
17338 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17339 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17340 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17341 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17342 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17343 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17344 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17345 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17346 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17347 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17349 /* Mnemonics shared by Neon and VFP. */
17350 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17351 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17352 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17354 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17355 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17357 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17358 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17360 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17361 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17362 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17363 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17364 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17365 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17366 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17367 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17369 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17370 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17371 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17374 /* NOTE: All VMOV encoding is special-cased! */
17375 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17376 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17378 #undef THUMB_VARIANT
17379 #define THUMB_VARIANT & fpu_neon_ext_v1
17381 #define ARM_VARIANT & fpu_neon_ext_v1
17383 /* Data processing with three registers of the same length. */
17384 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17385 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17386 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17387 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17388 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17389 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17390 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17391 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17392 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17393 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17394 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17395 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17396 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17397 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17398 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17399 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17400 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17401 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17402 /* If not immediate, fall back to neon_dyadic_i64_su.
17403 shl_imm should accept I8 I16 I32 I64,
17404 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17405 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17406 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17407 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17408 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17409 /* Logic ops, types optional & ignored. */
17410 nUF(vand
, _vand
, 2, (RNDQ
, NILO
), neon_logic
),
17411 nUF(vandq
, _vand
, 2, (RNQ
, NILO
), neon_logic
),
17412 nUF(vbic
, _vbic
, 2, (RNDQ
, NILO
), neon_logic
),
17413 nUF(vbicq
, _vbic
, 2, (RNQ
, NILO
), neon_logic
),
17414 nUF(vorr
, _vorr
, 2, (RNDQ
, NILO
), neon_logic
),
17415 nUF(vorrq
, _vorr
, 2, (RNQ
, NILO
), neon_logic
),
17416 nUF(vorn
, _vorn
, 2, (RNDQ
, NILO
), neon_logic
),
17417 nUF(vornq
, _vorn
, 2, (RNQ
, NILO
), neon_logic
),
17418 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17419 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17420 /* Bitfield ops, untyped. */
17421 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17422 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17423 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17424 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17425 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17426 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17427 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17428 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17429 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17430 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17431 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17432 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17433 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17434 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17435 back to neon_dyadic_if_su. */
17436 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17437 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17438 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17439 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17440 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17441 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17442 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17443 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17444 /* Comparison. Type I8 I16 I32 F32. */
17445 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17446 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17447 /* As above, D registers only. */
17448 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17449 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17450 /* Int and float variants, signedness unimportant. */
17451 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17452 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17453 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17454 /* Add/sub take types I8 I16 I32 I64 F32. */
17455 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17456 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17457 /* vtst takes sizes 8, 16, 32. */
17458 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17459 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17460 /* VMUL takes I8 I16 I32 F32 P8. */
17461 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17462 /* VQD{R}MULH takes S16 S32. */
17463 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17464 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17465 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17466 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17467 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17468 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17469 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17470 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17471 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17472 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17473 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17474 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17475 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17476 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17477 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17478 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17480 /* Two address, int/float. Types S8 S16 S32 F32. */
17481 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17482 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17484 /* Data processing with two registers and a shift amount. */
17485 /* Right shifts, and variants with rounding.
17486 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17487 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17488 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17489 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17490 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17491 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17492 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17493 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17494 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17495 /* Shift and insert. Sizes accepted 8 16 32 64. */
17496 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17497 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17498 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17499 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17500 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17501 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17502 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17503 /* Right shift immediate, saturating & narrowing, with rounding variants.
17504 Types accepted S16 S32 S64 U16 U32 U64. */
17505 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17506 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17507 /* As above, unsigned. Types accepted S16 S32 S64. */
17508 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17509 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17510 /* Right shift narrowing. Types accepted I16 I32 I64. */
17511 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17512 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17513 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17514 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17515 /* CVT with optional immediate for fixed-point variant. */
17516 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17518 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
17519 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
17521 /* Data processing, three registers of different lengths. */
17522 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17523 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17524 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17525 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17526 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17527 /* If not scalar, fall back to neon_dyadic_long.
17528 Vector types as above, scalar types S16 S32 U16 U32. */
17529 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17530 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17531 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17532 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17533 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17534 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17535 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17536 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17537 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17538 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17539 /* Saturating doubling multiplies. Types S16 S32. */
17540 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17541 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17542 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17543 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17544 S16 S32 U16 U32. */
17545 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17547 /* Extract. Size 8. */
17548 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17549 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17551 /* Two registers, miscellaneous. */
17552 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17553 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17554 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17555 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17556 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17557 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17558 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17559 /* Vector replicate. Sizes 8 16 32. */
17560 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17561 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17562 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17563 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17564 /* VMOVN. Types I16 I32 I64. */
17565 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17566 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17567 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17568 /* VQMOVUN. Types S16 S32 S64. */
17569 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17570 /* VZIP / VUZP. Sizes 8 16 32. */
17571 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17572 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17573 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17574 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17575 /* VQABS / VQNEG. Types S8 S16 S32. */
17576 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17577 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17578 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17579 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17580 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17581 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17582 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17583 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17584 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17585 /* Reciprocal estimates. Types U32 F32. */
17586 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17587 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17588 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17589 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17590 /* VCLS. Types S8 S16 S32. */
17591 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17592 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17593 /* VCLZ. Types I8 I16 I32. */
17594 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17595 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17596 /* VCNT. Size 8. */
17597 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17598 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17599 /* Two address, untyped. */
17600 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17601 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17602 /* VTRN. Sizes 8 16 32. */
17603 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17604 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17606 /* Table lookup. Size 8. */
17607 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17608 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17610 #undef THUMB_VARIANT
17611 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17613 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17615 /* Neon element/structure load/store. */
17616 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17617 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17618 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17619 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17620 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17621 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17622 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17623 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17625 #undef THUMB_VARIANT
17626 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
17628 #define ARM_VARIANT &fpu_vfp_ext_v3xd
17629 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17630 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17631 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17632 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17633 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17634 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17635 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17636 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17637 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17639 #undef THUMB_VARIANT
17640 #define THUMB_VARIANT & fpu_vfp_ext_v3
17642 #define ARM_VARIANT & fpu_vfp_ext_v3
17644 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17645 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17646 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17647 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17648 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17649 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17650 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17651 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17652 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17655 #define ARM_VARIANT &fpu_vfp_ext_fma
17656 #undef THUMB_VARIANT
17657 #define THUMB_VARIANT &fpu_vfp_ext_fma
17658 /* Mnemonics shared by Neon and VFP. These are included in the
17659 VFP FMA variant; NEON and VFP FMA always includes the NEON
17660 FMA instructions. */
17661 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17662 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17663 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
17664 the v form should always be used. */
17665 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17666 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17667 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17668 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17669 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17670 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17672 #undef THUMB_VARIANT
17674 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17676 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17677 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17678 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17679 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17680 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17681 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17682 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
17683 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
17686 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17688 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
17689 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
17690 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
17691 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
17692 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
17693 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
17694 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
17695 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
17696 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
17697 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17698 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17699 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17700 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17701 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17702 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17703 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17704 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17705 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17706 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
17707 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
17708 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17709 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17710 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17711 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17712 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17713 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17714 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
17715 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
17716 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
17717 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
17718 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
17719 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
17720 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
17721 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
17722 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17723 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17724 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17725 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17726 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17727 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17728 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17729 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17730 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17731 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17732 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17733 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17734 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
17735 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17736 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17737 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17738 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17739 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17740 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17741 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17742 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17743 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17744 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17745 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17746 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17747 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17748 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17749 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17750 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17751 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17752 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17753 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17754 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17755 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17756 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17757 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17758 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17759 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17760 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17761 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17762 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17763 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17764 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17765 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17766 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17767 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17768 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17769 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17770 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17771 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17772 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17773 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17774 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17775 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17776 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
17777 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17778 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17779 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17780 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17781 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17782 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17783 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17784 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17785 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17786 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17787 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17788 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17789 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17790 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17791 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17792 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17793 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17794 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17795 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17796 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17797 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17798 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
17799 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17800 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17801 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17802 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17803 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17804 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17805 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17806 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17807 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17808 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17809 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17810 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17811 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17812 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17813 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17814 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17815 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17816 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17817 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17818 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17819 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17820 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17821 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17822 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17823 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17824 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17825 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17826 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17827 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17828 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17829 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17830 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17831 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17832 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17833 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17834 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17835 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17836 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17837 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17838 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17839 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17840 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17841 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17842 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17843 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17844 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17845 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17846 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17847 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17848 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17849 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
17852 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
17854 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
17855 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
17856 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
17857 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17858 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17859 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17860 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17861 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17862 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17863 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17864 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17865 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17866 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17867 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17868 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17869 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17870 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17871 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17872 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17873 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17874 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
17875 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17876 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17877 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17878 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17879 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17880 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17881 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17882 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17883 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17884 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17885 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17886 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17887 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17888 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17889 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17890 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17891 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17892 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17893 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17894 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17895 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17896 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17897 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17898 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17899 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17900 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17901 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17902 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17903 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17904 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17905 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17906 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17907 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17908 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17909 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17910 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17913 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
17915 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17916 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17917 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17918 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17919 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17920 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17921 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17922 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17923 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
17924 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
17925 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
17926 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
17927 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
17928 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
17929 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
17930 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
17931 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
17932 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
17933 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
17934 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
17935 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
17936 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
17937 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
17938 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
17939 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
17940 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
17941 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
17942 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
17943 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
17944 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
17945 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
17946 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
17947 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
17948 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
17949 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
17950 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
17951 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
17952 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
17953 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
17954 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
17955 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
17956 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
17957 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
17958 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
17959 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
17960 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
17961 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
17962 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
17963 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
17964 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
17965 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
17966 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
17967 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
17968 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
17969 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17970 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17971 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17972 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17973 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17974 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17975 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
17976 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
17977 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
17978 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
17979 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17980 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17981 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17982 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17983 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17984 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17985 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17986 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17987 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17988 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17989 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17990 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17993 #undef THUMB_VARIANT
18020 /* MD interface: bits in the object file. */
18022 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18023 for use in the a.out file, and stores them in the array pointed to by buf.
18024 This knows about the endian-ness of the target machine and does
18025 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18026 2 (short) and 4 (long) Floating numbers are put out as a series of
18027 LITTLENUMS (shorts, here at least). */
18030 md_number_to_chars (char * buf
, valueT val
, int n
)
18032 if (target_big_endian
)
18033 number_to_chars_bigendian (buf
, val
, n
);
18035 number_to_chars_littleendian (buf
, val
, n
);
18039 md_chars_to_number (char * buf
, int n
)
18042 unsigned char * where
= (unsigned char *) buf
;
18044 if (target_big_endian
)
18049 result
|= (*where
++ & 255);
18057 result
|= (where
[n
] & 255);
18064 /* MD interface: Sections. */
18066 /* Estimate the size of a frag before relaxing. Assume everything fits in
18070 md_estimate_size_before_relax (fragS
* fragp
,
18071 segT segtype ATTRIBUTE_UNUSED
)
18077 /* Convert a machine dependent frag. */
18080 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18082 unsigned long insn
;
18083 unsigned long old_op
;
18091 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18093 old_op
= bfd_get_16(abfd
, buf
);
18094 if (fragp
->fr_symbol
)
18096 exp
.X_op
= O_symbol
;
18097 exp
.X_add_symbol
= fragp
->fr_symbol
;
18101 exp
.X_op
= O_constant
;
18103 exp
.X_add_number
= fragp
->fr_offset
;
18104 opcode
= fragp
->fr_subtype
;
18107 case T_MNEM_ldr_pc
:
18108 case T_MNEM_ldr_pc2
:
18109 case T_MNEM_ldr_sp
:
18110 case T_MNEM_str_sp
:
18117 if (fragp
->fr_var
== 4)
18119 insn
= THUMB_OP32 (opcode
);
18120 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18122 insn
|= (old_op
& 0x700) << 4;
18126 insn
|= (old_op
& 7) << 12;
18127 insn
|= (old_op
& 0x38) << 13;
18129 insn
|= 0x00000c00;
18130 put_thumb32_insn (buf
, insn
);
18131 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18135 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18137 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18140 if (fragp
->fr_var
== 4)
18142 insn
= THUMB_OP32 (opcode
);
18143 insn
|= (old_op
& 0xf0) << 4;
18144 put_thumb32_insn (buf
, insn
);
18145 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18149 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18150 exp
.X_add_number
-= 4;
18158 if (fragp
->fr_var
== 4)
18160 int r0off
= (opcode
== T_MNEM_mov
18161 || opcode
== T_MNEM_movs
) ? 0 : 8;
18162 insn
= THUMB_OP32 (opcode
);
18163 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18164 insn
|= (old_op
& 0x700) << r0off
;
18165 put_thumb32_insn (buf
, insn
);
18166 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18170 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18175 if (fragp
->fr_var
== 4)
18177 insn
= THUMB_OP32(opcode
);
18178 put_thumb32_insn (buf
, insn
);
18179 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18182 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18186 if (fragp
->fr_var
== 4)
18188 insn
= THUMB_OP32(opcode
);
18189 insn
|= (old_op
& 0xf00) << 14;
18190 put_thumb32_insn (buf
, insn
);
18191 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18194 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18197 case T_MNEM_add_sp
:
18198 case T_MNEM_add_pc
:
18199 case T_MNEM_inc_sp
:
18200 case T_MNEM_dec_sp
:
18201 if (fragp
->fr_var
== 4)
18203 /* ??? Choose between add and addw. */
18204 insn
= THUMB_OP32 (opcode
);
18205 insn
|= (old_op
& 0xf0) << 4;
18206 put_thumb32_insn (buf
, insn
);
18207 if (opcode
== T_MNEM_add_pc
)
18208 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18210 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18213 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18221 if (fragp
->fr_var
== 4)
18223 insn
= THUMB_OP32 (opcode
);
18224 insn
|= (old_op
& 0xf0) << 4;
18225 insn
|= (old_op
& 0xf) << 16;
18226 put_thumb32_insn (buf
, insn
);
18227 if (insn
& (1 << 20))
18228 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18230 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18233 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18239 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18240 (enum bfd_reloc_code_real
) reloc_type
);
18241 fixp
->fx_file
= fragp
->fr_file
;
18242 fixp
->fx_line
= fragp
->fr_line
;
18243 fragp
->fr_fix
+= fragp
->fr_var
;
18246 /* Return the size of a relaxable immediate operand instruction.
18247 SHIFT and SIZE specify the form of the allowable immediate. */
18249 relax_immediate (fragS
*fragp
, int size
, int shift
)
18255 /* ??? Should be able to do better than this. */
18256 if (fragp
->fr_symbol
)
18259 low
= (1 << shift
) - 1;
18260 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18261 offset
= fragp
->fr_offset
;
18262 /* Force misaligned offsets to 32-bit variant. */
18265 if (offset
& ~mask
)
18270 /* Get the address of a symbol during relaxation. */
18272 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18278 sym
= fragp
->fr_symbol
;
18279 sym_frag
= symbol_get_frag (sym
);
18280 know (S_GET_SEGMENT (sym
) != absolute_section
18281 || sym_frag
== &zero_address_frag
);
18282 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18284 /* If frag has yet to be reached on this pass, assume it will
18285 move by STRETCH just as we did. If this is not so, it will
18286 be because some frag between grows, and that will force
18290 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18294 /* Adjust stretch for any alignment frag. Note that if have
18295 been expanding the earlier code, the symbol may be
18296 defined in what appears to be an earlier frag. FIXME:
18297 This doesn't handle the fr_subtype field, which specifies
18298 a maximum number of bytes to skip when doing an
18300 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18302 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18305 stretch
= - ((- stretch
)
18306 & ~ ((1 << (int) f
->fr_offset
) - 1));
18308 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18320 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18323 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18328 /* Assume worst case for symbols not known to be in the same section. */
18329 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18330 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18333 val
= relaxed_symbol_addr (fragp
, stretch
);
18334 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18335 addr
= (addr
+ 4) & ~3;
18336 /* Force misaligned targets to 32-bit variant. */
18340 if (val
< 0 || val
> 1020)
18345 /* Return the size of a relaxable add/sub immediate instruction. */
18347 relax_addsub (fragS
*fragp
, asection
*sec
)
18352 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18353 op
= bfd_get_16(sec
->owner
, buf
);
18354 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18355 return relax_immediate (fragp
, 8, 0);
18357 return relax_immediate (fragp
, 3, 0);
18361 /* Return the size of a relaxable branch instruction. BITS is the
18362 size of the offset field in the narrow instruction. */
18365 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18371 /* Assume worst case for symbols not known to be in the same section. */
18372 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18373 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18377 if (S_IS_DEFINED (fragp
->fr_symbol
)
18378 && ARM_IS_FUNC (fragp
->fr_symbol
))
18382 val
= relaxed_symbol_addr (fragp
, stretch
);
18383 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18386 /* Offset is a signed value *2 */
18388 if (val
>= limit
|| val
< -limit
)
18394 /* Relax a machine dependent frag. This returns the amount by which
18395 the current size of the frag should change. */
18398 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18403 oldsize
= fragp
->fr_var
;
18404 switch (fragp
->fr_subtype
)
18406 case T_MNEM_ldr_pc2
:
18407 newsize
= relax_adr (fragp
, sec
, stretch
);
18409 case T_MNEM_ldr_pc
:
18410 case T_MNEM_ldr_sp
:
18411 case T_MNEM_str_sp
:
18412 newsize
= relax_immediate (fragp
, 8, 2);
18416 newsize
= relax_immediate (fragp
, 5, 2);
18420 newsize
= relax_immediate (fragp
, 5, 1);
18424 newsize
= relax_immediate (fragp
, 5, 0);
18427 newsize
= relax_adr (fragp
, sec
, stretch
);
18433 newsize
= relax_immediate (fragp
, 8, 0);
18436 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18439 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18441 case T_MNEM_add_sp
:
18442 case T_MNEM_add_pc
:
18443 newsize
= relax_immediate (fragp
, 8, 2);
18445 case T_MNEM_inc_sp
:
18446 case T_MNEM_dec_sp
:
18447 newsize
= relax_immediate (fragp
, 7, 2);
18453 newsize
= relax_addsub (fragp
, sec
);
18459 fragp
->fr_var
= newsize
;
18460 /* Freeze wide instructions that are at or before the same location as
18461 in the previous pass. This avoids infinite loops.
18462 Don't freeze them unconditionally because targets may be artificially
18463 misaligned by the expansion of preceding frags. */
18464 if (stretch
<= 0 && newsize
> 2)
18466 md_convert_frag (sec
->owner
, sec
, fragp
);
18470 return newsize
- oldsize
;
18473 /* Round up a section size to the appropriate boundary. */
18476 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18479 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18480 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18482 /* For a.out, force the section size to be aligned. If we don't do
18483 this, BFD will align it for us, but it will not write out the
18484 final bytes of the section. This may be a bug in BFD, but it is
18485 easier to fix it here since that is how the other a.out targets
18489 align
= bfd_get_section_alignment (stdoutput
, segment
);
18490 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18497 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18498 of an rs_align_code fragment. */
18501 arm_handle_align (fragS
* fragP
)
18503 static char const arm_noop
[2][2][4] =
18506 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18507 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18510 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18511 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18514 static char const thumb_noop
[2][2][2] =
18517 {0xc0, 0x46}, /* LE */
18518 {0x46, 0xc0}, /* BE */
18521 {0x00, 0xbf}, /* LE */
18522 {0xbf, 0x00} /* BE */
18525 static char const wide_thumb_noop
[2][4] =
18526 { /* Wide Thumb-2 */
18527 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18528 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18531 unsigned bytes
, fix
, noop_size
;
18534 const char *narrow_noop
= NULL
;
18539 if (fragP
->fr_type
!= rs_align_code
)
18542 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18543 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18546 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18547 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18550 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18553 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18555 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18557 narrow_noop
= thumb_noop
[1][target_big_endian
];
18558 noop
= wide_thumb_noop
[target_big_endian
];
18561 noop
= thumb_noop
[0][target_big_endian
];
18569 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18570 [target_big_endian
];
18577 fragP
->fr_var
= noop_size
;
18579 if (bytes
& (noop_size
- 1))
18581 fix
= bytes
& (noop_size
- 1);
18583 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18585 memset (p
, 0, fix
);
18592 if (bytes
& noop_size
)
18594 /* Insert a narrow noop. */
18595 memcpy (p
, narrow_noop
, noop_size
);
18597 bytes
-= noop_size
;
18601 /* Use wide noops for the remainder */
18605 while (bytes
>= noop_size
)
18607 memcpy (p
, noop
, noop_size
);
18609 bytes
-= noop_size
;
18613 fragP
->fr_fix
+= fix
;
18616 /* Called from md_do_align. Used to create an alignment
18617 frag in a code section. */
18620 arm_frag_align_code (int n
, int max
)
18624 /* We assume that there will never be a requirement
18625 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18626 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18631 _("alignments greater than %d bytes not supported in .text sections."),
18632 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18633 as_fatal ("%s", err_msg
);
18636 p
= frag_var (rs_align_code
,
18637 MAX_MEM_FOR_RS_ALIGN_CODE
,
18639 (relax_substateT
) max
,
18646 /* Perform target specific initialisation of a frag.
18647 Note - despite the name this initialisation is not done when the frag
18648 is created, but only when its type is assigned. A frag can be created
18649 and used a long time before its type is set, so beware of assuming that
18650 this initialisationis performed first. */
18654 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
18656 /* Record whether this frag is in an ARM or a THUMB area. */
18657 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
;
18660 #else /* OBJ_ELF is defined. */
18662 arm_init_frag (fragS
* fragP
, int max_chars
)
18664 /* If the current ARM vs THUMB mode has not already
18665 been recorded into this frag then do so now. */
18666 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
18668 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18670 /* Record a mapping symbol for alignment frags. We will delete this
18671 later if the alignment ends up empty. */
18672 switch (fragP
->fr_type
)
18675 case rs_align_test
:
18677 mapping_state_2 (MAP_DATA
, max_chars
);
18679 case rs_align_code
:
18680 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
18688 /* When we change sections we need to issue a new mapping symbol. */
18691 arm_elf_change_section (void)
18693 /* Link an unlinked unwind index table section to the .text section. */
18694 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
18695 && elf_linked_to_section (now_seg
) == NULL
)
18696 elf_linked_to_section (now_seg
) = text_section
;
18700 arm_elf_section_type (const char * str
, size_t len
)
18702 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
18703 return SHT_ARM_EXIDX
;
18708 /* Code to deal with unwinding tables. */
18710 static void add_unwind_adjustsp (offsetT
);
18712 /* Generate any deferred unwind frame offset. */
18715 flush_pending_unwind (void)
18719 offset
= unwind
.pending_offset
;
18720 unwind
.pending_offset
= 0;
18722 add_unwind_adjustsp (offset
);
18725 /* Add an opcode to this list for this function. Two-byte opcodes should
18726 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
18730 add_unwind_opcode (valueT op
, int length
)
18732 /* Add any deferred stack adjustment. */
18733 if (unwind
.pending_offset
)
18734 flush_pending_unwind ();
18736 unwind
.sp_restored
= 0;
18738 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
18740 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
18741 if (unwind
.opcodes
)
18742 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
18743 unwind
.opcode_alloc
);
18745 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
18750 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
18752 unwind
.opcode_count
++;
18756 /* Add unwind opcodes to adjust the stack pointer. */
18759 add_unwind_adjustsp (offsetT offset
)
18763 if (offset
> 0x200)
18765 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
18770 /* Long form: 0xb2, uleb128. */
18771 /* This might not fit in a word so add the individual bytes,
18772 remembering the list is built in reverse order. */
18773 o
= (valueT
) ((offset
- 0x204) >> 2);
18775 add_unwind_opcode (0, 1);
18777 /* Calculate the uleb128 encoding of the offset. */
18781 bytes
[n
] = o
& 0x7f;
18787 /* Add the insn. */
18789 add_unwind_opcode (bytes
[n
- 1], 1);
18790 add_unwind_opcode (0xb2, 1);
18792 else if (offset
> 0x100)
18794 /* Two short opcodes. */
18795 add_unwind_opcode (0x3f, 1);
18796 op
= (offset
- 0x104) >> 2;
18797 add_unwind_opcode (op
, 1);
18799 else if (offset
> 0)
18801 /* Short opcode. */
18802 op
= (offset
- 4) >> 2;
18803 add_unwind_opcode (op
, 1);
18805 else if (offset
< 0)
18808 while (offset
> 0x100)
18810 add_unwind_opcode (0x7f, 1);
18813 op
= ((offset
- 4) >> 2) | 0x40;
18814 add_unwind_opcode (op
, 1);
18818 /* Finish the list of unwind opcodes for this function. */
18820 finish_unwind_opcodes (void)
18824 if (unwind
.fp_used
)
18826 /* Adjust sp as necessary. */
18827 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
18828 flush_pending_unwind ();
18830 /* After restoring sp from the frame pointer. */
18831 op
= 0x90 | unwind
.fp_reg
;
18832 add_unwind_opcode (op
, 1);
18835 flush_pending_unwind ();
18839 /* Start an exception table entry. If idx is nonzero this is an index table
18843 start_unwind_section (const segT text_seg
, int idx
)
18845 const char * text_name
;
18846 const char * prefix
;
18847 const char * prefix_once
;
18848 const char * group_name
;
18852 size_t sec_name_len
;
18859 prefix
= ELF_STRING_ARM_unwind
;
18860 prefix_once
= ELF_STRING_ARM_unwind_once
;
18861 type
= SHT_ARM_EXIDX
;
18865 prefix
= ELF_STRING_ARM_unwind_info
;
18866 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
18867 type
= SHT_PROGBITS
;
18870 text_name
= segment_name (text_seg
);
18871 if (streq (text_name
, ".text"))
18874 if (strncmp (text_name
, ".gnu.linkonce.t.",
18875 strlen (".gnu.linkonce.t.")) == 0)
18877 prefix
= prefix_once
;
18878 text_name
+= strlen (".gnu.linkonce.t.");
18881 prefix_len
= strlen (prefix
);
18882 text_len
= strlen (text_name
);
18883 sec_name_len
= prefix_len
+ text_len
;
18884 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
18885 memcpy (sec_name
, prefix
, prefix_len
);
18886 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
18887 sec_name
[prefix_len
+ text_len
] = '\0';
18893 /* Handle COMDAT group. */
18894 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
18896 group_name
= elf_group_name (text_seg
);
18897 if (group_name
== NULL
)
18899 as_bad (_("Group section `%s' has no group signature"),
18900 segment_name (text_seg
));
18901 ignore_rest_of_line ();
18904 flags
|= SHF_GROUP
;
18908 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
18910 /* Set the section link for index tables. */
18912 elf_linked_to_section (now_seg
) = text_seg
;
18916 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
18917 personality routine data. Returns zero, or the index table value for
18918 and inline entry. */
18921 create_unwind_entry (int have_data
)
18926 /* The current word of data. */
18928 /* The number of bytes left in this word. */
18931 finish_unwind_opcodes ();
18933 /* Remember the current text section. */
18934 unwind
.saved_seg
= now_seg
;
18935 unwind
.saved_subseg
= now_subseg
;
18937 start_unwind_section (now_seg
, 0);
18939 if (unwind
.personality_routine
== NULL
)
18941 if (unwind
.personality_index
== -2)
18944 as_bad (_("handlerdata in cantunwind frame"));
18945 return 1; /* EXIDX_CANTUNWIND. */
18948 /* Use a default personality routine if none is specified. */
18949 if (unwind
.personality_index
== -1)
18951 if (unwind
.opcode_count
> 3)
18952 unwind
.personality_index
= 1;
18954 unwind
.personality_index
= 0;
18957 /* Space for the personality routine entry. */
18958 if (unwind
.personality_index
== 0)
18960 if (unwind
.opcode_count
> 3)
18961 as_bad (_("too many unwind opcodes for personality routine 0"));
18965 /* All the data is inline in the index table. */
18968 while (unwind
.opcode_count
> 0)
18970 unwind
.opcode_count
--;
18971 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
18975 /* Pad with "finish" opcodes. */
18977 data
= (data
<< 8) | 0xb0;
18984 /* We get two opcodes "free" in the first word. */
18985 size
= unwind
.opcode_count
- 2;
18988 /* An extra byte is required for the opcode count. */
18989 size
= unwind
.opcode_count
+ 1;
18991 size
= (size
+ 3) >> 2;
18993 as_bad (_("too many unwind opcodes"));
18995 frag_align (2, 0, 0);
18996 record_alignment (now_seg
, 2);
18997 unwind
.table_entry
= expr_build_dot ();
18999 /* Allocate the table entry. */
19000 ptr
= frag_more ((size
<< 2) + 4);
19001 where
= frag_now_fix () - ((size
<< 2) + 4);
19003 switch (unwind
.personality_index
)
19006 /* ??? Should this be a PLT generating relocation? */
19007 /* Custom personality routine. */
19008 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19009 BFD_RELOC_ARM_PREL31
);
19014 /* Set the first byte to the number of additional words. */
19019 /* ABI defined personality routines. */
19021 /* Three opcodes bytes are packed into the first word. */
19028 /* The size and first two opcode bytes go in the first word. */
19029 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19034 /* Should never happen. */
19038 /* Pack the opcodes into words (MSB first), reversing the list at the same
19040 while (unwind
.opcode_count
> 0)
19044 md_number_to_chars (ptr
, data
, 4);
19049 unwind
.opcode_count
--;
19051 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19054 /* Finish off the last word. */
19057 /* Pad with "finish" opcodes. */
19059 data
= (data
<< 8) | 0xb0;
19061 md_number_to_chars (ptr
, data
, 4);
19066 /* Add an empty descriptor if there is no user-specified data. */
19067 ptr
= frag_more (4);
19068 md_number_to_chars (ptr
, 0, 4);
19075 /* Initialize the DWARF-2 unwind information for this procedure. */
19078 tc_arm_frame_initial_instructions (void)
19080 cfi_add_CFA_def_cfa (REG_SP
, 0);
19082 #endif /* OBJ_ELF */
19084 /* Convert REGNAME to a DWARF-2 register number. */
19087 tc_arm_regname_to_dw2regnum (char *regname
)
19089 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19099 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19103 expr
.X_op
= O_secrel
;
19104 expr
.X_add_symbol
= symbol
;
19105 expr
.X_add_number
= 0;
19106 emit_expr (&expr
, size
);
19110 /* MD interface: Symbol and relocation handling. */
19112 /* Return the address within the segment that a PC-relative fixup is
19113 relative to. For ARM, PC-relative fixups applied to instructions
19114 are generally relative to the location of the fixup plus 8 bytes.
19115 Thumb branches are offset by 4, and Thumb loads relative to PC
19116 require special handling. */
19119 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19121 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19123 /* If this is pc-relative and we are going to emit a relocation
19124 then we just want to put out any pipeline compensation that the linker
19125 will need. Otherwise we want to use the calculated base.
19126 For WinCE we skip the bias for externals as well, since this
19127 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19129 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19130 || (arm_force_relocation (fixP
)
19132 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19138 switch (fixP
->fx_r_type
)
19140 /* PC relative addressing on the Thumb is slightly odd as the
19141 bottom two bits of the PC are forced to zero for the
19142 calculation. This happens *after* application of the
19143 pipeline offset. However, Thumb adrl already adjusts for
19144 this, so we need not do it again. */
19145 case BFD_RELOC_ARM_THUMB_ADD
:
19148 case BFD_RELOC_ARM_THUMB_OFFSET
:
19149 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19150 case BFD_RELOC_ARM_T32_ADD_PC12
:
19151 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19152 return (base
+ 4) & ~3;
19154 /* Thumb branches are simply offset by +4. */
19155 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19156 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19157 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19158 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19159 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19162 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19164 && ARM_IS_FUNC (fixP
->fx_addsy
)
19165 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19166 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19169 /* BLX is like branches above, but forces the low two bits of PC to
19171 case BFD_RELOC_THUMB_PCREL_BLX
:
19173 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19174 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19175 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19176 return (base
+ 4) & ~3;
19178 /* ARM mode branches are offset by +8. However, the Windows CE
19179 loader expects the relocation not to take this into account. */
19180 case BFD_RELOC_ARM_PCREL_BLX
:
19182 && ARM_IS_FUNC (fixP
->fx_addsy
)
19183 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19184 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19187 case BFD_RELOC_ARM_PCREL_CALL
:
19189 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19190 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19191 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19194 case BFD_RELOC_ARM_PCREL_BRANCH
:
19195 case BFD_RELOC_ARM_PCREL_JUMP
:
19196 case BFD_RELOC_ARM_PLT32
:
19198 /* When handling fixups immediately, because we have already
19199 discovered the value of a symbol, or the address of the frag involved
19200 we must account for the offset by +8, as the OS loader will never see the reloc.
19201 see fixup_segment() in write.c
19202 The S_IS_EXTERNAL test handles the case of global symbols.
19203 Those need the calculated base, not just the pipe compensation the linker will need. */
19205 && fixP
->fx_addsy
!= NULL
19206 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19207 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19215 /* ARM mode loads relative to PC are also offset by +8. Unlike
19216 branches, the Windows CE loader *does* expect the relocation
19217 to take this into account. */
19218 case BFD_RELOC_ARM_OFFSET_IMM
:
19219 case BFD_RELOC_ARM_OFFSET_IMM8
:
19220 case BFD_RELOC_ARM_HWLITERAL
:
19221 case BFD_RELOC_ARM_LITERAL
:
19222 case BFD_RELOC_ARM_CP_OFF_IMM
:
19226 /* Other PC-relative relocations are un-offset. */
19232 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19233 Otherwise we have no need to default values of symbols. */
19236 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19239 if (name
[0] == '_' && name
[1] == 'G'
19240 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19244 if (symbol_find (name
))
19245 as_bad (_("GOT already in the symbol table"));
19247 GOT_symbol
= symbol_new (name
, undefined_section
,
19248 (valueT
) 0, & zero_address_frag
);
19258 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19259 computed as two separate immediate values, added together. We
19260 already know that this value cannot be computed by just one ARM
19263 static unsigned int
19264 validate_immediate_twopart (unsigned int val
,
19265 unsigned int * highpart
)
19270 for (i
= 0; i
< 32; i
+= 2)
19271 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19277 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19279 else if (a
& 0xff0000)
19281 if (a
& 0xff000000)
19283 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19287 gas_assert (a
& 0xff000000);
19288 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19291 return (a
& 0xff) | (i
<< 7);
19298 validate_offset_imm (unsigned int val
, int hwse
)
19300 if ((hwse
&& val
> 255) || val
> 4095)
19305 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19306 negative immediate constant by altering the instruction. A bit of
19311 by inverting the second operand, and
19314 by negating the second operand. */
19317 negate_data_op (unsigned long * instruction
,
19318 unsigned long value
)
19321 unsigned long negated
, inverted
;
19323 negated
= encode_arm_immediate (-value
);
19324 inverted
= encode_arm_immediate (~value
);
19326 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19329 /* First negates. */
19330 case OPCODE_SUB
: /* ADD <-> SUB */
19331 new_inst
= OPCODE_ADD
;
19336 new_inst
= OPCODE_SUB
;
19340 case OPCODE_CMP
: /* CMP <-> CMN */
19341 new_inst
= OPCODE_CMN
;
19346 new_inst
= OPCODE_CMP
;
19350 /* Now Inverted ops. */
19351 case OPCODE_MOV
: /* MOV <-> MVN */
19352 new_inst
= OPCODE_MVN
;
19357 new_inst
= OPCODE_MOV
;
19361 case OPCODE_AND
: /* AND <-> BIC */
19362 new_inst
= OPCODE_BIC
;
19367 new_inst
= OPCODE_AND
;
19371 case OPCODE_ADC
: /* ADC <-> SBC */
19372 new_inst
= OPCODE_SBC
;
19377 new_inst
= OPCODE_ADC
;
19381 /* We cannot do anything. */
19386 if (value
== (unsigned) FAIL
)
19389 *instruction
&= OPCODE_MASK
;
19390 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19394 /* Like negate_data_op, but for Thumb-2. */
19396 static unsigned int
19397 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19401 unsigned int negated
, inverted
;
19403 negated
= encode_thumb32_immediate (-value
);
19404 inverted
= encode_thumb32_immediate (~value
);
19406 rd
= (*instruction
>> 8) & 0xf;
19407 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19410 /* ADD <-> SUB. Includes CMP <-> CMN. */
19411 case T2_OPCODE_SUB
:
19412 new_inst
= T2_OPCODE_ADD
;
19416 case T2_OPCODE_ADD
:
19417 new_inst
= T2_OPCODE_SUB
;
19421 /* ORR <-> ORN. Includes MOV <-> MVN. */
19422 case T2_OPCODE_ORR
:
19423 new_inst
= T2_OPCODE_ORN
;
19427 case T2_OPCODE_ORN
:
19428 new_inst
= T2_OPCODE_ORR
;
19432 /* AND <-> BIC. TST has no inverted equivalent. */
19433 case T2_OPCODE_AND
:
19434 new_inst
= T2_OPCODE_BIC
;
19441 case T2_OPCODE_BIC
:
19442 new_inst
= T2_OPCODE_AND
;
19447 case T2_OPCODE_ADC
:
19448 new_inst
= T2_OPCODE_SBC
;
19452 case T2_OPCODE_SBC
:
19453 new_inst
= T2_OPCODE_ADC
;
19457 /* We cannot do anything. */
19462 if (value
== (unsigned int)FAIL
)
19465 *instruction
&= T2_OPCODE_MASK
;
19466 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19470 /* Read a 32-bit thumb instruction from buf. */
19471 static unsigned long
19472 get_thumb32_insn (char * buf
)
19474 unsigned long insn
;
19475 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19476 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19482 /* We usually want to set the low bit on the address of thumb function
19483 symbols. In particular .word foo - . should have the low bit set.
19484 Generic code tries to fold the difference of two symbols to
19485 a constant. Prevent this and force a relocation when the first symbols
19486 is a thumb function. */
19489 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19491 if (op
== O_subtract
19492 && l
->X_op
== O_symbol
19493 && r
->X_op
== O_symbol
19494 && THUMB_IS_FUNC (l
->X_add_symbol
))
19496 l
->X_op
= O_subtract
;
19497 l
->X_op_symbol
= r
->X_add_symbol
;
19498 l
->X_add_number
-= r
->X_add_number
;
19502 /* Process as normal. */
19507 md_apply_fix (fixS
* fixP
,
19511 offsetT value
= * valP
;
19513 unsigned int newimm
;
19514 unsigned long temp
;
19516 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19518 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19520 /* Note whether this will delete the relocation. */
19522 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19525 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19526 consistency with the behaviour on 32-bit hosts. Remember value
19528 value
&= 0xffffffff;
19529 value
^= 0x80000000;
19530 value
-= 0x80000000;
19533 fixP
->fx_addnumber
= value
;
19535 /* Same treatment for fixP->fx_offset. */
19536 fixP
->fx_offset
&= 0xffffffff;
19537 fixP
->fx_offset
^= 0x80000000;
19538 fixP
->fx_offset
-= 0x80000000;
19540 switch (fixP
->fx_r_type
)
19542 case BFD_RELOC_NONE
:
19543 /* This will need to go in the object file. */
19547 case BFD_RELOC_ARM_IMMEDIATE
:
19548 /* We claim that this fixup has been processed here,
19549 even if in fact we generate an error because we do
19550 not have a reloc for it, so tc_gen_reloc will reject it. */
19554 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19556 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19557 _("undefined symbol %s used as an immediate value"),
19558 S_GET_NAME (fixP
->fx_addsy
));
19563 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19566 _("symbol %s is in a different section"),
19567 S_GET_NAME (fixP
->fx_addsy
));
19571 newimm
= encode_arm_immediate (value
);
19572 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19574 /* If the instruction will fail, see if we can fix things up by
19575 changing the opcode. */
19576 if (newimm
== (unsigned int) FAIL
19577 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19580 _("invalid constant (%lx) after fixup"),
19581 (unsigned long) value
);
19585 newimm
|= (temp
& 0xfffff000);
19586 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19589 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19591 unsigned int highpart
= 0;
19592 unsigned int newinsn
= 0xe1a00000; /* nop. */
19595 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19597 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19598 _("undefined symbol %s used as an immediate value"),
19599 S_GET_NAME (fixP
->fx_addsy
));
19604 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19606 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19607 _("symbol %s is in a different section"),
19608 S_GET_NAME (fixP
->fx_addsy
));
19612 newimm
= encode_arm_immediate (value
);
19613 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19615 /* If the instruction will fail, see if we can fix things up by
19616 changing the opcode. */
19617 if (newimm
== (unsigned int) FAIL
19618 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19620 /* No ? OK - try using two ADD instructions to generate
19622 newimm
= validate_immediate_twopart (value
, & highpart
);
19624 /* Yes - then make sure that the second instruction is
19626 if (newimm
!= (unsigned int) FAIL
)
19628 /* Still No ? Try using a negated value. */
19629 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19630 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19631 /* Otherwise - give up. */
19634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19635 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19640 /* Replace the first operand in the 2nd instruction (which
19641 is the PC) with the destination register. We have
19642 already added in the PC in the first instruction and we
19643 do not want to do it again. */
19644 newinsn
&= ~ 0xf0000;
19645 newinsn
|= ((newinsn
& 0x0f000) << 4);
19648 newimm
|= (temp
& 0xfffff000);
19649 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19651 highpart
|= (newinsn
& 0xfffff000);
19652 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
19656 case BFD_RELOC_ARM_OFFSET_IMM
:
19657 if (!fixP
->fx_done
&& seg
->use_rela_p
)
19660 case BFD_RELOC_ARM_LITERAL
:
19666 if (validate_offset_imm (value
, 0) == FAIL
)
19668 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
19669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19670 _("invalid literal constant: pool needs to be closer"));
19672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19673 _("bad immediate value for offset (%ld)"),
19678 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19679 newval
&= 0xff7ff000;
19680 newval
|= value
| (sign
? INDEX_UP
: 0);
19681 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19684 case BFD_RELOC_ARM_OFFSET_IMM8
:
19685 case BFD_RELOC_ARM_HWLITERAL
:
19691 if (validate_offset_imm (value
, 1) == FAIL
)
19693 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
19694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19695 _("invalid literal constant: pool needs to be closer"));
19697 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
19702 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19703 newval
&= 0xff7ff0f0;
19704 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
19705 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19708 case BFD_RELOC_ARM_T32_OFFSET_U8
:
19709 if (value
< 0 || value
> 1020 || value
% 4 != 0)
19710 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19711 _("bad immediate value for offset (%ld)"), (long) value
);
19714 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
19716 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
19719 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19720 /* This is a complicated relocation used for all varieties of Thumb32
19721 load/store instruction with immediate offset:
19723 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
19724 *4, optional writeback(W)
19725 (doubleword load/store)
19727 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
19728 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
19729 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
19730 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
19731 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
19733 Uppercase letters indicate bits that are already encoded at
19734 this point. Lowercase letters are our problem. For the
19735 second block of instructions, the secondary opcode nybble
19736 (bits 8..11) is present, and bit 23 is zero, even if this is
19737 a PC-relative operation. */
19738 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19740 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
19742 if ((newval
& 0xf0000000) == 0xe0000000)
19744 /* Doubleword load/store: 8-bit offset, scaled by 4. */
19746 newval
|= (1 << 23);
19749 if (value
% 4 != 0)
19751 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19752 _("offset not a multiple of 4"));
19758 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19759 _("offset out of range"));
19764 else if ((newval
& 0x000f0000) == 0x000f0000)
19766 /* PC-relative, 12-bit offset. */
19768 newval
|= (1 << 23);
19773 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19774 _("offset out of range"));
19779 else if ((newval
& 0x00000100) == 0x00000100)
19781 /* Writeback: 8-bit, +/- offset. */
19783 newval
|= (1 << 9);
19788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19789 _("offset out of range"));
19794 else if ((newval
& 0x00000f00) == 0x00000e00)
19796 /* T-instruction: positive 8-bit offset. */
19797 if (value
< 0 || value
> 0xff)
19799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19800 _("offset out of range"));
19808 /* Positive 12-bit or negative 8-bit offset. */
19812 newval
|= (1 << 23);
19822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19823 _("offset out of range"));
19830 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
19831 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
19834 case BFD_RELOC_ARM_SHIFT_IMM
:
19835 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19836 if (((unsigned long) value
) > 32
19838 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
19840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19841 _("shift expression is too large"));
19846 /* Shifts of zero must be done as lsl. */
19848 else if (value
== 32)
19850 newval
&= 0xfffff07f;
19851 newval
|= (value
& 0x1f) << 7;
19852 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19855 case BFD_RELOC_ARM_T32_IMMEDIATE
:
19856 case BFD_RELOC_ARM_T32_ADD_IMM
:
19857 case BFD_RELOC_ARM_T32_IMM12
:
19858 case BFD_RELOC_ARM_T32_ADD_PC12
:
19859 /* We claim that this fixup has been processed here,
19860 even if in fact we generate an error because we do
19861 not have a reloc for it, so tc_gen_reloc will reject it. */
19865 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19867 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19868 _("undefined symbol %s used as an immediate value"),
19869 S_GET_NAME (fixP
->fx_addsy
));
19873 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19875 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
19878 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19879 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19881 newimm
= encode_thumb32_immediate (value
);
19882 if (newimm
== (unsigned int) FAIL
)
19883 newimm
= thumb32_negate_data_op (&newval
, value
);
19885 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
19886 && newimm
== (unsigned int) FAIL
)
19888 /* Turn add/sum into addw/subw. */
19889 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19890 newval
= (newval
& 0xfeffffff) | 0x02000000;
19892 /* 12 bit immediate for addw/subw. */
19896 newval
^= 0x00a00000;
19899 newimm
= (unsigned int) FAIL
;
19904 if (newimm
== (unsigned int)FAIL
)
19906 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19907 _("invalid constant (%lx) after fixup"),
19908 (unsigned long) value
);
19912 newval
|= (newimm
& 0x800) << 15;
19913 newval
|= (newimm
& 0x700) << 4;
19914 newval
|= (newimm
& 0x0ff);
19916 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
19917 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
19920 case BFD_RELOC_ARM_SMC
:
19921 if (((unsigned long) value
) > 0xffff)
19922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19923 _("invalid smc expression"));
19924 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19925 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
19926 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19929 case BFD_RELOC_ARM_SWI
:
19930 if (fixP
->tc_fix_data
!= 0)
19932 if (((unsigned long) value
) > 0xff)
19933 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19934 _("invalid swi expression"));
19935 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19937 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19941 if (((unsigned long) value
) > 0x00ffffff)
19942 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19943 _("invalid swi expression"));
19944 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19946 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19950 case BFD_RELOC_ARM_MULTI
:
19951 if (((unsigned long) value
) > 0xffff)
19952 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19953 _("invalid expression in load/store multiple"));
19954 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
19955 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19959 case BFD_RELOC_ARM_PCREL_CALL
:
19961 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19963 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19964 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19965 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19966 /* Flip the bl to blx. This is a simple flip
19967 bit here because we generate PCREL_CALL for
19968 unconditional bls. */
19970 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19971 newval
= newval
| 0x10000000;
19972 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19978 goto arm_branch_common
;
19980 case BFD_RELOC_ARM_PCREL_JUMP
:
19981 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19983 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19984 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19985 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19987 /* This would map to a bl<cond>, b<cond>,
19988 b<always> to a Thumb function. We
19989 need to force a relocation for this particular
19991 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19995 case BFD_RELOC_ARM_PLT32
:
19997 case BFD_RELOC_ARM_PCREL_BRANCH
:
19999 goto arm_branch_common
;
20001 case BFD_RELOC_ARM_PCREL_BLX
:
20004 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20006 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20007 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20008 && ARM_IS_FUNC (fixP
->fx_addsy
))
20010 /* Flip the blx to a bl and warn. */
20011 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20012 newval
= 0xeb000000;
20013 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20014 _("blx to '%s' an ARM ISA state function changed to bl"),
20016 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20022 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20023 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20027 /* We are going to store value (shifted right by two) in the
20028 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20029 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20030 also be be clear. */
20032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20033 _("misaligned branch destination"));
20034 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20035 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20036 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20037 _("branch out of range"));
20039 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20041 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20042 newval
|= (value
>> 2) & 0x00ffffff;
20043 /* Set the H bit on BLX instructions. */
20047 newval
|= 0x01000000;
20049 newval
&= ~0x01000000;
20051 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20055 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20056 /* CBZ can only branch forward. */
20058 /* Attempts to use CBZ to branch to the next instruction
20059 (which, strictly speaking, are prohibited) will be turned into
20062 FIXME: It may be better to remove the instruction completely and
20063 perform relaxation. */
20066 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20067 newval
= 0xbf00; /* NOP encoding T1 */
20068 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20073 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20074 _("branch out of range"));
20076 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20078 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20079 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20080 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20085 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20086 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20087 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20088 _("branch out of range"));
20090 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20092 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20093 newval
|= (value
& 0x1ff) >> 1;
20094 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20098 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20099 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20100 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20101 _("branch out of range"));
20103 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20105 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20106 newval
|= (value
& 0xfff) >> 1;
20107 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20111 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20113 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20114 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20115 && S_IS_DEFINED (fixP
->fx_addsy
)
20116 && ARM_IS_FUNC (fixP
->fx_addsy
)
20117 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20119 /* Force a relocation for a branch 20 bits wide. */
20122 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20123 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20124 _("conditional branch out of range"));
20126 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20129 addressT S
, J1
, J2
, lo
, hi
;
20131 S
= (value
& 0x00100000) >> 20;
20132 J2
= (value
& 0x00080000) >> 19;
20133 J1
= (value
& 0x00040000) >> 18;
20134 hi
= (value
& 0x0003f000) >> 12;
20135 lo
= (value
& 0x00000ffe) >> 1;
20137 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20138 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20139 newval
|= (S
<< 10) | hi
;
20140 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20141 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20142 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20146 case BFD_RELOC_THUMB_PCREL_BLX
:
20148 /* If there is a blx from a thumb state function to
20149 another thumb function flip this to a bl and warn
20153 && S_IS_DEFINED (fixP
->fx_addsy
)
20154 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20155 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20156 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20158 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20159 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20160 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20162 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20163 newval
= newval
| 0x1000;
20164 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20165 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20170 goto thumb_bl_common
;
20172 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20174 /* A bl from Thumb state ISA to an internal ARM state function
20175 is converted to a blx. */
20177 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20178 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20179 && S_IS_DEFINED (fixP
->fx_addsy
)
20180 && ARM_IS_FUNC (fixP
->fx_addsy
)
20181 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20183 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20184 newval
= newval
& ~0x1000;
20185 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20186 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20193 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20194 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20195 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20198 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20199 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20200 _("branch out of range"));
20202 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20203 /* For a BLX instruction, make sure that the relocation is rounded up
20204 to a word boundary. This follows the semantics of the instruction
20205 which specifies that bit 1 of the target address will come from bit
20206 1 of the base address. */
20207 value
= (value
+ 1) & ~ 1;
20209 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20213 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20214 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20215 newval
|= (value
& 0x7fffff) >> 12;
20216 newval2
|= (value
& 0xfff) >> 1;
20217 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20218 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20222 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20223 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20224 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20225 _("branch out of range"));
20227 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20230 addressT S
, I1
, I2
, lo
, hi
;
20232 S
= (value
& 0x01000000) >> 24;
20233 I1
= (value
& 0x00800000) >> 23;
20234 I2
= (value
& 0x00400000) >> 22;
20235 hi
= (value
& 0x003ff000) >> 12;
20236 lo
= (value
& 0x00000ffe) >> 1;
20241 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20242 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20243 newval
|= (S
<< 10) | hi
;
20244 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
20245 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20246 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20251 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20252 md_number_to_chars (buf
, value
, 1);
20256 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20257 md_number_to_chars (buf
, value
, 2);
20261 case BFD_RELOC_ARM_TLS_GD32
:
20262 case BFD_RELOC_ARM_TLS_LE32
:
20263 case BFD_RELOC_ARM_TLS_IE32
:
20264 case BFD_RELOC_ARM_TLS_LDM32
:
20265 case BFD_RELOC_ARM_TLS_LDO32
:
20266 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20269 case BFD_RELOC_ARM_GOT32
:
20270 case BFD_RELOC_ARM_GOTOFF
:
20271 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20272 md_number_to_chars (buf
, 0, 4);
20275 case BFD_RELOC_ARM_TARGET2
:
20276 /* TARGET2 is not partial-inplace, so we need to write the
20277 addend here for REL targets, because it won't be written out
20278 during reloc processing later. */
20279 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20280 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20284 case BFD_RELOC_RVA
:
20286 case BFD_RELOC_ARM_TARGET1
:
20287 case BFD_RELOC_ARM_ROSEGREL32
:
20288 case BFD_RELOC_ARM_SBREL32
:
20289 case BFD_RELOC_32_PCREL
:
20291 case BFD_RELOC_32_SECREL
:
20293 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20295 /* For WinCE we only do this for pcrel fixups. */
20296 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20298 md_number_to_chars (buf
, value
, 4);
20302 case BFD_RELOC_ARM_PREL31
:
20303 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20305 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20306 if ((value
^ (value
>> 1)) & 0x40000000)
20308 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20309 _("rel31 relocation overflow"));
20311 newval
|= value
& 0x7fffffff;
20312 md_number_to_chars (buf
, newval
, 4);
20317 case BFD_RELOC_ARM_CP_OFF_IMM
:
20318 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20319 if (value
< -1023 || value
> 1023 || (value
& 3))
20320 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20321 _("co-processor offset out of range"));
20326 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20327 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20328 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20330 newval
= get_thumb32_insn (buf
);
20331 newval
&= 0xff7fff00;
20332 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20333 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20334 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20335 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20337 put_thumb32_insn (buf
, newval
);
20340 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20341 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20342 if (value
< -255 || value
> 255)
20343 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20344 _("co-processor offset out of range"));
20346 goto cp_off_common
;
20348 case BFD_RELOC_ARM_THUMB_OFFSET
:
20349 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20350 /* Exactly what ranges, and where the offset is inserted depends
20351 on the type of instruction, we can establish this from the
20353 switch (newval
>> 12)
20355 case 4: /* PC load. */
20356 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20357 forced to zero for these loads; md_pcrel_from has already
20358 compensated for this. */
20360 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20361 _("invalid offset, target not word aligned (0x%08lX)"),
20362 (((unsigned long) fixP
->fx_frag
->fr_address
20363 + (unsigned long) fixP
->fx_where
) & ~3)
20364 + (unsigned long) value
);
20366 if (value
& ~0x3fc)
20367 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20368 _("invalid offset, value too big (0x%08lX)"),
20371 newval
|= value
>> 2;
20374 case 9: /* SP load/store. */
20375 if (value
& ~0x3fc)
20376 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20377 _("invalid offset, value too big (0x%08lX)"),
20379 newval
|= value
>> 2;
20382 case 6: /* Word load/store. */
20384 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20385 _("invalid offset, value too big (0x%08lX)"),
20387 newval
|= value
<< 4; /* 6 - 2. */
20390 case 7: /* Byte load/store. */
20392 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20393 _("invalid offset, value too big (0x%08lX)"),
20395 newval
|= value
<< 6;
20398 case 8: /* Halfword load/store. */
20400 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20401 _("invalid offset, value too big (0x%08lX)"),
20403 newval
|= value
<< 5; /* 6 - 1. */
20407 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20408 "Unable to process relocation for thumb opcode: %lx",
20409 (unsigned long) newval
);
20412 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20415 case BFD_RELOC_ARM_THUMB_ADD
:
20416 /* This is a complicated relocation, since we use it for all of
20417 the following immediate relocations:
20421 9bit ADD/SUB SP word-aligned
20422 10bit ADD PC/SP word-aligned
20424 The type of instruction being processed is encoded in the
20431 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20433 int rd
= (newval
>> 4) & 0xf;
20434 int rs
= newval
& 0xf;
20435 int subtract
= !!(newval
& 0x8000);
20437 /* Check for HI regs, only very restricted cases allowed:
20438 Adjusting SP, and using PC or SP to get an address. */
20439 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20440 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20442 _("invalid Hi register with immediate"));
20444 /* If value is negative, choose the opposite instruction. */
20448 subtract
= !subtract
;
20450 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20451 _("immediate value out of range"));
20456 if (value
& ~0x1fc)
20457 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20458 _("invalid immediate for stack address calculation"));
20459 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20460 newval
|= value
>> 2;
20462 else if (rs
== REG_PC
|| rs
== REG_SP
)
20464 if (subtract
|| value
& ~0x3fc)
20465 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20466 _("invalid immediate for address calculation (value = 0x%08lX)"),
20467 (unsigned long) value
);
20468 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20470 newval
|= value
>> 2;
20475 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20476 _("immediate value out of range"));
20477 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20478 newval
|= (rd
<< 8) | value
;
20483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20484 _("immediate value out of range"));
20485 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20486 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20489 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20492 case BFD_RELOC_ARM_THUMB_IMM
:
20493 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20494 if (value
< 0 || value
> 255)
20495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20496 _("invalid immediate: %ld is out of range"),
20499 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20502 case BFD_RELOC_ARM_THUMB_SHIFT
:
20503 /* 5bit shift value (0..32). LSL cannot take 32. */
20504 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20505 temp
= newval
& 0xf800;
20506 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20507 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20508 _("invalid shift value: %ld"), (long) value
);
20509 /* Shifts of zero must be encoded as LSL. */
20511 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20512 /* Shifts of 32 are encoded as zero. */
20513 else if (value
== 32)
20515 newval
|= value
<< 6;
20516 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20519 case BFD_RELOC_VTABLE_INHERIT
:
20520 case BFD_RELOC_VTABLE_ENTRY
:
20524 case BFD_RELOC_ARM_MOVW
:
20525 case BFD_RELOC_ARM_MOVT
:
20526 case BFD_RELOC_ARM_THUMB_MOVW
:
20527 case BFD_RELOC_ARM_THUMB_MOVT
:
20528 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20530 /* REL format relocations are limited to a 16-bit addend. */
20531 if (!fixP
->fx_done
)
20533 if (value
< -0x8000 || value
> 0x7fff)
20534 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20535 _("offset out of range"));
20537 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20538 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20543 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20544 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20546 newval
= get_thumb32_insn (buf
);
20547 newval
&= 0xfbf08f00;
20548 newval
|= (value
& 0xf000) << 4;
20549 newval
|= (value
& 0x0800) << 15;
20550 newval
|= (value
& 0x0700) << 4;
20551 newval
|= (value
& 0x00ff);
20552 put_thumb32_insn (buf
, newval
);
20556 newval
= md_chars_to_number (buf
, 4);
20557 newval
&= 0xfff0f000;
20558 newval
|= value
& 0x0fff;
20559 newval
|= (value
& 0xf000) << 4;
20560 md_number_to_chars (buf
, newval
, 4);
20565 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20566 case BFD_RELOC_ARM_ALU_PC_G0
:
20567 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20568 case BFD_RELOC_ARM_ALU_PC_G1
:
20569 case BFD_RELOC_ARM_ALU_PC_G2
:
20570 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20571 case BFD_RELOC_ARM_ALU_SB_G0
:
20572 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20573 case BFD_RELOC_ARM_ALU_SB_G1
:
20574 case BFD_RELOC_ARM_ALU_SB_G2
:
20575 gas_assert (!fixP
->fx_done
);
20576 if (!seg
->use_rela_p
)
20579 bfd_vma encoded_addend
;
20580 bfd_vma addend_abs
= abs (value
);
20582 /* Check that the absolute value of the addend can be
20583 expressed as an 8-bit constant plus a rotation. */
20584 encoded_addend
= encode_arm_immediate (addend_abs
);
20585 if (encoded_addend
== (unsigned int) FAIL
)
20586 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20587 _("the offset 0x%08lX is not representable"),
20588 (unsigned long) addend_abs
);
20590 /* Extract the instruction. */
20591 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20593 /* If the addend is positive, use an ADD instruction.
20594 Otherwise use a SUB. Take care not to destroy the S bit. */
20595 insn
&= 0xff1fffff;
20601 /* Place the encoded addend into the first 12 bits of the
20603 insn
&= 0xfffff000;
20604 insn
|= encoded_addend
;
20606 /* Update the instruction. */
20607 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20611 case BFD_RELOC_ARM_LDR_PC_G0
:
20612 case BFD_RELOC_ARM_LDR_PC_G1
:
20613 case BFD_RELOC_ARM_LDR_PC_G2
:
20614 case BFD_RELOC_ARM_LDR_SB_G0
:
20615 case BFD_RELOC_ARM_LDR_SB_G1
:
20616 case BFD_RELOC_ARM_LDR_SB_G2
:
20617 gas_assert (!fixP
->fx_done
);
20618 if (!seg
->use_rela_p
)
20621 bfd_vma addend_abs
= abs (value
);
20623 /* Check that the absolute value of the addend can be
20624 encoded in 12 bits. */
20625 if (addend_abs
>= 0x1000)
20626 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20627 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20628 (unsigned long) addend_abs
);
20630 /* Extract the instruction. */
20631 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20633 /* If the addend is negative, clear bit 23 of the instruction.
20634 Otherwise set it. */
20636 insn
&= ~(1 << 23);
20640 /* Place the absolute value of the addend into the first 12 bits
20641 of the instruction. */
20642 insn
&= 0xfffff000;
20643 insn
|= addend_abs
;
20645 /* Update the instruction. */
20646 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20650 case BFD_RELOC_ARM_LDRS_PC_G0
:
20651 case BFD_RELOC_ARM_LDRS_PC_G1
:
20652 case BFD_RELOC_ARM_LDRS_PC_G2
:
20653 case BFD_RELOC_ARM_LDRS_SB_G0
:
20654 case BFD_RELOC_ARM_LDRS_SB_G1
:
20655 case BFD_RELOC_ARM_LDRS_SB_G2
:
20656 gas_assert (!fixP
->fx_done
);
20657 if (!seg
->use_rela_p
)
20660 bfd_vma addend_abs
= abs (value
);
20662 /* Check that the absolute value of the addend can be
20663 encoded in 8 bits. */
20664 if (addend_abs
>= 0x100)
20665 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20666 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
20667 (unsigned long) addend_abs
);
20669 /* Extract the instruction. */
20670 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20672 /* If the addend is negative, clear bit 23 of the instruction.
20673 Otherwise set it. */
20675 insn
&= ~(1 << 23);
20679 /* Place the first four bits of the absolute value of the addend
20680 into the first 4 bits of the instruction, and the remaining
20681 four into bits 8 .. 11. */
20682 insn
&= 0xfffff0f0;
20683 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
20685 /* Update the instruction. */
20686 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20690 case BFD_RELOC_ARM_LDC_PC_G0
:
20691 case BFD_RELOC_ARM_LDC_PC_G1
:
20692 case BFD_RELOC_ARM_LDC_PC_G2
:
20693 case BFD_RELOC_ARM_LDC_SB_G0
:
20694 case BFD_RELOC_ARM_LDC_SB_G1
:
20695 case BFD_RELOC_ARM_LDC_SB_G2
:
20696 gas_assert (!fixP
->fx_done
);
20697 if (!seg
->use_rela_p
)
20700 bfd_vma addend_abs
= abs (value
);
20702 /* Check that the absolute value of the addend is a multiple of
20703 four and, when divided by four, fits in 8 bits. */
20704 if (addend_abs
& 0x3)
20705 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20706 _("bad offset 0x%08lX (must be word-aligned)"),
20707 (unsigned long) addend_abs
);
20709 if ((addend_abs
>> 2) > 0xff)
20710 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20711 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
20712 (unsigned long) addend_abs
);
20714 /* Extract the instruction. */
20715 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20717 /* If the addend is negative, clear bit 23 of the instruction.
20718 Otherwise set it. */
20720 insn
&= ~(1 << 23);
20724 /* Place the addend (divided by four) into the first eight
20725 bits of the instruction. */
20726 insn
&= 0xfffffff0;
20727 insn
|= addend_abs
>> 2;
20729 /* Update the instruction. */
20730 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20734 case BFD_RELOC_ARM_V4BX
:
20735 /* This will need to go in the object file. */
20739 case BFD_RELOC_UNUSED
:
20741 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20742 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
20746 /* Translate internal representation of relocation info to BFD target
20750 tc_gen_reloc (asection
*section
, fixS
*fixp
)
20753 bfd_reloc_code_real_type code
;
20755 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
20757 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
20758 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
20759 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
20761 if (fixp
->fx_pcrel
)
20763 if (section
->use_rela_p
)
20764 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
20766 fixp
->fx_offset
= reloc
->address
;
20768 reloc
->addend
= fixp
->fx_offset
;
20770 switch (fixp
->fx_r_type
)
20773 if (fixp
->fx_pcrel
)
20775 code
= BFD_RELOC_8_PCREL
;
20780 if (fixp
->fx_pcrel
)
20782 code
= BFD_RELOC_16_PCREL
;
20787 if (fixp
->fx_pcrel
)
20789 code
= BFD_RELOC_32_PCREL
;
20793 case BFD_RELOC_ARM_MOVW
:
20794 if (fixp
->fx_pcrel
)
20796 code
= BFD_RELOC_ARM_MOVW_PCREL
;
20800 case BFD_RELOC_ARM_MOVT
:
20801 if (fixp
->fx_pcrel
)
20803 code
= BFD_RELOC_ARM_MOVT_PCREL
;
20807 case BFD_RELOC_ARM_THUMB_MOVW
:
20808 if (fixp
->fx_pcrel
)
20810 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
20814 case BFD_RELOC_ARM_THUMB_MOVT
:
20815 if (fixp
->fx_pcrel
)
20817 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
20821 case BFD_RELOC_NONE
:
20822 case BFD_RELOC_ARM_PCREL_BRANCH
:
20823 case BFD_RELOC_ARM_PCREL_BLX
:
20824 case BFD_RELOC_RVA
:
20825 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
20826 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
20827 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
20828 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20829 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20830 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20831 case BFD_RELOC_VTABLE_ENTRY
:
20832 case BFD_RELOC_VTABLE_INHERIT
:
20834 case BFD_RELOC_32_SECREL
:
20836 code
= fixp
->fx_r_type
;
20839 case BFD_RELOC_THUMB_PCREL_BLX
:
20841 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20842 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20845 code
= BFD_RELOC_THUMB_PCREL_BLX
;
20848 case BFD_RELOC_ARM_LITERAL
:
20849 case BFD_RELOC_ARM_HWLITERAL
:
20850 /* If this is called then the a literal has
20851 been referenced across a section boundary. */
20852 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20853 _("literal referenced across section boundary"));
20857 case BFD_RELOC_ARM_GOT32
:
20858 case BFD_RELOC_ARM_GOTOFF
:
20859 case BFD_RELOC_ARM_PLT32
:
20860 case BFD_RELOC_ARM_TARGET1
:
20861 case BFD_RELOC_ARM_ROSEGREL32
:
20862 case BFD_RELOC_ARM_SBREL32
:
20863 case BFD_RELOC_ARM_PREL31
:
20864 case BFD_RELOC_ARM_TARGET2
:
20865 case BFD_RELOC_ARM_TLS_LE32
:
20866 case BFD_RELOC_ARM_TLS_LDO32
:
20867 case BFD_RELOC_ARM_PCREL_CALL
:
20868 case BFD_RELOC_ARM_PCREL_JUMP
:
20869 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20870 case BFD_RELOC_ARM_ALU_PC_G0
:
20871 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20872 case BFD_RELOC_ARM_ALU_PC_G1
:
20873 case BFD_RELOC_ARM_ALU_PC_G2
:
20874 case BFD_RELOC_ARM_LDR_PC_G0
:
20875 case BFD_RELOC_ARM_LDR_PC_G1
:
20876 case BFD_RELOC_ARM_LDR_PC_G2
:
20877 case BFD_RELOC_ARM_LDRS_PC_G0
:
20878 case BFD_RELOC_ARM_LDRS_PC_G1
:
20879 case BFD_RELOC_ARM_LDRS_PC_G2
:
20880 case BFD_RELOC_ARM_LDC_PC_G0
:
20881 case BFD_RELOC_ARM_LDC_PC_G1
:
20882 case BFD_RELOC_ARM_LDC_PC_G2
:
20883 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20884 case BFD_RELOC_ARM_ALU_SB_G0
:
20885 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20886 case BFD_RELOC_ARM_ALU_SB_G1
:
20887 case BFD_RELOC_ARM_ALU_SB_G2
:
20888 case BFD_RELOC_ARM_LDR_SB_G0
:
20889 case BFD_RELOC_ARM_LDR_SB_G1
:
20890 case BFD_RELOC_ARM_LDR_SB_G2
:
20891 case BFD_RELOC_ARM_LDRS_SB_G0
:
20892 case BFD_RELOC_ARM_LDRS_SB_G1
:
20893 case BFD_RELOC_ARM_LDRS_SB_G2
:
20894 case BFD_RELOC_ARM_LDC_SB_G0
:
20895 case BFD_RELOC_ARM_LDC_SB_G1
:
20896 case BFD_RELOC_ARM_LDC_SB_G2
:
20897 case BFD_RELOC_ARM_V4BX
:
20898 code
= fixp
->fx_r_type
;
20901 case BFD_RELOC_ARM_TLS_GD32
:
20902 case BFD_RELOC_ARM_TLS_IE32
:
20903 case BFD_RELOC_ARM_TLS_LDM32
:
20904 /* BFD will include the symbol's address in the addend.
20905 But we don't want that, so subtract it out again here. */
20906 if (!S_IS_COMMON (fixp
->fx_addsy
))
20907 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
20908 code
= fixp
->fx_r_type
;
20912 case BFD_RELOC_ARM_IMMEDIATE
:
20913 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20914 _("internal relocation (type: IMMEDIATE) not fixed up"));
20917 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20918 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20919 _("ADRL used for a symbol not defined in the same file"));
20922 case BFD_RELOC_ARM_OFFSET_IMM
:
20923 if (section
->use_rela_p
)
20925 code
= fixp
->fx_r_type
;
20929 if (fixp
->fx_addsy
!= NULL
20930 && !S_IS_DEFINED (fixp
->fx_addsy
)
20931 && S_IS_LOCAL (fixp
->fx_addsy
))
20933 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20934 _("undefined local label `%s'"),
20935 S_GET_NAME (fixp
->fx_addsy
));
20939 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20940 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
20947 switch (fixp
->fx_r_type
)
20949 case BFD_RELOC_NONE
: type
= "NONE"; break;
20950 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
20951 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
20952 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
20953 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
20954 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
20955 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
20956 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
20957 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
20958 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
20959 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
20960 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
20961 default: type
= _("<unknown>"); break;
20963 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20964 _("cannot represent %s relocation in this object file format"),
20971 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
20973 && fixp
->fx_addsy
== GOT_symbol
)
20975 code
= BFD_RELOC_ARM_GOTPC
;
20976 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
20980 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
20982 if (reloc
->howto
== NULL
)
20984 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20985 _("cannot represent %s relocation in this object file format"),
20986 bfd_get_reloc_code_name (code
));
20990 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
20991 vtable entry to be used in the relocation's section offset. */
20992 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
20993 reloc
->address
= fixp
->fx_offset
;
20998 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21001 cons_fix_new_arm (fragS
* frag
,
21006 bfd_reloc_code_real_type type
;
21010 FIXME: @@ Should look at CPU word size. */
21014 type
= BFD_RELOC_8
;
21017 type
= BFD_RELOC_16
;
21021 type
= BFD_RELOC_32
;
21024 type
= BFD_RELOC_64
;
21029 if (exp
->X_op
== O_secrel
)
21031 exp
->X_op
= O_symbol
;
21032 type
= BFD_RELOC_32_SECREL
;
21036 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21039 #if defined (OBJ_COFF)
21041 arm_validate_fix (fixS
* fixP
)
21043 /* If the destination of the branch is a defined symbol which does not have
21044 the THUMB_FUNC attribute, then we must be calling a function which has
21045 the (interfacearm) attribute. We look for the Thumb entry point to that
21046 function and change the branch to refer to that function instead. */
21047 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21048 && fixP
->fx_addsy
!= NULL
21049 && S_IS_DEFINED (fixP
->fx_addsy
)
21050 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21052 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21059 arm_force_relocation (struct fix
* fixp
)
21061 #if defined (OBJ_COFF) && defined (TE_PE)
21062 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21066 /* In case we have a call or a branch to a function in ARM ISA mode from
21067 a thumb function or vice-versa force the relocation. These relocations
21068 are cleared off for some cores that might have blx and simple transformations
21072 switch (fixp
->fx_r_type
)
21074 case BFD_RELOC_ARM_PCREL_JUMP
:
21075 case BFD_RELOC_ARM_PCREL_CALL
:
21076 case BFD_RELOC_THUMB_PCREL_BLX
:
21077 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21081 case BFD_RELOC_ARM_PCREL_BLX
:
21082 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21083 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21084 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21085 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21094 /* Resolve these relocations even if the symbol is extern or weak. */
21095 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21096 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21097 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21098 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21099 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21100 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21101 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21104 /* Always leave these relocations for the linker. */
21105 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21106 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21107 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21110 /* Always generate relocations against function symbols. */
21111 if (fixp
->fx_r_type
== BFD_RELOC_32
21113 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21116 return generic_force_reloc (fixp
);
21119 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21120 /* Relocations against function names must be left unadjusted,
21121 so that the linker can use this information to generate interworking
21122 stubs. The MIPS version of this function
21123 also prevents relocations that are mips-16 specific, but I do not
21124 know why it does this.
21127 There is one other problem that ought to be addressed here, but
21128 which currently is not: Taking the address of a label (rather
21129 than a function) and then later jumping to that address. Such
21130 addresses also ought to have their bottom bit set (assuming that
21131 they reside in Thumb code), but at the moment they will not. */
21134 arm_fix_adjustable (fixS
* fixP
)
21136 if (fixP
->fx_addsy
== NULL
)
21139 /* Preserve relocations against symbols with function type. */
21140 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21143 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21144 && fixP
->fx_subsy
== NULL
)
21147 /* We need the symbol name for the VTABLE entries. */
21148 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21149 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21152 /* Don't allow symbols to be discarded on GOT related relocs. */
21153 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21154 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21155 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21156 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21157 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21158 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21159 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21160 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21161 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21164 /* Similarly for group relocations. */
21165 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21166 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21167 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21170 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21171 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21172 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21173 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21174 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21175 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21176 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21177 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21178 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21183 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21188 elf32_arm_target_format (void)
21191 return (target_big_endian
21192 ? "elf32-bigarm-symbian"
21193 : "elf32-littlearm-symbian");
21194 #elif defined (TE_VXWORKS)
21195 return (target_big_endian
21196 ? "elf32-bigarm-vxworks"
21197 : "elf32-littlearm-vxworks");
21199 if (target_big_endian
)
21200 return "elf32-bigarm";
21202 return "elf32-littlearm";
21207 armelf_frob_symbol (symbolS
* symp
,
21210 elf_frob_symbol (symp
, puntp
);
21214 /* MD interface: Finalization. */
21219 literal_pool
* pool
;
21221 /* Ensure that all the IT blocks are properly closed. */
21222 check_it_blocks_finished ();
21224 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21226 /* Put it at the end of the relevant section. */
21227 subseg_set (pool
->section
, pool
->sub_section
);
21229 arm_elf_change_section ();
21236 /* Remove any excess mapping symbols generated for alignment frags in
21237 SEC. We may have created a mapping symbol before a zero byte
21238 alignment; remove it if there's a mapping symbol after the
21241 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21242 void *dummy ATTRIBUTE_UNUSED
)
21244 segment_info_type
*seginfo
= seg_info (sec
);
21247 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21250 for (fragp
= seginfo
->frchainP
->frch_root
;
21252 fragp
= fragp
->fr_next
)
21254 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21255 fragS
*next
= fragp
->fr_next
;
21257 /* Variable-sized frags have been converted to fixed size by
21258 this point. But if this was variable-sized to start with,
21259 there will be a fixed-size frag after it. So don't handle
21261 if (sym
== NULL
|| next
== NULL
)
21264 if (S_GET_VALUE (sym
) < next
->fr_address
)
21265 /* Not at the end of this frag. */
21267 know (S_GET_VALUE (sym
) == next
->fr_address
);
21271 if (next
->tc_frag_data
.first_map
!= NULL
)
21273 /* Next frag starts with a mapping symbol. Discard this
21275 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21279 if (next
->fr_next
== NULL
)
21281 /* This mapping symbol is at the end of the section. Discard
21283 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21284 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21288 /* As long as we have empty frags without any mapping symbols,
21290 /* If the next frag is non-empty and does not start with a
21291 mapping symbol, then this mapping symbol is required. */
21292 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21295 next
= next
->fr_next
;
21297 while (next
!= NULL
);
21302 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21306 arm_adjust_symtab (void)
21311 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21313 if (ARM_IS_THUMB (sym
))
21315 if (THUMB_IS_FUNC (sym
))
21317 /* Mark the symbol as a Thumb function. */
21318 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21319 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21320 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21322 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21323 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21325 as_bad (_("%s: unexpected function type: %d"),
21326 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21328 else switch (S_GET_STORAGE_CLASS (sym
))
21331 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21334 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21337 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21345 if (ARM_IS_INTERWORK (sym
))
21346 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21353 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21355 if (ARM_IS_THUMB (sym
))
21357 elf_symbol_type
* elf_sym
;
21359 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21360 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21362 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21363 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21365 /* If it's a .thumb_func, declare it as so,
21366 otherwise tag label as .code 16. */
21367 if (THUMB_IS_FUNC (sym
))
21368 elf_sym
->internal_elf_sym
.st_info
=
21369 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21370 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21371 elf_sym
->internal_elf_sym
.st_info
=
21372 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21377 /* Remove any overlapping mapping symbols generated by alignment frags. */
21378 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21382 /* MD interface: Initialization. */
21385 set_constant_flonums (void)
21389 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21390 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21394 /* Auto-select Thumb mode if it's the only available instruction set for the
21395 given architecture. */
21398 autoselect_thumb_from_cpu_variant (void)
21400 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21401 opcode_select (16);
21410 if ( (arm_ops_hsh
= hash_new ()) == NULL
21411 || (arm_cond_hsh
= hash_new ()) == NULL
21412 || (arm_shift_hsh
= hash_new ()) == NULL
21413 || (arm_psr_hsh
= hash_new ()) == NULL
21414 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21415 || (arm_reg_hsh
= hash_new ()) == NULL
21416 || (arm_reloc_hsh
= hash_new ()) == NULL
21417 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21418 as_fatal (_("virtual memory exhausted"));
21420 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21421 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21422 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21423 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21424 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21425 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21426 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21427 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21428 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21429 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21430 (void *) (v7m_psrs
+ i
));
21431 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21432 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21434 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21436 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21437 (void *) (barrier_opt_names
+ i
));
21439 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21440 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21443 set_constant_flonums ();
21445 /* Set the cpu variant based on the command-line options. We prefer
21446 -mcpu= over -march= if both are set (as for GCC); and we prefer
21447 -mfpu= over any other way of setting the floating point unit.
21448 Use of legacy options with new options are faulted. */
21451 if (mcpu_cpu_opt
|| march_cpu_opt
)
21452 as_bad (_("use of old and new-style options to set CPU type"));
21454 mcpu_cpu_opt
= legacy_cpu
;
21456 else if (!mcpu_cpu_opt
)
21457 mcpu_cpu_opt
= march_cpu_opt
;
21462 as_bad (_("use of old and new-style options to set FPU type"));
21464 mfpu_opt
= legacy_fpu
;
21466 else if (!mfpu_opt
)
21468 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21469 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21470 /* Some environments specify a default FPU. If they don't, infer it
21471 from the processor. */
21473 mfpu_opt
= mcpu_fpu_opt
;
21475 mfpu_opt
= march_fpu_opt
;
21477 mfpu_opt
= &fpu_default
;
21483 if (mcpu_cpu_opt
!= NULL
)
21484 mfpu_opt
= &fpu_default
;
21485 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21486 mfpu_opt
= &fpu_arch_vfp_v2
;
21488 mfpu_opt
= &fpu_arch_fpa
;
21494 mcpu_cpu_opt
= &cpu_default
;
21495 selected_cpu
= cpu_default
;
21499 selected_cpu
= *mcpu_cpu_opt
;
21501 mcpu_cpu_opt
= &arm_arch_any
;
21504 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21506 autoselect_thumb_from_cpu_variant ();
21508 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21510 #if defined OBJ_COFF || defined OBJ_ELF
21512 unsigned int flags
= 0;
21514 #if defined OBJ_ELF
21515 flags
= meabi_flags
;
21517 switch (meabi_flags
)
21519 case EF_ARM_EABI_UNKNOWN
:
21521 /* Set the flags in the private structure. */
21522 if (uses_apcs_26
) flags
|= F_APCS26
;
21523 if (support_interwork
) flags
|= F_INTERWORK
;
21524 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21525 if (pic_code
) flags
|= F_PIC
;
21526 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21527 flags
|= F_SOFT_FLOAT
;
21529 switch (mfloat_abi_opt
)
21531 case ARM_FLOAT_ABI_SOFT
:
21532 case ARM_FLOAT_ABI_SOFTFP
:
21533 flags
|= F_SOFT_FLOAT
;
21536 case ARM_FLOAT_ABI_HARD
:
21537 if (flags
& F_SOFT_FLOAT
)
21538 as_bad (_("hard-float conflicts with specified fpu"));
21542 /* Using pure-endian doubles (even if soft-float). */
21543 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21544 flags
|= F_VFP_FLOAT
;
21546 #if defined OBJ_ELF
21547 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21548 flags
|= EF_ARM_MAVERICK_FLOAT
;
21551 case EF_ARM_EABI_VER4
:
21552 case EF_ARM_EABI_VER5
:
21553 /* No additional flags to set. */
21560 bfd_set_private_flags (stdoutput
, flags
);
21562 /* We have run out flags in the COFF header to encode the
21563 status of ATPCS support, so instead we create a dummy,
21564 empty, debug section called .arm.atpcs. */
21569 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21573 bfd_set_section_flags
21574 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21575 bfd_set_section_size (stdoutput
, sec
, 0);
21576 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21582 /* Record the CPU type as well. */
21583 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21584 mach
= bfd_mach_arm_iWMMXt2
;
21585 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21586 mach
= bfd_mach_arm_iWMMXt
;
21587 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21588 mach
= bfd_mach_arm_XScale
;
21589 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21590 mach
= bfd_mach_arm_ep9312
;
21591 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21592 mach
= bfd_mach_arm_5TE
;
21593 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21595 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21596 mach
= bfd_mach_arm_5T
;
21598 mach
= bfd_mach_arm_5
;
21600 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21602 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21603 mach
= bfd_mach_arm_4T
;
21605 mach
= bfd_mach_arm_4
;
21607 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21608 mach
= bfd_mach_arm_3M
;
21609 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21610 mach
= bfd_mach_arm_3
;
21611 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21612 mach
= bfd_mach_arm_2a
;
21613 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21614 mach
= bfd_mach_arm_2
;
21616 mach
= bfd_mach_arm_unknown
;
21618 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21621 /* Command line processing. */
21624 Invocation line includes a switch not recognized by the base assembler.
21625 See if it's a processor-specific option.
21627 This routine is somewhat complicated by the need for backwards
21628 compatibility (since older releases of gcc can't be changed).
21629 The new options try to make the interface as compatible as
21632 New options (supported) are:
21634 -mcpu=<cpu name> Assemble for selected processor
21635 -march=<architecture name> Assemble for selected architecture
21636 -mfpu=<fpu architecture> Assemble for selected FPU.
21637 -EB/-mbig-endian Big-endian
21638 -EL/-mlittle-endian Little-endian
21639 -k Generate PIC code
21640 -mthumb Start in Thumb mode
21641 -mthumb-interwork Code supports ARM/Thumb interworking
21643 -m[no-]warn-deprecated Warn about deprecated features
21645 For now we will also provide support for:
21647 -mapcs-32 32-bit Program counter
21648 -mapcs-26 26-bit Program counter
21649 -macps-float Floats passed in FP registers
21650 -mapcs-reentrant Reentrant code
21652 (sometime these will probably be replaced with -mapcs=<list of options>
21653 and -matpcs=<list of options>)
21655 The remaining options are only supported for back-wards compatibility.
21656 Cpu variants, the arm part is optional:
21657 -m[arm]1 Currently not supported.
21658 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21659 -m[arm]3 Arm 3 processor
21660 -m[arm]6[xx], Arm 6 processors
21661 -m[arm]7[xx][t][[d]m] Arm 7 processors
21662 -m[arm]8[10] Arm 8 processors
21663 -m[arm]9[20][tdmi] Arm 9 processors
21664 -mstrongarm[110[0]] StrongARM processors
21665 -mxscale XScale processors
21666 -m[arm]v[2345[t[e]]] Arm architectures
21667 -mall All (except the ARM1)
21669 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
21670 -mfpe-old (No float load/store multiples)
21671 -mvfpxd VFP Single precision
21673 -mno-fpu Disable all floating point instructions
21675 The following CPU names are recognized:
21676 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
21677 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
21678 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
21679 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
21680 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
21681 arm10t arm10e, arm1020t, arm1020e, arm10200e,
21682 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
21686 const char * md_shortopts
= "m:k";
21688 #ifdef ARM_BI_ENDIAN
21689 #define OPTION_EB (OPTION_MD_BASE + 0)
21690 #define OPTION_EL (OPTION_MD_BASE + 1)
21692 #if TARGET_BYTES_BIG_ENDIAN
21693 #define OPTION_EB (OPTION_MD_BASE + 0)
21695 #define OPTION_EL (OPTION_MD_BASE + 1)
21698 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
21700 struct option md_longopts
[] =
21703 {"EB", no_argument
, NULL
, OPTION_EB
},
21706 {"EL", no_argument
, NULL
, OPTION_EL
},
21708 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
21709 {NULL
, no_argument
, NULL
, 0}
21712 size_t md_longopts_size
= sizeof (md_longopts
);
21714 struct arm_option_table
21716 char *option
; /* Option name to match. */
21717 char *help
; /* Help information. */
21718 int *var
; /* Variable to change. */
21719 int value
; /* What to change it to. */
21720 char *deprecated
; /* If non-null, print this message. */
21723 struct arm_option_table arm_opts
[] =
21725 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
21726 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
21727 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
21728 &support_interwork
, 1, NULL
},
21729 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
21730 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
21731 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
21733 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
21734 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
21735 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
21736 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
21739 /* These are recognized by the assembler, but have no affect on code. */
21740 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
21741 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
21743 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
21744 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
21745 &warn_on_deprecated
, 0, NULL
},
21746 {NULL
, NULL
, NULL
, 0, NULL
}
21749 struct arm_legacy_option_table
21751 char *option
; /* Option name to match. */
21752 const arm_feature_set
**var
; /* Variable to change. */
21753 const arm_feature_set value
; /* What to change it to. */
21754 char *deprecated
; /* If non-null, print this message. */
21757 const struct arm_legacy_option_table arm_legacy_opts
[] =
21759 /* DON'T add any new processors to this list -- we want the whole list
21760 to go away... Add them to the processors table instead. */
21761 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21762 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21763 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21764 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21765 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21766 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21767 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21768 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21769 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21770 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21771 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21772 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21773 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21774 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21775 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21776 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21777 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21778 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21779 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21780 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21781 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21782 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21783 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21784 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21785 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21786 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21787 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21788 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21789 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21790 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21791 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21792 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21793 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21794 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21795 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21796 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21797 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21798 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21799 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21800 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21801 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21802 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21803 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21804 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21805 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21806 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21807 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21808 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21809 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21810 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21811 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21812 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21813 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21814 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21815 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21816 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21817 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21818 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21819 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21820 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21821 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21822 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21823 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21824 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21825 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21826 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21827 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21828 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21829 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
21830 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
21831 N_("use -mcpu=strongarm110")},
21832 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
21833 N_("use -mcpu=strongarm1100")},
21834 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
21835 N_("use -mcpu=strongarm1110")},
21836 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
21837 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
21838 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
21840 /* Architecture variants -- don't add any more to this list either. */
21841 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21842 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21843 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21844 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21845 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21846 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21847 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21848 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21849 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21850 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21851 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21852 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21853 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21854 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21855 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21856 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21857 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21858 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21860 /* Floating point variants -- don't add any more to this list either. */
21861 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
21862 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
21863 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
21864 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
21865 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
21867 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
21870 struct arm_cpu_option_table
21873 const arm_feature_set value
;
21874 /* For some CPUs we assume an FPU unless the user explicitly sets
21876 const arm_feature_set default_fpu
;
21877 /* The canonical name of the CPU, or NULL to use NAME converted to upper
21879 const char *canonical_name
;
21882 /* This list should, at a minimum, contain all the cpu names
21883 recognized by GCC. */
21884 static const struct arm_cpu_option_table arm_cpus
[] =
21886 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
21887 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
21888 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
21889 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21890 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21891 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21892 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21893 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21894 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21895 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21896 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21897 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21898 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21899 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21900 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21901 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21902 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21903 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21904 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21905 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21906 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21907 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21908 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21909 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21910 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21911 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21912 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21913 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21914 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21915 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21916 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21917 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21918 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21919 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21920 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21921 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21922 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21923 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21924 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21925 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
21926 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21927 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21928 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21929 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21930 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21931 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21932 /* For V5 or later processors we default to using VFP; but the user
21933 should really set the FPU type explicitly. */
21934 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21935 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21936 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
21937 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
21938 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
21939 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21940 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
21941 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21942 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21943 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
21944 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21945 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21946 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21947 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21948 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21949 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
21950 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21951 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21952 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21953 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
21954 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
21955 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
21956 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21957 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
21958 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
21959 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
21960 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
21961 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
21962 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
21963 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
21964 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
21965 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
21966 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
21967 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, NULL
},
21968 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
21969 | FPU_NEON_EXT_V1
),
21971 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
21972 | FPU_NEON_EXT_V1
),
21974 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
21975 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
, NULL
},
21976 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
21977 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
21978 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
21979 /* ??? XSCALE is really an architecture. */
21980 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
21981 /* ??? iwmmxt is not a processor. */
21982 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
21983 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
21984 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
21986 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
21987 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
21990 struct arm_arch_option_table
21993 const arm_feature_set value
;
21994 const arm_feature_set default_fpu
;
21997 /* This list should, at a minimum, contain all the architecture names
21998 recognized by GCC. */
21999 static const struct arm_arch_option_table arm_archs
[] =
22001 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22002 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22003 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22004 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22005 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22006 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22007 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22008 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22009 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22010 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22011 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22012 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22013 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22014 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22015 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22016 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22017 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22018 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22019 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22020 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22021 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22022 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22023 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22024 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22025 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22026 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22027 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22028 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22029 /* The official spelling of the ARMv7 profile variants is the dashed form.
22030 Accept the non-dashed form for compatibility with old toolchains. */
22031 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22032 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22033 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22034 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22035 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22036 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22037 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22038 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22039 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22040 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22043 /* ISA extensions in the co-processor space. */
22044 struct arm_option_cpu_value_table
22047 const arm_feature_set value
;
22050 static const struct arm_option_cpu_value_table arm_extensions
[] =
22052 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
22053 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
22054 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
22055 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
22056 {NULL
, ARM_ARCH_NONE
}
22059 /* This list should, at a minimum, contain all the fpu names
22060 recognized by GCC. */
22061 static const struct arm_option_cpu_value_table arm_fpus
[] =
22063 {"softfpa", FPU_NONE
},
22064 {"fpe", FPU_ARCH_FPE
},
22065 {"fpe2", FPU_ARCH_FPE
},
22066 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22067 {"fpa", FPU_ARCH_FPA
},
22068 {"fpa10", FPU_ARCH_FPA
},
22069 {"fpa11", FPU_ARCH_FPA
},
22070 {"arm7500fe", FPU_ARCH_FPA
},
22071 {"softvfp", FPU_ARCH_VFP
},
22072 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22073 {"vfp", FPU_ARCH_VFP_V2
},
22074 {"vfp9", FPU_ARCH_VFP_V2
},
22075 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22076 {"vfp10", FPU_ARCH_VFP_V2
},
22077 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22078 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22079 {"vfpv2", FPU_ARCH_VFP_V2
},
22080 {"vfpv3", FPU_ARCH_VFP_V3
},
22081 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22082 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22083 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22084 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22085 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22086 {"arm1020t", FPU_ARCH_VFP_V1
},
22087 {"arm1020e", FPU_ARCH_VFP_V2
},
22088 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22089 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22090 {"maverick", FPU_ARCH_MAVERICK
},
22091 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22092 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22093 {"vfpv4", FPU_ARCH_VFP_V4
},
22094 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22095 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22096 {NULL
, ARM_ARCH_NONE
}
22099 struct arm_option_value_table
22105 static const struct arm_option_value_table arm_float_abis
[] =
22107 {"hard", ARM_FLOAT_ABI_HARD
},
22108 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22109 {"soft", ARM_FLOAT_ABI_SOFT
},
22114 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22115 static const struct arm_option_value_table arm_eabis
[] =
22117 {"gnu", EF_ARM_EABI_UNKNOWN
},
22118 {"4", EF_ARM_EABI_VER4
},
22119 {"5", EF_ARM_EABI_VER5
},
22124 struct arm_long_option_table
22126 char * option
; /* Substring to match. */
22127 char * help
; /* Help information. */
22128 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22129 char * deprecated
; /* If non-null, print this message. */
22133 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22135 arm_feature_set
*ext_set
= (arm_feature_set
*)
22136 xmalloc (sizeof (arm_feature_set
));
22138 /* Copy the feature set, so that we can modify it. */
22139 *ext_set
= **opt_p
;
22142 while (str
!= NULL
&& *str
!= 0)
22144 const struct arm_option_cpu_value_table
* opt
;
22150 as_bad (_("invalid architectural extension"));
22155 ext
= strchr (str
, '+');
22158 optlen
= ext
- str
;
22160 optlen
= strlen (str
);
22164 as_bad (_("missing architectural extension"));
22168 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22169 if (strncmp (opt
->name
, str
, optlen
) == 0)
22171 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22175 if (opt
->name
== NULL
)
22177 as_bad (_("unknown architectural extension `%s'"), str
);
22188 arm_parse_cpu (char * str
)
22190 const struct arm_cpu_option_table
* opt
;
22191 char * ext
= strchr (str
, '+');
22195 optlen
= ext
- str
;
22197 optlen
= strlen (str
);
22201 as_bad (_("missing cpu name `%s'"), str
);
22205 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22206 if (strncmp (opt
->name
, str
, optlen
) == 0)
22208 mcpu_cpu_opt
= &opt
->value
;
22209 mcpu_fpu_opt
= &opt
->default_fpu
;
22210 if (opt
->canonical_name
)
22211 strcpy (selected_cpu_name
, opt
->canonical_name
);
22216 for (i
= 0; i
< optlen
; i
++)
22217 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22218 selected_cpu_name
[i
] = 0;
22222 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22227 as_bad (_("unknown cpu `%s'"), str
);
22232 arm_parse_arch (char * str
)
22234 const struct arm_arch_option_table
*opt
;
22235 char *ext
= strchr (str
, '+');
22239 optlen
= ext
- str
;
22241 optlen
= strlen (str
);
22245 as_bad (_("missing architecture name `%s'"), str
);
22249 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22250 if (streq (opt
->name
, str
))
22252 march_cpu_opt
= &opt
->value
;
22253 march_fpu_opt
= &opt
->default_fpu
;
22254 strcpy (selected_cpu_name
, opt
->name
);
22257 return arm_parse_extension (ext
, &march_cpu_opt
);
22262 as_bad (_("unknown architecture `%s'\n"), str
);
22267 arm_parse_fpu (char * str
)
22269 const struct arm_option_cpu_value_table
* opt
;
22271 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22272 if (streq (opt
->name
, str
))
22274 mfpu_opt
= &opt
->value
;
22278 as_bad (_("unknown floating point format `%s'\n"), str
);
22283 arm_parse_float_abi (char * str
)
22285 const struct arm_option_value_table
* opt
;
22287 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22288 if (streq (opt
->name
, str
))
22290 mfloat_abi_opt
= opt
->value
;
22294 as_bad (_("unknown floating point abi `%s'\n"), str
);
22300 arm_parse_eabi (char * str
)
22302 const struct arm_option_value_table
*opt
;
22304 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22305 if (streq (opt
->name
, str
))
22307 meabi_flags
= opt
->value
;
22310 as_bad (_("unknown EABI `%s'\n"), str
);
22316 arm_parse_it_mode (char * str
)
22318 bfd_boolean ret
= TRUE
;
22320 if (streq ("arm", str
))
22321 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22322 else if (streq ("thumb", str
))
22323 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22324 else if (streq ("always", str
))
22325 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22326 else if (streq ("never", str
))
22327 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22330 as_bad (_("unknown implicit IT mode `%s', should be "\
22331 "arm, thumb, always, or never."), str
);
22338 struct arm_long_option_table arm_long_opts
[] =
22340 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22341 arm_parse_cpu
, NULL
},
22342 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22343 arm_parse_arch
, NULL
},
22344 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22345 arm_parse_fpu
, NULL
},
22346 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22347 arm_parse_float_abi
, NULL
},
22349 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22350 arm_parse_eabi
, NULL
},
22352 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22353 arm_parse_it_mode
, NULL
},
22354 {NULL
, NULL
, 0, NULL
}
22358 md_parse_option (int c
, char * arg
)
22360 struct arm_option_table
*opt
;
22361 const struct arm_legacy_option_table
*fopt
;
22362 struct arm_long_option_table
*lopt
;
22368 target_big_endian
= 1;
22374 target_big_endian
= 0;
22378 case OPTION_FIX_V4BX
:
22383 /* Listing option. Just ignore these, we don't support additional
22388 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22390 if (c
== opt
->option
[0]
22391 && ((arg
== NULL
&& opt
->option
[1] == 0)
22392 || streq (arg
, opt
->option
+ 1)))
22394 /* If the option is deprecated, tell the user. */
22395 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22396 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22397 arg
? arg
: "", _(opt
->deprecated
));
22399 if (opt
->var
!= NULL
)
22400 *opt
->var
= opt
->value
;
22406 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22408 if (c
== fopt
->option
[0]
22409 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22410 || streq (arg
, fopt
->option
+ 1)))
22412 /* If the option is deprecated, tell the user. */
22413 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22414 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22415 arg
? arg
: "", _(fopt
->deprecated
));
22417 if (fopt
->var
!= NULL
)
22418 *fopt
->var
= &fopt
->value
;
22424 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22426 /* These options are expected to have an argument. */
22427 if (c
== lopt
->option
[0]
22429 && strncmp (arg
, lopt
->option
+ 1,
22430 strlen (lopt
->option
+ 1)) == 0)
22432 /* If the option is deprecated, tell the user. */
22433 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22434 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22435 _(lopt
->deprecated
));
22437 /* Call the sup-option parser. */
22438 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22449 md_show_usage (FILE * fp
)
22451 struct arm_option_table
*opt
;
22452 struct arm_long_option_table
*lopt
;
22454 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22456 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22457 if (opt
->help
!= NULL
)
22458 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22460 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22461 if (lopt
->help
!= NULL
)
22462 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22466 -EB assemble code for a big-endian cpu\n"));
22471 -EL assemble code for a little-endian cpu\n"));
22475 --fix-v4bx Allow BX in ARMv4 code\n"));
22483 arm_feature_set flags
;
22484 } cpu_arch_ver_table
;
22486 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22487 least features first. */
22488 static const cpu_arch_ver_table cpu_arch_ver
[] =
22494 {4, ARM_ARCH_V5TE
},
22495 {5, ARM_ARCH_V5TEJ
},
22499 {11, ARM_ARCH_V6M
},
22500 {8, ARM_ARCH_V6T2
},
22501 {10, ARM_ARCH_V7A
},
22502 {10, ARM_ARCH_V7R
},
22503 {10, ARM_ARCH_V7M
},
22507 /* Set an attribute if it has not already been set by the user. */
22509 aeabi_set_attribute_int (int tag
, int value
)
22512 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22513 || !attributes_set_explicitly
[tag
])
22514 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22518 aeabi_set_attribute_string (int tag
, const char *value
)
22521 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22522 || !attributes_set_explicitly
[tag
])
22523 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22526 /* Set the public EABI object attributes. */
22528 aeabi_set_public_attributes (void)
22531 arm_feature_set flags
;
22532 arm_feature_set tmp
;
22533 const cpu_arch_ver_table
*p
;
22535 /* Choose the architecture based on the capabilities of the requested cpu
22536 (if any) and/or the instructions actually used. */
22537 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22538 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22539 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22540 /*Allow the user to override the reported architecture. */
22543 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22544 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22549 for (p
= cpu_arch_ver
; p
->val
; p
++)
22551 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22554 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22558 /* Tag_CPU_name. */
22559 if (selected_cpu_name
[0])
22563 p
= selected_cpu_name
;
22564 if (strncmp (p
, "armv", 4) == 0)
22569 for (i
= 0; p
[i
]; i
++)
22570 p
[i
] = TOUPPER (p
[i
]);
22572 aeabi_set_attribute_string (Tag_CPU_name
, p
);
22575 /* Tag_CPU_arch. */
22576 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22578 /* Tag_CPU_arch_profile. */
22579 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22580 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22581 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22582 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22583 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22584 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22586 /* Tag_ARM_ISA_use. */
22587 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22589 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22591 /* Tag_THUMB_ISA_use. */
22592 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22594 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22595 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22597 /* Tag_VFP_arch. */
22598 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
22599 aeabi_set_attribute_int (Tag_VFP_arch
,
22600 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
22602 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22603 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22604 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3
))
22605 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22606 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22607 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22608 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22609 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22610 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22612 /* Tag_WMMX_arch. */
22613 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22614 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22615 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22616 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22618 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22619 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22620 aeabi_set_attribute_int
22621 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
22624 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
22625 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
22626 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
22629 /* Add the default contents for the .ARM.attributes section. */
22633 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22636 aeabi_set_public_attributes ();
22638 #endif /* OBJ_ELF */
22641 /* Parse a .cpu directive. */
22644 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
22646 const struct arm_cpu_option_table
*opt
;
22650 name
= input_line_pointer
;
22651 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22652 input_line_pointer
++;
22653 saved_char
= *input_line_pointer
;
22654 *input_line_pointer
= 0;
22656 /* Skip the first "all" entry. */
22657 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
22658 if (streq (opt
->name
, name
))
22660 mcpu_cpu_opt
= &opt
->value
;
22661 selected_cpu
= opt
->value
;
22662 if (opt
->canonical_name
)
22663 strcpy (selected_cpu_name
, opt
->canonical_name
);
22667 for (i
= 0; opt
->name
[i
]; i
++)
22668 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22669 selected_cpu_name
[i
] = 0;
22671 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22672 *input_line_pointer
= saved_char
;
22673 demand_empty_rest_of_line ();
22676 as_bad (_("unknown cpu `%s'"), name
);
22677 *input_line_pointer
= saved_char
;
22678 ignore_rest_of_line ();
22682 /* Parse a .arch directive. */
22685 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
22687 const struct arm_arch_option_table
*opt
;
22691 name
= input_line_pointer
;
22692 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22693 input_line_pointer
++;
22694 saved_char
= *input_line_pointer
;
22695 *input_line_pointer
= 0;
22697 /* Skip the first "all" entry. */
22698 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22699 if (streq (opt
->name
, name
))
22701 mcpu_cpu_opt
= &opt
->value
;
22702 selected_cpu
= opt
->value
;
22703 strcpy (selected_cpu_name
, opt
->name
);
22704 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22705 *input_line_pointer
= saved_char
;
22706 demand_empty_rest_of_line ();
22710 as_bad (_("unknown architecture `%s'\n"), name
);
22711 *input_line_pointer
= saved_char
;
22712 ignore_rest_of_line ();
22716 /* Parse a .object_arch directive. */
22719 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
22721 const struct arm_arch_option_table
*opt
;
22725 name
= input_line_pointer
;
22726 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22727 input_line_pointer
++;
22728 saved_char
= *input_line_pointer
;
22729 *input_line_pointer
= 0;
22731 /* Skip the first "all" entry. */
22732 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22733 if (streq (opt
->name
, name
))
22735 object_arch
= &opt
->value
;
22736 *input_line_pointer
= saved_char
;
22737 demand_empty_rest_of_line ();
22741 as_bad (_("unknown architecture `%s'\n"), name
);
22742 *input_line_pointer
= saved_char
;
22743 ignore_rest_of_line ();
22746 /* Parse a .fpu directive. */
22749 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
22751 const struct arm_option_cpu_value_table
*opt
;
22755 name
= input_line_pointer
;
22756 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22757 input_line_pointer
++;
22758 saved_char
= *input_line_pointer
;
22759 *input_line_pointer
= 0;
22761 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22762 if (streq (opt
->name
, name
))
22764 mfpu_opt
= &opt
->value
;
22765 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22766 *input_line_pointer
= saved_char
;
22767 demand_empty_rest_of_line ();
22771 as_bad (_("unknown floating point format `%s'\n"), name
);
22772 *input_line_pointer
= saved_char
;
22773 ignore_rest_of_line ();
22776 /* Copy symbol information. */
22779 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
22781 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
22785 /* Given a symbolic attribute NAME, return the proper integer value.
22786 Returns -1 if the attribute is not known. */
22789 arm_convert_symbolic_attribute (const char *name
)
22791 static const struct
22796 attribute_table
[] =
22798 /* When you modify this table you should
22799 also modify the list in doc/c-arm.texi. */
22800 #define T(tag) {#tag, tag}
22801 T (Tag_CPU_raw_name
),
22804 T (Tag_CPU_arch_profile
),
22805 T (Tag_ARM_ISA_use
),
22806 T (Tag_THUMB_ISA_use
),
22809 T (Tag_Advanced_SIMD_arch
),
22810 T (Tag_PCS_config
),
22811 T (Tag_ABI_PCS_R9_use
),
22812 T (Tag_ABI_PCS_RW_data
),
22813 T (Tag_ABI_PCS_RO_data
),
22814 T (Tag_ABI_PCS_GOT_use
),
22815 T (Tag_ABI_PCS_wchar_t
),
22816 T (Tag_ABI_FP_rounding
),
22817 T (Tag_ABI_FP_denormal
),
22818 T (Tag_ABI_FP_exceptions
),
22819 T (Tag_ABI_FP_user_exceptions
),
22820 T (Tag_ABI_FP_number_model
),
22821 T (Tag_ABI_align8_needed
),
22822 T (Tag_ABI_align8_preserved
),
22823 T (Tag_ABI_enum_size
),
22824 T (Tag_ABI_HardFP_use
),
22825 T (Tag_ABI_VFP_args
),
22826 T (Tag_ABI_WMMX_args
),
22827 T (Tag_ABI_optimization_goals
),
22828 T (Tag_ABI_FP_optimization_goals
),
22829 T (Tag_compatibility
),
22830 T (Tag_CPU_unaligned_access
),
22831 T (Tag_VFP_HP_extension
),
22832 T (Tag_ABI_FP_16bit_format
),
22833 T (Tag_nodefaults
),
22834 T (Tag_also_compatible_with
),
22835 T (Tag_conformance
),
22837 T (Tag_Virtualization_use
),
22838 T (Tag_MPextension_use
)
22846 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
22847 if (streq (name
, attribute_table
[i
].name
))
22848 return attribute_table
[i
].tag
;
22854 /* Apply sym value for relocations only in the case that
22855 they are for local symbols and you have the respective
22856 architectural feature for blx and simple switches. */
22858 arm_apply_sym_value (struct fix
* fixP
)
22861 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22862 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
22864 switch (fixP
->fx_r_type
)
22866 case BFD_RELOC_ARM_PCREL_BLX
:
22867 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22868 if (ARM_IS_FUNC (fixP
->fx_addsy
))
22872 case BFD_RELOC_ARM_PCREL_CALL
:
22873 case BFD_RELOC_THUMB_PCREL_BLX
:
22874 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
22885 #endif /* OBJ_ELF */