1 /* tc-h8300.c -- Assemble code for the Renesas H8/300
2 Copyright (C) 1991-2022 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Written By Steve Chamberlain <sac@cygnus.com>. */
25 #include "dwarf2dbg.h"
28 #define h8_opcodes ops
29 #include "opcode/h8300.h"
30 #include "safe-ctype.h"
33 const char comment_chars
[] = ";";
34 const char line_comment_chars
[] = "#";
36 const char line_separator_chars
[] = "!";
38 const char line_separator_chars
[] = "";
41 static void sbranch (int);
42 static void h8300hmode (int);
43 static void h8300smode (int);
44 static void h8300hnmode (int);
45 static void h8300snmode (int);
46 static void h8300sxmode (int);
47 static void h8300sxnmode (int);
48 static void pint (int);
55 static int default_mach
= bfd_mach_h8300
;
57 #define PSIZE (Hmode && !Nmode ? L_32 : L_16)
59 static int bsize
= L_8
; /* Default branch displacement. */
67 const struct h8_opcode
*opcode
;
70 static struct h8_instruction
*h8_instructions
;
73 h8300hmode (int arg ATTRIBUTE_UNUSED
)
77 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300h
))
78 as_warn (_("could not set architecture and machine"));
82 h8300smode (int arg ATTRIBUTE_UNUSED
)
86 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300s
))
87 as_warn (_("could not set architecture and machine"));
91 h8300hnmode (int arg ATTRIBUTE_UNUSED
)
96 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300hn
))
97 as_warn (_("could not set architecture and machine"));
101 h8300snmode (int arg ATTRIBUTE_UNUSED
)
106 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300sn
))
107 as_warn (_("could not set architecture and machine"));
111 h8300sxmode (int arg ATTRIBUTE_UNUSED
)
116 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300sx
))
117 as_warn (_("could not set architecture and machine"));
121 h8300sxnmode (int arg ATTRIBUTE_UNUSED
)
127 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300sxn
))
128 as_warn (_("could not set architecture and machine"));
138 pint (int arg ATTRIBUTE_UNUSED
)
140 cons (Hmode
? 4 : 2);
143 /* Like obj_elf_section, but issues a warning for new
144 sections which do not have an attribute specification. */
147 h8300_elf_section (int push
)
149 static const char * known_data_sections
[] = { ".rodata", ".tdata", ".tbss" };
150 static const char * known_data_prefixes
[] = { ".debug", ".zdebug", ".gnu.warning" };
151 char * saved_ilp
= input_line_pointer
;
154 name
= obj_elf_section_name ();
158 if (* input_line_pointer
!= ','
159 && bfd_get_section_by_name (stdoutput
, name
) == NULL
)
163 /* Ignore this warning for well known data sections. */
164 for (i
= ARRAY_SIZE (known_data_sections
); i
--;)
165 if (strcmp (name
, known_data_sections
[i
]) == 0)
169 for (i
= ARRAY_SIZE (known_data_prefixes
); i
--;)
170 if (startswith (name
, known_data_prefixes
[i
]))
174 as_warn (_("new section '%s' defined without attributes - this might cause problems"), name
);
177 /* FIXME: We ought to free the memory allocated by obj_elf_section_name()
178 for 'name', but we do not know if it was taken from the obstack, via
179 demand_copy_C_string(), or xmalloc()ed. */
180 input_line_pointer
= saved_ilp
;
181 obj_elf_section (push
);
184 /* This table describes all the machine specific pseudo-ops the assembler
185 has to support. The fields are:
186 pseudo-op name without dot
187 function to call to execute this pseudo-op
188 Integer arg to pass to the function. */
190 const pseudo_typeS md_pseudo_table
[] =
192 {"h8300h", h8300hmode
, 0},
193 {"h8300hn", h8300hnmode
, 0},
194 {"h8300s", h8300smode
, 0},
195 {"h8300sn", h8300snmode
, 0},
196 {"h8300sx", h8300sxmode
, 0},
197 {"h8300sxn", h8300sxnmode
, 0},
198 {"sbranch", sbranch
, L_8
},
199 {"lbranch", sbranch
, L_16
},
205 {"form", listing_psize
, 0},
206 {"heading", listing_title
, 0},
207 {"import", s_ignore
, 0},
208 {"page", listing_eject
, 0},
209 {"program", s_ignore
, 0},
211 {"section", h8300_elf_section
, 0},
212 {"section.s", h8300_elf_section
, 0},
213 {"sect", h8300_elf_section
, 0},
214 {"sect.s", h8300_elf_section
, 0},
219 const char EXP_CHARS
[] = "eE";
221 /* Chars that mean this number is a floating point constant
224 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
226 static htab_t opcode_hash_control
; /* Opcode mnemonics. */
228 /* This function is called once, at assembler startup time. This
229 should set up all the tables, etc. that the MD part of the assembler
235 unsigned int nopcodes
;
236 struct h8_opcode
*p
, *p1
;
237 struct h8_instruction
*pi
;
238 char prev_buffer
[100];
241 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, default_mach
))
242 as_warn (_("could not set architecture and machine"));
244 opcode_hash_control
= str_htab_create ();
247 nopcodes
= sizeof (h8_opcodes
) / sizeof (struct h8_opcode
);
249 h8_instructions
= XNEWVEC (struct h8_instruction
, nopcodes
);
251 pi
= h8_instructions
;
253 /* We do a minimum amount of sorting on the opcode table; this is to
254 make it easy to describe the mova instructions without unnecessary
256 Sorting only takes place inside blocks of instructions of the form
257 X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */
260 struct h8_opcode
*first_skipped
= 0;
262 const char *src
= p1
->name
;
267 /* Strip off any . part when inserting the opcode and only enter
268 unique codes into the hash table. */
269 dst
= buffer
= XNEWVEC (char, strlen (src
) + 1);
278 cmplen
= src
- p1
->name
+ 1;
285 str_hash_insert (opcode_hash_control
, buffer
, pi
, 0);
286 strcpy (prev_buffer
, buffer
);
289 for (p
= p1
; p
->name
; p
++)
291 /* A negative TIME is used to indicate that we've added this opcode
295 if (strncmp (p
->name
, buffer
, cmplen
) != 0
296 || (p
->name
[cmplen
] != '\0' && p
->name
[cmplen
] != '.'
297 && p
->name
[cmplen
- 1] != '/'))
299 if (first_skipped
== 0)
303 if (strncmp (p
->name
, buffer
, len
) != 0)
305 if (first_skipped
== 0)
311 pi
->size
= p
->name
[len
] == '.' ? p
->name
[len
+ 1] : 0;
314 /* Find the number of operands. */
316 while (pi
->noperands
< 3 && p
->args
.nib
[pi
->noperands
] != (op_type
) E
)
319 /* Find the length of the opcode in bytes. */
321 while (p
->data
.nib
[pi
->length
* 2] != (op_type
) E
)
330 /* Add entry for the NULL vector terminator. */
347 static void clever_message (const struct h8_instruction
*, struct h8_op
*);
348 static void fix_operand_size (struct h8_op
*, int);
349 static void build_bytes (const struct h8_instruction
*, struct h8_op
*);
350 static void do_a_fix_imm (int, int, struct h8_op
*, int, const struct h8_instruction
*);
351 static void check_operand (struct h8_op
*, unsigned int, const char *);
352 static const struct h8_instruction
* get_specific (const struct h8_instruction
*, struct h8_op
*, int) ;
353 static char *get_operands (unsigned, char *, struct h8_op
*);
354 static void get_operand (char **, struct h8_op
*, int);
355 static int parse_reg (char *, op_type
*, unsigned *, int);
356 static char *skip_colonthing (char *, int *);
357 static char *parse_exp (char *, struct h8_op
*);
359 static int constant_fits_size_p (struct h8_op
*, int, int);
363 WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp
372 /* Try to parse a reg name. Return the number of chars consumed. */
375 parse_reg (char *src
, op_type
*mode
, unsigned int *reg
, int direction
)
380 /* Cribbed from get_symbol_name. */
381 if (!is_name_beginner (*src
) || *src
== '\001')
384 while ((is_part_of_name (*end
) && *end
!= '.') || *end
== '\001')
388 if (len
== 2 && TOLOWER (src
[0]) == 's' && TOLOWER (src
[1]) == 'p')
390 *mode
= PSIZE
| REG
| direction
;
395 TOLOWER (src
[0]) == 'c' &&
396 TOLOWER (src
[1]) == 'c' &&
397 TOLOWER (src
[2]) == 'r')
404 TOLOWER (src
[0]) == 'e' &&
405 TOLOWER (src
[1]) == 'x' &&
406 TOLOWER (src
[2]) == 'r')
413 TOLOWER (src
[0]) == 'v' &&
414 TOLOWER (src
[1]) == 'b' &&
415 TOLOWER (src
[2]) == 'r')
422 TOLOWER (src
[0]) == 's' &&
423 TOLOWER (src
[1]) == 'b' &&
424 TOLOWER (src
[2]) == 'r')
430 if (len
== 2 && TOLOWER (src
[0]) == 'f' && TOLOWER (src
[1]) == 'p')
432 *mode
= PSIZE
| REG
| direction
;
436 if (len
== 3 && TOLOWER (src
[0]) == 'e' && TOLOWER (src
[1]) == 'r' &&
437 src
[2] >= '0' && src
[2] <= '7')
439 *mode
= L_32
| REG
| direction
;
442 as_warn (_("Reg not valid for H8/300"));
445 if (len
== 2 && TOLOWER (src
[0]) == 'e' && src
[1] >= '0' && src
[1] <= '7')
447 *mode
= L_16
| REG
| direction
;
448 *reg
= src
[1] - '0' + 8;
450 as_warn (_("Reg not valid for H8/300"));
454 if (TOLOWER (src
[0]) == 'r')
456 if (src
[1] >= '0' && src
[1] <= '7')
458 if (len
== 3 && TOLOWER (src
[2]) == 'l')
460 *mode
= L_8
| REG
| direction
;
461 *reg
= (src
[1] - '0') + 8;
464 if (len
== 3 && TOLOWER (src
[2]) == 'h')
466 *mode
= L_8
| REG
| direction
;
467 *reg
= (src
[1] - '0');
472 *mode
= L_16
| REG
| direction
;
473 *reg
= (src
[1] - '0');
483 /* Parse an immediate or address-related constant and store it in OP.
484 If the user also specifies the operand's size, store that size
485 in OP->MODE, otherwise leave it for later code to decide. */
488 parse_exp (char *src
, struct h8_op
*op
)
492 save
= input_line_pointer
;
493 input_line_pointer
= src
;
494 expression (&op
->exp
);
495 if (op
->exp
.X_op
== O_absent
)
496 as_bad (_("missing operand"));
497 src
= input_line_pointer
;
498 input_line_pointer
= save
;
500 return skip_colonthing (src
, &op
->mode
);
504 /* If SRC starts with an explicit operand size, skip it and store the size
505 in *MODE. Leave *MODE unchanged otherwise. */
508 skip_colonthing (char *src
, int *mode
)
514 if (src
[0] == '8' && !ISDIGIT (src
[1]))
516 else if (src
[0] == '2' && !ISDIGIT (src
[1]))
518 else if (src
[0] == '3' && !ISDIGIT (src
[1]))
520 else if (src
[0] == '4' && !ISDIGIT (src
[1]))
522 else if (src
[0] == '5' && !ISDIGIT (src
[1]))
524 else if (src
[0] == '2' && src
[1] == '4' && !ISDIGIT (src
[2]))
526 else if (src
[0] == '3' && src
[1] == '2' && !ISDIGIT (src
[2]))
528 else if (src
[0] == '1' && src
[1] == '6' && !ISDIGIT (src
[2]))
531 as_bad (_("invalid operand size requested"));
533 while (ISDIGIT (*src
))
539 /* The many forms of operand:
542 @Rn Register indirect
543 @(exp[:16], Rn) Register indirect with displacement
547 @aa:16 absolute 16 bit
550 #xx[:size] immediate data
551 @(exp:[8], pc) pc rel
552 @@aa[:8] memory indirect. */
555 constant_fits_width_p (struct h8_op
*operand
, offsetT width
)
559 num
= ((operand
->exp
.X_add_number
& 0xffffffff) ^ 0x80000000) - 0x80000000;
560 return (num
& ~width
) == 0 || (num
| width
) == ~0;
564 constant_fits_size_p (struct h8_op
*operand
, int size
, int no_symbols
)
569 && (operand
->exp
.X_add_symbol
!= 0 || operand
->exp
.X_op_symbol
!= 0))
571 num
= operand
->exp
.X_add_number
& 0xffffffff;
575 return (num
& ~3) == 0;
577 return (num
& ~7) == 0;
579 return num
>= 1 && num
< 8;
581 return (num
& ~15) == 0;
583 return num
>= 1 && num
< 32;
585 num
= (num
^ 0x80000000) - 0x80000000;
586 return (num
& ~0xFF) == 0 || (num
| 0x7F) == ~0;
588 return (num
& ~0xFF) == 0;
590 num
= (num
^ 0x80000000) - 0x80000000;
591 return (num
& ~0xFFFF) == 0 || (num
| 0x7FFF) == ~0;
593 return (num
& ~0xFFFF) == 0;
602 get_operand (char **ptr
, struct h8_op
*op
, int direction
)
611 /* Check for '(' and ')' for instructions ldm and stm. */
612 if (src
[0] == '(' && src
[8] == ')')
615 /* Gross. Gross. ldm and stm have a format not easily handled
616 by get_operand. We deal with it explicitly here. */
617 if (TOLOWER (src
[0]) == 'e' && TOLOWER (src
[1]) == 'r' &&
618 ISDIGIT (src
[2]) && src
[3] == '-' &&
619 TOLOWER (src
[4]) == 'e' && TOLOWER (src
[5]) == 'r' && ISDIGIT (src
[6]))
626 /* Check register pair's validity as per tech note TN-H8*-193A/E
627 from Renesas for H8S and H8SX hardware manual. */
628 if ( !(low
== 0 && (high
== 1 || high
== 2 || high
== 3))
629 && !(low
== 1 && (high
== 2 || high
== 3 || high
== 4) && SXmode
)
630 && !(low
== 2 && (high
== 3 || ((high
== 4 || high
== 5) && SXmode
)))
631 && !(low
== 3 && (high
== 4 || high
== 5 || high
== 6) && SXmode
)
632 && !(low
== 4 && (high
== 5 || high
== 6))
633 && !(low
== 4 && high
== 7 && SXmode
)
634 && !(low
== 5 && (high
== 6 || high
== 7) && SXmode
)
635 && !(low
== 6 && high
== 7 && SXmode
))
636 as_bad (_("Invalid register list for ldm/stm\n"));
638 /* Even sicker. We encode two registers into op->reg. One
639 for the low register to save, the other for the high
640 register to save; we also set the high bit in op->reg
641 so we know this is "very special". */
642 op
->reg
= 0x80000000 | (high
<< 8) | low
;
651 len
= parse_reg (src
, &op
->mode
, &op
->reg
, direction
);
657 int size
= op
->mode
& SIZE
;
662 as_warn (_("mismatch between register and suffix"));
663 op
->mode
= (op
->mode
& ~MODE
) | LOWREG
;
666 if (size
!= L_32
&& size
!= L_16
)
667 as_warn (_("mismatch between register and suffix"));
668 op
->mode
= (op
->mode
& ~MODE
) | LOWREG
;
669 op
->mode
= (op
->mode
& ~SIZE
) | L_16
;
672 op
->mode
= (op
->mode
& ~MODE
) | LOWREG
;
673 if (size
!= L_32
&& size
!= L_8
)
674 as_warn (_("mismatch between register and suffix"));
675 op
->mode
= (op
->mode
& ~MODE
) | LOWREG
;
676 op
->mode
= (op
->mode
& ~SIZE
) | L_8
;
679 as_warn (_("invalid suffix after register."));
693 *ptr
= parse_exp (src
+ 1, op
);
694 if (op
->exp
.X_add_number
>= 0x100)
699 /* FIXME : 2? or 4? */
700 if (op
->exp
.X_add_number
>= 0x400)
701 as_bad (_("address too high for vector table jmp/jsr"));
702 else if (op
->exp
.X_add_number
>= 0x200)
707 op
->exp
.X_add_number
= op
->exp
.X_add_number
/ divisor
- 0x80;
714 if (*src
== '-' || *src
== '+')
716 len
= parse_reg (src
+ 1, &mode
, &num
, direction
);
719 /* Oops, not a reg after all, must be ordinary exp. */
720 op
->mode
= ABS
| direction
;
721 *ptr
= parse_exp (src
, op
);
725 if (((mode
& SIZE
) != PSIZE
)
726 /* For Normal mode accept 16 bit and 32 bit pointer registers. */
727 && (!Nmode
|| ((mode
& SIZE
) != L_32
)))
728 as_bad (_("Wrong size pointer register for architecture."));
730 op
->mode
= src
[0] == '-' ? RDPREDEC
: RDPREINC
;
732 *ptr
= src
+ 1 + len
;
739 /* See if this is @(ERn.x, PC). */
740 len
= parse_reg (src
, &mode
, &op
->reg
, direction
);
741 if (len
!= 0 && (mode
& MODE
) == REG
&& src
[len
] == '.')
743 switch (TOLOWER (src
[len
+ 1]))
746 mode
= PCIDXB
| direction
;
749 mode
= PCIDXW
| direction
;
752 mode
= PCIDXL
| direction
;
759 && src
[len
+ 2] == ','
760 && TOLOWER (src
[len
+ 3]) != 'p'
761 && TOLOWER (src
[len
+ 4]) != 'c'
762 && src
[len
+ 5] != ')')
764 *ptr
= src
+ len
+ 6;
768 /* Fall through into disp case - the grammar is somewhat
769 ambiguous, so we should try whether it's a DISP operand
770 after all ("ER3.L" might be a poorly named label...). */
775 /* Start off assuming a 16 bit offset. */
777 src
= parse_exp (src
, op
);
780 op
->mode
|= ABS
| direction
;
787 as_bad (_("expected @(exp, reg16)"));
792 len
= parse_reg (src
, &mode
, &op
->reg
, direction
);
793 if (len
== 0 || (mode
& MODE
) != REG
)
795 as_bad (_("expected @(exp, reg16)"));
801 switch (TOLOWER (src
[1]))
804 op
->mode
|= INDEXB
| direction
;
807 op
->mode
|= INDEXW
| direction
;
810 op
->mode
|= INDEXL
| direction
;
813 as_bad (_("expected .L, .W or .B for register in indexed addressing mode"));
819 op
->mode
|= DISP
| direction
;
820 src
= skip_colonthing (src
, &op
->mode
);
824 as_bad (_("expected @(exp, reg16)"));
830 len
= parse_reg (src
, &mode
, &num
, direction
);
835 if (*src
== '+' || *src
== '-')
837 if (((mode
& SIZE
) != PSIZE
)
838 /* For Normal mode accept 16 bit and 32 bit pointer registers. */
839 && (!Nmode
|| ((mode
& SIZE
) != L_32
)))
840 as_bad (_("Wrong size pointer register for architecture."));
841 op
->mode
= *src
== '+' ? RSPOSTINC
: RSPOSTDEC
;
847 if (((mode
& SIZE
) != PSIZE
)
848 /* For Normal mode accept 16 bit and 32 bit pointer registers. */
849 && (!Nmode
|| ((mode
& SIZE
) != L_32
)))
850 as_bad (_("Wrong size pointer register for architecture."));
852 op
->mode
= direction
| IND
| PSIZE
;
860 /* must be a symbol */
862 op
->mode
= ABS
| direction
;
863 *ptr
= parse_exp (src
, op
);
871 *ptr
= parse_exp (src
+ 1, op
);
874 else if (startswith (src
, "mach") ||
875 startswith (src
, "macl") ||
876 startswith (src
, "MACH") ||
877 startswith (src
, "MACL"))
879 op
->reg
= TOLOWER (src
[3]) == 'l';
887 *ptr
= parse_exp (src
, op
);
892 get_operands (unsigned int noperands
, char *op_end
, struct h8_op
*operand
)
903 get_operand (&ptr
, operand
+ 0, SRC
);
907 get_operand (&ptr
, operand
+ 1, DST
);
913 get_operand (&ptr
, operand
+ 0, SRC
);
916 get_operand (&ptr
, operand
+ 1, DST
);
921 get_operand (&ptr
, operand
+ 0, SRC
);
924 get_operand (&ptr
, operand
+ 1, DST
);
927 get_operand (&ptr
, operand
+ 2, OP3
);
937 /* MOVA has special requirements. Rather than adding twice the amount of
938 addressing modes, we simply special case it a bit. */
940 get_mova_operands (char *op_end
, struct h8_op
*operand
)
944 if (ptr
[1] != '@' || ptr
[2] != '(')
948 ptr
= parse_exp (ptr
, &operand
[0]);
953 get_operand (&ptr
, operand
+ 1, DST
);
961 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXB
;
964 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXW
;
967 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXL
;
973 else if ((operand
[1].mode
& MODE
) == LOWREG
)
975 switch (operand
[1].mode
& SIZE
)
978 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXB
;
981 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXW
;
984 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXL
;
993 if (*ptr
++ != ')' || *ptr
++ != ',')
995 get_operand (&ptr
, operand
+ 2, OP3
);
996 /* See if we can use the short form of MOVA. */
997 if (((operand
[1].mode
& MODE
) == REG
|| (operand
[1].mode
& MODE
) == LOWREG
)
998 && (operand
[2].mode
& MODE
) == REG
999 && (operand
[1].reg
& 7) == (operand
[2].reg
& 7))
1001 operand
[1].mode
= operand
[2].mode
= 0;
1002 operand
[0].reg
= operand
[2].reg
& 7;
1007 as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\""));
1011 get_rtsl_operands (char *ptr
, struct h8_op
*operand
)
1013 int mode
, len
, type
= 0;
1014 unsigned int num
, num2
;
1022 len
= parse_reg (ptr
, &mode
, &num
, SRC
);
1023 if (len
== 0 || (mode
& MODE
) != REG
)
1025 as_bad (_("expected register"));
1031 len
= parse_reg (++ptr
, &mode
, &num2
, SRC
);
1032 if (len
== 0 || (mode
& MODE
) != REG
)
1034 as_bad (_("expected register"));
1038 /* CONST_xxx are used as placeholders in the opcode table. */
1042 as_bad (_("invalid register list"));
1047 num2
= num
, num
= 0;
1048 if (type
== 1 && *ptr
++ != ')')
1050 as_bad (_("expected closing paren"));
1053 operand
[0].mode
= RS32
;
1054 operand
[1].mode
= RD32
;
1055 operand
[0].reg
= num
;
1056 operand
[1].reg
= num2
;
1059 /* Passed a pointer to a list of opcodes which use different
1060 addressing modes, return the opcode which matches the opcodes
1063 static const struct h8_instruction
*
1064 get_specific (const struct h8_instruction
*instruction
,
1065 struct h8_op
*operands
, int size
)
1067 const struct h8_instruction
*this_try
= instruction
;
1068 const struct h8_instruction
*found_other
= 0, *found_mismatched
= 0;
1070 int this_index
= instruction
->idx
;
1073 /* There's only one ldm/stm and it's easier to just
1074 get out quick for them. */
1075 if (OP_KIND (instruction
->opcode
->how
) == O_LDM
1076 || OP_KIND (instruction
->opcode
->how
) == O_STM
)
1079 while (noperands
< 3 && operands
[noperands
].mode
!= 0)
1082 while (this_index
== instruction
->idx
&& !found
)
1087 this_try
= instruction
++;
1088 this_size
= this_try
->opcode
->how
& SN
;
1090 if (this_try
->noperands
!= noperands
)
1092 else if (this_try
->noperands
> 0)
1096 for (i
= 0; i
< this_try
->noperands
&& found
; i
++)
1098 op_type op
= this_try
->opcode
->args
.nib
[i
];
1099 int op_mode
= op
& MODE
;
1100 int op_size
= op
& SIZE
;
1101 int x
= operands
[i
].mode
;
1102 int x_mode
= x
& MODE
;
1103 int x_size
= x
& SIZE
;
1105 if (op_mode
== LOWREG
&& (x_mode
== REG
|| x_mode
== LOWREG
))
1107 if ((x_size
== L_8
&& (operands
[i
].reg
& 8) == 0)
1108 || (x_size
== L_16
&& (operands
[i
].reg
& 8) == 8))
1109 as_warn (_("can't use high part of register in operand %d"), i
);
1111 if (x_size
!= op_size
)
1114 else if (op_mode
== REG
)
1116 if (x_mode
== LOWREG
)
1122 x_size
= (Hmode
? L_32
: L_16
);
1124 op_size
= (Hmode
? L_32
: L_16
);
1126 /* The size of the reg is v important. */
1127 if (op_size
!= x_size
)
1130 else if (op_mode
& CTRL
) /* control register */
1132 if (!(x_mode
& CTRL
))
1138 if (op_mode
!= CCR
&&
1139 op_mode
!= CCR_EXR
&&
1140 op_mode
!= CC_EX_VB_SB
)
1144 if (op_mode
!= EXR
&&
1145 op_mode
!= CCR_EXR
&&
1146 op_mode
!= CC_EX_VB_SB
)
1150 if (op_mode
!= MACH
&&
1155 if (op_mode
!= MACL
&&
1160 if (op_mode
!= VBR
&&
1161 op_mode
!= VBR_SBR
&&
1162 op_mode
!= CC_EX_VB_SB
)
1166 if (op_mode
!= SBR
&&
1167 op_mode
!= VBR_SBR
&&
1168 op_mode
!= CC_EX_VB_SB
)
1173 else if ((op
& ABSJMP
) && (x_mode
== ABS
|| x_mode
== PCREL
))
1175 operands
[i
].mode
&= ~MODE
;
1176 operands
[i
].mode
|= ABSJMP
;
1177 /* But it may not be 24 bits long. */
1178 if (x_mode
== ABS
&& !Hmode
)
1180 operands
[i
].mode
&= ~SIZE
;
1181 operands
[i
].mode
|= L_16
;
1183 if ((operands
[i
].mode
& SIZE
) == L_32
1184 && (op_mode
& SIZE
) != L_32
)
1187 else if (x_mode
== IMM
&& op_mode
!= IMM
)
1189 offsetT num
= operands
[i
].exp
.X_add_number
& 0xffffffff;
1190 if (op_mode
== KBIT
|| op_mode
== DBIT
)
1191 /* This is ok if the immediate value is sensible. */;
1192 else if (op_mode
== CONST_2
)
1194 else if (op_mode
== CONST_4
)
1196 else if (op_mode
== CONST_8
)
1198 else if (op_mode
== CONST_16
)
1203 else if (op_mode
== PCREL
&& op_mode
== x_mode
)
1205 /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour:
1206 If x_size is L_8, promote it. */
1207 if (OP_KIND (this_try
->opcode
->how
) == O_MOVSD
1208 || OP_KIND (this_try
->opcode
->how
) == O_BSRBC
1209 || OP_KIND (this_try
->opcode
->how
) == O_BSRBS
)
1213 /* The size of the displacement is important. */
1214 if (op_size
!= x_size
)
1217 else if ((op_mode
== DISP
|| op_mode
== IMM
|| op_mode
== ABS
1218 || op_mode
== INDEXB
|| op_mode
== INDEXW
1219 || op_mode
== INDEXL
)
1220 && op_mode
== x_mode
)
1222 /* Promote a L_24 to L_32 if it makes us match. */
1223 if (x_size
== L_24
&& op_size
== L_32
)
1229 if (((x_size
== L_16
&& op_size
== L_16U
)
1230 || (x_size
== L_8
&& op_size
== L_8U
)
1231 || (x_size
== L_3
&& op_size
== L_3NZ
))
1232 /* We're deliberately more permissive for ABS modes. */
1234 || constant_fits_size_p (operands
+ i
, op_size
,
1238 if (x_size
!= 0 && op_size
!= x_size
)
1240 else if (x_size
== 0
1241 && ! constant_fits_size_p (operands
+ i
, op_size
,
1245 else if (op_mode
!= x_mode
)
1253 if ((this_try
->opcode
->available
== AV_H8SX
&& ! SXmode
)
1254 || (this_try
->opcode
->available
== AV_H8S
&& ! Smode
)
1255 || (this_try
->opcode
->available
== AV_H8H
&& ! Hmode
))
1256 found
= 0, found_other
= this_try
;
1257 else if (this_size
!= size
&& (this_size
!= SN
&& size
!= SN
))
1258 found_mismatched
= this_try
, found
= 0;
1266 as_warn (_("Opcode `%s' with these operand types not available in %s mode"),
1267 found_other
->opcode
->name
,
1268 (! Hmode
&& ! Smode
? "H8/300"
1273 else if (found_mismatched
)
1275 as_warn (_("mismatch between opcode size and operand size"));
1276 return found_mismatched
;
1282 check_operand (struct h8_op
*operand
, unsigned int width
, const char *string
)
1284 if (operand
->exp
.X_add_symbol
== 0
1285 && operand
->exp
.X_op_symbol
== 0)
1287 /* No symbol involved, let's look at offset, it's dangerous if
1288 any of the high bits are not 0 or ff's, find out by oring or
1289 anding with the width and seeing if the answer is 0 or all
1292 if (! constant_fits_width_p (operand
, width
))
1295 && (operand
->exp
.X_add_number
& 0xff00) == 0xff00)
1297 /* Just ignore this one - which happens when trying to
1298 fit a 16 bit address truncated into an 8 bit address
1299 of something like bset. */
1301 else if (strcmp (string
, "@") == 0
1303 && (operand
->exp
.X_add_number
& 0xff8000) == 0xff8000)
1305 /* Just ignore this one - which happens when trying to
1306 fit a 24 bit address truncated into a 16 bit address
1307 of something like mov.w. */
1311 as_warn (_("operand %s0x%lx out of range."), string
,
1312 (unsigned long) operand
->exp
.X_add_number
);
1318 /* RELAXMODE has one of 3 values:
1320 0 Output a "normal" reloc, no relaxing possible for this insn/reloc
1322 1 Output a relaxable 24bit absolute mov.w address relocation
1323 (may relax into a 16bit absolute address).
1325 2 Output a relaxable 16/24 absolute mov.b address relocation
1326 (may relax into an 8bit absolute address). */
1329 do_a_fix_imm (int offset
, int nibble
, struct h8_op
*operand
, int relaxmode
, const struct h8_instruction
*this_try
)
1334 char *bytes
= frag_now
->fr_literal
+ offset
;
1336 const char *t
= ((operand
->mode
& MODE
) == IMM
) ? "#" : "@";
1338 if (operand
->exp
.X_add_symbol
== 0)
1340 switch (operand
->mode
& SIZE
)
1343 check_operand (operand
, 0x3, t
);
1344 bytes
[0] |= (operand
->exp
.X_add_number
& 3) << (nibble
? 0 : 4);
1348 check_operand (operand
, 0x7, t
);
1349 bytes
[0] |= (operand
->exp
.X_add_number
& 7) << (nibble
? 0 : 4);
1352 check_operand (operand
, 0xF, t
);
1353 bytes
[0] |= (operand
->exp
.X_add_number
& 15) << (nibble
? 0 : 4);
1356 check_operand (operand
, 0x1F, t
);
1357 bytes
[0] |= operand
->exp
.X_add_number
& 31;
1361 check_operand (operand
, 0xff, t
);
1362 bytes
[0] |= operand
->exp
.X_add_number
;
1366 check_operand (operand
, 0xffff, t
);
1367 bytes
[0] |= operand
->exp
.X_add_number
>> 8;
1368 bytes
[1] |= operand
->exp
.X_add_number
>> 0;
1369 /* MOVA needs both relocs to relax the second operand properly. */
1371 && (OP_KIND(this_try
->opcode
->how
) == O_MOVAB
1372 || OP_KIND(this_try
->opcode
->how
) == O_MOVAW
1373 || OP_KIND(this_try
->opcode
->how
) == O_MOVAL
))
1376 fix_new_exp (frag_now
, offset
, 2, &operand
->exp
, 0, idx
);
1380 check_operand (operand
, 0xffffff, t
);
1381 bytes
[0] |= operand
->exp
.X_add_number
>> 16;
1382 bytes
[1] |= operand
->exp
.X_add_number
>> 8;
1383 bytes
[2] |= operand
->exp
.X_add_number
>> 0;
1387 /* This should be done with bfd. */
1388 bytes
[0] |= operand
->exp
.X_add_number
>> 24;
1389 bytes
[1] |= operand
->exp
.X_add_number
>> 16;
1390 bytes
[2] |= operand
->exp
.X_add_number
>> 8;
1391 bytes
[3] |= operand
->exp
.X_add_number
>> 0;
1394 if ((operand
->mode
& MODE
) == DISP
&& relaxmode
== 1)
1395 idx
= BFD_RELOC_H8_DISP32A16
;
1397 idx
= (relaxmode
== 2) ? R_MOV24B1
: R_MOVL1
;
1398 fix_new_exp (frag_now
, offset
, 4, &operand
->exp
, 0, idx
);
1405 switch (operand
->mode
& SIZE
)
1410 where
= (operand
->mode
& SIZE
) == L_24
? -1 : 0;
1411 if ((operand
->mode
& MODE
) == DISP
&& relaxmode
== 1)
1412 idx
= BFD_RELOC_H8_DISP32A16
;
1413 else if (relaxmode
== 2)
1415 else if (relaxmode
== 1)
1421 as_bad (_("Can't work out size of operand.\n"));
1431 operand
->exp
.X_add_number
=
1432 ((operand
->exp
.X_add_number
& 0xffff) ^ 0x8000) - 0x8000;
1433 operand
->exp
.X_add_number
|= (bytes
[0] << 8) | bytes
[1];
1439 operand
->exp
.X_add_number
=
1440 ((operand
->exp
.X_add_number
& 0xff) ^ 0x80) - 0x80;
1441 operand
->exp
.X_add_number
|= bytes
[0];
1444 fix_new_exp (frag_now
,
1453 /* Now we know what sort of opcodes it is, let's build the bytes. */
1456 build_bytes (const struct h8_instruction
*this_try
, struct h8_op
*operand
)
1459 char *output
= frag_more (this_try
->length
);
1460 const op_type
*nibble_ptr
= this_try
->opcode
->data
.nib
;
1462 unsigned int nibble_count
= 0;
1466 char asnibbles
[100];
1467 char *p
= asnibbles
;
1470 if (!Hmode
&& this_try
->opcode
->available
!= AV_H8
)
1471 as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"),
1472 this_try
->opcode
->name
);
1474 && this_try
->opcode
->available
!= AV_H8
1475 && this_try
->opcode
->available
!= AV_H8H
)
1476 as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"),
1477 this_try
->opcode
->name
);
1479 && this_try
->opcode
->available
!= AV_H8
1480 && this_try
->opcode
->available
!= AV_H8H
1481 && this_try
->opcode
->available
!= AV_H8S
)
1482 as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"),
1483 this_try
->opcode
->name
);
1485 while (*nibble_ptr
!= (op_type
) E
)
1492 d
= (c
& OP3
) == OP3
? 2 : (c
& DST
) == DST
? 1 : 0;
1500 if (c2
== REG
|| c2
== LOWREG
1501 || c2
== IND
|| c2
== PREINC
|| c2
== PREDEC
1502 || c2
== POSTINC
|| c2
== POSTDEC
)
1504 nib
= operand
[d
].reg
;
1509 else if (c
& CTRL
) /* Control reg operand. */
1510 nib
= operand
[d
].reg
;
1512 else if ((c
& DISPREG
) == (DISPREG
))
1514 nib
= operand
[d
].reg
;
1518 operand
[d
].mode
= c
;
1519 op_at
[d
] = nibble_count
;
1522 else if (c2
== IMM
|| c2
== PCREL
|| c2
== ABS
1523 || (c
& ABSJMP
) || c2
== DISP
)
1525 operand
[d
].mode
= c
;
1526 op_at
[d
] = nibble_count
;
1529 else if ((c
& IGNORE
) || (c
& DATA
))
1532 else if (c2
== DBIT
)
1534 switch (operand
[0].exp
.X_add_number
)
1543 as_bad (_("Need #1 or #2 here"));
1546 else if (c2
== KBIT
)
1548 switch (operand
[0].exp
.X_add_number
)
1558 as_warn (_("#4 not valid on H8/300."));
1563 as_bad (_("Need #1 or #2 here"));
1566 /* Stop it making a fix. */
1567 operand
[0].mode
= 0;
1571 operand
[d
].mode
|= MEMRELAX
;
1587 if (operand
[0].mode
== MACREG
)
1588 /* stmac has mac[hl] as the first operand. */
1589 nib
= 2 + operand
[0].reg
;
1591 /* ldmac has mac[hl] as the second operand. */
1592 nib
= 2 + operand
[1].reg
;
1600 /* Disgusting. Why, oh why didn't someone ask us for advice
1601 on the assembler format. */
1602 if (OP_KIND (this_try
->opcode
->how
) == O_LDM
)
1604 high
= (operand
[1].reg
>> 8) & 0xf;
1605 low
= (operand
[1].reg
) & 0xf;
1606 asnibbles
[2] = high
- low
;
1607 asnibbles
[7] = high
;
1609 else if (OP_KIND (this_try
->opcode
->how
) == O_STM
)
1611 high
= (operand
[0].reg
>> 8) & 0xf;
1612 low
= (operand
[0].reg
) & 0xf;
1613 asnibbles
[2] = high
- low
;
1617 for (i
= 0; i
< this_try
->length
; i
++)
1618 output
[i
] = (asnibbles
[i
* 2] << 4) | asnibbles
[i
* 2 + 1];
1620 /* Note if this is a mov.b or a bit manipulation instruction
1621 there is a special relaxation which only applies. */
1622 if ( this_try
->opcode
->how
== O (O_MOV
, SB
)
1623 || this_try
->opcode
->how
== O (O_BCLR
, SB
)
1624 || this_try
->opcode
->how
== O (O_BAND
, SB
)
1625 || this_try
->opcode
->how
== O (O_BIAND
, SB
)
1626 || this_try
->opcode
->how
== O (O_BILD
, SB
)
1627 || this_try
->opcode
->how
== O (O_BIOR
, SB
)
1628 || this_try
->opcode
->how
== O (O_BIST
, SB
)
1629 || this_try
->opcode
->how
== O (O_BIXOR
, SB
)
1630 || this_try
->opcode
->how
== O (O_BLD
, SB
)
1631 || this_try
->opcode
->how
== O (O_BNOT
, SB
)
1632 || this_try
->opcode
->how
== O (O_BOR
, SB
)
1633 || this_try
->opcode
->how
== O (O_BSET
, SB
)
1634 || this_try
->opcode
->how
== O (O_BST
, SB
)
1635 || this_try
->opcode
->how
== O (O_BTST
, SB
)
1636 || this_try
->opcode
->how
== O (O_BXOR
, SB
))
1639 /* Output any fixes. */
1640 for (i
= 0; i
< this_try
->noperands
; i
++)
1642 int x
= operand
[i
].mode
;
1643 int x_mode
= x
& MODE
;
1645 if (x_mode
== IMM
|| x_mode
== DISP
)
1646 do_a_fix_imm (output
- frag_now
->fr_literal
+ op_at
[i
] / 2,
1647 op_at
[i
] & 1, operand
+ i
, (x
& MEMRELAX
) != 0,
1649 else if (x_mode
== ABS
)
1650 do_a_fix_imm (output
- frag_now
->fr_literal
+ op_at
[i
] / 2,
1651 op_at
[i
] & 1, operand
+ i
,
1652 (x
& MEMRELAX
) ? movb
+ 1 : 0,
1655 else if (x_mode
== PCREL
)
1657 int size16
= (x
& SIZE
) == L_16
;
1658 int size
= size16
? 2 : 1;
1659 int type
= size16
? R_PCRWORD
: R_PCRBYTE
;
1662 check_operand (operand
+ i
, size16
? 0x7fff : 0x7f, "@");
1664 if (operand
[i
].exp
.X_add_number
& 1)
1665 as_warn (_("branch operand has odd offset (%lx)\n"),
1666 (unsigned long) operand
->exp
.X_add_number
);
1669 operand
[i
].exp
.X_add_number
=
1670 ((operand
[i
].exp
.X_add_number
& 0xffff) ^ 0x8000) - 0x8000;
1674 operand
[i
].exp
.X_add_number
=
1675 ((operand
[i
].exp
.X_add_number
& 0xff) ^ 0x80) - 0x80;
1680 operand
[i
].exp
.X_add_number
|= output
[op_at
[i
] / 2];
1682 fixP
= fix_new_exp (frag_now
,
1683 output
- frag_now
->fr_literal
+ op_at
[i
] / 2,
1688 fixP
->fx_signed
= 1;
1690 else if (x_mode
== MEMIND
)
1692 check_operand (operand
+ i
, 0xff, "@@");
1693 fix_new_exp (frag_now
,
1694 output
- frag_now
->fr_literal
+ 1,
1700 else if (x_mode
== VECIND
)
1702 check_operand (operand
+ i
, 0x7f, "@@");
1703 /* FIXME: approximating the effect of "B31" here...
1704 This is very hackish, and ought to be done a better way. */
1705 operand
[i
].exp
.X_add_number
|= 0x80;
1706 fix_new_exp (frag_now
,
1707 output
- frag_now
->fr_literal
+ 1,
1713 else if (x
& ABSJMP
)
1716 bfd_reloc_code_real_type reloc_type
= R_JMPL1
;
1718 /* To be compatible with the proposed H8 ELF format, we
1719 want the relocation's offset to point to the first byte
1720 that will be modified, not to the start of the instruction. */
1722 if ((operand
->mode
& SIZE
) == L_32
)
1725 reloc_type
= R_RELLONG
;
1730 /* This jmp may be a jump or a branch. */
1732 check_operand (operand
+ i
,
1733 SXmode
? 0xffffffff : Hmode
? 0xffffff : 0xffff,
1736 if (operand
[i
].exp
.X_add_number
& 1)
1737 as_warn (_("branch operand has odd offset (%lx)\n"),
1738 (unsigned long) operand
->exp
.X_add_number
);
1741 operand
[i
].exp
.X_add_number
=
1742 ((operand
[i
].exp
.X_add_number
& 0xffff) ^ 0x8000) - 0x8000;
1743 fix_new_exp (frag_now
,
1744 output
- frag_now
->fr_literal
+ where
,
1753 /* Try to give an intelligent error message for common and simple to
1757 clever_message (const struct h8_instruction
*instruction
,
1758 struct h8_op
*operand
)
1760 /* Find out if there was more than one possible opcode. */
1762 if ((instruction
+ 1)->idx
!= instruction
->idx
)
1766 /* Only one opcode of this flavour, try to guess which operand
1768 for (argn
= 0; argn
< instruction
->noperands
; argn
++)
1770 switch (instruction
->opcode
->args
.nib
[argn
])
1773 if (operand
[argn
].mode
!= RD16
)
1775 as_bad (_("destination operand must be 16 bit register"));
1782 if (operand
[argn
].mode
!= RS8
)
1784 as_bad (_("source operand must be 8 bit register"));
1790 if (operand
[argn
].mode
!= ABS16DST
)
1792 as_bad (_("destination operand must be 16bit absolute address"));
1797 if (operand
[argn
].mode
!= RD8
)
1799 as_bad (_("destination operand must be 8 bit register"));
1805 if (operand
[argn
].mode
!= ABS16SRC
)
1807 as_bad (_("source operand must be 16bit absolute address"));
1815 as_bad (_("invalid operands"));
1819 /* If OPERAND is part of an address, adjust its size and value given
1820 that it addresses SIZE bytes.
1822 This function decides how big non-immediate constants are when no
1823 size was explicitly given. It also scales down the assembly-level
1824 displacement in an @(d:2,ERn) operand. */
1827 fix_operand_size (struct h8_op
*operand
, int size
)
1829 if (SXmode
&& (operand
->mode
& MODE
) == DISP
)
1831 /* If the user didn't specify an operand width, see if we
1832 can use @(d:2,ERn). */
1833 if ((operand
->mode
& SIZE
) == 0
1834 && operand
->exp
.X_add_symbol
== 0
1835 && operand
->exp
.X_op_symbol
== 0
1836 && (operand
->exp
.X_add_number
== size
1837 || operand
->exp
.X_add_number
== size
* 2
1838 || operand
->exp
.X_add_number
== size
* 3))
1839 operand
->mode
|= L_2
;
1841 /* Scale down the displacement in an @(d:2,ERn) operand.
1842 X_add_number then contains the desired field value. */
1843 if ((operand
->mode
& SIZE
) == L_2
)
1845 if (operand
->exp
.X_add_number
% size
!= 0)
1846 as_warn (_("operand/size mis-match"));
1847 operand
->exp
.X_add_number
/= size
;
1851 if ((operand
->mode
& SIZE
) == 0)
1852 switch (operand
->mode
& MODE
)
1859 /* Pick a 24-bit address unless we know that a 16-bit address
1860 is safe. get_specific() will relax L_24 into L_32 where
1864 && ((((addressT
) operand
->exp
.X_add_number
+ 0x8000)
1865 & 0xffffffff) > 0xffff
1866 || operand
->exp
.X_add_symbol
!= 0
1867 || operand
->exp
.X_op_symbol
!= 0))
1868 operand
->mode
|= L_24
;
1870 operand
->mode
|= L_16
;
1874 if ((((addressT
) operand
->exp
.X_add_number
+ 0x80)
1875 & 0xffffffff) <= 0xff)
1877 if (operand
->exp
.X_add_symbol
!= NULL
)
1878 operand
->mode
|= bsize
;
1880 operand
->mode
|= L_8
;
1883 operand
->mode
|= L_16
;
1889 /* This is the guts of the machine-dependent assembler. STR points to
1890 a machine dependent instruction. This function is supposed to emit
1891 the frags/bytes it assembles. */
1894 md_assemble (char *str
)
1898 struct h8_op operand
[3];
1899 const struct h8_instruction
*instruction
;
1900 const struct h8_instruction
*prev_instruction
;
1907 /* Drop leading whitespace. */
1911 /* Find the op code end. */
1912 for (op_start
= op_end
= str
;
1913 *op_end
!= 0 && *op_end
!= ' ';
1923 else if (*op_end
== '/' && ! slash
)
1927 if (op_end
== op_start
)
1929 as_bad (_("can't find opcode "));
1935 /* The assembler stops scanning the opcode at slashes, so it fails
1936 to make characters following them lower case. Fix them. */
1939 *slash
= TOLOWER (*slash
);
1941 instruction
= (const struct h8_instruction
*)
1942 str_hash_find (opcode_hash_control
, op_start
);
1944 if (instruction
== NULL
)
1946 as_bad (_("unknown opcode"));
1950 /* We used to set input_line_pointer to the result of get_operands,
1951 but that is wrong. Our caller assumes we don't change it. */
1953 operand
[0].mode
= 0;
1954 operand
[1].mode
= 0;
1955 operand
[2].mode
= 0;
1957 if (OP_KIND (instruction
->opcode
->how
) == O_MOVAB
1958 || OP_KIND (instruction
->opcode
->how
) == O_MOVAW
1959 || OP_KIND (instruction
->opcode
->how
) == O_MOVAL
)
1960 get_mova_operands (op_end
, operand
);
1961 else if (OP_KIND (instruction
->opcode
->how
) == O_RTEL
1962 || OP_KIND (instruction
->opcode
->how
) == O_RTSL
)
1963 get_rtsl_operands (op_end
, operand
);
1965 get_operands (instruction
->noperands
, op_end
, operand
);
1968 prev_instruction
= instruction
;
1970 /* Now we have operands from instruction.
1971 Let's check them out for ldm and stm. */
1972 if (OP_KIND (instruction
->opcode
->how
) == O_LDM
)
1974 /* The first operand must be @er7+, and the
1975 second operand must be a register pair. */
1976 if ((operand
[0].mode
!= RSINC
)
1977 || (operand
[0].reg
!= 7)
1978 || ((operand
[1].reg
& 0x80000000) == 0))
1979 as_bad (_("invalid operand in ldm"));
1981 else if (OP_KIND (instruction
->opcode
->how
) == O_STM
)
1983 /* The first operand must be a register pair,
1984 and the second operand must be @-er7. */
1985 if (((operand
[0].reg
& 0x80000000) == 0)
1986 || (operand
[1].mode
!= RDDEC
)
1987 || (operand
[1].reg
!= 7))
1988 as_bad (_("invalid operand in stm"));
1994 switch (TOLOWER (*dot
))
2009 if (OP_KIND (instruction
->opcode
->how
) == O_MOVAB
||
2010 OP_KIND (instruction
->opcode
->how
) == O_MOVAW
||
2011 OP_KIND (instruction
->opcode
->how
) == O_MOVAL
)
2013 switch (operand
[0].mode
& MODE
)
2017 fix_operand_size (&operand
[1], 1);
2020 fix_operand_size (&operand
[1], 2);
2023 fix_operand_size (&operand
[1], 4);
2029 for (i
= 0; i
< 3 && operand
[i
].mode
!= 0; i
++)
2035 fix_operand_size (&operand
[i
], 1);
2038 fix_operand_size (&operand
[i
], 2);
2041 fix_operand_size (&operand
[i
], 4);
2046 instruction
= get_specific (instruction
, operand
, size
);
2048 if (instruction
== 0)
2050 /* Couldn't find an opcode which matched the operands. */
2051 char *where
= frag_more (2);
2055 clever_message (prev_instruction
, operand
);
2060 build_bytes (instruction
, operand
);
2062 dwarf2_emit_insn (instruction
->length
);
2066 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
2071 /* Various routines to kill one day. */
2074 md_atof (int type
, char *litP
, int *sizeP
)
2076 return ieee_md_atof (type
, litP
, sizeP
, true);
2079 #define OPTION_H_TICK_HEX (OPTION_MD_BASE)
2080 #define OPTION_MACH (OPTION_MD_BASE+1)
2082 const char *md_shortopts
= "";
2083 struct option md_longopts
[] =
2085 { "h-tick-hex", no_argument
, NULL
, OPTION_H_TICK_HEX
},
2086 { "mach", required_argument
, NULL
, OPTION_MACH
},
2087 {NULL
, no_argument
, NULL
, 0}
2090 size_t md_longopts_size
= sizeof (md_longopts
);
2095 void (*func
) (void);
2105 default_mach
= bfd_mach_h8300h
;
2115 default_mach
= bfd_mach_h8300hn
;
2125 default_mach
= bfd_mach_h8300s
;
2135 default_mach
= bfd_mach_h8300sn
;
2145 default_mach
= bfd_mach_h8300sx
;
2149 mach_h8300sxn (void)
2155 default_mach
= bfd_mach_h8300sxn
;
2158 const struct mach_func mach_table
[] =
2160 {"h8300h", mach_h8300h
},
2161 {"h8300hn", mach_h8300hn
},
2162 {"h8300s", mach_h8300s
},
2163 {"h8300sn", mach_h8300sn
},
2164 {"h8300sx", mach_h8300sx
},
2165 {"h8300sxn", mach_h8300sxn
}
2169 md_parse_option (int c ATTRIBUTE_UNUSED
, const char *arg ATTRIBUTE_UNUSED
)
2174 case OPTION_H_TICK_HEX
:
2175 enable_h_tick_hex
= 1;
2178 for (i
= 0; i
< sizeof(mach_table
) / sizeof(struct mach_func
); i
++)
2180 if (strcasecmp (arg
, mach_table
[i
].name
) == 0)
2182 mach_table
[i
].func();
2186 if (i
>= sizeof(mach_table
) / sizeof(struct mach_func
))
2187 as_bad (_("Invalid argument to --mach option: %s"), arg
);
2196 md_show_usage (FILE *stream
)
2198 fprintf (stream
, _(" H8300-specific assembler options:\n"));
2199 fprintf (stream
, _("\
2200 -mach=<name> Set the H8300 machine type to one of:\n\
2201 h8300h, h8300hn, h8300s, h8300sn, h8300sx, h8300sxn\n"));
2202 fprintf (stream
, _("\
2203 -h-tick-hex Support H'00 style hex constants\n"));
2206 void tc_aout_fix_to_chars (void);
2209 tc_aout_fix_to_chars (void)
2211 printf (_("call to tc_aout_fix_to_chars \n"));
2216 md_convert_frag (bfd
*headers ATTRIBUTE_UNUSED
,
2217 segT seg ATTRIBUTE_UNUSED
,
2218 fragS
*fragP ATTRIBUTE_UNUSED
)
2220 printf (_("call to md_convert_frag \n"));
2225 md_section_align (segT segment
, valueT size
)
2227 int align
= bfd_section_alignment (segment
);
2228 return ((size
+ (1 << align
) - 1) & (-1U << align
));
2232 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2234 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2237 switch (fixP
->fx_size
)
2243 *buf
++ = (val
>> 8);
2247 *buf
++ = (val
>> 24);
2248 *buf
++ = (val
>> 16);
2249 *buf
++ = (val
>> 8);
2253 /* This can arise when the .quad or .8byte pseudo-ops are used.
2254 Returning here (without setting fx_done) will cause the code
2255 to attempt to generate a reloc which will then fail with the
2256 slightly more helpful error message: "Cannot represent
2257 relocation type BFD_RELOC_64". */
2263 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
2268 md_estimate_size_before_relax (fragS
*fragP ATTRIBUTE_UNUSED
,
2269 segT segment_type ATTRIBUTE_UNUSED
)
2271 printf (_("call to md_estimate_size_before_relax \n"));
2275 /* Put number into target byte order. */
2277 md_number_to_chars (char *ptr
, valueT use
, int nbytes
)
2279 number_to_chars_bigendian (ptr
, use
, nbytes
);
2283 md_pcrel_from (fixS
*fixp
)
2285 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2286 _("Unexpected reference to a symbol in a non-code section"));
2291 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2294 bfd_reloc_code_real_type r_type
;
2296 if (fixp
->fx_addsy
&& fixp
->fx_subsy
)
2298 if ((S_GET_SEGMENT (fixp
->fx_addsy
) != S_GET_SEGMENT (fixp
->fx_subsy
))
2299 || S_GET_SEGMENT (fixp
->fx_addsy
) == undefined_section
)
2301 as_bad_subtract (fixp
);
2306 rel
= XNEW (arelent
);
2307 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
2308 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2309 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2310 rel
->addend
= fixp
->fx_offset
;
2312 r_type
= fixp
->fx_r_type
;
2316 fprintf (stderr
, "%s\n", bfd_get_reloc_code_name (r_type
));
2319 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, r_type
);
2320 if (rel
->howto
== NULL
)
2322 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2323 _("Cannot represent relocation type %s"),
2324 bfd_get_reloc_code_name (r_type
));