1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
294 invalid_vsib_address
,
295 invalid_vector_register_set
,
296 invalid_tmm_register_set
,
297 unsupported_vector_index_register
,
298 unsupported_broadcast
,
301 mask_not_on_destination
,
304 rc_sae_operand_not_last_imm
,
305 invalid_register_operand
,
310 /* TM holds the template for the insn were currently assembling. */
313 /* SUFFIX holds the instruction size suffix for byte, word, dword
314 or qword, if given. */
317 /* OPERANDS gives the number of given operands. */
318 unsigned int operands
;
320 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
321 of given register, displacement, memory operands and immediate
323 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
325 /* TYPES [i] is the type (see above #defines) which tells us how to
326 use OP[i] for the corresponding operand. */
327 i386_operand_type types
[MAX_OPERANDS
];
329 /* Displacement expression, immediate expression, or register for each
331 union i386_op op
[MAX_OPERANDS
];
333 /* Flags for operands. */
334 unsigned int flags
[MAX_OPERANDS
];
335 #define Operand_PCrel 1
336 #define Operand_Mem 2
338 /* Relocation type for operand */
339 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
341 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
342 the base index byte below. */
343 const reg_entry
*base_reg
;
344 const reg_entry
*index_reg
;
345 unsigned int log2_scale_factor
;
347 /* SEG gives the seg_entries of this insn. They are zero unless
348 explicit segment overrides are given. */
349 const seg_entry
*seg
[2];
351 /* Copied first memory operand string, for re-checking. */
354 /* PREFIX holds all the given prefix opcodes (usually null).
355 PREFIXES is the number of prefix opcodes. */
356 unsigned int prefixes
;
357 unsigned char prefix
[MAX_PREFIXES
];
359 /* Register is in low 3 bits of opcode. */
360 bfd_boolean short_form
;
362 /* The operand to a branch insn indicates an absolute branch. */
363 bfd_boolean jumpabsolute
;
365 /* Extended states. */
373 xstate_ymm
= 1 << 2 | xstate_xmm
,
375 xstate_zmm
= 1 << 3 | xstate_ymm
,
380 /* Has GOTPC or TLS relocation. */
381 bfd_boolean has_gotpc_tls_reloc
;
383 /* RM and SIB are the modrm byte and the sib byte where the
384 addressing modes of this insn are encoded. */
391 /* Masking attributes. */
392 struct Mask_Operation
*mask
;
394 /* Rounding control and SAE attributes. */
395 struct RC_Operation
*rounding
;
397 /* Broadcasting attributes. */
398 struct Broadcast_Operation
*broadcast
;
400 /* Compressed disp8*N attribute. */
401 unsigned int memshift
;
403 /* Prefer load or store in encoding. */
406 dir_encoding_default
= 0,
412 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
415 disp_encoding_default
= 0,
421 /* Prefer the REX byte in encoding. */
422 bfd_boolean rex_encoding
;
424 /* Disable instruction size optimization. */
425 bfd_boolean no_optimize
;
427 /* How to encode vector instructions. */
430 vex_encoding_default
= 0,
438 const char *rep_prefix
;
441 const char *hle_prefix
;
443 /* Have BND prefix. */
444 const char *bnd_prefix
;
446 /* Have NOTRACK prefix. */
447 const char *notrack_prefix
;
450 enum i386_error error
;
453 typedef struct _i386_insn i386_insn
;
455 /* Link RC type with corresponding string, that'll be looked for in
464 static const struct RC_name RC_NamesTable
[] =
466 { rne
, STRING_COMMA_LEN ("rn-sae") },
467 { rd
, STRING_COMMA_LEN ("rd-sae") },
468 { ru
, STRING_COMMA_LEN ("ru-sae") },
469 { rz
, STRING_COMMA_LEN ("rz-sae") },
470 { saeonly
, STRING_COMMA_LEN ("sae") },
473 /* List of chars besides those in app.c:symbol_chars that can start an
474 operand. Used to prevent the scrubber eating vital white-space. */
475 const char extra_symbol_chars
[] = "*%-([{}"
484 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
485 && !defined (TE_GNU) \
486 && !defined (TE_LINUX) \
487 && !defined (TE_FreeBSD) \
488 && !defined (TE_DragonFly) \
489 && !defined (TE_NetBSD))
490 /* This array holds the chars that always start a comment. If the
491 pre-processor is disabled, these aren't very useful. The option
492 --divide will remove '/' from this list. */
493 const char *i386_comment_chars
= "#/";
494 #define SVR4_COMMENT_CHARS 1
495 #define PREFIX_SEPARATOR '\\'
498 const char *i386_comment_chars
= "#";
499 #define PREFIX_SEPARATOR '/'
502 /* This array holds the chars that only start a comment at the beginning of
503 a line. If the line seems to have the form '# 123 filename'
504 .line and .file directives will appear in the pre-processed output.
505 Note that input_file.c hand checks for '#' at the beginning of the
506 first line of the input file. This is because the compiler outputs
507 #NO_APP at the beginning of its output.
508 Also note that comments started like this one will always work if
509 '/' isn't otherwise defined. */
510 const char line_comment_chars
[] = "#/";
512 const char line_separator_chars
[] = ";";
514 /* Chars that can be used to separate mant from exp in floating point
516 const char EXP_CHARS
[] = "eE";
518 /* Chars that mean this number is a floating point constant
521 const char FLT_CHARS
[] = "fFdDxX";
523 /* Tables for lexical analysis. */
524 static char mnemonic_chars
[256];
525 static char register_chars
[256];
526 static char operand_chars
[256];
527 static char identifier_chars
[256];
528 static char digit_chars
[256];
530 /* Lexical macros. */
531 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
532 #define is_operand_char(x) (operand_chars[(unsigned char) x])
533 #define is_register_char(x) (register_chars[(unsigned char) x])
534 #define is_space_char(x) ((x) == ' ')
535 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
536 #define is_digit_char(x) (digit_chars[(unsigned char) x])
538 /* All non-digit non-letter characters that may occur in an operand. */
539 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
541 /* md_assemble() always leaves the strings it's passed unaltered. To
542 effect this we maintain a stack of saved characters that we've smashed
543 with '\0's (indicating end of strings for various sub-fields of the
544 assembler instruction). */
545 static char save_stack
[32];
546 static char *save_stack_p
;
547 #define END_STRING_AND_SAVE(s) \
548 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
549 #define RESTORE_END_STRING(s) \
550 do { *(s) = *--save_stack_p; } while (0)
552 /* The instruction we're assembling. */
555 /* Possible templates for current insn. */
556 static const templates
*current_templates
;
558 /* Per instruction expressionS buffers: max displacements & immediates. */
559 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
560 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
562 /* Current operand we are working on. */
563 static int this_operand
= -1;
565 /* We support four different modes. FLAG_CODE variable is used to distinguish
573 static enum flag_code flag_code
;
574 static unsigned int object_64bit
;
575 static unsigned int disallow_64bit_reloc
;
576 static int use_rela_relocations
= 0;
577 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
578 static const char *tls_get_addr
;
580 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
581 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
582 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
584 /* The ELF ABI to use. */
592 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
595 #if defined (TE_PE) || defined (TE_PEP)
596 /* Use big object file format. */
597 static int use_big_obj
= 0;
600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
601 /* 1 if generating code for a shared library. */
602 static int shared
= 0;
605 /* 1 for intel syntax,
607 static int intel_syntax
= 0;
609 static enum x86_64_isa
611 amd64
= 1, /* AMD64 ISA. */
612 intel64
/* Intel64 ISA. */
615 /* 1 for intel mnemonic,
616 0 if att mnemonic. */
617 static int intel_mnemonic
= !SYSV386_COMPAT
;
619 /* 1 if pseudo registers are permitted. */
620 static int allow_pseudo_reg
= 0;
622 /* 1 if register prefix % not required. */
623 static int allow_naked_reg
= 0;
625 /* 1 if the assembler should add BND prefix for all control-transferring
626 instructions supporting it, even if this prefix wasn't specified
628 static int add_bnd_prefix
= 0;
630 /* 1 if pseudo index register, eiz/riz, is allowed . */
631 static int allow_index_reg
= 0;
633 /* 1 if the assembler should ignore LOCK prefix, even if it was
634 specified explicitly. */
635 static int omit_lock_prefix
= 0;
637 /* 1 if the assembler should encode lfence, mfence, and sfence as
638 "lock addl $0, (%{re}sp)". */
639 static int avoid_fence
= 0;
641 /* 1 if lfence should be inserted after every load. */
642 static int lfence_after_load
= 0;
644 /* Non-zero if lfence should be inserted before indirect branch. */
645 static enum lfence_before_indirect_branch_kind
647 lfence_branch_none
= 0,
648 lfence_branch_register
,
649 lfence_branch_memory
,
652 lfence_before_indirect_branch
;
654 /* Non-zero if lfence should be inserted before ret. */
655 static enum lfence_before_ret_kind
657 lfence_before_ret_none
= 0,
658 lfence_before_ret_not
,
659 lfence_before_ret_or
,
660 lfence_before_ret_shl
664 /* Types of previous instruction is .byte or prefix. */
679 /* 1 if the assembler should generate relax relocations. */
681 static int generate_relax_relocations
682 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
684 static enum check_kind
690 sse_check
, operand_check
= check_warning
;
692 /* Non-zero if branches should be aligned within power of 2 boundary. */
693 static int align_branch_power
= 0;
695 /* Types of branches to align. */
696 enum align_branch_kind
698 align_branch_none
= 0,
699 align_branch_jcc
= 1,
700 align_branch_fused
= 2,
701 align_branch_jmp
= 3,
702 align_branch_call
= 4,
703 align_branch_indirect
= 5,
707 /* Type bits of branches to align. */
708 enum align_branch_bit
710 align_branch_jcc_bit
= 1 << align_branch_jcc
,
711 align_branch_fused_bit
= 1 << align_branch_fused
,
712 align_branch_jmp_bit
= 1 << align_branch_jmp
,
713 align_branch_call_bit
= 1 << align_branch_call
,
714 align_branch_indirect_bit
= 1 << align_branch_indirect
,
715 align_branch_ret_bit
= 1 << align_branch_ret
718 static unsigned int align_branch
= (align_branch_jcc_bit
719 | align_branch_fused_bit
720 | align_branch_jmp_bit
);
722 /* Types of condition jump used by macro-fusion. */
725 mf_jcc_jo
= 0, /* base opcode 0x70 */
726 mf_jcc_jc
, /* base opcode 0x72 */
727 mf_jcc_je
, /* base opcode 0x74 */
728 mf_jcc_jna
, /* base opcode 0x76 */
729 mf_jcc_js
, /* base opcode 0x78 */
730 mf_jcc_jp
, /* base opcode 0x7a */
731 mf_jcc_jl
, /* base opcode 0x7c */
732 mf_jcc_jle
, /* base opcode 0x7e */
735 /* Types of compare flag-modifying insntructions used by macro-fusion. */
738 mf_cmp_test_and
, /* test/cmp */
739 mf_cmp_alu_cmp
, /* add/sub/cmp */
740 mf_cmp_incdec
/* inc/dec */
743 /* The maximum padding size for fused jcc. CMP like instruction can
744 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
746 #define MAX_FUSED_JCC_PADDING_SIZE 20
748 /* The maximum number of prefixes added for an instruction. */
749 static unsigned int align_branch_prefix_size
= 5;
752 1. Clear the REX_W bit with register operand if possible.
753 2. Above plus use 128bit vector instruction to clear the full vector
756 static int optimize
= 0;
759 1. Clear the REX_W bit with register operand if possible.
760 2. Above plus use 128bit vector instruction to clear the full vector
762 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
765 static int optimize_for_space
= 0;
767 /* Register prefix used for error message. */
768 static const char *register_prefix
= "%";
770 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
771 leave, push, and pop instructions so that gcc has the same stack
772 frame as in 32 bit mode. */
773 static char stackop_size
= '\0';
775 /* Non-zero to optimize code alignment. */
776 int optimize_align_code
= 1;
778 /* Non-zero to quieten some warnings. */
779 static int quiet_warnings
= 0;
782 static const char *cpu_arch_name
= NULL
;
783 static char *cpu_sub_arch_name
= NULL
;
785 /* CPU feature flags. */
786 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
788 /* If we have selected a cpu we are generating instructions for. */
789 static int cpu_arch_tune_set
= 0;
791 /* Cpu we are generating instructions for. */
792 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
794 /* CPU feature flags of cpu we are generating instructions for. */
795 static i386_cpu_flags cpu_arch_tune_flags
;
797 /* CPU instruction set architecture used. */
798 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
800 /* CPU feature flags of instruction set architecture used. */
801 i386_cpu_flags cpu_arch_isa_flags
;
803 /* If set, conditional jumps are not automatically promoted to handle
804 larger than a byte offset. */
805 static unsigned int no_cond_jump_promotion
= 0;
807 /* Encode SSE instructions with VEX prefix. */
808 static unsigned int sse2avx
;
810 /* Encode scalar AVX instructions with specific vector length. */
817 /* Encode VEX WIG instructions with specific vex.w. */
824 /* Encode scalar EVEX LIG instructions with specific vector length. */
832 /* Encode EVEX WIG instructions with specific evex.w. */
839 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
840 static enum rc_type evexrcig
= rne
;
842 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
843 static symbolS
*GOT_symbol
;
845 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
846 unsigned int x86_dwarf2_return_column
;
848 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
849 int x86_cie_data_alignment
;
851 /* Interface to relax_segment.
852 There are 3 major relax states for 386 jump insns because the
853 different types of jumps add different sizes to frags when we're
854 figuring out what sort of jump to choose to reach a given label.
856 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
857 branches which are handled by md_estimate_size_before_relax() and
858 i386_generic_table_relax_frag(). */
861 #define UNCOND_JUMP 0
863 #define COND_JUMP86 2
864 #define BRANCH_PADDING 3
865 #define BRANCH_PREFIX 4
866 #define FUSED_JCC_PADDING 5
871 #define SMALL16 (SMALL | CODE16)
873 #define BIG16 (BIG | CODE16)
877 #define INLINE __inline__
883 #define ENCODE_RELAX_STATE(type, size) \
884 ((relax_substateT) (((type) << 2) | (size)))
885 #define TYPE_FROM_RELAX_STATE(s) \
887 #define DISP_SIZE_FROM_RELAX_STATE(s) \
888 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
890 /* This table is used by relax_frag to promote short jumps to long
891 ones where necessary. SMALL (short) jumps may be promoted to BIG
892 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
893 don't allow a short jump in a 32 bit code segment to be promoted to
894 a 16 bit offset jump because it's slower (requires data size
895 prefix), and doesn't work, unless the destination is in the bottom
896 64k of the code segment (The top 16 bits of eip are zeroed). */
898 const relax_typeS md_relax_table
[] =
901 1) most positive reach of this state,
902 2) most negative reach of this state,
903 3) how many bytes this mode will have in the variable part of the frag
904 4) which index into the table to try if we can't fit into this one. */
906 /* UNCOND_JUMP states. */
907 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
908 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
909 /* dword jmp adds 4 bytes to frag:
910 0 extra opcode bytes, 4 displacement bytes. */
912 /* word jmp adds 2 byte2 to frag:
913 0 extra opcode bytes, 2 displacement bytes. */
916 /* COND_JUMP states. */
917 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
918 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
919 /* dword conditionals adds 5 bytes to frag:
920 1 extra opcode byte, 4 displacement bytes. */
922 /* word conditionals add 3 bytes to frag:
923 1 extra opcode byte, 2 displacement bytes. */
926 /* COND_JUMP86 states. */
927 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
928 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
929 /* dword conditionals adds 5 bytes to frag:
930 1 extra opcode byte, 4 displacement bytes. */
932 /* word conditionals add 4 bytes to frag:
933 1 displacement byte and a 3 byte long branch insn. */
937 static const arch_entry cpu_arch
[] =
939 /* Do not replace the first two entries - i386_target_format()
940 relies on them being there in this order. */
941 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
942 CPU_GENERIC32_FLAGS
, 0 },
943 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
944 CPU_GENERIC64_FLAGS
, 0 },
945 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
953 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
955 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
957 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
959 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
961 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
962 CPU_PENTIUMPRO_FLAGS
, 0 },
963 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
965 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
967 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
969 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
971 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
972 CPU_NOCONA_FLAGS
, 0 },
973 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
975 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
977 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
978 CPU_CORE2_FLAGS
, 1 },
979 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
980 CPU_CORE2_FLAGS
, 0 },
981 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
982 CPU_COREI7_FLAGS
, 0 },
983 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
985 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
987 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
988 CPU_IAMCU_FLAGS
, 0 },
989 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
991 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
993 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
994 CPU_ATHLON_FLAGS
, 0 },
995 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
997 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
999 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
1001 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
1002 CPU_AMDFAM10_FLAGS
, 0 },
1003 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1004 CPU_BDVER1_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1006 CPU_BDVER2_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1008 CPU_BDVER3_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1010 CPU_BDVER4_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1012 CPU_ZNVER1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1014 CPU_ZNVER2_FLAGS
, 0 },
1015 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1016 CPU_BTVER1_FLAGS
, 0 },
1017 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1018 CPU_BTVER2_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1020 CPU_8087_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1023 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1028 CPU_CMOV_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1030 CPU_FXSR_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1035 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1036 CPU_SSE2_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1038 CPU_SSE3_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE4A_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1042 CPU_SSSE3_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1044 CPU_SSE4_1_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1046 CPU_SSE4_2_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1048 CPU_SSE4_2_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1051 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1052 CPU_AVX2_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX512F_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512CD_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512ER_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512PF_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512DQ_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1064 CPU_AVX512BW_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1066 CPU_AVX512VL_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1070 CPU_VMFUNC_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1073 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1074 CPU_XSAVE_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1076 CPU_XSAVEOPT_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1078 CPU_XSAVEC_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1080 CPU_XSAVES_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1083 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1084 CPU_PCLMUL_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1086 CPU_PCLMUL_FLAGS
, 1 },
1087 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1088 CPU_FSGSBASE_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1090 CPU_RDRND_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1092 CPU_F16C_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1094 CPU_BMI2_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1097 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1098 CPU_FMA4_FLAGS
, 0 },
1099 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1101 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1103 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1104 CPU_MOVBE_FLAGS
, 0 },
1105 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1106 CPU_CX16_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1109 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1110 CPU_LZCNT_FLAGS
, 0 },
1111 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1112 CPU_POPCNT_FLAGS
, 0 },
1113 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1115 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1117 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1118 CPU_INVPCID_FLAGS
, 0 },
1119 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1120 CPU_CLFLUSH_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1123 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1124 CPU_SYSCALL_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1126 CPU_RDTSCP_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1128 CPU_3DNOW_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1130 CPU_3DNOWA_FLAGS
, 0 },
1131 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1132 CPU_PADLOCK_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1134 CPU_SVME_FLAGS
, 1 },
1135 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1136 CPU_SVME_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1138 CPU_SSE4A_FLAGS
, 0 },
1139 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1141 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1143 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1145 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1147 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1148 CPU_RDSEED_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1150 CPU_PRFCHW_FLAGS
, 0 },
1151 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1152 CPU_SMAP_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1155 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1157 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1158 CPU_CLFLUSHOPT_FLAGS
, 0 },
1159 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1160 CPU_PREFETCHWT1_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1163 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1164 CPU_CLWB_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1166 CPU_AVX512IFMA_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1168 CPU_AVX512VBMI_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_VBMI2_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1178 CPU_AVX512_VNNI_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1180 CPU_AVX512_BITALG_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1182 CPU_CLZERO_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1184 CPU_MWAITX_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1186 CPU_OSPKE_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1188 CPU_RDPID_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1190 CPU_PTWRITE_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1193 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1194 CPU_SHSTK_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1196 CPU_GFNI_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1198 CPU_VAES_FLAGS
, 0 },
1199 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1200 CPU_VPCLMULQDQ_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1202 CPU_WBNOINVD_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1204 CPU_PCONFIG_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1206 CPU_WAITPKG_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1208 CPU_CLDEMOTE_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1210 CPU_AMX_INT8_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1212 CPU_AMX_BF16_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1214 CPU_AMX_TILE_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1216 CPU_MOVDIRI_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1218 CPU_MOVDIR64B_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1220 CPU_AVX512_BF16_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1222 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1224 CPU_ENQCMD_FLAGS
, 0 },
1225 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1226 CPU_SERIALIZE_FLAGS
, 0 },
1227 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1228 CPU_RDPRU_FLAGS
, 0 },
1229 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1230 CPU_MCOMMIT_FLAGS
, 0 },
1231 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1232 CPU_SEV_ES_FLAGS
, 0 },
1233 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1234 CPU_TSXLDTRK_FLAGS
, 0 },
1237 static const noarch_entry cpu_noarch
[] =
1239 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1240 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1241 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1242 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1243 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1244 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1245 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1246 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1247 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1248 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1249 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1250 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1251 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1252 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1253 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1254 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1255 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1256 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1257 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1258 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1259 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1260 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1261 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1262 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1263 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1264 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1266 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1267 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1268 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1269 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1270 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1271 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1272 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1273 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1274 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1275 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1276 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1277 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1278 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1279 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1280 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1281 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1282 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1283 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1287 /* Like s_lcomm_internal in gas/read.c but the alignment string
1288 is allowed to be optional. */
1291 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1298 && *input_line_pointer
== ',')
1300 align
= parse_align (needs_align
- 1);
1302 if (align
== (addressT
) -1)
1317 bss_alloc (symbolP
, size
, align
);
1322 pe_lcomm (int needs_align
)
1324 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1328 const pseudo_typeS md_pseudo_table
[] =
1330 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1331 {"align", s_align_bytes
, 0},
1333 {"align", s_align_ptwo
, 0},
1335 {"arch", set_cpu_arch
, 0},
1339 {"lcomm", pe_lcomm
, 1},
1341 {"ffloat", float_cons
, 'f'},
1342 {"dfloat", float_cons
, 'd'},
1343 {"tfloat", float_cons
, 'x'},
1345 {"slong", signed_cons
, 4},
1346 {"noopt", s_ignore
, 0},
1347 {"optim", s_ignore
, 0},
1348 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1349 {"code16", set_code_flag
, CODE_16BIT
},
1350 {"code32", set_code_flag
, CODE_32BIT
},
1352 {"code64", set_code_flag
, CODE_64BIT
},
1354 {"intel_syntax", set_intel_syntax
, 1},
1355 {"att_syntax", set_intel_syntax
, 0},
1356 {"intel_mnemonic", set_intel_mnemonic
, 1},
1357 {"att_mnemonic", set_intel_mnemonic
, 0},
1358 {"allow_index_reg", set_allow_index_reg
, 1},
1359 {"disallow_index_reg", set_allow_index_reg
, 0},
1360 {"sse_check", set_check
, 0},
1361 {"operand_check", set_check
, 1},
1362 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1363 {"largecomm", handle_large_common
, 0},
1365 {"file", dwarf2_directive_file
, 0},
1366 {"loc", dwarf2_directive_loc
, 0},
1367 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1370 {"secrel32", pe_directive_secrel
, 0},
1375 /* For interface with expression (). */
1376 extern char *input_line_pointer
;
1378 /* Hash table for instruction mnemonic lookup. */
1379 static htab_t op_hash
;
1381 /* Hash table for register lookup. */
1382 static htab_t reg_hash
;
1384 /* Various efficient no-op patterns for aligning code labels.
1385 Note: Don't try to assemble the instructions in the comments.
1386 0L and 0w are not legal. */
1387 static const unsigned char f32_1
[] =
1389 static const unsigned char f32_2
[] =
1390 {0x66,0x90}; /* xchg %ax,%ax */
1391 static const unsigned char f32_3
[] =
1392 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1393 static const unsigned char f32_4
[] =
1394 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1395 static const unsigned char f32_6
[] =
1396 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1397 static const unsigned char f32_7
[] =
1398 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1399 static const unsigned char f16_3
[] =
1400 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1401 static const unsigned char f16_4
[] =
1402 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1403 static const unsigned char jump_disp8
[] =
1404 {0xeb}; /* jmp disp8 */
1405 static const unsigned char jump32_disp32
[] =
1406 {0xe9}; /* jmp disp32 */
1407 static const unsigned char jump16_disp32
[] =
1408 {0x66,0xe9}; /* jmp disp32 */
1409 /* 32-bit NOPs patterns. */
1410 static const unsigned char *const f32_patt
[] = {
1411 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1413 /* 16-bit NOPs patterns. */
1414 static const unsigned char *const f16_patt
[] = {
1415 f32_1
, f32_2
, f16_3
, f16_4
1417 /* nopl (%[re]ax) */
1418 static const unsigned char alt_3
[] =
1420 /* nopl 0(%[re]ax) */
1421 static const unsigned char alt_4
[] =
1422 {0x0f,0x1f,0x40,0x00};
1423 /* nopl 0(%[re]ax,%[re]ax,1) */
1424 static const unsigned char alt_5
[] =
1425 {0x0f,0x1f,0x44,0x00,0x00};
1426 /* nopw 0(%[re]ax,%[re]ax,1) */
1427 static const unsigned char alt_6
[] =
1428 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1429 /* nopl 0L(%[re]ax) */
1430 static const unsigned char alt_7
[] =
1431 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1432 /* nopl 0L(%[re]ax,%[re]ax,1) */
1433 static const unsigned char alt_8
[] =
1434 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1435 /* nopw 0L(%[re]ax,%[re]ax,1) */
1436 static const unsigned char alt_9
[] =
1437 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1438 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1439 static const unsigned char alt_10
[] =
1440 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1441 /* data16 nopw %cs:0L(%eax,%eax,1) */
1442 static const unsigned char alt_11
[] =
1443 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1444 /* 32-bit and 64-bit NOPs patterns. */
1445 static const unsigned char *const alt_patt
[] = {
1446 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1447 alt_9
, alt_10
, alt_11
1450 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1451 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1454 i386_output_nops (char *where
, const unsigned char *const *patt
,
1455 int count
, int max_single_nop_size
)
1458 /* Place the longer NOP first. */
1461 const unsigned char *nops
;
1463 if (max_single_nop_size
< 1)
1465 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1466 max_single_nop_size
);
1470 nops
= patt
[max_single_nop_size
- 1];
1472 /* Use the smaller one if the requsted one isn't available. */
1475 max_single_nop_size
--;
1476 nops
= patt
[max_single_nop_size
- 1];
1479 last
= count
% max_single_nop_size
;
1482 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1483 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1487 nops
= patt
[last
- 1];
1490 /* Use the smaller one plus one-byte NOP if the needed one
1493 nops
= patt
[last
- 1];
1494 memcpy (where
+ offset
, nops
, last
);
1495 where
[offset
+ last
] = *patt
[0];
1498 memcpy (where
+ offset
, nops
, last
);
1503 fits_in_imm7 (offsetT num
)
1505 return (num
& 0x7f) == num
;
1509 fits_in_imm31 (offsetT num
)
1511 return (num
& 0x7fffffff) == num
;
1514 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1515 single NOP instruction LIMIT. */
1518 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1520 const unsigned char *const *patt
= NULL
;
1521 int max_single_nop_size
;
1522 /* Maximum number of NOPs before switching to jump over NOPs. */
1523 int max_number_of_nops
;
1525 switch (fragP
->fr_type
)
1530 case rs_machine_dependent
:
1531 /* Allow NOP padding for jumps and calls. */
1532 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1533 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1540 /* We need to decide which NOP sequence to use for 32bit and
1541 64bit. When -mtune= is used:
1543 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1544 PROCESSOR_GENERIC32, f32_patt will be used.
1545 2. For the rest, alt_patt will be used.
1547 When -mtune= isn't used, alt_patt will be used if
1548 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1551 When -march= or .arch is used, we can't use anything beyond
1552 cpu_arch_isa_flags. */
1554 if (flag_code
== CODE_16BIT
)
1557 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1558 /* Limit number of NOPs to 2 in 16-bit mode. */
1559 max_number_of_nops
= 2;
1563 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1565 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1566 switch (cpu_arch_tune
)
1568 case PROCESSOR_UNKNOWN
:
1569 /* We use cpu_arch_isa_flags to check if we SHOULD
1570 optimize with nops. */
1571 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1576 case PROCESSOR_PENTIUM4
:
1577 case PROCESSOR_NOCONA
:
1578 case PROCESSOR_CORE
:
1579 case PROCESSOR_CORE2
:
1580 case PROCESSOR_COREI7
:
1581 case PROCESSOR_L1OM
:
1582 case PROCESSOR_K1OM
:
1583 case PROCESSOR_GENERIC64
:
1585 case PROCESSOR_ATHLON
:
1587 case PROCESSOR_AMDFAM10
:
1589 case PROCESSOR_ZNVER
:
1593 case PROCESSOR_I386
:
1594 case PROCESSOR_I486
:
1595 case PROCESSOR_PENTIUM
:
1596 case PROCESSOR_PENTIUMPRO
:
1597 case PROCESSOR_IAMCU
:
1598 case PROCESSOR_GENERIC32
:
1605 switch (fragP
->tc_frag_data
.tune
)
1607 case PROCESSOR_UNKNOWN
:
1608 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1609 PROCESSOR_UNKNOWN. */
1613 case PROCESSOR_I386
:
1614 case PROCESSOR_I486
:
1615 case PROCESSOR_PENTIUM
:
1616 case PROCESSOR_IAMCU
:
1618 case PROCESSOR_ATHLON
:
1620 case PROCESSOR_AMDFAM10
:
1622 case PROCESSOR_ZNVER
:
1624 case PROCESSOR_GENERIC32
:
1625 /* We use cpu_arch_isa_flags to check if we CAN optimize
1627 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1632 case PROCESSOR_PENTIUMPRO
:
1633 case PROCESSOR_PENTIUM4
:
1634 case PROCESSOR_NOCONA
:
1635 case PROCESSOR_CORE
:
1636 case PROCESSOR_CORE2
:
1637 case PROCESSOR_COREI7
:
1638 case PROCESSOR_L1OM
:
1639 case PROCESSOR_K1OM
:
1640 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1645 case PROCESSOR_GENERIC64
:
1651 if (patt
== f32_patt
)
1653 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1654 /* Limit number of NOPs to 2 for older processors. */
1655 max_number_of_nops
= 2;
1659 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1660 /* Limit number of NOPs to 7 for newer processors. */
1661 max_number_of_nops
= 7;
1666 limit
= max_single_nop_size
;
1668 if (fragP
->fr_type
== rs_fill_nop
)
1670 /* Output NOPs for .nop directive. */
1671 if (limit
> max_single_nop_size
)
1673 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1674 _("invalid single nop size: %d "
1675 "(expect within [0, %d])"),
1676 limit
, max_single_nop_size
);
1680 else if (fragP
->fr_type
!= rs_machine_dependent
)
1681 fragP
->fr_var
= count
;
1683 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1685 /* Generate jump over NOPs. */
1686 offsetT disp
= count
- 2;
1687 if (fits_in_imm7 (disp
))
1689 /* Use "jmp disp8" if possible. */
1691 where
[0] = jump_disp8
[0];
1697 unsigned int size_of_jump
;
1699 if (flag_code
== CODE_16BIT
)
1701 where
[0] = jump16_disp32
[0];
1702 where
[1] = jump16_disp32
[1];
1707 where
[0] = jump32_disp32
[0];
1711 count
-= size_of_jump
+ 4;
1712 if (!fits_in_imm31 (count
))
1714 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1715 _("jump over nop padding out of range"));
1719 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1720 where
+= size_of_jump
+ 4;
1724 /* Generate multiple NOPs. */
1725 i386_output_nops (where
, patt
, count
, limit
);
1729 operand_type_all_zero (const union i386_operand_type
*x
)
1731 switch (ARRAY_SIZE(x
->array
))
1742 return !x
->array
[0];
1749 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1751 switch (ARRAY_SIZE(x
->array
))
1767 x
->bitfield
.class = ClassNone
;
1768 x
->bitfield
.instance
= InstanceNone
;
1772 operand_type_equal (const union i386_operand_type
*x
,
1773 const union i386_operand_type
*y
)
1775 switch (ARRAY_SIZE(x
->array
))
1778 if (x
->array
[2] != y
->array
[2])
1782 if (x
->array
[1] != y
->array
[1])
1786 return x
->array
[0] == y
->array
[0];
1794 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1796 switch (ARRAY_SIZE(x
->array
))
1811 return !x
->array
[0];
1818 cpu_flags_equal (const union i386_cpu_flags
*x
,
1819 const union i386_cpu_flags
*y
)
1821 switch (ARRAY_SIZE(x
->array
))
1824 if (x
->array
[3] != y
->array
[3])
1828 if (x
->array
[2] != y
->array
[2])
1832 if (x
->array
[1] != y
->array
[1])
1836 return x
->array
[0] == y
->array
[0];
1844 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1846 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1847 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1850 static INLINE i386_cpu_flags
1851 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1853 switch (ARRAY_SIZE (x
.array
))
1856 x
.array
[3] &= y
.array
[3];
1859 x
.array
[2] &= y
.array
[2];
1862 x
.array
[1] &= y
.array
[1];
1865 x
.array
[0] &= y
.array
[0];
1873 static INLINE i386_cpu_flags
1874 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1876 switch (ARRAY_SIZE (x
.array
))
1879 x
.array
[3] |= y
.array
[3];
1882 x
.array
[2] |= y
.array
[2];
1885 x
.array
[1] |= y
.array
[1];
1888 x
.array
[0] |= y
.array
[0];
1896 static INLINE i386_cpu_flags
1897 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1899 switch (ARRAY_SIZE (x
.array
))
1902 x
.array
[3] &= ~y
.array
[3];
1905 x
.array
[2] &= ~y
.array
[2];
1908 x
.array
[1] &= ~y
.array
[1];
1911 x
.array
[0] &= ~y
.array
[0];
1919 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1921 #define CPU_FLAGS_ARCH_MATCH 0x1
1922 #define CPU_FLAGS_64BIT_MATCH 0x2
1924 #define CPU_FLAGS_PERFECT_MATCH \
1925 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1927 /* Return CPU flags match bits. */
1930 cpu_flags_match (const insn_template
*t
)
1932 i386_cpu_flags x
= t
->cpu_flags
;
1933 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1935 x
.bitfield
.cpu64
= 0;
1936 x
.bitfield
.cpuno64
= 0;
1938 if (cpu_flags_all_zero (&x
))
1940 /* This instruction is available on all archs. */
1941 match
|= CPU_FLAGS_ARCH_MATCH
;
1945 /* This instruction is available only on some archs. */
1946 i386_cpu_flags cpu
= cpu_arch_flags
;
1948 /* AVX512VL is no standalone feature - match it and then strip it. */
1949 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1951 x
.bitfield
.cpuavx512vl
= 0;
1953 cpu
= cpu_flags_and (x
, cpu
);
1954 if (!cpu_flags_all_zero (&cpu
))
1956 if (x
.bitfield
.cpuavx
)
1958 /* We need to check a few extra flags with AVX. */
1959 if (cpu
.bitfield
.cpuavx
1960 && (!t
->opcode_modifier
.sse2avx
1961 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1962 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1963 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1964 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1965 match
|= CPU_FLAGS_ARCH_MATCH
;
1967 else if (x
.bitfield
.cpuavx512f
)
1969 /* We need to check a few extra flags with AVX512F. */
1970 if (cpu
.bitfield
.cpuavx512f
1971 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1972 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1973 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1974 match
|= CPU_FLAGS_ARCH_MATCH
;
1977 match
|= CPU_FLAGS_ARCH_MATCH
;
1983 static INLINE i386_operand_type
1984 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1986 if (x
.bitfield
.class != y
.bitfield
.class)
1987 x
.bitfield
.class = ClassNone
;
1988 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1989 x
.bitfield
.instance
= InstanceNone
;
1991 switch (ARRAY_SIZE (x
.array
))
1994 x
.array
[2] &= y
.array
[2];
1997 x
.array
[1] &= y
.array
[1];
2000 x
.array
[0] &= y
.array
[0];
2008 static INLINE i386_operand_type
2009 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2011 gas_assert (y
.bitfield
.class == ClassNone
);
2012 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2014 switch (ARRAY_SIZE (x
.array
))
2017 x
.array
[2] &= ~y
.array
[2];
2020 x
.array
[1] &= ~y
.array
[1];
2023 x
.array
[0] &= ~y
.array
[0];
2031 static INLINE i386_operand_type
2032 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2034 gas_assert (x
.bitfield
.class == ClassNone
||
2035 y
.bitfield
.class == ClassNone
||
2036 x
.bitfield
.class == y
.bitfield
.class);
2037 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2038 y
.bitfield
.instance
== InstanceNone
||
2039 x
.bitfield
.instance
== y
.bitfield
.instance
);
2041 switch (ARRAY_SIZE (x
.array
))
2044 x
.array
[2] |= y
.array
[2];
2047 x
.array
[1] |= y
.array
[1];
2050 x
.array
[0] |= y
.array
[0];
2058 static INLINE i386_operand_type
2059 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2061 gas_assert (y
.bitfield
.class == ClassNone
);
2062 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2064 switch (ARRAY_SIZE (x
.array
))
2067 x
.array
[2] ^= y
.array
[2];
2070 x
.array
[1] ^= y
.array
[1];
2073 x
.array
[0] ^= y
.array
[0];
2081 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2082 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2083 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2084 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2085 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2086 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2087 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2088 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2089 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2090 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2091 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2092 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2093 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2094 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2095 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2096 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2097 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2108 operand_type_check (i386_operand_type t
, enum operand_type c
)
2113 return t
.bitfield
.class == Reg
;
2116 return (t
.bitfield
.imm8
2120 || t
.bitfield
.imm32s
2121 || t
.bitfield
.imm64
);
2124 return (t
.bitfield
.disp8
2125 || t
.bitfield
.disp16
2126 || t
.bitfield
.disp32
2127 || t
.bitfield
.disp32s
2128 || t
.bitfield
.disp64
);
2131 return (t
.bitfield
.disp8
2132 || t
.bitfield
.disp16
2133 || t
.bitfield
.disp32
2134 || t
.bitfield
.disp32s
2135 || t
.bitfield
.disp64
2136 || t
.bitfield
.baseindex
);
2145 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2146 between operand GIVEN and opeand WANTED for instruction template T. */
2149 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2152 return !((i
.types
[given
].bitfield
.byte
2153 && !t
->operand_types
[wanted
].bitfield
.byte
)
2154 || (i
.types
[given
].bitfield
.word
2155 && !t
->operand_types
[wanted
].bitfield
.word
)
2156 || (i
.types
[given
].bitfield
.dword
2157 && !t
->operand_types
[wanted
].bitfield
.dword
)
2158 || (i
.types
[given
].bitfield
.qword
2159 && !t
->operand_types
[wanted
].bitfield
.qword
)
2160 || (i
.types
[given
].bitfield
.tbyte
2161 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2164 /* Return 1 if there is no conflict in SIMD register between operand
2165 GIVEN and opeand WANTED for instruction template T. */
2168 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2171 return !((i
.types
[given
].bitfield
.xmmword
2172 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2173 || (i
.types
[given
].bitfield
.ymmword
2174 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2175 || (i
.types
[given
].bitfield
.zmmword
2176 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2177 || (i
.types
[given
].bitfield
.tmmword
2178 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2181 /* Return 1 if there is no conflict in any size between operand GIVEN
2182 and opeand WANTED for instruction template T. */
2185 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2188 return (match_operand_size (t
, wanted
, given
)
2189 && !((i
.types
[given
].bitfield
.unspecified
2191 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2192 || (i
.types
[given
].bitfield
.fword
2193 && !t
->operand_types
[wanted
].bitfield
.fword
)
2194 /* For scalar opcode templates to allow register and memory
2195 operands at the same time, some special casing is needed
2196 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2197 down-conversion vpmov*. */
2198 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2199 && t
->operand_types
[wanted
].bitfield
.byte
2200 + t
->operand_types
[wanted
].bitfield
.word
2201 + t
->operand_types
[wanted
].bitfield
.dword
2202 + t
->operand_types
[wanted
].bitfield
.qword
2203 > !!t
->opcode_modifier
.broadcast
)
2204 ? (i
.types
[given
].bitfield
.xmmword
2205 || i
.types
[given
].bitfield
.ymmword
2206 || i
.types
[given
].bitfield
.zmmword
)
2207 : !match_simd_size(t
, wanted
, given
))));
2210 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2211 operands for instruction template T, and it has MATCH_REVERSE set if there
2212 is no size conflict on any operands for the template with operands reversed
2213 (and the template allows for reversing in the first place). */
2215 #define MATCH_STRAIGHT 1
2216 #define MATCH_REVERSE 2
2218 static INLINE
unsigned int
2219 operand_size_match (const insn_template
*t
)
2221 unsigned int j
, match
= MATCH_STRAIGHT
;
2223 /* Don't check non-absolute jump instructions. */
2224 if (t
->opcode_modifier
.jump
2225 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2228 /* Check memory and accumulator operand size. */
2229 for (j
= 0; j
< i
.operands
; j
++)
2231 if (i
.types
[j
].bitfield
.class != Reg
2232 && i
.types
[j
].bitfield
.class != RegSIMD
2233 && t
->opcode_modifier
.anysize
)
2236 if (t
->operand_types
[j
].bitfield
.class == Reg
2237 && !match_operand_size (t
, j
, j
))
2243 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2244 && !match_simd_size (t
, j
, j
))
2250 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2251 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2257 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2264 if (!t
->opcode_modifier
.d
)
2268 i
.error
= operand_size_mismatch
;
2272 /* Check reverse. */
2273 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2275 for (j
= 0; j
< i
.operands
; j
++)
2277 unsigned int given
= i
.operands
- j
- 1;
2279 if (t
->operand_types
[j
].bitfield
.class == Reg
2280 && !match_operand_size (t
, j
, given
))
2283 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2284 && !match_simd_size (t
, j
, given
))
2287 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2288 && (!match_operand_size (t
, j
, given
)
2289 || !match_simd_size (t
, j
, given
)))
2292 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2296 return match
| MATCH_REVERSE
;
2300 operand_type_match (i386_operand_type overlap
,
2301 i386_operand_type given
)
2303 i386_operand_type temp
= overlap
;
2305 temp
.bitfield
.unspecified
= 0;
2306 temp
.bitfield
.byte
= 0;
2307 temp
.bitfield
.word
= 0;
2308 temp
.bitfield
.dword
= 0;
2309 temp
.bitfield
.fword
= 0;
2310 temp
.bitfield
.qword
= 0;
2311 temp
.bitfield
.tbyte
= 0;
2312 temp
.bitfield
.xmmword
= 0;
2313 temp
.bitfield
.ymmword
= 0;
2314 temp
.bitfield
.zmmword
= 0;
2315 temp
.bitfield
.tmmword
= 0;
2316 if (operand_type_all_zero (&temp
))
2319 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2323 i
.error
= operand_type_mismatch
;
2327 /* If given types g0 and g1 are registers they must be of the same type
2328 unless the expected operand type register overlap is null.
2329 Some Intel syntax memory operand size checking also happens here. */
2332 operand_type_register_match (i386_operand_type g0
,
2333 i386_operand_type t0
,
2334 i386_operand_type g1
,
2335 i386_operand_type t1
)
2337 if (g0
.bitfield
.class != Reg
2338 && g0
.bitfield
.class != RegSIMD
2339 && (!operand_type_check (g0
, anymem
)
2340 || g0
.bitfield
.unspecified
2341 || (t0
.bitfield
.class != Reg
2342 && t0
.bitfield
.class != RegSIMD
)))
2345 if (g1
.bitfield
.class != Reg
2346 && g1
.bitfield
.class != RegSIMD
2347 && (!operand_type_check (g1
, anymem
)
2348 || g1
.bitfield
.unspecified
2349 || (t1
.bitfield
.class != Reg
2350 && t1
.bitfield
.class != RegSIMD
)))
2353 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2354 && g0
.bitfield
.word
== g1
.bitfield
.word
2355 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2356 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2357 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2358 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2359 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2362 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2363 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2364 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2365 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2366 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2367 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2368 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2371 i
.error
= register_type_mismatch
;
2376 static INLINE
unsigned int
2377 register_number (const reg_entry
*r
)
2379 unsigned int nr
= r
->reg_num
;
2381 if (r
->reg_flags
& RegRex
)
2384 if (r
->reg_flags
& RegVRex
)
2390 static INLINE
unsigned int
2391 mode_from_disp_size (i386_operand_type t
)
2393 if (t
.bitfield
.disp8
)
2395 else if (t
.bitfield
.disp16
2396 || t
.bitfield
.disp32
2397 || t
.bitfield
.disp32s
)
2404 fits_in_signed_byte (addressT num
)
2406 return num
+ 0x80 <= 0xff;
2410 fits_in_unsigned_byte (addressT num
)
2416 fits_in_unsigned_word (addressT num
)
2418 return num
<= 0xffff;
2422 fits_in_signed_word (addressT num
)
2424 return num
+ 0x8000 <= 0xffff;
2428 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2433 return num
+ 0x80000000 <= 0xffffffff;
2435 } /* fits_in_signed_long() */
2438 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2443 return num
<= 0xffffffff;
2445 } /* fits_in_unsigned_long() */
2448 fits_in_disp8 (offsetT num
)
2450 int shift
= i
.memshift
;
2456 mask
= (1 << shift
) - 1;
2458 /* Return 0 if NUM isn't properly aligned. */
2462 /* Check if NUM will fit in 8bit after shift. */
2463 return fits_in_signed_byte (num
>> shift
);
2467 fits_in_imm4 (offsetT num
)
2469 return (num
& 0xf) == num
;
2472 static i386_operand_type
2473 smallest_imm_type (offsetT num
)
2475 i386_operand_type t
;
2477 operand_type_set (&t
, 0);
2478 t
.bitfield
.imm64
= 1;
2480 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2482 /* This code is disabled on the 486 because all the Imm1 forms
2483 in the opcode table are slower on the i486. They're the
2484 versions with the implicitly specified single-position
2485 displacement, which has another syntax if you really want to
2487 t
.bitfield
.imm1
= 1;
2488 t
.bitfield
.imm8
= 1;
2489 t
.bitfield
.imm8s
= 1;
2490 t
.bitfield
.imm16
= 1;
2491 t
.bitfield
.imm32
= 1;
2492 t
.bitfield
.imm32s
= 1;
2494 else if (fits_in_signed_byte (num
))
2496 t
.bitfield
.imm8
= 1;
2497 t
.bitfield
.imm8s
= 1;
2498 t
.bitfield
.imm16
= 1;
2499 t
.bitfield
.imm32
= 1;
2500 t
.bitfield
.imm32s
= 1;
2502 else if (fits_in_unsigned_byte (num
))
2504 t
.bitfield
.imm8
= 1;
2505 t
.bitfield
.imm16
= 1;
2506 t
.bitfield
.imm32
= 1;
2507 t
.bitfield
.imm32s
= 1;
2509 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2511 t
.bitfield
.imm16
= 1;
2512 t
.bitfield
.imm32
= 1;
2513 t
.bitfield
.imm32s
= 1;
2515 else if (fits_in_signed_long (num
))
2517 t
.bitfield
.imm32
= 1;
2518 t
.bitfield
.imm32s
= 1;
2520 else if (fits_in_unsigned_long (num
))
2521 t
.bitfield
.imm32
= 1;
2527 offset_in_range (offsetT val
, int size
)
2533 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2534 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2535 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2537 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2542 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2544 char buf1
[40], buf2
[40];
2546 sprint_value (buf1
, val
);
2547 sprint_value (buf2
, val
& mask
);
2548 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2563 a. PREFIX_EXIST if attempting to add a prefix where one from the
2564 same class already exists.
2565 b. PREFIX_LOCK if lock prefix is added.
2566 c. PREFIX_REP if rep/repne prefix is added.
2567 d. PREFIX_DS if ds prefix is added.
2568 e. PREFIX_OTHER if other prefix is added.
2571 static enum PREFIX_GROUP
2572 add_prefix (unsigned int prefix
)
2574 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2577 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2578 && flag_code
== CODE_64BIT
)
2580 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2581 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2582 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2583 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2594 case DS_PREFIX_OPCODE
:
2597 case CS_PREFIX_OPCODE
:
2598 case ES_PREFIX_OPCODE
:
2599 case FS_PREFIX_OPCODE
:
2600 case GS_PREFIX_OPCODE
:
2601 case SS_PREFIX_OPCODE
:
2605 case REPNE_PREFIX_OPCODE
:
2606 case REPE_PREFIX_OPCODE
:
2611 case LOCK_PREFIX_OPCODE
:
2620 case ADDR_PREFIX_OPCODE
:
2624 case DATA_PREFIX_OPCODE
:
2628 if (i
.prefix
[q
] != 0)
2636 i
.prefix
[q
] |= prefix
;
2639 as_bad (_("same type of prefix used twice"));
2645 update_code_flag (int value
, int check
)
2647 PRINTF_LIKE ((*as_error
));
2649 flag_code
= (enum flag_code
) value
;
2650 if (flag_code
== CODE_64BIT
)
2652 cpu_arch_flags
.bitfield
.cpu64
= 1;
2653 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2657 cpu_arch_flags
.bitfield
.cpu64
= 0;
2658 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2660 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2663 as_error
= as_fatal
;
2666 (*as_error
) (_("64bit mode not supported on `%s'."),
2667 cpu_arch_name
? cpu_arch_name
: default_arch
);
2669 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2672 as_error
= as_fatal
;
2675 (*as_error
) (_("32bit mode not supported on `%s'."),
2676 cpu_arch_name
? cpu_arch_name
: default_arch
);
2678 stackop_size
= '\0';
2682 set_code_flag (int value
)
2684 update_code_flag (value
, 0);
2688 set_16bit_gcc_code_flag (int new_code_flag
)
2690 flag_code
= (enum flag_code
) new_code_flag
;
2691 if (flag_code
!= CODE_16BIT
)
2693 cpu_arch_flags
.bitfield
.cpu64
= 0;
2694 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2695 stackop_size
= LONG_MNEM_SUFFIX
;
2699 set_intel_syntax (int syntax_flag
)
2701 /* Find out if register prefixing is specified. */
2702 int ask_naked_reg
= 0;
2705 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2708 int e
= get_symbol_name (&string
);
2710 if (strcmp (string
, "prefix") == 0)
2712 else if (strcmp (string
, "noprefix") == 0)
2715 as_bad (_("bad argument to syntax directive."));
2716 (void) restore_line_pointer (e
);
2718 demand_empty_rest_of_line ();
2720 intel_syntax
= syntax_flag
;
2722 if (ask_naked_reg
== 0)
2723 allow_naked_reg
= (intel_syntax
2724 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2726 allow_naked_reg
= (ask_naked_reg
< 0);
2728 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2730 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2731 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2732 register_prefix
= allow_naked_reg
? "" : "%";
2736 set_intel_mnemonic (int mnemonic_flag
)
2738 intel_mnemonic
= mnemonic_flag
;
2742 set_allow_index_reg (int flag
)
2744 allow_index_reg
= flag
;
2748 set_check (int what
)
2750 enum check_kind
*kind
;
2755 kind
= &operand_check
;
2766 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2769 int e
= get_symbol_name (&string
);
2771 if (strcmp (string
, "none") == 0)
2773 else if (strcmp (string
, "warning") == 0)
2774 *kind
= check_warning
;
2775 else if (strcmp (string
, "error") == 0)
2776 *kind
= check_error
;
2778 as_bad (_("bad argument to %s_check directive."), str
);
2779 (void) restore_line_pointer (e
);
2782 as_bad (_("missing argument for %s_check directive"), str
);
2784 demand_empty_rest_of_line ();
2788 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2789 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2791 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2792 static const char *arch
;
2794 /* Intel LIOM is only supported on ELF. */
2800 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2801 use default_arch. */
2802 arch
= cpu_arch_name
;
2804 arch
= default_arch
;
2807 /* If we are targeting Intel MCU, we must enable it. */
2808 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2809 || new_flag
.bitfield
.cpuiamcu
)
2812 /* If we are targeting Intel L1OM, we must enable it. */
2813 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2814 || new_flag
.bitfield
.cpul1om
)
2817 /* If we are targeting Intel K1OM, we must enable it. */
2818 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2819 || new_flag
.bitfield
.cpuk1om
)
2822 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2827 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2831 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2834 int e
= get_symbol_name (&string
);
2836 i386_cpu_flags flags
;
2838 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2840 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2842 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2846 cpu_arch_name
= cpu_arch
[j
].name
;
2847 cpu_sub_arch_name
= NULL
;
2848 cpu_arch_flags
= cpu_arch
[j
].flags
;
2849 if (flag_code
== CODE_64BIT
)
2851 cpu_arch_flags
.bitfield
.cpu64
= 1;
2852 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2856 cpu_arch_flags
.bitfield
.cpu64
= 0;
2857 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2859 cpu_arch_isa
= cpu_arch
[j
].type
;
2860 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2861 if (!cpu_arch_tune_set
)
2863 cpu_arch_tune
= cpu_arch_isa
;
2864 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2869 flags
= cpu_flags_or (cpu_arch_flags
,
2872 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2874 if (cpu_sub_arch_name
)
2876 char *name
= cpu_sub_arch_name
;
2877 cpu_sub_arch_name
= concat (name
,
2879 (const char *) NULL
);
2883 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2884 cpu_arch_flags
= flags
;
2885 cpu_arch_isa_flags
= flags
;
2889 = cpu_flags_or (cpu_arch_isa_flags
,
2891 (void) restore_line_pointer (e
);
2892 demand_empty_rest_of_line ();
2897 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2899 /* Disable an ISA extension. */
2900 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2901 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2903 flags
= cpu_flags_and_not (cpu_arch_flags
,
2904 cpu_noarch
[j
].flags
);
2905 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2907 if (cpu_sub_arch_name
)
2909 char *name
= cpu_sub_arch_name
;
2910 cpu_sub_arch_name
= concat (name
, string
,
2911 (const char *) NULL
);
2915 cpu_sub_arch_name
= xstrdup (string
);
2916 cpu_arch_flags
= flags
;
2917 cpu_arch_isa_flags
= flags
;
2919 (void) restore_line_pointer (e
);
2920 demand_empty_rest_of_line ();
2924 j
= ARRAY_SIZE (cpu_arch
);
2927 if (j
>= ARRAY_SIZE (cpu_arch
))
2928 as_bad (_("no such architecture: `%s'"), string
);
2930 *input_line_pointer
= e
;
2933 as_bad (_("missing cpu architecture"));
2935 no_cond_jump_promotion
= 0;
2936 if (*input_line_pointer
== ','
2937 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2942 ++input_line_pointer
;
2943 e
= get_symbol_name (&string
);
2945 if (strcmp (string
, "nojumps") == 0)
2946 no_cond_jump_promotion
= 1;
2947 else if (strcmp (string
, "jumps") == 0)
2950 as_bad (_("no such architecture modifier: `%s'"), string
);
2952 (void) restore_line_pointer (e
);
2955 demand_empty_rest_of_line ();
2958 enum bfd_architecture
2961 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2963 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2964 || flag_code
!= CODE_64BIT
)
2965 as_fatal (_("Intel L1OM is 64bit ELF only"));
2966 return bfd_arch_l1om
;
2968 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2970 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2971 || flag_code
!= CODE_64BIT
)
2972 as_fatal (_("Intel K1OM is 64bit ELF only"));
2973 return bfd_arch_k1om
;
2975 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2977 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2978 || flag_code
== CODE_64BIT
)
2979 as_fatal (_("Intel MCU is 32bit ELF only"));
2980 return bfd_arch_iamcu
;
2983 return bfd_arch_i386
;
2989 if (!strncmp (default_arch
, "x86_64", 6))
2991 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2993 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2994 || default_arch
[6] != '\0')
2995 as_fatal (_("Intel L1OM is 64bit ELF only"));
2996 return bfd_mach_l1om
;
2998 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3000 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3001 || default_arch
[6] != '\0')
3002 as_fatal (_("Intel K1OM is 64bit ELF only"));
3003 return bfd_mach_k1om
;
3005 else if (default_arch
[6] == '\0')
3006 return bfd_mach_x86_64
;
3008 return bfd_mach_x64_32
;
3010 else if (!strcmp (default_arch
, "i386")
3011 || !strcmp (default_arch
, "iamcu"))
3013 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3015 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3016 as_fatal (_("Intel MCU is 32bit ELF only"));
3017 return bfd_mach_i386_iamcu
;
3020 return bfd_mach_i386_i386
;
3023 as_fatal (_("unknown architecture"));
3029 /* Support pseudo prefixes like {disp32}. */
3030 lex_type
['{'] = LEX_BEGIN_NAME
;
3032 /* Initialize op_hash hash table. */
3033 op_hash
= str_htab_create ();
3036 const insn_template
*optab
;
3037 templates
*core_optab
;
3039 /* Setup for loop. */
3041 core_optab
= XNEW (templates
);
3042 core_optab
->start
= optab
;
3047 if (optab
->name
== NULL
3048 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3050 /* different name --> ship out current template list;
3051 add to hash table; & begin anew. */
3052 core_optab
->end
= optab
;
3053 str_hash_insert (op_hash
, (optab
- 1)->name
, (void *) core_optab
);
3054 if (optab
->name
== NULL
)
3056 core_optab
= XNEW (templates
);
3057 core_optab
->start
= optab
;
3062 /* Initialize reg_hash hash table. */
3063 reg_hash
= str_htab_create ();
3065 const reg_entry
*regtab
;
3066 unsigned int regtab_size
= i386_regtab_size
;
3068 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3069 str_hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3072 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3077 for (c
= 0; c
< 256; c
++)
3082 mnemonic_chars
[c
] = c
;
3083 register_chars
[c
] = c
;
3084 operand_chars
[c
] = c
;
3086 else if (ISLOWER (c
))
3088 mnemonic_chars
[c
] = c
;
3089 register_chars
[c
] = c
;
3090 operand_chars
[c
] = c
;
3092 else if (ISUPPER (c
))
3094 mnemonic_chars
[c
] = TOLOWER (c
);
3095 register_chars
[c
] = mnemonic_chars
[c
];
3096 operand_chars
[c
] = c
;
3098 else if (c
== '{' || c
== '}')
3100 mnemonic_chars
[c
] = c
;
3101 operand_chars
[c
] = c
;
3103 #ifdef SVR4_COMMENT_CHARS
3104 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3105 operand_chars
[c
] = c
;
3108 if (ISALPHA (c
) || ISDIGIT (c
))
3109 identifier_chars
[c
] = c
;
3112 identifier_chars
[c
] = c
;
3113 operand_chars
[c
] = c
;
3118 identifier_chars
['@'] = '@';
3121 identifier_chars
['?'] = '?';
3122 operand_chars
['?'] = '?';
3124 digit_chars
['-'] = '-';
3125 mnemonic_chars
['_'] = '_';
3126 mnemonic_chars
['-'] = '-';
3127 mnemonic_chars
['.'] = '.';
3128 identifier_chars
['_'] = '_';
3129 identifier_chars
['.'] = '.';
3131 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3132 operand_chars
[(unsigned char) *p
] = *p
;
3135 if (flag_code
== CODE_64BIT
)
3137 #if defined (OBJ_COFF) && defined (TE_PE)
3138 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3141 x86_dwarf2_return_column
= 16;
3143 x86_cie_data_alignment
= -8;
3147 x86_dwarf2_return_column
= 8;
3148 x86_cie_data_alignment
= -4;
3151 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3152 can be turned into BRANCH_PREFIX frag. */
3153 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3158 i386_print_statistics (FILE *file
)
3160 htab_print_statistics (file
, "i386 opcode", op_hash
);
3161 htab_print_statistics (file
, "i386 register", reg_hash
);
3166 /* Debugging routines for md_assemble. */
3167 static void pte (insn_template
*);
3168 static void pt (i386_operand_type
);
3169 static void pe (expressionS
*);
3170 static void ps (symbolS
*);
3173 pi (const char *line
, i386_insn
*x
)
3177 fprintf (stdout
, "%s: template ", line
);
3179 fprintf (stdout
, " address: base %s index %s scale %x\n",
3180 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3181 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3182 x
->log2_scale_factor
);
3183 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3184 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3185 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3186 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3187 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3188 (x
->rex
& REX_W
) != 0,
3189 (x
->rex
& REX_R
) != 0,
3190 (x
->rex
& REX_X
) != 0,
3191 (x
->rex
& REX_B
) != 0);
3192 for (j
= 0; j
< x
->operands
; j
++)
3194 fprintf (stdout
, " #%d: ", j
+ 1);
3196 fprintf (stdout
, "\n");
3197 if (x
->types
[j
].bitfield
.class == Reg
3198 || x
->types
[j
].bitfield
.class == RegMMX
3199 || x
->types
[j
].bitfield
.class == RegSIMD
3200 || x
->types
[j
].bitfield
.class == RegMask
3201 || x
->types
[j
].bitfield
.class == SReg
3202 || x
->types
[j
].bitfield
.class == RegCR
3203 || x
->types
[j
].bitfield
.class == RegDR
3204 || x
->types
[j
].bitfield
.class == RegTR
3205 || x
->types
[j
].bitfield
.class == RegBND
)
3206 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3207 if (operand_type_check (x
->types
[j
], imm
))
3209 if (operand_type_check (x
->types
[j
], disp
))
3210 pe (x
->op
[j
].disps
);
3215 pte (insn_template
*t
)
3218 fprintf (stdout
, " %d operands ", t
->operands
);
3219 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3220 if (t
->extension_opcode
!= None
)
3221 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3222 if (t
->opcode_modifier
.d
)
3223 fprintf (stdout
, "D");
3224 if (t
->opcode_modifier
.w
)
3225 fprintf (stdout
, "W");
3226 fprintf (stdout
, "\n");
3227 for (j
= 0; j
< t
->operands
; j
++)
3229 fprintf (stdout
, " #%d type ", j
+ 1);
3230 pt (t
->operand_types
[j
]);
3231 fprintf (stdout
, "\n");
3238 fprintf (stdout
, " operation %d\n", e
->X_op
);
3239 fprintf (stdout
, " add_number %ld (%lx)\n",
3240 (long) e
->X_add_number
, (long) e
->X_add_number
);
3241 if (e
->X_add_symbol
)
3243 fprintf (stdout
, " add_symbol ");
3244 ps (e
->X_add_symbol
);
3245 fprintf (stdout
, "\n");
3249 fprintf (stdout
, " op_symbol ");
3250 ps (e
->X_op_symbol
);
3251 fprintf (stdout
, "\n");
3258 fprintf (stdout
, "%s type %s%s",
3260 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3261 segment_name (S_GET_SEGMENT (s
)));
3264 static struct type_name
3266 i386_operand_type mask
;
3269 const type_names
[] =
3271 { OPERAND_TYPE_REG8
, "r8" },
3272 { OPERAND_TYPE_REG16
, "r16" },
3273 { OPERAND_TYPE_REG32
, "r32" },
3274 { OPERAND_TYPE_REG64
, "r64" },
3275 { OPERAND_TYPE_ACC8
, "acc8" },
3276 { OPERAND_TYPE_ACC16
, "acc16" },
3277 { OPERAND_TYPE_ACC32
, "acc32" },
3278 { OPERAND_TYPE_ACC64
, "acc64" },
3279 { OPERAND_TYPE_IMM8
, "i8" },
3280 { OPERAND_TYPE_IMM8
, "i8s" },
3281 { OPERAND_TYPE_IMM16
, "i16" },
3282 { OPERAND_TYPE_IMM32
, "i32" },
3283 { OPERAND_TYPE_IMM32S
, "i32s" },
3284 { OPERAND_TYPE_IMM64
, "i64" },
3285 { OPERAND_TYPE_IMM1
, "i1" },
3286 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3287 { OPERAND_TYPE_DISP8
, "d8" },
3288 { OPERAND_TYPE_DISP16
, "d16" },
3289 { OPERAND_TYPE_DISP32
, "d32" },
3290 { OPERAND_TYPE_DISP32S
, "d32s" },
3291 { OPERAND_TYPE_DISP64
, "d64" },
3292 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3293 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3294 { OPERAND_TYPE_CONTROL
, "control reg" },
3295 { OPERAND_TYPE_TEST
, "test reg" },
3296 { OPERAND_TYPE_DEBUG
, "debug reg" },
3297 { OPERAND_TYPE_FLOATREG
, "FReg" },
3298 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3299 { OPERAND_TYPE_SREG
, "SReg" },
3300 { OPERAND_TYPE_REGMMX
, "rMMX" },
3301 { OPERAND_TYPE_REGXMM
, "rXMM" },
3302 { OPERAND_TYPE_REGYMM
, "rYMM" },
3303 { OPERAND_TYPE_REGZMM
, "rZMM" },
3304 { OPERAND_TYPE_REGTMM
, "rTMM" },
3305 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3309 pt (i386_operand_type t
)
3312 i386_operand_type a
;
3314 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3316 a
= operand_type_and (t
, type_names
[j
].mask
);
3317 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3318 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3323 #endif /* DEBUG386 */
3325 static bfd_reloc_code_real_type
3326 reloc (unsigned int size
,
3329 bfd_reloc_code_real_type other
)
3331 if (other
!= NO_RELOC
)
3333 reloc_howto_type
*rel
;
3338 case BFD_RELOC_X86_64_GOT32
:
3339 return BFD_RELOC_X86_64_GOT64
;
3341 case BFD_RELOC_X86_64_GOTPLT64
:
3342 return BFD_RELOC_X86_64_GOTPLT64
;
3344 case BFD_RELOC_X86_64_PLTOFF64
:
3345 return BFD_RELOC_X86_64_PLTOFF64
;
3347 case BFD_RELOC_X86_64_GOTPC32
:
3348 other
= BFD_RELOC_X86_64_GOTPC64
;
3350 case BFD_RELOC_X86_64_GOTPCREL
:
3351 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3353 case BFD_RELOC_X86_64_TPOFF32
:
3354 other
= BFD_RELOC_X86_64_TPOFF64
;
3356 case BFD_RELOC_X86_64_DTPOFF32
:
3357 other
= BFD_RELOC_X86_64_DTPOFF64
;
3363 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3364 if (other
== BFD_RELOC_SIZE32
)
3367 other
= BFD_RELOC_SIZE64
;
3370 as_bad (_("there are no pc-relative size relocations"));
3376 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3377 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3380 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3382 as_bad (_("unknown relocation (%u)"), other
);
3383 else if (size
!= bfd_get_reloc_size (rel
))
3384 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3385 bfd_get_reloc_size (rel
),
3387 else if (pcrel
&& !rel
->pc_relative
)
3388 as_bad (_("non-pc-relative relocation for pc-relative field"));
3389 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3391 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3393 as_bad (_("relocated field and relocation type differ in signedness"));
3402 as_bad (_("there are no unsigned pc-relative relocations"));
3405 case 1: return BFD_RELOC_8_PCREL
;
3406 case 2: return BFD_RELOC_16_PCREL
;
3407 case 4: return BFD_RELOC_32_PCREL
;
3408 case 8: return BFD_RELOC_64_PCREL
;
3410 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3417 case 4: return BFD_RELOC_X86_64_32S
;
3422 case 1: return BFD_RELOC_8
;
3423 case 2: return BFD_RELOC_16
;
3424 case 4: return BFD_RELOC_32
;
3425 case 8: return BFD_RELOC_64
;
3427 as_bad (_("cannot do %s %u byte relocation"),
3428 sign
> 0 ? "signed" : "unsigned", size
);
3434 /* Here we decide which fixups can be adjusted to make them relative to
3435 the beginning of the section instead of the symbol. Basically we need
3436 to make sure that the dynamic relocations are done correctly, so in
3437 some cases we force the original symbol to be used. */
3440 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3442 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3446 /* Don't adjust pc-relative references to merge sections in 64-bit
3448 if (use_rela_relocations
3449 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3453 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3454 and changed later by validate_fix. */
3455 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3456 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3459 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3460 for size relocations. */
3461 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3462 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3463 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3464 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3465 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3466 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3467 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3468 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3470 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3471 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3472 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3473 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3474 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3475 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3476 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3477 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3478 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3483 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3484 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3485 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3487 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3488 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3489 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3490 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3491 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3498 intel_float_operand (const char *mnemonic
)
3500 /* Note that the value returned is meaningful only for opcodes with (memory)
3501 operands, hence the code here is free to improperly handle opcodes that
3502 have no operands (for better performance and smaller code). */
3504 if (mnemonic
[0] != 'f')
3505 return 0; /* non-math */
3507 switch (mnemonic
[1])
3509 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3510 the fs segment override prefix not currently handled because no
3511 call path can make opcodes without operands get here */
3513 return 2 /* integer op */;
3515 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3516 return 3; /* fldcw/fldenv */
3519 if (mnemonic
[2] != 'o' /* fnop */)
3520 return 3; /* non-waiting control op */
3523 if (mnemonic
[2] == 's')
3524 return 3; /* frstor/frstpm */
3527 if (mnemonic
[2] == 'a')
3528 return 3; /* fsave */
3529 if (mnemonic
[2] == 't')
3531 switch (mnemonic
[3])
3533 case 'c': /* fstcw */
3534 case 'd': /* fstdw */
3535 case 'e': /* fstenv */
3536 case 's': /* fsts[gw] */
3542 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3543 return 0; /* fxsave/fxrstor are not really math ops */
3550 /* Build the VEX prefix. */
3553 build_vex_prefix (const insn_template
*t
)
3555 unsigned int register_specifier
;
3556 unsigned int implied_prefix
;
3557 unsigned int vector_length
;
3560 /* Check register specifier. */
3561 if (i
.vex
.register_specifier
)
3563 register_specifier
=
3564 ~register_number (i
.vex
.register_specifier
) & 0xf;
3565 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3568 register_specifier
= 0xf;
3570 /* Use 2-byte VEX prefix by swapping destination and source operand
3571 if there are more than 1 register operand. */
3572 if (i
.reg_operands
> 1
3573 && i
.vec_encoding
!= vex_encoding_vex3
3574 && i
.dir_encoding
== dir_encoding_default
3575 && i
.operands
== i
.reg_operands
3576 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3577 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3578 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3581 unsigned int xchg
= i
.operands
- 1;
3582 union i386_op temp_op
;
3583 i386_operand_type temp_type
;
3585 temp_type
= i
.types
[xchg
];
3586 i
.types
[xchg
] = i
.types
[0];
3587 i
.types
[0] = temp_type
;
3588 temp_op
= i
.op
[xchg
];
3589 i
.op
[xchg
] = i
.op
[0];
3592 gas_assert (i
.rm
.mode
== 3);
3596 i
.rm
.regmem
= i
.rm
.reg
;
3599 if (i
.tm
.opcode_modifier
.d
)
3600 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3601 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3602 else /* Use the next insn. */
3606 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3607 are no memory operands and at least 3 register ones. */
3608 if (i
.reg_operands
>= 3
3609 && i
.vec_encoding
!= vex_encoding_vex3
3610 && i
.reg_operands
== i
.operands
- i
.imm_operands
3611 && i
.tm
.opcode_modifier
.vex
3612 && i
.tm
.opcode_modifier
.commutative
3613 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3615 && i
.vex
.register_specifier
3616 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3618 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3619 union i386_op temp_op
;
3620 i386_operand_type temp_type
;
3622 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3623 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3624 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3625 &i
.types
[i
.operands
- 3]));
3626 gas_assert (i
.rm
.mode
== 3);
3628 temp_type
= i
.types
[xchg
];
3629 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3630 i
.types
[xchg
+ 1] = temp_type
;
3631 temp_op
= i
.op
[xchg
];
3632 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3633 i
.op
[xchg
+ 1] = temp_op
;
3636 xchg
= i
.rm
.regmem
| 8;
3637 i
.rm
.regmem
= ~register_specifier
& 0xf;
3638 gas_assert (!(i
.rm
.regmem
& 8));
3639 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3640 register_specifier
= ~xchg
& 0xf;
3643 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3644 vector_length
= avxscalar
;
3645 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3651 /* Determine vector length from the last multi-length vector
3654 for (op
= t
->operands
; op
--;)
3655 if (t
->operand_types
[op
].bitfield
.xmmword
3656 && t
->operand_types
[op
].bitfield
.ymmword
3657 && i
.types
[op
].bitfield
.ymmword
)
3664 switch ((i
.tm
.base_opcode
>> (i
.tm
.opcode_length
<< 3)) & 0xff)
3669 case DATA_PREFIX_OPCODE
:
3672 case REPE_PREFIX_OPCODE
:
3675 case REPNE_PREFIX_OPCODE
:
3682 /* Check the REX.W bit and VEXW. */
3683 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3684 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3685 else if (i
.tm
.opcode_modifier
.vexw
)
3686 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3688 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3690 /* Use 2-byte VEX prefix if possible. */
3692 && i
.vec_encoding
!= vex_encoding_vex3
3693 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3694 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3696 /* 2-byte VEX prefix. */
3700 i
.vex
.bytes
[0] = 0xc5;
3702 /* Check the REX.R bit. */
3703 r
= (i
.rex
& REX_R
) ? 0 : 1;
3704 i
.vex
.bytes
[1] = (r
<< 7
3705 | register_specifier
<< 3
3706 | vector_length
<< 2
3711 /* 3-byte VEX prefix. */
3716 switch (i
.tm
.opcode_modifier
.vexopcode
)
3720 i
.vex
.bytes
[0] = 0xc4;
3724 i
.vex
.bytes
[0] = 0xc4;
3728 i
.vex
.bytes
[0] = 0xc4;
3732 i
.vex
.bytes
[0] = 0x8f;
3736 i
.vex
.bytes
[0] = 0x8f;
3740 i
.vex
.bytes
[0] = 0x8f;
3746 /* The high 3 bits of the second VEX byte are 1's compliment
3747 of RXB bits from REX. */
3748 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3750 i
.vex
.bytes
[2] = (w
<< 7
3751 | register_specifier
<< 3
3752 | vector_length
<< 2
3757 static INLINE bfd_boolean
3758 is_evex_encoding (const insn_template
*t
)
3760 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3761 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3762 || t
->opcode_modifier
.sae
;
3765 static INLINE bfd_boolean
3766 is_any_vex_encoding (const insn_template
*t
)
3768 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3769 || is_evex_encoding (t
);
3772 /* Build the EVEX prefix. */
3775 build_evex_prefix (void)
3777 unsigned int register_specifier
;
3778 unsigned int implied_prefix
;
3780 rex_byte vrex_used
= 0;
3782 /* Check register specifier. */
3783 if (i
.vex
.register_specifier
)
3785 gas_assert ((i
.vrex
& REX_X
) == 0);
3787 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3788 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3789 register_specifier
+= 8;
3790 /* The upper 16 registers are encoded in the fourth byte of the
3792 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3793 i
.vex
.bytes
[3] = 0x8;
3794 register_specifier
= ~register_specifier
& 0xf;
3798 register_specifier
= 0xf;
3800 /* Encode upper 16 vector index register in the fourth byte of
3802 if (!(i
.vrex
& REX_X
))
3803 i
.vex
.bytes
[3] = 0x8;
3808 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3813 case DATA_PREFIX_OPCODE
:
3816 case REPE_PREFIX_OPCODE
:
3819 case REPNE_PREFIX_OPCODE
:
3826 /* 4 byte EVEX prefix. */
3828 i
.vex
.bytes
[0] = 0x62;
3831 switch (i
.tm
.opcode_modifier
.vexopcode
)
3847 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3849 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3851 /* The fifth bit of the second EVEX byte is 1's compliment of the
3852 REX_R bit in VREX. */
3853 if (!(i
.vrex
& REX_R
))
3854 i
.vex
.bytes
[1] |= 0x10;
3858 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3860 /* When all operands are registers, the REX_X bit in REX is not
3861 used. We reuse it to encode the upper 16 registers, which is
3862 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3863 as 1's compliment. */
3864 if ((i
.vrex
& REX_B
))
3867 i
.vex
.bytes
[1] &= ~0x40;
3871 /* EVEX instructions shouldn't need the REX prefix. */
3872 i
.vrex
&= ~vrex_used
;
3873 gas_assert (i
.vrex
== 0);
3875 /* Check the REX.W bit and VEXW. */
3876 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3877 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3878 else if (i
.tm
.opcode_modifier
.vexw
)
3879 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3881 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3883 /* Encode the U bit. */
3884 implied_prefix
|= 0x4;
3886 /* The third byte of the EVEX prefix. */
3887 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3889 /* The fourth byte of the EVEX prefix. */
3890 /* The zeroing-masking bit. */
3891 if (i
.mask
&& i
.mask
->zeroing
)
3892 i
.vex
.bytes
[3] |= 0x80;
3894 /* Don't always set the broadcast bit if there is no RC. */
3897 /* Encode the vector length. */
3898 unsigned int vec_length
;
3900 if (!i
.tm
.opcode_modifier
.evex
3901 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3905 /* Determine vector length from the last multi-length vector
3907 for (op
= i
.operands
; op
--;)
3908 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3909 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3910 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3912 if (i
.types
[op
].bitfield
.zmmword
)
3914 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3917 else if (i
.types
[op
].bitfield
.ymmword
)
3919 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3922 else if (i
.types
[op
].bitfield
.xmmword
)
3924 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3927 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3929 switch (i
.broadcast
->bytes
)
3932 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3935 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3938 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3947 if (op
>= MAX_OPERANDS
)
3951 switch (i
.tm
.opcode_modifier
.evex
)
3953 case EVEXLIG
: /* LL' is ignored */
3954 vec_length
= evexlig
<< 5;
3957 vec_length
= 0 << 5;
3960 vec_length
= 1 << 5;
3963 vec_length
= 2 << 5;
3969 i
.vex
.bytes
[3] |= vec_length
;
3970 /* Encode the broadcast bit. */
3972 i
.vex
.bytes
[3] |= 0x10;
3976 if (i
.rounding
->type
!= saeonly
)
3977 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3979 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3982 if (i
.mask
&& i
.mask
->mask
)
3983 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3987 process_immext (void)
3991 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3992 which is coded in the same place as an 8-bit immediate field
3993 would be. Here we fake an 8-bit immediate operand from the
3994 opcode suffix stored in tm.extension_opcode.
3996 AVX instructions also use this encoding, for some of
3997 3 argument instructions. */
3999 gas_assert (i
.imm_operands
<= 1
4001 || (is_any_vex_encoding (&i
.tm
)
4002 && i
.operands
<= 4)));
4004 exp
= &im_expressions
[i
.imm_operands
++];
4005 i
.op
[i
.operands
].imms
= exp
;
4006 i
.types
[i
.operands
] = imm8
;
4008 exp
->X_op
= O_constant
;
4009 exp
->X_add_number
= i
.tm
.extension_opcode
;
4010 i
.tm
.extension_opcode
= None
;
4017 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4022 as_bad (_("invalid instruction `%s' after `%s'"),
4023 i
.tm
.name
, i
.hle_prefix
);
4026 if (i
.prefix
[LOCK_PREFIX
])
4028 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4032 case HLEPrefixRelease
:
4033 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4035 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4039 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4041 as_bad (_("memory destination needed for instruction `%s'"
4042 " after `xrelease'"), i
.tm
.name
);
4049 /* Try the shortest encoding by shortening operand size. */
4052 optimize_encoding (void)
4056 if (optimize_for_space
4057 && !is_any_vex_encoding (&i
.tm
)
4058 && i
.reg_operands
== 1
4059 && i
.imm_operands
== 1
4060 && !i
.types
[1].bitfield
.byte
4061 && i
.op
[0].imms
->X_op
== O_constant
4062 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4063 && (i
.tm
.base_opcode
== 0xa8
4064 || (i
.tm
.base_opcode
== 0xf6
4065 && i
.tm
.extension_opcode
== 0x0)))
4068 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4070 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4071 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4073 i
.types
[1].bitfield
.byte
= 1;
4074 /* Ignore the suffix. */
4076 /* Convert to byte registers. */
4077 if (i
.types
[1].bitfield
.word
)
4079 else if (i
.types
[1].bitfield
.dword
)
4083 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4088 else if (flag_code
== CODE_64BIT
4089 && !is_any_vex_encoding (&i
.tm
)
4090 && ((i
.types
[1].bitfield
.qword
4091 && i
.reg_operands
== 1
4092 && i
.imm_operands
== 1
4093 && i
.op
[0].imms
->X_op
== O_constant
4094 && ((i
.tm
.base_opcode
== 0xb8
4095 && i
.tm
.extension_opcode
== None
4096 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4097 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4098 && ((i
.tm
.base_opcode
== 0x24
4099 || i
.tm
.base_opcode
== 0xa8)
4100 || (i
.tm
.base_opcode
== 0x80
4101 && i
.tm
.extension_opcode
== 0x4)
4102 || ((i
.tm
.base_opcode
== 0xf6
4103 || (i
.tm
.base_opcode
| 1) == 0xc7)
4104 && i
.tm
.extension_opcode
== 0x0)))
4105 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4106 && i
.tm
.base_opcode
== 0x83
4107 && i
.tm
.extension_opcode
== 0x4)))
4108 || (i
.types
[0].bitfield
.qword
4109 && ((i
.reg_operands
== 2
4110 && i
.op
[0].regs
== i
.op
[1].regs
4111 && (i
.tm
.base_opcode
== 0x30
4112 || i
.tm
.base_opcode
== 0x28))
4113 || (i
.reg_operands
== 1
4115 && i
.tm
.base_opcode
== 0x30)))))
4118 andq $imm31, %r64 -> andl $imm31, %r32
4119 andq $imm7, %r64 -> andl $imm7, %r32
4120 testq $imm31, %r64 -> testl $imm31, %r32
4121 xorq %r64, %r64 -> xorl %r32, %r32
4122 subq %r64, %r64 -> subl %r32, %r32
4123 movq $imm31, %r64 -> movl $imm31, %r32
4124 movq $imm32, %r64 -> movl $imm32, %r32
4126 i
.tm
.opcode_modifier
.norex64
= 1;
4127 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4130 movq $imm31, %r64 -> movl $imm31, %r32
4131 movq $imm32, %r64 -> movl $imm32, %r32
4133 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4134 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4135 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4136 i
.types
[0].bitfield
.imm32
= 1;
4137 i
.types
[0].bitfield
.imm32s
= 0;
4138 i
.types
[0].bitfield
.imm64
= 0;
4139 i
.types
[1].bitfield
.dword
= 1;
4140 i
.types
[1].bitfield
.qword
= 0;
4141 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4144 movq $imm31, %r64 -> movl $imm31, %r32
4146 i
.tm
.base_opcode
= 0xb8;
4147 i
.tm
.extension_opcode
= None
;
4148 i
.tm
.opcode_modifier
.w
= 0;
4149 i
.tm
.opcode_modifier
.modrm
= 0;
4153 else if (optimize
> 1
4154 && !optimize_for_space
4155 && !is_any_vex_encoding (&i
.tm
)
4156 && i
.reg_operands
== 2
4157 && i
.op
[0].regs
== i
.op
[1].regs
4158 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4159 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4160 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4163 andb %rN, %rN -> testb %rN, %rN
4164 andw %rN, %rN -> testw %rN, %rN
4165 andq %rN, %rN -> testq %rN, %rN
4166 orb %rN, %rN -> testb %rN, %rN
4167 orw %rN, %rN -> testw %rN, %rN
4168 orq %rN, %rN -> testq %rN, %rN
4170 and outside of 64-bit mode
4172 andl %rN, %rN -> testl %rN, %rN
4173 orl %rN, %rN -> testl %rN, %rN
4175 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4177 else if (i
.reg_operands
== 3
4178 && i
.op
[0].regs
== i
.op
[1].regs
4179 && !i
.types
[2].bitfield
.xmmword
4180 && (i
.tm
.opcode_modifier
.vex
4181 || ((!i
.mask
|| i
.mask
->zeroing
)
4183 && is_evex_encoding (&i
.tm
)
4184 && (i
.vec_encoding
!= vex_encoding_evex
4185 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4186 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4187 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4188 && i
.types
[2].bitfield
.ymmword
))))
4189 && ((i
.tm
.base_opcode
== 0x55
4190 || i
.tm
.base_opcode
== 0x6655
4191 || i
.tm
.base_opcode
== 0x66df
4192 || i
.tm
.base_opcode
== 0x57
4193 || i
.tm
.base_opcode
== 0x6657
4194 || i
.tm
.base_opcode
== 0x66ef
4195 || i
.tm
.base_opcode
== 0x66f8
4196 || i
.tm
.base_opcode
== 0x66f9
4197 || i
.tm
.base_opcode
== 0x66fa
4198 || i
.tm
.base_opcode
== 0x66fb
4199 || i
.tm
.base_opcode
== 0x42
4200 || i
.tm
.base_opcode
== 0x6642
4201 || i
.tm
.base_opcode
== 0x47
4202 || i
.tm
.base_opcode
== 0x6647)
4203 && i
.tm
.extension_opcode
== None
))
4206 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4208 EVEX VOP %zmmM, %zmmM, %zmmN
4209 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4210 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4211 EVEX VOP %ymmM, %ymmM, %ymmN
4212 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4213 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4214 VEX VOP %ymmM, %ymmM, %ymmN
4215 -> VEX VOP %xmmM, %xmmM, %xmmN
4216 VOP, one of vpandn and vpxor:
4217 VEX VOP %ymmM, %ymmM, %ymmN
4218 -> VEX VOP %xmmM, %xmmM, %xmmN
4219 VOP, one of vpandnd and vpandnq:
4220 EVEX VOP %zmmM, %zmmM, %zmmN
4221 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4222 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4223 EVEX VOP %ymmM, %ymmM, %ymmN
4224 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4225 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4226 VOP, one of vpxord and vpxorq:
4227 EVEX VOP %zmmM, %zmmM, %zmmN
4228 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4229 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4230 EVEX VOP %ymmM, %ymmM, %ymmN
4231 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4232 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4233 VOP, one of kxord and kxorq:
4234 VEX VOP %kM, %kM, %kN
4235 -> VEX kxorw %kM, %kM, %kN
4236 VOP, one of kandnd and kandnq:
4237 VEX VOP %kM, %kM, %kN
4238 -> VEX kandnw %kM, %kM, %kN
4240 if (is_evex_encoding (&i
.tm
))
4242 if (i
.vec_encoding
!= vex_encoding_evex
)
4244 i
.tm
.opcode_modifier
.vex
= VEX128
;
4245 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4246 i
.tm
.opcode_modifier
.evex
= 0;
4248 else if (optimize
> 1)
4249 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4253 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4255 i
.tm
.base_opcode
&= 0xff;
4256 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4259 i
.tm
.opcode_modifier
.vex
= VEX128
;
4261 if (i
.tm
.opcode_modifier
.vex
)
4262 for (j
= 0; j
< 3; j
++)
4264 i
.types
[j
].bitfield
.xmmword
= 1;
4265 i
.types
[j
].bitfield
.ymmword
= 0;
4268 else if (i
.vec_encoding
!= vex_encoding_evex
4269 && !i
.types
[0].bitfield
.zmmword
4270 && !i
.types
[1].bitfield
.zmmword
4273 && is_evex_encoding (&i
.tm
)
4274 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4275 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4276 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4277 || (i
.tm
.base_opcode
& ~4) == 0x66db
4278 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4279 && i
.tm
.extension_opcode
== None
)
4282 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4283 vmovdqu32 and vmovdqu64:
4284 EVEX VOP %xmmM, %xmmN
4285 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4286 EVEX VOP %ymmM, %ymmN
4287 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4289 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4291 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4293 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4295 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4296 VOP, one of vpand, vpandn, vpor, vpxor:
4297 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4298 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4299 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4300 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4301 EVEX VOP{d,q} mem, %xmmM, %xmmN
4302 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4303 EVEX VOP{d,q} mem, %ymmM, %ymmN
4304 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4306 for (j
= 0; j
< i
.operands
; j
++)
4307 if (operand_type_check (i
.types
[j
], disp
)
4308 && i
.op
[j
].disps
->X_op
== O_constant
)
4310 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4311 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4312 bytes, we choose EVEX Disp8 over VEX Disp32. */
4313 int evex_disp8
, vex_disp8
;
4314 unsigned int memshift
= i
.memshift
;
4315 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4317 evex_disp8
= fits_in_disp8 (n
);
4319 vex_disp8
= fits_in_disp8 (n
);
4320 if (evex_disp8
!= vex_disp8
)
4322 i
.memshift
= memshift
;
4326 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4329 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4330 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4331 i
.tm
.opcode_modifier
.vex
4332 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4333 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4334 /* VPAND, VPOR, and VPXOR are commutative. */
4335 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4336 i
.tm
.opcode_modifier
.commutative
= 1;
4337 i
.tm
.opcode_modifier
.evex
= 0;
4338 i
.tm
.opcode_modifier
.masking
= 0;
4339 i
.tm
.opcode_modifier
.broadcast
= 0;
4340 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4343 i
.types
[j
].bitfield
.disp8
4344 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4348 /* Return non-zero for load instruction. */
4354 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4355 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4359 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4360 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4361 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4362 if (i
.tm
.opcode_modifier
.anysize
)
4365 /* pop, popf, popa. */
4366 if (strcmp (i
.tm
.name
, "pop") == 0
4367 || i
.tm
.base_opcode
== 0x9d
4368 || i
.tm
.base_opcode
== 0x61)
4371 /* movs, cmps, lods, scas. */
4372 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4376 if (base_opcode
== 0x6f
4377 || i
.tm
.base_opcode
== 0xd7)
4379 /* NB: For AMD-specific insns with implicit memory operands,
4380 they're intentionally not covered. */
4383 /* No memory operand. */
4384 if (!i
.mem_operands
)
4390 if (i
.tm
.base_opcode
== 0xae
4391 && i
.tm
.opcode_modifier
.vex
4392 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
4393 && i
.tm
.extension_opcode
== 2)
4398 /* test, not, neg, mul, imul, div, idiv. */
4399 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4400 && i
.tm
.extension_opcode
!= 1)
4404 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4407 /* add, or, adc, sbb, and, sub, xor, cmp. */
4408 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4411 /* bt, bts, btr, btc. */
4412 if (i
.tm
.base_opcode
== 0xfba
4413 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4416 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4417 if ((base_opcode
== 0xc1
4418 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4419 && i
.tm
.extension_opcode
!= 6)
4422 /* cmpxchg8b, cmpxchg16b, xrstors. */
4423 if (i
.tm
.base_opcode
== 0xfc7
4424 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4427 /* fxrstor, ldmxcsr, xrstor. */
4428 if (i
.tm
.base_opcode
== 0xfae
4429 && (i
.tm
.extension_opcode
== 1
4430 || i
.tm
.extension_opcode
== 2
4431 || i
.tm
.extension_opcode
== 5))
4434 /* lgdt, lidt, lmsw. */
4435 if (i
.tm
.base_opcode
== 0xf01
4436 && (i
.tm
.extension_opcode
== 2
4437 || i
.tm
.extension_opcode
== 3
4438 || i
.tm
.extension_opcode
== 6))
4442 if (i
.tm
.base_opcode
== 0xfc7
4443 && i
.tm
.extension_opcode
== 6)
4446 /* Check for x87 instructions. */
4447 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4449 /* Skip fst, fstp, fstenv, fstcw. */
4450 if (i
.tm
.base_opcode
== 0xd9
4451 && (i
.tm
.extension_opcode
== 2
4452 || i
.tm
.extension_opcode
== 3
4453 || i
.tm
.extension_opcode
== 6
4454 || i
.tm
.extension_opcode
== 7))
4457 /* Skip fisttp, fist, fistp, fstp. */
4458 if (i
.tm
.base_opcode
== 0xdb
4459 && (i
.tm
.extension_opcode
== 1
4460 || i
.tm
.extension_opcode
== 2
4461 || i
.tm
.extension_opcode
== 3
4462 || i
.tm
.extension_opcode
== 7))
4465 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4466 if (i
.tm
.base_opcode
== 0xdd
4467 && (i
.tm
.extension_opcode
== 1
4468 || i
.tm
.extension_opcode
== 2
4469 || i
.tm
.extension_opcode
== 3
4470 || i
.tm
.extension_opcode
== 6
4471 || i
.tm
.extension_opcode
== 7))
4474 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4475 if (i
.tm
.base_opcode
== 0xdf
4476 && (i
.tm
.extension_opcode
== 1
4477 || i
.tm
.extension_opcode
== 2
4478 || i
.tm
.extension_opcode
== 3
4479 || i
.tm
.extension_opcode
== 6
4480 || i
.tm
.extension_opcode
== 7))
4487 dest
= i
.operands
- 1;
4489 /* Check fake imm8 operand and 3 source operands. */
4490 if ((i
.tm
.opcode_modifier
.immext
4491 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4492 && i
.types
[dest
].bitfield
.imm8
)
4495 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4497 && (base_opcode
== 0x1
4498 || base_opcode
== 0x9
4499 || base_opcode
== 0x11
4500 || base_opcode
== 0x19
4501 || base_opcode
== 0x21
4502 || base_opcode
== 0x29
4503 || base_opcode
== 0x31
4504 || base_opcode
== 0x39
4505 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4506 || base_opcode
== 0xfc1))
4509 /* Check for load instruction. */
4510 return (i
.types
[dest
].bitfield
.class != ClassNone
4511 || i
.types
[dest
].bitfield
.instance
== Accum
);
4514 /* Output lfence, 0xfaee8, after instruction. */
4517 insert_lfence_after (void)
4519 if (lfence_after_load
&& load_insn_p ())
4521 /* There are also two REP string instructions that require
4522 special treatment. Specifically, the compare string (CMPS)
4523 and scan string (SCAS) instructions set EFLAGS in a manner
4524 that depends on the data being compared/scanned. When used
4525 with a REP prefix, the number of iterations may therefore
4526 vary depending on this data. If the data is a program secret
4527 chosen by the adversary using an LVI method,
4528 then this data-dependent behavior may leak some aspect
4530 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4531 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4532 && i
.prefix
[REP_PREFIX
])
4534 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4537 char *p
= frag_more (3);
4544 /* Output lfence, 0xfaee8, before instruction. */
4547 insert_lfence_before (void)
4551 if (is_any_vex_encoding (&i
.tm
))
4554 if (i
.tm
.base_opcode
== 0xff
4555 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4557 /* Insert lfence before indirect branch if needed. */
4559 if (lfence_before_indirect_branch
== lfence_branch_none
)
4562 if (i
.operands
!= 1)
4565 if (i
.reg_operands
== 1)
4567 /* Indirect branch via register. Don't insert lfence with
4568 -mlfence-after-load=yes. */
4569 if (lfence_after_load
4570 || lfence_before_indirect_branch
== lfence_branch_memory
)
4573 else if (i
.mem_operands
== 1
4574 && lfence_before_indirect_branch
!= lfence_branch_register
)
4576 as_warn (_("indirect `%s` with memory operand should be avoided"),
4583 if (last_insn
.kind
!= last_insn_other
4584 && last_insn
.seg
== now_seg
)
4586 as_warn_where (last_insn
.file
, last_insn
.line
,
4587 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4588 last_insn
.name
, i
.tm
.name
);
4599 /* Output or/not/shl and lfence before near ret. */
4600 if (lfence_before_ret
!= lfence_before_ret_none
4601 && (i
.tm
.base_opcode
== 0xc2
4602 || i
.tm
.base_opcode
== 0xc3))
4604 if (last_insn
.kind
!= last_insn_other
4605 && last_insn
.seg
== now_seg
)
4607 as_warn_where (last_insn
.file
, last_insn
.line
,
4608 _("`%s` skips -mlfence-before-ret on `%s`"),
4609 last_insn
.name
, i
.tm
.name
);
4613 /* Near ret ingore operand size override under CPU64. */
4614 char prefix
= flag_code
== CODE_64BIT
4616 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4618 if (lfence_before_ret
== lfence_before_ret_not
)
4620 /* not: 0xf71424, may add prefix
4621 for operand size override or 64-bit code. */
4622 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4636 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4639 if (lfence_before_ret
== lfence_before_ret_or
)
4641 /* or: 0x830c2400, may add prefix
4642 for operand size override or 64-bit code. */
4648 /* shl: 0xc1242400, may add prefix
4649 for operand size override or 64-bit code. */
4664 /* This is the guts of the machine-dependent assembler. LINE points to a
4665 machine dependent instruction. This function is supposed to emit
4666 the frags/bytes it assembles to. */
4669 md_assemble (char *line
)
4672 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4673 const insn_template
*t
;
4675 /* Initialize globals. */
4676 memset (&i
, '\0', sizeof (i
));
4677 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4678 i
.reloc
[j
] = NO_RELOC
;
4679 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4680 memset (im_expressions
, '\0', sizeof (im_expressions
));
4681 save_stack_p
= save_stack
;
4683 /* First parse an instruction mnemonic & call i386_operand for the operands.
4684 We assume that the scrubber has arranged it so that line[0] is the valid
4685 start of a (possibly prefixed) mnemonic. */
4687 line
= parse_insn (line
, mnemonic
);
4690 mnem_suffix
= i
.suffix
;
4692 line
= parse_operands (line
, mnemonic
);
4694 xfree (i
.memop1_string
);
4695 i
.memop1_string
= NULL
;
4699 /* Now we've parsed the mnemonic into a set of templates, and have the
4700 operands at hand. */
4702 /* All Intel opcodes have reversed operands except for "bound", "enter",
4703 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4704 intersegment "jmp" and "call" instructions with 2 immediate operands so
4705 that the immediate segment precedes the offset, as it does when in AT&T
4709 && (strcmp (mnemonic
, "bound") != 0)
4710 && (strcmp (mnemonic
, "invlpga") != 0)
4711 && (strncmp (mnemonic
, "monitor", 7) != 0)
4712 && (strncmp (mnemonic
, "mwait", 5) != 0)
4713 && (strcmp (mnemonic
, "tpause") != 0)
4714 && (strcmp (mnemonic
, "umwait") != 0)
4715 && !(operand_type_check (i
.types
[0], imm
)
4716 && operand_type_check (i
.types
[1], imm
)))
4719 /* The order of the immediates should be reversed
4720 for 2 immediates extrq and insertq instructions */
4721 if (i
.imm_operands
== 2
4722 && (strcmp (mnemonic
, "extrq") == 0
4723 || strcmp (mnemonic
, "insertq") == 0))
4724 swap_2_operands (0, 1);
4729 /* Don't optimize displacement for movabs since it only takes 64bit
4732 && i
.disp_encoding
!= disp_encoding_32bit
4733 && (flag_code
!= CODE_64BIT
4734 || strcmp (mnemonic
, "movabs") != 0))
4737 /* Next, we find a template that matches the given insn,
4738 making sure the overlap of the given operands types is consistent
4739 with the template operand types. */
4741 if (!(t
= match_template (mnem_suffix
)))
4744 if (sse_check
!= check_none
4745 && !i
.tm
.opcode_modifier
.noavx
4746 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4747 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4748 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4749 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4750 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4751 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4752 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4753 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4754 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4755 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4756 || i
.tm
.cpu_flags
.bitfield
.cpusha
4757 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4759 (sse_check
== check_warning
4761 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4764 if (i
.tm
.opcode_modifier
.fwait
)
4765 if (!add_prefix (FWAIT_OPCODE
))
4768 /* Check if REP prefix is OK. */
4769 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4771 as_bad (_("invalid instruction `%s' after `%s'"),
4772 i
.tm
.name
, i
.rep_prefix
);
4776 /* Check for lock without a lockable instruction. Destination operand
4777 must be memory unless it is xchg (0x86). */
4778 if (i
.prefix
[LOCK_PREFIX
]
4779 && (!i
.tm
.opcode_modifier
.islockable
4780 || i
.mem_operands
== 0
4781 || (i
.tm
.base_opcode
!= 0x86
4782 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4784 as_bad (_("expecting lockable instruction after `lock'"));
4788 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4789 if (i
.prefix
[DATA_PREFIX
]
4790 && (is_any_vex_encoding (&i
.tm
)
4791 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4792 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4794 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4798 /* Check if HLE prefix is OK. */
4799 if (i
.hle_prefix
&& !check_hle ())
4802 /* Check BND prefix. */
4803 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4804 as_bad (_("expecting valid branch instruction after `bnd'"));
4806 /* Check NOTRACK prefix. */
4807 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4808 as_bad (_("expecting indirect branch instruction after `notrack'"));
4810 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4812 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4813 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4814 else if (flag_code
!= CODE_16BIT
4815 ? i
.prefix
[ADDR_PREFIX
]
4816 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4817 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4820 /* Insert BND prefix. */
4821 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4823 if (!i
.prefix
[BND_PREFIX
])
4824 add_prefix (BND_PREFIX_OPCODE
);
4825 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4827 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4828 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4832 /* Check string instruction segment overrides. */
4833 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4835 gas_assert (i
.mem_operands
);
4836 if (!check_string ())
4838 i
.disp_operands
= 0;
4841 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4842 optimize_encoding ();
4844 if (!process_suffix ())
4847 /* Update operand types and check extended states. */
4848 for (j
= 0; j
< i
.operands
; j
++)
4850 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4851 switch (i
.tm
.operand_types
[j
].bitfield
.class)
4856 i
.xstate
|= xstate_mmx
;
4859 i
.xstate
|= xstate_zmm
;
4862 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
4863 i
.xstate
|= xstate_tmm
;
4864 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
4865 i
.xstate
|= xstate_zmm
;
4866 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
4867 i
.xstate
|= xstate_ymm
;
4868 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
4869 i
.xstate
|= xstate_xmm
;
4874 /* Make still unresolved immediate matches conform to size of immediate
4875 given in i.suffix. */
4876 if (!finalize_imm ())
4879 if (i
.types
[0].bitfield
.imm1
)
4880 i
.imm_operands
= 0; /* kludge for shift insns. */
4882 /* We only need to check those implicit registers for instructions
4883 with 3 operands or less. */
4884 if (i
.operands
<= 3)
4885 for (j
= 0; j
< i
.operands
; j
++)
4886 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4887 && !i
.types
[j
].bitfield
.xmmword
)
4890 /* For insns with operands there are more diddles to do to the opcode. */
4893 if (!process_operands ())
4896 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4898 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4899 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4902 if (is_any_vex_encoding (&i
.tm
))
4904 if (!cpu_arch_flags
.bitfield
.cpui286
)
4906 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4911 /* Check for explicit REX prefix. */
4912 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
4914 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
4918 if (i
.tm
.opcode_modifier
.vex
)
4919 build_vex_prefix (t
);
4921 build_evex_prefix ();
4923 /* The individual REX.RXBW bits got consumed. */
4924 i
.rex
&= REX_OPCODE
;
4927 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4928 instructions may define INT_OPCODE as well, so avoid this corner
4929 case for those instructions that use MODRM. */
4930 if (i
.tm
.base_opcode
== INT_OPCODE
4931 && !i
.tm
.opcode_modifier
.modrm
4932 && i
.op
[0].imms
->X_add_number
== 3)
4934 i
.tm
.base_opcode
= INT3_OPCODE
;
4938 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4939 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4940 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4941 && i
.op
[0].disps
->X_op
== O_constant
)
4943 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4944 the absolute address given by the constant. Since ix86 jumps and
4945 calls are pc relative, we need to generate a reloc. */
4946 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4947 i
.op
[0].disps
->X_op
= O_symbol
;
4950 /* For 8 bit registers we need an empty rex prefix. Also if the
4951 instruction already has a prefix, we need to convert old
4952 registers to new ones. */
4954 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4955 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4956 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4957 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4958 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4959 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4964 i
.rex
|= REX_OPCODE
;
4965 for (x
= 0; x
< 2; x
++)
4967 /* Look for 8 bit operand that uses old registers. */
4968 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4969 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4971 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4972 /* In case it is "hi" register, give up. */
4973 if (i
.op
[x
].regs
->reg_num
> 3)
4974 as_bad (_("can't encode register '%s%s' in an "
4975 "instruction requiring REX prefix."),
4976 register_prefix
, i
.op
[x
].regs
->reg_name
);
4978 /* Otherwise it is equivalent to the extended register.
4979 Since the encoding doesn't change this is merely
4980 cosmetic cleanup for debug output. */
4982 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4987 if (i
.rex
== 0 && i
.rex_encoding
)
4989 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4990 that uses legacy register. If it is "hi" register, don't add
4991 the REX_OPCODE byte. */
4993 for (x
= 0; x
< 2; x
++)
4994 if (i
.types
[x
].bitfield
.class == Reg
4995 && i
.types
[x
].bitfield
.byte
4996 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4997 && i
.op
[x
].regs
->reg_num
> 3)
4999 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5000 i
.rex_encoding
= FALSE
;
5009 add_prefix (REX_OPCODE
| i
.rex
);
5011 insert_lfence_before ();
5013 /* We are ready to output the insn. */
5016 insert_lfence_after ();
5018 last_insn
.seg
= now_seg
;
5020 if (i
.tm
.opcode_modifier
.isprefix
)
5022 last_insn
.kind
= last_insn_prefix
;
5023 last_insn
.name
= i
.tm
.name
;
5024 last_insn
.file
= as_where (&last_insn
.line
);
5027 last_insn
.kind
= last_insn_other
;
5031 parse_insn (char *line
, char *mnemonic
)
5034 char *token_start
= l
;
5037 const insn_template
*t
;
5043 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5048 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5050 as_bad (_("no such instruction: `%s'"), token_start
);
5055 if (!is_space_char (*l
)
5056 && *l
!= END_OF_INSN
5058 || (*l
!= PREFIX_SEPARATOR
5061 as_bad (_("invalid character %s in mnemonic"),
5062 output_invalid (*l
));
5065 if (token_start
== l
)
5067 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5068 as_bad (_("expecting prefix; got nothing"));
5070 as_bad (_("expecting mnemonic; got nothing"));
5074 /* Look up instruction (or prefix) via hash table. */
5075 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5077 if (*l
!= END_OF_INSN
5078 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5079 && current_templates
5080 && current_templates
->start
->opcode_modifier
.isprefix
)
5082 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5084 as_bad ((flag_code
!= CODE_64BIT
5085 ? _("`%s' is only supported in 64-bit mode")
5086 : _("`%s' is not supported in 64-bit mode")),
5087 current_templates
->start
->name
);
5090 /* If we are in 16-bit mode, do not allow addr16 or data16.
5091 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5092 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5093 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5094 && flag_code
!= CODE_64BIT
5095 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5096 ^ (flag_code
== CODE_16BIT
)))
5098 as_bad (_("redundant %s prefix"),
5099 current_templates
->start
->name
);
5102 if (current_templates
->start
->opcode_length
== 0)
5104 /* Handle pseudo prefixes. */
5105 switch (current_templates
->start
->base_opcode
)
5109 i
.disp_encoding
= disp_encoding_8bit
;
5113 i
.disp_encoding
= disp_encoding_16bit
;
5117 i
.disp_encoding
= disp_encoding_32bit
;
5121 i
.dir_encoding
= dir_encoding_load
;
5125 i
.dir_encoding
= dir_encoding_store
;
5129 i
.vec_encoding
= vex_encoding_vex
;
5133 i
.vec_encoding
= vex_encoding_vex3
;
5137 i
.vec_encoding
= vex_encoding_evex
;
5141 i
.rex_encoding
= TRUE
;
5143 case Prefix_NoOptimize
:
5145 i
.no_optimize
= TRUE
;
5153 /* Add prefix, checking for repeated prefixes. */
5154 switch (add_prefix (current_templates
->start
->base_opcode
))
5159 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5160 i
.notrack_prefix
= current_templates
->start
->name
;
5163 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5164 i
.hle_prefix
= current_templates
->start
->name
;
5165 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5166 i
.bnd_prefix
= current_templates
->start
->name
;
5168 i
.rep_prefix
= current_templates
->start
->name
;
5174 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5181 if (!current_templates
)
5183 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5184 Check if we should swap operand or force 32bit displacement in
5186 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5187 i
.dir_encoding
= dir_encoding_swap
;
5188 else if (mnem_p
- 3 == dot_p
5191 i
.disp_encoding
= disp_encoding_8bit
;
5192 else if (mnem_p
- 4 == dot_p
5196 i
.disp_encoding
= disp_encoding_32bit
;
5201 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5204 if (!current_templates
)
5207 if (mnem_p
> mnemonic
)
5209 /* See if we can get a match by trimming off a suffix. */
5212 case WORD_MNEM_SUFFIX
:
5213 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5214 i
.suffix
= SHORT_MNEM_SUFFIX
;
5217 case BYTE_MNEM_SUFFIX
:
5218 case QWORD_MNEM_SUFFIX
:
5219 i
.suffix
= mnem_p
[-1];
5221 current_templates
= (const templates
*) str_hash_find (op_hash
,
5224 case SHORT_MNEM_SUFFIX
:
5225 case LONG_MNEM_SUFFIX
:
5228 i
.suffix
= mnem_p
[-1];
5230 current_templates
= (const templates
*) str_hash_find (op_hash
,
5239 if (intel_float_operand (mnemonic
) == 1)
5240 i
.suffix
= SHORT_MNEM_SUFFIX
;
5242 i
.suffix
= LONG_MNEM_SUFFIX
;
5244 current_templates
= (const templates
*) str_hash_find (op_hash
,
5251 if (!current_templates
)
5253 as_bad (_("no such instruction: `%s'"), token_start
);
5258 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5259 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5261 /* Check for a branch hint. We allow ",pt" and ",pn" for
5262 predict taken and predict not taken respectively.
5263 I'm not sure that branch hints actually do anything on loop
5264 and jcxz insns (JumpByte) for current Pentium4 chips. They
5265 may work in the future and it doesn't hurt to accept them
5267 if (l
[0] == ',' && l
[1] == 'p')
5271 if (!add_prefix (DS_PREFIX_OPCODE
))
5275 else if (l
[2] == 'n')
5277 if (!add_prefix (CS_PREFIX_OPCODE
))
5283 /* Any other comma loses. */
5286 as_bad (_("invalid character %s in mnemonic"),
5287 output_invalid (*l
));
5291 /* Check if instruction is supported on specified architecture. */
5293 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5295 supported
|= cpu_flags_match (t
);
5296 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5298 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5299 as_warn (_("use .code16 to ensure correct addressing mode"));
5305 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5306 as_bad (flag_code
== CODE_64BIT
5307 ? _("`%s' is not supported in 64-bit mode")
5308 : _("`%s' is only supported in 64-bit mode"),
5309 current_templates
->start
->name
);
5311 as_bad (_("`%s' is not supported on `%s%s'"),
5312 current_templates
->start
->name
,
5313 cpu_arch_name
? cpu_arch_name
: default_arch
,
5314 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5320 parse_operands (char *l
, const char *mnemonic
)
5324 /* 1 if operand is pending after ','. */
5325 unsigned int expecting_operand
= 0;
5327 /* Non-zero if operand parens not balanced. */
5328 unsigned int paren_not_balanced
;
5330 while (*l
!= END_OF_INSN
)
5332 /* Skip optional white space before operand. */
5333 if (is_space_char (*l
))
5335 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5337 as_bad (_("invalid character %s before operand %d"),
5338 output_invalid (*l
),
5342 token_start
= l
; /* After white space. */
5343 paren_not_balanced
= 0;
5344 while (paren_not_balanced
|| *l
!= ',')
5346 if (*l
== END_OF_INSN
)
5348 if (paren_not_balanced
)
5351 as_bad (_("unbalanced parenthesis in operand %d."),
5354 as_bad (_("unbalanced brackets in operand %d."),
5359 break; /* we are done */
5361 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5363 as_bad (_("invalid character %s in operand %d"),
5364 output_invalid (*l
),
5371 ++paren_not_balanced
;
5373 --paren_not_balanced
;
5378 ++paren_not_balanced
;
5380 --paren_not_balanced
;
5384 if (l
!= token_start
)
5385 { /* Yes, we've read in another operand. */
5386 unsigned int operand_ok
;
5387 this_operand
= i
.operands
++;
5388 if (i
.operands
> MAX_OPERANDS
)
5390 as_bad (_("spurious operands; (%d operands/instruction max)"),
5394 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5395 /* Now parse operand adding info to 'i' as we go along. */
5396 END_STRING_AND_SAVE (l
);
5398 if (i
.mem_operands
> 1)
5400 as_bad (_("too many memory references for `%s'"),
5407 i386_intel_operand (token_start
,
5408 intel_float_operand (mnemonic
));
5410 operand_ok
= i386_att_operand (token_start
);
5412 RESTORE_END_STRING (l
);
5418 if (expecting_operand
)
5420 expecting_operand_after_comma
:
5421 as_bad (_("expecting operand after ','; got nothing"));
5426 as_bad (_("expecting operand before ','; got nothing"));
5431 /* Now *l must be either ',' or END_OF_INSN. */
5434 if (*++l
== END_OF_INSN
)
5436 /* Just skip it, if it's \n complain. */
5437 goto expecting_operand_after_comma
;
5439 expecting_operand
= 1;
5446 swap_2_operands (int xchg1
, int xchg2
)
5448 union i386_op temp_op
;
5449 i386_operand_type temp_type
;
5450 unsigned int temp_flags
;
5451 enum bfd_reloc_code_real temp_reloc
;
5453 temp_type
= i
.types
[xchg2
];
5454 i
.types
[xchg2
] = i
.types
[xchg1
];
5455 i
.types
[xchg1
] = temp_type
;
5457 temp_flags
= i
.flags
[xchg2
];
5458 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5459 i
.flags
[xchg1
] = temp_flags
;
5461 temp_op
= i
.op
[xchg2
];
5462 i
.op
[xchg2
] = i
.op
[xchg1
];
5463 i
.op
[xchg1
] = temp_op
;
5465 temp_reloc
= i
.reloc
[xchg2
];
5466 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5467 i
.reloc
[xchg1
] = temp_reloc
;
5471 if (i
.mask
->operand
== xchg1
)
5472 i
.mask
->operand
= xchg2
;
5473 else if (i
.mask
->operand
== xchg2
)
5474 i
.mask
->operand
= xchg1
;
5478 if (i
.broadcast
->operand
== xchg1
)
5479 i
.broadcast
->operand
= xchg2
;
5480 else if (i
.broadcast
->operand
== xchg2
)
5481 i
.broadcast
->operand
= xchg1
;
5485 if (i
.rounding
->operand
== xchg1
)
5486 i
.rounding
->operand
= xchg2
;
5487 else if (i
.rounding
->operand
== xchg2
)
5488 i
.rounding
->operand
= xchg1
;
5493 swap_operands (void)
5499 swap_2_operands (1, i
.operands
- 2);
5503 swap_2_operands (0, i
.operands
- 1);
5509 if (i
.mem_operands
== 2)
5511 const seg_entry
*temp_seg
;
5512 temp_seg
= i
.seg
[0];
5513 i
.seg
[0] = i
.seg
[1];
5514 i
.seg
[1] = temp_seg
;
5518 /* Try to ensure constant immediates are represented in the smallest
5523 char guess_suffix
= 0;
5527 guess_suffix
= i
.suffix
;
5528 else if (i
.reg_operands
)
5530 /* Figure out a suffix from the last register operand specified.
5531 We can't do this properly yet, i.e. excluding special register
5532 instances, but the following works for instructions with
5533 immediates. In any case, we can't set i.suffix yet. */
5534 for (op
= i
.operands
; --op
>= 0;)
5535 if (i
.types
[op
].bitfield
.class != Reg
)
5537 else if (i
.types
[op
].bitfield
.byte
)
5539 guess_suffix
= BYTE_MNEM_SUFFIX
;
5542 else if (i
.types
[op
].bitfield
.word
)
5544 guess_suffix
= WORD_MNEM_SUFFIX
;
5547 else if (i
.types
[op
].bitfield
.dword
)
5549 guess_suffix
= LONG_MNEM_SUFFIX
;
5552 else if (i
.types
[op
].bitfield
.qword
)
5554 guess_suffix
= QWORD_MNEM_SUFFIX
;
5558 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5559 guess_suffix
= WORD_MNEM_SUFFIX
;
5561 for (op
= i
.operands
; --op
>= 0;)
5562 if (operand_type_check (i
.types
[op
], imm
))
5564 switch (i
.op
[op
].imms
->X_op
)
5567 /* If a suffix is given, this operand may be shortened. */
5568 switch (guess_suffix
)
5570 case LONG_MNEM_SUFFIX
:
5571 i
.types
[op
].bitfield
.imm32
= 1;
5572 i
.types
[op
].bitfield
.imm64
= 1;
5574 case WORD_MNEM_SUFFIX
:
5575 i
.types
[op
].bitfield
.imm16
= 1;
5576 i
.types
[op
].bitfield
.imm32
= 1;
5577 i
.types
[op
].bitfield
.imm32s
= 1;
5578 i
.types
[op
].bitfield
.imm64
= 1;
5580 case BYTE_MNEM_SUFFIX
:
5581 i
.types
[op
].bitfield
.imm8
= 1;
5582 i
.types
[op
].bitfield
.imm8s
= 1;
5583 i
.types
[op
].bitfield
.imm16
= 1;
5584 i
.types
[op
].bitfield
.imm32
= 1;
5585 i
.types
[op
].bitfield
.imm32s
= 1;
5586 i
.types
[op
].bitfield
.imm64
= 1;
5590 /* If this operand is at most 16 bits, convert it
5591 to a signed 16 bit number before trying to see
5592 whether it will fit in an even smaller size.
5593 This allows a 16-bit operand such as $0xffe0 to
5594 be recognised as within Imm8S range. */
5595 if ((i
.types
[op
].bitfield
.imm16
)
5596 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5598 i
.op
[op
].imms
->X_add_number
=
5599 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5602 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5603 if ((i
.types
[op
].bitfield
.imm32
)
5604 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5607 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5608 ^ ((offsetT
) 1 << 31))
5609 - ((offsetT
) 1 << 31));
5613 = operand_type_or (i
.types
[op
],
5614 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5616 /* We must avoid matching of Imm32 templates when 64bit
5617 only immediate is available. */
5618 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5619 i
.types
[op
].bitfield
.imm32
= 0;
5626 /* Symbols and expressions. */
5628 /* Convert symbolic operand to proper sizes for matching, but don't
5629 prevent matching a set of insns that only supports sizes other
5630 than those matching the insn suffix. */
5632 i386_operand_type mask
, allowed
;
5633 const insn_template
*t
;
5635 operand_type_set (&mask
, 0);
5636 operand_type_set (&allowed
, 0);
5638 for (t
= current_templates
->start
;
5639 t
< current_templates
->end
;
5642 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5643 allowed
= operand_type_and (allowed
, anyimm
);
5645 switch (guess_suffix
)
5647 case QWORD_MNEM_SUFFIX
:
5648 mask
.bitfield
.imm64
= 1;
5649 mask
.bitfield
.imm32s
= 1;
5651 case LONG_MNEM_SUFFIX
:
5652 mask
.bitfield
.imm32
= 1;
5654 case WORD_MNEM_SUFFIX
:
5655 mask
.bitfield
.imm16
= 1;
5657 case BYTE_MNEM_SUFFIX
:
5658 mask
.bitfield
.imm8
= 1;
5663 allowed
= operand_type_and (mask
, allowed
);
5664 if (!operand_type_all_zero (&allowed
))
5665 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5672 /* Try to use the smallest displacement type too. */
5674 optimize_disp (void)
5678 for (op
= i
.operands
; --op
>= 0;)
5679 if (operand_type_check (i
.types
[op
], disp
))
5681 if (i
.op
[op
].disps
->X_op
== O_constant
)
5683 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5685 if (i
.types
[op
].bitfield
.disp16
5686 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5688 /* If this operand is at most 16 bits, convert
5689 to a signed 16 bit number and don't use 64bit
5691 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5692 i
.types
[op
].bitfield
.disp64
= 0;
5695 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5696 if (i
.types
[op
].bitfield
.disp32
5697 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5699 /* If this operand is at most 32 bits, convert
5700 to a signed 32 bit number and don't use 64bit
5702 op_disp
&= (((offsetT
) 2 << 31) - 1);
5703 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5704 i
.types
[op
].bitfield
.disp64
= 0;
5707 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5709 i
.types
[op
].bitfield
.disp8
= 0;
5710 i
.types
[op
].bitfield
.disp16
= 0;
5711 i
.types
[op
].bitfield
.disp32
= 0;
5712 i
.types
[op
].bitfield
.disp32s
= 0;
5713 i
.types
[op
].bitfield
.disp64
= 0;
5717 else if (flag_code
== CODE_64BIT
)
5719 if (fits_in_signed_long (op_disp
))
5721 i
.types
[op
].bitfield
.disp64
= 0;
5722 i
.types
[op
].bitfield
.disp32s
= 1;
5724 if (i
.prefix
[ADDR_PREFIX
]
5725 && fits_in_unsigned_long (op_disp
))
5726 i
.types
[op
].bitfield
.disp32
= 1;
5728 if ((i
.types
[op
].bitfield
.disp32
5729 || i
.types
[op
].bitfield
.disp32s
5730 || i
.types
[op
].bitfield
.disp16
)
5731 && fits_in_disp8 (op_disp
))
5732 i
.types
[op
].bitfield
.disp8
= 1;
5734 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5735 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5737 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5738 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5739 i
.types
[op
].bitfield
.disp8
= 0;
5740 i
.types
[op
].bitfield
.disp16
= 0;
5741 i
.types
[op
].bitfield
.disp32
= 0;
5742 i
.types
[op
].bitfield
.disp32s
= 0;
5743 i
.types
[op
].bitfield
.disp64
= 0;
5746 /* We only support 64bit displacement on constants. */
5747 i
.types
[op
].bitfield
.disp64
= 0;
5751 /* Return 1 if there is a match in broadcast bytes between operand
5752 GIVEN and instruction template T. */
5755 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5757 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5758 && i
.types
[given
].bitfield
.byte
)
5759 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5760 && i
.types
[given
].bitfield
.word
)
5761 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5762 && i
.types
[given
].bitfield
.dword
)
5763 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5764 && i
.types
[given
].bitfield
.qword
));
5767 /* Check if operands are valid for the instruction. */
5770 check_VecOperands (const insn_template
*t
)
5775 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5776 any one operand are implicity requiring AVX512VL support if the actual
5777 operand size is YMMword or XMMword. Since this function runs after
5778 template matching, there's no need to check for YMMword/XMMword in
5780 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5781 if (!cpu_flags_all_zero (&cpu
)
5782 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5783 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5785 for (op
= 0; op
< t
->operands
; ++op
)
5787 if (t
->operand_types
[op
].bitfield
.zmmword
5788 && (i
.types
[op
].bitfield
.ymmword
5789 || i
.types
[op
].bitfield
.xmmword
))
5791 i
.error
= unsupported
;
5797 /* Without VSIB byte, we can't have a vector register for index. */
5798 if (!t
->opcode_modifier
.sib
5800 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5801 || i
.index_reg
->reg_type
.bitfield
.ymmword
5802 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5804 i
.error
= unsupported_vector_index_register
;
5808 /* Check if default mask is allowed. */
5809 if (t
->opcode_modifier
.nodefmask
5810 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5812 i
.error
= no_default_mask
;
5816 /* For VSIB byte, we need a vector register for index, and all vector
5817 registers must be distinct. */
5818 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
5821 || !((t
->opcode_modifier
.sib
== VECSIB128
5822 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5823 || (t
->opcode_modifier
.sib
== VECSIB256
5824 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5825 || (t
->opcode_modifier
.sib
== VECSIB512
5826 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5828 i
.error
= invalid_vsib_address
;
5832 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5833 if (i
.reg_operands
== 2 && !i
.mask
)
5835 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5836 gas_assert (i
.types
[0].bitfield
.xmmword
5837 || i
.types
[0].bitfield
.ymmword
);
5838 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5839 gas_assert (i
.types
[2].bitfield
.xmmword
5840 || i
.types
[2].bitfield
.ymmword
);
5841 if (operand_check
== check_none
)
5843 if (register_number (i
.op
[0].regs
)
5844 != register_number (i
.index_reg
)
5845 && register_number (i
.op
[2].regs
)
5846 != register_number (i
.index_reg
)
5847 && register_number (i
.op
[0].regs
)
5848 != register_number (i
.op
[2].regs
))
5850 if (operand_check
== check_error
)
5852 i
.error
= invalid_vector_register_set
;
5855 as_warn (_("mask, index, and destination registers should be distinct"));
5857 else if (i
.reg_operands
== 1 && i
.mask
)
5859 if (i
.types
[1].bitfield
.class == RegSIMD
5860 && (i
.types
[1].bitfield
.xmmword
5861 || i
.types
[1].bitfield
.ymmword
5862 || i
.types
[1].bitfield
.zmmword
)
5863 && (register_number (i
.op
[1].regs
)
5864 == register_number (i
.index_reg
)))
5866 if (operand_check
== check_error
)
5868 i
.error
= invalid_vector_register_set
;
5871 if (operand_check
!= check_none
)
5872 as_warn (_("index and destination registers should be distinct"));
5877 /* For AMX instructions with three tmmword operands, all tmmword operand must be
5879 if (t
->operand_types
[0].bitfield
.tmmword
5880 && i
.reg_operands
== 3)
5882 if (register_number (i
.op
[0].regs
)
5883 == register_number (i
.op
[1].regs
)
5884 || register_number (i
.op
[0].regs
)
5885 == register_number (i
.op
[2].regs
)
5886 || register_number (i
.op
[1].regs
)
5887 == register_number (i
.op
[2].regs
))
5889 i
.error
= invalid_tmm_register_set
;
5894 /* Check if broadcast is supported by the instruction and is applied
5895 to the memory operand. */
5898 i386_operand_type type
, overlap
;
5900 /* Check if specified broadcast is supported in this instruction,
5901 and its broadcast bytes match the memory operand. */
5902 op
= i
.broadcast
->operand
;
5903 if (!t
->opcode_modifier
.broadcast
5904 || !(i
.flags
[op
] & Operand_Mem
)
5905 || (!i
.types
[op
].bitfield
.unspecified
5906 && !match_broadcast_size (t
, op
)))
5909 i
.error
= unsupported_broadcast
;
5913 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5914 * i
.broadcast
->type
);
5915 operand_type_set (&type
, 0);
5916 switch (i
.broadcast
->bytes
)
5919 type
.bitfield
.word
= 1;
5922 type
.bitfield
.dword
= 1;
5925 type
.bitfield
.qword
= 1;
5928 type
.bitfield
.xmmword
= 1;
5931 type
.bitfield
.ymmword
= 1;
5934 type
.bitfield
.zmmword
= 1;
5940 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5941 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5942 && t
->operand_types
[op
].bitfield
.byte
5943 + t
->operand_types
[op
].bitfield
.word
5944 + t
->operand_types
[op
].bitfield
.dword
5945 + t
->operand_types
[op
].bitfield
.qword
> 1)
5947 overlap
.bitfield
.xmmword
= 0;
5948 overlap
.bitfield
.ymmword
= 0;
5949 overlap
.bitfield
.zmmword
= 0;
5951 if (operand_type_all_zero (&overlap
))
5954 if (t
->opcode_modifier
.checkregsize
)
5958 type
.bitfield
.baseindex
= 1;
5959 for (j
= 0; j
< i
.operands
; ++j
)
5962 && !operand_type_register_match(i
.types
[j
],
5963 t
->operand_types
[j
],
5965 t
->operand_types
[op
]))
5970 /* If broadcast is supported in this instruction, we need to check if
5971 operand of one-element size isn't specified without broadcast. */
5972 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5974 /* Find memory operand. */
5975 for (op
= 0; op
< i
.operands
; op
++)
5976 if (i
.flags
[op
] & Operand_Mem
)
5978 gas_assert (op
< i
.operands
);
5979 /* Check size of the memory operand. */
5980 if (match_broadcast_size (t
, op
))
5982 i
.error
= broadcast_needed
;
5987 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5989 /* Check if requested masking is supported. */
5992 switch (t
->opcode_modifier
.masking
)
5996 case MERGING_MASKING
:
5997 if (i
.mask
->zeroing
)
6000 i
.error
= unsupported_masking
;
6004 case DYNAMIC_MASKING
:
6005 /* Memory destinations allow only merging masking. */
6006 if (i
.mask
->zeroing
&& i
.mem_operands
)
6008 /* Find memory operand. */
6009 for (op
= 0; op
< i
.operands
; op
++)
6010 if (i
.flags
[op
] & Operand_Mem
)
6012 gas_assert (op
< i
.operands
);
6013 if (op
== i
.operands
- 1)
6015 i
.error
= unsupported_masking
;
6025 /* Check if masking is applied to dest operand. */
6026 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
6028 i
.error
= mask_not_on_destination
;
6035 if (!t
->opcode_modifier
.sae
6036 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6038 i
.error
= unsupported_rc_sae
;
6041 /* If the instruction has several immediate operands and one of
6042 them is rounding, the rounding operand should be the last
6043 immediate operand. */
6044 if (i
.imm_operands
> 1
6045 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6047 i
.error
= rc_sae_operand_not_last_imm
;
6052 /* Check the special Imm4 cases; must be the first operand. */
6053 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6055 if (i
.op
[0].imms
->X_op
!= O_constant
6056 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6062 /* Turn off Imm<N> so that update_imm won't complain. */
6063 operand_type_set (&i
.types
[0], 0);
6066 /* Check vector Disp8 operand. */
6067 if (t
->opcode_modifier
.disp8memshift
6068 && i
.disp_encoding
!= disp_encoding_32bit
)
6071 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6072 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6073 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6076 const i386_operand_type
*type
= NULL
;
6079 for (op
= 0; op
< i
.operands
; op
++)
6080 if (i
.flags
[op
] & Operand_Mem
)
6082 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6083 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6084 else if (t
->operand_types
[op
].bitfield
.xmmword
6085 + t
->operand_types
[op
].bitfield
.ymmword
6086 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6087 type
= &t
->operand_types
[op
];
6088 else if (!i
.types
[op
].bitfield
.unspecified
)
6089 type
= &i
.types
[op
];
6091 else if (i
.types
[op
].bitfield
.class == RegSIMD
6092 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6094 if (i
.types
[op
].bitfield
.zmmword
)
6096 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6098 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6104 if (type
->bitfield
.zmmword
)
6106 else if (type
->bitfield
.ymmword
)
6108 else if (type
->bitfield
.xmmword
)
6112 /* For the check in fits_in_disp8(). */
6113 if (i
.memshift
== 0)
6117 for (op
= 0; op
< i
.operands
; op
++)
6118 if (operand_type_check (i
.types
[op
], disp
)
6119 && i
.op
[op
].disps
->X_op
== O_constant
)
6121 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6123 i
.types
[op
].bitfield
.disp8
= 1;
6126 i
.types
[op
].bitfield
.disp8
= 0;
6135 /* Check if encoding requirements are met by the instruction. */
6138 VEX_check_encoding (const insn_template
*t
)
6140 if (i
.vec_encoding
== vex_encoding_error
)
6142 i
.error
= unsupported
;
6146 if (i
.vec_encoding
== vex_encoding_evex
)
6148 /* This instruction must be encoded with EVEX prefix. */
6149 if (!is_evex_encoding (t
))
6151 i
.error
= unsupported
;
6157 if (!t
->opcode_modifier
.vex
)
6159 /* This instruction template doesn't have VEX prefix. */
6160 if (i
.vec_encoding
!= vex_encoding_default
)
6162 i
.error
= unsupported
;
6171 static const insn_template
*
6172 match_template (char mnem_suffix
)
6174 /* Points to template once we've found it. */
6175 const insn_template
*t
;
6176 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6177 i386_operand_type overlap4
;
6178 unsigned int found_reverse_match
;
6179 i386_opcode_modifier suffix_check
;
6180 i386_operand_type operand_types
[MAX_OPERANDS
];
6181 int addr_prefix_disp
;
6182 unsigned int j
, size_match
, check_register
;
6183 enum i386_error specific_error
= 0;
6185 #if MAX_OPERANDS != 5
6186 # error "MAX_OPERANDS must be 5."
6189 found_reverse_match
= 0;
6190 addr_prefix_disp
= -1;
6192 /* Prepare for mnemonic suffix check. */
6193 memset (&suffix_check
, 0, sizeof (suffix_check
));
6194 switch (mnem_suffix
)
6196 case BYTE_MNEM_SUFFIX
:
6197 suffix_check
.no_bsuf
= 1;
6199 case WORD_MNEM_SUFFIX
:
6200 suffix_check
.no_wsuf
= 1;
6202 case SHORT_MNEM_SUFFIX
:
6203 suffix_check
.no_ssuf
= 1;
6205 case LONG_MNEM_SUFFIX
:
6206 suffix_check
.no_lsuf
= 1;
6208 case QWORD_MNEM_SUFFIX
:
6209 suffix_check
.no_qsuf
= 1;
6212 /* NB: In Intel syntax, normally we can check for memory operand
6213 size when there is no mnemonic suffix. But jmp and call have
6214 2 different encodings with Dword memory operand size, one with
6215 No_ldSuf and the other without. i.suffix is set to
6216 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6217 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6218 suffix_check
.no_ldsuf
= 1;
6221 /* Must have right number of operands. */
6222 i
.error
= number_of_operands_mismatch
;
6224 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6226 addr_prefix_disp
= -1;
6227 found_reverse_match
= 0;
6229 if (i
.operands
!= t
->operands
)
6232 /* Check processor support. */
6233 i
.error
= unsupported
;
6234 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6237 /* Check AT&T mnemonic. */
6238 i
.error
= unsupported_with_intel_mnemonic
;
6239 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6242 /* Check AT&T/Intel syntax. */
6243 i
.error
= unsupported_syntax
;
6244 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6245 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6248 /* Check Intel64/AMD64 ISA. */
6252 /* Default: Don't accept Intel64. */
6253 if (t
->opcode_modifier
.isa64
== INTEL64
)
6257 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6258 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6262 /* -mintel64: Don't accept AMD64. */
6263 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6268 /* Check the suffix. */
6269 i
.error
= invalid_instruction_suffix
;
6270 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6271 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6272 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6273 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6274 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6275 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6278 size_match
= operand_size_match (t
);
6282 /* This is intentionally not
6284 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6286 as the case of a missing * on the operand is accepted (perhaps with
6287 a warning, issued further down). */
6288 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6290 i
.error
= operand_type_mismatch
;
6294 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6295 operand_types
[j
] = t
->operand_types
[j
];
6297 /* In general, don't allow
6298 - 64-bit operands outside of 64-bit mode,
6299 - 32-bit operands on pre-386. */
6300 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6301 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6302 && flag_code
!= CODE_64BIT
6303 && (t
->base_opcode
!= 0x0fc7
6304 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
6305 || (i
.suffix
== LONG_MNEM_SUFFIX
6306 && !cpu_arch_flags
.bitfield
.cpui386
))
6308 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6309 && !intel_float_operand (t
->name
))
6310 : intel_float_operand (t
->name
) != 2)
6311 && (t
->operands
== i
.imm_operands
6312 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6313 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6314 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6315 || (operand_types
[j
].bitfield
.class != RegMMX
6316 && operand_types
[j
].bitfield
.class != RegSIMD
6317 && operand_types
[j
].bitfield
.class != RegMask
))
6318 && !t
->opcode_modifier
.sib
)
6321 /* Do not verify operands when there are none. */
6324 if (VEX_check_encoding (t
))
6326 specific_error
= i
.error
;
6330 /* We've found a match; break out of loop. */
6334 if (!t
->opcode_modifier
.jump
6335 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6337 /* There should be only one Disp operand. */
6338 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6339 if (operand_type_check (operand_types
[j
], disp
))
6341 if (j
< MAX_OPERANDS
)
6343 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6345 addr_prefix_disp
= j
;
6347 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6348 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6352 override
= !override
;
6355 if (operand_types
[j
].bitfield
.disp32
6356 && operand_types
[j
].bitfield
.disp16
)
6358 operand_types
[j
].bitfield
.disp16
= override
;
6359 operand_types
[j
].bitfield
.disp32
= !override
;
6361 operand_types
[j
].bitfield
.disp32s
= 0;
6362 operand_types
[j
].bitfield
.disp64
= 0;
6366 if (operand_types
[j
].bitfield
.disp32s
6367 || operand_types
[j
].bitfield
.disp64
)
6369 operand_types
[j
].bitfield
.disp64
&= !override
;
6370 operand_types
[j
].bitfield
.disp32s
&= !override
;
6371 operand_types
[j
].bitfield
.disp32
= override
;
6373 operand_types
[j
].bitfield
.disp16
= 0;
6379 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6380 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6383 /* We check register size if needed. */
6384 if (t
->opcode_modifier
.checkregsize
)
6386 check_register
= (1 << t
->operands
) - 1;
6388 check_register
&= ~(1 << i
.broadcast
->operand
);
6393 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6394 switch (t
->operands
)
6397 if (!operand_type_match (overlap0
, i
.types
[0]))
6401 /* xchg %eax, %eax is a special case. It is an alias for nop
6402 only in 32bit mode and we can use opcode 0x90. In 64bit
6403 mode, we can't use 0x90 for xchg %eax, %eax since it should
6404 zero-extend %eax to %rax. */
6405 if (flag_code
== CODE_64BIT
6406 && t
->base_opcode
== 0x90
6407 && i
.types
[0].bitfield
.instance
== Accum
6408 && i
.types
[0].bitfield
.dword
6409 && i
.types
[1].bitfield
.instance
== Accum
6410 && i
.types
[1].bitfield
.dword
)
6412 /* xrelease mov %eax, <disp> is another special case. It must not
6413 match the accumulator-only encoding of mov. */
6414 if (flag_code
!= CODE_64BIT
6416 && t
->base_opcode
== 0xa0
6417 && i
.types
[0].bitfield
.instance
== Accum
6418 && (i
.flags
[1] & Operand_Mem
))
6423 if (!(size_match
& MATCH_STRAIGHT
))
6425 /* Reverse direction of operands if swapping is possible in the first
6426 place (operands need to be symmetric) and
6427 - the load form is requested, and the template is a store form,
6428 - the store form is requested, and the template is a load form,
6429 - the non-default (swapped) form is requested. */
6430 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6431 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6432 && !operand_type_all_zero (&overlap1
))
6433 switch (i
.dir_encoding
)
6435 case dir_encoding_load
:
6436 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6437 || t
->opcode_modifier
.regmem
)
6441 case dir_encoding_store
:
6442 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6443 && !t
->opcode_modifier
.regmem
)
6447 case dir_encoding_swap
:
6450 case dir_encoding_default
:
6453 /* If we want store form, we skip the current load. */
6454 if ((i
.dir_encoding
== dir_encoding_store
6455 || i
.dir_encoding
== dir_encoding_swap
)
6456 && i
.mem_operands
== 0
6457 && t
->opcode_modifier
.load
)
6462 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6463 if (!operand_type_match (overlap0
, i
.types
[0])
6464 || !operand_type_match (overlap1
, i
.types
[1])
6465 || ((check_register
& 3) == 3
6466 && !operand_type_register_match (i
.types
[0],
6471 /* Check if other direction is valid ... */
6472 if (!t
->opcode_modifier
.d
)
6476 if (!(size_match
& MATCH_REVERSE
))
6478 /* Try reversing direction of operands. */
6479 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6480 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6481 if (!operand_type_match (overlap0
, i
.types
[0])
6482 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6484 && !operand_type_register_match (i
.types
[0],
6485 operand_types
[i
.operands
- 1],
6486 i
.types
[i
.operands
- 1],
6489 /* Does not match either direction. */
6492 /* found_reverse_match holds which of D or FloatR
6494 if (!t
->opcode_modifier
.d
)
6495 found_reverse_match
= 0;
6496 else if (operand_types
[0].bitfield
.tbyte
)
6497 found_reverse_match
= Opcode_FloatD
;
6498 else if (operand_types
[0].bitfield
.xmmword
6499 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6500 || operand_types
[0].bitfield
.class == RegMMX
6501 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6502 || is_any_vex_encoding(t
))
6503 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6504 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6506 found_reverse_match
= Opcode_D
;
6507 if (t
->opcode_modifier
.floatr
)
6508 found_reverse_match
|= Opcode_FloatR
;
6512 /* Found a forward 2 operand match here. */
6513 switch (t
->operands
)
6516 overlap4
= operand_type_and (i
.types
[4],
6520 overlap3
= operand_type_and (i
.types
[3],
6524 overlap2
= operand_type_and (i
.types
[2],
6529 switch (t
->operands
)
6532 if (!operand_type_match (overlap4
, i
.types
[4])
6533 || !operand_type_register_match (i
.types
[3],
6540 if (!operand_type_match (overlap3
, i
.types
[3])
6541 || ((check_register
& 0xa) == 0xa
6542 && !operand_type_register_match (i
.types
[1],
6546 || ((check_register
& 0xc) == 0xc
6547 && !operand_type_register_match (i
.types
[2],
6554 /* Here we make use of the fact that there are no
6555 reverse match 3 operand instructions. */
6556 if (!operand_type_match (overlap2
, i
.types
[2])
6557 || ((check_register
& 5) == 5
6558 && !operand_type_register_match (i
.types
[0],
6562 || ((check_register
& 6) == 6
6563 && !operand_type_register_match (i
.types
[1],
6571 /* Found either forward/reverse 2, 3 or 4 operand match here:
6572 slip through to break. */
6575 /* Check if vector operands are valid. */
6576 if (check_VecOperands (t
))
6578 specific_error
= i
.error
;
6582 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6583 if (VEX_check_encoding (t
))
6585 specific_error
= i
.error
;
6589 /* We've found a match; break out of loop. */
6593 if (t
== current_templates
->end
)
6595 /* We found no match. */
6596 const char *err_msg
;
6597 switch (specific_error
? specific_error
: i
.error
)
6601 case operand_size_mismatch
:
6602 err_msg
= _("operand size mismatch");
6604 case operand_type_mismatch
:
6605 err_msg
= _("operand type mismatch");
6607 case register_type_mismatch
:
6608 err_msg
= _("register type mismatch");
6610 case number_of_operands_mismatch
:
6611 err_msg
= _("number of operands mismatch");
6613 case invalid_instruction_suffix
:
6614 err_msg
= _("invalid instruction suffix");
6617 err_msg
= _("constant doesn't fit in 4 bits");
6619 case unsupported_with_intel_mnemonic
:
6620 err_msg
= _("unsupported with Intel mnemonic");
6622 case unsupported_syntax
:
6623 err_msg
= _("unsupported syntax");
6626 as_bad (_("unsupported instruction `%s'"),
6627 current_templates
->start
->name
);
6629 case invalid_sib_address
:
6630 err_msg
= _("invalid SIB address");
6632 case invalid_vsib_address
:
6633 err_msg
= _("invalid VSIB address");
6635 case invalid_vector_register_set
:
6636 err_msg
= _("mask, index, and destination registers must be distinct");
6638 case invalid_tmm_register_set
:
6639 err_msg
= _("all tmm registers must be distinct");
6641 case unsupported_vector_index_register
:
6642 err_msg
= _("unsupported vector index register");
6644 case unsupported_broadcast
:
6645 err_msg
= _("unsupported broadcast");
6647 case broadcast_needed
:
6648 err_msg
= _("broadcast is needed for operand of such type");
6650 case unsupported_masking
:
6651 err_msg
= _("unsupported masking");
6653 case mask_not_on_destination
:
6654 err_msg
= _("mask not on destination operand");
6656 case no_default_mask
:
6657 err_msg
= _("default mask isn't allowed");
6659 case unsupported_rc_sae
:
6660 err_msg
= _("unsupported static rounding/sae");
6662 case rc_sae_operand_not_last_imm
:
6664 err_msg
= _("RC/SAE operand must precede immediate operands");
6666 err_msg
= _("RC/SAE operand must follow immediate operands");
6668 case invalid_register_operand
:
6669 err_msg
= _("invalid register operand");
6672 as_bad (_("%s for `%s'"), err_msg
,
6673 current_templates
->start
->name
);
6677 if (!quiet_warnings
)
6680 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6681 as_warn (_("indirect %s without `*'"), t
->name
);
6683 if (t
->opcode_modifier
.isprefix
6684 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6686 /* Warn them that a data or address size prefix doesn't
6687 affect assembly of the next line of code. */
6688 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6692 /* Copy the template we found. */
6695 if (addr_prefix_disp
!= -1)
6696 i
.tm
.operand_types
[addr_prefix_disp
]
6697 = operand_types
[addr_prefix_disp
];
6699 if (found_reverse_match
)
6701 /* If we found a reverse match we must alter the opcode direction
6702 bit and clear/flip the regmem modifier one. found_reverse_match
6703 holds bits to change (different for int & float insns). */
6705 i
.tm
.base_opcode
^= found_reverse_match
;
6707 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6708 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6710 /* Certain SIMD insns have their load forms specified in the opcode
6711 table, and hence we need to _set_ RegMem instead of clearing it.
6712 We need to avoid setting the bit though on insns like KMOVW. */
6713 i
.tm
.opcode_modifier
.regmem
6714 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6715 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6716 && !i
.tm
.opcode_modifier
.regmem
;
6725 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6726 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6728 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6730 as_bad (_("`%s' operand %u must use `%ses' segment"),
6732 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6737 /* There's only ever one segment override allowed per instruction.
6738 This instruction possibly has a legal segment override on the
6739 second operand, so copy the segment to where non-string
6740 instructions store it, allowing common code. */
6741 i
.seg
[op
] = i
.seg
[1];
6747 process_suffix (void)
6749 /* If matched instruction specifies an explicit instruction mnemonic
6751 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6752 i
.suffix
= WORD_MNEM_SUFFIX
;
6753 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6754 i
.suffix
= LONG_MNEM_SUFFIX
;
6755 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6756 i
.suffix
= QWORD_MNEM_SUFFIX
;
6757 else if (i
.reg_operands
6758 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6759 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6761 unsigned int numop
= i
.operands
;
6763 /* movsx/movzx want only their source operand considered here, for the
6764 ambiguity checking below. The suffix will be replaced afterwards
6765 to represent the destination (register). */
6766 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6767 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6770 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6771 if (i
.tm
.base_opcode
== 0xf20f38f0
6772 && i
.tm
.operand_types
[1].bitfield
.qword
)
6775 /* If there's no instruction mnemonic suffix we try to invent one
6776 based on GPR operands. */
6779 /* We take i.suffix from the last register operand specified,
6780 Destination register type is more significant than source
6781 register type. crc32 in SSE4.2 prefers source register
6783 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6786 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6787 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6789 if (i
.types
[op
].bitfield
.class != Reg
)
6791 if (i
.types
[op
].bitfield
.byte
)
6792 i
.suffix
= BYTE_MNEM_SUFFIX
;
6793 else if (i
.types
[op
].bitfield
.word
)
6794 i
.suffix
= WORD_MNEM_SUFFIX
;
6795 else if (i
.types
[op
].bitfield
.dword
)
6796 i
.suffix
= LONG_MNEM_SUFFIX
;
6797 else if (i
.types
[op
].bitfield
.qword
)
6798 i
.suffix
= QWORD_MNEM_SUFFIX
;
6804 /* As an exception, movsx/movzx silently default to a byte source
6806 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6807 && !i
.suffix
&& !intel_syntax
)
6808 i
.suffix
= BYTE_MNEM_SUFFIX
;
6810 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6813 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6814 && i
.tm
.opcode_modifier
.no_bsuf
)
6816 else if (!check_byte_reg ())
6819 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6822 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6823 && i
.tm
.opcode_modifier
.no_lsuf
6824 && !i
.tm
.opcode_modifier
.todword
6825 && !i
.tm
.opcode_modifier
.toqword
)
6827 else if (!check_long_reg ())
6830 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6833 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6834 && i
.tm
.opcode_modifier
.no_qsuf
6835 && !i
.tm
.opcode_modifier
.todword
6836 && !i
.tm
.opcode_modifier
.toqword
)
6838 else if (!check_qword_reg ())
6841 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6844 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6845 && i
.tm
.opcode_modifier
.no_wsuf
)
6847 else if (!check_word_reg ())
6850 else if (intel_syntax
6851 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6852 /* Do nothing if the instruction is going to ignore the prefix. */
6857 /* Undo the movsx/movzx change done above. */
6860 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6863 i
.suffix
= stackop_size
;
6864 if (stackop_size
== LONG_MNEM_SUFFIX
)
6866 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6867 .code16gcc directive to support 16-bit mode with
6868 32-bit address. For IRET without a suffix, generate
6869 16-bit IRET (opcode 0xcf) to return from an interrupt
6871 if (i
.tm
.base_opcode
== 0xcf)
6873 i
.suffix
= WORD_MNEM_SUFFIX
;
6874 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6876 /* Warn about changed behavior for segment register push/pop. */
6877 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6878 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6883 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6884 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6885 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6886 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6887 && i
.tm
.extension_opcode
<= 3)))
6892 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6894 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6895 || i
.tm
.opcode_modifier
.no_lsuf
)
6896 i
.suffix
= QWORD_MNEM_SUFFIX
;
6901 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6902 i
.suffix
= LONG_MNEM_SUFFIX
;
6905 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6906 i
.suffix
= WORD_MNEM_SUFFIX
;
6912 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6913 /* Also cover lret/retf/iret in 64-bit mode. */
6914 || (flag_code
== CODE_64BIT
6915 && !i
.tm
.opcode_modifier
.no_lsuf
6916 && !i
.tm
.opcode_modifier
.no_qsuf
))
6917 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6918 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6919 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
6920 /* Accept FLDENV et al without suffix. */
6921 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6923 unsigned int suffixes
, evex
= 0;
6925 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6926 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6928 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6930 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6932 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6934 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6937 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6938 also suitable for AT&T syntax mode, it was requested that this be
6939 restricted to just Intel syntax. */
6940 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6944 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6946 if (is_evex_encoding (&i
.tm
)
6947 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6949 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6950 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6951 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6952 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6953 if (!i
.tm
.opcode_modifier
.evex
6954 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6955 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6958 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6959 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6960 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6963 /* Any properly sized operand disambiguates the insn. */
6964 if (i
.types
[op
].bitfield
.xmmword
6965 || i
.types
[op
].bitfield
.ymmword
6966 || i
.types
[op
].bitfield
.zmmword
)
6968 suffixes
&= ~(7 << 6);
6973 if ((i
.flags
[op
] & Operand_Mem
)
6974 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6976 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6978 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6980 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6982 if (is_evex_encoding (&i
.tm
))
6988 /* Are multiple suffixes / operand sizes allowed? */
6989 if (suffixes
& (suffixes
- 1))
6992 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6993 || operand_check
== check_error
))
6995 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6998 if (operand_check
== check_error
)
7000 as_bad (_("no instruction mnemonic suffix given and "
7001 "no register operands; can't size `%s'"), i
.tm
.name
);
7004 if (operand_check
== check_warning
)
7005 as_warn (_("%s; using default for `%s'"),
7007 ? _("ambiguous operand size")
7008 : _("no instruction mnemonic suffix given and "
7009 "no register operands"),
7012 if (i
.tm
.opcode_modifier
.floatmf
)
7013 i
.suffix
= SHORT_MNEM_SUFFIX
;
7014 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
7015 || (i
.tm
.base_opcode
== 0x63
7016 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7017 /* handled below */;
7019 i
.tm
.opcode_modifier
.evex
= evex
;
7020 else if (flag_code
== CODE_16BIT
)
7021 i
.suffix
= WORD_MNEM_SUFFIX
;
7022 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7023 i
.suffix
= LONG_MNEM_SUFFIX
;
7025 i
.suffix
= QWORD_MNEM_SUFFIX
;
7029 if ((i
.tm
.base_opcode
| 8) == 0xfbe
7030 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7032 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7033 In AT&T syntax, if there is no suffix (warned about above), the default
7034 will be byte extension. */
7035 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7036 i
.tm
.base_opcode
|= 1;
7038 /* For further processing, the suffix should represent the destination
7039 (register). This is already the case when one was used with
7040 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7041 no suffix to begin with. */
7042 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7044 if (i
.types
[1].bitfield
.word
)
7045 i
.suffix
= WORD_MNEM_SUFFIX
;
7046 else if (i
.types
[1].bitfield
.qword
)
7047 i
.suffix
= QWORD_MNEM_SUFFIX
;
7049 i
.suffix
= LONG_MNEM_SUFFIX
;
7051 i
.tm
.opcode_modifier
.w
= 0;
7055 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7056 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7057 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7059 /* Change the opcode based on the operand size given by i.suffix. */
7062 /* Size floating point instruction. */
7063 case LONG_MNEM_SUFFIX
:
7064 if (i
.tm
.opcode_modifier
.floatmf
)
7066 i
.tm
.base_opcode
^= 4;
7070 case WORD_MNEM_SUFFIX
:
7071 case QWORD_MNEM_SUFFIX
:
7072 /* It's not a byte, select word/dword operation. */
7073 if (i
.tm
.opcode_modifier
.w
)
7076 i
.tm
.base_opcode
|= 8;
7078 i
.tm
.base_opcode
|= 1;
7081 case SHORT_MNEM_SUFFIX
:
7082 /* Now select between word & dword operations via the operand
7083 size prefix, except for instructions that will ignore this
7085 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7086 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7087 && !i
.tm
.opcode_modifier
.floatmf
7088 && !is_any_vex_encoding (&i
.tm
)
7089 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7090 || (flag_code
== CODE_64BIT
7091 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7093 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7095 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7096 prefix
= ADDR_PREFIX_OPCODE
;
7098 if (!add_prefix (prefix
))
7102 /* Set mode64 for an operand. */
7103 if (i
.suffix
== QWORD_MNEM_SUFFIX
7104 && flag_code
== CODE_64BIT
7105 && !i
.tm
.opcode_modifier
.norex64
7106 && !i
.tm
.opcode_modifier
.vexw
7107 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7109 && ! (i
.operands
== 2
7110 && i
.tm
.base_opcode
== 0x90
7111 && i
.tm
.extension_opcode
== None
7112 && i
.types
[0].bitfield
.instance
== Accum
7113 && i
.types
[0].bitfield
.qword
7114 && i
.types
[1].bitfield
.instance
== Accum
7115 && i
.types
[1].bitfield
.qword
))
7121 /* Select word/dword/qword operation with explict data sizing prefix
7122 when there are no suitable register operands. */
7123 if (i
.tm
.opcode_modifier
.w
7124 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7126 || (i
.reg_operands
== 1
7128 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7130 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7131 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7133 || i
.tm
.base_opcode
== 0xf20f38f0))))
7134 i
.tm
.base_opcode
|= 1;
7138 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7140 gas_assert (!i
.suffix
);
7141 gas_assert (i
.reg_operands
);
7143 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7146 /* The address size override prefix changes the size of the
7148 if (flag_code
== CODE_64BIT
7149 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7151 as_bad (_("16-bit addressing unavailable for `%s'"),
7156 if ((flag_code
== CODE_32BIT
7157 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7158 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7159 && !add_prefix (ADDR_PREFIX_OPCODE
))
7164 /* Check invalid register operand when the address size override
7165 prefix changes the size of register operands. */
7167 enum { need_word
, need_dword
, need_qword
} need
;
7169 if (flag_code
== CODE_32BIT
)
7170 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7171 else if (i
.prefix
[ADDR_PREFIX
])
7174 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7176 for (op
= 0; op
< i
.operands
; op
++)
7178 if (i
.types
[op
].bitfield
.class != Reg
)
7184 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7188 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7192 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7197 as_bad (_("invalid register operand size for `%s'"),
7208 check_byte_reg (void)
7212 for (op
= i
.operands
; --op
>= 0;)
7214 /* Skip non-register operands. */
7215 if (i
.types
[op
].bitfield
.class != Reg
)
7218 /* If this is an eight bit register, it's OK. If it's the 16 or
7219 32 bit version of an eight bit register, we will just use the
7220 low portion, and that's OK too. */
7221 if (i
.types
[op
].bitfield
.byte
)
7224 /* I/O port address operands are OK too. */
7225 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7226 && i
.tm
.operand_types
[op
].bitfield
.word
)
7229 /* crc32 only wants its source operand checked here. */
7230 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
7233 /* Any other register is bad. */
7234 as_bad (_("`%s%s' not allowed with `%s%c'"),
7235 register_prefix
, i
.op
[op
].regs
->reg_name
,
7236 i
.tm
.name
, i
.suffix
);
7243 check_long_reg (void)
7247 for (op
= i
.operands
; --op
>= 0;)
7248 /* Skip non-register operands. */
7249 if (i
.types
[op
].bitfield
.class != Reg
)
7251 /* Reject eight bit registers, except where the template requires
7252 them. (eg. movzb) */
7253 else if (i
.types
[op
].bitfield
.byte
7254 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7255 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7256 && (i
.tm
.operand_types
[op
].bitfield
.word
7257 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7259 as_bad (_("`%s%s' not allowed with `%s%c'"),
7261 i
.op
[op
].regs
->reg_name
,
7266 /* Error if the e prefix on a general reg is missing. */
7267 else if (i
.types
[op
].bitfield
.word
7268 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7269 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7270 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7272 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7273 register_prefix
, i
.op
[op
].regs
->reg_name
,
7277 /* Warn if the r prefix on a general reg is present. */
7278 else if (i
.types
[op
].bitfield
.qword
7279 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7280 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7281 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7284 && i
.tm
.opcode_modifier
.toqword
7285 && i
.types
[0].bitfield
.class != RegSIMD
)
7287 /* Convert to QWORD. We want REX byte. */
7288 i
.suffix
= QWORD_MNEM_SUFFIX
;
7292 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7293 register_prefix
, i
.op
[op
].regs
->reg_name
,
7302 check_qword_reg (void)
7306 for (op
= i
.operands
; --op
>= 0; )
7307 /* Skip non-register operands. */
7308 if (i
.types
[op
].bitfield
.class != Reg
)
7310 /* Reject eight bit registers, except where the template requires
7311 them. (eg. movzb) */
7312 else if (i
.types
[op
].bitfield
.byte
7313 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7314 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7315 && (i
.tm
.operand_types
[op
].bitfield
.word
7316 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7318 as_bad (_("`%s%s' not allowed with `%s%c'"),
7320 i
.op
[op
].regs
->reg_name
,
7325 /* Warn if the r prefix on a general reg is missing. */
7326 else if ((i
.types
[op
].bitfield
.word
7327 || i
.types
[op
].bitfield
.dword
)
7328 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7329 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7330 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7332 /* Prohibit these changes in the 64bit mode, since the
7333 lowering is more complicated. */
7335 && i
.tm
.opcode_modifier
.todword
7336 && i
.types
[0].bitfield
.class != RegSIMD
)
7338 /* Convert to DWORD. We don't want REX byte. */
7339 i
.suffix
= LONG_MNEM_SUFFIX
;
7343 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7344 register_prefix
, i
.op
[op
].regs
->reg_name
,
7353 check_word_reg (void)
7356 for (op
= i
.operands
; --op
>= 0;)
7357 /* Skip non-register operands. */
7358 if (i
.types
[op
].bitfield
.class != Reg
)
7360 /* Reject eight bit registers, except where the template requires
7361 them. (eg. movzb) */
7362 else if (i
.types
[op
].bitfield
.byte
7363 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7364 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7365 && (i
.tm
.operand_types
[op
].bitfield
.word
7366 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7368 as_bad (_("`%s%s' not allowed with `%s%c'"),
7370 i
.op
[op
].regs
->reg_name
,
7375 /* Error if the e or r prefix on a general reg is present. */
7376 else if ((i
.types
[op
].bitfield
.dword
7377 || i
.types
[op
].bitfield
.qword
)
7378 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7379 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7380 && i
.tm
.operand_types
[op
].bitfield
.word
)
7382 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7383 register_prefix
, i
.op
[op
].regs
->reg_name
,
7391 update_imm (unsigned int j
)
7393 i386_operand_type overlap
= i
.types
[j
];
7394 if ((overlap
.bitfield
.imm8
7395 || overlap
.bitfield
.imm8s
7396 || overlap
.bitfield
.imm16
7397 || overlap
.bitfield
.imm32
7398 || overlap
.bitfield
.imm32s
7399 || overlap
.bitfield
.imm64
)
7400 && !operand_type_equal (&overlap
, &imm8
)
7401 && !operand_type_equal (&overlap
, &imm8s
)
7402 && !operand_type_equal (&overlap
, &imm16
)
7403 && !operand_type_equal (&overlap
, &imm32
)
7404 && !operand_type_equal (&overlap
, &imm32s
)
7405 && !operand_type_equal (&overlap
, &imm64
))
7409 i386_operand_type temp
;
7411 operand_type_set (&temp
, 0);
7412 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7414 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7415 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7417 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7418 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7419 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7421 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7422 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7425 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7428 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7429 || operand_type_equal (&overlap
, &imm16_32
)
7430 || operand_type_equal (&overlap
, &imm16_32s
))
7432 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7437 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7438 overlap
= operand_type_and (overlap
, imm32s
);
7439 else if (i
.prefix
[DATA_PREFIX
])
7440 overlap
= operand_type_and (overlap
,
7441 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7442 if (!operand_type_equal (&overlap
, &imm8
)
7443 && !operand_type_equal (&overlap
, &imm8s
)
7444 && !operand_type_equal (&overlap
, &imm16
)
7445 && !operand_type_equal (&overlap
, &imm32
)
7446 && !operand_type_equal (&overlap
, &imm32s
)
7447 && !operand_type_equal (&overlap
, &imm64
))
7449 as_bad (_("no instruction mnemonic suffix given; "
7450 "can't determine immediate size"));
7454 i
.types
[j
] = overlap
;
7464 /* Update the first 2 immediate operands. */
7465 n
= i
.operands
> 2 ? 2 : i
.operands
;
7468 for (j
= 0; j
< n
; j
++)
7469 if (update_imm (j
) == 0)
7472 /* The 3rd operand can't be immediate operand. */
7473 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7480 process_operands (void)
7482 /* Default segment register this instruction will use for memory
7483 accesses. 0 means unknown. This is only for optimizing out
7484 unnecessary segment overrides. */
7485 const seg_entry
*default_seg
= 0;
7487 if (i
.tm
.opcode_modifier
.sse2avx
)
7489 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7491 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7492 i
.prefix
[REX_PREFIX
] = 0;
7495 /* ImmExt should be processed after SSE2AVX. */
7496 else if (i
.tm
.opcode_modifier
.immext
)
7499 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7501 unsigned int dupl
= i
.operands
;
7502 unsigned int dest
= dupl
- 1;
7505 /* The destination must be an xmm register. */
7506 gas_assert (i
.reg_operands
7507 && MAX_OPERANDS
> dupl
7508 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7510 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7511 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7513 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7515 /* Keep xmm0 for instructions with VEX prefix and 3
7517 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7518 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7523 /* We remove the first xmm0 and keep the number of
7524 operands unchanged, which in fact duplicates the
7526 for (j
= 1; j
< i
.operands
; j
++)
7528 i
.op
[j
- 1] = i
.op
[j
];
7529 i
.types
[j
- 1] = i
.types
[j
];
7530 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7531 i
.flags
[j
- 1] = i
.flags
[j
];
7535 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7537 gas_assert ((MAX_OPERANDS
- 1) > dupl
7538 && (i
.tm
.opcode_modifier
.vexsources
7541 /* Add the implicit xmm0 for instructions with VEX prefix
7543 for (j
= i
.operands
; j
> 0; j
--)
7545 i
.op
[j
] = i
.op
[j
- 1];
7546 i
.types
[j
] = i
.types
[j
- 1];
7547 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7548 i
.flags
[j
] = i
.flags
[j
- 1];
7551 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7552 i
.types
[0] = regxmm
;
7553 i
.tm
.operand_types
[0] = regxmm
;
7556 i
.reg_operands
+= 2;
7561 i
.op
[dupl
] = i
.op
[dest
];
7562 i
.types
[dupl
] = i
.types
[dest
];
7563 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7564 i
.flags
[dupl
] = i
.flags
[dest
];
7573 i
.op
[dupl
] = i
.op
[dest
];
7574 i
.types
[dupl
] = i
.types
[dest
];
7575 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7576 i
.flags
[dupl
] = i
.flags
[dest
];
7579 if (i
.tm
.opcode_modifier
.immext
)
7582 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7583 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7587 for (j
= 1; j
< i
.operands
; j
++)
7589 i
.op
[j
- 1] = i
.op
[j
];
7590 i
.types
[j
- 1] = i
.types
[j
];
7592 /* We need to adjust fields in i.tm since they are used by
7593 build_modrm_byte. */
7594 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7596 i
.flags
[j
- 1] = i
.flags
[j
];
7603 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7605 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7607 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7608 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7609 regnum
= register_number (i
.op
[1].regs
);
7610 first_reg_in_group
= regnum
& ~3;
7611 last_reg_in_group
= first_reg_in_group
+ 3;
7612 if (regnum
!= first_reg_in_group
)
7613 as_warn (_("source register `%s%s' implicitly denotes"
7614 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7615 register_prefix
, i
.op
[1].regs
->reg_name
,
7616 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7617 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7620 else if (i
.tm
.opcode_modifier
.regkludge
)
7622 /* The imul $imm, %reg instruction is converted into
7623 imul $imm, %reg, %reg, and the clr %reg instruction
7624 is converted into xor %reg, %reg. */
7626 unsigned int first_reg_op
;
7628 if (operand_type_check (i
.types
[0], reg
))
7632 /* Pretend we saw the extra register operand. */
7633 gas_assert (i
.reg_operands
== 1
7634 && i
.op
[first_reg_op
+ 1].regs
== 0);
7635 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7636 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7641 if (i
.tm
.opcode_modifier
.modrm
)
7643 /* The opcode is completed (modulo i.tm.extension_opcode which
7644 must be put into the modrm byte). Now, we make the modrm and
7645 index base bytes based on all the info we've collected. */
7647 default_seg
= build_modrm_byte ();
7649 else if (i
.types
[0].bitfield
.class == SReg
)
7651 if (flag_code
!= CODE_64BIT
7652 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7653 && i
.op
[0].regs
->reg_num
== 1
7654 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7655 && i
.op
[0].regs
->reg_num
< 4)
7657 as_bad (_("you can't `%s %s%s'"),
7658 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7661 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7663 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7664 i
.tm
.opcode_length
= 2;
7666 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7668 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7672 else if (i
.tm
.opcode_modifier
.isstring
)
7674 /* For the string instructions that allow a segment override
7675 on one of their operands, the default segment is ds. */
7678 else if (i
.short_form
)
7680 /* The register or float register operand is in operand
7682 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7684 /* Register goes in low 3 bits of opcode. */
7685 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7686 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7688 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7690 /* Warn about some common errors, but press on regardless.
7691 The first case can be generated by gcc (<= 2.8.1). */
7692 if (i
.operands
== 2)
7694 /* Reversed arguments on faddp, fsubp, etc. */
7695 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7696 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7697 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7701 /* Extraneous `l' suffix on fp insn. */
7702 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7703 register_prefix
, i
.op
[0].regs
->reg_name
);
7708 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7709 && i
.tm
.base_opcode
== 0x8d /* lea */
7710 && !is_any_vex_encoding(&i
.tm
))
7712 if (!quiet_warnings
)
7713 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7717 i
.prefix
[SEG_PREFIX
] = 0;
7721 /* If a segment was explicitly specified, and the specified segment
7722 is neither the default nor the one already recorded from a prefix,
7723 use an opcode prefix to select it. If we never figured out what
7724 the default segment is, then default_seg will be zero at this
7725 point, and the specified segment prefix will always be used. */
7727 && i
.seg
[0] != default_seg
7728 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7730 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7736 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7737 bfd_boolean do_sse2avx
)
7739 if (r
->reg_flags
& RegRex
)
7741 if (i
.rex
& rex_bit
)
7742 as_bad (_("same type of prefix used twice"));
7745 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7747 gas_assert (i
.vex
.register_specifier
== r
);
7748 i
.vex
.register_specifier
+= 8;
7751 if (r
->reg_flags
& RegVRex
)
7755 static const seg_entry
*
7756 build_modrm_byte (void)
7758 const seg_entry
*default_seg
= 0;
7759 unsigned int source
, dest
;
7762 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7765 unsigned int nds
, reg_slot
;
7768 dest
= i
.operands
- 1;
7771 /* There are 2 kinds of instructions:
7772 1. 5 operands: 4 register operands or 3 register operands
7773 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7774 VexW0 or VexW1. The destination must be either XMM, YMM or
7776 2. 4 operands: 4 register operands or 3 register operands
7777 plus 1 memory operand, with VexXDS. */
7778 gas_assert ((i
.reg_operands
== 4
7779 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7780 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7781 && i
.tm
.opcode_modifier
.vexw
7782 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7784 /* If VexW1 is set, the first non-immediate operand is the source and
7785 the second non-immediate one is encoded in the immediate operand. */
7786 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7788 source
= i
.imm_operands
;
7789 reg_slot
= i
.imm_operands
+ 1;
7793 source
= i
.imm_operands
+ 1;
7794 reg_slot
= i
.imm_operands
;
7797 if (i
.imm_operands
== 0)
7799 /* When there is no immediate operand, generate an 8bit
7800 immediate operand to encode the first operand. */
7801 exp
= &im_expressions
[i
.imm_operands
++];
7802 i
.op
[i
.operands
].imms
= exp
;
7803 i
.types
[i
.operands
] = imm8
;
7806 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7807 exp
->X_op
= O_constant
;
7808 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7809 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7813 gas_assert (i
.imm_operands
== 1);
7814 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7815 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7817 /* Turn on Imm8 again so that output_imm will generate it. */
7818 i
.types
[0].bitfield
.imm8
= 1;
7820 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7821 i
.op
[0].imms
->X_add_number
7822 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7823 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7826 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7827 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7832 /* i.reg_operands MUST be the number of real register operands;
7833 implicit registers do not count. If there are 3 register
7834 operands, it must be a instruction with VexNDS. For a
7835 instruction with VexNDD, the destination register is encoded
7836 in VEX prefix. If there are 4 register operands, it must be
7837 a instruction with VEX prefix and 3 sources. */
7838 if (i
.mem_operands
== 0
7839 && ((i
.reg_operands
== 2
7840 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7841 || (i
.reg_operands
== 3
7842 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7843 || (i
.reg_operands
== 4 && vex_3_sources
)))
7851 /* When there are 3 operands, one of them may be immediate,
7852 which may be the first or the last operand. Otherwise,
7853 the first operand must be shift count register (cl) or it
7854 is an instruction with VexNDS. */
7855 gas_assert (i
.imm_operands
== 1
7856 || (i
.imm_operands
== 0
7857 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7858 || (i
.types
[0].bitfield
.instance
== RegC
7859 && i
.types
[0].bitfield
.byte
))));
7860 if (operand_type_check (i
.types
[0], imm
)
7861 || (i
.types
[0].bitfield
.instance
== RegC
7862 && i
.types
[0].bitfield
.byte
))
7868 /* When there are 4 operands, the first two must be 8bit
7869 immediate operands. The source operand will be the 3rd
7872 For instructions with VexNDS, if the first operand
7873 an imm8, the source operand is the 2nd one. If the last
7874 operand is imm8, the source operand is the first one. */
7875 gas_assert ((i
.imm_operands
== 2
7876 && i
.types
[0].bitfield
.imm8
7877 && i
.types
[1].bitfield
.imm8
)
7878 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7879 && i
.imm_operands
== 1
7880 && (i
.types
[0].bitfield
.imm8
7881 || i
.types
[i
.operands
- 1].bitfield
.imm8
7883 if (i
.imm_operands
== 2)
7887 if (i
.types
[0].bitfield
.imm8
)
7894 if (is_evex_encoding (&i
.tm
))
7896 /* For EVEX instructions, when there are 5 operands, the
7897 first one must be immediate operand. If the second one
7898 is immediate operand, the source operand is the 3th
7899 one. If the last one is immediate operand, the source
7900 operand is the 2nd one. */
7901 gas_assert (i
.imm_operands
== 2
7902 && i
.tm
.opcode_modifier
.sae
7903 && operand_type_check (i
.types
[0], imm
));
7904 if (operand_type_check (i
.types
[1], imm
))
7906 else if (operand_type_check (i
.types
[4], imm
))
7920 /* RC/SAE operand could be between DEST and SRC. That happens
7921 when one operand is GPR and the other one is XMM/YMM/ZMM
7923 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7926 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7928 /* For instructions with VexNDS, the register-only source
7929 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7930 register. It is encoded in VEX prefix. */
7932 i386_operand_type op
;
7935 /* Swap two source operands if needed. */
7936 if (i
.tm
.opcode_modifier
.swapsources
)
7944 op
= i
.tm
.operand_types
[vvvv
];
7945 if ((dest
+ 1) >= i
.operands
7946 || ((op
.bitfield
.class != Reg
7947 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7948 && op
.bitfield
.class != RegSIMD
7949 && !operand_type_equal (&op
, ®mask
)))
7951 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7957 /* One of the register operands will be encoded in the i.rm.reg
7958 field, the other in the combined i.rm.mode and i.rm.regmem
7959 fields. If no form of this instruction supports a memory
7960 destination operand, then we assume the source operand may
7961 sometimes be a memory operand and so we need to store the
7962 destination in the i.rm.reg field. */
7963 if (!i
.tm
.opcode_modifier
.regmem
7964 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7966 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7967 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7968 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
7969 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
7973 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7974 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7975 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
7976 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
7978 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7980 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7983 add_prefix (LOCK_PREFIX_OPCODE
);
7987 { /* If it's not 2 reg operands... */
7992 unsigned int fake_zero_displacement
= 0;
7995 for (op
= 0; op
< i
.operands
; op
++)
7996 if (i
.flags
[op
] & Operand_Mem
)
7998 gas_assert (op
< i
.operands
);
8000 if (i
.tm
.opcode_modifier
.sib
)
8002 /* The index register of VSIB shouldn't be RegIZ. */
8003 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8004 && i
.index_reg
->reg_num
== RegIZ
)
8007 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8010 i
.sib
.base
= NO_BASE_REGISTER
;
8011 i
.sib
.scale
= i
.log2_scale_factor
;
8012 i
.types
[op
].bitfield
.disp8
= 0;
8013 i
.types
[op
].bitfield
.disp16
= 0;
8014 i
.types
[op
].bitfield
.disp64
= 0;
8015 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8017 /* Must be 32 bit */
8018 i
.types
[op
].bitfield
.disp32
= 1;
8019 i
.types
[op
].bitfield
.disp32s
= 0;
8023 i
.types
[op
].bitfield
.disp32
= 0;
8024 i
.types
[op
].bitfield
.disp32s
= 1;
8028 /* Since the mandatory SIB always has index register, so
8029 the code logic remains unchanged. The non-mandatory SIB
8030 without index register is allowed and will be handled
8034 if (i
.index_reg
->reg_num
== RegIZ
)
8035 i
.sib
.index
= NO_INDEX_REGISTER
;
8037 i
.sib
.index
= i
.index_reg
->reg_num
;
8038 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
8044 if (i
.base_reg
== 0)
8047 if (!i
.disp_operands
)
8048 fake_zero_displacement
= 1;
8049 if (i
.index_reg
== 0)
8051 i386_operand_type newdisp
;
8053 /* Both check for VSIB and mandatory non-vector SIB. */
8054 gas_assert (!i
.tm
.opcode_modifier
.sib
8055 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8056 /* Operand is just <disp> */
8057 if (flag_code
== CODE_64BIT
)
8059 /* 64bit mode overwrites the 32bit absolute
8060 addressing by RIP relative addressing and
8061 absolute addressing is encoded by one of the
8062 redundant SIB forms. */
8063 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8064 i
.sib
.base
= NO_BASE_REGISTER
;
8065 i
.sib
.index
= NO_INDEX_REGISTER
;
8066 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
8068 else if ((flag_code
== CODE_16BIT
)
8069 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8071 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8076 i
.rm
.regmem
= NO_BASE_REGISTER
;
8079 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8080 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8082 else if (!i
.tm
.opcode_modifier
.sib
)
8084 /* !i.base_reg && i.index_reg */
8085 if (i
.index_reg
->reg_num
== RegIZ
)
8086 i
.sib
.index
= NO_INDEX_REGISTER
;
8088 i
.sib
.index
= i
.index_reg
->reg_num
;
8089 i
.sib
.base
= NO_BASE_REGISTER
;
8090 i
.sib
.scale
= i
.log2_scale_factor
;
8091 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8092 i
.types
[op
].bitfield
.disp8
= 0;
8093 i
.types
[op
].bitfield
.disp16
= 0;
8094 i
.types
[op
].bitfield
.disp64
= 0;
8095 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8097 /* Must be 32 bit */
8098 i
.types
[op
].bitfield
.disp32
= 1;
8099 i
.types
[op
].bitfield
.disp32s
= 0;
8103 i
.types
[op
].bitfield
.disp32
= 0;
8104 i
.types
[op
].bitfield
.disp32s
= 1;
8106 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8110 /* RIP addressing for 64bit mode. */
8111 else if (i
.base_reg
->reg_num
== RegIP
)
8113 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8114 i
.rm
.regmem
= NO_BASE_REGISTER
;
8115 i
.types
[op
].bitfield
.disp8
= 0;
8116 i
.types
[op
].bitfield
.disp16
= 0;
8117 i
.types
[op
].bitfield
.disp32
= 0;
8118 i
.types
[op
].bitfield
.disp32s
= 1;
8119 i
.types
[op
].bitfield
.disp64
= 0;
8120 i
.flags
[op
] |= Operand_PCrel
;
8121 if (! i
.disp_operands
)
8122 fake_zero_displacement
= 1;
8124 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8126 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8127 switch (i
.base_reg
->reg_num
)
8130 if (i
.index_reg
== 0)
8132 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8133 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8137 if (i
.index_reg
== 0)
8140 if (operand_type_check (i
.types
[op
], disp
) == 0)
8142 /* fake (%bp) into 0(%bp) */
8143 if (i
.disp_encoding
== disp_encoding_16bit
)
8144 i
.types
[op
].bitfield
.disp16
= 1;
8146 i
.types
[op
].bitfield
.disp8
= 1;
8147 fake_zero_displacement
= 1;
8150 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8151 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8153 default: /* (%si) -> 4 or (%di) -> 5 */
8154 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8156 if (!fake_zero_displacement
8160 fake_zero_displacement
= 1;
8161 if (i
.disp_encoding
== disp_encoding_8bit
)
8162 i
.types
[op
].bitfield
.disp8
= 1;
8164 i
.types
[op
].bitfield
.disp16
= 1;
8166 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8168 else /* i.base_reg and 32/64 bit mode */
8170 if (flag_code
== CODE_64BIT
8171 && operand_type_check (i
.types
[op
], disp
))
8173 i
.types
[op
].bitfield
.disp16
= 0;
8174 i
.types
[op
].bitfield
.disp64
= 0;
8175 if (i
.prefix
[ADDR_PREFIX
] == 0)
8177 i
.types
[op
].bitfield
.disp32
= 0;
8178 i
.types
[op
].bitfield
.disp32s
= 1;
8182 i
.types
[op
].bitfield
.disp32
= 1;
8183 i
.types
[op
].bitfield
.disp32s
= 0;
8187 if (!i
.tm
.opcode_modifier
.sib
)
8188 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8189 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8191 i
.sib
.base
= i
.base_reg
->reg_num
;
8192 /* x86-64 ignores REX prefix bit here to avoid decoder
8194 if (!(i
.base_reg
->reg_flags
& RegRex
)
8195 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8196 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8198 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8200 fake_zero_displacement
= 1;
8201 if (i
.disp_encoding
== disp_encoding_32bit
)
8202 i
.types
[op
].bitfield
.disp32
= 1;
8204 i
.types
[op
].bitfield
.disp8
= 1;
8206 i
.sib
.scale
= i
.log2_scale_factor
;
8207 if (i
.index_reg
== 0)
8209 /* Only check for VSIB. */
8210 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8211 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8212 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8214 /* <disp>(%esp) becomes two byte modrm with no index
8215 register. We've already stored the code for esp
8216 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8217 Any base register besides %esp will not use the
8218 extra modrm byte. */
8219 i
.sib
.index
= NO_INDEX_REGISTER
;
8221 else if (!i
.tm
.opcode_modifier
.sib
)
8223 if (i
.index_reg
->reg_num
== RegIZ
)
8224 i
.sib
.index
= NO_INDEX_REGISTER
;
8226 i
.sib
.index
= i
.index_reg
->reg_num
;
8227 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8228 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8233 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8234 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8238 if (!fake_zero_displacement
8242 fake_zero_displacement
= 1;
8243 if (i
.disp_encoding
== disp_encoding_8bit
)
8244 i
.types
[op
].bitfield
.disp8
= 1;
8246 i
.types
[op
].bitfield
.disp32
= 1;
8248 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8252 if (fake_zero_displacement
)
8254 /* Fakes a zero displacement assuming that i.types[op]
8255 holds the correct displacement size. */
8258 gas_assert (i
.op
[op
].disps
== 0);
8259 exp
= &disp_expressions
[i
.disp_operands
++];
8260 i
.op
[op
].disps
= exp
;
8261 exp
->X_op
= O_constant
;
8262 exp
->X_add_number
= 0;
8263 exp
->X_add_symbol
= (symbolS
*) 0;
8264 exp
->X_op_symbol
= (symbolS
*) 0;
8272 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8274 if (operand_type_check (i
.types
[0], imm
))
8275 i
.vex
.register_specifier
= NULL
;
8278 /* VEX.vvvv encodes one of the sources when the first
8279 operand is not an immediate. */
8280 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8281 i
.vex
.register_specifier
= i
.op
[0].regs
;
8283 i
.vex
.register_specifier
= i
.op
[1].regs
;
8286 /* Destination is a XMM register encoded in the ModRM.reg
8288 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8289 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8292 /* ModRM.rm and VEX.B encodes the other source. */
8293 if (!i
.mem_operands
)
8297 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8298 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8300 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8302 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8306 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8308 i
.vex
.register_specifier
= i
.op
[2].regs
;
8309 if (!i
.mem_operands
)
8312 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8313 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8317 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8318 (if any) based on i.tm.extension_opcode. Again, we must be
8319 careful to make sure that segment/control/debug/test/MMX
8320 registers are coded into the i.rm.reg field. */
8321 else if (i
.reg_operands
)
8324 unsigned int vex_reg
= ~0;
8326 for (op
= 0; op
< i
.operands
; op
++)
8327 if (i
.types
[op
].bitfield
.class == Reg
8328 || i
.types
[op
].bitfield
.class == RegBND
8329 || i
.types
[op
].bitfield
.class == RegMask
8330 || i
.types
[op
].bitfield
.class == SReg
8331 || i
.types
[op
].bitfield
.class == RegCR
8332 || i
.types
[op
].bitfield
.class == RegDR
8333 || i
.types
[op
].bitfield
.class == RegTR
8334 || i
.types
[op
].bitfield
.class == RegSIMD
8335 || i
.types
[op
].bitfield
.class == RegMMX
)
8340 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8342 /* For instructions with VexNDS, the register-only
8343 source operand is encoded in VEX prefix. */
8344 gas_assert (mem
!= (unsigned int) ~0);
8349 gas_assert (op
< i
.operands
);
8353 /* Check register-only source operand when two source
8354 operands are swapped. */
8355 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8356 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8360 gas_assert (mem
== (vex_reg
+ 1)
8361 && op
< i
.operands
);
8366 gas_assert (vex_reg
< i
.operands
);
8370 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8372 /* For instructions with VexNDD, the register destination
8373 is encoded in VEX prefix. */
8374 if (i
.mem_operands
== 0)
8376 /* There is no memory operand. */
8377 gas_assert ((op
+ 2) == i
.operands
);
8382 /* There are only 2 non-immediate operands. */
8383 gas_assert (op
< i
.imm_operands
+ 2
8384 && i
.operands
== i
.imm_operands
+ 2);
8385 vex_reg
= i
.imm_operands
+ 1;
8389 gas_assert (op
< i
.operands
);
8391 if (vex_reg
!= (unsigned int) ~0)
8393 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8395 if ((type
->bitfield
.class != Reg
8396 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8397 && type
->bitfield
.class != RegSIMD
8398 && !operand_type_equal (type
, ®mask
))
8401 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8404 /* Don't set OP operand twice. */
8407 /* If there is an extension opcode to put here, the
8408 register number must be put into the regmem field. */
8409 if (i
.tm
.extension_opcode
!= None
)
8411 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8412 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8413 i
.tm
.opcode_modifier
.sse2avx
);
8417 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8418 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8419 i
.tm
.opcode_modifier
.sse2avx
);
8423 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8424 must set it to 3 to indicate this is a register operand
8425 in the regmem field. */
8426 if (!i
.mem_operands
)
8430 /* Fill in i.rm.reg field with extension opcode (if any). */
8431 if (i
.tm
.extension_opcode
!= None
)
8432 i
.rm
.reg
= i
.tm
.extension_opcode
;
8438 frag_opcode_byte (unsigned char byte
)
8440 if (now_seg
!= absolute_section
)
8441 FRAG_APPEND_1_CHAR (byte
);
8443 ++abs_section_offset
;
8447 flip_code16 (unsigned int code16
)
8449 gas_assert (i
.tm
.operands
== 1);
8451 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8452 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8453 || i
.tm
.operand_types
[0].bitfield
.disp32s
8454 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8459 output_branch (void)
8465 relax_substateT subtype
;
8469 if (now_seg
== absolute_section
)
8471 as_bad (_("relaxable branches not supported in absolute section"));
8475 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8476 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8479 if (i
.prefix
[DATA_PREFIX
] != 0)
8483 code16
^= flip_code16(code16
);
8485 /* Pentium4 branch hints. */
8486 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8487 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8492 if (i
.prefix
[REX_PREFIX
] != 0)
8498 /* BND prefixed jump. */
8499 if (i
.prefix
[BND_PREFIX
] != 0)
8505 if (i
.prefixes
!= 0)
8506 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8508 /* It's always a symbol; End frag & setup for relax.
8509 Make sure there is enough room in this frag for the largest
8510 instruction we may generate in md_convert_frag. This is 2
8511 bytes for the opcode and room for the prefix and largest
8513 frag_grow (prefix
+ 2 + 4);
8514 /* Prefix and 1 opcode byte go in fr_fix. */
8515 p
= frag_more (prefix
+ 1);
8516 if (i
.prefix
[DATA_PREFIX
] != 0)
8517 *p
++ = DATA_PREFIX_OPCODE
;
8518 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8519 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8520 *p
++ = i
.prefix
[SEG_PREFIX
];
8521 if (i
.prefix
[BND_PREFIX
] != 0)
8522 *p
++ = BND_PREFIX_OPCODE
;
8523 if (i
.prefix
[REX_PREFIX
] != 0)
8524 *p
++ = i
.prefix
[REX_PREFIX
];
8525 *p
= i
.tm
.base_opcode
;
8527 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8528 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8529 else if (cpu_arch_flags
.bitfield
.cpui386
)
8530 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8532 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8535 sym
= i
.op
[0].disps
->X_add_symbol
;
8536 off
= i
.op
[0].disps
->X_add_number
;
8538 if (i
.op
[0].disps
->X_op
!= O_constant
8539 && i
.op
[0].disps
->X_op
!= O_symbol
)
8541 /* Handle complex expressions. */
8542 sym
= make_expr_symbol (i
.op
[0].disps
);
8546 /* 1 possible extra opcode + 4 byte displacement go in var part.
8547 Pass reloc in fr_var. */
8548 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8551 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8552 /* Return TRUE iff PLT32 relocation should be used for branching to
8556 need_plt32_p (symbolS
*s
)
8558 /* PLT32 relocation is ELF only. */
8563 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8564 krtld support it. */
8568 /* Since there is no need to prepare for PLT branch on x86-64, we
8569 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8570 be used as a marker for 32-bit PC-relative branches. */
8574 /* Weak or undefined symbol need PLT32 relocation. */
8575 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8578 /* Non-global symbol doesn't need PLT32 relocation. */
8579 if (! S_IS_EXTERNAL (s
))
8582 /* Other global symbols need PLT32 relocation. NB: Symbol with
8583 non-default visibilities are treated as normal global symbol
8584 so that PLT32 relocation can be used as a marker for 32-bit
8585 PC-relative branches. It is useful for linker relaxation. */
8596 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8598 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8600 /* This is a loop or jecxz type instruction. */
8602 if (i
.prefix
[ADDR_PREFIX
] != 0)
8604 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8607 /* Pentium4 branch hints. */
8608 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8609 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8611 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8620 if (flag_code
== CODE_16BIT
)
8623 if (i
.prefix
[DATA_PREFIX
] != 0)
8625 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8627 code16
^= flip_code16(code16
);
8635 /* BND prefixed jump. */
8636 if (i
.prefix
[BND_PREFIX
] != 0)
8638 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8642 if (i
.prefix
[REX_PREFIX
] != 0)
8644 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8648 if (i
.prefixes
!= 0)
8649 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8651 if (now_seg
== absolute_section
)
8653 abs_section_offset
+= i
.tm
.opcode_length
+ size
;
8657 p
= frag_more (i
.tm
.opcode_length
+ size
);
8658 switch (i
.tm
.opcode_length
)
8661 *p
++ = i
.tm
.base_opcode
>> 8;
8664 *p
++ = i
.tm
.base_opcode
;
8670 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8672 && jump_reloc
== NO_RELOC
8673 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8674 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8677 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8679 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8680 i
.op
[0].disps
, 1, jump_reloc
);
8682 /* All jumps handled here are signed, but don't use a signed limit
8683 check for 32 and 16 bit jumps as we want to allow wrap around at
8684 4G and 64k respectively. */
8686 fixP
->fx_signed
= 1;
8690 output_interseg_jump (void)
8698 if (flag_code
== CODE_16BIT
)
8702 if (i
.prefix
[DATA_PREFIX
] != 0)
8709 gas_assert (!i
.prefix
[REX_PREFIX
]);
8715 if (i
.prefixes
!= 0)
8716 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8718 if (now_seg
== absolute_section
)
8720 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8724 /* 1 opcode; 2 segment; offset */
8725 p
= frag_more (prefix
+ 1 + 2 + size
);
8727 if (i
.prefix
[DATA_PREFIX
] != 0)
8728 *p
++ = DATA_PREFIX_OPCODE
;
8730 if (i
.prefix
[REX_PREFIX
] != 0)
8731 *p
++ = i
.prefix
[REX_PREFIX
];
8733 *p
++ = i
.tm
.base_opcode
;
8734 if (i
.op
[1].imms
->X_op
== O_constant
)
8736 offsetT n
= i
.op
[1].imms
->X_add_number
;
8739 && !fits_in_unsigned_word (n
)
8740 && !fits_in_signed_word (n
))
8742 as_bad (_("16-bit jump out of range"));
8745 md_number_to_chars (p
, n
, size
);
8748 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8749 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8750 if (i
.op
[0].imms
->X_op
!= O_constant
)
8751 as_bad (_("can't handle non absolute segment in `%s'"),
8753 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8756 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8761 asection
*seg
= now_seg
;
8762 subsegT subseg
= now_subseg
;
8764 unsigned int alignment
, align_size_1
;
8765 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8766 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8767 unsigned int padding
;
8769 if (!IS_ELF
|| !x86_used_note
)
8772 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8774 /* The .note.gnu.property section layout:
8776 Field Length Contents
8779 n_descsz 4 The note descriptor size
8780 n_type 4 NT_GNU_PROPERTY_TYPE_0
8782 n_desc n_descsz The program property array
8786 /* Create the .note.gnu.property section. */
8787 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8788 bfd_set_section_flags (sec
,
8795 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8806 bfd_set_section_alignment (sec
, alignment
);
8807 elf_section_type (sec
) = SHT_NOTE
;
8809 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8811 isa_1_descsz_raw
= 4 + 4 + 4;
8812 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8813 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8815 feature_2_descsz_raw
= isa_1_descsz
;
8816 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8818 feature_2_descsz_raw
+= 4 + 4 + 4;
8819 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8820 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8823 descsz
= feature_2_descsz
;
8824 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8825 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8827 /* Write n_namsz. */
8828 md_number_to_chars (p
, (valueT
) 4, 4);
8830 /* Write n_descsz. */
8831 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8834 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8837 memcpy (p
+ 4 * 3, "GNU", 4);
8839 /* Write 4-byte type. */
8840 md_number_to_chars (p
+ 4 * 4,
8841 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8843 /* Write 4-byte data size. */
8844 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8846 /* Write 4-byte data. */
8847 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8849 /* Zero out paddings. */
8850 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8852 memset (p
+ 4 * 7, 0, padding
);
8854 /* Write 4-byte type. */
8855 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8856 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8858 /* Write 4-byte data size. */
8859 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8861 /* Write 4-byte data. */
8862 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8863 (valueT
) x86_feature_2_used
, 4);
8865 /* Zero out paddings. */
8866 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8868 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8870 /* We probably can't restore the current segment, for there likely
8873 subseg_set (seg
, subseg
);
8878 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8879 const char *frag_now_ptr
)
8881 unsigned int len
= 0;
8883 if (start_frag
!= frag_now
)
8885 const fragS
*fr
= start_frag
;
8890 } while (fr
&& fr
!= frag_now
);
8893 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8896 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8897 be macro-fused with conditional jumps.
8898 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8899 or is one of the following format:
8912 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8914 /* No RIP address. */
8915 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8918 /* No VEX/EVEX encoding. */
8919 if (is_any_vex_encoding (&i
.tm
))
8922 /* add, sub without add/sub m, imm. */
8923 if (i
.tm
.base_opcode
<= 5
8924 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8925 || ((i
.tm
.base_opcode
| 3) == 0x83
8926 && (i
.tm
.extension_opcode
== 0x5
8927 || i
.tm
.extension_opcode
== 0x0)))
8929 *mf_cmp_p
= mf_cmp_alu_cmp
;
8930 return !(i
.mem_operands
&& i
.imm_operands
);
8933 /* and without and m, imm. */
8934 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8935 || ((i
.tm
.base_opcode
| 3) == 0x83
8936 && i
.tm
.extension_opcode
== 0x4))
8938 *mf_cmp_p
= mf_cmp_test_and
;
8939 return !(i
.mem_operands
&& i
.imm_operands
);
8942 /* test without test m imm. */
8943 if ((i
.tm
.base_opcode
| 1) == 0x85
8944 || (i
.tm
.base_opcode
| 1) == 0xa9
8945 || ((i
.tm
.base_opcode
| 1) == 0xf7
8946 && i
.tm
.extension_opcode
== 0))
8948 *mf_cmp_p
= mf_cmp_test_and
;
8949 return !(i
.mem_operands
&& i
.imm_operands
);
8952 /* cmp without cmp m, imm. */
8953 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8954 || ((i
.tm
.base_opcode
| 3) == 0x83
8955 && (i
.tm
.extension_opcode
== 0x7)))
8957 *mf_cmp_p
= mf_cmp_alu_cmp
;
8958 return !(i
.mem_operands
&& i
.imm_operands
);
8961 /* inc, dec without inc/dec m. */
8962 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8963 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8964 || ((i
.tm
.base_opcode
| 1) == 0xff
8965 && i
.tm
.extension_opcode
<= 0x1))
8967 *mf_cmp_p
= mf_cmp_incdec
;
8968 return !i
.mem_operands
;
8974 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8977 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8979 /* NB: Don't work with COND_JUMP86 without i386. */
8980 if (!align_branch_power
8981 || now_seg
== absolute_section
8982 || !cpu_arch_flags
.bitfield
.cpui386
8983 || !(align_branch
& align_branch_fused_bit
))
8986 if (maybe_fused_with_jcc_p (mf_cmp_p
))
8988 if (last_insn
.kind
== last_insn_other
8989 || last_insn
.seg
!= now_seg
)
8992 as_warn_where (last_insn
.file
, last_insn
.line
,
8993 _("`%s` skips -malign-branch-boundary on `%s`"),
8994 last_insn
.name
, i
.tm
.name
);
9000 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9003 add_branch_prefix_frag_p (void)
9005 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9006 to PadLock instructions since they include prefixes in opcode. */
9007 if (!align_branch_power
9008 || !align_branch_prefix_size
9009 || now_seg
== absolute_section
9010 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9011 || !cpu_arch_flags
.bitfield
.cpui386
)
9014 /* Don't add prefix if it is a prefix or there is no operand in case
9015 that segment prefix is special. */
9016 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9019 if (last_insn
.kind
== last_insn_other
9020 || last_insn
.seg
!= now_seg
)
9024 as_warn_where (last_insn
.file
, last_insn
.line
,
9025 _("`%s` skips -malign-branch-boundary on `%s`"),
9026 last_insn
.name
, i
.tm
.name
);
9031 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9034 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9035 enum mf_jcc_kind
*mf_jcc_p
)
9039 /* NB: Don't work with COND_JUMP86 without i386. */
9040 if (!align_branch_power
9041 || now_seg
== absolute_section
9042 || !cpu_arch_flags
.bitfield
.cpui386
)
9047 /* Check for jcc and direct jmp. */
9048 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9050 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9052 *branch_p
= align_branch_jmp
;
9053 add_padding
= align_branch
& align_branch_jmp_bit
;
9057 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9058 igore the lowest bit. */
9059 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9060 *branch_p
= align_branch_jcc
;
9061 if ((align_branch
& align_branch_jcc_bit
))
9065 else if (is_any_vex_encoding (&i
.tm
))
9067 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9070 *branch_p
= align_branch_ret
;
9071 if ((align_branch
& align_branch_ret_bit
))
9076 /* Check for indirect jmp, direct and indirect calls. */
9077 if (i
.tm
.base_opcode
== 0xe8)
9080 *branch_p
= align_branch_call
;
9081 if ((align_branch
& align_branch_call_bit
))
9084 else if (i
.tm
.base_opcode
== 0xff
9085 && (i
.tm
.extension_opcode
== 2
9086 || i
.tm
.extension_opcode
== 4))
9088 /* Indirect call and jmp. */
9089 *branch_p
= align_branch_indirect
;
9090 if ((align_branch
& align_branch_indirect_bit
))
9097 && (i
.op
[0].disps
->X_op
== O_symbol
9098 || (i
.op
[0].disps
->X_op
== O_subtract
9099 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9101 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9102 /* No padding to call to global or undefined tls_get_addr. */
9103 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9104 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9110 && last_insn
.kind
!= last_insn_other
9111 && last_insn
.seg
== now_seg
)
9114 as_warn_where (last_insn
.file
, last_insn
.line
,
9115 _("`%s` skips -malign-branch-boundary on `%s`"),
9116 last_insn
.name
, i
.tm
.name
);
9126 fragS
*insn_start_frag
;
9127 offsetT insn_start_off
;
9128 fragS
*fragP
= NULL
;
9129 enum align_branch_kind branch
= align_branch_none
;
9130 /* The initializer is arbitrary just to avoid uninitialized error.
9131 it's actually either assigned in add_branch_padding_frag_p
9132 or never be used. */
9133 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9135 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9136 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9138 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
9139 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
9140 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
9141 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
9142 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
9143 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
9144 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
9145 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
9146 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
9147 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
9148 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
9149 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
9150 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
9151 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
9152 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9153 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
9154 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
9155 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
9156 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
9157 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
9158 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
9159 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
9160 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
9161 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
9162 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
9163 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
9164 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
9165 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
9166 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
9167 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
9168 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
9169 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
9170 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
9171 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
9172 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
9173 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
9174 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
9175 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
9176 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
9177 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
9178 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
9179 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
9180 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
9181 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
9182 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
9183 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
9184 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
9185 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
9186 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
9187 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
9189 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9190 || i
.tm
.cpu_flags
.bitfield
.cpu287
9191 || i
.tm
.cpu_flags
.bitfield
.cpu387
9192 || i
.tm
.cpu_flags
.bitfield
.cpu687
9193 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9194 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9195 if ((i
.xstate
& xstate_mmx
)
9196 || i
.tm
.base_opcode
== 0xf77 /* emms */
9197 || i
.tm
.base_opcode
== 0xf0e /* femms */)
9198 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9199 if ((i
.xstate
& xstate_xmm
))
9200 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9201 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9202 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9203 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9204 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9205 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9206 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9207 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9208 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9209 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9210 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9211 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9212 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9214 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9215 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9216 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9220 /* Tie dwarf2 debug info to the address at the start of the insn.
9221 We can't do this after the insn has been output as the current
9222 frag may have been closed off. eg. by frag_var. */
9223 dwarf2_emit_insn (0);
9225 insn_start_frag
= frag_now
;
9226 insn_start_off
= frag_now_fix ();
9228 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9231 /* Branch can be 8 bytes. Leave some room for prefixes. */
9232 unsigned int max_branch_padding_size
= 14;
9234 /* Align section to boundary. */
9235 record_alignment (now_seg
, align_branch_power
);
9237 /* Make room for padding. */
9238 frag_grow (max_branch_padding_size
);
9240 /* Start of the padding. */
9245 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9246 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9249 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9250 fragP
->tc_frag_data
.branch_type
= branch
;
9251 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9255 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9257 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9258 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9260 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9261 output_interseg_jump ();
9264 /* Output normal instructions here. */
9268 unsigned int prefix
;
9269 enum mf_cmp_kind mf_cmp
;
9272 && (i
.tm
.base_opcode
== 0xfaee8
9273 || i
.tm
.base_opcode
== 0xfaef0
9274 || i
.tm
.base_opcode
== 0xfaef8))
9276 /* Encode lfence, mfence, and sfence as
9277 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9278 if (now_seg
!= absolute_section
)
9280 offsetT val
= 0x240483f0ULL
;
9283 md_number_to_chars (p
, val
, 5);
9286 abs_section_offset
+= 5;
9290 /* Some processors fail on LOCK prefix. This options makes
9291 assembler ignore LOCK prefix and serves as a workaround. */
9292 if (omit_lock_prefix
)
9294 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9296 i
.prefix
[LOCK_PREFIX
] = 0;
9300 /* Skip if this is a branch. */
9302 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9304 /* Make room for padding. */
9305 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9310 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9311 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9314 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9315 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9316 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9318 else if (add_branch_prefix_frag_p ())
9320 unsigned int max_prefix_size
= align_branch_prefix_size
;
9322 /* Make room for padding. */
9323 frag_grow (max_prefix_size
);
9328 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9329 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9332 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9335 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9336 don't need the explicit prefix. */
9337 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9339 switch (i
.tm
.opcode_length
)
9342 if (i
.tm
.base_opcode
& 0xff000000)
9344 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
9345 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9346 || prefix
!= REPE_PREFIX_OPCODE
9347 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
9348 add_prefix (prefix
);
9352 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
9354 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
9355 add_prefix (prefix
);
9361 /* Check for pseudo prefixes. */
9362 as_bad_where (insn_start_frag
->fr_file
,
9363 insn_start_frag
->fr_line
,
9364 _("pseudo prefix without instruction"));
9370 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9371 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9372 R_X86_64_GOTTPOFF relocation so that linker can safely
9373 perform IE->LE optimization. A dummy REX_OPCODE prefix
9374 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9375 relocation for GDesc -> IE/LE optimization. */
9376 if (x86_elf_abi
== X86_64_X32_ABI
9378 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9379 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9380 && i
.prefix
[REX_PREFIX
] == 0)
9381 add_prefix (REX_OPCODE
);
9384 /* The prefix bytes. */
9385 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9387 frag_opcode_byte (*q
);
9391 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9397 frag_opcode_byte (*q
);
9400 /* There should be no other prefixes for instructions
9405 /* For EVEX instructions i.vrex should become 0 after
9406 build_evex_prefix. For VEX instructions upper 16 registers
9407 aren't available, so VREX should be 0. */
9410 /* Now the VEX prefix. */
9411 if (now_seg
!= absolute_section
)
9413 p
= frag_more (i
.vex
.length
);
9414 for (j
= 0; j
< i
.vex
.length
; j
++)
9415 p
[j
] = i
.vex
.bytes
[j
];
9418 abs_section_offset
+= i
.vex
.length
;
9421 /* Now the opcode; be careful about word order here! */
9422 if (now_seg
== absolute_section
)
9423 abs_section_offset
+= i
.tm
.opcode_length
;
9424 else if (i
.tm
.opcode_length
== 1)
9426 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9430 switch (i
.tm
.opcode_length
)
9434 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9435 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9439 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9449 /* Put out high byte first: can't use md_number_to_chars! */
9450 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9451 *p
= i
.tm
.base_opcode
& 0xff;
9454 /* Now the modrm byte and sib byte (if present). */
9455 if (i
.tm
.opcode_modifier
.modrm
)
9457 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9459 | (i
.rm
.mode
<< 6));
9460 /* If i.rm.regmem == ESP (4)
9461 && i.rm.mode != (Register mode)
9463 ==> need second modrm byte. */
9464 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9466 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9467 frag_opcode_byte ((i
.sib
.base
<< 0)
9468 | (i
.sib
.index
<< 3)
9469 | (i
.sib
.scale
<< 6));
9472 if (i
.disp_operands
)
9473 output_disp (insn_start_frag
, insn_start_off
);
9476 output_imm (insn_start_frag
, insn_start_off
);
9479 * frag_now_fix () returning plain abs_section_offset when we're in the
9480 * absolute section, and abs_section_offset not getting updated as data
9481 * gets added to the frag breaks the logic below.
9483 if (now_seg
!= absolute_section
)
9485 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9487 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9491 /* NB: Don't add prefix with GOTPC relocation since
9492 output_disp() above depends on the fixed encoding
9493 length. Can't add prefix with TLS relocation since
9494 it breaks TLS linker optimization. */
9495 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9496 /* Prefix count on the current instruction. */
9497 unsigned int count
= i
.vex
.length
;
9499 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9500 /* REX byte is encoded in VEX/EVEX prefix. */
9501 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9504 /* Count prefixes for extended opcode maps. */
9506 switch (i
.tm
.opcode_length
)
9509 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9512 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9524 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9533 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9536 /* Set the maximum prefix size in BRANCH_PREFIX
9538 if (fragP
->tc_frag_data
.max_bytes
> max
)
9539 fragP
->tc_frag_data
.max_bytes
= max
;
9540 if (fragP
->tc_frag_data
.max_bytes
> count
)
9541 fragP
->tc_frag_data
.max_bytes
-= count
;
9543 fragP
->tc_frag_data
.max_bytes
= 0;
9547 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9549 unsigned int max_prefix_size
;
9550 if (align_branch_prefix_size
> max
)
9551 max_prefix_size
= max
;
9553 max_prefix_size
= align_branch_prefix_size
;
9554 if (max_prefix_size
> count
)
9555 fragP
->tc_frag_data
.max_prefix_length
9556 = max_prefix_size
- count
;
9559 /* Use existing segment prefix if possible. Use CS
9560 segment prefix in 64-bit mode. In 32-bit mode, use SS
9561 segment prefix with ESP/EBP base register and use DS
9562 segment prefix without ESP/EBP base register. */
9563 if (i
.prefix
[SEG_PREFIX
])
9564 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9565 else if (flag_code
== CODE_64BIT
)
9566 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9568 && (i
.base_reg
->reg_num
== 4
9569 || i
.base_reg
->reg_num
== 5))
9570 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9572 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9577 /* NB: Don't work with COND_JUMP86 without i386. */
9578 if (align_branch_power
9579 && now_seg
!= absolute_section
9580 && cpu_arch_flags
.bitfield
.cpui386
)
9582 /* Terminate each frag so that we can add prefix and check for
9584 frag_wane (frag_now
);
9591 pi ("" /*line*/, &i
);
9593 #endif /* DEBUG386 */
9596 /* Return the size of the displacement operand N. */
9599 disp_size (unsigned int n
)
9603 if (i
.types
[n
].bitfield
.disp64
)
9605 else if (i
.types
[n
].bitfield
.disp8
)
9607 else if (i
.types
[n
].bitfield
.disp16
)
9612 /* Return the size of the immediate operand N. */
9615 imm_size (unsigned int n
)
9618 if (i
.types
[n
].bitfield
.imm64
)
9620 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9622 else if (i
.types
[n
].bitfield
.imm16
)
9628 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9633 for (n
= 0; n
< i
.operands
; n
++)
9635 if (operand_type_check (i
.types
[n
], disp
))
9637 int size
= disp_size (n
);
9639 if (now_seg
== absolute_section
)
9640 abs_section_offset
+= size
;
9641 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9643 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9645 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9647 p
= frag_more (size
);
9648 md_number_to_chars (p
, val
, size
);
9652 enum bfd_reloc_code_real reloc_type
;
9653 int sign
= i
.types
[n
].bitfield
.disp32s
;
9654 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9657 /* We can't have 8 bit displacement here. */
9658 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9660 /* The PC relative address is computed relative
9661 to the instruction boundary, so in case immediate
9662 fields follows, we need to adjust the value. */
9663 if (pcrel
&& i
.imm_operands
)
9668 for (n1
= 0; n1
< i
.operands
; n1
++)
9669 if (operand_type_check (i
.types
[n1
], imm
))
9671 /* Only one immediate is allowed for PC
9672 relative address. */
9673 gas_assert (sz
== 0);
9675 i
.op
[n
].disps
->X_add_number
-= sz
;
9677 /* We should find the immediate. */
9678 gas_assert (sz
!= 0);
9681 p
= frag_more (size
);
9682 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9684 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9685 && (((reloc_type
== BFD_RELOC_32
9686 || reloc_type
== BFD_RELOC_X86_64_32S
9687 || (reloc_type
== BFD_RELOC_64
9689 && (i
.op
[n
].disps
->X_op
== O_symbol
9690 || (i
.op
[n
].disps
->X_op
== O_add
9691 && ((symbol_get_value_expression
9692 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9694 || reloc_type
== BFD_RELOC_32_PCREL
))
9698 reloc_type
= BFD_RELOC_386_GOTPC
;
9699 i
.has_gotpc_tls_reloc
= TRUE
;
9700 i
.op
[n
].imms
->X_add_number
+=
9701 encoding_length (insn_start_frag
, insn_start_off
, p
);
9703 else if (reloc_type
== BFD_RELOC_64
)
9704 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9706 /* Don't do the adjustment for x86-64, as there
9707 the pcrel addressing is relative to the _next_
9708 insn, and that is taken care of in other code. */
9709 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9711 else if (align_branch_power
)
9715 case BFD_RELOC_386_TLS_GD
:
9716 case BFD_RELOC_386_TLS_LDM
:
9717 case BFD_RELOC_386_TLS_IE
:
9718 case BFD_RELOC_386_TLS_IE_32
:
9719 case BFD_RELOC_386_TLS_GOTIE
:
9720 case BFD_RELOC_386_TLS_GOTDESC
:
9721 case BFD_RELOC_386_TLS_DESC_CALL
:
9722 case BFD_RELOC_X86_64_TLSGD
:
9723 case BFD_RELOC_X86_64_TLSLD
:
9724 case BFD_RELOC_X86_64_GOTTPOFF
:
9725 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9726 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9727 i
.has_gotpc_tls_reloc
= TRUE
;
9732 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9733 size
, i
.op
[n
].disps
, pcrel
,
9735 /* Check for "call/jmp *mem", "mov mem, %reg",
9736 "test %reg, mem" and "binop mem, %reg" where binop
9737 is one of adc, add, and, cmp, or, sbb, sub, xor
9738 instructions without data prefix. Always generate
9739 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9740 if (i
.prefix
[DATA_PREFIX
] == 0
9741 && (generate_relax_relocations
9744 && i
.rm
.regmem
== 5))
9746 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9747 && !is_any_vex_encoding(&i
.tm
)
9748 && ((i
.operands
== 1
9749 && i
.tm
.base_opcode
== 0xff
9750 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9752 && (i
.tm
.base_opcode
== 0x8b
9753 || i
.tm
.base_opcode
== 0x85
9754 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9758 fixP
->fx_tcbit
= i
.rex
!= 0;
9760 && (i
.base_reg
->reg_num
== RegIP
))
9761 fixP
->fx_tcbit2
= 1;
9764 fixP
->fx_tcbit2
= 1;
9772 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9777 for (n
= 0; n
< i
.operands
; n
++)
9779 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9780 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9783 if (operand_type_check (i
.types
[n
], imm
))
9785 int size
= imm_size (n
);
9787 if (now_seg
== absolute_section
)
9788 abs_section_offset
+= size
;
9789 else if (i
.op
[n
].imms
->X_op
== O_constant
)
9793 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9795 p
= frag_more (size
);
9796 md_number_to_chars (p
, val
, size
);
9800 /* Not absolute_section.
9801 Need a 32-bit fixup (don't support 8bit
9802 non-absolute imms). Try to support other
9804 enum bfd_reloc_code_real reloc_type
;
9807 if (i
.types
[n
].bitfield
.imm32s
9808 && (i
.suffix
== QWORD_MNEM_SUFFIX
9809 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9814 p
= frag_more (size
);
9815 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9817 /* This is tough to explain. We end up with this one if we
9818 * have operands that look like
9819 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9820 * obtain the absolute address of the GOT, and it is strongly
9821 * preferable from a performance point of view to avoid using
9822 * a runtime relocation for this. The actual sequence of
9823 * instructions often look something like:
9828 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9830 * The call and pop essentially return the absolute address
9831 * of the label .L66 and store it in %ebx. The linker itself
9832 * will ultimately change the first operand of the addl so
9833 * that %ebx points to the GOT, but to keep things simple, the
9834 * .o file must have this operand set so that it generates not
9835 * the absolute address of .L66, but the absolute address of
9836 * itself. This allows the linker itself simply treat a GOTPC
9837 * relocation as asking for a pcrel offset to the GOT to be
9838 * added in, and the addend of the relocation is stored in the
9839 * operand field for the instruction itself.
9841 * Our job here is to fix the operand so that it would add
9842 * the correct offset so that %ebx would point to itself. The
9843 * thing that is tricky is that .-.L66 will point to the
9844 * beginning of the instruction, so we need to further modify
9845 * the operand so that it will point to itself. There are
9846 * other cases where you have something like:
9848 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9850 * and here no correction would be required. Internally in
9851 * the assembler we treat operands of this form as not being
9852 * pcrel since the '.' is explicitly mentioned, and I wonder
9853 * whether it would simplify matters to do it this way. Who
9854 * knows. In earlier versions of the PIC patches, the
9855 * pcrel_adjust field was used to store the correction, but
9856 * since the expression is not pcrel, I felt it would be
9857 * confusing to do it this way. */
9859 if ((reloc_type
== BFD_RELOC_32
9860 || reloc_type
== BFD_RELOC_X86_64_32S
9861 || reloc_type
== BFD_RELOC_64
)
9863 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9864 && (i
.op
[n
].imms
->X_op
== O_symbol
9865 || (i
.op
[n
].imms
->X_op
== O_add
9866 && ((symbol_get_value_expression
9867 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9871 reloc_type
= BFD_RELOC_386_GOTPC
;
9873 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9875 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9876 i
.has_gotpc_tls_reloc
= TRUE
;
9877 i
.op
[n
].imms
->X_add_number
+=
9878 encoding_length (insn_start_frag
, insn_start_off
, p
);
9880 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9881 i
.op
[n
].imms
, 0, reloc_type
);
9887 /* x86_cons_fix_new is called via the expression parsing code when a
9888 reloc is needed. We use this hook to get the correct .got reloc. */
9889 static int cons_sign
= -1;
9892 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9893 expressionS
*exp
, bfd_reloc_code_real_type r
)
9895 r
= reloc (len
, 0, cons_sign
, r
);
9898 if (exp
->X_op
== O_secrel
)
9900 exp
->X_op
= O_symbol
;
9901 r
= BFD_RELOC_32_SECREL
;
9905 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9908 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9909 purpose of the `.dc.a' internal pseudo-op. */
9912 x86_address_bytes (void)
9914 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9916 return stdoutput
->arch_info
->bits_per_address
/ 8;
9919 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9921 # define lex_got(reloc, adjust, types) NULL
9923 /* Parse operands of the form
9924 <symbol>@GOTOFF+<nnn>
9925 and similar .plt or .got references.
9927 If we find one, set up the correct relocation in RELOC and copy the
9928 input string, minus the `@GOTOFF' into a malloc'd buffer for
9929 parsing by the calling routine. Return this buffer, and if ADJUST
9930 is non-null set it to the length of the string we removed from the
9931 input line. Otherwise return NULL. */
9933 lex_got (enum bfd_reloc_code_real
*rel
,
9935 i386_operand_type
*types
)
9937 /* Some of the relocations depend on the size of what field is to
9938 be relocated. But in our callers i386_immediate and i386_displacement
9939 we don't yet know the operand size (this will be set by insn
9940 matching). Hence we record the word32 relocation here,
9941 and adjust the reloc according to the real size in reloc(). */
9942 static const struct {
9945 const enum bfd_reloc_code_real rel
[2];
9946 const i386_operand_type types64
;
9948 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9949 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9951 OPERAND_TYPE_IMM32_64
},
9953 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9954 BFD_RELOC_X86_64_PLTOFF64
},
9955 OPERAND_TYPE_IMM64
},
9956 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9957 BFD_RELOC_X86_64_PLT32
},
9958 OPERAND_TYPE_IMM32_32S_DISP32
},
9959 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9960 BFD_RELOC_X86_64_GOTPLT64
},
9961 OPERAND_TYPE_IMM64_DISP64
},
9962 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9963 BFD_RELOC_X86_64_GOTOFF64
},
9964 OPERAND_TYPE_IMM64_DISP64
},
9965 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9966 BFD_RELOC_X86_64_GOTPCREL
},
9967 OPERAND_TYPE_IMM32_32S_DISP32
},
9968 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9969 BFD_RELOC_X86_64_TLSGD
},
9970 OPERAND_TYPE_IMM32_32S_DISP32
},
9971 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9972 _dummy_first_bfd_reloc_code_real
},
9973 OPERAND_TYPE_NONE
},
9974 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9975 BFD_RELOC_X86_64_TLSLD
},
9976 OPERAND_TYPE_IMM32_32S_DISP32
},
9977 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9978 BFD_RELOC_X86_64_GOTTPOFF
},
9979 OPERAND_TYPE_IMM32_32S_DISP32
},
9980 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9981 BFD_RELOC_X86_64_TPOFF32
},
9982 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9983 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9984 _dummy_first_bfd_reloc_code_real
},
9985 OPERAND_TYPE_NONE
},
9986 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9987 BFD_RELOC_X86_64_DTPOFF32
},
9988 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9989 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9990 _dummy_first_bfd_reloc_code_real
},
9991 OPERAND_TYPE_NONE
},
9992 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9993 _dummy_first_bfd_reloc_code_real
},
9994 OPERAND_TYPE_NONE
},
9995 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9996 BFD_RELOC_X86_64_GOT32
},
9997 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9998 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9999 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10000 OPERAND_TYPE_IMM32_32S_DISP32
},
10001 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10002 BFD_RELOC_X86_64_TLSDESC_CALL
},
10003 OPERAND_TYPE_IMM32_32S_DISP32
},
10008 #if defined (OBJ_MAYBE_ELF)
10013 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10014 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10017 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10019 int len
= gotrel
[j
].len
;
10020 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10022 if (gotrel
[j
].rel
[object_64bit
] != 0)
10025 char *tmpbuf
, *past_reloc
;
10027 *rel
= gotrel
[j
].rel
[object_64bit
];
10031 if (flag_code
!= CODE_64BIT
)
10033 types
->bitfield
.imm32
= 1;
10034 types
->bitfield
.disp32
= 1;
10037 *types
= gotrel
[j
].types64
;
10040 if (j
!= 0 && GOT_symbol
== NULL
)
10041 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10043 /* The length of the first part of our input line. */
10044 first
= cp
- input_line_pointer
;
10046 /* The second part goes from after the reloc token until
10047 (and including) an end_of_line char or comma. */
10048 past_reloc
= cp
+ 1 + len
;
10050 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10052 second
= cp
+ 1 - past_reloc
;
10054 /* Allocate and copy string. The trailing NUL shouldn't
10055 be necessary, but be safe. */
10056 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10057 memcpy (tmpbuf
, input_line_pointer
, first
);
10058 if (second
!= 0 && *past_reloc
!= ' ')
10059 /* Replace the relocation token with ' ', so that
10060 errors like foo@GOTOFF1 will be detected. */
10061 tmpbuf
[first
++] = ' ';
10063 /* Increment length by 1 if the relocation token is
10068 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10069 tmpbuf
[first
+ second
] = '\0';
10073 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10074 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10079 /* Might be a symbol version string. Don't as_bad here. */
10088 /* Parse operands of the form
10089 <symbol>@SECREL32+<nnn>
10091 If we find one, set up the correct relocation in RELOC and copy the
10092 input string, minus the `@SECREL32' into a malloc'd buffer for
10093 parsing by the calling routine. Return this buffer, and if ADJUST
10094 is non-null set it to the length of the string we removed from the
10095 input line. Otherwise return NULL.
10097 This function is copied from the ELF version above adjusted for PE targets. */
10100 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
10101 int *adjust ATTRIBUTE_UNUSED
,
10102 i386_operand_type
*types
)
10104 static const struct
10108 const enum bfd_reloc_code_real rel
[2];
10109 const i386_operand_type types64
;
10113 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10114 BFD_RELOC_32_SECREL
},
10115 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10121 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10122 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10125 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10127 int len
= gotrel
[j
].len
;
10129 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10131 if (gotrel
[j
].rel
[object_64bit
] != 0)
10134 char *tmpbuf
, *past_reloc
;
10136 *rel
= gotrel
[j
].rel
[object_64bit
];
10142 if (flag_code
!= CODE_64BIT
)
10144 types
->bitfield
.imm32
= 1;
10145 types
->bitfield
.disp32
= 1;
10148 *types
= gotrel
[j
].types64
;
10151 /* The length of the first part of our input line. */
10152 first
= cp
- input_line_pointer
;
10154 /* The second part goes from after the reloc token until
10155 (and including) an end_of_line char or comma. */
10156 past_reloc
= cp
+ 1 + len
;
10158 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10160 second
= cp
+ 1 - past_reloc
;
10162 /* Allocate and copy string. The trailing NUL shouldn't
10163 be necessary, but be safe. */
10164 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10165 memcpy (tmpbuf
, input_line_pointer
, first
);
10166 if (second
!= 0 && *past_reloc
!= ' ')
10167 /* Replace the relocation token with ' ', so that
10168 errors like foo@SECLREL321 will be detected. */
10169 tmpbuf
[first
++] = ' ';
10170 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10171 tmpbuf
[first
+ second
] = '\0';
10175 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10176 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10181 /* Might be a symbol version string. Don't as_bad here. */
10187 bfd_reloc_code_real_type
10188 x86_cons (expressionS
*exp
, int size
)
10190 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10192 intel_syntax
= -intel_syntax
;
10195 if (size
== 4 || (object_64bit
&& size
== 8))
10197 /* Handle @GOTOFF and the like in an expression. */
10199 char *gotfree_input_line
;
10202 save
= input_line_pointer
;
10203 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10204 if (gotfree_input_line
)
10205 input_line_pointer
= gotfree_input_line
;
10209 if (gotfree_input_line
)
10211 /* expression () has merrily parsed up to the end of line,
10212 or a comma - in the wrong buffer. Transfer how far
10213 input_line_pointer has moved to the right buffer. */
10214 input_line_pointer
= (save
10215 + (input_line_pointer
- gotfree_input_line
)
10217 free (gotfree_input_line
);
10218 if (exp
->X_op
== O_constant
10219 || exp
->X_op
== O_absent
10220 || exp
->X_op
== O_illegal
10221 || exp
->X_op
== O_register
10222 || exp
->X_op
== O_big
)
10224 char c
= *input_line_pointer
;
10225 *input_line_pointer
= 0;
10226 as_bad (_("missing or invalid expression `%s'"), save
);
10227 *input_line_pointer
= c
;
10229 else if ((got_reloc
== BFD_RELOC_386_PLT32
10230 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10231 && exp
->X_op
!= O_symbol
)
10233 char c
= *input_line_pointer
;
10234 *input_line_pointer
= 0;
10235 as_bad (_("invalid PLT expression `%s'"), save
);
10236 *input_line_pointer
= c
;
10243 intel_syntax
= -intel_syntax
;
10246 i386_intel_simplify (exp
);
10252 signed_cons (int size
)
10254 if (flag_code
== CODE_64BIT
)
10262 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10269 if (exp
.X_op
== O_symbol
)
10270 exp
.X_op
= O_secrel
;
10272 emit_expr (&exp
, 4);
10274 while (*input_line_pointer
++ == ',');
10276 input_line_pointer
--;
10277 demand_empty_rest_of_line ();
10281 /* Handle Vector operations. */
10284 check_VecOperations (char *op_string
, char *op_end
)
10286 const reg_entry
*mask
;
10291 && (op_end
== NULL
|| op_string
< op_end
))
10294 if (*op_string
== '{')
10298 /* Check broadcasts. */
10299 if (strncmp (op_string
, "1to", 3) == 0)
10304 goto duplicated_vec_op
;
10307 if (*op_string
== '8')
10309 else if (*op_string
== '4')
10311 else if (*op_string
== '2')
10313 else if (*op_string
== '1'
10314 && *(op_string
+1) == '6')
10321 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10326 broadcast_op
.type
= bcst_type
;
10327 broadcast_op
.operand
= this_operand
;
10328 broadcast_op
.bytes
= 0;
10329 i
.broadcast
= &broadcast_op
;
10331 /* Check masking operation. */
10332 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10334 if (mask
== &bad_reg
)
10337 /* k0 can't be used for write mask. */
10338 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10340 as_bad (_("`%s%s' can't be used for write mask"),
10341 register_prefix
, mask
->reg_name
);
10347 mask_op
.mask
= mask
;
10348 mask_op
.zeroing
= 0;
10349 mask_op
.operand
= this_operand
;
10355 goto duplicated_vec_op
;
10357 i
.mask
->mask
= mask
;
10359 /* Only "{z}" is allowed here. No need to check
10360 zeroing mask explicitly. */
10361 if (i
.mask
->operand
!= this_operand
)
10363 as_bad (_("invalid write mask `%s'"), saved
);
10368 op_string
= end_op
;
10370 /* Check zeroing-flag for masking operation. */
10371 else if (*op_string
== 'z')
10375 mask_op
.mask
= NULL
;
10376 mask_op
.zeroing
= 1;
10377 mask_op
.operand
= this_operand
;
10382 if (i
.mask
->zeroing
)
10385 as_bad (_("duplicated `%s'"), saved
);
10389 i
.mask
->zeroing
= 1;
10391 /* Only "{%k}" is allowed here. No need to check mask
10392 register explicitly. */
10393 if (i
.mask
->operand
!= this_operand
)
10395 as_bad (_("invalid zeroing-masking `%s'"),
10404 goto unknown_vec_op
;
10406 if (*op_string
!= '}')
10408 as_bad (_("missing `}' in `%s'"), saved
);
10413 /* Strip whitespace since the addition of pseudo prefixes
10414 changed how the scrubber treats '{'. */
10415 if (is_space_char (*op_string
))
10421 /* We don't know this one. */
10422 as_bad (_("unknown vector operation: `%s'"), saved
);
10426 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10428 as_bad (_("zeroing-masking only allowed with write mask"));
10436 i386_immediate (char *imm_start
)
10438 char *save_input_line_pointer
;
10439 char *gotfree_input_line
;
10442 i386_operand_type types
;
10444 operand_type_set (&types
, ~0);
10446 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10448 as_bad (_("at most %d immediate operands are allowed"),
10449 MAX_IMMEDIATE_OPERANDS
);
10453 exp
= &im_expressions
[i
.imm_operands
++];
10454 i
.op
[this_operand
].imms
= exp
;
10456 if (is_space_char (*imm_start
))
10459 save_input_line_pointer
= input_line_pointer
;
10460 input_line_pointer
= imm_start
;
10462 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10463 if (gotfree_input_line
)
10464 input_line_pointer
= gotfree_input_line
;
10466 exp_seg
= expression (exp
);
10468 SKIP_WHITESPACE ();
10470 /* Handle vector operations. */
10471 if (*input_line_pointer
== '{')
10473 input_line_pointer
= check_VecOperations (input_line_pointer
,
10475 if (input_line_pointer
== NULL
)
10479 if (*input_line_pointer
)
10480 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10482 input_line_pointer
= save_input_line_pointer
;
10483 if (gotfree_input_line
)
10485 free (gotfree_input_line
);
10487 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10488 exp
->X_op
= O_illegal
;
10491 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10495 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10496 i386_operand_type types
, const char *imm_start
)
10498 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10501 as_bad (_("missing or invalid immediate expression `%s'"),
10505 else if (exp
->X_op
== O_constant
)
10507 /* Size it properly later. */
10508 i
.types
[this_operand
].bitfield
.imm64
= 1;
10509 /* If not 64bit, sign extend val. */
10510 if (flag_code
!= CODE_64BIT
10511 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10513 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10515 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10516 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10517 && exp_seg
!= absolute_section
10518 && exp_seg
!= text_section
10519 && exp_seg
!= data_section
10520 && exp_seg
!= bss_section
10521 && exp_seg
!= undefined_section
10522 && !bfd_is_com_section (exp_seg
))
10524 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10528 else if (!intel_syntax
&& exp_seg
== reg_section
)
10531 as_bad (_("illegal immediate register operand %s"), imm_start
);
10536 /* This is an address. The size of the address will be
10537 determined later, depending on destination register,
10538 suffix, or the default for the section. */
10539 i
.types
[this_operand
].bitfield
.imm8
= 1;
10540 i
.types
[this_operand
].bitfield
.imm16
= 1;
10541 i
.types
[this_operand
].bitfield
.imm32
= 1;
10542 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10543 i
.types
[this_operand
].bitfield
.imm64
= 1;
10544 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10552 i386_scale (char *scale
)
10555 char *save
= input_line_pointer
;
10557 input_line_pointer
= scale
;
10558 val
= get_absolute_expression ();
10563 i
.log2_scale_factor
= 0;
10566 i
.log2_scale_factor
= 1;
10569 i
.log2_scale_factor
= 2;
10572 i
.log2_scale_factor
= 3;
10576 char sep
= *input_line_pointer
;
10578 *input_line_pointer
= '\0';
10579 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10581 *input_line_pointer
= sep
;
10582 input_line_pointer
= save
;
10586 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10588 as_warn (_("scale factor of %d without an index register"),
10589 1 << i
.log2_scale_factor
);
10590 i
.log2_scale_factor
= 0;
10592 scale
= input_line_pointer
;
10593 input_line_pointer
= save
;
10598 i386_displacement (char *disp_start
, char *disp_end
)
10602 char *save_input_line_pointer
;
10603 char *gotfree_input_line
;
10605 i386_operand_type bigdisp
, types
= anydisp
;
10608 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10610 as_bad (_("at most %d displacement operands are allowed"),
10611 MAX_MEMORY_OPERANDS
);
10615 operand_type_set (&bigdisp
, 0);
10617 || i
.types
[this_operand
].bitfield
.baseindex
10618 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10619 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10621 i386_addressing_mode ();
10622 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10623 if (flag_code
== CODE_64BIT
)
10627 bigdisp
.bitfield
.disp32s
= 1;
10628 bigdisp
.bitfield
.disp64
= 1;
10631 bigdisp
.bitfield
.disp32
= 1;
10633 else if ((flag_code
== CODE_16BIT
) ^ override
)
10634 bigdisp
.bitfield
.disp16
= 1;
10636 bigdisp
.bitfield
.disp32
= 1;
10640 /* For PC-relative branches, the width of the displacement may be
10641 dependent upon data size, but is never dependent upon address size.
10642 Also make sure to not unintentionally match against a non-PC-relative
10643 branch template. */
10644 static templates aux_templates
;
10645 const insn_template
*t
= current_templates
->start
;
10646 bfd_boolean has_intel64
= FALSE
;
10648 aux_templates
.start
= t
;
10649 while (++t
< current_templates
->end
)
10651 if (t
->opcode_modifier
.jump
10652 != current_templates
->start
->opcode_modifier
.jump
)
10654 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10655 has_intel64
= TRUE
;
10657 if (t
< current_templates
->end
)
10659 aux_templates
.end
= t
;
10660 current_templates
= &aux_templates
;
10663 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10664 if (flag_code
== CODE_64BIT
)
10666 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10667 && (!intel64
|| !has_intel64
))
10668 bigdisp
.bitfield
.disp16
= 1;
10670 bigdisp
.bitfield
.disp32s
= 1;
10675 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10677 : LONG_MNEM_SUFFIX
));
10678 bigdisp
.bitfield
.disp32
= 1;
10679 if ((flag_code
== CODE_16BIT
) ^ override
)
10681 bigdisp
.bitfield
.disp32
= 0;
10682 bigdisp
.bitfield
.disp16
= 1;
10686 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10689 exp
= &disp_expressions
[i
.disp_operands
];
10690 i
.op
[this_operand
].disps
= exp
;
10692 save_input_line_pointer
= input_line_pointer
;
10693 input_line_pointer
= disp_start
;
10694 END_STRING_AND_SAVE (disp_end
);
10696 #ifndef GCC_ASM_O_HACK
10697 #define GCC_ASM_O_HACK 0
10700 END_STRING_AND_SAVE (disp_end
+ 1);
10701 if (i
.types
[this_operand
].bitfield
.baseIndex
10702 && displacement_string_end
[-1] == '+')
10704 /* This hack is to avoid a warning when using the "o"
10705 constraint within gcc asm statements.
10708 #define _set_tssldt_desc(n,addr,limit,type) \
10709 __asm__ __volatile__ ( \
10710 "movw %w2,%0\n\t" \
10711 "movw %w1,2+%0\n\t" \
10712 "rorl $16,%1\n\t" \
10713 "movb %b1,4+%0\n\t" \
10714 "movb %4,5+%0\n\t" \
10715 "movb $0,6+%0\n\t" \
10716 "movb %h1,7+%0\n\t" \
10718 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10720 This works great except that the output assembler ends
10721 up looking a bit weird if it turns out that there is
10722 no offset. You end up producing code that looks like:
10735 So here we provide the missing zero. */
10737 *displacement_string_end
= '0';
10740 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10741 if (gotfree_input_line
)
10742 input_line_pointer
= gotfree_input_line
;
10744 exp_seg
= expression (exp
);
10746 SKIP_WHITESPACE ();
10747 if (*input_line_pointer
)
10748 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10750 RESTORE_END_STRING (disp_end
+ 1);
10752 input_line_pointer
= save_input_line_pointer
;
10753 if (gotfree_input_line
)
10755 free (gotfree_input_line
);
10757 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10758 exp
->X_op
= O_illegal
;
10761 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10763 RESTORE_END_STRING (disp_end
);
10769 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10770 i386_operand_type types
, const char *disp_start
)
10772 i386_operand_type bigdisp
;
10775 /* We do this to make sure that the section symbol is in
10776 the symbol table. We will ultimately change the relocation
10777 to be relative to the beginning of the section. */
10778 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10779 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10780 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10782 if (exp
->X_op
!= O_symbol
)
10785 if (S_IS_LOCAL (exp
->X_add_symbol
)
10786 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10787 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10788 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10789 exp
->X_op
= O_subtract
;
10790 exp
->X_op_symbol
= GOT_symbol
;
10791 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10792 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10793 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10794 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10796 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10799 else if (exp
->X_op
== O_absent
10800 || exp
->X_op
== O_illegal
10801 || exp
->X_op
== O_big
)
10804 as_bad (_("missing or invalid displacement expression `%s'"),
10809 else if (flag_code
== CODE_64BIT
10810 && !i
.prefix
[ADDR_PREFIX
]
10811 && exp
->X_op
== O_constant
)
10813 /* Since displacement is signed extended to 64bit, don't allow
10814 disp32 and turn off disp32s if they are out of range. */
10815 i
.types
[this_operand
].bitfield
.disp32
= 0;
10816 if (!fits_in_signed_long (exp
->X_add_number
))
10818 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10819 if (i
.types
[this_operand
].bitfield
.baseindex
)
10821 as_bad (_("0x%lx out range of signed 32bit displacement"),
10822 (long) exp
->X_add_number
);
10828 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10829 else if (exp
->X_op
!= O_constant
10830 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10831 && exp_seg
!= absolute_section
10832 && exp_seg
!= text_section
10833 && exp_seg
!= data_section
10834 && exp_seg
!= bss_section
10835 && exp_seg
!= undefined_section
10836 && !bfd_is_com_section (exp_seg
))
10838 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10843 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10844 /* Constants get taken care of by optimize_disp(). */
10845 && exp
->X_op
!= O_constant
)
10846 i
.types
[this_operand
].bitfield
.disp8
= 1;
10848 /* Check if this is a displacement only operand. */
10849 bigdisp
= i
.types
[this_operand
];
10850 bigdisp
.bitfield
.disp8
= 0;
10851 bigdisp
.bitfield
.disp16
= 0;
10852 bigdisp
.bitfield
.disp32
= 0;
10853 bigdisp
.bitfield
.disp32s
= 0;
10854 bigdisp
.bitfield
.disp64
= 0;
10855 if (operand_type_all_zero (&bigdisp
))
10856 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10862 /* Return the active addressing mode, taking address override and
10863 registers forming the address into consideration. Update the
10864 address override prefix if necessary. */
10866 static enum flag_code
10867 i386_addressing_mode (void)
10869 enum flag_code addr_mode
;
10871 if (i
.prefix
[ADDR_PREFIX
])
10872 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10873 else if (flag_code
== CODE_16BIT
10874 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10875 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10876 from md_assemble() by "is not a valid base/index expression"
10877 when there is a base and/or index. */
10878 && !i
.types
[this_operand
].bitfield
.baseindex
)
10880 /* MPX insn memory operands with neither base nor index must be forced
10881 to use 32-bit addressing in 16-bit mode. */
10882 addr_mode
= CODE_32BIT
;
10883 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10885 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10886 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10890 addr_mode
= flag_code
;
10892 #if INFER_ADDR_PREFIX
10893 if (i
.mem_operands
== 0)
10895 /* Infer address prefix from the first memory operand. */
10896 const reg_entry
*addr_reg
= i
.base_reg
;
10898 if (addr_reg
== NULL
)
10899 addr_reg
= i
.index_reg
;
10903 if (addr_reg
->reg_type
.bitfield
.dword
)
10904 addr_mode
= CODE_32BIT
;
10905 else if (flag_code
!= CODE_64BIT
10906 && addr_reg
->reg_type
.bitfield
.word
)
10907 addr_mode
= CODE_16BIT
;
10909 if (addr_mode
!= flag_code
)
10911 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10913 /* Change the size of any displacement too. At most one
10914 of Disp16 or Disp32 is set.
10915 FIXME. There doesn't seem to be any real need for
10916 separate Disp16 and Disp32 flags. The same goes for
10917 Imm16 and Imm32. Removing them would probably clean
10918 up the code quite a lot. */
10919 if (flag_code
!= CODE_64BIT
10920 && (i
.types
[this_operand
].bitfield
.disp16
10921 || i
.types
[this_operand
].bitfield
.disp32
))
10922 i
.types
[this_operand
]
10923 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10933 /* Make sure the memory operand we've been dealt is valid.
10934 Return 1 on success, 0 on a failure. */
10937 i386_index_check (const char *operand_string
)
10939 const char *kind
= "base/index";
10940 enum flag_code addr_mode
= i386_addressing_mode ();
10942 if (current_templates
->start
->opcode_modifier
.isstring
10943 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10944 && (current_templates
->end
[-1].opcode_modifier
.isstring
10945 || i
.mem_operands
))
10947 /* Memory operands of string insns are special in that they only allow
10948 a single register (rDI, rSI, or rBX) as their memory address. */
10949 const reg_entry
*expected_reg
;
10950 static const char *di_si
[][2] =
10956 static const char *bx
[] = { "ebx", "bx", "rbx" };
10958 kind
= "string address";
10960 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10962 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10963 - IS_STRING_ES_OP0
;
10966 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10967 || ((!i
.mem_operands
!= !intel_syntax
)
10968 && current_templates
->end
[-1].operand_types
[1]
10969 .bitfield
.baseindex
))
10971 expected_reg
= (const reg_entry
*)str_hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10974 expected_reg
= (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
10976 if (i
.base_reg
!= expected_reg
10978 || operand_type_check (i
.types
[this_operand
], disp
))
10980 /* The second memory operand must have the same size as
10984 && !((addr_mode
== CODE_64BIT
10985 && i
.base_reg
->reg_type
.bitfield
.qword
)
10986 || (addr_mode
== CODE_32BIT
10987 ? i
.base_reg
->reg_type
.bitfield
.dword
10988 : i
.base_reg
->reg_type
.bitfield
.word
)))
10991 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10993 intel_syntax
? '[' : '(',
10995 expected_reg
->reg_name
,
10996 intel_syntax
? ']' : ')');
11003 as_bad (_("`%s' is not a valid %s expression"),
11004 operand_string
, kind
);
11009 if (addr_mode
!= CODE_16BIT
)
11011 /* 32-bit/64-bit checks. */
11012 if (i
.disp_encoding
== disp_encoding_16bit
)
11015 as_bad (_("invalid `%s' prefix"),
11016 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11021 && ((addr_mode
== CODE_64BIT
11022 ? !i
.base_reg
->reg_type
.bitfield
.qword
11023 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11024 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11025 || i
.base_reg
->reg_num
== RegIZ
))
11027 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11028 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11029 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11030 && ((addr_mode
== CODE_64BIT
11031 ? !i
.index_reg
->reg_type
.bitfield
.qword
11032 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11033 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11036 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11037 if (current_templates
->start
->base_opcode
== 0xf30f1b
11038 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11039 || current_templates
->start
->opcode_modifier
.sib
== SIBMEM
)
11041 /* They cannot use RIP-relative addressing. */
11042 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11044 as_bad (_("`%s' cannot be used here"), operand_string
);
11048 /* bndldx and bndstx ignore their scale factor. */
11049 if ((current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11050 && i
.log2_scale_factor
)
11051 as_warn (_("register scaling is being ignored here"));
11056 /* 16-bit checks. */
11057 if (i
.disp_encoding
== disp_encoding_32bit
)
11061 && (!i
.base_reg
->reg_type
.bitfield
.word
11062 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11064 && (!i
.index_reg
->reg_type
.bitfield
.word
11065 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11067 && i
.base_reg
->reg_num
< 6
11068 && i
.index_reg
->reg_num
>= 6
11069 && i
.log2_scale_factor
== 0))))
11076 /* Handle vector immediates. */
11079 RC_SAE_immediate (const char *imm_start
)
11081 unsigned int match_found
, j
;
11082 const char *pstr
= imm_start
;
11090 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11092 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11096 rc_op
.type
= RC_NamesTable
[j
].type
;
11097 rc_op
.operand
= this_operand
;
11098 i
.rounding
= &rc_op
;
11102 as_bad (_("duplicated `%s'"), imm_start
);
11105 pstr
+= RC_NamesTable
[j
].len
;
11113 if (*pstr
++ != '}')
11115 as_bad (_("Missing '}': '%s'"), imm_start
);
11118 /* RC/SAE immediate string should contain nothing more. */;
11121 as_bad (_("Junk after '}': '%s'"), imm_start
);
11125 exp
= &im_expressions
[i
.imm_operands
++];
11126 i
.op
[this_operand
].imms
= exp
;
11128 exp
->X_op
= O_constant
;
11129 exp
->X_add_number
= 0;
11130 exp
->X_add_symbol
= (symbolS
*) 0;
11131 exp
->X_op_symbol
= (symbolS
*) 0;
11133 i
.types
[this_operand
].bitfield
.imm8
= 1;
11137 /* Only string instructions can have a second memory operand, so
11138 reduce current_templates to just those if it contains any. */
11140 maybe_adjust_templates (void)
11142 const insn_template
*t
;
11144 gas_assert (i
.mem_operands
== 1);
11146 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11147 if (t
->opcode_modifier
.isstring
)
11150 if (t
< current_templates
->end
)
11152 static templates aux_templates
;
11153 bfd_boolean recheck
;
11155 aux_templates
.start
= t
;
11156 for (; t
< current_templates
->end
; ++t
)
11157 if (!t
->opcode_modifier
.isstring
)
11159 aux_templates
.end
= t
;
11161 /* Determine whether to re-check the first memory operand. */
11162 recheck
= (aux_templates
.start
!= current_templates
->start
11163 || t
!= current_templates
->end
);
11165 current_templates
= &aux_templates
;
11169 i
.mem_operands
= 0;
11170 if (i
.memop1_string
!= NULL
11171 && i386_index_check (i
.memop1_string
) == 0)
11173 i
.mem_operands
= 1;
11180 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11184 i386_att_operand (char *operand_string
)
11186 const reg_entry
*r
;
11188 char *op_string
= operand_string
;
11190 if (is_space_char (*op_string
))
11193 /* We check for an absolute prefix (differentiating,
11194 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11195 if (*op_string
== ABSOLUTE_PREFIX
)
11198 if (is_space_char (*op_string
))
11200 i
.jumpabsolute
= TRUE
;
11203 /* Check if operand is a register. */
11204 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11206 i386_operand_type temp
;
11211 /* Check for a segment override by searching for ':' after a
11212 segment register. */
11213 op_string
= end_op
;
11214 if (is_space_char (*op_string
))
11216 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11218 switch (r
->reg_num
)
11221 i
.seg
[i
.mem_operands
] = &es
;
11224 i
.seg
[i
.mem_operands
] = &cs
;
11227 i
.seg
[i
.mem_operands
] = &ss
;
11230 i
.seg
[i
.mem_operands
] = &ds
;
11233 i
.seg
[i
.mem_operands
] = &fs
;
11236 i
.seg
[i
.mem_operands
] = &gs
;
11240 /* Skip the ':' and whitespace. */
11242 if (is_space_char (*op_string
))
11245 if (!is_digit_char (*op_string
)
11246 && !is_identifier_char (*op_string
)
11247 && *op_string
!= '('
11248 && *op_string
!= ABSOLUTE_PREFIX
)
11250 as_bad (_("bad memory operand `%s'"), op_string
);
11253 /* Handle case of %es:*foo. */
11254 if (*op_string
== ABSOLUTE_PREFIX
)
11257 if (is_space_char (*op_string
))
11259 i
.jumpabsolute
= TRUE
;
11261 goto do_memory_reference
;
11264 /* Handle vector operations. */
11265 if (*op_string
== '{')
11267 op_string
= check_VecOperations (op_string
, NULL
);
11268 if (op_string
== NULL
)
11274 as_bad (_("junk `%s' after register"), op_string
);
11277 temp
= r
->reg_type
;
11278 temp
.bitfield
.baseindex
= 0;
11279 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11281 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11282 i
.op
[this_operand
].regs
= r
;
11285 else if (*op_string
== REGISTER_PREFIX
)
11287 as_bad (_("bad register name `%s'"), op_string
);
11290 else if (*op_string
== IMMEDIATE_PREFIX
)
11293 if (i
.jumpabsolute
)
11295 as_bad (_("immediate operand illegal with absolute jump"));
11298 if (!i386_immediate (op_string
))
11301 else if (RC_SAE_immediate (operand_string
))
11303 /* If it is a RC or SAE immediate, do nothing. */
11306 else if (is_digit_char (*op_string
)
11307 || is_identifier_char (*op_string
)
11308 || *op_string
== '"'
11309 || *op_string
== '(')
11311 /* This is a memory reference of some sort. */
11314 /* Start and end of displacement string expression (if found). */
11315 char *displacement_string_start
;
11316 char *displacement_string_end
;
11319 do_memory_reference
:
11320 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11322 if ((i
.mem_operands
== 1
11323 && !current_templates
->start
->opcode_modifier
.isstring
)
11324 || i
.mem_operands
== 2)
11326 as_bad (_("too many memory references for `%s'"),
11327 current_templates
->start
->name
);
11331 /* Check for base index form. We detect the base index form by
11332 looking for an ')' at the end of the operand, searching
11333 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11335 base_string
= op_string
+ strlen (op_string
);
11337 /* Handle vector operations. */
11338 vop_start
= strchr (op_string
, '{');
11339 if (vop_start
&& vop_start
< base_string
)
11341 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11343 base_string
= vop_start
;
11347 if (is_space_char (*base_string
))
11350 /* If we only have a displacement, set-up for it to be parsed later. */
11351 displacement_string_start
= op_string
;
11352 displacement_string_end
= base_string
+ 1;
11354 if (*base_string
== ')')
11357 unsigned int parens_balanced
= 1;
11358 /* We've already checked that the number of left & right ()'s are
11359 equal, so this loop will not be infinite. */
11363 if (*base_string
== ')')
11365 if (*base_string
== '(')
11368 while (parens_balanced
);
11370 temp_string
= base_string
;
11372 /* Skip past '(' and whitespace. */
11374 if (is_space_char (*base_string
))
11377 if (*base_string
== ','
11378 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11381 displacement_string_end
= temp_string
;
11383 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11387 if (i
.base_reg
== &bad_reg
)
11389 base_string
= end_op
;
11390 if (is_space_char (*base_string
))
11394 /* There may be an index reg or scale factor here. */
11395 if (*base_string
== ',')
11398 if (is_space_char (*base_string
))
11401 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11404 if (i
.index_reg
== &bad_reg
)
11406 base_string
= end_op
;
11407 if (is_space_char (*base_string
))
11409 if (*base_string
== ',')
11412 if (is_space_char (*base_string
))
11415 else if (*base_string
!= ')')
11417 as_bad (_("expecting `,' or `)' "
11418 "after index register in `%s'"),
11423 else if (*base_string
== REGISTER_PREFIX
)
11425 end_op
= strchr (base_string
, ',');
11428 as_bad (_("bad register name `%s'"), base_string
);
11432 /* Check for scale factor. */
11433 if (*base_string
!= ')')
11435 char *end_scale
= i386_scale (base_string
);
11440 base_string
= end_scale
;
11441 if (is_space_char (*base_string
))
11443 if (*base_string
!= ')')
11445 as_bad (_("expecting `)' "
11446 "after scale factor in `%s'"),
11451 else if (!i
.index_reg
)
11453 as_bad (_("expecting index register or scale factor "
11454 "after `,'; got '%c'"),
11459 else if (*base_string
!= ')')
11461 as_bad (_("expecting `,' or `)' "
11462 "after base register in `%s'"),
11467 else if (*base_string
== REGISTER_PREFIX
)
11469 end_op
= strchr (base_string
, ',');
11472 as_bad (_("bad register name `%s'"), base_string
);
11477 /* If there's an expression beginning the operand, parse it,
11478 assuming displacement_string_start and
11479 displacement_string_end are meaningful. */
11480 if (displacement_string_start
!= displacement_string_end
)
11482 if (!i386_displacement (displacement_string_start
,
11483 displacement_string_end
))
11487 /* Special case for (%dx) while doing input/output op. */
11489 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11490 && i
.base_reg
->reg_type
.bitfield
.word
11491 && i
.index_reg
== 0
11492 && i
.log2_scale_factor
== 0
11493 && i
.seg
[i
.mem_operands
] == 0
11494 && !operand_type_check (i
.types
[this_operand
], disp
))
11496 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11500 if (i386_index_check (operand_string
) == 0)
11502 i
.flags
[this_operand
] |= Operand_Mem
;
11503 if (i
.mem_operands
== 0)
11504 i
.memop1_string
= xstrdup (operand_string
);
11509 /* It's not a memory operand; argh! */
11510 as_bad (_("invalid char %s beginning operand %d `%s'"),
11511 output_invalid (*op_string
),
11516 return 1; /* Normal return. */
11519 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11520 that an rs_machine_dependent frag may reach. */
11523 i386_frag_max_var (fragS
*frag
)
11525 /* The only relaxable frags are for jumps.
11526 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11527 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11528 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11531 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11533 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11535 /* STT_GNU_IFUNC symbol must go through PLT. */
11536 if ((symbol_get_bfdsym (fr_symbol
)->flags
11537 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11540 if (!S_IS_EXTERNAL (fr_symbol
))
11541 /* Symbol may be weak or local. */
11542 return !S_IS_WEAK (fr_symbol
);
11544 /* Global symbols with non-default visibility can't be preempted. */
11545 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11548 if (fr_var
!= NO_RELOC
)
11549 switch ((enum bfd_reloc_code_real
) fr_var
)
11551 case BFD_RELOC_386_PLT32
:
11552 case BFD_RELOC_X86_64_PLT32
:
11553 /* Symbol with PLT relocation may be preempted. */
11559 /* Global symbols with default visibility in a shared library may be
11560 preempted by another definition. */
11565 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11566 Note also work for Skylake and Cascadelake.
11567 ---------------------------------------------------------------------
11568 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11569 | ------ | ----------- | ------- | -------- |
11571 | Jno | N | N | Y |
11572 | Jc/Jb | Y | N | Y |
11573 | Jae/Jnb | Y | N | Y |
11574 | Je/Jz | Y | Y | Y |
11575 | Jne/Jnz | Y | Y | Y |
11576 | Jna/Jbe | Y | N | Y |
11577 | Ja/Jnbe | Y | N | Y |
11579 | Jns | N | N | Y |
11580 | Jp/Jpe | N | N | Y |
11581 | Jnp/Jpo | N | N | Y |
11582 | Jl/Jnge | Y | Y | Y |
11583 | Jge/Jnl | Y | Y | Y |
11584 | Jle/Jng | Y | Y | Y |
11585 | Jg/Jnle | Y | Y | Y |
11586 --------------------------------------------------------------------- */
11588 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11590 if (mf_cmp
== mf_cmp_alu_cmp
)
11591 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11592 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11593 if (mf_cmp
== mf_cmp_incdec
)
11594 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11595 || mf_jcc
== mf_jcc_jle
);
11596 if (mf_cmp
== mf_cmp_test_and
)
11601 /* Return the next non-empty frag. */
11604 i386_next_non_empty_frag (fragS
*fragP
)
11606 /* There may be a frag with a ".fill 0" when there is no room in
11607 the current frag for frag_grow in output_insn. */
11608 for (fragP
= fragP
->fr_next
;
11610 && fragP
->fr_type
== rs_fill
11611 && fragP
->fr_fix
== 0);
11612 fragP
= fragP
->fr_next
)
11617 /* Return the next jcc frag after BRANCH_PADDING. */
11620 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11622 fragS
*branch_fragP
;
11626 if (pad_fragP
->fr_type
== rs_machine_dependent
11627 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11628 == BRANCH_PADDING
))
11630 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11631 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11633 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11634 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11635 pad_fragP
->tc_frag_data
.mf_type
))
11636 return branch_fragP
;
11642 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11645 i386_classify_machine_dependent_frag (fragS
*fragP
)
11649 fragS
*branch_fragP
;
11651 unsigned int max_prefix_length
;
11653 if (fragP
->tc_frag_data
.classified
)
11656 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11657 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11658 for (next_fragP
= fragP
;
11659 next_fragP
!= NULL
;
11660 next_fragP
= next_fragP
->fr_next
)
11662 next_fragP
->tc_frag_data
.classified
= 1;
11663 if (next_fragP
->fr_type
== rs_machine_dependent
)
11664 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11666 case BRANCH_PADDING
:
11667 /* The BRANCH_PADDING frag must be followed by a branch
11669 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11670 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11672 case FUSED_JCC_PADDING
:
11673 /* Check if this is a fused jcc:
11675 CMP like instruction
11679 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11680 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11681 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11684 /* The BRANCH_PADDING frag is merged with the
11685 FUSED_JCC_PADDING frag. */
11686 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11687 /* CMP like instruction size. */
11688 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11689 frag_wane (pad_fragP
);
11690 /* Skip to branch_fragP. */
11691 next_fragP
= branch_fragP
;
11693 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11695 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11697 next_fragP
->fr_subtype
11698 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11699 next_fragP
->tc_frag_data
.max_bytes
11700 = next_fragP
->tc_frag_data
.max_prefix_length
;
11701 /* This will be updated in the BRANCH_PREFIX scan. */
11702 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11705 frag_wane (next_fragP
);
11710 /* Stop if there is no BRANCH_PREFIX. */
11711 if (!align_branch_prefix_size
)
11714 /* Scan for BRANCH_PREFIX. */
11715 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11717 if (fragP
->fr_type
!= rs_machine_dependent
11718 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11722 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11723 COND_JUMP_PREFIX. */
11724 max_prefix_length
= 0;
11725 for (next_fragP
= fragP
;
11726 next_fragP
!= NULL
;
11727 next_fragP
= next_fragP
->fr_next
)
11729 if (next_fragP
->fr_type
== rs_fill
)
11730 /* Skip rs_fill frags. */
11732 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11733 /* Stop for all other frags. */
11736 /* rs_machine_dependent frags. */
11737 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11740 /* Count BRANCH_PREFIX frags. */
11741 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11743 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11744 frag_wane (next_fragP
);
11748 += next_fragP
->tc_frag_data
.max_bytes
;
11750 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11752 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11753 == FUSED_JCC_PADDING
))
11755 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11756 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11760 /* Stop for other rs_machine_dependent frags. */
11764 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11766 /* Skip to the next frag. */
11767 fragP
= next_fragP
;
11771 /* Compute padding size for
11774 CMP like instruction
11776 COND_JUMP/UNCOND_JUMP
11781 COND_JUMP/UNCOND_JUMP
11785 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11787 unsigned int offset
, size
, padding_size
;
11788 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11790 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11792 address
= fragP
->fr_address
;
11793 address
+= fragP
->fr_fix
;
11795 /* CMP like instrunction size. */
11796 size
= fragP
->tc_frag_data
.cmp_size
;
11798 /* The base size of the branch frag. */
11799 size
+= branch_fragP
->fr_fix
;
11801 /* Add opcode and displacement bytes for the rs_machine_dependent
11803 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11804 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11806 /* Check if branch is within boundary and doesn't end at the last
11808 offset
= address
& ((1U << align_branch_power
) - 1);
11809 if ((offset
+ size
) >= (1U << align_branch_power
))
11810 /* Padding needed to avoid crossing boundary. */
11811 padding_size
= (1U << align_branch_power
) - offset
;
11813 /* No padding needed. */
11816 /* The return value may be saved in tc_frag_data.length which is
11818 if (!fits_in_unsigned_byte (padding_size
))
11821 return padding_size
;
11824 /* i386_generic_table_relax_frag()
11826 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11827 grow/shrink padding to align branch frags. Hand others to
11831 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11833 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11834 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11836 long padding_size
= i386_branch_padding_size (fragP
, 0);
11837 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11839 /* When the BRANCH_PREFIX frag is used, the computed address
11840 must match the actual address and there should be no padding. */
11841 if (fragP
->tc_frag_data
.padding_address
11842 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11846 /* Update the padding size. */
11848 fragP
->tc_frag_data
.length
= padding_size
;
11852 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11854 fragS
*padding_fragP
, *next_fragP
;
11855 long padding_size
, left_size
, last_size
;
11857 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11858 if (!padding_fragP
)
11859 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11860 return (fragP
->tc_frag_data
.length
11861 - fragP
->tc_frag_data
.last_length
);
11863 /* Compute the relative address of the padding frag in the very
11864 first time where the BRANCH_PREFIX frag sizes are zero. */
11865 if (!fragP
->tc_frag_data
.padding_address
)
11866 fragP
->tc_frag_data
.padding_address
11867 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11869 /* First update the last length from the previous interation. */
11870 left_size
= fragP
->tc_frag_data
.prefix_length
;
11871 for (next_fragP
= fragP
;
11872 next_fragP
!= padding_fragP
;
11873 next_fragP
= next_fragP
->fr_next
)
11874 if (next_fragP
->fr_type
== rs_machine_dependent
11875 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11880 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11884 if (max
> left_size
)
11889 next_fragP
->tc_frag_data
.last_length
= size
;
11893 next_fragP
->tc_frag_data
.last_length
= 0;
11896 /* Check the padding size for the padding frag. */
11897 padding_size
= i386_branch_padding_size
11898 (padding_fragP
, (fragP
->fr_address
11899 + fragP
->tc_frag_data
.padding_address
));
11901 last_size
= fragP
->tc_frag_data
.prefix_length
;
11902 /* Check if there is change from the last interation. */
11903 if (padding_size
== last_size
)
11905 /* Update the expected address of the padding frag. */
11906 padding_fragP
->tc_frag_data
.padding_address
11907 = (fragP
->fr_address
+ padding_size
11908 + fragP
->tc_frag_data
.padding_address
);
11912 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11914 /* No padding if there is no sufficient room. Clear the
11915 expected address of the padding frag. */
11916 padding_fragP
->tc_frag_data
.padding_address
= 0;
11920 /* Store the expected address of the padding frag. */
11921 padding_fragP
->tc_frag_data
.padding_address
11922 = (fragP
->fr_address
+ padding_size
11923 + fragP
->tc_frag_data
.padding_address
);
11925 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11927 /* Update the length for the current interation. */
11928 left_size
= padding_size
;
11929 for (next_fragP
= fragP
;
11930 next_fragP
!= padding_fragP
;
11931 next_fragP
= next_fragP
->fr_next
)
11932 if (next_fragP
->fr_type
== rs_machine_dependent
11933 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11938 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11942 if (max
> left_size
)
11947 next_fragP
->tc_frag_data
.length
= size
;
11951 next_fragP
->tc_frag_data
.length
= 0;
11954 return (fragP
->tc_frag_data
.length
11955 - fragP
->tc_frag_data
.last_length
);
11957 return relax_frag (segment
, fragP
, stretch
);
11960 /* md_estimate_size_before_relax()
11962 Called just before relax() for rs_machine_dependent frags. The x86
11963 assembler uses these frags to handle variable size jump
11966 Any symbol that is now undefined will not become defined.
11967 Return the correct fr_subtype in the frag.
11968 Return the initial "guess for variable size of frag" to caller.
11969 The guess is actually the growth beyond the fixed part. Whatever
11970 we do to grow the fixed or variable part contributes to our
11974 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11976 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11977 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11978 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11980 i386_classify_machine_dependent_frag (fragP
);
11981 return fragP
->tc_frag_data
.length
;
11984 /* We've already got fragP->fr_subtype right; all we have to do is
11985 check for un-relaxable symbols. On an ELF system, we can't relax
11986 an externally visible symbol, because it may be overridden by a
11988 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11989 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11991 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11994 #if defined (OBJ_COFF) && defined (TE_PE)
11995 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11996 && S_IS_WEAK (fragP
->fr_symbol
))
12000 /* Symbol is undefined in this segment, or we need to keep a
12001 reloc so that weak symbols can be overridden. */
12002 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12003 enum bfd_reloc_code_real reloc_type
;
12004 unsigned char *opcode
;
12007 if (fragP
->fr_var
!= NO_RELOC
)
12008 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12009 else if (size
== 2)
12010 reloc_type
= BFD_RELOC_16_PCREL
;
12011 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12012 else if (need_plt32_p (fragP
->fr_symbol
))
12013 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12016 reloc_type
= BFD_RELOC_32_PCREL
;
12018 old_fr_fix
= fragP
->fr_fix
;
12019 opcode
= (unsigned char *) fragP
->fr_opcode
;
12021 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12024 /* Make jmp (0xeb) a (d)word displacement jump. */
12026 fragP
->fr_fix
+= size
;
12027 fix_new (fragP
, old_fr_fix
, size
,
12029 fragP
->fr_offset
, 1,
12035 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12037 /* Negate the condition, and branch past an
12038 unconditional jump. */
12041 /* Insert an unconditional jump. */
12043 /* We added two extra opcode bytes, and have a two byte
12045 fragP
->fr_fix
+= 2 + 2;
12046 fix_new (fragP
, old_fr_fix
+ 2, 2,
12048 fragP
->fr_offset
, 1,
12052 /* Fall through. */
12055 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12059 fragP
->fr_fix
+= 1;
12060 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12062 fragP
->fr_offset
, 1,
12063 BFD_RELOC_8_PCREL
);
12064 fixP
->fx_signed
= 1;
12068 /* This changes the byte-displacement jump 0x7N
12069 to the (d)word-displacement jump 0x0f,0x8N. */
12070 opcode
[1] = opcode
[0] + 0x10;
12071 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12072 /* We've added an opcode byte. */
12073 fragP
->fr_fix
+= 1 + size
;
12074 fix_new (fragP
, old_fr_fix
+ 1, size
,
12076 fragP
->fr_offset
, 1,
12081 BAD_CASE (fragP
->fr_subtype
);
12085 return fragP
->fr_fix
- old_fr_fix
;
12088 /* Guess size depending on current relax state. Initially the relax
12089 state will correspond to a short jump and we return 1, because
12090 the variable part of the frag (the branch offset) is one byte
12091 long. However, we can relax a section more than once and in that
12092 case we must either set fr_subtype back to the unrelaxed state,
12093 or return the value for the appropriate branch. */
12094 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12097 /* Called after relax() is finished.
12099 In: Address of frag.
12100 fr_type == rs_machine_dependent.
12101 fr_subtype is what the address relaxed to.
12103 Out: Any fixSs and constants are set up.
12104 Caller will turn frag into a ".space 0". */
12107 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12110 unsigned char *opcode
;
12111 unsigned char *where_to_put_displacement
= NULL
;
12112 offsetT target_address
;
12113 offsetT opcode_address
;
12114 unsigned int extension
= 0;
12115 offsetT displacement_from_opcode_start
;
12117 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12118 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12119 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12121 /* Generate nop padding. */
12122 unsigned int size
= fragP
->tc_frag_data
.length
;
12125 if (size
> fragP
->tc_frag_data
.max_bytes
)
12131 const char *branch
= "branch";
12132 const char *prefix
= "";
12133 fragS
*padding_fragP
;
12134 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12137 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12138 switch (fragP
->tc_frag_data
.default_prefix
)
12143 case CS_PREFIX_OPCODE
:
12146 case DS_PREFIX_OPCODE
:
12149 case ES_PREFIX_OPCODE
:
12152 case FS_PREFIX_OPCODE
:
12155 case GS_PREFIX_OPCODE
:
12158 case SS_PREFIX_OPCODE
:
12163 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12164 "%s within %d-byte boundary\n");
12166 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12167 "align %s within %d-byte boundary\n");
12171 padding_fragP
= fragP
;
12172 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12173 "%s within %d-byte boundary\n");
12177 switch (padding_fragP
->tc_frag_data
.branch_type
)
12179 case align_branch_jcc
:
12182 case align_branch_fused
:
12183 branch
= "fused jcc";
12185 case align_branch_jmp
:
12188 case align_branch_call
:
12191 case align_branch_indirect
:
12192 branch
= "indiret branch";
12194 case align_branch_ret
:
12201 fprintf (stdout
, msg
,
12202 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12203 (long long) fragP
->fr_address
, branch
,
12204 1 << align_branch_power
);
12206 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12207 memset (fragP
->fr_opcode
,
12208 fragP
->tc_frag_data
.default_prefix
, size
);
12210 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12212 fragP
->fr_fix
+= size
;
12217 opcode
= (unsigned char *) fragP
->fr_opcode
;
12219 /* Address we want to reach in file space. */
12220 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12222 /* Address opcode resides at in file space. */
12223 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12225 /* Displacement from opcode start to fill into instruction. */
12226 displacement_from_opcode_start
= target_address
- opcode_address
;
12228 if ((fragP
->fr_subtype
& BIG
) == 0)
12230 /* Don't have to change opcode. */
12231 extension
= 1; /* 1 opcode + 1 displacement */
12232 where_to_put_displacement
= &opcode
[1];
12236 if (no_cond_jump_promotion
12237 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12238 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12239 _("long jump required"));
12241 switch (fragP
->fr_subtype
)
12243 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12244 extension
= 4; /* 1 opcode + 4 displacement */
12246 where_to_put_displacement
= &opcode
[1];
12249 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12250 extension
= 2; /* 1 opcode + 2 displacement */
12252 where_to_put_displacement
= &opcode
[1];
12255 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12256 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12257 extension
= 5; /* 2 opcode + 4 displacement */
12258 opcode
[1] = opcode
[0] + 0x10;
12259 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12260 where_to_put_displacement
= &opcode
[2];
12263 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12264 extension
= 3; /* 2 opcode + 2 displacement */
12265 opcode
[1] = opcode
[0] + 0x10;
12266 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12267 where_to_put_displacement
= &opcode
[2];
12270 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12275 where_to_put_displacement
= &opcode
[3];
12279 BAD_CASE (fragP
->fr_subtype
);
12284 /* If size if less then four we are sure that the operand fits,
12285 but if it's 4, then it could be that the displacement is larger
12287 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12289 && ((addressT
) (displacement_from_opcode_start
- extension
12290 + ((addressT
) 1 << 31))
12291 > (((addressT
) 2 << 31) - 1)))
12293 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12294 _("jump target out of range"));
12295 /* Make us emit 0. */
12296 displacement_from_opcode_start
= extension
;
12298 /* Now put displacement after opcode. */
12299 md_number_to_chars ((char *) where_to_put_displacement
,
12300 (valueT
) (displacement_from_opcode_start
- extension
),
12301 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12302 fragP
->fr_fix
+= extension
;
12305 /* Apply a fixup (fixP) to segment data, once it has been determined
12306 by our caller that we have all the info we need to fix it up.
12308 Parameter valP is the pointer to the value of the bits.
12310 On the 386, immediates, displacements, and data pointers are all in
12311 the same (little-endian) format, so we don't need to care about which
12312 we are handling. */
12315 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12317 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12318 valueT value
= *valP
;
12320 #if !defined (TE_Mach)
12321 if (fixP
->fx_pcrel
)
12323 switch (fixP
->fx_r_type
)
12329 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12332 case BFD_RELOC_X86_64_32S
:
12333 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12336 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12339 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12344 if (fixP
->fx_addsy
!= NULL
12345 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12346 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12347 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12348 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12349 && !use_rela_relocations
)
12351 /* This is a hack. There should be a better way to handle this.
12352 This covers for the fact that bfd_install_relocation will
12353 subtract the current location (for partial_inplace, PC relative
12354 relocations); see more below. */
12358 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12361 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12363 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12366 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12368 if ((sym_seg
== seg
12369 || (symbol_section_p (fixP
->fx_addsy
)
12370 && sym_seg
!= absolute_section
))
12371 && !generic_force_reloc (fixP
))
12373 /* Yes, we add the values in twice. This is because
12374 bfd_install_relocation subtracts them out again. I think
12375 bfd_install_relocation is broken, but I don't dare change
12377 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12381 #if defined (OBJ_COFF) && defined (TE_PE)
12382 /* For some reason, the PE format does not store a
12383 section address offset for a PC relative symbol. */
12384 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12385 || S_IS_WEAK (fixP
->fx_addsy
))
12386 value
+= md_pcrel_from (fixP
);
12389 #if defined (OBJ_COFF) && defined (TE_PE)
12390 if (fixP
->fx_addsy
!= NULL
12391 && S_IS_WEAK (fixP
->fx_addsy
)
12392 /* PR 16858: Do not modify weak function references. */
12393 && ! fixP
->fx_pcrel
)
12395 #if !defined (TE_PEP)
12396 /* For x86 PE weak function symbols are neither PC-relative
12397 nor do they set S_IS_FUNCTION. So the only reliable way
12398 to detect them is to check the flags of their containing
12400 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12401 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12405 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12409 /* Fix a few things - the dynamic linker expects certain values here,
12410 and we must not disappoint it. */
12411 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12412 if (IS_ELF
&& fixP
->fx_addsy
)
12413 switch (fixP
->fx_r_type
)
12415 case BFD_RELOC_386_PLT32
:
12416 case BFD_RELOC_X86_64_PLT32
:
12417 /* Make the jump instruction point to the address of the operand.
12418 At runtime we merely add the offset to the actual PLT entry.
12419 NB: Subtract the offset size only for jump instructions. */
12420 if (fixP
->fx_pcrel
)
12424 case BFD_RELOC_386_TLS_GD
:
12425 case BFD_RELOC_386_TLS_LDM
:
12426 case BFD_RELOC_386_TLS_IE_32
:
12427 case BFD_RELOC_386_TLS_IE
:
12428 case BFD_RELOC_386_TLS_GOTIE
:
12429 case BFD_RELOC_386_TLS_GOTDESC
:
12430 case BFD_RELOC_X86_64_TLSGD
:
12431 case BFD_RELOC_X86_64_TLSLD
:
12432 case BFD_RELOC_X86_64_GOTTPOFF
:
12433 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12434 value
= 0; /* Fully resolved at runtime. No addend. */
12436 case BFD_RELOC_386_TLS_LE
:
12437 case BFD_RELOC_386_TLS_LDO_32
:
12438 case BFD_RELOC_386_TLS_LE_32
:
12439 case BFD_RELOC_X86_64_DTPOFF32
:
12440 case BFD_RELOC_X86_64_DTPOFF64
:
12441 case BFD_RELOC_X86_64_TPOFF32
:
12442 case BFD_RELOC_X86_64_TPOFF64
:
12443 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12446 case BFD_RELOC_386_TLS_DESC_CALL
:
12447 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12448 value
= 0; /* Fully resolved at runtime. No addend. */
12449 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12453 case BFD_RELOC_VTABLE_INHERIT
:
12454 case BFD_RELOC_VTABLE_ENTRY
:
12461 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12463 #endif /* !defined (TE_Mach) */
12465 /* Are we finished with this relocation now? */
12466 if (fixP
->fx_addsy
== NULL
)
12468 #if defined (OBJ_COFF) && defined (TE_PE)
12469 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12472 /* Remember value for tc_gen_reloc. */
12473 fixP
->fx_addnumber
= value
;
12474 /* Clear out the frag for now. */
12478 else if (use_rela_relocations
)
12480 fixP
->fx_no_overflow
= 1;
12481 /* Remember value for tc_gen_reloc. */
12482 fixP
->fx_addnumber
= value
;
12486 md_number_to_chars (p
, value
, fixP
->fx_size
);
12490 md_atof (int type
, char *litP
, int *sizeP
)
12492 /* This outputs the LITTLENUMs in REVERSE order;
12493 in accord with the bigendian 386. */
12494 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12497 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12500 output_invalid (int c
)
12503 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12506 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12507 "(0x%x)", (unsigned char) c
);
12508 return output_invalid_buf
;
12511 /* Verify that @r can be used in the current context. */
12513 static bfd_boolean
check_register (const reg_entry
*r
)
12515 if (allow_pseudo_reg
)
12518 if (operand_type_all_zero (&r
->reg_type
))
12521 if ((r
->reg_type
.bitfield
.dword
12522 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12523 || r
->reg_type
.bitfield
.class == RegCR
12524 || r
->reg_type
.bitfield
.class == RegDR
)
12525 && !cpu_arch_flags
.bitfield
.cpui386
)
12528 if (r
->reg_type
.bitfield
.class == RegTR
12529 && (flag_code
== CODE_64BIT
12530 || !cpu_arch_flags
.bitfield
.cpui386
12531 || cpu_arch_isa_flags
.bitfield
.cpui586
12532 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12535 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12538 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12540 if (r
->reg_type
.bitfield
.zmmword
12541 || r
->reg_type
.bitfield
.class == RegMask
)
12544 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12546 if (r
->reg_type
.bitfield
.ymmword
)
12549 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12554 if (r
->reg_type
.bitfield
.tmmword
12555 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12556 || flag_code
!= CODE_64BIT
))
12559 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12562 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12563 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12566 /* Upper 16 vector registers are only available with VREX in 64bit
12567 mode, and require EVEX encoding. */
12568 if (r
->reg_flags
& RegVRex
)
12570 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12571 || flag_code
!= CODE_64BIT
)
12574 if (i
.vec_encoding
== vex_encoding_default
)
12575 i
.vec_encoding
= vex_encoding_evex
;
12576 else if (i
.vec_encoding
!= vex_encoding_evex
)
12577 i
.vec_encoding
= vex_encoding_error
;
12580 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12581 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12582 && flag_code
!= CODE_64BIT
)
12585 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12592 /* REG_STRING starts *before* REGISTER_PREFIX. */
12594 static const reg_entry
*
12595 parse_real_register (char *reg_string
, char **end_op
)
12597 char *s
= reg_string
;
12599 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12600 const reg_entry
*r
;
12602 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12603 if (*s
== REGISTER_PREFIX
)
12606 if (is_space_char (*s
))
12609 p
= reg_name_given
;
12610 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12612 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12613 return (const reg_entry
*) NULL
;
12617 /* For naked regs, make sure that we are not dealing with an identifier.
12618 This prevents confusing an identifier like `eax_var' with register
12620 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12621 return (const reg_entry
*) NULL
;
12625 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12627 /* Handle floating point regs, allowing spaces in the (i) part. */
12628 if (r
== i386_regtab
/* %st is first entry of table */)
12630 if (!cpu_arch_flags
.bitfield
.cpu8087
12631 && !cpu_arch_flags
.bitfield
.cpu287
12632 && !cpu_arch_flags
.bitfield
.cpu387
12633 && !allow_pseudo_reg
)
12634 return (const reg_entry
*) NULL
;
12636 if (is_space_char (*s
))
12641 if (is_space_char (*s
))
12643 if (*s
>= '0' && *s
<= '7')
12645 int fpr
= *s
- '0';
12647 if (is_space_char (*s
))
12652 r
= (const reg_entry
*) str_hash_find (reg_hash
, "st(0)");
12657 /* We have "%st(" then garbage. */
12658 return (const reg_entry
*) NULL
;
12662 return r
&& check_register (r
) ? r
: NULL
;
12665 /* REG_STRING starts *before* REGISTER_PREFIX. */
12667 static const reg_entry
*
12668 parse_register (char *reg_string
, char **end_op
)
12670 const reg_entry
*r
;
12672 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12673 r
= parse_real_register (reg_string
, end_op
);
12678 char *save
= input_line_pointer
;
12682 input_line_pointer
= reg_string
;
12683 c
= get_symbol_name (®_string
);
12684 symbolP
= symbol_find (reg_string
);
12685 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12687 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12689 know (e
->X_op
== O_register
);
12690 know (e
->X_add_number
>= 0
12691 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12692 r
= i386_regtab
+ e
->X_add_number
;
12693 if (!check_register (r
))
12695 as_bad (_("register '%s%s' cannot be used here"),
12696 register_prefix
, r
->reg_name
);
12699 *end_op
= input_line_pointer
;
12701 *input_line_pointer
= c
;
12702 input_line_pointer
= save
;
12708 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12710 const reg_entry
*r
;
12711 char *end
= input_line_pointer
;
12714 r
= parse_register (name
, &input_line_pointer
);
12715 if (r
&& end
<= input_line_pointer
)
12717 *nextcharP
= *input_line_pointer
;
12718 *input_line_pointer
= 0;
12721 e
->X_op
= O_register
;
12722 e
->X_add_number
= r
- i386_regtab
;
12725 e
->X_op
= O_illegal
;
12728 input_line_pointer
= end
;
12730 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12734 md_operand (expressionS
*e
)
12737 const reg_entry
*r
;
12739 switch (*input_line_pointer
)
12741 case REGISTER_PREFIX
:
12742 r
= parse_real_register (input_line_pointer
, &end
);
12745 e
->X_op
= O_register
;
12746 e
->X_add_number
= r
- i386_regtab
;
12747 input_line_pointer
= end
;
12752 gas_assert (intel_syntax
);
12753 end
= input_line_pointer
++;
12755 if (*input_line_pointer
== ']')
12757 ++input_line_pointer
;
12758 e
->X_op_symbol
= make_expr_symbol (e
);
12759 e
->X_add_symbol
= NULL
;
12760 e
->X_add_number
= 0;
12765 e
->X_op
= O_absent
;
12766 input_line_pointer
= end
;
12773 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12774 const char *md_shortopts
= "kVQ:sqnO::";
12776 const char *md_shortopts
= "qnO::";
12779 #define OPTION_32 (OPTION_MD_BASE + 0)
12780 #define OPTION_64 (OPTION_MD_BASE + 1)
12781 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12782 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12783 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12784 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12785 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12786 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12787 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12788 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12789 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12790 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12791 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12792 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12793 #define OPTION_X32 (OPTION_MD_BASE + 14)
12794 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12795 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12796 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12797 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12798 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12799 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12800 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12801 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12802 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12803 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12804 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12805 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12806 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12807 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12808 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12809 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12810 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12811 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12812 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12814 struct option md_longopts
[] =
12816 {"32", no_argument
, NULL
, OPTION_32
},
12817 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12818 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12819 {"64", no_argument
, NULL
, OPTION_64
},
12821 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12822 {"x32", no_argument
, NULL
, OPTION_X32
},
12823 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12824 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12826 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12827 {"march", required_argument
, NULL
, OPTION_MARCH
},
12828 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12829 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12830 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12831 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12832 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12833 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12834 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12835 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12836 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12837 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12838 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12839 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12840 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12841 # if defined (TE_PE) || defined (TE_PEP)
12842 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12844 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12845 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12846 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12847 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12848 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12849 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12850 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12851 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12852 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12853 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12854 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12855 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12856 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12857 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12858 {NULL
, no_argument
, NULL
, 0}
12860 size_t md_longopts_size
= sizeof (md_longopts
);
12863 md_parse_option (int c
, const char *arg
)
12866 char *arch
, *next
, *saved
, *type
;
12871 optimize_align_code
= 0;
12875 quiet_warnings
= 1;
12878 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12879 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12880 should be emitted or not. FIXME: Not implemented. */
12882 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12886 /* -V: SVR4 argument to print version ID. */
12888 print_version_id ();
12891 /* -k: Ignore for FreeBSD compatibility. */
12896 /* -s: On i386 Solaris, this tells the native assembler to use
12897 .stab instead of .stab.excl. We always use .stab anyhow. */
12900 case OPTION_MSHARED
:
12904 case OPTION_X86_USED_NOTE
:
12905 if (strcasecmp (arg
, "yes") == 0)
12907 else if (strcasecmp (arg
, "no") == 0)
12910 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12915 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12916 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12919 const char **list
, **l
;
12921 list
= bfd_target_list ();
12922 for (l
= list
; *l
!= NULL
; l
++)
12923 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12924 || strcmp (*l
, "coff-x86-64") == 0
12925 || strcmp (*l
, "pe-x86-64") == 0
12926 || strcmp (*l
, "pei-x86-64") == 0
12927 || strcmp (*l
, "mach-o-x86-64") == 0)
12929 default_arch
= "x86_64";
12933 as_fatal (_("no compiled in support for x86_64"));
12939 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12943 const char **list
, **l
;
12945 list
= bfd_target_list ();
12946 for (l
= list
; *l
!= NULL
; l
++)
12947 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12949 default_arch
= "x86_64:32";
12953 as_fatal (_("no compiled in support for 32bit x86_64"));
12957 as_fatal (_("32bit x86_64 is only supported for ELF"));
12962 default_arch
= "i386";
12965 case OPTION_DIVIDE
:
12966 #ifdef SVR4_COMMENT_CHARS
12971 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12973 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12977 i386_comment_chars
= n
;
12983 saved
= xstrdup (arg
);
12985 /* Allow -march=+nosse. */
12991 as_fatal (_("invalid -march= option: `%s'"), arg
);
12992 next
= strchr (arch
, '+');
12995 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12997 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13000 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13003 cpu_arch_name
= cpu_arch
[j
].name
;
13004 cpu_sub_arch_name
= NULL
;
13005 cpu_arch_flags
= cpu_arch
[j
].flags
;
13006 cpu_arch_isa
= cpu_arch
[j
].type
;
13007 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13008 if (!cpu_arch_tune_set
)
13010 cpu_arch_tune
= cpu_arch_isa
;
13011 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13015 else if (*cpu_arch
[j
].name
== '.'
13016 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13018 /* ISA extension. */
13019 i386_cpu_flags flags
;
13021 flags
= cpu_flags_or (cpu_arch_flags
,
13022 cpu_arch
[j
].flags
);
13024 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13026 if (cpu_sub_arch_name
)
13028 char *name
= cpu_sub_arch_name
;
13029 cpu_sub_arch_name
= concat (name
,
13031 (const char *) NULL
);
13035 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13036 cpu_arch_flags
= flags
;
13037 cpu_arch_isa_flags
= flags
;
13041 = cpu_flags_or (cpu_arch_isa_flags
,
13042 cpu_arch
[j
].flags
);
13047 if (j
>= ARRAY_SIZE (cpu_arch
))
13049 /* Disable an ISA extension. */
13050 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13051 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13053 i386_cpu_flags flags
;
13055 flags
= cpu_flags_and_not (cpu_arch_flags
,
13056 cpu_noarch
[j
].flags
);
13057 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13059 if (cpu_sub_arch_name
)
13061 char *name
= cpu_sub_arch_name
;
13062 cpu_sub_arch_name
= concat (arch
,
13063 (const char *) NULL
);
13067 cpu_sub_arch_name
= xstrdup (arch
);
13068 cpu_arch_flags
= flags
;
13069 cpu_arch_isa_flags
= flags
;
13074 if (j
>= ARRAY_SIZE (cpu_noarch
))
13075 j
= ARRAY_SIZE (cpu_arch
);
13078 if (j
>= ARRAY_SIZE (cpu_arch
))
13079 as_fatal (_("invalid -march= option: `%s'"), arg
);
13083 while (next
!= NULL
);
13089 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13090 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13092 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13094 cpu_arch_tune_set
= 1;
13095 cpu_arch_tune
= cpu_arch
[j
].type
;
13096 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13100 if (j
>= ARRAY_SIZE (cpu_arch
))
13101 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13104 case OPTION_MMNEMONIC
:
13105 if (strcasecmp (arg
, "att") == 0)
13106 intel_mnemonic
= 0;
13107 else if (strcasecmp (arg
, "intel") == 0)
13108 intel_mnemonic
= 1;
13110 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13113 case OPTION_MSYNTAX
:
13114 if (strcasecmp (arg
, "att") == 0)
13116 else if (strcasecmp (arg
, "intel") == 0)
13119 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13122 case OPTION_MINDEX_REG
:
13123 allow_index_reg
= 1;
13126 case OPTION_MNAKED_REG
:
13127 allow_naked_reg
= 1;
13130 case OPTION_MSSE2AVX
:
13134 case OPTION_MSSE_CHECK
:
13135 if (strcasecmp (arg
, "error") == 0)
13136 sse_check
= check_error
;
13137 else if (strcasecmp (arg
, "warning") == 0)
13138 sse_check
= check_warning
;
13139 else if (strcasecmp (arg
, "none") == 0)
13140 sse_check
= check_none
;
13142 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13145 case OPTION_MOPERAND_CHECK
:
13146 if (strcasecmp (arg
, "error") == 0)
13147 operand_check
= check_error
;
13148 else if (strcasecmp (arg
, "warning") == 0)
13149 operand_check
= check_warning
;
13150 else if (strcasecmp (arg
, "none") == 0)
13151 operand_check
= check_none
;
13153 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13156 case OPTION_MAVXSCALAR
:
13157 if (strcasecmp (arg
, "128") == 0)
13158 avxscalar
= vex128
;
13159 else if (strcasecmp (arg
, "256") == 0)
13160 avxscalar
= vex256
;
13162 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13165 case OPTION_MVEXWIG
:
13166 if (strcmp (arg
, "0") == 0)
13168 else if (strcmp (arg
, "1") == 0)
13171 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13174 case OPTION_MADD_BND_PREFIX
:
13175 add_bnd_prefix
= 1;
13178 case OPTION_MEVEXLIG
:
13179 if (strcmp (arg
, "128") == 0)
13180 evexlig
= evexl128
;
13181 else if (strcmp (arg
, "256") == 0)
13182 evexlig
= evexl256
;
13183 else if (strcmp (arg
, "512") == 0)
13184 evexlig
= evexl512
;
13186 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13189 case OPTION_MEVEXRCIG
:
13190 if (strcmp (arg
, "rne") == 0)
13192 else if (strcmp (arg
, "rd") == 0)
13194 else if (strcmp (arg
, "ru") == 0)
13196 else if (strcmp (arg
, "rz") == 0)
13199 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13202 case OPTION_MEVEXWIG
:
13203 if (strcmp (arg
, "0") == 0)
13205 else if (strcmp (arg
, "1") == 0)
13208 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13211 # if defined (TE_PE) || defined (TE_PEP)
13212 case OPTION_MBIG_OBJ
:
13217 case OPTION_MOMIT_LOCK_PREFIX
:
13218 if (strcasecmp (arg
, "yes") == 0)
13219 omit_lock_prefix
= 1;
13220 else if (strcasecmp (arg
, "no") == 0)
13221 omit_lock_prefix
= 0;
13223 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13226 case OPTION_MFENCE_AS_LOCK_ADD
:
13227 if (strcasecmp (arg
, "yes") == 0)
13229 else if (strcasecmp (arg
, "no") == 0)
13232 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13235 case OPTION_MLFENCE_AFTER_LOAD
:
13236 if (strcasecmp (arg
, "yes") == 0)
13237 lfence_after_load
= 1;
13238 else if (strcasecmp (arg
, "no") == 0)
13239 lfence_after_load
= 0;
13241 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13244 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13245 if (strcasecmp (arg
, "all") == 0)
13247 lfence_before_indirect_branch
= lfence_branch_all
;
13248 if (lfence_before_ret
== lfence_before_ret_none
)
13249 lfence_before_ret
= lfence_before_ret_shl
;
13251 else if (strcasecmp (arg
, "memory") == 0)
13252 lfence_before_indirect_branch
= lfence_branch_memory
;
13253 else if (strcasecmp (arg
, "register") == 0)
13254 lfence_before_indirect_branch
= lfence_branch_register
;
13255 else if (strcasecmp (arg
, "none") == 0)
13256 lfence_before_indirect_branch
= lfence_branch_none
;
13258 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13262 case OPTION_MLFENCE_BEFORE_RET
:
13263 if (strcasecmp (arg
, "or") == 0)
13264 lfence_before_ret
= lfence_before_ret_or
;
13265 else if (strcasecmp (arg
, "not") == 0)
13266 lfence_before_ret
= lfence_before_ret_not
;
13267 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13268 lfence_before_ret
= lfence_before_ret_shl
;
13269 else if (strcasecmp (arg
, "none") == 0)
13270 lfence_before_ret
= lfence_before_ret_none
;
13272 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13276 case OPTION_MRELAX_RELOCATIONS
:
13277 if (strcasecmp (arg
, "yes") == 0)
13278 generate_relax_relocations
= 1;
13279 else if (strcasecmp (arg
, "no") == 0)
13280 generate_relax_relocations
= 0;
13282 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13285 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13288 long int align
= strtoul (arg
, &end
, 0);
13293 align_branch_power
= 0;
13296 else if (align
>= 16)
13299 for (align_power
= 0;
13301 align
>>= 1, align_power
++)
13303 /* Limit alignment power to 31. */
13304 if (align
== 1 && align_power
< 32)
13306 align_branch_power
= align_power
;
13311 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13315 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13318 int align
= strtoul (arg
, &end
, 0);
13319 /* Some processors only support 5 prefixes. */
13320 if (*end
== '\0' && align
>= 0 && align
< 6)
13322 align_branch_prefix_size
= align
;
13325 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13330 case OPTION_MALIGN_BRANCH
:
13332 saved
= xstrdup (arg
);
13336 next
= strchr (type
, '+');
13339 if (strcasecmp (type
, "jcc") == 0)
13340 align_branch
|= align_branch_jcc_bit
;
13341 else if (strcasecmp (type
, "fused") == 0)
13342 align_branch
|= align_branch_fused_bit
;
13343 else if (strcasecmp (type
, "jmp") == 0)
13344 align_branch
|= align_branch_jmp_bit
;
13345 else if (strcasecmp (type
, "call") == 0)
13346 align_branch
|= align_branch_call_bit
;
13347 else if (strcasecmp (type
, "ret") == 0)
13348 align_branch
|= align_branch_ret_bit
;
13349 else if (strcasecmp (type
, "indirect") == 0)
13350 align_branch
|= align_branch_indirect_bit
;
13352 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13355 while (next
!= NULL
);
13359 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13360 align_branch_power
= 5;
13361 align_branch_prefix_size
= 5;
13362 align_branch
= (align_branch_jcc_bit
13363 | align_branch_fused_bit
13364 | align_branch_jmp_bit
);
13367 case OPTION_MAMD64
:
13371 case OPTION_MINTEL64
:
13379 /* Turn off -Os. */
13380 optimize_for_space
= 0;
13382 else if (*arg
== 's')
13384 optimize_for_space
= 1;
13385 /* Turn on all encoding optimizations. */
13386 optimize
= INT_MAX
;
13390 optimize
= atoi (arg
);
13391 /* Turn off -Os. */
13392 optimize_for_space
= 0;
13402 #define MESSAGE_TEMPLATE \
13406 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13407 int *left_p
, const char *name
, int len
)
13409 int size
= sizeof (MESSAGE_TEMPLATE
);
13410 int left
= *left_p
;
13412 /* Reserve 2 spaces for ", " or ",\0" */
13415 /* Check if there is any room. */
13423 p
= mempcpy (p
, name
, len
);
13427 /* Output the current message now and start a new one. */
13430 fprintf (stream
, "%s\n", message
);
13432 left
= size
- (start
- message
) - len
- 2;
13434 gas_assert (left
>= 0);
13436 p
= mempcpy (p
, name
, len
);
13444 show_arch (FILE *stream
, int ext
, int check
)
13446 static char message
[] = MESSAGE_TEMPLATE
;
13447 char *start
= message
+ 27;
13449 int size
= sizeof (MESSAGE_TEMPLATE
);
13456 left
= size
- (start
- message
);
13457 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13459 /* Should it be skipped? */
13460 if (cpu_arch
[j
].skip
)
13463 name
= cpu_arch
[j
].name
;
13464 len
= cpu_arch
[j
].len
;
13467 /* It is an extension. Skip if we aren't asked to show it. */
13478 /* It is an processor. Skip if we show only extension. */
13481 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13483 /* It is an impossible processor - skip. */
13487 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13490 /* Display disabled extensions. */
13492 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13494 name
= cpu_noarch
[j
].name
;
13495 len
= cpu_noarch
[j
].len
;
13496 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13501 fprintf (stream
, "%s\n", message
);
13505 md_show_usage (FILE *stream
)
13507 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13508 fprintf (stream
, _("\
13509 -Qy, -Qn ignored\n\
13510 -V print assembler version number\n\
13513 fprintf (stream
, _("\
13514 -n Do not optimize code alignment\n\
13515 -q quieten some warnings\n"));
13516 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13517 fprintf (stream
, _("\
13520 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13521 || defined (TE_PE) || defined (TE_PEP))
13522 fprintf (stream
, _("\
13523 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13525 #ifdef SVR4_COMMENT_CHARS
13526 fprintf (stream
, _("\
13527 --divide do not treat `/' as a comment character\n"));
13529 fprintf (stream
, _("\
13530 --divide ignored\n"));
13532 fprintf (stream
, _("\
13533 -march=CPU[,+EXTENSION...]\n\
13534 generate code for CPU and EXTENSION, CPU is one of:\n"));
13535 show_arch (stream
, 0, 1);
13536 fprintf (stream
, _("\
13537 EXTENSION is combination of:\n"));
13538 show_arch (stream
, 1, 0);
13539 fprintf (stream
, _("\
13540 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13541 show_arch (stream
, 0, 0);
13542 fprintf (stream
, _("\
13543 -msse2avx encode SSE instructions with VEX prefix\n"));
13544 fprintf (stream
, _("\
13545 -msse-check=[none|error|warning] (default: warning)\n\
13546 check SSE instructions\n"));
13547 fprintf (stream
, _("\
13548 -moperand-check=[none|error|warning] (default: warning)\n\
13549 check operand combinations for validity\n"));
13550 fprintf (stream
, _("\
13551 -mavxscalar=[128|256] (default: 128)\n\
13552 encode scalar AVX instructions with specific vector\n\
13554 fprintf (stream
, _("\
13555 -mvexwig=[0|1] (default: 0)\n\
13556 encode VEX instructions with specific VEX.W value\n\
13557 for VEX.W bit ignored instructions\n"));
13558 fprintf (stream
, _("\
13559 -mevexlig=[128|256|512] (default: 128)\n\
13560 encode scalar EVEX instructions with specific vector\n\
13562 fprintf (stream
, _("\
13563 -mevexwig=[0|1] (default: 0)\n\
13564 encode EVEX instructions with specific EVEX.W value\n\
13565 for EVEX.W bit ignored instructions\n"));
13566 fprintf (stream
, _("\
13567 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13568 encode EVEX instructions with specific EVEX.RC value\n\
13569 for SAE-only ignored instructions\n"));
13570 fprintf (stream
, _("\
13571 -mmnemonic=[att|intel] "));
13572 if (SYSV386_COMPAT
)
13573 fprintf (stream
, _("(default: att)\n"));
13575 fprintf (stream
, _("(default: intel)\n"));
13576 fprintf (stream
, _("\
13577 use AT&T/Intel mnemonic\n"));
13578 fprintf (stream
, _("\
13579 -msyntax=[att|intel] (default: att)\n\
13580 use AT&T/Intel syntax\n"));
13581 fprintf (stream
, _("\
13582 -mindex-reg support pseudo index registers\n"));
13583 fprintf (stream
, _("\
13584 -mnaked-reg don't require `%%' prefix for registers\n"));
13585 fprintf (stream
, _("\
13586 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13587 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13588 fprintf (stream
, _("\
13589 -mshared disable branch optimization for shared code\n"));
13590 fprintf (stream
, _("\
13591 -mx86-used-note=[no|yes] "));
13592 if (DEFAULT_X86_USED_NOTE
)
13593 fprintf (stream
, _("(default: yes)\n"));
13595 fprintf (stream
, _("(default: no)\n"));
13596 fprintf (stream
, _("\
13597 generate x86 used ISA and feature properties\n"));
13599 #if defined (TE_PE) || defined (TE_PEP)
13600 fprintf (stream
, _("\
13601 -mbig-obj generate big object files\n"));
13603 fprintf (stream
, _("\
13604 -momit-lock-prefix=[no|yes] (default: no)\n\
13605 strip all lock prefixes\n"));
13606 fprintf (stream
, _("\
13607 -mfence-as-lock-add=[no|yes] (default: no)\n\
13608 encode lfence, mfence and sfence as\n\
13609 lock addl $0x0, (%%{re}sp)\n"));
13610 fprintf (stream
, _("\
13611 -mrelax-relocations=[no|yes] "));
13612 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13613 fprintf (stream
, _("(default: yes)\n"));
13615 fprintf (stream
, _("(default: no)\n"));
13616 fprintf (stream
, _("\
13617 generate relax relocations\n"));
13618 fprintf (stream
, _("\
13619 -malign-branch-boundary=NUM (default: 0)\n\
13620 align branches within NUM byte boundary\n"));
13621 fprintf (stream
, _("\
13622 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13623 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13625 specify types of branches to align\n"));
13626 fprintf (stream
, _("\
13627 -malign-branch-prefix-size=NUM (default: 5)\n\
13628 align branches with NUM prefixes per instruction\n"));
13629 fprintf (stream
, _("\
13630 -mbranches-within-32B-boundaries\n\
13631 align branches within 32 byte boundary\n"));
13632 fprintf (stream
, _("\
13633 -mlfence-after-load=[no|yes] (default: no)\n\
13634 generate lfence after load\n"));
13635 fprintf (stream
, _("\
13636 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13637 generate lfence before indirect near branch\n"));
13638 fprintf (stream
, _("\
13639 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13640 generate lfence before ret\n"));
13641 fprintf (stream
, _("\
13642 -mamd64 accept only AMD64 ISA [default]\n"));
13643 fprintf (stream
, _("\
13644 -mintel64 accept only Intel64 ISA\n"));
13647 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13648 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13649 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13651 /* Pick the target format to use. */
13654 i386_target_format (void)
13656 if (!strncmp (default_arch
, "x86_64", 6))
13658 update_code_flag (CODE_64BIT
, 1);
13659 if (default_arch
[6] == '\0')
13660 x86_elf_abi
= X86_64_ABI
;
13662 x86_elf_abi
= X86_64_X32_ABI
;
13664 else if (!strcmp (default_arch
, "i386"))
13665 update_code_flag (CODE_32BIT
, 1);
13666 else if (!strcmp (default_arch
, "iamcu"))
13668 update_code_flag (CODE_32BIT
, 1);
13669 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13671 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13672 cpu_arch_name
= "iamcu";
13673 cpu_sub_arch_name
= NULL
;
13674 cpu_arch_flags
= iamcu_flags
;
13675 cpu_arch_isa
= PROCESSOR_IAMCU
;
13676 cpu_arch_isa_flags
= iamcu_flags
;
13677 if (!cpu_arch_tune_set
)
13679 cpu_arch_tune
= cpu_arch_isa
;
13680 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13683 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13684 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13688 as_fatal (_("unknown architecture"));
13690 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13691 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13692 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13693 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13695 switch (OUTPUT_FLAVOR
)
13697 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13698 case bfd_target_aout_flavour
:
13699 return AOUT_TARGET_FORMAT
;
13701 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13702 # if defined (TE_PE) || defined (TE_PEP)
13703 case bfd_target_coff_flavour
:
13704 if (flag_code
== CODE_64BIT
)
13705 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13707 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13708 # elif defined (TE_GO32)
13709 case bfd_target_coff_flavour
:
13710 return "coff-go32";
13712 case bfd_target_coff_flavour
:
13713 return "coff-i386";
13716 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13717 case bfd_target_elf_flavour
:
13719 const char *format
;
13721 switch (x86_elf_abi
)
13724 format
= ELF_TARGET_FORMAT
;
13726 tls_get_addr
= "___tls_get_addr";
13730 use_rela_relocations
= 1;
13733 tls_get_addr
= "__tls_get_addr";
13735 format
= ELF_TARGET_FORMAT64
;
13737 case X86_64_X32_ABI
:
13738 use_rela_relocations
= 1;
13741 tls_get_addr
= "__tls_get_addr";
13743 disallow_64bit_reloc
= 1;
13744 format
= ELF_TARGET_FORMAT32
;
13747 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13749 if (x86_elf_abi
!= X86_64_ABI
)
13750 as_fatal (_("Intel L1OM is 64bit only"));
13751 return ELF_TARGET_L1OM_FORMAT
;
13753 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13755 if (x86_elf_abi
!= X86_64_ABI
)
13756 as_fatal (_("Intel K1OM is 64bit only"));
13757 return ELF_TARGET_K1OM_FORMAT
;
13759 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13761 if (x86_elf_abi
!= I386_ABI
)
13762 as_fatal (_("Intel MCU is 32bit only"));
13763 return ELF_TARGET_IAMCU_FORMAT
;
13769 #if defined (OBJ_MACH_O)
13770 case bfd_target_mach_o_flavour
:
13771 if (flag_code
== CODE_64BIT
)
13773 use_rela_relocations
= 1;
13775 return "mach-o-x86-64";
13778 return "mach-o-i386";
13786 #endif /* OBJ_MAYBE_ more than one */
13789 md_undefined_symbol (char *name
)
13791 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13792 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13793 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13794 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13798 if (symbol_find (name
))
13799 as_bad (_("GOT already in symbol table"));
13800 GOT_symbol
= symbol_new (name
, undefined_section
,
13801 &zero_address_frag
, 0);
13808 /* Round up a section size to the appropriate boundary. */
13811 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13813 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13814 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13816 /* For a.out, force the section size to be aligned. If we don't do
13817 this, BFD will align it for us, but it will not write out the
13818 final bytes of the section. This may be a bug in BFD, but it is
13819 easier to fix it here since that is how the other a.out targets
13823 align
= bfd_section_alignment (segment
);
13824 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13831 /* On the i386, PC-relative offsets are relative to the start of the
13832 next instruction. That is, the address of the offset, plus its
13833 size, since the offset is always the last part of the insn. */
13836 md_pcrel_from (fixS
*fixP
)
13838 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13844 s_bss (int ignore ATTRIBUTE_UNUSED
)
13848 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13850 obj_elf_section_change_hook ();
13852 temp
= get_absolute_expression ();
13853 subseg_set (bss_section
, (subsegT
) temp
);
13854 demand_empty_rest_of_line ();
13859 /* Remember constant directive. */
13862 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13864 if (last_insn
.kind
!= last_insn_directive
13865 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13867 last_insn
.seg
= now_seg
;
13868 last_insn
.kind
= last_insn_directive
;
13869 last_insn
.name
= "constant directive";
13870 last_insn
.file
= as_where (&last_insn
.line
);
13871 if (lfence_before_ret
!= lfence_before_ret_none
)
13873 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13874 as_warn (_("constant directive skips -mlfence-before-ret "
13875 "and -mlfence-before-indirect-branch"));
13877 as_warn (_("constant directive skips -mlfence-before-ret"));
13879 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13880 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13885 i386_validate_fix (fixS
*fixp
)
13887 if (fixp
->fx_subsy
)
13889 if (fixp
->fx_subsy
== GOT_symbol
)
13891 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13895 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13896 if (fixp
->fx_tcbit2
)
13897 fixp
->fx_r_type
= (fixp
->fx_tcbit
13898 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13899 : BFD_RELOC_X86_64_GOTPCRELX
);
13902 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13907 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13909 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13911 fixp
->fx_subsy
= 0;
13914 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13917 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
13918 to section. Since PLT32 relocation must be against symbols,
13919 turn such PLT32 relocation into PC32 relocation. */
13921 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
13922 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
13923 && symbol_section_p (fixp
->fx_addsy
))
13924 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
13927 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13928 && fixp
->fx_tcbit2
)
13929 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13936 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13939 bfd_reloc_code_real_type code
;
13941 switch (fixp
->fx_r_type
)
13943 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13944 case BFD_RELOC_SIZE32
:
13945 case BFD_RELOC_SIZE64
:
13946 if (S_IS_DEFINED (fixp
->fx_addsy
)
13947 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13949 /* Resolve size relocation against local symbol to size of
13950 the symbol plus addend. */
13951 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13952 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13953 && !fits_in_unsigned_long (value
))
13954 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13955 _("symbol size computation overflow"));
13956 fixp
->fx_addsy
= NULL
;
13957 fixp
->fx_subsy
= NULL
;
13958 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13962 /* Fall through. */
13964 case BFD_RELOC_X86_64_PLT32
:
13965 case BFD_RELOC_X86_64_GOT32
:
13966 case BFD_RELOC_X86_64_GOTPCREL
:
13967 case BFD_RELOC_X86_64_GOTPCRELX
:
13968 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13969 case BFD_RELOC_386_PLT32
:
13970 case BFD_RELOC_386_GOT32
:
13971 case BFD_RELOC_386_GOT32X
:
13972 case BFD_RELOC_386_GOTOFF
:
13973 case BFD_RELOC_386_GOTPC
:
13974 case BFD_RELOC_386_TLS_GD
:
13975 case BFD_RELOC_386_TLS_LDM
:
13976 case BFD_RELOC_386_TLS_LDO_32
:
13977 case BFD_RELOC_386_TLS_IE_32
:
13978 case BFD_RELOC_386_TLS_IE
:
13979 case BFD_RELOC_386_TLS_GOTIE
:
13980 case BFD_RELOC_386_TLS_LE_32
:
13981 case BFD_RELOC_386_TLS_LE
:
13982 case BFD_RELOC_386_TLS_GOTDESC
:
13983 case BFD_RELOC_386_TLS_DESC_CALL
:
13984 case BFD_RELOC_X86_64_TLSGD
:
13985 case BFD_RELOC_X86_64_TLSLD
:
13986 case BFD_RELOC_X86_64_DTPOFF32
:
13987 case BFD_RELOC_X86_64_DTPOFF64
:
13988 case BFD_RELOC_X86_64_GOTTPOFF
:
13989 case BFD_RELOC_X86_64_TPOFF32
:
13990 case BFD_RELOC_X86_64_TPOFF64
:
13991 case BFD_RELOC_X86_64_GOTOFF64
:
13992 case BFD_RELOC_X86_64_GOTPC32
:
13993 case BFD_RELOC_X86_64_GOT64
:
13994 case BFD_RELOC_X86_64_GOTPCREL64
:
13995 case BFD_RELOC_X86_64_GOTPC64
:
13996 case BFD_RELOC_X86_64_GOTPLT64
:
13997 case BFD_RELOC_X86_64_PLTOFF64
:
13998 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13999 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14000 case BFD_RELOC_RVA
:
14001 case BFD_RELOC_VTABLE_ENTRY
:
14002 case BFD_RELOC_VTABLE_INHERIT
:
14004 case BFD_RELOC_32_SECREL
:
14006 code
= fixp
->fx_r_type
;
14008 case BFD_RELOC_X86_64_32S
:
14009 if (!fixp
->fx_pcrel
)
14011 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14012 code
= fixp
->fx_r_type
;
14015 /* Fall through. */
14017 if (fixp
->fx_pcrel
)
14019 switch (fixp
->fx_size
)
14022 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14023 _("can not do %d byte pc-relative relocation"),
14025 code
= BFD_RELOC_32_PCREL
;
14027 case 1: code
= BFD_RELOC_8_PCREL
; break;
14028 case 2: code
= BFD_RELOC_16_PCREL
; break;
14029 case 4: code
= BFD_RELOC_32_PCREL
; break;
14031 case 8: code
= BFD_RELOC_64_PCREL
; break;
14037 switch (fixp
->fx_size
)
14040 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14041 _("can not do %d byte relocation"),
14043 code
= BFD_RELOC_32
;
14045 case 1: code
= BFD_RELOC_8
; break;
14046 case 2: code
= BFD_RELOC_16
; break;
14047 case 4: code
= BFD_RELOC_32
; break;
14049 case 8: code
= BFD_RELOC_64
; break;
14056 if ((code
== BFD_RELOC_32
14057 || code
== BFD_RELOC_32_PCREL
14058 || code
== BFD_RELOC_X86_64_32S
)
14060 && fixp
->fx_addsy
== GOT_symbol
)
14063 code
= BFD_RELOC_386_GOTPC
;
14065 code
= BFD_RELOC_X86_64_GOTPC32
;
14067 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14069 && fixp
->fx_addsy
== GOT_symbol
)
14071 code
= BFD_RELOC_X86_64_GOTPC64
;
14074 rel
= XNEW (arelent
);
14075 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14076 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14078 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14080 if (!use_rela_relocations
)
14082 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14083 vtable entry to be used in the relocation's section offset. */
14084 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14085 rel
->address
= fixp
->fx_offset
;
14086 #if defined (OBJ_COFF) && defined (TE_PE)
14087 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14088 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14093 /* Use the rela in 64bit mode. */
14096 if (disallow_64bit_reloc
)
14099 case BFD_RELOC_X86_64_DTPOFF64
:
14100 case BFD_RELOC_X86_64_TPOFF64
:
14101 case BFD_RELOC_64_PCREL
:
14102 case BFD_RELOC_X86_64_GOTOFF64
:
14103 case BFD_RELOC_X86_64_GOT64
:
14104 case BFD_RELOC_X86_64_GOTPCREL64
:
14105 case BFD_RELOC_X86_64_GOTPC64
:
14106 case BFD_RELOC_X86_64_GOTPLT64
:
14107 case BFD_RELOC_X86_64_PLTOFF64
:
14108 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14109 _("cannot represent relocation type %s in x32 mode"),
14110 bfd_get_reloc_code_name (code
));
14116 if (!fixp
->fx_pcrel
)
14117 rel
->addend
= fixp
->fx_offset
;
14121 case BFD_RELOC_X86_64_PLT32
:
14122 case BFD_RELOC_X86_64_GOT32
:
14123 case BFD_RELOC_X86_64_GOTPCREL
:
14124 case BFD_RELOC_X86_64_GOTPCRELX
:
14125 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14126 case BFD_RELOC_X86_64_TLSGD
:
14127 case BFD_RELOC_X86_64_TLSLD
:
14128 case BFD_RELOC_X86_64_GOTTPOFF
:
14129 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14130 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14131 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14134 rel
->addend
= (section
->vma
14136 + fixp
->fx_addnumber
14137 + md_pcrel_from (fixp
));
14142 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14143 if (rel
->howto
== NULL
)
14145 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14146 _("cannot represent relocation type %s"),
14147 bfd_get_reloc_code_name (code
));
14148 /* Set howto to a garbage value so that we can keep going. */
14149 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14150 gas_assert (rel
->howto
!= NULL
);
14156 #include "tc-i386-intel.c"
14159 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14161 int saved_naked_reg
;
14162 char saved_register_dot
;
14164 saved_naked_reg
= allow_naked_reg
;
14165 allow_naked_reg
= 1;
14166 saved_register_dot
= register_chars
['.'];
14167 register_chars
['.'] = '.';
14168 allow_pseudo_reg
= 1;
14169 expression_and_evaluate (exp
);
14170 allow_pseudo_reg
= 0;
14171 register_chars
['.'] = saved_register_dot
;
14172 allow_naked_reg
= saved_naked_reg
;
14174 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14176 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14178 exp
->X_op
= O_constant
;
14179 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14180 .dw2_regnum
[flag_code
>> 1];
14183 exp
->X_op
= O_illegal
;
14188 tc_x86_frame_initial_instructions (void)
14190 static unsigned int sp_regno
[2];
14192 if (!sp_regno
[flag_code
>> 1])
14194 char *saved_input
= input_line_pointer
;
14195 char sp
[][4] = {"esp", "rsp"};
14198 input_line_pointer
= sp
[flag_code
>> 1];
14199 tc_x86_parse_to_dw2regnum (&exp
);
14200 gas_assert (exp
.X_op
== O_constant
);
14201 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14202 input_line_pointer
= saved_input
;
14205 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14206 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14210 x86_dwarf2_addr_size (void)
14212 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14213 if (x86_elf_abi
== X86_64_X32_ABI
)
14216 return bfd_arch_bits_per_address (stdoutput
) / 8;
14220 i386_elf_section_type (const char *str
, size_t len
)
14222 if (flag_code
== CODE_64BIT
14223 && len
== sizeof ("unwind") - 1
14224 && strncmp (str
, "unwind", 6) == 0)
14225 return SHT_X86_64_UNWIND
;
14232 i386_solaris_fix_up_eh_frame (segT sec
)
14234 if (flag_code
== CODE_64BIT
)
14235 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14241 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14245 exp
.X_op
= O_secrel
;
14246 exp
.X_add_symbol
= symbol
;
14247 exp
.X_add_number
= 0;
14248 emit_expr (&exp
, size
);
14252 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14253 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14256 x86_64_section_letter (int letter
, const char **ptr_msg
)
14258 if (flag_code
== CODE_64BIT
)
14261 return SHF_X86_64_LARGE
;
14263 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14266 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14271 x86_64_section_word (char *str
, size_t len
)
14273 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14274 return SHF_X86_64_LARGE
;
14280 handle_large_common (int small ATTRIBUTE_UNUSED
)
14282 if (flag_code
!= CODE_64BIT
)
14284 s_comm_internal (0, elf_common_parse
);
14285 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14289 static segT lbss_section
;
14290 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14291 asection
*saved_bss_section
= bss_section
;
14293 if (lbss_section
== NULL
)
14295 flagword applicable
;
14296 segT seg
= now_seg
;
14297 subsegT subseg
= now_subseg
;
14299 /* The .lbss section is for local .largecomm symbols. */
14300 lbss_section
= subseg_new (".lbss", 0);
14301 applicable
= bfd_applicable_section_flags (stdoutput
);
14302 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14303 seg_info (lbss_section
)->bss
= 1;
14305 subseg_set (seg
, subseg
);
14308 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14309 bss_section
= lbss_section
;
14311 s_comm_internal (0, elf_common_parse
);
14313 elf_com_section_ptr
= saved_com_section_ptr
;
14314 bss_section
= saved_bss_section
;
14317 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */