1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
293 invalid_vsib_address
,
294 invalid_vector_register_set
,
295 unsupported_vector_index_register
,
296 unsupported_broadcast
,
299 mask_not_on_destination
,
302 rc_sae_operand_not_last_imm
,
303 invalid_register_operand
,
308 /* TM holds the template for the insn were currently assembling. */
311 /* SUFFIX holds the instruction size suffix for byte, word, dword
312 or qword, if given. */
315 /* OPERANDS gives the number of given operands. */
316 unsigned int operands
;
318 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
319 of given register, displacement, memory operands and immediate
321 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
323 /* TYPES [i] is the type (see above #defines) which tells us how to
324 use OP[i] for the corresponding operand. */
325 i386_operand_type types
[MAX_OPERANDS
];
327 /* Displacement expression, immediate expression, or register for each
329 union i386_op op
[MAX_OPERANDS
];
331 /* Flags for operands. */
332 unsigned int flags
[MAX_OPERANDS
];
333 #define Operand_PCrel 1
334 #define Operand_Mem 2
336 /* Relocation type for operand */
337 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
339 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
340 the base index byte below. */
341 const reg_entry
*base_reg
;
342 const reg_entry
*index_reg
;
343 unsigned int log2_scale_factor
;
345 /* SEG gives the seg_entries of this insn. They are zero unless
346 explicit segment overrides are given. */
347 const seg_entry
*seg
[2];
349 /* Copied first memory operand string, for re-checking. */
352 /* PREFIX holds all the given prefix opcodes (usually null).
353 PREFIXES is the number of prefix opcodes. */
354 unsigned int prefixes
;
355 unsigned char prefix
[MAX_PREFIXES
];
357 /* Register is in low 3 bits of opcode. */
358 bfd_boolean short_form
;
360 /* The operand to a branch insn indicates an absolute branch. */
361 bfd_boolean jumpabsolute
;
363 /* Has MMX register operands. */
364 bfd_boolean has_regmmx
;
366 /* Has XMM register operands. */
367 bfd_boolean has_regxmm
;
369 /* Has YMM register operands. */
370 bfd_boolean has_regymm
;
372 /* Has ZMM register operands. */
373 bfd_boolean has_regzmm
;
375 /* Has GOTPC or TLS relocation. */
376 bfd_boolean has_gotpc_tls_reloc
;
378 /* RM and SIB are the modrm byte and the sib byte where the
379 addressing modes of this insn are encoded. */
386 /* Masking attributes. */
387 struct Mask_Operation
*mask
;
389 /* Rounding control and SAE attributes. */
390 struct RC_Operation
*rounding
;
392 /* Broadcasting attributes. */
393 struct Broadcast_Operation
*broadcast
;
395 /* Compressed disp8*N attribute. */
396 unsigned int memshift
;
398 /* Prefer load or store in encoding. */
401 dir_encoding_default
= 0,
407 /* Prefer 8bit or 32bit displacement in encoding. */
410 disp_encoding_default
= 0,
415 /* Prefer the REX byte in encoding. */
416 bfd_boolean rex_encoding
;
418 /* Disable instruction size optimization. */
419 bfd_boolean no_optimize
;
421 /* How to encode vector instructions. */
424 vex_encoding_default
= 0,
432 const char *rep_prefix
;
435 const char *hle_prefix
;
437 /* Have BND prefix. */
438 const char *bnd_prefix
;
440 /* Have NOTRACK prefix. */
441 const char *notrack_prefix
;
444 enum i386_error error
;
447 typedef struct _i386_insn i386_insn
;
449 /* Link RC type with corresponding string, that'll be looked for in
458 static const struct RC_name RC_NamesTable
[] =
460 { rne
, STRING_COMMA_LEN ("rn-sae") },
461 { rd
, STRING_COMMA_LEN ("rd-sae") },
462 { ru
, STRING_COMMA_LEN ("ru-sae") },
463 { rz
, STRING_COMMA_LEN ("rz-sae") },
464 { saeonly
, STRING_COMMA_LEN ("sae") },
467 /* List of chars besides those in app.c:symbol_chars that can start an
468 operand. Used to prevent the scrubber eating vital white-space. */
469 const char extra_symbol_chars
[] = "*%-([{}"
478 #if (defined (TE_I386AIX) \
479 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
480 && !defined (TE_GNU) \
481 && !defined (TE_LINUX) \
482 && !defined (TE_FreeBSD) \
483 && !defined (TE_DragonFly) \
484 && !defined (TE_NetBSD)))
485 /* This array holds the chars that always start a comment. If the
486 pre-processor is disabled, these aren't very useful. The option
487 --divide will remove '/' from this list. */
488 const char *i386_comment_chars
= "#/";
489 #define SVR4_COMMENT_CHARS 1
490 #define PREFIX_SEPARATOR '\\'
493 const char *i386_comment_chars
= "#";
494 #define PREFIX_SEPARATOR '/'
497 /* This array holds the chars that only start a comment at the beginning of
498 a line. If the line seems to have the form '# 123 filename'
499 .line and .file directives will appear in the pre-processed output.
500 Note that input_file.c hand checks for '#' at the beginning of the
501 first line of the input file. This is because the compiler outputs
502 #NO_APP at the beginning of its output.
503 Also note that comments started like this one will always work if
504 '/' isn't otherwise defined. */
505 const char line_comment_chars
[] = "#/";
507 const char line_separator_chars
[] = ";";
509 /* Chars that can be used to separate mant from exp in floating point
511 const char EXP_CHARS
[] = "eE";
513 /* Chars that mean this number is a floating point constant
516 const char FLT_CHARS
[] = "fFdDxX";
518 /* Tables for lexical analysis. */
519 static char mnemonic_chars
[256];
520 static char register_chars
[256];
521 static char operand_chars
[256];
522 static char identifier_chars
[256];
523 static char digit_chars
[256];
525 /* Lexical macros. */
526 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
527 #define is_operand_char(x) (operand_chars[(unsigned char) x])
528 #define is_register_char(x) (register_chars[(unsigned char) x])
529 #define is_space_char(x) ((x) == ' ')
530 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
531 #define is_digit_char(x) (digit_chars[(unsigned char) x])
533 /* All non-digit non-letter characters that may occur in an operand. */
534 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
536 /* md_assemble() always leaves the strings it's passed unaltered. To
537 effect this we maintain a stack of saved characters that we've smashed
538 with '\0's (indicating end of strings for various sub-fields of the
539 assembler instruction). */
540 static char save_stack
[32];
541 static char *save_stack_p
;
542 #define END_STRING_AND_SAVE(s) \
543 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
544 #define RESTORE_END_STRING(s) \
545 do { *(s) = *--save_stack_p; } while (0)
547 /* The instruction we're assembling. */
550 /* Possible templates for current insn. */
551 static const templates
*current_templates
;
553 /* Per instruction expressionS buffers: max displacements & immediates. */
554 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
555 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
557 /* Current operand we are working on. */
558 static int this_operand
= -1;
560 /* We support four different modes. FLAG_CODE variable is used to distinguish
568 static enum flag_code flag_code
;
569 static unsigned int object_64bit
;
570 static unsigned int disallow_64bit_reloc
;
571 static int use_rela_relocations
= 0;
572 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
573 static const char *tls_get_addr
;
575 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
576 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
577 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
579 /* The ELF ABI to use. */
587 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
590 #if defined (TE_PE) || defined (TE_PEP)
591 /* Use big object file format. */
592 static int use_big_obj
= 0;
595 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
596 /* 1 if generating code for a shared library. */
597 static int shared
= 0;
600 /* 1 for intel syntax,
602 static int intel_syntax
= 0;
604 static enum x86_64_isa
606 amd64
= 1, /* AMD64 ISA. */
607 intel64
/* Intel64 ISA. */
610 /* 1 for intel mnemonic,
611 0 if att mnemonic. */
612 static int intel_mnemonic
= !SYSV386_COMPAT
;
614 /* 1 if pseudo registers are permitted. */
615 static int allow_pseudo_reg
= 0;
617 /* 1 if register prefix % not required. */
618 static int allow_naked_reg
= 0;
620 /* 1 if the assembler should add BND prefix for all control-transferring
621 instructions supporting it, even if this prefix wasn't specified
623 static int add_bnd_prefix
= 0;
625 /* 1 if pseudo index register, eiz/riz, is allowed . */
626 static int allow_index_reg
= 0;
628 /* 1 if the assembler should ignore LOCK prefix, even if it was
629 specified explicitly. */
630 static int omit_lock_prefix
= 0;
632 /* 1 if the assembler should encode lfence, mfence, and sfence as
633 "lock addl $0, (%{re}sp)". */
634 static int avoid_fence
= 0;
636 /* 1 if lfence should be inserted after every load. */
637 static int lfence_after_load
= 0;
639 /* Non-zero if lfence should be inserted before indirect branch. */
640 static enum lfence_before_indirect_branch_kind
642 lfence_branch_none
= 0,
643 lfence_branch_register
,
644 lfence_branch_memory
,
647 lfence_before_indirect_branch
;
649 /* Non-zero if lfence should be inserted before ret. */
650 static enum lfence_before_ret_kind
652 lfence_before_ret_none
= 0,
653 lfence_before_ret_not
,
654 lfence_before_ret_or
,
655 lfence_before_ret_shl
659 /* Types of previous instruction is .byte or prefix. */
674 /* 1 if the assembler should generate relax relocations. */
676 static int generate_relax_relocations
677 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
679 static enum check_kind
685 sse_check
, operand_check
= check_warning
;
687 /* Non-zero if branches should be aligned within power of 2 boundary. */
688 static int align_branch_power
= 0;
690 /* Types of branches to align. */
691 enum align_branch_kind
693 align_branch_none
= 0,
694 align_branch_jcc
= 1,
695 align_branch_fused
= 2,
696 align_branch_jmp
= 3,
697 align_branch_call
= 4,
698 align_branch_indirect
= 5,
702 /* Type bits of branches to align. */
703 enum align_branch_bit
705 align_branch_jcc_bit
= 1 << align_branch_jcc
,
706 align_branch_fused_bit
= 1 << align_branch_fused
,
707 align_branch_jmp_bit
= 1 << align_branch_jmp
,
708 align_branch_call_bit
= 1 << align_branch_call
,
709 align_branch_indirect_bit
= 1 << align_branch_indirect
,
710 align_branch_ret_bit
= 1 << align_branch_ret
713 static unsigned int align_branch
= (align_branch_jcc_bit
714 | align_branch_fused_bit
715 | align_branch_jmp_bit
);
717 /* Types of condition jump used by macro-fusion. */
720 mf_jcc_jo
= 0, /* base opcode 0x70 */
721 mf_jcc_jc
, /* base opcode 0x72 */
722 mf_jcc_je
, /* base opcode 0x74 */
723 mf_jcc_jna
, /* base opcode 0x76 */
724 mf_jcc_js
, /* base opcode 0x78 */
725 mf_jcc_jp
, /* base opcode 0x7a */
726 mf_jcc_jl
, /* base opcode 0x7c */
727 mf_jcc_jle
, /* base opcode 0x7e */
730 /* Types of compare flag-modifying insntructions used by macro-fusion. */
733 mf_cmp_test_and
, /* test/cmp */
734 mf_cmp_alu_cmp
, /* add/sub/cmp */
735 mf_cmp_incdec
/* inc/dec */
738 /* The maximum padding size for fused jcc. CMP like instruction can
739 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
741 #define MAX_FUSED_JCC_PADDING_SIZE 20
743 /* The maximum number of prefixes added for an instruction. */
744 static unsigned int align_branch_prefix_size
= 5;
747 1. Clear the REX_W bit with register operand if possible.
748 2. Above plus use 128bit vector instruction to clear the full vector
751 static int optimize
= 0;
754 1. Clear the REX_W bit with register operand if possible.
755 2. Above plus use 128bit vector instruction to clear the full vector
757 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
760 static int optimize_for_space
= 0;
762 /* Register prefix used for error message. */
763 static const char *register_prefix
= "%";
765 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
766 leave, push, and pop instructions so that gcc has the same stack
767 frame as in 32 bit mode. */
768 static char stackop_size
= '\0';
770 /* Non-zero to optimize code alignment. */
771 int optimize_align_code
= 1;
773 /* Non-zero to quieten some warnings. */
774 static int quiet_warnings
= 0;
777 static const char *cpu_arch_name
= NULL
;
778 static char *cpu_sub_arch_name
= NULL
;
780 /* CPU feature flags. */
781 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
783 /* If we have selected a cpu we are generating instructions for. */
784 static int cpu_arch_tune_set
= 0;
786 /* Cpu we are generating instructions for. */
787 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
789 /* CPU feature flags of cpu we are generating instructions for. */
790 static i386_cpu_flags cpu_arch_tune_flags
;
792 /* CPU instruction set architecture used. */
793 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
795 /* CPU feature flags of instruction set architecture used. */
796 i386_cpu_flags cpu_arch_isa_flags
;
798 /* If set, conditional jumps are not automatically promoted to handle
799 larger than a byte offset. */
800 static unsigned int no_cond_jump_promotion
= 0;
802 /* Encode SSE instructions with VEX prefix. */
803 static unsigned int sse2avx
;
805 /* Encode scalar AVX instructions with specific vector length. */
812 /* Encode VEX WIG instructions with specific vex.w. */
819 /* Encode scalar EVEX LIG instructions with specific vector length. */
827 /* Encode EVEX WIG instructions with specific evex.w. */
834 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
835 static enum rc_type evexrcig
= rne
;
837 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
838 static symbolS
*GOT_symbol
;
840 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
841 unsigned int x86_dwarf2_return_column
;
843 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
844 int x86_cie_data_alignment
;
846 /* Interface to relax_segment.
847 There are 3 major relax states for 386 jump insns because the
848 different types of jumps add different sizes to frags when we're
849 figuring out what sort of jump to choose to reach a given label.
851 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
852 branches which are handled by md_estimate_size_before_relax() and
853 i386_generic_table_relax_frag(). */
856 #define UNCOND_JUMP 0
858 #define COND_JUMP86 2
859 #define BRANCH_PADDING 3
860 #define BRANCH_PREFIX 4
861 #define FUSED_JCC_PADDING 5
866 #define SMALL16 (SMALL | CODE16)
868 #define BIG16 (BIG | CODE16)
872 #define INLINE __inline__
878 #define ENCODE_RELAX_STATE(type, size) \
879 ((relax_substateT) (((type) << 2) | (size)))
880 #define TYPE_FROM_RELAX_STATE(s) \
882 #define DISP_SIZE_FROM_RELAX_STATE(s) \
883 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
885 /* This table is used by relax_frag to promote short jumps to long
886 ones where necessary. SMALL (short) jumps may be promoted to BIG
887 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
888 don't allow a short jump in a 32 bit code segment to be promoted to
889 a 16 bit offset jump because it's slower (requires data size
890 prefix), and doesn't work, unless the destination is in the bottom
891 64k of the code segment (The top 16 bits of eip are zeroed). */
893 const relax_typeS md_relax_table
[] =
896 1) most positive reach of this state,
897 2) most negative reach of this state,
898 3) how many bytes this mode will have in the variable part of the frag
899 4) which index into the table to try if we can't fit into this one. */
901 /* UNCOND_JUMP states. */
902 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
903 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
904 /* dword jmp adds 4 bytes to frag:
905 0 extra opcode bytes, 4 displacement bytes. */
907 /* word jmp adds 2 byte2 to frag:
908 0 extra opcode bytes, 2 displacement bytes. */
911 /* COND_JUMP states. */
912 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
913 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
914 /* dword conditionals adds 5 bytes to frag:
915 1 extra opcode byte, 4 displacement bytes. */
917 /* word conditionals add 3 bytes to frag:
918 1 extra opcode byte, 2 displacement bytes. */
921 /* COND_JUMP86 states. */
922 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
923 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
924 /* dword conditionals adds 5 bytes to frag:
925 1 extra opcode byte, 4 displacement bytes. */
927 /* word conditionals add 4 bytes to frag:
928 1 displacement byte and a 3 byte long branch insn. */
932 static const arch_entry cpu_arch
[] =
934 /* Do not replace the first two entries - i386_target_format()
935 relies on them being there in this order. */
936 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
937 CPU_GENERIC32_FLAGS
, 0 },
938 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
939 CPU_GENERIC64_FLAGS
, 0 },
940 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
946 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
948 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
950 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
952 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
954 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
956 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
957 CPU_PENTIUMPRO_FLAGS
, 0 },
958 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
960 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
962 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
964 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
966 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
967 CPU_NOCONA_FLAGS
, 0 },
968 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
970 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
972 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
973 CPU_CORE2_FLAGS
, 1 },
974 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
975 CPU_CORE2_FLAGS
, 0 },
976 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
977 CPU_COREI7_FLAGS
, 0 },
978 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
980 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
982 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
983 CPU_IAMCU_FLAGS
, 0 },
984 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
986 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
988 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
989 CPU_ATHLON_FLAGS
, 0 },
990 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
992 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
994 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
996 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
997 CPU_AMDFAM10_FLAGS
, 0 },
998 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
999 CPU_BDVER1_FLAGS
, 0 },
1000 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1001 CPU_BDVER2_FLAGS
, 0 },
1002 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1003 CPU_BDVER3_FLAGS
, 0 },
1004 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1005 CPU_BDVER4_FLAGS
, 0 },
1006 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1007 CPU_ZNVER1_FLAGS
, 0 },
1008 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1009 CPU_ZNVER2_FLAGS
, 0 },
1010 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1011 CPU_BTVER1_FLAGS
, 0 },
1012 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1013 CPU_BTVER2_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1015 CPU_8087_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1022 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1023 CPU_CMOV_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1025 CPU_FXSR_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1031 CPU_SSE2_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1033 CPU_SSE3_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1035 CPU_SSE4A_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1037 CPU_SSSE3_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1039 CPU_SSE4_1_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1041 CPU_SSE4_2_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1043 CPU_SSE4_2_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1046 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1047 CPU_AVX2_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1049 CPU_AVX512F_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1051 CPU_AVX512CD_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1053 CPU_AVX512ER_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1055 CPU_AVX512PF_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1057 CPU_AVX512DQ_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1059 CPU_AVX512BW_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1061 CPU_AVX512VL_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1064 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1065 CPU_VMFUNC_FLAGS
, 0 },
1066 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1068 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1069 CPU_XSAVE_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1071 CPU_XSAVEOPT_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1073 CPU_XSAVEC_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1075 CPU_XSAVES_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1078 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1079 CPU_PCLMUL_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1081 CPU_PCLMUL_FLAGS
, 1 },
1082 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1083 CPU_FSGSBASE_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1085 CPU_RDRND_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1087 CPU_F16C_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1089 CPU_BMI2_FLAGS
, 0 },
1090 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1092 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1093 CPU_FMA4_FLAGS
, 0 },
1094 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1096 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1098 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1099 CPU_MOVBE_FLAGS
, 0 },
1100 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1101 CPU_CX16_FLAGS
, 0 },
1102 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1104 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1105 CPU_LZCNT_FLAGS
, 0 },
1106 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1107 CPU_POPCNT_FLAGS
, 0 },
1108 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1110 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1112 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1113 CPU_INVPCID_FLAGS
, 0 },
1114 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1115 CPU_CLFLUSH_FLAGS
, 0 },
1116 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1118 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1119 CPU_SYSCALL_FLAGS
, 0 },
1120 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1121 CPU_RDTSCP_FLAGS
, 0 },
1122 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1123 CPU_3DNOW_FLAGS
, 0 },
1124 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1125 CPU_3DNOWA_FLAGS
, 0 },
1126 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1127 CPU_PADLOCK_FLAGS
, 0 },
1128 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1129 CPU_SVME_FLAGS
, 1 },
1130 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1131 CPU_SVME_FLAGS
, 0 },
1132 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1133 CPU_SSE4A_FLAGS
, 0 },
1134 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1136 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1138 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1140 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1142 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1143 CPU_RDSEED_FLAGS
, 0 },
1144 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1145 CPU_PRFCHW_FLAGS
, 0 },
1146 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1147 CPU_SMAP_FLAGS
, 0 },
1148 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1150 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1152 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1153 CPU_CLFLUSHOPT_FLAGS
, 0 },
1154 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1155 CPU_PREFETCHWT1_FLAGS
, 0 },
1156 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1158 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1159 CPU_CLWB_FLAGS
, 0 },
1160 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1161 CPU_AVX512IFMA_FLAGS
, 0 },
1162 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1163 CPU_AVX512VBMI_FLAGS
, 0 },
1164 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1165 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1166 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1167 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1168 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1169 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1170 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1171 CPU_AVX512_VBMI2_FLAGS
, 0 },
1172 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1173 CPU_AVX512_VNNI_FLAGS
, 0 },
1174 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1175 CPU_AVX512_BITALG_FLAGS
, 0 },
1176 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1177 CPU_CLZERO_FLAGS
, 0 },
1178 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1179 CPU_MWAITX_FLAGS
, 0 },
1180 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1181 CPU_OSPKE_FLAGS
, 0 },
1182 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1183 CPU_RDPID_FLAGS
, 0 },
1184 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1185 CPU_PTWRITE_FLAGS
, 0 },
1186 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1188 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1189 CPU_SHSTK_FLAGS
, 0 },
1190 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1191 CPU_GFNI_FLAGS
, 0 },
1192 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1193 CPU_VAES_FLAGS
, 0 },
1194 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1195 CPU_VPCLMULQDQ_FLAGS
, 0 },
1196 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1197 CPU_WBNOINVD_FLAGS
, 0 },
1198 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1199 CPU_PCONFIG_FLAGS
, 0 },
1200 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1201 CPU_WAITPKG_FLAGS
, 0 },
1202 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1203 CPU_CLDEMOTE_FLAGS
, 0 },
1204 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1205 CPU_MOVDIRI_FLAGS
, 0 },
1206 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1207 CPU_MOVDIR64B_FLAGS
, 0 },
1208 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1209 CPU_AVX512_BF16_FLAGS
, 0 },
1210 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1211 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1212 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1213 CPU_ENQCMD_FLAGS
, 0 },
1214 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1215 CPU_SERIALIZE_FLAGS
, 0 },
1216 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1217 CPU_RDPRU_FLAGS
, 0 },
1218 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1219 CPU_MCOMMIT_FLAGS
, 0 },
1220 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1221 CPU_SEV_ES_FLAGS
, 0 },
1222 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1223 CPU_TSXLDTRK_FLAGS
, 0 },
1226 static const noarch_entry cpu_noarch
[] =
1228 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1229 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1230 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1231 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1232 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1233 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1234 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1235 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1236 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1237 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1238 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1239 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1240 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1241 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1242 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1243 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1244 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1245 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1246 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1247 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1248 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1249 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1250 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1251 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1252 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1253 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1254 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1255 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1256 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1257 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1258 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1259 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1260 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1261 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1262 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1263 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1264 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1266 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1267 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1268 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1269 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1273 /* Like s_lcomm_internal in gas/read.c but the alignment string
1274 is allowed to be optional. */
1277 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1284 && *input_line_pointer
== ',')
1286 align
= parse_align (needs_align
- 1);
1288 if (align
== (addressT
) -1)
1303 bss_alloc (symbolP
, size
, align
);
1308 pe_lcomm (int needs_align
)
1310 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1314 const pseudo_typeS md_pseudo_table
[] =
1316 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1317 {"align", s_align_bytes
, 0},
1319 {"align", s_align_ptwo
, 0},
1321 {"arch", set_cpu_arch
, 0},
1325 {"lcomm", pe_lcomm
, 1},
1327 {"ffloat", float_cons
, 'f'},
1328 {"dfloat", float_cons
, 'd'},
1329 {"tfloat", float_cons
, 'x'},
1331 {"slong", signed_cons
, 4},
1332 {"noopt", s_ignore
, 0},
1333 {"optim", s_ignore
, 0},
1334 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1335 {"code16", set_code_flag
, CODE_16BIT
},
1336 {"code32", set_code_flag
, CODE_32BIT
},
1338 {"code64", set_code_flag
, CODE_64BIT
},
1340 {"intel_syntax", set_intel_syntax
, 1},
1341 {"att_syntax", set_intel_syntax
, 0},
1342 {"intel_mnemonic", set_intel_mnemonic
, 1},
1343 {"att_mnemonic", set_intel_mnemonic
, 0},
1344 {"allow_index_reg", set_allow_index_reg
, 1},
1345 {"disallow_index_reg", set_allow_index_reg
, 0},
1346 {"sse_check", set_check
, 0},
1347 {"operand_check", set_check
, 1},
1348 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1349 {"largecomm", handle_large_common
, 0},
1351 {"file", dwarf2_directive_file
, 0},
1352 {"loc", dwarf2_directive_loc
, 0},
1353 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1356 {"secrel32", pe_directive_secrel
, 0},
1361 /* For interface with expression (). */
1362 extern char *input_line_pointer
;
1364 /* Hash table for instruction mnemonic lookup. */
1365 static struct hash_control
*op_hash
;
1367 /* Hash table for register lookup. */
1368 static struct hash_control
*reg_hash
;
1370 /* Various efficient no-op patterns for aligning code labels.
1371 Note: Don't try to assemble the instructions in the comments.
1372 0L and 0w are not legal. */
1373 static const unsigned char f32_1
[] =
1375 static const unsigned char f32_2
[] =
1376 {0x66,0x90}; /* xchg %ax,%ax */
1377 static const unsigned char f32_3
[] =
1378 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1379 static const unsigned char f32_4
[] =
1380 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1381 static const unsigned char f32_6
[] =
1382 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1383 static const unsigned char f32_7
[] =
1384 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1385 static const unsigned char f16_3
[] =
1386 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1387 static const unsigned char f16_4
[] =
1388 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1389 static const unsigned char jump_disp8
[] =
1390 {0xeb}; /* jmp disp8 */
1391 static const unsigned char jump32_disp32
[] =
1392 {0xe9}; /* jmp disp32 */
1393 static const unsigned char jump16_disp32
[] =
1394 {0x66,0xe9}; /* jmp disp32 */
1395 /* 32-bit NOPs patterns. */
1396 static const unsigned char *const f32_patt
[] = {
1397 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1399 /* 16-bit NOPs patterns. */
1400 static const unsigned char *const f16_patt
[] = {
1401 f32_1
, f32_2
, f16_3
, f16_4
1403 /* nopl (%[re]ax) */
1404 static const unsigned char alt_3
[] =
1406 /* nopl 0(%[re]ax) */
1407 static const unsigned char alt_4
[] =
1408 {0x0f,0x1f,0x40,0x00};
1409 /* nopl 0(%[re]ax,%[re]ax,1) */
1410 static const unsigned char alt_5
[] =
1411 {0x0f,0x1f,0x44,0x00,0x00};
1412 /* nopw 0(%[re]ax,%[re]ax,1) */
1413 static const unsigned char alt_6
[] =
1414 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1415 /* nopl 0L(%[re]ax) */
1416 static const unsigned char alt_7
[] =
1417 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1418 /* nopl 0L(%[re]ax,%[re]ax,1) */
1419 static const unsigned char alt_8
[] =
1420 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1421 /* nopw 0L(%[re]ax,%[re]ax,1) */
1422 static const unsigned char alt_9
[] =
1423 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1424 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1425 static const unsigned char alt_10
[] =
1426 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1427 /* data16 nopw %cs:0L(%eax,%eax,1) */
1428 static const unsigned char alt_11
[] =
1429 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1430 /* 32-bit and 64-bit NOPs patterns. */
1431 static const unsigned char *const alt_patt
[] = {
1432 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1433 alt_9
, alt_10
, alt_11
1436 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1437 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1440 i386_output_nops (char *where
, const unsigned char *const *patt
,
1441 int count
, int max_single_nop_size
)
1444 /* Place the longer NOP first. */
1447 const unsigned char *nops
;
1449 if (max_single_nop_size
< 1)
1451 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1452 max_single_nop_size
);
1456 nops
= patt
[max_single_nop_size
- 1];
1458 /* Use the smaller one if the requsted one isn't available. */
1461 max_single_nop_size
--;
1462 nops
= patt
[max_single_nop_size
- 1];
1465 last
= count
% max_single_nop_size
;
1468 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1469 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1473 nops
= patt
[last
- 1];
1476 /* Use the smaller one plus one-byte NOP if the needed one
1479 nops
= patt
[last
- 1];
1480 memcpy (where
+ offset
, nops
, last
);
1481 where
[offset
+ last
] = *patt
[0];
1484 memcpy (where
+ offset
, nops
, last
);
1489 fits_in_imm7 (offsetT num
)
1491 return (num
& 0x7f) == num
;
1495 fits_in_imm31 (offsetT num
)
1497 return (num
& 0x7fffffff) == num
;
1500 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1501 single NOP instruction LIMIT. */
1504 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1506 const unsigned char *const *patt
= NULL
;
1507 int max_single_nop_size
;
1508 /* Maximum number of NOPs before switching to jump over NOPs. */
1509 int max_number_of_nops
;
1511 switch (fragP
->fr_type
)
1516 case rs_machine_dependent
:
1517 /* Allow NOP padding for jumps and calls. */
1518 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1519 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1526 /* We need to decide which NOP sequence to use for 32bit and
1527 64bit. When -mtune= is used:
1529 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1530 PROCESSOR_GENERIC32, f32_patt will be used.
1531 2. For the rest, alt_patt will be used.
1533 When -mtune= isn't used, alt_patt will be used if
1534 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1537 When -march= or .arch is used, we can't use anything beyond
1538 cpu_arch_isa_flags. */
1540 if (flag_code
== CODE_16BIT
)
1543 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1544 /* Limit number of NOPs to 2 in 16-bit mode. */
1545 max_number_of_nops
= 2;
1549 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1551 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1552 switch (cpu_arch_tune
)
1554 case PROCESSOR_UNKNOWN
:
1555 /* We use cpu_arch_isa_flags to check if we SHOULD
1556 optimize with nops. */
1557 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1562 case PROCESSOR_PENTIUM4
:
1563 case PROCESSOR_NOCONA
:
1564 case PROCESSOR_CORE
:
1565 case PROCESSOR_CORE2
:
1566 case PROCESSOR_COREI7
:
1567 case PROCESSOR_L1OM
:
1568 case PROCESSOR_K1OM
:
1569 case PROCESSOR_GENERIC64
:
1571 case PROCESSOR_ATHLON
:
1573 case PROCESSOR_AMDFAM10
:
1575 case PROCESSOR_ZNVER
:
1579 case PROCESSOR_I386
:
1580 case PROCESSOR_I486
:
1581 case PROCESSOR_PENTIUM
:
1582 case PROCESSOR_PENTIUMPRO
:
1583 case PROCESSOR_IAMCU
:
1584 case PROCESSOR_GENERIC32
:
1591 switch (fragP
->tc_frag_data
.tune
)
1593 case PROCESSOR_UNKNOWN
:
1594 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1595 PROCESSOR_UNKNOWN. */
1599 case PROCESSOR_I386
:
1600 case PROCESSOR_I486
:
1601 case PROCESSOR_PENTIUM
:
1602 case PROCESSOR_IAMCU
:
1604 case PROCESSOR_ATHLON
:
1606 case PROCESSOR_AMDFAM10
:
1608 case PROCESSOR_ZNVER
:
1610 case PROCESSOR_GENERIC32
:
1611 /* We use cpu_arch_isa_flags to check if we CAN optimize
1613 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1618 case PROCESSOR_PENTIUMPRO
:
1619 case PROCESSOR_PENTIUM4
:
1620 case PROCESSOR_NOCONA
:
1621 case PROCESSOR_CORE
:
1622 case PROCESSOR_CORE2
:
1623 case PROCESSOR_COREI7
:
1624 case PROCESSOR_L1OM
:
1625 case PROCESSOR_K1OM
:
1626 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1631 case PROCESSOR_GENERIC64
:
1637 if (patt
== f32_patt
)
1639 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1640 /* Limit number of NOPs to 2 for older processors. */
1641 max_number_of_nops
= 2;
1645 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1646 /* Limit number of NOPs to 7 for newer processors. */
1647 max_number_of_nops
= 7;
1652 limit
= max_single_nop_size
;
1654 if (fragP
->fr_type
== rs_fill_nop
)
1656 /* Output NOPs for .nop directive. */
1657 if (limit
> max_single_nop_size
)
1659 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1660 _("invalid single nop size: %d "
1661 "(expect within [0, %d])"),
1662 limit
, max_single_nop_size
);
1666 else if (fragP
->fr_type
!= rs_machine_dependent
)
1667 fragP
->fr_var
= count
;
1669 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1671 /* Generate jump over NOPs. */
1672 offsetT disp
= count
- 2;
1673 if (fits_in_imm7 (disp
))
1675 /* Use "jmp disp8" if possible. */
1677 where
[0] = jump_disp8
[0];
1683 unsigned int size_of_jump
;
1685 if (flag_code
== CODE_16BIT
)
1687 where
[0] = jump16_disp32
[0];
1688 where
[1] = jump16_disp32
[1];
1693 where
[0] = jump32_disp32
[0];
1697 count
-= size_of_jump
+ 4;
1698 if (!fits_in_imm31 (count
))
1700 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1701 _("jump over nop padding out of range"));
1705 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1706 where
+= size_of_jump
+ 4;
1710 /* Generate multiple NOPs. */
1711 i386_output_nops (where
, patt
, count
, limit
);
1715 operand_type_all_zero (const union i386_operand_type
*x
)
1717 switch (ARRAY_SIZE(x
->array
))
1728 return !x
->array
[0];
1735 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1737 switch (ARRAY_SIZE(x
->array
))
1753 x
->bitfield
.class = ClassNone
;
1754 x
->bitfield
.instance
= InstanceNone
;
1758 operand_type_equal (const union i386_operand_type
*x
,
1759 const union i386_operand_type
*y
)
1761 switch (ARRAY_SIZE(x
->array
))
1764 if (x
->array
[2] != y
->array
[2])
1768 if (x
->array
[1] != y
->array
[1])
1772 return x
->array
[0] == y
->array
[0];
1780 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1782 switch (ARRAY_SIZE(x
->array
))
1797 return !x
->array
[0];
1804 cpu_flags_equal (const union i386_cpu_flags
*x
,
1805 const union i386_cpu_flags
*y
)
1807 switch (ARRAY_SIZE(x
->array
))
1810 if (x
->array
[3] != y
->array
[3])
1814 if (x
->array
[2] != y
->array
[2])
1818 if (x
->array
[1] != y
->array
[1])
1822 return x
->array
[0] == y
->array
[0];
1830 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1832 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1833 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1836 static INLINE i386_cpu_flags
1837 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1839 switch (ARRAY_SIZE (x
.array
))
1842 x
.array
[3] &= y
.array
[3];
1845 x
.array
[2] &= y
.array
[2];
1848 x
.array
[1] &= y
.array
[1];
1851 x
.array
[0] &= y
.array
[0];
1859 static INLINE i386_cpu_flags
1860 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1862 switch (ARRAY_SIZE (x
.array
))
1865 x
.array
[3] |= y
.array
[3];
1868 x
.array
[2] |= y
.array
[2];
1871 x
.array
[1] |= y
.array
[1];
1874 x
.array
[0] |= y
.array
[0];
1882 static INLINE i386_cpu_flags
1883 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1885 switch (ARRAY_SIZE (x
.array
))
1888 x
.array
[3] &= ~y
.array
[3];
1891 x
.array
[2] &= ~y
.array
[2];
1894 x
.array
[1] &= ~y
.array
[1];
1897 x
.array
[0] &= ~y
.array
[0];
1905 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1907 #define CPU_FLAGS_ARCH_MATCH 0x1
1908 #define CPU_FLAGS_64BIT_MATCH 0x2
1910 #define CPU_FLAGS_PERFECT_MATCH \
1911 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1913 /* Return CPU flags match bits. */
1916 cpu_flags_match (const insn_template
*t
)
1918 i386_cpu_flags x
= t
->cpu_flags
;
1919 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1921 x
.bitfield
.cpu64
= 0;
1922 x
.bitfield
.cpuno64
= 0;
1924 if (cpu_flags_all_zero (&x
))
1926 /* This instruction is available on all archs. */
1927 match
|= CPU_FLAGS_ARCH_MATCH
;
1931 /* This instruction is available only on some archs. */
1932 i386_cpu_flags cpu
= cpu_arch_flags
;
1934 /* AVX512VL is no standalone feature - match it and then strip it. */
1935 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1937 x
.bitfield
.cpuavx512vl
= 0;
1939 cpu
= cpu_flags_and (x
, cpu
);
1940 if (!cpu_flags_all_zero (&cpu
))
1942 if (x
.bitfield
.cpuavx
)
1944 /* We need to check a few extra flags with AVX. */
1945 if (cpu
.bitfield
.cpuavx
1946 && (!t
->opcode_modifier
.sse2avx
1947 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1948 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1949 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1950 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1951 match
|= CPU_FLAGS_ARCH_MATCH
;
1953 else if (x
.bitfield
.cpuavx512f
)
1955 /* We need to check a few extra flags with AVX512F. */
1956 if (cpu
.bitfield
.cpuavx512f
1957 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1958 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1959 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1960 match
|= CPU_FLAGS_ARCH_MATCH
;
1963 match
|= CPU_FLAGS_ARCH_MATCH
;
1969 static INLINE i386_operand_type
1970 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1972 if (x
.bitfield
.class != y
.bitfield
.class)
1973 x
.bitfield
.class = ClassNone
;
1974 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1975 x
.bitfield
.instance
= InstanceNone
;
1977 switch (ARRAY_SIZE (x
.array
))
1980 x
.array
[2] &= y
.array
[2];
1983 x
.array
[1] &= y
.array
[1];
1986 x
.array
[0] &= y
.array
[0];
1994 static INLINE i386_operand_type
1995 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1997 gas_assert (y
.bitfield
.class == ClassNone
);
1998 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2000 switch (ARRAY_SIZE (x
.array
))
2003 x
.array
[2] &= ~y
.array
[2];
2006 x
.array
[1] &= ~y
.array
[1];
2009 x
.array
[0] &= ~y
.array
[0];
2017 static INLINE i386_operand_type
2018 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2020 gas_assert (x
.bitfield
.class == ClassNone
||
2021 y
.bitfield
.class == ClassNone
||
2022 x
.bitfield
.class == y
.bitfield
.class);
2023 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2024 y
.bitfield
.instance
== InstanceNone
||
2025 x
.bitfield
.instance
== y
.bitfield
.instance
);
2027 switch (ARRAY_SIZE (x
.array
))
2030 x
.array
[2] |= y
.array
[2];
2033 x
.array
[1] |= y
.array
[1];
2036 x
.array
[0] |= y
.array
[0];
2044 static INLINE i386_operand_type
2045 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2047 gas_assert (y
.bitfield
.class == ClassNone
);
2048 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2050 switch (ARRAY_SIZE (x
.array
))
2053 x
.array
[2] ^= y
.array
[2];
2056 x
.array
[1] ^= y
.array
[1];
2059 x
.array
[0] ^= y
.array
[0];
2067 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2068 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2069 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2070 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2071 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2072 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2073 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2074 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2075 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2076 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2077 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2078 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2079 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2080 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2081 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2082 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2083 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2094 operand_type_check (i386_operand_type t
, enum operand_type c
)
2099 return t
.bitfield
.class == Reg
;
2102 return (t
.bitfield
.imm8
2106 || t
.bitfield
.imm32s
2107 || t
.bitfield
.imm64
);
2110 return (t
.bitfield
.disp8
2111 || t
.bitfield
.disp16
2112 || t
.bitfield
.disp32
2113 || t
.bitfield
.disp32s
2114 || t
.bitfield
.disp64
);
2117 return (t
.bitfield
.disp8
2118 || t
.bitfield
.disp16
2119 || t
.bitfield
.disp32
2120 || t
.bitfield
.disp32s
2121 || t
.bitfield
.disp64
2122 || t
.bitfield
.baseindex
);
2131 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2132 between operand GIVEN and opeand WANTED for instruction template T. */
2135 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2138 return !((i
.types
[given
].bitfield
.byte
2139 && !t
->operand_types
[wanted
].bitfield
.byte
)
2140 || (i
.types
[given
].bitfield
.word
2141 && !t
->operand_types
[wanted
].bitfield
.word
)
2142 || (i
.types
[given
].bitfield
.dword
2143 && !t
->operand_types
[wanted
].bitfield
.dword
)
2144 || (i
.types
[given
].bitfield
.qword
2145 && !t
->operand_types
[wanted
].bitfield
.qword
)
2146 || (i
.types
[given
].bitfield
.tbyte
2147 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2150 /* Return 1 if there is no conflict in SIMD register between operand
2151 GIVEN and opeand WANTED for instruction template T. */
2154 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2157 return !((i
.types
[given
].bitfield
.xmmword
2158 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2159 || (i
.types
[given
].bitfield
.ymmword
2160 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2161 || (i
.types
[given
].bitfield
.zmmword
2162 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2165 /* Return 1 if there is no conflict in any size between operand GIVEN
2166 and opeand WANTED for instruction template T. */
2169 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2172 return (match_operand_size (t
, wanted
, given
)
2173 && !((i
.types
[given
].bitfield
.unspecified
2175 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2176 || (i
.types
[given
].bitfield
.fword
2177 && !t
->operand_types
[wanted
].bitfield
.fword
)
2178 /* For scalar opcode templates to allow register and memory
2179 operands at the same time, some special casing is needed
2180 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2181 down-conversion vpmov*. */
2182 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2183 && t
->operand_types
[wanted
].bitfield
.byte
2184 + t
->operand_types
[wanted
].bitfield
.word
2185 + t
->operand_types
[wanted
].bitfield
.dword
2186 + t
->operand_types
[wanted
].bitfield
.qword
2187 > !!t
->opcode_modifier
.broadcast
)
2188 ? (i
.types
[given
].bitfield
.xmmword
2189 || i
.types
[given
].bitfield
.ymmword
2190 || i
.types
[given
].bitfield
.zmmword
)
2191 : !match_simd_size(t
, wanted
, given
))));
2194 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2195 operands for instruction template T, and it has MATCH_REVERSE set if there
2196 is no size conflict on any operands for the template with operands reversed
2197 (and the template allows for reversing in the first place). */
2199 #define MATCH_STRAIGHT 1
2200 #define MATCH_REVERSE 2
2202 static INLINE
unsigned int
2203 operand_size_match (const insn_template
*t
)
2205 unsigned int j
, match
= MATCH_STRAIGHT
;
2207 /* Don't check non-absolute jump instructions. */
2208 if (t
->opcode_modifier
.jump
2209 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2212 /* Check memory and accumulator operand size. */
2213 for (j
= 0; j
< i
.operands
; j
++)
2215 if (i
.types
[j
].bitfield
.class != Reg
2216 && i
.types
[j
].bitfield
.class != RegSIMD
2217 && t
->opcode_modifier
.anysize
)
2220 if (t
->operand_types
[j
].bitfield
.class == Reg
2221 && !match_operand_size (t
, j
, j
))
2227 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2228 && !match_simd_size (t
, j
, j
))
2234 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2235 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2241 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2248 if (!t
->opcode_modifier
.d
)
2252 i
.error
= operand_size_mismatch
;
2256 /* Check reverse. */
2257 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2259 for (j
= 0; j
< i
.operands
; j
++)
2261 unsigned int given
= i
.operands
- j
- 1;
2263 if (t
->operand_types
[j
].bitfield
.class == Reg
2264 && !match_operand_size (t
, j
, given
))
2267 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2268 && !match_simd_size (t
, j
, given
))
2271 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2272 && (!match_operand_size (t
, j
, given
)
2273 || !match_simd_size (t
, j
, given
)))
2276 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2280 return match
| MATCH_REVERSE
;
2284 operand_type_match (i386_operand_type overlap
,
2285 i386_operand_type given
)
2287 i386_operand_type temp
= overlap
;
2289 temp
.bitfield
.unspecified
= 0;
2290 temp
.bitfield
.byte
= 0;
2291 temp
.bitfield
.word
= 0;
2292 temp
.bitfield
.dword
= 0;
2293 temp
.bitfield
.fword
= 0;
2294 temp
.bitfield
.qword
= 0;
2295 temp
.bitfield
.tbyte
= 0;
2296 temp
.bitfield
.xmmword
= 0;
2297 temp
.bitfield
.ymmword
= 0;
2298 temp
.bitfield
.zmmword
= 0;
2299 if (operand_type_all_zero (&temp
))
2302 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2306 i
.error
= operand_type_mismatch
;
2310 /* If given types g0 and g1 are registers they must be of the same type
2311 unless the expected operand type register overlap is null.
2312 Some Intel syntax memory operand size checking also happens here. */
2315 operand_type_register_match (i386_operand_type g0
,
2316 i386_operand_type t0
,
2317 i386_operand_type g1
,
2318 i386_operand_type t1
)
2320 if (g0
.bitfield
.class != Reg
2321 && g0
.bitfield
.class != RegSIMD
2322 && (!operand_type_check (g0
, anymem
)
2323 || g0
.bitfield
.unspecified
2324 || (t0
.bitfield
.class != Reg
2325 && t0
.bitfield
.class != RegSIMD
)))
2328 if (g1
.bitfield
.class != Reg
2329 && g1
.bitfield
.class != RegSIMD
2330 && (!operand_type_check (g1
, anymem
)
2331 || g1
.bitfield
.unspecified
2332 || (t1
.bitfield
.class != Reg
2333 && t1
.bitfield
.class != RegSIMD
)))
2336 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2337 && g0
.bitfield
.word
== g1
.bitfield
.word
2338 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2339 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2340 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2341 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2342 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2345 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2346 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2347 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2348 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2349 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2350 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2351 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2354 i
.error
= register_type_mismatch
;
2359 static INLINE
unsigned int
2360 register_number (const reg_entry
*r
)
2362 unsigned int nr
= r
->reg_num
;
2364 if (r
->reg_flags
& RegRex
)
2367 if (r
->reg_flags
& RegVRex
)
2373 static INLINE
unsigned int
2374 mode_from_disp_size (i386_operand_type t
)
2376 if (t
.bitfield
.disp8
)
2378 else if (t
.bitfield
.disp16
2379 || t
.bitfield
.disp32
2380 || t
.bitfield
.disp32s
)
2387 fits_in_signed_byte (addressT num
)
2389 return num
+ 0x80 <= 0xff;
2393 fits_in_unsigned_byte (addressT num
)
2399 fits_in_unsigned_word (addressT num
)
2401 return num
<= 0xffff;
2405 fits_in_signed_word (addressT num
)
2407 return num
+ 0x8000 <= 0xffff;
2411 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2416 return num
+ 0x80000000 <= 0xffffffff;
2418 } /* fits_in_signed_long() */
2421 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2426 return num
<= 0xffffffff;
2428 } /* fits_in_unsigned_long() */
2431 fits_in_disp8 (offsetT num
)
2433 int shift
= i
.memshift
;
2439 mask
= (1 << shift
) - 1;
2441 /* Return 0 if NUM isn't properly aligned. */
2445 /* Check if NUM will fit in 8bit after shift. */
2446 return fits_in_signed_byte (num
>> shift
);
2450 fits_in_imm4 (offsetT num
)
2452 return (num
& 0xf) == num
;
2455 static i386_operand_type
2456 smallest_imm_type (offsetT num
)
2458 i386_operand_type t
;
2460 operand_type_set (&t
, 0);
2461 t
.bitfield
.imm64
= 1;
2463 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2465 /* This code is disabled on the 486 because all the Imm1 forms
2466 in the opcode table are slower on the i486. They're the
2467 versions with the implicitly specified single-position
2468 displacement, which has another syntax if you really want to
2470 t
.bitfield
.imm1
= 1;
2471 t
.bitfield
.imm8
= 1;
2472 t
.bitfield
.imm8s
= 1;
2473 t
.bitfield
.imm16
= 1;
2474 t
.bitfield
.imm32
= 1;
2475 t
.bitfield
.imm32s
= 1;
2477 else if (fits_in_signed_byte (num
))
2479 t
.bitfield
.imm8
= 1;
2480 t
.bitfield
.imm8s
= 1;
2481 t
.bitfield
.imm16
= 1;
2482 t
.bitfield
.imm32
= 1;
2483 t
.bitfield
.imm32s
= 1;
2485 else if (fits_in_unsigned_byte (num
))
2487 t
.bitfield
.imm8
= 1;
2488 t
.bitfield
.imm16
= 1;
2489 t
.bitfield
.imm32
= 1;
2490 t
.bitfield
.imm32s
= 1;
2492 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2494 t
.bitfield
.imm16
= 1;
2495 t
.bitfield
.imm32
= 1;
2496 t
.bitfield
.imm32s
= 1;
2498 else if (fits_in_signed_long (num
))
2500 t
.bitfield
.imm32
= 1;
2501 t
.bitfield
.imm32s
= 1;
2503 else if (fits_in_unsigned_long (num
))
2504 t
.bitfield
.imm32
= 1;
2510 offset_in_range (offsetT val
, int size
)
2516 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2517 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2518 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2520 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2526 /* If BFD64, sign extend val for 32bit address mode. */
2527 if (flag_code
!= CODE_64BIT
2528 || i
.prefix
[ADDR_PREFIX
])
2529 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2530 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2533 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2535 char buf1
[40], buf2
[40];
2537 sprint_value (buf1
, val
);
2538 sprint_value (buf2
, val
& mask
);
2539 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2554 a. PREFIX_EXIST if attempting to add a prefix where one from the
2555 same class already exists.
2556 b. PREFIX_LOCK if lock prefix is added.
2557 c. PREFIX_REP if rep/repne prefix is added.
2558 d. PREFIX_DS if ds prefix is added.
2559 e. PREFIX_OTHER if other prefix is added.
2562 static enum PREFIX_GROUP
2563 add_prefix (unsigned int prefix
)
2565 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2568 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2569 && flag_code
== CODE_64BIT
)
2571 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2572 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2573 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2574 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2585 case DS_PREFIX_OPCODE
:
2588 case CS_PREFIX_OPCODE
:
2589 case ES_PREFIX_OPCODE
:
2590 case FS_PREFIX_OPCODE
:
2591 case GS_PREFIX_OPCODE
:
2592 case SS_PREFIX_OPCODE
:
2596 case REPNE_PREFIX_OPCODE
:
2597 case REPE_PREFIX_OPCODE
:
2602 case LOCK_PREFIX_OPCODE
:
2611 case ADDR_PREFIX_OPCODE
:
2615 case DATA_PREFIX_OPCODE
:
2619 if (i
.prefix
[q
] != 0)
2627 i
.prefix
[q
] |= prefix
;
2630 as_bad (_("same type of prefix used twice"));
2636 update_code_flag (int value
, int check
)
2638 PRINTF_LIKE ((*as_error
));
2640 flag_code
= (enum flag_code
) value
;
2641 if (flag_code
== CODE_64BIT
)
2643 cpu_arch_flags
.bitfield
.cpu64
= 1;
2644 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2648 cpu_arch_flags
.bitfield
.cpu64
= 0;
2649 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2651 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2654 as_error
= as_fatal
;
2657 (*as_error
) (_("64bit mode not supported on `%s'."),
2658 cpu_arch_name
? cpu_arch_name
: default_arch
);
2660 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2663 as_error
= as_fatal
;
2666 (*as_error
) (_("32bit mode not supported on `%s'."),
2667 cpu_arch_name
? cpu_arch_name
: default_arch
);
2669 stackop_size
= '\0';
2673 set_code_flag (int value
)
2675 update_code_flag (value
, 0);
2679 set_16bit_gcc_code_flag (int new_code_flag
)
2681 flag_code
= (enum flag_code
) new_code_flag
;
2682 if (flag_code
!= CODE_16BIT
)
2684 cpu_arch_flags
.bitfield
.cpu64
= 0;
2685 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2686 stackop_size
= LONG_MNEM_SUFFIX
;
2690 set_intel_syntax (int syntax_flag
)
2692 /* Find out if register prefixing is specified. */
2693 int ask_naked_reg
= 0;
2696 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2699 int e
= get_symbol_name (&string
);
2701 if (strcmp (string
, "prefix") == 0)
2703 else if (strcmp (string
, "noprefix") == 0)
2706 as_bad (_("bad argument to syntax directive."));
2707 (void) restore_line_pointer (e
);
2709 demand_empty_rest_of_line ();
2711 intel_syntax
= syntax_flag
;
2713 if (ask_naked_reg
== 0)
2714 allow_naked_reg
= (intel_syntax
2715 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2717 allow_naked_reg
= (ask_naked_reg
< 0);
2719 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2721 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2722 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2723 register_prefix
= allow_naked_reg
? "" : "%";
2727 set_intel_mnemonic (int mnemonic_flag
)
2729 intel_mnemonic
= mnemonic_flag
;
2733 set_allow_index_reg (int flag
)
2735 allow_index_reg
= flag
;
2739 set_check (int what
)
2741 enum check_kind
*kind
;
2746 kind
= &operand_check
;
2757 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2760 int e
= get_symbol_name (&string
);
2762 if (strcmp (string
, "none") == 0)
2764 else if (strcmp (string
, "warning") == 0)
2765 *kind
= check_warning
;
2766 else if (strcmp (string
, "error") == 0)
2767 *kind
= check_error
;
2769 as_bad (_("bad argument to %s_check directive."), str
);
2770 (void) restore_line_pointer (e
);
2773 as_bad (_("missing argument for %s_check directive"), str
);
2775 demand_empty_rest_of_line ();
2779 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2780 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2782 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2783 static const char *arch
;
2785 /* Intel LIOM is only supported on ELF. */
2791 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2792 use default_arch. */
2793 arch
= cpu_arch_name
;
2795 arch
= default_arch
;
2798 /* If we are targeting Intel MCU, we must enable it. */
2799 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2800 || new_flag
.bitfield
.cpuiamcu
)
2803 /* If we are targeting Intel L1OM, we must enable it. */
2804 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2805 || new_flag
.bitfield
.cpul1om
)
2808 /* If we are targeting Intel K1OM, we must enable it. */
2809 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2810 || new_flag
.bitfield
.cpuk1om
)
2813 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2818 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2822 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2825 int e
= get_symbol_name (&string
);
2827 i386_cpu_flags flags
;
2829 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2831 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2833 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2837 cpu_arch_name
= cpu_arch
[j
].name
;
2838 cpu_sub_arch_name
= NULL
;
2839 cpu_arch_flags
= cpu_arch
[j
].flags
;
2840 if (flag_code
== CODE_64BIT
)
2842 cpu_arch_flags
.bitfield
.cpu64
= 1;
2843 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2847 cpu_arch_flags
.bitfield
.cpu64
= 0;
2848 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2850 cpu_arch_isa
= cpu_arch
[j
].type
;
2851 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2852 if (!cpu_arch_tune_set
)
2854 cpu_arch_tune
= cpu_arch_isa
;
2855 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2860 flags
= cpu_flags_or (cpu_arch_flags
,
2863 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2865 if (cpu_sub_arch_name
)
2867 char *name
= cpu_sub_arch_name
;
2868 cpu_sub_arch_name
= concat (name
,
2870 (const char *) NULL
);
2874 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2875 cpu_arch_flags
= flags
;
2876 cpu_arch_isa_flags
= flags
;
2880 = cpu_flags_or (cpu_arch_isa_flags
,
2882 (void) restore_line_pointer (e
);
2883 demand_empty_rest_of_line ();
2888 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2890 /* Disable an ISA extension. */
2891 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2892 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2894 flags
= cpu_flags_and_not (cpu_arch_flags
,
2895 cpu_noarch
[j
].flags
);
2896 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2898 if (cpu_sub_arch_name
)
2900 char *name
= cpu_sub_arch_name
;
2901 cpu_sub_arch_name
= concat (name
, string
,
2902 (const char *) NULL
);
2906 cpu_sub_arch_name
= xstrdup (string
);
2907 cpu_arch_flags
= flags
;
2908 cpu_arch_isa_flags
= flags
;
2910 (void) restore_line_pointer (e
);
2911 demand_empty_rest_of_line ();
2915 j
= ARRAY_SIZE (cpu_arch
);
2918 if (j
>= ARRAY_SIZE (cpu_arch
))
2919 as_bad (_("no such architecture: `%s'"), string
);
2921 *input_line_pointer
= e
;
2924 as_bad (_("missing cpu architecture"));
2926 no_cond_jump_promotion
= 0;
2927 if (*input_line_pointer
== ','
2928 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2933 ++input_line_pointer
;
2934 e
= get_symbol_name (&string
);
2936 if (strcmp (string
, "nojumps") == 0)
2937 no_cond_jump_promotion
= 1;
2938 else if (strcmp (string
, "jumps") == 0)
2941 as_bad (_("no such architecture modifier: `%s'"), string
);
2943 (void) restore_line_pointer (e
);
2946 demand_empty_rest_of_line ();
2949 enum bfd_architecture
2952 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2954 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2955 || flag_code
!= CODE_64BIT
)
2956 as_fatal (_("Intel L1OM is 64bit ELF only"));
2957 return bfd_arch_l1om
;
2959 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2961 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2962 || flag_code
!= CODE_64BIT
)
2963 as_fatal (_("Intel K1OM is 64bit ELF only"));
2964 return bfd_arch_k1om
;
2966 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2968 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2969 || flag_code
== CODE_64BIT
)
2970 as_fatal (_("Intel MCU is 32bit ELF only"));
2971 return bfd_arch_iamcu
;
2974 return bfd_arch_i386
;
2980 if (!strncmp (default_arch
, "x86_64", 6))
2982 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2984 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2985 || default_arch
[6] != '\0')
2986 as_fatal (_("Intel L1OM is 64bit ELF only"));
2987 return bfd_mach_l1om
;
2989 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2991 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2992 || default_arch
[6] != '\0')
2993 as_fatal (_("Intel K1OM is 64bit ELF only"));
2994 return bfd_mach_k1om
;
2996 else if (default_arch
[6] == '\0')
2997 return bfd_mach_x86_64
;
2999 return bfd_mach_x64_32
;
3001 else if (!strcmp (default_arch
, "i386")
3002 || !strcmp (default_arch
, "iamcu"))
3004 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3006 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3007 as_fatal (_("Intel MCU is 32bit ELF only"));
3008 return bfd_mach_i386_iamcu
;
3011 return bfd_mach_i386_i386
;
3014 as_fatal (_("unknown architecture"));
3020 const char *hash_err
;
3022 /* Support pseudo prefixes like {disp32}. */
3023 lex_type
['{'] = LEX_BEGIN_NAME
;
3025 /* Initialize op_hash hash table. */
3026 op_hash
= hash_new ();
3029 const insn_template
*optab
;
3030 templates
*core_optab
;
3032 /* Setup for loop. */
3034 core_optab
= XNEW (templates
);
3035 core_optab
->start
= optab
;
3040 if (optab
->name
== NULL
3041 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3043 /* different name --> ship out current template list;
3044 add to hash table; & begin anew. */
3045 core_optab
->end
= optab
;
3046 hash_err
= hash_insert (op_hash
,
3048 (void *) core_optab
);
3051 as_fatal (_("can't hash %s: %s"),
3055 if (optab
->name
== NULL
)
3057 core_optab
= XNEW (templates
);
3058 core_optab
->start
= optab
;
3063 /* Initialize reg_hash hash table. */
3064 reg_hash
= hash_new ();
3066 const reg_entry
*regtab
;
3067 unsigned int regtab_size
= i386_regtab_size
;
3069 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3071 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3073 as_fatal (_("can't hash %s: %s"),
3079 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3084 for (c
= 0; c
< 256; c
++)
3089 mnemonic_chars
[c
] = c
;
3090 register_chars
[c
] = c
;
3091 operand_chars
[c
] = c
;
3093 else if (ISLOWER (c
))
3095 mnemonic_chars
[c
] = c
;
3096 register_chars
[c
] = c
;
3097 operand_chars
[c
] = c
;
3099 else if (ISUPPER (c
))
3101 mnemonic_chars
[c
] = TOLOWER (c
);
3102 register_chars
[c
] = mnemonic_chars
[c
];
3103 operand_chars
[c
] = c
;
3105 else if (c
== '{' || c
== '}')
3107 mnemonic_chars
[c
] = c
;
3108 operand_chars
[c
] = c
;
3111 if (ISALPHA (c
) || ISDIGIT (c
))
3112 identifier_chars
[c
] = c
;
3115 identifier_chars
[c
] = c
;
3116 operand_chars
[c
] = c
;
3121 identifier_chars
['@'] = '@';
3124 identifier_chars
['?'] = '?';
3125 operand_chars
['?'] = '?';
3127 digit_chars
['-'] = '-';
3128 mnemonic_chars
['_'] = '_';
3129 mnemonic_chars
['-'] = '-';
3130 mnemonic_chars
['.'] = '.';
3131 identifier_chars
['_'] = '_';
3132 identifier_chars
['.'] = '.';
3134 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3135 operand_chars
[(unsigned char) *p
] = *p
;
3138 if (flag_code
== CODE_64BIT
)
3140 #if defined (OBJ_COFF) && defined (TE_PE)
3141 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3144 x86_dwarf2_return_column
= 16;
3146 x86_cie_data_alignment
= -8;
3150 x86_dwarf2_return_column
= 8;
3151 x86_cie_data_alignment
= -4;
3154 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3155 can be turned into BRANCH_PREFIX frag. */
3156 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3161 i386_print_statistics (FILE *file
)
3163 hash_print_statistics (file
, "i386 opcode", op_hash
);
3164 hash_print_statistics (file
, "i386 register", reg_hash
);
3169 /* Debugging routines for md_assemble. */
3170 static void pte (insn_template
*);
3171 static void pt (i386_operand_type
);
3172 static void pe (expressionS
*);
3173 static void ps (symbolS
*);
3176 pi (const char *line
, i386_insn
*x
)
3180 fprintf (stdout
, "%s: template ", line
);
3182 fprintf (stdout
, " address: base %s index %s scale %x\n",
3183 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3184 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3185 x
->log2_scale_factor
);
3186 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3187 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3188 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3189 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3190 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3191 (x
->rex
& REX_W
) != 0,
3192 (x
->rex
& REX_R
) != 0,
3193 (x
->rex
& REX_X
) != 0,
3194 (x
->rex
& REX_B
) != 0);
3195 for (j
= 0; j
< x
->operands
; j
++)
3197 fprintf (stdout
, " #%d: ", j
+ 1);
3199 fprintf (stdout
, "\n");
3200 if (x
->types
[j
].bitfield
.class == Reg
3201 || x
->types
[j
].bitfield
.class == RegMMX
3202 || x
->types
[j
].bitfield
.class == RegSIMD
3203 || x
->types
[j
].bitfield
.class == RegMask
3204 || x
->types
[j
].bitfield
.class == SReg
3205 || x
->types
[j
].bitfield
.class == RegCR
3206 || x
->types
[j
].bitfield
.class == RegDR
3207 || x
->types
[j
].bitfield
.class == RegTR
3208 || x
->types
[j
].bitfield
.class == RegBND
)
3209 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3210 if (operand_type_check (x
->types
[j
], imm
))
3212 if (operand_type_check (x
->types
[j
], disp
))
3213 pe (x
->op
[j
].disps
);
3218 pte (insn_template
*t
)
3221 fprintf (stdout
, " %d operands ", t
->operands
);
3222 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3223 if (t
->extension_opcode
!= None
)
3224 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3225 if (t
->opcode_modifier
.d
)
3226 fprintf (stdout
, "D");
3227 if (t
->opcode_modifier
.w
)
3228 fprintf (stdout
, "W");
3229 fprintf (stdout
, "\n");
3230 for (j
= 0; j
< t
->operands
; j
++)
3232 fprintf (stdout
, " #%d type ", j
+ 1);
3233 pt (t
->operand_types
[j
]);
3234 fprintf (stdout
, "\n");
3241 fprintf (stdout
, " operation %d\n", e
->X_op
);
3242 fprintf (stdout
, " add_number %ld (%lx)\n",
3243 (long) e
->X_add_number
, (long) e
->X_add_number
);
3244 if (e
->X_add_symbol
)
3246 fprintf (stdout
, " add_symbol ");
3247 ps (e
->X_add_symbol
);
3248 fprintf (stdout
, "\n");
3252 fprintf (stdout
, " op_symbol ");
3253 ps (e
->X_op_symbol
);
3254 fprintf (stdout
, "\n");
3261 fprintf (stdout
, "%s type %s%s",
3263 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3264 segment_name (S_GET_SEGMENT (s
)));
3267 static struct type_name
3269 i386_operand_type mask
;
3272 const type_names
[] =
3274 { OPERAND_TYPE_REG8
, "r8" },
3275 { OPERAND_TYPE_REG16
, "r16" },
3276 { OPERAND_TYPE_REG32
, "r32" },
3277 { OPERAND_TYPE_REG64
, "r64" },
3278 { OPERAND_TYPE_ACC8
, "acc8" },
3279 { OPERAND_TYPE_ACC16
, "acc16" },
3280 { OPERAND_TYPE_ACC32
, "acc32" },
3281 { OPERAND_TYPE_ACC64
, "acc64" },
3282 { OPERAND_TYPE_IMM8
, "i8" },
3283 { OPERAND_TYPE_IMM8
, "i8s" },
3284 { OPERAND_TYPE_IMM16
, "i16" },
3285 { OPERAND_TYPE_IMM32
, "i32" },
3286 { OPERAND_TYPE_IMM32S
, "i32s" },
3287 { OPERAND_TYPE_IMM64
, "i64" },
3288 { OPERAND_TYPE_IMM1
, "i1" },
3289 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3290 { OPERAND_TYPE_DISP8
, "d8" },
3291 { OPERAND_TYPE_DISP16
, "d16" },
3292 { OPERAND_TYPE_DISP32
, "d32" },
3293 { OPERAND_TYPE_DISP32S
, "d32s" },
3294 { OPERAND_TYPE_DISP64
, "d64" },
3295 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3296 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3297 { OPERAND_TYPE_CONTROL
, "control reg" },
3298 { OPERAND_TYPE_TEST
, "test reg" },
3299 { OPERAND_TYPE_DEBUG
, "debug reg" },
3300 { OPERAND_TYPE_FLOATREG
, "FReg" },
3301 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3302 { OPERAND_TYPE_SREG
, "SReg" },
3303 { OPERAND_TYPE_REGMMX
, "rMMX" },
3304 { OPERAND_TYPE_REGXMM
, "rXMM" },
3305 { OPERAND_TYPE_REGYMM
, "rYMM" },
3306 { OPERAND_TYPE_REGZMM
, "rZMM" },
3307 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3311 pt (i386_operand_type t
)
3314 i386_operand_type a
;
3316 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3318 a
= operand_type_and (t
, type_names
[j
].mask
);
3319 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3320 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3325 #endif /* DEBUG386 */
3327 static bfd_reloc_code_real_type
3328 reloc (unsigned int size
,
3331 bfd_reloc_code_real_type other
)
3333 if (other
!= NO_RELOC
)
3335 reloc_howto_type
*rel
;
3340 case BFD_RELOC_X86_64_GOT32
:
3341 return BFD_RELOC_X86_64_GOT64
;
3343 case BFD_RELOC_X86_64_GOTPLT64
:
3344 return BFD_RELOC_X86_64_GOTPLT64
;
3346 case BFD_RELOC_X86_64_PLTOFF64
:
3347 return BFD_RELOC_X86_64_PLTOFF64
;
3349 case BFD_RELOC_X86_64_GOTPC32
:
3350 other
= BFD_RELOC_X86_64_GOTPC64
;
3352 case BFD_RELOC_X86_64_GOTPCREL
:
3353 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3355 case BFD_RELOC_X86_64_TPOFF32
:
3356 other
= BFD_RELOC_X86_64_TPOFF64
;
3358 case BFD_RELOC_X86_64_DTPOFF32
:
3359 other
= BFD_RELOC_X86_64_DTPOFF64
;
3365 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3366 if (other
== BFD_RELOC_SIZE32
)
3369 other
= BFD_RELOC_SIZE64
;
3372 as_bad (_("there are no pc-relative size relocations"));
3378 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3379 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3382 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3384 as_bad (_("unknown relocation (%u)"), other
);
3385 else if (size
!= bfd_get_reloc_size (rel
))
3386 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3387 bfd_get_reloc_size (rel
),
3389 else if (pcrel
&& !rel
->pc_relative
)
3390 as_bad (_("non-pc-relative relocation for pc-relative field"));
3391 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3393 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3395 as_bad (_("relocated field and relocation type differ in signedness"));
3404 as_bad (_("there are no unsigned pc-relative relocations"));
3407 case 1: return BFD_RELOC_8_PCREL
;
3408 case 2: return BFD_RELOC_16_PCREL
;
3409 case 4: return BFD_RELOC_32_PCREL
;
3410 case 8: return BFD_RELOC_64_PCREL
;
3412 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3419 case 4: return BFD_RELOC_X86_64_32S
;
3424 case 1: return BFD_RELOC_8
;
3425 case 2: return BFD_RELOC_16
;
3426 case 4: return BFD_RELOC_32
;
3427 case 8: return BFD_RELOC_64
;
3429 as_bad (_("cannot do %s %u byte relocation"),
3430 sign
> 0 ? "signed" : "unsigned", size
);
3436 /* Here we decide which fixups can be adjusted to make them relative to
3437 the beginning of the section instead of the symbol. Basically we need
3438 to make sure that the dynamic relocations are done correctly, so in
3439 some cases we force the original symbol to be used. */
3442 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3444 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3448 /* Don't adjust pc-relative references to merge sections in 64-bit
3450 if (use_rela_relocations
3451 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3455 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3456 and changed later by validate_fix. */
3457 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3458 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3461 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3462 for size relocations. */
3463 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3464 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3465 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3466 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3467 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3468 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3470 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3471 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3472 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3473 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3474 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3475 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3476 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3477 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3478 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3483 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3484 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3485 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3487 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3488 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3489 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3490 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3491 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3492 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3493 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3500 intel_float_operand (const char *mnemonic
)
3502 /* Note that the value returned is meaningful only for opcodes with (memory)
3503 operands, hence the code here is free to improperly handle opcodes that
3504 have no operands (for better performance and smaller code). */
3506 if (mnemonic
[0] != 'f')
3507 return 0; /* non-math */
3509 switch (mnemonic
[1])
3511 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3512 the fs segment override prefix not currently handled because no
3513 call path can make opcodes without operands get here */
3515 return 2 /* integer op */;
3517 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3518 return 3; /* fldcw/fldenv */
3521 if (mnemonic
[2] != 'o' /* fnop */)
3522 return 3; /* non-waiting control op */
3525 if (mnemonic
[2] == 's')
3526 return 3; /* frstor/frstpm */
3529 if (mnemonic
[2] == 'a')
3530 return 3; /* fsave */
3531 if (mnemonic
[2] == 't')
3533 switch (mnemonic
[3])
3535 case 'c': /* fstcw */
3536 case 'd': /* fstdw */
3537 case 'e': /* fstenv */
3538 case 's': /* fsts[gw] */
3544 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3545 return 0; /* fxsave/fxrstor are not really math ops */
3552 /* Build the VEX prefix. */
3555 build_vex_prefix (const insn_template
*t
)
3557 unsigned int register_specifier
;
3558 unsigned int implied_prefix
;
3559 unsigned int vector_length
;
3562 /* Check register specifier. */
3563 if (i
.vex
.register_specifier
)
3565 register_specifier
=
3566 ~register_number (i
.vex
.register_specifier
) & 0xf;
3567 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3570 register_specifier
= 0xf;
3572 /* Use 2-byte VEX prefix by swapping destination and source operand
3573 if there are more than 1 register operand. */
3574 if (i
.reg_operands
> 1
3575 && i
.vec_encoding
!= vex_encoding_vex3
3576 && i
.dir_encoding
== dir_encoding_default
3577 && i
.operands
== i
.reg_operands
3578 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3579 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3580 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3583 unsigned int xchg
= i
.operands
- 1;
3584 union i386_op temp_op
;
3585 i386_operand_type temp_type
;
3587 temp_type
= i
.types
[xchg
];
3588 i
.types
[xchg
] = i
.types
[0];
3589 i
.types
[0] = temp_type
;
3590 temp_op
= i
.op
[xchg
];
3591 i
.op
[xchg
] = i
.op
[0];
3594 gas_assert (i
.rm
.mode
== 3);
3598 i
.rm
.regmem
= i
.rm
.reg
;
3601 if (i
.tm
.opcode_modifier
.d
)
3602 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3603 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3604 else /* Use the next insn. */
3608 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3609 are no memory operands and at least 3 register ones. */
3610 if (i
.reg_operands
>= 3
3611 && i
.vec_encoding
!= vex_encoding_vex3
3612 && i
.reg_operands
== i
.operands
- i
.imm_operands
3613 && i
.tm
.opcode_modifier
.vex
3614 && i
.tm
.opcode_modifier
.commutative
3615 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3617 && i
.vex
.register_specifier
3618 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3620 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3621 union i386_op temp_op
;
3622 i386_operand_type temp_type
;
3624 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3625 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3626 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3627 &i
.types
[i
.operands
- 3]));
3628 gas_assert (i
.rm
.mode
== 3);
3630 temp_type
= i
.types
[xchg
];
3631 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3632 i
.types
[xchg
+ 1] = temp_type
;
3633 temp_op
= i
.op
[xchg
];
3634 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3635 i
.op
[xchg
+ 1] = temp_op
;
3638 xchg
= i
.rm
.regmem
| 8;
3639 i
.rm
.regmem
= ~register_specifier
& 0xf;
3640 gas_assert (!(i
.rm
.regmem
& 8));
3641 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3642 register_specifier
= ~xchg
& 0xf;
3645 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3646 vector_length
= avxscalar
;
3647 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3653 /* Determine vector length from the last multi-length vector
3656 for (op
= t
->operands
; op
--;)
3657 if (t
->operand_types
[op
].bitfield
.xmmword
3658 && t
->operand_types
[op
].bitfield
.ymmword
3659 && i
.types
[op
].bitfield
.ymmword
)
3666 switch ((i
.tm
.base_opcode
>> (i
.tm
.opcode_length
<< 3)) & 0xff)
3671 case DATA_PREFIX_OPCODE
:
3674 case REPE_PREFIX_OPCODE
:
3677 case REPNE_PREFIX_OPCODE
:
3684 /* Check the REX.W bit and VEXW. */
3685 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3686 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3687 else if (i
.tm
.opcode_modifier
.vexw
)
3688 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3690 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3692 /* Use 2-byte VEX prefix if possible. */
3694 && i
.vec_encoding
!= vex_encoding_vex3
3695 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3696 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3698 /* 2-byte VEX prefix. */
3702 i
.vex
.bytes
[0] = 0xc5;
3704 /* Check the REX.R bit. */
3705 r
= (i
.rex
& REX_R
) ? 0 : 1;
3706 i
.vex
.bytes
[1] = (r
<< 7
3707 | register_specifier
<< 3
3708 | vector_length
<< 2
3713 /* 3-byte VEX prefix. */
3718 switch (i
.tm
.opcode_modifier
.vexopcode
)
3722 i
.vex
.bytes
[0] = 0xc4;
3726 i
.vex
.bytes
[0] = 0xc4;
3730 i
.vex
.bytes
[0] = 0xc4;
3734 i
.vex
.bytes
[0] = 0x8f;
3738 i
.vex
.bytes
[0] = 0x8f;
3742 i
.vex
.bytes
[0] = 0x8f;
3748 /* The high 3 bits of the second VEX byte are 1's compliment
3749 of RXB bits from REX. */
3750 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3752 i
.vex
.bytes
[2] = (w
<< 7
3753 | register_specifier
<< 3
3754 | vector_length
<< 2
3759 static INLINE bfd_boolean
3760 is_evex_encoding (const insn_template
*t
)
3762 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3763 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3764 || t
->opcode_modifier
.sae
;
3767 static INLINE bfd_boolean
3768 is_any_vex_encoding (const insn_template
*t
)
3770 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3771 || is_evex_encoding (t
);
3774 /* Build the EVEX prefix. */
3777 build_evex_prefix (void)
3779 unsigned int register_specifier
;
3780 unsigned int implied_prefix
;
3782 rex_byte vrex_used
= 0;
3784 /* Check register specifier. */
3785 if (i
.vex
.register_specifier
)
3787 gas_assert ((i
.vrex
& REX_X
) == 0);
3789 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3790 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3791 register_specifier
+= 8;
3792 /* The upper 16 registers are encoded in the fourth byte of the
3794 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3795 i
.vex
.bytes
[3] = 0x8;
3796 register_specifier
= ~register_specifier
& 0xf;
3800 register_specifier
= 0xf;
3802 /* Encode upper 16 vector index register in the fourth byte of
3804 if (!(i
.vrex
& REX_X
))
3805 i
.vex
.bytes
[3] = 0x8;
3810 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3815 case DATA_PREFIX_OPCODE
:
3818 case REPE_PREFIX_OPCODE
:
3821 case REPNE_PREFIX_OPCODE
:
3828 /* 4 byte EVEX prefix. */
3830 i
.vex
.bytes
[0] = 0x62;
3833 switch (i
.tm
.opcode_modifier
.vexopcode
)
3849 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3851 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3853 /* The fifth bit of the second EVEX byte is 1's compliment of the
3854 REX_R bit in VREX. */
3855 if (!(i
.vrex
& REX_R
))
3856 i
.vex
.bytes
[1] |= 0x10;
3860 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3862 /* When all operands are registers, the REX_X bit in REX is not
3863 used. We reuse it to encode the upper 16 registers, which is
3864 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3865 as 1's compliment. */
3866 if ((i
.vrex
& REX_B
))
3869 i
.vex
.bytes
[1] &= ~0x40;
3873 /* EVEX instructions shouldn't need the REX prefix. */
3874 i
.vrex
&= ~vrex_used
;
3875 gas_assert (i
.vrex
== 0);
3877 /* Check the REX.W bit and VEXW. */
3878 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3879 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3880 else if (i
.tm
.opcode_modifier
.vexw
)
3881 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3883 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3885 /* Encode the U bit. */
3886 implied_prefix
|= 0x4;
3888 /* The third byte of the EVEX prefix. */
3889 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3891 /* The fourth byte of the EVEX prefix. */
3892 /* The zeroing-masking bit. */
3893 if (i
.mask
&& i
.mask
->zeroing
)
3894 i
.vex
.bytes
[3] |= 0x80;
3896 /* Don't always set the broadcast bit if there is no RC. */
3899 /* Encode the vector length. */
3900 unsigned int vec_length
;
3902 if (!i
.tm
.opcode_modifier
.evex
3903 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3907 /* Determine vector length from the last multi-length vector
3909 for (op
= i
.operands
; op
--;)
3910 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3911 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3912 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3914 if (i
.types
[op
].bitfield
.zmmword
)
3916 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3919 else if (i
.types
[op
].bitfield
.ymmword
)
3921 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3924 else if (i
.types
[op
].bitfield
.xmmword
)
3926 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3929 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3931 switch (i
.broadcast
->bytes
)
3934 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3937 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3940 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3949 if (op
>= MAX_OPERANDS
)
3953 switch (i
.tm
.opcode_modifier
.evex
)
3955 case EVEXLIG
: /* LL' is ignored */
3956 vec_length
= evexlig
<< 5;
3959 vec_length
= 0 << 5;
3962 vec_length
= 1 << 5;
3965 vec_length
= 2 << 5;
3971 i
.vex
.bytes
[3] |= vec_length
;
3972 /* Encode the broadcast bit. */
3974 i
.vex
.bytes
[3] |= 0x10;
3978 if (i
.rounding
->type
!= saeonly
)
3979 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3981 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3984 if (i
.mask
&& i
.mask
->mask
)
3985 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3989 process_immext (void)
3993 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3994 which is coded in the same place as an 8-bit immediate field
3995 would be. Here we fake an 8-bit immediate operand from the
3996 opcode suffix stored in tm.extension_opcode.
3998 AVX instructions also use this encoding, for some of
3999 3 argument instructions. */
4001 gas_assert (i
.imm_operands
<= 1
4003 || (is_any_vex_encoding (&i
.tm
)
4004 && i
.operands
<= 4)));
4006 exp
= &im_expressions
[i
.imm_operands
++];
4007 i
.op
[i
.operands
].imms
= exp
;
4008 i
.types
[i
.operands
] = imm8
;
4010 exp
->X_op
= O_constant
;
4011 exp
->X_add_number
= i
.tm
.extension_opcode
;
4012 i
.tm
.extension_opcode
= None
;
4019 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4024 as_bad (_("invalid instruction `%s' after `%s'"),
4025 i
.tm
.name
, i
.hle_prefix
);
4028 if (i
.prefix
[LOCK_PREFIX
])
4030 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4034 case HLEPrefixRelease
:
4035 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4037 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4041 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4043 as_bad (_("memory destination needed for instruction `%s'"
4044 " after `xrelease'"), i
.tm
.name
);
4051 /* Try the shortest encoding by shortening operand size. */
4054 optimize_encoding (void)
4058 if (optimize_for_space
4059 && !is_any_vex_encoding (&i
.tm
)
4060 && i
.reg_operands
== 1
4061 && i
.imm_operands
== 1
4062 && !i
.types
[1].bitfield
.byte
4063 && i
.op
[0].imms
->X_op
== O_constant
4064 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4065 && (i
.tm
.base_opcode
== 0xa8
4066 || (i
.tm
.base_opcode
== 0xf6
4067 && i
.tm
.extension_opcode
== 0x0)))
4070 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4072 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4073 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4075 i
.types
[1].bitfield
.byte
= 1;
4076 /* Ignore the suffix. */
4078 /* Convert to byte registers. */
4079 if (i
.types
[1].bitfield
.word
)
4081 else if (i
.types
[1].bitfield
.dword
)
4085 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4090 else if (flag_code
== CODE_64BIT
4091 && !is_any_vex_encoding (&i
.tm
)
4092 && ((i
.types
[1].bitfield
.qword
4093 && i
.reg_operands
== 1
4094 && i
.imm_operands
== 1
4095 && i
.op
[0].imms
->X_op
== O_constant
4096 && ((i
.tm
.base_opcode
== 0xb8
4097 && i
.tm
.extension_opcode
== None
4098 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4099 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4100 && ((i
.tm
.base_opcode
== 0x24
4101 || i
.tm
.base_opcode
== 0xa8)
4102 || (i
.tm
.base_opcode
== 0x80
4103 && i
.tm
.extension_opcode
== 0x4)
4104 || ((i
.tm
.base_opcode
== 0xf6
4105 || (i
.tm
.base_opcode
| 1) == 0xc7)
4106 && i
.tm
.extension_opcode
== 0x0)))
4107 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4108 && i
.tm
.base_opcode
== 0x83
4109 && i
.tm
.extension_opcode
== 0x4)))
4110 || (i
.types
[0].bitfield
.qword
4111 && ((i
.reg_operands
== 2
4112 && i
.op
[0].regs
== i
.op
[1].regs
4113 && (i
.tm
.base_opcode
== 0x30
4114 || i
.tm
.base_opcode
== 0x28))
4115 || (i
.reg_operands
== 1
4117 && i
.tm
.base_opcode
== 0x30)))))
4120 andq $imm31, %r64 -> andl $imm31, %r32
4121 andq $imm7, %r64 -> andl $imm7, %r32
4122 testq $imm31, %r64 -> testl $imm31, %r32
4123 xorq %r64, %r64 -> xorl %r32, %r32
4124 subq %r64, %r64 -> subl %r32, %r32
4125 movq $imm31, %r64 -> movl $imm31, %r32
4126 movq $imm32, %r64 -> movl $imm32, %r32
4128 i
.tm
.opcode_modifier
.norex64
= 1;
4129 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4132 movq $imm31, %r64 -> movl $imm31, %r32
4133 movq $imm32, %r64 -> movl $imm32, %r32
4135 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4136 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4137 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4138 i
.types
[0].bitfield
.imm32
= 1;
4139 i
.types
[0].bitfield
.imm32s
= 0;
4140 i
.types
[0].bitfield
.imm64
= 0;
4141 i
.types
[1].bitfield
.dword
= 1;
4142 i
.types
[1].bitfield
.qword
= 0;
4143 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4146 movq $imm31, %r64 -> movl $imm31, %r32
4148 i
.tm
.base_opcode
= 0xb8;
4149 i
.tm
.extension_opcode
= None
;
4150 i
.tm
.opcode_modifier
.w
= 0;
4151 i
.tm
.opcode_modifier
.modrm
= 0;
4155 else if (optimize
> 1
4156 && !optimize_for_space
4157 && !is_any_vex_encoding (&i
.tm
)
4158 && i
.reg_operands
== 2
4159 && i
.op
[0].regs
== i
.op
[1].regs
4160 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4161 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4162 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4165 andb %rN, %rN -> testb %rN, %rN
4166 andw %rN, %rN -> testw %rN, %rN
4167 andq %rN, %rN -> testq %rN, %rN
4168 orb %rN, %rN -> testb %rN, %rN
4169 orw %rN, %rN -> testw %rN, %rN
4170 orq %rN, %rN -> testq %rN, %rN
4172 and outside of 64-bit mode
4174 andl %rN, %rN -> testl %rN, %rN
4175 orl %rN, %rN -> testl %rN, %rN
4177 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4179 else if (i
.reg_operands
== 3
4180 && i
.op
[0].regs
== i
.op
[1].regs
4181 && !i
.types
[2].bitfield
.xmmword
4182 && (i
.tm
.opcode_modifier
.vex
4183 || ((!i
.mask
|| i
.mask
->zeroing
)
4185 && is_evex_encoding (&i
.tm
)
4186 && (i
.vec_encoding
!= vex_encoding_evex
4187 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4188 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4189 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4190 && i
.types
[2].bitfield
.ymmword
))))
4191 && ((i
.tm
.base_opcode
== 0x55
4192 || i
.tm
.base_opcode
== 0x6655
4193 || i
.tm
.base_opcode
== 0x66df
4194 || i
.tm
.base_opcode
== 0x57
4195 || i
.tm
.base_opcode
== 0x6657
4196 || i
.tm
.base_opcode
== 0x66ef
4197 || i
.tm
.base_opcode
== 0x66f8
4198 || i
.tm
.base_opcode
== 0x66f9
4199 || i
.tm
.base_opcode
== 0x66fa
4200 || i
.tm
.base_opcode
== 0x66fb
4201 || i
.tm
.base_opcode
== 0x42
4202 || i
.tm
.base_opcode
== 0x6642
4203 || i
.tm
.base_opcode
== 0x47
4204 || i
.tm
.base_opcode
== 0x6647)
4205 && i
.tm
.extension_opcode
== None
))
4208 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4210 EVEX VOP %zmmM, %zmmM, %zmmN
4211 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4212 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4213 EVEX VOP %ymmM, %ymmM, %ymmN
4214 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4215 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4216 VEX VOP %ymmM, %ymmM, %ymmN
4217 -> VEX VOP %xmmM, %xmmM, %xmmN
4218 VOP, one of vpandn and vpxor:
4219 VEX VOP %ymmM, %ymmM, %ymmN
4220 -> VEX VOP %xmmM, %xmmM, %xmmN
4221 VOP, one of vpandnd and vpandnq:
4222 EVEX VOP %zmmM, %zmmM, %zmmN
4223 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4224 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4225 EVEX VOP %ymmM, %ymmM, %ymmN
4226 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4227 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4228 VOP, one of vpxord and vpxorq:
4229 EVEX VOP %zmmM, %zmmM, %zmmN
4230 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4231 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4232 EVEX VOP %ymmM, %ymmM, %ymmN
4233 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4234 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4235 VOP, one of kxord and kxorq:
4236 VEX VOP %kM, %kM, %kN
4237 -> VEX kxorw %kM, %kM, %kN
4238 VOP, one of kandnd and kandnq:
4239 VEX VOP %kM, %kM, %kN
4240 -> VEX kandnw %kM, %kM, %kN
4242 if (is_evex_encoding (&i
.tm
))
4244 if (i
.vec_encoding
!= vex_encoding_evex
)
4246 i
.tm
.opcode_modifier
.vex
= VEX128
;
4247 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4248 i
.tm
.opcode_modifier
.evex
= 0;
4250 else if (optimize
> 1)
4251 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4255 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4257 i
.tm
.base_opcode
&= 0xff;
4258 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4261 i
.tm
.opcode_modifier
.vex
= VEX128
;
4263 if (i
.tm
.opcode_modifier
.vex
)
4264 for (j
= 0; j
< 3; j
++)
4266 i
.types
[j
].bitfield
.xmmword
= 1;
4267 i
.types
[j
].bitfield
.ymmword
= 0;
4270 else if (i
.vec_encoding
!= vex_encoding_evex
4271 && !i
.types
[0].bitfield
.zmmword
4272 && !i
.types
[1].bitfield
.zmmword
4275 && is_evex_encoding (&i
.tm
)
4276 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4277 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4278 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4279 || (i
.tm
.base_opcode
& ~4) == 0x66db
4280 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4281 && i
.tm
.extension_opcode
== None
)
4284 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4285 vmovdqu32 and vmovdqu64:
4286 EVEX VOP %xmmM, %xmmN
4287 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4288 EVEX VOP %ymmM, %ymmN
4289 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4291 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4293 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4295 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4297 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4298 VOP, one of vpand, vpandn, vpor, vpxor:
4299 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4300 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4301 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4302 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4303 EVEX VOP{d,q} mem, %xmmM, %xmmN
4304 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4305 EVEX VOP{d,q} mem, %ymmM, %ymmN
4306 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4308 for (j
= 0; j
< i
.operands
; j
++)
4309 if (operand_type_check (i
.types
[j
], disp
)
4310 && i
.op
[j
].disps
->X_op
== O_constant
)
4312 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4313 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4314 bytes, we choose EVEX Disp8 over VEX Disp32. */
4315 int evex_disp8
, vex_disp8
;
4316 unsigned int memshift
= i
.memshift
;
4317 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4319 evex_disp8
= fits_in_disp8 (n
);
4321 vex_disp8
= fits_in_disp8 (n
);
4322 if (evex_disp8
!= vex_disp8
)
4324 i
.memshift
= memshift
;
4328 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4331 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4332 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4333 i
.tm
.opcode_modifier
.vex
4334 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4335 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4336 /* VPAND, VPOR, and VPXOR are commutative. */
4337 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4338 i
.tm
.opcode_modifier
.commutative
= 1;
4339 i
.tm
.opcode_modifier
.evex
= 0;
4340 i
.tm
.opcode_modifier
.masking
= 0;
4341 i
.tm
.opcode_modifier
.broadcast
= 0;
4342 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4345 i
.types
[j
].bitfield
.disp8
4346 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4350 /* Return non-zero for load instruction. */
4356 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4357 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4361 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4362 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4363 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4364 if (i
.tm
.opcode_modifier
.anysize
)
4367 /* pop, popf, popa. */
4368 if (strcmp (i
.tm
.name
, "pop") == 0
4369 || i
.tm
.base_opcode
== 0x9d
4370 || i
.tm
.base_opcode
== 0x61)
4373 /* movs, cmps, lods, scas. */
4374 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4378 if (base_opcode
== 0x6f
4379 || i
.tm
.base_opcode
== 0xd7)
4381 /* NB: For AMD-specific insns with implicit memory operands,
4382 they're intentionally not covered. */
4385 /* No memory operand. */
4386 if (!i
.mem_operands
)
4392 if (i
.tm
.base_opcode
== 0xae
4393 && i
.tm
.opcode_modifier
.vex
4394 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
4395 && i
.tm
.extension_opcode
== 2)
4400 /* test, not, neg, mul, imul, div, idiv. */
4401 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4402 && i
.tm
.extension_opcode
!= 1)
4406 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4409 /* add, or, adc, sbb, and, sub, xor, cmp. */
4410 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4413 /* bt, bts, btr, btc. */
4414 if (i
.tm
.base_opcode
== 0xfba
4415 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4418 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4419 if ((base_opcode
== 0xc1
4420 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4421 && i
.tm
.extension_opcode
!= 6)
4424 /* cmpxchg8b, cmpxchg16b, xrstors. */
4425 if (i
.tm
.base_opcode
== 0xfc7
4426 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4429 /* fxrstor, ldmxcsr, xrstor. */
4430 if (i
.tm
.base_opcode
== 0xfae
4431 && (i
.tm
.extension_opcode
== 1
4432 || i
.tm
.extension_opcode
== 2
4433 || i
.tm
.extension_opcode
== 5))
4436 /* lgdt, lidt, lmsw. */
4437 if (i
.tm
.base_opcode
== 0xf01
4438 && (i
.tm
.extension_opcode
== 2
4439 || i
.tm
.extension_opcode
== 3
4440 || i
.tm
.extension_opcode
== 6))
4444 if (i
.tm
.base_opcode
== 0xfc7
4445 && i
.tm
.extension_opcode
== 6)
4448 /* Check for x87 instructions. */
4449 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4451 /* Skip fst, fstp, fstenv, fstcw. */
4452 if (i
.tm
.base_opcode
== 0xd9
4453 && (i
.tm
.extension_opcode
== 2
4454 || i
.tm
.extension_opcode
== 3
4455 || i
.tm
.extension_opcode
== 6
4456 || i
.tm
.extension_opcode
== 7))
4459 /* Skip fisttp, fist, fistp, fstp. */
4460 if (i
.tm
.base_opcode
== 0xdb
4461 && (i
.tm
.extension_opcode
== 1
4462 || i
.tm
.extension_opcode
== 2
4463 || i
.tm
.extension_opcode
== 3
4464 || i
.tm
.extension_opcode
== 7))
4467 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4468 if (i
.tm
.base_opcode
== 0xdd
4469 && (i
.tm
.extension_opcode
== 1
4470 || i
.tm
.extension_opcode
== 2
4471 || i
.tm
.extension_opcode
== 3
4472 || i
.tm
.extension_opcode
== 6
4473 || i
.tm
.extension_opcode
== 7))
4476 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4477 if (i
.tm
.base_opcode
== 0xdf
4478 && (i
.tm
.extension_opcode
== 1
4479 || i
.tm
.extension_opcode
== 2
4480 || i
.tm
.extension_opcode
== 3
4481 || i
.tm
.extension_opcode
== 6
4482 || i
.tm
.extension_opcode
== 7))
4489 dest
= i
.operands
- 1;
4491 /* Check fake imm8 operand and 3 source operands. */
4492 if ((i
.tm
.opcode_modifier
.immext
4493 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4494 && i
.types
[dest
].bitfield
.imm8
)
4497 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4499 && (base_opcode
== 0x1
4500 || base_opcode
== 0x9
4501 || base_opcode
== 0x11
4502 || base_opcode
== 0x19
4503 || base_opcode
== 0x21
4504 || base_opcode
== 0x29
4505 || base_opcode
== 0x31
4506 || base_opcode
== 0x39
4507 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4508 || base_opcode
== 0xfc1))
4511 /* Check for load instruction. */
4512 return (i
.types
[dest
].bitfield
.class != ClassNone
4513 || i
.types
[dest
].bitfield
.instance
== Accum
);
4516 /* Output lfence, 0xfaee8, after instruction. */
4519 insert_lfence_after (void)
4521 if (lfence_after_load
&& load_insn_p ())
4523 /* There are also two REP string instructions that require
4524 special treatment. Specifically, the compare string (CMPS)
4525 and scan string (SCAS) instructions set EFLAGS in a manner
4526 that depends on the data being compared/scanned. When used
4527 with a REP prefix, the number of iterations may therefore
4528 vary depending on this data. If the data is a program secret
4529 chosen by the adversary using an LVI method,
4530 then this data-dependent behavior may leak some aspect
4532 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4533 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4534 && i
.prefix
[REP_PREFIX
])
4536 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4539 char *p
= frag_more (3);
4546 /* Output lfence, 0xfaee8, before instruction. */
4549 insert_lfence_before (void)
4553 if (is_any_vex_encoding (&i
.tm
))
4556 if (i
.tm
.base_opcode
== 0xff
4557 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4559 /* Insert lfence before indirect branch if needed. */
4561 if (lfence_before_indirect_branch
== lfence_branch_none
)
4564 if (i
.operands
!= 1)
4567 if (i
.reg_operands
== 1)
4569 /* Indirect branch via register. Don't insert lfence with
4570 -mlfence-after-load=yes. */
4571 if (lfence_after_load
4572 || lfence_before_indirect_branch
== lfence_branch_memory
)
4575 else if (i
.mem_operands
== 1
4576 && lfence_before_indirect_branch
!= lfence_branch_register
)
4578 as_warn (_("indirect `%s` with memory operand should be avoided"),
4585 if (last_insn
.kind
!= last_insn_other
4586 && last_insn
.seg
== now_seg
)
4588 as_warn_where (last_insn
.file
, last_insn
.line
,
4589 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4590 last_insn
.name
, i
.tm
.name
);
4601 /* Output or/not/shl and lfence before near ret. */
4602 if (lfence_before_ret
!= lfence_before_ret_none
4603 && (i
.tm
.base_opcode
== 0xc2
4604 || i
.tm
.base_opcode
== 0xc3))
4606 if (last_insn
.kind
!= last_insn_other
4607 && last_insn
.seg
== now_seg
)
4609 as_warn_where (last_insn
.file
, last_insn
.line
,
4610 _("`%s` skips -mlfence-before-ret on `%s`"),
4611 last_insn
.name
, i
.tm
.name
);
4615 /* Near ret ingore operand size override under CPU64. */
4616 char prefix
= flag_code
== CODE_64BIT
4618 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4620 if (lfence_before_ret
== lfence_before_ret_not
)
4622 /* not: 0xf71424, may add prefix
4623 for operand size override or 64-bit code. */
4624 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4638 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4641 if (lfence_before_ret
== lfence_before_ret_or
)
4643 /* or: 0x830c2400, may add prefix
4644 for operand size override or 64-bit code. */
4650 /* shl: 0xc1242400, may add prefix
4651 for operand size override or 64-bit code. */
4666 /* This is the guts of the machine-dependent assembler. LINE points to a
4667 machine dependent instruction. This function is supposed to emit
4668 the frags/bytes it assembles to. */
4671 md_assemble (char *line
)
4674 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4675 const insn_template
*t
;
4677 /* Initialize globals. */
4678 memset (&i
, '\0', sizeof (i
));
4679 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4680 i
.reloc
[j
] = NO_RELOC
;
4681 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4682 memset (im_expressions
, '\0', sizeof (im_expressions
));
4683 save_stack_p
= save_stack
;
4685 /* First parse an instruction mnemonic & call i386_operand for the operands.
4686 We assume that the scrubber has arranged it so that line[0] is the valid
4687 start of a (possibly prefixed) mnemonic. */
4689 line
= parse_insn (line
, mnemonic
);
4692 mnem_suffix
= i
.suffix
;
4694 line
= parse_operands (line
, mnemonic
);
4696 xfree (i
.memop1_string
);
4697 i
.memop1_string
= NULL
;
4701 /* Now we've parsed the mnemonic into a set of templates, and have the
4702 operands at hand. */
4704 /* All Intel opcodes have reversed operands except for "bound", "enter",
4705 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4706 intersegment "jmp" and "call" instructions with 2 immediate operands so
4707 that the immediate segment precedes the offset, as it does when in AT&T
4711 && (strcmp (mnemonic
, "bound") != 0)
4712 && (strcmp (mnemonic
, "invlpga") != 0)
4713 && (strncmp (mnemonic
, "monitor", 7) != 0)
4714 && (strncmp (mnemonic
, "mwait", 5) != 0)
4715 && (strcmp (mnemonic
, "tpause") != 0)
4716 && (strcmp (mnemonic
, "umwait") != 0)
4717 && !(operand_type_check (i
.types
[0], imm
)
4718 && operand_type_check (i
.types
[1], imm
)))
4721 /* The order of the immediates should be reversed
4722 for 2 immediates extrq and insertq instructions */
4723 if (i
.imm_operands
== 2
4724 && (strcmp (mnemonic
, "extrq") == 0
4725 || strcmp (mnemonic
, "insertq") == 0))
4726 swap_2_operands (0, 1);
4731 /* Don't optimize displacement for movabs since it only takes 64bit
4734 && i
.disp_encoding
!= disp_encoding_32bit
4735 && (flag_code
!= CODE_64BIT
4736 || strcmp (mnemonic
, "movabs") != 0))
4739 /* Next, we find a template that matches the given insn,
4740 making sure the overlap of the given operands types is consistent
4741 with the template operand types. */
4743 if (!(t
= match_template (mnem_suffix
)))
4746 if (sse_check
!= check_none
4747 && !i
.tm
.opcode_modifier
.noavx
4748 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4749 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4750 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4751 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4752 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4753 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4754 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4755 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4756 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4757 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4758 || i
.tm
.cpu_flags
.bitfield
.cpusha
4759 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4761 (sse_check
== check_warning
4763 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4766 if (i
.tm
.opcode_modifier
.fwait
)
4767 if (!add_prefix (FWAIT_OPCODE
))
4770 /* Check if REP prefix is OK. */
4771 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4773 as_bad (_("invalid instruction `%s' after `%s'"),
4774 i
.tm
.name
, i
.rep_prefix
);
4778 /* Check for lock without a lockable instruction. Destination operand
4779 must be memory unless it is xchg (0x86). */
4780 if (i
.prefix
[LOCK_PREFIX
]
4781 && (!i
.tm
.opcode_modifier
.islockable
4782 || i
.mem_operands
== 0
4783 || (i
.tm
.base_opcode
!= 0x86
4784 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4786 as_bad (_("expecting lockable instruction after `lock'"));
4790 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4791 if (i
.prefix
[DATA_PREFIX
]
4792 && (is_any_vex_encoding (&i
.tm
)
4793 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4794 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4796 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4800 /* Check if HLE prefix is OK. */
4801 if (i
.hle_prefix
&& !check_hle ())
4804 /* Check BND prefix. */
4805 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4806 as_bad (_("expecting valid branch instruction after `bnd'"));
4808 /* Check NOTRACK prefix. */
4809 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4810 as_bad (_("expecting indirect branch instruction after `notrack'"));
4812 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4814 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4815 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4816 else if (flag_code
!= CODE_16BIT
4817 ? i
.prefix
[ADDR_PREFIX
]
4818 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4819 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4822 /* Insert BND prefix. */
4823 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4825 if (!i
.prefix
[BND_PREFIX
])
4826 add_prefix (BND_PREFIX_OPCODE
);
4827 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4829 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4830 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4834 /* Check string instruction segment overrides. */
4835 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4837 gas_assert (i
.mem_operands
);
4838 if (!check_string ())
4840 i
.disp_operands
= 0;
4843 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4844 optimize_encoding ();
4846 if (!process_suffix ())
4849 /* Update operand types. */
4850 for (j
= 0; j
< i
.operands
; j
++)
4851 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4853 /* Make still unresolved immediate matches conform to size of immediate
4854 given in i.suffix. */
4855 if (!finalize_imm ())
4858 if (i
.types
[0].bitfield
.imm1
)
4859 i
.imm_operands
= 0; /* kludge for shift insns. */
4861 /* We only need to check those implicit registers for instructions
4862 with 3 operands or less. */
4863 if (i
.operands
<= 3)
4864 for (j
= 0; j
< i
.operands
; j
++)
4865 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4866 && !i
.types
[j
].bitfield
.xmmword
)
4869 /* For insns with operands there are more diddles to do to the opcode. */
4872 if (!process_operands ())
4875 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4877 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4878 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4881 if (is_any_vex_encoding (&i
.tm
))
4883 if (!cpu_arch_flags
.bitfield
.cpui286
)
4885 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4890 /* Check for explicit REX prefix. */
4891 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
4893 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
4897 if (i
.tm
.opcode_modifier
.vex
)
4898 build_vex_prefix (t
);
4900 build_evex_prefix ();
4902 /* The individual REX.RXBW bits got consumed. */
4903 i
.rex
&= REX_OPCODE
;
4906 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4907 instructions may define INT_OPCODE as well, so avoid this corner
4908 case for those instructions that use MODRM. */
4909 if (i
.tm
.base_opcode
== INT_OPCODE
4910 && !i
.tm
.opcode_modifier
.modrm
4911 && i
.op
[0].imms
->X_add_number
== 3)
4913 i
.tm
.base_opcode
= INT3_OPCODE
;
4917 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4918 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4919 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4920 && i
.op
[0].disps
->X_op
== O_constant
)
4922 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4923 the absolute address given by the constant. Since ix86 jumps and
4924 calls are pc relative, we need to generate a reloc. */
4925 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4926 i
.op
[0].disps
->X_op
= O_symbol
;
4929 /* For 8 bit registers we need an empty rex prefix. Also if the
4930 instruction already has a prefix, we need to convert old
4931 registers to new ones. */
4933 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4934 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4935 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4936 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4937 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4938 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4943 i
.rex
|= REX_OPCODE
;
4944 for (x
= 0; x
< 2; x
++)
4946 /* Look for 8 bit operand that uses old registers. */
4947 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4948 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4950 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4951 /* In case it is "hi" register, give up. */
4952 if (i
.op
[x
].regs
->reg_num
> 3)
4953 as_bad (_("can't encode register '%s%s' in an "
4954 "instruction requiring REX prefix."),
4955 register_prefix
, i
.op
[x
].regs
->reg_name
);
4957 /* Otherwise it is equivalent to the extended register.
4958 Since the encoding doesn't change this is merely
4959 cosmetic cleanup for debug output. */
4961 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4966 if (i
.rex
== 0 && i
.rex_encoding
)
4968 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4969 that uses legacy register. If it is "hi" register, don't add
4970 the REX_OPCODE byte. */
4972 for (x
= 0; x
< 2; x
++)
4973 if (i
.types
[x
].bitfield
.class == Reg
4974 && i
.types
[x
].bitfield
.byte
4975 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4976 && i
.op
[x
].regs
->reg_num
> 3)
4978 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4979 i
.rex_encoding
= FALSE
;
4988 add_prefix (REX_OPCODE
| i
.rex
);
4990 insert_lfence_before ();
4992 /* We are ready to output the insn. */
4995 insert_lfence_after ();
4997 last_insn
.seg
= now_seg
;
4999 if (i
.tm
.opcode_modifier
.isprefix
)
5001 last_insn
.kind
= last_insn_prefix
;
5002 last_insn
.name
= i
.tm
.name
;
5003 last_insn
.file
= as_where (&last_insn
.line
);
5006 last_insn
.kind
= last_insn_other
;
5010 parse_insn (char *line
, char *mnemonic
)
5013 char *token_start
= l
;
5016 const insn_template
*t
;
5022 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5027 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5029 as_bad (_("no such instruction: `%s'"), token_start
);
5034 if (!is_space_char (*l
)
5035 && *l
!= END_OF_INSN
5037 || (*l
!= PREFIX_SEPARATOR
5040 as_bad (_("invalid character %s in mnemonic"),
5041 output_invalid (*l
));
5044 if (token_start
== l
)
5046 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5047 as_bad (_("expecting prefix; got nothing"));
5049 as_bad (_("expecting mnemonic; got nothing"));
5053 /* Look up instruction (or prefix) via hash table. */
5054 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5056 if (*l
!= END_OF_INSN
5057 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5058 && current_templates
5059 && current_templates
->start
->opcode_modifier
.isprefix
)
5061 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5063 as_bad ((flag_code
!= CODE_64BIT
5064 ? _("`%s' is only supported in 64-bit mode")
5065 : _("`%s' is not supported in 64-bit mode")),
5066 current_templates
->start
->name
);
5069 /* If we are in 16-bit mode, do not allow addr16 or data16.
5070 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5071 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5072 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5073 && flag_code
!= CODE_64BIT
5074 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5075 ^ (flag_code
== CODE_16BIT
)))
5077 as_bad (_("redundant %s prefix"),
5078 current_templates
->start
->name
);
5081 if (current_templates
->start
->opcode_length
== 0)
5083 /* Handle pseudo prefixes. */
5084 switch (current_templates
->start
->base_opcode
)
5088 i
.disp_encoding
= disp_encoding_8bit
;
5092 i
.disp_encoding
= disp_encoding_32bit
;
5096 i
.dir_encoding
= dir_encoding_load
;
5100 i
.dir_encoding
= dir_encoding_store
;
5104 i
.vec_encoding
= vex_encoding_vex
;
5108 i
.vec_encoding
= vex_encoding_vex3
;
5112 i
.vec_encoding
= vex_encoding_evex
;
5116 i
.rex_encoding
= TRUE
;
5120 i
.no_optimize
= TRUE
;
5128 /* Add prefix, checking for repeated prefixes. */
5129 switch (add_prefix (current_templates
->start
->base_opcode
))
5134 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5135 i
.notrack_prefix
= current_templates
->start
->name
;
5138 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5139 i
.hle_prefix
= current_templates
->start
->name
;
5140 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5141 i
.bnd_prefix
= current_templates
->start
->name
;
5143 i
.rep_prefix
= current_templates
->start
->name
;
5149 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5156 if (!current_templates
)
5158 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5159 Check if we should swap operand or force 32bit displacement in
5161 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5162 i
.dir_encoding
= dir_encoding_swap
;
5163 else if (mnem_p
- 3 == dot_p
5166 i
.disp_encoding
= disp_encoding_8bit
;
5167 else if (mnem_p
- 4 == dot_p
5171 i
.disp_encoding
= disp_encoding_32bit
;
5176 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5179 if (!current_templates
)
5182 if (mnem_p
> mnemonic
)
5184 /* See if we can get a match by trimming off a suffix. */
5187 case WORD_MNEM_SUFFIX
:
5188 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5189 i
.suffix
= SHORT_MNEM_SUFFIX
;
5192 case BYTE_MNEM_SUFFIX
:
5193 case QWORD_MNEM_SUFFIX
:
5194 i
.suffix
= mnem_p
[-1];
5196 current_templates
= (const templates
*) hash_find (op_hash
,
5199 case SHORT_MNEM_SUFFIX
:
5200 case LONG_MNEM_SUFFIX
:
5203 i
.suffix
= mnem_p
[-1];
5205 current_templates
= (const templates
*) hash_find (op_hash
,
5214 if (intel_float_operand (mnemonic
) == 1)
5215 i
.suffix
= SHORT_MNEM_SUFFIX
;
5217 i
.suffix
= LONG_MNEM_SUFFIX
;
5219 current_templates
= (const templates
*) hash_find (op_hash
,
5226 if (!current_templates
)
5228 as_bad (_("no such instruction: `%s'"), token_start
);
5233 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5234 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5236 /* Check for a branch hint. We allow ",pt" and ",pn" for
5237 predict taken and predict not taken respectively.
5238 I'm not sure that branch hints actually do anything on loop
5239 and jcxz insns (JumpByte) for current Pentium4 chips. They
5240 may work in the future and it doesn't hurt to accept them
5242 if (l
[0] == ',' && l
[1] == 'p')
5246 if (!add_prefix (DS_PREFIX_OPCODE
))
5250 else if (l
[2] == 'n')
5252 if (!add_prefix (CS_PREFIX_OPCODE
))
5258 /* Any other comma loses. */
5261 as_bad (_("invalid character %s in mnemonic"),
5262 output_invalid (*l
));
5266 /* Check if instruction is supported on specified architecture. */
5268 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5270 supported
|= cpu_flags_match (t
);
5271 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5273 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5274 as_warn (_("use .code16 to ensure correct addressing mode"));
5280 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5281 as_bad (flag_code
== CODE_64BIT
5282 ? _("`%s' is not supported in 64-bit mode")
5283 : _("`%s' is only supported in 64-bit mode"),
5284 current_templates
->start
->name
);
5286 as_bad (_("`%s' is not supported on `%s%s'"),
5287 current_templates
->start
->name
,
5288 cpu_arch_name
? cpu_arch_name
: default_arch
,
5289 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5295 parse_operands (char *l
, const char *mnemonic
)
5299 /* 1 if operand is pending after ','. */
5300 unsigned int expecting_operand
= 0;
5302 /* Non-zero if operand parens not balanced. */
5303 unsigned int paren_not_balanced
;
5305 while (*l
!= END_OF_INSN
)
5307 /* Skip optional white space before operand. */
5308 if (is_space_char (*l
))
5310 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5312 as_bad (_("invalid character %s before operand %d"),
5313 output_invalid (*l
),
5317 token_start
= l
; /* After white space. */
5318 paren_not_balanced
= 0;
5319 while (paren_not_balanced
|| *l
!= ',')
5321 if (*l
== END_OF_INSN
)
5323 if (paren_not_balanced
)
5326 as_bad (_("unbalanced parenthesis in operand %d."),
5329 as_bad (_("unbalanced brackets in operand %d."),
5334 break; /* we are done */
5336 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5338 as_bad (_("invalid character %s in operand %d"),
5339 output_invalid (*l
),
5346 ++paren_not_balanced
;
5348 --paren_not_balanced
;
5353 ++paren_not_balanced
;
5355 --paren_not_balanced
;
5359 if (l
!= token_start
)
5360 { /* Yes, we've read in another operand. */
5361 unsigned int operand_ok
;
5362 this_operand
= i
.operands
++;
5363 if (i
.operands
> MAX_OPERANDS
)
5365 as_bad (_("spurious operands; (%d operands/instruction max)"),
5369 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5370 /* Now parse operand adding info to 'i' as we go along. */
5371 END_STRING_AND_SAVE (l
);
5373 if (i
.mem_operands
> 1)
5375 as_bad (_("too many memory references for `%s'"),
5382 i386_intel_operand (token_start
,
5383 intel_float_operand (mnemonic
));
5385 operand_ok
= i386_att_operand (token_start
);
5387 RESTORE_END_STRING (l
);
5393 if (expecting_operand
)
5395 expecting_operand_after_comma
:
5396 as_bad (_("expecting operand after ','; got nothing"));
5401 as_bad (_("expecting operand before ','; got nothing"));
5406 /* Now *l must be either ',' or END_OF_INSN. */
5409 if (*++l
== END_OF_INSN
)
5411 /* Just skip it, if it's \n complain. */
5412 goto expecting_operand_after_comma
;
5414 expecting_operand
= 1;
5421 swap_2_operands (int xchg1
, int xchg2
)
5423 union i386_op temp_op
;
5424 i386_operand_type temp_type
;
5425 unsigned int temp_flags
;
5426 enum bfd_reloc_code_real temp_reloc
;
5428 temp_type
= i
.types
[xchg2
];
5429 i
.types
[xchg2
] = i
.types
[xchg1
];
5430 i
.types
[xchg1
] = temp_type
;
5432 temp_flags
= i
.flags
[xchg2
];
5433 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5434 i
.flags
[xchg1
] = temp_flags
;
5436 temp_op
= i
.op
[xchg2
];
5437 i
.op
[xchg2
] = i
.op
[xchg1
];
5438 i
.op
[xchg1
] = temp_op
;
5440 temp_reloc
= i
.reloc
[xchg2
];
5441 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5442 i
.reloc
[xchg1
] = temp_reloc
;
5446 if (i
.mask
->operand
== xchg1
)
5447 i
.mask
->operand
= xchg2
;
5448 else if (i
.mask
->operand
== xchg2
)
5449 i
.mask
->operand
= xchg1
;
5453 if (i
.broadcast
->operand
== xchg1
)
5454 i
.broadcast
->operand
= xchg2
;
5455 else if (i
.broadcast
->operand
== xchg2
)
5456 i
.broadcast
->operand
= xchg1
;
5460 if (i
.rounding
->operand
== xchg1
)
5461 i
.rounding
->operand
= xchg2
;
5462 else if (i
.rounding
->operand
== xchg2
)
5463 i
.rounding
->operand
= xchg1
;
5468 swap_operands (void)
5474 swap_2_operands (1, i
.operands
- 2);
5478 swap_2_operands (0, i
.operands
- 1);
5484 if (i
.mem_operands
== 2)
5486 const seg_entry
*temp_seg
;
5487 temp_seg
= i
.seg
[0];
5488 i
.seg
[0] = i
.seg
[1];
5489 i
.seg
[1] = temp_seg
;
5493 /* Try to ensure constant immediates are represented in the smallest
5498 char guess_suffix
= 0;
5502 guess_suffix
= i
.suffix
;
5503 else if (i
.reg_operands
)
5505 /* Figure out a suffix from the last register operand specified.
5506 We can't do this properly yet, i.e. excluding special register
5507 instances, but the following works for instructions with
5508 immediates. In any case, we can't set i.suffix yet. */
5509 for (op
= i
.operands
; --op
>= 0;)
5510 if (i
.types
[op
].bitfield
.class != Reg
)
5512 else if (i
.types
[op
].bitfield
.byte
)
5514 guess_suffix
= BYTE_MNEM_SUFFIX
;
5517 else if (i
.types
[op
].bitfield
.word
)
5519 guess_suffix
= WORD_MNEM_SUFFIX
;
5522 else if (i
.types
[op
].bitfield
.dword
)
5524 guess_suffix
= LONG_MNEM_SUFFIX
;
5527 else if (i
.types
[op
].bitfield
.qword
)
5529 guess_suffix
= QWORD_MNEM_SUFFIX
;
5533 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5534 guess_suffix
= WORD_MNEM_SUFFIX
;
5536 for (op
= i
.operands
; --op
>= 0;)
5537 if (operand_type_check (i
.types
[op
], imm
))
5539 switch (i
.op
[op
].imms
->X_op
)
5542 /* If a suffix is given, this operand may be shortened. */
5543 switch (guess_suffix
)
5545 case LONG_MNEM_SUFFIX
:
5546 i
.types
[op
].bitfield
.imm32
= 1;
5547 i
.types
[op
].bitfield
.imm64
= 1;
5549 case WORD_MNEM_SUFFIX
:
5550 i
.types
[op
].bitfield
.imm16
= 1;
5551 i
.types
[op
].bitfield
.imm32
= 1;
5552 i
.types
[op
].bitfield
.imm32s
= 1;
5553 i
.types
[op
].bitfield
.imm64
= 1;
5555 case BYTE_MNEM_SUFFIX
:
5556 i
.types
[op
].bitfield
.imm8
= 1;
5557 i
.types
[op
].bitfield
.imm8s
= 1;
5558 i
.types
[op
].bitfield
.imm16
= 1;
5559 i
.types
[op
].bitfield
.imm32
= 1;
5560 i
.types
[op
].bitfield
.imm32s
= 1;
5561 i
.types
[op
].bitfield
.imm64
= 1;
5565 /* If this operand is at most 16 bits, convert it
5566 to a signed 16 bit number before trying to see
5567 whether it will fit in an even smaller size.
5568 This allows a 16-bit operand such as $0xffe0 to
5569 be recognised as within Imm8S range. */
5570 if ((i
.types
[op
].bitfield
.imm16
)
5571 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5573 i
.op
[op
].imms
->X_add_number
=
5574 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5577 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5578 if ((i
.types
[op
].bitfield
.imm32
)
5579 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5582 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5583 ^ ((offsetT
) 1 << 31))
5584 - ((offsetT
) 1 << 31));
5588 = operand_type_or (i
.types
[op
],
5589 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5591 /* We must avoid matching of Imm32 templates when 64bit
5592 only immediate is available. */
5593 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5594 i
.types
[op
].bitfield
.imm32
= 0;
5601 /* Symbols and expressions. */
5603 /* Convert symbolic operand to proper sizes for matching, but don't
5604 prevent matching a set of insns that only supports sizes other
5605 than those matching the insn suffix. */
5607 i386_operand_type mask
, allowed
;
5608 const insn_template
*t
;
5610 operand_type_set (&mask
, 0);
5611 operand_type_set (&allowed
, 0);
5613 for (t
= current_templates
->start
;
5614 t
< current_templates
->end
;
5617 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5618 allowed
= operand_type_and (allowed
, anyimm
);
5620 switch (guess_suffix
)
5622 case QWORD_MNEM_SUFFIX
:
5623 mask
.bitfield
.imm64
= 1;
5624 mask
.bitfield
.imm32s
= 1;
5626 case LONG_MNEM_SUFFIX
:
5627 mask
.bitfield
.imm32
= 1;
5629 case WORD_MNEM_SUFFIX
:
5630 mask
.bitfield
.imm16
= 1;
5632 case BYTE_MNEM_SUFFIX
:
5633 mask
.bitfield
.imm8
= 1;
5638 allowed
= operand_type_and (mask
, allowed
);
5639 if (!operand_type_all_zero (&allowed
))
5640 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5647 /* Try to use the smallest displacement type too. */
5649 optimize_disp (void)
5653 for (op
= i
.operands
; --op
>= 0;)
5654 if (operand_type_check (i
.types
[op
], disp
))
5656 if (i
.op
[op
].disps
->X_op
== O_constant
)
5658 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5660 if (i
.types
[op
].bitfield
.disp16
5661 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5663 /* If this operand is at most 16 bits, convert
5664 to a signed 16 bit number and don't use 64bit
5666 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5667 i
.types
[op
].bitfield
.disp64
= 0;
5670 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5671 if (i
.types
[op
].bitfield
.disp32
5672 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5674 /* If this operand is at most 32 bits, convert
5675 to a signed 32 bit number and don't use 64bit
5677 op_disp
&= (((offsetT
) 2 << 31) - 1);
5678 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5679 i
.types
[op
].bitfield
.disp64
= 0;
5682 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5684 i
.types
[op
].bitfield
.disp8
= 0;
5685 i
.types
[op
].bitfield
.disp16
= 0;
5686 i
.types
[op
].bitfield
.disp32
= 0;
5687 i
.types
[op
].bitfield
.disp32s
= 0;
5688 i
.types
[op
].bitfield
.disp64
= 0;
5692 else if (flag_code
== CODE_64BIT
)
5694 if (fits_in_signed_long (op_disp
))
5696 i
.types
[op
].bitfield
.disp64
= 0;
5697 i
.types
[op
].bitfield
.disp32s
= 1;
5699 if (i
.prefix
[ADDR_PREFIX
]
5700 && fits_in_unsigned_long (op_disp
))
5701 i
.types
[op
].bitfield
.disp32
= 1;
5703 if ((i
.types
[op
].bitfield
.disp32
5704 || i
.types
[op
].bitfield
.disp32s
5705 || i
.types
[op
].bitfield
.disp16
)
5706 && fits_in_disp8 (op_disp
))
5707 i
.types
[op
].bitfield
.disp8
= 1;
5709 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5710 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5712 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5713 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5714 i
.types
[op
].bitfield
.disp8
= 0;
5715 i
.types
[op
].bitfield
.disp16
= 0;
5716 i
.types
[op
].bitfield
.disp32
= 0;
5717 i
.types
[op
].bitfield
.disp32s
= 0;
5718 i
.types
[op
].bitfield
.disp64
= 0;
5721 /* We only support 64bit displacement on constants. */
5722 i
.types
[op
].bitfield
.disp64
= 0;
5726 /* Return 1 if there is a match in broadcast bytes between operand
5727 GIVEN and instruction template T. */
5730 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5732 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5733 && i
.types
[given
].bitfield
.byte
)
5734 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5735 && i
.types
[given
].bitfield
.word
)
5736 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5737 && i
.types
[given
].bitfield
.dword
)
5738 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5739 && i
.types
[given
].bitfield
.qword
));
5742 /* Check if operands are valid for the instruction. */
5745 check_VecOperands (const insn_template
*t
)
5750 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5751 any one operand are implicity requiring AVX512VL support if the actual
5752 operand size is YMMword or XMMword. Since this function runs after
5753 template matching, there's no need to check for YMMword/XMMword in
5755 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5756 if (!cpu_flags_all_zero (&cpu
)
5757 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5758 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5760 for (op
= 0; op
< t
->operands
; ++op
)
5762 if (t
->operand_types
[op
].bitfield
.zmmword
5763 && (i
.types
[op
].bitfield
.ymmword
5764 || i
.types
[op
].bitfield
.xmmword
))
5766 i
.error
= unsupported
;
5772 /* Without VSIB byte, we can't have a vector register for index. */
5773 if (!t
->opcode_modifier
.sib
5775 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5776 || i
.index_reg
->reg_type
.bitfield
.ymmword
5777 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5779 i
.error
= unsupported_vector_index_register
;
5783 /* Check if default mask is allowed. */
5784 if (t
->opcode_modifier
.nodefmask
5785 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5787 i
.error
= no_default_mask
;
5791 /* For VSIB byte, we need a vector register for index, and all vector
5792 registers must be distinct. */
5793 if (t
->opcode_modifier
.sib
)
5796 || !((t
->opcode_modifier
.sib
== VECSIB128
5797 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5798 || (t
->opcode_modifier
.sib
== VECSIB256
5799 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5800 || (t
->opcode_modifier
.sib
== VECSIB512
5801 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5803 i
.error
= invalid_vsib_address
;
5807 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5808 if (i
.reg_operands
== 2 && !i
.mask
)
5810 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5811 gas_assert (i
.types
[0].bitfield
.xmmword
5812 || i
.types
[0].bitfield
.ymmword
);
5813 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5814 gas_assert (i
.types
[2].bitfield
.xmmword
5815 || i
.types
[2].bitfield
.ymmword
);
5816 if (operand_check
== check_none
)
5818 if (register_number (i
.op
[0].regs
)
5819 != register_number (i
.index_reg
)
5820 && register_number (i
.op
[2].regs
)
5821 != register_number (i
.index_reg
)
5822 && register_number (i
.op
[0].regs
)
5823 != register_number (i
.op
[2].regs
))
5825 if (operand_check
== check_error
)
5827 i
.error
= invalid_vector_register_set
;
5830 as_warn (_("mask, index, and destination registers should be distinct"));
5832 else if (i
.reg_operands
== 1 && i
.mask
)
5834 if (i
.types
[1].bitfield
.class == RegSIMD
5835 && (i
.types
[1].bitfield
.xmmword
5836 || i
.types
[1].bitfield
.ymmword
5837 || i
.types
[1].bitfield
.zmmword
)
5838 && (register_number (i
.op
[1].regs
)
5839 == register_number (i
.index_reg
)))
5841 if (operand_check
== check_error
)
5843 i
.error
= invalid_vector_register_set
;
5846 if (operand_check
!= check_none
)
5847 as_warn (_("index and destination registers should be distinct"));
5852 /* Check if broadcast is supported by the instruction and is applied
5853 to the memory operand. */
5856 i386_operand_type type
, overlap
;
5858 /* Check if specified broadcast is supported in this instruction,
5859 and its broadcast bytes match the memory operand. */
5860 op
= i
.broadcast
->operand
;
5861 if (!t
->opcode_modifier
.broadcast
5862 || !(i
.flags
[op
] & Operand_Mem
)
5863 || (!i
.types
[op
].bitfield
.unspecified
5864 && !match_broadcast_size (t
, op
)))
5867 i
.error
= unsupported_broadcast
;
5871 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5872 * i
.broadcast
->type
);
5873 operand_type_set (&type
, 0);
5874 switch (i
.broadcast
->bytes
)
5877 type
.bitfield
.word
= 1;
5880 type
.bitfield
.dword
= 1;
5883 type
.bitfield
.qword
= 1;
5886 type
.bitfield
.xmmword
= 1;
5889 type
.bitfield
.ymmword
= 1;
5892 type
.bitfield
.zmmword
= 1;
5898 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5899 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5900 && t
->operand_types
[op
].bitfield
.byte
5901 + t
->operand_types
[op
].bitfield
.word
5902 + t
->operand_types
[op
].bitfield
.dword
5903 + t
->operand_types
[op
].bitfield
.qword
> 1)
5905 overlap
.bitfield
.xmmword
= 0;
5906 overlap
.bitfield
.ymmword
= 0;
5907 overlap
.bitfield
.zmmword
= 0;
5909 if (operand_type_all_zero (&overlap
))
5912 if (t
->opcode_modifier
.checkregsize
)
5916 type
.bitfield
.baseindex
= 1;
5917 for (j
= 0; j
< i
.operands
; ++j
)
5920 && !operand_type_register_match(i
.types
[j
],
5921 t
->operand_types
[j
],
5923 t
->operand_types
[op
]))
5928 /* If broadcast is supported in this instruction, we need to check if
5929 operand of one-element size isn't specified without broadcast. */
5930 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5932 /* Find memory operand. */
5933 for (op
= 0; op
< i
.operands
; op
++)
5934 if (i
.flags
[op
] & Operand_Mem
)
5936 gas_assert (op
< i
.operands
);
5937 /* Check size of the memory operand. */
5938 if (match_broadcast_size (t
, op
))
5940 i
.error
= broadcast_needed
;
5945 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5947 /* Check if requested masking is supported. */
5950 switch (t
->opcode_modifier
.masking
)
5954 case MERGING_MASKING
:
5955 if (i
.mask
->zeroing
)
5958 i
.error
= unsupported_masking
;
5962 case DYNAMIC_MASKING
:
5963 /* Memory destinations allow only merging masking. */
5964 if (i
.mask
->zeroing
&& i
.mem_operands
)
5966 /* Find memory operand. */
5967 for (op
= 0; op
< i
.operands
; op
++)
5968 if (i
.flags
[op
] & Operand_Mem
)
5970 gas_assert (op
< i
.operands
);
5971 if (op
== i
.operands
- 1)
5973 i
.error
= unsupported_masking
;
5983 /* Check if masking is applied to dest operand. */
5984 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5986 i
.error
= mask_not_on_destination
;
5993 if (!t
->opcode_modifier
.sae
5994 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5996 i
.error
= unsupported_rc_sae
;
5999 /* If the instruction has several immediate operands and one of
6000 them is rounding, the rounding operand should be the last
6001 immediate operand. */
6002 if (i
.imm_operands
> 1
6003 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6005 i
.error
= rc_sae_operand_not_last_imm
;
6010 /* Check the special Imm4 cases; must be the first operand. */
6011 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6013 if (i
.op
[0].imms
->X_op
!= O_constant
6014 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6020 /* Turn off Imm<N> so that update_imm won't complain. */
6021 operand_type_set (&i
.types
[0], 0);
6024 /* Check vector Disp8 operand. */
6025 if (t
->opcode_modifier
.disp8memshift
6026 && i
.disp_encoding
!= disp_encoding_32bit
)
6029 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6030 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6031 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6034 const i386_operand_type
*type
= NULL
;
6037 for (op
= 0; op
< i
.operands
; op
++)
6038 if (i
.flags
[op
] & Operand_Mem
)
6040 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6041 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6042 else if (t
->operand_types
[op
].bitfield
.xmmword
6043 + t
->operand_types
[op
].bitfield
.ymmword
6044 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6045 type
= &t
->operand_types
[op
];
6046 else if (!i
.types
[op
].bitfield
.unspecified
)
6047 type
= &i
.types
[op
];
6049 else if (i
.types
[op
].bitfield
.class == RegSIMD
6050 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6052 if (i
.types
[op
].bitfield
.zmmword
)
6054 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6056 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6062 if (type
->bitfield
.zmmword
)
6064 else if (type
->bitfield
.ymmword
)
6066 else if (type
->bitfield
.xmmword
)
6070 /* For the check in fits_in_disp8(). */
6071 if (i
.memshift
== 0)
6075 for (op
= 0; op
< i
.operands
; op
++)
6076 if (operand_type_check (i
.types
[op
], disp
)
6077 && i
.op
[op
].disps
->X_op
== O_constant
)
6079 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6081 i
.types
[op
].bitfield
.disp8
= 1;
6084 i
.types
[op
].bitfield
.disp8
= 0;
6093 /* Check if encoding requirements are met by the instruction. */
6096 VEX_check_encoding (const insn_template
*t
)
6098 if (i
.vec_encoding
== vex_encoding_error
)
6100 i
.error
= unsupported
;
6104 if (i
.vec_encoding
== vex_encoding_evex
)
6106 /* This instruction must be encoded with EVEX prefix. */
6107 if (!is_evex_encoding (t
))
6109 i
.error
= unsupported
;
6115 if (!t
->opcode_modifier
.vex
)
6117 /* This instruction template doesn't have VEX prefix. */
6118 if (i
.vec_encoding
!= vex_encoding_default
)
6120 i
.error
= unsupported
;
6129 static const insn_template
*
6130 match_template (char mnem_suffix
)
6132 /* Points to template once we've found it. */
6133 const insn_template
*t
;
6134 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6135 i386_operand_type overlap4
;
6136 unsigned int found_reverse_match
;
6137 i386_opcode_modifier suffix_check
;
6138 i386_operand_type operand_types
[MAX_OPERANDS
];
6139 int addr_prefix_disp
;
6140 unsigned int j
, size_match
, check_register
;
6141 enum i386_error specific_error
= 0;
6143 #if MAX_OPERANDS != 5
6144 # error "MAX_OPERANDS must be 5."
6147 found_reverse_match
= 0;
6148 addr_prefix_disp
= -1;
6150 /* Prepare for mnemonic suffix check. */
6151 memset (&suffix_check
, 0, sizeof (suffix_check
));
6152 switch (mnem_suffix
)
6154 case BYTE_MNEM_SUFFIX
:
6155 suffix_check
.no_bsuf
= 1;
6157 case WORD_MNEM_SUFFIX
:
6158 suffix_check
.no_wsuf
= 1;
6160 case SHORT_MNEM_SUFFIX
:
6161 suffix_check
.no_ssuf
= 1;
6163 case LONG_MNEM_SUFFIX
:
6164 suffix_check
.no_lsuf
= 1;
6166 case QWORD_MNEM_SUFFIX
:
6167 suffix_check
.no_qsuf
= 1;
6170 /* NB: In Intel syntax, normally we can check for memory operand
6171 size when there is no mnemonic suffix. But jmp and call have
6172 2 different encodings with Dword memory operand size, one with
6173 No_ldSuf and the other without. i.suffix is set to
6174 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6175 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6176 suffix_check
.no_ldsuf
= 1;
6179 /* Must have right number of operands. */
6180 i
.error
= number_of_operands_mismatch
;
6182 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6184 addr_prefix_disp
= -1;
6185 found_reverse_match
= 0;
6187 if (i
.operands
!= t
->operands
)
6190 /* Check processor support. */
6191 i
.error
= unsupported
;
6192 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6195 /* Check AT&T mnemonic. */
6196 i
.error
= unsupported_with_intel_mnemonic
;
6197 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6200 /* Check AT&T/Intel syntax. */
6201 i
.error
= unsupported_syntax
;
6202 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6203 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6206 /* Check Intel64/AMD64 ISA. */
6210 /* Default: Don't accept Intel64. */
6211 if (t
->opcode_modifier
.isa64
== INTEL64
)
6215 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6216 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6220 /* -mintel64: Don't accept AMD64. */
6221 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6226 /* Check the suffix. */
6227 i
.error
= invalid_instruction_suffix
;
6228 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6229 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6230 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6231 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6232 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6233 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6236 size_match
= operand_size_match (t
);
6240 /* This is intentionally not
6242 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6244 as the case of a missing * on the operand is accepted (perhaps with
6245 a warning, issued further down). */
6246 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6248 i
.error
= operand_type_mismatch
;
6252 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6253 operand_types
[j
] = t
->operand_types
[j
];
6255 /* In general, don't allow
6256 - 64-bit operands outside of 64-bit mode,
6257 - 32-bit operands on pre-386. */
6258 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6259 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6260 && flag_code
!= CODE_64BIT
6261 && (t
->base_opcode
!= 0x0fc7
6262 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
6263 || (i
.suffix
== LONG_MNEM_SUFFIX
6264 && !cpu_arch_flags
.bitfield
.cpui386
))
6266 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6267 && !intel_float_operand (t
->name
))
6268 : intel_float_operand (t
->name
) != 2)
6269 && (t
->operands
== i
.imm_operands
6270 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6271 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6272 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6273 || (operand_types
[j
].bitfield
.class != RegMMX
6274 && operand_types
[j
].bitfield
.class != RegSIMD
6275 && operand_types
[j
].bitfield
.class != RegMask
))
6276 && !t
->opcode_modifier
.sib
)
6279 /* Do not verify operands when there are none. */
6282 if (VEX_check_encoding (t
))
6284 specific_error
= i
.error
;
6288 /* We've found a match; break out of loop. */
6292 if (!t
->opcode_modifier
.jump
6293 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6295 /* There should be only one Disp operand. */
6296 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6297 if (operand_type_check (operand_types
[j
], disp
))
6299 if (j
< MAX_OPERANDS
)
6301 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6303 addr_prefix_disp
= j
;
6305 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6306 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6310 override
= !override
;
6313 if (operand_types
[j
].bitfield
.disp32
6314 && operand_types
[j
].bitfield
.disp16
)
6316 operand_types
[j
].bitfield
.disp16
= override
;
6317 operand_types
[j
].bitfield
.disp32
= !override
;
6319 operand_types
[j
].bitfield
.disp32s
= 0;
6320 operand_types
[j
].bitfield
.disp64
= 0;
6324 if (operand_types
[j
].bitfield
.disp32s
6325 || operand_types
[j
].bitfield
.disp64
)
6327 operand_types
[j
].bitfield
.disp64
&= !override
;
6328 operand_types
[j
].bitfield
.disp32s
&= !override
;
6329 operand_types
[j
].bitfield
.disp32
= override
;
6331 operand_types
[j
].bitfield
.disp16
= 0;
6337 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6338 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6341 /* We check register size if needed. */
6342 if (t
->opcode_modifier
.checkregsize
)
6344 check_register
= (1 << t
->operands
) - 1;
6346 check_register
&= ~(1 << i
.broadcast
->operand
);
6351 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6352 switch (t
->operands
)
6355 if (!operand_type_match (overlap0
, i
.types
[0]))
6359 /* xchg %eax, %eax is a special case. It is an alias for nop
6360 only in 32bit mode and we can use opcode 0x90. In 64bit
6361 mode, we can't use 0x90 for xchg %eax, %eax since it should
6362 zero-extend %eax to %rax. */
6363 if (flag_code
== CODE_64BIT
6364 && t
->base_opcode
== 0x90
6365 && i
.types
[0].bitfield
.instance
== Accum
6366 && i
.types
[0].bitfield
.dword
6367 && i
.types
[1].bitfield
.instance
== Accum
6368 && i
.types
[1].bitfield
.dword
)
6370 /* xrelease mov %eax, <disp> is another special case. It must not
6371 match the accumulator-only encoding of mov. */
6372 if (flag_code
!= CODE_64BIT
6374 && t
->base_opcode
== 0xa0
6375 && i
.types
[0].bitfield
.instance
== Accum
6376 && (i
.flags
[1] & Operand_Mem
))
6381 if (!(size_match
& MATCH_STRAIGHT
))
6383 /* Reverse direction of operands if swapping is possible in the first
6384 place (operands need to be symmetric) and
6385 - the load form is requested, and the template is a store form,
6386 - the store form is requested, and the template is a load form,
6387 - the non-default (swapped) form is requested. */
6388 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6389 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6390 && !operand_type_all_zero (&overlap1
))
6391 switch (i
.dir_encoding
)
6393 case dir_encoding_load
:
6394 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6395 || t
->opcode_modifier
.regmem
)
6399 case dir_encoding_store
:
6400 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6401 && !t
->opcode_modifier
.regmem
)
6405 case dir_encoding_swap
:
6408 case dir_encoding_default
:
6411 /* If we want store form, we skip the current load. */
6412 if ((i
.dir_encoding
== dir_encoding_store
6413 || i
.dir_encoding
== dir_encoding_swap
)
6414 && i
.mem_operands
== 0
6415 && t
->opcode_modifier
.load
)
6420 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6421 if (!operand_type_match (overlap0
, i
.types
[0])
6422 || !operand_type_match (overlap1
, i
.types
[1])
6423 || ((check_register
& 3) == 3
6424 && !operand_type_register_match (i
.types
[0],
6429 /* Check if other direction is valid ... */
6430 if (!t
->opcode_modifier
.d
)
6434 if (!(size_match
& MATCH_REVERSE
))
6436 /* Try reversing direction of operands. */
6437 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6438 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6439 if (!operand_type_match (overlap0
, i
.types
[0])
6440 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6442 && !operand_type_register_match (i
.types
[0],
6443 operand_types
[i
.operands
- 1],
6444 i
.types
[i
.operands
- 1],
6447 /* Does not match either direction. */
6450 /* found_reverse_match holds which of D or FloatR
6452 if (!t
->opcode_modifier
.d
)
6453 found_reverse_match
= 0;
6454 else if (operand_types
[0].bitfield
.tbyte
)
6455 found_reverse_match
= Opcode_FloatD
;
6456 else if (operand_types
[0].bitfield
.xmmword
6457 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6458 || operand_types
[0].bitfield
.class == RegMMX
6459 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6460 || is_any_vex_encoding(t
))
6461 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6462 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6464 found_reverse_match
= Opcode_D
;
6465 if (t
->opcode_modifier
.floatr
)
6466 found_reverse_match
|= Opcode_FloatR
;
6470 /* Found a forward 2 operand match here. */
6471 switch (t
->operands
)
6474 overlap4
= operand_type_and (i
.types
[4],
6478 overlap3
= operand_type_and (i
.types
[3],
6482 overlap2
= operand_type_and (i
.types
[2],
6487 switch (t
->operands
)
6490 if (!operand_type_match (overlap4
, i
.types
[4])
6491 || !operand_type_register_match (i
.types
[3],
6498 if (!operand_type_match (overlap3
, i
.types
[3])
6499 || ((check_register
& 0xa) == 0xa
6500 && !operand_type_register_match (i
.types
[1],
6504 || ((check_register
& 0xc) == 0xc
6505 && !operand_type_register_match (i
.types
[2],
6512 /* Here we make use of the fact that there are no
6513 reverse match 3 operand instructions. */
6514 if (!operand_type_match (overlap2
, i
.types
[2])
6515 || ((check_register
& 5) == 5
6516 && !operand_type_register_match (i
.types
[0],
6520 || ((check_register
& 6) == 6
6521 && !operand_type_register_match (i
.types
[1],
6529 /* Found either forward/reverse 2, 3 or 4 operand match here:
6530 slip through to break. */
6533 /* Check if vector operands are valid. */
6534 if (check_VecOperands (t
))
6536 specific_error
= i
.error
;
6540 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6541 if (VEX_check_encoding (t
))
6543 specific_error
= i
.error
;
6547 /* We've found a match; break out of loop. */
6551 if (t
== current_templates
->end
)
6553 /* We found no match. */
6554 const char *err_msg
;
6555 switch (specific_error
? specific_error
: i
.error
)
6559 case operand_size_mismatch
:
6560 err_msg
= _("operand size mismatch");
6562 case operand_type_mismatch
:
6563 err_msg
= _("operand type mismatch");
6565 case register_type_mismatch
:
6566 err_msg
= _("register type mismatch");
6568 case number_of_operands_mismatch
:
6569 err_msg
= _("number of operands mismatch");
6571 case invalid_instruction_suffix
:
6572 err_msg
= _("invalid instruction suffix");
6575 err_msg
= _("constant doesn't fit in 4 bits");
6577 case unsupported_with_intel_mnemonic
:
6578 err_msg
= _("unsupported with Intel mnemonic");
6580 case unsupported_syntax
:
6581 err_msg
= _("unsupported syntax");
6584 as_bad (_("unsupported instruction `%s'"),
6585 current_templates
->start
->name
);
6587 case invalid_vsib_address
:
6588 err_msg
= _("invalid VSIB address");
6590 case invalid_vector_register_set
:
6591 err_msg
= _("mask, index, and destination registers must be distinct");
6593 case unsupported_vector_index_register
:
6594 err_msg
= _("unsupported vector index register");
6596 case unsupported_broadcast
:
6597 err_msg
= _("unsupported broadcast");
6599 case broadcast_needed
:
6600 err_msg
= _("broadcast is needed for operand of such type");
6602 case unsupported_masking
:
6603 err_msg
= _("unsupported masking");
6605 case mask_not_on_destination
:
6606 err_msg
= _("mask not on destination operand");
6608 case no_default_mask
:
6609 err_msg
= _("default mask isn't allowed");
6611 case unsupported_rc_sae
:
6612 err_msg
= _("unsupported static rounding/sae");
6614 case rc_sae_operand_not_last_imm
:
6616 err_msg
= _("RC/SAE operand must precede immediate operands");
6618 err_msg
= _("RC/SAE operand must follow immediate operands");
6620 case invalid_register_operand
:
6621 err_msg
= _("invalid register operand");
6624 as_bad (_("%s for `%s'"), err_msg
,
6625 current_templates
->start
->name
);
6629 if (!quiet_warnings
)
6632 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6633 as_warn (_("indirect %s without `*'"), t
->name
);
6635 if (t
->opcode_modifier
.isprefix
6636 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6638 /* Warn them that a data or address size prefix doesn't
6639 affect assembly of the next line of code. */
6640 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6644 /* Copy the template we found. */
6647 if (addr_prefix_disp
!= -1)
6648 i
.tm
.operand_types
[addr_prefix_disp
]
6649 = operand_types
[addr_prefix_disp
];
6651 if (found_reverse_match
)
6653 /* If we found a reverse match we must alter the opcode direction
6654 bit and clear/flip the regmem modifier one. found_reverse_match
6655 holds bits to change (different for int & float insns). */
6657 i
.tm
.base_opcode
^= found_reverse_match
;
6659 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6660 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6662 /* Certain SIMD insns have their load forms specified in the opcode
6663 table, and hence we need to _set_ RegMem instead of clearing it.
6664 We need to avoid setting the bit though on insns like KMOVW. */
6665 i
.tm
.opcode_modifier
.regmem
6666 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6667 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6668 && !i
.tm
.opcode_modifier
.regmem
;
6677 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6678 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6680 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6682 as_bad (_("`%s' operand %u must use `%ses' segment"),
6684 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6689 /* There's only ever one segment override allowed per instruction.
6690 This instruction possibly has a legal segment override on the
6691 second operand, so copy the segment to where non-string
6692 instructions store it, allowing common code. */
6693 i
.seg
[op
] = i
.seg
[1];
6699 process_suffix (void)
6701 /* If matched instruction specifies an explicit instruction mnemonic
6703 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6704 i
.suffix
= WORD_MNEM_SUFFIX
;
6705 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6706 i
.suffix
= LONG_MNEM_SUFFIX
;
6707 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6708 i
.suffix
= QWORD_MNEM_SUFFIX
;
6709 else if (i
.reg_operands
6710 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6711 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6713 unsigned int numop
= i
.operands
;
6715 /* movsx/movzx want only their source operand considered here, for the
6716 ambiguity checking below. The suffix will be replaced afterwards
6717 to represent the destination (register). */
6718 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6719 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6722 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6723 if (i
.tm
.base_opcode
== 0xf20f38f0
6724 && i
.tm
.operand_types
[1].bitfield
.qword
)
6727 /* If there's no instruction mnemonic suffix we try to invent one
6728 based on GPR operands. */
6731 /* We take i.suffix from the last register operand specified,
6732 Destination register type is more significant than source
6733 register type. crc32 in SSE4.2 prefers source register
6735 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6738 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6739 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6741 if (i
.types
[op
].bitfield
.class != Reg
)
6743 if (i
.types
[op
].bitfield
.byte
)
6744 i
.suffix
= BYTE_MNEM_SUFFIX
;
6745 else if (i
.types
[op
].bitfield
.word
)
6746 i
.suffix
= WORD_MNEM_SUFFIX
;
6747 else if (i
.types
[op
].bitfield
.dword
)
6748 i
.suffix
= LONG_MNEM_SUFFIX
;
6749 else if (i
.types
[op
].bitfield
.qword
)
6750 i
.suffix
= QWORD_MNEM_SUFFIX
;
6756 /* As an exception, movsx/movzx silently default to a byte source
6758 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6759 && !i
.suffix
&& !intel_syntax
)
6760 i
.suffix
= BYTE_MNEM_SUFFIX
;
6762 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6765 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6766 && i
.tm
.opcode_modifier
.no_bsuf
)
6768 else if (!check_byte_reg ())
6771 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6774 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6775 && i
.tm
.opcode_modifier
.no_lsuf
6776 && !i
.tm
.opcode_modifier
.todword
6777 && !i
.tm
.opcode_modifier
.toqword
)
6779 else if (!check_long_reg ())
6782 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6785 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6786 && i
.tm
.opcode_modifier
.no_qsuf
6787 && !i
.tm
.opcode_modifier
.todword
6788 && !i
.tm
.opcode_modifier
.toqword
)
6790 else if (!check_qword_reg ())
6793 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6796 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6797 && i
.tm
.opcode_modifier
.no_wsuf
)
6799 else if (!check_word_reg ())
6802 else if (intel_syntax
6803 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6804 /* Do nothing if the instruction is going to ignore the prefix. */
6809 /* Undo the movsx/movzx change done above. */
6812 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6815 i
.suffix
= stackop_size
;
6816 if (stackop_size
== LONG_MNEM_SUFFIX
)
6818 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6819 .code16gcc directive to support 16-bit mode with
6820 32-bit address. For IRET without a suffix, generate
6821 16-bit IRET (opcode 0xcf) to return from an interrupt
6823 if (i
.tm
.base_opcode
== 0xcf)
6825 i
.suffix
= WORD_MNEM_SUFFIX
;
6826 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6828 /* Warn about changed behavior for segment register push/pop. */
6829 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6830 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6835 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6836 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6837 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6838 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6839 && i
.tm
.extension_opcode
<= 3)))
6844 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6846 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6847 || i
.tm
.opcode_modifier
.no_lsuf
)
6848 i
.suffix
= QWORD_MNEM_SUFFIX
;
6853 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6854 i
.suffix
= LONG_MNEM_SUFFIX
;
6857 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6858 i
.suffix
= WORD_MNEM_SUFFIX
;
6864 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6865 /* Also cover lret/retf/iret in 64-bit mode. */
6866 || (flag_code
== CODE_64BIT
6867 && !i
.tm
.opcode_modifier
.no_lsuf
6868 && !i
.tm
.opcode_modifier
.no_qsuf
))
6869 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6870 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6871 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
6872 /* Accept FLDENV et al without suffix. */
6873 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6875 unsigned int suffixes
, evex
= 0;
6877 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6878 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6880 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6882 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6884 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6886 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6889 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6890 also suitable for AT&T syntax mode, it was requested that this be
6891 restricted to just Intel syntax. */
6892 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6896 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6898 if (is_evex_encoding (&i
.tm
)
6899 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6901 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6902 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6903 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6904 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6905 if (!i
.tm
.opcode_modifier
.evex
6906 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6907 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6910 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6911 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6912 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6915 /* Any properly sized operand disambiguates the insn. */
6916 if (i
.types
[op
].bitfield
.xmmword
6917 || i
.types
[op
].bitfield
.ymmword
6918 || i
.types
[op
].bitfield
.zmmword
)
6920 suffixes
&= ~(7 << 6);
6925 if ((i
.flags
[op
] & Operand_Mem
)
6926 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6928 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6930 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6932 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6934 if (is_evex_encoding (&i
.tm
))
6940 /* Are multiple suffixes / operand sizes allowed? */
6941 if (suffixes
& (suffixes
- 1))
6944 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6945 || operand_check
== check_error
))
6947 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6950 if (operand_check
== check_error
)
6952 as_bad (_("no instruction mnemonic suffix given and "
6953 "no register operands; can't size `%s'"), i
.tm
.name
);
6956 if (operand_check
== check_warning
)
6957 as_warn (_("%s; using default for `%s'"),
6959 ? _("ambiguous operand size")
6960 : _("no instruction mnemonic suffix given and "
6961 "no register operands"),
6964 if (i
.tm
.opcode_modifier
.floatmf
)
6965 i
.suffix
= SHORT_MNEM_SUFFIX
;
6966 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
6967 || (i
.tm
.base_opcode
== 0x63
6968 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6969 /* handled below */;
6971 i
.tm
.opcode_modifier
.evex
= evex
;
6972 else if (flag_code
== CODE_16BIT
)
6973 i
.suffix
= WORD_MNEM_SUFFIX
;
6974 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6975 i
.suffix
= LONG_MNEM_SUFFIX
;
6977 i
.suffix
= QWORD_MNEM_SUFFIX
;
6981 if ((i
.tm
.base_opcode
| 8) == 0xfbe
6982 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6984 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6985 In AT&T syntax, if there is no suffix (warned about above), the default
6986 will be byte extension. */
6987 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
6988 i
.tm
.base_opcode
|= 1;
6990 /* For further processing, the suffix should represent the destination
6991 (register). This is already the case when one was used with
6992 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6993 no suffix to begin with. */
6994 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
6996 if (i
.types
[1].bitfield
.word
)
6997 i
.suffix
= WORD_MNEM_SUFFIX
;
6998 else if (i
.types
[1].bitfield
.qword
)
6999 i
.suffix
= QWORD_MNEM_SUFFIX
;
7001 i
.suffix
= LONG_MNEM_SUFFIX
;
7003 i
.tm
.opcode_modifier
.w
= 0;
7007 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7008 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7009 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7011 /* Change the opcode based on the operand size given by i.suffix. */
7014 /* Size floating point instruction. */
7015 case LONG_MNEM_SUFFIX
:
7016 if (i
.tm
.opcode_modifier
.floatmf
)
7018 i
.tm
.base_opcode
^= 4;
7022 case WORD_MNEM_SUFFIX
:
7023 case QWORD_MNEM_SUFFIX
:
7024 /* It's not a byte, select word/dword operation. */
7025 if (i
.tm
.opcode_modifier
.w
)
7028 i
.tm
.base_opcode
|= 8;
7030 i
.tm
.base_opcode
|= 1;
7033 case SHORT_MNEM_SUFFIX
:
7034 /* Now select between word & dword operations via the operand
7035 size prefix, except for instructions that will ignore this
7037 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7038 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7039 && !i
.tm
.opcode_modifier
.floatmf
7040 && !is_any_vex_encoding (&i
.tm
)
7041 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7042 || (flag_code
== CODE_64BIT
7043 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7045 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7047 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7048 prefix
= ADDR_PREFIX_OPCODE
;
7050 if (!add_prefix (prefix
))
7054 /* Set mode64 for an operand. */
7055 if (i
.suffix
== QWORD_MNEM_SUFFIX
7056 && flag_code
== CODE_64BIT
7057 && !i
.tm
.opcode_modifier
.norex64
7058 && !i
.tm
.opcode_modifier
.vexw
7059 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7061 && ! (i
.operands
== 2
7062 && i
.tm
.base_opcode
== 0x90
7063 && i
.tm
.extension_opcode
== None
7064 && i
.types
[0].bitfield
.instance
== Accum
7065 && i
.types
[0].bitfield
.qword
7066 && i
.types
[1].bitfield
.instance
== Accum
7067 && i
.types
[1].bitfield
.qword
))
7073 /* Select word/dword/qword operation with explict data sizing prefix
7074 when there are no suitable register operands. */
7075 if (i
.tm
.opcode_modifier
.w
7076 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7078 || (i
.reg_operands
== 1
7080 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7082 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7083 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7085 || i
.tm
.base_opcode
== 0xf20f38f0))))
7086 i
.tm
.base_opcode
|= 1;
7090 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7092 gas_assert (!i
.suffix
);
7093 gas_assert (i
.reg_operands
);
7095 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7098 /* The address size override prefix changes the size of the
7100 if (flag_code
== CODE_64BIT
7101 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7103 as_bad (_("16-bit addressing unavailable for `%s'"),
7108 if ((flag_code
== CODE_32BIT
7109 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7110 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7111 && !add_prefix (ADDR_PREFIX_OPCODE
))
7116 /* Check invalid register operand when the address size override
7117 prefix changes the size of register operands. */
7119 enum { need_word
, need_dword
, need_qword
} need
;
7121 if (flag_code
== CODE_32BIT
)
7122 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7123 else if (i
.prefix
[ADDR_PREFIX
])
7126 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7128 for (op
= 0; op
< i
.operands
; op
++)
7130 if (i
.types
[op
].bitfield
.class != Reg
)
7136 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7140 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7144 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7149 as_bad (_("invalid register operand size for `%s'"),
7160 check_byte_reg (void)
7164 for (op
= i
.operands
; --op
>= 0;)
7166 /* Skip non-register operands. */
7167 if (i
.types
[op
].bitfield
.class != Reg
)
7170 /* If this is an eight bit register, it's OK. If it's the 16 or
7171 32 bit version of an eight bit register, we will just use the
7172 low portion, and that's OK too. */
7173 if (i
.types
[op
].bitfield
.byte
)
7176 /* I/O port address operands are OK too. */
7177 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7178 && i
.tm
.operand_types
[op
].bitfield
.word
)
7181 /* crc32 only wants its source operand checked here. */
7182 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
7185 /* Any other register is bad. */
7186 as_bad (_("`%s%s' not allowed with `%s%c'"),
7187 register_prefix
, i
.op
[op
].regs
->reg_name
,
7188 i
.tm
.name
, i
.suffix
);
7195 check_long_reg (void)
7199 for (op
= i
.operands
; --op
>= 0;)
7200 /* Skip non-register operands. */
7201 if (i
.types
[op
].bitfield
.class != Reg
)
7203 /* Reject eight bit registers, except where the template requires
7204 them. (eg. movzb) */
7205 else if (i
.types
[op
].bitfield
.byte
7206 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7207 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7208 && (i
.tm
.operand_types
[op
].bitfield
.word
7209 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7211 as_bad (_("`%s%s' not allowed with `%s%c'"),
7213 i
.op
[op
].regs
->reg_name
,
7218 /* Error if the e prefix on a general reg is missing. */
7219 else if (i
.types
[op
].bitfield
.word
7220 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7221 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7222 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7224 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7225 register_prefix
, i
.op
[op
].regs
->reg_name
,
7229 /* Warn if the r prefix on a general reg is present. */
7230 else if (i
.types
[op
].bitfield
.qword
7231 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7232 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7233 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7236 && i
.tm
.opcode_modifier
.toqword
7237 && i
.types
[0].bitfield
.class != RegSIMD
)
7239 /* Convert to QWORD. We want REX byte. */
7240 i
.suffix
= QWORD_MNEM_SUFFIX
;
7244 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7245 register_prefix
, i
.op
[op
].regs
->reg_name
,
7254 check_qword_reg (void)
7258 for (op
= i
.operands
; --op
>= 0; )
7259 /* Skip non-register operands. */
7260 if (i
.types
[op
].bitfield
.class != Reg
)
7262 /* Reject eight bit registers, except where the template requires
7263 them. (eg. movzb) */
7264 else if (i
.types
[op
].bitfield
.byte
7265 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7266 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7267 && (i
.tm
.operand_types
[op
].bitfield
.word
7268 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7270 as_bad (_("`%s%s' not allowed with `%s%c'"),
7272 i
.op
[op
].regs
->reg_name
,
7277 /* Warn if the r prefix on a general reg is missing. */
7278 else if ((i
.types
[op
].bitfield
.word
7279 || i
.types
[op
].bitfield
.dword
)
7280 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7281 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7282 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7284 /* Prohibit these changes in the 64bit mode, since the
7285 lowering is more complicated. */
7287 && i
.tm
.opcode_modifier
.todword
7288 && i
.types
[0].bitfield
.class != RegSIMD
)
7290 /* Convert to DWORD. We don't want REX byte. */
7291 i
.suffix
= LONG_MNEM_SUFFIX
;
7295 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7296 register_prefix
, i
.op
[op
].regs
->reg_name
,
7305 check_word_reg (void)
7308 for (op
= i
.operands
; --op
>= 0;)
7309 /* Skip non-register operands. */
7310 if (i
.types
[op
].bitfield
.class != Reg
)
7312 /* Reject eight bit registers, except where the template requires
7313 them. (eg. movzb) */
7314 else if (i
.types
[op
].bitfield
.byte
7315 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7316 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7317 && (i
.tm
.operand_types
[op
].bitfield
.word
7318 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7320 as_bad (_("`%s%s' not allowed with `%s%c'"),
7322 i
.op
[op
].regs
->reg_name
,
7327 /* Error if the e or r prefix on a general reg is present. */
7328 else if ((i
.types
[op
].bitfield
.dword
7329 || i
.types
[op
].bitfield
.qword
)
7330 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7331 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7332 && i
.tm
.operand_types
[op
].bitfield
.word
)
7334 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7335 register_prefix
, i
.op
[op
].regs
->reg_name
,
7343 update_imm (unsigned int j
)
7345 i386_operand_type overlap
= i
.types
[j
];
7346 if ((overlap
.bitfield
.imm8
7347 || overlap
.bitfield
.imm8s
7348 || overlap
.bitfield
.imm16
7349 || overlap
.bitfield
.imm32
7350 || overlap
.bitfield
.imm32s
7351 || overlap
.bitfield
.imm64
)
7352 && !operand_type_equal (&overlap
, &imm8
)
7353 && !operand_type_equal (&overlap
, &imm8s
)
7354 && !operand_type_equal (&overlap
, &imm16
)
7355 && !operand_type_equal (&overlap
, &imm32
)
7356 && !operand_type_equal (&overlap
, &imm32s
)
7357 && !operand_type_equal (&overlap
, &imm64
))
7361 i386_operand_type temp
;
7363 operand_type_set (&temp
, 0);
7364 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7366 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7367 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7369 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7370 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7371 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7373 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7374 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7377 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7380 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7381 || operand_type_equal (&overlap
, &imm16_32
)
7382 || operand_type_equal (&overlap
, &imm16_32s
))
7384 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7389 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7390 overlap
= operand_type_and (overlap
, imm32s
);
7391 else if (i
.prefix
[DATA_PREFIX
])
7392 overlap
= operand_type_and (overlap
,
7393 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7394 if (!operand_type_equal (&overlap
, &imm8
)
7395 && !operand_type_equal (&overlap
, &imm8s
)
7396 && !operand_type_equal (&overlap
, &imm16
)
7397 && !operand_type_equal (&overlap
, &imm32
)
7398 && !operand_type_equal (&overlap
, &imm32s
)
7399 && !operand_type_equal (&overlap
, &imm64
))
7401 as_bad (_("no instruction mnemonic suffix given; "
7402 "can't determine immediate size"));
7406 i
.types
[j
] = overlap
;
7416 /* Update the first 2 immediate operands. */
7417 n
= i
.operands
> 2 ? 2 : i
.operands
;
7420 for (j
= 0; j
< n
; j
++)
7421 if (update_imm (j
) == 0)
7424 /* The 3rd operand can't be immediate operand. */
7425 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7432 process_operands (void)
7434 /* Default segment register this instruction will use for memory
7435 accesses. 0 means unknown. This is only for optimizing out
7436 unnecessary segment overrides. */
7437 const seg_entry
*default_seg
= 0;
7439 if (i
.tm
.opcode_modifier
.sse2avx
)
7441 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7443 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7444 i
.prefix
[REX_PREFIX
] = 0;
7447 /* ImmExt should be processed after SSE2AVX. */
7448 else if (i
.tm
.opcode_modifier
.immext
)
7451 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7453 unsigned int dupl
= i
.operands
;
7454 unsigned int dest
= dupl
- 1;
7457 /* The destination must be an xmm register. */
7458 gas_assert (i
.reg_operands
7459 && MAX_OPERANDS
> dupl
7460 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7462 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7463 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7465 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7467 /* Keep xmm0 for instructions with VEX prefix and 3
7469 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7470 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7475 /* We remove the first xmm0 and keep the number of
7476 operands unchanged, which in fact duplicates the
7478 for (j
= 1; j
< i
.operands
; j
++)
7480 i
.op
[j
- 1] = i
.op
[j
];
7481 i
.types
[j
- 1] = i
.types
[j
];
7482 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7483 i
.flags
[j
- 1] = i
.flags
[j
];
7487 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7489 gas_assert ((MAX_OPERANDS
- 1) > dupl
7490 && (i
.tm
.opcode_modifier
.vexsources
7493 /* Add the implicit xmm0 for instructions with VEX prefix
7495 for (j
= i
.operands
; j
> 0; j
--)
7497 i
.op
[j
] = i
.op
[j
- 1];
7498 i
.types
[j
] = i
.types
[j
- 1];
7499 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7500 i
.flags
[j
] = i
.flags
[j
- 1];
7503 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7504 i
.types
[0] = regxmm
;
7505 i
.tm
.operand_types
[0] = regxmm
;
7508 i
.reg_operands
+= 2;
7513 i
.op
[dupl
] = i
.op
[dest
];
7514 i
.types
[dupl
] = i
.types
[dest
];
7515 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7516 i
.flags
[dupl
] = i
.flags
[dest
];
7525 i
.op
[dupl
] = i
.op
[dest
];
7526 i
.types
[dupl
] = i
.types
[dest
];
7527 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7528 i
.flags
[dupl
] = i
.flags
[dest
];
7531 if (i
.tm
.opcode_modifier
.immext
)
7534 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7535 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7539 for (j
= 1; j
< i
.operands
; j
++)
7541 i
.op
[j
- 1] = i
.op
[j
];
7542 i
.types
[j
- 1] = i
.types
[j
];
7544 /* We need to adjust fields in i.tm since they are used by
7545 build_modrm_byte. */
7546 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7548 i
.flags
[j
- 1] = i
.flags
[j
];
7555 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7557 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7559 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7560 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7561 regnum
= register_number (i
.op
[1].regs
);
7562 first_reg_in_group
= regnum
& ~3;
7563 last_reg_in_group
= first_reg_in_group
+ 3;
7564 if (regnum
!= first_reg_in_group
)
7565 as_warn (_("source register `%s%s' implicitly denotes"
7566 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7567 register_prefix
, i
.op
[1].regs
->reg_name
,
7568 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7569 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7572 else if (i
.tm
.opcode_modifier
.regkludge
)
7574 /* The imul $imm, %reg instruction is converted into
7575 imul $imm, %reg, %reg, and the clr %reg instruction
7576 is converted into xor %reg, %reg. */
7578 unsigned int first_reg_op
;
7580 if (operand_type_check (i
.types
[0], reg
))
7584 /* Pretend we saw the extra register operand. */
7585 gas_assert (i
.reg_operands
== 1
7586 && i
.op
[first_reg_op
+ 1].regs
== 0);
7587 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7588 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7593 if (i
.tm
.opcode_modifier
.modrm
)
7595 /* The opcode is completed (modulo i.tm.extension_opcode which
7596 must be put into the modrm byte). Now, we make the modrm and
7597 index base bytes based on all the info we've collected. */
7599 default_seg
= build_modrm_byte ();
7601 else if (i
.types
[0].bitfield
.class == SReg
)
7603 if (flag_code
!= CODE_64BIT
7604 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7605 && i
.op
[0].regs
->reg_num
== 1
7606 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7607 && i
.op
[0].regs
->reg_num
< 4)
7609 as_bad (_("you can't `%s %s%s'"),
7610 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7613 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7615 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7616 i
.tm
.opcode_length
= 2;
7618 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7620 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7624 else if (i
.tm
.opcode_modifier
.isstring
)
7626 /* For the string instructions that allow a segment override
7627 on one of their operands, the default segment is ds. */
7630 else if (i
.short_form
)
7632 /* The register or float register operand is in operand
7634 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7636 /* Register goes in low 3 bits of opcode. */
7637 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7638 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7640 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7642 /* Warn about some common errors, but press on regardless.
7643 The first case can be generated by gcc (<= 2.8.1). */
7644 if (i
.operands
== 2)
7646 /* Reversed arguments on faddp, fsubp, etc. */
7647 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7648 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7649 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7653 /* Extraneous `l' suffix on fp insn. */
7654 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7655 register_prefix
, i
.op
[0].regs
->reg_name
);
7660 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7661 && i
.tm
.base_opcode
== 0x8d /* lea */
7662 && !is_any_vex_encoding(&i
.tm
))
7664 if (!quiet_warnings
)
7665 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7669 i
.prefix
[SEG_PREFIX
] = 0;
7673 /* If a segment was explicitly specified, and the specified segment
7674 is neither the default nor the one already recorded from a prefix,
7675 use an opcode prefix to select it. If we never figured out what
7676 the default segment is, then default_seg will be zero at this
7677 point, and the specified segment prefix will always be used. */
7679 && i
.seg
[0] != default_seg
7680 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7682 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7688 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7689 bfd_boolean do_sse2avx
)
7691 if (r
->reg_flags
& RegRex
)
7693 if (i
.rex
& rex_bit
)
7694 as_bad (_("same type of prefix used twice"));
7697 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7699 gas_assert (i
.vex
.register_specifier
== r
);
7700 i
.vex
.register_specifier
+= 8;
7703 if (r
->reg_flags
& RegVRex
)
7707 static const seg_entry
*
7708 build_modrm_byte (void)
7710 const seg_entry
*default_seg
= 0;
7711 unsigned int source
, dest
;
7714 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7717 unsigned int nds
, reg_slot
;
7720 dest
= i
.operands
- 1;
7723 /* There are 2 kinds of instructions:
7724 1. 5 operands: 4 register operands or 3 register operands
7725 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7726 VexW0 or VexW1. The destination must be either XMM, YMM or
7728 2. 4 operands: 4 register operands or 3 register operands
7729 plus 1 memory operand, with VexXDS. */
7730 gas_assert ((i
.reg_operands
== 4
7731 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7732 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7733 && i
.tm
.opcode_modifier
.vexw
7734 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7736 /* If VexW1 is set, the first non-immediate operand is the source and
7737 the second non-immediate one is encoded in the immediate operand. */
7738 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7740 source
= i
.imm_operands
;
7741 reg_slot
= i
.imm_operands
+ 1;
7745 source
= i
.imm_operands
+ 1;
7746 reg_slot
= i
.imm_operands
;
7749 if (i
.imm_operands
== 0)
7751 /* When there is no immediate operand, generate an 8bit
7752 immediate operand to encode the first operand. */
7753 exp
= &im_expressions
[i
.imm_operands
++];
7754 i
.op
[i
.operands
].imms
= exp
;
7755 i
.types
[i
.operands
] = imm8
;
7758 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7759 exp
->X_op
= O_constant
;
7760 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7761 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7765 gas_assert (i
.imm_operands
== 1);
7766 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7767 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7769 /* Turn on Imm8 again so that output_imm will generate it. */
7770 i
.types
[0].bitfield
.imm8
= 1;
7772 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7773 i
.op
[0].imms
->X_add_number
7774 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7775 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7778 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7779 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7784 /* i.reg_operands MUST be the number of real register operands;
7785 implicit registers do not count. If there are 3 register
7786 operands, it must be a instruction with VexNDS. For a
7787 instruction with VexNDD, the destination register is encoded
7788 in VEX prefix. If there are 4 register operands, it must be
7789 a instruction with VEX prefix and 3 sources. */
7790 if (i
.mem_operands
== 0
7791 && ((i
.reg_operands
== 2
7792 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7793 || (i
.reg_operands
== 3
7794 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7795 || (i
.reg_operands
== 4 && vex_3_sources
)))
7803 /* When there are 3 operands, one of them may be immediate,
7804 which may be the first or the last operand. Otherwise,
7805 the first operand must be shift count register (cl) or it
7806 is an instruction with VexNDS. */
7807 gas_assert (i
.imm_operands
== 1
7808 || (i
.imm_operands
== 0
7809 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7810 || (i
.types
[0].bitfield
.instance
== RegC
7811 && i
.types
[0].bitfield
.byte
))));
7812 if (operand_type_check (i
.types
[0], imm
)
7813 || (i
.types
[0].bitfield
.instance
== RegC
7814 && i
.types
[0].bitfield
.byte
))
7820 /* When there are 4 operands, the first two must be 8bit
7821 immediate operands. The source operand will be the 3rd
7824 For instructions with VexNDS, if the first operand
7825 an imm8, the source operand is the 2nd one. If the last
7826 operand is imm8, the source operand is the first one. */
7827 gas_assert ((i
.imm_operands
== 2
7828 && i
.types
[0].bitfield
.imm8
7829 && i
.types
[1].bitfield
.imm8
)
7830 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7831 && i
.imm_operands
== 1
7832 && (i
.types
[0].bitfield
.imm8
7833 || i
.types
[i
.operands
- 1].bitfield
.imm8
7835 if (i
.imm_operands
== 2)
7839 if (i
.types
[0].bitfield
.imm8
)
7846 if (is_evex_encoding (&i
.tm
))
7848 /* For EVEX instructions, when there are 5 operands, the
7849 first one must be immediate operand. If the second one
7850 is immediate operand, the source operand is the 3th
7851 one. If the last one is immediate operand, the source
7852 operand is the 2nd one. */
7853 gas_assert (i
.imm_operands
== 2
7854 && i
.tm
.opcode_modifier
.sae
7855 && operand_type_check (i
.types
[0], imm
));
7856 if (operand_type_check (i
.types
[1], imm
))
7858 else if (operand_type_check (i
.types
[4], imm
))
7872 /* RC/SAE operand could be between DEST and SRC. That happens
7873 when one operand is GPR and the other one is XMM/YMM/ZMM
7875 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7878 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7880 /* For instructions with VexNDS, the register-only source
7881 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7882 register. It is encoded in VEX prefix. */
7884 i386_operand_type op
;
7887 /* Check register-only source operand when two source
7888 operands are swapped. */
7889 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7890 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7898 op
= i
.tm
.operand_types
[vvvv
];
7899 if ((dest
+ 1) >= i
.operands
7900 || ((op
.bitfield
.class != Reg
7901 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7902 && op
.bitfield
.class != RegSIMD
7903 && !operand_type_equal (&op
, ®mask
)))
7905 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7911 /* One of the register operands will be encoded in the i.rm.reg
7912 field, the other in the combined i.rm.mode and i.rm.regmem
7913 fields. If no form of this instruction supports a memory
7914 destination operand, then we assume the source operand may
7915 sometimes be a memory operand and so we need to store the
7916 destination in the i.rm.reg field. */
7917 if (!i
.tm
.opcode_modifier
.regmem
7918 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7920 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7921 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7922 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7923 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7924 i
.has_regmmx
= TRUE
;
7925 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7926 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7928 if (i
.types
[dest
].bitfield
.zmmword
7929 || i
.types
[source
].bitfield
.zmmword
)
7930 i
.has_regzmm
= TRUE
;
7931 else if (i
.types
[dest
].bitfield
.ymmword
7932 || i
.types
[source
].bitfield
.ymmword
)
7933 i
.has_regymm
= TRUE
;
7935 i
.has_regxmm
= TRUE
;
7937 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
7938 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
7942 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7943 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7944 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
7945 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
7947 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7949 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7952 add_prefix (LOCK_PREFIX_OPCODE
);
7956 { /* If it's not 2 reg operands... */
7961 unsigned int fake_zero_displacement
= 0;
7964 for (op
= 0; op
< i
.operands
; op
++)
7965 if (i
.flags
[op
] & Operand_Mem
)
7967 gas_assert (op
< i
.operands
);
7969 if (i
.tm
.opcode_modifier
.sib
)
7971 if (i
.index_reg
->reg_num
== RegIZ
)
7974 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7977 i
.sib
.base
= NO_BASE_REGISTER
;
7978 i
.sib
.scale
= i
.log2_scale_factor
;
7979 i
.types
[op
].bitfield
.disp8
= 0;
7980 i
.types
[op
].bitfield
.disp16
= 0;
7981 i
.types
[op
].bitfield
.disp64
= 0;
7982 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7984 /* Must be 32 bit */
7985 i
.types
[op
].bitfield
.disp32
= 1;
7986 i
.types
[op
].bitfield
.disp32s
= 0;
7990 i
.types
[op
].bitfield
.disp32
= 0;
7991 i
.types
[op
].bitfield
.disp32s
= 1;
7994 i
.sib
.index
= i
.index_reg
->reg_num
;
7995 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
8000 if (i
.base_reg
== 0)
8003 if (!i
.disp_operands
)
8004 fake_zero_displacement
= 1;
8005 if (i
.index_reg
== 0)
8007 i386_operand_type newdisp
;
8009 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8010 /* Operand is just <disp> */
8011 if (flag_code
== CODE_64BIT
)
8013 /* 64bit mode overwrites the 32bit absolute
8014 addressing by RIP relative addressing and
8015 absolute addressing is encoded by one of the
8016 redundant SIB forms. */
8017 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8018 i
.sib
.base
= NO_BASE_REGISTER
;
8019 i
.sib
.index
= NO_INDEX_REGISTER
;
8020 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
8022 else if ((flag_code
== CODE_16BIT
)
8023 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8025 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8030 i
.rm
.regmem
= NO_BASE_REGISTER
;
8033 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8034 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8036 else if (!i
.tm
.opcode_modifier
.sib
)
8038 /* !i.base_reg && i.index_reg */
8039 if (i
.index_reg
->reg_num
== RegIZ
)
8040 i
.sib
.index
= NO_INDEX_REGISTER
;
8042 i
.sib
.index
= i
.index_reg
->reg_num
;
8043 i
.sib
.base
= NO_BASE_REGISTER
;
8044 i
.sib
.scale
= i
.log2_scale_factor
;
8045 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8046 i
.types
[op
].bitfield
.disp8
= 0;
8047 i
.types
[op
].bitfield
.disp16
= 0;
8048 i
.types
[op
].bitfield
.disp64
= 0;
8049 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8051 /* Must be 32 bit */
8052 i
.types
[op
].bitfield
.disp32
= 1;
8053 i
.types
[op
].bitfield
.disp32s
= 0;
8057 i
.types
[op
].bitfield
.disp32
= 0;
8058 i
.types
[op
].bitfield
.disp32s
= 1;
8060 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8064 /* RIP addressing for 64bit mode. */
8065 else if (i
.base_reg
->reg_num
== RegIP
)
8067 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8068 i
.rm
.regmem
= NO_BASE_REGISTER
;
8069 i
.types
[op
].bitfield
.disp8
= 0;
8070 i
.types
[op
].bitfield
.disp16
= 0;
8071 i
.types
[op
].bitfield
.disp32
= 0;
8072 i
.types
[op
].bitfield
.disp32s
= 1;
8073 i
.types
[op
].bitfield
.disp64
= 0;
8074 i
.flags
[op
] |= Operand_PCrel
;
8075 if (! i
.disp_operands
)
8076 fake_zero_displacement
= 1;
8078 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8080 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8081 switch (i
.base_reg
->reg_num
)
8084 if (i
.index_reg
== 0)
8086 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8087 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8091 if (i
.index_reg
== 0)
8094 if (operand_type_check (i
.types
[op
], disp
) == 0)
8096 /* fake (%bp) into 0(%bp) */
8097 i
.types
[op
].bitfield
.disp8
= 1;
8098 fake_zero_displacement
= 1;
8101 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8102 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8104 default: /* (%si) -> 4 or (%di) -> 5 */
8105 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8107 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8109 else /* i.base_reg and 32/64 bit mode */
8111 if (flag_code
== CODE_64BIT
8112 && operand_type_check (i
.types
[op
], disp
))
8114 i
.types
[op
].bitfield
.disp16
= 0;
8115 i
.types
[op
].bitfield
.disp64
= 0;
8116 if (i
.prefix
[ADDR_PREFIX
] == 0)
8118 i
.types
[op
].bitfield
.disp32
= 0;
8119 i
.types
[op
].bitfield
.disp32s
= 1;
8123 i
.types
[op
].bitfield
.disp32
= 1;
8124 i
.types
[op
].bitfield
.disp32s
= 0;
8128 if (!i
.tm
.opcode_modifier
.sib
)
8129 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8130 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8132 i
.sib
.base
= i
.base_reg
->reg_num
;
8133 /* x86-64 ignores REX prefix bit here to avoid decoder
8135 if (!(i
.base_reg
->reg_flags
& RegRex
)
8136 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8137 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8139 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8141 fake_zero_displacement
= 1;
8142 i
.types
[op
].bitfield
.disp8
= 1;
8144 i
.sib
.scale
= i
.log2_scale_factor
;
8145 if (i
.index_reg
== 0)
8147 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8148 /* <disp>(%esp) becomes two byte modrm with no index
8149 register. We've already stored the code for esp
8150 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8151 Any base register besides %esp will not use the
8152 extra modrm byte. */
8153 i
.sib
.index
= NO_INDEX_REGISTER
;
8155 else if (!i
.tm
.opcode_modifier
.sib
)
8157 if (i
.index_reg
->reg_num
== RegIZ
)
8158 i
.sib
.index
= NO_INDEX_REGISTER
;
8160 i
.sib
.index
= i
.index_reg
->reg_num
;
8161 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8162 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8167 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8168 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8172 if (!fake_zero_displacement
8176 fake_zero_displacement
= 1;
8177 if (i
.disp_encoding
== disp_encoding_8bit
)
8178 i
.types
[op
].bitfield
.disp8
= 1;
8180 i
.types
[op
].bitfield
.disp32
= 1;
8182 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8186 if (fake_zero_displacement
)
8188 /* Fakes a zero displacement assuming that i.types[op]
8189 holds the correct displacement size. */
8192 gas_assert (i
.op
[op
].disps
== 0);
8193 exp
= &disp_expressions
[i
.disp_operands
++];
8194 i
.op
[op
].disps
= exp
;
8195 exp
->X_op
= O_constant
;
8196 exp
->X_add_number
= 0;
8197 exp
->X_add_symbol
= (symbolS
*) 0;
8198 exp
->X_op_symbol
= (symbolS
*) 0;
8206 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8208 if (operand_type_check (i
.types
[0], imm
))
8209 i
.vex
.register_specifier
= NULL
;
8212 /* VEX.vvvv encodes one of the sources when the first
8213 operand is not an immediate. */
8214 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8215 i
.vex
.register_specifier
= i
.op
[0].regs
;
8217 i
.vex
.register_specifier
= i
.op
[1].regs
;
8220 /* Destination is a XMM register encoded in the ModRM.reg
8222 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8223 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8226 /* ModRM.rm and VEX.B encodes the other source. */
8227 if (!i
.mem_operands
)
8231 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8232 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8234 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8236 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8240 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8242 i
.vex
.register_specifier
= i
.op
[2].regs
;
8243 if (!i
.mem_operands
)
8246 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8247 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8251 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8252 (if any) based on i.tm.extension_opcode. Again, we must be
8253 careful to make sure that segment/control/debug/test/MMX
8254 registers are coded into the i.rm.reg field. */
8255 else if (i
.reg_operands
)
8258 unsigned int vex_reg
= ~0;
8260 for (op
= 0; op
< i
.operands
; op
++)
8262 if (i
.types
[op
].bitfield
.class == Reg
8263 || i
.types
[op
].bitfield
.class == RegBND
8264 || i
.types
[op
].bitfield
.class == RegMask
8265 || i
.types
[op
].bitfield
.class == SReg
8266 || i
.types
[op
].bitfield
.class == RegCR
8267 || i
.types
[op
].bitfield
.class == RegDR
8268 || i
.types
[op
].bitfield
.class == RegTR
)
8270 if (i
.types
[op
].bitfield
.class == RegSIMD
)
8272 if (i
.types
[op
].bitfield
.zmmword
)
8273 i
.has_regzmm
= TRUE
;
8274 else if (i
.types
[op
].bitfield
.ymmword
)
8275 i
.has_regymm
= TRUE
;
8277 i
.has_regxmm
= TRUE
;
8280 if (i
.types
[op
].bitfield
.class == RegMMX
)
8282 i
.has_regmmx
= TRUE
;
8289 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8291 /* For instructions with VexNDS, the register-only
8292 source operand is encoded in VEX prefix. */
8293 gas_assert (mem
!= (unsigned int) ~0);
8298 gas_assert (op
< i
.operands
);
8302 /* Check register-only source operand when two source
8303 operands are swapped. */
8304 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8305 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8309 gas_assert (mem
== (vex_reg
+ 1)
8310 && op
< i
.operands
);
8315 gas_assert (vex_reg
< i
.operands
);
8319 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8321 /* For instructions with VexNDD, the register destination
8322 is encoded in VEX prefix. */
8323 if (i
.mem_operands
== 0)
8325 /* There is no memory operand. */
8326 gas_assert ((op
+ 2) == i
.operands
);
8331 /* There are only 2 non-immediate operands. */
8332 gas_assert (op
< i
.imm_operands
+ 2
8333 && i
.operands
== i
.imm_operands
+ 2);
8334 vex_reg
= i
.imm_operands
+ 1;
8338 gas_assert (op
< i
.operands
);
8340 if (vex_reg
!= (unsigned int) ~0)
8342 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8344 if ((type
->bitfield
.class != Reg
8345 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8346 && type
->bitfield
.class != RegSIMD
8347 && !operand_type_equal (type
, ®mask
))
8350 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8353 /* Don't set OP operand twice. */
8356 /* If there is an extension opcode to put here, the
8357 register number must be put into the regmem field. */
8358 if (i
.tm
.extension_opcode
!= None
)
8360 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8361 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8362 i
.tm
.opcode_modifier
.sse2avx
);
8366 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8367 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8368 i
.tm
.opcode_modifier
.sse2avx
);
8372 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8373 must set it to 3 to indicate this is a register operand
8374 in the regmem field. */
8375 if (!i
.mem_operands
)
8379 /* Fill in i.rm.reg field with extension opcode (if any). */
8380 if (i
.tm
.extension_opcode
!= None
)
8381 i
.rm
.reg
= i
.tm
.extension_opcode
;
8387 flip_code16 (unsigned int code16
)
8389 gas_assert (i
.tm
.operands
== 1);
8391 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8392 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8393 || i
.tm
.operand_types
[0].bitfield
.disp32s
8394 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8399 output_branch (void)
8405 relax_substateT subtype
;
8409 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8410 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8413 if (i
.prefix
[DATA_PREFIX
] != 0)
8417 code16
^= flip_code16(code16
);
8419 /* Pentium4 branch hints. */
8420 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8421 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8426 if (i
.prefix
[REX_PREFIX
] != 0)
8432 /* BND prefixed jump. */
8433 if (i
.prefix
[BND_PREFIX
] != 0)
8439 if (i
.prefixes
!= 0)
8440 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8442 /* It's always a symbol; End frag & setup for relax.
8443 Make sure there is enough room in this frag for the largest
8444 instruction we may generate in md_convert_frag. This is 2
8445 bytes for the opcode and room for the prefix and largest
8447 frag_grow (prefix
+ 2 + 4);
8448 /* Prefix and 1 opcode byte go in fr_fix. */
8449 p
= frag_more (prefix
+ 1);
8450 if (i
.prefix
[DATA_PREFIX
] != 0)
8451 *p
++ = DATA_PREFIX_OPCODE
;
8452 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8453 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8454 *p
++ = i
.prefix
[SEG_PREFIX
];
8455 if (i
.prefix
[BND_PREFIX
] != 0)
8456 *p
++ = BND_PREFIX_OPCODE
;
8457 if (i
.prefix
[REX_PREFIX
] != 0)
8458 *p
++ = i
.prefix
[REX_PREFIX
];
8459 *p
= i
.tm
.base_opcode
;
8461 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8462 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8463 else if (cpu_arch_flags
.bitfield
.cpui386
)
8464 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8466 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8469 sym
= i
.op
[0].disps
->X_add_symbol
;
8470 off
= i
.op
[0].disps
->X_add_number
;
8472 if (i
.op
[0].disps
->X_op
!= O_constant
8473 && i
.op
[0].disps
->X_op
!= O_symbol
)
8475 /* Handle complex expressions. */
8476 sym
= make_expr_symbol (i
.op
[0].disps
);
8480 /* 1 possible extra opcode + 4 byte displacement go in var part.
8481 Pass reloc in fr_var. */
8482 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8485 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8486 /* Return TRUE iff PLT32 relocation should be used for branching to
8490 need_plt32_p (symbolS
*s
)
8492 /* PLT32 relocation is ELF only. */
8497 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8498 krtld support it. */
8502 /* Since there is no need to prepare for PLT branch on x86-64, we
8503 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8504 be used as a marker for 32-bit PC-relative branches. */
8508 /* Weak or undefined symbol need PLT32 relocation. */
8509 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8512 /* Non-global symbol doesn't need PLT32 relocation. */
8513 if (! S_IS_EXTERNAL (s
))
8516 /* Other global symbols need PLT32 relocation. NB: Symbol with
8517 non-default visibilities are treated as normal global symbol
8518 so that PLT32 relocation can be used as a marker for 32-bit
8519 PC-relative branches. It is useful for linker relaxation. */
8530 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8532 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8534 /* This is a loop or jecxz type instruction. */
8536 if (i
.prefix
[ADDR_PREFIX
] != 0)
8538 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8541 /* Pentium4 branch hints. */
8542 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8543 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8545 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8554 if (flag_code
== CODE_16BIT
)
8557 if (i
.prefix
[DATA_PREFIX
] != 0)
8559 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8561 code16
^= flip_code16(code16
);
8569 /* BND prefixed jump. */
8570 if (i
.prefix
[BND_PREFIX
] != 0)
8572 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8576 if (i
.prefix
[REX_PREFIX
] != 0)
8578 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8582 if (i
.prefixes
!= 0)
8583 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8585 p
= frag_more (i
.tm
.opcode_length
+ size
);
8586 switch (i
.tm
.opcode_length
)
8589 *p
++ = i
.tm
.base_opcode
>> 8;
8592 *p
++ = i
.tm
.base_opcode
;
8598 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8600 && jump_reloc
== NO_RELOC
8601 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8602 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8605 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8607 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8608 i
.op
[0].disps
, 1, jump_reloc
);
8610 /* All jumps handled here are signed, but don't use a signed limit
8611 check for 32 and 16 bit jumps as we want to allow wrap around at
8612 4G and 64k respectively. */
8614 fixP
->fx_signed
= 1;
8618 output_interseg_jump (void)
8626 if (flag_code
== CODE_16BIT
)
8630 if (i
.prefix
[DATA_PREFIX
] != 0)
8637 gas_assert (!i
.prefix
[REX_PREFIX
]);
8643 if (i
.prefixes
!= 0)
8644 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8646 /* 1 opcode; 2 segment; offset */
8647 p
= frag_more (prefix
+ 1 + 2 + size
);
8649 if (i
.prefix
[DATA_PREFIX
] != 0)
8650 *p
++ = DATA_PREFIX_OPCODE
;
8652 if (i
.prefix
[REX_PREFIX
] != 0)
8653 *p
++ = i
.prefix
[REX_PREFIX
];
8655 *p
++ = i
.tm
.base_opcode
;
8656 if (i
.op
[1].imms
->X_op
== O_constant
)
8658 offsetT n
= i
.op
[1].imms
->X_add_number
;
8661 && !fits_in_unsigned_word (n
)
8662 && !fits_in_signed_word (n
))
8664 as_bad (_("16-bit jump out of range"));
8667 md_number_to_chars (p
, n
, size
);
8670 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8671 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8672 if (i
.op
[0].imms
->X_op
!= O_constant
)
8673 as_bad (_("can't handle non absolute segment in `%s'"),
8675 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8678 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8683 asection
*seg
= now_seg
;
8684 subsegT subseg
= now_subseg
;
8686 unsigned int alignment
, align_size_1
;
8687 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8688 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8689 unsigned int padding
;
8691 if (!IS_ELF
|| !x86_used_note
)
8694 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8696 /* The .note.gnu.property section layout:
8698 Field Length Contents
8701 n_descsz 4 The note descriptor size
8702 n_type 4 NT_GNU_PROPERTY_TYPE_0
8704 n_desc n_descsz The program property array
8708 /* Create the .note.gnu.property section. */
8709 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8710 bfd_set_section_flags (sec
,
8717 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8728 bfd_set_section_alignment (sec
, alignment
);
8729 elf_section_type (sec
) = SHT_NOTE
;
8731 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8733 isa_1_descsz_raw
= 4 + 4 + 4;
8734 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8735 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8737 feature_2_descsz_raw
= isa_1_descsz
;
8738 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8740 feature_2_descsz_raw
+= 4 + 4 + 4;
8741 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8742 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8745 descsz
= feature_2_descsz
;
8746 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8747 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8749 /* Write n_namsz. */
8750 md_number_to_chars (p
, (valueT
) 4, 4);
8752 /* Write n_descsz. */
8753 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8756 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8759 memcpy (p
+ 4 * 3, "GNU", 4);
8761 /* Write 4-byte type. */
8762 md_number_to_chars (p
+ 4 * 4,
8763 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8765 /* Write 4-byte data size. */
8766 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8768 /* Write 4-byte data. */
8769 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8771 /* Zero out paddings. */
8772 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8774 memset (p
+ 4 * 7, 0, padding
);
8776 /* Write 4-byte type. */
8777 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8778 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8780 /* Write 4-byte data size. */
8781 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8783 /* Write 4-byte data. */
8784 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8785 (valueT
) x86_feature_2_used
, 4);
8787 /* Zero out paddings. */
8788 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8790 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8792 /* We probably can't restore the current segment, for there likely
8795 subseg_set (seg
, subseg
);
8800 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8801 const char *frag_now_ptr
)
8803 unsigned int len
= 0;
8805 if (start_frag
!= frag_now
)
8807 const fragS
*fr
= start_frag
;
8812 } while (fr
&& fr
!= frag_now
);
8815 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8818 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8819 be macro-fused with conditional jumps.
8820 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8821 or is one of the following format:
8834 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8836 /* No RIP address. */
8837 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8840 /* No VEX/EVEX encoding. */
8841 if (is_any_vex_encoding (&i
.tm
))
8844 /* add, sub without add/sub m, imm. */
8845 if (i
.tm
.base_opcode
<= 5
8846 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8847 || ((i
.tm
.base_opcode
| 3) == 0x83
8848 && (i
.tm
.extension_opcode
== 0x5
8849 || i
.tm
.extension_opcode
== 0x0)))
8851 *mf_cmp_p
= mf_cmp_alu_cmp
;
8852 return !(i
.mem_operands
&& i
.imm_operands
);
8855 /* and without and m, imm. */
8856 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8857 || ((i
.tm
.base_opcode
| 3) == 0x83
8858 && i
.tm
.extension_opcode
== 0x4))
8860 *mf_cmp_p
= mf_cmp_test_and
;
8861 return !(i
.mem_operands
&& i
.imm_operands
);
8864 /* test without test m imm. */
8865 if ((i
.tm
.base_opcode
| 1) == 0x85
8866 || (i
.tm
.base_opcode
| 1) == 0xa9
8867 || ((i
.tm
.base_opcode
| 1) == 0xf7
8868 && i
.tm
.extension_opcode
== 0))
8870 *mf_cmp_p
= mf_cmp_test_and
;
8871 return !(i
.mem_operands
&& i
.imm_operands
);
8874 /* cmp without cmp m, imm. */
8875 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8876 || ((i
.tm
.base_opcode
| 3) == 0x83
8877 && (i
.tm
.extension_opcode
== 0x7)))
8879 *mf_cmp_p
= mf_cmp_alu_cmp
;
8880 return !(i
.mem_operands
&& i
.imm_operands
);
8883 /* inc, dec without inc/dec m. */
8884 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8885 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8886 || ((i
.tm
.base_opcode
| 1) == 0xff
8887 && i
.tm
.extension_opcode
<= 0x1))
8889 *mf_cmp_p
= mf_cmp_incdec
;
8890 return !i
.mem_operands
;
8896 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8899 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8901 /* NB: Don't work with COND_JUMP86 without i386. */
8902 if (!align_branch_power
8903 || now_seg
== absolute_section
8904 || !cpu_arch_flags
.bitfield
.cpui386
8905 || !(align_branch
& align_branch_fused_bit
))
8908 if (maybe_fused_with_jcc_p (mf_cmp_p
))
8910 if (last_insn
.kind
== last_insn_other
8911 || last_insn
.seg
!= now_seg
)
8914 as_warn_where (last_insn
.file
, last_insn
.line
,
8915 _("`%s` skips -malign-branch-boundary on `%s`"),
8916 last_insn
.name
, i
.tm
.name
);
8922 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8925 add_branch_prefix_frag_p (void)
8927 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8928 to PadLock instructions since they include prefixes in opcode. */
8929 if (!align_branch_power
8930 || !align_branch_prefix_size
8931 || now_seg
== absolute_section
8932 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8933 || !cpu_arch_flags
.bitfield
.cpui386
)
8936 /* Don't add prefix if it is a prefix or there is no operand in case
8937 that segment prefix is special. */
8938 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8941 if (last_insn
.kind
== last_insn_other
8942 || last_insn
.seg
!= now_seg
)
8946 as_warn_where (last_insn
.file
, last_insn
.line
,
8947 _("`%s` skips -malign-branch-boundary on `%s`"),
8948 last_insn
.name
, i
.tm
.name
);
8953 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8956 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
8957 enum mf_jcc_kind
*mf_jcc_p
)
8961 /* NB: Don't work with COND_JUMP86 without i386. */
8962 if (!align_branch_power
8963 || now_seg
== absolute_section
8964 || !cpu_arch_flags
.bitfield
.cpui386
)
8969 /* Check for jcc and direct jmp. */
8970 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8972 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8974 *branch_p
= align_branch_jmp
;
8975 add_padding
= align_branch
& align_branch_jmp_bit
;
8979 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
8980 igore the lowest bit. */
8981 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
8982 *branch_p
= align_branch_jcc
;
8983 if ((align_branch
& align_branch_jcc_bit
))
8987 else if (is_any_vex_encoding (&i
.tm
))
8989 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8992 *branch_p
= align_branch_ret
;
8993 if ((align_branch
& align_branch_ret_bit
))
8998 /* Check for indirect jmp, direct and indirect calls. */
8999 if (i
.tm
.base_opcode
== 0xe8)
9002 *branch_p
= align_branch_call
;
9003 if ((align_branch
& align_branch_call_bit
))
9006 else if (i
.tm
.base_opcode
== 0xff
9007 && (i
.tm
.extension_opcode
== 2
9008 || i
.tm
.extension_opcode
== 4))
9010 /* Indirect call and jmp. */
9011 *branch_p
= align_branch_indirect
;
9012 if ((align_branch
& align_branch_indirect_bit
))
9019 && (i
.op
[0].disps
->X_op
== O_symbol
9020 || (i
.op
[0].disps
->X_op
== O_subtract
9021 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9023 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9024 /* No padding to call to global or undefined tls_get_addr. */
9025 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9026 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9032 && last_insn
.kind
!= last_insn_other
9033 && last_insn
.seg
== now_seg
)
9036 as_warn_where (last_insn
.file
, last_insn
.line
,
9037 _("`%s` skips -malign-branch-boundary on `%s`"),
9038 last_insn
.name
, i
.tm
.name
);
9048 fragS
*insn_start_frag
;
9049 offsetT insn_start_off
;
9050 fragS
*fragP
= NULL
;
9051 enum align_branch_kind branch
= align_branch_none
;
9052 /* The initializer is arbitrary just to avoid uninitialized error.
9053 it's actually either assigned in add_branch_padding_frag_p
9054 or never be used. */
9055 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9057 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9058 if (IS_ELF
&& x86_used_note
)
9060 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
9061 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
9062 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
9063 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
9064 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
9065 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
9066 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
9067 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
9068 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
9069 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
9070 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
9071 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
9072 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
9073 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
9074 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9075 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
9076 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
9077 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
9078 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
9079 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
9080 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
9081 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
9082 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
9083 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
9084 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
9085 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
9086 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
9087 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
9088 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
9089 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
9090 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
9091 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
9092 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
9093 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
9094 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
9095 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
9096 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
9097 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
9098 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
9099 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
9100 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
9101 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
9102 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
9103 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
9104 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
9105 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
9106 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
9107 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
9108 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
9109 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
9111 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9112 || i
.tm
.cpu_flags
.bitfield
.cpu287
9113 || i
.tm
.cpu_flags
.bitfield
.cpu387
9114 || i
.tm
.cpu_flags
.bitfield
.cpu687
9115 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9116 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9118 || i
.tm
.base_opcode
== 0xf77 /* emms */
9119 || i
.tm
.base_opcode
== 0xf0e /* femms */
9120 || i
.tm
.base_opcode
== 0xf2a /* cvtpi2ps */
9121 || i
.tm
.base_opcode
== 0x660f2a /* cvtpi2pd */)
9122 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9124 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9126 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9128 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9129 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9130 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9131 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9132 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9133 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9134 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9135 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9136 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9140 /* Tie dwarf2 debug info to the address at the start of the insn.
9141 We can't do this after the insn has been output as the current
9142 frag may have been closed off. eg. by frag_var. */
9143 dwarf2_emit_insn (0);
9145 insn_start_frag
= frag_now
;
9146 insn_start_off
= frag_now_fix ();
9148 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9151 /* Branch can be 8 bytes. Leave some room for prefixes. */
9152 unsigned int max_branch_padding_size
= 14;
9154 /* Align section to boundary. */
9155 record_alignment (now_seg
, align_branch_power
);
9157 /* Make room for padding. */
9158 frag_grow (max_branch_padding_size
);
9160 /* Start of the padding. */
9165 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9166 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9169 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9170 fragP
->tc_frag_data
.branch_type
= branch
;
9171 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9175 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9177 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9178 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9180 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9181 output_interseg_jump ();
9184 /* Output normal instructions here. */
9188 unsigned int prefix
;
9189 enum mf_cmp_kind mf_cmp
;
9192 && (i
.tm
.base_opcode
== 0xfaee8
9193 || i
.tm
.base_opcode
== 0xfaef0
9194 || i
.tm
.base_opcode
== 0xfaef8))
9196 /* Encode lfence, mfence, and sfence as
9197 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9198 offsetT val
= 0x240483f0ULL
;
9200 md_number_to_chars (p
, val
, 5);
9204 /* Some processors fail on LOCK prefix. This options makes
9205 assembler ignore LOCK prefix and serves as a workaround. */
9206 if (omit_lock_prefix
)
9208 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9210 i
.prefix
[LOCK_PREFIX
] = 0;
9214 /* Skip if this is a branch. */
9216 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9218 /* Make room for padding. */
9219 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9224 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9225 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9228 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9229 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9230 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9232 else if (add_branch_prefix_frag_p ())
9234 unsigned int max_prefix_size
= align_branch_prefix_size
;
9236 /* Make room for padding. */
9237 frag_grow (max_prefix_size
);
9242 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9243 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9246 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9249 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9250 don't need the explicit prefix. */
9251 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9253 switch (i
.tm
.opcode_length
)
9256 if (i
.tm
.base_opcode
& 0xff000000)
9258 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
9259 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9260 || prefix
!= REPE_PREFIX_OPCODE
9261 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
9262 add_prefix (prefix
);
9266 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
9268 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
9269 add_prefix (prefix
);
9275 /* Check for pseudo prefixes. */
9276 as_bad_where (insn_start_frag
->fr_file
,
9277 insn_start_frag
->fr_line
,
9278 _("pseudo prefix without instruction"));
9284 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9285 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9286 R_X86_64_GOTTPOFF relocation so that linker can safely
9287 perform IE->LE optimization. A dummy REX_OPCODE prefix
9288 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9289 relocation for GDesc -> IE/LE optimization. */
9290 if (x86_elf_abi
== X86_64_X32_ABI
9292 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9293 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9294 && i
.prefix
[REX_PREFIX
] == 0)
9295 add_prefix (REX_OPCODE
);
9298 /* The prefix bytes. */
9299 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9301 FRAG_APPEND_1_CHAR (*q
);
9305 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9311 FRAG_APPEND_1_CHAR (*q
);
9314 /* There should be no other prefixes for instructions
9319 /* For EVEX instructions i.vrex should become 0 after
9320 build_evex_prefix. For VEX instructions upper 16 registers
9321 aren't available, so VREX should be 0. */
9324 /* Now the VEX prefix. */
9325 p
= frag_more (i
.vex
.length
);
9326 for (j
= 0; j
< i
.vex
.length
; j
++)
9327 p
[j
] = i
.vex
.bytes
[j
];
9330 /* Now the opcode; be careful about word order here! */
9331 if (i
.tm
.opcode_length
== 1)
9333 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9337 switch (i
.tm
.opcode_length
)
9341 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9342 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9346 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9356 /* Put out high byte first: can't use md_number_to_chars! */
9357 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9358 *p
= i
.tm
.base_opcode
& 0xff;
9361 /* Now the modrm byte and sib byte (if present). */
9362 if (i
.tm
.opcode_modifier
.modrm
)
9364 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
9367 /* If i.rm.regmem == ESP (4)
9368 && i.rm.mode != (Register mode)
9370 ==> need second modrm byte. */
9371 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9373 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9374 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
9376 | i
.sib
.scale
<< 6));
9379 if (i
.disp_operands
)
9380 output_disp (insn_start_frag
, insn_start_off
);
9383 output_imm (insn_start_frag
, insn_start_off
);
9386 * frag_now_fix () returning plain abs_section_offset when we're in the
9387 * absolute section, and abs_section_offset not getting updated as data
9388 * gets added to the frag breaks the logic below.
9390 if (now_seg
!= absolute_section
)
9392 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9394 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9398 /* NB: Don't add prefix with GOTPC relocation since
9399 output_disp() above depends on the fixed encoding
9400 length. Can't add prefix with TLS relocation since
9401 it breaks TLS linker optimization. */
9402 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9403 /* Prefix count on the current instruction. */
9404 unsigned int count
= i
.vex
.length
;
9406 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9407 /* REX byte is encoded in VEX/EVEX prefix. */
9408 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9411 /* Count prefixes for extended opcode maps. */
9413 switch (i
.tm
.opcode_length
)
9416 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9419 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9431 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9440 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9443 /* Set the maximum prefix size in BRANCH_PREFIX
9445 if (fragP
->tc_frag_data
.max_bytes
> max
)
9446 fragP
->tc_frag_data
.max_bytes
= max
;
9447 if (fragP
->tc_frag_data
.max_bytes
> count
)
9448 fragP
->tc_frag_data
.max_bytes
-= count
;
9450 fragP
->tc_frag_data
.max_bytes
= 0;
9454 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9456 unsigned int max_prefix_size
;
9457 if (align_branch_prefix_size
> max
)
9458 max_prefix_size
= max
;
9460 max_prefix_size
= align_branch_prefix_size
;
9461 if (max_prefix_size
> count
)
9462 fragP
->tc_frag_data
.max_prefix_length
9463 = max_prefix_size
- count
;
9466 /* Use existing segment prefix if possible. Use CS
9467 segment prefix in 64-bit mode. In 32-bit mode, use SS
9468 segment prefix with ESP/EBP base register and use DS
9469 segment prefix without ESP/EBP base register. */
9470 if (i
.prefix
[SEG_PREFIX
])
9471 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9472 else if (flag_code
== CODE_64BIT
)
9473 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9475 && (i
.base_reg
->reg_num
== 4
9476 || i
.base_reg
->reg_num
== 5))
9477 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9479 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9484 /* NB: Don't work with COND_JUMP86 without i386. */
9485 if (align_branch_power
9486 && now_seg
!= absolute_section
9487 && cpu_arch_flags
.bitfield
.cpui386
)
9489 /* Terminate each frag so that we can add prefix and check for
9491 frag_wane (frag_now
);
9498 pi ("" /*line*/, &i
);
9500 #endif /* DEBUG386 */
9503 /* Return the size of the displacement operand N. */
9506 disp_size (unsigned int n
)
9510 if (i
.types
[n
].bitfield
.disp64
)
9512 else if (i
.types
[n
].bitfield
.disp8
)
9514 else if (i
.types
[n
].bitfield
.disp16
)
9519 /* Return the size of the immediate operand N. */
9522 imm_size (unsigned int n
)
9525 if (i
.types
[n
].bitfield
.imm64
)
9527 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9529 else if (i
.types
[n
].bitfield
.imm16
)
9535 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9540 for (n
= 0; n
< i
.operands
; n
++)
9542 if (operand_type_check (i
.types
[n
], disp
))
9544 if (i
.op
[n
].disps
->X_op
== O_constant
)
9546 int size
= disp_size (n
);
9547 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9549 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9551 p
= frag_more (size
);
9552 md_number_to_chars (p
, val
, size
);
9556 enum bfd_reloc_code_real reloc_type
;
9557 int size
= disp_size (n
);
9558 int sign
= i
.types
[n
].bitfield
.disp32s
;
9559 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9562 /* We can't have 8 bit displacement here. */
9563 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9565 /* The PC relative address is computed relative
9566 to the instruction boundary, so in case immediate
9567 fields follows, we need to adjust the value. */
9568 if (pcrel
&& i
.imm_operands
)
9573 for (n1
= 0; n1
< i
.operands
; n1
++)
9574 if (operand_type_check (i
.types
[n1
], imm
))
9576 /* Only one immediate is allowed for PC
9577 relative address. */
9578 gas_assert (sz
== 0);
9580 i
.op
[n
].disps
->X_add_number
-= sz
;
9582 /* We should find the immediate. */
9583 gas_assert (sz
!= 0);
9586 p
= frag_more (size
);
9587 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9589 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9590 && (((reloc_type
== BFD_RELOC_32
9591 || reloc_type
== BFD_RELOC_X86_64_32S
9592 || (reloc_type
== BFD_RELOC_64
9594 && (i
.op
[n
].disps
->X_op
== O_symbol
9595 || (i
.op
[n
].disps
->X_op
== O_add
9596 && ((symbol_get_value_expression
9597 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9599 || reloc_type
== BFD_RELOC_32_PCREL
))
9603 reloc_type
= BFD_RELOC_386_GOTPC
;
9604 i
.has_gotpc_tls_reloc
= TRUE
;
9605 i
.op
[n
].imms
->X_add_number
+=
9606 encoding_length (insn_start_frag
, insn_start_off
, p
);
9608 else if (reloc_type
== BFD_RELOC_64
)
9609 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9611 /* Don't do the adjustment for x86-64, as there
9612 the pcrel addressing is relative to the _next_
9613 insn, and that is taken care of in other code. */
9614 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9616 else if (align_branch_power
)
9620 case BFD_RELOC_386_TLS_GD
:
9621 case BFD_RELOC_386_TLS_LDM
:
9622 case BFD_RELOC_386_TLS_IE
:
9623 case BFD_RELOC_386_TLS_IE_32
:
9624 case BFD_RELOC_386_TLS_GOTIE
:
9625 case BFD_RELOC_386_TLS_GOTDESC
:
9626 case BFD_RELOC_386_TLS_DESC_CALL
:
9627 case BFD_RELOC_X86_64_TLSGD
:
9628 case BFD_RELOC_X86_64_TLSLD
:
9629 case BFD_RELOC_X86_64_GOTTPOFF
:
9630 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9631 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9632 i
.has_gotpc_tls_reloc
= TRUE
;
9637 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9638 size
, i
.op
[n
].disps
, pcrel
,
9640 /* Check for "call/jmp *mem", "mov mem, %reg",
9641 "test %reg, mem" and "binop mem, %reg" where binop
9642 is one of adc, add, and, cmp, or, sbb, sub, xor
9643 instructions without data prefix. Always generate
9644 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9645 if (i
.prefix
[DATA_PREFIX
] == 0
9646 && (generate_relax_relocations
9649 && i
.rm
.regmem
== 5))
9651 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9652 && !is_any_vex_encoding(&i
.tm
)
9653 && ((i
.operands
== 1
9654 && i
.tm
.base_opcode
== 0xff
9655 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9657 && (i
.tm
.base_opcode
== 0x8b
9658 || i
.tm
.base_opcode
== 0x85
9659 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9663 fixP
->fx_tcbit
= i
.rex
!= 0;
9665 && (i
.base_reg
->reg_num
== RegIP
))
9666 fixP
->fx_tcbit2
= 1;
9669 fixP
->fx_tcbit2
= 1;
9677 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9682 for (n
= 0; n
< i
.operands
; n
++)
9684 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9685 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9688 if (operand_type_check (i
.types
[n
], imm
))
9690 if (i
.op
[n
].imms
->X_op
== O_constant
)
9692 int size
= imm_size (n
);
9695 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9697 p
= frag_more (size
);
9698 md_number_to_chars (p
, val
, size
);
9702 /* Not absolute_section.
9703 Need a 32-bit fixup (don't support 8bit
9704 non-absolute imms). Try to support other
9706 enum bfd_reloc_code_real reloc_type
;
9707 int size
= imm_size (n
);
9710 if (i
.types
[n
].bitfield
.imm32s
9711 && (i
.suffix
== QWORD_MNEM_SUFFIX
9712 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9717 p
= frag_more (size
);
9718 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9720 /* This is tough to explain. We end up with this one if we
9721 * have operands that look like
9722 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9723 * obtain the absolute address of the GOT, and it is strongly
9724 * preferable from a performance point of view to avoid using
9725 * a runtime relocation for this. The actual sequence of
9726 * instructions often look something like:
9731 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9733 * The call and pop essentially return the absolute address
9734 * of the label .L66 and store it in %ebx. The linker itself
9735 * will ultimately change the first operand of the addl so
9736 * that %ebx points to the GOT, but to keep things simple, the
9737 * .o file must have this operand set so that it generates not
9738 * the absolute address of .L66, but the absolute address of
9739 * itself. This allows the linker itself simply treat a GOTPC
9740 * relocation as asking for a pcrel offset to the GOT to be
9741 * added in, and the addend of the relocation is stored in the
9742 * operand field for the instruction itself.
9744 * Our job here is to fix the operand so that it would add
9745 * the correct offset so that %ebx would point to itself. The
9746 * thing that is tricky is that .-.L66 will point to the
9747 * beginning of the instruction, so we need to further modify
9748 * the operand so that it will point to itself. There are
9749 * other cases where you have something like:
9751 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9753 * and here no correction would be required. Internally in
9754 * the assembler we treat operands of this form as not being
9755 * pcrel since the '.' is explicitly mentioned, and I wonder
9756 * whether it would simplify matters to do it this way. Who
9757 * knows. In earlier versions of the PIC patches, the
9758 * pcrel_adjust field was used to store the correction, but
9759 * since the expression is not pcrel, I felt it would be
9760 * confusing to do it this way. */
9762 if ((reloc_type
== BFD_RELOC_32
9763 || reloc_type
== BFD_RELOC_X86_64_32S
9764 || reloc_type
== BFD_RELOC_64
)
9766 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9767 && (i
.op
[n
].imms
->X_op
== O_symbol
9768 || (i
.op
[n
].imms
->X_op
== O_add
9769 && ((symbol_get_value_expression
9770 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9774 reloc_type
= BFD_RELOC_386_GOTPC
;
9776 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9778 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9779 i
.has_gotpc_tls_reloc
= TRUE
;
9780 i
.op
[n
].imms
->X_add_number
+=
9781 encoding_length (insn_start_frag
, insn_start_off
, p
);
9783 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9784 i
.op
[n
].imms
, 0, reloc_type
);
9790 /* x86_cons_fix_new is called via the expression parsing code when a
9791 reloc is needed. We use this hook to get the correct .got reloc. */
9792 static int cons_sign
= -1;
9795 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9796 expressionS
*exp
, bfd_reloc_code_real_type r
)
9798 r
= reloc (len
, 0, cons_sign
, r
);
9801 if (exp
->X_op
== O_secrel
)
9803 exp
->X_op
= O_symbol
;
9804 r
= BFD_RELOC_32_SECREL
;
9808 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9811 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9812 purpose of the `.dc.a' internal pseudo-op. */
9815 x86_address_bytes (void)
9817 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9819 return stdoutput
->arch_info
->bits_per_address
/ 8;
9822 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9824 # define lex_got(reloc, adjust, types) NULL
9826 /* Parse operands of the form
9827 <symbol>@GOTOFF+<nnn>
9828 and similar .plt or .got references.
9830 If we find one, set up the correct relocation in RELOC and copy the
9831 input string, minus the `@GOTOFF' into a malloc'd buffer for
9832 parsing by the calling routine. Return this buffer, and if ADJUST
9833 is non-null set it to the length of the string we removed from the
9834 input line. Otherwise return NULL. */
9836 lex_got (enum bfd_reloc_code_real
*rel
,
9838 i386_operand_type
*types
)
9840 /* Some of the relocations depend on the size of what field is to
9841 be relocated. But in our callers i386_immediate and i386_displacement
9842 we don't yet know the operand size (this will be set by insn
9843 matching). Hence we record the word32 relocation here,
9844 and adjust the reloc according to the real size in reloc(). */
9845 static const struct {
9848 const enum bfd_reloc_code_real rel
[2];
9849 const i386_operand_type types64
;
9851 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9852 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9854 OPERAND_TYPE_IMM32_64
},
9856 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9857 BFD_RELOC_X86_64_PLTOFF64
},
9858 OPERAND_TYPE_IMM64
},
9859 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9860 BFD_RELOC_X86_64_PLT32
},
9861 OPERAND_TYPE_IMM32_32S_DISP32
},
9862 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9863 BFD_RELOC_X86_64_GOTPLT64
},
9864 OPERAND_TYPE_IMM64_DISP64
},
9865 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9866 BFD_RELOC_X86_64_GOTOFF64
},
9867 OPERAND_TYPE_IMM64_DISP64
},
9868 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9869 BFD_RELOC_X86_64_GOTPCREL
},
9870 OPERAND_TYPE_IMM32_32S_DISP32
},
9871 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9872 BFD_RELOC_X86_64_TLSGD
},
9873 OPERAND_TYPE_IMM32_32S_DISP32
},
9874 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9875 _dummy_first_bfd_reloc_code_real
},
9876 OPERAND_TYPE_NONE
},
9877 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9878 BFD_RELOC_X86_64_TLSLD
},
9879 OPERAND_TYPE_IMM32_32S_DISP32
},
9880 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9881 BFD_RELOC_X86_64_GOTTPOFF
},
9882 OPERAND_TYPE_IMM32_32S_DISP32
},
9883 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9884 BFD_RELOC_X86_64_TPOFF32
},
9885 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9886 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9887 _dummy_first_bfd_reloc_code_real
},
9888 OPERAND_TYPE_NONE
},
9889 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9890 BFD_RELOC_X86_64_DTPOFF32
},
9891 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9892 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9893 _dummy_first_bfd_reloc_code_real
},
9894 OPERAND_TYPE_NONE
},
9895 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9896 _dummy_first_bfd_reloc_code_real
},
9897 OPERAND_TYPE_NONE
},
9898 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9899 BFD_RELOC_X86_64_GOT32
},
9900 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9901 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9902 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9903 OPERAND_TYPE_IMM32_32S_DISP32
},
9904 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9905 BFD_RELOC_X86_64_TLSDESC_CALL
},
9906 OPERAND_TYPE_IMM32_32S_DISP32
},
9911 #if defined (OBJ_MAYBE_ELF)
9916 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9917 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9920 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9922 int len
= gotrel
[j
].len
;
9923 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9925 if (gotrel
[j
].rel
[object_64bit
] != 0)
9928 char *tmpbuf
, *past_reloc
;
9930 *rel
= gotrel
[j
].rel
[object_64bit
];
9934 if (flag_code
!= CODE_64BIT
)
9936 types
->bitfield
.imm32
= 1;
9937 types
->bitfield
.disp32
= 1;
9940 *types
= gotrel
[j
].types64
;
9943 if (j
!= 0 && GOT_symbol
== NULL
)
9944 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9946 /* The length of the first part of our input line. */
9947 first
= cp
- input_line_pointer
;
9949 /* The second part goes from after the reloc token until
9950 (and including) an end_of_line char or comma. */
9951 past_reloc
= cp
+ 1 + len
;
9953 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9955 second
= cp
+ 1 - past_reloc
;
9957 /* Allocate and copy string. The trailing NUL shouldn't
9958 be necessary, but be safe. */
9959 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9960 memcpy (tmpbuf
, input_line_pointer
, first
);
9961 if (second
!= 0 && *past_reloc
!= ' ')
9962 /* Replace the relocation token with ' ', so that
9963 errors like foo@GOTOFF1 will be detected. */
9964 tmpbuf
[first
++] = ' ';
9966 /* Increment length by 1 if the relocation token is
9971 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9972 tmpbuf
[first
+ second
] = '\0';
9976 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9977 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9982 /* Might be a symbol version string. Don't as_bad here. */
9991 /* Parse operands of the form
9992 <symbol>@SECREL32+<nnn>
9994 If we find one, set up the correct relocation in RELOC and copy the
9995 input string, minus the `@SECREL32' into a malloc'd buffer for
9996 parsing by the calling routine. Return this buffer, and if ADJUST
9997 is non-null set it to the length of the string we removed from the
9998 input line. Otherwise return NULL.
10000 This function is copied from the ELF version above adjusted for PE targets. */
10003 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
10004 int *adjust ATTRIBUTE_UNUSED
,
10005 i386_operand_type
*types
)
10007 static const struct
10011 const enum bfd_reloc_code_real rel
[2];
10012 const i386_operand_type types64
;
10016 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10017 BFD_RELOC_32_SECREL
},
10018 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10024 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10025 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10028 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10030 int len
= gotrel
[j
].len
;
10032 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10034 if (gotrel
[j
].rel
[object_64bit
] != 0)
10037 char *tmpbuf
, *past_reloc
;
10039 *rel
= gotrel
[j
].rel
[object_64bit
];
10045 if (flag_code
!= CODE_64BIT
)
10047 types
->bitfield
.imm32
= 1;
10048 types
->bitfield
.disp32
= 1;
10051 *types
= gotrel
[j
].types64
;
10054 /* The length of the first part of our input line. */
10055 first
= cp
- input_line_pointer
;
10057 /* The second part goes from after the reloc token until
10058 (and including) an end_of_line char or comma. */
10059 past_reloc
= cp
+ 1 + len
;
10061 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10063 second
= cp
+ 1 - past_reloc
;
10065 /* Allocate and copy string. The trailing NUL shouldn't
10066 be necessary, but be safe. */
10067 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10068 memcpy (tmpbuf
, input_line_pointer
, first
);
10069 if (second
!= 0 && *past_reloc
!= ' ')
10070 /* Replace the relocation token with ' ', so that
10071 errors like foo@SECLREL321 will be detected. */
10072 tmpbuf
[first
++] = ' ';
10073 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10074 tmpbuf
[first
+ second
] = '\0';
10078 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10079 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10084 /* Might be a symbol version string. Don't as_bad here. */
10090 bfd_reloc_code_real_type
10091 x86_cons (expressionS
*exp
, int size
)
10093 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10095 intel_syntax
= -intel_syntax
;
10098 if (size
== 4 || (object_64bit
&& size
== 8))
10100 /* Handle @GOTOFF and the like in an expression. */
10102 char *gotfree_input_line
;
10105 save
= input_line_pointer
;
10106 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10107 if (gotfree_input_line
)
10108 input_line_pointer
= gotfree_input_line
;
10112 if (gotfree_input_line
)
10114 /* expression () has merrily parsed up to the end of line,
10115 or a comma - in the wrong buffer. Transfer how far
10116 input_line_pointer has moved to the right buffer. */
10117 input_line_pointer
= (save
10118 + (input_line_pointer
- gotfree_input_line
)
10120 free (gotfree_input_line
);
10121 if (exp
->X_op
== O_constant
10122 || exp
->X_op
== O_absent
10123 || exp
->X_op
== O_illegal
10124 || exp
->X_op
== O_register
10125 || exp
->X_op
== O_big
)
10127 char c
= *input_line_pointer
;
10128 *input_line_pointer
= 0;
10129 as_bad (_("missing or invalid expression `%s'"), save
);
10130 *input_line_pointer
= c
;
10132 else if ((got_reloc
== BFD_RELOC_386_PLT32
10133 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10134 && exp
->X_op
!= O_symbol
)
10136 char c
= *input_line_pointer
;
10137 *input_line_pointer
= 0;
10138 as_bad (_("invalid PLT expression `%s'"), save
);
10139 *input_line_pointer
= c
;
10146 intel_syntax
= -intel_syntax
;
10149 i386_intel_simplify (exp
);
10155 signed_cons (int size
)
10157 if (flag_code
== CODE_64BIT
)
10165 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10172 if (exp
.X_op
== O_symbol
)
10173 exp
.X_op
= O_secrel
;
10175 emit_expr (&exp
, 4);
10177 while (*input_line_pointer
++ == ',');
10179 input_line_pointer
--;
10180 demand_empty_rest_of_line ();
10184 /* Handle Vector operations. */
10187 check_VecOperations (char *op_string
, char *op_end
)
10189 const reg_entry
*mask
;
10194 && (op_end
== NULL
|| op_string
< op_end
))
10197 if (*op_string
== '{')
10201 /* Check broadcasts. */
10202 if (strncmp (op_string
, "1to", 3) == 0)
10207 goto duplicated_vec_op
;
10210 if (*op_string
== '8')
10212 else if (*op_string
== '4')
10214 else if (*op_string
== '2')
10216 else if (*op_string
== '1'
10217 && *(op_string
+1) == '6')
10224 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10229 broadcast_op
.type
= bcst_type
;
10230 broadcast_op
.operand
= this_operand
;
10231 broadcast_op
.bytes
= 0;
10232 i
.broadcast
= &broadcast_op
;
10234 /* Check masking operation. */
10235 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10237 if (mask
== &bad_reg
)
10240 /* k0 can't be used for write mask. */
10241 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10243 as_bad (_("`%s%s' can't be used for write mask"),
10244 register_prefix
, mask
->reg_name
);
10250 mask_op
.mask
= mask
;
10251 mask_op
.zeroing
= 0;
10252 mask_op
.operand
= this_operand
;
10258 goto duplicated_vec_op
;
10260 i
.mask
->mask
= mask
;
10262 /* Only "{z}" is allowed here. No need to check
10263 zeroing mask explicitly. */
10264 if (i
.mask
->operand
!= this_operand
)
10266 as_bad (_("invalid write mask `%s'"), saved
);
10271 op_string
= end_op
;
10273 /* Check zeroing-flag for masking operation. */
10274 else if (*op_string
== 'z')
10278 mask_op
.mask
= NULL
;
10279 mask_op
.zeroing
= 1;
10280 mask_op
.operand
= this_operand
;
10285 if (i
.mask
->zeroing
)
10288 as_bad (_("duplicated `%s'"), saved
);
10292 i
.mask
->zeroing
= 1;
10294 /* Only "{%k}" is allowed here. No need to check mask
10295 register explicitly. */
10296 if (i
.mask
->operand
!= this_operand
)
10298 as_bad (_("invalid zeroing-masking `%s'"),
10307 goto unknown_vec_op
;
10309 if (*op_string
!= '}')
10311 as_bad (_("missing `}' in `%s'"), saved
);
10316 /* Strip whitespace since the addition of pseudo prefixes
10317 changed how the scrubber treats '{'. */
10318 if (is_space_char (*op_string
))
10324 /* We don't know this one. */
10325 as_bad (_("unknown vector operation: `%s'"), saved
);
10329 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10331 as_bad (_("zeroing-masking only allowed with write mask"));
10339 i386_immediate (char *imm_start
)
10341 char *save_input_line_pointer
;
10342 char *gotfree_input_line
;
10345 i386_operand_type types
;
10347 operand_type_set (&types
, ~0);
10349 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10351 as_bad (_("at most %d immediate operands are allowed"),
10352 MAX_IMMEDIATE_OPERANDS
);
10356 exp
= &im_expressions
[i
.imm_operands
++];
10357 i
.op
[this_operand
].imms
= exp
;
10359 if (is_space_char (*imm_start
))
10362 save_input_line_pointer
= input_line_pointer
;
10363 input_line_pointer
= imm_start
;
10365 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10366 if (gotfree_input_line
)
10367 input_line_pointer
= gotfree_input_line
;
10369 exp_seg
= expression (exp
);
10371 SKIP_WHITESPACE ();
10373 /* Handle vector operations. */
10374 if (*input_line_pointer
== '{')
10376 input_line_pointer
= check_VecOperations (input_line_pointer
,
10378 if (input_line_pointer
== NULL
)
10382 if (*input_line_pointer
)
10383 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10385 input_line_pointer
= save_input_line_pointer
;
10386 if (gotfree_input_line
)
10388 free (gotfree_input_line
);
10390 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10391 exp
->X_op
= O_illegal
;
10394 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10398 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10399 i386_operand_type types
, const char *imm_start
)
10401 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10404 as_bad (_("missing or invalid immediate expression `%s'"),
10408 else if (exp
->X_op
== O_constant
)
10410 /* Size it properly later. */
10411 i
.types
[this_operand
].bitfield
.imm64
= 1;
10412 /* If not 64bit, sign extend val. */
10413 if (flag_code
!= CODE_64BIT
10414 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10416 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10418 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10419 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10420 && exp_seg
!= absolute_section
10421 && exp_seg
!= text_section
10422 && exp_seg
!= data_section
10423 && exp_seg
!= bss_section
10424 && exp_seg
!= undefined_section
10425 && !bfd_is_com_section (exp_seg
))
10427 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10431 else if (!intel_syntax
&& exp_seg
== reg_section
)
10434 as_bad (_("illegal immediate register operand %s"), imm_start
);
10439 /* This is an address. The size of the address will be
10440 determined later, depending on destination register,
10441 suffix, or the default for the section. */
10442 i
.types
[this_operand
].bitfield
.imm8
= 1;
10443 i
.types
[this_operand
].bitfield
.imm16
= 1;
10444 i
.types
[this_operand
].bitfield
.imm32
= 1;
10445 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10446 i
.types
[this_operand
].bitfield
.imm64
= 1;
10447 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10455 i386_scale (char *scale
)
10458 char *save
= input_line_pointer
;
10460 input_line_pointer
= scale
;
10461 val
= get_absolute_expression ();
10466 i
.log2_scale_factor
= 0;
10469 i
.log2_scale_factor
= 1;
10472 i
.log2_scale_factor
= 2;
10475 i
.log2_scale_factor
= 3;
10479 char sep
= *input_line_pointer
;
10481 *input_line_pointer
= '\0';
10482 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10484 *input_line_pointer
= sep
;
10485 input_line_pointer
= save
;
10489 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10491 as_warn (_("scale factor of %d without an index register"),
10492 1 << i
.log2_scale_factor
);
10493 i
.log2_scale_factor
= 0;
10495 scale
= input_line_pointer
;
10496 input_line_pointer
= save
;
10501 i386_displacement (char *disp_start
, char *disp_end
)
10505 char *save_input_line_pointer
;
10506 char *gotfree_input_line
;
10508 i386_operand_type bigdisp
, types
= anydisp
;
10511 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10513 as_bad (_("at most %d displacement operands are allowed"),
10514 MAX_MEMORY_OPERANDS
);
10518 operand_type_set (&bigdisp
, 0);
10520 || i
.types
[this_operand
].bitfield
.baseindex
10521 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10522 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10524 i386_addressing_mode ();
10525 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10526 if (flag_code
== CODE_64BIT
)
10530 bigdisp
.bitfield
.disp32s
= 1;
10531 bigdisp
.bitfield
.disp64
= 1;
10534 bigdisp
.bitfield
.disp32
= 1;
10536 else if ((flag_code
== CODE_16BIT
) ^ override
)
10537 bigdisp
.bitfield
.disp16
= 1;
10539 bigdisp
.bitfield
.disp32
= 1;
10543 /* For PC-relative branches, the width of the displacement may be
10544 dependent upon data size, but is never dependent upon address size.
10545 Also make sure to not unintentionally match against a non-PC-relative
10546 branch template. */
10547 static templates aux_templates
;
10548 const insn_template
*t
= current_templates
->start
;
10549 bfd_boolean has_intel64
= FALSE
;
10551 aux_templates
.start
= t
;
10552 while (++t
< current_templates
->end
)
10554 if (t
->opcode_modifier
.jump
10555 != current_templates
->start
->opcode_modifier
.jump
)
10557 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10558 has_intel64
= TRUE
;
10560 if (t
< current_templates
->end
)
10562 aux_templates
.end
= t
;
10563 current_templates
= &aux_templates
;
10566 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10567 if (flag_code
== CODE_64BIT
)
10569 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10570 && (!intel64
|| !has_intel64
))
10571 bigdisp
.bitfield
.disp16
= 1;
10573 bigdisp
.bitfield
.disp32s
= 1;
10578 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10580 : LONG_MNEM_SUFFIX
));
10581 bigdisp
.bitfield
.disp32
= 1;
10582 if ((flag_code
== CODE_16BIT
) ^ override
)
10584 bigdisp
.bitfield
.disp32
= 0;
10585 bigdisp
.bitfield
.disp16
= 1;
10589 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10592 exp
= &disp_expressions
[i
.disp_operands
];
10593 i
.op
[this_operand
].disps
= exp
;
10595 save_input_line_pointer
= input_line_pointer
;
10596 input_line_pointer
= disp_start
;
10597 END_STRING_AND_SAVE (disp_end
);
10599 #ifndef GCC_ASM_O_HACK
10600 #define GCC_ASM_O_HACK 0
10603 END_STRING_AND_SAVE (disp_end
+ 1);
10604 if (i
.types
[this_operand
].bitfield
.baseIndex
10605 && displacement_string_end
[-1] == '+')
10607 /* This hack is to avoid a warning when using the "o"
10608 constraint within gcc asm statements.
10611 #define _set_tssldt_desc(n,addr,limit,type) \
10612 __asm__ __volatile__ ( \
10613 "movw %w2,%0\n\t" \
10614 "movw %w1,2+%0\n\t" \
10615 "rorl $16,%1\n\t" \
10616 "movb %b1,4+%0\n\t" \
10617 "movb %4,5+%0\n\t" \
10618 "movb $0,6+%0\n\t" \
10619 "movb %h1,7+%0\n\t" \
10621 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10623 This works great except that the output assembler ends
10624 up looking a bit weird if it turns out that there is
10625 no offset. You end up producing code that looks like:
10638 So here we provide the missing zero. */
10640 *displacement_string_end
= '0';
10643 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10644 if (gotfree_input_line
)
10645 input_line_pointer
= gotfree_input_line
;
10647 exp_seg
= expression (exp
);
10649 SKIP_WHITESPACE ();
10650 if (*input_line_pointer
)
10651 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10653 RESTORE_END_STRING (disp_end
+ 1);
10655 input_line_pointer
= save_input_line_pointer
;
10656 if (gotfree_input_line
)
10658 free (gotfree_input_line
);
10660 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10661 exp
->X_op
= O_illegal
;
10664 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10666 RESTORE_END_STRING (disp_end
);
10672 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10673 i386_operand_type types
, const char *disp_start
)
10675 i386_operand_type bigdisp
;
10678 /* We do this to make sure that the section symbol is in
10679 the symbol table. We will ultimately change the relocation
10680 to be relative to the beginning of the section. */
10681 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10682 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10683 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10685 if (exp
->X_op
!= O_symbol
)
10688 if (S_IS_LOCAL (exp
->X_add_symbol
)
10689 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10690 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10691 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10692 exp
->X_op
= O_subtract
;
10693 exp
->X_op_symbol
= GOT_symbol
;
10694 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10695 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10696 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10697 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10699 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10702 else if (exp
->X_op
== O_absent
10703 || exp
->X_op
== O_illegal
10704 || exp
->X_op
== O_big
)
10707 as_bad (_("missing or invalid displacement expression `%s'"),
10712 else if (flag_code
== CODE_64BIT
10713 && !i
.prefix
[ADDR_PREFIX
]
10714 && exp
->X_op
== O_constant
)
10716 /* Since displacement is signed extended to 64bit, don't allow
10717 disp32 and turn off disp32s if they are out of range. */
10718 i
.types
[this_operand
].bitfield
.disp32
= 0;
10719 if (!fits_in_signed_long (exp
->X_add_number
))
10721 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10722 if (i
.types
[this_operand
].bitfield
.baseindex
)
10724 as_bad (_("0x%lx out range of signed 32bit displacement"),
10725 (long) exp
->X_add_number
);
10731 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10732 else if (exp
->X_op
!= O_constant
10733 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10734 && exp_seg
!= absolute_section
10735 && exp_seg
!= text_section
10736 && exp_seg
!= data_section
10737 && exp_seg
!= bss_section
10738 && exp_seg
!= undefined_section
10739 && !bfd_is_com_section (exp_seg
))
10741 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10746 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10747 /* Constants get taken care of by optimize_disp(). */
10748 && exp
->X_op
!= O_constant
)
10749 i
.types
[this_operand
].bitfield
.disp8
= 1;
10751 /* Check if this is a displacement only operand. */
10752 bigdisp
= i
.types
[this_operand
];
10753 bigdisp
.bitfield
.disp8
= 0;
10754 bigdisp
.bitfield
.disp16
= 0;
10755 bigdisp
.bitfield
.disp32
= 0;
10756 bigdisp
.bitfield
.disp32s
= 0;
10757 bigdisp
.bitfield
.disp64
= 0;
10758 if (operand_type_all_zero (&bigdisp
))
10759 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10765 /* Return the active addressing mode, taking address override and
10766 registers forming the address into consideration. Update the
10767 address override prefix if necessary. */
10769 static enum flag_code
10770 i386_addressing_mode (void)
10772 enum flag_code addr_mode
;
10774 if (i
.prefix
[ADDR_PREFIX
])
10775 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10776 else if (flag_code
== CODE_16BIT
10777 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10778 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10779 from md_assemble() by "is not a valid base/index expression"
10780 when there is a base and/or index. */
10781 && !i
.types
[this_operand
].bitfield
.baseindex
)
10783 /* MPX insn memory operands with neither base nor index must be forced
10784 to use 32-bit addressing in 16-bit mode. */
10785 addr_mode
= CODE_32BIT
;
10786 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10788 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10789 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10793 addr_mode
= flag_code
;
10795 #if INFER_ADDR_PREFIX
10796 if (i
.mem_operands
== 0)
10798 /* Infer address prefix from the first memory operand. */
10799 const reg_entry
*addr_reg
= i
.base_reg
;
10801 if (addr_reg
== NULL
)
10802 addr_reg
= i
.index_reg
;
10806 if (addr_reg
->reg_type
.bitfield
.dword
)
10807 addr_mode
= CODE_32BIT
;
10808 else if (flag_code
!= CODE_64BIT
10809 && addr_reg
->reg_type
.bitfield
.word
)
10810 addr_mode
= CODE_16BIT
;
10812 if (addr_mode
!= flag_code
)
10814 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10816 /* Change the size of any displacement too. At most one
10817 of Disp16 or Disp32 is set.
10818 FIXME. There doesn't seem to be any real need for
10819 separate Disp16 and Disp32 flags. The same goes for
10820 Imm16 and Imm32. Removing them would probably clean
10821 up the code quite a lot. */
10822 if (flag_code
!= CODE_64BIT
10823 && (i
.types
[this_operand
].bitfield
.disp16
10824 || i
.types
[this_operand
].bitfield
.disp32
))
10825 i
.types
[this_operand
]
10826 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10836 /* Make sure the memory operand we've been dealt is valid.
10837 Return 1 on success, 0 on a failure. */
10840 i386_index_check (const char *operand_string
)
10842 const char *kind
= "base/index";
10843 enum flag_code addr_mode
= i386_addressing_mode ();
10845 if (current_templates
->start
->opcode_modifier
.isstring
10846 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10847 && (current_templates
->end
[-1].opcode_modifier
.isstring
10848 || i
.mem_operands
))
10850 /* Memory operands of string insns are special in that they only allow
10851 a single register (rDI, rSI, or rBX) as their memory address. */
10852 const reg_entry
*expected_reg
;
10853 static const char *di_si
[][2] =
10859 static const char *bx
[] = { "ebx", "bx", "rbx" };
10861 kind
= "string address";
10863 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10865 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10866 - IS_STRING_ES_OP0
;
10869 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10870 || ((!i
.mem_operands
!= !intel_syntax
)
10871 && current_templates
->end
[-1].operand_types
[1]
10872 .bitfield
.baseindex
))
10874 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10877 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10879 if (i
.base_reg
!= expected_reg
10881 || operand_type_check (i
.types
[this_operand
], disp
))
10883 /* The second memory operand must have the same size as
10887 && !((addr_mode
== CODE_64BIT
10888 && i
.base_reg
->reg_type
.bitfield
.qword
)
10889 || (addr_mode
== CODE_32BIT
10890 ? i
.base_reg
->reg_type
.bitfield
.dword
10891 : i
.base_reg
->reg_type
.bitfield
.word
)))
10894 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10896 intel_syntax
? '[' : '(',
10898 expected_reg
->reg_name
,
10899 intel_syntax
? ']' : ')');
10906 as_bad (_("`%s' is not a valid %s expression"),
10907 operand_string
, kind
);
10912 if (addr_mode
!= CODE_16BIT
)
10914 /* 32-bit/64-bit checks. */
10916 && ((addr_mode
== CODE_64BIT
10917 ? !i
.base_reg
->reg_type
.bitfield
.qword
10918 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10919 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10920 || i
.base_reg
->reg_num
== RegIZ
))
10922 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10923 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10924 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10925 && ((addr_mode
== CODE_64BIT
10926 ? !i
.index_reg
->reg_type
.bitfield
.qword
10927 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10928 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10931 /* bndmk, bndldx, and bndstx have special restrictions. */
10932 if (current_templates
->start
->base_opcode
== 0xf30f1b
10933 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10935 /* They cannot use RIP-relative addressing. */
10936 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10938 as_bad (_("`%s' cannot be used here"), operand_string
);
10942 /* bndldx and bndstx ignore their scale factor. */
10943 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10944 && i
.log2_scale_factor
)
10945 as_warn (_("register scaling is being ignored here"));
10950 /* 16-bit checks. */
10952 && (!i
.base_reg
->reg_type
.bitfield
.word
10953 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10955 && (!i
.index_reg
->reg_type
.bitfield
.word
10956 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10958 && i
.base_reg
->reg_num
< 6
10959 && i
.index_reg
->reg_num
>= 6
10960 && i
.log2_scale_factor
== 0))))
10967 /* Handle vector immediates. */
10970 RC_SAE_immediate (const char *imm_start
)
10972 unsigned int match_found
, j
;
10973 const char *pstr
= imm_start
;
10981 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10983 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10987 rc_op
.type
= RC_NamesTable
[j
].type
;
10988 rc_op
.operand
= this_operand
;
10989 i
.rounding
= &rc_op
;
10993 as_bad (_("duplicated `%s'"), imm_start
);
10996 pstr
+= RC_NamesTable
[j
].len
;
11004 if (*pstr
++ != '}')
11006 as_bad (_("Missing '}': '%s'"), imm_start
);
11009 /* RC/SAE immediate string should contain nothing more. */;
11012 as_bad (_("Junk after '}': '%s'"), imm_start
);
11016 exp
= &im_expressions
[i
.imm_operands
++];
11017 i
.op
[this_operand
].imms
= exp
;
11019 exp
->X_op
= O_constant
;
11020 exp
->X_add_number
= 0;
11021 exp
->X_add_symbol
= (symbolS
*) 0;
11022 exp
->X_op_symbol
= (symbolS
*) 0;
11024 i
.types
[this_operand
].bitfield
.imm8
= 1;
11028 /* Only string instructions can have a second memory operand, so
11029 reduce current_templates to just those if it contains any. */
11031 maybe_adjust_templates (void)
11033 const insn_template
*t
;
11035 gas_assert (i
.mem_operands
== 1);
11037 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11038 if (t
->opcode_modifier
.isstring
)
11041 if (t
< current_templates
->end
)
11043 static templates aux_templates
;
11044 bfd_boolean recheck
;
11046 aux_templates
.start
= t
;
11047 for (; t
< current_templates
->end
; ++t
)
11048 if (!t
->opcode_modifier
.isstring
)
11050 aux_templates
.end
= t
;
11052 /* Determine whether to re-check the first memory operand. */
11053 recheck
= (aux_templates
.start
!= current_templates
->start
11054 || t
!= current_templates
->end
);
11056 current_templates
= &aux_templates
;
11060 i
.mem_operands
= 0;
11061 if (i
.memop1_string
!= NULL
11062 && i386_index_check (i
.memop1_string
) == 0)
11064 i
.mem_operands
= 1;
11071 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11075 i386_att_operand (char *operand_string
)
11077 const reg_entry
*r
;
11079 char *op_string
= operand_string
;
11081 if (is_space_char (*op_string
))
11084 /* We check for an absolute prefix (differentiating,
11085 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11086 if (*op_string
== ABSOLUTE_PREFIX
)
11089 if (is_space_char (*op_string
))
11091 i
.jumpabsolute
= TRUE
;
11094 /* Check if operand is a register. */
11095 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11097 i386_operand_type temp
;
11102 /* Check for a segment override by searching for ':' after a
11103 segment register. */
11104 op_string
= end_op
;
11105 if (is_space_char (*op_string
))
11107 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11109 switch (r
->reg_num
)
11112 i
.seg
[i
.mem_operands
] = &es
;
11115 i
.seg
[i
.mem_operands
] = &cs
;
11118 i
.seg
[i
.mem_operands
] = &ss
;
11121 i
.seg
[i
.mem_operands
] = &ds
;
11124 i
.seg
[i
.mem_operands
] = &fs
;
11127 i
.seg
[i
.mem_operands
] = &gs
;
11131 /* Skip the ':' and whitespace. */
11133 if (is_space_char (*op_string
))
11136 if (!is_digit_char (*op_string
)
11137 && !is_identifier_char (*op_string
)
11138 && *op_string
!= '('
11139 && *op_string
!= ABSOLUTE_PREFIX
)
11141 as_bad (_("bad memory operand `%s'"), op_string
);
11144 /* Handle case of %es:*foo. */
11145 if (*op_string
== ABSOLUTE_PREFIX
)
11148 if (is_space_char (*op_string
))
11150 i
.jumpabsolute
= TRUE
;
11152 goto do_memory_reference
;
11155 /* Handle vector operations. */
11156 if (*op_string
== '{')
11158 op_string
= check_VecOperations (op_string
, NULL
);
11159 if (op_string
== NULL
)
11165 as_bad (_("junk `%s' after register"), op_string
);
11168 temp
= r
->reg_type
;
11169 temp
.bitfield
.baseindex
= 0;
11170 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11172 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11173 i
.op
[this_operand
].regs
= r
;
11176 else if (*op_string
== REGISTER_PREFIX
)
11178 as_bad (_("bad register name `%s'"), op_string
);
11181 else if (*op_string
== IMMEDIATE_PREFIX
)
11184 if (i
.jumpabsolute
)
11186 as_bad (_("immediate operand illegal with absolute jump"));
11189 if (!i386_immediate (op_string
))
11192 else if (RC_SAE_immediate (operand_string
))
11194 /* If it is a RC or SAE immediate, do nothing. */
11197 else if (is_digit_char (*op_string
)
11198 || is_identifier_char (*op_string
)
11199 || *op_string
== '"'
11200 || *op_string
== '(')
11202 /* This is a memory reference of some sort. */
11205 /* Start and end of displacement string expression (if found). */
11206 char *displacement_string_start
;
11207 char *displacement_string_end
;
11210 do_memory_reference
:
11211 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11213 if ((i
.mem_operands
== 1
11214 && !current_templates
->start
->opcode_modifier
.isstring
)
11215 || i
.mem_operands
== 2)
11217 as_bad (_("too many memory references for `%s'"),
11218 current_templates
->start
->name
);
11222 /* Check for base index form. We detect the base index form by
11223 looking for an ')' at the end of the operand, searching
11224 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11226 base_string
= op_string
+ strlen (op_string
);
11228 /* Handle vector operations. */
11229 vop_start
= strchr (op_string
, '{');
11230 if (vop_start
&& vop_start
< base_string
)
11232 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11234 base_string
= vop_start
;
11238 if (is_space_char (*base_string
))
11241 /* If we only have a displacement, set-up for it to be parsed later. */
11242 displacement_string_start
= op_string
;
11243 displacement_string_end
= base_string
+ 1;
11245 if (*base_string
== ')')
11248 unsigned int parens_balanced
= 1;
11249 /* We've already checked that the number of left & right ()'s are
11250 equal, so this loop will not be infinite. */
11254 if (*base_string
== ')')
11256 if (*base_string
== '(')
11259 while (parens_balanced
);
11261 temp_string
= base_string
;
11263 /* Skip past '(' and whitespace. */
11265 if (is_space_char (*base_string
))
11268 if (*base_string
== ','
11269 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11272 displacement_string_end
= temp_string
;
11274 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11278 if (i
.base_reg
== &bad_reg
)
11280 base_string
= end_op
;
11281 if (is_space_char (*base_string
))
11285 /* There may be an index reg or scale factor here. */
11286 if (*base_string
== ',')
11289 if (is_space_char (*base_string
))
11292 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11295 if (i
.index_reg
== &bad_reg
)
11297 base_string
= end_op
;
11298 if (is_space_char (*base_string
))
11300 if (*base_string
== ',')
11303 if (is_space_char (*base_string
))
11306 else if (*base_string
!= ')')
11308 as_bad (_("expecting `,' or `)' "
11309 "after index register in `%s'"),
11314 else if (*base_string
== REGISTER_PREFIX
)
11316 end_op
= strchr (base_string
, ',');
11319 as_bad (_("bad register name `%s'"), base_string
);
11323 /* Check for scale factor. */
11324 if (*base_string
!= ')')
11326 char *end_scale
= i386_scale (base_string
);
11331 base_string
= end_scale
;
11332 if (is_space_char (*base_string
))
11334 if (*base_string
!= ')')
11336 as_bad (_("expecting `)' "
11337 "after scale factor in `%s'"),
11342 else if (!i
.index_reg
)
11344 as_bad (_("expecting index register or scale factor "
11345 "after `,'; got '%c'"),
11350 else if (*base_string
!= ')')
11352 as_bad (_("expecting `,' or `)' "
11353 "after base register in `%s'"),
11358 else if (*base_string
== REGISTER_PREFIX
)
11360 end_op
= strchr (base_string
, ',');
11363 as_bad (_("bad register name `%s'"), base_string
);
11368 /* If there's an expression beginning the operand, parse it,
11369 assuming displacement_string_start and
11370 displacement_string_end are meaningful. */
11371 if (displacement_string_start
!= displacement_string_end
)
11373 if (!i386_displacement (displacement_string_start
,
11374 displacement_string_end
))
11378 /* Special case for (%dx) while doing input/output op. */
11380 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11381 && i
.base_reg
->reg_type
.bitfield
.word
11382 && i
.index_reg
== 0
11383 && i
.log2_scale_factor
== 0
11384 && i
.seg
[i
.mem_operands
] == 0
11385 && !operand_type_check (i
.types
[this_operand
], disp
))
11387 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11391 if (i386_index_check (operand_string
) == 0)
11393 i
.flags
[this_operand
] |= Operand_Mem
;
11394 if (i
.mem_operands
== 0)
11395 i
.memop1_string
= xstrdup (operand_string
);
11400 /* It's not a memory operand; argh! */
11401 as_bad (_("invalid char %s beginning operand %d `%s'"),
11402 output_invalid (*op_string
),
11407 return 1; /* Normal return. */
11410 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11411 that an rs_machine_dependent frag may reach. */
11414 i386_frag_max_var (fragS
*frag
)
11416 /* The only relaxable frags are for jumps.
11417 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11418 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11419 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11422 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11424 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11426 /* STT_GNU_IFUNC symbol must go through PLT. */
11427 if ((symbol_get_bfdsym (fr_symbol
)->flags
11428 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11431 if (!S_IS_EXTERNAL (fr_symbol
))
11432 /* Symbol may be weak or local. */
11433 return !S_IS_WEAK (fr_symbol
);
11435 /* Global symbols with non-default visibility can't be preempted. */
11436 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11439 if (fr_var
!= NO_RELOC
)
11440 switch ((enum bfd_reloc_code_real
) fr_var
)
11442 case BFD_RELOC_386_PLT32
:
11443 case BFD_RELOC_X86_64_PLT32
:
11444 /* Symbol with PLT relocation may be preempted. */
11450 /* Global symbols with default visibility in a shared library may be
11451 preempted by another definition. */
11456 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11457 Note also work for Skylake and Cascadelake.
11458 ---------------------------------------------------------------------
11459 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11460 | ------ | ----------- | ------- | -------- |
11462 | Jno | N | N | Y |
11463 | Jc/Jb | Y | N | Y |
11464 | Jae/Jnb | Y | N | Y |
11465 | Je/Jz | Y | Y | Y |
11466 | Jne/Jnz | Y | Y | Y |
11467 | Jna/Jbe | Y | N | Y |
11468 | Ja/Jnbe | Y | N | Y |
11470 | Jns | N | N | Y |
11471 | Jp/Jpe | N | N | Y |
11472 | Jnp/Jpo | N | N | Y |
11473 | Jl/Jnge | Y | Y | Y |
11474 | Jge/Jnl | Y | Y | Y |
11475 | Jle/Jng | Y | Y | Y |
11476 | Jg/Jnle | Y | Y | Y |
11477 --------------------------------------------------------------------- */
11479 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11481 if (mf_cmp
== mf_cmp_alu_cmp
)
11482 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11483 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11484 if (mf_cmp
== mf_cmp_incdec
)
11485 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11486 || mf_jcc
== mf_jcc_jle
);
11487 if (mf_cmp
== mf_cmp_test_and
)
11492 /* Return the next non-empty frag. */
11495 i386_next_non_empty_frag (fragS
*fragP
)
11497 /* There may be a frag with a ".fill 0" when there is no room in
11498 the current frag for frag_grow in output_insn. */
11499 for (fragP
= fragP
->fr_next
;
11501 && fragP
->fr_type
== rs_fill
11502 && fragP
->fr_fix
== 0);
11503 fragP
= fragP
->fr_next
)
11508 /* Return the next jcc frag after BRANCH_PADDING. */
11511 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11513 fragS
*branch_fragP
;
11517 if (pad_fragP
->fr_type
== rs_machine_dependent
11518 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11519 == BRANCH_PADDING
))
11521 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11522 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11524 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11525 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11526 pad_fragP
->tc_frag_data
.mf_type
))
11527 return branch_fragP
;
11533 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11536 i386_classify_machine_dependent_frag (fragS
*fragP
)
11540 fragS
*branch_fragP
;
11542 unsigned int max_prefix_length
;
11544 if (fragP
->tc_frag_data
.classified
)
11547 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11548 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11549 for (next_fragP
= fragP
;
11550 next_fragP
!= NULL
;
11551 next_fragP
= next_fragP
->fr_next
)
11553 next_fragP
->tc_frag_data
.classified
= 1;
11554 if (next_fragP
->fr_type
== rs_machine_dependent
)
11555 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11557 case BRANCH_PADDING
:
11558 /* The BRANCH_PADDING frag must be followed by a branch
11560 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11561 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11563 case FUSED_JCC_PADDING
:
11564 /* Check if this is a fused jcc:
11566 CMP like instruction
11570 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11571 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11572 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11575 /* The BRANCH_PADDING frag is merged with the
11576 FUSED_JCC_PADDING frag. */
11577 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11578 /* CMP like instruction size. */
11579 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11580 frag_wane (pad_fragP
);
11581 /* Skip to branch_fragP. */
11582 next_fragP
= branch_fragP
;
11584 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11586 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11588 next_fragP
->fr_subtype
11589 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11590 next_fragP
->tc_frag_data
.max_bytes
11591 = next_fragP
->tc_frag_data
.max_prefix_length
;
11592 /* This will be updated in the BRANCH_PREFIX scan. */
11593 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11596 frag_wane (next_fragP
);
11601 /* Stop if there is no BRANCH_PREFIX. */
11602 if (!align_branch_prefix_size
)
11605 /* Scan for BRANCH_PREFIX. */
11606 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11608 if (fragP
->fr_type
!= rs_machine_dependent
11609 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11613 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11614 COND_JUMP_PREFIX. */
11615 max_prefix_length
= 0;
11616 for (next_fragP
= fragP
;
11617 next_fragP
!= NULL
;
11618 next_fragP
= next_fragP
->fr_next
)
11620 if (next_fragP
->fr_type
== rs_fill
)
11621 /* Skip rs_fill frags. */
11623 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11624 /* Stop for all other frags. */
11627 /* rs_machine_dependent frags. */
11628 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11631 /* Count BRANCH_PREFIX frags. */
11632 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11634 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11635 frag_wane (next_fragP
);
11639 += next_fragP
->tc_frag_data
.max_bytes
;
11641 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11643 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11644 == FUSED_JCC_PADDING
))
11646 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11647 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11651 /* Stop for other rs_machine_dependent frags. */
11655 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11657 /* Skip to the next frag. */
11658 fragP
= next_fragP
;
11662 /* Compute padding size for
11665 CMP like instruction
11667 COND_JUMP/UNCOND_JUMP
11672 COND_JUMP/UNCOND_JUMP
11676 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11678 unsigned int offset
, size
, padding_size
;
11679 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11681 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11683 address
= fragP
->fr_address
;
11684 address
+= fragP
->fr_fix
;
11686 /* CMP like instrunction size. */
11687 size
= fragP
->tc_frag_data
.cmp_size
;
11689 /* The base size of the branch frag. */
11690 size
+= branch_fragP
->fr_fix
;
11692 /* Add opcode and displacement bytes for the rs_machine_dependent
11694 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11695 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11697 /* Check if branch is within boundary and doesn't end at the last
11699 offset
= address
& ((1U << align_branch_power
) - 1);
11700 if ((offset
+ size
) >= (1U << align_branch_power
))
11701 /* Padding needed to avoid crossing boundary. */
11702 padding_size
= (1U << align_branch_power
) - offset
;
11704 /* No padding needed. */
11707 /* The return value may be saved in tc_frag_data.length which is
11709 if (!fits_in_unsigned_byte (padding_size
))
11712 return padding_size
;
11715 /* i386_generic_table_relax_frag()
11717 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11718 grow/shrink padding to align branch frags. Hand others to
11722 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11724 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11725 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11727 long padding_size
= i386_branch_padding_size (fragP
, 0);
11728 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11730 /* When the BRANCH_PREFIX frag is used, the computed address
11731 must match the actual address and there should be no padding. */
11732 if (fragP
->tc_frag_data
.padding_address
11733 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11737 /* Update the padding size. */
11739 fragP
->tc_frag_data
.length
= padding_size
;
11743 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11745 fragS
*padding_fragP
, *next_fragP
;
11746 long padding_size
, left_size
, last_size
;
11748 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11749 if (!padding_fragP
)
11750 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11751 return (fragP
->tc_frag_data
.length
11752 - fragP
->tc_frag_data
.last_length
);
11754 /* Compute the relative address of the padding frag in the very
11755 first time where the BRANCH_PREFIX frag sizes are zero. */
11756 if (!fragP
->tc_frag_data
.padding_address
)
11757 fragP
->tc_frag_data
.padding_address
11758 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11760 /* First update the last length from the previous interation. */
11761 left_size
= fragP
->tc_frag_data
.prefix_length
;
11762 for (next_fragP
= fragP
;
11763 next_fragP
!= padding_fragP
;
11764 next_fragP
= next_fragP
->fr_next
)
11765 if (next_fragP
->fr_type
== rs_machine_dependent
11766 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11771 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11775 if (max
> left_size
)
11780 next_fragP
->tc_frag_data
.last_length
= size
;
11784 next_fragP
->tc_frag_data
.last_length
= 0;
11787 /* Check the padding size for the padding frag. */
11788 padding_size
= i386_branch_padding_size
11789 (padding_fragP
, (fragP
->fr_address
11790 + fragP
->tc_frag_data
.padding_address
));
11792 last_size
= fragP
->tc_frag_data
.prefix_length
;
11793 /* Check if there is change from the last interation. */
11794 if (padding_size
== last_size
)
11796 /* Update the expected address of the padding frag. */
11797 padding_fragP
->tc_frag_data
.padding_address
11798 = (fragP
->fr_address
+ padding_size
11799 + fragP
->tc_frag_data
.padding_address
);
11803 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11805 /* No padding if there is no sufficient room. Clear the
11806 expected address of the padding frag. */
11807 padding_fragP
->tc_frag_data
.padding_address
= 0;
11811 /* Store the expected address of the padding frag. */
11812 padding_fragP
->tc_frag_data
.padding_address
11813 = (fragP
->fr_address
+ padding_size
11814 + fragP
->tc_frag_data
.padding_address
);
11816 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11818 /* Update the length for the current interation. */
11819 left_size
= padding_size
;
11820 for (next_fragP
= fragP
;
11821 next_fragP
!= padding_fragP
;
11822 next_fragP
= next_fragP
->fr_next
)
11823 if (next_fragP
->fr_type
== rs_machine_dependent
11824 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11829 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11833 if (max
> left_size
)
11838 next_fragP
->tc_frag_data
.length
= size
;
11842 next_fragP
->tc_frag_data
.length
= 0;
11845 return (fragP
->tc_frag_data
.length
11846 - fragP
->tc_frag_data
.last_length
);
11848 return relax_frag (segment
, fragP
, stretch
);
11851 /* md_estimate_size_before_relax()
11853 Called just before relax() for rs_machine_dependent frags. The x86
11854 assembler uses these frags to handle variable size jump
11857 Any symbol that is now undefined will not become defined.
11858 Return the correct fr_subtype in the frag.
11859 Return the initial "guess for variable size of frag" to caller.
11860 The guess is actually the growth beyond the fixed part. Whatever
11861 we do to grow the fixed or variable part contributes to our
11865 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11867 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11868 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11869 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11871 i386_classify_machine_dependent_frag (fragP
);
11872 return fragP
->tc_frag_data
.length
;
11875 /* We've already got fragP->fr_subtype right; all we have to do is
11876 check for un-relaxable symbols. On an ELF system, we can't relax
11877 an externally visible symbol, because it may be overridden by a
11879 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11880 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11882 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11885 #if defined (OBJ_COFF) && defined (TE_PE)
11886 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11887 && S_IS_WEAK (fragP
->fr_symbol
))
11891 /* Symbol is undefined in this segment, or we need to keep a
11892 reloc so that weak symbols can be overridden. */
11893 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11894 enum bfd_reloc_code_real reloc_type
;
11895 unsigned char *opcode
;
11898 if (fragP
->fr_var
!= NO_RELOC
)
11899 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11900 else if (size
== 2)
11901 reloc_type
= BFD_RELOC_16_PCREL
;
11902 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11903 else if (need_plt32_p (fragP
->fr_symbol
))
11904 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11907 reloc_type
= BFD_RELOC_32_PCREL
;
11909 old_fr_fix
= fragP
->fr_fix
;
11910 opcode
= (unsigned char *) fragP
->fr_opcode
;
11912 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11915 /* Make jmp (0xeb) a (d)word displacement jump. */
11917 fragP
->fr_fix
+= size
;
11918 fix_new (fragP
, old_fr_fix
, size
,
11920 fragP
->fr_offset
, 1,
11926 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11928 /* Negate the condition, and branch past an
11929 unconditional jump. */
11932 /* Insert an unconditional jump. */
11934 /* We added two extra opcode bytes, and have a two byte
11936 fragP
->fr_fix
+= 2 + 2;
11937 fix_new (fragP
, old_fr_fix
+ 2, 2,
11939 fragP
->fr_offset
, 1,
11943 /* Fall through. */
11946 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11950 fragP
->fr_fix
+= 1;
11951 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11953 fragP
->fr_offset
, 1,
11954 BFD_RELOC_8_PCREL
);
11955 fixP
->fx_signed
= 1;
11959 /* This changes the byte-displacement jump 0x7N
11960 to the (d)word-displacement jump 0x0f,0x8N. */
11961 opcode
[1] = opcode
[0] + 0x10;
11962 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11963 /* We've added an opcode byte. */
11964 fragP
->fr_fix
+= 1 + size
;
11965 fix_new (fragP
, old_fr_fix
+ 1, size
,
11967 fragP
->fr_offset
, 1,
11972 BAD_CASE (fragP
->fr_subtype
);
11976 return fragP
->fr_fix
- old_fr_fix
;
11979 /* Guess size depending on current relax state. Initially the relax
11980 state will correspond to a short jump and we return 1, because
11981 the variable part of the frag (the branch offset) is one byte
11982 long. However, we can relax a section more than once and in that
11983 case we must either set fr_subtype back to the unrelaxed state,
11984 or return the value for the appropriate branch. */
11985 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11988 /* Called after relax() is finished.
11990 In: Address of frag.
11991 fr_type == rs_machine_dependent.
11992 fr_subtype is what the address relaxed to.
11994 Out: Any fixSs and constants are set up.
11995 Caller will turn frag into a ".space 0". */
11998 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12001 unsigned char *opcode
;
12002 unsigned char *where_to_put_displacement
= NULL
;
12003 offsetT target_address
;
12004 offsetT opcode_address
;
12005 unsigned int extension
= 0;
12006 offsetT displacement_from_opcode_start
;
12008 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12009 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12010 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12012 /* Generate nop padding. */
12013 unsigned int size
= fragP
->tc_frag_data
.length
;
12016 if (size
> fragP
->tc_frag_data
.max_bytes
)
12022 const char *branch
= "branch";
12023 const char *prefix
= "";
12024 fragS
*padding_fragP
;
12025 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12028 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12029 switch (fragP
->tc_frag_data
.default_prefix
)
12034 case CS_PREFIX_OPCODE
:
12037 case DS_PREFIX_OPCODE
:
12040 case ES_PREFIX_OPCODE
:
12043 case FS_PREFIX_OPCODE
:
12046 case GS_PREFIX_OPCODE
:
12049 case SS_PREFIX_OPCODE
:
12054 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12055 "%s within %d-byte boundary\n");
12057 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12058 "align %s within %d-byte boundary\n");
12062 padding_fragP
= fragP
;
12063 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12064 "%s within %d-byte boundary\n");
12068 switch (padding_fragP
->tc_frag_data
.branch_type
)
12070 case align_branch_jcc
:
12073 case align_branch_fused
:
12074 branch
= "fused jcc";
12076 case align_branch_jmp
:
12079 case align_branch_call
:
12082 case align_branch_indirect
:
12083 branch
= "indiret branch";
12085 case align_branch_ret
:
12092 fprintf (stdout
, msg
,
12093 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12094 (long long) fragP
->fr_address
, branch
,
12095 1 << align_branch_power
);
12097 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12098 memset (fragP
->fr_opcode
,
12099 fragP
->tc_frag_data
.default_prefix
, size
);
12101 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12103 fragP
->fr_fix
+= size
;
12108 opcode
= (unsigned char *) fragP
->fr_opcode
;
12110 /* Address we want to reach in file space. */
12111 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12113 /* Address opcode resides at in file space. */
12114 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12116 /* Displacement from opcode start to fill into instruction. */
12117 displacement_from_opcode_start
= target_address
- opcode_address
;
12119 if ((fragP
->fr_subtype
& BIG
) == 0)
12121 /* Don't have to change opcode. */
12122 extension
= 1; /* 1 opcode + 1 displacement */
12123 where_to_put_displacement
= &opcode
[1];
12127 if (no_cond_jump_promotion
12128 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12129 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12130 _("long jump required"));
12132 switch (fragP
->fr_subtype
)
12134 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12135 extension
= 4; /* 1 opcode + 4 displacement */
12137 where_to_put_displacement
= &opcode
[1];
12140 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12141 extension
= 2; /* 1 opcode + 2 displacement */
12143 where_to_put_displacement
= &opcode
[1];
12146 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12147 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12148 extension
= 5; /* 2 opcode + 4 displacement */
12149 opcode
[1] = opcode
[0] + 0x10;
12150 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12151 where_to_put_displacement
= &opcode
[2];
12154 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12155 extension
= 3; /* 2 opcode + 2 displacement */
12156 opcode
[1] = opcode
[0] + 0x10;
12157 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12158 where_to_put_displacement
= &opcode
[2];
12161 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12166 where_to_put_displacement
= &opcode
[3];
12170 BAD_CASE (fragP
->fr_subtype
);
12175 /* If size if less then four we are sure that the operand fits,
12176 but if it's 4, then it could be that the displacement is larger
12178 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12180 && ((addressT
) (displacement_from_opcode_start
- extension
12181 + ((addressT
) 1 << 31))
12182 > (((addressT
) 2 << 31) - 1)))
12184 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12185 _("jump target out of range"));
12186 /* Make us emit 0. */
12187 displacement_from_opcode_start
= extension
;
12189 /* Now put displacement after opcode. */
12190 md_number_to_chars ((char *) where_to_put_displacement
,
12191 (valueT
) (displacement_from_opcode_start
- extension
),
12192 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12193 fragP
->fr_fix
+= extension
;
12196 /* Apply a fixup (fixP) to segment data, once it has been determined
12197 by our caller that we have all the info we need to fix it up.
12199 Parameter valP is the pointer to the value of the bits.
12201 On the 386, immediates, displacements, and data pointers are all in
12202 the same (little-endian) format, so we don't need to care about which
12203 we are handling. */
12206 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12208 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12209 valueT value
= *valP
;
12211 #if !defined (TE_Mach)
12212 if (fixP
->fx_pcrel
)
12214 switch (fixP
->fx_r_type
)
12220 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12223 case BFD_RELOC_X86_64_32S
:
12224 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12227 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12230 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12235 if (fixP
->fx_addsy
!= NULL
12236 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12237 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12238 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12239 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12240 && !use_rela_relocations
)
12242 /* This is a hack. There should be a better way to handle this.
12243 This covers for the fact that bfd_install_relocation will
12244 subtract the current location (for partial_inplace, PC relative
12245 relocations); see more below. */
12249 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12252 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12254 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12257 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12259 if ((sym_seg
== seg
12260 || (symbol_section_p (fixP
->fx_addsy
)
12261 && sym_seg
!= absolute_section
))
12262 && !generic_force_reloc (fixP
))
12264 /* Yes, we add the values in twice. This is because
12265 bfd_install_relocation subtracts them out again. I think
12266 bfd_install_relocation is broken, but I don't dare change
12268 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12272 #if defined (OBJ_COFF) && defined (TE_PE)
12273 /* For some reason, the PE format does not store a
12274 section address offset for a PC relative symbol. */
12275 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12276 || S_IS_WEAK (fixP
->fx_addsy
))
12277 value
+= md_pcrel_from (fixP
);
12280 #if defined (OBJ_COFF) && defined (TE_PE)
12281 if (fixP
->fx_addsy
!= NULL
12282 && S_IS_WEAK (fixP
->fx_addsy
)
12283 /* PR 16858: Do not modify weak function references. */
12284 && ! fixP
->fx_pcrel
)
12286 #if !defined (TE_PEP)
12287 /* For x86 PE weak function symbols are neither PC-relative
12288 nor do they set S_IS_FUNCTION. So the only reliable way
12289 to detect them is to check the flags of their containing
12291 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12292 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12296 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12300 /* Fix a few things - the dynamic linker expects certain values here,
12301 and we must not disappoint it. */
12302 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12303 if (IS_ELF
&& fixP
->fx_addsy
)
12304 switch (fixP
->fx_r_type
)
12306 case BFD_RELOC_386_PLT32
:
12307 case BFD_RELOC_X86_64_PLT32
:
12308 /* Make the jump instruction point to the address of the operand.
12309 At runtime we merely add the offset to the actual PLT entry.
12310 NB: Subtract the offset size only for jump instructions. */
12311 if (fixP
->fx_pcrel
)
12315 case BFD_RELOC_386_TLS_GD
:
12316 case BFD_RELOC_386_TLS_LDM
:
12317 case BFD_RELOC_386_TLS_IE_32
:
12318 case BFD_RELOC_386_TLS_IE
:
12319 case BFD_RELOC_386_TLS_GOTIE
:
12320 case BFD_RELOC_386_TLS_GOTDESC
:
12321 case BFD_RELOC_X86_64_TLSGD
:
12322 case BFD_RELOC_X86_64_TLSLD
:
12323 case BFD_RELOC_X86_64_GOTTPOFF
:
12324 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12325 value
= 0; /* Fully resolved at runtime. No addend. */
12327 case BFD_RELOC_386_TLS_LE
:
12328 case BFD_RELOC_386_TLS_LDO_32
:
12329 case BFD_RELOC_386_TLS_LE_32
:
12330 case BFD_RELOC_X86_64_DTPOFF32
:
12331 case BFD_RELOC_X86_64_DTPOFF64
:
12332 case BFD_RELOC_X86_64_TPOFF32
:
12333 case BFD_RELOC_X86_64_TPOFF64
:
12334 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12337 case BFD_RELOC_386_TLS_DESC_CALL
:
12338 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12339 value
= 0; /* Fully resolved at runtime. No addend. */
12340 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12344 case BFD_RELOC_VTABLE_INHERIT
:
12345 case BFD_RELOC_VTABLE_ENTRY
:
12352 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12354 #endif /* !defined (TE_Mach) */
12356 /* Are we finished with this relocation now? */
12357 if (fixP
->fx_addsy
== NULL
)
12359 #if defined (OBJ_COFF) && defined (TE_PE)
12360 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12363 /* Remember value for tc_gen_reloc. */
12364 fixP
->fx_addnumber
= value
;
12365 /* Clear out the frag for now. */
12369 else if (use_rela_relocations
)
12371 fixP
->fx_no_overflow
= 1;
12372 /* Remember value for tc_gen_reloc. */
12373 fixP
->fx_addnumber
= value
;
12377 md_number_to_chars (p
, value
, fixP
->fx_size
);
12381 md_atof (int type
, char *litP
, int *sizeP
)
12383 /* This outputs the LITTLENUMs in REVERSE order;
12384 in accord with the bigendian 386. */
12385 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12388 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12391 output_invalid (int c
)
12394 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12397 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12398 "(0x%x)", (unsigned char) c
);
12399 return output_invalid_buf
;
12402 /* Verify that @r can be used in the current context. */
12404 static bfd_boolean
check_register (const reg_entry
*r
)
12406 if (allow_pseudo_reg
)
12409 if (operand_type_all_zero (&r
->reg_type
))
12412 if ((r
->reg_type
.bitfield
.dword
12413 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12414 || r
->reg_type
.bitfield
.class == RegCR
12415 || r
->reg_type
.bitfield
.class == RegDR
)
12416 && !cpu_arch_flags
.bitfield
.cpui386
)
12419 if (r
->reg_type
.bitfield
.class == RegTR
12420 && (flag_code
== CODE_64BIT
12421 || !cpu_arch_flags
.bitfield
.cpui386
12422 || cpu_arch_isa_flags
.bitfield
.cpui586
12423 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12426 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12429 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12431 if (r
->reg_type
.bitfield
.zmmword
12432 || r
->reg_type
.bitfield
.class == RegMask
)
12435 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12437 if (r
->reg_type
.bitfield
.ymmword
)
12440 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12445 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12448 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12449 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12452 /* Upper 16 vector registers are only available with VREX in 64bit
12453 mode, and require EVEX encoding. */
12454 if (r
->reg_flags
& RegVRex
)
12456 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12457 || flag_code
!= CODE_64BIT
)
12460 if (i
.vec_encoding
== vex_encoding_default
)
12461 i
.vec_encoding
= vex_encoding_evex
;
12462 else if (i
.vec_encoding
!= vex_encoding_evex
)
12463 i
.vec_encoding
= vex_encoding_error
;
12466 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12467 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12468 && flag_code
!= CODE_64BIT
)
12471 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12478 /* REG_STRING starts *before* REGISTER_PREFIX. */
12480 static const reg_entry
*
12481 parse_real_register (char *reg_string
, char **end_op
)
12483 char *s
= reg_string
;
12485 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12486 const reg_entry
*r
;
12488 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12489 if (*s
== REGISTER_PREFIX
)
12492 if (is_space_char (*s
))
12495 p
= reg_name_given
;
12496 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12498 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12499 return (const reg_entry
*) NULL
;
12503 /* For naked regs, make sure that we are not dealing with an identifier.
12504 This prevents confusing an identifier like `eax_var' with register
12506 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12507 return (const reg_entry
*) NULL
;
12511 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
12513 /* Handle floating point regs, allowing spaces in the (i) part. */
12514 if (r
== i386_regtab
/* %st is first entry of table */)
12516 if (!cpu_arch_flags
.bitfield
.cpu8087
12517 && !cpu_arch_flags
.bitfield
.cpu287
12518 && !cpu_arch_flags
.bitfield
.cpu387
12519 && !allow_pseudo_reg
)
12520 return (const reg_entry
*) NULL
;
12522 if (is_space_char (*s
))
12527 if (is_space_char (*s
))
12529 if (*s
>= '0' && *s
<= '7')
12531 int fpr
= *s
- '0';
12533 if (is_space_char (*s
))
12538 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
12543 /* We have "%st(" then garbage. */
12544 return (const reg_entry
*) NULL
;
12548 return r
&& check_register (r
) ? r
: NULL
;
12551 /* REG_STRING starts *before* REGISTER_PREFIX. */
12553 static const reg_entry
*
12554 parse_register (char *reg_string
, char **end_op
)
12556 const reg_entry
*r
;
12558 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12559 r
= parse_real_register (reg_string
, end_op
);
12564 char *save
= input_line_pointer
;
12568 input_line_pointer
= reg_string
;
12569 c
= get_symbol_name (®_string
);
12570 symbolP
= symbol_find (reg_string
);
12571 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12573 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12575 know (e
->X_op
== O_register
);
12576 know (e
->X_add_number
>= 0
12577 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12578 r
= i386_regtab
+ e
->X_add_number
;
12579 if (!check_register (r
))
12581 as_bad (_("register '%s%s' cannot be used here"),
12582 register_prefix
, r
->reg_name
);
12585 *end_op
= input_line_pointer
;
12587 *input_line_pointer
= c
;
12588 input_line_pointer
= save
;
12594 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12596 const reg_entry
*r
;
12597 char *end
= input_line_pointer
;
12600 r
= parse_register (name
, &input_line_pointer
);
12601 if (r
&& end
<= input_line_pointer
)
12603 *nextcharP
= *input_line_pointer
;
12604 *input_line_pointer
= 0;
12607 e
->X_op
= O_register
;
12608 e
->X_add_number
= r
- i386_regtab
;
12611 e
->X_op
= O_illegal
;
12614 input_line_pointer
= end
;
12616 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12620 md_operand (expressionS
*e
)
12623 const reg_entry
*r
;
12625 switch (*input_line_pointer
)
12627 case REGISTER_PREFIX
:
12628 r
= parse_real_register (input_line_pointer
, &end
);
12631 e
->X_op
= O_register
;
12632 e
->X_add_number
= r
- i386_regtab
;
12633 input_line_pointer
= end
;
12638 gas_assert (intel_syntax
);
12639 end
= input_line_pointer
++;
12641 if (*input_line_pointer
== ']')
12643 ++input_line_pointer
;
12644 e
->X_op_symbol
= make_expr_symbol (e
);
12645 e
->X_add_symbol
= NULL
;
12646 e
->X_add_number
= 0;
12651 e
->X_op
= O_absent
;
12652 input_line_pointer
= end
;
12659 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12660 const char *md_shortopts
= "kVQ:sqnO::";
12662 const char *md_shortopts
= "qnO::";
12665 #define OPTION_32 (OPTION_MD_BASE + 0)
12666 #define OPTION_64 (OPTION_MD_BASE + 1)
12667 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12668 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12669 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12670 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12671 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12672 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12673 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12674 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12675 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12676 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12677 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12678 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12679 #define OPTION_X32 (OPTION_MD_BASE + 14)
12680 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12681 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12682 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12683 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12684 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12685 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12686 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12687 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12688 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12689 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12690 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12691 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12692 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12693 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12694 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12695 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12696 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12697 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12698 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12700 struct option md_longopts
[] =
12702 {"32", no_argument
, NULL
, OPTION_32
},
12703 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12704 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12705 {"64", no_argument
, NULL
, OPTION_64
},
12707 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12708 {"x32", no_argument
, NULL
, OPTION_X32
},
12709 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12710 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12712 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12713 {"march", required_argument
, NULL
, OPTION_MARCH
},
12714 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12715 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12716 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12717 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12718 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12719 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12720 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12721 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12722 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12723 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12724 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12725 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12726 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12727 # if defined (TE_PE) || defined (TE_PEP)
12728 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12730 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12731 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12732 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12733 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12734 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12735 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12736 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12737 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12738 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12739 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12740 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12741 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12742 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12743 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12744 {NULL
, no_argument
, NULL
, 0}
12746 size_t md_longopts_size
= sizeof (md_longopts
);
12749 md_parse_option (int c
, const char *arg
)
12752 char *arch
, *next
, *saved
, *type
;
12757 optimize_align_code
= 0;
12761 quiet_warnings
= 1;
12764 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12765 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12766 should be emitted or not. FIXME: Not implemented. */
12768 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12772 /* -V: SVR4 argument to print version ID. */
12774 print_version_id ();
12777 /* -k: Ignore for FreeBSD compatibility. */
12782 /* -s: On i386 Solaris, this tells the native assembler to use
12783 .stab instead of .stab.excl. We always use .stab anyhow. */
12786 case OPTION_MSHARED
:
12790 case OPTION_X86_USED_NOTE
:
12791 if (strcasecmp (arg
, "yes") == 0)
12793 else if (strcasecmp (arg
, "no") == 0)
12796 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12801 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12802 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12805 const char **list
, **l
;
12807 list
= bfd_target_list ();
12808 for (l
= list
; *l
!= NULL
; l
++)
12809 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12810 || strcmp (*l
, "coff-x86-64") == 0
12811 || strcmp (*l
, "pe-x86-64") == 0
12812 || strcmp (*l
, "pei-x86-64") == 0
12813 || strcmp (*l
, "mach-o-x86-64") == 0)
12815 default_arch
= "x86_64";
12819 as_fatal (_("no compiled in support for x86_64"));
12825 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12829 const char **list
, **l
;
12831 list
= bfd_target_list ();
12832 for (l
= list
; *l
!= NULL
; l
++)
12833 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12835 default_arch
= "x86_64:32";
12839 as_fatal (_("no compiled in support for 32bit x86_64"));
12843 as_fatal (_("32bit x86_64 is only supported for ELF"));
12848 default_arch
= "i386";
12851 case OPTION_DIVIDE
:
12852 #ifdef SVR4_COMMENT_CHARS
12857 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12859 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12863 i386_comment_chars
= n
;
12869 saved
= xstrdup (arg
);
12871 /* Allow -march=+nosse. */
12877 as_fatal (_("invalid -march= option: `%s'"), arg
);
12878 next
= strchr (arch
, '+');
12881 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12883 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12886 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12889 cpu_arch_name
= cpu_arch
[j
].name
;
12890 cpu_sub_arch_name
= NULL
;
12891 cpu_arch_flags
= cpu_arch
[j
].flags
;
12892 cpu_arch_isa
= cpu_arch
[j
].type
;
12893 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12894 if (!cpu_arch_tune_set
)
12896 cpu_arch_tune
= cpu_arch_isa
;
12897 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12901 else if (*cpu_arch
[j
].name
== '.'
12902 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12904 /* ISA extension. */
12905 i386_cpu_flags flags
;
12907 flags
= cpu_flags_or (cpu_arch_flags
,
12908 cpu_arch
[j
].flags
);
12910 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12912 if (cpu_sub_arch_name
)
12914 char *name
= cpu_sub_arch_name
;
12915 cpu_sub_arch_name
= concat (name
,
12917 (const char *) NULL
);
12921 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12922 cpu_arch_flags
= flags
;
12923 cpu_arch_isa_flags
= flags
;
12927 = cpu_flags_or (cpu_arch_isa_flags
,
12928 cpu_arch
[j
].flags
);
12933 if (j
>= ARRAY_SIZE (cpu_arch
))
12935 /* Disable an ISA extension. */
12936 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12937 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12939 i386_cpu_flags flags
;
12941 flags
= cpu_flags_and_not (cpu_arch_flags
,
12942 cpu_noarch
[j
].flags
);
12943 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12945 if (cpu_sub_arch_name
)
12947 char *name
= cpu_sub_arch_name
;
12948 cpu_sub_arch_name
= concat (arch
,
12949 (const char *) NULL
);
12953 cpu_sub_arch_name
= xstrdup (arch
);
12954 cpu_arch_flags
= flags
;
12955 cpu_arch_isa_flags
= flags
;
12960 if (j
>= ARRAY_SIZE (cpu_noarch
))
12961 j
= ARRAY_SIZE (cpu_arch
);
12964 if (j
>= ARRAY_SIZE (cpu_arch
))
12965 as_fatal (_("invalid -march= option: `%s'"), arg
);
12969 while (next
!= NULL
);
12975 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12976 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12978 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12980 cpu_arch_tune_set
= 1;
12981 cpu_arch_tune
= cpu_arch
[j
].type
;
12982 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12986 if (j
>= ARRAY_SIZE (cpu_arch
))
12987 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12990 case OPTION_MMNEMONIC
:
12991 if (strcasecmp (arg
, "att") == 0)
12992 intel_mnemonic
= 0;
12993 else if (strcasecmp (arg
, "intel") == 0)
12994 intel_mnemonic
= 1;
12996 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12999 case OPTION_MSYNTAX
:
13000 if (strcasecmp (arg
, "att") == 0)
13002 else if (strcasecmp (arg
, "intel") == 0)
13005 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13008 case OPTION_MINDEX_REG
:
13009 allow_index_reg
= 1;
13012 case OPTION_MNAKED_REG
:
13013 allow_naked_reg
= 1;
13016 case OPTION_MSSE2AVX
:
13020 case OPTION_MSSE_CHECK
:
13021 if (strcasecmp (arg
, "error") == 0)
13022 sse_check
= check_error
;
13023 else if (strcasecmp (arg
, "warning") == 0)
13024 sse_check
= check_warning
;
13025 else if (strcasecmp (arg
, "none") == 0)
13026 sse_check
= check_none
;
13028 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13031 case OPTION_MOPERAND_CHECK
:
13032 if (strcasecmp (arg
, "error") == 0)
13033 operand_check
= check_error
;
13034 else if (strcasecmp (arg
, "warning") == 0)
13035 operand_check
= check_warning
;
13036 else if (strcasecmp (arg
, "none") == 0)
13037 operand_check
= check_none
;
13039 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13042 case OPTION_MAVXSCALAR
:
13043 if (strcasecmp (arg
, "128") == 0)
13044 avxscalar
= vex128
;
13045 else if (strcasecmp (arg
, "256") == 0)
13046 avxscalar
= vex256
;
13048 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13051 case OPTION_MVEXWIG
:
13052 if (strcmp (arg
, "0") == 0)
13054 else if (strcmp (arg
, "1") == 0)
13057 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13060 case OPTION_MADD_BND_PREFIX
:
13061 add_bnd_prefix
= 1;
13064 case OPTION_MEVEXLIG
:
13065 if (strcmp (arg
, "128") == 0)
13066 evexlig
= evexl128
;
13067 else if (strcmp (arg
, "256") == 0)
13068 evexlig
= evexl256
;
13069 else if (strcmp (arg
, "512") == 0)
13070 evexlig
= evexl512
;
13072 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13075 case OPTION_MEVEXRCIG
:
13076 if (strcmp (arg
, "rne") == 0)
13078 else if (strcmp (arg
, "rd") == 0)
13080 else if (strcmp (arg
, "ru") == 0)
13082 else if (strcmp (arg
, "rz") == 0)
13085 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13088 case OPTION_MEVEXWIG
:
13089 if (strcmp (arg
, "0") == 0)
13091 else if (strcmp (arg
, "1") == 0)
13094 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13097 # if defined (TE_PE) || defined (TE_PEP)
13098 case OPTION_MBIG_OBJ
:
13103 case OPTION_MOMIT_LOCK_PREFIX
:
13104 if (strcasecmp (arg
, "yes") == 0)
13105 omit_lock_prefix
= 1;
13106 else if (strcasecmp (arg
, "no") == 0)
13107 omit_lock_prefix
= 0;
13109 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13112 case OPTION_MFENCE_AS_LOCK_ADD
:
13113 if (strcasecmp (arg
, "yes") == 0)
13115 else if (strcasecmp (arg
, "no") == 0)
13118 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13121 case OPTION_MLFENCE_AFTER_LOAD
:
13122 if (strcasecmp (arg
, "yes") == 0)
13123 lfence_after_load
= 1;
13124 else if (strcasecmp (arg
, "no") == 0)
13125 lfence_after_load
= 0;
13127 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13130 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13131 if (strcasecmp (arg
, "all") == 0)
13133 lfence_before_indirect_branch
= lfence_branch_all
;
13134 if (lfence_before_ret
== lfence_before_ret_none
)
13135 lfence_before_ret
= lfence_before_ret_shl
;
13137 else if (strcasecmp (arg
, "memory") == 0)
13138 lfence_before_indirect_branch
= lfence_branch_memory
;
13139 else if (strcasecmp (arg
, "register") == 0)
13140 lfence_before_indirect_branch
= lfence_branch_register
;
13141 else if (strcasecmp (arg
, "none") == 0)
13142 lfence_before_indirect_branch
= lfence_branch_none
;
13144 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13148 case OPTION_MLFENCE_BEFORE_RET
:
13149 if (strcasecmp (arg
, "or") == 0)
13150 lfence_before_ret
= lfence_before_ret_or
;
13151 else if (strcasecmp (arg
, "not") == 0)
13152 lfence_before_ret
= lfence_before_ret_not
;
13153 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13154 lfence_before_ret
= lfence_before_ret_shl
;
13155 else if (strcasecmp (arg
, "none") == 0)
13156 lfence_before_ret
= lfence_before_ret_none
;
13158 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13162 case OPTION_MRELAX_RELOCATIONS
:
13163 if (strcasecmp (arg
, "yes") == 0)
13164 generate_relax_relocations
= 1;
13165 else if (strcasecmp (arg
, "no") == 0)
13166 generate_relax_relocations
= 0;
13168 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13171 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13174 long int align
= strtoul (arg
, &end
, 0);
13179 align_branch_power
= 0;
13182 else if (align
>= 16)
13185 for (align_power
= 0;
13187 align
>>= 1, align_power
++)
13189 /* Limit alignment power to 31. */
13190 if (align
== 1 && align_power
< 32)
13192 align_branch_power
= align_power
;
13197 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13201 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13204 int align
= strtoul (arg
, &end
, 0);
13205 /* Some processors only support 5 prefixes. */
13206 if (*end
== '\0' && align
>= 0 && align
< 6)
13208 align_branch_prefix_size
= align
;
13211 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13216 case OPTION_MALIGN_BRANCH
:
13218 saved
= xstrdup (arg
);
13222 next
= strchr (type
, '+');
13225 if (strcasecmp (type
, "jcc") == 0)
13226 align_branch
|= align_branch_jcc_bit
;
13227 else if (strcasecmp (type
, "fused") == 0)
13228 align_branch
|= align_branch_fused_bit
;
13229 else if (strcasecmp (type
, "jmp") == 0)
13230 align_branch
|= align_branch_jmp_bit
;
13231 else if (strcasecmp (type
, "call") == 0)
13232 align_branch
|= align_branch_call_bit
;
13233 else if (strcasecmp (type
, "ret") == 0)
13234 align_branch
|= align_branch_ret_bit
;
13235 else if (strcasecmp (type
, "indirect") == 0)
13236 align_branch
|= align_branch_indirect_bit
;
13238 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13241 while (next
!= NULL
);
13245 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13246 align_branch_power
= 5;
13247 align_branch_prefix_size
= 5;
13248 align_branch
= (align_branch_jcc_bit
13249 | align_branch_fused_bit
13250 | align_branch_jmp_bit
);
13253 case OPTION_MAMD64
:
13257 case OPTION_MINTEL64
:
13265 /* Turn off -Os. */
13266 optimize_for_space
= 0;
13268 else if (*arg
== 's')
13270 optimize_for_space
= 1;
13271 /* Turn on all encoding optimizations. */
13272 optimize
= INT_MAX
;
13276 optimize
= atoi (arg
);
13277 /* Turn off -Os. */
13278 optimize_for_space
= 0;
13288 #define MESSAGE_TEMPLATE \
13292 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13293 int *left_p
, const char *name
, int len
)
13295 int size
= sizeof (MESSAGE_TEMPLATE
);
13296 int left
= *left_p
;
13298 /* Reserve 2 spaces for ", " or ",\0" */
13301 /* Check if there is any room. */
13309 p
= mempcpy (p
, name
, len
);
13313 /* Output the current message now and start a new one. */
13316 fprintf (stream
, "%s\n", message
);
13318 left
= size
- (start
- message
) - len
- 2;
13320 gas_assert (left
>= 0);
13322 p
= mempcpy (p
, name
, len
);
13330 show_arch (FILE *stream
, int ext
, int check
)
13332 static char message
[] = MESSAGE_TEMPLATE
;
13333 char *start
= message
+ 27;
13335 int size
= sizeof (MESSAGE_TEMPLATE
);
13342 left
= size
- (start
- message
);
13343 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13345 /* Should it be skipped? */
13346 if (cpu_arch
[j
].skip
)
13349 name
= cpu_arch
[j
].name
;
13350 len
= cpu_arch
[j
].len
;
13353 /* It is an extension. Skip if we aren't asked to show it. */
13364 /* It is an processor. Skip if we show only extension. */
13367 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13369 /* It is an impossible processor - skip. */
13373 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13376 /* Display disabled extensions. */
13378 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13380 name
= cpu_noarch
[j
].name
;
13381 len
= cpu_noarch
[j
].len
;
13382 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13387 fprintf (stream
, "%s\n", message
);
13391 md_show_usage (FILE *stream
)
13393 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13394 fprintf (stream
, _("\
13395 -Qy, -Qn ignored\n\
13396 -V print assembler version number\n\
13399 fprintf (stream
, _("\
13400 -n Do not optimize code alignment\n\
13401 -q quieten some warnings\n"));
13402 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13403 fprintf (stream
, _("\
13406 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13407 || defined (TE_PE) || defined (TE_PEP))
13408 fprintf (stream
, _("\
13409 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13411 #ifdef SVR4_COMMENT_CHARS
13412 fprintf (stream
, _("\
13413 --divide do not treat `/' as a comment character\n"));
13415 fprintf (stream
, _("\
13416 --divide ignored\n"));
13418 fprintf (stream
, _("\
13419 -march=CPU[,+EXTENSION...]\n\
13420 generate code for CPU and EXTENSION, CPU is one of:\n"));
13421 show_arch (stream
, 0, 1);
13422 fprintf (stream
, _("\
13423 EXTENSION is combination of:\n"));
13424 show_arch (stream
, 1, 0);
13425 fprintf (stream
, _("\
13426 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13427 show_arch (stream
, 0, 0);
13428 fprintf (stream
, _("\
13429 -msse2avx encode SSE instructions with VEX prefix\n"));
13430 fprintf (stream
, _("\
13431 -msse-check=[none|error|warning] (default: warning)\n\
13432 check SSE instructions\n"));
13433 fprintf (stream
, _("\
13434 -moperand-check=[none|error|warning] (default: warning)\n\
13435 check operand combinations for validity\n"));
13436 fprintf (stream
, _("\
13437 -mavxscalar=[128|256] (default: 128)\n\
13438 encode scalar AVX instructions with specific vector\n\
13440 fprintf (stream
, _("\
13441 -mvexwig=[0|1] (default: 0)\n\
13442 encode VEX instructions with specific VEX.W value\n\
13443 for VEX.W bit ignored instructions\n"));
13444 fprintf (stream
, _("\
13445 -mevexlig=[128|256|512] (default: 128)\n\
13446 encode scalar EVEX instructions with specific vector\n\
13448 fprintf (stream
, _("\
13449 -mevexwig=[0|1] (default: 0)\n\
13450 encode EVEX instructions with specific EVEX.W value\n\
13451 for EVEX.W bit ignored instructions\n"));
13452 fprintf (stream
, _("\
13453 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13454 encode EVEX instructions with specific EVEX.RC value\n\
13455 for SAE-only ignored instructions\n"));
13456 fprintf (stream
, _("\
13457 -mmnemonic=[att|intel] "));
13458 if (SYSV386_COMPAT
)
13459 fprintf (stream
, _("(default: att)\n"));
13461 fprintf (stream
, _("(default: intel)\n"));
13462 fprintf (stream
, _("\
13463 use AT&T/Intel mnemonic\n"));
13464 fprintf (stream
, _("\
13465 -msyntax=[att|intel] (default: att)\n\
13466 use AT&T/Intel syntax\n"));
13467 fprintf (stream
, _("\
13468 -mindex-reg support pseudo index registers\n"));
13469 fprintf (stream
, _("\
13470 -mnaked-reg don't require `%%' prefix for registers\n"));
13471 fprintf (stream
, _("\
13472 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13473 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13474 fprintf (stream
, _("\
13475 -mshared disable branch optimization for shared code\n"));
13476 fprintf (stream
, _("\
13477 -mx86-used-note=[no|yes] "));
13478 if (DEFAULT_X86_USED_NOTE
)
13479 fprintf (stream
, _("(default: yes)\n"));
13481 fprintf (stream
, _("(default: no)\n"));
13482 fprintf (stream
, _("\
13483 generate x86 used ISA and feature properties\n"));
13485 #if defined (TE_PE) || defined (TE_PEP)
13486 fprintf (stream
, _("\
13487 -mbig-obj generate big object files\n"));
13489 fprintf (stream
, _("\
13490 -momit-lock-prefix=[no|yes] (default: no)\n\
13491 strip all lock prefixes\n"));
13492 fprintf (stream
, _("\
13493 -mfence-as-lock-add=[no|yes] (default: no)\n\
13494 encode lfence, mfence and sfence as\n\
13495 lock addl $0x0, (%%{re}sp)\n"));
13496 fprintf (stream
, _("\
13497 -mrelax-relocations=[no|yes] "));
13498 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13499 fprintf (stream
, _("(default: yes)\n"));
13501 fprintf (stream
, _("(default: no)\n"));
13502 fprintf (stream
, _("\
13503 generate relax relocations\n"));
13504 fprintf (stream
, _("\
13505 -malign-branch-boundary=NUM (default: 0)\n\
13506 align branches within NUM byte boundary\n"));
13507 fprintf (stream
, _("\
13508 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13509 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13511 specify types of branches to align\n"));
13512 fprintf (stream
, _("\
13513 -malign-branch-prefix-size=NUM (default: 5)\n\
13514 align branches with NUM prefixes per instruction\n"));
13515 fprintf (stream
, _("\
13516 -mbranches-within-32B-boundaries\n\
13517 align branches within 32 byte boundary\n"));
13518 fprintf (stream
, _("\
13519 -mlfence-after-load=[no|yes] (default: no)\n\
13520 generate lfence after load\n"));
13521 fprintf (stream
, _("\
13522 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13523 generate lfence before indirect near branch\n"));
13524 fprintf (stream
, _("\
13525 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13526 generate lfence before ret\n"));
13527 fprintf (stream
, _("\
13528 -mamd64 accept only AMD64 ISA [default]\n"));
13529 fprintf (stream
, _("\
13530 -mintel64 accept only Intel64 ISA\n"));
13533 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13534 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13535 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13537 /* Pick the target format to use. */
13540 i386_target_format (void)
13542 if (!strncmp (default_arch
, "x86_64", 6))
13544 update_code_flag (CODE_64BIT
, 1);
13545 if (default_arch
[6] == '\0')
13546 x86_elf_abi
= X86_64_ABI
;
13548 x86_elf_abi
= X86_64_X32_ABI
;
13550 else if (!strcmp (default_arch
, "i386"))
13551 update_code_flag (CODE_32BIT
, 1);
13552 else if (!strcmp (default_arch
, "iamcu"))
13554 update_code_flag (CODE_32BIT
, 1);
13555 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13557 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13558 cpu_arch_name
= "iamcu";
13559 cpu_sub_arch_name
= NULL
;
13560 cpu_arch_flags
= iamcu_flags
;
13561 cpu_arch_isa
= PROCESSOR_IAMCU
;
13562 cpu_arch_isa_flags
= iamcu_flags
;
13563 if (!cpu_arch_tune_set
)
13565 cpu_arch_tune
= cpu_arch_isa
;
13566 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13569 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13570 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13574 as_fatal (_("unknown architecture"));
13576 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13577 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13578 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13579 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13581 switch (OUTPUT_FLAVOR
)
13583 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13584 case bfd_target_aout_flavour
:
13585 return AOUT_TARGET_FORMAT
;
13587 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13588 # if defined (TE_PE) || defined (TE_PEP)
13589 case bfd_target_coff_flavour
:
13590 if (flag_code
== CODE_64BIT
)
13591 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13593 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13594 # elif defined (TE_GO32)
13595 case bfd_target_coff_flavour
:
13596 return "coff-go32";
13598 case bfd_target_coff_flavour
:
13599 return "coff-i386";
13602 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13603 case bfd_target_elf_flavour
:
13605 const char *format
;
13607 switch (x86_elf_abi
)
13610 format
= ELF_TARGET_FORMAT
;
13612 tls_get_addr
= "___tls_get_addr";
13616 use_rela_relocations
= 1;
13619 tls_get_addr
= "__tls_get_addr";
13621 format
= ELF_TARGET_FORMAT64
;
13623 case X86_64_X32_ABI
:
13624 use_rela_relocations
= 1;
13627 tls_get_addr
= "__tls_get_addr";
13629 disallow_64bit_reloc
= 1;
13630 format
= ELF_TARGET_FORMAT32
;
13633 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13635 if (x86_elf_abi
!= X86_64_ABI
)
13636 as_fatal (_("Intel L1OM is 64bit only"));
13637 return ELF_TARGET_L1OM_FORMAT
;
13639 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13641 if (x86_elf_abi
!= X86_64_ABI
)
13642 as_fatal (_("Intel K1OM is 64bit only"));
13643 return ELF_TARGET_K1OM_FORMAT
;
13645 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13647 if (x86_elf_abi
!= I386_ABI
)
13648 as_fatal (_("Intel MCU is 32bit only"));
13649 return ELF_TARGET_IAMCU_FORMAT
;
13655 #if defined (OBJ_MACH_O)
13656 case bfd_target_mach_o_flavour
:
13657 if (flag_code
== CODE_64BIT
)
13659 use_rela_relocations
= 1;
13661 return "mach-o-x86-64";
13664 return "mach-o-i386";
13672 #endif /* OBJ_MAYBE_ more than one */
13675 md_undefined_symbol (char *name
)
13677 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13678 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13679 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13680 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13684 if (symbol_find (name
))
13685 as_bad (_("GOT already in symbol table"));
13686 GOT_symbol
= symbol_new (name
, undefined_section
,
13687 (valueT
) 0, &zero_address_frag
);
13694 /* Round up a section size to the appropriate boundary. */
13697 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13699 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13700 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13702 /* For a.out, force the section size to be aligned. If we don't do
13703 this, BFD will align it for us, but it will not write out the
13704 final bytes of the section. This may be a bug in BFD, but it is
13705 easier to fix it here since that is how the other a.out targets
13709 align
= bfd_section_alignment (segment
);
13710 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13717 /* On the i386, PC-relative offsets are relative to the start of the
13718 next instruction. That is, the address of the offset, plus its
13719 size, since the offset is always the last part of the insn. */
13722 md_pcrel_from (fixS
*fixP
)
13724 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13730 s_bss (int ignore ATTRIBUTE_UNUSED
)
13734 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13736 obj_elf_section_change_hook ();
13738 temp
= get_absolute_expression ();
13739 subseg_set (bss_section
, (subsegT
) temp
);
13740 demand_empty_rest_of_line ();
13745 /* Remember constant directive. */
13748 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13750 if (last_insn
.kind
!= last_insn_directive
13751 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13753 last_insn
.seg
= now_seg
;
13754 last_insn
.kind
= last_insn_directive
;
13755 last_insn
.name
= "constant directive";
13756 last_insn
.file
= as_where (&last_insn
.line
);
13757 if (lfence_before_ret
!= lfence_before_ret_none
)
13759 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13760 as_warn (_("constant directive skips -mlfence-before-ret "
13761 "and -mlfence-before-indirect-branch"));
13763 as_warn (_("constant directive skips -mlfence-before-ret"));
13765 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13766 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13771 i386_validate_fix (fixS
*fixp
)
13773 if (fixp
->fx_subsy
)
13775 if (fixp
->fx_subsy
== GOT_symbol
)
13777 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13781 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13782 if (fixp
->fx_tcbit2
)
13783 fixp
->fx_r_type
= (fixp
->fx_tcbit
13784 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13785 : BFD_RELOC_X86_64_GOTPCRELX
);
13788 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13793 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13795 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13797 fixp
->fx_subsy
= 0;
13800 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13801 else if (!object_64bit
)
13803 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13804 && fixp
->fx_tcbit2
)
13805 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13811 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13814 bfd_reloc_code_real_type code
;
13816 switch (fixp
->fx_r_type
)
13818 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13819 case BFD_RELOC_SIZE32
:
13820 case BFD_RELOC_SIZE64
:
13821 if (S_IS_DEFINED (fixp
->fx_addsy
)
13822 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13824 /* Resolve size relocation against local symbol to size of
13825 the symbol plus addend. */
13826 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13827 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13828 && !fits_in_unsigned_long (value
))
13829 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13830 _("symbol size computation overflow"));
13831 fixp
->fx_addsy
= NULL
;
13832 fixp
->fx_subsy
= NULL
;
13833 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13837 /* Fall through. */
13839 case BFD_RELOC_X86_64_PLT32
:
13840 case BFD_RELOC_X86_64_GOT32
:
13841 case BFD_RELOC_X86_64_GOTPCREL
:
13842 case BFD_RELOC_X86_64_GOTPCRELX
:
13843 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13844 case BFD_RELOC_386_PLT32
:
13845 case BFD_RELOC_386_GOT32
:
13846 case BFD_RELOC_386_GOT32X
:
13847 case BFD_RELOC_386_GOTOFF
:
13848 case BFD_RELOC_386_GOTPC
:
13849 case BFD_RELOC_386_TLS_GD
:
13850 case BFD_RELOC_386_TLS_LDM
:
13851 case BFD_RELOC_386_TLS_LDO_32
:
13852 case BFD_RELOC_386_TLS_IE_32
:
13853 case BFD_RELOC_386_TLS_IE
:
13854 case BFD_RELOC_386_TLS_GOTIE
:
13855 case BFD_RELOC_386_TLS_LE_32
:
13856 case BFD_RELOC_386_TLS_LE
:
13857 case BFD_RELOC_386_TLS_GOTDESC
:
13858 case BFD_RELOC_386_TLS_DESC_CALL
:
13859 case BFD_RELOC_X86_64_TLSGD
:
13860 case BFD_RELOC_X86_64_TLSLD
:
13861 case BFD_RELOC_X86_64_DTPOFF32
:
13862 case BFD_RELOC_X86_64_DTPOFF64
:
13863 case BFD_RELOC_X86_64_GOTTPOFF
:
13864 case BFD_RELOC_X86_64_TPOFF32
:
13865 case BFD_RELOC_X86_64_TPOFF64
:
13866 case BFD_RELOC_X86_64_GOTOFF64
:
13867 case BFD_RELOC_X86_64_GOTPC32
:
13868 case BFD_RELOC_X86_64_GOT64
:
13869 case BFD_RELOC_X86_64_GOTPCREL64
:
13870 case BFD_RELOC_X86_64_GOTPC64
:
13871 case BFD_RELOC_X86_64_GOTPLT64
:
13872 case BFD_RELOC_X86_64_PLTOFF64
:
13873 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13874 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13875 case BFD_RELOC_RVA
:
13876 case BFD_RELOC_VTABLE_ENTRY
:
13877 case BFD_RELOC_VTABLE_INHERIT
:
13879 case BFD_RELOC_32_SECREL
:
13881 code
= fixp
->fx_r_type
;
13883 case BFD_RELOC_X86_64_32S
:
13884 if (!fixp
->fx_pcrel
)
13886 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13887 code
= fixp
->fx_r_type
;
13890 /* Fall through. */
13892 if (fixp
->fx_pcrel
)
13894 switch (fixp
->fx_size
)
13897 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13898 _("can not do %d byte pc-relative relocation"),
13900 code
= BFD_RELOC_32_PCREL
;
13902 case 1: code
= BFD_RELOC_8_PCREL
; break;
13903 case 2: code
= BFD_RELOC_16_PCREL
; break;
13904 case 4: code
= BFD_RELOC_32_PCREL
; break;
13906 case 8: code
= BFD_RELOC_64_PCREL
; break;
13912 switch (fixp
->fx_size
)
13915 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13916 _("can not do %d byte relocation"),
13918 code
= BFD_RELOC_32
;
13920 case 1: code
= BFD_RELOC_8
; break;
13921 case 2: code
= BFD_RELOC_16
; break;
13922 case 4: code
= BFD_RELOC_32
; break;
13924 case 8: code
= BFD_RELOC_64
; break;
13931 if ((code
== BFD_RELOC_32
13932 || code
== BFD_RELOC_32_PCREL
13933 || code
== BFD_RELOC_X86_64_32S
)
13935 && fixp
->fx_addsy
== GOT_symbol
)
13938 code
= BFD_RELOC_386_GOTPC
;
13940 code
= BFD_RELOC_X86_64_GOTPC32
;
13942 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13944 && fixp
->fx_addsy
== GOT_symbol
)
13946 code
= BFD_RELOC_X86_64_GOTPC64
;
13949 rel
= XNEW (arelent
);
13950 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13951 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13953 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13955 if (!use_rela_relocations
)
13957 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13958 vtable entry to be used in the relocation's section offset. */
13959 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13960 rel
->address
= fixp
->fx_offset
;
13961 #if defined (OBJ_COFF) && defined (TE_PE)
13962 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13963 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13968 /* Use the rela in 64bit mode. */
13971 if (disallow_64bit_reloc
)
13974 case BFD_RELOC_X86_64_DTPOFF64
:
13975 case BFD_RELOC_X86_64_TPOFF64
:
13976 case BFD_RELOC_64_PCREL
:
13977 case BFD_RELOC_X86_64_GOTOFF64
:
13978 case BFD_RELOC_X86_64_GOT64
:
13979 case BFD_RELOC_X86_64_GOTPCREL64
:
13980 case BFD_RELOC_X86_64_GOTPC64
:
13981 case BFD_RELOC_X86_64_GOTPLT64
:
13982 case BFD_RELOC_X86_64_PLTOFF64
:
13983 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13984 _("cannot represent relocation type %s in x32 mode"),
13985 bfd_get_reloc_code_name (code
));
13991 if (!fixp
->fx_pcrel
)
13992 rel
->addend
= fixp
->fx_offset
;
13996 case BFD_RELOC_X86_64_PLT32
:
13997 case BFD_RELOC_X86_64_GOT32
:
13998 case BFD_RELOC_X86_64_GOTPCREL
:
13999 case BFD_RELOC_X86_64_GOTPCRELX
:
14000 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14001 case BFD_RELOC_X86_64_TLSGD
:
14002 case BFD_RELOC_X86_64_TLSLD
:
14003 case BFD_RELOC_X86_64_GOTTPOFF
:
14004 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14005 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14006 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14009 rel
->addend
= (section
->vma
14011 + fixp
->fx_addnumber
14012 + md_pcrel_from (fixp
));
14017 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14018 if (rel
->howto
== NULL
)
14020 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14021 _("cannot represent relocation type %s"),
14022 bfd_get_reloc_code_name (code
));
14023 /* Set howto to a garbage value so that we can keep going. */
14024 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14025 gas_assert (rel
->howto
!= NULL
);
14031 #include "tc-i386-intel.c"
14034 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14036 int saved_naked_reg
;
14037 char saved_register_dot
;
14039 saved_naked_reg
= allow_naked_reg
;
14040 allow_naked_reg
= 1;
14041 saved_register_dot
= register_chars
['.'];
14042 register_chars
['.'] = '.';
14043 allow_pseudo_reg
= 1;
14044 expression_and_evaluate (exp
);
14045 allow_pseudo_reg
= 0;
14046 register_chars
['.'] = saved_register_dot
;
14047 allow_naked_reg
= saved_naked_reg
;
14049 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14051 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14053 exp
->X_op
= O_constant
;
14054 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14055 .dw2_regnum
[flag_code
>> 1];
14058 exp
->X_op
= O_illegal
;
14063 tc_x86_frame_initial_instructions (void)
14065 static unsigned int sp_regno
[2];
14067 if (!sp_regno
[flag_code
>> 1])
14069 char *saved_input
= input_line_pointer
;
14070 char sp
[][4] = {"esp", "rsp"};
14073 input_line_pointer
= sp
[flag_code
>> 1];
14074 tc_x86_parse_to_dw2regnum (&exp
);
14075 gas_assert (exp
.X_op
== O_constant
);
14076 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14077 input_line_pointer
= saved_input
;
14080 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14081 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14085 x86_dwarf2_addr_size (void)
14087 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14088 if (x86_elf_abi
== X86_64_X32_ABI
)
14091 return bfd_arch_bits_per_address (stdoutput
) / 8;
14095 i386_elf_section_type (const char *str
, size_t len
)
14097 if (flag_code
== CODE_64BIT
14098 && len
== sizeof ("unwind") - 1
14099 && strncmp (str
, "unwind", 6) == 0)
14100 return SHT_X86_64_UNWIND
;
14107 i386_solaris_fix_up_eh_frame (segT sec
)
14109 if (flag_code
== CODE_64BIT
)
14110 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14116 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14120 exp
.X_op
= O_secrel
;
14121 exp
.X_add_symbol
= symbol
;
14122 exp
.X_add_number
= 0;
14123 emit_expr (&exp
, size
);
14127 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14128 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14131 x86_64_section_letter (int letter
, const char **ptr_msg
)
14133 if (flag_code
== CODE_64BIT
)
14136 return SHF_X86_64_LARGE
;
14138 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14141 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14146 x86_64_section_word (char *str
, size_t len
)
14148 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14149 return SHF_X86_64_LARGE
;
14155 handle_large_common (int small ATTRIBUTE_UNUSED
)
14157 if (flag_code
!= CODE_64BIT
)
14159 s_comm_internal (0, elf_common_parse
);
14160 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14164 static segT lbss_section
;
14165 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14166 asection
*saved_bss_section
= bss_section
;
14168 if (lbss_section
== NULL
)
14170 flagword applicable
;
14171 segT seg
= now_seg
;
14172 subsegT subseg
= now_subseg
;
14174 /* The .lbss section is for local .largecomm symbols. */
14175 lbss_section
= subseg_new (".lbss", 0);
14176 applicable
= bfd_applicable_section_flags (stdoutput
);
14177 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14178 seg_info (lbss_section
)->bss
= 1;
14180 subseg_set (seg
, subseg
);
14183 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14184 bss_section
= lbss_section
;
14186 s_comm_internal (0, elf_common_parse
);
14188 elf_com_section_ptr
= saved_com_section_ptr
;
14189 bss_section
= saved_bss_section
;
14192 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */