1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2022 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
44 #define DEFAULT_ARCH "i386"
49 #define INLINE __inline__
55 /* Prefixes will be emitted in the order defined below.
56 WAIT_PREFIX must be the first prefix since FWAIT is really is an
57 instruction, and so must come before any prefixes.
58 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
59 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
65 #define HLE_PREFIX REP_PREFIX
66 #define BND_PREFIX REP_PREFIX
68 #define REX_PREFIX 6 /* must come last. */
69 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
84 #define END_OF_INSN '\0'
86 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
88 /* This matches the C -> StaticRounding alias in the opcode table. */
89 #define commutative staticrounding
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const insn_template
*start
;
101 const insn_template
*end
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* 386 opcode byte to code indirect addressing. */
126 /* x86 arch names, types and features */
129 const char *name
; /* arch name */
130 unsigned int len
:8; /* arch string length */
131 bool skip
:1; /* show_arch should skip this. */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags enable
; /* cpu feature enable flags */
134 i386_cpu_flags disable
; /* cpu feature disable flags */
138 static void update_code_flag (int, int);
139 static void set_code_flag (int);
140 static void set_16bit_gcc_code_flag (int);
141 static void set_intel_syntax (int);
142 static void set_intel_mnemonic (int);
143 static void set_allow_index_reg (int);
144 static void set_check (int);
145 static void set_cpu_arch (int);
147 static void pe_directive_secrel (int);
148 static void pe_directive_secidx (int);
150 static void signed_cons (int);
151 static char *output_invalid (int c
);
152 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
154 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
156 static int i386_att_operand (char *);
157 static int i386_intel_operand (char *, int);
158 static int i386_intel_simplify (expressionS
*);
159 static int i386_intel_parse_name (const char *, expressionS
*);
160 static const reg_entry
*parse_register (char *, char **);
161 static char *parse_insn (char *, char *);
162 static char *parse_operands (char *, const char *);
163 static void swap_operands (void);
164 static void swap_2_operands (unsigned int, unsigned int);
165 static enum flag_code
i386_addressing_mode (void);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (char);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const reg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
187 /* GNU_PROPERTY_X86_ISA_1_USED. */
188 static unsigned int x86_isa_1_used
;
189 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
190 static unsigned int x86_feature_2_used
;
191 /* Generate x86 used ISA and feature properties. */
192 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
195 static const char *default_arch
= DEFAULT_ARCH
;
197 /* parse_register() returns this when a register alias cannot be used. */
198 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
199 { Dw2Inval
, Dw2Inval
} };
201 static const reg_entry
*reg_eax
;
202 static const reg_entry
*reg_ds
;
203 static const reg_entry
*reg_es
;
204 static const reg_entry
*reg_ss
;
205 static const reg_entry
*reg_st0
;
206 static const reg_entry
*reg_k0
;
211 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
212 unsigned char bytes
[4];
214 /* Destination or source register specifier. */
215 const reg_entry
*register_specifier
;
218 /* 'md_assemble ()' gathers together information and puts it into a
225 const reg_entry
*regs
;
230 no_error
, /* Must be first. */
231 operand_size_mismatch
,
232 operand_type_mismatch
,
233 register_type_mismatch
,
234 number_of_operands_mismatch
,
235 invalid_instruction_suffix
,
237 unsupported_with_intel_mnemonic
,
241 invalid_vsib_address
,
242 invalid_vector_register_set
,
243 invalid_tmm_register_set
,
244 invalid_dest_and_src_register_set
,
245 unsupported_vector_index_register
,
246 unsupported_broadcast
,
249 mask_not_on_destination
,
252 invalid_register_operand
,
257 /* TM holds the template for the insn were currently assembling. */
260 /* SUFFIX holds the instruction size suffix for byte, word, dword
261 or qword, if given. */
264 /* OPCODE_LENGTH holds the number of base opcode bytes. */
265 unsigned char opcode_length
;
267 /* OPERANDS gives the number of given operands. */
268 unsigned int operands
;
270 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
271 of given register, displacement, memory operands and immediate
273 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
275 /* TYPES [i] is the type (see above #defines) which tells us how to
276 use OP[i] for the corresponding operand. */
277 i386_operand_type types
[MAX_OPERANDS
];
279 /* Displacement expression, immediate expression, or register for each
281 union i386_op op
[MAX_OPERANDS
];
283 /* Flags for operands. */
284 unsigned int flags
[MAX_OPERANDS
];
285 #define Operand_PCrel 1
286 #define Operand_Mem 2
288 /* Relocation type for operand */
289 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
291 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
292 the base index byte below. */
293 const reg_entry
*base_reg
;
294 const reg_entry
*index_reg
;
295 unsigned int log2_scale_factor
;
297 /* SEG gives the seg_entries of this insn. They are zero unless
298 explicit segment overrides are given. */
299 const reg_entry
*seg
[2];
301 /* Copied first memory operand string, for re-checking. */
304 /* PREFIX holds all the given prefix opcodes (usually null).
305 PREFIXES is the number of prefix opcodes. */
306 unsigned int prefixes
;
307 unsigned char prefix
[MAX_PREFIXES
];
309 /* Register is in low 3 bits of opcode. */
312 /* The operand to a branch insn indicates an absolute branch. */
315 /* The operand to a branch insn indicates a far branch. */
318 /* There is a memory operand of (%dx) which should be only used
319 with input/output instructions. */
320 bool input_output_operand
;
322 /* Extended states. */
330 xstate_ymm
= 1 << 2 | xstate_xmm
,
332 xstate_zmm
= 1 << 3 | xstate_ymm
,
335 /* Use MASK state. */
339 /* Has GOTPC or TLS relocation. */
340 bool has_gotpc_tls_reloc
;
342 /* RM and SIB are the modrm byte and the sib byte where the
343 addressing modes of this insn are encoded. */
350 /* Masking attributes.
352 The struct describes masking, applied to OPERAND in the instruction.
353 REG is a pointer to the corresponding mask register. ZEROING tells
354 whether merging or zeroing mask is used. */
355 struct Mask_Operation
357 const reg_entry
*reg
;
358 unsigned int zeroing
;
359 /* The operand where this operation is associated. */
360 unsigned int operand
;
363 /* Rounding control and SAE attributes. */
375 /* In Intel syntax the operand modifier form is supposed to be used, but
376 we continue to accept the immediate forms as well. */
380 /* Broadcasting attributes.
382 The struct describes broadcasting, applied to OPERAND. TYPE is
383 expresses the broadcast factor. */
384 struct Broadcast_Operation
386 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
389 /* Index of broadcasted operand. */
390 unsigned int operand
;
392 /* Number of bytes to broadcast. */
396 /* Compressed disp8*N attribute. */
397 unsigned int memshift
;
399 /* Prefer load or store in encoding. */
402 dir_encoding_default
= 0,
408 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
411 disp_encoding_default
= 0,
417 /* Prefer the REX byte in encoding. */
420 /* Disable instruction size optimization. */
423 /* How to encode vector instructions. */
426 vex_encoding_default
= 0,
434 const char *rep_prefix
;
437 const char *hle_prefix
;
439 /* Have BND prefix. */
440 const char *bnd_prefix
;
442 /* Have NOTRACK prefix. */
443 const char *notrack_prefix
;
446 enum i386_error error
;
449 typedef struct _i386_insn i386_insn
;
451 /* Link RC type with corresponding string, that'll be looked for in
460 static const struct RC_name RC_NamesTable
[] =
462 { rne
, STRING_COMMA_LEN ("rn-sae") },
463 { rd
, STRING_COMMA_LEN ("rd-sae") },
464 { ru
, STRING_COMMA_LEN ("ru-sae") },
465 { rz
, STRING_COMMA_LEN ("rz-sae") },
466 { saeonly
, STRING_COMMA_LEN ("sae") },
469 /* To be indexed by segment register number. */
470 static const unsigned char i386_seg_prefixes
[] = {
479 /* List of chars besides those in app.c:symbol_chars that can start an
480 operand. Used to prevent the scrubber eating vital white-space. */
481 const char extra_symbol_chars
[] = "*%-([{}"
490 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
491 && !defined (TE_GNU) \
492 && !defined (TE_LINUX) \
493 && !defined (TE_Haiku) \
494 && !defined (TE_FreeBSD) \
495 && !defined (TE_DragonFly) \
496 && !defined (TE_NetBSD))
497 /* This array holds the chars that always start a comment. If the
498 pre-processor is disabled, these aren't very useful. The option
499 --divide will remove '/' from this list. */
500 const char *i386_comment_chars
= "#/";
501 #define SVR4_COMMENT_CHARS 1
502 #define PREFIX_SEPARATOR '\\'
505 const char *i386_comment_chars
= "#";
506 #define PREFIX_SEPARATOR '/'
509 /* This array holds the chars that only start a comment at the beginning of
510 a line. If the line seems to have the form '# 123 filename'
511 .line and .file directives will appear in the pre-processed output.
512 Note that input_file.c hand checks for '#' at the beginning of the
513 first line of the input file. This is because the compiler outputs
514 #NO_APP at the beginning of its output.
515 Also note that comments started like this one will always work if
516 '/' isn't otherwise defined. */
517 const char line_comment_chars
[] = "#/";
519 const char line_separator_chars
[] = ";";
521 /* Chars that can be used to separate mant from exp in floating point
523 const char EXP_CHARS
[] = "eE";
525 /* Chars that mean this number is a floating point constant
528 const char FLT_CHARS
[] = "fFdDxXhHbB";
530 /* Tables for lexical analysis. */
531 static char mnemonic_chars
[256];
532 static char register_chars
[256];
533 static char operand_chars
[256];
534 static char identifier_chars
[256];
536 /* Lexical macros. */
537 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
538 #define is_operand_char(x) (operand_chars[(unsigned char) x])
539 #define is_register_char(x) (register_chars[(unsigned char) x])
540 #define is_space_char(x) ((x) == ' ')
541 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
543 /* All non-digit non-letter characters that may occur in an operand. */
544 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
546 /* md_assemble() always leaves the strings it's passed unaltered. To
547 effect this we maintain a stack of saved characters that we've smashed
548 with '\0's (indicating end of strings for various sub-fields of the
549 assembler instruction). */
550 static char save_stack
[32];
551 static char *save_stack_p
;
552 #define END_STRING_AND_SAVE(s) \
553 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
554 #define RESTORE_END_STRING(s) \
555 do { *(s) = *--save_stack_p; } while (0)
557 /* The instruction we're assembling. */
560 /* Possible templates for current insn. */
561 static const templates
*current_templates
;
563 /* Per instruction expressionS buffers: max displacements & immediates. */
564 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
565 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
567 /* Current operand we are working on. */
568 static int this_operand
= -1;
570 /* We support four different modes. FLAG_CODE variable is used to distinguish
578 static enum flag_code flag_code
;
579 static unsigned int object_64bit
;
580 static unsigned int disallow_64bit_reloc
;
581 static int use_rela_relocations
= 0;
582 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
583 static const char *tls_get_addr
;
585 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
586 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
587 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
589 /* The ELF ABI to use. */
597 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
600 #if defined (TE_PE) || defined (TE_PEP)
601 /* Use big object file format. */
602 static int use_big_obj
= 0;
605 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
606 /* 1 if generating code for a shared library. */
607 static int shared
= 0;
609 unsigned int x86_sframe_cfa_sp_reg
;
610 /* The other CFA base register for SFrame unwind info. */
611 unsigned int x86_sframe_cfa_fp_reg
;
612 unsigned int x86_sframe_cfa_ra_reg
;
616 /* 1 for intel syntax,
618 static int intel_syntax
= 0;
620 static enum x86_64_isa
622 amd64
= 1, /* AMD64 ISA. */
623 intel64
/* Intel64 ISA. */
626 /* 1 for intel mnemonic,
627 0 if att mnemonic. */
628 static int intel_mnemonic
= !SYSV386_COMPAT
;
630 /* 1 if pseudo registers are permitted. */
631 static int allow_pseudo_reg
= 0;
633 /* 1 if register prefix % not required. */
634 static int allow_naked_reg
= 0;
636 /* 1 if the assembler should add BND prefix for all control-transferring
637 instructions supporting it, even if this prefix wasn't specified
639 static int add_bnd_prefix
= 0;
641 /* 1 if pseudo index register, eiz/riz, is allowed . */
642 static int allow_index_reg
= 0;
644 /* 1 if the assembler should ignore LOCK prefix, even if it was
645 specified explicitly. */
646 static int omit_lock_prefix
= 0;
648 /* 1 if the assembler should encode lfence, mfence, and sfence as
649 "lock addl $0, (%{re}sp)". */
650 static int avoid_fence
= 0;
652 /* 1 if lfence should be inserted after every load. */
653 static int lfence_after_load
= 0;
655 /* Non-zero if lfence should be inserted before indirect branch. */
656 static enum lfence_before_indirect_branch_kind
658 lfence_branch_none
= 0,
659 lfence_branch_register
,
660 lfence_branch_memory
,
663 lfence_before_indirect_branch
;
665 /* Non-zero if lfence should be inserted before ret. */
666 static enum lfence_before_ret_kind
668 lfence_before_ret_none
= 0,
669 lfence_before_ret_not
,
670 lfence_before_ret_or
,
671 lfence_before_ret_shl
675 /* Types of previous instruction is .byte or prefix. */
690 /* 1 if the assembler should generate relax relocations. */
692 static int generate_relax_relocations
693 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
695 static enum check_kind
701 sse_check
, operand_check
= check_warning
;
703 /* Non-zero if branches should be aligned within power of 2 boundary. */
704 static int align_branch_power
= 0;
706 /* Types of branches to align. */
707 enum align_branch_kind
709 align_branch_none
= 0,
710 align_branch_jcc
= 1,
711 align_branch_fused
= 2,
712 align_branch_jmp
= 3,
713 align_branch_call
= 4,
714 align_branch_indirect
= 5,
718 /* Type bits of branches to align. */
719 enum align_branch_bit
721 align_branch_jcc_bit
= 1 << align_branch_jcc
,
722 align_branch_fused_bit
= 1 << align_branch_fused
,
723 align_branch_jmp_bit
= 1 << align_branch_jmp
,
724 align_branch_call_bit
= 1 << align_branch_call
,
725 align_branch_indirect_bit
= 1 << align_branch_indirect
,
726 align_branch_ret_bit
= 1 << align_branch_ret
729 static unsigned int align_branch
= (align_branch_jcc_bit
730 | align_branch_fused_bit
731 | align_branch_jmp_bit
);
733 /* Types of condition jump used by macro-fusion. */
736 mf_jcc_jo
= 0, /* base opcode 0x70 */
737 mf_jcc_jc
, /* base opcode 0x72 */
738 mf_jcc_je
, /* base opcode 0x74 */
739 mf_jcc_jna
, /* base opcode 0x76 */
740 mf_jcc_js
, /* base opcode 0x78 */
741 mf_jcc_jp
, /* base opcode 0x7a */
742 mf_jcc_jl
, /* base opcode 0x7c */
743 mf_jcc_jle
, /* base opcode 0x7e */
746 /* Types of compare flag-modifying insntructions used by macro-fusion. */
749 mf_cmp_test_and
, /* test/cmp */
750 mf_cmp_alu_cmp
, /* add/sub/cmp */
751 mf_cmp_incdec
/* inc/dec */
754 /* The maximum padding size for fused jcc. CMP like instruction can
755 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
757 #define MAX_FUSED_JCC_PADDING_SIZE 20
759 /* The maximum number of prefixes added for an instruction. */
760 static unsigned int align_branch_prefix_size
= 5;
763 1. Clear the REX_W bit with register operand if possible.
764 2. Above plus use 128bit vector instruction to clear the full vector
767 static int optimize
= 0;
770 1. Clear the REX_W bit with register operand if possible.
771 2. Above plus use 128bit vector instruction to clear the full vector
773 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
776 static int optimize_for_space
= 0;
778 /* Register prefix used for error message. */
779 static const char *register_prefix
= "%";
781 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
782 leave, push, and pop instructions so that gcc has the same stack
783 frame as in 32 bit mode. */
784 static char stackop_size
= '\0';
786 /* Non-zero to optimize code alignment. */
787 int optimize_align_code
= 1;
789 /* Non-zero to quieten some warnings. */
790 static int quiet_warnings
= 0;
792 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
793 static bool pre_386_16bit_warned
;
796 static const char *cpu_arch_name
= NULL
;
797 static char *cpu_sub_arch_name
= NULL
;
799 /* CPU feature flags. */
800 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
802 /* If we have selected a cpu we are generating instructions for. */
803 static int cpu_arch_tune_set
= 0;
805 /* Cpu we are generating instructions for. */
806 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
808 /* CPU feature flags of cpu we are generating instructions for. */
809 static i386_cpu_flags cpu_arch_tune_flags
;
811 /* CPU instruction set architecture used. */
812 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
814 /* CPU feature flags of instruction set architecture used. */
815 i386_cpu_flags cpu_arch_isa_flags
;
817 /* If set, conditional jumps are not automatically promoted to handle
818 larger than a byte offset. */
819 static bool no_cond_jump_promotion
= false;
821 /* Encode SSE instructions with VEX prefix. */
822 static unsigned int sse2avx
;
824 /* Encode aligned vector move as unaligned vector move. */
825 static unsigned int use_unaligned_vector_move
;
827 /* Encode scalar AVX instructions with specific vector length. */
834 /* Encode VEX WIG instructions with specific vex.w. */
841 /* Encode scalar EVEX LIG instructions with specific vector length. */
849 /* Encode EVEX WIG instructions with specific evex.w. */
856 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
857 static enum rc_type evexrcig
= rne
;
859 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
860 static symbolS
*GOT_symbol
;
862 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
863 unsigned int x86_dwarf2_return_column
;
865 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
866 int x86_cie_data_alignment
;
868 /* Interface to relax_segment.
869 There are 3 major relax states for 386 jump insns because the
870 different types of jumps add different sizes to frags when we're
871 figuring out what sort of jump to choose to reach a given label.
873 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
874 branches which are handled by md_estimate_size_before_relax() and
875 i386_generic_table_relax_frag(). */
878 #define UNCOND_JUMP 0
880 #define COND_JUMP86 2
881 #define BRANCH_PADDING 3
882 #define BRANCH_PREFIX 4
883 #define FUSED_JCC_PADDING 5
888 #define SMALL16 (SMALL | CODE16)
890 #define BIG16 (BIG | CODE16)
894 #define INLINE __inline__
900 #define ENCODE_RELAX_STATE(type, size) \
901 ((relax_substateT) (((type) << 2) | (size)))
902 #define TYPE_FROM_RELAX_STATE(s) \
904 #define DISP_SIZE_FROM_RELAX_STATE(s) \
905 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
907 /* This table is used by relax_frag to promote short jumps to long
908 ones where necessary. SMALL (short) jumps may be promoted to BIG
909 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
910 don't allow a short jump in a 32 bit code segment to be promoted to
911 a 16 bit offset jump because it's slower (requires data size
912 prefix), and doesn't work, unless the destination is in the bottom
913 64k of the code segment (The top 16 bits of eip are zeroed). */
915 const relax_typeS md_relax_table
[] =
918 1) most positive reach of this state,
919 2) most negative reach of this state,
920 3) how many bytes this mode will have in the variable part of the frag
921 4) which index into the table to try if we can't fit into this one. */
923 /* UNCOND_JUMP states. */
924 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
925 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
926 /* dword jmp adds 4 bytes to frag:
927 0 extra opcode bytes, 4 displacement bytes. */
929 /* word jmp adds 2 byte2 to frag:
930 0 extra opcode bytes, 2 displacement bytes. */
933 /* COND_JUMP states. */
934 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
935 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
936 /* dword conditionals adds 5 bytes to frag:
937 1 extra opcode byte, 4 displacement bytes. */
939 /* word conditionals add 3 bytes to frag:
940 1 extra opcode byte, 2 displacement bytes. */
943 /* COND_JUMP86 states. */
944 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
945 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
946 /* dword conditionals adds 5 bytes to frag:
947 1 extra opcode byte, 4 displacement bytes. */
949 /* word conditionals add 4 bytes to frag:
950 1 displacement byte and a 3 byte long branch insn. */
954 #define ARCH(n, t, f, s) \
955 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, CPU_ ## f ## _FLAGS, \
957 #define SUBARCH(n, e, d, s) \
958 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, CPU_ ## e ## _FLAGS, \
959 CPU_ ## d ## _FLAGS }
961 static const arch_entry cpu_arch
[] =
963 /* Do not replace the first two entries - i386_target_format() and
964 set_cpu_arch() rely on them being there in this order. */
965 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
966 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
967 ARCH (i8086
, UNKNOWN
, NONE
, false),
968 ARCH (i186
, UNKNOWN
, I186
, false),
969 ARCH (i286
, UNKNOWN
, I286
, false),
970 ARCH (i386
, I386
, I386
, false),
971 ARCH (i486
, I486
, I486
, false),
972 ARCH (i586
, PENTIUM
, I586
, false),
973 ARCH (i686
, PENTIUMPRO
, I686
, false),
974 ARCH (pentium
, PENTIUM
, I586
, false),
975 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
976 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
977 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
978 ARCH (pentium4
, PENTIUM4
, P4
, false),
979 ARCH (prescott
, NOCONA
, CORE
, false),
980 ARCH (nocona
, NOCONA
, NOCONA
, false),
981 ARCH (yonah
, CORE
, CORE
, true),
982 ARCH (core
, CORE
, CORE
, false),
983 ARCH (merom
, CORE2
, CORE2
, true),
984 ARCH (core2
, CORE2
, CORE2
, false),
985 ARCH (corei7
, COREI7
, COREI7
, false),
986 ARCH (iamcu
, IAMCU
, IAMCU
, false),
987 ARCH (k6
, K6
, K6
, false),
988 ARCH (k6_2
, K6
, K6_2
, false),
989 ARCH (athlon
, ATHLON
, ATHLON
, false),
990 ARCH (sledgehammer
, K8
, K8
, true),
991 ARCH (opteron
, K8
, K8
, false),
992 ARCH (k8
, K8
, K8
, false),
993 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
994 ARCH (bdver1
, BD
, BDVER1
, false),
995 ARCH (bdver2
, BD
, BDVER2
, false),
996 ARCH (bdver3
, BD
, BDVER3
, false),
997 ARCH (bdver4
, BD
, BDVER4
, false),
998 ARCH (znver1
, ZNVER
, ZNVER1
, false),
999 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1000 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1001 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1002 ARCH (btver1
, BT
, BTVER1
, false),
1003 ARCH (btver2
, BT
, BTVER2
, false),
1005 SUBARCH (8087, 8087, ANY_X87
, false),
1006 SUBARCH (87, NONE
, ANY_X87
, false), /* Disable only! */
1007 SUBARCH (287, 287, ANY_287
, false),
1008 SUBARCH (387, 387, ANY_387
, false),
1009 SUBARCH (687, 687, ANY_687
, false),
1010 SUBARCH (cmov
, CMOV
, ANY_CMOV
, false),
1011 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1012 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1013 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1014 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1015 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1016 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1017 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1018 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1019 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1020 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1021 SUBARCH (avx
, AVX
, ANY_AVX
, false),
1022 SUBARCH (avx2
, AVX2
, ANY_AVX2
, false),
1023 SUBARCH (avx512f
, AVX512F
, ANY_AVX512F
, false),
1024 SUBARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, false),
1025 SUBARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, false),
1026 SUBARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, false),
1027 SUBARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, false),
1028 SUBARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, false),
1029 SUBARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, false),
1030 SUBARCH (vmx
, VMX
, VMX
, false),
1031 SUBARCH (vmfunc
, VMFUNC
, VMFUNC
, false),
1032 SUBARCH (smx
, SMX
, SMX
, false),
1033 SUBARCH (xsave
, XSAVE
, XSAVE
, false),
1034 SUBARCH (xsaveopt
, XSAVEOPT
, XSAVEOPT
, false),
1035 SUBARCH (xsavec
, XSAVEC
, XSAVEC
, false),
1036 SUBARCH (xsaves
, XSAVES
, XSAVES
, false),
1037 SUBARCH (aes
, AES
, AES
, false),
1038 SUBARCH (pclmul
, PCLMUL
, PCLMUL
, false),
1039 SUBARCH (clmul
, PCLMUL
, PCLMUL
, true),
1040 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1041 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1042 SUBARCH (f16c
, F16C
, F16C
, false),
1043 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1044 SUBARCH (fma
, FMA
, FMA
, false),
1045 SUBARCH (fma4
, FMA4
, FMA4
, false),
1046 SUBARCH (xop
, XOP
, XOP
, false),
1047 SUBARCH (lwp
, LWP
, LWP
, false),
1048 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1049 SUBARCH (cx16
, CX16
, CX16
, false),
1050 SUBARCH (ept
, EPT
, EPT
, false),
1051 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1052 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1053 SUBARCH (hle
, HLE
, HLE
, false),
1054 SUBARCH (rtm
, RTM
, RTM
, false),
1055 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1056 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1057 SUBARCH (nop
, NOP
, NOP
, false),
1058 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1059 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1060 SUBARCH (3dnow
, 3DNOW
, 3DNOW
, false),
1061 SUBARCH (3dnowa
, 3DNOWA
, 3DNOWA
, false),
1062 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1063 SUBARCH (pacifica
, SVME
, SVME
, true),
1064 SUBARCH (svme
, SVME
, SVME
, false),
1065 SUBARCH (abm
, ABM
, ABM
, false),
1066 SUBARCH (bmi
, BMI
, BMI
, false),
1067 SUBARCH (tbm
, TBM
, TBM
, false),
1068 SUBARCH (adx
, ADX
, ADX
, false),
1069 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1070 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1071 SUBARCH (smap
, SMAP
, SMAP
, false),
1072 SUBARCH (mpx
, MPX
, MPX
, false),
1073 SUBARCH (sha
, SHA
, SHA
, false),
1074 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1075 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1076 SUBARCH (se1
, SE1
, SE1
, false),
1077 SUBARCH (clwb
, CLWB
, CLWB
, false),
1078 SUBARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, false),
1079 SUBARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, false),
1080 SUBARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, false),
1081 SUBARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, false),
1082 SUBARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, false),
1083 SUBARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, false),
1084 SUBARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, false),
1085 SUBARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, false),
1086 SUBARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, false),
1087 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1088 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1089 SUBARCH (ospke
, OSPKE
, OSPKE
, false),
1090 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1091 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1092 SUBARCH (ibt
, IBT
, ANY_IBT
, false),
1093 SUBARCH (shstk
, SHSTK
, ANY_SHSTK
, false),
1094 SUBARCH (gfni
, GFNI
, GFNI
, false),
1095 SUBARCH (vaes
, VAES
, VAES
, false),
1096 SUBARCH (vpclmulqdq
, VPCLMULQDQ
, VPCLMULQDQ
, false),
1097 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1098 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1099 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1100 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1101 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1102 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1103 SUBARCH (amx_fp16
, AMX_FP16
, AMX_FP16
, false),
1104 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1105 SUBARCH (movdiri
, MOVDIRI
, ANY_MOVDIRI
, false),
1106 SUBARCH (movdir64b
, MOVDIR64B
, ANY_MOVDIR64B
, false),
1107 SUBARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, false),
1108 SUBARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1109 ANY_AVX512_VP2INTERSECT
, false),
1110 SUBARCH (tdx
, TDX
, ANY_TDX
, false),
1111 SUBARCH (enqcmd
, ENQCMD
, ANY_ENQCMD
, false),
1112 SUBARCH (serialize
, SERIALIZE
, ANY_SERIALIZE
, false),
1113 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1114 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1115 SUBARCH (sev_es
, SEV_ES
, SEV_ES
, false),
1116 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1117 SUBARCH (kl
, KL
, ANY_KL
, false),
1118 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1119 SUBARCH (uintr
, UINTR
, ANY_UINTR
, false),
1120 SUBARCH (hreset
, HRESET
, ANY_HRESET
, false),
1121 SUBARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, false),
1122 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1123 SUBARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, false),
1124 SUBARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, false),
1125 SUBARCH (cmpccxadd
, CMPCCXADD
, ANY_CMPCCXADD
, false),
1126 SUBARCH (wrmsrns
, WRMSRNS
, ANY_WRMSRNS
, false),
1127 SUBARCH (msrlist
, MSRLIST
, ANY_MSRLIST
, false),
1128 SUBARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, false),
1129 SUBARCH (rao_int
, RAO_INT
, ANY_RAO_INT
, false),
1130 SUBARCH (rmpquery
, RMPQUERY
, RMPQUERY
, false),
1137 /* Like s_lcomm_internal in gas/read.c but the alignment string
1138 is allowed to be optional. */
1141 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1148 && *input_line_pointer
== ',')
1150 align
= parse_align (needs_align
- 1);
1152 if (align
== (addressT
) -1)
1167 bss_alloc (symbolP
, size
, align
);
1172 pe_lcomm (int needs_align
)
1174 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1178 const pseudo_typeS md_pseudo_table
[] =
1180 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1181 {"align", s_align_bytes
, 0},
1183 {"align", s_align_ptwo
, 0},
1185 {"arch", set_cpu_arch
, 0},
1189 {"lcomm", pe_lcomm
, 1},
1191 {"ffloat", float_cons
, 'f'},
1192 {"dfloat", float_cons
, 'd'},
1193 {"tfloat", float_cons
, 'x'},
1194 {"hfloat", float_cons
, 'h'},
1195 {"bfloat16", float_cons
, 'b'},
1197 {"slong", signed_cons
, 4},
1198 {"noopt", s_ignore
, 0},
1199 {"optim", s_ignore
, 0},
1200 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1201 {"code16", set_code_flag
, CODE_16BIT
},
1202 {"code32", set_code_flag
, CODE_32BIT
},
1204 {"code64", set_code_flag
, CODE_64BIT
},
1206 {"intel_syntax", set_intel_syntax
, 1},
1207 {"att_syntax", set_intel_syntax
, 0},
1208 {"intel_mnemonic", set_intel_mnemonic
, 1},
1209 {"att_mnemonic", set_intel_mnemonic
, 0},
1210 {"allow_index_reg", set_allow_index_reg
, 1},
1211 {"disallow_index_reg", set_allow_index_reg
, 0},
1212 {"sse_check", set_check
, 0},
1213 {"operand_check", set_check
, 1},
1214 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1215 {"largecomm", handle_large_common
, 0},
1217 {"file", dwarf2_directive_file
, 0},
1218 {"loc", dwarf2_directive_loc
, 0},
1219 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1222 {"secrel32", pe_directive_secrel
, 0},
1223 {"secidx", pe_directive_secidx
, 0},
1228 /* For interface with expression (). */
1229 extern char *input_line_pointer
;
1231 /* Hash table for instruction mnemonic lookup. */
1232 static htab_t op_hash
;
1234 /* Hash table for register lookup. */
1235 static htab_t reg_hash
;
1237 /* Various efficient no-op patterns for aligning code labels.
1238 Note: Don't try to assemble the instructions in the comments.
1239 0L and 0w are not legal. */
1240 static const unsigned char f32_1
[] =
1242 static const unsigned char f32_2
[] =
1243 {0x66,0x90}; /* xchg %ax,%ax */
1244 static const unsigned char f32_3
[] =
1245 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1246 static const unsigned char f32_4
[] =
1247 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1248 static const unsigned char f32_6
[] =
1249 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1250 static const unsigned char f32_7
[] =
1251 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1252 static const unsigned char f16_3
[] =
1253 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1254 static const unsigned char f16_4
[] =
1255 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1256 static const unsigned char jump_disp8
[] =
1257 {0xeb}; /* jmp disp8 */
1258 static const unsigned char jump32_disp32
[] =
1259 {0xe9}; /* jmp disp32 */
1260 static const unsigned char jump16_disp32
[] =
1261 {0x66,0xe9}; /* jmp disp32 */
1262 /* 32-bit NOPs patterns. */
1263 static const unsigned char *const f32_patt
[] = {
1264 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1266 /* 16-bit NOPs patterns. */
1267 static const unsigned char *const f16_patt
[] = {
1268 f32_1
, f32_2
, f16_3
, f16_4
1270 /* nopl (%[re]ax) */
1271 static const unsigned char alt_3
[] =
1273 /* nopl 0(%[re]ax) */
1274 static const unsigned char alt_4
[] =
1275 {0x0f,0x1f,0x40,0x00};
1276 /* nopl 0(%[re]ax,%[re]ax,1) */
1277 static const unsigned char alt_5
[] =
1278 {0x0f,0x1f,0x44,0x00,0x00};
1279 /* nopw 0(%[re]ax,%[re]ax,1) */
1280 static const unsigned char alt_6
[] =
1281 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1282 /* nopl 0L(%[re]ax) */
1283 static const unsigned char alt_7
[] =
1284 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1285 /* nopl 0L(%[re]ax,%[re]ax,1) */
1286 static const unsigned char alt_8
[] =
1287 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1288 /* nopw 0L(%[re]ax,%[re]ax,1) */
1289 static const unsigned char alt_9
[] =
1290 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1291 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1292 static const unsigned char alt_10
[] =
1293 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1294 /* data16 nopw %cs:0L(%eax,%eax,1) */
1295 static const unsigned char alt_11
[] =
1296 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1297 /* 32-bit and 64-bit NOPs patterns. */
1298 static const unsigned char *const alt_patt
[] = {
1299 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1300 alt_9
, alt_10
, alt_11
1303 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1304 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1307 i386_output_nops (char *where
, const unsigned char *const *patt
,
1308 int count
, int max_single_nop_size
)
1311 /* Place the longer NOP first. */
1314 const unsigned char *nops
;
1316 if (max_single_nop_size
< 1)
1318 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1319 max_single_nop_size
);
1323 nops
= patt
[max_single_nop_size
- 1];
1325 /* Use the smaller one if the requsted one isn't available. */
1328 max_single_nop_size
--;
1329 nops
= patt
[max_single_nop_size
- 1];
1332 last
= count
% max_single_nop_size
;
1335 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1336 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1340 nops
= patt
[last
- 1];
1343 /* Use the smaller one plus one-byte NOP if the needed one
1346 nops
= patt
[last
- 1];
1347 memcpy (where
+ offset
, nops
, last
);
1348 where
[offset
+ last
] = *patt
[0];
1351 memcpy (where
+ offset
, nops
, last
);
1356 fits_in_imm7 (offsetT num
)
1358 return (num
& 0x7f) == num
;
1362 fits_in_imm31 (offsetT num
)
1364 return (num
& 0x7fffffff) == num
;
1367 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1368 single NOP instruction LIMIT. */
1371 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1373 const unsigned char *const *patt
= NULL
;
1374 int max_single_nop_size
;
1375 /* Maximum number of NOPs before switching to jump over NOPs. */
1376 int max_number_of_nops
;
1378 switch (fragP
->fr_type
)
1383 case rs_machine_dependent
:
1384 /* Allow NOP padding for jumps and calls. */
1385 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1386 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1393 /* We need to decide which NOP sequence to use for 32bit and
1394 64bit. When -mtune= is used:
1396 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1397 PROCESSOR_GENERIC32, f32_patt will be used.
1398 2. For the rest, alt_patt will be used.
1400 When -mtune= isn't used, alt_patt will be used if
1401 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1404 When -march= or .arch is used, we can't use anything beyond
1405 cpu_arch_isa_flags. */
1407 if (flag_code
== CODE_16BIT
)
1410 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1411 /* Limit number of NOPs to 2 in 16-bit mode. */
1412 max_number_of_nops
= 2;
1416 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1418 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1419 switch (cpu_arch_tune
)
1421 case PROCESSOR_UNKNOWN
:
1422 /* We use cpu_arch_isa_flags to check if we SHOULD
1423 optimize with nops. */
1424 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1429 case PROCESSOR_PENTIUM4
:
1430 case PROCESSOR_NOCONA
:
1431 case PROCESSOR_CORE
:
1432 case PROCESSOR_CORE2
:
1433 case PROCESSOR_COREI7
:
1434 case PROCESSOR_GENERIC64
:
1436 case PROCESSOR_ATHLON
:
1438 case PROCESSOR_AMDFAM10
:
1440 case PROCESSOR_ZNVER
:
1444 case PROCESSOR_I386
:
1445 case PROCESSOR_I486
:
1446 case PROCESSOR_PENTIUM
:
1447 case PROCESSOR_PENTIUMPRO
:
1448 case PROCESSOR_IAMCU
:
1449 case PROCESSOR_GENERIC32
:
1452 case PROCESSOR_NONE
:
1458 switch (fragP
->tc_frag_data
.tune
)
1460 case PROCESSOR_UNKNOWN
:
1461 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1462 PROCESSOR_UNKNOWN. */
1466 case PROCESSOR_I386
:
1467 case PROCESSOR_I486
:
1468 case PROCESSOR_PENTIUM
:
1469 case PROCESSOR_IAMCU
:
1471 case PROCESSOR_ATHLON
:
1473 case PROCESSOR_AMDFAM10
:
1475 case PROCESSOR_ZNVER
:
1477 case PROCESSOR_GENERIC32
:
1478 /* We use cpu_arch_isa_flags to check if we CAN optimize
1480 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1485 case PROCESSOR_PENTIUMPRO
:
1486 case PROCESSOR_PENTIUM4
:
1487 case PROCESSOR_NOCONA
:
1488 case PROCESSOR_CORE
:
1489 case PROCESSOR_CORE2
:
1490 case PROCESSOR_COREI7
:
1491 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1496 case PROCESSOR_GENERIC64
:
1499 case PROCESSOR_NONE
:
1504 if (patt
== f32_patt
)
1506 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1507 /* Limit number of NOPs to 2 for older processors. */
1508 max_number_of_nops
= 2;
1512 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1513 /* Limit number of NOPs to 7 for newer processors. */
1514 max_number_of_nops
= 7;
1519 limit
= max_single_nop_size
;
1521 if (fragP
->fr_type
== rs_fill_nop
)
1523 /* Output NOPs for .nop directive. */
1524 if (limit
> max_single_nop_size
)
1526 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1527 _("invalid single nop size: %d "
1528 "(expect within [0, %d])"),
1529 limit
, max_single_nop_size
);
1533 else if (fragP
->fr_type
!= rs_machine_dependent
)
1534 fragP
->fr_var
= count
;
1536 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1538 /* Generate jump over NOPs. */
1539 offsetT disp
= count
- 2;
1540 if (fits_in_imm7 (disp
))
1542 /* Use "jmp disp8" if possible. */
1544 where
[0] = jump_disp8
[0];
1550 unsigned int size_of_jump
;
1552 if (flag_code
== CODE_16BIT
)
1554 where
[0] = jump16_disp32
[0];
1555 where
[1] = jump16_disp32
[1];
1560 where
[0] = jump32_disp32
[0];
1564 count
-= size_of_jump
+ 4;
1565 if (!fits_in_imm31 (count
))
1567 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1568 _("jump over nop padding out of range"));
1572 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1573 where
+= size_of_jump
+ 4;
1577 /* Generate multiple NOPs. */
1578 i386_output_nops (where
, patt
, count
, limit
);
1582 operand_type_all_zero (const union i386_operand_type
*x
)
1584 switch (ARRAY_SIZE(x
->array
))
1595 return !x
->array
[0];
1602 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1604 switch (ARRAY_SIZE(x
->array
))
1620 x
->bitfield
.class = ClassNone
;
1621 x
->bitfield
.instance
= InstanceNone
;
1625 operand_type_equal (const union i386_operand_type
*x
,
1626 const union i386_operand_type
*y
)
1628 switch (ARRAY_SIZE(x
->array
))
1631 if (x
->array
[2] != y
->array
[2])
1635 if (x
->array
[1] != y
->array
[1])
1639 return x
->array
[0] == y
->array
[0];
1647 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1649 switch (ARRAY_SIZE(x
->array
))
1668 return !x
->array
[0];
1675 cpu_flags_equal (const union i386_cpu_flags
*x
,
1676 const union i386_cpu_flags
*y
)
1678 switch (ARRAY_SIZE(x
->array
))
1681 if (x
->array
[4] != y
->array
[4])
1685 if (x
->array
[3] != y
->array
[3])
1689 if (x
->array
[2] != y
->array
[2])
1693 if (x
->array
[1] != y
->array
[1])
1697 return x
->array
[0] == y
->array
[0];
1705 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1707 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1708 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1711 static INLINE i386_cpu_flags
1712 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1714 switch (ARRAY_SIZE (x
.array
))
1717 x
.array
[4] &= y
.array
[4];
1720 x
.array
[3] &= y
.array
[3];
1723 x
.array
[2] &= y
.array
[2];
1726 x
.array
[1] &= y
.array
[1];
1729 x
.array
[0] &= y
.array
[0];
1737 static INLINE i386_cpu_flags
1738 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1740 switch (ARRAY_SIZE (x
.array
))
1743 x
.array
[4] |= y
.array
[4];
1746 x
.array
[3] |= y
.array
[3];
1749 x
.array
[2] |= y
.array
[2];
1752 x
.array
[1] |= y
.array
[1];
1755 x
.array
[0] |= y
.array
[0];
1763 static INLINE i386_cpu_flags
1764 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1766 switch (ARRAY_SIZE (x
.array
))
1769 x
.array
[4] &= ~y
.array
[4];
1772 x
.array
[3] &= ~y
.array
[3];
1775 x
.array
[2] &= ~y
.array
[2];
1778 x
.array
[1] &= ~y
.array
[1];
1781 x
.array
[0] &= ~y
.array
[0];
1789 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1791 #define CPU_FLAGS_ARCH_MATCH 0x1
1792 #define CPU_FLAGS_64BIT_MATCH 0x2
1794 #define CPU_FLAGS_PERFECT_MATCH \
1795 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1797 /* Return CPU flags match bits. */
1800 cpu_flags_match (const insn_template
*t
)
1802 i386_cpu_flags x
= t
->cpu_flags
;
1803 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1805 x
.bitfield
.cpu64
= 0;
1806 x
.bitfield
.cpuno64
= 0;
1808 if (cpu_flags_all_zero (&x
))
1810 /* This instruction is available on all archs. */
1811 match
|= CPU_FLAGS_ARCH_MATCH
;
1815 /* This instruction is available only on some archs. */
1816 i386_cpu_flags cpu
= cpu_arch_flags
;
1818 /* AVX512VL is no standalone feature - match it and then strip it. */
1819 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1821 x
.bitfield
.cpuavx512vl
= 0;
1823 /* AVX and AVX2 present at the same time express an operand size
1824 dependency - strip AVX2 for the purposes here. The operand size
1825 dependent check occurs in check_vecOperands(). */
1826 if (x
.bitfield
.cpuavx
&& x
.bitfield
.cpuavx2
)
1827 x
.bitfield
.cpuavx2
= 0;
1829 cpu
= cpu_flags_and (x
, cpu
);
1830 if (!cpu_flags_all_zero (&cpu
))
1832 if (x
.bitfield
.cpuavx
)
1834 /* We need to check a few extra flags with AVX. */
1835 if (cpu
.bitfield
.cpuavx
1836 && (!t
->opcode_modifier
.sse2avx
1837 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1838 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1839 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1840 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1841 match
|= CPU_FLAGS_ARCH_MATCH
;
1843 else if (x
.bitfield
.cpuavx512f
)
1845 /* We need to check a few extra flags with AVX512F. */
1846 if (cpu
.bitfield
.cpuavx512f
1847 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1848 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1849 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1850 match
|= CPU_FLAGS_ARCH_MATCH
;
1853 match
|= CPU_FLAGS_ARCH_MATCH
;
1859 static INLINE i386_operand_type
1860 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1862 if (x
.bitfield
.class != y
.bitfield
.class)
1863 x
.bitfield
.class = ClassNone
;
1864 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1865 x
.bitfield
.instance
= InstanceNone
;
1867 switch (ARRAY_SIZE (x
.array
))
1870 x
.array
[2] &= y
.array
[2];
1873 x
.array
[1] &= y
.array
[1];
1876 x
.array
[0] &= y
.array
[0];
1884 static INLINE i386_operand_type
1885 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1887 gas_assert (y
.bitfield
.class == ClassNone
);
1888 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1890 switch (ARRAY_SIZE (x
.array
))
1893 x
.array
[2] &= ~y
.array
[2];
1896 x
.array
[1] &= ~y
.array
[1];
1899 x
.array
[0] &= ~y
.array
[0];
1907 static INLINE i386_operand_type
1908 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1910 gas_assert (x
.bitfield
.class == ClassNone
||
1911 y
.bitfield
.class == ClassNone
||
1912 x
.bitfield
.class == y
.bitfield
.class);
1913 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1914 y
.bitfield
.instance
== InstanceNone
||
1915 x
.bitfield
.instance
== y
.bitfield
.instance
);
1917 switch (ARRAY_SIZE (x
.array
))
1920 x
.array
[2] |= y
.array
[2];
1923 x
.array
[1] |= y
.array
[1];
1926 x
.array
[0] |= y
.array
[0];
1934 static INLINE i386_operand_type
1935 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1937 gas_assert (y
.bitfield
.class == ClassNone
);
1938 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1940 switch (ARRAY_SIZE (x
.array
))
1943 x
.array
[2] ^= y
.array
[2];
1946 x
.array
[1] ^= y
.array
[1];
1949 x
.array
[0] ^= y
.array
[0];
1957 static const i386_operand_type anydisp
= {
1958 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
1970 operand_type_check (i386_operand_type t
, enum operand_type c
)
1975 return t
.bitfield
.class == Reg
;
1978 return (t
.bitfield
.imm8
1982 || t
.bitfield
.imm32s
1983 || t
.bitfield
.imm64
);
1986 return (t
.bitfield
.disp8
1987 || t
.bitfield
.disp16
1988 || t
.bitfield
.disp32
1989 || t
.bitfield
.disp64
);
1992 return (t
.bitfield
.disp8
1993 || t
.bitfield
.disp16
1994 || t
.bitfield
.disp32
1995 || t
.bitfield
.disp64
1996 || t
.bitfield
.baseindex
);
2005 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2006 between operand GIVEN and opeand WANTED for instruction template T. */
2009 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2012 return !((i
.types
[given
].bitfield
.byte
2013 && !t
->operand_types
[wanted
].bitfield
.byte
)
2014 || (i
.types
[given
].bitfield
.word
2015 && !t
->operand_types
[wanted
].bitfield
.word
)
2016 || (i
.types
[given
].bitfield
.dword
2017 && !t
->operand_types
[wanted
].bitfield
.dword
)
2018 || (i
.types
[given
].bitfield
.qword
2019 && !t
->operand_types
[wanted
].bitfield
.qword
)
2020 || (i
.types
[given
].bitfield
.tbyte
2021 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2024 /* Return 1 if there is no conflict in SIMD register between operand
2025 GIVEN and opeand WANTED for instruction template T. */
2028 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2031 return !((i
.types
[given
].bitfield
.xmmword
2032 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2033 || (i
.types
[given
].bitfield
.ymmword
2034 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2035 || (i
.types
[given
].bitfield
.zmmword
2036 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2037 || (i
.types
[given
].bitfield
.tmmword
2038 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2041 /* Return 1 if there is no conflict in any size between operand GIVEN
2042 and opeand WANTED for instruction template T. */
2045 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2048 return (match_operand_size (t
, wanted
, given
)
2049 && !((i
.types
[given
].bitfield
.unspecified
2050 && !i
.broadcast
.type
2051 && !i
.broadcast
.bytes
2052 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2053 || (i
.types
[given
].bitfield
.fword
2054 && !t
->operand_types
[wanted
].bitfield
.fword
)
2055 /* For scalar opcode templates to allow register and memory
2056 operands at the same time, some special casing is needed
2057 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2058 down-conversion vpmov*. */
2059 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2060 && t
->operand_types
[wanted
].bitfield
.byte
2061 + t
->operand_types
[wanted
].bitfield
.word
2062 + t
->operand_types
[wanted
].bitfield
.dword
2063 + t
->operand_types
[wanted
].bitfield
.qword
2064 > !!t
->opcode_modifier
.broadcast
)
2065 ? (i
.types
[given
].bitfield
.xmmword
2066 || i
.types
[given
].bitfield
.ymmword
2067 || i
.types
[given
].bitfield
.zmmword
)
2068 : !match_simd_size(t
, wanted
, given
))));
2071 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2072 operands for instruction template T, and it has MATCH_REVERSE set if there
2073 is no size conflict on any operands for the template with operands reversed
2074 (and the template allows for reversing in the first place). */
2076 #define MATCH_STRAIGHT 1
2077 #define MATCH_REVERSE 2
2079 static INLINE
unsigned int
2080 operand_size_match (const insn_template
*t
)
2082 unsigned int j
, match
= MATCH_STRAIGHT
;
2084 /* Don't check non-absolute jump instructions. */
2085 if (t
->opcode_modifier
.jump
2086 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2089 /* Check memory and accumulator operand size. */
2090 for (j
= 0; j
< i
.operands
; j
++)
2092 if (i
.types
[j
].bitfield
.class != Reg
2093 && i
.types
[j
].bitfield
.class != RegSIMD
2094 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2097 if (t
->operand_types
[j
].bitfield
.class == Reg
2098 && !match_operand_size (t
, j
, j
))
2104 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2105 && !match_simd_size (t
, j
, j
))
2111 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2112 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2118 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2125 if (!t
->opcode_modifier
.d
)
2128 /* Check reverse. */
2129 gas_assert ((i
.operands
>= 2 && i
.operands
<= 3)
2130 || t
->opcode_modifier
.vexsources
);
2132 for (j
= 0; j
< i
.operands
; j
++)
2134 unsigned int given
= i
.operands
- j
- 1;
2136 /* For 4- and 5-operand insns VEX.W controls just the first two
2137 register operands. */
2138 if (t
->opcode_modifier
.vexsources
)
2139 given
= j
< 2 ? 1 - j
: j
;
2141 if (t
->operand_types
[j
].bitfield
.class == Reg
2142 && !match_operand_size (t
, j
, given
))
2145 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2146 && !match_simd_size (t
, j
, given
))
2149 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2150 && (!match_operand_size (t
, j
, given
)
2151 || !match_simd_size (t
, j
, given
)))
2154 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2158 return match
| MATCH_REVERSE
;
2162 operand_type_match (i386_operand_type overlap
,
2163 i386_operand_type given
)
2165 i386_operand_type temp
= overlap
;
2167 temp
.bitfield
.unspecified
= 0;
2168 temp
.bitfield
.byte
= 0;
2169 temp
.bitfield
.word
= 0;
2170 temp
.bitfield
.dword
= 0;
2171 temp
.bitfield
.fword
= 0;
2172 temp
.bitfield
.qword
= 0;
2173 temp
.bitfield
.tbyte
= 0;
2174 temp
.bitfield
.xmmword
= 0;
2175 temp
.bitfield
.ymmword
= 0;
2176 temp
.bitfield
.zmmword
= 0;
2177 temp
.bitfield
.tmmword
= 0;
2178 if (operand_type_all_zero (&temp
))
2181 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2185 i
.error
= operand_type_mismatch
;
2189 /* If given types g0 and g1 are registers they must be of the same type
2190 unless the expected operand type register overlap is null.
2191 Intel syntax sized memory operands are also checked here. */
2194 operand_type_register_match (i386_operand_type g0
,
2195 i386_operand_type t0
,
2196 i386_operand_type g1
,
2197 i386_operand_type t1
)
2199 if (g0
.bitfield
.class != Reg
2200 && g0
.bitfield
.class != RegSIMD
2201 && (g0
.bitfield
.unspecified
2202 || !operand_type_check (g0
, anymem
)))
2205 if (g1
.bitfield
.class != Reg
2206 && g1
.bitfield
.class != RegSIMD
2207 && (g1
.bitfield
.unspecified
2208 || !operand_type_check (g1
, anymem
)))
2211 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2212 && g0
.bitfield
.word
== g1
.bitfield
.word
2213 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2214 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2215 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2216 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2217 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2220 /* If expectations overlap in no more than a single size, all is fine. */
2221 g0
= operand_type_and (t0
, t1
);
2222 if (g0
.bitfield
.byte
2226 + g0
.bitfield
.xmmword
2227 + g0
.bitfield
.ymmword
2228 + g0
.bitfield
.zmmword
<= 1)
2231 i
.error
= register_type_mismatch
;
2236 static INLINE
unsigned int
2237 register_number (const reg_entry
*r
)
2239 unsigned int nr
= r
->reg_num
;
2241 if (r
->reg_flags
& RegRex
)
2244 if (r
->reg_flags
& RegVRex
)
2250 static INLINE
unsigned int
2251 mode_from_disp_size (i386_operand_type t
)
2253 if (t
.bitfield
.disp8
)
2255 else if (t
.bitfield
.disp16
2256 || t
.bitfield
.disp32
)
2263 fits_in_signed_byte (addressT num
)
2265 return num
+ 0x80 <= 0xff;
2269 fits_in_unsigned_byte (addressT num
)
2275 fits_in_unsigned_word (addressT num
)
2277 return num
<= 0xffff;
2281 fits_in_signed_word (addressT num
)
2283 return num
+ 0x8000 <= 0xffff;
2287 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2292 return num
+ 0x80000000 <= 0xffffffff;
2294 } /* fits_in_signed_long() */
2297 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2302 return num
<= 0xffffffff;
2304 } /* fits_in_unsigned_long() */
2306 static INLINE valueT
extend_to_32bit_address (addressT num
)
2309 if (fits_in_unsigned_long(num
))
2310 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2312 if (!fits_in_signed_long (num
))
2313 return num
& 0xffffffff;
2320 fits_in_disp8 (offsetT num
)
2322 int shift
= i
.memshift
;
2328 mask
= (1 << shift
) - 1;
2330 /* Return 0 if NUM isn't properly aligned. */
2334 /* Check if NUM will fit in 8bit after shift. */
2335 return fits_in_signed_byte (num
>> shift
);
2339 fits_in_imm4 (offsetT num
)
2341 return (num
& 0xf) == num
;
2344 static i386_operand_type
2345 smallest_imm_type (offsetT num
)
2347 i386_operand_type t
;
2349 operand_type_set (&t
, 0);
2350 t
.bitfield
.imm64
= 1;
2352 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2354 /* This code is disabled on the 486 because all the Imm1 forms
2355 in the opcode table are slower on the i486. They're the
2356 versions with the implicitly specified single-position
2357 displacement, which has another syntax if you really want to
2359 t
.bitfield
.imm1
= 1;
2360 t
.bitfield
.imm8
= 1;
2361 t
.bitfield
.imm8s
= 1;
2362 t
.bitfield
.imm16
= 1;
2363 t
.bitfield
.imm32
= 1;
2364 t
.bitfield
.imm32s
= 1;
2366 else if (fits_in_signed_byte (num
))
2368 t
.bitfield
.imm8
= 1;
2369 t
.bitfield
.imm8s
= 1;
2370 t
.bitfield
.imm16
= 1;
2371 t
.bitfield
.imm32
= 1;
2372 t
.bitfield
.imm32s
= 1;
2374 else if (fits_in_unsigned_byte (num
))
2376 t
.bitfield
.imm8
= 1;
2377 t
.bitfield
.imm16
= 1;
2378 t
.bitfield
.imm32
= 1;
2379 t
.bitfield
.imm32s
= 1;
2381 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2383 t
.bitfield
.imm16
= 1;
2384 t
.bitfield
.imm32
= 1;
2385 t
.bitfield
.imm32s
= 1;
2387 else if (fits_in_signed_long (num
))
2389 t
.bitfield
.imm32
= 1;
2390 t
.bitfield
.imm32s
= 1;
2392 else if (fits_in_unsigned_long (num
))
2393 t
.bitfield
.imm32
= 1;
2399 offset_in_range (offsetT val
, int size
)
2405 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2406 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2408 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2410 case sizeof (val
): return val
;
2414 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2415 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2416 (uint64_t) val
, (uint64_t) (val
& mask
));
2431 a. PREFIX_EXIST if attempting to add a prefix where one from the
2432 same class already exists.
2433 b. PREFIX_LOCK if lock prefix is added.
2434 c. PREFIX_REP if rep/repne prefix is added.
2435 d. PREFIX_DS if ds prefix is added.
2436 e. PREFIX_OTHER if other prefix is added.
2439 static enum PREFIX_GROUP
2440 add_prefix (unsigned int prefix
)
2442 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2445 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2446 && flag_code
== CODE_64BIT
)
2448 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2449 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2450 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2451 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2462 case DS_PREFIX_OPCODE
:
2465 case CS_PREFIX_OPCODE
:
2466 case ES_PREFIX_OPCODE
:
2467 case FS_PREFIX_OPCODE
:
2468 case GS_PREFIX_OPCODE
:
2469 case SS_PREFIX_OPCODE
:
2473 case REPNE_PREFIX_OPCODE
:
2474 case REPE_PREFIX_OPCODE
:
2479 case LOCK_PREFIX_OPCODE
:
2488 case ADDR_PREFIX_OPCODE
:
2492 case DATA_PREFIX_OPCODE
:
2496 if (i
.prefix
[q
] != 0)
2504 i
.prefix
[q
] |= prefix
;
2507 as_bad (_("same type of prefix used twice"));
2513 update_code_flag (int value
, int check
)
2515 PRINTF_LIKE ((*as_error
));
2517 flag_code
= (enum flag_code
) value
;
2518 if (flag_code
== CODE_64BIT
)
2520 cpu_arch_flags
.bitfield
.cpu64
= 1;
2521 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2525 cpu_arch_flags
.bitfield
.cpu64
= 0;
2526 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2528 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2531 as_error
= as_fatal
;
2534 (*as_error
) (_("64bit mode not supported on `%s'."),
2535 cpu_arch_name
? cpu_arch_name
: default_arch
);
2537 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2540 as_error
= as_fatal
;
2543 (*as_error
) (_("32bit mode not supported on `%s'."),
2544 cpu_arch_name
? cpu_arch_name
: default_arch
);
2546 stackop_size
= '\0';
2550 set_code_flag (int value
)
2552 update_code_flag (value
, 0);
2556 set_16bit_gcc_code_flag (int new_code_flag
)
2558 flag_code
= (enum flag_code
) new_code_flag
;
2559 if (flag_code
!= CODE_16BIT
)
2561 cpu_arch_flags
.bitfield
.cpu64
= 0;
2562 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2563 stackop_size
= LONG_MNEM_SUFFIX
;
2567 set_intel_syntax (int syntax_flag
)
2569 /* Find out if register prefixing is specified. */
2570 int ask_naked_reg
= 0;
2573 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2576 int e
= get_symbol_name (&string
);
2578 if (strcmp (string
, "prefix") == 0)
2580 else if (strcmp (string
, "noprefix") == 0)
2583 as_bad (_("bad argument to syntax directive."));
2584 (void) restore_line_pointer (e
);
2586 demand_empty_rest_of_line ();
2588 intel_syntax
= syntax_flag
;
2590 if (ask_naked_reg
== 0)
2591 allow_naked_reg
= (intel_syntax
2592 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2594 allow_naked_reg
= (ask_naked_reg
< 0);
2596 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2598 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2599 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2600 register_prefix
= allow_naked_reg
? "" : "%";
2604 set_intel_mnemonic (int mnemonic_flag
)
2606 intel_mnemonic
= mnemonic_flag
;
2610 set_allow_index_reg (int flag
)
2612 allow_index_reg
= flag
;
2616 set_check (int what
)
2618 enum check_kind
*kind
;
2623 kind
= &operand_check
;
2634 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2637 int e
= get_symbol_name (&string
);
2639 if (strcmp (string
, "none") == 0)
2641 else if (strcmp (string
, "warning") == 0)
2642 *kind
= check_warning
;
2643 else if (strcmp (string
, "error") == 0)
2644 *kind
= check_error
;
2646 as_bad (_("bad argument to %s_check directive."), str
);
2647 (void) restore_line_pointer (e
);
2650 as_bad (_("missing argument for %s_check directive"), str
);
2652 demand_empty_rest_of_line ();
2656 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2657 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2659 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2660 static const char *arch
;
2662 /* Intel MCU is only supported on ELF. */
2668 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2669 use default_arch. */
2670 arch
= cpu_arch_name
;
2672 arch
= default_arch
;
2675 /* If we are targeting Intel MCU, we must enable it. */
2676 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2677 == new_flag
.bitfield
.cpuiamcu
)
2680 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2685 extend_cpu_sub_arch_name (const char *name
)
2687 if (cpu_sub_arch_name
)
2688 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2689 ".", name
, (const char *) NULL
);
2691 cpu_sub_arch_name
= concat (".", name
, (const char *) NULL
);
2695 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2697 typedef struct arch_stack_entry
2699 const struct arch_stack_entry
*prev
;
2702 i386_cpu_flags flags
;
2703 i386_cpu_flags isa_flags
;
2704 enum processor_type isa
;
2705 enum flag_code flag_code
;
2707 bool no_cond_jump_promotion
;
2709 static const arch_stack_entry
*arch_stack_top
;
2713 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2716 int e
= get_symbol_name (&s
);
2717 const char *string
= s
;
2719 i386_cpu_flags flags
;
2721 if (strcmp (string
, "default") == 0)
2723 if (strcmp (default_arch
, "iamcu") == 0)
2724 string
= default_arch
;
2727 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2729 cpu_arch_name
= NULL
;
2730 free (cpu_sub_arch_name
);
2731 cpu_sub_arch_name
= NULL
;
2732 cpu_arch_flags
= cpu_unknown_flags
;
2733 if (flag_code
== CODE_64BIT
)
2735 cpu_arch_flags
.bitfield
.cpu64
= 1;
2736 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2740 cpu_arch_flags
.bitfield
.cpu64
= 0;
2741 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2743 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2744 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2745 if (!cpu_arch_tune_set
)
2747 cpu_arch_tune
= cpu_arch_isa
;
2748 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2751 j
= ARRAY_SIZE (cpu_arch
) + 1;
2754 else if (strcmp (string
, "push") == 0)
2756 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2758 top
->name
= cpu_arch_name
;
2759 if (cpu_sub_arch_name
)
2760 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2762 top
->sub_name
= NULL
;
2763 top
->flags
= cpu_arch_flags
;
2764 top
->isa
= cpu_arch_isa
;
2765 top
->isa_flags
= cpu_arch_isa_flags
;
2766 top
->flag_code
= flag_code
;
2767 top
->stackop_size
= stackop_size
;
2768 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2770 top
->prev
= arch_stack_top
;
2771 arch_stack_top
= top
;
2773 (void) restore_line_pointer (e
);
2774 demand_empty_rest_of_line ();
2777 else if (strcmp (string
, "pop") == 0)
2779 const arch_stack_entry
*top
= arch_stack_top
;
2782 as_bad (_(".arch stack is empty"));
2783 else if (top
->flag_code
!= flag_code
2784 || top
->stackop_size
!= stackop_size
)
2786 static const unsigned int bits
[] = {
2792 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2793 bits
[top
->flag_code
],
2794 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2798 arch_stack_top
= top
->prev
;
2800 cpu_arch_name
= top
->name
;
2801 free (cpu_sub_arch_name
);
2802 cpu_sub_arch_name
= top
->sub_name
;
2803 cpu_arch_flags
= top
->flags
;
2804 cpu_arch_isa
= top
->isa
;
2805 cpu_arch_isa_flags
= top
->isa_flags
;
2806 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2811 (void) restore_line_pointer (e
);
2812 demand_empty_rest_of_line ();
2816 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2818 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2819 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2823 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2825 cpu_arch_name
= cpu_arch
[j
].name
;
2826 free (cpu_sub_arch_name
);
2827 cpu_sub_arch_name
= NULL
;
2828 cpu_arch_flags
= cpu_arch
[j
].enable
;
2829 if (flag_code
== CODE_64BIT
)
2831 cpu_arch_flags
.bitfield
.cpu64
= 1;
2832 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2836 cpu_arch_flags
.bitfield
.cpu64
= 0;
2837 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2839 cpu_arch_isa
= cpu_arch
[j
].type
;
2840 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2841 if (!cpu_arch_tune_set
)
2843 cpu_arch_tune
= cpu_arch_isa
;
2844 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2846 pre_386_16bit_warned
= false;
2850 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
2853 flags
= cpu_flags_or (cpu_arch_flags
,
2854 cpu_arch
[j
].enable
);
2856 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2858 extend_cpu_sub_arch_name (string
+ 1);
2859 cpu_arch_flags
= flags
;
2860 cpu_arch_isa_flags
= flags
;
2864 = cpu_flags_or (cpu_arch_isa_flags
,
2865 cpu_arch
[j
].enable
);
2866 (void) restore_line_pointer (e
);
2867 demand_empty_rest_of_line ();
2872 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
2874 /* Disable an ISA extension. */
2875 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2876 if (cpu_arch
[j
].type
== PROCESSOR_NONE
2877 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
2879 flags
= cpu_flags_and_not (cpu_arch_flags
,
2880 cpu_arch
[j
].disable
);
2881 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2883 extend_cpu_sub_arch_name (string
+ 1);
2884 cpu_arch_flags
= flags
;
2885 cpu_arch_isa_flags
= flags
;
2887 (void) restore_line_pointer (e
);
2888 demand_empty_rest_of_line ();
2893 if (j
== ARRAY_SIZE (cpu_arch
))
2894 as_bad (_("no such architecture: `%s'"), string
);
2896 *input_line_pointer
= e
;
2899 as_bad (_("missing cpu architecture"));
2901 no_cond_jump_promotion
= 0;
2902 if (*input_line_pointer
== ','
2903 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2908 ++input_line_pointer
;
2909 e
= get_symbol_name (&string
);
2911 if (strcmp (string
, "nojumps") == 0)
2912 no_cond_jump_promotion
= 1;
2913 else if (strcmp (string
, "jumps") == 0)
2916 as_bad (_("no such architecture modifier: `%s'"), string
);
2918 (void) restore_line_pointer (e
);
2921 demand_empty_rest_of_line ();
2924 enum bfd_architecture
2927 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2929 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2930 || flag_code
== CODE_64BIT
)
2931 as_fatal (_("Intel MCU is 32bit ELF only"));
2932 return bfd_arch_iamcu
;
2935 return bfd_arch_i386
;
2941 if (startswith (default_arch
, "x86_64"))
2943 if (default_arch
[6] == '\0')
2944 return bfd_mach_x86_64
;
2946 return bfd_mach_x64_32
;
2948 else if (!strcmp (default_arch
, "i386")
2949 || !strcmp (default_arch
, "iamcu"))
2951 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2953 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2954 as_fatal (_("Intel MCU is 32bit ELF only"));
2955 return bfd_mach_i386_iamcu
;
2958 return bfd_mach_i386_i386
;
2961 as_fatal (_("unknown architecture"));
2964 #include "opcodes/i386-tbl.h"
2969 /* Support pseudo prefixes like {disp32}. */
2970 lex_type
['{'] = LEX_BEGIN_NAME
;
2972 /* Initialize op_hash hash table. */
2973 op_hash
= str_htab_create ();
2976 const insn_template
*const *sets
= i386_op_sets
;
2977 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
2979 /* Type checks to compensate for the conversion through void * which
2980 occurs during hash table insertion / lookup. */
2981 (void)(sets
== ¤t_templates
->start
);
2982 (void)(end
== ¤t_templates
->end
);
2983 for (; sets
< end
; ++sets
)
2984 if (str_hash_insert (op_hash
, (*sets
)->name
, sets
, 0))
2985 as_fatal (_("duplicate %s"), (*sets
)->name
);
2988 /* Initialize reg_hash hash table. */
2989 reg_hash
= str_htab_create ();
2991 const reg_entry
*regtab
;
2992 unsigned int regtab_size
= i386_regtab_size
;
2994 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2996 switch (regtab
->reg_type
.bitfield
.class)
2999 if (regtab
->reg_type
.bitfield
.dword
)
3001 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3004 else if (regtab
->reg_type
.bitfield
.tbyte
)
3006 /* There's no point inserting st(<N>) in the hash table, as
3007 parentheses aren't included in register_chars[] anyway. */
3008 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3015 switch (regtab
->reg_num
)
3017 case 0: reg_es
= regtab
; break;
3018 case 2: reg_ss
= regtab
; break;
3019 case 3: reg_ds
= regtab
; break;
3024 if (!regtab
->reg_num
)
3029 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3030 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3034 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3039 for (c
= 0; c
< 256; c
++)
3041 if (ISDIGIT (c
) || ISLOWER (c
))
3043 mnemonic_chars
[c
] = c
;
3044 register_chars
[c
] = c
;
3045 operand_chars
[c
] = c
;
3047 else if (ISUPPER (c
))
3049 mnemonic_chars
[c
] = TOLOWER (c
);
3050 register_chars
[c
] = mnemonic_chars
[c
];
3051 operand_chars
[c
] = c
;
3053 else if (c
== '{' || c
== '}')
3055 mnemonic_chars
[c
] = c
;
3056 operand_chars
[c
] = c
;
3058 #ifdef SVR4_COMMENT_CHARS
3059 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3060 operand_chars
[c
] = c
;
3063 if (ISALPHA (c
) || ISDIGIT (c
))
3064 identifier_chars
[c
] = c
;
3067 identifier_chars
[c
] = c
;
3068 operand_chars
[c
] = c
;
3073 identifier_chars
['@'] = '@';
3076 identifier_chars
['?'] = '?';
3077 operand_chars
['?'] = '?';
3079 mnemonic_chars
['_'] = '_';
3080 mnemonic_chars
['-'] = '-';
3081 mnemonic_chars
['.'] = '.';
3082 identifier_chars
['_'] = '_';
3083 identifier_chars
['.'] = '.';
3085 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3086 operand_chars
[(unsigned char) *p
] = *p
;
3089 if (flag_code
== CODE_64BIT
)
3091 #if defined (OBJ_COFF) && defined (TE_PE)
3092 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3095 x86_dwarf2_return_column
= 16;
3097 x86_cie_data_alignment
= -8;
3098 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3099 x86_sframe_cfa_sp_reg
= 7;
3100 x86_sframe_cfa_fp_reg
= 6;
3105 x86_dwarf2_return_column
= 8;
3106 x86_cie_data_alignment
= -4;
3109 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3110 can be turned into BRANCH_PREFIX frag. */
3111 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3116 i386_print_statistics (FILE *file
)
3118 htab_print_statistics (file
, "i386 opcode", op_hash
);
3119 htab_print_statistics (file
, "i386 register", reg_hash
);
3125 htab_delete (op_hash
);
3126 htab_delete (reg_hash
);
3131 /* Debugging routines for md_assemble. */
3132 static void pte (insn_template
*);
3133 static void pt (i386_operand_type
);
3134 static void pe (expressionS
*);
3135 static void ps (symbolS
*);
3138 pi (const char *line
, i386_insn
*x
)
3142 fprintf (stdout
, "%s: template ", line
);
3144 fprintf (stdout
, " address: base %s index %s scale %x\n",
3145 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3146 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3147 x
->log2_scale_factor
);
3148 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3149 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3150 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3151 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3152 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3153 (x
->rex
& REX_W
) != 0,
3154 (x
->rex
& REX_R
) != 0,
3155 (x
->rex
& REX_X
) != 0,
3156 (x
->rex
& REX_B
) != 0);
3157 for (j
= 0; j
< x
->operands
; j
++)
3159 fprintf (stdout
, " #%d: ", j
+ 1);
3161 fprintf (stdout
, "\n");
3162 if (x
->types
[j
].bitfield
.class == Reg
3163 || x
->types
[j
].bitfield
.class == RegMMX
3164 || x
->types
[j
].bitfield
.class == RegSIMD
3165 || x
->types
[j
].bitfield
.class == RegMask
3166 || x
->types
[j
].bitfield
.class == SReg
3167 || x
->types
[j
].bitfield
.class == RegCR
3168 || x
->types
[j
].bitfield
.class == RegDR
3169 || x
->types
[j
].bitfield
.class == RegTR
3170 || x
->types
[j
].bitfield
.class == RegBND
)
3171 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3172 if (operand_type_check (x
->types
[j
], imm
))
3174 if (operand_type_check (x
->types
[j
], disp
))
3175 pe (x
->op
[j
].disps
);
3180 pte (insn_template
*t
)
3182 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3183 static const char *const opc_spc
[] = {
3184 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3185 "XOP08", "XOP09", "XOP0A",
3189 fprintf (stdout
, " %d operands ", t
->operands
);
3190 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3191 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3192 if (opc_spc
[t
->opcode_modifier
.opcodespace
])
3193 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_modifier
.opcodespace
]);
3194 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3195 if (t
->extension_opcode
!= None
)
3196 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3197 if (t
->opcode_modifier
.d
)
3198 fprintf (stdout
, "D");
3199 if (t
->opcode_modifier
.w
)
3200 fprintf (stdout
, "W");
3201 fprintf (stdout
, "\n");
3202 for (j
= 0; j
< t
->operands
; j
++)
3204 fprintf (stdout
, " #%d type ", j
+ 1);
3205 pt (t
->operand_types
[j
]);
3206 fprintf (stdout
, "\n");
3213 fprintf (stdout
, " operation %d\n", e
->X_op
);
3214 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3215 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3216 if (e
->X_add_symbol
)
3218 fprintf (stdout
, " add_symbol ");
3219 ps (e
->X_add_symbol
);
3220 fprintf (stdout
, "\n");
3224 fprintf (stdout
, " op_symbol ");
3225 ps (e
->X_op_symbol
);
3226 fprintf (stdout
, "\n");
3233 fprintf (stdout
, "%s type %s%s",
3235 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3236 segment_name (S_GET_SEGMENT (s
)));
3239 static struct type_name
3241 i386_operand_type mask
;
3244 const type_names
[] =
3246 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3247 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3248 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3249 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3250 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3251 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3252 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3253 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3254 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3255 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3256 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3257 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3258 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3259 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3260 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3261 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3262 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3263 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3264 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3265 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3266 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3267 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3268 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3269 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3270 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3271 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3272 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3273 { { .bitfield
= { .class = SReg
} }, "SReg" },
3274 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3275 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3276 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3277 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3278 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3279 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3283 pt (i386_operand_type t
)
3286 i386_operand_type a
;
3288 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3290 a
= operand_type_and (t
, type_names
[j
].mask
);
3291 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3292 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3297 #endif /* DEBUG386 */
3299 static bfd_reloc_code_real_type
3300 reloc (unsigned int size
,
3303 bfd_reloc_code_real_type other
)
3305 if (other
!= NO_RELOC
)
3307 reloc_howto_type
*rel
;
3312 case BFD_RELOC_X86_64_GOT32
:
3313 return BFD_RELOC_X86_64_GOT64
;
3315 case BFD_RELOC_X86_64_GOTPLT64
:
3316 return BFD_RELOC_X86_64_GOTPLT64
;
3318 case BFD_RELOC_X86_64_PLTOFF64
:
3319 return BFD_RELOC_X86_64_PLTOFF64
;
3321 case BFD_RELOC_X86_64_GOTPC32
:
3322 other
= BFD_RELOC_X86_64_GOTPC64
;
3324 case BFD_RELOC_X86_64_GOTPCREL
:
3325 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3327 case BFD_RELOC_X86_64_TPOFF32
:
3328 other
= BFD_RELOC_X86_64_TPOFF64
;
3330 case BFD_RELOC_X86_64_DTPOFF32
:
3331 other
= BFD_RELOC_X86_64_DTPOFF64
;
3337 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3338 if (other
== BFD_RELOC_SIZE32
)
3341 other
= BFD_RELOC_SIZE64
;
3344 as_bad (_("there are no pc-relative size relocations"));
3350 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3351 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3354 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3356 as_bad (_("unknown relocation (%u)"), other
);
3357 else if (size
!= bfd_get_reloc_size (rel
))
3358 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3359 bfd_get_reloc_size (rel
),
3361 else if (pcrel
&& !rel
->pc_relative
)
3362 as_bad (_("non-pc-relative relocation for pc-relative field"));
3363 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3365 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3367 as_bad (_("relocated field and relocation type differ in signedness"));
3376 as_bad (_("there are no unsigned pc-relative relocations"));
3379 case 1: return BFD_RELOC_8_PCREL
;
3380 case 2: return BFD_RELOC_16_PCREL
;
3381 case 4: return BFD_RELOC_32_PCREL
;
3382 case 8: return BFD_RELOC_64_PCREL
;
3384 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3391 case 4: return BFD_RELOC_X86_64_32S
;
3396 case 1: return BFD_RELOC_8
;
3397 case 2: return BFD_RELOC_16
;
3398 case 4: return BFD_RELOC_32
;
3399 case 8: return BFD_RELOC_64
;
3401 as_bad (_("cannot do %s %u byte relocation"),
3402 sign
> 0 ? "signed" : "unsigned", size
);
3408 /* Here we decide which fixups can be adjusted to make them relative to
3409 the beginning of the section instead of the symbol. Basically we need
3410 to make sure that the dynamic relocations are done correctly, so in
3411 some cases we force the original symbol to be used. */
3414 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3416 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3420 /* Don't adjust pc-relative references to merge sections in 64-bit
3422 if (use_rela_relocations
3423 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3427 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3428 and changed later by validate_fix. */
3429 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3430 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3433 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3434 for size relocations. */
3435 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3436 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3437 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3438 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3439 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3440 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3441 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3442 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3443 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3444 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3445 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3446 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3447 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3448 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3449 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3450 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3451 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3452 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3453 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3454 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3455 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3456 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3457 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3458 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3459 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3460 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3461 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3462 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3463 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3464 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3465 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3472 want_disp32 (const insn_template
*t
)
3474 return flag_code
!= CODE_64BIT
3475 || i
.prefix
[ADDR_PREFIX
]
3476 || (t
->base_opcode
== 0x8d
3477 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
3478 && (!i
.types
[1].bitfield
.qword
3479 || t
->opcode_modifier
.size
== SIZE32
));
3483 intel_float_operand (const char *mnemonic
)
3485 /* Note that the value returned is meaningful only for opcodes with (memory)
3486 operands, hence the code here is free to improperly handle opcodes that
3487 have no operands (for better performance and smaller code). */
3489 if (mnemonic
[0] != 'f')
3490 return 0; /* non-math */
3492 switch (mnemonic
[1])
3494 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3495 the fs segment override prefix not currently handled because no
3496 call path can make opcodes without operands get here */
3498 return 2 /* integer op */;
3500 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3501 return 3; /* fldcw/fldenv */
3504 if (mnemonic
[2] != 'o' /* fnop */)
3505 return 3; /* non-waiting control op */
3508 if (mnemonic
[2] == 's')
3509 return 3; /* frstor/frstpm */
3512 if (mnemonic
[2] == 'a')
3513 return 3; /* fsave */
3514 if (mnemonic
[2] == 't')
3516 switch (mnemonic
[3])
3518 case 'c': /* fstcw */
3519 case 'd': /* fstdw */
3520 case 'e': /* fstenv */
3521 case 's': /* fsts[gw] */
3527 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3528 return 0; /* fxsave/fxrstor are not really math ops */
3536 install_template (const insn_template
*t
)
3542 /* Note that for pseudo prefixes this produces a length of 1. But for them
3543 the length isn't interesting at all. */
3544 for (l
= 1; l
< 4; ++l
)
3545 if (!(t
->base_opcode
>> (8 * l
)))
3548 i
.opcode_length
= l
;
3551 /* Build the VEX prefix. */
3554 build_vex_prefix (const insn_template
*t
)
3556 unsigned int register_specifier
;
3557 unsigned int vector_length
;
3560 /* Check register specifier. */
3561 if (i
.vex
.register_specifier
)
3563 register_specifier
=
3564 ~register_number (i
.vex
.register_specifier
) & 0xf;
3565 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3568 register_specifier
= 0xf;
3570 /* Use 2-byte VEX prefix by swapping destination and source operand
3571 if there are more than 1 register operand. */
3572 if (i
.reg_operands
> 1
3573 && i
.vec_encoding
!= vex_encoding_vex3
3574 && i
.dir_encoding
== dir_encoding_default
3575 && i
.operands
== i
.reg_operands
3576 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3577 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3578 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3581 unsigned int xchg
= i
.operands
- 1;
3582 union i386_op temp_op
;
3583 i386_operand_type temp_type
;
3585 temp_type
= i
.types
[xchg
];
3586 i
.types
[xchg
] = i
.types
[0];
3587 i
.types
[0] = temp_type
;
3588 temp_op
= i
.op
[xchg
];
3589 i
.op
[xchg
] = i
.op
[0];
3592 gas_assert (i
.rm
.mode
== 3);
3596 i
.rm
.regmem
= i
.rm
.reg
;
3599 if (i
.tm
.opcode_modifier
.d
)
3600 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3601 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3602 else /* Use the next insn. */
3603 install_template (&t
[1]);
3606 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3607 are no memory operands and at least 3 register ones. */
3608 if (i
.reg_operands
>= 3
3609 && i
.vec_encoding
!= vex_encoding_vex3
3610 && i
.reg_operands
== i
.operands
- i
.imm_operands
3611 && i
.tm
.opcode_modifier
.vex
3612 && i
.tm
.opcode_modifier
.commutative
3613 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3615 && i
.vex
.register_specifier
3616 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3618 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3619 union i386_op temp_op
;
3620 i386_operand_type temp_type
;
3622 gas_assert (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
);
3623 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3624 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3625 &i
.types
[i
.operands
- 3]));
3626 gas_assert (i
.rm
.mode
== 3);
3628 temp_type
= i
.types
[xchg
];
3629 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3630 i
.types
[xchg
+ 1] = temp_type
;
3631 temp_op
= i
.op
[xchg
];
3632 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3633 i
.op
[xchg
+ 1] = temp_op
;
3636 xchg
= i
.rm
.regmem
| 8;
3637 i
.rm
.regmem
= ~register_specifier
& 0xf;
3638 gas_assert (!(i
.rm
.regmem
& 8));
3639 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3640 register_specifier
= ~xchg
& 0xf;
3643 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3644 vector_length
= avxscalar
;
3645 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3651 /* Determine vector length from the last multi-length vector
3654 for (op
= t
->operands
; op
--;)
3655 if (t
->operand_types
[op
].bitfield
.xmmword
3656 && t
->operand_types
[op
].bitfield
.ymmword
3657 && i
.types
[op
].bitfield
.ymmword
)
3664 /* Check the REX.W bit and VEXW. */
3665 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3666 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3667 else if (i
.tm
.opcode_modifier
.vexw
)
3668 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3670 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3672 /* Use 2-byte VEX prefix if possible. */
3674 && i
.vec_encoding
!= vex_encoding_vex3
3675 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3676 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3678 /* 2-byte VEX prefix. */
3682 i
.vex
.bytes
[0] = 0xc5;
3684 /* Check the REX.R bit. */
3685 r
= (i
.rex
& REX_R
) ? 0 : 1;
3686 i
.vex
.bytes
[1] = (r
<< 7
3687 | register_specifier
<< 3
3688 | vector_length
<< 2
3689 | i
.tm
.opcode_modifier
.opcodeprefix
);
3693 /* 3-byte VEX prefix. */
3696 switch (i
.tm
.opcode_modifier
.opcodespace
)
3701 i
.vex
.bytes
[0] = 0xc4;
3706 i
.vex
.bytes
[0] = 0x8f;
3712 /* The high 3 bits of the second VEX byte are 1's compliment
3713 of RXB bits from REX. */
3714 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3716 i
.vex
.bytes
[2] = (w
<< 7
3717 | register_specifier
<< 3
3718 | vector_length
<< 2
3719 | i
.tm
.opcode_modifier
.opcodeprefix
);
3724 is_evex_encoding (const insn_template
*t
)
3726 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3727 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3728 || t
->opcode_modifier
.sae
;
3732 is_any_vex_encoding (const insn_template
*t
)
3734 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3738 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3740 unsigned int op
, bytes
;
3741 const i386_operand_type
*types
;
3743 if (i
.broadcast
.type
)
3744 return i
.broadcast
.bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
3745 * i
.broadcast
.type
);
3747 gas_assert (intel_syntax
);
3749 for (op
= 0; op
< t
->operands
; ++op
)
3750 if (t
->operand_types
[op
].bitfield
.baseindex
)
3753 gas_assert (op
< t
->operands
);
3755 if (t
->opcode_modifier
.evex
3756 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3757 switch (i
.broadcast
.bytes
)
3760 if (t
->operand_types
[op
].bitfield
.word
)
3764 if (t
->operand_types
[op
].bitfield
.dword
)
3768 if (t
->operand_types
[op
].bitfield
.qword
)
3772 if (t
->operand_types
[op
].bitfield
.xmmword
)
3774 if (t
->operand_types
[op
].bitfield
.ymmword
)
3776 if (t
->operand_types
[op
].bitfield
.zmmword
)
3783 gas_assert (op
+ 1 < t
->operands
);
3785 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3786 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3787 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3789 types
= &i
.types
[op
+ 1];
3792 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3793 types
= &t
->operand_types
[op
];
3795 if (types
->bitfield
.zmmword
)
3797 else if (types
->bitfield
.ymmword
)
3803 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3804 t
->name
, bytes
* 8);
3809 /* Build the EVEX prefix. */
3812 build_evex_prefix (void)
3814 unsigned int register_specifier
, w
;
3815 rex_byte vrex_used
= 0;
3817 /* Check register specifier. */
3818 if (i
.vex
.register_specifier
)
3820 gas_assert ((i
.vrex
& REX_X
) == 0);
3822 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3823 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3824 register_specifier
+= 8;
3825 /* The upper 16 registers are encoded in the fourth byte of the
3827 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3828 i
.vex
.bytes
[3] = 0x8;
3829 register_specifier
= ~register_specifier
& 0xf;
3833 register_specifier
= 0xf;
3835 /* Encode upper 16 vector index register in the fourth byte of
3837 if (!(i
.vrex
& REX_X
))
3838 i
.vex
.bytes
[3] = 0x8;
3843 /* 4 byte EVEX prefix. */
3845 i
.vex
.bytes
[0] = 0x62;
3847 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3849 gas_assert (i
.tm
.opcode_modifier
.opcodespace
>= SPACE_0F
);
3850 gas_assert (i
.tm
.opcode_modifier
.opcodespace
<= SPACE_EVEXMAP6
);
3851 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3853 /* The fifth bit of the second EVEX byte is 1's compliment of the
3854 REX_R bit in VREX. */
3855 if (!(i
.vrex
& REX_R
))
3856 i
.vex
.bytes
[1] |= 0x10;
3860 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3862 /* When all operands are registers, the REX_X bit in REX is not
3863 used. We reuse it to encode the upper 16 registers, which is
3864 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3865 as 1's compliment. */
3866 if ((i
.vrex
& REX_B
))
3869 i
.vex
.bytes
[1] &= ~0x40;
3873 /* EVEX instructions shouldn't need the REX prefix. */
3874 i
.vrex
&= ~vrex_used
;
3875 gas_assert (i
.vrex
== 0);
3877 /* Check the REX.W bit and VEXW. */
3878 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3879 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3880 else if (i
.tm
.opcode_modifier
.vexw
)
3881 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3883 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3885 /* The third byte of the EVEX prefix. */
3886 i
.vex
.bytes
[2] = ((w
<< 7)
3887 | (register_specifier
<< 3)
3888 | 4 /* Encode the U bit. */
3889 | i
.tm
.opcode_modifier
.opcodeprefix
);
3891 /* The fourth byte of the EVEX prefix. */
3892 /* The zeroing-masking bit. */
3893 if (i
.mask
.reg
&& i
.mask
.zeroing
)
3894 i
.vex
.bytes
[3] |= 0x80;
3896 /* Don't always set the broadcast bit if there is no RC. */
3897 if (i
.rounding
.type
== rc_none
)
3899 /* Encode the vector length. */
3900 unsigned int vec_length
;
3902 if (!i
.tm
.opcode_modifier
.evex
3903 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3907 /* Determine vector length from the last multi-length vector
3909 for (op
= i
.operands
; op
--;)
3910 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3911 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3912 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3914 if (i
.types
[op
].bitfield
.zmmword
)
3916 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3919 else if (i
.types
[op
].bitfield
.ymmword
)
3921 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3924 else if (i
.types
[op
].bitfield
.xmmword
)
3926 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3929 else if (i
.broadcast
.bytes
&& op
== i
.broadcast
.operand
)
3931 switch (get_broadcast_bytes (&i
.tm
, true))
3934 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3937 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3940 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3949 if (op
>= MAX_OPERANDS
)
3953 switch (i
.tm
.opcode_modifier
.evex
)
3955 case EVEXLIG
: /* LL' is ignored */
3956 vec_length
= evexlig
<< 5;
3959 vec_length
= 0 << 5;
3962 vec_length
= 1 << 5;
3965 vec_length
= 2 << 5;
3971 i
.vex
.bytes
[3] |= vec_length
;
3972 /* Encode the broadcast bit. */
3973 if (i
.broadcast
.bytes
)
3974 i
.vex
.bytes
[3] |= 0x10;
3976 else if (i
.rounding
.type
!= saeonly
)
3977 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
3979 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3982 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
3986 process_immext (void)
3990 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3991 which is coded in the same place as an 8-bit immediate field
3992 would be. Here we fake an 8-bit immediate operand from the
3993 opcode suffix stored in tm.extension_opcode.
3995 AVX instructions also use this encoding, for some of
3996 3 argument instructions. */
3998 gas_assert (i
.imm_operands
<= 1
4000 || (is_any_vex_encoding (&i
.tm
)
4001 && i
.operands
<= 4)));
4003 exp
= &im_expressions
[i
.imm_operands
++];
4004 i
.op
[i
.operands
].imms
= exp
;
4005 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4007 exp
->X_op
= O_constant
;
4008 exp
->X_add_number
= i
.tm
.extension_opcode
;
4009 i
.tm
.extension_opcode
= None
;
4016 switch (i
.tm
.opcode_modifier
.prefixok
)
4024 as_bad (_("invalid instruction `%s' after `%s'"),
4025 i
.tm
.name
, i
.hle_prefix
);
4028 if (i
.prefix
[LOCK_PREFIX
])
4030 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4034 case PrefixHLERelease
:
4035 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4037 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4041 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4043 as_bad (_("memory destination needed for instruction `%s'"
4044 " after `xrelease'"), i
.tm
.name
);
4051 /* Encode aligned vector move as unaligned vector move. */
4054 encode_with_unaligned_vector_move (void)
4056 switch (i
.tm
.base_opcode
)
4058 case 0x28: /* Load instructions. */
4059 case 0x29: /* Store instructions. */
4060 /* movaps/movapd/vmovaps/vmovapd. */
4061 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4062 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4063 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4065 case 0x6f: /* Load instructions. */
4066 case 0x7f: /* Store instructions. */
4067 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4068 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4069 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4070 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4077 /* Try the shortest encoding by shortening operand size. */
4080 optimize_encoding (void)
4084 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4085 && i
.tm
.base_opcode
== 0x8d)
4088 lea symbol, %rN -> mov $symbol, %rN
4089 lea (%rM), %rN -> mov %rM, %rN
4090 lea (,%rM,1), %rN -> mov %rM, %rN
4092 and in 32-bit mode for 16-bit addressing
4094 lea (%rM), %rN -> movzx %rM, %rN
4096 and in 64-bit mode zap 32-bit addressing in favor of using a
4097 32-bit (or less) destination.
4099 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4101 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4102 i
.tm
.opcode_modifier
.size
= SIZE32
;
4103 i
.prefix
[ADDR_PREFIX
] = 0;
4106 if (!i
.index_reg
&& !i
.base_reg
)
4109 lea symbol, %rN -> mov $symbol, %rN
4111 if (flag_code
== CODE_64BIT
)
4113 /* Don't transform a relocation to a 16-bit one. */
4115 && i
.op
[0].disps
->X_op
!= O_constant
4116 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4119 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4120 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4122 i
.tm
.base_opcode
= 0xb8;
4123 i
.tm
.opcode_modifier
.modrm
= 0;
4124 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4125 i
.types
[0].bitfield
.imm32
= 1;
4128 i
.tm
.opcode_modifier
.size
= SIZE16
;
4129 i
.types
[0].bitfield
.imm16
= 1;
4134 /* Subject to further optimization below. */
4135 i
.tm
.base_opcode
= 0xc7;
4136 i
.tm
.extension_opcode
= 0;
4137 i
.types
[0].bitfield
.imm32s
= 1;
4138 i
.types
[0].bitfield
.baseindex
= 0;
4141 /* Outside of 64-bit mode address and operand sizes have to match if
4142 a relocation is involved, as otherwise we wouldn't (currently) or
4143 even couldn't express the relocation correctly. */
4144 else if (i
.op
[0].disps
4145 && i
.op
[0].disps
->X_op
!= O_constant
4146 && ((!i
.prefix
[ADDR_PREFIX
])
4147 != (flag_code
== CODE_32BIT
4148 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4149 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4151 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4152 destination is going to grow encoding size. */
4153 else if (flag_code
== CODE_16BIT
4154 && (optimize
<= 1 || optimize_for_space
)
4155 && !i
.prefix
[ADDR_PREFIX
]
4156 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4160 i
.tm
.base_opcode
= 0xb8;
4161 i
.tm
.opcode_modifier
.modrm
= 0;
4162 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4163 i
.types
[0].bitfield
.imm32
= 1;
4165 i
.types
[0].bitfield
.imm16
= 1;
4168 && i
.op
[0].disps
->X_op
== O_constant
4169 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4170 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4172 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4173 i
.op
[0].disps
->X_add_number
&= 0xffff;
4176 i
.tm
.operand_types
[0] = i
.types
[0];
4180 i
.op
[0].imms
= &im_expressions
[0];
4181 i
.op
[0].imms
->X_op
= O_absent
;
4184 else if (i
.op
[0].disps
4185 && (i
.op
[0].disps
->X_op
!= O_constant
4186 || i
.op
[0].disps
->X_add_number
))
4191 lea (%rM), %rN -> mov %rM, %rN
4192 lea (,%rM,1), %rN -> mov %rM, %rN
4193 lea (%rM), %rN -> movzx %rM, %rN
4195 const reg_entry
*addr_reg
;
4197 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4198 addr_reg
= i
.base_reg
;
4199 else if (!i
.base_reg
4200 && i
.index_reg
->reg_num
!= RegIZ
4201 && !i
.log2_scale_factor
)
4202 addr_reg
= i
.index_reg
;
4206 if (addr_reg
->reg_type
.bitfield
.word
4207 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4209 if (flag_code
!= CODE_32BIT
)
4211 i
.tm
.opcode_modifier
.opcodespace
= SPACE_0F
;
4212 i
.tm
.base_opcode
= 0xb7;
4215 i
.tm
.base_opcode
= 0x8b;
4217 if (addr_reg
->reg_type
.bitfield
.dword
4218 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4219 i
.tm
.opcode_modifier
.size
= SIZE32
;
4221 i
.op
[0].regs
= addr_reg
;
4226 i
.disp_operands
= 0;
4227 i
.prefix
[ADDR_PREFIX
] = 0;
4228 i
.prefix
[SEG_PREFIX
] = 0;
4232 if (optimize_for_space
4233 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4234 && i
.reg_operands
== 1
4235 && i
.imm_operands
== 1
4236 && !i
.types
[1].bitfield
.byte
4237 && i
.op
[0].imms
->X_op
== O_constant
4238 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4239 && (i
.tm
.base_opcode
== 0xa8
4240 || (i
.tm
.base_opcode
== 0xf6
4241 && i
.tm
.extension_opcode
== 0x0)))
4244 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4246 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4247 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4249 i
.types
[1].bitfield
.byte
= 1;
4250 /* Ignore the suffix. */
4252 /* Convert to byte registers. */
4253 if (i
.types
[1].bitfield
.word
)
4255 else if (i
.types
[1].bitfield
.dword
)
4259 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4264 else if (flag_code
== CODE_64BIT
4265 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4266 && ((i
.types
[1].bitfield
.qword
4267 && i
.reg_operands
== 1
4268 && i
.imm_operands
== 1
4269 && i
.op
[0].imms
->X_op
== O_constant
4270 && ((i
.tm
.base_opcode
== 0xb8
4271 && i
.tm
.extension_opcode
== None
4272 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4273 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4274 && ((i
.tm
.base_opcode
== 0x24
4275 || i
.tm
.base_opcode
== 0xa8)
4276 || (i
.tm
.base_opcode
== 0x80
4277 && i
.tm
.extension_opcode
== 0x4)
4278 || ((i
.tm
.base_opcode
== 0xf6
4279 || (i
.tm
.base_opcode
| 1) == 0xc7)
4280 && i
.tm
.extension_opcode
== 0x0)))
4281 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4282 && i
.tm
.base_opcode
== 0x83
4283 && i
.tm
.extension_opcode
== 0x4)))
4284 || (i
.types
[0].bitfield
.qword
4285 && ((i
.reg_operands
== 2
4286 && i
.op
[0].regs
== i
.op
[1].regs
4287 && (i
.tm
.base_opcode
== 0x30
4288 || i
.tm
.base_opcode
== 0x28))
4289 || (i
.reg_operands
== 1
4291 && i
.tm
.base_opcode
== 0x30)))))
4294 andq $imm31, %r64 -> andl $imm31, %r32
4295 andq $imm7, %r64 -> andl $imm7, %r32
4296 testq $imm31, %r64 -> testl $imm31, %r32
4297 xorq %r64, %r64 -> xorl %r32, %r32
4298 subq %r64, %r64 -> subl %r32, %r32
4299 movq $imm31, %r64 -> movl $imm31, %r32
4300 movq $imm32, %r64 -> movl $imm32, %r32
4302 i
.tm
.opcode_modifier
.norex64
= 1;
4303 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4306 movq $imm31, %r64 -> movl $imm31, %r32
4307 movq $imm32, %r64 -> movl $imm32, %r32
4309 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4310 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4311 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4312 i
.types
[0].bitfield
.imm32
= 1;
4313 i
.types
[0].bitfield
.imm32s
= 0;
4314 i
.types
[0].bitfield
.imm64
= 0;
4315 i
.types
[1].bitfield
.dword
= 1;
4316 i
.types
[1].bitfield
.qword
= 0;
4317 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4320 movq $imm31, %r64 -> movl $imm31, %r32
4322 i
.tm
.base_opcode
= 0xb8;
4323 i
.tm
.extension_opcode
= None
;
4324 i
.tm
.opcode_modifier
.w
= 0;
4325 i
.tm
.opcode_modifier
.modrm
= 0;
4329 else if (optimize
> 1
4330 && !optimize_for_space
4331 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4332 && i
.reg_operands
== 2
4333 && i
.op
[0].regs
== i
.op
[1].regs
4334 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4335 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4336 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4339 andb %rN, %rN -> testb %rN, %rN
4340 andw %rN, %rN -> testw %rN, %rN
4341 andq %rN, %rN -> testq %rN, %rN
4342 orb %rN, %rN -> testb %rN, %rN
4343 orw %rN, %rN -> testw %rN, %rN
4344 orq %rN, %rN -> testq %rN, %rN
4346 and outside of 64-bit mode
4348 andl %rN, %rN -> testl %rN, %rN
4349 orl %rN, %rN -> testl %rN, %rN
4351 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4353 else if (i
.reg_operands
== 3
4354 && i
.op
[0].regs
== i
.op
[1].regs
4355 && !i
.types
[2].bitfield
.xmmword
4356 && (i
.tm
.opcode_modifier
.vex
4357 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4358 && is_evex_encoding (&i
.tm
)
4359 && (i
.vec_encoding
!= vex_encoding_evex
4360 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4361 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4362 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4363 && i
.types
[2].bitfield
.ymmword
))))
4364 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4365 && ((i
.tm
.base_opcode
| 2) == 0x57
4366 || i
.tm
.base_opcode
== 0xdf
4367 || i
.tm
.base_opcode
== 0xef
4368 || (i
.tm
.base_opcode
| 3) == 0xfb
4369 || i
.tm
.base_opcode
== 0x42
4370 || i
.tm
.base_opcode
== 0x47))
4373 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4375 EVEX VOP %zmmM, %zmmM, %zmmN
4376 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4377 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4378 EVEX VOP %ymmM, %ymmM, %ymmN
4379 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4380 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4381 VEX VOP %ymmM, %ymmM, %ymmN
4382 -> VEX VOP %xmmM, %xmmM, %xmmN
4383 VOP, one of vpandn and vpxor:
4384 VEX VOP %ymmM, %ymmM, %ymmN
4385 -> VEX VOP %xmmM, %xmmM, %xmmN
4386 VOP, one of vpandnd and vpandnq:
4387 EVEX VOP %zmmM, %zmmM, %zmmN
4388 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4389 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4390 EVEX VOP %ymmM, %ymmM, %ymmN
4391 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4392 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4393 VOP, one of vpxord and vpxorq:
4394 EVEX VOP %zmmM, %zmmM, %zmmN
4395 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4396 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4397 EVEX VOP %ymmM, %ymmM, %ymmN
4398 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4399 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4400 VOP, one of kxord and kxorq:
4401 VEX VOP %kM, %kM, %kN
4402 -> VEX kxorw %kM, %kM, %kN
4403 VOP, one of kandnd and kandnq:
4404 VEX VOP %kM, %kM, %kN
4405 -> VEX kandnw %kM, %kM, %kN
4407 if (is_evex_encoding (&i
.tm
))
4409 if (i
.vec_encoding
!= vex_encoding_evex
)
4411 i
.tm
.opcode_modifier
.vex
= VEX128
;
4412 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4413 i
.tm
.opcode_modifier
.evex
= 0;
4415 else if (optimize
> 1)
4416 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4420 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4422 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4423 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4426 i
.tm
.opcode_modifier
.vex
= VEX128
;
4428 if (i
.tm
.opcode_modifier
.vex
)
4429 for (j
= 0; j
< 3; j
++)
4431 i
.types
[j
].bitfield
.xmmword
= 1;
4432 i
.types
[j
].bitfield
.ymmword
= 0;
4435 else if (i
.vec_encoding
!= vex_encoding_evex
4436 && !i
.types
[0].bitfield
.zmmword
4437 && !i
.types
[1].bitfield
.zmmword
4439 && !i
.broadcast
.bytes
4440 && is_evex_encoding (&i
.tm
)
4441 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4442 || (i
.tm
.base_opcode
& ~4) == 0xdb
4443 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4444 && i
.tm
.extension_opcode
== None
)
4447 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4448 vmovdqu32 and vmovdqu64:
4449 EVEX VOP %xmmM, %xmmN
4450 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4451 EVEX VOP %ymmM, %ymmN
4452 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4454 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4456 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4458 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4460 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4461 VOP, one of vpand, vpandn, vpor, vpxor:
4462 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4463 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4464 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4465 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4466 EVEX VOP{d,q} mem, %xmmM, %xmmN
4467 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4468 EVEX VOP{d,q} mem, %ymmM, %ymmN
4469 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4471 for (j
= 0; j
< i
.operands
; j
++)
4472 if (operand_type_check (i
.types
[j
], disp
)
4473 && i
.op
[j
].disps
->X_op
== O_constant
)
4475 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4476 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4477 bytes, we choose EVEX Disp8 over VEX Disp32. */
4478 int evex_disp8
, vex_disp8
;
4479 unsigned int memshift
= i
.memshift
;
4480 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4482 evex_disp8
= fits_in_disp8 (n
);
4484 vex_disp8
= fits_in_disp8 (n
);
4485 if (evex_disp8
!= vex_disp8
)
4487 i
.memshift
= memshift
;
4491 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4494 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4495 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4496 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4497 i
.tm
.opcode_modifier
.vex
4498 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4499 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4500 /* VPAND, VPOR, and VPXOR are commutative. */
4501 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4502 i
.tm
.opcode_modifier
.commutative
= 1;
4503 i
.tm
.opcode_modifier
.evex
= 0;
4504 i
.tm
.opcode_modifier
.masking
= 0;
4505 i
.tm
.opcode_modifier
.broadcast
= 0;
4506 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4509 i
.types
[j
].bitfield
.disp8
4510 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4514 /* Return non-zero for load instruction. */
4520 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4521 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4525 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4526 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4527 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4531 if (strcmp (i
.tm
.name
, "pop") == 0)
4535 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
4538 if (i
.tm
.base_opcode
== 0x9d
4539 || i
.tm
.base_opcode
== 0x61)
4542 /* movs, cmps, lods, scas. */
4543 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4547 if (base_opcode
== 0x6f
4548 || i
.tm
.base_opcode
== 0xd7)
4550 /* NB: For AMD-specific insns with implicit memory operands,
4551 they're intentionally not covered. */
4554 /* No memory operand. */
4555 if (!i
.mem_operands
)
4561 if (i
.tm
.base_opcode
== 0xae
4562 && i
.tm
.opcode_modifier
.vex
4563 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4564 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4565 && i
.tm
.extension_opcode
== 2)
4568 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
4570 /* test, not, neg, mul, imul, div, idiv. */
4571 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4572 && i
.tm
.extension_opcode
!= 1)
4576 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4579 /* add, or, adc, sbb, and, sub, xor, cmp. */
4580 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4583 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4584 if ((base_opcode
== 0xc1
4585 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4586 && i
.tm
.extension_opcode
!= 6)
4589 /* Check for x87 instructions. */
4590 if (base_opcode
>= 0xd8 && base_opcode
<= 0xdf)
4592 /* Skip fst, fstp, fstenv, fstcw. */
4593 if (i
.tm
.base_opcode
== 0xd9
4594 && (i
.tm
.extension_opcode
== 2
4595 || i
.tm
.extension_opcode
== 3
4596 || i
.tm
.extension_opcode
== 6
4597 || i
.tm
.extension_opcode
== 7))
4600 /* Skip fisttp, fist, fistp, fstp. */
4601 if (i
.tm
.base_opcode
== 0xdb
4602 && (i
.tm
.extension_opcode
== 1
4603 || i
.tm
.extension_opcode
== 2
4604 || i
.tm
.extension_opcode
== 3
4605 || i
.tm
.extension_opcode
== 7))
4608 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4609 if (i
.tm
.base_opcode
== 0xdd
4610 && (i
.tm
.extension_opcode
== 1
4611 || i
.tm
.extension_opcode
== 2
4612 || i
.tm
.extension_opcode
== 3
4613 || i
.tm
.extension_opcode
== 6
4614 || i
.tm
.extension_opcode
== 7))
4617 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4618 if (i
.tm
.base_opcode
== 0xdf
4619 && (i
.tm
.extension_opcode
== 1
4620 || i
.tm
.extension_opcode
== 2
4621 || i
.tm
.extension_opcode
== 3
4622 || i
.tm
.extension_opcode
== 6
4623 || i
.tm
.extension_opcode
== 7))
4629 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
)
4631 /* bt, bts, btr, btc. */
4632 if (i
.tm
.base_opcode
== 0xba
4633 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4636 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4637 if (i
.tm
.base_opcode
== 0xc7
4638 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4639 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4640 || i
.tm
.extension_opcode
== 6))
4643 /* fxrstor, ldmxcsr, xrstor. */
4644 if (i
.tm
.base_opcode
== 0xae
4645 && (i
.tm
.extension_opcode
== 1
4646 || i
.tm
.extension_opcode
== 2
4647 || i
.tm
.extension_opcode
== 5))
4650 /* lgdt, lidt, lmsw. */
4651 if (i
.tm
.base_opcode
== 0x01
4652 && (i
.tm
.extension_opcode
== 2
4653 || i
.tm
.extension_opcode
== 3
4654 || i
.tm
.extension_opcode
== 6))
4658 dest
= i
.operands
- 1;
4660 /* Check fake imm8 operand and 3 source operands. */
4661 if ((i
.tm
.opcode_modifier
.immext
4662 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4663 && i
.types
[dest
].bitfield
.imm8
)
4666 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4667 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4668 && (base_opcode
== 0x1
4669 || base_opcode
== 0x9
4670 || base_opcode
== 0x11
4671 || base_opcode
== 0x19
4672 || base_opcode
== 0x21
4673 || base_opcode
== 0x29
4674 || base_opcode
== 0x31
4675 || base_opcode
== 0x39
4676 || (base_opcode
| 2) == 0x87))
4680 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4681 && base_opcode
== 0xc1)
4684 /* Check for load instruction. */
4685 return (i
.types
[dest
].bitfield
.class != ClassNone
4686 || i
.types
[dest
].bitfield
.instance
== Accum
);
4689 /* Output lfence, 0xfaee8, after instruction. */
4692 insert_lfence_after (void)
4694 if (lfence_after_load
&& load_insn_p ())
4696 /* There are also two REP string instructions that require
4697 special treatment. Specifically, the compare string (CMPS)
4698 and scan string (SCAS) instructions set EFLAGS in a manner
4699 that depends on the data being compared/scanned. When used
4700 with a REP prefix, the number of iterations may therefore
4701 vary depending on this data. If the data is a program secret
4702 chosen by the adversary using an LVI method,
4703 then this data-dependent behavior may leak some aspect
4705 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4706 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4707 && i
.prefix
[REP_PREFIX
])
4709 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4712 char *p
= frag_more (3);
4719 /* Output lfence, 0xfaee8, before instruction. */
4722 insert_lfence_before (void)
4726 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
4729 if (i
.tm
.base_opcode
== 0xff
4730 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4732 /* Insert lfence before indirect branch if needed. */
4734 if (lfence_before_indirect_branch
== lfence_branch_none
)
4737 if (i
.operands
!= 1)
4740 if (i
.reg_operands
== 1)
4742 /* Indirect branch via register. Don't insert lfence with
4743 -mlfence-after-load=yes. */
4744 if (lfence_after_load
4745 || lfence_before_indirect_branch
== lfence_branch_memory
)
4748 else if (i
.mem_operands
== 1
4749 && lfence_before_indirect_branch
!= lfence_branch_register
)
4751 as_warn (_("indirect `%s` with memory operand should be avoided"),
4758 if (last_insn
.kind
!= last_insn_other
4759 && last_insn
.seg
== now_seg
)
4761 as_warn_where (last_insn
.file
, last_insn
.line
,
4762 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4763 last_insn
.name
, i
.tm
.name
);
4774 /* Output or/not/shl and lfence before near ret. */
4775 if (lfence_before_ret
!= lfence_before_ret_none
4776 && (i
.tm
.base_opcode
== 0xc2
4777 || i
.tm
.base_opcode
== 0xc3))
4779 if (last_insn
.kind
!= last_insn_other
4780 && last_insn
.seg
== now_seg
)
4782 as_warn_where (last_insn
.file
, last_insn
.line
,
4783 _("`%s` skips -mlfence-before-ret on `%s`"),
4784 last_insn
.name
, i
.tm
.name
);
4788 /* Near ret ingore operand size override under CPU64. */
4789 char prefix
= flag_code
== CODE_64BIT
4791 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4793 if (lfence_before_ret
== lfence_before_ret_not
)
4795 /* not: 0xf71424, may add prefix
4796 for operand size override or 64-bit code. */
4797 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4811 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4814 if (lfence_before_ret
== lfence_before_ret_or
)
4816 /* or: 0x830c2400, may add prefix
4817 for operand size override or 64-bit code. */
4823 /* shl: 0xc1242400, may add prefix
4824 for operand size override or 64-bit code. */
4839 /* This is the guts of the machine-dependent assembler. LINE points to a
4840 machine dependent instruction. This function is supposed to emit
4841 the frags/bytes it assembles to. */
4844 md_assemble (char *line
)
4847 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4848 const insn_template
*t
;
4850 /* Initialize globals. */
4851 memset (&i
, '\0', sizeof (i
));
4852 i
.rounding
.type
= rc_none
;
4853 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4854 i
.reloc
[j
] = NO_RELOC
;
4855 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4856 memset (im_expressions
, '\0', sizeof (im_expressions
));
4857 save_stack_p
= save_stack
;
4859 /* First parse an instruction mnemonic & call i386_operand for the operands.
4860 We assume that the scrubber has arranged it so that line[0] is the valid
4861 start of a (possibly prefixed) mnemonic. */
4863 line
= parse_insn (line
, mnemonic
);
4866 mnem_suffix
= i
.suffix
;
4868 line
= parse_operands (line
, mnemonic
);
4870 xfree (i
.memop1_string
);
4871 i
.memop1_string
= NULL
;
4875 /* Now we've parsed the mnemonic into a set of templates, and have the
4876 operands at hand. */
4878 /* All Intel opcodes have reversed operands except for "bound", "enter",
4879 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
4880 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
4881 intersegment "jmp" and "call" instructions with 2 immediate operands so
4882 that the immediate segment precedes the offset consistently in Intel and
4886 && (strcmp (mnemonic
, "bound") != 0)
4887 && (strncmp (mnemonic
, "invlpg", 6) != 0)
4888 && !startswith (mnemonic
, "monitor")
4889 && !startswith (mnemonic
, "mwait")
4890 && (strcmp (mnemonic
, "pvalidate") != 0)
4891 && !startswith (mnemonic
, "rmp")
4892 && (strcmp (mnemonic
, "tpause") != 0)
4893 && (strcmp (mnemonic
, "umwait") != 0)
4894 && !(i
.operands
== 2
4895 && operand_type_check (i
.types
[0], imm
)
4896 && operand_type_check (i
.types
[1], imm
)))
4899 /* The order of the immediates should be reversed
4900 for 2 immediates extrq and insertq instructions */
4901 if (i
.imm_operands
== 2
4902 && (strcmp (mnemonic
, "extrq") == 0
4903 || strcmp (mnemonic
, "insertq") == 0))
4904 swap_2_operands (0, 1);
4909 if (i
.disp_operands
&& !want_disp32 (current_templates
->start
)
4910 && (!current_templates
->start
->opcode_modifier
.jump
4911 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
4913 for (j
= 0; j
< i
.operands
; ++j
)
4915 const expressionS
*exp
= i
.op
[j
].disps
;
4917 if (!operand_type_check (i
.types
[j
], disp
))
4920 if (exp
->X_op
!= O_constant
)
4923 /* Since displacement is signed extended to 64bit, don't allow
4924 disp32 if it is out of range. */
4925 if (fits_in_signed_long (exp
->X_add_number
))
4928 i
.types
[j
].bitfield
.disp32
= 0;
4929 if (i
.types
[j
].bitfield
.baseindex
)
4931 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
4932 (uint64_t) exp
->X_add_number
);
4938 /* Don't optimize displacement for movabs since it only takes 64bit
4941 && i
.disp_encoding
<= disp_encoding_8bit
4942 && (flag_code
!= CODE_64BIT
4943 || strcmp (mnemonic
, "movabs") != 0))
4946 /* Next, we find a template that matches the given insn,
4947 making sure the overlap of the given operands types is consistent
4948 with the template operand types. */
4950 if (!(t
= match_template (mnem_suffix
)))
4953 if (sse_check
!= check_none
4954 /* The opcode space check isn't strictly needed; it's there only to
4955 bypass the logic below when easily possible. */
4956 && t
->opcode_modifier
.opcodespace
>= SPACE_0F
4957 && t
->opcode_modifier
.opcodespace
<= SPACE_0F3A
4958 && !i
.tm
.cpu_flags
.bitfield
.cpusse4a
4959 && !is_any_vex_encoding (t
))
4963 for (j
= 0; j
< t
->operands
; ++j
)
4965 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
4967 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
4971 if (j
>= t
->operands
&& simd
)
4972 (sse_check
== check_warning
4974 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4977 if (i
.tm
.opcode_modifier
.fwait
)
4978 if (!add_prefix (FWAIT_OPCODE
))
4981 /* Check if REP prefix is OK. */
4982 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
4984 as_bad (_("invalid instruction `%s' after `%s'"),
4985 i
.tm
.name
, i
.rep_prefix
);
4989 /* Check for lock without a lockable instruction. Destination operand
4990 must be memory unless it is xchg (0x86). */
4991 if (i
.prefix
[LOCK_PREFIX
]
4992 && (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
4993 || i
.mem_operands
== 0
4994 || (i
.tm
.base_opcode
!= 0x86
4995 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4997 as_bad (_("expecting lockable instruction after `lock'"));
5001 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5002 if (i
.prefix
[DATA_PREFIX
]
5003 && (is_any_vex_encoding (&i
.tm
)
5004 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5005 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
5007 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
5011 /* Check if HLE prefix is OK. */
5012 if (i
.hle_prefix
&& !check_hle ())
5015 /* Check BND prefix. */
5016 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5017 as_bad (_("expecting valid branch instruction after `bnd'"));
5019 /* Check NOTRACK prefix. */
5020 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5021 as_bad (_("expecting indirect branch instruction after `notrack'"));
5023 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
5025 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5026 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5027 else if (flag_code
!= CODE_16BIT
5028 ? i
.prefix
[ADDR_PREFIX
]
5029 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5030 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5033 /* Insert BND prefix. */
5034 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5036 if (!i
.prefix
[BND_PREFIX
])
5037 add_prefix (BND_PREFIX_OPCODE
);
5038 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5040 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5041 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5045 /* Check string instruction segment overrides. */
5046 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5048 gas_assert (i
.mem_operands
);
5049 if (!check_string ())
5051 i
.disp_operands
= 0;
5054 /* The memory operand of (%dx) should be only used with input/output
5055 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5056 if (i
.input_output_operand
5057 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5058 || i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
))
5060 as_bad (_("input/output port address isn't allowed with `%s'"),
5065 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5066 optimize_encoding ();
5068 if (use_unaligned_vector_move
)
5069 encode_with_unaligned_vector_move ();
5071 if (!process_suffix ())
5074 /* Check if IP-relative addressing requirements can be satisfied. */
5075 if (i
.tm
.cpu_flags
.bitfield
.cpuprefetchi
5076 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5077 as_warn (_("'%s' only supports RIP-relative address"), i
.tm
.name
);
5079 /* Update operand types and check extended states. */
5080 for (j
= 0; j
< i
.operands
; j
++)
5082 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5083 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5088 i
.xstate
|= xstate_mmx
;
5091 i
.xstate
|= xstate_mask
;
5094 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5095 i
.xstate
|= xstate_tmm
;
5096 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
5097 i
.xstate
|= xstate_zmm
;
5098 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
5099 i
.xstate
|= xstate_ymm
;
5100 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5101 i
.xstate
|= xstate_xmm
;
5106 /* Make still unresolved immediate matches conform to size of immediate
5107 given in i.suffix. */
5108 if (!finalize_imm ())
5111 if (i
.types
[0].bitfield
.imm1
)
5112 i
.imm_operands
= 0; /* kludge for shift insns. */
5114 /* We only need to check those implicit registers for instructions
5115 with 3 operands or less. */
5116 if (i
.operands
<= 3)
5117 for (j
= 0; j
< i
.operands
; j
++)
5118 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
5119 && !i
.types
[j
].bitfield
.xmmword
)
5122 /* For insns with operands there are more diddles to do to the opcode. */
5125 if (!process_operands ())
5128 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5130 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5131 as_warn (_("translating to `%sp'"), i
.tm
.name
);
5134 if (is_any_vex_encoding (&i
.tm
))
5136 if (!cpu_arch_flags
.bitfield
.cpui286
)
5138 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5143 /* Check for explicit REX prefix. */
5144 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5146 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
5150 if (i
.tm
.opcode_modifier
.vex
)
5151 build_vex_prefix (t
);
5153 build_evex_prefix ();
5155 /* The individual REX.RXBW bits got consumed. */
5156 i
.rex
&= REX_OPCODE
;
5159 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
5160 instructions may define INT_OPCODE as well, so avoid this corner
5161 case for those instructions that use MODRM. */
5162 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
5163 && i
.tm
.base_opcode
== INT_OPCODE
5164 && !i
.tm
.opcode_modifier
.modrm
5165 && i
.op
[0].imms
->X_add_number
== 3)
5167 i
.tm
.base_opcode
= INT3_OPCODE
;
5171 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5172 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5173 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5174 && i
.op
[0].disps
->X_op
== O_constant
)
5176 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5177 the absolute address given by the constant. Since ix86 jumps and
5178 calls are pc relative, we need to generate a reloc. */
5179 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5180 i
.op
[0].disps
->X_op
= O_symbol
;
5183 /* For 8 bit registers we need an empty rex prefix. Also if the
5184 instruction already has a prefix, we need to convert old
5185 registers to new ones. */
5187 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5188 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5189 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5190 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5191 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5192 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5197 i
.rex
|= REX_OPCODE
;
5198 for (x
= 0; x
< 2; x
++)
5200 /* Look for 8 bit operand that uses old registers. */
5201 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5202 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5204 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5205 /* In case it is "hi" register, give up. */
5206 if (i
.op
[x
].regs
->reg_num
> 3)
5207 as_bad (_("can't encode register '%s%s' in an "
5208 "instruction requiring REX prefix."),
5209 register_prefix
, i
.op
[x
].regs
->reg_name
);
5211 /* Otherwise it is equivalent to the extended register.
5212 Since the encoding doesn't change this is merely
5213 cosmetic cleanup for debug output. */
5215 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5220 if (i
.rex
== 0 && i
.rex_encoding
)
5222 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5223 that uses legacy register. If it is "hi" register, don't add
5224 the REX_OPCODE byte. */
5226 for (x
= 0; x
< 2; x
++)
5227 if (i
.types
[x
].bitfield
.class == Reg
5228 && i
.types
[x
].bitfield
.byte
5229 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5230 && i
.op
[x
].regs
->reg_num
> 3)
5232 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5233 i
.rex_encoding
= false;
5242 add_prefix (REX_OPCODE
| i
.rex
);
5244 insert_lfence_before ();
5246 /* We are ready to output the insn. */
5249 insert_lfence_after ();
5251 last_insn
.seg
= now_seg
;
5253 if (i
.tm
.opcode_modifier
.isprefix
)
5255 last_insn
.kind
= last_insn_prefix
;
5256 last_insn
.name
= i
.tm
.name
;
5257 last_insn
.file
= as_where (&last_insn
.line
);
5260 last_insn
.kind
= last_insn_other
;
5264 parse_insn (char *line
, char *mnemonic
)
5267 char *token_start
= l
;
5270 const insn_template
*t
;
5276 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5281 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5283 as_bad (_("no such instruction: `%s'"), token_start
);
5288 if (!is_space_char (*l
)
5289 && *l
!= END_OF_INSN
5291 || (*l
!= PREFIX_SEPARATOR
5294 as_bad (_("invalid character %s in mnemonic"),
5295 output_invalid (*l
));
5298 if (token_start
== l
)
5300 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5301 as_bad (_("expecting prefix; got nothing"));
5303 as_bad (_("expecting mnemonic; got nothing"));
5307 /* Look up instruction (or prefix) via hash table. */
5308 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5310 if (*l
!= END_OF_INSN
5311 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5312 && current_templates
5313 && current_templates
->start
->opcode_modifier
.isprefix
)
5315 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5317 as_bad ((flag_code
!= CODE_64BIT
5318 ? _("`%s' is only supported in 64-bit mode")
5319 : _("`%s' is not supported in 64-bit mode")),
5320 current_templates
->start
->name
);
5323 /* If we are in 16-bit mode, do not allow addr16 or data16.
5324 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5325 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5326 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5327 && flag_code
!= CODE_64BIT
5328 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5329 ^ (flag_code
== CODE_16BIT
)))
5331 as_bad (_("redundant %s prefix"),
5332 current_templates
->start
->name
);
5336 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5338 /* Handle pseudo prefixes. */
5339 switch (current_templates
->start
->extension_opcode
)
5343 i
.disp_encoding
= disp_encoding_8bit
;
5347 i
.disp_encoding
= disp_encoding_16bit
;
5351 i
.disp_encoding
= disp_encoding_32bit
;
5355 i
.dir_encoding
= dir_encoding_load
;
5359 i
.dir_encoding
= dir_encoding_store
;
5363 i
.vec_encoding
= vex_encoding_vex
;
5367 i
.vec_encoding
= vex_encoding_vex3
;
5371 i
.vec_encoding
= vex_encoding_evex
;
5375 i
.rex_encoding
= true;
5377 case Prefix_NoOptimize
:
5379 i
.no_optimize
= true;
5387 /* Add prefix, checking for repeated prefixes. */
5388 switch (add_prefix (current_templates
->start
->base_opcode
))
5393 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5394 i
.notrack_prefix
= current_templates
->start
->name
;
5397 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5398 i
.hle_prefix
= current_templates
->start
->name
;
5399 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5400 i
.bnd_prefix
= current_templates
->start
->name
;
5402 i
.rep_prefix
= current_templates
->start
->name
;
5408 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5415 if (!current_templates
)
5417 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5418 Check if we should swap operand or force 32bit displacement in
5420 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5421 i
.dir_encoding
= dir_encoding_swap
;
5422 else if (mnem_p
- 3 == dot_p
5425 i
.disp_encoding
= disp_encoding_8bit
;
5426 else if (mnem_p
- 4 == dot_p
5430 i
.disp_encoding
= disp_encoding_32bit
;
5435 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5438 if (!current_templates
)
5441 if (mnem_p
> mnemonic
)
5443 /* See if we can get a match by trimming off a suffix. */
5446 case WORD_MNEM_SUFFIX
:
5447 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5448 i
.suffix
= SHORT_MNEM_SUFFIX
;
5451 case BYTE_MNEM_SUFFIX
:
5452 case QWORD_MNEM_SUFFIX
:
5453 i
.suffix
= mnem_p
[-1];
5456 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5458 case SHORT_MNEM_SUFFIX
:
5459 case LONG_MNEM_SUFFIX
:
5462 i
.suffix
= mnem_p
[-1];
5465 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5473 if (intel_float_operand (mnemonic
) == 1)
5474 i
.suffix
= SHORT_MNEM_SUFFIX
;
5476 i
.suffix
= LONG_MNEM_SUFFIX
;
5479 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5485 if (!current_templates
)
5487 as_bad (_("no such instruction: `%s'"), token_start
);
5492 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5493 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5495 /* Check for a branch hint. We allow ",pt" and ",pn" for
5496 predict taken and predict not taken respectively.
5497 I'm not sure that branch hints actually do anything on loop
5498 and jcxz insns (JumpByte) for current Pentium4 chips. They
5499 may work in the future and it doesn't hurt to accept them
5501 if (l
[0] == ',' && l
[1] == 'p')
5505 if (!add_prefix (DS_PREFIX_OPCODE
))
5509 else if (l
[2] == 'n')
5511 if (!add_prefix (CS_PREFIX_OPCODE
))
5517 /* Any other comma loses. */
5520 as_bad (_("invalid character %s in mnemonic"),
5521 output_invalid (*l
));
5525 /* Check if instruction is supported on specified architecture. */
5527 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5529 supported
|= cpu_flags_match (t
);
5530 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5534 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5535 as_bad (flag_code
== CODE_64BIT
5536 ? _("`%s' is not supported in 64-bit mode")
5537 : _("`%s' is only supported in 64-bit mode"),
5538 current_templates
->start
->name
);
5540 as_bad (_("`%s' is not supported on `%s%s'"),
5541 current_templates
->start
->name
,
5542 cpu_arch_name
? cpu_arch_name
: default_arch
,
5543 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5549 parse_operands (char *l
, const char *mnemonic
)
5553 /* 1 if operand is pending after ','. */
5554 unsigned int expecting_operand
= 0;
5556 while (*l
!= END_OF_INSN
)
5558 /* Non-zero if operand parens not balanced. */
5559 unsigned int paren_not_balanced
= 0;
5560 /* True if inside double quotes. */
5561 bool in_quotes
= false;
5563 /* Skip optional white space before operand. */
5564 if (is_space_char (*l
))
5566 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5568 as_bad (_("invalid character %s before operand %d"),
5569 output_invalid (*l
),
5573 token_start
= l
; /* After white space. */
5574 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
5576 if (*l
== END_OF_INSN
)
5580 as_bad (_("unbalanced double quotes in operand %d."),
5584 if (paren_not_balanced
)
5586 know (!intel_syntax
);
5587 as_bad (_("unbalanced parenthesis in operand %d."),
5592 break; /* we are done */
5594 else if (*l
== '\\' && l
[1] == '"')
5597 in_quotes
= !in_quotes
;
5598 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
5600 as_bad (_("invalid character %s in operand %d"),
5601 output_invalid (*l
),
5605 if (!intel_syntax
&& !in_quotes
)
5608 ++paren_not_balanced
;
5610 --paren_not_balanced
;
5614 if (l
!= token_start
)
5615 { /* Yes, we've read in another operand. */
5616 unsigned int operand_ok
;
5617 this_operand
= i
.operands
++;
5618 if (i
.operands
> MAX_OPERANDS
)
5620 as_bad (_("spurious operands; (%d operands/instruction max)"),
5624 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5625 /* Now parse operand adding info to 'i' as we go along. */
5626 END_STRING_AND_SAVE (l
);
5628 if (i
.mem_operands
> 1)
5630 as_bad (_("too many memory references for `%s'"),
5637 i386_intel_operand (token_start
,
5638 intel_float_operand (mnemonic
));
5640 operand_ok
= i386_att_operand (token_start
);
5642 RESTORE_END_STRING (l
);
5648 if (expecting_operand
)
5650 expecting_operand_after_comma
:
5651 as_bad (_("expecting operand after ','; got nothing"));
5656 as_bad (_("expecting operand before ','; got nothing"));
5661 /* Now *l must be either ',' or END_OF_INSN. */
5664 if (*++l
== END_OF_INSN
)
5666 /* Just skip it, if it's \n complain. */
5667 goto expecting_operand_after_comma
;
5669 expecting_operand
= 1;
5676 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
5678 union i386_op temp_op
;
5679 i386_operand_type temp_type
;
5680 unsigned int temp_flags
;
5681 enum bfd_reloc_code_real temp_reloc
;
5683 temp_type
= i
.types
[xchg2
];
5684 i
.types
[xchg2
] = i
.types
[xchg1
];
5685 i
.types
[xchg1
] = temp_type
;
5687 temp_flags
= i
.flags
[xchg2
];
5688 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5689 i
.flags
[xchg1
] = temp_flags
;
5691 temp_op
= i
.op
[xchg2
];
5692 i
.op
[xchg2
] = i
.op
[xchg1
];
5693 i
.op
[xchg1
] = temp_op
;
5695 temp_reloc
= i
.reloc
[xchg2
];
5696 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5697 i
.reloc
[xchg1
] = temp_reloc
;
5701 if (i
.mask
.operand
== xchg1
)
5702 i
.mask
.operand
= xchg2
;
5703 else if (i
.mask
.operand
== xchg2
)
5704 i
.mask
.operand
= xchg1
;
5706 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
5708 if (i
.broadcast
.operand
== xchg1
)
5709 i
.broadcast
.operand
= xchg2
;
5710 else if (i
.broadcast
.operand
== xchg2
)
5711 i
.broadcast
.operand
= xchg1
;
5716 swap_operands (void)
5722 swap_2_operands (1, i
.operands
- 2);
5726 swap_2_operands (0, i
.operands
- 1);
5732 if (i
.mem_operands
== 2)
5734 const reg_entry
*temp_seg
;
5735 temp_seg
= i
.seg
[0];
5736 i
.seg
[0] = i
.seg
[1];
5737 i
.seg
[1] = temp_seg
;
5741 /* Try to ensure constant immediates are represented in the smallest
5746 char guess_suffix
= 0;
5750 guess_suffix
= i
.suffix
;
5751 else if (i
.reg_operands
)
5753 /* Figure out a suffix from the last register operand specified.
5754 We can't do this properly yet, i.e. excluding special register
5755 instances, but the following works for instructions with
5756 immediates. In any case, we can't set i.suffix yet. */
5757 for (op
= i
.operands
; --op
>= 0;)
5758 if (i
.types
[op
].bitfield
.class != Reg
)
5760 else if (i
.types
[op
].bitfield
.byte
)
5762 guess_suffix
= BYTE_MNEM_SUFFIX
;
5765 else if (i
.types
[op
].bitfield
.word
)
5767 guess_suffix
= WORD_MNEM_SUFFIX
;
5770 else if (i
.types
[op
].bitfield
.dword
)
5772 guess_suffix
= LONG_MNEM_SUFFIX
;
5775 else if (i
.types
[op
].bitfield
.qword
)
5777 guess_suffix
= QWORD_MNEM_SUFFIX
;
5781 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5782 guess_suffix
= WORD_MNEM_SUFFIX
;
5784 for (op
= i
.operands
; --op
>= 0;)
5785 if (operand_type_check (i
.types
[op
], imm
))
5787 switch (i
.op
[op
].imms
->X_op
)
5790 /* If a suffix is given, this operand may be shortened. */
5791 switch (guess_suffix
)
5793 case LONG_MNEM_SUFFIX
:
5794 i
.types
[op
].bitfield
.imm32
= 1;
5795 i
.types
[op
].bitfield
.imm64
= 1;
5797 case WORD_MNEM_SUFFIX
:
5798 i
.types
[op
].bitfield
.imm16
= 1;
5799 i
.types
[op
].bitfield
.imm32
= 1;
5800 i
.types
[op
].bitfield
.imm32s
= 1;
5801 i
.types
[op
].bitfield
.imm64
= 1;
5803 case BYTE_MNEM_SUFFIX
:
5804 i
.types
[op
].bitfield
.imm8
= 1;
5805 i
.types
[op
].bitfield
.imm8s
= 1;
5806 i
.types
[op
].bitfield
.imm16
= 1;
5807 i
.types
[op
].bitfield
.imm32
= 1;
5808 i
.types
[op
].bitfield
.imm32s
= 1;
5809 i
.types
[op
].bitfield
.imm64
= 1;
5813 /* If this operand is at most 16 bits, convert it
5814 to a signed 16 bit number before trying to see
5815 whether it will fit in an even smaller size.
5816 This allows a 16-bit operand such as $0xffe0 to
5817 be recognised as within Imm8S range. */
5818 if ((i
.types
[op
].bitfield
.imm16
)
5819 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
5821 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5822 ^ 0x8000) - 0x8000);
5825 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5826 if ((i
.types
[op
].bitfield
.imm32
)
5827 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
5829 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5830 ^ ((offsetT
) 1 << 31))
5831 - ((offsetT
) 1 << 31));
5835 = operand_type_or (i
.types
[op
],
5836 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5838 /* We must avoid matching of Imm32 templates when 64bit
5839 only immediate is available. */
5840 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5841 i
.types
[op
].bitfield
.imm32
= 0;
5848 /* Symbols and expressions. */
5850 /* Convert symbolic operand to proper sizes for matching, but don't
5851 prevent matching a set of insns that only supports sizes other
5852 than those matching the insn suffix. */
5854 i386_operand_type mask
, allowed
;
5855 const insn_template
*t
= current_templates
->start
;
5857 operand_type_set (&mask
, 0);
5858 switch (guess_suffix
)
5860 case QWORD_MNEM_SUFFIX
:
5861 mask
.bitfield
.imm64
= 1;
5862 mask
.bitfield
.imm32s
= 1;
5864 case LONG_MNEM_SUFFIX
:
5865 mask
.bitfield
.imm32
= 1;
5867 case WORD_MNEM_SUFFIX
:
5868 mask
.bitfield
.imm16
= 1;
5870 case BYTE_MNEM_SUFFIX
:
5871 mask
.bitfield
.imm8
= 1;
5877 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
5878 while (++t
< current_templates
->end
)
5880 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5881 allowed
= operand_type_and (allowed
, mask
);
5884 if (!operand_type_all_zero (&allowed
))
5885 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5892 /* Try to use the smallest displacement type too. */
5894 optimize_disp (void)
5898 for (op
= i
.operands
; --op
>= 0;)
5899 if (operand_type_check (i
.types
[op
], disp
))
5901 if (i
.op
[op
].disps
->X_op
== O_constant
)
5903 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5905 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5907 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
5908 i
.op
[op
].disps
= NULL
;
5913 if (i
.types
[op
].bitfield
.disp16
5914 && fits_in_unsigned_word (op_disp
))
5916 /* If this operand is at most 16 bits, convert
5917 to a signed 16 bit number and don't use 64bit
5919 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
5920 i
.types
[op
].bitfield
.disp64
= 0;
5924 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5925 if ((flag_code
!= CODE_64BIT
5926 ? i
.types
[op
].bitfield
.disp32
5927 : want_disp32 (current_templates
->start
)
5928 && (!current_templates
->start
->opcode_modifier
.jump
5929 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
5930 && fits_in_unsigned_long (op_disp
))
5932 /* If this operand is at most 32 bits, convert
5933 to a signed 32 bit number and don't use 64bit
5935 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5936 i
.types
[op
].bitfield
.disp64
= 0;
5937 i
.types
[op
].bitfield
.disp32
= 1;
5940 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
5942 i
.types
[op
].bitfield
.disp64
= 0;
5943 i
.types
[op
].bitfield
.disp32
= 1;
5946 if ((i
.types
[op
].bitfield
.disp32
5947 || i
.types
[op
].bitfield
.disp16
)
5948 && fits_in_disp8 (op_disp
))
5949 i
.types
[op
].bitfield
.disp8
= 1;
5951 i
.op
[op
].disps
->X_add_number
= op_disp
;
5953 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5954 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5956 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5957 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5958 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
5961 /* We only support 64bit displacement on constants. */
5962 i
.types
[op
].bitfield
.disp64
= 0;
5966 /* Return 1 if there is a match in broadcast bytes between operand
5967 GIVEN and instruction template T. */
5970 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5972 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5973 && i
.types
[given
].bitfield
.byte
)
5974 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5975 && i
.types
[given
].bitfield
.word
)
5976 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5977 && i
.types
[given
].bitfield
.dword
)
5978 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5979 && i
.types
[given
].bitfield
.qword
));
5982 /* Check if operands are valid for the instruction. */
5985 check_VecOperands (const insn_template
*t
)
5990 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5991 any one operand are implicity requiring AVX512VL support if the actual
5992 operand size is YMMword or XMMword. Since this function runs after
5993 template matching, there's no need to check for YMMword/XMMword in
5995 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5996 if (!cpu_flags_all_zero (&cpu
)
5997 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5998 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6000 for (op
= 0; op
< t
->operands
; ++op
)
6002 if (t
->operand_types
[op
].bitfield
.zmmword
6003 && (i
.types
[op
].bitfield
.ymmword
6004 || i
.types
[op
].bitfield
.xmmword
))
6006 i
.error
= unsupported
;
6012 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6013 requiring AVX2 support if the actual operand size is YMMword. */
6014 if (t
->cpu_flags
.bitfield
.cpuavx
6015 && t
->cpu_flags
.bitfield
.cpuavx2
6016 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6018 for (op
= 0; op
< t
->operands
; ++op
)
6020 if (t
->operand_types
[op
].bitfield
.xmmword
6021 && i
.types
[op
].bitfield
.ymmword
)
6023 i
.error
= unsupported
;
6029 /* Without VSIB byte, we can't have a vector register for index. */
6030 if (!t
->opcode_modifier
.sib
6032 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6033 || i
.index_reg
->reg_type
.bitfield
.ymmword
6034 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6036 i
.error
= unsupported_vector_index_register
;
6040 /* Check if default mask is allowed. */
6041 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6042 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6044 i
.error
= no_default_mask
;
6048 /* For VSIB byte, we need a vector register for index, and all vector
6049 registers must be distinct. */
6050 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6053 || !((t
->opcode_modifier
.sib
== VECSIB128
6054 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6055 || (t
->opcode_modifier
.sib
== VECSIB256
6056 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6057 || (t
->opcode_modifier
.sib
== VECSIB512
6058 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6060 i
.error
= invalid_vsib_address
;
6064 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6065 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6067 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6068 gas_assert (i
.types
[0].bitfield
.xmmword
6069 || i
.types
[0].bitfield
.ymmword
);
6070 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6071 gas_assert (i
.types
[2].bitfield
.xmmword
6072 || i
.types
[2].bitfield
.ymmword
);
6073 if (operand_check
== check_none
)
6075 if (register_number (i
.op
[0].regs
)
6076 != register_number (i
.index_reg
)
6077 && register_number (i
.op
[2].regs
)
6078 != register_number (i
.index_reg
)
6079 && register_number (i
.op
[0].regs
)
6080 != register_number (i
.op
[2].regs
))
6082 if (operand_check
== check_error
)
6084 i
.error
= invalid_vector_register_set
;
6087 as_warn (_("mask, index, and destination registers should be distinct"));
6089 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6091 if (i
.types
[1].bitfield
.class == RegSIMD
6092 && (i
.types
[1].bitfield
.xmmword
6093 || i
.types
[1].bitfield
.ymmword
6094 || i
.types
[1].bitfield
.zmmword
)
6095 && (register_number (i
.op
[1].regs
)
6096 == register_number (i
.index_reg
)))
6098 if (operand_check
== check_error
)
6100 i
.error
= invalid_vector_register_set
;
6103 if (operand_check
!= check_none
)
6104 as_warn (_("index and destination registers should be distinct"));
6109 /* For AMX instructions with 3 TMM register operands, all operands
6110 must be distinct. */
6111 if (i
.reg_operands
== 3
6112 && t
->operand_types
[0].bitfield
.tmmword
6113 && (i
.op
[0].regs
== i
.op
[1].regs
6114 || i
.op
[0].regs
== i
.op
[2].regs
6115 || i
.op
[1].regs
== i
.op
[2].regs
))
6117 i
.error
= invalid_tmm_register_set
;
6121 /* For some special instructions require that destination must be distinct
6122 from source registers. */
6123 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6125 unsigned int dest_reg
= i
.operands
- 1;
6127 know (i
.operands
>= 3);
6129 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6130 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6131 || (i
.reg_operands
> 2
6132 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6134 i
.error
= invalid_dest_and_src_register_set
;
6139 /* Check if broadcast is supported by the instruction and is applied
6140 to the memory operand. */
6141 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6143 i386_operand_type type
, overlap
;
6145 /* Check if specified broadcast is supported in this instruction,
6146 and its broadcast bytes match the memory operand. */
6147 op
= i
.broadcast
.operand
;
6148 if (!t
->opcode_modifier
.broadcast
6149 || !(i
.flags
[op
] & Operand_Mem
)
6150 || (!i
.types
[op
].bitfield
.unspecified
6151 && !match_broadcast_size (t
, op
)))
6154 i
.error
= unsupported_broadcast
;
6158 if (i
.broadcast
.type
)
6159 i
.broadcast
.bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
6160 * i
.broadcast
.type
);
6161 operand_type_set (&type
, 0);
6162 switch (get_broadcast_bytes (t
, false))
6165 type
.bitfield
.word
= 1;
6168 type
.bitfield
.dword
= 1;
6171 type
.bitfield
.qword
= 1;
6174 type
.bitfield
.xmmword
= 1;
6177 type
.bitfield
.ymmword
= 1;
6180 type
.bitfield
.zmmword
= 1;
6186 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6187 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6188 && t
->operand_types
[op
].bitfield
.byte
6189 + t
->operand_types
[op
].bitfield
.word
6190 + t
->operand_types
[op
].bitfield
.dword
6191 + t
->operand_types
[op
].bitfield
.qword
> 1)
6193 overlap
.bitfield
.xmmword
= 0;
6194 overlap
.bitfield
.ymmword
= 0;
6195 overlap
.bitfield
.zmmword
= 0;
6197 if (operand_type_all_zero (&overlap
))
6200 if (t
->opcode_modifier
.checkregsize
)
6204 type
.bitfield
.baseindex
= 1;
6205 for (j
= 0; j
< i
.operands
; ++j
)
6208 && !operand_type_register_match(i
.types
[j
],
6209 t
->operand_types
[j
],
6211 t
->operand_types
[op
]))
6216 /* If broadcast is supported in this instruction, we need to check if
6217 operand of one-element size isn't specified without broadcast. */
6218 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6220 /* Find memory operand. */
6221 for (op
= 0; op
< i
.operands
; op
++)
6222 if (i
.flags
[op
] & Operand_Mem
)
6224 gas_assert (op
< i
.operands
);
6225 /* Check size of the memory operand. */
6226 if (match_broadcast_size (t
, op
))
6228 i
.error
= broadcast_needed
;
6233 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6235 /* Check if requested masking is supported. */
6238 switch (t
->opcode_modifier
.masking
)
6242 case MERGING_MASKING
:
6246 i
.error
= unsupported_masking
;
6250 case DYNAMIC_MASKING
:
6251 /* Memory destinations allow only merging masking. */
6252 if (i
.mask
.zeroing
&& i
.mem_operands
)
6254 /* Find memory operand. */
6255 for (op
= 0; op
< i
.operands
; op
++)
6256 if (i
.flags
[op
] & Operand_Mem
)
6258 gas_assert (op
< i
.operands
);
6259 if (op
== i
.operands
- 1)
6261 i
.error
= unsupported_masking
;
6271 /* Check if masking is applied to dest operand. */
6272 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6274 i
.error
= mask_not_on_destination
;
6279 if (i
.rounding
.type
!= rc_none
)
6281 if (!t
->opcode_modifier
.sae
6282 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6285 i
.error
= unsupported_rc_sae
;
6289 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6291 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6293 for (op
= 0; op
< t
->operands
; ++op
)
6294 if (i
.types
[op
].bitfield
.zmmword
)
6296 if (op
>= t
->operands
)
6298 i
.error
= operand_size_mismatch
;
6304 /* Check the special Imm4 cases; must be the first operand. */
6305 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6307 if (i
.op
[0].imms
->X_op
!= O_constant
6308 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6314 /* Turn off Imm<N> so that update_imm won't complain. */
6315 operand_type_set (&i
.types
[0], 0);
6318 /* Check vector Disp8 operand. */
6319 if (t
->opcode_modifier
.disp8memshift
6320 && i
.disp_encoding
<= disp_encoding_8bit
)
6322 if (i
.broadcast
.bytes
)
6323 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6324 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6325 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6328 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6331 for (op
= 0; op
< i
.operands
; op
++)
6332 if (i
.flags
[op
] & Operand_Mem
)
6334 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6335 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6336 else if (t
->operand_types
[op
].bitfield
.xmmword
6337 + t
->operand_types
[op
].bitfield
.ymmword
6338 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6339 type
= &t
->operand_types
[op
];
6340 else if (!i
.types
[op
].bitfield
.unspecified
)
6341 type
= &i
.types
[op
];
6342 else /* Ambiguities get resolved elsewhere. */
6343 fallback
= &t
->operand_types
[op
];
6345 else if (i
.types
[op
].bitfield
.class == RegSIMD
6346 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6348 if (i
.types
[op
].bitfield
.zmmword
)
6350 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6352 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6356 if (!type
&& !i
.memshift
)
6360 if (type
->bitfield
.zmmword
)
6362 else if (type
->bitfield
.ymmword
)
6364 else if (type
->bitfield
.xmmword
)
6368 /* For the check in fits_in_disp8(). */
6369 if (i
.memshift
== 0)
6373 for (op
= 0; op
< i
.operands
; op
++)
6374 if (operand_type_check (i
.types
[op
], disp
)
6375 && i
.op
[op
].disps
->X_op
== O_constant
)
6377 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6379 i
.types
[op
].bitfield
.disp8
= 1;
6382 i
.types
[op
].bitfield
.disp8
= 0;
6391 /* Check if encoding requirements are met by the instruction. */
6394 VEX_check_encoding (const insn_template
*t
)
6396 if (i
.vec_encoding
== vex_encoding_error
)
6398 i
.error
= unsupported
;
6402 if (i
.vec_encoding
== vex_encoding_evex
)
6404 /* This instruction must be encoded with EVEX prefix. */
6405 if (!is_evex_encoding (t
))
6407 i
.error
= unsupported
;
6413 if (!t
->opcode_modifier
.vex
)
6415 /* This instruction template doesn't have VEX prefix. */
6416 if (i
.vec_encoding
!= vex_encoding_default
)
6418 i
.error
= unsupported
;
6427 /* Helper function for the progress() macro in match_template(). */
6428 static INLINE
enum i386_error
progress (enum i386_error
new,
6429 enum i386_error last
,
6430 unsigned int line
, unsigned int *line_p
)
6432 if (line
<= *line_p
)
6438 static const insn_template
*
6439 match_template (char mnem_suffix
)
6441 /* Points to template once we've found it. */
6442 const insn_template
*t
;
6443 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6444 i386_operand_type overlap4
;
6445 unsigned int found_reverse_match
;
6446 i386_operand_type operand_types
[MAX_OPERANDS
];
6447 int addr_prefix_disp
;
6448 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
6449 enum i386_error specific_error
= number_of_operands_mismatch
;
6450 #define progress(err) progress (err, specific_error, __LINE__, &errline)
6452 #if MAX_OPERANDS != 5
6453 # error "MAX_OPERANDS must be 5."
6456 found_reverse_match
= 0;
6457 addr_prefix_disp
= -1;
6459 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6461 addr_prefix_disp
= -1;
6462 found_reverse_match
= 0;
6464 /* Must have right number of operands. */
6465 if (i
.operands
!= t
->operands
)
6468 /* Check processor support. */
6469 specific_error
= progress (unsupported
);
6470 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6473 /* Check AT&T mnemonic. */
6474 specific_error
= progress (unsupported_with_intel_mnemonic
);
6475 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6478 /* Check AT&T/Intel syntax. */
6479 specific_error
= progress (unsupported_syntax
);
6480 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6481 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6484 /* Check Intel64/AMD64 ISA. */
6488 /* Default: Don't accept Intel64. */
6489 if (t
->opcode_modifier
.isa64
== INTEL64
)
6493 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6494 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6498 /* -mintel64: Don't accept AMD64. */
6499 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6504 /* Check the suffix. */
6505 specific_error
= progress (invalid_instruction_suffix
);
6506 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
6507 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
6508 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
6509 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
6510 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
6513 specific_error
= progress (operand_size_mismatch
);
6514 size_match
= operand_size_match (t
);
6518 /* This is intentionally not
6520 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6522 as the case of a missing * on the operand is accepted (perhaps with
6523 a warning, issued further down). */
6524 specific_error
= progress (operand_type_mismatch
);
6525 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6528 /* In Intel syntax, normally we can check for memory operand size when
6529 there is no mnemonic suffix. But jmp and call have 2 different
6530 encodings with Dword memory operand size. Skip the "near" one
6531 (permitting a register operand) when "far" was requested. */
6533 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
6534 && t
->operand_types
[0].bitfield
.class == Reg
)
6537 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6538 operand_types
[j
] = t
->operand_types
[j
];
6540 /* In general, don't allow
6541 - 64-bit operands outside of 64-bit mode,
6542 - 32-bit operands on pre-386. */
6543 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
6544 : operand_size_mismatch
);
6545 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6546 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6547 && flag_code
!= CODE_64BIT
6548 && !(t
->opcode_modifier
.opcodespace
== SPACE_0F
6549 && t
->base_opcode
== 0xc7
6550 && t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
6551 && t
->extension_opcode
== 1) /* cmpxchg8b */)
6552 || (i
.suffix
== LONG_MNEM_SUFFIX
6553 && !cpu_arch_flags
.bitfield
.cpui386
))
6555 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6556 && !intel_float_operand (t
->name
))
6557 : intel_float_operand (t
->name
) != 2)
6558 && (t
->operands
== i
.imm_operands
6559 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6560 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6561 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6562 || (operand_types
[j
].bitfield
.class != RegMMX
6563 && operand_types
[j
].bitfield
.class != RegSIMD
6564 && operand_types
[j
].bitfield
.class != RegMask
))
6565 && !t
->opcode_modifier
.sib
)
6568 /* Do not verify operands when there are none. */
6571 if (VEX_check_encoding (t
))
6573 specific_error
= progress (i
.error
);
6577 /* We've found a match; break out of loop. */
6581 if (!t
->opcode_modifier
.jump
6582 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6584 /* There should be only one Disp operand. */
6585 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6586 if (operand_type_check (operand_types
[j
], disp
))
6588 if (j
< MAX_OPERANDS
)
6590 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6592 addr_prefix_disp
= j
;
6594 /* Address size prefix will turn Disp64 operand into Disp32 and
6595 Disp32/Disp16 one into Disp16/Disp32 respectively. */
6599 override
= !override
;
6602 if (operand_types
[j
].bitfield
.disp32
6603 && operand_types
[j
].bitfield
.disp16
)
6605 operand_types
[j
].bitfield
.disp16
= override
;
6606 operand_types
[j
].bitfield
.disp32
= !override
;
6608 gas_assert (!operand_types
[j
].bitfield
.disp64
);
6612 if (operand_types
[j
].bitfield
.disp64
)
6614 gas_assert (!operand_types
[j
].bitfield
.disp32
);
6615 operand_types
[j
].bitfield
.disp32
= override
;
6616 operand_types
[j
].bitfield
.disp64
= !override
;
6618 operand_types
[j
].bitfield
.disp16
= 0;
6626 case BFD_RELOC_386_GOT32
:
6627 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6628 if (t
->base_opcode
== 0xa0
6629 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
)
6632 case BFD_RELOC_386_TLS_GOTIE
:
6633 case BFD_RELOC_386_TLS_LE_32
:
6634 case BFD_RELOC_X86_64_GOTTPOFF
:
6635 case BFD_RELOC_X86_64_TLSLD
:
6636 /* Don't allow KMOV in TLS code sequences. */
6637 if (t
->opcode_modifier
.vex
)
6644 /* We check register size if needed. */
6645 if (t
->opcode_modifier
.checkregsize
)
6647 check_register
= (1 << t
->operands
) - 1;
6648 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6649 check_register
&= ~(1 << i
.broadcast
.operand
);
6654 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6655 switch (t
->operands
)
6658 if (!operand_type_match (overlap0
, i
.types
[0]))
6662 /* xchg %eax, %eax is a special case. It is an alias for nop
6663 only in 32bit mode and we can use opcode 0x90. In 64bit
6664 mode, we can't use 0x90 for xchg %eax, %eax since it should
6665 zero-extend %eax to %rax. */
6666 if (flag_code
== CODE_64BIT
6667 && t
->base_opcode
== 0x90
6668 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6669 && i
.types
[0].bitfield
.instance
== Accum
6670 && i
.types
[0].bitfield
.dword
6671 && i
.types
[1].bitfield
.instance
== Accum
)
6673 /* xrelease mov %eax, <disp> is another special case. It must not
6674 match the accumulator-only encoding of mov. */
6675 if (flag_code
!= CODE_64BIT
6677 && t
->base_opcode
== 0xa0
6678 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6679 && i
.types
[0].bitfield
.instance
== Accum
6680 && (i
.flags
[1] & Operand_Mem
))
6685 if (!(size_match
& MATCH_STRAIGHT
))
6687 /* Reverse direction of operands if swapping is possible in the first
6688 place (operands need to be symmetric) and
6689 - the load form is requested, and the template is a store form,
6690 - the store form is requested, and the template is a load form,
6691 - the non-default (swapped) form is requested. */
6692 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6693 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6694 && !operand_type_all_zero (&overlap1
))
6695 switch (i
.dir_encoding
)
6697 case dir_encoding_load
:
6698 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6699 || t
->opcode_modifier
.regmem
)
6703 case dir_encoding_store
:
6704 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6705 && !t
->opcode_modifier
.regmem
)
6709 case dir_encoding_swap
:
6712 case dir_encoding_default
:
6715 /* If we want store form, we skip the current load. */
6716 if ((i
.dir_encoding
== dir_encoding_store
6717 || i
.dir_encoding
== dir_encoding_swap
)
6718 && i
.mem_operands
== 0
6719 && t
->opcode_modifier
.load
)
6724 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6725 if (!operand_type_match (overlap0
, i
.types
[0])
6726 || !operand_type_match (overlap1
, i
.types
[1])
6727 || ((check_register
& 3) == 3
6728 && !operand_type_register_match (i
.types
[0],
6733 specific_error
= progress (i
.error
);
6735 /* Check if other direction is valid ... */
6736 if (!t
->opcode_modifier
.d
)
6740 if (!(size_match
& MATCH_REVERSE
))
6742 /* Try reversing direction of operands. */
6743 j
= t
->opcode_modifier
.vexsources
? 1 : i
.operands
- 1;
6744 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
6745 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
6746 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
6747 gas_assert (t
->operands
!= 3 || !check_register
);
6748 if (!operand_type_match (overlap0
, i
.types
[0])
6749 || !operand_type_match (overlap1
, i
.types
[j
])
6750 || (t
->operands
== 3
6751 && !operand_type_match (overlap2
, i
.types
[1]))
6753 && !operand_type_register_match (i
.types
[0],
6758 /* Does not match either direction. */
6759 specific_error
= progress (i
.error
);
6762 /* found_reverse_match holds which variant of D
6764 if (!t
->opcode_modifier
.d
)
6765 found_reverse_match
= 0;
6766 else if (operand_types
[0].bitfield
.tbyte
)
6768 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
6769 found_reverse_match
= Opcode_FloatD
;
6770 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
6771 if ((t
->base_opcode
& 0x20)
6772 && (intel_syntax
|| intel_mnemonic
))
6773 found_reverse_match
|= Opcode_FloatR
;
6775 else if (t
->opcode_modifier
.vexsources
)
6777 found_reverse_match
= Opcode_VexW
;
6778 goto check_operands_345
;
6780 else if (t
->opcode_modifier
.opcodespace
!= SPACE_BASE
6781 && (t
->opcode_modifier
.opcodespace
!= SPACE_0F
6782 /* MOV to/from CR/DR/TR, as an exception, follow
6783 the base opcode space encoding model. */
6784 || (t
->base_opcode
| 7) != 0x27))
6785 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6786 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
6787 else if (!t
->opcode_modifier
.commutative
)
6788 found_reverse_match
= Opcode_D
;
6790 found_reverse_match
= ~0;
6794 /* Found a forward 2 operand match here. */
6796 switch (t
->operands
)
6799 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
6800 if (!operand_type_match (overlap4
, i
.types
[4])
6801 || !operand_type_register_match (i
.types
[3],
6806 specific_error
= progress (i
.error
);
6811 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
6812 if (!operand_type_match (overlap3
, i
.types
[3])
6813 || ((check_register
& 0xa) == 0xa
6814 && !operand_type_register_match (i
.types
[1],
6818 || ((check_register
& 0xc) == 0xc
6819 && !operand_type_register_match (i
.types
[2],
6824 specific_error
= progress (i
.error
);
6829 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
6830 if (!operand_type_match (overlap2
, i
.types
[2])
6831 || ((check_register
& 5) == 5
6832 && !operand_type_register_match (i
.types
[0],
6836 || ((check_register
& 6) == 6
6837 && !operand_type_register_match (i
.types
[1],
6842 specific_error
= progress (i
.error
);
6848 /* Found either forward/reverse 2, 3 or 4 operand match here:
6849 slip through to break. */
6852 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6853 if (VEX_check_encoding (t
))
6855 specific_error
= progress (i
.error
);
6859 /* Check if vector operands are valid. */
6860 if (check_VecOperands (t
))
6862 specific_error
= progress (i
.error
);
6866 /* We've found a match; break out of loop. */
6872 if (t
== current_templates
->end
)
6874 /* We found no match. */
6875 const char *err_msg
;
6876 switch (specific_error
)
6880 case operand_size_mismatch
:
6881 err_msg
= _("operand size mismatch");
6883 case operand_type_mismatch
:
6884 err_msg
= _("operand type mismatch");
6886 case register_type_mismatch
:
6887 err_msg
= _("register type mismatch");
6889 case number_of_operands_mismatch
:
6890 err_msg
= _("number of operands mismatch");
6892 case invalid_instruction_suffix
:
6893 err_msg
= _("invalid instruction suffix");
6896 err_msg
= _("constant doesn't fit in 4 bits");
6898 case unsupported_with_intel_mnemonic
:
6899 err_msg
= _("unsupported with Intel mnemonic");
6901 case unsupported_syntax
:
6902 err_msg
= _("unsupported syntax");
6905 as_bad (_("unsupported instruction `%s'"),
6906 current_templates
->start
->name
);
6908 case invalid_sib_address
:
6909 err_msg
= _("invalid SIB address");
6911 case invalid_vsib_address
:
6912 err_msg
= _("invalid VSIB address");
6914 case invalid_vector_register_set
:
6915 err_msg
= _("mask, index, and destination registers must be distinct");
6917 case invalid_tmm_register_set
:
6918 err_msg
= _("all tmm registers must be distinct");
6920 case invalid_dest_and_src_register_set
:
6921 err_msg
= _("destination and source registers must be distinct");
6923 case unsupported_vector_index_register
:
6924 err_msg
= _("unsupported vector index register");
6926 case unsupported_broadcast
:
6927 err_msg
= _("unsupported broadcast");
6929 case broadcast_needed
:
6930 err_msg
= _("broadcast is needed for operand of such type");
6932 case unsupported_masking
:
6933 err_msg
= _("unsupported masking");
6935 case mask_not_on_destination
:
6936 err_msg
= _("mask not on destination operand");
6938 case no_default_mask
:
6939 err_msg
= _("default mask isn't allowed");
6941 case unsupported_rc_sae
:
6942 err_msg
= _("unsupported static rounding/sae");
6944 case invalid_register_operand
:
6945 err_msg
= _("invalid register operand");
6948 as_bad (_("%s for `%s'"), err_msg
,
6949 current_templates
->start
->name
);
6953 if (!quiet_warnings
)
6956 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6957 as_warn (_("indirect %s without `*'"), t
->name
);
6959 if (t
->opcode_modifier
.isprefix
6960 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6962 /* Warn them that a data or address size prefix doesn't
6963 affect assembly of the next line of code. */
6964 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6968 /* Copy the template we found. */
6969 install_template (t
);
6971 if (addr_prefix_disp
!= -1)
6972 i
.tm
.operand_types
[addr_prefix_disp
]
6973 = operand_types
[addr_prefix_disp
];
6975 switch (found_reverse_match
)
6981 /* If we found a reverse match we must alter the opcode direction
6982 bit and clear/flip the regmem modifier one. found_reverse_match
6983 holds bits to change (different for int & float insns). */
6985 i
.tm
.base_opcode
^= found_reverse_match
;
6987 /* Certain SIMD insns have their load forms specified in the opcode
6988 table, and hence we need to _set_ RegMem instead of clearing it.
6989 We need to avoid setting the bit though on insns like KMOVW. */
6990 i
.tm
.opcode_modifier
.regmem
6991 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6992 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6993 && !i
.tm
.opcode_modifier
.regmem
;
6997 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6998 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7002 /* Only the first two register operands need reversing, alongside
7004 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7006 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7007 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7008 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7018 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7019 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7021 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7023 as_bad (_("`%s' operand %u must use `%ses' segment"),
7025 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7030 /* There's only ever one segment override allowed per instruction.
7031 This instruction possibly has a legal segment override on the
7032 second operand, so copy the segment to where non-string
7033 instructions store it, allowing common code. */
7034 i
.seg
[op
] = i
.seg
[1];
7040 process_suffix (void)
7042 bool is_crc32
= false, is_movx
= false;
7044 /* If matched instruction specifies an explicit instruction mnemonic
7046 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7047 i
.suffix
= WORD_MNEM_SUFFIX
;
7048 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7049 i
.suffix
= LONG_MNEM_SUFFIX
;
7050 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7051 i
.suffix
= QWORD_MNEM_SUFFIX
;
7052 else if (i
.reg_operands
7053 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7054 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7056 unsigned int numop
= i
.operands
;
7059 is_movx
= (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
7060 && (i
.tm
.base_opcode
| 8) == 0xbe)
7061 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7062 && i
.tm
.base_opcode
== 0x63
7063 && i
.tm
.cpu_flags
.bitfield
.cpu64
);
7066 is_crc32
= (i
.tm
.base_opcode
== 0xf0
7067 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
7068 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
);
7070 /* movsx/movzx want only their source operand considered here, for the
7071 ambiguity checking below. The suffix will be replaced afterwards
7072 to represent the destination (register). */
7073 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7076 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7077 if (is_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7080 /* If there's no instruction mnemonic suffix we try to invent one
7081 based on GPR operands. */
7084 /* We take i.suffix from the last register operand specified,
7085 Destination register type is more significant than source
7086 register type. crc32 in SSE4.2 prefers source register
7088 unsigned int op
= is_crc32
? 1 : i
.operands
;
7091 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7092 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7094 if (i
.types
[op
].bitfield
.class != Reg
)
7096 if (i
.types
[op
].bitfield
.byte
)
7097 i
.suffix
= BYTE_MNEM_SUFFIX
;
7098 else if (i
.types
[op
].bitfield
.word
)
7099 i
.suffix
= WORD_MNEM_SUFFIX
;
7100 else if (i
.types
[op
].bitfield
.dword
)
7101 i
.suffix
= LONG_MNEM_SUFFIX
;
7102 else if (i
.types
[op
].bitfield
.qword
)
7103 i
.suffix
= QWORD_MNEM_SUFFIX
;
7109 /* As an exception, movsx/movzx silently default to a byte source
7111 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7112 i
.suffix
= BYTE_MNEM_SUFFIX
;
7114 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7116 if (!check_byte_reg ())
7119 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7121 if (!check_long_reg ())
7124 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7126 if (!check_qword_reg ())
7129 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7131 if (!check_word_reg ())
7134 else if (intel_syntax
7135 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7136 /* Do nothing if the instruction is going to ignore the prefix. */
7141 /* Undo the movsx/movzx change done above. */
7144 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7147 i
.suffix
= stackop_size
;
7148 if (stackop_size
== LONG_MNEM_SUFFIX
)
7150 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7151 .code16gcc directive to support 16-bit mode with
7152 32-bit address. For IRET without a suffix, generate
7153 16-bit IRET (opcode 0xcf) to return from an interrupt
7155 if (i
.tm
.base_opcode
== 0xcf)
7157 i
.suffix
= WORD_MNEM_SUFFIX
;
7158 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7160 /* Warn about changed behavior for segment register push/pop. */
7161 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7162 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7167 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7168 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7169 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7170 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
7171 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7172 && i
.tm
.extension_opcode
<= 3)))
7177 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7179 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7180 || i
.tm
.opcode_modifier
.no_lsuf
)
7181 i
.suffix
= QWORD_MNEM_SUFFIX
;
7186 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7187 i
.suffix
= LONG_MNEM_SUFFIX
;
7190 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7191 i
.suffix
= WORD_MNEM_SUFFIX
;
7197 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7198 /* Also cover lret/retf/iret in 64-bit mode. */
7199 || (flag_code
== CODE_64BIT
7200 && !i
.tm
.opcode_modifier
.no_lsuf
7201 && !i
.tm
.opcode_modifier
.no_qsuf
))
7202 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7203 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7204 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7205 /* Accept FLDENV et al without suffix. */
7206 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7208 unsigned int suffixes
, evex
= 0;
7210 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7211 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7213 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7215 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7217 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7220 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7221 also suitable for AT&T syntax mode, it was requested that this be
7222 restricted to just Intel syntax. */
7223 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7224 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7228 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7230 if (is_evex_encoding (&i
.tm
)
7231 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7233 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7234 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7235 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7236 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7237 if (!i
.tm
.opcode_modifier
.evex
7238 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7239 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7242 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7243 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7244 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7247 /* Any properly sized operand disambiguates the insn. */
7248 if (i
.types
[op
].bitfield
.xmmword
7249 || i
.types
[op
].bitfield
.ymmword
7250 || i
.types
[op
].bitfield
.zmmword
)
7252 suffixes
&= ~(7 << 6);
7257 if ((i
.flags
[op
] & Operand_Mem
)
7258 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7260 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7262 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7264 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7266 if (is_evex_encoding (&i
.tm
))
7272 /* Are multiple suffixes / operand sizes allowed? */
7273 if (suffixes
& (suffixes
- 1))
7276 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7277 || operand_check
== check_error
))
7279 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
7282 if (operand_check
== check_error
)
7284 as_bad (_("no instruction mnemonic suffix given and "
7285 "no register operands; can't size `%s'"), i
.tm
.name
);
7288 if (operand_check
== check_warning
)
7289 as_warn (_("%s; using default for `%s'"),
7291 ? _("ambiguous operand size")
7292 : _("no instruction mnemonic suffix given and "
7293 "no register operands"),
7296 if (i
.tm
.opcode_modifier
.floatmf
)
7297 i
.suffix
= SHORT_MNEM_SUFFIX
;
7299 /* handled below */;
7301 i
.tm
.opcode_modifier
.evex
= evex
;
7302 else if (flag_code
== CODE_16BIT
)
7303 i
.suffix
= WORD_MNEM_SUFFIX
;
7304 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7305 i
.suffix
= LONG_MNEM_SUFFIX
;
7307 i
.suffix
= QWORD_MNEM_SUFFIX
;
7313 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7314 In AT&T syntax, if there is no suffix (warned about above), the default
7315 will be byte extension. */
7316 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7317 i
.tm
.base_opcode
|= 1;
7319 /* For further processing, the suffix should represent the destination
7320 (register). This is already the case when one was used with
7321 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7322 no suffix to begin with. */
7323 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7325 if (i
.types
[1].bitfield
.word
)
7326 i
.suffix
= WORD_MNEM_SUFFIX
;
7327 else if (i
.types
[1].bitfield
.qword
)
7328 i
.suffix
= QWORD_MNEM_SUFFIX
;
7330 i
.suffix
= LONG_MNEM_SUFFIX
;
7332 i
.tm
.opcode_modifier
.w
= 0;
7336 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7337 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7338 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7340 /* Change the opcode based on the operand size given by i.suffix. */
7343 /* Size floating point instruction. */
7344 case LONG_MNEM_SUFFIX
:
7345 if (i
.tm
.opcode_modifier
.floatmf
)
7347 i
.tm
.base_opcode
^= 4;
7351 case WORD_MNEM_SUFFIX
:
7352 case QWORD_MNEM_SUFFIX
:
7353 /* It's not a byte, select word/dword operation. */
7354 if (i
.tm
.opcode_modifier
.w
)
7357 i
.tm
.base_opcode
|= 8;
7359 i
.tm
.base_opcode
|= 1;
7362 case SHORT_MNEM_SUFFIX
:
7363 /* Now select between word & dword operations via the operand
7364 size prefix, except for instructions that will ignore this
7366 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7367 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7368 && !i
.tm
.opcode_modifier
.floatmf
7369 && !is_any_vex_encoding (&i
.tm
)
7370 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7371 || (flag_code
== CODE_64BIT
7372 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7374 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7376 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7377 prefix
= ADDR_PREFIX_OPCODE
;
7379 if (!add_prefix (prefix
))
7383 /* Set mode64 for an operand. */
7384 if (i
.suffix
== QWORD_MNEM_SUFFIX
7385 && flag_code
== CODE_64BIT
7386 && !i
.tm
.opcode_modifier
.norex64
7387 && !i
.tm
.opcode_modifier
.vexw
7388 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7390 && ! (i
.operands
== 2
7391 && i
.tm
.base_opcode
== 0x90
7392 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7393 && i
.types
[0].bitfield
.instance
== Accum
7394 && i
.types
[0].bitfield
.qword
7395 && i
.types
[1].bitfield
.instance
== Accum
))
7401 /* Select word/dword/qword operation with explicit data sizing prefix
7402 when there are no suitable register operands. */
7403 if (i
.tm
.opcode_modifier
.w
7404 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7406 || (i
.reg_operands
== 1
7408 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7410 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7411 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7414 i
.tm
.base_opcode
|= 1;
7418 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7420 gas_assert (!i
.suffix
);
7421 gas_assert (i
.reg_operands
);
7423 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7426 /* The address size override prefix changes the size of the
7428 if (flag_code
== CODE_64BIT
7429 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7431 as_bad (_("16-bit addressing unavailable for `%s'"),
7436 if ((flag_code
== CODE_32BIT
7437 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7438 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7439 && !add_prefix (ADDR_PREFIX_OPCODE
))
7444 /* Check invalid register operand when the address size override
7445 prefix changes the size of register operands. */
7447 enum { need_word
, need_dword
, need_qword
} need
;
7449 /* Check the register operand for the address size prefix if
7450 the memory operand has no real registers, like symbol, DISP
7451 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7452 if (i
.mem_operands
== 1
7453 && i
.reg_operands
== 1
7455 && i
.types
[1].bitfield
.class == Reg
7456 && (flag_code
== CODE_32BIT
7457 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7458 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7459 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7460 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7461 || (x86_elf_abi
== X86_64_X32_ABI
7463 && i
.base_reg
->reg_num
== RegIP
7464 && i
.base_reg
->reg_type
.bitfield
.qword
))
7468 && !add_prefix (ADDR_PREFIX_OPCODE
))
7471 if (flag_code
== CODE_32BIT
)
7472 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7473 else if (i
.prefix
[ADDR_PREFIX
])
7476 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7478 for (op
= 0; op
< i
.operands
; op
++)
7480 if (i
.types
[op
].bitfield
.class != Reg
)
7486 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7490 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7494 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7499 as_bad (_("invalid register operand size for `%s'"),
7510 check_byte_reg (void)
7514 for (op
= i
.operands
; --op
>= 0;)
7516 /* Skip non-register operands. */
7517 if (i
.types
[op
].bitfield
.class != Reg
)
7520 /* If this is an eight bit register, it's OK. If it's the 16 or
7521 32 bit version of an eight bit register, we will just use the
7522 low portion, and that's OK too. */
7523 if (i
.types
[op
].bitfield
.byte
)
7526 /* I/O port address operands are OK too. */
7527 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7528 && i
.tm
.operand_types
[op
].bitfield
.word
)
7531 /* crc32 only wants its source operand checked here. */
7532 if (i
.tm
.base_opcode
== 0xf0
7533 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
7534 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
7538 /* Any other register is bad. */
7539 as_bad (_("`%s%s' not allowed with `%s%c'"),
7540 register_prefix
, i
.op
[op
].regs
->reg_name
,
7541 i
.tm
.name
, i
.suffix
);
7548 check_long_reg (void)
7552 for (op
= i
.operands
; --op
>= 0;)
7553 /* Skip non-register operands. */
7554 if (i
.types
[op
].bitfield
.class != Reg
)
7556 /* Reject eight bit registers, except where the template requires
7557 them. (eg. movzb) */
7558 else if (i
.types
[op
].bitfield
.byte
7559 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7560 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7561 && (i
.tm
.operand_types
[op
].bitfield
.word
7562 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7564 as_bad (_("`%s%s' not allowed with `%s%c'"),
7566 i
.op
[op
].regs
->reg_name
,
7571 /* Error if the e prefix on a general reg is missing. */
7572 else if (i
.types
[op
].bitfield
.word
7573 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7574 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7575 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7577 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7578 register_prefix
, i
.op
[op
].regs
->reg_name
,
7582 /* Warn if the r prefix on a general reg is present. */
7583 else if (i
.types
[op
].bitfield
.qword
7584 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7585 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7586 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7588 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7589 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
7596 check_qword_reg (void)
7600 for (op
= i
.operands
; --op
>= 0; )
7601 /* Skip non-register operands. */
7602 if (i
.types
[op
].bitfield
.class != Reg
)
7604 /* Reject eight bit registers, except where the template requires
7605 them. (eg. movzb) */
7606 else if (i
.types
[op
].bitfield
.byte
7607 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7608 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7609 && (i
.tm
.operand_types
[op
].bitfield
.word
7610 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7612 as_bad (_("`%s%s' not allowed with `%s%c'"),
7614 i
.op
[op
].regs
->reg_name
,
7619 /* Warn if the r prefix on a general reg is missing. */
7620 else if ((i
.types
[op
].bitfield
.word
7621 || i
.types
[op
].bitfield
.dword
)
7622 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7623 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7624 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7626 /* Prohibit these changes in the 64bit mode, since the
7627 lowering is more complicated. */
7628 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7629 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
7636 check_word_reg (void)
7639 for (op
= i
.operands
; --op
>= 0;)
7640 /* Skip non-register operands. */
7641 if (i
.types
[op
].bitfield
.class != Reg
)
7643 /* Reject eight bit registers, except where the template requires
7644 them. (eg. movzb) */
7645 else if (i
.types
[op
].bitfield
.byte
7646 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7647 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7648 && (i
.tm
.operand_types
[op
].bitfield
.word
7649 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7651 as_bad (_("`%s%s' not allowed with `%s%c'"),
7653 i
.op
[op
].regs
->reg_name
,
7658 /* Error if the e or r prefix on a general reg is present. */
7659 else if ((i
.types
[op
].bitfield
.dword
7660 || i
.types
[op
].bitfield
.qword
)
7661 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7662 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7663 && i
.tm
.operand_types
[op
].bitfield
.word
)
7665 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7666 register_prefix
, i
.op
[op
].regs
->reg_name
,
7674 update_imm (unsigned int j
)
7676 i386_operand_type overlap
= i
.types
[j
];
7677 if (overlap
.bitfield
.imm8
7678 + overlap
.bitfield
.imm8s
7679 + overlap
.bitfield
.imm16
7680 + overlap
.bitfield
.imm32
7681 + overlap
.bitfield
.imm32s
7682 + overlap
.bitfield
.imm64
> 1)
7684 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
7685 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
7686 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
7687 static const i386_operand_type imm16_32
= { .bitfield
=
7688 { .imm16
= 1, .imm32
= 1 }
7690 static const i386_operand_type imm16_32s
= { .bitfield
=
7691 { .imm16
= 1, .imm32s
= 1 }
7693 static const i386_operand_type imm16_32_32s
= { .bitfield
=
7694 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
7699 i386_operand_type temp
;
7701 operand_type_set (&temp
, 0);
7702 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7704 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7705 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7707 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7708 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7709 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7711 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7712 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7715 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7718 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7719 || operand_type_equal (&overlap
, &imm16_32
)
7720 || operand_type_equal (&overlap
, &imm16_32s
))
7722 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7727 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7728 overlap
= operand_type_and (overlap
, imm32s
);
7729 else if (i
.prefix
[DATA_PREFIX
])
7730 overlap
= operand_type_and (overlap
,
7731 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7732 if (overlap
.bitfield
.imm8
7733 + overlap
.bitfield
.imm8s
7734 + overlap
.bitfield
.imm16
7735 + overlap
.bitfield
.imm32
7736 + overlap
.bitfield
.imm32s
7737 + overlap
.bitfield
.imm64
!= 1)
7739 as_bad (_("no instruction mnemonic suffix given; "
7740 "can't determine immediate size"));
7744 i
.types
[j
] = overlap
;
7754 /* Update the first 2 immediate operands. */
7755 n
= i
.operands
> 2 ? 2 : i
.operands
;
7758 for (j
= 0; j
< n
; j
++)
7759 if (update_imm (j
) == 0)
7762 /* The 3rd operand can't be immediate operand. */
7763 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7770 process_operands (void)
7772 /* Default segment register this instruction will use for memory
7773 accesses. 0 means unknown. This is only for optimizing out
7774 unnecessary segment overrides. */
7775 const reg_entry
*default_seg
= NULL
;
7777 if (i
.tm
.opcode_modifier
.sse2avx
)
7779 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7781 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7782 i
.prefix
[REX_PREFIX
] = 0;
7785 /* ImmExt should be processed after SSE2AVX. */
7786 else if (i
.tm
.opcode_modifier
.immext
)
7789 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7791 static const i386_operand_type regxmm
= {
7792 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
7794 unsigned int dupl
= i
.operands
;
7795 unsigned int dest
= dupl
- 1;
7798 /* The destination must be an xmm register. */
7799 gas_assert (i
.reg_operands
7800 && MAX_OPERANDS
> dupl
7801 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7803 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7804 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7806 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7808 /* Keep xmm0 for instructions with VEX prefix and 3
7810 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7811 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7816 /* We remove the first xmm0 and keep the number of
7817 operands unchanged, which in fact duplicates the
7819 for (j
= 1; j
< i
.operands
; j
++)
7821 i
.op
[j
- 1] = i
.op
[j
];
7822 i
.types
[j
- 1] = i
.types
[j
];
7823 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7824 i
.flags
[j
- 1] = i
.flags
[j
];
7828 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
7830 gas_assert ((MAX_OPERANDS
- 1) > dupl
7831 && (i
.tm
.opcode_modifier
.vexsources
7834 /* Add the implicit xmm0 for instructions with VEX prefix
7836 for (j
= i
.operands
; j
> 0; j
--)
7838 i
.op
[j
] = i
.op
[j
- 1];
7839 i
.types
[j
] = i
.types
[j
- 1];
7840 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7841 i
.flags
[j
] = i
.flags
[j
- 1];
7844 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7845 i
.types
[0] = regxmm
;
7846 i
.tm
.operand_types
[0] = regxmm
;
7849 i
.reg_operands
+= 2;
7854 i
.op
[dupl
] = i
.op
[dest
];
7855 i
.types
[dupl
] = i
.types
[dest
];
7856 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7857 i
.flags
[dupl
] = i
.flags
[dest
];
7866 i
.op
[dupl
] = i
.op
[dest
];
7867 i
.types
[dupl
] = i
.types
[dest
];
7868 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7869 i
.flags
[dupl
] = i
.flags
[dest
];
7872 if (i
.tm
.opcode_modifier
.immext
)
7875 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7876 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7880 for (j
= 1; j
< i
.operands
; j
++)
7882 i
.op
[j
- 1] = i
.op
[j
];
7883 i
.types
[j
- 1] = i
.types
[j
];
7885 /* We need to adjust fields in i.tm since they are used by
7886 build_modrm_byte. */
7887 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7889 i
.flags
[j
- 1] = i
.flags
[j
];
7896 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
7898 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7900 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7901 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7902 regnum
= register_number (i
.op
[1].regs
);
7903 first_reg_in_group
= regnum
& ~3;
7904 last_reg_in_group
= first_reg_in_group
+ 3;
7905 if (regnum
!= first_reg_in_group
)
7906 as_warn (_("source register `%s%s' implicitly denotes"
7907 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7908 register_prefix
, i
.op
[1].regs
->reg_name
,
7909 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7910 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7913 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
7915 /* The imul $imm, %reg instruction is converted into
7916 imul $imm, %reg, %reg, and the clr %reg instruction
7917 is converted into xor %reg, %reg. */
7919 unsigned int first_reg_op
;
7921 if (operand_type_check (i
.types
[0], reg
))
7925 /* Pretend we saw the extra register operand. */
7926 gas_assert (i
.reg_operands
== 1
7927 && i
.op
[first_reg_op
+ 1].regs
== 0);
7928 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7929 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7934 if (i
.tm
.opcode_modifier
.modrm
)
7936 /* The opcode is completed (modulo i.tm.extension_opcode which
7937 must be put into the modrm byte). Now, we make the modrm and
7938 index base bytes based on all the info we've collected. */
7940 default_seg
= build_modrm_byte ();
7942 else if (i
.types
[0].bitfield
.class == SReg
)
7944 if (flag_code
!= CODE_64BIT
7945 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7946 && i
.op
[0].regs
->reg_num
== 1
7947 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
7948 && i
.op
[0].regs
->reg_num
< 4)
7950 as_bad (_("you can't `%s %s%s'"),
7951 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7954 if (i
.op
[0].regs
->reg_num
> 3
7955 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
7957 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
7958 i
.tm
.opcode_modifier
.opcodespace
= SPACE_0F
;
7960 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7962 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7963 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
7965 default_seg
= reg_ds
;
7967 else if (i
.tm
.opcode_modifier
.isstring
)
7969 /* For the string instructions that allow a segment override
7970 on one of their operands, the default segment is ds. */
7971 default_seg
= reg_ds
;
7973 else if (i
.short_form
)
7975 /* The register or float register operand is in operand
7977 const reg_entry
*r
= i
.op
[0].regs
;
7980 || (r
->reg_type
.bitfield
.instance
== Accum
&& i
.op
[1].regs
))
7982 /* Register goes in low 3 bits of opcode. */
7983 i
.tm
.base_opcode
|= r
->reg_num
;
7984 if ((r
->reg_flags
& RegRex
) != 0)
7986 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
7988 /* Warn about some common errors, but press on regardless. */
7989 if (i
.operands
!= 2)
7991 /* Extraneous `l' suffix on fp insn. */
7992 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7993 register_prefix
, i
.op
[0].regs
->reg_name
);
7995 else if (i
.op
[0].regs
->reg_type
.bitfield
.instance
!= Accum
)
7997 /* Reversed arguments on faddp or fmulp. */
7998 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7999 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8000 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8005 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8006 && i
.tm
.base_opcode
== 0x8d /* lea */
8007 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
8008 && !is_any_vex_encoding(&i
.tm
))
8010 if (!quiet_warnings
)
8011 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
8015 i
.prefix
[SEG_PREFIX
] = 0;
8019 /* If a segment was explicitly specified, and the specified segment
8020 is neither the default nor the one already recorded from a prefix,
8021 use an opcode prefix to select it. If we never figured out what
8022 the default segment is, then default_seg will be zero at this
8023 point, and the specified segment prefix will always be used. */
8025 && i
.seg
[0] != default_seg
8026 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8028 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8034 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8037 if (r
->reg_flags
& RegRex
)
8039 if (i
.rex
& rex_bit
)
8040 as_bad (_("same type of prefix used twice"));
8043 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8045 gas_assert (i
.vex
.register_specifier
== r
);
8046 i
.vex
.register_specifier
+= 8;
8049 if (r
->reg_flags
& RegVRex
)
8053 static const reg_entry
*
8054 build_modrm_byte (void)
8056 const reg_entry
*default_seg
= NULL
;
8057 unsigned int source
, dest
;
8060 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
8063 unsigned int nds
, reg_slot
;
8066 dest
= i
.operands
- 1;
8069 /* There are 2 kinds of instructions:
8070 1. 5 operands: 4 register operands or 3 register operands
8071 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8072 VexW0 or VexW1. The destination must be either XMM, YMM or
8074 2. 4 operands: 4 register operands or 3 register operands
8075 plus 1 memory operand, with VexXDS. */
8076 gas_assert ((i
.reg_operands
== 4
8077 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
8078 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8079 && i
.tm
.opcode_modifier
.vexw
8080 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8082 /* If VexW1 is set, the first non-immediate operand is the source and
8083 the second non-immediate one is encoded in the immediate operand. */
8084 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
8086 source
= i
.imm_operands
;
8087 reg_slot
= i
.imm_operands
+ 1;
8091 source
= i
.imm_operands
+ 1;
8092 reg_slot
= i
.imm_operands
;
8095 if (i
.imm_operands
== 0)
8097 /* When there is no immediate operand, generate an 8bit
8098 immediate operand to encode the first operand. */
8099 exp
= &im_expressions
[i
.imm_operands
++];
8100 i
.op
[i
.operands
].imms
= exp
;
8101 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8104 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8105 exp
->X_op
= O_constant
;
8106 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
8107 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
8111 gas_assert (i
.imm_operands
== 1);
8112 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8113 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8115 /* Turn on Imm8 again so that output_imm will generate it. */
8116 i
.types
[0].bitfield
.imm8
= 1;
8118 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8119 i
.op
[0].imms
->X_add_number
8120 |= register_number (i
.op
[reg_slot
].regs
) << 4;
8121 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
8124 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
8125 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
8130 /* i.reg_operands MUST be the number of real register operands;
8131 implicit registers do not count. If there are 3 register
8132 operands, it must be a instruction with VexNDS. For a
8133 instruction with VexNDD, the destination register is encoded
8134 in VEX prefix. If there are 4 register operands, it must be
8135 a instruction with VEX prefix and 3 sources. */
8136 if (i
.mem_operands
== 0
8137 && ((i
.reg_operands
== 2
8138 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
8139 || (i
.reg_operands
== 3
8140 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8141 || (i
.reg_operands
== 4 && vex_3_sources
)))
8149 /* When there are 3 operands, one of them may be immediate,
8150 which may be the first or the last operand. Otherwise,
8151 the first operand must be shift count register (cl) or it
8152 is an instruction with VexNDS. */
8153 gas_assert (i
.imm_operands
== 1
8154 || (i
.imm_operands
== 0
8155 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8156 || (i
.types
[0].bitfield
.instance
== RegC
8157 && i
.types
[0].bitfield
.byte
))));
8158 if (operand_type_check (i
.types
[0], imm
)
8159 || (i
.types
[0].bitfield
.instance
== RegC
8160 && i
.types
[0].bitfield
.byte
))
8166 /* When there are 4 operands, the first two must be 8bit
8167 immediate operands. The source operand will be the 3rd
8170 For instructions with VexNDS, if the first operand
8171 an imm8, the source operand is the 2nd one. If the last
8172 operand is imm8, the source operand is the first one. */
8173 gas_assert ((i
.imm_operands
== 2
8174 && i
.types
[0].bitfield
.imm8
8175 && i
.types
[1].bitfield
.imm8
)
8176 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8177 && i
.imm_operands
== 1
8178 && (i
.types
[0].bitfield
.imm8
8179 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
8180 if (i
.imm_operands
== 2)
8184 if (i
.types
[0].bitfield
.imm8
)
8191 gas_assert (!is_evex_encoding (&i
.tm
));
8192 gas_assert (i
.imm_operands
== 1 && vex_3_sources
);
8202 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8204 /* For instructions with VexNDS, the register-only source
8205 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
8206 register. It is encoded in VEX prefix. */
8208 i386_operand_type op
;
8211 /* Swap two source operands if needed. */
8212 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
)
8220 op
= i
.tm
.operand_types
[vvvv
];
8221 if ((dest
+ 1) >= i
.operands
8222 || ((op
.bitfield
.class != Reg
8223 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
8224 && op
.bitfield
.class != RegSIMD
8225 && op
.bitfield
.class != RegMask
))
8227 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
8233 /* One of the register operands will be encoded in the i.rm.reg
8234 field, the other in the combined i.rm.mode and i.rm.regmem
8235 fields. If no form of this instruction supports a memory
8236 destination operand, then we assume the source operand may
8237 sometimes be a memory operand and so we need to store the
8238 destination in the i.rm.reg field. */
8239 if (!i
.tm
.opcode_modifier
.regmem
8240 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
8242 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8243 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8244 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8245 set_rex_vrex (i
.op
[source
].regs
, REX_B
, false);
8249 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8250 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8251 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8252 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
8254 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8256 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8259 add_prefix (LOCK_PREFIX_OPCODE
);
8263 { /* If it's not 2 reg operands... */
8268 unsigned int fake_zero_displacement
= 0;
8271 for (op
= 0; op
< i
.operands
; op
++)
8272 if (i
.flags
[op
] & Operand_Mem
)
8274 gas_assert (op
< i
.operands
);
8276 if (i
.tm
.opcode_modifier
.sib
)
8278 /* The index register of VSIB shouldn't be RegIZ. */
8279 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8280 && i
.index_reg
->reg_num
== RegIZ
)
8283 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8286 i
.sib
.base
= NO_BASE_REGISTER
;
8287 i
.sib
.scale
= i
.log2_scale_factor
;
8288 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8289 i
.types
[op
].bitfield
.disp32
= 1;
8292 /* Since the mandatory SIB always has index register, so
8293 the code logic remains unchanged. The non-mandatory SIB
8294 without index register is allowed and will be handled
8298 if (i
.index_reg
->reg_num
== RegIZ
)
8299 i
.sib
.index
= NO_INDEX_REGISTER
;
8301 i
.sib
.index
= i
.index_reg
->reg_num
;
8302 set_rex_vrex (i
.index_reg
, REX_X
, false);
8306 default_seg
= reg_ds
;
8308 if (i
.base_reg
== 0)
8311 if (!i
.disp_operands
)
8312 fake_zero_displacement
= 1;
8313 if (i
.index_reg
== 0)
8315 /* Both check for VSIB and mandatory non-vector SIB. */
8316 gas_assert (!i
.tm
.opcode_modifier
.sib
8317 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8318 /* Operand is just <disp> */
8319 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8320 if (flag_code
== CODE_64BIT
)
8322 /* 64bit mode overwrites the 32bit absolute
8323 addressing by RIP relative addressing and
8324 absolute addressing is encoded by one of the
8325 redundant SIB forms. */
8326 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8327 i
.sib
.base
= NO_BASE_REGISTER
;
8328 i
.sib
.index
= NO_INDEX_REGISTER
;
8329 i
.types
[op
].bitfield
.disp32
= 1;
8331 else if ((flag_code
== CODE_16BIT
)
8332 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8334 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8335 i
.types
[op
].bitfield
.disp16
= 1;
8339 i
.rm
.regmem
= NO_BASE_REGISTER
;
8340 i
.types
[op
].bitfield
.disp32
= 1;
8343 else if (!i
.tm
.opcode_modifier
.sib
)
8345 /* !i.base_reg && i.index_reg */
8346 if (i
.index_reg
->reg_num
== RegIZ
)
8347 i
.sib
.index
= NO_INDEX_REGISTER
;
8349 i
.sib
.index
= i
.index_reg
->reg_num
;
8350 i
.sib
.base
= NO_BASE_REGISTER
;
8351 i
.sib
.scale
= i
.log2_scale_factor
;
8352 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8353 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8354 i
.types
[op
].bitfield
.disp32
= 1;
8355 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8359 /* RIP addressing for 64bit mode. */
8360 else if (i
.base_reg
->reg_num
== RegIP
)
8362 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8363 i
.rm
.regmem
= NO_BASE_REGISTER
;
8364 i
.types
[op
].bitfield
.disp8
= 0;
8365 i
.types
[op
].bitfield
.disp16
= 0;
8366 i
.types
[op
].bitfield
.disp32
= 1;
8367 i
.types
[op
].bitfield
.disp64
= 0;
8368 i
.flags
[op
] |= Operand_PCrel
;
8369 if (! i
.disp_operands
)
8370 fake_zero_displacement
= 1;
8372 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8374 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8375 switch (i
.base_reg
->reg_num
)
8378 if (i
.index_reg
== 0)
8380 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8381 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8384 default_seg
= reg_ss
;
8385 if (i
.index_reg
== 0)
8388 if (operand_type_check (i
.types
[op
], disp
) == 0)
8390 /* fake (%bp) into 0(%bp) */
8391 if (i
.disp_encoding
== disp_encoding_16bit
)
8392 i
.types
[op
].bitfield
.disp16
= 1;
8394 i
.types
[op
].bitfield
.disp8
= 1;
8395 fake_zero_displacement
= 1;
8398 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8399 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8401 default: /* (%si) -> 4 or (%di) -> 5 */
8402 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8404 if (!fake_zero_displacement
8408 fake_zero_displacement
= 1;
8409 if (i
.disp_encoding
== disp_encoding_8bit
)
8410 i
.types
[op
].bitfield
.disp8
= 1;
8412 i
.types
[op
].bitfield
.disp16
= 1;
8414 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8416 else /* i.base_reg and 32/64 bit mode */
8418 if (operand_type_check (i
.types
[op
], disp
))
8420 i
.types
[op
].bitfield
.disp16
= 0;
8421 i
.types
[op
].bitfield
.disp64
= 0;
8422 i
.types
[op
].bitfield
.disp32
= 1;
8425 if (!i
.tm
.opcode_modifier
.sib
)
8426 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8427 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8429 i
.sib
.base
= i
.base_reg
->reg_num
;
8430 /* x86-64 ignores REX prefix bit here to avoid decoder
8432 if (!(i
.base_reg
->reg_flags
& RegRex
)
8433 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8434 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8435 default_seg
= reg_ss
;
8436 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8438 fake_zero_displacement
= 1;
8439 if (i
.disp_encoding
== disp_encoding_32bit
)
8440 i
.types
[op
].bitfield
.disp32
= 1;
8442 i
.types
[op
].bitfield
.disp8
= 1;
8444 i
.sib
.scale
= i
.log2_scale_factor
;
8445 if (i
.index_reg
== 0)
8447 /* Only check for VSIB. */
8448 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8449 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8450 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8452 /* <disp>(%esp) becomes two byte modrm with no index
8453 register. We've already stored the code for esp
8454 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8455 Any base register besides %esp will not use the
8456 extra modrm byte. */
8457 i
.sib
.index
= NO_INDEX_REGISTER
;
8459 else if (!i
.tm
.opcode_modifier
.sib
)
8461 if (i
.index_reg
->reg_num
== RegIZ
)
8462 i
.sib
.index
= NO_INDEX_REGISTER
;
8464 i
.sib
.index
= i
.index_reg
->reg_num
;
8465 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8466 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8471 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8472 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8476 if (!fake_zero_displacement
8480 fake_zero_displacement
= 1;
8481 if (i
.disp_encoding
== disp_encoding_8bit
)
8482 i
.types
[op
].bitfield
.disp8
= 1;
8484 i
.types
[op
].bitfield
.disp32
= 1;
8486 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8490 if (fake_zero_displacement
)
8492 /* Fakes a zero displacement assuming that i.types[op]
8493 holds the correct displacement size. */
8496 gas_assert (i
.op
[op
].disps
== 0);
8497 exp
= &disp_expressions
[i
.disp_operands
++];
8498 i
.op
[op
].disps
= exp
;
8499 exp
->X_op
= O_constant
;
8500 exp
->X_add_number
= 0;
8501 exp
->X_add_symbol
= (symbolS
*) 0;
8502 exp
->X_op_symbol
= (symbolS
*) 0;
8510 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8512 if (operand_type_check (i
.types
[0], imm
))
8513 i
.vex
.register_specifier
= NULL
;
8516 /* VEX.vvvv encodes one of the sources when the first
8517 operand is not an immediate. */
8518 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8519 i
.vex
.register_specifier
= i
.op
[0].regs
;
8521 i
.vex
.register_specifier
= i
.op
[1].regs
;
8524 /* Destination is a XMM register encoded in the ModRM.reg
8526 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8527 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8530 /* ModRM.rm and VEX.B encodes the other source. */
8531 if (!i
.mem_operands
)
8535 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8536 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8538 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8540 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8544 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8546 i
.vex
.register_specifier
= i
.op
[2].regs
;
8547 if (!i
.mem_operands
)
8550 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8551 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8555 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8556 (if any) based on i.tm.extension_opcode. Again, we must be
8557 careful to make sure that segment/control/debug/test/MMX
8558 registers are coded into the i.rm.reg field. */
8559 else if (i
.reg_operands
)
8562 unsigned int vex_reg
= ~0;
8564 for (op
= 0; op
< i
.operands
; op
++)
8565 if (i
.types
[op
].bitfield
.class == Reg
8566 || i
.types
[op
].bitfield
.class == RegBND
8567 || i
.types
[op
].bitfield
.class == RegMask
8568 || i
.types
[op
].bitfield
.class == SReg
8569 || i
.types
[op
].bitfield
.class == RegCR
8570 || i
.types
[op
].bitfield
.class == RegDR
8571 || i
.types
[op
].bitfield
.class == RegTR
8572 || i
.types
[op
].bitfield
.class == RegSIMD
8573 || i
.types
[op
].bitfield
.class == RegMMX
)
8578 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8580 /* For instructions with VexNDS, the register-only
8581 source operand is encoded in VEX prefix. */
8582 gas_assert (mem
!= (unsigned int) ~0);
8584 if (op
> mem
|| i
.tm
.cpu_flags
.bitfield
.cpucmpccxadd
)
8587 gas_assert (op
< i
.operands
);
8591 /* Check register-only source operand when two source
8592 operands are swapped. */
8593 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8594 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8598 gas_assert (mem
== (vex_reg
+ 1)
8599 && op
< i
.operands
);
8604 gas_assert (vex_reg
< i
.operands
);
8608 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8610 /* For instructions with VexNDD, the register destination
8611 is encoded in VEX prefix. */
8612 if (i
.mem_operands
== 0)
8614 /* There is no memory operand. */
8615 gas_assert ((op
+ 2) == i
.operands
);
8620 /* There are only 2 non-immediate operands. */
8621 gas_assert (op
< i
.imm_operands
+ 2
8622 && i
.operands
== i
.imm_operands
+ 2);
8623 vex_reg
= i
.imm_operands
+ 1;
8627 gas_assert (op
< i
.operands
);
8629 if (vex_reg
!= (unsigned int) ~0)
8631 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8633 if ((type
->bitfield
.class != Reg
8634 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8635 && type
->bitfield
.class != RegSIMD
8636 && type
->bitfield
.class != RegMask
)
8639 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8642 /* Don't set OP operand twice. */
8645 /* If there is an extension opcode to put here, the
8646 register number must be put into the regmem field. */
8647 if (i
.tm
.extension_opcode
!= None
)
8649 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8650 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8651 i
.tm
.opcode_modifier
.sse2avx
);
8655 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8656 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8657 i
.tm
.opcode_modifier
.sse2avx
);
8661 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8662 must set it to 3 to indicate this is a register operand
8663 in the regmem field. */
8664 if (!i
.mem_operands
)
8668 /* Fill in i.rm.reg field with extension opcode (if any). */
8669 if (i
.tm
.extension_opcode
!= None
)
8670 i
.rm
.reg
= i
.tm
.extension_opcode
;
8676 frag_opcode_byte (unsigned char byte
)
8678 if (now_seg
!= absolute_section
)
8679 FRAG_APPEND_1_CHAR (byte
);
8681 ++abs_section_offset
;
8685 flip_code16 (unsigned int code16
)
8687 gas_assert (i
.tm
.operands
== 1);
8689 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8690 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8691 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8696 output_branch (void)
8702 relax_substateT subtype
;
8706 if (now_seg
== absolute_section
)
8708 as_bad (_("relaxable branches not supported in absolute section"));
8712 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8713 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
8716 if (i
.prefix
[DATA_PREFIX
] != 0)
8720 code16
^= flip_code16(code16
);
8722 /* Pentium4 branch hints. */
8723 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8724 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8729 if (i
.prefix
[REX_PREFIX
] != 0)
8735 /* BND prefixed jump. */
8736 if (i
.prefix
[BND_PREFIX
] != 0)
8742 if (i
.prefixes
!= 0)
8743 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8745 /* It's always a symbol; End frag & setup for relax.
8746 Make sure there is enough room in this frag for the largest
8747 instruction we may generate in md_convert_frag. This is 2
8748 bytes for the opcode and room for the prefix and largest
8750 frag_grow (prefix
+ 2 + 4);
8751 /* Prefix and 1 opcode byte go in fr_fix. */
8752 p
= frag_more (prefix
+ 1);
8753 if (i
.prefix
[DATA_PREFIX
] != 0)
8754 *p
++ = DATA_PREFIX_OPCODE
;
8755 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8756 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8757 *p
++ = i
.prefix
[SEG_PREFIX
];
8758 if (i
.prefix
[BND_PREFIX
] != 0)
8759 *p
++ = BND_PREFIX_OPCODE
;
8760 if (i
.prefix
[REX_PREFIX
] != 0)
8761 *p
++ = i
.prefix
[REX_PREFIX
];
8762 *p
= i
.tm
.base_opcode
;
8764 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8765 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8766 else if (cpu_arch_flags
.bitfield
.cpui386
)
8767 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8769 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8772 sym
= i
.op
[0].disps
->X_add_symbol
;
8773 off
= i
.op
[0].disps
->X_add_number
;
8775 if (i
.op
[0].disps
->X_op
!= O_constant
8776 && i
.op
[0].disps
->X_op
!= O_symbol
)
8778 /* Handle complex expressions. */
8779 sym
= make_expr_symbol (i
.op
[0].disps
);
8783 frag_now
->tc_frag_data
.code64
= flag_code
== CODE_64BIT
;
8785 /* 1 possible extra opcode + 4 byte displacement go in var part.
8786 Pass reloc in fr_var. */
8787 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8790 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8791 /* Return TRUE iff PLT32 relocation should be used for branching to
8795 need_plt32_p (symbolS
*s
)
8797 /* PLT32 relocation is ELF only. */
8802 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8803 krtld support it. */
8807 /* Since there is no need to prepare for PLT branch on x86-64, we
8808 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8809 be used as a marker for 32-bit PC-relative branches. */
8816 /* Weak or undefined symbol need PLT32 relocation. */
8817 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8820 /* Non-global symbol doesn't need PLT32 relocation. */
8821 if (! S_IS_EXTERNAL (s
))
8824 /* Other global symbols need PLT32 relocation. NB: Symbol with
8825 non-default visibilities are treated as normal global symbol
8826 so that PLT32 relocation can be used as a marker for 32-bit
8827 PC-relative branches. It is useful for linker relaxation. */
8838 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8840 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8842 /* This is a loop or jecxz type instruction. */
8844 if (i
.prefix
[ADDR_PREFIX
] != 0)
8846 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8849 /* Pentium4 branch hints. */
8850 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8851 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8853 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8862 if (flag_code
== CODE_16BIT
)
8865 if (i
.prefix
[DATA_PREFIX
] != 0)
8867 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8869 code16
^= flip_code16(code16
);
8877 /* BND prefixed jump. */
8878 if (i
.prefix
[BND_PREFIX
] != 0)
8880 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8884 if (i
.prefix
[REX_PREFIX
] != 0)
8886 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8890 if (i
.prefixes
!= 0)
8891 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8893 if (now_seg
== absolute_section
)
8895 abs_section_offset
+= i
.opcode_length
+ size
;
8899 p
= frag_more (i
.opcode_length
+ size
);
8900 switch (i
.opcode_length
)
8903 *p
++ = i
.tm
.base_opcode
>> 8;
8906 *p
++ = i
.tm
.base_opcode
;
8912 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8913 if (flag_code
== CODE_64BIT
&& size
== 4
8914 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
8915 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8916 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8919 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8921 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8922 i
.op
[0].disps
, 1, jump_reloc
);
8924 /* All jumps handled here are signed, but don't unconditionally use a
8925 signed limit check for 32 and 16 bit jumps as we want to allow wrap
8926 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
8931 fixP
->fx_signed
= 1;
8935 if (i
.tm
.base_opcode
== 0xc7f8)
8936 fixP
->fx_signed
= 1;
8940 if (flag_code
== CODE_64BIT
)
8941 fixP
->fx_signed
= 1;
8947 output_interseg_jump (void)
8955 if (flag_code
== CODE_16BIT
)
8959 if (i
.prefix
[DATA_PREFIX
] != 0)
8966 gas_assert (!i
.prefix
[REX_PREFIX
]);
8972 if (i
.prefixes
!= 0)
8973 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8975 if (now_seg
== absolute_section
)
8977 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8981 /* 1 opcode; 2 segment; offset */
8982 p
= frag_more (prefix
+ 1 + 2 + size
);
8984 if (i
.prefix
[DATA_PREFIX
] != 0)
8985 *p
++ = DATA_PREFIX_OPCODE
;
8987 if (i
.prefix
[REX_PREFIX
] != 0)
8988 *p
++ = i
.prefix
[REX_PREFIX
];
8990 *p
++ = i
.tm
.base_opcode
;
8991 if (i
.op
[1].imms
->X_op
== O_constant
)
8993 offsetT n
= i
.op
[1].imms
->X_add_number
;
8996 && !fits_in_unsigned_word (n
)
8997 && !fits_in_signed_word (n
))
8999 as_bad (_("16-bit jump out of range"));
9002 md_number_to_chars (p
, n
, size
);
9005 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9006 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9009 if (i
.op
[0].imms
->X_op
== O_constant
)
9010 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9012 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9013 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9016 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9021 asection
*seg
= now_seg
;
9022 subsegT subseg
= now_subseg
;
9024 unsigned int alignment
, align_size_1
;
9025 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9026 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9027 unsigned int padding
;
9029 if (!IS_ELF
|| !x86_used_note
)
9032 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9034 /* The .note.gnu.property section layout:
9036 Field Length Contents
9039 n_descsz 4 The note descriptor size
9040 n_type 4 NT_GNU_PROPERTY_TYPE_0
9042 n_desc n_descsz The program property array
9046 /* Create the .note.gnu.property section. */
9047 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9048 bfd_set_section_flags (sec
,
9055 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9066 bfd_set_section_alignment (sec
, alignment
);
9067 elf_section_type (sec
) = SHT_NOTE
;
9069 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9071 isa_1_descsz_raw
= 4 + 4 + 4;
9072 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9073 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9075 feature_2_descsz_raw
= isa_1_descsz
;
9076 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9078 feature_2_descsz_raw
+= 4 + 4 + 4;
9079 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9080 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9083 descsz
= feature_2_descsz
;
9084 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9085 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9087 /* Write n_namsz. */
9088 md_number_to_chars (p
, (valueT
) 4, 4);
9090 /* Write n_descsz. */
9091 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9094 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9097 memcpy (p
+ 4 * 3, "GNU", 4);
9099 /* Write 4-byte type. */
9100 md_number_to_chars (p
+ 4 * 4,
9101 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9103 /* Write 4-byte data size. */
9104 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9106 /* Write 4-byte data. */
9107 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9109 /* Zero out paddings. */
9110 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9112 memset (p
+ 4 * 7, 0, padding
);
9114 /* Write 4-byte type. */
9115 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9116 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9118 /* Write 4-byte data size. */
9119 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9121 /* Write 4-byte data. */
9122 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9123 (valueT
) x86_feature_2_used
, 4);
9125 /* Zero out paddings. */
9126 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9128 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9130 /* We probably can't restore the current segment, for there likely
9133 subseg_set (seg
, subseg
);
9137 x86_support_sframe_p (void)
9139 /* At this time, SFrame unwind is supported for AMD64 ABI only. */
9140 return (x86_elf_abi
== X86_64_ABI
);
9144 x86_sframe_ra_tracking_p (void)
9146 /* In AMD64, return address is always stored on the stack at a fixed offset
9147 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9148 Do not track explicitly via an SFrame Frame Row Entry. */
9153 x86_sframe_cfa_ra_offset (void)
9155 gas_assert (x86_elf_abi
== X86_64_ABI
);
9156 return (offsetT
) -8;
9160 x86_sframe_get_abi_arch (void)
9162 unsigned char sframe_abi_arch
= 0;
9164 if (x86_support_sframe_p ())
9166 gas_assert (!target_big_endian
);
9167 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9170 return sframe_abi_arch
;
9176 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9177 const char *frag_now_ptr
)
9179 unsigned int len
= 0;
9181 if (start_frag
!= frag_now
)
9183 const fragS
*fr
= start_frag
;
9188 } while (fr
&& fr
!= frag_now
);
9191 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9194 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9195 be macro-fused with conditional jumps.
9196 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9197 or is one of the following format:
9210 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9212 /* No RIP address. */
9213 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9216 /* No opcodes outside of base encoding space. */
9217 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9220 /* add, sub without add/sub m, imm. */
9221 if (i
.tm
.base_opcode
<= 5
9222 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9223 || ((i
.tm
.base_opcode
| 3) == 0x83
9224 && (i
.tm
.extension_opcode
== 0x5
9225 || i
.tm
.extension_opcode
== 0x0)))
9227 *mf_cmp_p
= mf_cmp_alu_cmp
;
9228 return !(i
.mem_operands
&& i
.imm_operands
);
9231 /* and without and m, imm. */
9232 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9233 || ((i
.tm
.base_opcode
| 3) == 0x83
9234 && i
.tm
.extension_opcode
== 0x4))
9236 *mf_cmp_p
= mf_cmp_test_and
;
9237 return !(i
.mem_operands
&& i
.imm_operands
);
9240 /* test without test m imm. */
9241 if ((i
.tm
.base_opcode
| 1) == 0x85
9242 || (i
.tm
.base_opcode
| 1) == 0xa9
9243 || ((i
.tm
.base_opcode
| 1) == 0xf7
9244 && i
.tm
.extension_opcode
== 0))
9246 *mf_cmp_p
= mf_cmp_test_and
;
9247 return !(i
.mem_operands
&& i
.imm_operands
);
9250 /* cmp without cmp m, imm. */
9251 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9252 || ((i
.tm
.base_opcode
| 3) == 0x83
9253 && (i
.tm
.extension_opcode
== 0x7)))
9255 *mf_cmp_p
= mf_cmp_alu_cmp
;
9256 return !(i
.mem_operands
&& i
.imm_operands
);
9259 /* inc, dec without inc/dec m. */
9260 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
9261 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9262 || ((i
.tm
.base_opcode
| 1) == 0xff
9263 && i
.tm
.extension_opcode
<= 0x1))
9265 *mf_cmp_p
= mf_cmp_incdec
;
9266 return !i
.mem_operands
;
9272 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9275 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9277 /* NB: Don't work with COND_JUMP86 without i386. */
9278 if (!align_branch_power
9279 || now_seg
== absolute_section
9280 || !cpu_arch_flags
.bitfield
.cpui386
9281 || !(align_branch
& align_branch_fused_bit
))
9284 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9286 if (last_insn
.kind
== last_insn_other
9287 || last_insn
.seg
!= now_seg
)
9290 as_warn_where (last_insn
.file
, last_insn
.line
,
9291 _("`%s` skips -malign-branch-boundary on `%s`"),
9292 last_insn
.name
, i
.tm
.name
);
9298 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9301 add_branch_prefix_frag_p (void)
9303 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9304 to PadLock instructions since they include prefixes in opcode. */
9305 if (!align_branch_power
9306 || !align_branch_prefix_size
9307 || now_seg
== absolute_section
9308 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9309 || !cpu_arch_flags
.bitfield
.cpui386
)
9312 /* Don't add prefix if it is a prefix or there is no operand in case
9313 that segment prefix is special. */
9314 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9317 if (last_insn
.kind
== last_insn_other
9318 || last_insn
.seg
!= now_seg
)
9322 as_warn_where (last_insn
.file
, last_insn
.line
,
9323 _("`%s` skips -malign-branch-boundary on `%s`"),
9324 last_insn
.name
, i
.tm
.name
);
9329 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9332 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9333 enum mf_jcc_kind
*mf_jcc_p
)
9337 /* NB: Don't work with COND_JUMP86 without i386. */
9338 if (!align_branch_power
9339 || now_seg
== absolute_section
9340 || !cpu_arch_flags
.bitfield
.cpui386
9341 || i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9346 /* Check for jcc and direct jmp. */
9347 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9349 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9351 *branch_p
= align_branch_jmp
;
9352 add_padding
= align_branch
& align_branch_jmp_bit
;
9356 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9357 igore the lowest bit. */
9358 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9359 *branch_p
= align_branch_jcc
;
9360 if ((align_branch
& align_branch_jcc_bit
))
9364 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9367 *branch_p
= align_branch_ret
;
9368 if ((align_branch
& align_branch_ret_bit
))
9373 /* Check for indirect jmp, direct and indirect calls. */
9374 if (i
.tm
.base_opcode
== 0xe8)
9377 *branch_p
= align_branch_call
;
9378 if ((align_branch
& align_branch_call_bit
))
9381 else if (i
.tm
.base_opcode
== 0xff
9382 && (i
.tm
.extension_opcode
== 2
9383 || i
.tm
.extension_opcode
== 4))
9385 /* Indirect call and jmp. */
9386 *branch_p
= align_branch_indirect
;
9387 if ((align_branch
& align_branch_indirect_bit
))
9394 && (i
.op
[0].disps
->X_op
== O_symbol
9395 || (i
.op
[0].disps
->X_op
== O_subtract
9396 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9398 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9399 /* No padding to call to global or undefined tls_get_addr. */
9400 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9401 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9407 && last_insn
.kind
!= last_insn_other
9408 && last_insn
.seg
== now_seg
)
9411 as_warn_where (last_insn
.file
, last_insn
.line
,
9412 _("`%s` skips -malign-branch-boundary on `%s`"),
9413 last_insn
.name
, i
.tm
.name
);
9423 fragS
*insn_start_frag
;
9424 offsetT insn_start_off
;
9425 fragS
*fragP
= NULL
;
9426 enum align_branch_kind branch
= align_branch_none
;
9427 /* The initializer is arbitrary just to avoid uninitialized error.
9428 it's actually either assigned in add_branch_padding_frag_p
9429 or never be used. */
9430 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9432 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9433 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9435 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9436 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9437 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9439 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9440 || i
.tm
.cpu_flags
.bitfield
.cpu287
9441 || i
.tm
.cpu_flags
.bitfield
.cpu387
9442 || i
.tm
.cpu_flags
.bitfield
.cpu687
9443 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9444 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9446 if ((i
.xstate
& xstate_mmx
)
9447 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
9448 && !is_any_vex_encoding (&i
.tm
)
9449 && (i
.tm
.base_opcode
== 0x77 /* emms */
9450 || i
.tm
.base_opcode
== 0x0e /* femms */)))
9451 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9455 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9456 i
.xstate
|= xstate_zmm
;
9457 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9458 i
.xstate
|= xstate_ymm
;
9459 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9460 i
.xstate
|= xstate_xmm
;
9463 /* vzeroall / vzeroupper */
9464 if (i
.tm
.base_opcode
== 0x77 && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9465 i
.xstate
|= xstate_ymm
;
9467 if ((i
.xstate
& xstate_xmm
)
9468 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9469 || (i
.tm
.base_opcode
== 0xae
9470 && (i
.tm
.cpu_flags
.bitfield
.cpusse
9471 || i
.tm
.cpu_flags
.bitfield
.cpuavx
))
9472 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9473 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9474 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9476 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9477 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9478 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9479 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9480 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9481 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9482 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9483 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9484 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9485 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9486 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9487 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9488 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9489 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9491 if (x86_feature_2_used
9492 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9493 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9494 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
9495 && i
.tm
.base_opcode
== 0xc7
9496 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
9497 && i
.tm
.extension_opcode
== 1) /* cmpxchg8b */)
9498 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9499 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9500 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9501 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9502 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9503 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9504 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9505 /* LAHF-SAHF insns in 64-bit mode. */
9506 || (flag_code
== CODE_64BIT
9507 && (i
.tm
.base_opcode
| 1) == 0x9f
9508 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
))
9509 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9510 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9511 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9512 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9513 XOP, FMA4, LPW, TBM, and AMX. */
9514 || (i
.tm
.opcode_modifier
.vex
9515 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9516 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9517 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9518 && !i
.tm
.cpu_flags
.bitfield
.cpuxop
9519 && !i
.tm
.cpu_flags
.bitfield
.cpufma4
9520 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9521 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9522 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9523 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9524 || i
.tm
.cpu_flags
.bitfield
.cpufma
9525 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9526 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9527 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9528 || (x86_feature_2_used
9529 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9530 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9531 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9532 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9533 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9534 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9535 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9536 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9537 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9538 AVX512-4FMAPS, and AVX512-4VNNIW. */
9539 || (i
.tm
.opcode_modifier
.evex
9540 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9541 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9542 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
9543 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9544 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9548 /* Tie dwarf2 debug info to the address at the start of the insn.
9549 We can't do this after the insn has been output as the current
9550 frag may have been closed off. eg. by frag_var. */
9551 dwarf2_emit_insn (0);
9553 insn_start_frag
= frag_now
;
9554 insn_start_off
= frag_now_fix ();
9556 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9559 /* Branch can be 8 bytes. Leave some room for prefixes. */
9560 unsigned int max_branch_padding_size
= 14;
9562 /* Align section to boundary. */
9563 record_alignment (now_seg
, align_branch_power
);
9565 /* Make room for padding. */
9566 frag_grow (max_branch_padding_size
);
9568 /* Start of the padding. */
9573 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9574 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9577 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9578 fragP
->tc_frag_data
.branch_type
= branch
;
9579 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9582 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9583 && !pre_386_16bit_warned
)
9585 as_warn (_("use .code16 to ensure correct addressing mode"));
9586 pre_386_16bit_warned
= true;
9590 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9592 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9593 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9595 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9596 output_interseg_jump ();
9599 /* Output normal instructions here. */
9603 enum mf_cmp_kind mf_cmp
;
9606 && (i
.tm
.base_opcode
== 0xaee8
9607 || i
.tm
.base_opcode
== 0xaef0
9608 || i
.tm
.base_opcode
== 0xaef8))
9610 /* Encode lfence, mfence, and sfence as
9611 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9612 if (flag_code
== CODE_16BIT
)
9613 as_bad (_("Cannot convert `%s' in 16-bit mode"), i
.tm
.name
);
9614 else if (omit_lock_prefix
)
9615 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9617 else if (now_seg
!= absolute_section
)
9619 offsetT val
= 0x240483f0ULL
;
9622 md_number_to_chars (p
, val
, 5);
9625 abs_section_offset
+= 5;
9629 /* Some processors fail on LOCK prefix. This options makes
9630 assembler ignore LOCK prefix and serves as a workaround. */
9631 if (omit_lock_prefix
)
9633 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9634 && i
.tm
.opcode_modifier
.isprefix
)
9636 i
.prefix
[LOCK_PREFIX
] = 0;
9640 /* Skip if this is a branch. */
9642 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9644 /* Make room for padding. */
9645 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9650 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9651 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9654 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9655 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9656 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9658 else if (add_branch_prefix_frag_p ())
9660 unsigned int max_prefix_size
= align_branch_prefix_size
;
9662 /* Make room for padding. */
9663 frag_grow (max_prefix_size
);
9668 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9669 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9672 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9675 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9676 don't need the explicit prefix. */
9677 if (!is_any_vex_encoding (&i
.tm
))
9679 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9688 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9689 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9693 switch (i
.opcode_length
)
9698 /* Check for pseudo prefixes. */
9699 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
9701 as_bad_where (insn_start_frag
->fr_file
,
9702 insn_start_frag
->fr_line
,
9703 _("pseudo prefix without instruction"));
9713 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9714 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9715 R_X86_64_GOTTPOFF relocation so that linker can safely
9716 perform IE->LE optimization. A dummy REX_OPCODE prefix
9717 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9718 relocation for GDesc -> IE/LE optimization. */
9719 if (x86_elf_abi
== X86_64_X32_ABI
9721 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9722 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9723 && i
.prefix
[REX_PREFIX
] == 0)
9724 add_prefix (REX_OPCODE
);
9727 /* The prefix bytes. */
9728 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9730 frag_opcode_byte (*q
);
9734 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9740 frag_opcode_byte (*q
);
9743 /* There should be no other prefixes for instructions
9748 /* For EVEX instructions i.vrex should become 0 after
9749 build_evex_prefix. For VEX instructions upper 16 registers
9750 aren't available, so VREX should be 0. */
9753 /* Now the VEX prefix. */
9754 if (now_seg
!= absolute_section
)
9756 p
= frag_more (i
.vex
.length
);
9757 for (j
= 0; j
< i
.vex
.length
; j
++)
9758 p
[j
] = i
.vex
.bytes
[j
];
9761 abs_section_offset
+= i
.vex
.length
;
9764 /* Now the opcode; be careful about word order here! */
9765 j
= i
.opcode_length
;
9767 switch (i
.tm
.opcode_modifier
.opcodespace
)
9782 if (now_seg
== absolute_section
)
9783 abs_section_offset
+= j
;
9786 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9792 && i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9795 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_0F
)
9796 *p
++ = i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
9800 switch (i
.opcode_length
)
9803 /* Put out high byte first: can't use md_number_to_chars! */
9804 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9807 *p
= i
.tm
.base_opcode
& 0xff;
9816 /* Now the modrm byte and sib byte (if present). */
9817 if (i
.tm
.opcode_modifier
.modrm
)
9819 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9821 | (i
.rm
.mode
<< 6));
9822 /* If i.rm.regmem == ESP (4)
9823 && i.rm.mode != (Register mode)
9825 ==> need second modrm byte. */
9826 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9828 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9829 frag_opcode_byte ((i
.sib
.base
<< 0)
9830 | (i
.sib
.index
<< 3)
9831 | (i
.sib
.scale
<< 6));
9834 if (i
.disp_operands
)
9835 output_disp (insn_start_frag
, insn_start_off
);
9838 output_imm (insn_start_frag
, insn_start_off
);
9841 * frag_now_fix () returning plain abs_section_offset when we're in the
9842 * absolute section, and abs_section_offset not getting updated as data
9843 * gets added to the frag breaks the logic below.
9845 if (now_seg
!= absolute_section
)
9847 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9849 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9853 /* NB: Don't add prefix with GOTPC relocation since
9854 output_disp() above depends on the fixed encoding
9855 length. Can't add prefix with TLS relocation since
9856 it breaks TLS linker optimization. */
9857 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9858 /* Prefix count on the current instruction. */
9859 unsigned int count
= i
.vex
.length
;
9861 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9862 /* REX byte is encoded in VEX/EVEX prefix. */
9863 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9866 /* Count prefixes for extended opcode maps. */
9868 switch (i
.tm
.opcode_modifier
.opcodespace
)
9883 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9886 /* Set the maximum prefix size in BRANCH_PREFIX
9888 if (fragP
->tc_frag_data
.max_bytes
> max
)
9889 fragP
->tc_frag_data
.max_bytes
= max
;
9890 if (fragP
->tc_frag_data
.max_bytes
> count
)
9891 fragP
->tc_frag_data
.max_bytes
-= count
;
9893 fragP
->tc_frag_data
.max_bytes
= 0;
9897 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9899 unsigned int max_prefix_size
;
9900 if (align_branch_prefix_size
> max
)
9901 max_prefix_size
= max
;
9903 max_prefix_size
= align_branch_prefix_size
;
9904 if (max_prefix_size
> count
)
9905 fragP
->tc_frag_data
.max_prefix_length
9906 = max_prefix_size
- count
;
9909 /* Use existing segment prefix if possible. Use CS
9910 segment prefix in 64-bit mode. In 32-bit mode, use SS
9911 segment prefix with ESP/EBP base register and use DS
9912 segment prefix without ESP/EBP base register. */
9913 if (i
.prefix
[SEG_PREFIX
])
9914 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9915 else if (flag_code
== CODE_64BIT
)
9916 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9918 && (i
.base_reg
->reg_num
== 4
9919 || i
.base_reg
->reg_num
== 5))
9920 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9922 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9927 /* NB: Don't work with COND_JUMP86 without i386. */
9928 if (align_branch_power
9929 && now_seg
!= absolute_section
9930 && cpu_arch_flags
.bitfield
.cpui386
)
9932 /* Terminate each frag so that we can add prefix and check for
9934 frag_wane (frag_now
);
9941 pi ("" /*line*/, &i
);
9943 #endif /* DEBUG386 */
9946 /* Return the size of the displacement operand N. */
9949 disp_size (unsigned int n
)
9953 if (i
.types
[n
].bitfield
.disp64
)
9955 else if (i
.types
[n
].bitfield
.disp8
)
9957 else if (i
.types
[n
].bitfield
.disp16
)
9962 /* Return the size of the immediate operand N. */
9965 imm_size (unsigned int n
)
9968 if (i
.types
[n
].bitfield
.imm64
)
9970 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9972 else if (i
.types
[n
].bitfield
.imm16
)
9978 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9983 for (n
= 0; n
< i
.operands
; n
++)
9985 if (operand_type_check (i
.types
[n
], disp
))
9987 int size
= disp_size (n
);
9989 if (now_seg
== absolute_section
)
9990 abs_section_offset
+= size
;
9991 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9993 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9995 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9997 p
= frag_more (size
);
9998 md_number_to_chars (p
, val
, size
);
10002 enum bfd_reloc_code_real reloc_type
;
10003 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10004 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10005 && (!want_disp32 (&i
.tm
)
10006 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10007 && !i
.types
[n
].bitfield
.baseindex
)))
10011 /* We can't have 8 bit displacement here. */
10012 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10014 /* The PC relative address is computed relative
10015 to the instruction boundary, so in case immediate
10016 fields follows, we need to adjust the value. */
10017 if (pcrel
&& i
.imm_operands
)
10022 for (n1
= 0; n1
< i
.operands
; n1
++)
10023 if (operand_type_check (i
.types
[n1
], imm
))
10025 /* Only one immediate is allowed for PC
10026 relative address. */
10027 gas_assert (sz
== 0);
10028 sz
= imm_size (n1
);
10029 i
.op
[n
].disps
->X_add_number
-= sz
;
10031 /* We should find the immediate. */
10032 gas_assert (sz
!= 0);
10035 p
= frag_more (size
);
10036 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10038 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10039 && (((reloc_type
== BFD_RELOC_32
10040 || reloc_type
== BFD_RELOC_X86_64_32S
10041 || (reloc_type
== BFD_RELOC_64
10043 && (i
.op
[n
].disps
->X_op
== O_symbol
10044 || (i
.op
[n
].disps
->X_op
== O_add
10045 && ((symbol_get_value_expression
10046 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10048 || reloc_type
== BFD_RELOC_32_PCREL
))
10052 reloc_type
= BFD_RELOC_386_GOTPC
;
10053 i
.has_gotpc_tls_reloc
= true;
10054 i
.op
[n
].disps
->X_add_number
+=
10055 encoding_length (insn_start_frag
, insn_start_off
, p
);
10057 else if (reloc_type
== BFD_RELOC_64
)
10058 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10060 /* Don't do the adjustment for x86-64, as there
10061 the pcrel addressing is relative to the _next_
10062 insn, and that is taken care of in other code. */
10063 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10065 else if (align_branch_power
)
10067 switch (reloc_type
)
10069 case BFD_RELOC_386_TLS_GD
:
10070 case BFD_RELOC_386_TLS_LDM
:
10071 case BFD_RELOC_386_TLS_IE
:
10072 case BFD_RELOC_386_TLS_IE_32
:
10073 case BFD_RELOC_386_TLS_GOTIE
:
10074 case BFD_RELOC_386_TLS_GOTDESC
:
10075 case BFD_RELOC_386_TLS_DESC_CALL
:
10076 case BFD_RELOC_X86_64_TLSGD
:
10077 case BFD_RELOC_X86_64_TLSLD
:
10078 case BFD_RELOC_X86_64_GOTTPOFF
:
10079 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10080 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10081 i
.has_gotpc_tls_reloc
= true;
10086 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10087 size
, i
.op
[n
].disps
, pcrel
,
10090 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10091 && !i
.prefix
[ADDR_PREFIX
])
10092 fixP
->fx_signed
= 1;
10094 /* Check for "call/jmp *mem", "mov mem, %reg",
10095 "test %reg, mem" and "binop mem, %reg" where binop
10096 is one of adc, add, and, cmp, or, sbb, sub, xor
10097 instructions without data prefix. Always generate
10098 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10099 if (i
.prefix
[DATA_PREFIX
] == 0
10100 && (generate_relax_relocations
10103 && i
.rm
.regmem
== 5))
10105 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10106 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
10107 && ((i
.operands
== 1
10108 && i
.tm
.base_opcode
== 0xff
10109 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10110 || (i
.operands
== 2
10111 && (i
.tm
.base_opcode
== 0x8b
10112 || i
.tm
.base_opcode
== 0x85
10113 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10117 fixP
->fx_tcbit
= i
.rex
!= 0;
10119 && (i
.base_reg
->reg_num
== RegIP
))
10120 fixP
->fx_tcbit2
= 1;
10123 fixP
->fx_tcbit2
= 1;
10131 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10136 for (n
= 0; n
< i
.operands
; n
++)
10138 if (operand_type_check (i
.types
[n
], imm
))
10140 int size
= imm_size (n
);
10142 if (now_seg
== absolute_section
)
10143 abs_section_offset
+= size
;
10144 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10148 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10150 p
= frag_more (size
);
10151 md_number_to_chars (p
, val
, size
);
10155 /* Not absolute_section.
10156 Need a 32-bit fixup (don't support 8bit
10157 non-absolute imms). Try to support other
10159 enum bfd_reloc_code_real reloc_type
;
10162 if (i
.types
[n
].bitfield
.imm32s
10163 && (i
.suffix
== QWORD_MNEM_SUFFIX
10164 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
10169 p
= frag_more (size
);
10170 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10172 /* This is tough to explain. We end up with this one if we
10173 * have operands that look like
10174 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10175 * obtain the absolute address of the GOT, and it is strongly
10176 * preferable from a performance point of view to avoid using
10177 * a runtime relocation for this. The actual sequence of
10178 * instructions often look something like:
10183 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10185 * The call and pop essentially return the absolute address
10186 * of the label .L66 and store it in %ebx. The linker itself
10187 * will ultimately change the first operand of the addl so
10188 * that %ebx points to the GOT, but to keep things simple, the
10189 * .o file must have this operand set so that it generates not
10190 * the absolute address of .L66, but the absolute address of
10191 * itself. This allows the linker itself simply treat a GOTPC
10192 * relocation as asking for a pcrel offset to the GOT to be
10193 * added in, and the addend of the relocation is stored in the
10194 * operand field for the instruction itself.
10196 * Our job here is to fix the operand so that it would add
10197 * the correct offset so that %ebx would point to itself. The
10198 * thing that is tricky is that .-.L66 will point to the
10199 * beginning of the instruction, so we need to further modify
10200 * the operand so that it will point to itself. There are
10201 * other cases where you have something like:
10203 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10205 * and here no correction would be required. Internally in
10206 * the assembler we treat operands of this form as not being
10207 * pcrel since the '.' is explicitly mentioned, and I wonder
10208 * whether it would simplify matters to do it this way. Who
10209 * knows. In earlier versions of the PIC patches, the
10210 * pcrel_adjust field was used to store the correction, but
10211 * since the expression is not pcrel, I felt it would be
10212 * confusing to do it this way. */
10214 if ((reloc_type
== BFD_RELOC_32
10215 || reloc_type
== BFD_RELOC_X86_64_32S
10216 || reloc_type
== BFD_RELOC_64
)
10218 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10219 && (i
.op
[n
].imms
->X_op
== O_symbol
10220 || (i
.op
[n
].imms
->X_op
== O_add
10221 && ((symbol_get_value_expression
10222 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10226 reloc_type
= BFD_RELOC_386_GOTPC
;
10227 else if (size
== 4)
10228 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10229 else if (size
== 8)
10230 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10231 i
.has_gotpc_tls_reloc
= true;
10232 i
.op
[n
].imms
->X_add_number
+=
10233 encoding_length (insn_start_frag
, insn_start_off
, p
);
10235 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10236 i
.op
[n
].imms
, 0, reloc_type
);
10242 /* x86_cons_fix_new is called via the expression parsing code when a
10243 reloc is needed. We use this hook to get the correct .got reloc. */
10244 static int cons_sign
= -1;
10247 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10248 expressionS
*exp
, bfd_reloc_code_real_type r
)
10250 r
= reloc (len
, 0, cons_sign
, r
);
10253 if (exp
->X_op
== O_secrel
)
10255 exp
->X_op
= O_symbol
;
10256 r
= BFD_RELOC_32_SECREL
;
10258 else if (exp
->X_op
== O_secidx
)
10259 r
= BFD_RELOC_16_SECIDX
;
10262 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10265 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10266 purpose of the `.dc.a' internal pseudo-op. */
10269 x86_address_bytes (void)
10271 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10273 return stdoutput
->arch_info
->bits_per_address
/ 8;
10276 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10277 || defined (LEX_AT)) && !defined (TE_PE)
10278 # define lex_got(reloc, adjust, types) NULL
10280 /* Parse operands of the form
10281 <symbol>@GOTOFF+<nnn>
10282 and similar .plt or .got references.
10284 If we find one, set up the correct relocation in RELOC and copy the
10285 input string, minus the `@GOTOFF' into a malloc'd buffer for
10286 parsing by the calling routine. Return this buffer, and if ADJUST
10287 is non-null set it to the length of the string we removed from the
10288 input line. Otherwise return NULL. */
10290 lex_got (enum bfd_reloc_code_real
*rel
,
10292 i386_operand_type
*types
)
10294 /* Some of the relocations depend on the size of what field is to
10295 be relocated. But in our callers i386_immediate and i386_displacement
10296 we don't yet know the operand size (this will be set by insn
10297 matching). Hence we record the word32 relocation here,
10298 and adjust the reloc according to the real size in reloc(). */
10299 static const struct
10303 const enum bfd_reloc_code_real rel
[2];
10304 const i386_operand_type types64
;
10305 bool need_GOT_symbol
;
10310 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10311 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10312 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10313 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10314 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10315 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10316 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10317 { .imm64 = 1, .disp64 = 1 } }
10320 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10321 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10322 BFD_RELOC_SIZE32
},
10323 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10325 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10326 BFD_RELOC_X86_64_PLTOFF64
},
10327 { .bitfield
= { .imm64
= 1 } }, true },
10328 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10329 BFD_RELOC_X86_64_PLT32
},
10330 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10331 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10332 BFD_RELOC_X86_64_GOTPLT64
},
10333 OPERAND_TYPE_IMM64_DISP64
, true },
10334 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10335 BFD_RELOC_X86_64_GOTOFF64
},
10336 OPERAND_TYPE_IMM64_DISP64
, true },
10337 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10338 BFD_RELOC_X86_64_GOTPCREL
},
10339 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10340 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10341 BFD_RELOC_X86_64_TLSGD
},
10342 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10343 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10344 _dummy_first_bfd_reloc_code_real
},
10345 OPERAND_TYPE_NONE
, true },
10346 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10347 BFD_RELOC_X86_64_TLSLD
},
10348 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10349 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10350 BFD_RELOC_X86_64_GOTTPOFF
},
10351 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10352 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10353 BFD_RELOC_X86_64_TPOFF32
},
10354 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10355 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10356 _dummy_first_bfd_reloc_code_real
},
10357 OPERAND_TYPE_NONE
, true },
10358 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10359 BFD_RELOC_X86_64_DTPOFF32
},
10360 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10361 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10362 _dummy_first_bfd_reloc_code_real
},
10363 OPERAND_TYPE_NONE
, true },
10364 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10365 _dummy_first_bfd_reloc_code_real
},
10366 OPERAND_TYPE_NONE
, true },
10367 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10368 BFD_RELOC_X86_64_GOT32
},
10369 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10370 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10371 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10372 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10373 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10374 BFD_RELOC_X86_64_TLSDESC_CALL
},
10375 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10377 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10378 BFD_RELOC_32_SECREL
},
10379 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10382 #undef OPERAND_TYPE_IMM32_32S_DISP32
10383 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10384 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10385 #undef OPERAND_TYPE_IMM64_DISP64
10391 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10396 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10397 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10400 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10402 int len
= gotrel
[j
].len
;
10403 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10405 if (gotrel
[j
].rel
[object_64bit
] != 0)
10408 char *tmpbuf
, *past_reloc
;
10410 *rel
= gotrel
[j
].rel
[object_64bit
];
10414 if (flag_code
!= CODE_64BIT
)
10416 types
->bitfield
.imm32
= 1;
10417 types
->bitfield
.disp32
= 1;
10420 *types
= gotrel
[j
].types64
;
10423 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10424 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10426 /* The length of the first part of our input line. */
10427 first
= cp
- input_line_pointer
;
10429 /* The second part goes from after the reloc token until
10430 (and including) an end_of_line char or comma. */
10431 past_reloc
= cp
+ 1 + len
;
10433 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10435 second
= cp
+ 1 - past_reloc
;
10437 /* Allocate and copy string. The trailing NUL shouldn't
10438 be necessary, but be safe. */
10439 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10440 memcpy (tmpbuf
, input_line_pointer
, first
);
10441 if (second
!= 0 && *past_reloc
!= ' ')
10442 /* Replace the relocation token with ' ', so that
10443 errors like foo@GOTOFF1 will be detected. */
10444 tmpbuf
[first
++] = ' ';
10446 /* Increment length by 1 if the relocation token is
10451 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10452 tmpbuf
[first
+ second
] = '\0';
10456 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10457 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10462 /* Might be a symbol version string. Don't as_bad here. */
10467 bfd_reloc_code_real_type
10468 x86_cons (expressionS
*exp
, int size
)
10470 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10472 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10473 && !defined (LEX_AT)) \
10475 intel_syntax
= -intel_syntax
;
10478 if (size
== 4 || (object_64bit
&& size
== 8))
10480 /* Handle @GOTOFF and the like in an expression. */
10482 char *gotfree_input_line
;
10485 save
= input_line_pointer
;
10486 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10487 if (gotfree_input_line
)
10488 input_line_pointer
= gotfree_input_line
;
10492 if (gotfree_input_line
)
10494 /* expression () has merrily parsed up to the end of line,
10495 or a comma - in the wrong buffer. Transfer how far
10496 input_line_pointer has moved to the right buffer. */
10497 input_line_pointer
= (save
10498 + (input_line_pointer
- gotfree_input_line
)
10500 free (gotfree_input_line
);
10501 if (exp
->X_op
== O_constant
10502 || exp
->X_op
== O_absent
10503 || exp
->X_op
== O_illegal
10504 || exp
->X_op
== O_register
10505 || exp
->X_op
== O_big
)
10507 char c
= *input_line_pointer
;
10508 *input_line_pointer
= 0;
10509 as_bad (_("missing or invalid expression `%s'"), save
);
10510 *input_line_pointer
= c
;
10512 else if ((got_reloc
== BFD_RELOC_386_PLT32
10513 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10514 && exp
->X_op
!= O_symbol
)
10516 char c
= *input_line_pointer
;
10517 *input_line_pointer
= 0;
10518 as_bad (_("invalid PLT expression `%s'"), save
);
10519 *input_line_pointer
= c
;
10526 intel_syntax
= -intel_syntax
;
10529 i386_intel_simplify (exp
);
10534 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10535 if (size
== 4 && exp
->X_op
== O_constant
&& !object_64bit
)
10536 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10542 signed_cons (int size
)
10552 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10559 if (exp
.X_op
== O_symbol
)
10560 exp
.X_op
= O_secrel
;
10562 emit_expr (&exp
, 4);
10564 while (*input_line_pointer
++ == ',');
10566 input_line_pointer
--;
10567 demand_empty_rest_of_line ();
10571 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
10578 if (exp
.X_op
== O_symbol
)
10579 exp
.X_op
= O_secidx
;
10581 emit_expr (&exp
, 2);
10583 while (*input_line_pointer
++ == ',');
10585 input_line_pointer
--;
10586 demand_empty_rest_of_line ();
10590 /* Handle Rounding Control / SAE specifiers. */
10593 RC_SAE_specifier (const char *pstr
)
10597 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10599 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10601 if (i
.rounding
.type
!= rc_none
)
10603 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
10607 i
.rounding
.type
= RC_NamesTable
[j
].type
;
10609 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
10616 /* Handle Vector operations. */
10619 check_VecOperations (char *op_string
)
10621 const reg_entry
*mask
;
10628 if (*op_string
== '{')
10632 /* Check broadcasts. */
10633 if (startswith (op_string
, "1to"))
10635 unsigned int bcst_type
;
10637 if (i
.broadcast
.type
)
10638 goto duplicated_vec_op
;
10641 if (*op_string
== '8')
10643 else if (*op_string
== '4')
10645 else if (*op_string
== '2')
10647 else if (*op_string
== '1'
10648 && *(op_string
+1) == '6')
10653 else if (*op_string
== '3'
10654 && *(op_string
+1) == '2')
10661 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10666 i
.broadcast
.type
= bcst_type
;
10667 i
.broadcast
.operand
= this_operand
;
10669 /* Check masking operation. */
10670 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10672 if (mask
== &bad_reg
)
10675 /* k0 can't be used for write mask. */
10676 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10678 as_bad (_("`%s%s' can't be used for write mask"),
10679 register_prefix
, mask
->reg_name
);
10686 i
.mask
.operand
= this_operand
;
10688 else if (i
.mask
.reg
->reg_num
)
10689 goto duplicated_vec_op
;
10694 /* Only "{z}" is allowed here. No need to check
10695 zeroing mask explicitly. */
10696 if (i
.mask
.operand
!= (unsigned int) this_operand
)
10698 as_bad (_("invalid write mask `%s'"), saved
);
10703 op_string
= end_op
;
10705 /* Check zeroing-flag for masking operation. */
10706 else if (*op_string
== 'z')
10710 i
.mask
.reg
= reg_k0
;
10711 i
.mask
.zeroing
= 1;
10712 i
.mask
.operand
= this_operand
;
10716 if (i
.mask
.zeroing
)
10719 as_bad (_("duplicated `%s'"), saved
);
10723 i
.mask
.zeroing
= 1;
10725 /* Only "{%k}" is allowed here. No need to check mask
10726 register explicitly. */
10727 if (i
.mask
.operand
!= (unsigned int) this_operand
)
10729 as_bad (_("invalid zeroing-masking `%s'"),
10737 else if (intel_syntax
10738 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
10739 i
.rounding
.modifier
= true;
10741 goto unknown_vec_op
;
10743 if (*op_string
!= '}')
10745 as_bad (_("missing `}' in `%s'"), saved
);
10750 /* Strip whitespace since the addition of pseudo prefixes
10751 changed how the scrubber treats '{'. */
10752 if (is_space_char (*op_string
))
10758 /* We don't know this one. */
10759 as_bad (_("unknown vector operation: `%s'"), saved
);
10763 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
10765 as_bad (_("zeroing-masking only allowed with write mask"));
10773 i386_immediate (char *imm_start
)
10775 char *save_input_line_pointer
;
10776 char *gotfree_input_line
;
10779 i386_operand_type types
;
10781 operand_type_set (&types
, ~0);
10783 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10785 as_bad (_("at most %d immediate operands are allowed"),
10786 MAX_IMMEDIATE_OPERANDS
);
10790 exp
= &im_expressions
[i
.imm_operands
++];
10791 i
.op
[this_operand
].imms
= exp
;
10793 if (is_space_char (*imm_start
))
10796 save_input_line_pointer
= input_line_pointer
;
10797 input_line_pointer
= imm_start
;
10799 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10800 if (gotfree_input_line
)
10801 input_line_pointer
= gotfree_input_line
;
10803 exp_seg
= expression (exp
);
10805 SKIP_WHITESPACE ();
10806 if (*input_line_pointer
)
10807 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10809 input_line_pointer
= save_input_line_pointer
;
10810 if (gotfree_input_line
)
10812 free (gotfree_input_line
);
10814 if (exp
->X_op
== O_constant
)
10815 exp
->X_op
= O_illegal
;
10818 if (exp_seg
== reg_section
)
10820 as_bad (_("illegal immediate register operand %s"), imm_start
);
10824 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10828 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10829 i386_operand_type types
, const char *imm_start
)
10831 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10834 as_bad (_("missing or invalid immediate expression `%s'"),
10838 else if (exp
->X_op
== O_constant
)
10840 /* Size it properly later. */
10841 i
.types
[this_operand
].bitfield
.imm64
= 1;
10843 /* If not 64bit, sign/zero extend val, to account for wraparound
10845 if (flag_code
!= CODE_64BIT
)
10846 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10848 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10849 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10850 && exp_seg
!= absolute_section
10851 && exp_seg
!= text_section
10852 && exp_seg
!= data_section
10853 && exp_seg
!= bss_section
10854 && exp_seg
!= undefined_section
10855 && !bfd_is_com_section (exp_seg
))
10857 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10863 /* This is an address. The size of the address will be
10864 determined later, depending on destination register,
10865 suffix, or the default for the section. */
10866 i
.types
[this_operand
].bitfield
.imm8
= 1;
10867 i
.types
[this_operand
].bitfield
.imm16
= 1;
10868 i
.types
[this_operand
].bitfield
.imm32
= 1;
10869 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10870 i
.types
[this_operand
].bitfield
.imm64
= 1;
10871 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10879 i386_scale (char *scale
)
10882 char *save
= input_line_pointer
;
10884 input_line_pointer
= scale
;
10885 val
= get_absolute_expression ();
10890 i
.log2_scale_factor
= 0;
10893 i
.log2_scale_factor
= 1;
10896 i
.log2_scale_factor
= 2;
10899 i
.log2_scale_factor
= 3;
10903 char sep
= *input_line_pointer
;
10905 *input_line_pointer
= '\0';
10906 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10908 *input_line_pointer
= sep
;
10909 input_line_pointer
= save
;
10913 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10915 as_warn (_("scale factor of %d without an index register"),
10916 1 << i
.log2_scale_factor
);
10917 i
.log2_scale_factor
= 0;
10919 scale
= input_line_pointer
;
10920 input_line_pointer
= save
;
10925 i386_displacement (char *disp_start
, char *disp_end
)
10929 char *save_input_line_pointer
;
10930 char *gotfree_input_line
;
10932 i386_operand_type bigdisp
, types
= anydisp
;
10935 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10937 as_bad (_("at most %d displacement operands are allowed"),
10938 MAX_MEMORY_OPERANDS
);
10942 operand_type_set (&bigdisp
, 0);
10944 || i
.types
[this_operand
].bitfield
.baseindex
10945 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10946 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10948 i386_addressing_mode ();
10949 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10950 if (flag_code
== CODE_64BIT
)
10952 bigdisp
.bitfield
.disp32
= 1;
10954 bigdisp
.bitfield
.disp64
= 1;
10956 else if ((flag_code
== CODE_16BIT
) ^ override
)
10957 bigdisp
.bitfield
.disp16
= 1;
10959 bigdisp
.bitfield
.disp32
= 1;
10963 /* For PC-relative branches, the width of the displacement may be
10964 dependent upon data size, but is never dependent upon address size.
10965 Also make sure to not unintentionally match against a non-PC-relative
10966 branch template. */
10967 static templates aux_templates
;
10968 const insn_template
*t
= current_templates
->start
;
10969 bool has_intel64
= false;
10971 aux_templates
.start
= t
;
10972 while (++t
< current_templates
->end
)
10974 if (t
->opcode_modifier
.jump
10975 != current_templates
->start
->opcode_modifier
.jump
)
10977 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10978 has_intel64
= true;
10980 if (t
< current_templates
->end
)
10982 aux_templates
.end
= t
;
10983 current_templates
= &aux_templates
;
10986 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10987 if (flag_code
== CODE_64BIT
)
10989 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10990 && (!intel64
|| !has_intel64
))
10991 bigdisp
.bitfield
.disp16
= 1;
10993 bigdisp
.bitfield
.disp32
= 1;
10998 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
11000 : LONG_MNEM_SUFFIX
));
11001 bigdisp
.bitfield
.disp32
= 1;
11002 if ((flag_code
== CODE_16BIT
) ^ override
)
11004 bigdisp
.bitfield
.disp32
= 0;
11005 bigdisp
.bitfield
.disp16
= 1;
11009 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11012 exp
= &disp_expressions
[i
.disp_operands
];
11013 i
.op
[this_operand
].disps
= exp
;
11015 save_input_line_pointer
= input_line_pointer
;
11016 input_line_pointer
= disp_start
;
11017 END_STRING_AND_SAVE (disp_end
);
11019 #ifndef GCC_ASM_O_HACK
11020 #define GCC_ASM_O_HACK 0
11023 END_STRING_AND_SAVE (disp_end
+ 1);
11024 if (i
.types
[this_operand
].bitfield
.baseIndex
11025 && displacement_string_end
[-1] == '+')
11027 /* This hack is to avoid a warning when using the "o"
11028 constraint within gcc asm statements.
11031 #define _set_tssldt_desc(n,addr,limit,type) \
11032 __asm__ __volatile__ ( \
11033 "movw %w2,%0\n\t" \
11034 "movw %w1,2+%0\n\t" \
11035 "rorl $16,%1\n\t" \
11036 "movb %b1,4+%0\n\t" \
11037 "movb %4,5+%0\n\t" \
11038 "movb $0,6+%0\n\t" \
11039 "movb %h1,7+%0\n\t" \
11041 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
11043 This works great except that the output assembler ends
11044 up looking a bit weird if it turns out that there is
11045 no offset. You end up producing code that looks like:
11058 So here we provide the missing zero. */
11060 *displacement_string_end
= '0';
11063 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11064 if (gotfree_input_line
)
11065 input_line_pointer
= gotfree_input_line
;
11067 exp_seg
= expression (exp
);
11069 SKIP_WHITESPACE ();
11070 if (*input_line_pointer
)
11071 as_bad (_("junk `%s' after expression"), input_line_pointer
);
11073 RESTORE_END_STRING (disp_end
+ 1);
11075 input_line_pointer
= save_input_line_pointer
;
11076 if (gotfree_input_line
)
11078 free (gotfree_input_line
);
11080 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
11081 exp
->X_op
= O_illegal
;
11084 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
11086 RESTORE_END_STRING (disp_end
);
11092 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
11093 i386_operand_type types
, const char *disp_start
)
11097 /* We do this to make sure that the section symbol is in
11098 the symbol table. We will ultimately change the relocation
11099 to be relative to the beginning of the section. */
11100 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
11101 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
11102 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
11104 if (exp
->X_op
!= O_symbol
)
11107 if (S_IS_LOCAL (exp
->X_add_symbol
)
11108 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
11109 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
11110 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
11111 exp
->X_op
= O_subtract
;
11112 exp
->X_op_symbol
= GOT_symbol
;
11113 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
11114 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
11115 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
11116 i
.reloc
[this_operand
] = BFD_RELOC_64
;
11118 i
.reloc
[this_operand
] = BFD_RELOC_32
;
11121 else if (exp
->X_op
== O_absent
11122 || exp
->X_op
== O_illegal
11123 || exp
->X_op
== O_big
)
11126 as_bad (_("missing or invalid displacement expression `%s'"),
11131 else if (exp
->X_op
== O_constant
)
11133 /* Sizing gets taken care of by optimize_disp().
11135 If not 64bit, sign/zero extend val, to account for wraparound
11137 if (flag_code
!= CODE_64BIT
)
11138 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
11141 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11142 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
11143 && exp_seg
!= absolute_section
11144 && exp_seg
!= text_section
11145 && exp_seg
!= data_section
11146 && exp_seg
!= bss_section
11147 && exp_seg
!= undefined_section
11148 && !bfd_is_com_section (exp_seg
))
11150 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
11155 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
11156 i
.types
[this_operand
].bitfield
.disp8
= 1;
11158 /* Check if this is a displacement only operand. */
11159 if (!i
.types
[this_operand
].bitfield
.baseindex
)
11160 i
.types
[this_operand
] =
11161 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
11162 operand_type_and (i
.types
[this_operand
], types
));
11167 /* Return the active addressing mode, taking address override and
11168 registers forming the address into consideration. Update the
11169 address override prefix if necessary. */
11171 static enum flag_code
11172 i386_addressing_mode (void)
11174 enum flag_code addr_mode
;
11176 if (i
.prefix
[ADDR_PREFIX
])
11177 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
11178 else if (flag_code
== CODE_16BIT
11179 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
11180 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
11181 from md_assemble() by "is not a valid base/index expression"
11182 when there is a base and/or index. */
11183 && !i
.types
[this_operand
].bitfield
.baseindex
)
11185 /* MPX insn memory operands with neither base nor index must be forced
11186 to use 32-bit addressing in 16-bit mode. */
11187 addr_mode
= CODE_32BIT
;
11188 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11190 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
11191 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
11195 addr_mode
= flag_code
;
11197 #if INFER_ADDR_PREFIX
11198 if (i
.mem_operands
== 0)
11200 /* Infer address prefix from the first memory operand. */
11201 const reg_entry
*addr_reg
= i
.base_reg
;
11203 if (addr_reg
== NULL
)
11204 addr_reg
= i
.index_reg
;
11208 if (addr_reg
->reg_type
.bitfield
.dword
)
11209 addr_mode
= CODE_32BIT
;
11210 else if (flag_code
!= CODE_64BIT
11211 && addr_reg
->reg_type
.bitfield
.word
)
11212 addr_mode
= CODE_16BIT
;
11214 if (addr_mode
!= flag_code
)
11216 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11218 /* Change the size of any displacement too. At most one
11219 of Disp16 or Disp32 is set.
11220 FIXME. There doesn't seem to be any real need for
11221 separate Disp16 and Disp32 flags. The same goes for
11222 Imm16 and Imm32. Removing them would probably clean
11223 up the code quite a lot. */
11224 if (flag_code
!= CODE_64BIT
11225 && (i
.types
[this_operand
].bitfield
.disp16
11226 || i
.types
[this_operand
].bitfield
.disp32
))
11228 static const i386_operand_type disp16_32
= {
11229 .bitfield
= { .disp16
= 1, .disp32
= 1 }
11232 i
.types
[this_operand
]
11233 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
11244 /* Make sure the memory operand we've been dealt is valid.
11245 Return 1 on success, 0 on a failure. */
11248 i386_index_check (const char *operand_string
)
11250 const char *kind
= "base/index";
11251 enum flag_code addr_mode
= i386_addressing_mode ();
11252 const insn_template
*t
= current_templates
->start
;
11254 if (t
->opcode_modifier
.isstring
11255 && (current_templates
->end
[-1].opcode_modifier
.isstring
11256 || i
.mem_operands
))
11258 /* Memory operands of string insns are special in that they only allow
11259 a single register (rDI, rSI, or rBX) as their memory address. */
11260 const reg_entry
*expected_reg
;
11261 static const char *di_si
[][2] =
11267 static const char *bx
[] = { "ebx", "bx", "rbx" };
11269 kind
= "string address";
11271 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
11273 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
11274 - IS_STRING_ES_OP0
;
11277 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
11278 || ((!i
.mem_operands
!= !intel_syntax
)
11279 && current_templates
->end
[-1].operand_types
[1]
11280 .bitfield
.baseindex
))
11283 = (const reg_entry
*) str_hash_find (reg_hash
,
11284 di_si
[addr_mode
][op
== es_op
]);
11288 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11290 if (i
.base_reg
!= expected_reg
11292 || operand_type_check (i
.types
[this_operand
], disp
))
11294 /* The second memory operand must have the same size as
11298 && !((addr_mode
== CODE_64BIT
11299 && i
.base_reg
->reg_type
.bitfield
.qword
)
11300 || (addr_mode
== CODE_32BIT
11301 ? i
.base_reg
->reg_type
.bitfield
.dword
11302 : i
.base_reg
->reg_type
.bitfield
.word
)))
11305 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11307 intel_syntax
? '[' : '(',
11309 expected_reg
->reg_name
,
11310 intel_syntax
? ']' : ')');
11317 as_bad (_("`%s' is not a valid %s expression"),
11318 operand_string
, kind
);
11323 if (addr_mode
!= CODE_16BIT
)
11325 /* 32-bit/64-bit checks. */
11326 if (i
.disp_encoding
== disp_encoding_16bit
)
11329 as_bad (_("invalid `%s' prefix"),
11330 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11335 && ((addr_mode
== CODE_64BIT
11336 ? !i
.base_reg
->reg_type
.bitfield
.qword
11337 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11338 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11339 || i
.base_reg
->reg_num
== RegIZ
))
11341 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11342 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11343 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11344 && ((addr_mode
== CODE_64BIT
11345 ? !i
.index_reg
->reg_type
.bitfield
.qword
11346 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11347 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11350 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11351 if ((t
->opcode_modifier
.opcodeprefix
== PREFIX_0XF3
11352 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11353 && t
->base_opcode
== 0x1b)
11354 || (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11355 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11356 && (t
->base_opcode
& ~1) == 0x1a)
11357 || t
->opcode_modifier
.sib
== SIBMEM
)
11359 /* They cannot use RIP-relative addressing. */
11360 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11362 as_bad (_("`%s' cannot be used here"), operand_string
);
11366 /* bndldx and bndstx ignore their scale factor. */
11367 if (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11368 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11369 && (t
->base_opcode
& ~1) == 0x1a
11370 && i
.log2_scale_factor
)
11371 as_warn (_("register scaling is being ignored here"));
11376 /* 16-bit checks. */
11377 if (i
.disp_encoding
== disp_encoding_32bit
)
11381 && (!i
.base_reg
->reg_type
.bitfield
.word
11382 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11384 && (!i
.index_reg
->reg_type
.bitfield
.word
11385 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11387 && i
.base_reg
->reg_num
< 6
11388 && i
.index_reg
->reg_num
>= 6
11389 && i
.log2_scale_factor
== 0))))
11396 /* Handle vector immediates. */
11399 RC_SAE_immediate (const char *imm_start
)
11401 const char *pstr
= imm_start
;
11406 pstr
= RC_SAE_specifier (pstr
+ 1);
11410 if (*pstr
++ != '}')
11412 as_bad (_("Missing '}': '%s'"), imm_start
);
11415 /* RC/SAE immediate string should contain nothing more. */;
11418 as_bad (_("Junk after '}': '%s'"), imm_start
);
11422 /* Internally this doesn't count as an operand. */
11428 /* Only string instructions can have a second memory operand, so
11429 reduce current_templates to just those if it contains any. */
11431 maybe_adjust_templates (void)
11433 const insn_template
*t
;
11435 gas_assert (i
.mem_operands
== 1);
11437 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11438 if (t
->opcode_modifier
.isstring
)
11441 if (t
< current_templates
->end
)
11443 static templates aux_templates
;
11446 aux_templates
.start
= t
;
11447 for (; t
< current_templates
->end
; ++t
)
11448 if (!t
->opcode_modifier
.isstring
)
11450 aux_templates
.end
= t
;
11452 /* Determine whether to re-check the first memory operand. */
11453 recheck
= (aux_templates
.start
!= current_templates
->start
11454 || t
!= current_templates
->end
);
11456 current_templates
= &aux_templates
;
11460 i
.mem_operands
= 0;
11461 if (i
.memop1_string
!= NULL
11462 && i386_index_check (i
.memop1_string
) == 0)
11464 i
.mem_operands
= 1;
11471 static INLINE
bool starts_memory_operand (char c
)
11474 || is_identifier_char (c
)
11475 || strchr ("([\"+-!~", c
);
11478 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11482 i386_att_operand (char *operand_string
)
11484 const reg_entry
*r
;
11486 char *op_string
= operand_string
;
11488 if (is_space_char (*op_string
))
11491 /* We check for an absolute prefix (differentiating,
11492 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11493 if (*op_string
== ABSOLUTE_PREFIX
)
11496 if (is_space_char (*op_string
))
11498 i
.jumpabsolute
= true;
11501 /* Check if operand is a register. */
11502 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11504 i386_operand_type temp
;
11509 /* Check for a segment override by searching for ':' after a
11510 segment register. */
11511 op_string
= end_op
;
11512 if (is_space_char (*op_string
))
11514 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11516 i
.seg
[i
.mem_operands
] = r
;
11518 /* Skip the ':' and whitespace. */
11520 if (is_space_char (*op_string
))
11523 /* Handle case of %es:*foo. */
11524 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
)
11527 if (is_space_char (*op_string
))
11529 i
.jumpabsolute
= true;
11532 if (!starts_memory_operand (*op_string
))
11534 as_bad (_("bad memory operand `%s'"), op_string
);
11537 goto do_memory_reference
;
11540 /* Handle vector operations. */
11541 if (*op_string
== '{')
11543 op_string
= check_VecOperations (op_string
);
11544 if (op_string
== NULL
)
11550 as_bad (_("junk `%s' after register"), op_string
);
11553 temp
= r
->reg_type
;
11554 temp
.bitfield
.baseindex
= 0;
11555 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11557 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11558 i
.op
[this_operand
].regs
= r
;
11561 /* A GPR may follow an RC or SAE immediate only if a (vector) register
11562 operand was also present earlier on. */
11563 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
11564 && i
.reg_operands
== 1)
11568 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
11569 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
11571 as_bad (_("`%s': misplaced `{%s}'"),
11572 current_templates
->start
->name
, RC_NamesTable
[j
].name
);
11576 else if (*op_string
== REGISTER_PREFIX
)
11578 as_bad (_("bad register name `%s'"), op_string
);
11581 else if (*op_string
== IMMEDIATE_PREFIX
)
11584 if (i
.jumpabsolute
)
11586 as_bad (_("immediate operand illegal with absolute jump"));
11589 if (!i386_immediate (op_string
))
11591 if (i
.rounding
.type
!= rc_none
)
11593 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
11594 current_templates
->start
->name
);
11598 else if (RC_SAE_immediate (operand_string
))
11600 /* If it is a RC or SAE immediate, do the necessary placement check:
11601 Only another immediate or a GPR may precede it. */
11602 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
11603 || (i
.reg_operands
== 1
11604 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
11606 as_bad (_("`%s': misplaced `%s'"),
11607 current_templates
->start
->name
, operand_string
);
11611 else if (starts_memory_operand (*op_string
))
11613 /* This is a memory reference of some sort. */
11616 /* Start and end of displacement string expression (if found). */
11617 char *displacement_string_start
;
11618 char *displacement_string_end
;
11620 do_memory_reference
:
11621 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11623 if ((i
.mem_operands
== 1
11624 && !current_templates
->start
->opcode_modifier
.isstring
)
11625 || i
.mem_operands
== 2)
11627 as_bad (_("too many memory references for `%s'"),
11628 current_templates
->start
->name
);
11632 /* Check for base index form. We detect the base index form by
11633 looking for an ')' at the end of the operand, searching
11634 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11636 base_string
= op_string
+ strlen (op_string
);
11638 /* Handle vector operations. */
11640 if (is_space_char (*base_string
))
11643 if (*base_string
== '}')
11645 char *vop_start
= NULL
;
11647 while (base_string
-- > op_string
)
11649 if (*base_string
== '"')
11651 if (*base_string
!= '{')
11654 vop_start
= base_string
;
11657 if (is_space_char (*base_string
))
11660 if (*base_string
!= '}')
11668 as_bad (_("unbalanced figure braces"));
11672 if (check_VecOperations (vop_start
) == NULL
)
11676 /* If we only have a displacement, set-up for it to be parsed later. */
11677 displacement_string_start
= op_string
;
11678 displacement_string_end
= base_string
+ 1;
11680 if (*base_string
== ')')
11683 unsigned int parens_not_balanced
= 0;
11684 bool in_quotes
= false;
11686 /* We've already checked that the number of left & right ()'s are
11687 equal, and that there's a matching set of double quotes. */
11688 end_op
= base_string
;
11689 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
11691 if (*temp_string
== '\\' && temp_string
[1] == '"')
11693 else if (*temp_string
== '"')
11694 in_quotes
= !in_quotes
;
11695 else if (!in_quotes
)
11697 if (*temp_string
== '(' && !parens_not_balanced
++)
11698 base_string
= temp_string
;
11699 if (*temp_string
== ')')
11700 --parens_not_balanced
;
11704 temp_string
= base_string
;
11706 /* Skip past '(' and whitespace. */
11707 gas_assert (*base_string
== '(');
11709 if (is_space_char (*base_string
))
11712 if (*base_string
== ','
11713 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11716 displacement_string_end
= temp_string
;
11718 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11722 if (i
.base_reg
== &bad_reg
)
11724 base_string
= end_op
;
11725 if (is_space_char (*base_string
))
11729 /* There may be an index reg or scale factor here. */
11730 if (*base_string
== ',')
11733 if (is_space_char (*base_string
))
11736 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11739 if (i
.index_reg
== &bad_reg
)
11741 base_string
= end_op
;
11742 if (is_space_char (*base_string
))
11744 if (*base_string
== ',')
11747 if (is_space_char (*base_string
))
11750 else if (*base_string
!= ')')
11752 as_bad (_("expecting `,' or `)' "
11753 "after index register in `%s'"),
11758 else if (*base_string
== REGISTER_PREFIX
)
11760 end_op
= strchr (base_string
, ',');
11763 as_bad (_("bad register name `%s'"), base_string
);
11767 /* Check for scale factor. */
11768 if (*base_string
!= ')')
11770 char *end_scale
= i386_scale (base_string
);
11775 base_string
= end_scale
;
11776 if (is_space_char (*base_string
))
11778 if (*base_string
!= ')')
11780 as_bad (_("expecting `)' "
11781 "after scale factor in `%s'"),
11786 else if (!i
.index_reg
)
11788 as_bad (_("expecting index register or scale factor "
11789 "after `,'; got '%c'"),
11794 else if (*base_string
!= ')')
11796 as_bad (_("expecting `,' or `)' "
11797 "after base register in `%s'"),
11802 else if (*base_string
== REGISTER_PREFIX
)
11804 end_op
= strchr (base_string
, ',');
11807 as_bad (_("bad register name `%s'"), base_string
);
11812 /* If there's an expression beginning the operand, parse it,
11813 assuming displacement_string_start and
11814 displacement_string_end are meaningful. */
11815 if (displacement_string_start
!= displacement_string_end
)
11817 if (!i386_displacement (displacement_string_start
,
11818 displacement_string_end
))
11822 /* Special case for (%dx) while doing input/output op. */
11824 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11825 && i
.base_reg
->reg_type
.bitfield
.word
11826 && i
.index_reg
== 0
11827 && i
.log2_scale_factor
== 0
11828 && i
.seg
[i
.mem_operands
] == 0
11829 && !operand_type_check (i
.types
[this_operand
], disp
))
11831 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11832 i
.input_output_operand
= true;
11836 if (i386_index_check (operand_string
) == 0)
11838 i
.flags
[this_operand
] |= Operand_Mem
;
11839 if (i
.mem_operands
== 0)
11840 i
.memop1_string
= xstrdup (operand_string
);
11845 /* It's not a memory operand; argh! */
11846 as_bad (_("invalid char %s beginning operand %d `%s'"),
11847 output_invalid (*op_string
),
11852 return 1; /* Normal return. */
11855 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11856 that an rs_machine_dependent frag may reach. */
11859 i386_frag_max_var (fragS
*frag
)
11861 /* The only relaxable frags are for jumps.
11862 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11863 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11864 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11867 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11869 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11871 /* STT_GNU_IFUNC symbol must go through PLT. */
11872 if ((symbol_get_bfdsym (fr_symbol
)->flags
11873 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11876 if (!S_IS_EXTERNAL (fr_symbol
))
11877 /* Symbol may be weak or local. */
11878 return !S_IS_WEAK (fr_symbol
);
11880 /* Global symbols with non-default visibility can't be preempted. */
11881 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11884 if (fr_var
!= NO_RELOC
)
11885 switch ((enum bfd_reloc_code_real
) fr_var
)
11887 case BFD_RELOC_386_PLT32
:
11888 case BFD_RELOC_X86_64_PLT32
:
11889 /* Symbol with PLT relocation may be preempted. */
11895 /* Global symbols with default visibility in a shared library may be
11896 preempted by another definition. */
11901 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11902 Note also work for Skylake and Cascadelake.
11903 ---------------------------------------------------------------------
11904 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11905 | ------ | ----------- | ------- | -------- |
11907 | Jno | N | N | Y |
11908 | Jc/Jb | Y | N | Y |
11909 | Jae/Jnb | Y | N | Y |
11910 | Je/Jz | Y | Y | Y |
11911 | Jne/Jnz | Y | Y | Y |
11912 | Jna/Jbe | Y | N | Y |
11913 | Ja/Jnbe | Y | N | Y |
11915 | Jns | N | N | Y |
11916 | Jp/Jpe | N | N | Y |
11917 | Jnp/Jpo | N | N | Y |
11918 | Jl/Jnge | Y | Y | Y |
11919 | Jge/Jnl | Y | Y | Y |
11920 | Jle/Jng | Y | Y | Y |
11921 | Jg/Jnle | Y | Y | Y |
11922 --------------------------------------------------------------------- */
11924 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11926 if (mf_cmp
== mf_cmp_alu_cmp
)
11927 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11928 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11929 if (mf_cmp
== mf_cmp_incdec
)
11930 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11931 || mf_jcc
== mf_jcc_jle
);
11932 if (mf_cmp
== mf_cmp_test_and
)
11937 /* Return the next non-empty frag. */
11940 i386_next_non_empty_frag (fragS
*fragP
)
11942 /* There may be a frag with a ".fill 0" when there is no room in
11943 the current frag for frag_grow in output_insn. */
11944 for (fragP
= fragP
->fr_next
;
11946 && fragP
->fr_type
== rs_fill
11947 && fragP
->fr_fix
== 0);
11948 fragP
= fragP
->fr_next
)
11953 /* Return the next jcc frag after BRANCH_PADDING. */
11956 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11958 fragS
*branch_fragP
;
11962 if (pad_fragP
->fr_type
== rs_machine_dependent
11963 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11964 == BRANCH_PADDING
))
11966 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11967 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11969 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11970 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11971 pad_fragP
->tc_frag_data
.mf_type
))
11972 return branch_fragP
;
11978 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11981 i386_classify_machine_dependent_frag (fragS
*fragP
)
11985 fragS
*branch_fragP
;
11987 unsigned int max_prefix_length
;
11989 if (fragP
->tc_frag_data
.classified
)
11992 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11993 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11994 for (next_fragP
= fragP
;
11995 next_fragP
!= NULL
;
11996 next_fragP
= next_fragP
->fr_next
)
11998 next_fragP
->tc_frag_data
.classified
= 1;
11999 if (next_fragP
->fr_type
== rs_machine_dependent
)
12000 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
12002 case BRANCH_PADDING
:
12003 /* The BRANCH_PADDING frag must be followed by a branch
12005 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
12006 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
12008 case FUSED_JCC_PADDING
:
12009 /* Check if this is a fused jcc:
12011 CMP like instruction
12015 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
12016 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
12017 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
12020 /* The BRANCH_PADDING frag is merged with the
12021 FUSED_JCC_PADDING frag. */
12022 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
12023 /* CMP like instruction size. */
12024 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
12025 frag_wane (pad_fragP
);
12026 /* Skip to branch_fragP. */
12027 next_fragP
= branch_fragP
;
12029 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
12031 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
12033 next_fragP
->fr_subtype
12034 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
12035 next_fragP
->tc_frag_data
.max_bytes
12036 = next_fragP
->tc_frag_data
.max_prefix_length
;
12037 /* This will be updated in the BRANCH_PREFIX scan. */
12038 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
12041 frag_wane (next_fragP
);
12046 /* Stop if there is no BRANCH_PREFIX. */
12047 if (!align_branch_prefix_size
)
12050 /* Scan for BRANCH_PREFIX. */
12051 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
12053 if (fragP
->fr_type
!= rs_machine_dependent
12054 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12058 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
12059 COND_JUMP_PREFIX. */
12060 max_prefix_length
= 0;
12061 for (next_fragP
= fragP
;
12062 next_fragP
!= NULL
;
12063 next_fragP
= next_fragP
->fr_next
)
12065 if (next_fragP
->fr_type
== rs_fill
)
12066 /* Skip rs_fill frags. */
12068 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
12069 /* Stop for all other frags. */
12072 /* rs_machine_dependent frags. */
12073 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12076 /* Count BRANCH_PREFIX frags. */
12077 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
12079 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
12080 frag_wane (next_fragP
);
12084 += next_fragP
->tc_frag_data
.max_bytes
;
12086 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12088 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12089 == FUSED_JCC_PADDING
))
12091 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
12092 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
12096 /* Stop for other rs_machine_dependent frags. */
12100 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
12102 /* Skip to the next frag. */
12103 fragP
= next_fragP
;
12107 /* Compute padding size for
12110 CMP like instruction
12112 COND_JUMP/UNCOND_JUMP
12117 COND_JUMP/UNCOND_JUMP
12121 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
12123 unsigned int offset
, size
, padding_size
;
12124 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
12126 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
12128 address
= fragP
->fr_address
;
12129 address
+= fragP
->fr_fix
;
12131 /* CMP like instrunction size. */
12132 size
= fragP
->tc_frag_data
.cmp_size
;
12134 /* The base size of the branch frag. */
12135 size
+= branch_fragP
->fr_fix
;
12137 /* Add opcode and displacement bytes for the rs_machine_dependent
12139 if (branch_fragP
->fr_type
== rs_machine_dependent
)
12140 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
12142 /* Check if branch is within boundary and doesn't end at the last
12144 offset
= address
& ((1U << align_branch_power
) - 1);
12145 if ((offset
+ size
) >= (1U << align_branch_power
))
12146 /* Padding needed to avoid crossing boundary. */
12147 padding_size
= (1U << align_branch_power
) - offset
;
12149 /* No padding needed. */
12152 /* The return value may be saved in tc_frag_data.length which is
12154 if (!fits_in_unsigned_byte (padding_size
))
12157 return padding_size
;
12160 /* i386_generic_table_relax_frag()
12162 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
12163 grow/shrink padding to align branch frags. Hand others to
12167 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
12169 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12170 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12172 long padding_size
= i386_branch_padding_size (fragP
, 0);
12173 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
12175 /* When the BRANCH_PREFIX frag is used, the computed address
12176 must match the actual address and there should be no padding. */
12177 if (fragP
->tc_frag_data
.padding_address
12178 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
12182 /* Update the padding size. */
12184 fragP
->tc_frag_data
.length
= padding_size
;
12188 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12190 fragS
*padding_fragP
, *next_fragP
;
12191 long padding_size
, left_size
, last_size
;
12193 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12194 if (!padding_fragP
)
12195 /* Use the padding set by the leading BRANCH_PREFIX frag. */
12196 return (fragP
->tc_frag_data
.length
12197 - fragP
->tc_frag_data
.last_length
);
12199 /* Compute the relative address of the padding frag in the very
12200 first time where the BRANCH_PREFIX frag sizes are zero. */
12201 if (!fragP
->tc_frag_data
.padding_address
)
12202 fragP
->tc_frag_data
.padding_address
12203 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
12205 /* First update the last length from the previous interation. */
12206 left_size
= fragP
->tc_frag_data
.prefix_length
;
12207 for (next_fragP
= fragP
;
12208 next_fragP
!= padding_fragP
;
12209 next_fragP
= next_fragP
->fr_next
)
12210 if (next_fragP
->fr_type
== rs_machine_dependent
12211 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12216 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12220 if (max
> left_size
)
12225 next_fragP
->tc_frag_data
.last_length
= size
;
12229 next_fragP
->tc_frag_data
.last_length
= 0;
12232 /* Check the padding size for the padding frag. */
12233 padding_size
= i386_branch_padding_size
12234 (padding_fragP
, (fragP
->fr_address
12235 + fragP
->tc_frag_data
.padding_address
));
12237 last_size
= fragP
->tc_frag_data
.prefix_length
;
12238 /* Check if there is change from the last interation. */
12239 if (padding_size
== last_size
)
12241 /* Update the expected address of the padding frag. */
12242 padding_fragP
->tc_frag_data
.padding_address
12243 = (fragP
->fr_address
+ padding_size
12244 + fragP
->tc_frag_data
.padding_address
);
12248 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
12250 /* No padding if there is no sufficient room. Clear the
12251 expected address of the padding frag. */
12252 padding_fragP
->tc_frag_data
.padding_address
= 0;
12256 /* Store the expected address of the padding frag. */
12257 padding_fragP
->tc_frag_data
.padding_address
12258 = (fragP
->fr_address
+ padding_size
12259 + fragP
->tc_frag_data
.padding_address
);
12261 fragP
->tc_frag_data
.prefix_length
= padding_size
;
12263 /* Update the length for the current interation. */
12264 left_size
= padding_size
;
12265 for (next_fragP
= fragP
;
12266 next_fragP
!= padding_fragP
;
12267 next_fragP
= next_fragP
->fr_next
)
12268 if (next_fragP
->fr_type
== rs_machine_dependent
12269 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12274 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12278 if (max
> left_size
)
12283 next_fragP
->tc_frag_data
.length
= size
;
12287 next_fragP
->tc_frag_data
.length
= 0;
12290 return (fragP
->tc_frag_data
.length
12291 - fragP
->tc_frag_data
.last_length
);
12293 return relax_frag (segment
, fragP
, stretch
);
12296 /* md_estimate_size_before_relax()
12298 Called just before relax() for rs_machine_dependent frags. The x86
12299 assembler uses these frags to handle variable size jump
12302 Any symbol that is now undefined will not become defined.
12303 Return the correct fr_subtype in the frag.
12304 Return the initial "guess for variable size of frag" to caller.
12305 The guess is actually the growth beyond the fixed part. Whatever
12306 we do to grow the fixed or variable part contributes to our
12310 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12312 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12313 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12314 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12316 i386_classify_machine_dependent_frag (fragP
);
12317 return fragP
->tc_frag_data
.length
;
12320 /* We've already got fragP->fr_subtype right; all we have to do is
12321 check for un-relaxable symbols. On an ELF system, we can't relax
12322 an externally visible symbol, because it may be overridden by a
12324 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12325 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12327 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12330 #if defined (OBJ_COFF) && defined (TE_PE)
12331 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12332 && S_IS_WEAK (fragP
->fr_symbol
))
12336 /* Symbol is undefined in this segment, or we need to keep a
12337 reloc so that weak symbols can be overridden. */
12338 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12339 enum bfd_reloc_code_real reloc_type
;
12340 unsigned char *opcode
;
12344 if (fragP
->fr_var
!= NO_RELOC
)
12345 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12346 else if (size
== 2)
12347 reloc_type
= BFD_RELOC_16_PCREL
;
12348 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12349 else if (fragP
->tc_frag_data
.code64
&& fragP
->fr_offset
== 0
12350 && need_plt32_p (fragP
->fr_symbol
))
12351 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12354 reloc_type
= BFD_RELOC_32_PCREL
;
12356 old_fr_fix
= fragP
->fr_fix
;
12357 opcode
= (unsigned char *) fragP
->fr_opcode
;
12359 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12362 /* Make jmp (0xeb) a (d)word displacement jump. */
12364 fragP
->fr_fix
+= size
;
12365 fixP
= fix_new (fragP
, old_fr_fix
, size
,
12367 fragP
->fr_offset
, 1,
12373 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12375 /* Negate the condition, and branch past an
12376 unconditional jump. */
12379 /* Insert an unconditional jump. */
12381 /* We added two extra opcode bytes, and have a two byte
12383 fragP
->fr_fix
+= 2 + 2;
12384 fix_new (fragP
, old_fr_fix
+ 2, 2,
12386 fragP
->fr_offset
, 1,
12390 /* Fall through. */
12393 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12395 fragP
->fr_fix
+= 1;
12396 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12398 fragP
->fr_offset
, 1,
12399 BFD_RELOC_8_PCREL
);
12400 fixP
->fx_signed
= 1;
12404 /* This changes the byte-displacement jump 0x7N
12405 to the (d)word-displacement jump 0x0f,0x8N. */
12406 opcode
[1] = opcode
[0] + 0x10;
12407 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12408 /* We've added an opcode byte. */
12409 fragP
->fr_fix
+= 1 + size
;
12410 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
12412 fragP
->fr_offset
, 1,
12417 BAD_CASE (fragP
->fr_subtype
);
12421 /* All jumps handled here are signed, but don't unconditionally use a
12422 signed limit check for 32 and 16 bit jumps as we want to allow wrap
12423 around at 4G (outside of 64-bit mode) and 64k. */
12424 if (size
== 4 && flag_code
== CODE_64BIT
)
12425 fixP
->fx_signed
= 1;
12428 return fragP
->fr_fix
- old_fr_fix
;
12431 /* Guess size depending on current relax state. Initially the relax
12432 state will correspond to a short jump and we return 1, because
12433 the variable part of the frag (the branch offset) is one byte
12434 long. However, we can relax a section more than once and in that
12435 case we must either set fr_subtype back to the unrelaxed state,
12436 or return the value for the appropriate branch. */
12437 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12440 /* Called after relax() is finished.
12442 In: Address of frag.
12443 fr_type == rs_machine_dependent.
12444 fr_subtype is what the address relaxed to.
12446 Out: Any fixSs and constants are set up.
12447 Caller will turn frag into a ".space 0". */
12450 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12453 unsigned char *opcode
;
12454 unsigned char *where_to_put_displacement
= NULL
;
12455 offsetT target_address
;
12456 offsetT opcode_address
;
12457 unsigned int extension
= 0;
12458 offsetT displacement_from_opcode_start
;
12460 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12461 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12462 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12464 /* Generate nop padding. */
12465 unsigned int size
= fragP
->tc_frag_data
.length
;
12468 if (size
> fragP
->tc_frag_data
.max_bytes
)
12474 const char *branch
= "branch";
12475 const char *prefix
= "";
12476 fragS
*padding_fragP
;
12477 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12480 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12481 switch (fragP
->tc_frag_data
.default_prefix
)
12486 case CS_PREFIX_OPCODE
:
12489 case DS_PREFIX_OPCODE
:
12492 case ES_PREFIX_OPCODE
:
12495 case FS_PREFIX_OPCODE
:
12498 case GS_PREFIX_OPCODE
:
12501 case SS_PREFIX_OPCODE
:
12506 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12507 "%s within %d-byte boundary\n");
12509 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12510 "align %s within %d-byte boundary\n");
12514 padding_fragP
= fragP
;
12515 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12516 "%s within %d-byte boundary\n");
12520 switch (padding_fragP
->tc_frag_data
.branch_type
)
12522 case align_branch_jcc
:
12525 case align_branch_fused
:
12526 branch
= "fused jcc";
12528 case align_branch_jmp
:
12531 case align_branch_call
:
12534 case align_branch_indirect
:
12535 branch
= "indiret branch";
12537 case align_branch_ret
:
12544 fprintf (stdout
, msg
,
12545 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12546 (long long) fragP
->fr_address
, branch
,
12547 1 << align_branch_power
);
12549 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12550 memset (fragP
->fr_opcode
,
12551 fragP
->tc_frag_data
.default_prefix
, size
);
12553 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12555 fragP
->fr_fix
+= size
;
12560 opcode
= (unsigned char *) fragP
->fr_opcode
;
12562 /* Address we want to reach in file space. */
12563 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12565 /* Address opcode resides at in file space. */
12566 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12568 /* Displacement from opcode start to fill into instruction. */
12569 displacement_from_opcode_start
= target_address
- opcode_address
;
12571 if ((fragP
->fr_subtype
& BIG
) == 0)
12573 /* Don't have to change opcode. */
12574 extension
= 1; /* 1 opcode + 1 displacement */
12575 where_to_put_displacement
= &opcode
[1];
12579 if (no_cond_jump_promotion
12580 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12581 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12582 _("long jump required"));
12584 switch (fragP
->fr_subtype
)
12586 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12587 extension
= 4; /* 1 opcode + 4 displacement */
12589 where_to_put_displacement
= &opcode
[1];
12592 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12593 extension
= 2; /* 1 opcode + 2 displacement */
12595 where_to_put_displacement
= &opcode
[1];
12598 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12599 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12600 extension
= 5; /* 2 opcode + 4 displacement */
12601 opcode
[1] = opcode
[0] + 0x10;
12602 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12603 where_to_put_displacement
= &opcode
[2];
12606 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12607 extension
= 3; /* 2 opcode + 2 displacement */
12608 opcode
[1] = opcode
[0] + 0x10;
12609 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12610 where_to_put_displacement
= &opcode
[2];
12613 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12618 where_to_put_displacement
= &opcode
[3];
12622 BAD_CASE (fragP
->fr_subtype
);
12627 /* If size if less then four we are sure that the operand fits,
12628 but if it's 4, then it could be that the displacement is larger
12630 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12632 && ((addressT
) (displacement_from_opcode_start
- extension
12633 + ((addressT
) 1 << 31))
12634 > (((addressT
) 2 << 31) - 1)))
12636 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12637 _("jump target out of range"));
12638 /* Make us emit 0. */
12639 displacement_from_opcode_start
= extension
;
12641 /* Now put displacement after opcode. */
12642 md_number_to_chars ((char *) where_to_put_displacement
,
12643 (valueT
) (displacement_from_opcode_start
- extension
),
12644 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12645 fragP
->fr_fix
+= extension
;
12648 /* Apply a fixup (fixP) to segment data, once it has been determined
12649 by our caller that we have all the info we need to fix it up.
12651 Parameter valP is the pointer to the value of the bits.
12653 On the 386, immediates, displacements, and data pointers are all in
12654 the same (little-endian) format, so we don't need to care about which
12655 we are handling. */
12658 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12660 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12661 valueT value
= *valP
;
12663 #if !defined (TE_Mach)
12664 if (fixP
->fx_pcrel
)
12666 switch (fixP
->fx_r_type
)
12672 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12675 case BFD_RELOC_X86_64_32S
:
12676 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12679 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12682 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12687 if (fixP
->fx_addsy
!= NULL
12688 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12689 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12690 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12691 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12692 && !use_rela_relocations
)
12694 /* This is a hack. There should be a better way to handle this.
12695 This covers for the fact that bfd_install_relocation will
12696 subtract the current location (for partial_inplace, PC relative
12697 relocations); see more below. */
12701 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12704 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12706 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12709 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12711 if ((sym_seg
== seg
12712 || (symbol_section_p (fixP
->fx_addsy
)
12713 && sym_seg
!= absolute_section
))
12714 && !generic_force_reloc (fixP
))
12716 /* Yes, we add the values in twice. This is because
12717 bfd_install_relocation subtracts them out again. I think
12718 bfd_install_relocation is broken, but I don't dare change
12720 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12724 #if defined (OBJ_COFF) && defined (TE_PE)
12725 /* For some reason, the PE format does not store a
12726 section address offset for a PC relative symbol. */
12727 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12728 || S_IS_WEAK (fixP
->fx_addsy
))
12729 value
+= md_pcrel_from (fixP
);
12732 #if defined (OBJ_COFF) && defined (TE_PE)
12733 if (fixP
->fx_addsy
!= NULL
12734 && S_IS_WEAK (fixP
->fx_addsy
)
12735 /* PR 16858: Do not modify weak function references. */
12736 && ! fixP
->fx_pcrel
)
12738 #if !defined (TE_PEP)
12739 /* For x86 PE weak function symbols are neither PC-relative
12740 nor do they set S_IS_FUNCTION. So the only reliable way
12741 to detect them is to check the flags of their containing
12743 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12744 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12748 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12752 /* Fix a few things - the dynamic linker expects certain values here,
12753 and we must not disappoint it. */
12754 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12755 if (IS_ELF
&& fixP
->fx_addsy
)
12756 switch (fixP
->fx_r_type
)
12758 case BFD_RELOC_386_PLT32
:
12759 case BFD_RELOC_X86_64_PLT32
:
12760 /* Make the jump instruction point to the address of the operand.
12761 At runtime we merely add the offset to the actual PLT entry.
12762 NB: Subtract the offset size only for jump instructions. */
12763 if (fixP
->fx_pcrel
)
12767 case BFD_RELOC_386_TLS_GD
:
12768 case BFD_RELOC_386_TLS_LDM
:
12769 case BFD_RELOC_386_TLS_IE_32
:
12770 case BFD_RELOC_386_TLS_IE
:
12771 case BFD_RELOC_386_TLS_GOTIE
:
12772 case BFD_RELOC_386_TLS_GOTDESC
:
12773 case BFD_RELOC_X86_64_TLSGD
:
12774 case BFD_RELOC_X86_64_TLSLD
:
12775 case BFD_RELOC_X86_64_GOTTPOFF
:
12776 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12777 value
= 0; /* Fully resolved at runtime. No addend. */
12779 case BFD_RELOC_386_TLS_LE
:
12780 case BFD_RELOC_386_TLS_LDO_32
:
12781 case BFD_RELOC_386_TLS_LE_32
:
12782 case BFD_RELOC_X86_64_DTPOFF32
:
12783 case BFD_RELOC_X86_64_DTPOFF64
:
12784 case BFD_RELOC_X86_64_TPOFF32
:
12785 case BFD_RELOC_X86_64_TPOFF64
:
12786 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12789 case BFD_RELOC_386_TLS_DESC_CALL
:
12790 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12791 value
= 0; /* Fully resolved at runtime. No addend. */
12792 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12796 case BFD_RELOC_VTABLE_INHERIT
:
12797 case BFD_RELOC_VTABLE_ENTRY
:
12804 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12806 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
12808 value
= extend_to_32bit_address (value
);
12811 #endif /* !defined (TE_Mach) */
12813 /* Are we finished with this relocation now? */
12814 if (fixP
->fx_addsy
== NULL
)
12817 switch (fixP
->fx_r_type
)
12819 case BFD_RELOC_X86_64_32S
:
12820 fixP
->fx_signed
= 1;
12827 #if defined (OBJ_COFF) && defined (TE_PE)
12828 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12831 /* Remember value for tc_gen_reloc. */
12832 fixP
->fx_addnumber
= value
;
12833 /* Clear out the frag for now. */
12837 else if (use_rela_relocations
)
12839 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
12840 fixP
->fx_no_overflow
= 1;
12841 /* Remember value for tc_gen_reloc. */
12842 fixP
->fx_addnumber
= value
;
12846 md_number_to_chars (p
, value
, fixP
->fx_size
);
12850 md_atof (int type
, char *litP
, int *sizeP
)
12852 /* This outputs the LITTLENUMs in REVERSE order;
12853 in accord with the bigendian 386. */
12854 return ieee_md_atof (type
, litP
, sizeP
, false);
12857 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12860 output_invalid (int c
)
12863 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12866 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12867 "(0x%x)", (unsigned char) c
);
12868 return output_invalid_buf
;
12871 /* Verify that @r can be used in the current context. */
12873 static bool check_register (const reg_entry
*r
)
12875 if (allow_pseudo_reg
)
12878 if (operand_type_all_zero (&r
->reg_type
))
12881 if ((r
->reg_type
.bitfield
.dword
12882 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12883 || r
->reg_type
.bitfield
.class == RegCR
12884 || r
->reg_type
.bitfield
.class == RegDR
)
12885 && !cpu_arch_flags
.bitfield
.cpui386
)
12888 if (r
->reg_type
.bitfield
.class == RegTR
12889 && (flag_code
== CODE_64BIT
12890 || !cpu_arch_flags
.bitfield
.cpui386
12891 || cpu_arch_isa_flags
.bitfield
.cpui586
12892 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12895 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12898 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12900 if (r
->reg_type
.bitfield
.zmmword
12901 || r
->reg_type
.bitfield
.class == RegMask
)
12904 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12906 if (r
->reg_type
.bitfield
.ymmword
)
12909 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12914 if (r
->reg_type
.bitfield
.tmmword
12915 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12916 || flag_code
!= CODE_64BIT
))
12919 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12922 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12923 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12926 /* Upper 16 vector registers are only available with VREX in 64bit
12927 mode, and require EVEX encoding. */
12928 if (r
->reg_flags
& RegVRex
)
12930 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12931 || flag_code
!= CODE_64BIT
)
12934 if (i
.vec_encoding
== vex_encoding_default
)
12935 i
.vec_encoding
= vex_encoding_evex
;
12936 else if (i
.vec_encoding
!= vex_encoding_evex
)
12937 i
.vec_encoding
= vex_encoding_error
;
12940 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12941 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12942 && flag_code
!= CODE_64BIT
)
12945 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12952 /* REG_STRING starts *before* REGISTER_PREFIX. */
12954 static const reg_entry
*
12955 parse_real_register (char *reg_string
, char **end_op
)
12957 char *s
= reg_string
;
12959 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12960 const reg_entry
*r
;
12962 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12963 if (*s
== REGISTER_PREFIX
)
12966 if (is_space_char (*s
))
12969 p
= reg_name_given
;
12970 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12972 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12973 return (const reg_entry
*) NULL
;
12977 /* For naked regs, make sure that we are not dealing with an identifier.
12978 This prevents confusing an identifier like `eax_var' with register
12980 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12981 return (const reg_entry
*) NULL
;
12985 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12987 /* Handle floating point regs, allowing spaces in the (i) part. */
12990 if (!cpu_arch_flags
.bitfield
.cpu8087
12991 && !cpu_arch_flags
.bitfield
.cpu287
12992 && !cpu_arch_flags
.bitfield
.cpu387
12993 && !allow_pseudo_reg
)
12994 return (const reg_entry
*) NULL
;
12996 if (is_space_char (*s
))
13001 if (is_space_char (*s
))
13003 if (*s
>= '0' && *s
<= '7')
13005 int fpr
= *s
- '0';
13007 if (is_space_char (*s
))
13012 know (r
[fpr
].reg_num
== fpr
);
13016 /* We have "%st(" then garbage. */
13017 return (const reg_entry
*) NULL
;
13021 return r
&& check_register (r
) ? r
: NULL
;
13024 /* REG_STRING starts *before* REGISTER_PREFIX. */
13026 static const reg_entry
*
13027 parse_register (char *reg_string
, char **end_op
)
13029 const reg_entry
*r
;
13031 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
13032 r
= parse_real_register (reg_string
, end_op
);
13037 char *save
= input_line_pointer
;
13041 input_line_pointer
= reg_string
;
13042 c
= get_symbol_name (®_string
);
13043 symbolP
= symbol_find (reg_string
);
13044 while (symbolP
&& S_GET_SEGMENT (symbolP
) != reg_section
)
13046 const expressionS
*e
= symbol_get_value_expression(symbolP
);
13048 if (e
->X_op
!= O_symbol
|| e
->X_add_number
)
13050 symbolP
= e
->X_add_symbol
;
13052 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
13054 const expressionS
*e
= symbol_get_value_expression (symbolP
);
13056 know (e
->X_op
== O_register
);
13057 know (e
->X_add_number
>= 0
13058 && (valueT
) e
->X_add_number
< i386_regtab_size
);
13059 r
= i386_regtab
+ e
->X_add_number
;
13060 if (!check_register (r
))
13062 as_bad (_("register '%s%s' cannot be used here"),
13063 register_prefix
, r
->reg_name
);
13066 *end_op
= input_line_pointer
;
13068 *input_line_pointer
= c
;
13069 input_line_pointer
= save
;
13075 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
13077 const reg_entry
*r
= NULL
;
13078 char *end
= input_line_pointer
;
13081 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
13082 r
= parse_real_register (name
, &input_line_pointer
);
13083 if (r
&& end
<= input_line_pointer
)
13085 *nextcharP
= *input_line_pointer
;
13086 *input_line_pointer
= 0;
13089 e
->X_op
= O_register
;
13090 e
->X_add_number
= r
- i386_regtab
;
13093 e
->X_op
= O_illegal
;
13096 input_line_pointer
= end
;
13098 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
13102 md_operand (expressionS
*e
)
13105 const reg_entry
*r
;
13107 switch (*input_line_pointer
)
13109 case REGISTER_PREFIX
:
13110 r
= parse_real_register (input_line_pointer
, &end
);
13113 e
->X_op
= O_register
;
13114 e
->X_add_number
= r
- i386_regtab
;
13115 input_line_pointer
= end
;
13120 gas_assert (intel_syntax
);
13121 end
= input_line_pointer
++;
13123 if (*input_line_pointer
== ']')
13125 ++input_line_pointer
;
13126 e
->X_op_symbol
= make_expr_symbol (e
);
13127 e
->X_add_symbol
= NULL
;
13128 e
->X_add_number
= 0;
13133 e
->X_op
= O_absent
;
13134 input_line_pointer
= end
;
13141 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13142 const char *md_shortopts
= "kVQ:sqnO::";
13144 const char *md_shortopts
= "qnO::";
13147 #define OPTION_32 (OPTION_MD_BASE + 0)
13148 #define OPTION_64 (OPTION_MD_BASE + 1)
13149 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
13150 #define OPTION_MARCH (OPTION_MD_BASE + 3)
13151 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
13152 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
13153 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
13154 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
13155 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
13156 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
13157 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
13158 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
13159 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
13160 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
13161 #define OPTION_X32 (OPTION_MD_BASE + 14)
13162 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
13163 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
13164 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
13165 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
13166 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
13167 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
13168 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
13169 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
13170 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
13171 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
13172 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
13173 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
13174 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
13175 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
13176 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
13177 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
13178 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
13179 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
13180 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
13181 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
13183 struct option md_longopts
[] =
13185 {"32", no_argument
, NULL
, OPTION_32
},
13186 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13187 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13188 {"64", no_argument
, NULL
, OPTION_64
},
13190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13191 {"x32", no_argument
, NULL
, OPTION_X32
},
13192 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
13193 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
13195 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
13196 {"march", required_argument
, NULL
, OPTION_MARCH
},
13197 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
13198 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
13199 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
13200 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
13201 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
13202 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
13203 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
13204 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
13205 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
13206 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
13207 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
13208 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
13209 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
13210 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
13211 # if defined (TE_PE) || defined (TE_PEP)
13212 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
13214 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
13215 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
13216 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
13217 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
13218 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
13219 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
13220 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
13221 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
13222 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
13223 {"mlfence-before-indirect-branch", required_argument
, NULL
,
13224 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
13225 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
13226 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
13227 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
13228 {NULL
, no_argument
, NULL
, 0}
13230 size_t md_longopts_size
= sizeof (md_longopts
);
13233 md_parse_option (int c
, const char *arg
)
13236 char *arch
, *next
, *saved
, *type
;
13241 optimize_align_code
= 0;
13245 quiet_warnings
= 1;
13248 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13249 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
13250 should be emitted or not. FIXME: Not implemented. */
13252 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
13256 /* -V: SVR4 argument to print version ID. */
13258 print_version_id ();
13261 /* -k: Ignore for FreeBSD compatibility. */
13266 /* -s: On i386 Solaris, this tells the native assembler to use
13267 .stab instead of .stab.excl. We always use .stab anyhow. */
13270 case OPTION_MSHARED
:
13274 case OPTION_X86_USED_NOTE
:
13275 if (strcasecmp (arg
, "yes") == 0)
13277 else if (strcasecmp (arg
, "no") == 0)
13280 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
13285 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13286 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13289 const char **list
, **l
;
13291 list
= bfd_target_list ();
13292 for (l
= list
; *l
!= NULL
; l
++)
13293 if (startswith (*l
, "elf64-x86-64")
13294 || strcmp (*l
, "coff-x86-64") == 0
13295 || strcmp (*l
, "pe-x86-64") == 0
13296 || strcmp (*l
, "pei-x86-64") == 0
13297 || strcmp (*l
, "mach-o-x86-64") == 0)
13299 default_arch
= "x86_64";
13303 as_fatal (_("no compiled in support for x86_64"));
13309 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13313 const char **list
, **l
;
13315 list
= bfd_target_list ();
13316 for (l
= list
; *l
!= NULL
; l
++)
13317 if (startswith (*l
, "elf32-x86-64"))
13319 default_arch
= "x86_64:32";
13323 as_fatal (_("no compiled in support for 32bit x86_64"));
13327 as_fatal (_("32bit x86_64 is only supported for ELF"));
13332 default_arch
= "i386";
13335 case OPTION_DIVIDE
:
13336 #ifdef SVR4_COMMENT_CHARS
13341 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13343 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13347 i386_comment_chars
= n
;
13353 saved
= xstrdup (arg
);
13355 /* Allow -march=+nosse. */
13361 as_fatal (_("invalid -march= option: `%s'"), arg
);
13362 next
= strchr (arch
, '+');
13365 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13367 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
13368 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
13371 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
13374 cpu_arch_name
= cpu_arch
[j
].name
;
13375 free (cpu_sub_arch_name
);
13376 cpu_sub_arch_name
= NULL
;
13377 cpu_arch_flags
= cpu_arch
[j
].enable
;
13378 cpu_arch_isa
= cpu_arch
[j
].type
;
13379 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
13380 if (!cpu_arch_tune_set
)
13382 cpu_arch_tune
= cpu_arch_isa
;
13383 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13387 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
13388 && strcmp (arch
, cpu_arch
[j
].name
) == 0
13389 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
13391 /* ISA extension. */
13392 i386_cpu_flags flags
;
13394 flags
= cpu_flags_or (cpu_arch_flags
,
13395 cpu_arch
[j
].enable
);
13397 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13399 extend_cpu_sub_arch_name (arch
);
13400 cpu_arch_flags
= flags
;
13401 cpu_arch_isa_flags
= flags
;
13405 = cpu_flags_or (cpu_arch_isa_flags
,
13406 cpu_arch
[j
].enable
);
13411 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
13413 /* Disable an ISA extension. */
13414 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13415 if (cpu_arch
[j
].type
== PROCESSOR_NONE
13416 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
13418 i386_cpu_flags flags
;
13420 flags
= cpu_flags_and_not (cpu_arch_flags
,
13421 cpu_arch
[j
].disable
);
13422 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13424 extend_cpu_sub_arch_name (arch
);
13425 cpu_arch_flags
= flags
;
13426 cpu_arch_isa_flags
= flags
;
13432 if (j
>= ARRAY_SIZE (cpu_arch
))
13433 as_fatal (_("invalid -march= option: `%s'"), arg
);
13437 while (next
!= NULL
);
13443 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13444 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13446 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
13447 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
13449 cpu_arch_tune_set
= 1;
13450 cpu_arch_tune
= cpu_arch
[j
].type
;
13451 cpu_arch_tune_flags
= cpu_arch
[j
].enable
;
13455 if (j
>= ARRAY_SIZE (cpu_arch
))
13456 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13459 case OPTION_MMNEMONIC
:
13460 if (strcasecmp (arg
, "att") == 0)
13461 intel_mnemonic
= 0;
13462 else if (strcasecmp (arg
, "intel") == 0)
13463 intel_mnemonic
= 1;
13465 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13468 case OPTION_MSYNTAX
:
13469 if (strcasecmp (arg
, "att") == 0)
13471 else if (strcasecmp (arg
, "intel") == 0)
13474 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13477 case OPTION_MINDEX_REG
:
13478 allow_index_reg
= 1;
13481 case OPTION_MNAKED_REG
:
13482 allow_naked_reg
= 1;
13485 case OPTION_MSSE2AVX
:
13489 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
13490 use_unaligned_vector_move
= 1;
13493 case OPTION_MSSE_CHECK
:
13494 if (strcasecmp (arg
, "error") == 0)
13495 sse_check
= check_error
;
13496 else if (strcasecmp (arg
, "warning") == 0)
13497 sse_check
= check_warning
;
13498 else if (strcasecmp (arg
, "none") == 0)
13499 sse_check
= check_none
;
13501 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13504 case OPTION_MOPERAND_CHECK
:
13505 if (strcasecmp (arg
, "error") == 0)
13506 operand_check
= check_error
;
13507 else if (strcasecmp (arg
, "warning") == 0)
13508 operand_check
= check_warning
;
13509 else if (strcasecmp (arg
, "none") == 0)
13510 operand_check
= check_none
;
13512 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13515 case OPTION_MAVXSCALAR
:
13516 if (strcasecmp (arg
, "128") == 0)
13517 avxscalar
= vex128
;
13518 else if (strcasecmp (arg
, "256") == 0)
13519 avxscalar
= vex256
;
13521 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13524 case OPTION_MVEXWIG
:
13525 if (strcmp (arg
, "0") == 0)
13527 else if (strcmp (arg
, "1") == 0)
13530 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13533 case OPTION_MADD_BND_PREFIX
:
13534 add_bnd_prefix
= 1;
13537 case OPTION_MEVEXLIG
:
13538 if (strcmp (arg
, "128") == 0)
13539 evexlig
= evexl128
;
13540 else if (strcmp (arg
, "256") == 0)
13541 evexlig
= evexl256
;
13542 else if (strcmp (arg
, "512") == 0)
13543 evexlig
= evexl512
;
13545 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13548 case OPTION_MEVEXRCIG
:
13549 if (strcmp (arg
, "rne") == 0)
13551 else if (strcmp (arg
, "rd") == 0)
13553 else if (strcmp (arg
, "ru") == 0)
13555 else if (strcmp (arg
, "rz") == 0)
13558 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13561 case OPTION_MEVEXWIG
:
13562 if (strcmp (arg
, "0") == 0)
13564 else if (strcmp (arg
, "1") == 0)
13567 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13570 # if defined (TE_PE) || defined (TE_PEP)
13571 case OPTION_MBIG_OBJ
:
13576 case OPTION_MOMIT_LOCK_PREFIX
:
13577 if (strcasecmp (arg
, "yes") == 0)
13578 omit_lock_prefix
= 1;
13579 else if (strcasecmp (arg
, "no") == 0)
13580 omit_lock_prefix
= 0;
13582 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13585 case OPTION_MFENCE_AS_LOCK_ADD
:
13586 if (strcasecmp (arg
, "yes") == 0)
13588 else if (strcasecmp (arg
, "no") == 0)
13591 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13594 case OPTION_MLFENCE_AFTER_LOAD
:
13595 if (strcasecmp (arg
, "yes") == 0)
13596 lfence_after_load
= 1;
13597 else if (strcasecmp (arg
, "no") == 0)
13598 lfence_after_load
= 0;
13600 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13603 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13604 if (strcasecmp (arg
, "all") == 0)
13606 lfence_before_indirect_branch
= lfence_branch_all
;
13607 if (lfence_before_ret
== lfence_before_ret_none
)
13608 lfence_before_ret
= lfence_before_ret_shl
;
13610 else if (strcasecmp (arg
, "memory") == 0)
13611 lfence_before_indirect_branch
= lfence_branch_memory
;
13612 else if (strcasecmp (arg
, "register") == 0)
13613 lfence_before_indirect_branch
= lfence_branch_register
;
13614 else if (strcasecmp (arg
, "none") == 0)
13615 lfence_before_indirect_branch
= lfence_branch_none
;
13617 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13621 case OPTION_MLFENCE_BEFORE_RET
:
13622 if (strcasecmp (arg
, "or") == 0)
13623 lfence_before_ret
= lfence_before_ret_or
;
13624 else if (strcasecmp (arg
, "not") == 0)
13625 lfence_before_ret
= lfence_before_ret_not
;
13626 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13627 lfence_before_ret
= lfence_before_ret_shl
;
13628 else if (strcasecmp (arg
, "none") == 0)
13629 lfence_before_ret
= lfence_before_ret_none
;
13631 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13635 case OPTION_MRELAX_RELOCATIONS
:
13636 if (strcasecmp (arg
, "yes") == 0)
13637 generate_relax_relocations
= 1;
13638 else if (strcasecmp (arg
, "no") == 0)
13639 generate_relax_relocations
= 0;
13641 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13644 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13647 long int align
= strtoul (arg
, &end
, 0);
13652 align_branch_power
= 0;
13655 else if (align
>= 16)
13658 for (align_power
= 0;
13660 align
>>= 1, align_power
++)
13662 /* Limit alignment power to 31. */
13663 if (align
== 1 && align_power
< 32)
13665 align_branch_power
= align_power
;
13670 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13674 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13677 int align
= strtoul (arg
, &end
, 0);
13678 /* Some processors only support 5 prefixes. */
13679 if (*end
== '\0' && align
>= 0 && align
< 6)
13681 align_branch_prefix_size
= align
;
13684 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13689 case OPTION_MALIGN_BRANCH
:
13691 saved
= xstrdup (arg
);
13695 next
= strchr (type
, '+');
13698 if (strcasecmp (type
, "jcc") == 0)
13699 align_branch
|= align_branch_jcc_bit
;
13700 else if (strcasecmp (type
, "fused") == 0)
13701 align_branch
|= align_branch_fused_bit
;
13702 else if (strcasecmp (type
, "jmp") == 0)
13703 align_branch
|= align_branch_jmp_bit
;
13704 else if (strcasecmp (type
, "call") == 0)
13705 align_branch
|= align_branch_call_bit
;
13706 else if (strcasecmp (type
, "ret") == 0)
13707 align_branch
|= align_branch_ret_bit
;
13708 else if (strcasecmp (type
, "indirect") == 0)
13709 align_branch
|= align_branch_indirect_bit
;
13711 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13714 while (next
!= NULL
);
13718 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13719 align_branch_power
= 5;
13720 align_branch_prefix_size
= 5;
13721 align_branch
= (align_branch_jcc_bit
13722 | align_branch_fused_bit
13723 | align_branch_jmp_bit
);
13726 case OPTION_MAMD64
:
13730 case OPTION_MINTEL64
:
13738 /* Turn off -Os. */
13739 optimize_for_space
= 0;
13741 else if (*arg
== 's')
13743 optimize_for_space
= 1;
13744 /* Turn on all encoding optimizations. */
13745 optimize
= INT_MAX
;
13749 optimize
= atoi (arg
);
13750 /* Turn off -Os. */
13751 optimize_for_space
= 0;
13761 #define MESSAGE_TEMPLATE \
13765 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13766 int *left_p
, const char *name
, int len
)
13768 int size
= sizeof (MESSAGE_TEMPLATE
);
13769 int left
= *left_p
;
13771 /* Reserve 2 spaces for ", " or ",\0" */
13774 /* Check if there is any room. */
13782 p
= mempcpy (p
, name
, len
);
13786 /* Output the current message now and start a new one. */
13789 fprintf (stream
, "%s\n", message
);
13791 left
= size
- (start
- message
) - len
- 2;
13793 gas_assert (left
>= 0);
13795 p
= mempcpy (p
, name
, len
);
13803 show_arch (FILE *stream
, int ext
, int check
)
13805 static char message
[] = MESSAGE_TEMPLATE
;
13806 char *start
= message
+ 27;
13808 int size
= sizeof (MESSAGE_TEMPLATE
);
13815 left
= size
- (start
- message
);
13819 p
= output_message (stream
, p
, message
, start
, &left
,
13820 STRING_COMMA_LEN ("default"));
13821 p
= output_message (stream
, p
, message
, start
, &left
,
13822 STRING_COMMA_LEN ("push"));
13823 p
= output_message (stream
, p
, message
, start
, &left
,
13824 STRING_COMMA_LEN ("pop"));
13827 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13829 /* Should it be skipped? */
13830 if (cpu_arch
[j
].skip
)
13833 name
= cpu_arch
[j
].name
;
13834 len
= cpu_arch
[j
].len
;
13835 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
13837 /* It is an extension. Skip if we aren't asked to show it. */
13838 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
13843 /* It is an processor. Skip if we show only extension. */
13846 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
13848 /* It is an impossible processor - skip. */
13852 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13855 /* Display disabled extensions. */
13857 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13861 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
13862 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
13864 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
13865 p
= output_message (stream
, p
, message
, start
, &left
, str
,
13871 fprintf (stream
, "%s\n", message
);
13875 md_show_usage (FILE *stream
)
13877 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13878 fprintf (stream
, _("\
13879 -Qy, -Qn ignored\n\
13880 -V print assembler version number\n\
13883 fprintf (stream
, _("\
13884 -n do not optimize code alignment\n\
13885 -O{012s} attempt some code optimizations\n\
13886 -q quieten some warnings\n"));
13887 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13888 fprintf (stream
, _("\
13892 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13893 fprintf (stream
, _("\
13894 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
13895 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
13896 fprintf (stream
, _("\
13897 --32/--64 generate 32bit/64bit object\n"));
13900 #ifdef SVR4_COMMENT_CHARS
13901 fprintf (stream
, _("\
13902 --divide do not treat `/' as a comment character\n"));
13904 fprintf (stream
, _("\
13905 --divide ignored\n"));
13907 fprintf (stream
, _("\
13908 -march=CPU[,+EXTENSION...]\n\
13909 generate code for CPU and EXTENSION, CPU is one of:\n"));
13910 show_arch (stream
, 0, 1);
13911 fprintf (stream
, _("\
13912 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
13913 show_arch (stream
, 1, 0);
13914 fprintf (stream
, _("\
13915 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13916 show_arch (stream
, 0, 0);
13917 fprintf (stream
, _("\
13918 -msse2avx encode SSE instructions with VEX prefix\n"));
13919 fprintf (stream
, _("\
13920 -muse-unaligned-vector-move\n\
13921 encode aligned vector move as unaligned vector move\n"));
13922 fprintf (stream
, _("\
13923 -msse-check=[none|error|warning] (default: warning)\n\
13924 check SSE instructions\n"));
13925 fprintf (stream
, _("\
13926 -moperand-check=[none|error|warning] (default: warning)\n\
13927 check operand combinations for validity\n"));
13928 fprintf (stream
, _("\
13929 -mavxscalar=[128|256] (default: 128)\n\
13930 encode scalar AVX instructions with specific vector\n\
13932 fprintf (stream
, _("\
13933 -mvexwig=[0|1] (default: 0)\n\
13934 encode VEX instructions with specific VEX.W value\n\
13935 for VEX.W bit ignored instructions\n"));
13936 fprintf (stream
, _("\
13937 -mevexlig=[128|256|512] (default: 128)\n\
13938 encode scalar EVEX instructions with specific vector\n\
13940 fprintf (stream
, _("\
13941 -mevexwig=[0|1] (default: 0)\n\
13942 encode EVEX instructions with specific EVEX.W value\n\
13943 for EVEX.W bit ignored instructions\n"));
13944 fprintf (stream
, _("\
13945 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13946 encode EVEX instructions with specific EVEX.RC value\n\
13947 for SAE-only ignored instructions\n"));
13948 fprintf (stream
, _("\
13949 -mmnemonic=[att|intel] "));
13950 if (SYSV386_COMPAT
)
13951 fprintf (stream
, _("(default: att)\n"));
13953 fprintf (stream
, _("(default: intel)\n"));
13954 fprintf (stream
, _("\
13955 use AT&T/Intel mnemonic\n"));
13956 fprintf (stream
, _("\
13957 -msyntax=[att|intel] (default: att)\n\
13958 use AT&T/Intel syntax\n"));
13959 fprintf (stream
, _("\
13960 -mindex-reg support pseudo index registers\n"));
13961 fprintf (stream
, _("\
13962 -mnaked-reg don't require `%%' prefix for registers\n"));
13963 fprintf (stream
, _("\
13964 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13965 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13966 fprintf (stream
, _("\
13967 -mshared disable branch optimization for shared code\n"));
13968 fprintf (stream
, _("\
13969 -mx86-used-note=[no|yes] "));
13970 if (DEFAULT_X86_USED_NOTE
)
13971 fprintf (stream
, _("(default: yes)\n"));
13973 fprintf (stream
, _("(default: no)\n"));
13974 fprintf (stream
, _("\
13975 generate x86 used ISA and feature properties\n"));
13977 #if defined (TE_PE) || defined (TE_PEP)
13978 fprintf (stream
, _("\
13979 -mbig-obj generate big object files\n"));
13981 fprintf (stream
, _("\
13982 -momit-lock-prefix=[no|yes] (default: no)\n\
13983 strip all lock prefixes\n"));
13984 fprintf (stream
, _("\
13985 -mfence-as-lock-add=[no|yes] (default: no)\n\
13986 encode lfence, mfence and sfence as\n\
13987 lock addl $0x0, (%%{re}sp)\n"));
13988 fprintf (stream
, _("\
13989 -mrelax-relocations=[no|yes] "));
13990 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13991 fprintf (stream
, _("(default: yes)\n"));
13993 fprintf (stream
, _("(default: no)\n"));
13994 fprintf (stream
, _("\
13995 generate relax relocations\n"));
13996 fprintf (stream
, _("\
13997 -malign-branch-boundary=NUM (default: 0)\n\
13998 align branches within NUM byte boundary\n"));
13999 fprintf (stream
, _("\
14000 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
14001 TYPE is combination of jcc, fused, jmp, call, ret,\n\
14003 specify types of branches to align\n"));
14004 fprintf (stream
, _("\
14005 -malign-branch-prefix-size=NUM (default: 5)\n\
14006 align branches with NUM prefixes per instruction\n"));
14007 fprintf (stream
, _("\
14008 -mbranches-within-32B-boundaries\n\
14009 align branches within 32 byte boundary\n"));
14010 fprintf (stream
, _("\
14011 -mlfence-after-load=[no|yes] (default: no)\n\
14012 generate lfence after load\n"));
14013 fprintf (stream
, _("\
14014 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
14015 generate lfence before indirect near branch\n"));
14016 fprintf (stream
, _("\
14017 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
14018 generate lfence before ret\n"));
14019 fprintf (stream
, _("\
14020 -mamd64 accept only AMD64 ISA [default]\n"));
14021 fprintf (stream
, _("\
14022 -mintel64 accept only Intel64 ISA\n"));
14025 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
14026 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14027 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14029 /* Pick the target format to use. */
14032 i386_target_format (void)
14034 if (startswith (default_arch
, "x86_64"))
14036 update_code_flag (CODE_64BIT
, 1);
14037 if (default_arch
[6] == '\0')
14038 x86_elf_abi
= X86_64_ABI
;
14040 x86_elf_abi
= X86_64_X32_ABI
;
14042 else if (!strcmp (default_arch
, "i386"))
14043 update_code_flag (CODE_32BIT
, 1);
14044 else if (!strcmp (default_arch
, "iamcu"))
14046 update_code_flag (CODE_32BIT
, 1);
14047 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
14049 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
14050 cpu_arch_name
= "iamcu";
14051 free (cpu_sub_arch_name
);
14052 cpu_sub_arch_name
= NULL
;
14053 cpu_arch_flags
= iamcu_flags
;
14054 cpu_arch_isa
= PROCESSOR_IAMCU
;
14055 cpu_arch_isa_flags
= iamcu_flags
;
14056 if (!cpu_arch_tune_set
)
14058 cpu_arch_tune
= cpu_arch_isa
;
14059 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
14062 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
14063 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
14067 as_fatal (_("unknown architecture"));
14069 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
14070 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
14071 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
14072 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
14074 switch (OUTPUT_FLAVOR
)
14076 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
14077 case bfd_target_aout_flavour
:
14078 return AOUT_TARGET_FORMAT
;
14080 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
14081 # if defined (TE_PE) || defined (TE_PEP)
14082 case bfd_target_coff_flavour
:
14083 if (flag_code
== CODE_64BIT
)
14086 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
14088 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
14089 # elif defined (TE_GO32)
14090 case bfd_target_coff_flavour
:
14091 return "coff-go32";
14093 case bfd_target_coff_flavour
:
14094 return "coff-i386";
14097 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14098 case bfd_target_elf_flavour
:
14100 const char *format
;
14102 switch (x86_elf_abi
)
14105 format
= ELF_TARGET_FORMAT
;
14107 tls_get_addr
= "___tls_get_addr";
14111 use_rela_relocations
= 1;
14114 tls_get_addr
= "__tls_get_addr";
14116 format
= ELF_TARGET_FORMAT64
;
14118 case X86_64_X32_ABI
:
14119 use_rela_relocations
= 1;
14122 tls_get_addr
= "__tls_get_addr";
14124 disallow_64bit_reloc
= 1;
14125 format
= ELF_TARGET_FORMAT32
;
14128 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
14130 if (x86_elf_abi
!= I386_ABI
)
14131 as_fatal (_("Intel MCU is 32bit only"));
14132 return ELF_TARGET_IAMCU_FORMAT
;
14138 #if defined (OBJ_MACH_O)
14139 case bfd_target_mach_o_flavour
:
14140 if (flag_code
== CODE_64BIT
)
14142 use_rela_relocations
= 1;
14144 return "mach-o-x86-64";
14147 return "mach-o-i386";
14155 #endif /* OBJ_MAYBE_ more than one */
14158 md_undefined_symbol (char *name
)
14160 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
14161 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
14162 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
14163 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
14167 if (symbol_find (name
))
14168 as_bad (_("GOT already in symbol table"));
14169 GOT_symbol
= symbol_new (name
, undefined_section
,
14170 &zero_address_frag
, 0);
14177 /* Round up a section size to the appropriate boundary. */
14180 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
14182 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
14183 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
14185 /* For a.out, force the section size to be aligned. If we don't do
14186 this, BFD will align it for us, but it will not write out the
14187 final bytes of the section. This may be a bug in BFD, but it is
14188 easier to fix it here since that is how the other a.out targets
14192 align
= bfd_section_alignment (segment
);
14193 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
14200 /* On the i386, PC-relative offsets are relative to the start of the
14201 next instruction. That is, the address of the offset, plus its
14202 size, since the offset is always the last part of the insn. */
14205 md_pcrel_from (fixS
*fixP
)
14207 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14213 s_bss (int ignore ATTRIBUTE_UNUSED
)
14217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14219 obj_elf_section_change_hook ();
14221 temp
= get_absolute_expression ();
14222 subseg_set (bss_section
, (subsegT
) temp
);
14223 demand_empty_rest_of_line ();
14228 /* Remember constant directive. */
14231 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
14233 if (last_insn
.kind
!= last_insn_directive
14234 && (bfd_section_flags (now_seg
) & SEC_CODE
))
14236 last_insn
.seg
= now_seg
;
14237 last_insn
.kind
= last_insn_directive
;
14238 last_insn
.name
= "constant directive";
14239 last_insn
.file
= as_where (&last_insn
.line
);
14240 if (lfence_before_ret
!= lfence_before_ret_none
)
14242 if (lfence_before_indirect_branch
!= lfence_branch_none
)
14243 as_warn (_("constant directive skips -mlfence-before-ret "
14244 "and -mlfence-before-indirect-branch"));
14246 as_warn (_("constant directive skips -mlfence-before-ret"));
14248 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
14249 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
14254 i386_validate_fix (fixS
*fixp
)
14256 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
14258 reloc_howto_type
*howto
;
14260 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
14261 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14262 _("invalid %s relocation against register"),
14263 howto
? howto
->name
: "<unknown>");
14267 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14268 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14269 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
14270 return IS_ELF
&& fixp
->fx_addsy
14271 && (!S_IS_DEFINED (fixp
->fx_addsy
)
14272 || S_IS_EXTERNAL (fixp
->fx_addsy
));
14275 if (fixp
->fx_subsy
)
14277 if (fixp
->fx_subsy
== GOT_symbol
)
14279 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
14283 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14284 if (fixp
->fx_tcbit2
)
14285 fixp
->fx_r_type
= (fixp
->fx_tcbit
14286 ? BFD_RELOC_X86_64_REX_GOTPCRELX
14287 : BFD_RELOC_X86_64_GOTPCRELX
);
14290 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
14295 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
14297 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
14299 fixp
->fx_subsy
= 0;
14302 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14305 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
14306 to section. Since PLT32 relocation must be against symbols,
14307 turn such PLT32 relocation into PC32 relocation. */
14309 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
14310 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
14311 && symbol_section_p (fixp
->fx_addsy
))
14312 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
14315 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
14316 && fixp
->fx_tcbit2
)
14317 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
14326 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14329 bfd_reloc_code_real_type code
;
14331 switch (fixp
->fx_r_type
)
14333 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14336 case BFD_RELOC_SIZE32
:
14337 case BFD_RELOC_SIZE64
:
14339 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
14340 && (!fixp
->fx_subsy
14341 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
14342 sym
= fixp
->fx_addsy
;
14343 else if (fixp
->fx_subsy
14344 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
14345 && (!fixp
->fx_addsy
14346 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
14347 sym
= fixp
->fx_subsy
;
14350 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
14352 /* Resolve size relocation against local symbol to size of
14353 the symbol plus addend. */
14354 valueT value
= S_GET_SIZE (sym
);
14356 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
14357 value
= bfd_section_size (S_GET_SEGMENT (sym
));
14358 if (sym
== fixp
->fx_subsy
)
14361 if (fixp
->fx_addsy
)
14362 value
+= S_GET_VALUE (fixp
->fx_addsy
);
14364 else if (fixp
->fx_subsy
)
14365 value
-= S_GET_VALUE (fixp
->fx_subsy
);
14366 value
+= fixp
->fx_offset
;
14367 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14369 && !fits_in_unsigned_long (value
))
14370 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14371 _("symbol size computation overflow"));
14372 fixp
->fx_addsy
= NULL
;
14373 fixp
->fx_subsy
= NULL
;
14374 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14377 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
14379 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14380 "unsupported expression involving @size");
14384 /* Fall through. */
14386 case BFD_RELOC_X86_64_PLT32
:
14387 case BFD_RELOC_X86_64_GOT32
:
14388 case BFD_RELOC_X86_64_GOTPCREL
:
14389 case BFD_RELOC_X86_64_GOTPCRELX
:
14390 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14391 case BFD_RELOC_386_PLT32
:
14392 case BFD_RELOC_386_GOT32
:
14393 case BFD_RELOC_386_GOT32X
:
14394 case BFD_RELOC_386_GOTOFF
:
14395 case BFD_RELOC_386_GOTPC
:
14396 case BFD_RELOC_386_TLS_GD
:
14397 case BFD_RELOC_386_TLS_LDM
:
14398 case BFD_RELOC_386_TLS_LDO_32
:
14399 case BFD_RELOC_386_TLS_IE_32
:
14400 case BFD_RELOC_386_TLS_IE
:
14401 case BFD_RELOC_386_TLS_GOTIE
:
14402 case BFD_RELOC_386_TLS_LE_32
:
14403 case BFD_RELOC_386_TLS_LE
:
14404 case BFD_RELOC_386_TLS_GOTDESC
:
14405 case BFD_RELOC_386_TLS_DESC_CALL
:
14406 case BFD_RELOC_X86_64_TLSGD
:
14407 case BFD_RELOC_X86_64_TLSLD
:
14408 case BFD_RELOC_X86_64_DTPOFF32
:
14409 case BFD_RELOC_X86_64_DTPOFF64
:
14410 case BFD_RELOC_X86_64_GOTTPOFF
:
14411 case BFD_RELOC_X86_64_TPOFF32
:
14412 case BFD_RELOC_X86_64_TPOFF64
:
14413 case BFD_RELOC_X86_64_GOTOFF64
:
14414 case BFD_RELOC_X86_64_GOTPC32
:
14415 case BFD_RELOC_X86_64_GOT64
:
14416 case BFD_RELOC_X86_64_GOTPCREL64
:
14417 case BFD_RELOC_X86_64_GOTPC64
:
14418 case BFD_RELOC_X86_64_GOTPLT64
:
14419 case BFD_RELOC_X86_64_PLTOFF64
:
14420 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14421 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14422 case BFD_RELOC_RVA
:
14423 case BFD_RELOC_VTABLE_ENTRY
:
14424 case BFD_RELOC_VTABLE_INHERIT
:
14426 case BFD_RELOC_32_SECREL
:
14427 case BFD_RELOC_16_SECIDX
:
14429 code
= fixp
->fx_r_type
;
14431 case BFD_RELOC_X86_64_32S
:
14432 if (!fixp
->fx_pcrel
)
14434 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14435 code
= fixp
->fx_r_type
;
14438 /* Fall through. */
14440 if (fixp
->fx_pcrel
)
14442 switch (fixp
->fx_size
)
14445 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14446 _("can not do %d byte pc-relative relocation"),
14448 code
= BFD_RELOC_32_PCREL
;
14450 case 1: code
= BFD_RELOC_8_PCREL
; break;
14451 case 2: code
= BFD_RELOC_16_PCREL
; break;
14452 case 4: code
= BFD_RELOC_32_PCREL
; break;
14454 case 8: code
= BFD_RELOC_64_PCREL
; break;
14460 switch (fixp
->fx_size
)
14463 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14464 _("can not do %d byte relocation"),
14466 code
= BFD_RELOC_32
;
14468 case 1: code
= BFD_RELOC_8
; break;
14469 case 2: code
= BFD_RELOC_16
; break;
14470 case 4: code
= BFD_RELOC_32
; break;
14472 case 8: code
= BFD_RELOC_64
; break;
14479 if ((code
== BFD_RELOC_32
14480 || code
== BFD_RELOC_32_PCREL
14481 || code
== BFD_RELOC_X86_64_32S
)
14483 && fixp
->fx_addsy
== GOT_symbol
)
14486 code
= BFD_RELOC_386_GOTPC
;
14488 code
= BFD_RELOC_X86_64_GOTPC32
;
14490 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14492 && fixp
->fx_addsy
== GOT_symbol
)
14494 code
= BFD_RELOC_X86_64_GOTPC64
;
14497 rel
= XNEW (arelent
);
14498 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14499 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14501 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14503 if (!use_rela_relocations
)
14505 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14506 vtable entry to be used in the relocation's section offset. */
14507 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14508 rel
->address
= fixp
->fx_offset
;
14509 #if defined (OBJ_COFF) && defined (TE_PE)
14510 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14511 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14516 /* Use the rela in 64bit mode. */
14519 if (disallow_64bit_reloc
)
14522 case BFD_RELOC_X86_64_DTPOFF64
:
14523 case BFD_RELOC_X86_64_TPOFF64
:
14524 case BFD_RELOC_64_PCREL
:
14525 case BFD_RELOC_X86_64_GOTOFF64
:
14526 case BFD_RELOC_X86_64_GOT64
:
14527 case BFD_RELOC_X86_64_GOTPCREL64
:
14528 case BFD_RELOC_X86_64_GOTPC64
:
14529 case BFD_RELOC_X86_64_GOTPLT64
:
14530 case BFD_RELOC_X86_64_PLTOFF64
:
14531 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14532 _("cannot represent relocation type %s in x32 mode"),
14533 bfd_get_reloc_code_name (code
));
14539 if (!fixp
->fx_pcrel
)
14540 rel
->addend
= fixp
->fx_offset
;
14544 case BFD_RELOC_X86_64_PLT32
:
14545 case BFD_RELOC_X86_64_GOT32
:
14546 case BFD_RELOC_X86_64_GOTPCREL
:
14547 case BFD_RELOC_X86_64_GOTPCRELX
:
14548 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14549 case BFD_RELOC_X86_64_TLSGD
:
14550 case BFD_RELOC_X86_64_TLSLD
:
14551 case BFD_RELOC_X86_64_GOTTPOFF
:
14552 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14553 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14554 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14557 rel
->addend
= (section
->vma
14559 + fixp
->fx_addnumber
14560 + md_pcrel_from (fixp
));
14565 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14566 if (rel
->howto
== NULL
)
14568 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14569 _("cannot represent relocation type %s"),
14570 bfd_get_reloc_code_name (code
));
14571 /* Set howto to a garbage value so that we can keep going. */
14572 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14573 gas_assert (rel
->howto
!= NULL
);
14579 #include "tc-i386-intel.c"
14582 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14584 int saved_naked_reg
;
14585 char saved_register_dot
;
14587 saved_naked_reg
= allow_naked_reg
;
14588 allow_naked_reg
= 1;
14589 saved_register_dot
= register_chars
['.'];
14590 register_chars
['.'] = '.';
14591 allow_pseudo_reg
= 1;
14592 expression_and_evaluate (exp
);
14593 allow_pseudo_reg
= 0;
14594 register_chars
['.'] = saved_register_dot
;
14595 allow_naked_reg
= saved_naked_reg
;
14597 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14599 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14601 exp
->X_op
= O_constant
;
14602 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14603 .dw2_regnum
[flag_code
>> 1];
14606 exp
->X_op
= O_illegal
;
14611 tc_x86_frame_initial_instructions (void)
14613 static unsigned int sp_regno
[2];
14615 if (!sp_regno
[flag_code
>> 1])
14617 char *saved_input
= input_line_pointer
;
14618 char sp
[][4] = {"esp", "rsp"};
14621 input_line_pointer
= sp
[flag_code
>> 1];
14622 tc_x86_parse_to_dw2regnum (&exp
);
14623 gas_assert (exp
.X_op
== O_constant
);
14624 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14625 input_line_pointer
= saved_input
;
14628 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14629 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14633 x86_dwarf2_addr_size (void)
14635 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14636 if (x86_elf_abi
== X86_64_X32_ABI
)
14639 return bfd_arch_bits_per_address (stdoutput
) / 8;
14643 i386_elf_section_type (const char *str
, size_t len
)
14645 if (flag_code
== CODE_64BIT
14646 && len
== sizeof ("unwind") - 1
14647 && startswith (str
, "unwind"))
14648 return SHT_X86_64_UNWIND
;
14655 i386_solaris_fix_up_eh_frame (segT sec
)
14657 if (flag_code
== CODE_64BIT
)
14658 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14664 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14668 exp
.X_op
= O_secrel
;
14669 exp
.X_add_symbol
= symbol
;
14670 exp
.X_add_number
= 0;
14671 emit_expr (&exp
, size
);
14675 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14676 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14679 x86_64_section_letter (int letter
, const char **ptr_msg
)
14681 if (flag_code
== CODE_64BIT
)
14684 return SHF_X86_64_LARGE
;
14686 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14689 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14694 x86_64_section_word (char *str
, size_t len
)
14696 if (len
== 5 && flag_code
== CODE_64BIT
&& startswith (str
, "large"))
14697 return SHF_X86_64_LARGE
;
14703 handle_large_common (int small ATTRIBUTE_UNUSED
)
14705 if (flag_code
!= CODE_64BIT
)
14707 s_comm_internal (0, elf_common_parse
);
14708 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14712 static segT lbss_section
;
14713 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14714 asection
*saved_bss_section
= bss_section
;
14716 if (lbss_section
== NULL
)
14718 flagword applicable
;
14719 segT seg
= now_seg
;
14720 subsegT subseg
= now_subseg
;
14722 /* The .lbss section is for local .largecomm symbols. */
14723 lbss_section
= subseg_new (".lbss", 0);
14724 applicable
= bfd_applicable_section_flags (stdoutput
);
14725 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14726 seg_info (lbss_section
)->bss
= 1;
14728 subseg_set (seg
, subseg
);
14731 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14732 bss_section
= lbss_section
;
14734 s_comm_internal (0, elf_common_parse
);
14736 elf_com_section_ptr
= saved_com_section_ptr
;
14737 bss_section
= saved_bss_section
;
14740 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */