1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
30 #include "safe-ctype.h"
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
55 static int fits_in_signed_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_word
PARAMS ((offsetT
));
58 static int fits_in_signed_word
PARAMS ((offsetT
));
59 static int fits_in_unsigned_long
PARAMS ((offsetT
));
60 static int fits_in_signed_long
PARAMS ((offsetT
));
61 static int smallest_imm_type
PARAMS ((offsetT
));
62 static offsetT offset_in_range
PARAMS ((offsetT
, int));
63 static int add_prefix
PARAMS ((unsigned int));
64 static void set_code_flag
PARAMS ((int));
65 static void set_16bit_gcc_code_flag
PARAMS ((int));
66 static void set_intel_syntax
PARAMS ((int));
67 static void set_cpu_arch
PARAMS ((int));
70 static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
72 #define RELOC_ENUM enum bfd_reloc_code_real
74 #define RELOC_ENUM int
78 #define DEFAULT_ARCH "i386"
80 static char *default_arch
= DEFAULT_ARCH
;
82 /* 'md_assemble ()' gathers together information and puts it into a
89 const reg_entry
*regs
;
94 /* TM holds the template for the insn were currently assembling. */
97 /* SUFFIX holds the instruction mnemonic suffix if given.
98 (e.g. 'l' for 'movl') */
101 /* OPERANDS gives the number of given operands. */
102 unsigned int operands
;
104 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
105 of given register, displacement, memory operands and immediate
107 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
109 /* TYPES [i] is the type (see above #defines) which tells us how to
110 use OP[i] for the corresponding operand. */
111 unsigned int types
[MAX_OPERANDS
];
113 /* Displacement expression, immediate expression, or register for each
115 union i386_op op
[MAX_OPERANDS
];
117 /* Flags for operands. */
118 unsigned int flags
[MAX_OPERANDS
];
119 #define Operand_PCrel 1
121 /* Relocation type for operand */
122 RELOC_ENUM reloc
[MAX_OPERANDS
];
124 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
125 the base index byte below. */
126 const reg_entry
*base_reg
;
127 const reg_entry
*index_reg
;
128 unsigned int log2_scale_factor
;
130 /* SEG gives the seg_entries of this insn. They are zero unless
131 explicit segment overrides are given. */
132 const seg_entry
*seg
[2];
134 /* PREFIX holds all the given prefix opcodes (usually null).
135 PREFIXES is the number of prefix opcodes. */
136 unsigned int prefixes
;
137 unsigned char prefix
[MAX_PREFIXES
];
139 /* RM and SIB are the modrm byte and the sib byte where the
140 addressing modes of this insn are encoded. */
147 typedef struct _i386_insn i386_insn
;
149 /* List of chars besides those in app.c:symbol_chars that can start an
150 operand. Used to prevent the scrubber eating vital white-space. */
152 const char extra_symbol_chars
[] = "*%-(@";
154 const char extra_symbol_chars
[] = "*%-(";
157 /* This array holds the chars that always start a comment. If the
158 pre-processor is disabled, these aren't very useful. */
159 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD) && !defined(TE_NetBSD))
160 /* Putting '/' here makes it impossible to use the divide operator.
161 However, we need it for compatibility with SVR4 systems. */
162 const char comment_chars
[] = "#/";
163 #define PREFIX_SEPARATOR '\\'
165 const char comment_chars
[] = "#";
166 #define PREFIX_SEPARATOR '/'
169 /* This array holds the chars that only start a comment at the beginning of
170 a line. If the line seems to have the form '# 123 filename'
171 .line and .file directives will appear in the pre-processed output.
172 Note that input_file.c hand checks for '#' at the beginning of the
173 first line of the input file. This is because the compiler outputs
174 #NO_APP at the beginning of its output.
175 Also note that comments started like this one will always work if
176 '/' isn't otherwise defined. */
177 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD) && !defined(TE_NetBSD))
178 const char line_comment_chars
[] = "";
180 const char line_comment_chars
[] = "/";
183 const char line_separator_chars
[] = ";";
185 /* Chars that can be used to separate mant from exp in floating point
187 const char EXP_CHARS
[] = "eE";
189 /* Chars that mean this number is a floating point constant
192 const char FLT_CHARS
[] = "fFdDxX";
194 /* Tables for lexical analysis. */
195 static char mnemonic_chars
[256];
196 static char register_chars
[256];
197 static char operand_chars
[256];
198 static char identifier_chars
[256];
199 static char digit_chars
[256];
201 /* Lexical macros. */
202 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
203 #define is_operand_char(x) (operand_chars[(unsigned char) x])
204 #define is_register_char(x) (register_chars[(unsigned char) x])
205 #define is_space_char(x) ((x) == ' ')
206 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
207 #define is_digit_char(x) (digit_chars[(unsigned char) x])
209 /* All non-digit non-letter charcters that may occur in an operand. */
210 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
212 /* md_assemble() always leaves the strings it's passed unaltered. To
213 effect this we maintain a stack of saved characters that we've smashed
214 with '\0's (indicating end of strings for various sub-fields of the
215 assembler instruction). */
216 static char save_stack
[32];
217 static char *save_stack_p
;
218 #define END_STRING_AND_SAVE(s) \
219 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
220 #define RESTORE_END_STRING(s) \
221 do { *(s) = *--save_stack_p; } while (0)
223 /* The instruction we're assembling. */
226 /* Possible templates for current insn. */
227 static const templates
*current_templates
;
229 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
230 static expressionS disp_expressions
[2], im_expressions
[2];
232 /* Current operand we are working on. */
233 static int this_operand
;
235 /* We support four different modes. FLAG_CODE variable is used to distinguish
242 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
244 static enum flag_code flag_code
;
245 static int use_rela_relocations
= 0;
247 /* The names used to print error messages. */
248 static const char *flag_code_names
[] =
255 /* 1 for intel syntax,
257 static int intel_syntax
= 0;
259 /* 1 if register prefix % not required. */
260 static int allow_naked_reg
= 0;
262 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
263 leave, push, and pop instructions so that gcc has the same stack
264 frame as in 32 bit mode. */
265 static char stackop_size
= '\0';
267 /* Non-zero to quieten some warnings. */
268 static int quiet_warnings
= 0;
271 static const char *cpu_arch_name
= NULL
;
273 /* CPU feature flags. */
274 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
276 /* If set, conditional jumps are not automatically promoted to handle
277 larger than a byte offset. */
278 static unsigned int no_cond_jump_promotion
= 0;
280 /* Interface to relax_segment.
281 There are 3 major relax states for 386 jump insns because the
282 different types of jumps add different sizes to frags when we're
283 figuring out what sort of jump to choose to reach a given label. */
286 #define UNCOND_JUMP 0
288 #define COND_JUMP86 2
293 #define SMALL16 (SMALL|CODE16)
295 #define BIG16 (BIG|CODE16)
299 #define INLINE __inline__
305 #define ENCODE_RELAX_STATE(type, size) \
306 ((relax_substateT) (((type) << 2) | (size)))
307 #define TYPE_FROM_RELAX_STATE(s) \
309 #define DISP_SIZE_FROM_RELAX_STATE(s) \
310 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
312 /* This table is used by relax_frag to promote short jumps to long
313 ones where necessary. SMALL (short) jumps may be promoted to BIG
314 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
315 don't allow a short jump in a 32 bit code segment to be promoted to
316 a 16 bit offset jump because it's slower (requires data size
317 prefix), and doesn't work, unless the destination is in the bottom
318 64k of the code segment (The top 16 bits of eip are zeroed). */
320 const relax_typeS md_relax_table
[] =
323 1) most positive reach of this state,
324 2) most negative reach of this state,
325 3) how many bytes this mode will have in the variable part of the frag
326 4) which index into the table to try if we can't fit into this one. */
328 /* UNCOND_JUMP states. */
329 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
330 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
331 /* dword jmp adds 4 bytes to frag:
332 0 extra opcode bytes, 4 displacement bytes. */
334 /* word jmp adds 2 byte2 to frag:
335 0 extra opcode bytes, 2 displacement bytes. */
338 /* COND_JUMP states. */
339 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
340 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
341 /* dword conditionals adds 5 bytes to frag:
342 1 extra opcode byte, 4 displacement bytes. */
344 /* word conditionals add 3 bytes to frag:
345 1 extra opcode byte, 2 displacement bytes. */
348 /* COND_JUMP86 states. */
349 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
350 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
351 /* dword conditionals adds 5 bytes to frag:
352 1 extra opcode byte, 4 displacement bytes. */
354 /* word conditionals add 4 bytes to frag:
355 1 displacement byte and a 3 byte long branch insn. */
359 static const arch_entry cpu_arch
[] = {
361 {"i186", Cpu086
|Cpu186
},
362 {"i286", Cpu086
|Cpu186
|Cpu286
},
363 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
364 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
365 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
366 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
367 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
368 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
369 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
370 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
371 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
372 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
377 i386_align_code (fragP
, count
)
381 /* Various efficient no-op patterns for aligning code labels.
382 Note: Don't try to assemble the instructions in the comments.
383 0L and 0w are not legal. */
384 static const char f32_1
[] =
386 static const char f32_2
[] =
387 {0x89,0xf6}; /* movl %esi,%esi */
388 static const char f32_3
[] =
389 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
390 static const char f32_4
[] =
391 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
392 static const char f32_5
[] =
394 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
395 static const char f32_6
[] =
396 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
397 static const char f32_7
[] =
398 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
399 static const char f32_8
[] =
401 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
402 static const char f32_9
[] =
403 {0x89,0xf6, /* movl %esi,%esi */
404 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
405 static const char f32_10
[] =
406 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
407 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
408 static const char f32_11
[] =
409 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
410 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
411 static const char f32_12
[] =
412 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
413 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
414 static const char f32_13
[] =
415 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
416 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
417 static const char f32_14
[] =
418 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
419 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
420 static const char f32_15
[] =
421 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
422 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
423 static const char f16_3
[] =
424 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
425 static const char f16_4
[] =
426 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
427 static const char f16_5
[] =
429 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
430 static const char f16_6
[] =
431 {0x89,0xf6, /* mov %si,%si */
432 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
433 static const char f16_7
[] =
434 {0x8d,0x74,0x00, /* lea 0(%si),%si */
435 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
436 static const char f16_8
[] =
437 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
438 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
439 static const char *const f32_patt
[] = {
440 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
441 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
443 static const char *const f16_patt
[] = {
444 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
445 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
448 /* ??? We can't use these fillers for x86_64, since they often kills the
449 upper halves. Solve later. */
450 if (flag_code
== CODE_64BIT
)
453 if (count
> 0 && count
<= 15)
455 if (flag_code
== CODE_16BIT
)
457 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
458 f16_patt
[count
- 1], count
);
460 /* Adjust jump offset. */
461 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
464 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
465 f32_patt
[count
- 1], count
);
466 fragP
->fr_var
= count
;
470 static char *output_invalid
PARAMS ((int c
));
471 static int i386_operand
PARAMS ((char *operand_string
));
472 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
473 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
477 static void s_bss
PARAMS ((int));
480 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
482 static INLINE
unsigned int
483 mode_from_disp_size (t
)
486 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
490 fits_in_signed_byte (num
)
493 return (num
>= -128) && (num
<= 127);
497 fits_in_unsigned_byte (num
)
500 return (num
& 0xff) == num
;
504 fits_in_unsigned_word (num
)
507 return (num
& 0xffff) == num
;
511 fits_in_signed_word (num
)
514 return (-32768 <= num
) && (num
<= 32767);
517 fits_in_signed_long (num
)
518 offsetT num ATTRIBUTE_UNUSED
;
523 return (!(((offsetT
) -1 << 31) & num
)
524 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
526 } /* fits_in_signed_long() */
528 fits_in_unsigned_long (num
)
529 offsetT num ATTRIBUTE_UNUSED
;
534 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
536 } /* fits_in_unsigned_long() */
539 smallest_imm_type (num
)
542 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
543 && !(cpu_arch_flags
& (CpuUnknown
)))
545 /* This code is disabled on the 486 because all the Imm1 forms
546 in the opcode table are slower on the i486. They're the
547 versions with the implicitly specified single-position
548 displacement, which has another syntax if you really want to
551 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
553 return (fits_in_signed_byte (num
)
554 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
555 : fits_in_unsigned_byte (num
)
556 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
557 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
558 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
559 : fits_in_signed_long (num
)
560 ? (Imm32
| Imm32S
| Imm64
)
561 : fits_in_unsigned_long (num
)
567 offset_in_range (val
, size
)
575 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
576 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
577 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
579 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
584 /* If BFD64, sign extend val. */
585 if (!use_rela_relocations
)
586 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
587 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
589 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
591 char buf1
[40], buf2
[40];
593 sprint_value (buf1
, val
);
594 sprint_value (buf2
, val
& mask
);
595 as_warn (_("%s shortened to %s"), buf1
, buf2
);
600 /* Returns 0 if attempting to add a prefix where one from the same
601 class already exists, 1 if non rep/repne added, 2 if rep/repne
610 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
618 case CS_PREFIX_OPCODE
:
619 case DS_PREFIX_OPCODE
:
620 case ES_PREFIX_OPCODE
:
621 case FS_PREFIX_OPCODE
:
622 case GS_PREFIX_OPCODE
:
623 case SS_PREFIX_OPCODE
:
627 case REPNE_PREFIX_OPCODE
:
628 case REPE_PREFIX_OPCODE
:
631 case LOCK_PREFIX_OPCODE
:
639 case ADDR_PREFIX_OPCODE
:
643 case DATA_PREFIX_OPCODE
:
650 as_bad (_("same type of prefix used twice"));
655 i
.prefix
[q
] = prefix
;
660 set_code_flag (value
)
664 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
665 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
666 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
668 as_bad (_("64bit mode not supported on this CPU."));
670 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
672 as_bad (_("32bit mode not supported on this CPU."));
678 set_16bit_gcc_code_flag (new_code_flag
)
681 flag_code
= new_code_flag
;
682 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
683 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
688 set_intel_syntax (syntax_flag
)
691 /* Find out if register prefixing is specified. */
692 int ask_naked_reg
= 0;
695 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
697 char *string
= input_line_pointer
;
698 int e
= get_symbol_end ();
700 if (strcmp (string
, "prefix") == 0)
702 else if (strcmp (string
, "noprefix") == 0)
705 as_bad (_("bad argument to syntax directive."));
706 *input_line_pointer
= e
;
708 demand_empty_rest_of_line ();
710 intel_syntax
= syntax_flag
;
712 if (ask_naked_reg
== 0)
715 allow_naked_reg
= (intel_syntax
716 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
718 /* Conservative default. */
723 allow_naked_reg
= (ask_naked_reg
< 0);
728 int dummy ATTRIBUTE_UNUSED
;
732 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
734 char *string
= input_line_pointer
;
735 int e
= get_symbol_end ();
738 for (i
= 0; cpu_arch
[i
].name
; i
++)
740 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
742 cpu_arch_name
= cpu_arch
[i
].name
;
743 cpu_arch_flags
= (cpu_arch
[i
].flags
744 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
748 if (!cpu_arch
[i
].name
)
749 as_bad (_("no such architecture: `%s'"), string
);
751 *input_line_pointer
= e
;
754 as_bad (_("missing cpu architecture"));
756 no_cond_jump_promotion
= 0;
757 if (*input_line_pointer
== ','
758 && ! is_end_of_line
[(unsigned char) input_line_pointer
[1]])
760 char *string
= ++input_line_pointer
;
761 int e
= get_symbol_end ();
763 if (strcmp (string
, "nojumps") == 0)
764 no_cond_jump_promotion
= 1;
765 else if (strcmp (string
, "jumps") == 0)
768 as_bad (_("no such architecture modifier: `%s'"), string
);
770 *input_line_pointer
= e
;
773 demand_empty_rest_of_line ();
776 const pseudo_typeS md_pseudo_table
[] =
778 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
779 {"align", s_align_bytes
, 0},
781 {"align", s_align_ptwo
, 0},
783 {"arch", set_cpu_arch
, 0},
787 {"ffloat", float_cons
, 'f'},
788 {"dfloat", float_cons
, 'd'},
789 {"tfloat", float_cons
, 'x'},
791 {"noopt", s_ignore
, 0},
792 {"optim", s_ignore
, 0},
793 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
794 {"code16", set_code_flag
, CODE_16BIT
},
795 {"code32", set_code_flag
, CODE_32BIT
},
796 {"code64", set_code_flag
, CODE_64BIT
},
797 {"intel_syntax", set_intel_syntax
, 1},
798 {"att_syntax", set_intel_syntax
, 0},
799 {"file", dwarf2_directive_file
, 0},
800 {"loc", dwarf2_directive_loc
, 0},
804 /* For interface with expression (). */
805 extern char *input_line_pointer
;
807 /* Hash table for instruction mnemonic lookup. */
808 static struct hash_control
*op_hash
;
810 /* Hash table for register lookup. */
811 static struct hash_control
*reg_hash
;
817 if (!strcmp (default_arch
, "x86_64"))
818 return bfd_mach_x86_64
;
819 else if (!strcmp (default_arch
, "i386"))
820 return bfd_mach_i386_i386
;
822 as_fatal (_("Unknown architecture"));
829 const char *hash_err
;
831 /* Initialize op_hash hash table. */
832 op_hash
= hash_new ();
835 register const template *optab
;
836 register templates
*core_optab
;
838 /* Setup for loop. */
840 core_optab
= (templates
*) xmalloc (sizeof (templates
));
841 core_optab
->start
= optab
;
846 if (optab
->name
== NULL
847 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
849 /* different name --> ship out current template list;
850 add to hash table; & begin anew. */
851 core_optab
->end
= optab
;
852 hash_err
= hash_insert (op_hash
,
857 as_fatal (_("Internal Error: Can't hash %s: %s"),
861 if (optab
->name
== NULL
)
863 core_optab
= (templates
*) xmalloc (sizeof (templates
));
864 core_optab
->start
= optab
;
869 /* Initialize reg_hash hash table. */
870 reg_hash
= hash_new ();
872 register const reg_entry
*regtab
;
874 for (regtab
= i386_regtab
;
875 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
878 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
880 as_fatal (_("Internal Error: Can't hash %s: %s"),
886 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
891 for (c
= 0; c
< 256; c
++)
896 mnemonic_chars
[c
] = c
;
897 register_chars
[c
] = c
;
898 operand_chars
[c
] = c
;
900 else if (ISLOWER (c
))
902 mnemonic_chars
[c
] = c
;
903 register_chars
[c
] = c
;
904 operand_chars
[c
] = c
;
906 else if (ISUPPER (c
))
908 mnemonic_chars
[c
] = TOLOWER (c
);
909 register_chars
[c
] = mnemonic_chars
[c
];
910 operand_chars
[c
] = c
;
913 if (ISALPHA (c
) || ISDIGIT (c
))
914 identifier_chars
[c
] = c
;
917 identifier_chars
[c
] = c
;
918 operand_chars
[c
] = c
;
923 identifier_chars
['@'] = '@';
925 digit_chars
['-'] = '-';
926 identifier_chars
['_'] = '_';
927 identifier_chars
['.'] = '.';
929 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
930 operand_chars
[(unsigned char) *p
] = *p
;
933 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
934 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
936 record_alignment (text_section
, 2);
937 record_alignment (data_section
, 2);
938 record_alignment (bss_section
, 2);
944 i386_print_statistics (file
)
947 hash_print_statistics (file
, "i386 opcode", op_hash
);
948 hash_print_statistics (file
, "i386 register", reg_hash
);
953 /* Debugging routines for md_assemble. */
954 static void pi
PARAMS ((char *, i386_insn
*));
955 static void pte
PARAMS ((template *));
956 static void pt
PARAMS ((unsigned int));
957 static void pe
PARAMS ((expressionS
*));
958 static void ps
PARAMS ((symbolS
*));
967 fprintf (stdout
, "%s: template ", line
);
969 fprintf (stdout
, " address: base %s index %s scale %x\n",
970 x
->base_reg
? x
->base_reg
->reg_name
: "none",
971 x
->index_reg
? x
->index_reg
->reg_name
: "none",
972 x
->log2_scale_factor
);
973 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
974 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
975 fprintf (stdout
, " sib: base %x index %x scale %x\n",
976 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
977 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
978 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
979 for (i
= 0; i
< x
->operands
; i
++)
981 fprintf (stdout
, " #%d: ", i
+ 1);
983 fprintf (stdout
, "\n");
985 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
986 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
987 if (x
->types
[i
] & Imm
)
989 if (x
->types
[i
] & Disp
)
999 fprintf (stdout
, " %d operands ", t
->operands
);
1000 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1001 if (t
->extension_opcode
!= None
)
1002 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1003 if (t
->opcode_modifier
& D
)
1004 fprintf (stdout
, "D");
1005 if (t
->opcode_modifier
& W
)
1006 fprintf (stdout
, "W");
1007 fprintf (stdout
, "\n");
1008 for (i
= 0; i
< t
->operands
; i
++)
1010 fprintf (stdout
, " #%d type ", i
+ 1);
1011 pt (t
->operand_types
[i
]);
1012 fprintf (stdout
, "\n");
1020 fprintf (stdout
, " operation %d\n", e
->X_op
);
1021 fprintf (stdout
, " add_number %ld (%lx)\n",
1022 (long) e
->X_add_number
, (long) e
->X_add_number
);
1023 if (e
->X_add_symbol
)
1025 fprintf (stdout
, " add_symbol ");
1026 ps (e
->X_add_symbol
);
1027 fprintf (stdout
, "\n");
1031 fprintf (stdout
, " op_symbol ");
1032 ps (e
->X_op_symbol
);
1033 fprintf (stdout
, "\n");
1041 fprintf (stdout
, "%s type %s%s",
1043 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1044 segment_name (S_GET_SEGMENT (s
)));
1066 { BaseIndex
, "BaseIndex" },
1070 { Disp32S
, "d32s" },
1072 { InOutPortReg
, "InOutPortReg" },
1073 { ShiftCount
, "ShiftCount" },
1074 { Control
, "control reg" },
1075 { Test
, "test reg" },
1076 { Debug
, "debug reg" },
1077 { FloatReg
, "FReg" },
1078 { FloatAcc
, "FAcc" },
1082 { JumpAbsolute
, "Jump Absolute" },
1093 register struct type_name
*ty
;
1095 for (ty
= type_names
; ty
->mask
; ty
++)
1097 fprintf (stdout
, "%s, ", ty
->tname
);
1101 #endif /* DEBUG386 */
1104 tc_i386_force_relocation (fixp
)
1107 #ifdef BFD_ASSEMBLER
1108 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1109 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1114 return fixp
->fx_r_type
== 7;
1118 #ifdef BFD_ASSEMBLER
1120 static bfd_reloc_code_real_type
1121 reloc (size
, pcrel
, sign
, other
)
1125 bfd_reloc_code_real_type other
;
1127 if (other
!= NO_RELOC
)
1133 as_bad (_("There are no unsigned pc-relative relocations"));
1136 case 1: return BFD_RELOC_8_PCREL
;
1137 case 2: return BFD_RELOC_16_PCREL
;
1138 case 4: return BFD_RELOC_32_PCREL
;
1140 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1147 case 4: return BFD_RELOC_X86_64_32S
;
1152 case 1: return BFD_RELOC_8
;
1153 case 2: return BFD_RELOC_16
;
1154 case 4: return BFD_RELOC_32
;
1155 case 8: return BFD_RELOC_64
;
1157 as_bad (_("can not do %s %d byte relocation"),
1158 sign
? "signed" : "unsigned", size
);
1162 return BFD_RELOC_NONE
;
1165 /* Here we decide which fixups can be adjusted to make them relative to
1166 the beginning of the section instead of the symbol. Basically we need
1167 to make sure that the dynamic relocations are done correctly, so in
1168 some cases we force the original symbol to be used. */
1171 tc_i386_fix_adjustable (fixP
)
1174 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1175 /* Prevent all adjustments to global symbols, or else dynamic
1176 linking will not work correctly. */
1177 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1178 || S_IS_WEAK (fixP
->fx_addsy
))
1181 /* adjust_reloc_syms doesn't know about the GOT. */
1182 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1183 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1184 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1185 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1186 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1187 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1188 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1189 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1194 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1195 #define BFD_RELOC_16 0
1196 #define BFD_RELOC_32 0
1197 #define BFD_RELOC_16_PCREL 0
1198 #define BFD_RELOC_32_PCREL 0
1199 #define BFD_RELOC_386_PLT32 0
1200 #define BFD_RELOC_386_GOT32 0
1201 #define BFD_RELOC_386_GOTOFF 0
1202 #define BFD_RELOC_X86_64_PLT32 0
1203 #define BFD_RELOC_X86_64_GOT32 0
1204 #define BFD_RELOC_X86_64_GOTPCREL 0
1207 static int intel_float_operand
PARAMS ((char *mnemonic
));
1210 intel_float_operand (mnemonic
)
1213 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1216 if (mnemonic
[0] == 'f')
1222 /* This is the guts of the machine-dependent assembler. LINE points to a
1223 machine dependent instruction. This function is supposed to emit
1224 the frags/bytes it assembles to. */
1230 /* Points to template once we've found it. */
1235 char mnemonic
[MAX_MNEM_SIZE
];
1237 /* Initialize globals. */
1238 memset (&i
, '\0', sizeof (i
));
1239 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1240 i
.reloc
[j
] = NO_RELOC
;
1241 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1242 memset (im_expressions
, '\0', sizeof (im_expressions
));
1243 save_stack_p
= save_stack
;
1245 /* First parse an instruction mnemonic & call i386_operand for the operands.
1246 We assume that the scrubber has arranged it so that line[0] is the valid
1247 start of a (possibly prefixed) mnemonic. */
1250 char *token_start
= l
;
1253 /* Non-zero if we found a prefix only acceptable with string insns. */
1254 const char *expecting_string_instruction
= NULL
;
1259 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1262 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1264 as_bad (_("no such instruction: `%s'"), token_start
);
1269 if (!is_space_char (*l
)
1270 && *l
!= END_OF_INSN
1271 && *l
!= PREFIX_SEPARATOR
1274 as_bad (_("invalid character %s in mnemonic"),
1275 output_invalid (*l
));
1278 if (token_start
== l
)
1280 if (*l
== PREFIX_SEPARATOR
)
1281 as_bad (_("expecting prefix; got nothing"));
1283 as_bad (_("expecting mnemonic; got nothing"));
1287 /* Look up instruction (or prefix) via hash table. */
1288 current_templates
= hash_find (op_hash
, mnemonic
);
1290 if (*l
!= END_OF_INSN
1291 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1292 && current_templates
1293 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1295 /* If we are in 16-bit mode, do not allow addr16 or data16.
1296 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1297 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1298 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1299 ^ (flag_code
== CODE_16BIT
)))
1301 as_bad (_("redundant %s prefix"),
1302 current_templates
->start
->name
);
1305 /* Add prefix, checking for repeated prefixes. */
1306 switch (add_prefix (current_templates
->start
->base_opcode
))
1311 expecting_string_instruction
= current_templates
->start
->name
;
1314 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1321 if (!current_templates
)
1323 /* See if we can get a match by trimming off a suffix. */
1326 case WORD_MNEM_SUFFIX
:
1327 case BYTE_MNEM_SUFFIX
:
1328 case QWORD_MNEM_SUFFIX
:
1329 i
.suffix
= mnem_p
[-1];
1331 current_templates
= hash_find (op_hash
, mnemonic
);
1333 case SHORT_MNEM_SUFFIX
:
1334 case LONG_MNEM_SUFFIX
:
1337 i
.suffix
= mnem_p
[-1];
1339 current_templates
= hash_find (op_hash
, mnemonic
);
1347 if (intel_float_operand (mnemonic
))
1348 i
.suffix
= SHORT_MNEM_SUFFIX
;
1350 i
.suffix
= LONG_MNEM_SUFFIX
;
1352 current_templates
= hash_find (op_hash
, mnemonic
);
1356 if (!current_templates
)
1358 as_bad (_("no such instruction: `%s'"), token_start
);
1363 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1365 /* Check for a branch hint. We allow ",pt" and ",pn" for
1366 predict taken and predict not taken respectively.
1367 I'm not sure that branch hints actually do anything on loop
1368 and jcxz insns (JumpByte) for current Pentium4 chips. They
1369 may work in the future and it doesn't hurt to accept them
1371 if (l
[0] == ',' && l
[1] == 'p')
1375 if (! add_prefix (DS_PREFIX_OPCODE
))
1379 else if (l
[2] == 'n')
1381 if (! add_prefix (CS_PREFIX_OPCODE
))
1387 /* Any other comma loses. */
1390 as_bad (_("invalid character %s in mnemonic"),
1391 output_invalid (*l
));
1395 /* Check if instruction is supported on specified architecture. */
1396 if (cpu_arch_flags
!= 0)
1398 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1399 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1401 as_warn (_("`%s' is not supported on `%s'"),
1402 current_templates
->start
->name
, cpu_arch_name
);
1404 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1406 as_warn (_("use .code16 to ensure correct addressing mode"));
1410 /* Check for rep/repne without a string instruction. */
1411 if (expecting_string_instruction
1412 && !(current_templates
->start
->opcode_modifier
& IsString
))
1414 as_bad (_("expecting string instruction after `%s'"),
1415 expecting_string_instruction
);
1419 /* There may be operands to parse. */
1420 if (*l
!= END_OF_INSN
)
1422 /* 1 if operand is pending after ','. */
1423 unsigned int expecting_operand
= 0;
1425 /* Non-zero if operand parens not balanced. */
1426 unsigned int paren_not_balanced
;
1430 /* Skip optional white space before operand. */
1431 if (is_space_char (*l
))
1433 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1435 as_bad (_("invalid character %s before operand %d"),
1436 output_invalid (*l
),
1440 token_start
= l
; /* after white space */
1441 paren_not_balanced
= 0;
1442 while (paren_not_balanced
|| *l
!= ',')
1444 if (*l
== END_OF_INSN
)
1446 if (paren_not_balanced
)
1449 as_bad (_("unbalanced parenthesis in operand %d."),
1452 as_bad (_("unbalanced brackets in operand %d."),
1457 break; /* we are done */
1459 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1461 as_bad (_("invalid character %s in operand %d"),
1462 output_invalid (*l
),
1469 ++paren_not_balanced
;
1471 --paren_not_balanced
;
1476 ++paren_not_balanced
;
1478 --paren_not_balanced
;
1482 if (l
!= token_start
)
1483 { /* Yes, we've read in another operand. */
1484 unsigned int operand_ok
;
1485 this_operand
= i
.operands
++;
1486 if (i
.operands
> MAX_OPERANDS
)
1488 as_bad (_("spurious operands; (%d operands/instruction max)"),
1492 /* Now parse operand adding info to 'i' as we go along. */
1493 END_STRING_AND_SAVE (l
);
1497 i386_intel_operand (token_start
,
1498 intel_float_operand (mnemonic
));
1500 operand_ok
= i386_operand (token_start
);
1502 RESTORE_END_STRING (l
);
1508 if (expecting_operand
)
1510 expecting_operand_after_comma
:
1511 as_bad (_("expecting operand after ','; got nothing"));
1516 as_bad (_("expecting operand before ','; got nothing"));
1521 /* Now *l must be either ',' or END_OF_INSN. */
1524 if (*++l
== END_OF_INSN
)
1526 /* Just skip it, if it's \n complain. */
1527 goto expecting_operand_after_comma
;
1529 expecting_operand
= 1;
1532 while (*l
!= END_OF_INSN
);
1536 /* Now we've parsed the mnemonic into a set of templates, and have the
1539 Next, we find a template that matches the given insn,
1540 making sure the overlap of the given operands types is consistent
1541 with the template operand types. */
1543 #define MATCH(overlap, given, template) \
1544 ((overlap & ~JumpAbsolute) \
1545 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1547 /* If given types r0 and r1 are registers they must be of the same type
1548 unless the expected operand type register overlap is null.
1549 Note that Acc in a template matches every size of reg. */
1550 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1551 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1552 ((g0) & Reg) == ((g1) & Reg) || \
1553 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1556 register unsigned int overlap0
, overlap1
;
1557 unsigned int overlap2
;
1558 unsigned int found_reverse_match
;
1561 /* All intel opcodes have reversed operands except for "bound" and
1562 "enter". We also don't reverse intersegment "jmp" and "call"
1563 instructions with 2 immediate operands so that the immediate segment
1564 precedes the offset, as it does when in AT&T mode. "enter" and the
1565 intersegment "jmp" and "call" instructions are the only ones that
1566 have two immediate operands. */
1567 if (intel_syntax
&& i
.operands
> 1
1568 && (strcmp (mnemonic
, "bound") != 0)
1569 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1571 union i386_op temp_op
;
1572 unsigned int temp_type
;
1573 RELOC_ENUM temp_reloc
;
1577 if (i
.operands
== 2)
1582 else if (i
.operands
== 3)
1587 temp_type
= i
.types
[xchg2
];
1588 i
.types
[xchg2
] = i
.types
[xchg1
];
1589 i
.types
[xchg1
] = temp_type
;
1590 temp_op
= i
.op
[xchg2
];
1591 i
.op
[xchg2
] = i
.op
[xchg1
];
1592 i
.op
[xchg1
] = temp_op
;
1593 temp_reloc
= i
.reloc
[xchg2
];
1594 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1595 i
.reloc
[xchg1
] = temp_reloc
;
1597 if (i
.mem_operands
== 2)
1599 const seg_entry
*temp_seg
;
1600 temp_seg
= i
.seg
[0];
1601 i
.seg
[0] = i
.seg
[1];
1602 i
.seg
[1] = temp_seg
;
1608 /* Try to ensure constant immediates are represented in the smallest
1610 char guess_suffix
= 0;
1614 guess_suffix
= i
.suffix
;
1615 else if (i
.reg_operands
)
1617 /* Figure out a suffix from the last register operand specified.
1618 We can't do this properly yet, ie. excluding InOutPortReg,
1619 but the following works for instructions with immediates.
1620 In any case, we can't set i.suffix yet. */
1621 for (op
= i
.operands
; --op
>= 0;)
1622 if (i
.types
[op
] & Reg
)
1624 if (i
.types
[op
] & Reg8
)
1625 guess_suffix
= BYTE_MNEM_SUFFIX
;
1626 else if (i
.types
[op
] & Reg16
)
1627 guess_suffix
= WORD_MNEM_SUFFIX
;
1628 else if (i
.types
[op
] & Reg32
)
1629 guess_suffix
= LONG_MNEM_SUFFIX
;
1630 else if (i
.types
[op
] & Reg64
)
1631 guess_suffix
= QWORD_MNEM_SUFFIX
;
1635 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1636 guess_suffix
= WORD_MNEM_SUFFIX
;
1638 for (op
= i
.operands
; --op
>= 0;)
1639 if (i
.types
[op
] & Imm
)
1641 switch (i
.op
[op
].imms
->X_op
)
1644 /* If a suffix is given, this operand may be shortened. */
1645 switch (guess_suffix
)
1647 case LONG_MNEM_SUFFIX
:
1648 i
.types
[op
] |= Imm32
| Imm64
;
1650 case WORD_MNEM_SUFFIX
:
1651 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1653 case BYTE_MNEM_SUFFIX
:
1654 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1658 /* If this operand is at most 16 bits, convert it
1659 to a signed 16 bit number before trying to see
1660 whether it will fit in an even smaller size.
1661 This allows a 16-bit operand such as $0xffe0 to
1662 be recognised as within Imm8S range. */
1663 if ((i
.types
[op
] & Imm16
)
1664 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1666 i
.op
[op
].imms
->X_add_number
=
1667 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1669 if ((i
.types
[op
] & Imm32
)
1670 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1672 i
.op
[op
].imms
->X_add_number
=
1673 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1675 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1676 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1677 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1678 i
.types
[op
] &= ~Imm32
;
1683 /* Symbols and expressions. */
1685 /* Convert symbolic operand to proper sizes for matching. */
1686 switch (guess_suffix
)
1688 case QWORD_MNEM_SUFFIX
:
1689 i
.types
[op
] = Imm64
| Imm32S
;
1691 case LONG_MNEM_SUFFIX
:
1692 i
.types
[op
] = Imm32
| Imm64
;
1694 case WORD_MNEM_SUFFIX
:
1695 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1698 case BYTE_MNEM_SUFFIX
:
1699 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1708 if (i
.disp_operands
)
1710 /* Try to use the smallest displacement type too. */
1713 for (op
= i
.operands
; --op
>= 0;)
1714 if ((i
.types
[op
] & Disp
)
1715 && i
.op
[op
].disps
->X_op
== O_constant
)
1717 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1719 if (i
.types
[op
] & Disp16
)
1721 /* We know this operand is at most 16 bits, so
1722 convert to a signed 16 bit number before trying
1723 to see whether it will fit in an even smaller
1726 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1728 else if (i
.types
[op
] & Disp32
)
1730 /* We know this operand is at most 32 bits, so convert to a
1731 signed 32 bit number before trying to see whether it will
1732 fit in an even smaller size. */
1733 disp
&= (((offsetT
) 2 << 31) - 1);
1734 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1736 if (flag_code
== CODE_64BIT
)
1738 if (fits_in_signed_long (disp
))
1739 i
.types
[op
] |= Disp32S
;
1740 if (fits_in_unsigned_long (disp
))
1741 i
.types
[op
] |= Disp32
;
1743 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1744 && fits_in_signed_byte (disp
))
1745 i
.types
[op
] |= Disp8
;
1752 found_reverse_match
= 0;
1753 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1755 : (i
.suffix
== WORD_MNEM_SUFFIX
1757 : (i
.suffix
== SHORT_MNEM_SUFFIX
1759 : (i
.suffix
== LONG_MNEM_SUFFIX
1761 : (i
.suffix
== QWORD_MNEM_SUFFIX
1763 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1765 for (t
= current_templates
->start
;
1766 t
< current_templates
->end
;
1769 /* Must have right number of operands. */
1770 if (i
.operands
!= t
->operands
)
1773 /* Check the suffix, except for some instructions in intel mode. */
1774 if ((t
->opcode_modifier
& suffix_check
)
1776 && (t
->opcode_modifier
& IgnoreSize
))
1778 && t
->base_opcode
== 0xd9
1779 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1780 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1783 /* Do not verify operands when there are none. */
1784 else if (!t
->operands
)
1786 if (t
->cpu_flags
& ~cpu_arch_flags
)
1788 /* We've found a match; break out of loop. */
1792 overlap0
= i
.types
[0] & t
->operand_types
[0];
1793 switch (t
->operands
)
1796 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1801 overlap1
= i
.types
[1] & t
->operand_types
[1];
1802 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1803 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1804 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1805 t
->operand_types
[0],
1806 overlap1
, i
.types
[1],
1807 t
->operand_types
[1]))
1809 /* Check if other direction is valid ... */
1810 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1813 /* Try reversing direction of operands. */
1814 overlap0
= i
.types
[0] & t
->operand_types
[1];
1815 overlap1
= i
.types
[1] & t
->operand_types
[0];
1816 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1817 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1818 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1819 t
->operand_types
[1],
1820 overlap1
, i
.types
[1],
1821 t
->operand_types
[0]))
1823 /* Does not match either direction. */
1826 /* found_reverse_match holds which of D or FloatDR
1828 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1830 /* Found a forward 2 operand match here. */
1831 else if (t
->operands
== 3)
1833 /* Here we make use of the fact that there are no
1834 reverse match 3 operand instructions, and all 3
1835 operand instructions only need to be checked for
1836 register consistency between operands 2 and 3. */
1837 overlap2
= i
.types
[2] & t
->operand_types
[2];
1838 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1839 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1840 t
->operand_types
[1],
1841 overlap2
, i
.types
[2],
1842 t
->operand_types
[2]))
1846 /* Found either forward/reverse 2 or 3 operand match here:
1847 slip through to break. */
1849 if (t
->cpu_flags
& ~cpu_arch_flags
)
1851 found_reverse_match
= 0;
1854 /* We've found a match; break out of loop. */
1857 if (t
== current_templates
->end
)
1859 /* We found no match. */
1860 as_bad (_("suffix or operands invalid for `%s'"),
1861 current_templates
->start
->name
);
1865 if (!quiet_warnings
)
1868 && ((i
.types
[0] & JumpAbsolute
)
1869 != (t
->operand_types
[0] & JumpAbsolute
)))
1871 as_warn (_("indirect %s without `*'"), t
->name
);
1874 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1875 == (IsPrefix
|IgnoreSize
))
1877 /* Warn them that a data or address size prefix doesn't
1878 affect assembly of the next line of code. */
1879 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1883 /* Copy the template we found. */
1885 if (found_reverse_match
)
1887 /* If we found a reverse match we must alter the opcode
1888 direction bit. found_reverse_match holds bits to change
1889 (different for int & float insns). */
1891 i
.tm
.base_opcode
^= found_reverse_match
;
1893 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1894 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1897 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1900 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1901 i
.tm
.base_opcode
^= FloatR
;
1903 if (i
.tm
.opcode_modifier
& FWait
)
1904 if (! add_prefix (FWAIT_OPCODE
))
1907 /* Check string instruction segment overrides. */
1908 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1910 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1911 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1913 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1915 as_bad (_("`%s' operand %d must use `%%es' segment"),
1920 /* There's only ever one segment override allowed per instruction.
1921 This instruction possibly has a legal segment override on the
1922 second operand, so copy the segment to where non-string
1923 instructions store it, allowing common code. */
1924 i
.seg
[0] = i
.seg
[1];
1926 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1928 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1930 as_bad (_("`%s' operand %d must use `%%es' segment"),
1938 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1941 for (op
= i
.operands
; --op
>= 0;)
1942 if ((i
.types
[op
] & Reg
)
1943 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1945 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1946 i
.op
[op
].regs
->reg_name
);
1951 /* If matched instruction specifies an explicit instruction mnemonic
1953 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1955 if (i
.tm
.opcode_modifier
& Size16
)
1956 i
.suffix
= WORD_MNEM_SUFFIX
;
1957 else if (i
.tm
.opcode_modifier
& Size64
)
1958 i
.suffix
= QWORD_MNEM_SUFFIX
;
1960 i
.suffix
= LONG_MNEM_SUFFIX
;
1962 else if (i
.reg_operands
)
1964 /* If there's no instruction mnemonic suffix we try to invent one
1965 based on register operands. */
1968 /* We take i.suffix from the last register operand specified,
1969 Destination register type is more significant than source
1972 for (op
= i
.operands
; --op
>= 0;)
1973 if ((i
.types
[op
] & Reg
)
1974 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1976 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1977 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1978 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1983 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1986 for (op
= i
.operands
; --op
>= 0;)
1988 /* If this is an eight bit register, it's OK. If it's
1989 the 16 or 32 bit version of an eight bit register,
1990 we will just use the low portion, and that's OK too. */
1991 if (i
.types
[op
] & Reg8
)
1994 /* movzx and movsx should not generate this warning. */
1996 && (i
.tm
.base_opcode
== 0xfb7
1997 || i
.tm
.base_opcode
== 0xfb6
1998 || i
.tm
.base_opcode
== 0x63
1999 || i
.tm
.base_opcode
== 0xfbe
2000 || i
.tm
.base_opcode
== 0xfbf))
2003 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
2005 /* Check that the template allows eight bit regs
2006 This kills insns such as `orb $1,%edx', which
2007 maybe should be allowed. */
2008 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
2012 /* Prohibit these changes in the 64bit mode, since
2013 the lowering is more complicated. */
2014 if (flag_code
== CODE_64BIT
2015 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2016 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2017 i
.op
[op
].regs
->reg_name
,
2019 #if REGISTER_WARNINGS
2021 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2022 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2024 + (i
.types
[op
] & Reg16
2025 ? REGNAM_AL
- REGNAM_AX
2026 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2027 i
.op
[op
].regs
->reg_name
,
2032 /* Any other register is bad. */
2033 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2035 | Control
| Debug
| Test
2036 | FloatReg
| FloatAcc
))
2038 as_bad (_("`%%%s' not allowed with `%s%c'"),
2039 i
.op
[op
].regs
->reg_name
,
2046 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2050 for (op
= i
.operands
; --op
>= 0;)
2051 /* Reject eight bit registers, except where the template
2052 requires them. (eg. movzb) */
2053 if ((i
.types
[op
] & Reg8
) != 0
2054 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2056 as_bad (_("`%%%s' not allowed with `%s%c'"),
2057 i
.op
[op
].regs
->reg_name
,
2062 /* Warn if the e prefix on a general reg is missing. */
2063 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2064 && (i
.types
[op
] & Reg16
) != 0
2065 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2067 /* Prohibit these changes in the 64bit mode, since
2068 the lowering is more complicated. */
2069 if (flag_code
== CODE_64BIT
)
2070 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2071 i
.op
[op
].regs
->reg_name
,
2073 #if REGISTER_WARNINGS
2075 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2076 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2077 i
.op
[op
].regs
->reg_name
,
2081 /* Warn if the r prefix on a general reg is missing. */
2082 else if ((i
.types
[op
] & Reg64
) != 0
2083 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2085 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2086 i
.op
[op
].regs
->reg_name
,
2090 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2094 for (op
= i
.operands
; --op
>= 0; )
2095 /* Reject eight bit registers, except where the template
2096 requires them. (eg. movzb) */
2097 if ((i
.types
[op
] & Reg8
) != 0
2098 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2100 as_bad (_("`%%%s' not allowed with `%s%c'"),
2101 i
.op
[op
].regs
->reg_name
,
2106 /* Warn if the e prefix on a general reg is missing. */
2107 else if (((i
.types
[op
] & Reg16
) != 0
2108 || (i
.types
[op
] & Reg32
) != 0)
2109 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2111 /* Prohibit these changes in the 64bit mode, since
2112 the lowering is more complicated. */
2113 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2114 i
.op
[op
].regs
->reg_name
,
2118 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2121 for (op
= i
.operands
; --op
>= 0;)
2122 /* Reject eight bit registers, except where the template
2123 requires them. (eg. movzb) */
2124 if ((i
.types
[op
] & Reg8
) != 0
2125 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2127 as_bad (_("`%%%s' not allowed with `%s%c'"),
2128 i
.op
[op
].regs
->reg_name
,
2133 /* Warn if the e prefix on a general reg is present. */
2134 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2135 && (i
.types
[op
] & Reg32
) != 0
2136 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2138 /* Prohibit these changes in the 64bit mode, since
2139 the lowering is more complicated. */
2140 if (flag_code
== CODE_64BIT
)
2141 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2142 i
.op
[op
].regs
->reg_name
,
2145 #if REGISTER_WARNINGS
2146 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2147 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2148 i
.op
[op
].regs
->reg_name
,
2153 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2154 /* Do nothing if the instruction is going to ignore the prefix. */
2159 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2161 i
.suffix
= stackop_size
;
2163 /* Make still unresolved immediate matches conform to size of immediate
2164 given in i.suffix. Note: overlap2 cannot be an immediate! */
2165 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2166 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2167 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2168 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2172 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2173 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2174 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2176 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2177 || overlap0
== (Imm16
| Imm32
)
2178 || overlap0
== (Imm16
| Imm32S
))
2181 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2183 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2184 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2185 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2187 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2191 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2192 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2193 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2194 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2198 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2199 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2200 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2202 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2203 || overlap1
== (Imm16
| Imm32
)
2204 || overlap1
== (Imm16
| Imm32S
))
2207 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2209 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2210 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2211 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2213 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2217 assert ((overlap2
& Imm
) == 0);
2219 i
.types
[0] = overlap0
;
2220 if (overlap0
& ImplicitRegister
)
2222 if (overlap0
& Imm1
)
2223 i
.imm_operands
= 0; /* kludge for shift insns. */
2225 i
.types
[1] = overlap1
;
2226 if (overlap1
& ImplicitRegister
)
2229 i
.types
[2] = overlap2
;
2230 if (overlap2
& ImplicitRegister
)
2233 /* Finalize opcode. First, we change the opcode based on the operand
2234 size given by i.suffix: We need not change things for byte insns. */
2236 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2238 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2242 /* For movzx and movsx, need to check the register type. */
2244 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2245 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2247 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2249 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2250 if (!add_prefix (prefix
))
2254 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2256 /* It's not a byte, select word/dword operation. */
2257 if (i
.tm
.opcode_modifier
& W
)
2259 if (i
.tm
.opcode_modifier
& ShortForm
)
2260 i
.tm
.base_opcode
|= 8;
2262 i
.tm
.base_opcode
|= 1;
2264 /* Now select between word & dword operations via the operand
2265 size prefix, except for instructions that will ignore this
2267 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2268 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2269 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2271 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2272 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2273 prefix
= ADDR_PREFIX_OPCODE
;
2275 if (! add_prefix (prefix
))
2279 /* Set mode64 for an operand. */
2280 if (i
.suffix
== QWORD_MNEM_SUFFIX
2281 && !(i
.tm
.opcode_modifier
& NoRex64
))
2284 if (flag_code
< CODE_64BIT
)
2286 as_bad (_("64bit operations available only in 64bit modes."));
2291 /* Size floating point instruction. */
2292 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2294 if (i
.tm
.opcode_modifier
& FloatMF
)
2295 i
.tm
.base_opcode
^= 4;
2299 if (i
.tm
.opcode_modifier
& ImmExt
)
2301 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2302 opcode suffix which is coded in the same place as an 8-bit
2303 immediate field would be. Here we fake an 8-bit immediate
2304 operand from the opcode suffix stored in tm.extension_opcode. */
2308 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2310 exp
= &im_expressions
[i
.imm_operands
++];
2311 i
.op
[i
.operands
].imms
= exp
;
2312 i
.types
[i
.operands
++] = Imm8
;
2313 exp
->X_op
= O_constant
;
2314 exp
->X_add_number
= i
.tm
.extension_opcode
;
2315 i
.tm
.extension_opcode
= None
;
2318 /* For insns with operands there are more diddles to do to the opcode. */
2321 /* Default segment register this instruction will use
2322 for memory accesses. 0 means unknown.
2323 This is only for optimizing out unnecessary segment overrides. */
2324 const seg_entry
*default_seg
= 0;
2326 /* The imul $imm, %reg instruction is converted into
2327 imul $imm, %reg, %reg, and the clr %reg instruction
2328 is converted into xor %reg, %reg. */
2329 if (i
.tm
.opcode_modifier
& regKludge
)
2331 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2332 /* Pretend we saw the extra register operand. */
2333 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2334 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2335 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2339 if (i
.tm
.opcode_modifier
& ShortForm
)
2341 /* The register or float register operand is in operand 0 or 1. */
2342 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2343 /* Register goes in low 3 bits of opcode. */
2344 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2345 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2347 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2349 /* Warn about some common errors, but press on regardless.
2350 The first case can be generated by gcc (<= 2.8.1). */
2351 if (i
.operands
== 2)
2353 /* Reversed arguments on faddp, fsubp, etc. */
2354 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2355 i
.op
[1].regs
->reg_name
,
2356 i
.op
[0].regs
->reg_name
);
2360 /* Extraneous `l' suffix on fp insn. */
2361 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2362 i
.op
[0].regs
->reg_name
);
2366 else if (i
.tm
.opcode_modifier
& Modrm
)
2368 /* The opcode is completed (modulo i.tm.extension_opcode which
2369 must be put into the modrm byte).
2370 Now, we make the modrm & index base bytes based on all the
2371 info we've collected. */
2373 /* i.reg_operands MUST be the number of real register operands;
2374 implicit registers do not count. */
2375 if (i
.reg_operands
== 2)
2377 unsigned int source
, dest
;
2378 source
= ((i
.types
[0]
2379 & (Reg
| RegMMX
| RegXMM
2381 | Control
| Debug
| Test
))
2386 /* One of the register operands will be encoded in the
2387 i.tm.reg field, the other in the combined i.tm.mode
2388 and i.tm.regmem fields. If no form of this
2389 instruction supports a memory destination operand,
2390 then we assume the source operand may sometimes be
2391 a memory operand and so we need to store the
2392 destination in the i.rm.reg field. */
2393 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2395 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2396 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2397 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2399 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2404 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2405 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2406 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2408 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2413 { /* If it's not 2 reg operands... */
2416 unsigned int fake_zero_displacement
= 0;
2417 unsigned int op
= ((i
.types
[0] & AnyMem
)
2419 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2426 if (! i
.disp_operands
)
2427 fake_zero_displacement
= 1;
2430 /* Operand is just <disp> */
2431 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2433 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2434 i
.types
[op
] &= ~Disp
;
2435 i
.types
[op
] |= Disp16
;
2437 else if (flag_code
!= CODE_64BIT
)
2439 i
.rm
.regmem
= NO_BASE_REGISTER
;
2440 i
.types
[op
] &= ~Disp
;
2441 i
.types
[op
] |= Disp32
;
2445 /* 64bit mode overwrites the 32bit
2446 absolute addressing by RIP relative
2447 addressing and absolute addressing
2448 is encoded by one of the redundant
2451 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2452 i
.sib
.base
= NO_BASE_REGISTER
;
2453 i
.sib
.index
= NO_INDEX_REGISTER
;
2454 i
.types
[op
] &= ~Disp
;
2455 i
.types
[op
] |= Disp32S
;
2458 else /* ! i.base_reg && i.index_reg */
2460 i
.sib
.index
= i
.index_reg
->reg_num
;
2461 i
.sib
.base
= NO_BASE_REGISTER
;
2462 i
.sib
.scale
= i
.log2_scale_factor
;
2463 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2464 i
.types
[op
] &= ~Disp
;
2465 if (flag_code
!= CODE_64BIT
)
2466 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2468 i
.types
[op
] |= Disp32S
;
2469 if (i
.index_reg
->reg_flags
& RegRex
)
2473 /* RIP addressing for 64bit mode. */
2474 else if (i
.base_reg
->reg_type
== BaseIndex
)
2476 i
.rm
.regmem
= NO_BASE_REGISTER
;
2477 i
.types
[op
] &= ~Disp
;
2478 i
.types
[op
] |= Disp32S
;
2479 i
.flags
[op
] = Operand_PCrel
;
2481 else if (i
.base_reg
->reg_type
& Reg16
)
2483 switch (i
.base_reg
->reg_num
)
2488 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2489 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2496 if ((i
.types
[op
] & Disp
) == 0)
2498 /* fake (%bp) into 0(%bp) */
2499 i
.types
[op
] |= Disp8
;
2500 fake_zero_displacement
= 1;
2503 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2504 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2506 default: /* (%si) -> 4 or (%di) -> 5 */
2507 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2509 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2511 else /* i.base_reg and 32/64 bit mode */
2513 if (flag_code
== CODE_64BIT
2514 && (i
.types
[op
] & Disp
))
2516 if (i
.types
[op
] & Disp8
)
2517 i
.types
[op
] = Disp8
| Disp32S
;
2519 i
.types
[op
] = Disp32S
;
2521 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2522 if (i
.base_reg
->reg_flags
& RegRex
)
2524 i
.sib
.base
= i
.base_reg
->reg_num
;
2525 /* x86-64 ignores REX prefix bit here to avoid
2526 decoder complications. */
2527 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2530 if (i
.disp_operands
== 0)
2532 fake_zero_displacement
= 1;
2533 i
.types
[op
] |= Disp8
;
2536 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2540 i
.sib
.scale
= i
.log2_scale_factor
;
2543 /* <disp>(%esp) becomes two byte modrm
2544 with no index register. We've already
2545 stored the code for esp in i.rm.regmem
2546 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2547 base register besides %esp will not use
2548 the extra modrm byte. */
2549 i
.sib
.index
= NO_INDEX_REGISTER
;
2550 #if ! SCALE1_WHEN_NO_INDEX
2551 /* Another case where we force the second
2553 if (i
.log2_scale_factor
)
2554 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2559 i
.sib
.index
= i
.index_reg
->reg_num
;
2560 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2561 if (i
.index_reg
->reg_flags
& RegRex
)
2564 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2567 if (fake_zero_displacement
)
2569 /* Fakes a zero displacement assuming that i.types[op]
2570 holds the correct displacement size. */
2573 assert (i
.op
[op
].disps
== 0);
2574 exp
= &disp_expressions
[i
.disp_operands
++];
2575 i
.op
[op
].disps
= exp
;
2576 exp
->X_op
= O_constant
;
2577 exp
->X_add_number
= 0;
2578 exp
->X_add_symbol
= (symbolS
*) 0;
2579 exp
->X_op_symbol
= (symbolS
*) 0;
2583 /* Fill in i.rm.reg or i.rm.regmem field with register
2584 operand (if any) based on i.tm.extension_opcode.
2585 Again, we must be careful to make sure that
2586 segment/control/debug/test/MMX registers are coded
2587 into the i.rm.reg field. */
2592 & (Reg
| RegMMX
| RegXMM
2594 | Control
| Debug
| Test
))
2597 & (Reg
| RegMMX
| RegXMM
2599 | Control
| Debug
| Test
))
2602 /* If there is an extension opcode to put here, the
2603 register number must be put into the regmem field. */
2604 if (i
.tm
.extension_opcode
!= None
)
2606 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2607 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2612 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2613 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2617 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2618 we must set it to 3 to indicate this is a register
2619 operand in the regmem field. */
2620 if (!i
.mem_operands
)
2624 /* Fill in i.rm.reg field with extension opcode (if any). */
2625 if (i
.tm
.extension_opcode
!= None
)
2626 i
.rm
.reg
= i
.tm
.extension_opcode
;
2629 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2631 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2632 && i
.op
[0].regs
->reg_num
== 1)
2634 as_bad (_("you can't `pop %%cs'"));
2637 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2638 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2641 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2645 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2647 /* For the string instructions that allow a segment override
2648 on one of their operands, the default segment is ds. */
2652 /* If a segment was explicitly specified,
2653 and the specified segment is not the default,
2654 use an opcode prefix to select it.
2655 If we never figured out what the default segment is,
2656 then default_seg will be zero at this point,
2657 and the specified segment prefix will always be used. */
2658 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2660 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2664 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2666 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2667 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2671 /* Handle conversion of 'int $3' --> special int3 insn. */
2672 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2674 i
.tm
.base_opcode
= INT3_OPCODE
;
2678 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2679 && i
.op
[0].disps
->X_op
== O_constant
)
2681 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2682 the absolute address given by the constant. Since ix86 jumps and
2683 calls are pc relative, we need to generate a reloc. */
2684 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2685 i
.op
[0].disps
->X_op
= O_symbol
;
2688 if (i
.tm
.opcode_modifier
& Rex64
)
2691 /* For 8bit registers we would need an empty rex prefix.
2692 Also in the case instruction is already having prefix,
2693 we need to convert old registers to new ones. */
2695 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2696 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2697 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2698 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2702 for (x
= 0; x
< 2; x
++)
2704 /* Look for 8bit operand that does use old registers. */
2705 if (i
.types
[x
] & Reg8
2706 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2708 /* In case it is "hi" register, give up. */
2709 if (i
.op
[x
].regs
->reg_num
> 3)
2710 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2711 i
.op
[x
].regs
->reg_name
);
2713 /* Otherwise it is equivalent to the extended register.
2714 Since the encoding don't change this is merely cosmetical
2715 cleanup for debug output. */
2717 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2722 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2724 | (i
.rex
.mode64
? 8 : 0)
2725 | (i
.rex
.extX
? 4 : 0)
2726 | (i
.rex
.extY
? 2 : 0)
2727 | (i
.rex
.extZ
? 1 : 0));
2729 /* We are ready to output the insn. */
2733 /* Tie dwarf2 debug info to the address at the start of the insn.
2734 We can't do this after the insn has been output as the current
2735 frag may have been closed off. eg. by frag_var. */
2736 dwarf2_emit_insn (0);
2739 if (i
.tm
.opcode_modifier
& Jump
)
2743 relax_substateT subtype
;
2748 if (flag_code
== CODE_16BIT
)
2752 if (i
.prefix
[DATA_PREFIX
])
2758 /* Pentium4 branch hints. */
2759 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2760 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2765 if (i
.prefix
[REX_PREFIX
])
2771 if (i
.prefixes
!= 0 && !intel_syntax
)
2772 as_warn (_("skipping prefixes on this instruction"));
2774 /* It's always a symbol; End frag & setup for relax.
2775 Make sure there is enough room in this frag for the largest
2776 instruction we may generate in md_convert_frag. This is 2
2777 bytes for the opcode and room for the prefix and largest
2779 frag_grow (prefix
+ 2 + 4);
2780 /* Prefix and 1 opcode byte go in fr_fix. */
2781 p
= frag_more (prefix
+ 1);
2782 if (i
.prefix
[DATA_PREFIX
])
2783 *p
++ = DATA_PREFIX_OPCODE
;
2784 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2785 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2786 *p
++ = i
.prefix
[SEG_PREFIX
];
2787 if (i
.prefix
[REX_PREFIX
])
2788 *p
++ = i
.prefix
[REX_PREFIX
];
2789 *p
= i
.tm
.base_opcode
;
2791 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2792 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2793 else if ((cpu_arch_flags
& Cpu386
) != 0)
2794 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2796 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
2799 sym
= i
.op
[0].disps
->X_add_symbol
;
2800 off
= i
.op
[0].disps
->X_add_number
;
2802 if (i
.op
[0].disps
->X_op
!= O_constant
2803 && i
.op
[0].disps
->X_op
!= O_symbol
)
2805 /* Handle complex expressions. */
2806 sym
= make_expr_symbol (i
.op
[0].disps
);
2810 /* 1 possible extra opcode + 4 byte displacement go in var part.
2811 Pass reloc in fr_var. */
2812 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
2814 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2818 if (i
.tm
.opcode_modifier
& JumpByte
)
2820 /* This is a loop or jecxz type instruction. */
2822 if (i
.prefix
[ADDR_PREFIX
])
2824 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2827 /* Pentium4 branch hints. */
2828 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2829 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2831 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
2840 if (flag_code
== CODE_16BIT
)
2843 if (i
.prefix
[DATA_PREFIX
])
2845 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2855 if (i
.prefix
[REX_PREFIX
])
2857 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2861 if (i
.prefixes
!= 0 && !intel_syntax
)
2862 as_warn (_("skipping prefixes on this instruction"));
2864 p
= frag_more (1 + size
);
2865 *p
++ = i
.tm
.base_opcode
;
2867 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2868 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
2870 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2877 if (flag_code
== CODE_16BIT
)
2881 if (i
.prefix
[DATA_PREFIX
])
2887 if (i
.prefix
[REX_PREFIX
])
2897 if (i
.prefixes
!= 0 && !intel_syntax
)
2898 as_warn (_("skipping prefixes on this instruction"));
2900 /* 1 opcode; 2 segment; offset */
2901 p
= frag_more (prefix
+ 1 + 2 + size
);
2903 if (i
.prefix
[DATA_PREFIX
])
2904 *p
++ = DATA_PREFIX_OPCODE
;
2906 if (i
.prefix
[REX_PREFIX
])
2907 *p
++ = i
.prefix
[REX_PREFIX
];
2909 *p
++ = i
.tm
.base_opcode
;
2910 if (i
.op
[1].imms
->X_op
== O_constant
)
2912 offsetT n
= i
.op
[1].imms
->X_add_number
;
2915 && !fits_in_unsigned_word (n
)
2916 && !fits_in_signed_word (n
))
2918 as_bad (_("16-bit jump out of range"));
2921 md_number_to_chars (p
, n
, size
);
2924 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2925 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
2926 if (i
.op
[0].imms
->X_op
!= O_constant
)
2927 as_bad (_("can't handle non absolute segment in `%s'"),
2929 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2933 /* Output normal instructions here. */
2936 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2937 byte for the SSE instructions to specify prefix they require. */
2938 if (i
.tm
.base_opcode
& 0xff0000)
2939 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2941 /* The prefix bytes. */
2943 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2949 md_number_to_chars (p
, (valueT
) *q
, 1);
2953 /* Now the opcode; be careful about word order here! */
2954 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2956 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2961 /* Put out high byte first: can't use md_number_to_chars! */
2962 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2963 *p
= i
.tm
.base_opcode
& 0xff;
2966 /* Now the modrm byte and sib byte (if present). */
2967 if (i
.tm
.opcode_modifier
& Modrm
)
2970 md_number_to_chars (p
,
2971 (valueT
) (i
.rm
.regmem
<< 0
2975 /* If i.rm.regmem == ESP (4)
2976 && i.rm.mode != (Register mode)
2978 ==> need second modrm byte. */
2979 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2981 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2984 md_number_to_chars (p
,
2985 (valueT
) (i
.sib
.base
<< 0
2987 | i
.sib
.scale
<< 6),
2992 if (i
.disp_operands
)
2994 register unsigned int n
;
2996 for (n
= 0; n
< i
.operands
; n
++)
2998 if (i
.types
[n
] & Disp
)
3000 if (i
.op
[n
].disps
->X_op
== O_constant
)
3006 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3009 if (i
.types
[n
] & Disp8
)
3011 if (i
.types
[n
] & Disp64
)
3014 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3016 p
= frag_more (size
);
3017 md_number_to_chars (p
, val
, size
);
3023 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3025 /* The PC relative address is computed relative
3026 to the instruction boundary, so in case immediate
3027 fields follows, we need to adjust the value. */
3028 if (pcrel
&& i
.imm_operands
)
3031 register unsigned int n1
;
3033 for (n1
= 0; n1
< i
.operands
; n1
++)
3034 if (i
.types
[n1
] & Imm
)
3036 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3039 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3041 if (i
.types
[n1
] & Imm64
)
3046 /* We should find the immediate. */
3047 if (n1
== i
.operands
)
3049 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3052 if (i
.types
[n
] & Disp32S
)
3055 if (i
.types
[n
] & (Disp16
| Disp64
))
3058 if (i
.types
[n
] & Disp64
)
3062 p
= frag_more (size
);
3063 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3064 i
.op
[n
].disps
, pcrel
,
3065 reloc (size
, pcrel
, sign
, i
.reloc
[n
]));
3071 /* Output immediate. */
3074 register unsigned int n
;
3076 for (n
= 0; n
< i
.operands
; n
++)
3078 if (i
.types
[n
] & Imm
)
3080 if (i
.op
[n
].imms
->X_op
== O_constant
)
3086 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3089 if (i
.types
[n
] & (Imm8
| Imm8S
))
3091 else if (i
.types
[n
] & Imm64
)
3094 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3096 p
= frag_more (size
);
3097 md_number_to_chars (p
, val
, size
);
3101 /* Not absolute_section.
3102 Need a 32-bit fixup (don't support 8bit
3103 non-absolute imms). Try to support other
3105 RELOC_ENUM reloc_type
;
3109 if ((i
.types
[n
] & (Imm32S
))
3110 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3112 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3115 if (i
.types
[n
] & (Imm8
| Imm8S
))
3117 if (i
.types
[n
] & Imm64
)
3121 p
= frag_more (size
);
3122 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3123 #ifdef BFD_ASSEMBLER
3124 if (reloc_type
== BFD_RELOC_32
3126 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3127 && (i
.op
[n
].imms
->X_op
== O_symbol
3128 || (i
.op
[n
].imms
->X_op
== O_add
3129 && ((symbol_get_value_expression
3130 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3133 /* We don't support dynamic linking on x86-64 yet. */
3134 if (flag_code
== CODE_64BIT
)
3136 reloc_type
= BFD_RELOC_386_GOTPC
;
3137 i
.op
[n
].imms
->X_add_number
+= 3;
3140 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3141 i
.op
[n
].imms
, 0, reloc_type
);
3153 #endif /* DEBUG386 */
3158 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3160 /* Parse operands of the form
3161 <symbol>@GOTOFF+<nnn>
3162 and similar .plt or .got references.
3164 If we find one, set up the correct relocation in RELOC and copy the
3165 input string, minus the `@GOTOFF' into a malloc'd buffer for
3166 parsing by the calling routine. Return this buffer, and if ADJUST
3167 is non-null set it to the length of the string we removed from the
3168 input line. Otherwise return NULL. */
3170 lex_got (reloc
, adjust
)
3174 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3175 static const struct {
3177 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3179 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3180 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3181 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3182 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3187 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3188 if (is_end_of_line
[(unsigned char) *cp
])
3191 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3195 len
= strlen (gotrel
[j
].str
);
3196 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3198 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3201 char *tmpbuf
, *past_reloc
;
3203 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3207 if (GOT_symbol
== NULL
)
3208 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3210 /* Replace the relocation token with ' ', so that
3211 errors like foo@GOTOFF1 will be detected. */
3213 /* The length of the first part of our input line. */
3214 first
= cp
- input_line_pointer
;
3216 /* The second part goes from after the reloc token until
3217 (and including) an end_of_line char. Don't use strlen
3218 here as the end_of_line char may not be a NUL. */
3219 past_reloc
= cp
+ 1 + len
;
3220 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3222 second
= cp
- past_reloc
;
3224 /* Allocate and copy string. The trailing NUL shouldn't
3225 be necessary, but be safe. */
3226 tmpbuf
= xmalloc (first
+ second
+ 2);
3227 memcpy (tmpbuf
, input_line_pointer
, first
);
3228 tmpbuf
[first
] = ' ';
3229 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3230 tmpbuf
[first
+ second
+ 1] = '\0';
3234 as_bad (_("@%s reloc is not supported in %s bit mode"),
3235 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3240 /* Might be a symbol version string. Don't as_bad here. */
3244 /* x86_cons_fix_new is called via the expression parsing code when a
3245 reloc is needed. We use this hook to get the correct .got reloc. */
3246 static RELOC_ENUM got_reloc
= NO_RELOC
;
3249 x86_cons_fix_new (frag
, off
, len
, exp
)
3255 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3256 got_reloc
= NO_RELOC
;
3257 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3261 x86_cons (exp
, size
)
3267 /* Handle @GOTOFF and the like in an expression. */
3269 char *gotfree_input_line
;
3272 save
= input_line_pointer
;
3273 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3274 if (gotfree_input_line
)
3275 input_line_pointer
= gotfree_input_line
;
3279 if (gotfree_input_line
)
3281 /* expression () has merrily parsed up to the end of line,
3282 or a comma - in the wrong buffer. Transfer how far
3283 input_line_pointer has moved to the right buffer. */
3284 input_line_pointer
= (save
3285 + (input_line_pointer
- gotfree_input_line
)
3287 free (gotfree_input_line
);
3295 static int i386_immediate
PARAMS ((char *));
3298 i386_immediate (imm_start
)
3301 char *save_input_line_pointer
;
3303 char *gotfree_input_line
;
3308 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3310 as_bad (_("only 1 or 2 immediate operands are allowed"));
3314 exp
= &im_expressions
[i
.imm_operands
++];
3315 i
.op
[this_operand
].imms
= exp
;
3317 if (is_space_char (*imm_start
))
3320 save_input_line_pointer
= input_line_pointer
;
3321 input_line_pointer
= imm_start
;
3324 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3325 if (gotfree_input_line
)
3326 input_line_pointer
= gotfree_input_line
;
3329 exp_seg
= expression (exp
);
3332 if (*input_line_pointer
)
3333 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3335 input_line_pointer
= save_input_line_pointer
;
3337 if (gotfree_input_line
)
3338 free (gotfree_input_line
);
3341 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3343 /* Missing or bad expr becomes absolute 0. */
3344 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3346 exp
->X_op
= O_constant
;
3347 exp
->X_add_number
= 0;
3348 exp
->X_add_symbol
= (symbolS
*) 0;
3349 exp
->X_op_symbol
= (symbolS
*) 0;
3351 else if (exp
->X_op
== O_constant
)
3353 /* Size it properly later. */
3354 i
.types
[this_operand
] |= Imm64
;
3355 /* If BFD64, sign extend val. */
3356 if (!use_rela_relocations
)
3357 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3358 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3360 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3362 #ifdef BFD_ASSEMBLER
3363 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3365 && exp_seg
!= text_section
3366 && exp_seg
!= data_section
3367 && exp_seg
!= bss_section
3368 && exp_seg
!= undefined_section
3369 #ifdef BFD_ASSEMBLER
3370 && !bfd_is_com_section (exp_seg
)
3374 #ifdef BFD_ASSEMBLER
3375 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3377 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3384 /* This is an address. The size of the address will be
3385 determined later, depending on destination register,
3386 suffix, or the default for the section. */
3387 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3393 static char *i386_scale
PARAMS ((char *));
3400 char *save
= input_line_pointer
;
3402 input_line_pointer
= scale
;
3403 val
= get_absolute_expression ();
3409 i
.log2_scale_factor
= 0;
3412 i
.log2_scale_factor
= 1;
3415 i
.log2_scale_factor
= 2;
3418 i
.log2_scale_factor
= 3;
3421 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3423 input_line_pointer
= save
;
3426 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3428 as_warn (_("scale factor of %d without an index register"),
3429 1 << i
.log2_scale_factor
);
3430 #if SCALE1_WHEN_NO_INDEX
3431 i
.log2_scale_factor
= 0;
3434 scale
= input_line_pointer
;
3435 input_line_pointer
= save
;
3439 static int i386_displacement
PARAMS ((char *, char *));
3442 i386_displacement (disp_start
, disp_end
)
3446 register expressionS
*exp
;
3448 char *save_input_line_pointer
;
3450 char *gotfree_input_line
;
3452 int bigdisp
= Disp32
;
3454 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3456 if (flag_code
== CODE_64BIT
)
3458 i
.types
[this_operand
] |= bigdisp
;
3460 exp
= &disp_expressions
[i
.disp_operands
];
3461 i
.op
[this_operand
].disps
= exp
;
3463 save_input_line_pointer
= input_line_pointer
;
3464 input_line_pointer
= disp_start
;
3465 END_STRING_AND_SAVE (disp_end
);
3467 #ifndef GCC_ASM_O_HACK
3468 #define GCC_ASM_O_HACK 0
3471 END_STRING_AND_SAVE (disp_end
+ 1);
3472 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3473 && displacement_string_end
[-1] == '+')
3475 /* This hack is to avoid a warning when using the "o"
3476 constraint within gcc asm statements.
3479 #define _set_tssldt_desc(n,addr,limit,type) \
3480 __asm__ __volatile__ ( \
3482 "movw %w1,2+%0\n\t" \
3484 "movb %b1,4+%0\n\t" \
3485 "movb %4,5+%0\n\t" \
3486 "movb $0,6+%0\n\t" \
3487 "movb %h1,7+%0\n\t" \
3489 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3491 This works great except that the output assembler ends
3492 up looking a bit weird if it turns out that there is
3493 no offset. You end up producing code that looks like:
3506 So here we provide the missing zero. */
3508 *displacement_string_end
= '0';
3512 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3513 if (gotfree_input_line
)
3514 input_line_pointer
= gotfree_input_line
;
3517 exp_seg
= expression (exp
);
3520 if (*input_line_pointer
)
3521 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3523 RESTORE_END_STRING (disp_end
+ 1);
3525 RESTORE_END_STRING (disp_end
);
3526 input_line_pointer
= save_input_line_pointer
;
3528 if (gotfree_input_line
)
3529 free (gotfree_input_line
);
3532 #ifdef BFD_ASSEMBLER
3533 /* We do this to make sure that the section symbol is in
3534 the symbol table. We will ultimately change the relocation
3535 to be relative to the beginning of the section. */
3536 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3537 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3539 if (exp
->X_op
!= O_symbol
)
3541 as_bad (_("bad expression used with @%s"),
3542 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3548 if (S_IS_LOCAL (exp
->X_add_symbol
)
3549 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3550 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3551 exp
->X_op
= O_subtract
;
3552 exp
->X_op_symbol
= GOT_symbol
;
3553 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3554 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3556 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3560 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3562 /* Missing or bad expr becomes absolute 0. */
3563 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3565 exp
->X_op
= O_constant
;
3566 exp
->X_add_number
= 0;
3567 exp
->X_add_symbol
= (symbolS
*) 0;
3568 exp
->X_op_symbol
= (symbolS
*) 0;
3571 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3572 if (exp
->X_op
!= O_constant
3573 #ifdef BFD_ASSEMBLER
3574 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3576 && exp_seg
!= text_section
3577 && exp_seg
!= data_section
3578 && exp_seg
!= bss_section
3579 && exp_seg
!= undefined_section
)
3581 #ifdef BFD_ASSEMBLER
3582 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3584 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3589 else if (flag_code
== CODE_64BIT
)
3590 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3594 static int i386_index_check
PARAMS ((const char *));
3596 /* Make sure the memory operand we've been dealt is valid.
3597 Return 1 on success, 0 on a failure. */
3600 i386_index_check (operand_string
)
3601 const char *operand_string
;
3604 #if INFER_ADDR_PREFIX
3610 if (flag_code
== CODE_64BIT
)
3614 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3615 && (i
.base_reg
->reg_type
!= BaseIndex
3618 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3619 != (Reg64
|BaseIndex
))))
3624 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3628 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3629 != (Reg16
|BaseIndex
)))
3631 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3632 != (Reg16
|BaseIndex
))
3634 && i
.base_reg
->reg_num
< 6
3635 && i
.index_reg
->reg_num
>= 6
3636 && i
.log2_scale_factor
== 0))))
3643 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3645 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3646 != (Reg32
|BaseIndex
))))
3652 #if INFER_ADDR_PREFIX
3653 if (flag_code
!= CODE_64BIT
3654 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3656 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3658 /* Change the size of any displacement too. At most one of
3659 Disp16 or Disp32 is set.
3660 FIXME. There doesn't seem to be any real need for separate
3661 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3662 Removing them would probably clean up the code quite a lot. */
3663 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3664 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3669 as_bad (_("`%s' is not a valid base/index expression"),
3673 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3675 flag_code_names
[flag_code
]);
3681 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3685 i386_operand (operand_string
)
3686 char *operand_string
;
3690 char *op_string
= operand_string
;
3692 if (is_space_char (*op_string
))
3695 /* We check for an absolute prefix (differentiating,
3696 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3697 if (*op_string
== ABSOLUTE_PREFIX
)
3700 if (is_space_char (*op_string
))
3702 i
.types
[this_operand
] |= JumpAbsolute
;
3705 /* Check if operand is a register. */
3706 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3707 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3709 /* Check for a segment override by searching for ':' after a
3710 segment register. */
3712 if (is_space_char (*op_string
))
3714 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3719 i
.seg
[i
.mem_operands
] = &es
;
3722 i
.seg
[i
.mem_operands
] = &cs
;
3725 i
.seg
[i
.mem_operands
] = &ss
;
3728 i
.seg
[i
.mem_operands
] = &ds
;
3731 i
.seg
[i
.mem_operands
] = &fs
;
3734 i
.seg
[i
.mem_operands
] = &gs
;
3738 /* Skip the ':' and whitespace. */
3740 if (is_space_char (*op_string
))
3743 if (!is_digit_char (*op_string
)
3744 && !is_identifier_char (*op_string
)
3745 && *op_string
!= '('
3746 && *op_string
!= ABSOLUTE_PREFIX
)
3748 as_bad (_("bad memory operand `%s'"), op_string
);
3751 /* Handle case of %es:*foo. */
3752 if (*op_string
== ABSOLUTE_PREFIX
)
3755 if (is_space_char (*op_string
))
3757 i
.types
[this_operand
] |= JumpAbsolute
;
3759 goto do_memory_reference
;
3763 as_bad (_("junk `%s' after register"), op_string
);
3766 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3767 i
.op
[this_operand
].regs
= r
;
3770 else if (*op_string
== REGISTER_PREFIX
)
3772 as_bad (_("bad register name `%s'"), op_string
);
3775 else if (*op_string
== IMMEDIATE_PREFIX
)
3778 if (i
.types
[this_operand
] & JumpAbsolute
)
3780 as_bad (_("immediate operand illegal with absolute jump"));
3783 if (!i386_immediate (op_string
))
3786 else if (is_digit_char (*op_string
)
3787 || is_identifier_char (*op_string
)
3788 || *op_string
== '(')
3790 /* This is a memory reference of some sort. */
3793 /* Start and end of displacement string expression (if found). */
3794 char *displacement_string_start
;
3795 char *displacement_string_end
;
3797 do_memory_reference
:
3798 if ((i
.mem_operands
== 1
3799 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3800 || i
.mem_operands
== 2)
3802 as_bad (_("too many memory references for `%s'"),
3803 current_templates
->start
->name
);
3807 /* Check for base index form. We detect the base index form by
3808 looking for an ')' at the end of the operand, searching
3809 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3811 base_string
= op_string
+ strlen (op_string
);
3814 if (is_space_char (*base_string
))
3817 /* If we only have a displacement, set-up for it to be parsed later. */
3818 displacement_string_start
= op_string
;
3819 displacement_string_end
= base_string
+ 1;
3821 if (*base_string
== ')')
3824 unsigned int parens_balanced
= 1;
3825 /* We've already checked that the number of left & right ()'s are
3826 equal, so this loop will not be infinite. */
3830 if (*base_string
== ')')
3832 if (*base_string
== '(')
3835 while (parens_balanced
);
3837 temp_string
= base_string
;
3839 /* Skip past '(' and whitespace. */
3841 if (is_space_char (*base_string
))
3844 if (*base_string
== ','
3845 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3846 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3848 displacement_string_end
= temp_string
;
3850 i
.types
[this_operand
] |= BaseIndex
;
3854 base_string
= end_op
;
3855 if (is_space_char (*base_string
))
3859 /* There may be an index reg or scale factor here. */
3860 if (*base_string
== ',')
3863 if (is_space_char (*base_string
))
3866 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3867 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3869 base_string
= end_op
;
3870 if (is_space_char (*base_string
))
3872 if (*base_string
== ',')
3875 if (is_space_char (*base_string
))
3878 else if (*base_string
!= ')')
3880 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3885 else if (*base_string
== REGISTER_PREFIX
)
3887 as_bad (_("bad register name `%s'"), base_string
);
3891 /* Check for scale factor. */
3892 if (*base_string
!= ')')
3894 char *end_scale
= i386_scale (base_string
);
3899 base_string
= end_scale
;
3900 if (is_space_char (*base_string
))
3902 if (*base_string
!= ')')
3904 as_bad (_("expecting `)' after scale factor in `%s'"),
3909 else if (!i
.index_reg
)
3911 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3916 else if (*base_string
!= ')')
3918 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3923 else if (*base_string
== REGISTER_PREFIX
)
3925 as_bad (_("bad register name `%s'"), base_string
);
3930 /* If there's an expression beginning the operand, parse it,
3931 assuming displacement_string_start and
3932 displacement_string_end are meaningful. */
3933 if (displacement_string_start
!= displacement_string_end
)
3935 if (!i386_displacement (displacement_string_start
,
3936 displacement_string_end
))
3940 /* Special case for (%dx) while doing input/output op. */
3942 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3944 && i
.log2_scale_factor
== 0
3945 && i
.seg
[i
.mem_operands
] == 0
3946 && (i
.types
[this_operand
] & Disp
) == 0)
3948 i
.types
[this_operand
] = InOutPortReg
;
3952 if (i386_index_check (operand_string
) == 0)
3958 /* It's not a memory operand; argh! */
3959 as_bad (_("invalid char %s beginning operand %d `%s'"),
3960 output_invalid (*op_string
),
3965 return 1; /* Normal return. */
3968 /* md_estimate_size_before_relax()
3970 Called just before relax() for rs_machine_dependent frags. The x86
3971 assembler uses these frags to handle variable size jump
3974 Any symbol that is now undefined will not become defined.
3975 Return the correct fr_subtype in the frag.
3976 Return the initial "guess for variable size of frag" to caller.
3977 The guess is actually the growth beyond the fixed part. Whatever
3978 we do to grow the fixed or variable part contributes to our
3982 md_estimate_size_before_relax (fragP
, segment
)
3983 register fragS
*fragP
;
3984 register segT segment
;
3986 /* We've already got fragP->fr_subtype right; all we have to do is
3987 check for un-relaxable symbols. On an ELF system, we can't relax
3988 an externally visible symbol, because it may be overridden by a
3990 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3991 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3992 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3993 || S_IS_WEAK (fragP
->fr_symbol
)
3997 /* Symbol is undefined in this segment, or we need to keep a
3998 reloc so that weak symbols can be overridden. */
3999 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4000 RELOC_ENUM reloc_type
;
4001 unsigned char *opcode
;
4004 if (fragP
->fr_var
!= NO_RELOC
)
4005 reloc_type
= fragP
->fr_var
;
4007 reloc_type
= BFD_RELOC_16_PCREL
;
4009 reloc_type
= BFD_RELOC_32_PCREL
;
4011 old_fr_fix
= fragP
->fr_fix
;
4012 opcode
= (unsigned char *) fragP
->fr_opcode
;
4014 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4017 /* Make jmp (0xeb) a (d)word displacement jump. */
4019 fragP
->fr_fix
+= size
;
4020 fix_new (fragP
, old_fr_fix
, size
,
4022 fragP
->fr_offset
, 1,
4027 if (no_cond_jump_promotion
)
4032 /* Negate the condition, and branch past an
4033 unconditional jump. */
4036 /* Insert an unconditional jump. */
4038 /* We added two extra opcode bytes, and have a two byte
4040 fragP
->fr_fix
+= 2 + 2;
4041 fix_new (fragP
, old_fr_fix
+ 2, 2,
4043 fragP
->fr_offset
, 1,
4050 if (no_cond_jump_promotion
)
4053 /* This changes the byte-displacement jump 0x7N
4054 to the (d)word-displacement jump 0x0f,0x8N. */
4055 opcode
[1] = opcode
[0] + 0x10;
4056 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4057 /* We've added an opcode byte. */
4058 fragP
->fr_fix
+= 1 + size
;
4059 fix_new (fragP
, old_fr_fix
+ 1, size
,
4061 fragP
->fr_offset
, 1,
4066 BAD_CASE (fragP
->fr_subtype
);
4070 return fragP
->fr_fix
- old_fr_fix
;
4074 /* Guess size depending on current relax state. Initially the relax
4075 state will correspond to a short jump and we return 1, because
4076 the variable part of the frag (the branch offset) is one byte
4077 long. However, we can relax a section more than once and in that
4078 case we must either set fr_subtype back to the unrelaxed state,
4079 or return the value for the appropriate branch. */
4080 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4083 /* Called after relax() is finished.
4085 In: Address of frag.
4086 fr_type == rs_machine_dependent.
4087 fr_subtype is what the address relaxed to.
4089 Out: Any fixSs and constants are set up.
4090 Caller will turn frag into a ".space 0". */
4092 #ifndef BFD_ASSEMBLER
4094 md_convert_frag (headers
, sec
, fragP
)
4095 object_headers
*headers ATTRIBUTE_UNUSED
;
4096 segT sec ATTRIBUTE_UNUSED
;
4097 register fragS
*fragP
;
4100 md_convert_frag (abfd
, sec
, fragP
)
4101 bfd
*abfd ATTRIBUTE_UNUSED
;
4102 segT sec ATTRIBUTE_UNUSED
;
4103 register fragS
*fragP
;
4106 register unsigned char *opcode
;
4107 unsigned char *where_to_put_displacement
= NULL
;
4108 offsetT target_address
;
4109 offsetT opcode_address
;
4110 unsigned int extension
= 0;
4111 offsetT displacement_from_opcode_start
;
4113 opcode
= (unsigned char *) fragP
->fr_opcode
;
4115 /* Address we want to reach in file space. */
4116 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4118 /* Address opcode resides at in file space. */
4119 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4121 /* Displacement from opcode start to fill into instruction. */
4122 displacement_from_opcode_start
= target_address
- opcode_address
;
4124 if ((fragP
->fr_subtype
& BIG
) == 0)
4126 /* Don't have to change opcode. */
4127 extension
= 1; /* 1 opcode + 1 displacement */
4128 where_to_put_displacement
= &opcode
[1];
4132 if (no_cond_jump_promotion
4133 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4134 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4136 switch (fragP
->fr_subtype
)
4138 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4139 extension
= 4; /* 1 opcode + 4 displacement */
4141 where_to_put_displacement
= &opcode
[1];
4144 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4145 extension
= 2; /* 1 opcode + 2 displacement */
4147 where_to_put_displacement
= &opcode
[1];
4150 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4151 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4152 extension
= 5; /* 2 opcode + 4 displacement */
4153 opcode
[1] = opcode
[0] + 0x10;
4154 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4155 where_to_put_displacement
= &opcode
[2];
4158 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4159 extension
= 3; /* 2 opcode + 2 displacement */
4160 opcode
[1] = opcode
[0] + 0x10;
4161 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4162 where_to_put_displacement
= &opcode
[2];
4165 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4170 where_to_put_displacement
= &opcode
[3];
4174 BAD_CASE (fragP
->fr_subtype
);
4179 /* Now put displacement after opcode. */
4180 md_number_to_chars ((char *) where_to_put_displacement
,
4181 (valueT
) (displacement_from_opcode_start
- extension
),
4182 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4183 fragP
->fr_fix
+= extension
;
4186 /* Size of byte displacement jmp. */
4187 int md_short_jump_size
= 2;
4189 /* Size of dword displacement jmp. */
4190 int md_long_jump_size
= 5;
4192 /* Size of relocation record. */
4193 const int md_reloc_size
= 8;
4196 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4198 addressT from_addr
, to_addr
;
4199 fragS
*frag ATTRIBUTE_UNUSED
;
4200 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4204 offset
= to_addr
- (from_addr
+ 2);
4205 /* Opcode for byte-disp jump. */
4206 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4207 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4211 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4213 addressT from_addr
, to_addr
;
4214 fragS
*frag ATTRIBUTE_UNUSED
;
4215 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4219 offset
= to_addr
- (from_addr
+ 5);
4220 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4221 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4224 /* Apply a fixup (fixS) to segment data, once it has been determined
4225 by our caller that we have all the info we need to fix it up.
4227 On the 386, immediates, displacements, and data pointers are all in
4228 the same (little-endian) format, so we don't need to care about which
4232 md_apply_fix3 (fixP
, valp
, seg
)
4233 /* The fix we're to put in. */
4236 /* Pointer to the value of the bits. */
4239 /* Segment fix is from. */
4240 segT seg ATTRIBUTE_UNUSED
;
4242 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4243 valueT value
= *valp
;
4245 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4248 switch (fixP
->fx_r_type
)
4254 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4257 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4260 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4265 /* This is a hack. There should be a better way to handle this.
4266 This covers for the fact that bfd_install_relocation will
4267 subtract the current location (for partial_inplace, PC relative
4268 relocations); see more below. */
4269 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4270 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4271 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4272 && fixP
->fx_addsy
&& !use_rela_relocations
)
4275 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4277 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4280 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4282 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4283 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4285 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4288 || (symbol_section_p (fixP
->fx_addsy
)
4289 && fseg
!= absolute_section
))
4290 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4291 && ! S_IS_WEAK (fixP
->fx_addsy
)
4292 && S_IS_DEFINED (fixP
->fx_addsy
)
4293 && ! S_IS_COMMON (fixP
->fx_addsy
))
4295 /* Yes, we add the values in twice. This is because
4296 bfd_perform_relocation subtracts them out again. I think
4297 bfd_perform_relocation is broken, but I don't dare change
4299 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4303 #if defined (OBJ_COFF) && defined (TE_PE)
4304 /* For some reason, the PE format does not store a section
4305 address offset for a PC relative symbol. */
4306 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4307 value
+= md_pcrel_from (fixP
);
4311 /* Fix a few things - the dynamic linker expects certain values here,
4312 and we must not dissappoint it. */
4313 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4314 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4316 switch (fixP
->fx_r_type
)
4318 case BFD_RELOC_386_PLT32
:
4319 case BFD_RELOC_X86_64_PLT32
:
4320 /* Make the jump instruction point to the address of the operand. At
4321 runtime we merely add the offset to the actual PLT entry. */
4324 case BFD_RELOC_386_GOTPC
:
4326 /* This is tough to explain. We end up with this one if we have
4327 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4328 * here is to obtain the absolute address of the GOT, and it is strongly
4329 * preferable from a performance point of view to avoid using a runtime
4330 * relocation for this. The actual sequence of instructions often look
4336 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4338 * The call and pop essentially return the absolute address of
4339 * the label .L66 and store it in %ebx. The linker itself will
4340 * ultimately change the first operand of the addl so that %ebx points to
4341 * the GOT, but to keep things simple, the .o file must have this operand
4342 * set so that it generates not the absolute address of .L66, but the
4343 * absolute address of itself. This allows the linker itself simply
4344 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4345 * added in, and the addend of the relocation is stored in the operand
4346 * field for the instruction itself.
4348 * Our job here is to fix the operand so that it would add the correct
4349 * offset so that %ebx would point to itself. The thing that is tricky is
4350 * that .-.L66 will point to the beginning of the instruction, so we need
4351 * to further modify the operand so that it will point to itself.
4352 * There are other cases where you have something like:
4354 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4356 * and here no correction would be required. Internally in the assembler
4357 * we treat operands of this form as not being pcrel since the '.' is
4358 * explicitly mentioned, and I wonder whether it would simplify matters
4359 * to do it this way. Who knows. In earlier versions of the PIC patches,
4360 * the pcrel_adjust field was used to store the correction, but since the
4361 * expression is not pcrel, I felt it would be confusing to do it this
4366 case BFD_RELOC_386_GOT32
:
4367 case BFD_RELOC_X86_64_GOT32
:
4368 value
= 0; /* Fully resolved at runtime. No addend. */
4370 case BFD_RELOC_386_GOTOFF
:
4371 case BFD_RELOC_X86_64_GOTPCREL
:
4374 case BFD_RELOC_VTABLE_INHERIT
:
4375 case BFD_RELOC_VTABLE_ENTRY
:
4382 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4384 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4386 #ifndef BFD_ASSEMBLER
4387 md_number_to_chars (p
, value
, fixP
->fx_size
);
4389 /* Are we finished with this relocation now? */
4390 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4392 else if (use_rela_relocations
)
4394 fixP
->fx_no_overflow
= 1;
4397 md_number_to_chars (p
, value
, fixP
->fx_size
);
4403 #define MAX_LITTLENUMS 6
4405 /* Turn the string pointed to by litP into a floating point constant
4406 of type TYPE, and emit the appropriate bytes. The number of
4407 LITTLENUMS emitted is stored in *SIZEP. An error message is
4408 returned, or NULL on OK. */
4411 md_atof (type
, litP
, sizeP
)
4417 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4418 LITTLENUM_TYPE
*wordP
;
4440 return _("Bad call to md_atof ()");
4442 t
= atof_ieee (input_line_pointer
, type
, words
);
4444 input_line_pointer
= t
;
4446 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4447 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4448 the bigendian 386. */
4449 for (wordP
= words
+ prec
- 1; prec
--;)
4451 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4452 litP
+= sizeof (LITTLENUM_TYPE
);
4457 char output_invalid_buf
[8];
4464 sprintf (output_invalid_buf
, "'%c'", c
);
4466 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4467 return output_invalid_buf
;
4470 /* REG_STRING starts *before* REGISTER_PREFIX. */
4472 static const reg_entry
*
4473 parse_register (reg_string
, end_op
)
4477 char *s
= reg_string
;
4479 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4482 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4483 if (*s
== REGISTER_PREFIX
)
4486 if (is_space_char (*s
))
4490 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4492 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4493 return (const reg_entry
*) NULL
;
4497 /* For naked regs, make sure that we are not dealing with an identifier.
4498 This prevents confusing an identifier like `eax_var' with register
4500 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4501 return (const reg_entry
*) NULL
;
4505 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4507 /* Handle floating point regs, allowing spaces in the (i) part. */
4508 if (r
== i386_regtab
/* %st is first entry of table */)
4510 if (is_space_char (*s
))
4515 if (is_space_char (*s
))
4517 if (*s
>= '0' && *s
<= '7')
4519 r
= &i386_float_regtab
[*s
- '0'];
4521 if (is_space_char (*s
))
4529 /* We have "%st(" then garbage. */
4530 return (const reg_entry
*) NULL
;
4537 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4538 const char *md_shortopts
= "kVQ:sq";
4540 const char *md_shortopts
= "q";
4543 struct option md_longopts
[] = {
4544 #define OPTION_32 (OPTION_MD_BASE + 0)
4545 {"32", no_argument
, NULL
, OPTION_32
},
4546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4547 #define OPTION_64 (OPTION_MD_BASE + 1)
4548 {"64", no_argument
, NULL
, OPTION_64
},
4550 {NULL
, no_argument
, NULL
, 0}
4552 size_t md_longopts_size
= sizeof (md_longopts
);
4555 md_parse_option (c
, arg
)
4557 char *arg ATTRIBUTE_UNUSED
;
4565 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4566 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4567 should be emitted or not. FIXME: Not implemented. */
4571 /* -V: SVR4 argument to print version ID. */
4573 print_version_id ();
4576 /* -k: Ignore for FreeBSD compatibility. */
4581 /* -s: On i386 Solaris, this tells the native assembler to use
4582 .stab instead of .stab.excl. We always use .stab anyhow. */
4587 const char **list
, **l
;
4589 list
= bfd_target_list ();
4590 for (l
= list
; *l
!= NULL
; l
++)
4591 if (strcmp (*l
, "elf64-x86-64") == 0)
4593 default_arch
= "x86_64";
4597 as_fatal (_("No compiled in support for x86_64"));
4604 default_arch
= "i386";
4614 md_show_usage (stream
)
4617 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4618 fprintf (stream
, _("\
4620 -V print assembler version number\n\
4622 -q quieten some warnings\n\
4625 fprintf (stream
, _("\
4626 -q quieten some warnings\n"));
4630 #ifdef BFD_ASSEMBLER
4631 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4632 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4634 /* Pick the target format to use. */
4637 i386_target_format ()
4639 if (!strcmp (default_arch
, "x86_64"))
4640 set_code_flag (CODE_64BIT
);
4641 else if (!strcmp (default_arch
, "i386"))
4642 set_code_flag (CODE_32BIT
);
4644 as_fatal (_("Unknown architecture"));
4645 switch (OUTPUT_FLAVOR
)
4647 #ifdef OBJ_MAYBE_AOUT
4648 case bfd_target_aout_flavour
:
4649 return AOUT_TARGET_FORMAT
;
4651 #ifdef OBJ_MAYBE_COFF
4652 case bfd_target_coff_flavour
:
4655 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4656 case bfd_target_elf_flavour
:
4658 if (flag_code
== CODE_64BIT
)
4659 use_rela_relocations
= 1;
4660 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4669 #endif /* OBJ_MAYBE_ more than one */
4670 #endif /* BFD_ASSEMBLER */
4673 md_undefined_symbol (name
)
4676 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4677 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4678 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4679 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4683 if (symbol_find (name
))
4684 as_bad (_("GOT already in symbol table"));
4685 GOT_symbol
= symbol_new (name
, undefined_section
,
4686 (valueT
) 0, &zero_address_frag
);
4693 /* Round up a section size to the appropriate boundary. */
4696 md_section_align (segment
, size
)
4697 segT segment ATTRIBUTE_UNUSED
;
4700 #ifdef BFD_ASSEMBLER
4701 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4702 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4704 /* For a.out, force the section size to be aligned. If we don't do
4705 this, BFD will align it for us, but it will not write out the
4706 final bytes of the section. This may be a bug in BFD, but it is
4707 easier to fix it here since that is how the other a.out targets
4711 align
= bfd_get_section_alignment (stdoutput
, segment
);
4712 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4720 /* On the i386, PC-relative offsets are relative to the start of the
4721 next instruction. That is, the address of the offset, plus its
4722 size, since the offset is always the last part of the insn. */
4725 md_pcrel_from (fixP
)
4728 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4735 int ignore ATTRIBUTE_UNUSED
;
4739 temp
= get_absolute_expression ();
4740 subseg_set (bss_section
, (subsegT
) temp
);
4741 demand_empty_rest_of_line ();
4746 #ifdef BFD_ASSEMBLER
4749 i386_validate_fix (fixp
)
4752 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4754 /* GOTOFF relocation are nonsense in 64bit mode. */
4755 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
4757 if (flag_code
!= CODE_64BIT
)
4759 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
4763 if (flag_code
== CODE_64BIT
)
4765 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4772 tc_gen_reloc (section
, fixp
)
4773 asection
*section ATTRIBUTE_UNUSED
;
4777 bfd_reloc_code_real_type code
;
4779 switch (fixp
->fx_r_type
)
4781 case BFD_RELOC_X86_64_PLT32
:
4782 case BFD_RELOC_X86_64_GOT32
:
4783 case BFD_RELOC_X86_64_GOTPCREL
:
4784 case BFD_RELOC_386_PLT32
:
4785 case BFD_RELOC_386_GOT32
:
4786 case BFD_RELOC_386_GOTOFF
:
4787 case BFD_RELOC_386_GOTPC
:
4788 case BFD_RELOC_X86_64_32S
:
4790 case BFD_RELOC_VTABLE_ENTRY
:
4791 case BFD_RELOC_VTABLE_INHERIT
:
4792 code
= fixp
->fx_r_type
;
4797 switch (fixp
->fx_size
)
4800 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4801 _("can not do %d byte pc-relative relocation"),
4803 code
= BFD_RELOC_32_PCREL
;
4805 case 1: code
= BFD_RELOC_8_PCREL
; break;
4806 case 2: code
= BFD_RELOC_16_PCREL
; break;
4807 case 4: code
= BFD_RELOC_32_PCREL
; break;
4812 switch (fixp
->fx_size
)
4815 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4816 _("can not do %d byte relocation"),
4818 code
= BFD_RELOC_32
;
4820 case 1: code
= BFD_RELOC_8
; break;
4821 case 2: code
= BFD_RELOC_16
; break;
4822 case 4: code
= BFD_RELOC_32
; break;
4823 case 8: code
= BFD_RELOC_64
; break;
4829 if (code
== BFD_RELOC_32
4831 && fixp
->fx_addsy
== GOT_symbol
)
4833 /* We don't support GOTPC on 64bit targets. */
4834 if (flag_code
== CODE_64BIT
)
4836 code
= BFD_RELOC_386_GOTPC
;
4839 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4840 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4841 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4843 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4844 if (!use_rela_relocations
)
4846 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4847 vtable entry to be used in the relocation's section offset. */
4848 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4849 rel
->address
= fixp
->fx_offset
;
4852 rel
->addend
= fixp
->fx_addnumber
;
4856 /* Use the rela in 64bit mode. */
4859 rel
->addend
= fixp
->fx_offset
;
4861 rel
->addend
-= fixp
->fx_size
;
4864 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4865 if (rel
->howto
== NULL
)
4867 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4868 _("cannot represent relocation type %s"),
4869 bfd_get_reloc_code_name (code
));
4870 /* Set howto to a garbage value so that we can keep going. */
4871 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4872 assert (rel
->howto
!= NULL
);
4878 #else /* ! BFD_ASSEMBLER */
4880 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4882 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4885 relax_addressT segment_address_in_file
;
4887 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4888 Out: GNU LD relocation length code: 0, 1, or 2. */
4890 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4893 know (fixP
->fx_addsy
!= NULL
);
4895 md_number_to_chars (where
,
4896 (valueT
) (fixP
->fx_frag
->fr_address
4897 + fixP
->fx_where
- segment_address_in_file
),
4900 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4901 ? S_GET_TYPE (fixP
->fx_addsy
)
4902 : fixP
->fx_addsy
->sy_number
);
4904 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4905 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4906 where
[4] = r_symbolnum
& 0x0ff;
4907 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4908 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4909 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4912 #endif /* OBJ_AOUT or OBJ_BOUT. */
4914 #if defined (I386COFF)
4917 tc_coff_fix2rtype (fixP
)
4920 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4923 return (fixP
->fx_pcrel
?
4924 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4925 fixP
->fx_size
== 2 ? R_PCRWORD
:
4927 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4928 fixP
->fx_size
== 2 ? R_RELWORD
:
4933 tc_coff_sizemachdep (frag
)
4937 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4942 #endif /* I386COFF */
4944 #endif /* ! BFD_ASSEMBLER */
4946 /* Parse operands using Intel syntax. This implements a recursive descent
4947 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4950 FIXME: We do not recognize the full operand grammar defined in the MASM
4951 documentation. In particular, all the structure/union and
4952 high-level macro operands are missing.
4954 Uppercase words are terminals, lower case words are non-terminals.
4955 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4956 bars '|' denote choices. Most grammar productions are implemented in
4957 functions called 'intel_<production>'.
4959 Initial production is 'expr'.
4965 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4967 constant digits [[ radixOverride ]]
4969 dataType BYTE | WORD | DWORD | QWORD | XWORD
5002 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5003 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5005 hexdigit a | b | c | d | e | f
5006 | A | B | C | D | E | F
5016 register specialRegister
5020 segmentRegister CS | DS | ES | FS | GS | SS
5022 specialRegister CR0 | CR2 | CR3
5023 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5024 | TR3 | TR4 | TR5 | TR6 | TR7
5026 We simplify the grammar in obvious places (e.g., register parsing is
5027 done by calling parse_register) and eliminate immediate left recursion
5028 to implement a recursive-descent parser.
5068 /* Parsing structure for the intel syntax parser. Used to implement the
5069 semantic actions for the operand grammar. */
5070 struct intel_parser_s
5072 char *op_string
; /* The string being parsed. */
5073 int got_a_float
; /* Whether the operand is a float. */
5074 int op_modifier
; /* Operand modifier. */
5075 int is_mem
; /* 1 if operand is memory reference. */
5076 const reg_entry
*reg
; /* Last register reference found. */
5077 char *disp
; /* Displacement string being built. */
5080 static struct intel_parser_s intel_parser
;
5082 /* Token structure for parsing intel syntax. */
5085 int code
; /* Token code. */
5086 const reg_entry
*reg
; /* Register entry for register tokens. */
5087 char *str
; /* String representation. */
5090 static struct intel_token cur_token
, prev_token
;
5092 /* Token codes for the intel parser. Since T_SHORT is already used
5093 by COFF, undefine it first to prevent a warning. */
5108 /* Prototypes for intel parser functions. */
5109 static int intel_match_token
PARAMS ((int code
));
5110 static void intel_get_token
PARAMS ((void));
5111 static void intel_putback_token
PARAMS ((void));
5112 static int intel_expr
PARAMS ((void));
5113 static int intel_e05
PARAMS ((void));
5114 static int intel_e05_1
PARAMS ((void));
5115 static int intel_e06
PARAMS ((void));
5116 static int intel_e06_1
PARAMS ((void));
5117 static int intel_e09
PARAMS ((void));
5118 static int intel_e09_1
PARAMS ((void));
5119 static int intel_e10
PARAMS ((void));
5120 static int intel_e10_1
PARAMS ((void));
5121 static int intel_e11
PARAMS ((void));
5124 i386_intel_operand (operand_string
, got_a_float
)
5125 char *operand_string
;
5131 /* Initialize token holders. */
5132 cur_token
.code
= prev_token
.code
= T_NIL
;
5133 cur_token
.reg
= prev_token
.reg
= NULL
;
5134 cur_token
.str
= prev_token
.str
= NULL
;
5136 /* Initialize parser structure. */
5137 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5140 strcpy (intel_parser
.op_string
, operand_string
);
5141 intel_parser
.got_a_float
= got_a_float
;
5142 intel_parser
.op_modifier
= -1;
5143 intel_parser
.is_mem
= 0;
5144 intel_parser
.reg
= NULL
;
5145 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5146 if (intel_parser
.disp
== NULL
)
5148 intel_parser
.disp
[0] = '\0';
5150 /* Read the first token and start the parser. */
5152 ret
= intel_expr ();
5156 /* If we found a memory reference, hand it over to i386_displacement
5157 to fill in the rest of the operand fields. */
5158 if (intel_parser
.is_mem
)
5160 if ((i
.mem_operands
== 1
5161 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5162 || i
.mem_operands
== 2)
5164 as_bad (_("too many memory references for '%s'"),
5165 current_templates
->start
->name
);
5170 char *s
= intel_parser
.disp
;
5173 /* Add the displacement expression. */
5175 ret
= i386_displacement (s
, s
+ strlen (s
))
5176 && i386_index_check (s
);
5180 /* Constant and OFFSET expressions are handled by i386_immediate. */
5181 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5182 || intel_parser
.reg
== NULL
)
5183 ret
= i386_immediate (intel_parser
.disp
);
5187 free (intel_parser
.disp
);
5197 /* expr SHORT e05 */
5198 if (cur_token
.code
== T_SHORT
)
5200 intel_parser
.op_modifier
= SHORT
;
5201 intel_match_token (T_SHORT
);
5203 return (intel_e05 ());
5208 return intel_e05 ();
5218 return (intel_e06 () && intel_e05_1 ());
5224 /* e05' addOp e06 e05' */
5225 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5227 strcat (intel_parser
.disp
, cur_token
.str
);
5228 intel_match_token (cur_token
.code
);
5230 return (intel_e06 () && intel_e05_1 ());
5245 return (intel_e09 () && intel_e06_1 ());
5251 /* e06' mulOp e09 e06' */
5252 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5254 strcat (intel_parser
.disp
, cur_token
.str
);
5255 intel_match_token (cur_token
.code
);
5257 return (intel_e09 () && intel_e06_1 ());
5265 /* e09 OFFSET e10 e09'
5274 /* e09 OFFSET e10 e09' */
5275 if (cur_token
.code
== T_OFFSET
)
5277 intel_parser
.is_mem
= 0;
5278 intel_parser
.op_modifier
= OFFSET_FLAT
;
5279 intel_match_token (T_OFFSET
);
5281 return (intel_e10 () && intel_e09_1 ());
5286 return (intel_e10 () && intel_e09_1 ());
5292 /* e09' PTR e10 e09' */
5293 if (cur_token
.code
== T_PTR
)
5295 if (prev_token
.code
== T_BYTE
)
5296 i
.suffix
= BYTE_MNEM_SUFFIX
;
5298 else if (prev_token
.code
== T_WORD
)
5300 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5301 i
.suffix
= SHORT_MNEM_SUFFIX
;
5303 i
.suffix
= WORD_MNEM_SUFFIX
;
5306 else if (prev_token
.code
== T_DWORD
)
5308 if (intel_parser
.got_a_float
== 1) /* "f..." */
5309 i
.suffix
= SHORT_MNEM_SUFFIX
;
5311 i
.suffix
= LONG_MNEM_SUFFIX
;
5314 else if (prev_token
.code
== T_QWORD
)
5316 if (intel_parser
.got_a_float
== 1) /* "f..." */
5317 i
.suffix
= LONG_MNEM_SUFFIX
;
5319 i
.suffix
= QWORD_MNEM_SUFFIX
;
5322 else if (prev_token
.code
== T_XWORD
)
5323 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5327 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5331 intel_match_token (T_PTR
);
5333 return (intel_e10 () && intel_e09_1 ());
5336 /* e09 : e10 e09' */
5337 else if (cur_token
.code
== ':')
5339 /* Mark as a memory operand only if it's not already known to be an
5340 offset expression. */
5341 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5342 intel_parser
.is_mem
= 1;
5344 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5359 return (intel_e11 () && intel_e10_1 ());
5365 /* e10' [ expr ] e10' */
5366 if (cur_token
.code
== '[')
5368 intel_match_token ('[');
5370 /* Mark as a memory operand only if it's not already known to be an
5371 offset expression. If it's an offset expression, we need to keep
5373 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5374 intel_parser
.is_mem
= 1;
5376 strcat (intel_parser
.disp
, "[");
5378 /* Add a '+' to the displacement string if necessary. */
5379 if (*intel_parser
.disp
!= '\0'
5380 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5381 strcat (intel_parser
.disp
, "+");
5383 if (intel_expr () && intel_match_token (']'))
5385 /* Preserve brackets when the operand is an offset expression. */
5386 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5387 strcat (intel_parser
.disp
, "]");
5389 return intel_e10_1 ();
5416 if (cur_token
.code
== '(')
5418 intel_match_token ('(');
5419 strcat (intel_parser
.disp
, "(");
5421 if (intel_expr () && intel_match_token (')'))
5423 strcat (intel_parser
.disp
, ")");
5431 else if (cur_token
.code
== '[')
5433 intel_match_token ('[');
5435 /* Mark as a memory operand only if it's not already known to be an
5436 offset expression. If it's an offset expression, we need to keep
5438 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5439 intel_parser
.is_mem
= 1;
5441 strcat (intel_parser
.disp
, "[");
5443 /* Operands for jump/call inside brackets denote absolute addresses. */
5444 if (current_templates
->start
->opcode_modifier
& Jump
5445 || current_templates
->start
->opcode_modifier
& JumpDword
5446 || current_templates
->start
->opcode_modifier
& JumpByte
5447 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5448 i
.types
[this_operand
] |= JumpAbsolute
;
5450 /* Add a '+' to the displacement string if necessary. */
5451 if (*intel_parser
.disp
!= '\0'
5452 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5453 strcat (intel_parser
.disp
, "+");
5455 if (intel_expr () && intel_match_token (']'))
5457 /* Preserve brackets when the operand is an offset expression. */
5458 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5459 strcat (intel_parser
.disp
, "]");
5472 else if (cur_token
.code
== T_BYTE
5473 || cur_token
.code
== T_WORD
5474 || cur_token
.code
== T_DWORD
5475 || cur_token
.code
== T_QWORD
5476 || cur_token
.code
== T_XWORD
)
5478 intel_match_token (cur_token
.code
);
5485 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5487 strcat (intel_parser
.disp
, cur_token
.str
);
5488 intel_match_token (cur_token
.code
);
5490 /* Mark as a memory operand only if it's not already known to be an
5491 offset expression. */
5492 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5493 intel_parser
.is_mem
= 1;
5499 else if (cur_token
.code
== T_REG
)
5501 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5503 intel_match_token (T_REG
);
5505 /* Check for segment change. */
5506 if (cur_token
.code
== ':')
5508 if (reg
->reg_type
& (SReg2
| SReg3
))
5510 switch (reg
->reg_num
)
5513 i
.seg
[i
.mem_operands
] = &es
;
5516 i
.seg
[i
.mem_operands
] = &cs
;
5519 i
.seg
[i
.mem_operands
] = &ss
;
5522 i
.seg
[i
.mem_operands
] = &ds
;
5525 i
.seg
[i
.mem_operands
] = &fs
;
5528 i
.seg
[i
.mem_operands
] = &gs
;
5534 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5539 /* Not a segment register. Check for register scaling. */
5540 else if (cur_token
.code
== '*')
5542 if (!intel_parser
.is_mem
)
5544 as_bad (_("Register scaling only allowed in memory operands."));
5548 /* What follows must be a valid scale. */
5549 if (intel_match_token ('*')
5550 && strchr ("01248", *cur_token
.str
))
5553 i
.types
[this_operand
] |= BaseIndex
;
5555 /* Set the scale after setting the register (otherwise,
5556 i386_scale will complain) */
5557 i386_scale (cur_token
.str
);
5558 intel_match_token (T_CONST
);
5562 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5568 /* No scaling. If this is a memory operand, the register is either a
5569 base register (first occurrence) or an index register (second
5571 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5573 if (i
.base_reg
&& i
.index_reg
)
5575 as_bad (_("Too many register references in memory operand.\n"));
5579 if (i
.base_reg
== NULL
)
5584 i
.types
[this_operand
] |= BaseIndex
;
5587 /* Offset modifier. Add the register to the displacement string to be
5588 parsed as an immediate expression after we're done. */
5589 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5590 strcat (intel_parser
.disp
, reg
->reg_name
);
5592 /* It's neither base nor index nor offset. */
5595 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5596 i
.op
[this_operand
].regs
= reg
;
5600 /* Since registers are not part of the displacement string (except
5601 when we're parsing offset operands), we may need to remove any
5602 preceding '+' from the displacement string. */
5603 if (*intel_parser
.disp
!= '\0'
5604 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5606 char *s
= intel_parser
.disp
;
5607 s
+= strlen (s
) - 1;
5616 else if (cur_token
.code
== T_ID
)
5618 /* Add the identifier to the displacement string. */
5619 strcat (intel_parser
.disp
, cur_token
.str
);
5620 intel_match_token (T_ID
);
5622 /* The identifier represents a memory reference only if it's not
5623 preceded by an offset modifier. */
5624 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5625 intel_parser
.is_mem
= 1;
5631 else if (cur_token
.code
== T_CONST
5632 || cur_token
.code
== '-'
5633 || cur_token
.code
== '+')
5637 /* Allow constants that start with `+' or `-'. */
5638 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5640 strcat (intel_parser
.disp
, cur_token
.str
);
5641 intel_match_token (cur_token
.code
);
5642 if (cur_token
.code
!= T_CONST
)
5644 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5650 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5651 if (save_str
== NULL
)
5653 strcpy (save_str
, cur_token
.str
);
5655 /* Get the next token to check for register scaling. */
5656 intel_match_token (cur_token
.code
);
5658 /* Check if this constant is a scaling factor for an index register. */
5659 if (cur_token
.code
== '*')
5661 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5663 if (!intel_parser
.is_mem
)
5665 as_bad (_("Register scaling only allowed in memory operands."));
5669 /* The constant is followed by `* reg', so it must be
5671 if (strchr ("01248", *save_str
))
5673 i
.index_reg
= cur_token
.reg
;
5674 i
.types
[this_operand
] |= BaseIndex
;
5676 /* Set the scale after setting the register (otherwise,
5677 i386_scale will complain) */
5678 i386_scale (save_str
);
5679 intel_match_token (T_REG
);
5681 /* Since registers are not part of the displacement
5682 string, we may need to remove any preceding '+' from
5683 the displacement string. */
5684 if (*intel_parser
.disp
!= '\0')
5686 char *s
= intel_parser
.disp
;
5687 s
+= strlen (s
) - 1;
5700 /* The constant was not used for register scaling. Since we have
5701 already consumed the token following `*' we now need to put it
5702 back in the stream. */
5704 intel_putback_token ();
5707 /* Add the constant to the displacement string. */
5708 strcat (intel_parser
.disp
, save_str
);
5714 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5718 /* Match the given token against cur_token. If they match, read the next
5719 token from the operand string. */
5721 intel_match_token (code
)
5724 if (cur_token
.code
== code
)
5731 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5736 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5741 const reg_entry
*reg
;
5742 struct intel_token new_token
;
5744 new_token
.code
= T_NIL
;
5745 new_token
.reg
= NULL
;
5746 new_token
.str
= NULL
;
5748 /* Free the memory allocated to the previous token and move
5749 cur_token to prev_token. */
5751 free (prev_token
.str
);
5753 prev_token
= cur_token
;
5755 /* Skip whitespace. */
5756 while (is_space_char (*intel_parser
.op_string
))
5757 intel_parser
.op_string
++;
5759 /* Return an empty token if we find nothing else on the line. */
5760 if (*intel_parser
.op_string
== '\0')
5762 cur_token
= new_token
;
5766 /* The new token cannot be larger than the remainder of the operand
5768 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
5769 if (new_token
.str
== NULL
)
5771 new_token
.str
[0] = '\0';
5773 if (strchr ("0123456789", *intel_parser
.op_string
))
5775 char *p
= new_token
.str
;
5776 char *q
= intel_parser
.op_string
;
5777 new_token
.code
= T_CONST
;
5779 /* Allow any kind of identifier char to encompass floating point and
5780 hexadecimal numbers. */
5781 while (is_identifier_char (*q
))
5785 /* Recognize special symbol names [0-9][bf]. */
5786 if (strlen (intel_parser
.op_string
) == 2
5787 && (intel_parser
.op_string
[1] == 'b'
5788 || intel_parser
.op_string
[1] == 'f'))
5789 new_token
.code
= T_ID
;
5792 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5794 new_token
.code
= *intel_parser
.op_string
;
5795 new_token
.str
[0] = *intel_parser
.op_string
;
5796 new_token
.str
[1] = '\0';
5799 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5800 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5802 new_token
.code
= T_REG
;
5803 new_token
.reg
= reg
;
5805 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5807 new_token
.str
[0] = REGISTER_PREFIX
;
5808 new_token
.str
[1] = '\0';
5811 strcat (new_token
.str
, reg
->reg_name
);
5814 else if (is_identifier_char (*intel_parser
.op_string
))
5816 char *p
= new_token
.str
;
5817 char *q
= intel_parser
.op_string
;
5819 /* A '.' or '$' followed by an identifier char is an identifier.
5820 Otherwise, it's operator '.' followed by an expression. */
5821 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5823 new_token
.code
= *q
;
5824 new_token
.str
[0] = *q
;
5825 new_token
.str
[1] = '\0';
5829 while (is_identifier_char (*q
) || *q
== '@')
5833 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5834 new_token
.code
= T_BYTE
;
5836 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5837 new_token
.code
= T_WORD
;
5839 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5840 new_token
.code
= T_DWORD
;
5842 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5843 new_token
.code
= T_QWORD
;
5845 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5846 new_token
.code
= T_XWORD
;
5848 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5849 new_token
.code
= T_PTR
;
5851 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5852 new_token
.code
= T_SHORT
;
5854 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5856 new_token
.code
= T_OFFSET
;
5858 /* ??? This is not mentioned in the MASM grammar but gcc
5859 makes use of it with -mintel-syntax. OFFSET may be
5860 followed by FLAT: */
5861 if (strncasecmp (q
, " FLAT:", 6) == 0)
5862 strcat (new_token
.str
, " FLAT:");
5865 /* ??? This is not mentioned in the MASM grammar. */
5866 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5867 new_token
.code
= T_OFFSET
;
5870 new_token
.code
= T_ID
;
5875 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5877 intel_parser
.op_string
+= strlen (new_token
.str
);
5878 cur_token
= new_token
;
5881 /* Put cur_token back into the token stream and make cur_token point to
5884 intel_putback_token ()
5886 intel_parser
.op_string
-= strlen (cur_token
.str
);
5887 free (cur_token
.str
);
5888 cur_token
= prev_token
;
5890 /* Forget prev_token. */
5891 prev_token
.code
= T_NIL
;
5892 prev_token
.reg
= NULL
;
5893 prev_token
.str
= NULL
;