1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2021 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
37 #ifndef INFER_ADDR_PREFIX
38 #define INFER_ADDR_PREFIX 1
42 #define DEFAULT_ARCH "i386"
47 #define INLINE __inline__
53 /* Prefixes will be emitted in the order defined below.
54 WAIT_PREFIX must be the first prefix since FWAIT is really is an
55 instruction, and so must come before any prefixes.
56 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
57 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
63 #define HLE_PREFIX REP_PREFIX
64 #define BND_PREFIX REP_PREFIX
66 #define REX_PREFIX 6 /* must come last. */
67 #define MAX_PREFIXES 7 /* max prefixes per opcode */
69 /* we define the syntax here (modulo base,index,scale syntax) */
70 #define REGISTER_PREFIX '%'
71 #define IMMEDIATE_PREFIX '$'
72 #define ABSOLUTE_PREFIX '*'
74 /* these are the instruction mnemonic suffixes in AT&T syntax or
75 memory operand size in Intel syntax. */
76 #define WORD_MNEM_SUFFIX 'w'
77 #define BYTE_MNEM_SUFFIX 'b'
78 #define SHORT_MNEM_SUFFIX 's'
79 #define LONG_MNEM_SUFFIX 'l'
80 #define QWORD_MNEM_SUFFIX 'q'
81 /* Intel Syntax. Use a non-ascii letter since since it never appears
83 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
85 #define END_OF_INSN '\0'
87 /* This matches the C -> StaticRounding alias in the opcode table. */
88 #define commutative staticrounding
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (unsigned int, unsigned int);
171 static enum flag_code
i386_addressing_mode (void);
172 static void optimize_imm (void);
173 static void optimize_disp (void);
174 static const insn_template
*match_template (char);
175 static int check_string (void);
176 static int process_suffix (void);
177 static int check_byte_reg (void);
178 static int check_long_reg (void);
179 static int check_qword_reg (void);
180 static int check_word_reg (void);
181 static int finalize_imm (void);
182 static int process_operands (void);
183 static const reg_entry
*build_modrm_byte (void);
184 static void output_insn (void);
185 static void output_imm (fragS
*, offsetT
);
186 static void output_disp (fragS
*, offsetT
);
188 static void s_bss (int);
190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 /* GNU_PROPERTY_X86_ISA_1_USED. */
194 static unsigned int x86_isa_1_used
;
195 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
196 static unsigned int x86_feature_2_used
;
197 /* Generate x86 used ISA and feature properties. */
198 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
201 static const char *default_arch
= DEFAULT_ARCH
;
203 /* parse_register() returns this when a register alias cannot be used. */
204 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
205 { Dw2Inval
, Dw2Inval
} };
207 static const reg_entry
*reg_eax
;
208 static const reg_entry
*reg_ds
;
209 static const reg_entry
*reg_es
;
210 static const reg_entry
*reg_ss
;
211 static const reg_entry
*reg_st0
;
212 static const reg_entry
*reg_k0
;
217 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
218 unsigned char bytes
[4];
220 /* Destination or source register specifier. */
221 const reg_entry
*register_specifier
;
224 /* 'md_assemble ()' gathers together information and puts it into a
231 const reg_entry
*regs
;
236 operand_size_mismatch
,
237 operand_type_mismatch
,
238 register_type_mismatch
,
239 number_of_operands_mismatch
,
240 invalid_instruction_suffix
,
242 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 unsupported_vector_index_register
,
250 unsupported_broadcast
,
253 mask_not_on_destination
,
256 rc_sae_operand_not_last_imm
,
257 invalid_register_operand
,
262 /* TM holds the template for the insn were currently assembling. */
265 /* SUFFIX holds the instruction size suffix for byte, word, dword
266 or qword, if given. */
269 /* OPCODE_LENGTH holds the number of base opcode bytes. */
270 unsigned char opcode_length
;
272 /* OPERANDS gives the number of given operands. */
273 unsigned int operands
;
275 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
276 of given register, displacement, memory operands and immediate
278 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
280 /* TYPES [i] is the type (see above #defines) which tells us how to
281 use OP[i] for the corresponding operand. */
282 i386_operand_type types
[MAX_OPERANDS
];
284 /* Displacement expression, immediate expression, or register for each
286 union i386_op op
[MAX_OPERANDS
];
288 /* Flags for operands. */
289 unsigned int flags
[MAX_OPERANDS
];
290 #define Operand_PCrel 1
291 #define Operand_Mem 2
293 /* Relocation type for operand */
294 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
296 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
297 the base index byte below. */
298 const reg_entry
*base_reg
;
299 const reg_entry
*index_reg
;
300 unsigned int log2_scale_factor
;
302 /* SEG gives the seg_entries of this insn. They are zero unless
303 explicit segment overrides are given. */
304 const reg_entry
*seg
[2];
306 /* Copied first memory operand string, for re-checking. */
309 /* PREFIX holds all the given prefix opcodes (usually null).
310 PREFIXES is the number of prefix opcodes. */
311 unsigned int prefixes
;
312 unsigned char prefix
[MAX_PREFIXES
];
314 /* Register is in low 3 bits of opcode. */
317 /* The operand to a branch insn indicates an absolute branch. */
320 /* Extended states. */
328 xstate_ymm
= 1 << 2 | xstate_xmm
,
330 xstate_zmm
= 1 << 3 | xstate_ymm
,
333 /* Use MASK state. */
337 /* Has GOTPC or TLS relocation. */
338 bool has_gotpc_tls_reloc
;
340 /* RM and SIB are the modrm byte and the sib byte where the
341 addressing modes of this insn are encoded. */
348 /* Masking attributes.
350 The struct describes masking, applied to OPERAND in the instruction.
351 REG is a pointer to the corresponding mask register. ZEROING tells
352 whether merging or zeroing mask is used. */
353 struct Mask_Operation
355 const reg_entry
*reg
;
356 unsigned int zeroing
;
357 /* The operand where this operation is associated. */
358 unsigned int operand
;
361 /* Rounding control and SAE attributes. */
374 unsigned int operand
;
377 /* Broadcasting attributes.
379 The struct describes broadcasting, applied to OPERAND. TYPE is
380 expresses the broadcast factor. */
381 struct Broadcast_Operation
383 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
386 /* Index of broadcasted operand. */
387 unsigned int operand
;
389 /* Number of bytes to broadcast. */
393 /* Compressed disp8*N attribute. */
394 unsigned int memshift
;
396 /* Prefer load or store in encoding. */
399 dir_encoding_default
= 0,
405 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
408 disp_encoding_default
= 0,
414 /* Prefer the REX byte in encoding. */
417 /* Disable instruction size optimization. */
420 /* How to encode vector instructions. */
423 vex_encoding_default
= 0,
431 const char *rep_prefix
;
434 const char *hle_prefix
;
436 /* Have BND prefix. */
437 const char *bnd_prefix
;
439 /* Have NOTRACK prefix. */
440 const char *notrack_prefix
;
443 enum i386_error error
;
446 typedef struct _i386_insn i386_insn
;
448 /* Link RC type with corresponding string, that'll be looked for in
457 static const struct RC_name RC_NamesTable
[] =
459 { rne
, STRING_COMMA_LEN ("rn-sae") },
460 { rd
, STRING_COMMA_LEN ("rd-sae") },
461 { ru
, STRING_COMMA_LEN ("ru-sae") },
462 { rz
, STRING_COMMA_LEN ("rz-sae") },
463 { saeonly
, STRING_COMMA_LEN ("sae") },
466 /* List of chars besides those in app.c:symbol_chars that can start an
467 operand. Used to prevent the scrubber eating vital white-space. */
468 const char extra_symbol_chars
[] = "*%-([{}"
477 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
478 && !defined (TE_GNU) \
479 && !defined (TE_LINUX) \
480 && !defined (TE_FreeBSD) \
481 && !defined (TE_DragonFly) \
482 && !defined (TE_NetBSD))
483 /* This array holds the chars that always start a comment. If the
484 pre-processor is disabled, these aren't very useful. The option
485 --divide will remove '/' from this list. */
486 const char *i386_comment_chars
= "#/";
487 #define SVR4_COMMENT_CHARS 1
488 #define PREFIX_SEPARATOR '\\'
491 const char *i386_comment_chars
= "#";
492 #define PREFIX_SEPARATOR '/'
495 /* This array holds the chars that only start a comment at the beginning of
496 a line. If the line seems to have the form '# 123 filename'
497 .line and .file directives will appear in the pre-processed output.
498 Note that input_file.c hand checks for '#' at the beginning of the
499 first line of the input file. This is because the compiler outputs
500 #NO_APP at the beginning of its output.
501 Also note that comments started like this one will always work if
502 '/' isn't otherwise defined. */
503 const char line_comment_chars
[] = "#/";
505 const char line_separator_chars
[] = ";";
507 /* Chars that can be used to separate mant from exp in floating point
509 const char EXP_CHARS
[] = "eE";
511 /* Chars that mean this number is a floating point constant
514 const char FLT_CHARS
[] = "fFdDxX";
516 /* Tables for lexical analysis. */
517 static char mnemonic_chars
[256];
518 static char register_chars
[256];
519 static char operand_chars
[256];
520 static char identifier_chars
[256];
522 /* Lexical macros. */
523 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
524 #define is_operand_char(x) (operand_chars[(unsigned char) x])
525 #define is_register_char(x) (register_chars[(unsigned char) x])
526 #define is_space_char(x) ((x) == ' ')
527 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
529 /* All non-digit non-letter characters that may occur in an operand. */
530 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
532 /* md_assemble() always leaves the strings it's passed unaltered. To
533 effect this we maintain a stack of saved characters that we've smashed
534 with '\0's (indicating end of strings for various sub-fields of the
535 assembler instruction). */
536 static char save_stack
[32];
537 static char *save_stack_p
;
538 #define END_STRING_AND_SAVE(s) \
539 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
540 #define RESTORE_END_STRING(s) \
541 do { *(s) = *--save_stack_p; } while (0)
543 /* The instruction we're assembling. */
546 /* Possible templates for current insn. */
547 static const templates
*current_templates
;
549 /* Per instruction expressionS buffers: max displacements & immediates. */
550 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
551 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
553 /* Current operand we are working on. */
554 static int this_operand
= -1;
556 /* We support four different modes. FLAG_CODE variable is used to distinguish
564 static enum flag_code flag_code
;
565 static unsigned int object_64bit
;
566 static unsigned int disallow_64bit_reloc
;
567 static int use_rela_relocations
= 0;
568 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
569 static const char *tls_get_addr
;
571 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
572 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
575 /* The ELF ABI to use. */
583 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
586 #if defined (TE_PE) || defined (TE_PEP)
587 /* Use big object file format. */
588 static int use_big_obj
= 0;
591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
592 /* 1 if generating code for a shared library. */
593 static int shared
= 0;
596 /* 1 for intel syntax,
598 static int intel_syntax
= 0;
600 static enum x86_64_isa
602 amd64
= 1, /* AMD64 ISA. */
603 intel64
/* Intel64 ISA. */
606 /* 1 for intel mnemonic,
607 0 if att mnemonic. */
608 static int intel_mnemonic
= !SYSV386_COMPAT
;
610 /* 1 if pseudo registers are permitted. */
611 static int allow_pseudo_reg
= 0;
613 /* 1 if register prefix % not required. */
614 static int allow_naked_reg
= 0;
616 /* 1 if the assembler should add BND prefix for all control-transferring
617 instructions supporting it, even if this prefix wasn't specified
619 static int add_bnd_prefix
= 0;
621 /* 1 if pseudo index register, eiz/riz, is allowed . */
622 static int allow_index_reg
= 0;
624 /* 1 if the assembler should ignore LOCK prefix, even if it was
625 specified explicitly. */
626 static int omit_lock_prefix
= 0;
628 /* 1 if the assembler should encode lfence, mfence, and sfence as
629 "lock addl $0, (%{re}sp)". */
630 static int avoid_fence
= 0;
632 /* 1 if lfence should be inserted after every load. */
633 static int lfence_after_load
= 0;
635 /* Non-zero if lfence should be inserted before indirect branch. */
636 static enum lfence_before_indirect_branch_kind
638 lfence_branch_none
= 0,
639 lfence_branch_register
,
640 lfence_branch_memory
,
643 lfence_before_indirect_branch
;
645 /* Non-zero if lfence should be inserted before ret. */
646 static enum lfence_before_ret_kind
648 lfence_before_ret_none
= 0,
649 lfence_before_ret_not
,
650 lfence_before_ret_or
,
651 lfence_before_ret_shl
655 /* Types of previous instruction is .byte or prefix. */
670 /* 1 if the assembler should generate relax relocations. */
672 static int generate_relax_relocations
673 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
675 static enum check_kind
681 sse_check
, operand_check
= check_warning
;
683 /* Non-zero if branches should be aligned within power of 2 boundary. */
684 static int align_branch_power
= 0;
686 /* Types of branches to align. */
687 enum align_branch_kind
689 align_branch_none
= 0,
690 align_branch_jcc
= 1,
691 align_branch_fused
= 2,
692 align_branch_jmp
= 3,
693 align_branch_call
= 4,
694 align_branch_indirect
= 5,
698 /* Type bits of branches to align. */
699 enum align_branch_bit
701 align_branch_jcc_bit
= 1 << align_branch_jcc
,
702 align_branch_fused_bit
= 1 << align_branch_fused
,
703 align_branch_jmp_bit
= 1 << align_branch_jmp
,
704 align_branch_call_bit
= 1 << align_branch_call
,
705 align_branch_indirect_bit
= 1 << align_branch_indirect
,
706 align_branch_ret_bit
= 1 << align_branch_ret
709 static unsigned int align_branch
= (align_branch_jcc_bit
710 | align_branch_fused_bit
711 | align_branch_jmp_bit
);
713 /* Types of condition jump used by macro-fusion. */
716 mf_jcc_jo
= 0, /* base opcode 0x70 */
717 mf_jcc_jc
, /* base opcode 0x72 */
718 mf_jcc_je
, /* base opcode 0x74 */
719 mf_jcc_jna
, /* base opcode 0x76 */
720 mf_jcc_js
, /* base opcode 0x78 */
721 mf_jcc_jp
, /* base opcode 0x7a */
722 mf_jcc_jl
, /* base opcode 0x7c */
723 mf_jcc_jle
, /* base opcode 0x7e */
726 /* Types of compare flag-modifying insntructions used by macro-fusion. */
729 mf_cmp_test_and
, /* test/cmp */
730 mf_cmp_alu_cmp
, /* add/sub/cmp */
731 mf_cmp_incdec
/* inc/dec */
734 /* The maximum padding size for fused jcc. CMP like instruction can
735 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
737 #define MAX_FUSED_JCC_PADDING_SIZE 20
739 /* The maximum number of prefixes added for an instruction. */
740 static unsigned int align_branch_prefix_size
= 5;
743 1. Clear the REX_W bit with register operand if possible.
744 2. Above plus use 128bit vector instruction to clear the full vector
747 static int optimize
= 0;
750 1. Clear the REX_W bit with register operand if possible.
751 2. Above plus use 128bit vector instruction to clear the full vector
753 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
756 static int optimize_for_space
= 0;
758 /* Register prefix used for error message. */
759 static const char *register_prefix
= "%";
761 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
762 leave, push, and pop instructions so that gcc has the same stack
763 frame as in 32 bit mode. */
764 static char stackop_size
= '\0';
766 /* Non-zero to optimize code alignment. */
767 int optimize_align_code
= 1;
769 /* Non-zero to quieten some warnings. */
770 static int quiet_warnings
= 0;
773 static const char *cpu_arch_name
= NULL
;
774 static char *cpu_sub_arch_name
= NULL
;
776 /* CPU feature flags. */
777 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
779 /* If we have selected a cpu we are generating instructions for. */
780 static int cpu_arch_tune_set
= 0;
782 /* Cpu we are generating instructions for. */
783 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
785 /* CPU feature flags of cpu we are generating instructions for. */
786 static i386_cpu_flags cpu_arch_tune_flags
;
788 /* CPU instruction set architecture used. */
789 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
791 /* CPU feature flags of instruction set architecture used. */
792 i386_cpu_flags cpu_arch_isa_flags
;
794 /* If set, conditional jumps are not automatically promoted to handle
795 larger than a byte offset. */
796 static unsigned int no_cond_jump_promotion
= 0;
798 /* Encode SSE instructions with VEX prefix. */
799 static unsigned int sse2avx
;
801 /* Encode scalar AVX instructions with specific vector length. */
808 /* Encode VEX WIG instructions with specific vex.w. */
815 /* Encode scalar EVEX LIG instructions with specific vector length. */
823 /* Encode EVEX WIG instructions with specific evex.w. */
830 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
831 static enum rc_type evexrcig
= rne
;
833 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
834 static symbolS
*GOT_symbol
;
836 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
837 unsigned int x86_dwarf2_return_column
;
839 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
840 int x86_cie_data_alignment
;
842 /* Interface to relax_segment.
843 There are 3 major relax states for 386 jump insns because the
844 different types of jumps add different sizes to frags when we're
845 figuring out what sort of jump to choose to reach a given label.
847 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
848 branches which are handled by md_estimate_size_before_relax() and
849 i386_generic_table_relax_frag(). */
852 #define UNCOND_JUMP 0
854 #define COND_JUMP86 2
855 #define BRANCH_PADDING 3
856 #define BRANCH_PREFIX 4
857 #define FUSED_JCC_PADDING 5
862 #define SMALL16 (SMALL | CODE16)
864 #define BIG16 (BIG | CODE16)
868 #define INLINE __inline__
874 #define ENCODE_RELAX_STATE(type, size) \
875 ((relax_substateT) (((type) << 2) | (size)))
876 #define TYPE_FROM_RELAX_STATE(s) \
878 #define DISP_SIZE_FROM_RELAX_STATE(s) \
879 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
881 /* This table is used by relax_frag to promote short jumps to long
882 ones where necessary. SMALL (short) jumps may be promoted to BIG
883 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
884 don't allow a short jump in a 32 bit code segment to be promoted to
885 a 16 bit offset jump because it's slower (requires data size
886 prefix), and doesn't work, unless the destination is in the bottom
887 64k of the code segment (The top 16 bits of eip are zeroed). */
889 const relax_typeS md_relax_table
[] =
892 1) most positive reach of this state,
893 2) most negative reach of this state,
894 3) how many bytes this mode will have in the variable part of the frag
895 4) which index into the table to try if we can't fit into this one. */
897 /* UNCOND_JUMP states. */
898 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
899 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
900 /* dword jmp adds 4 bytes to frag:
901 0 extra opcode bytes, 4 displacement bytes. */
903 /* word jmp adds 2 byte2 to frag:
904 0 extra opcode bytes, 2 displacement bytes. */
907 /* COND_JUMP states. */
908 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
909 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
910 /* dword conditionals adds 5 bytes to frag:
911 1 extra opcode byte, 4 displacement bytes. */
913 /* word conditionals add 3 bytes to frag:
914 1 extra opcode byte, 2 displacement bytes. */
917 /* COND_JUMP86 states. */
918 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
919 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
920 /* dword conditionals adds 5 bytes to frag:
921 1 extra opcode byte, 4 displacement bytes. */
923 /* word conditionals add 4 bytes to frag:
924 1 displacement byte and a 3 byte long branch insn. */
928 static const arch_entry cpu_arch
[] =
930 /* Do not replace the first two entries - i386_target_format()
931 relies on them being there in this order. */
932 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
933 CPU_GENERIC32_FLAGS
, 0 },
934 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
935 CPU_GENERIC64_FLAGS
, 0 },
936 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
938 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
944 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
946 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
948 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
950 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
952 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
953 CPU_PENTIUMPRO_FLAGS
, 0 },
954 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
956 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
958 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
960 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
962 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
963 CPU_NOCONA_FLAGS
, 0 },
964 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
966 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
968 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
969 CPU_CORE2_FLAGS
, 1 },
970 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
971 CPU_CORE2_FLAGS
, 0 },
972 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
973 CPU_COREI7_FLAGS
, 0 },
974 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
976 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
978 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
979 CPU_IAMCU_FLAGS
, 0 },
980 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
982 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
984 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
985 CPU_ATHLON_FLAGS
, 0 },
986 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
988 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
990 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
992 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
993 CPU_AMDFAM10_FLAGS
, 0 },
994 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
995 CPU_BDVER1_FLAGS
, 0 },
996 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
997 CPU_BDVER2_FLAGS
, 0 },
998 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
999 CPU_BDVER3_FLAGS
, 0 },
1000 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1001 CPU_BDVER4_FLAGS
, 0 },
1002 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1003 CPU_ZNVER1_FLAGS
, 0 },
1004 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1005 CPU_ZNVER2_FLAGS
, 0 },
1006 { STRING_COMMA_LEN ("znver3"), PROCESSOR_ZNVER
,
1007 CPU_ZNVER3_FLAGS
, 0 },
1008 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1009 CPU_BTVER1_FLAGS
, 0 },
1010 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1011 CPU_BTVER2_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1013 CPU_8087_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1021 CPU_CMOV_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1023 CPU_FXSR_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1026 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1029 CPU_SSE2_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1031 CPU_SSE3_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1033 CPU_SSE4A_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1035 CPU_SSSE3_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1037 CPU_SSE4_1_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1039 CPU_SSE4_2_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1041 CPU_SSE4_2_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1044 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1045 CPU_AVX2_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1047 CPU_AVX512F_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1049 CPU_AVX512CD_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1051 CPU_AVX512ER_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1053 CPU_AVX512PF_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1055 CPU_AVX512DQ_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1057 CPU_AVX512BW_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1059 CPU_AVX512VL_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1062 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1063 CPU_VMFUNC_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1066 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1067 CPU_XSAVE_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1069 CPU_XSAVEOPT_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1071 CPU_XSAVEC_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1073 CPU_XSAVES_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1076 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1077 CPU_PCLMUL_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1079 CPU_PCLMUL_FLAGS
, 1 },
1080 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1081 CPU_FSGSBASE_FLAGS
, 0 },
1082 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1083 CPU_RDRND_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1085 CPU_F16C_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1087 CPU_BMI2_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1090 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1091 CPU_FMA4_FLAGS
, 0 },
1092 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1094 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1096 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1097 CPU_MOVBE_FLAGS
, 0 },
1098 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1099 CPU_CX16_FLAGS
, 0 },
1100 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1102 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1103 CPU_LZCNT_FLAGS
, 0 },
1104 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1105 CPU_POPCNT_FLAGS
, 0 },
1106 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1108 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1110 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1111 CPU_INVPCID_FLAGS
, 0 },
1112 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1113 CPU_CLFLUSH_FLAGS
, 0 },
1114 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1116 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1117 CPU_SYSCALL_FLAGS
, 0 },
1118 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1119 CPU_RDTSCP_FLAGS
, 0 },
1120 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1121 CPU_3DNOW_FLAGS
, 0 },
1122 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1123 CPU_3DNOWA_FLAGS
, 0 },
1124 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1125 CPU_PADLOCK_FLAGS
, 0 },
1126 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1127 CPU_SVME_FLAGS
, 1 },
1128 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1129 CPU_SVME_FLAGS
, 0 },
1130 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1131 CPU_SSE4A_FLAGS
, 0 },
1132 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1134 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1136 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1138 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1140 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1141 CPU_RDSEED_FLAGS
, 0 },
1142 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1143 CPU_PRFCHW_FLAGS
, 0 },
1144 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1145 CPU_SMAP_FLAGS
, 0 },
1146 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1148 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1150 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1151 CPU_CLFLUSHOPT_FLAGS
, 0 },
1152 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1153 CPU_PREFETCHWT1_FLAGS
, 0 },
1154 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1156 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1157 CPU_CLWB_FLAGS
, 0 },
1158 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1159 CPU_AVX512IFMA_FLAGS
, 0 },
1160 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1161 CPU_AVX512VBMI_FLAGS
, 0 },
1162 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1163 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1164 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1165 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1166 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1167 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1168 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1169 CPU_AVX512_VBMI2_FLAGS
, 0 },
1170 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1171 CPU_AVX512_VNNI_FLAGS
, 0 },
1172 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1173 CPU_AVX512_BITALG_FLAGS
, 0 },
1174 { STRING_COMMA_LEN (".avx_vnni"), PROCESSOR_UNKNOWN
,
1175 CPU_AVX_VNNI_FLAGS
, 0 },
1176 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1177 CPU_CLZERO_FLAGS
, 0 },
1178 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1179 CPU_MWAITX_FLAGS
, 0 },
1180 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1181 CPU_OSPKE_FLAGS
, 0 },
1182 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1183 CPU_RDPID_FLAGS
, 0 },
1184 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1185 CPU_PTWRITE_FLAGS
, 0 },
1186 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1188 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1189 CPU_SHSTK_FLAGS
, 0 },
1190 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1191 CPU_GFNI_FLAGS
, 0 },
1192 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1193 CPU_VAES_FLAGS
, 0 },
1194 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1195 CPU_VPCLMULQDQ_FLAGS
, 0 },
1196 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1197 CPU_WBNOINVD_FLAGS
, 0 },
1198 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1199 CPU_PCONFIG_FLAGS
, 0 },
1200 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1201 CPU_WAITPKG_FLAGS
, 0 },
1202 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1203 CPU_CLDEMOTE_FLAGS
, 0 },
1204 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1205 CPU_AMX_INT8_FLAGS
, 0 },
1206 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1207 CPU_AMX_BF16_FLAGS
, 0 },
1208 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1209 CPU_AMX_TILE_FLAGS
, 0 },
1210 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1211 CPU_MOVDIRI_FLAGS
, 0 },
1212 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1213 CPU_MOVDIR64B_FLAGS
, 0 },
1214 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1215 CPU_AVX512_BF16_FLAGS
, 0 },
1216 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1217 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1218 { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN
,
1220 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1221 CPU_ENQCMD_FLAGS
, 0 },
1222 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1223 CPU_SERIALIZE_FLAGS
, 0 },
1224 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1225 CPU_RDPRU_FLAGS
, 0 },
1226 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1227 CPU_MCOMMIT_FLAGS
, 0 },
1228 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1229 CPU_SEV_ES_FLAGS
, 0 },
1230 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1231 CPU_TSXLDTRK_FLAGS
, 0 },
1232 { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN
,
1234 { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN
,
1235 CPU_WIDEKL_FLAGS
, 0 },
1236 { STRING_COMMA_LEN (".uintr"), PROCESSOR_UNKNOWN
,
1237 CPU_UINTR_FLAGS
, 0 },
1238 { STRING_COMMA_LEN (".hreset"), PROCESSOR_UNKNOWN
,
1239 CPU_HRESET_FLAGS
, 0 },
1242 static const noarch_entry cpu_noarch
[] =
1244 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1245 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1246 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1247 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1248 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1249 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1250 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1251 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1252 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1253 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1254 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1255 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1256 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1257 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1258 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1259 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1260 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1261 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1262 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1263 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1264 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1266 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1267 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1268 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1269 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1270 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1271 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1272 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1273 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1274 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1275 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1276 { STRING_COMMA_LEN ("noavx_vnni"), CPU_ANY_AVX_VNNI_FLAGS
},
1277 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1278 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1279 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1280 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1281 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1282 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1283 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1284 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1285 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1286 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1287 { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS
},
1288 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1289 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1290 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1291 { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS
},
1292 { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS
},
1293 { STRING_COMMA_LEN ("nouintr"), CPU_ANY_UINTR_FLAGS
},
1294 { STRING_COMMA_LEN ("nohreset"), CPU_ANY_HRESET_FLAGS
},
1298 /* Like s_lcomm_internal in gas/read.c but the alignment string
1299 is allowed to be optional. */
1302 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1309 && *input_line_pointer
== ',')
1311 align
= parse_align (needs_align
- 1);
1313 if (align
== (addressT
) -1)
1328 bss_alloc (symbolP
, size
, align
);
1333 pe_lcomm (int needs_align
)
1335 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1339 const pseudo_typeS md_pseudo_table
[] =
1341 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1342 {"align", s_align_bytes
, 0},
1344 {"align", s_align_ptwo
, 0},
1346 {"arch", set_cpu_arch
, 0},
1350 {"lcomm", pe_lcomm
, 1},
1352 {"ffloat", float_cons
, 'f'},
1353 {"dfloat", float_cons
, 'd'},
1354 {"tfloat", float_cons
, 'x'},
1356 {"slong", signed_cons
, 4},
1357 {"noopt", s_ignore
, 0},
1358 {"optim", s_ignore
, 0},
1359 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1360 {"code16", set_code_flag
, CODE_16BIT
},
1361 {"code32", set_code_flag
, CODE_32BIT
},
1363 {"code64", set_code_flag
, CODE_64BIT
},
1365 {"intel_syntax", set_intel_syntax
, 1},
1366 {"att_syntax", set_intel_syntax
, 0},
1367 {"intel_mnemonic", set_intel_mnemonic
, 1},
1368 {"att_mnemonic", set_intel_mnemonic
, 0},
1369 {"allow_index_reg", set_allow_index_reg
, 1},
1370 {"disallow_index_reg", set_allow_index_reg
, 0},
1371 {"sse_check", set_check
, 0},
1372 {"operand_check", set_check
, 1},
1373 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1374 {"largecomm", handle_large_common
, 0},
1376 {"file", dwarf2_directive_file
, 0},
1377 {"loc", dwarf2_directive_loc
, 0},
1378 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1381 {"secrel32", pe_directive_secrel
, 0},
1386 /* For interface with expression (). */
1387 extern char *input_line_pointer
;
1389 /* Hash table for instruction mnemonic lookup. */
1390 static htab_t op_hash
;
1392 /* Hash table for register lookup. */
1393 static htab_t reg_hash
;
1395 /* Various efficient no-op patterns for aligning code labels.
1396 Note: Don't try to assemble the instructions in the comments.
1397 0L and 0w are not legal. */
1398 static const unsigned char f32_1
[] =
1400 static const unsigned char f32_2
[] =
1401 {0x66,0x90}; /* xchg %ax,%ax */
1402 static const unsigned char f32_3
[] =
1403 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1404 static const unsigned char f32_4
[] =
1405 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1406 static const unsigned char f32_6
[] =
1407 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1408 static const unsigned char f32_7
[] =
1409 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1410 static const unsigned char f16_3
[] =
1411 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1412 static const unsigned char f16_4
[] =
1413 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1414 static const unsigned char jump_disp8
[] =
1415 {0xeb}; /* jmp disp8 */
1416 static const unsigned char jump32_disp32
[] =
1417 {0xe9}; /* jmp disp32 */
1418 static const unsigned char jump16_disp32
[] =
1419 {0x66,0xe9}; /* jmp disp32 */
1420 /* 32-bit NOPs patterns. */
1421 static const unsigned char *const f32_patt
[] = {
1422 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1424 /* 16-bit NOPs patterns. */
1425 static const unsigned char *const f16_patt
[] = {
1426 f32_1
, f32_2
, f16_3
, f16_4
1428 /* nopl (%[re]ax) */
1429 static const unsigned char alt_3
[] =
1431 /* nopl 0(%[re]ax) */
1432 static const unsigned char alt_4
[] =
1433 {0x0f,0x1f,0x40,0x00};
1434 /* nopl 0(%[re]ax,%[re]ax,1) */
1435 static const unsigned char alt_5
[] =
1436 {0x0f,0x1f,0x44,0x00,0x00};
1437 /* nopw 0(%[re]ax,%[re]ax,1) */
1438 static const unsigned char alt_6
[] =
1439 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1440 /* nopl 0L(%[re]ax) */
1441 static const unsigned char alt_7
[] =
1442 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1443 /* nopl 0L(%[re]ax,%[re]ax,1) */
1444 static const unsigned char alt_8
[] =
1445 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1446 /* nopw 0L(%[re]ax,%[re]ax,1) */
1447 static const unsigned char alt_9
[] =
1448 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1449 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1450 static const unsigned char alt_10
[] =
1451 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1452 /* data16 nopw %cs:0L(%eax,%eax,1) */
1453 static const unsigned char alt_11
[] =
1454 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1455 /* 32-bit and 64-bit NOPs patterns. */
1456 static const unsigned char *const alt_patt
[] = {
1457 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1458 alt_9
, alt_10
, alt_11
1461 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1462 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1465 i386_output_nops (char *where
, const unsigned char *const *patt
,
1466 int count
, int max_single_nop_size
)
1469 /* Place the longer NOP first. */
1472 const unsigned char *nops
;
1474 if (max_single_nop_size
< 1)
1476 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1477 max_single_nop_size
);
1481 nops
= patt
[max_single_nop_size
- 1];
1483 /* Use the smaller one if the requsted one isn't available. */
1486 max_single_nop_size
--;
1487 nops
= patt
[max_single_nop_size
- 1];
1490 last
= count
% max_single_nop_size
;
1493 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1494 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1498 nops
= patt
[last
- 1];
1501 /* Use the smaller one plus one-byte NOP if the needed one
1504 nops
= patt
[last
- 1];
1505 memcpy (where
+ offset
, nops
, last
);
1506 where
[offset
+ last
] = *patt
[0];
1509 memcpy (where
+ offset
, nops
, last
);
1514 fits_in_imm7 (offsetT num
)
1516 return (num
& 0x7f) == num
;
1520 fits_in_imm31 (offsetT num
)
1522 return (num
& 0x7fffffff) == num
;
1525 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1526 single NOP instruction LIMIT. */
1529 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1531 const unsigned char *const *patt
= NULL
;
1532 int max_single_nop_size
;
1533 /* Maximum number of NOPs before switching to jump over NOPs. */
1534 int max_number_of_nops
;
1536 switch (fragP
->fr_type
)
1541 case rs_machine_dependent
:
1542 /* Allow NOP padding for jumps and calls. */
1543 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1544 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1551 /* We need to decide which NOP sequence to use for 32bit and
1552 64bit. When -mtune= is used:
1554 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1555 PROCESSOR_GENERIC32, f32_patt will be used.
1556 2. For the rest, alt_patt will be used.
1558 When -mtune= isn't used, alt_patt will be used if
1559 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1562 When -march= or .arch is used, we can't use anything beyond
1563 cpu_arch_isa_flags. */
1565 if (flag_code
== CODE_16BIT
)
1568 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1569 /* Limit number of NOPs to 2 in 16-bit mode. */
1570 max_number_of_nops
= 2;
1574 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1576 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1577 switch (cpu_arch_tune
)
1579 case PROCESSOR_UNKNOWN
:
1580 /* We use cpu_arch_isa_flags to check if we SHOULD
1581 optimize with nops. */
1582 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1587 case PROCESSOR_PENTIUM4
:
1588 case PROCESSOR_NOCONA
:
1589 case PROCESSOR_CORE
:
1590 case PROCESSOR_CORE2
:
1591 case PROCESSOR_COREI7
:
1592 case PROCESSOR_L1OM
:
1593 case PROCESSOR_K1OM
:
1594 case PROCESSOR_GENERIC64
:
1596 case PROCESSOR_ATHLON
:
1598 case PROCESSOR_AMDFAM10
:
1600 case PROCESSOR_ZNVER
:
1604 case PROCESSOR_I386
:
1605 case PROCESSOR_I486
:
1606 case PROCESSOR_PENTIUM
:
1607 case PROCESSOR_PENTIUMPRO
:
1608 case PROCESSOR_IAMCU
:
1609 case PROCESSOR_GENERIC32
:
1616 switch (fragP
->tc_frag_data
.tune
)
1618 case PROCESSOR_UNKNOWN
:
1619 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1620 PROCESSOR_UNKNOWN. */
1624 case PROCESSOR_I386
:
1625 case PROCESSOR_I486
:
1626 case PROCESSOR_PENTIUM
:
1627 case PROCESSOR_IAMCU
:
1629 case PROCESSOR_ATHLON
:
1631 case PROCESSOR_AMDFAM10
:
1633 case PROCESSOR_ZNVER
:
1635 case PROCESSOR_GENERIC32
:
1636 /* We use cpu_arch_isa_flags to check if we CAN optimize
1638 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1643 case PROCESSOR_PENTIUMPRO
:
1644 case PROCESSOR_PENTIUM4
:
1645 case PROCESSOR_NOCONA
:
1646 case PROCESSOR_CORE
:
1647 case PROCESSOR_CORE2
:
1648 case PROCESSOR_COREI7
:
1649 case PROCESSOR_L1OM
:
1650 case PROCESSOR_K1OM
:
1651 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1656 case PROCESSOR_GENERIC64
:
1662 if (patt
== f32_patt
)
1664 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1665 /* Limit number of NOPs to 2 for older processors. */
1666 max_number_of_nops
= 2;
1670 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1671 /* Limit number of NOPs to 7 for newer processors. */
1672 max_number_of_nops
= 7;
1677 limit
= max_single_nop_size
;
1679 if (fragP
->fr_type
== rs_fill_nop
)
1681 /* Output NOPs for .nop directive. */
1682 if (limit
> max_single_nop_size
)
1684 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1685 _("invalid single nop size: %d "
1686 "(expect within [0, %d])"),
1687 limit
, max_single_nop_size
);
1691 else if (fragP
->fr_type
!= rs_machine_dependent
)
1692 fragP
->fr_var
= count
;
1694 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1696 /* Generate jump over NOPs. */
1697 offsetT disp
= count
- 2;
1698 if (fits_in_imm7 (disp
))
1700 /* Use "jmp disp8" if possible. */
1702 where
[0] = jump_disp8
[0];
1708 unsigned int size_of_jump
;
1710 if (flag_code
== CODE_16BIT
)
1712 where
[0] = jump16_disp32
[0];
1713 where
[1] = jump16_disp32
[1];
1718 where
[0] = jump32_disp32
[0];
1722 count
-= size_of_jump
+ 4;
1723 if (!fits_in_imm31 (count
))
1725 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1726 _("jump over nop padding out of range"));
1730 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1731 where
+= size_of_jump
+ 4;
1735 /* Generate multiple NOPs. */
1736 i386_output_nops (where
, patt
, count
, limit
);
1740 operand_type_all_zero (const union i386_operand_type
*x
)
1742 switch (ARRAY_SIZE(x
->array
))
1753 return !x
->array
[0];
1760 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1762 switch (ARRAY_SIZE(x
->array
))
1778 x
->bitfield
.class = ClassNone
;
1779 x
->bitfield
.instance
= InstanceNone
;
1783 operand_type_equal (const union i386_operand_type
*x
,
1784 const union i386_operand_type
*y
)
1786 switch (ARRAY_SIZE(x
->array
))
1789 if (x
->array
[2] != y
->array
[2])
1793 if (x
->array
[1] != y
->array
[1])
1797 return x
->array
[0] == y
->array
[0];
1805 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1807 switch (ARRAY_SIZE(x
->array
))
1822 return !x
->array
[0];
1829 cpu_flags_equal (const union i386_cpu_flags
*x
,
1830 const union i386_cpu_flags
*y
)
1832 switch (ARRAY_SIZE(x
->array
))
1835 if (x
->array
[3] != y
->array
[3])
1839 if (x
->array
[2] != y
->array
[2])
1843 if (x
->array
[1] != y
->array
[1])
1847 return x
->array
[0] == y
->array
[0];
1855 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1857 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1858 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1861 static INLINE i386_cpu_flags
1862 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1864 switch (ARRAY_SIZE (x
.array
))
1867 x
.array
[3] &= y
.array
[3];
1870 x
.array
[2] &= y
.array
[2];
1873 x
.array
[1] &= y
.array
[1];
1876 x
.array
[0] &= y
.array
[0];
1884 static INLINE i386_cpu_flags
1885 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1887 switch (ARRAY_SIZE (x
.array
))
1890 x
.array
[3] |= y
.array
[3];
1893 x
.array
[2] |= y
.array
[2];
1896 x
.array
[1] |= y
.array
[1];
1899 x
.array
[0] |= y
.array
[0];
1907 static INLINE i386_cpu_flags
1908 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1910 switch (ARRAY_SIZE (x
.array
))
1913 x
.array
[3] &= ~y
.array
[3];
1916 x
.array
[2] &= ~y
.array
[2];
1919 x
.array
[1] &= ~y
.array
[1];
1922 x
.array
[0] &= ~y
.array
[0];
1930 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1932 #define CPU_FLAGS_ARCH_MATCH 0x1
1933 #define CPU_FLAGS_64BIT_MATCH 0x2
1935 #define CPU_FLAGS_PERFECT_MATCH \
1936 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1938 /* Return CPU flags match bits. */
1941 cpu_flags_match (const insn_template
*t
)
1943 i386_cpu_flags x
= t
->cpu_flags
;
1944 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1946 x
.bitfield
.cpu64
= 0;
1947 x
.bitfield
.cpuno64
= 0;
1949 if (cpu_flags_all_zero (&x
))
1951 /* This instruction is available on all archs. */
1952 match
|= CPU_FLAGS_ARCH_MATCH
;
1956 /* This instruction is available only on some archs. */
1957 i386_cpu_flags cpu
= cpu_arch_flags
;
1959 /* AVX512VL is no standalone feature - match it and then strip it. */
1960 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1962 x
.bitfield
.cpuavx512vl
= 0;
1964 cpu
= cpu_flags_and (x
, cpu
);
1965 if (!cpu_flags_all_zero (&cpu
))
1967 if (x
.bitfield
.cpuavx
)
1969 /* We need to check a few extra flags with AVX. */
1970 if (cpu
.bitfield
.cpuavx
1971 && (!t
->opcode_modifier
.sse2avx
1972 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1973 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1974 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1975 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1976 match
|= CPU_FLAGS_ARCH_MATCH
;
1978 else if (x
.bitfield
.cpuavx512f
)
1980 /* We need to check a few extra flags with AVX512F. */
1981 if (cpu
.bitfield
.cpuavx512f
1982 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1983 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1984 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1985 match
|= CPU_FLAGS_ARCH_MATCH
;
1988 match
|= CPU_FLAGS_ARCH_MATCH
;
1994 static INLINE i386_operand_type
1995 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1997 if (x
.bitfield
.class != y
.bitfield
.class)
1998 x
.bitfield
.class = ClassNone
;
1999 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
2000 x
.bitfield
.instance
= InstanceNone
;
2002 switch (ARRAY_SIZE (x
.array
))
2005 x
.array
[2] &= y
.array
[2];
2008 x
.array
[1] &= y
.array
[1];
2011 x
.array
[0] &= y
.array
[0];
2019 static INLINE i386_operand_type
2020 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2022 gas_assert (y
.bitfield
.class == ClassNone
);
2023 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2025 switch (ARRAY_SIZE (x
.array
))
2028 x
.array
[2] &= ~y
.array
[2];
2031 x
.array
[1] &= ~y
.array
[1];
2034 x
.array
[0] &= ~y
.array
[0];
2042 static INLINE i386_operand_type
2043 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2045 gas_assert (x
.bitfield
.class == ClassNone
||
2046 y
.bitfield
.class == ClassNone
||
2047 x
.bitfield
.class == y
.bitfield
.class);
2048 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2049 y
.bitfield
.instance
== InstanceNone
||
2050 x
.bitfield
.instance
== y
.bitfield
.instance
);
2052 switch (ARRAY_SIZE (x
.array
))
2055 x
.array
[2] |= y
.array
[2];
2058 x
.array
[1] |= y
.array
[1];
2061 x
.array
[0] |= y
.array
[0];
2069 static INLINE i386_operand_type
2070 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2072 gas_assert (y
.bitfield
.class == ClassNone
);
2073 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2075 switch (ARRAY_SIZE (x
.array
))
2078 x
.array
[2] ^= y
.array
[2];
2081 x
.array
[1] ^= y
.array
[1];
2084 x
.array
[0] ^= y
.array
[0];
2092 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2093 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2094 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2095 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2096 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2097 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2098 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2099 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2100 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2101 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2102 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2103 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2104 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2105 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2106 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2107 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2108 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2119 operand_type_check (i386_operand_type t
, enum operand_type c
)
2124 return t
.bitfield
.class == Reg
;
2127 return (t
.bitfield
.imm8
2131 || t
.bitfield
.imm32s
2132 || t
.bitfield
.imm64
);
2135 return (t
.bitfield
.disp8
2136 || t
.bitfield
.disp16
2137 || t
.bitfield
.disp32
2138 || t
.bitfield
.disp32s
2139 || t
.bitfield
.disp64
);
2142 return (t
.bitfield
.disp8
2143 || t
.bitfield
.disp16
2144 || t
.bitfield
.disp32
2145 || t
.bitfield
.disp32s
2146 || t
.bitfield
.disp64
2147 || t
.bitfield
.baseindex
);
2156 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2157 between operand GIVEN and opeand WANTED for instruction template T. */
2160 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2163 return !((i
.types
[given
].bitfield
.byte
2164 && !t
->operand_types
[wanted
].bitfield
.byte
)
2165 || (i
.types
[given
].bitfield
.word
2166 && !t
->operand_types
[wanted
].bitfield
.word
)
2167 || (i
.types
[given
].bitfield
.dword
2168 && !t
->operand_types
[wanted
].bitfield
.dword
)
2169 || (i
.types
[given
].bitfield
.qword
2170 && !t
->operand_types
[wanted
].bitfield
.qword
)
2171 || (i
.types
[given
].bitfield
.tbyte
2172 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2175 /* Return 1 if there is no conflict in SIMD register between operand
2176 GIVEN and opeand WANTED for instruction template T. */
2179 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2182 return !((i
.types
[given
].bitfield
.xmmword
2183 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2184 || (i
.types
[given
].bitfield
.ymmword
2185 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2186 || (i
.types
[given
].bitfield
.zmmword
2187 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2188 || (i
.types
[given
].bitfield
.tmmword
2189 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2192 /* Return 1 if there is no conflict in any size between operand GIVEN
2193 and opeand WANTED for instruction template T. */
2196 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2199 return (match_operand_size (t
, wanted
, given
)
2200 && !((i
.types
[given
].bitfield
.unspecified
2201 && !i
.broadcast
.type
2202 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2203 || (i
.types
[given
].bitfield
.fword
2204 && !t
->operand_types
[wanted
].bitfield
.fword
)
2205 /* For scalar opcode templates to allow register and memory
2206 operands at the same time, some special casing is needed
2207 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2208 down-conversion vpmov*. */
2209 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2210 && t
->operand_types
[wanted
].bitfield
.byte
2211 + t
->operand_types
[wanted
].bitfield
.word
2212 + t
->operand_types
[wanted
].bitfield
.dword
2213 + t
->operand_types
[wanted
].bitfield
.qword
2214 > !!t
->opcode_modifier
.broadcast
)
2215 ? (i
.types
[given
].bitfield
.xmmword
2216 || i
.types
[given
].bitfield
.ymmword
2217 || i
.types
[given
].bitfield
.zmmword
)
2218 : !match_simd_size(t
, wanted
, given
))));
2221 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2222 operands for instruction template T, and it has MATCH_REVERSE set if there
2223 is no size conflict on any operands for the template with operands reversed
2224 (and the template allows for reversing in the first place). */
2226 #define MATCH_STRAIGHT 1
2227 #define MATCH_REVERSE 2
2229 static INLINE
unsigned int
2230 operand_size_match (const insn_template
*t
)
2232 unsigned int j
, match
= MATCH_STRAIGHT
;
2234 /* Don't check non-absolute jump instructions. */
2235 if (t
->opcode_modifier
.jump
2236 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2239 /* Check memory and accumulator operand size. */
2240 for (j
= 0; j
< i
.operands
; j
++)
2242 if (i
.types
[j
].bitfield
.class != Reg
2243 && i
.types
[j
].bitfield
.class != RegSIMD
2244 && t
->opcode_modifier
.anysize
)
2247 if (t
->operand_types
[j
].bitfield
.class == Reg
2248 && !match_operand_size (t
, j
, j
))
2254 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2255 && !match_simd_size (t
, j
, j
))
2261 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2262 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2268 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2275 if (!t
->opcode_modifier
.d
)
2279 i
.error
= operand_size_mismatch
;
2283 /* Check reverse. */
2284 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2286 for (j
= 0; j
< i
.operands
; j
++)
2288 unsigned int given
= i
.operands
- j
- 1;
2290 if (t
->operand_types
[j
].bitfield
.class == Reg
2291 && !match_operand_size (t
, j
, given
))
2294 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2295 && !match_simd_size (t
, j
, given
))
2298 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2299 && (!match_operand_size (t
, j
, given
)
2300 || !match_simd_size (t
, j
, given
)))
2303 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2307 return match
| MATCH_REVERSE
;
2311 operand_type_match (i386_operand_type overlap
,
2312 i386_operand_type given
)
2314 i386_operand_type temp
= overlap
;
2316 temp
.bitfield
.unspecified
= 0;
2317 temp
.bitfield
.byte
= 0;
2318 temp
.bitfield
.word
= 0;
2319 temp
.bitfield
.dword
= 0;
2320 temp
.bitfield
.fword
= 0;
2321 temp
.bitfield
.qword
= 0;
2322 temp
.bitfield
.tbyte
= 0;
2323 temp
.bitfield
.xmmword
= 0;
2324 temp
.bitfield
.ymmword
= 0;
2325 temp
.bitfield
.zmmword
= 0;
2326 temp
.bitfield
.tmmword
= 0;
2327 if (operand_type_all_zero (&temp
))
2330 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2334 i
.error
= operand_type_mismatch
;
2338 /* If given types g0 and g1 are registers they must be of the same type
2339 unless the expected operand type register overlap is null.
2340 Some Intel syntax memory operand size checking also happens here. */
2343 operand_type_register_match (i386_operand_type g0
,
2344 i386_operand_type t0
,
2345 i386_operand_type g1
,
2346 i386_operand_type t1
)
2348 if (g0
.bitfield
.class != Reg
2349 && g0
.bitfield
.class != RegSIMD
2350 && (!operand_type_check (g0
, anymem
)
2351 || g0
.bitfield
.unspecified
2352 || (t0
.bitfield
.class != Reg
2353 && t0
.bitfield
.class != RegSIMD
)))
2356 if (g1
.bitfield
.class != Reg
2357 && g1
.bitfield
.class != RegSIMD
2358 && (!operand_type_check (g1
, anymem
)
2359 || g1
.bitfield
.unspecified
2360 || (t1
.bitfield
.class != Reg
2361 && t1
.bitfield
.class != RegSIMD
)))
2364 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2365 && g0
.bitfield
.word
== g1
.bitfield
.word
2366 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2367 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2368 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2369 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2370 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2373 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2374 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2375 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2376 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2377 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2378 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2379 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2382 i
.error
= register_type_mismatch
;
2387 static INLINE
unsigned int
2388 register_number (const reg_entry
*r
)
2390 unsigned int nr
= r
->reg_num
;
2392 if (r
->reg_flags
& RegRex
)
2395 if (r
->reg_flags
& RegVRex
)
2401 static INLINE
unsigned int
2402 mode_from_disp_size (i386_operand_type t
)
2404 if (t
.bitfield
.disp8
)
2406 else if (t
.bitfield
.disp16
2407 || t
.bitfield
.disp32
2408 || t
.bitfield
.disp32s
)
2415 fits_in_signed_byte (addressT num
)
2417 return num
+ 0x80 <= 0xff;
2421 fits_in_unsigned_byte (addressT num
)
2427 fits_in_unsigned_word (addressT num
)
2429 return num
<= 0xffff;
2433 fits_in_signed_word (addressT num
)
2435 return num
+ 0x8000 <= 0xffff;
2439 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2444 return num
+ 0x80000000 <= 0xffffffff;
2446 } /* fits_in_signed_long() */
2449 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2454 return num
<= 0xffffffff;
2456 } /* fits_in_unsigned_long() */
2458 static INLINE valueT
extend_to_32bit_address (addressT num
)
2461 if (fits_in_unsigned_long(num
))
2462 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2464 if (!fits_in_signed_long (num
))
2465 return num
& 0xffffffff;
2472 fits_in_disp8 (offsetT num
)
2474 int shift
= i
.memshift
;
2480 mask
= (1 << shift
) - 1;
2482 /* Return 0 if NUM isn't properly aligned. */
2486 /* Check if NUM will fit in 8bit after shift. */
2487 return fits_in_signed_byte (num
>> shift
);
2491 fits_in_imm4 (offsetT num
)
2493 return (num
& 0xf) == num
;
2496 static i386_operand_type
2497 smallest_imm_type (offsetT num
)
2499 i386_operand_type t
;
2501 operand_type_set (&t
, 0);
2502 t
.bitfield
.imm64
= 1;
2504 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2506 /* This code is disabled on the 486 because all the Imm1 forms
2507 in the opcode table are slower on the i486. They're the
2508 versions with the implicitly specified single-position
2509 displacement, which has another syntax if you really want to
2511 t
.bitfield
.imm1
= 1;
2512 t
.bitfield
.imm8
= 1;
2513 t
.bitfield
.imm8s
= 1;
2514 t
.bitfield
.imm16
= 1;
2515 t
.bitfield
.imm32
= 1;
2516 t
.bitfield
.imm32s
= 1;
2518 else if (fits_in_signed_byte (num
))
2520 t
.bitfield
.imm8
= 1;
2521 t
.bitfield
.imm8s
= 1;
2522 t
.bitfield
.imm16
= 1;
2523 t
.bitfield
.imm32
= 1;
2524 t
.bitfield
.imm32s
= 1;
2526 else if (fits_in_unsigned_byte (num
))
2528 t
.bitfield
.imm8
= 1;
2529 t
.bitfield
.imm16
= 1;
2530 t
.bitfield
.imm32
= 1;
2531 t
.bitfield
.imm32s
= 1;
2533 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2535 t
.bitfield
.imm16
= 1;
2536 t
.bitfield
.imm32
= 1;
2537 t
.bitfield
.imm32s
= 1;
2539 else if (fits_in_signed_long (num
))
2541 t
.bitfield
.imm32
= 1;
2542 t
.bitfield
.imm32s
= 1;
2544 else if (fits_in_unsigned_long (num
))
2545 t
.bitfield
.imm32
= 1;
2551 offset_in_range (offsetT val
, int size
)
2557 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2558 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2559 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2561 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2566 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2568 char buf1
[40], buf2
[40];
2570 bfd_sprintf_vma (stdoutput
, buf1
, val
);
2571 bfd_sprintf_vma (stdoutput
, buf2
, val
& mask
);
2572 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2587 a. PREFIX_EXIST if attempting to add a prefix where one from the
2588 same class already exists.
2589 b. PREFIX_LOCK if lock prefix is added.
2590 c. PREFIX_REP if rep/repne prefix is added.
2591 d. PREFIX_DS if ds prefix is added.
2592 e. PREFIX_OTHER if other prefix is added.
2595 static enum PREFIX_GROUP
2596 add_prefix (unsigned int prefix
)
2598 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2601 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2602 && flag_code
== CODE_64BIT
)
2604 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2605 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2606 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2607 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2618 case DS_PREFIX_OPCODE
:
2621 case CS_PREFIX_OPCODE
:
2622 case ES_PREFIX_OPCODE
:
2623 case FS_PREFIX_OPCODE
:
2624 case GS_PREFIX_OPCODE
:
2625 case SS_PREFIX_OPCODE
:
2629 case REPNE_PREFIX_OPCODE
:
2630 case REPE_PREFIX_OPCODE
:
2635 case LOCK_PREFIX_OPCODE
:
2644 case ADDR_PREFIX_OPCODE
:
2648 case DATA_PREFIX_OPCODE
:
2652 if (i
.prefix
[q
] != 0)
2660 i
.prefix
[q
] |= prefix
;
2663 as_bad (_("same type of prefix used twice"));
2669 update_code_flag (int value
, int check
)
2671 PRINTF_LIKE ((*as_error
));
2673 flag_code
= (enum flag_code
) value
;
2674 if (flag_code
== CODE_64BIT
)
2676 cpu_arch_flags
.bitfield
.cpu64
= 1;
2677 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2681 cpu_arch_flags
.bitfield
.cpu64
= 0;
2682 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2684 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2687 as_error
= as_fatal
;
2690 (*as_error
) (_("64bit mode not supported on `%s'."),
2691 cpu_arch_name
? cpu_arch_name
: default_arch
);
2693 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2696 as_error
= as_fatal
;
2699 (*as_error
) (_("32bit mode not supported on `%s'."),
2700 cpu_arch_name
? cpu_arch_name
: default_arch
);
2702 stackop_size
= '\0';
2706 set_code_flag (int value
)
2708 update_code_flag (value
, 0);
2712 set_16bit_gcc_code_flag (int new_code_flag
)
2714 flag_code
= (enum flag_code
) new_code_flag
;
2715 if (flag_code
!= CODE_16BIT
)
2717 cpu_arch_flags
.bitfield
.cpu64
= 0;
2718 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2719 stackop_size
= LONG_MNEM_SUFFIX
;
2723 set_intel_syntax (int syntax_flag
)
2725 /* Find out if register prefixing is specified. */
2726 int ask_naked_reg
= 0;
2729 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2732 int e
= get_symbol_name (&string
);
2734 if (strcmp (string
, "prefix") == 0)
2736 else if (strcmp (string
, "noprefix") == 0)
2739 as_bad (_("bad argument to syntax directive."));
2740 (void) restore_line_pointer (e
);
2742 demand_empty_rest_of_line ();
2744 intel_syntax
= syntax_flag
;
2746 if (ask_naked_reg
== 0)
2747 allow_naked_reg
= (intel_syntax
2748 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2750 allow_naked_reg
= (ask_naked_reg
< 0);
2752 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2754 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2755 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2756 register_prefix
= allow_naked_reg
? "" : "%";
2760 set_intel_mnemonic (int mnemonic_flag
)
2762 intel_mnemonic
= mnemonic_flag
;
2766 set_allow_index_reg (int flag
)
2768 allow_index_reg
= flag
;
2772 set_check (int what
)
2774 enum check_kind
*kind
;
2779 kind
= &operand_check
;
2790 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2793 int e
= get_symbol_name (&string
);
2795 if (strcmp (string
, "none") == 0)
2797 else if (strcmp (string
, "warning") == 0)
2798 *kind
= check_warning
;
2799 else if (strcmp (string
, "error") == 0)
2800 *kind
= check_error
;
2802 as_bad (_("bad argument to %s_check directive."), str
);
2803 (void) restore_line_pointer (e
);
2806 as_bad (_("missing argument for %s_check directive"), str
);
2808 demand_empty_rest_of_line ();
2812 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2813 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2815 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2816 static const char *arch
;
2818 /* Intel LIOM is only supported on ELF. */
2824 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2825 use default_arch. */
2826 arch
= cpu_arch_name
;
2828 arch
= default_arch
;
2831 /* If we are targeting Intel MCU, we must enable it. */
2832 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2833 || new_flag
.bitfield
.cpuiamcu
)
2836 /* If we are targeting Intel L1OM, we must enable it. */
2837 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2838 || new_flag
.bitfield
.cpul1om
)
2841 /* If we are targeting Intel K1OM, we must enable it. */
2842 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2843 || new_flag
.bitfield
.cpuk1om
)
2846 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2851 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2855 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2858 int e
= get_symbol_name (&string
);
2860 i386_cpu_flags flags
;
2862 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2864 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2866 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2870 cpu_arch_name
= cpu_arch
[j
].name
;
2871 cpu_sub_arch_name
= NULL
;
2872 cpu_arch_flags
= cpu_arch
[j
].flags
;
2873 if (flag_code
== CODE_64BIT
)
2875 cpu_arch_flags
.bitfield
.cpu64
= 1;
2876 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2880 cpu_arch_flags
.bitfield
.cpu64
= 0;
2881 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2883 cpu_arch_isa
= cpu_arch
[j
].type
;
2884 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2885 if (!cpu_arch_tune_set
)
2887 cpu_arch_tune
= cpu_arch_isa
;
2888 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2893 flags
= cpu_flags_or (cpu_arch_flags
,
2896 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2898 if (cpu_sub_arch_name
)
2900 char *name
= cpu_sub_arch_name
;
2901 cpu_sub_arch_name
= concat (name
,
2903 (const char *) NULL
);
2907 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2908 cpu_arch_flags
= flags
;
2909 cpu_arch_isa_flags
= flags
;
2913 = cpu_flags_or (cpu_arch_isa_flags
,
2915 (void) restore_line_pointer (e
);
2916 demand_empty_rest_of_line ();
2921 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2923 /* Disable an ISA extension. */
2924 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2925 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2927 flags
= cpu_flags_and_not (cpu_arch_flags
,
2928 cpu_noarch
[j
].flags
);
2929 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2931 if (cpu_sub_arch_name
)
2933 char *name
= cpu_sub_arch_name
;
2934 cpu_sub_arch_name
= concat (name
, string
,
2935 (const char *) NULL
);
2939 cpu_sub_arch_name
= xstrdup (string
);
2940 cpu_arch_flags
= flags
;
2941 cpu_arch_isa_flags
= flags
;
2943 (void) restore_line_pointer (e
);
2944 demand_empty_rest_of_line ();
2948 j
= ARRAY_SIZE (cpu_arch
);
2951 if (j
>= ARRAY_SIZE (cpu_arch
))
2952 as_bad (_("no such architecture: `%s'"), string
);
2954 *input_line_pointer
= e
;
2957 as_bad (_("missing cpu architecture"));
2959 no_cond_jump_promotion
= 0;
2960 if (*input_line_pointer
== ','
2961 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2966 ++input_line_pointer
;
2967 e
= get_symbol_name (&string
);
2969 if (strcmp (string
, "nojumps") == 0)
2970 no_cond_jump_promotion
= 1;
2971 else if (strcmp (string
, "jumps") == 0)
2974 as_bad (_("no such architecture modifier: `%s'"), string
);
2976 (void) restore_line_pointer (e
);
2979 demand_empty_rest_of_line ();
2982 enum bfd_architecture
2985 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2987 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2988 || flag_code
!= CODE_64BIT
)
2989 as_fatal (_("Intel L1OM is 64bit ELF only"));
2990 return bfd_arch_l1om
;
2992 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2994 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2995 || flag_code
!= CODE_64BIT
)
2996 as_fatal (_("Intel K1OM is 64bit ELF only"));
2997 return bfd_arch_k1om
;
2999 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3001 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3002 || flag_code
== CODE_64BIT
)
3003 as_fatal (_("Intel MCU is 32bit ELF only"));
3004 return bfd_arch_iamcu
;
3007 return bfd_arch_i386
;
3013 if (startswith (default_arch
, "x86_64"))
3015 if (cpu_arch_isa
== PROCESSOR_L1OM
)
3017 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3018 || default_arch
[6] != '\0')
3019 as_fatal (_("Intel L1OM is 64bit ELF only"));
3020 return bfd_mach_l1om
;
3022 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3024 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3025 || default_arch
[6] != '\0')
3026 as_fatal (_("Intel K1OM is 64bit ELF only"));
3027 return bfd_mach_k1om
;
3029 else if (default_arch
[6] == '\0')
3030 return bfd_mach_x86_64
;
3032 return bfd_mach_x64_32
;
3034 else if (!strcmp (default_arch
, "i386")
3035 || !strcmp (default_arch
, "iamcu"))
3037 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3039 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3040 as_fatal (_("Intel MCU is 32bit ELF only"));
3041 return bfd_mach_i386_iamcu
;
3044 return bfd_mach_i386_i386
;
3047 as_fatal (_("unknown architecture"));
3053 /* Support pseudo prefixes like {disp32}. */
3054 lex_type
['{'] = LEX_BEGIN_NAME
;
3056 /* Initialize op_hash hash table. */
3057 op_hash
= str_htab_create ();
3060 const insn_template
*optab
;
3061 templates
*core_optab
;
3063 /* Setup for loop. */
3065 core_optab
= XNEW (templates
);
3066 core_optab
->start
= optab
;
3071 if (optab
->name
== NULL
3072 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3074 /* different name --> ship out current template list;
3075 add to hash table; & begin anew. */
3076 core_optab
->end
= optab
;
3077 if (str_hash_insert (op_hash
, (optab
- 1)->name
, core_optab
, 0))
3078 as_fatal (_("duplicate %s"), (optab
- 1)->name
);
3080 if (optab
->name
== NULL
)
3082 core_optab
= XNEW (templates
);
3083 core_optab
->start
= optab
;
3088 /* Initialize reg_hash hash table. */
3089 reg_hash
= str_htab_create ();
3091 const reg_entry
*regtab
;
3092 unsigned int regtab_size
= i386_regtab_size
;
3094 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3096 switch (regtab
->reg_type
.bitfield
.class)
3099 if (regtab
->reg_type
.bitfield
.dword
)
3101 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3104 else if (regtab
->reg_type
.bitfield
.tbyte
)
3106 /* There's no point inserting st(<N>) in the hash table, as
3107 parentheses aren't included in register_chars[] anyway. */
3108 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3115 switch (regtab
->reg_num
)
3117 case 0: reg_es
= regtab
; break;
3118 case 2: reg_ss
= regtab
; break;
3119 case 3: reg_ds
= regtab
; break;
3124 if (!regtab
->reg_num
)
3129 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3130 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3134 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3139 for (c
= 0; c
< 256; c
++)
3141 if (ISDIGIT (c
) || ISLOWER (c
))
3143 mnemonic_chars
[c
] = c
;
3144 register_chars
[c
] = c
;
3145 operand_chars
[c
] = c
;
3147 else if (ISUPPER (c
))
3149 mnemonic_chars
[c
] = TOLOWER (c
);
3150 register_chars
[c
] = mnemonic_chars
[c
];
3151 operand_chars
[c
] = c
;
3153 else if (c
== '{' || c
== '}')
3155 mnemonic_chars
[c
] = c
;
3156 operand_chars
[c
] = c
;
3158 #ifdef SVR4_COMMENT_CHARS
3159 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3160 operand_chars
[c
] = c
;
3163 if (ISALPHA (c
) || ISDIGIT (c
))
3164 identifier_chars
[c
] = c
;
3167 identifier_chars
[c
] = c
;
3168 operand_chars
[c
] = c
;
3173 identifier_chars
['@'] = '@';
3176 identifier_chars
['?'] = '?';
3177 operand_chars
['?'] = '?';
3179 mnemonic_chars
['_'] = '_';
3180 mnemonic_chars
['-'] = '-';
3181 mnemonic_chars
['.'] = '.';
3182 identifier_chars
['_'] = '_';
3183 identifier_chars
['.'] = '.';
3185 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3186 operand_chars
[(unsigned char) *p
] = *p
;
3189 if (flag_code
== CODE_64BIT
)
3191 #if defined (OBJ_COFF) && defined (TE_PE)
3192 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3195 x86_dwarf2_return_column
= 16;
3197 x86_cie_data_alignment
= -8;
3201 x86_dwarf2_return_column
= 8;
3202 x86_cie_data_alignment
= -4;
3205 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3206 can be turned into BRANCH_PREFIX frag. */
3207 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3212 i386_print_statistics (FILE *file
)
3214 htab_print_statistics (file
, "i386 opcode", op_hash
);
3215 htab_print_statistics (file
, "i386 register", reg_hash
);
3220 /* Debugging routines for md_assemble. */
3221 static void pte (insn_template
*);
3222 static void pt (i386_operand_type
);
3223 static void pe (expressionS
*);
3224 static void ps (symbolS
*);
3227 pi (const char *line
, i386_insn
*x
)
3231 fprintf (stdout
, "%s: template ", line
);
3233 fprintf (stdout
, " address: base %s index %s scale %x\n",
3234 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3235 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3236 x
->log2_scale_factor
);
3237 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3238 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3239 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3240 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3241 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3242 (x
->rex
& REX_W
) != 0,
3243 (x
->rex
& REX_R
) != 0,
3244 (x
->rex
& REX_X
) != 0,
3245 (x
->rex
& REX_B
) != 0);
3246 for (j
= 0; j
< x
->operands
; j
++)
3248 fprintf (stdout
, " #%d: ", j
+ 1);
3250 fprintf (stdout
, "\n");
3251 if (x
->types
[j
].bitfield
.class == Reg
3252 || x
->types
[j
].bitfield
.class == RegMMX
3253 || x
->types
[j
].bitfield
.class == RegSIMD
3254 || x
->types
[j
].bitfield
.class == RegMask
3255 || x
->types
[j
].bitfield
.class == SReg
3256 || x
->types
[j
].bitfield
.class == RegCR
3257 || x
->types
[j
].bitfield
.class == RegDR
3258 || x
->types
[j
].bitfield
.class == RegTR
3259 || x
->types
[j
].bitfield
.class == RegBND
)
3260 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3261 if (operand_type_check (x
->types
[j
], imm
))
3263 if (operand_type_check (x
->types
[j
], disp
))
3264 pe (x
->op
[j
].disps
);
3269 pte (insn_template
*t
)
3271 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3272 static const char *const opc_spc
[] = {
3273 NULL
, "0f", "0f38", "0f3a", NULL
, NULL
, NULL
, NULL
,
3274 "XOP08", "XOP09", "XOP0A",
3278 fprintf (stdout
, " %d operands ", t
->operands
);
3279 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3280 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3281 if (opc_spc
[t
->opcode_modifier
.opcodespace
])
3282 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_modifier
.opcodespace
]);
3283 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3284 if (t
->extension_opcode
!= None
)
3285 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3286 if (t
->opcode_modifier
.d
)
3287 fprintf (stdout
, "D");
3288 if (t
->opcode_modifier
.w
)
3289 fprintf (stdout
, "W");
3290 fprintf (stdout
, "\n");
3291 for (j
= 0; j
< t
->operands
; j
++)
3293 fprintf (stdout
, " #%d type ", j
+ 1);
3294 pt (t
->operand_types
[j
]);
3295 fprintf (stdout
, "\n");
3302 fprintf (stdout
, " operation %d\n", e
->X_op
);
3303 fprintf (stdout
, " add_number %" BFD_VMA_FMT
"d (%" BFD_VMA_FMT
"x)\n",
3304 e
->X_add_number
, e
->X_add_number
);
3305 if (e
->X_add_symbol
)
3307 fprintf (stdout
, " add_symbol ");
3308 ps (e
->X_add_symbol
);
3309 fprintf (stdout
, "\n");
3313 fprintf (stdout
, " op_symbol ");
3314 ps (e
->X_op_symbol
);
3315 fprintf (stdout
, "\n");
3322 fprintf (stdout
, "%s type %s%s",
3324 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3325 segment_name (S_GET_SEGMENT (s
)));
3328 static struct type_name
3330 i386_operand_type mask
;
3333 const type_names
[] =
3335 { OPERAND_TYPE_REG8
, "r8" },
3336 { OPERAND_TYPE_REG16
, "r16" },
3337 { OPERAND_TYPE_REG32
, "r32" },
3338 { OPERAND_TYPE_REG64
, "r64" },
3339 { OPERAND_TYPE_ACC8
, "acc8" },
3340 { OPERAND_TYPE_ACC16
, "acc16" },
3341 { OPERAND_TYPE_ACC32
, "acc32" },
3342 { OPERAND_TYPE_ACC64
, "acc64" },
3343 { OPERAND_TYPE_IMM8
, "i8" },
3344 { OPERAND_TYPE_IMM8
, "i8s" },
3345 { OPERAND_TYPE_IMM16
, "i16" },
3346 { OPERAND_TYPE_IMM32
, "i32" },
3347 { OPERAND_TYPE_IMM32S
, "i32s" },
3348 { OPERAND_TYPE_IMM64
, "i64" },
3349 { OPERAND_TYPE_IMM1
, "i1" },
3350 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3351 { OPERAND_TYPE_DISP8
, "d8" },
3352 { OPERAND_TYPE_DISP16
, "d16" },
3353 { OPERAND_TYPE_DISP32
, "d32" },
3354 { OPERAND_TYPE_DISP32S
, "d32s" },
3355 { OPERAND_TYPE_DISP64
, "d64" },
3356 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3357 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3358 { OPERAND_TYPE_CONTROL
, "control reg" },
3359 { OPERAND_TYPE_TEST
, "test reg" },
3360 { OPERAND_TYPE_DEBUG
, "debug reg" },
3361 { OPERAND_TYPE_FLOATREG
, "FReg" },
3362 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3363 { OPERAND_TYPE_SREG
, "SReg" },
3364 { OPERAND_TYPE_REGMMX
, "rMMX" },
3365 { OPERAND_TYPE_REGXMM
, "rXMM" },
3366 { OPERAND_TYPE_REGYMM
, "rYMM" },
3367 { OPERAND_TYPE_REGZMM
, "rZMM" },
3368 { OPERAND_TYPE_REGTMM
, "rTMM" },
3369 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3373 pt (i386_operand_type t
)
3376 i386_operand_type a
;
3378 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3380 a
= operand_type_and (t
, type_names
[j
].mask
);
3381 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3382 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3387 #endif /* DEBUG386 */
3389 static bfd_reloc_code_real_type
3390 reloc (unsigned int size
,
3393 bfd_reloc_code_real_type other
)
3395 if (other
!= NO_RELOC
)
3397 reloc_howto_type
*rel
;
3402 case BFD_RELOC_X86_64_GOT32
:
3403 return BFD_RELOC_X86_64_GOT64
;
3405 case BFD_RELOC_X86_64_GOTPLT64
:
3406 return BFD_RELOC_X86_64_GOTPLT64
;
3408 case BFD_RELOC_X86_64_PLTOFF64
:
3409 return BFD_RELOC_X86_64_PLTOFF64
;
3411 case BFD_RELOC_X86_64_GOTPC32
:
3412 other
= BFD_RELOC_X86_64_GOTPC64
;
3414 case BFD_RELOC_X86_64_GOTPCREL
:
3415 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3417 case BFD_RELOC_X86_64_TPOFF32
:
3418 other
= BFD_RELOC_X86_64_TPOFF64
;
3420 case BFD_RELOC_X86_64_DTPOFF32
:
3421 other
= BFD_RELOC_X86_64_DTPOFF64
;
3427 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3428 if (other
== BFD_RELOC_SIZE32
)
3431 other
= BFD_RELOC_SIZE64
;
3434 as_bad (_("there are no pc-relative size relocations"));
3440 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3441 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3444 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3446 as_bad (_("unknown relocation (%u)"), other
);
3447 else if (size
!= bfd_get_reloc_size (rel
))
3448 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3449 bfd_get_reloc_size (rel
),
3451 else if (pcrel
&& !rel
->pc_relative
)
3452 as_bad (_("non-pc-relative relocation for pc-relative field"));
3453 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3455 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3457 as_bad (_("relocated field and relocation type differ in signedness"));
3466 as_bad (_("there are no unsigned pc-relative relocations"));
3469 case 1: return BFD_RELOC_8_PCREL
;
3470 case 2: return BFD_RELOC_16_PCREL
;
3471 case 4: return BFD_RELOC_32_PCREL
;
3472 case 8: return BFD_RELOC_64_PCREL
;
3474 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3481 case 4: return BFD_RELOC_X86_64_32S
;
3486 case 1: return BFD_RELOC_8
;
3487 case 2: return BFD_RELOC_16
;
3488 case 4: return BFD_RELOC_32
;
3489 case 8: return BFD_RELOC_64
;
3491 as_bad (_("cannot do %s %u byte relocation"),
3492 sign
> 0 ? "signed" : "unsigned", size
);
3498 /* Here we decide which fixups can be adjusted to make them relative to
3499 the beginning of the section instead of the symbol. Basically we need
3500 to make sure that the dynamic relocations are done correctly, so in
3501 some cases we force the original symbol to be used. */
3504 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3506 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3510 /* Don't adjust pc-relative references to merge sections in 64-bit
3512 if (use_rela_relocations
3513 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3517 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3518 and changed later by validate_fix. */
3519 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3520 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3523 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3524 for size relocations. */
3525 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3526 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3527 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3528 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3529 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3530 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3531 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3532 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3533 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3534 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3535 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3536 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3537 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3538 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3539 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3540 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3541 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3542 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3543 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3544 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3545 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3546 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3547 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3548 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3549 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3550 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3551 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3552 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3553 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3554 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3555 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3562 want_disp32 (const insn_template
*t
)
3564 return flag_code
!= CODE_64BIT
3565 || i
.prefix
[ADDR_PREFIX
]
3566 || (t
->base_opcode
== 0x8d
3567 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
3568 && (!i
.types
[1].bitfield
.qword
3569 || t
->opcode_modifier
.size
== SIZE32
));
3573 intel_float_operand (const char *mnemonic
)
3575 /* Note that the value returned is meaningful only for opcodes with (memory)
3576 operands, hence the code here is free to improperly handle opcodes that
3577 have no operands (for better performance and smaller code). */
3579 if (mnemonic
[0] != 'f')
3580 return 0; /* non-math */
3582 switch (mnemonic
[1])
3584 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3585 the fs segment override prefix not currently handled because no
3586 call path can make opcodes without operands get here */
3588 return 2 /* integer op */;
3590 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3591 return 3; /* fldcw/fldenv */
3594 if (mnemonic
[2] != 'o' /* fnop */)
3595 return 3; /* non-waiting control op */
3598 if (mnemonic
[2] == 's')
3599 return 3; /* frstor/frstpm */
3602 if (mnemonic
[2] == 'a')
3603 return 3; /* fsave */
3604 if (mnemonic
[2] == 't')
3606 switch (mnemonic
[3])
3608 case 'c': /* fstcw */
3609 case 'd': /* fstdw */
3610 case 'e': /* fstenv */
3611 case 's': /* fsts[gw] */
3617 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3618 return 0; /* fxsave/fxrstor are not really math ops */
3626 install_template (const insn_template
*t
)
3632 /* Note that for pseudo prefixes this produces a length of 1. But for them
3633 the length isn't interesting at all. */
3634 for (l
= 1; l
< 4; ++l
)
3635 if (!(t
->base_opcode
>> (8 * l
)))
3638 i
.opcode_length
= l
;
3641 /* Build the VEX prefix. */
3644 build_vex_prefix (const insn_template
*t
)
3646 unsigned int register_specifier
;
3647 unsigned int vector_length
;
3650 /* Check register specifier. */
3651 if (i
.vex
.register_specifier
)
3653 register_specifier
=
3654 ~register_number (i
.vex
.register_specifier
) & 0xf;
3655 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3658 register_specifier
= 0xf;
3660 /* Use 2-byte VEX prefix by swapping destination and source operand
3661 if there are more than 1 register operand. */
3662 if (i
.reg_operands
> 1
3663 && i
.vec_encoding
!= vex_encoding_vex3
3664 && i
.dir_encoding
== dir_encoding_default
3665 && i
.operands
== i
.reg_operands
3666 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3667 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3668 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3671 unsigned int xchg
= i
.operands
- 1;
3672 union i386_op temp_op
;
3673 i386_operand_type temp_type
;
3675 temp_type
= i
.types
[xchg
];
3676 i
.types
[xchg
] = i
.types
[0];
3677 i
.types
[0] = temp_type
;
3678 temp_op
= i
.op
[xchg
];
3679 i
.op
[xchg
] = i
.op
[0];
3682 gas_assert (i
.rm
.mode
== 3);
3686 i
.rm
.regmem
= i
.rm
.reg
;
3689 if (i
.tm
.opcode_modifier
.d
)
3690 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3691 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3692 else /* Use the next insn. */
3693 install_template (&t
[1]);
3696 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3697 are no memory operands and at least 3 register ones. */
3698 if (i
.reg_operands
>= 3
3699 && i
.vec_encoding
!= vex_encoding_vex3
3700 && i
.reg_operands
== i
.operands
- i
.imm_operands
3701 && i
.tm
.opcode_modifier
.vex
3702 && i
.tm
.opcode_modifier
.commutative
3703 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3705 && i
.vex
.register_specifier
3706 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3708 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3709 union i386_op temp_op
;
3710 i386_operand_type temp_type
;
3712 gas_assert (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
);
3713 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3714 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3715 &i
.types
[i
.operands
- 3]));
3716 gas_assert (i
.rm
.mode
== 3);
3718 temp_type
= i
.types
[xchg
];
3719 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3720 i
.types
[xchg
+ 1] = temp_type
;
3721 temp_op
= i
.op
[xchg
];
3722 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3723 i
.op
[xchg
+ 1] = temp_op
;
3726 xchg
= i
.rm
.regmem
| 8;
3727 i
.rm
.regmem
= ~register_specifier
& 0xf;
3728 gas_assert (!(i
.rm
.regmem
& 8));
3729 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3730 register_specifier
= ~xchg
& 0xf;
3733 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3734 vector_length
= avxscalar
;
3735 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3741 /* Determine vector length from the last multi-length vector
3744 for (op
= t
->operands
; op
--;)
3745 if (t
->operand_types
[op
].bitfield
.xmmword
3746 && t
->operand_types
[op
].bitfield
.ymmword
3747 && i
.types
[op
].bitfield
.ymmword
)
3754 /* Check the REX.W bit and VEXW. */
3755 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3756 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3757 else if (i
.tm
.opcode_modifier
.vexw
)
3758 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3760 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3762 /* Use 2-byte VEX prefix if possible. */
3764 && i
.vec_encoding
!= vex_encoding_vex3
3765 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3766 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3768 /* 2-byte VEX prefix. */
3772 i
.vex
.bytes
[0] = 0xc5;
3774 /* Check the REX.R bit. */
3775 r
= (i
.rex
& REX_R
) ? 0 : 1;
3776 i
.vex
.bytes
[1] = (r
<< 7
3777 | register_specifier
<< 3
3778 | vector_length
<< 2
3779 | i
.tm
.opcode_modifier
.opcodeprefix
);
3783 /* 3-byte VEX prefix. */
3786 switch (i
.tm
.opcode_modifier
.opcodespace
)
3791 i
.vex
.bytes
[0] = 0xc4;
3796 i
.vex
.bytes
[0] = 0x8f;
3802 /* The high 3 bits of the second VEX byte are 1's compliment
3803 of RXB bits from REX. */
3804 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3806 i
.vex
.bytes
[2] = (w
<< 7
3807 | register_specifier
<< 3
3808 | vector_length
<< 2
3809 | i
.tm
.opcode_modifier
.opcodeprefix
);
3814 is_evex_encoding (const insn_template
*t
)
3816 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3817 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3818 || t
->opcode_modifier
.sae
;
3822 is_any_vex_encoding (const insn_template
*t
)
3824 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3827 /* Build the EVEX prefix. */
3830 build_evex_prefix (void)
3832 unsigned int register_specifier
, w
;
3833 rex_byte vrex_used
= 0;
3835 /* Check register specifier. */
3836 if (i
.vex
.register_specifier
)
3838 gas_assert ((i
.vrex
& REX_X
) == 0);
3840 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3841 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3842 register_specifier
+= 8;
3843 /* The upper 16 registers are encoded in the fourth byte of the
3845 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3846 i
.vex
.bytes
[3] = 0x8;
3847 register_specifier
= ~register_specifier
& 0xf;
3851 register_specifier
= 0xf;
3853 /* Encode upper 16 vector index register in the fourth byte of
3855 if (!(i
.vrex
& REX_X
))
3856 i
.vex
.bytes
[3] = 0x8;
3861 /* 4 byte EVEX prefix. */
3863 i
.vex
.bytes
[0] = 0x62;
3865 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3867 gas_assert (i
.tm
.opcode_modifier
.opcodespace
>= SPACE_0F
);
3868 gas_assert (i
.tm
.opcode_modifier
.opcodespace
<= SPACE_0F3A
);
3869 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3871 /* The fifth bit of the second EVEX byte is 1's compliment of the
3872 REX_R bit in VREX. */
3873 if (!(i
.vrex
& REX_R
))
3874 i
.vex
.bytes
[1] |= 0x10;
3878 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3880 /* When all operands are registers, the REX_X bit in REX is not
3881 used. We reuse it to encode the upper 16 registers, which is
3882 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3883 as 1's compliment. */
3884 if ((i
.vrex
& REX_B
))
3887 i
.vex
.bytes
[1] &= ~0x40;
3891 /* EVEX instructions shouldn't need the REX prefix. */
3892 i
.vrex
&= ~vrex_used
;
3893 gas_assert (i
.vrex
== 0);
3895 /* Check the REX.W bit and VEXW. */
3896 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3897 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3898 else if (i
.tm
.opcode_modifier
.vexw
)
3899 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3901 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3903 /* The third byte of the EVEX prefix. */
3904 i
.vex
.bytes
[2] = ((w
<< 7)
3905 | (register_specifier
<< 3)
3906 | 4 /* Encode the U bit. */
3907 | i
.tm
.opcode_modifier
.opcodeprefix
);
3909 /* The fourth byte of the EVEX prefix. */
3910 /* The zeroing-masking bit. */
3911 if (i
.mask
.reg
&& i
.mask
.zeroing
)
3912 i
.vex
.bytes
[3] |= 0x80;
3914 /* Don't always set the broadcast bit if there is no RC. */
3915 if (i
.rounding
.type
== rc_none
)
3917 /* Encode the vector length. */
3918 unsigned int vec_length
;
3920 if (!i
.tm
.opcode_modifier
.evex
3921 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3925 /* Determine vector length from the last multi-length vector
3927 for (op
= i
.operands
; op
--;)
3928 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3929 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3930 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3932 if (i
.types
[op
].bitfield
.zmmword
)
3934 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3937 else if (i
.types
[op
].bitfield
.ymmword
)
3939 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3942 else if (i
.types
[op
].bitfield
.xmmword
)
3944 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3947 else if (i
.broadcast
.type
&& op
== i
.broadcast
.operand
)
3949 switch (i
.broadcast
.bytes
)
3952 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3955 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3958 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3967 if (op
>= MAX_OPERANDS
)
3971 switch (i
.tm
.opcode_modifier
.evex
)
3973 case EVEXLIG
: /* LL' is ignored */
3974 vec_length
= evexlig
<< 5;
3977 vec_length
= 0 << 5;
3980 vec_length
= 1 << 5;
3983 vec_length
= 2 << 5;
3989 i
.vex
.bytes
[3] |= vec_length
;
3990 /* Encode the broadcast bit. */
3991 if (i
.broadcast
.type
)
3992 i
.vex
.bytes
[3] |= 0x10;
3994 else if (i
.rounding
.type
!= saeonly
)
3995 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
3997 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4000 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4004 process_immext (void)
4008 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4009 which is coded in the same place as an 8-bit immediate field
4010 would be. Here we fake an 8-bit immediate operand from the
4011 opcode suffix stored in tm.extension_opcode.
4013 AVX instructions also use this encoding, for some of
4014 3 argument instructions. */
4016 gas_assert (i
.imm_operands
<= 1
4018 || (is_any_vex_encoding (&i
.tm
)
4019 && i
.operands
<= 4)));
4021 exp
= &im_expressions
[i
.imm_operands
++];
4022 i
.op
[i
.operands
].imms
= exp
;
4023 i
.types
[i
.operands
] = imm8
;
4025 exp
->X_op
= O_constant
;
4026 exp
->X_add_number
= i
.tm
.extension_opcode
;
4027 i
.tm
.extension_opcode
= None
;
4034 switch (i
.tm
.opcode_modifier
.prefixok
)
4042 as_bad (_("invalid instruction `%s' after `%s'"),
4043 i
.tm
.name
, i
.hle_prefix
);
4046 if (i
.prefix
[LOCK_PREFIX
])
4048 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4052 case PrefixHLERelease
:
4053 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4055 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4059 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4061 as_bad (_("memory destination needed for instruction `%s'"
4062 " after `xrelease'"), i
.tm
.name
);
4069 /* Try the shortest encoding by shortening operand size. */
4072 optimize_encoding (void)
4076 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4077 && i
.tm
.base_opcode
== 0x8d)
4080 lea symbol, %rN -> mov $symbol, %rN
4081 lea (%rM), %rN -> mov %rM, %rN
4082 lea (,%rM,1), %rN -> mov %rM, %rN
4084 and in 32-bit mode for 16-bit addressing
4086 lea (%rM), %rN -> movzx %rM, %rN
4088 and in 64-bit mode zap 32-bit addressing in favor of using a
4089 32-bit (or less) destination.
4091 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4093 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4094 i
.tm
.opcode_modifier
.size
= SIZE32
;
4095 i
.prefix
[ADDR_PREFIX
] = 0;
4098 if (!i
.index_reg
&& !i
.base_reg
)
4101 lea symbol, %rN -> mov $symbol, %rN
4103 if (flag_code
== CODE_64BIT
)
4105 /* Don't transform a relocation to a 16-bit one. */
4107 && i
.op
[0].disps
->X_op
!= O_constant
4108 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4111 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4112 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4114 i
.tm
.base_opcode
= 0xb8;
4115 i
.tm
.opcode_modifier
.modrm
= 0;
4116 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4117 i
.types
[0].bitfield
.imm32
= 1;
4120 i
.tm
.opcode_modifier
.size
= SIZE16
;
4121 i
.types
[0].bitfield
.imm16
= 1;
4126 /* Subject to further optimization below. */
4127 i
.tm
.base_opcode
= 0xc7;
4128 i
.tm
.extension_opcode
= 0;
4129 i
.types
[0].bitfield
.imm32s
= 1;
4130 i
.types
[0].bitfield
.baseindex
= 0;
4133 /* Outside of 64-bit mode address and operand sizes have to match if
4134 a relocation is involved, as otherwise we wouldn't (currently) or
4135 even couldn't express the relocation correctly. */
4136 else if (i
.op
[0].disps
4137 && i
.op
[0].disps
->X_op
!= O_constant
4138 && ((!i
.prefix
[ADDR_PREFIX
])
4139 != (flag_code
== CODE_32BIT
4140 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4141 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4145 i
.tm
.base_opcode
= 0xb8;
4146 i
.tm
.opcode_modifier
.modrm
= 0;
4147 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4148 i
.types
[0].bitfield
.imm32
= 1;
4150 i
.types
[0].bitfield
.imm16
= 1;
4153 && i
.op
[0].disps
->X_op
== O_constant
4154 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4155 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4157 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4158 i
.op
[0].disps
->X_add_number
&= 0xffff;
4161 i
.tm
.operand_types
[0] = i
.types
[0];
4165 i
.op
[0].imms
= &im_expressions
[0];
4166 i
.op
[0].imms
->X_op
= O_absent
;
4169 else if (i
.op
[0].disps
4170 && (i
.op
[0].disps
->X_op
!= O_constant
4171 || i
.op
[0].disps
->X_add_number
))
4176 lea (%rM), %rN -> mov %rM, %rN
4177 lea (,%rM,1), %rN -> mov %rM, %rN
4178 lea (%rM), %rN -> movzx %rM, %rN
4180 const reg_entry
*addr_reg
;
4182 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4183 addr_reg
= i
.base_reg
;
4184 else if (!i
.base_reg
4185 && i
.index_reg
->reg_num
!= RegIZ
4186 && !i
.log2_scale_factor
)
4187 addr_reg
= i
.index_reg
;
4191 if (addr_reg
->reg_type
.bitfield
.word
4192 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4194 if (flag_code
!= CODE_32BIT
)
4196 i
.tm
.opcode_modifier
.opcodespace
= SPACE_0F
;
4197 i
.tm
.base_opcode
= 0xb7;
4200 i
.tm
.base_opcode
= 0x8b;
4202 if (addr_reg
->reg_type
.bitfield
.dword
4203 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4204 i
.tm
.opcode_modifier
.size
= SIZE32
;
4206 i
.op
[0].regs
= addr_reg
;
4211 i
.disp_operands
= 0;
4212 i
.prefix
[ADDR_PREFIX
] = 0;
4213 i
.prefix
[SEG_PREFIX
] = 0;
4217 if (optimize_for_space
4218 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4219 && i
.reg_operands
== 1
4220 && i
.imm_operands
== 1
4221 && !i
.types
[1].bitfield
.byte
4222 && i
.op
[0].imms
->X_op
== O_constant
4223 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4224 && (i
.tm
.base_opcode
== 0xa8
4225 || (i
.tm
.base_opcode
== 0xf6
4226 && i
.tm
.extension_opcode
== 0x0)))
4229 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4231 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4232 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4234 i
.types
[1].bitfield
.byte
= 1;
4235 /* Ignore the suffix. */
4237 /* Convert to byte registers. */
4238 if (i
.types
[1].bitfield
.word
)
4240 else if (i
.types
[1].bitfield
.dword
)
4244 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4249 else if (flag_code
== CODE_64BIT
4250 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4251 && ((i
.types
[1].bitfield
.qword
4252 && i
.reg_operands
== 1
4253 && i
.imm_operands
== 1
4254 && i
.op
[0].imms
->X_op
== O_constant
4255 && ((i
.tm
.base_opcode
== 0xb8
4256 && i
.tm
.extension_opcode
== None
4257 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4258 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4259 && ((i
.tm
.base_opcode
== 0x24
4260 || i
.tm
.base_opcode
== 0xa8)
4261 || (i
.tm
.base_opcode
== 0x80
4262 && i
.tm
.extension_opcode
== 0x4)
4263 || ((i
.tm
.base_opcode
== 0xf6
4264 || (i
.tm
.base_opcode
| 1) == 0xc7)
4265 && i
.tm
.extension_opcode
== 0x0)))
4266 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4267 && i
.tm
.base_opcode
== 0x83
4268 && i
.tm
.extension_opcode
== 0x4)))
4269 || (i
.types
[0].bitfield
.qword
4270 && ((i
.reg_operands
== 2
4271 && i
.op
[0].regs
== i
.op
[1].regs
4272 && (i
.tm
.base_opcode
== 0x30
4273 || i
.tm
.base_opcode
== 0x28))
4274 || (i
.reg_operands
== 1
4276 && i
.tm
.base_opcode
== 0x30)))))
4279 andq $imm31, %r64 -> andl $imm31, %r32
4280 andq $imm7, %r64 -> andl $imm7, %r32
4281 testq $imm31, %r64 -> testl $imm31, %r32
4282 xorq %r64, %r64 -> xorl %r32, %r32
4283 subq %r64, %r64 -> subl %r32, %r32
4284 movq $imm31, %r64 -> movl $imm31, %r32
4285 movq $imm32, %r64 -> movl $imm32, %r32
4287 i
.tm
.opcode_modifier
.norex64
= 1;
4288 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4291 movq $imm31, %r64 -> movl $imm31, %r32
4292 movq $imm32, %r64 -> movl $imm32, %r32
4294 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4295 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4296 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4297 i
.types
[0].bitfield
.imm32
= 1;
4298 i
.types
[0].bitfield
.imm32s
= 0;
4299 i
.types
[0].bitfield
.imm64
= 0;
4300 i
.types
[1].bitfield
.dword
= 1;
4301 i
.types
[1].bitfield
.qword
= 0;
4302 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4305 movq $imm31, %r64 -> movl $imm31, %r32
4307 i
.tm
.base_opcode
= 0xb8;
4308 i
.tm
.extension_opcode
= None
;
4309 i
.tm
.opcode_modifier
.w
= 0;
4310 i
.tm
.opcode_modifier
.modrm
= 0;
4314 else if (optimize
> 1
4315 && !optimize_for_space
4316 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4317 && i
.reg_operands
== 2
4318 && i
.op
[0].regs
== i
.op
[1].regs
4319 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4320 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4321 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4324 andb %rN, %rN -> testb %rN, %rN
4325 andw %rN, %rN -> testw %rN, %rN
4326 andq %rN, %rN -> testq %rN, %rN
4327 orb %rN, %rN -> testb %rN, %rN
4328 orw %rN, %rN -> testw %rN, %rN
4329 orq %rN, %rN -> testq %rN, %rN
4331 and outside of 64-bit mode
4333 andl %rN, %rN -> testl %rN, %rN
4334 orl %rN, %rN -> testl %rN, %rN
4336 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4338 else if (i
.reg_operands
== 3
4339 && i
.op
[0].regs
== i
.op
[1].regs
4340 && !i
.types
[2].bitfield
.xmmword
4341 && (i
.tm
.opcode_modifier
.vex
4342 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4343 && i
.rounding
.type
== rc_none
4344 && is_evex_encoding (&i
.tm
)
4345 && (i
.vec_encoding
!= vex_encoding_evex
4346 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4347 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4348 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4349 && i
.types
[2].bitfield
.ymmword
))))
4350 && ((i
.tm
.base_opcode
== 0x55
4351 || i
.tm
.base_opcode
== 0x57
4352 || i
.tm
.base_opcode
== 0xdf
4353 || i
.tm
.base_opcode
== 0xef
4354 || i
.tm
.base_opcode
== 0xf8
4355 || i
.tm
.base_opcode
== 0xf9
4356 || i
.tm
.base_opcode
== 0xfa
4357 || i
.tm
.base_opcode
== 0xfb
4358 || i
.tm
.base_opcode
== 0x42
4359 || i
.tm
.base_opcode
== 0x47)
4360 && i
.tm
.extension_opcode
== None
))
4363 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4365 EVEX VOP %zmmM, %zmmM, %zmmN
4366 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4367 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4368 EVEX VOP %ymmM, %ymmM, %ymmN
4369 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4370 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4371 VEX VOP %ymmM, %ymmM, %ymmN
4372 -> VEX VOP %xmmM, %xmmM, %xmmN
4373 VOP, one of vpandn and vpxor:
4374 VEX VOP %ymmM, %ymmM, %ymmN
4375 -> VEX VOP %xmmM, %xmmM, %xmmN
4376 VOP, one of vpandnd and vpandnq:
4377 EVEX VOP %zmmM, %zmmM, %zmmN
4378 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4379 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4380 EVEX VOP %ymmM, %ymmM, %ymmN
4381 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4382 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4383 VOP, one of vpxord and vpxorq:
4384 EVEX VOP %zmmM, %zmmM, %zmmN
4385 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4386 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4387 EVEX VOP %ymmM, %ymmM, %ymmN
4388 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4389 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4390 VOP, one of kxord and kxorq:
4391 VEX VOP %kM, %kM, %kN
4392 -> VEX kxorw %kM, %kM, %kN
4393 VOP, one of kandnd and kandnq:
4394 VEX VOP %kM, %kM, %kN
4395 -> VEX kandnw %kM, %kM, %kN
4397 if (is_evex_encoding (&i
.tm
))
4399 if (i
.vec_encoding
!= vex_encoding_evex
)
4401 i
.tm
.opcode_modifier
.vex
= VEX128
;
4402 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4403 i
.tm
.opcode_modifier
.evex
= 0;
4405 else if (optimize
> 1)
4406 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4410 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4412 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4413 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4416 i
.tm
.opcode_modifier
.vex
= VEX128
;
4418 if (i
.tm
.opcode_modifier
.vex
)
4419 for (j
= 0; j
< 3; j
++)
4421 i
.types
[j
].bitfield
.xmmword
= 1;
4422 i
.types
[j
].bitfield
.ymmword
= 0;
4425 else if (i
.vec_encoding
!= vex_encoding_evex
4426 && !i
.types
[0].bitfield
.zmmword
4427 && !i
.types
[1].bitfield
.zmmword
4429 && !i
.broadcast
.type
4430 && is_evex_encoding (&i
.tm
)
4431 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4432 || (i
.tm
.base_opcode
& ~4) == 0xdb
4433 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4434 && i
.tm
.extension_opcode
== None
)
4437 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4438 vmovdqu32 and vmovdqu64:
4439 EVEX VOP %xmmM, %xmmN
4440 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4441 EVEX VOP %ymmM, %ymmN
4442 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4444 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4446 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4448 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4450 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4451 VOP, one of vpand, vpandn, vpor, vpxor:
4452 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4453 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4454 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4455 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4456 EVEX VOP{d,q} mem, %xmmM, %xmmN
4457 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4458 EVEX VOP{d,q} mem, %ymmM, %ymmN
4459 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4461 for (j
= 0; j
< i
.operands
; j
++)
4462 if (operand_type_check (i
.types
[j
], disp
)
4463 && i
.op
[j
].disps
->X_op
== O_constant
)
4465 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4466 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4467 bytes, we choose EVEX Disp8 over VEX Disp32. */
4468 int evex_disp8
, vex_disp8
;
4469 unsigned int memshift
= i
.memshift
;
4470 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4472 evex_disp8
= fits_in_disp8 (n
);
4474 vex_disp8
= fits_in_disp8 (n
);
4475 if (evex_disp8
!= vex_disp8
)
4477 i
.memshift
= memshift
;
4481 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4484 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4485 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4486 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4487 i
.tm
.opcode_modifier
.vex
4488 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4489 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4490 /* VPAND, VPOR, and VPXOR are commutative. */
4491 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4492 i
.tm
.opcode_modifier
.commutative
= 1;
4493 i
.tm
.opcode_modifier
.evex
= 0;
4494 i
.tm
.opcode_modifier
.masking
= 0;
4495 i
.tm
.opcode_modifier
.broadcast
= 0;
4496 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4499 i
.types
[j
].bitfield
.disp8
4500 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4504 /* Return non-zero for load instruction. */
4510 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4511 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4515 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4516 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4517 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4518 if (i
.tm
.opcode_modifier
.anysize
)
4522 if (strcmp (i
.tm
.name
, "pop") == 0)
4526 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
4529 if (i
.tm
.base_opcode
== 0x9d
4530 || i
.tm
.base_opcode
== 0x61)
4533 /* movs, cmps, lods, scas. */
4534 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4538 if (base_opcode
== 0x6f
4539 || i
.tm
.base_opcode
== 0xd7)
4541 /* NB: For AMD-specific insns with implicit memory operands,
4542 they're intentionally not covered. */
4545 /* No memory operand. */
4546 if (!i
.mem_operands
)
4552 if (i
.tm
.base_opcode
== 0xae
4553 && i
.tm
.opcode_modifier
.vex
4554 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4555 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4556 && i
.tm
.extension_opcode
== 2)
4559 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
4561 /* test, not, neg, mul, imul, div, idiv. */
4562 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4563 && i
.tm
.extension_opcode
!= 1)
4567 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4570 /* add, or, adc, sbb, and, sub, xor, cmp. */
4571 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4574 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4575 if ((base_opcode
== 0xc1
4576 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4577 && i
.tm
.extension_opcode
!= 6)
4580 /* Check for x87 instructions. */
4581 if (base_opcode
>= 0xd8 && base_opcode
<= 0xdf)
4583 /* Skip fst, fstp, fstenv, fstcw. */
4584 if (i
.tm
.base_opcode
== 0xd9
4585 && (i
.tm
.extension_opcode
== 2
4586 || i
.tm
.extension_opcode
== 3
4587 || i
.tm
.extension_opcode
== 6
4588 || i
.tm
.extension_opcode
== 7))
4591 /* Skip fisttp, fist, fistp, fstp. */
4592 if (i
.tm
.base_opcode
== 0xdb
4593 && (i
.tm
.extension_opcode
== 1
4594 || i
.tm
.extension_opcode
== 2
4595 || i
.tm
.extension_opcode
== 3
4596 || i
.tm
.extension_opcode
== 7))
4599 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4600 if (i
.tm
.base_opcode
== 0xdd
4601 && (i
.tm
.extension_opcode
== 1
4602 || i
.tm
.extension_opcode
== 2
4603 || i
.tm
.extension_opcode
== 3
4604 || i
.tm
.extension_opcode
== 6
4605 || i
.tm
.extension_opcode
== 7))
4608 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4609 if (i
.tm
.base_opcode
== 0xdf
4610 && (i
.tm
.extension_opcode
== 1
4611 || i
.tm
.extension_opcode
== 2
4612 || i
.tm
.extension_opcode
== 3
4613 || i
.tm
.extension_opcode
== 6
4614 || i
.tm
.extension_opcode
== 7))
4620 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
)
4622 /* bt, bts, btr, btc. */
4623 if (i
.tm
.base_opcode
== 0xba
4624 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4627 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4628 if (i
.tm
.base_opcode
== 0xc7
4629 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4630 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4631 || i
.tm
.extension_opcode
== 6))
4634 /* fxrstor, ldmxcsr, xrstor. */
4635 if (i
.tm
.base_opcode
== 0xae
4636 && (i
.tm
.extension_opcode
== 1
4637 || i
.tm
.extension_opcode
== 2
4638 || i
.tm
.extension_opcode
== 5))
4641 /* lgdt, lidt, lmsw. */
4642 if (i
.tm
.base_opcode
== 0x01
4643 && (i
.tm
.extension_opcode
== 2
4644 || i
.tm
.extension_opcode
== 3
4645 || i
.tm
.extension_opcode
== 6))
4649 dest
= i
.operands
- 1;
4651 /* Check fake imm8 operand and 3 source operands. */
4652 if ((i
.tm
.opcode_modifier
.immext
4653 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4654 && i
.types
[dest
].bitfield
.imm8
)
4657 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4658 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
4659 && (base_opcode
== 0x1
4660 || base_opcode
== 0x9
4661 || base_opcode
== 0x11
4662 || base_opcode
== 0x19
4663 || base_opcode
== 0x21
4664 || base_opcode
== 0x29
4665 || base_opcode
== 0x31
4666 || base_opcode
== 0x39
4667 || (base_opcode
| 2) == 0x87))
4671 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4672 && base_opcode
== 0xc1)
4675 /* Check for load instruction. */
4676 return (i
.types
[dest
].bitfield
.class != ClassNone
4677 || i
.types
[dest
].bitfield
.instance
== Accum
);
4680 /* Output lfence, 0xfaee8, after instruction. */
4683 insert_lfence_after (void)
4685 if (lfence_after_load
&& load_insn_p ())
4687 /* There are also two REP string instructions that require
4688 special treatment. Specifically, the compare string (CMPS)
4689 and scan string (SCAS) instructions set EFLAGS in a manner
4690 that depends on the data being compared/scanned. When used
4691 with a REP prefix, the number of iterations may therefore
4692 vary depending on this data. If the data is a program secret
4693 chosen by the adversary using an LVI method,
4694 then this data-dependent behavior may leak some aspect
4696 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4697 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4698 && i
.prefix
[REP_PREFIX
])
4700 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4703 char *p
= frag_more (3);
4710 /* Output lfence, 0xfaee8, before instruction. */
4713 insert_lfence_before (void)
4717 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
4720 if (i
.tm
.base_opcode
== 0xff
4721 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4723 /* Insert lfence before indirect branch if needed. */
4725 if (lfence_before_indirect_branch
== lfence_branch_none
)
4728 if (i
.operands
!= 1)
4731 if (i
.reg_operands
== 1)
4733 /* Indirect branch via register. Don't insert lfence with
4734 -mlfence-after-load=yes. */
4735 if (lfence_after_load
4736 || lfence_before_indirect_branch
== lfence_branch_memory
)
4739 else if (i
.mem_operands
== 1
4740 && lfence_before_indirect_branch
!= lfence_branch_register
)
4742 as_warn (_("indirect `%s` with memory operand should be avoided"),
4749 if (last_insn
.kind
!= last_insn_other
4750 && last_insn
.seg
== now_seg
)
4752 as_warn_where (last_insn
.file
, last_insn
.line
,
4753 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4754 last_insn
.name
, i
.tm
.name
);
4765 /* Output or/not/shl and lfence before near ret. */
4766 if (lfence_before_ret
!= lfence_before_ret_none
4767 && (i
.tm
.base_opcode
== 0xc2
4768 || i
.tm
.base_opcode
== 0xc3))
4770 if (last_insn
.kind
!= last_insn_other
4771 && last_insn
.seg
== now_seg
)
4773 as_warn_where (last_insn
.file
, last_insn
.line
,
4774 _("`%s` skips -mlfence-before-ret on `%s`"),
4775 last_insn
.name
, i
.tm
.name
);
4779 /* Near ret ingore operand size override under CPU64. */
4780 char prefix
= flag_code
== CODE_64BIT
4782 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4784 if (lfence_before_ret
== lfence_before_ret_not
)
4786 /* not: 0xf71424, may add prefix
4787 for operand size override or 64-bit code. */
4788 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4802 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4805 if (lfence_before_ret
== lfence_before_ret_or
)
4807 /* or: 0x830c2400, may add prefix
4808 for operand size override or 64-bit code. */
4814 /* shl: 0xc1242400, may add prefix
4815 for operand size override or 64-bit code. */
4830 /* This is the guts of the machine-dependent assembler. LINE points to a
4831 machine dependent instruction. This function is supposed to emit
4832 the frags/bytes it assembles to. */
4835 md_assemble (char *line
)
4838 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4839 const insn_template
*t
;
4841 /* Initialize globals. */
4842 memset (&i
, '\0', sizeof (i
));
4843 i
.rounding
.type
= rc_none
;
4844 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4845 i
.reloc
[j
] = NO_RELOC
;
4846 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4847 memset (im_expressions
, '\0', sizeof (im_expressions
));
4848 save_stack_p
= save_stack
;
4850 /* First parse an instruction mnemonic & call i386_operand for the operands.
4851 We assume that the scrubber has arranged it so that line[0] is the valid
4852 start of a (possibly prefixed) mnemonic. */
4854 line
= parse_insn (line
, mnemonic
);
4857 mnem_suffix
= i
.suffix
;
4859 line
= parse_operands (line
, mnemonic
);
4861 xfree (i
.memop1_string
);
4862 i
.memop1_string
= NULL
;
4866 /* Now we've parsed the mnemonic into a set of templates, and have the
4867 operands at hand. */
4869 /* All Intel opcodes have reversed operands except for "bound", "enter",
4870 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
4871 "rmpadjust", and "rmpupdate". We also don't reverse intersegment "jmp"
4872 and "call" instructions with 2 immediate operands so that the immediate
4873 segment precedes the offset consistently in Intel and AT&T modes. */
4876 && (strcmp (mnemonic
, "bound") != 0)
4877 && (strncmp (mnemonic
, "invlpg", 6) != 0)
4878 && !startswith (mnemonic
, "monitor")
4879 && !startswith (mnemonic
, "mwait")
4880 && (strcmp (mnemonic
, "pvalidate") != 0)
4881 && !startswith (mnemonic
, "rmp")
4882 && (strcmp (mnemonic
, "tpause") != 0)
4883 && (strcmp (mnemonic
, "umwait") != 0)
4884 && !(operand_type_check (i
.types
[0], imm
)
4885 && operand_type_check (i
.types
[1], imm
)))
4888 /* The order of the immediates should be reversed
4889 for 2 immediates extrq and insertq instructions */
4890 if (i
.imm_operands
== 2
4891 && (strcmp (mnemonic
, "extrq") == 0
4892 || strcmp (mnemonic
, "insertq") == 0))
4893 swap_2_operands (0, 1);
4898 if (i
.disp_operands
&& !want_disp32 (current_templates
->start
))
4900 for (j
= 0; j
< i
.operands
; ++j
)
4902 const expressionS
*exp
= i
.op
[j
].disps
;
4904 if (!operand_type_check (i
.types
[j
], disp
))
4907 if (exp
->X_op
!= O_constant
)
4910 /* Since displacement is signed extended to 64bit, don't allow
4911 disp32 and turn off disp32s if they are out of range. */
4912 i
.types
[j
].bitfield
.disp32
= 0;
4913 if (fits_in_signed_long (exp
->X_add_number
))
4916 i
.types
[j
].bitfield
.disp32s
= 0;
4917 if (i
.types
[j
].bitfield
.baseindex
)
4919 as_bad (_("0x%" BFD_VMA_FMT
"x out of range of signed 32bit displacement"),
4926 /* Don't optimize displacement for movabs since it only takes 64bit
4929 && i
.disp_encoding
!= disp_encoding_32bit
4930 && (flag_code
!= CODE_64BIT
4931 || strcmp (mnemonic
, "movabs") != 0))
4934 /* Next, we find a template that matches the given insn,
4935 making sure the overlap of the given operands types is consistent
4936 with the template operand types. */
4938 if (!(t
= match_template (mnem_suffix
)))
4941 if (sse_check
!= check_none
4942 && !i
.tm
.opcode_modifier
.noavx
4943 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4944 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4945 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4946 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4947 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4948 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4949 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4950 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4951 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4952 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4953 || i
.tm
.cpu_flags
.bitfield
.cpusha
4954 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4956 (sse_check
== check_warning
4958 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4961 if (i
.tm
.opcode_modifier
.fwait
)
4962 if (!add_prefix (FWAIT_OPCODE
))
4965 /* Check if REP prefix is OK. */
4966 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
4968 as_bad (_("invalid instruction `%s' after `%s'"),
4969 i
.tm
.name
, i
.rep_prefix
);
4973 /* Check for lock without a lockable instruction. Destination operand
4974 must be memory unless it is xchg (0x86). */
4975 if (i
.prefix
[LOCK_PREFIX
]
4976 && (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
4977 || i
.mem_operands
== 0
4978 || (i
.tm
.base_opcode
!= 0x86
4979 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4981 as_bad (_("expecting lockable instruction after `lock'"));
4985 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4986 if (i
.prefix
[DATA_PREFIX
]
4987 && (is_any_vex_encoding (&i
.tm
)
4988 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4989 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4991 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4995 /* Check if HLE prefix is OK. */
4996 if (i
.hle_prefix
&& !check_hle ())
4999 /* Check BND prefix. */
5000 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5001 as_bad (_("expecting valid branch instruction after `bnd'"));
5003 /* Check NOTRACK prefix. */
5004 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5005 as_bad (_("expecting indirect branch instruction after `notrack'"));
5007 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
5009 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5010 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5011 else if (flag_code
!= CODE_16BIT
5012 ? i
.prefix
[ADDR_PREFIX
]
5013 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5014 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5017 /* Insert BND prefix. */
5018 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5020 if (!i
.prefix
[BND_PREFIX
])
5021 add_prefix (BND_PREFIX_OPCODE
);
5022 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5024 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5025 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5029 /* Check string instruction segment overrides. */
5030 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5032 gas_assert (i
.mem_operands
);
5033 if (!check_string ())
5035 i
.disp_operands
= 0;
5038 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5039 optimize_encoding ();
5041 if (!process_suffix ())
5044 /* Update operand types and check extended states. */
5045 for (j
= 0; j
< i
.operands
; j
++)
5047 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5048 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5053 i
.xstate
|= xstate_mmx
;
5056 i
.xstate
|= xstate_mask
;
5059 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5060 i
.xstate
|= xstate_tmm
;
5061 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
5062 i
.xstate
|= xstate_zmm
;
5063 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
5064 i
.xstate
|= xstate_ymm
;
5065 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5066 i
.xstate
|= xstate_xmm
;
5071 /* Make still unresolved immediate matches conform to size of immediate
5072 given in i.suffix. */
5073 if (!finalize_imm ())
5076 if (i
.types
[0].bitfield
.imm1
)
5077 i
.imm_operands
= 0; /* kludge for shift insns. */
5079 /* We only need to check those implicit registers for instructions
5080 with 3 operands or less. */
5081 if (i
.operands
<= 3)
5082 for (j
= 0; j
< i
.operands
; j
++)
5083 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
5084 && !i
.types
[j
].bitfield
.xmmword
)
5087 /* For insns with operands there are more diddles to do to the opcode. */
5090 if (!process_operands ())
5093 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5095 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5096 as_warn (_("translating to `%sp'"), i
.tm
.name
);
5099 if (is_any_vex_encoding (&i
.tm
))
5101 if (!cpu_arch_flags
.bitfield
.cpui286
)
5103 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5108 /* Check for explicit REX prefix. */
5109 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5111 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
5115 if (i
.tm
.opcode_modifier
.vex
)
5116 build_vex_prefix (t
);
5118 build_evex_prefix ();
5120 /* The individual REX.RXBW bits got consumed. */
5121 i
.rex
&= REX_OPCODE
;
5124 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
5125 instructions may define INT_OPCODE as well, so avoid this corner
5126 case for those instructions that use MODRM. */
5127 if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
5128 && i
.tm
.base_opcode
== INT_OPCODE
5129 && !i
.tm
.opcode_modifier
.modrm
5130 && i
.op
[0].imms
->X_add_number
== 3)
5132 i
.tm
.base_opcode
= INT3_OPCODE
;
5136 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5137 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5138 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5139 && i
.op
[0].disps
->X_op
== O_constant
)
5141 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5142 the absolute address given by the constant. Since ix86 jumps and
5143 calls are pc relative, we need to generate a reloc. */
5144 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5145 i
.op
[0].disps
->X_op
= O_symbol
;
5148 /* For 8 bit registers we need an empty rex prefix. Also if the
5149 instruction already has a prefix, we need to convert old
5150 registers to new ones. */
5152 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5153 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5154 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5155 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5156 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5157 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5162 i
.rex
|= REX_OPCODE
;
5163 for (x
= 0; x
< 2; x
++)
5165 /* Look for 8 bit operand that uses old registers. */
5166 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5167 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5169 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5170 /* In case it is "hi" register, give up. */
5171 if (i
.op
[x
].regs
->reg_num
> 3)
5172 as_bad (_("can't encode register '%s%s' in an "
5173 "instruction requiring REX prefix."),
5174 register_prefix
, i
.op
[x
].regs
->reg_name
);
5176 /* Otherwise it is equivalent to the extended register.
5177 Since the encoding doesn't change this is merely
5178 cosmetic cleanup for debug output. */
5180 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5185 if (i
.rex
== 0 && i
.rex_encoding
)
5187 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5188 that uses legacy register. If it is "hi" register, don't add
5189 the REX_OPCODE byte. */
5191 for (x
= 0; x
< 2; x
++)
5192 if (i
.types
[x
].bitfield
.class == Reg
5193 && i
.types
[x
].bitfield
.byte
5194 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5195 && i
.op
[x
].regs
->reg_num
> 3)
5197 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5198 i
.rex_encoding
= false;
5207 add_prefix (REX_OPCODE
| i
.rex
);
5209 insert_lfence_before ();
5211 /* We are ready to output the insn. */
5214 insert_lfence_after ();
5216 last_insn
.seg
= now_seg
;
5218 if (i
.tm
.opcode_modifier
.isprefix
)
5220 last_insn
.kind
= last_insn_prefix
;
5221 last_insn
.name
= i
.tm
.name
;
5222 last_insn
.file
= as_where (&last_insn
.line
);
5225 last_insn
.kind
= last_insn_other
;
5229 parse_insn (char *line
, char *mnemonic
)
5232 char *token_start
= l
;
5235 const insn_template
*t
;
5241 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5246 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5248 as_bad (_("no such instruction: `%s'"), token_start
);
5253 if (!is_space_char (*l
)
5254 && *l
!= END_OF_INSN
5256 || (*l
!= PREFIX_SEPARATOR
5259 as_bad (_("invalid character %s in mnemonic"),
5260 output_invalid (*l
));
5263 if (token_start
== l
)
5265 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5266 as_bad (_("expecting prefix; got nothing"));
5268 as_bad (_("expecting mnemonic; got nothing"));
5272 /* Look up instruction (or prefix) via hash table. */
5273 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5275 if (*l
!= END_OF_INSN
5276 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5277 && current_templates
5278 && current_templates
->start
->opcode_modifier
.isprefix
)
5280 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5282 as_bad ((flag_code
!= CODE_64BIT
5283 ? _("`%s' is only supported in 64-bit mode")
5284 : _("`%s' is not supported in 64-bit mode")),
5285 current_templates
->start
->name
);
5288 /* If we are in 16-bit mode, do not allow addr16 or data16.
5289 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5290 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5291 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5292 && flag_code
!= CODE_64BIT
5293 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5294 ^ (flag_code
== CODE_16BIT
)))
5296 as_bad (_("redundant %s prefix"),
5297 current_templates
->start
->name
);
5301 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5303 /* Handle pseudo prefixes. */
5304 switch (current_templates
->start
->extension_opcode
)
5308 i
.disp_encoding
= disp_encoding_8bit
;
5312 i
.disp_encoding
= disp_encoding_16bit
;
5316 i
.disp_encoding
= disp_encoding_32bit
;
5320 i
.dir_encoding
= dir_encoding_load
;
5324 i
.dir_encoding
= dir_encoding_store
;
5328 i
.vec_encoding
= vex_encoding_vex
;
5332 i
.vec_encoding
= vex_encoding_vex3
;
5336 i
.vec_encoding
= vex_encoding_evex
;
5340 i
.rex_encoding
= true;
5342 case Prefix_NoOptimize
:
5344 i
.no_optimize
= true;
5352 /* Add prefix, checking for repeated prefixes. */
5353 switch (add_prefix (current_templates
->start
->base_opcode
))
5358 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5359 i
.notrack_prefix
= current_templates
->start
->name
;
5362 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5363 i
.hle_prefix
= current_templates
->start
->name
;
5364 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5365 i
.bnd_prefix
= current_templates
->start
->name
;
5367 i
.rep_prefix
= current_templates
->start
->name
;
5373 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5380 if (!current_templates
)
5382 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5383 Check if we should swap operand or force 32bit displacement in
5385 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5386 i
.dir_encoding
= dir_encoding_swap
;
5387 else if (mnem_p
- 3 == dot_p
5390 i
.disp_encoding
= disp_encoding_8bit
;
5391 else if (mnem_p
- 4 == dot_p
5395 i
.disp_encoding
= disp_encoding_32bit
;
5400 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5403 if (!current_templates
)
5406 if (mnem_p
> mnemonic
)
5408 /* See if we can get a match by trimming off a suffix. */
5411 case WORD_MNEM_SUFFIX
:
5412 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5413 i
.suffix
= SHORT_MNEM_SUFFIX
;
5416 case BYTE_MNEM_SUFFIX
:
5417 case QWORD_MNEM_SUFFIX
:
5418 i
.suffix
= mnem_p
[-1];
5421 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5423 case SHORT_MNEM_SUFFIX
:
5424 case LONG_MNEM_SUFFIX
:
5427 i
.suffix
= mnem_p
[-1];
5430 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5438 if (intel_float_operand (mnemonic
) == 1)
5439 i
.suffix
= SHORT_MNEM_SUFFIX
;
5441 i
.suffix
= LONG_MNEM_SUFFIX
;
5444 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5450 if (!current_templates
)
5452 as_bad (_("no such instruction: `%s'"), token_start
);
5457 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5458 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5460 /* Check for a branch hint. We allow ",pt" and ",pn" for
5461 predict taken and predict not taken respectively.
5462 I'm not sure that branch hints actually do anything on loop
5463 and jcxz insns (JumpByte) for current Pentium4 chips. They
5464 may work in the future and it doesn't hurt to accept them
5466 if (l
[0] == ',' && l
[1] == 'p')
5470 if (!add_prefix (DS_PREFIX_OPCODE
))
5474 else if (l
[2] == 'n')
5476 if (!add_prefix (CS_PREFIX_OPCODE
))
5482 /* Any other comma loses. */
5485 as_bad (_("invalid character %s in mnemonic"),
5486 output_invalid (*l
));
5490 /* Check if instruction is supported on specified architecture. */
5492 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5494 supported
|= cpu_flags_match (t
);
5495 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5497 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5498 as_warn (_("use .code16 to ensure correct addressing mode"));
5504 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5505 as_bad (flag_code
== CODE_64BIT
5506 ? _("`%s' is not supported in 64-bit mode")
5507 : _("`%s' is only supported in 64-bit mode"),
5508 current_templates
->start
->name
);
5510 as_bad (_("`%s' is not supported on `%s%s'"),
5511 current_templates
->start
->name
,
5512 cpu_arch_name
? cpu_arch_name
: default_arch
,
5513 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5519 parse_operands (char *l
, const char *mnemonic
)
5523 /* 1 if operand is pending after ','. */
5524 unsigned int expecting_operand
= 0;
5526 while (*l
!= END_OF_INSN
)
5528 /* Non-zero if operand parens not balanced. */
5529 unsigned int paren_not_balanced
= 0;
5530 /* True if inside double quotes. */
5531 bool in_quotes
= false;
5533 /* Skip optional white space before operand. */
5534 if (is_space_char (*l
))
5536 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5538 as_bad (_("invalid character %s before operand %d"),
5539 output_invalid (*l
),
5543 token_start
= l
; /* After white space. */
5544 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
5546 if (*l
== END_OF_INSN
)
5550 as_bad (_("unbalanced double quotes in operand %d."),
5554 if (paren_not_balanced
)
5556 know (!intel_syntax
);
5557 as_bad (_("unbalanced parenthesis in operand %d."),
5562 break; /* we are done */
5564 else if (*l
== '\\' && l
[1] == '"')
5567 in_quotes
= !in_quotes
;
5568 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
5570 as_bad (_("invalid character %s in operand %d"),
5571 output_invalid (*l
),
5575 if (!intel_syntax
&& !in_quotes
)
5578 ++paren_not_balanced
;
5580 --paren_not_balanced
;
5584 if (l
!= token_start
)
5585 { /* Yes, we've read in another operand. */
5586 unsigned int operand_ok
;
5587 this_operand
= i
.operands
++;
5588 if (i
.operands
> MAX_OPERANDS
)
5590 as_bad (_("spurious operands; (%d operands/instruction max)"),
5594 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5595 /* Now parse operand adding info to 'i' as we go along. */
5596 END_STRING_AND_SAVE (l
);
5598 if (i
.mem_operands
> 1)
5600 as_bad (_("too many memory references for `%s'"),
5607 i386_intel_operand (token_start
,
5608 intel_float_operand (mnemonic
));
5610 operand_ok
= i386_att_operand (token_start
);
5612 RESTORE_END_STRING (l
);
5618 if (expecting_operand
)
5620 expecting_operand_after_comma
:
5621 as_bad (_("expecting operand after ','; got nothing"));
5626 as_bad (_("expecting operand before ','; got nothing"));
5631 /* Now *l must be either ',' or END_OF_INSN. */
5634 if (*++l
== END_OF_INSN
)
5636 /* Just skip it, if it's \n complain. */
5637 goto expecting_operand_after_comma
;
5639 expecting_operand
= 1;
5646 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
5648 union i386_op temp_op
;
5649 i386_operand_type temp_type
;
5650 unsigned int temp_flags
;
5651 enum bfd_reloc_code_real temp_reloc
;
5653 temp_type
= i
.types
[xchg2
];
5654 i
.types
[xchg2
] = i
.types
[xchg1
];
5655 i
.types
[xchg1
] = temp_type
;
5657 temp_flags
= i
.flags
[xchg2
];
5658 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5659 i
.flags
[xchg1
] = temp_flags
;
5661 temp_op
= i
.op
[xchg2
];
5662 i
.op
[xchg2
] = i
.op
[xchg1
];
5663 i
.op
[xchg1
] = temp_op
;
5665 temp_reloc
= i
.reloc
[xchg2
];
5666 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5667 i
.reloc
[xchg1
] = temp_reloc
;
5671 if (i
.mask
.operand
== xchg1
)
5672 i
.mask
.operand
= xchg2
;
5673 else if (i
.mask
.operand
== xchg2
)
5674 i
.mask
.operand
= xchg1
;
5676 if (i
.broadcast
.type
)
5678 if (i
.broadcast
.operand
== xchg1
)
5679 i
.broadcast
.operand
= xchg2
;
5680 else if (i
.broadcast
.operand
== xchg2
)
5681 i
.broadcast
.operand
= xchg1
;
5683 if (i
.rounding
.type
!= rc_none
)
5685 if (i
.rounding
.operand
== xchg1
)
5686 i
.rounding
.operand
= xchg2
;
5687 else if (i
.rounding
.operand
== xchg2
)
5688 i
.rounding
.operand
= xchg1
;
5693 swap_operands (void)
5699 swap_2_operands (1, i
.operands
- 2);
5703 swap_2_operands (0, i
.operands
- 1);
5709 if (i
.mem_operands
== 2)
5711 const reg_entry
*temp_seg
;
5712 temp_seg
= i
.seg
[0];
5713 i
.seg
[0] = i
.seg
[1];
5714 i
.seg
[1] = temp_seg
;
5718 /* Try to ensure constant immediates are represented in the smallest
5723 char guess_suffix
= 0;
5727 guess_suffix
= i
.suffix
;
5728 else if (i
.reg_operands
)
5730 /* Figure out a suffix from the last register operand specified.
5731 We can't do this properly yet, i.e. excluding special register
5732 instances, but the following works for instructions with
5733 immediates. In any case, we can't set i.suffix yet. */
5734 for (op
= i
.operands
; --op
>= 0;)
5735 if (i
.types
[op
].bitfield
.class != Reg
)
5737 else if (i
.types
[op
].bitfield
.byte
)
5739 guess_suffix
= BYTE_MNEM_SUFFIX
;
5742 else if (i
.types
[op
].bitfield
.word
)
5744 guess_suffix
= WORD_MNEM_SUFFIX
;
5747 else if (i
.types
[op
].bitfield
.dword
)
5749 guess_suffix
= LONG_MNEM_SUFFIX
;
5752 else if (i
.types
[op
].bitfield
.qword
)
5754 guess_suffix
= QWORD_MNEM_SUFFIX
;
5758 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5759 guess_suffix
= WORD_MNEM_SUFFIX
;
5761 for (op
= i
.operands
; --op
>= 0;)
5762 if (operand_type_check (i
.types
[op
], imm
))
5764 switch (i
.op
[op
].imms
->X_op
)
5767 /* If a suffix is given, this operand may be shortened. */
5768 switch (guess_suffix
)
5770 case LONG_MNEM_SUFFIX
:
5771 i
.types
[op
].bitfield
.imm32
= 1;
5772 i
.types
[op
].bitfield
.imm64
= 1;
5774 case WORD_MNEM_SUFFIX
:
5775 i
.types
[op
].bitfield
.imm16
= 1;
5776 i
.types
[op
].bitfield
.imm32
= 1;
5777 i
.types
[op
].bitfield
.imm32s
= 1;
5778 i
.types
[op
].bitfield
.imm64
= 1;
5780 case BYTE_MNEM_SUFFIX
:
5781 i
.types
[op
].bitfield
.imm8
= 1;
5782 i
.types
[op
].bitfield
.imm8s
= 1;
5783 i
.types
[op
].bitfield
.imm16
= 1;
5784 i
.types
[op
].bitfield
.imm32
= 1;
5785 i
.types
[op
].bitfield
.imm32s
= 1;
5786 i
.types
[op
].bitfield
.imm64
= 1;
5790 /* If this operand is at most 16 bits, convert it
5791 to a signed 16 bit number before trying to see
5792 whether it will fit in an even smaller size.
5793 This allows a 16-bit operand such as $0xffe0 to
5794 be recognised as within Imm8S range. */
5795 if ((i
.types
[op
].bitfield
.imm16
)
5796 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5798 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5799 ^ 0x8000) - 0x8000);
5802 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5803 if ((i
.types
[op
].bitfield
.imm32
)
5804 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5807 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5808 ^ ((offsetT
) 1 << 31))
5809 - ((offsetT
) 1 << 31));
5813 = operand_type_or (i
.types
[op
],
5814 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5816 /* We must avoid matching of Imm32 templates when 64bit
5817 only immediate is available. */
5818 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5819 i
.types
[op
].bitfield
.imm32
= 0;
5826 /* Symbols and expressions. */
5828 /* Convert symbolic operand to proper sizes for matching, but don't
5829 prevent matching a set of insns that only supports sizes other
5830 than those matching the insn suffix. */
5832 i386_operand_type mask
, allowed
;
5833 const insn_template
*t
= current_templates
->start
;
5835 operand_type_set (&mask
, 0);
5836 allowed
= t
->operand_types
[op
];
5838 while (++t
< current_templates
->end
)
5840 allowed
= operand_type_and (allowed
, anyimm
);
5841 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5843 switch (guess_suffix
)
5845 case QWORD_MNEM_SUFFIX
:
5846 mask
.bitfield
.imm64
= 1;
5847 mask
.bitfield
.imm32s
= 1;
5849 case LONG_MNEM_SUFFIX
:
5850 mask
.bitfield
.imm32
= 1;
5852 case WORD_MNEM_SUFFIX
:
5853 mask
.bitfield
.imm16
= 1;
5855 case BYTE_MNEM_SUFFIX
:
5856 mask
.bitfield
.imm8
= 1;
5861 allowed
= operand_type_and (mask
, allowed
);
5862 if (!operand_type_all_zero (&allowed
))
5863 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5870 /* Try to use the smallest displacement type too. */
5872 optimize_disp (void)
5876 for (op
= i
.operands
; --op
>= 0;)
5877 if (operand_type_check (i
.types
[op
], disp
))
5879 if (i
.op
[op
].disps
->X_op
== O_constant
)
5881 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5883 if (i
.types
[op
].bitfield
.disp16
5884 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5886 /* If this operand is at most 16 bits, convert
5887 to a signed 16 bit number and don't use 64bit
5889 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5890 i
.types
[op
].bitfield
.disp64
= 0;
5892 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5894 i
.types
[op
].bitfield
.disp8
= 0;
5895 i
.types
[op
].bitfield
.disp16
= 0;
5896 i
.types
[op
].bitfield
.disp32
= 0;
5897 i
.types
[op
].bitfield
.disp32s
= 0;
5898 i
.types
[op
].bitfield
.disp64
= 0;
5903 else if (flag_code
== CODE_64BIT
)
5905 if (want_disp32 (current_templates
->start
)
5906 && fits_in_unsigned_long (op_disp
))
5907 i
.types
[op
].bitfield
.disp32
= 1;
5909 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5910 if (i
.types
[op
].bitfield
.disp32
5911 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5913 /* If this operand is at most 32 bits, convert
5914 to a signed 32 bit number and don't use 64bit
5916 op_disp
&= (((offsetT
) 2 << 31) - 1);
5917 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5918 i
.types
[op
].bitfield
.disp64
= 0;
5921 if (fits_in_signed_long (op_disp
))
5923 i
.types
[op
].bitfield
.disp64
= 0;
5924 i
.types
[op
].bitfield
.disp32s
= 1;
5928 if ((i
.types
[op
].bitfield
.disp32
5929 || i
.types
[op
].bitfield
.disp32s
5930 || i
.types
[op
].bitfield
.disp16
)
5931 && fits_in_disp8 (op_disp
))
5932 i
.types
[op
].bitfield
.disp8
= 1;
5934 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5935 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5937 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5938 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5939 i
.types
[op
].bitfield
.disp8
= 0;
5940 i
.types
[op
].bitfield
.disp16
= 0;
5941 i
.types
[op
].bitfield
.disp32
= 0;
5942 i
.types
[op
].bitfield
.disp32s
= 0;
5943 i
.types
[op
].bitfield
.disp64
= 0;
5946 /* We only support 64bit displacement on constants. */
5947 i
.types
[op
].bitfield
.disp64
= 0;
5951 /* Return 1 if there is a match in broadcast bytes between operand
5952 GIVEN and instruction template T. */
5955 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5957 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5958 && i
.types
[given
].bitfield
.byte
)
5959 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5960 && i
.types
[given
].bitfield
.word
)
5961 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5962 && i
.types
[given
].bitfield
.dword
)
5963 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5964 && i
.types
[given
].bitfield
.qword
));
5967 /* Check if operands are valid for the instruction. */
5970 check_VecOperands (const insn_template
*t
)
5975 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5976 any one operand are implicity requiring AVX512VL support if the actual
5977 operand size is YMMword or XMMword. Since this function runs after
5978 template matching, there's no need to check for YMMword/XMMword in
5980 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5981 if (!cpu_flags_all_zero (&cpu
)
5982 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5983 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5985 for (op
= 0; op
< t
->operands
; ++op
)
5987 if (t
->operand_types
[op
].bitfield
.zmmword
5988 && (i
.types
[op
].bitfield
.ymmword
5989 || i
.types
[op
].bitfield
.xmmword
))
5991 i
.error
= unsupported
;
5997 /* Without VSIB byte, we can't have a vector register for index. */
5998 if (!t
->opcode_modifier
.sib
6000 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6001 || i
.index_reg
->reg_type
.bitfield
.ymmword
6002 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6004 i
.error
= unsupported_vector_index_register
;
6008 /* Check if default mask is allowed. */
6009 if (t
->opcode_modifier
.nodefmask
6010 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6012 i
.error
= no_default_mask
;
6016 /* For VSIB byte, we need a vector register for index, and all vector
6017 registers must be distinct. */
6018 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6021 || !((t
->opcode_modifier
.sib
== VECSIB128
6022 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6023 || (t
->opcode_modifier
.sib
== VECSIB256
6024 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6025 || (t
->opcode_modifier
.sib
== VECSIB512
6026 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6028 i
.error
= invalid_vsib_address
;
6032 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6033 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6035 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6036 gas_assert (i
.types
[0].bitfield
.xmmword
6037 || i
.types
[0].bitfield
.ymmword
);
6038 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6039 gas_assert (i
.types
[2].bitfield
.xmmword
6040 || i
.types
[2].bitfield
.ymmword
);
6041 if (operand_check
== check_none
)
6043 if (register_number (i
.op
[0].regs
)
6044 != register_number (i
.index_reg
)
6045 && register_number (i
.op
[2].regs
)
6046 != register_number (i
.index_reg
)
6047 && register_number (i
.op
[0].regs
)
6048 != register_number (i
.op
[2].regs
))
6050 if (operand_check
== check_error
)
6052 i
.error
= invalid_vector_register_set
;
6055 as_warn (_("mask, index, and destination registers should be distinct"));
6057 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6059 if (i
.types
[1].bitfield
.class == RegSIMD
6060 && (i
.types
[1].bitfield
.xmmword
6061 || i
.types
[1].bitfield
.ymmword
6062 || i
.types
[1].bitfield
.zmmword
)
6063 && (register_number (i
.op
[1].regs
)
6064 == register_number (i
.index_reg
)))
6066 if (operand_check
== check_error
)
6068 i
.error
= invalid_vector_register_set
;
6071 if (operand_check
!= check_none
)
6072 as_warn (_("index and destination registers should be distinct"));
6077 /* For AMX instructions with three tmmword operands, all tmmword operand must be
6079 if (t
->operand_types
[0].bitfield
.tmmword
6080 && i
.reg_operands
== 3)
6082 if (register_number (i
.op
[0].regs
)
6083 == register_number (i
.op
[1].regs
)
6084 || register_number (i
.op
[0].regs
)
6085 == register_number (i
.op
[2].regs
)
6086 || register_number (i
.op
[1].regs
)
6087 == register_number (i
.op
[2].regs
))
6089 i
.error
= invalid_tmm_register_set
;
6094 /* Check if broadcast is supported by the instruction and is applied
6095 to the memory operand. */
6096 if (i
.broadcast
.type
)
6098 i386_operand_type type
, overlap
;
6100 /* Check if specified broadcast is supported in this instruction,
6101 and its broadcast bytes match the memory operand. */
6102 op
= i
.broadcast
.operand
;
6103 if (!t
->opcode_modifier
.broadcast
6104 || !(i
.flags
[op
] & Operand_Mem
)
6105 || (!i
.types
[op
].bitfield
.unspecified
6106 && !match_broadcast_size (t
, op
)))
6109 i
.error
= unsupported_broadcast
;
6113 i
.broadcast
.bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
6114 * i
.broadcast
.type
);
6115 operand_type_set (&type
, 0);
6116 switch (i
.broadcast
.bytes
)
6119 type
.bitfield
.word
= 1;
6122 type
.bitfield
.dword
= 1;
6125 type
.bitfield
.qword
= 1;
6128 type
.bitfield
.xmmword
= 1;
6131 type
.bitfield
.ymmword
= 1;
6134 type
.bitfield
.zmmword
= 1;
6140 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6141 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6142 && t
->operand_types
[op
].bitfield
.byte
6143 + t
->operand_types
[op
].bitfield
.word
6144 + t
->operand_types
[op
].bitfield
.dword
6145 + t
->operand_types
[op
].bitfield
.qword
> 1)
6147 overlap
.bitfield
.xmmword
= 0;
6148 overlap
.bitfield
.ymmword
= 0;
6149 overlap
.bitfield
.zmmword
= 0;
6151 if (operand_type_all_zero (&overlap
))
6154 if (t
->opcode_modifier
.checkregsize
)
6158 type
.bitfield
.baseindex
= 1;
6159 for (j
= 0; j
< i
.operands
; ++j
)
6162 && !operand_type_register_match(i
.types
[j
],
6163 t
->operand_types
[j
],
6165 t
->operand_types
[op
]))
6170 /* If broadcast is supported in this instruction, we need to check if
6171 operand of one-element size isn't specified without broadcast. */
6172 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6174 /* Find memory operand. */
6175 for (op
= 0; op
< i
.operands
; op
++)
6176 if (i
.flags
[op
] & Operand_Mem
)
6178 gas_assert (op
< i
.operands
);
6179 /* Check size of the memory operand. */
6180 if (match_broadcast_size (t
, op
))
6182 i
.error
= broadcast_needed
;
6187 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6189 /* Check if requested masking is supported. */
6192 switch (t
->opcode_modifier
.masking
)
6196 case MERGING_MASKING
:
6200 i
.error
= unsupported_masking
;
6204 case DYNAMIC_MASKING
:
6205 /* Memory destinations allow only merging masking. */
6206 if (i
.mask
.zeroing
&& i
.mem_operands
)
6208 /* Find memory operand. */
6209 for (op
= 0; op
< i
.operands
; op
++)
6210 if (i
.flags
[op
] & Operand_Mem
)
6212 gas_assert (op
< i
.operands
);
6213 if (op
== i
.operands
- 1)
6215 i
.error
= unsupported_masking
;
6225 /* Check if masking is applied to dest operand. */
6226 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6228 i
.error
= mask_not_on_destination
;
6233 if (i
.rounding
.type
!= rc_none
)
6235 if (!t
->opcode_modifier
.sae
6236 || (i
.rounding
.type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6238 i
.error
= unsupported_rc_sae
;
6241 /* If the instruction has several immediate operands and one of
6242 them is rounding, the rounding operand should be the last
6243 immediate operand. */
6244 if (i
.imm_operands
> 1
6245 && i
.rounding
.operand
!= i
.imm_operands
- 1)
6247 i
.error
= rc_sae_operand_not_last_imm
;
6252 /* Check the special Imm4 cases; must be the first operand. */
6253 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6255 if (i
.op
[0].imms
->X_op
!= O_constant
6256 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6262 /* Turn off Imm<N> so that update_imm won't complain. */
6263 operand_type_set (&i
.types
[0], 0);
6266 /* Check vector Disp8 operand. */
6267 if (t
->opcode_modifier
.disp8memshift
6268 && i
.disp_encoding
!= disp_encoding_32bit
)
6270 if (i
.broadcast
.type
)
6271 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6272 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6273 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6276 const i386_operand_type
*type
= NULL
;
6279 for (op
= 0; op
< i
.operands
; op
++)
6280 if (i
.flags
[op
] & Operand_Mem
)
6282 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6283 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6284 else if (t
->operand_types
[op
].bitfield
.xmmword
6285 + t
->operand_types
[op
].bitfield
.ymmword
6286 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6287 type
= &t
->operand_types
[op
];
6288 else if (!i
.types
[op
].bitfield
.unspecified
)
6289 type
= &i
.types
[op
];
6291 else if (i
.types
[op
].bitfield
.class == RegSIMD
6292 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6294 if (i
.types
[op
].bitfield
.zmmword
)
6296 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6298 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6304 if (type
->bitfield
.zmmword
)
6306 else if (type
->bitfield
.ymmword
)
6308 else if (type
->bitfield
.xmmword
)
6312 /* For the check in fits_in_disp8(). */
6313 if (i
.memshift
== 0)
6317 for (op
= 0; op
< i
.operands
; op
++)
6318 if (operand_type_check (i
.types
[op
], disp
)
6319 && i
.op
[op
].disps
->X_op
== O_constant
)
6321 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6323 i
.types
[op
].bitfield
.disp8
= 1;
6326 i
.types
[op
].bitfield
.disp8
= 0;
6335 /* Check if encoding requirements are met by the instruction. */
6338 VEX_check_encoding (const insn_template
*t
)
6340 if (i
.vec_encoding
== vex_encoding_error
)
6342 i
.error
= unsupported
;
6346 if (i
.vec_encoding
== vex_encoding_evex
)
6348 /* This instruction must be encoded with EVEX prefix. */
6349 if (!is_evex_encoding (t
))
6351 i
.error
= unsupported
;
6357 if (!t
->opcode_modifier
.vex
)
6359 /* This instruction template doesn't have VEX prefix. */
6360 if (i
.vec_encoding
!= vex_encoding_default
)
6362 i
.error
= unsupported
;
6371 static const insn_template
*
6372 match_template (char mnem_suffix
)
6374 /* Points to template once we've found it. */
6375 const insn_template
*t
;
6376 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6377 i386_operand_type overlap4
;
6378 unsigned int found_reverse_match
;
6379 i386_opcode_modifier suffix_check
;
6380 i386_operand_type operand_types
[MAX_OPERANDS
];
6381 int addr_prefix_disp
;
6382 unsigned int j
, size_match
, check_register
;
6383 enum i386_error specific_error
= 0;
6385 #if MAX_OPERANDS != 5
6386 # error "MAX_OPERANDS must be 5."
6389 found_reverse_match
= 0;
6390 addr_prefix_disp
= -1;
6392 /* Prepare for mnemonic suffix check. */
6393 memset (&suffix_check
, 0, sizeof (suffix_check
));
6394 switch (mnem_suffix
)
6396 case BYTE_MNEM_SUFFIX
:
6397 suffix_check
.no_bsuf
= 1;
6399 case WORD_MNEM_SUFFIX
:
6400 suffix_check
.no_wsuf
= 1;
6402 case SHORT_MNEM_SUFFIX
:
6403 suffix_check
.no_ssuf
= 1;
6405 case LONG_MNEM_SUFFIX
:
6406 suffix_check
.no_lsuf
= 1;
6408 case QWORD_MNEM_SUFFIX
:
6409 suffix_check
.no_qsuf
= 1;
6412 /* NB: In Intel syntax, normally we can check for memory operand
6413 size when there is no mnemonic suffix. But jmp and call have
6414 2 different encodings with Dword memory operand size, one with
6415 No_ldSuf and the other without. i.suffix is set to
6416 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6417 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6418 suffix_check
.no_ldsuf
= 1;
6421 /* Must have right number of operands. */
6422 i
.error
= number_of_operands_mismatch
;
6424 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6426 addr_prefix_disp
= -1;
6427 found_reverse_match
= 0;
6429 if (i
.operands
!= t
->operands
)
6432 /* Check processor support. */
6433 i
.error
= unsupported
;
6434 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6437 /* Check Pseudo Prefix. */
6438 i
.error
= unsupported
;
6439 if (t
->opcode_modifier
.pseudovexprefix
6440 && !(i
.vec_encoding
== vex_encoding_vex
6441 || i
.vec_encoding
== vex_encoding_vex3
))
6444 /* Check AT&T mnemonic. */
6445 i
.error
= unsupported_with_intel_mnemonic
;
6446 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6449 /* Check AT&T/Intel syntax. */
6450 i
.error
= unsupported_syntax
;
6451 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6452 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6455 /* Check Intel64/AMD64 ISA. */
6459 /* Default: Don't accept Intel64. */
6460 if (t
->opcode_modifier
.isa64
== INTEL64
)
6464 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6465 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6469 /* -mintel64: Don't accept AMD64. */
6470 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6475 /* Check the suffix. */
6476 i
.error
= invalid_instruction_suffix
;
6477 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6478 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6479 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6480 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6481 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6482 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6485 size_match
= operand_size_match (t
);
6489 /* This is intentionally not
6491 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6493 as the case of a missing * on the operand is accepted (perhaps with
6494 a warning, issued further down). */
6495 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6497 i
.error
= operand_type_mismatch
;
6501 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6502 operand_types
[j
] = t
->operand_types
[j
];
6504 /* In general, don't allow
6505 - 64-bit operands outside of 64-bit mode,
6506 - 32-bit operands on pre-386. */
6507 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6508 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6509 && flag_code
!= CODE_64BIT
6510 && !(t
->opcode_modifier
.opcodespace
== SPACE_0F
6511 && t
->base_opcode
== 0xc7
6512 && t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
6513 && t
->extension_opcode
== 1) /* cmpxchg8b */)
6514 || (i
.suffix
== LONG_MNEM_SUFFIX
6515 && !cpu_arch_flags
.bitfield
.cpui386
))
6517 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6518 && !intel_float_operand (t
->name
))
6519 : intel_float_operand (t
->name
) != 2)
6520 && (t
->operands
== i
.imm_operands
6521 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6522 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6523 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6524 || (operand_types
[j
].bitfield
.class != RegMMX
6525 && operand_types
[j
].bitfield
.class != RegSIMD
6526 && operand_types
[j
].bitfield
.class != RegMask
))
6527 && !t
->opcode_modifier
.sib
)
6530 /* Do not verify operands when there are none. */
6533 if (VEX_check_encoding (t
))
6535 specific_error
= i
.error
;
6539 /* We've found a match; break out of loop. */
6543 if (!t
->opcode_modifier
.jump
6544 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6546 /* There should be only one Disp operand. */
6547 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6548 if (operand_type_check (operand_types
[j
], disp
))
6550 if (j
< MAX_OPERANDS
)
6552 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6554 addr_prefix_disp
= j
;
6556 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6557 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6561 override
= !override
;
6564 if (operand_types
[j
].bitfield
.disp32
6565 && operand_types
[j
].bitfield
.disp16
)
6567 operand_types
[j
].bitfield
.disp16
= override
;
6568 operand_types
[j
].bitfield
.disp32
= !override
;
6570 operand_types
[j
].bitfield
.disp32s
= 0;
6571 operand_types
[j
].bitfield
.disp64
= 0;
6575 if (operand_types
[j
].bitfield
.disp32s
6576 || operand_types
[j
].bitfield
.disp64
)
6578 operand_types
[j
].bitfield
.disp64
&= !override
;
6579 operand_types
[j
].bitfield
.disp32s
&= !override
;
6580 operand_types
[j
].bitfield
.disp32
= override
;
6582 operand_types
[j
].bitfield
.disp16
= 0;
6588 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6589 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
6590 && t
->base_opcode
== 0xa0
6591 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
)
6594 /* We check register size if needed. */
6595 if (t
->opcode_modifier
.checkregsize
)
6597 check_register
= (1 << t
->operands
) - 1;
6598 if (i
.broadcast
.type
)
6599 check_register
&= ~(1 << i
.broadcast
.operand
);
6604 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6605 switch (t
->operands
)
6608 if (!operand_type_match (overlap0
, i
.types
[0]))
6612 /* xchg %eax, %eax is a special case. It is an alias for nop
6613 only in 32bit mode and we can use opcode 0x90. In 64bit
6614 mode, we can't use 0x90 for xchg %eax, %eax since it should
6615 zero-extend %eax to %rax. */
6616 if (flag_code
== CODE_64BIT
6617 && t
->base_opcode
== 0x90
6618 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6619 && i
.types
[0].bitfield
.instance
== Accum
6620 && i
.types
[0].bitfield
.dword
6621 && i
.types
[1].bitfield
.instance
== Accum
6622 && i
.types
[1].bitfield
.dword
)
6624 /* xrelease mov %eax, <disp> is another special case. It must not
6625 match the accumulator-only encoding of mov. */
6626 if (flag_code
!= CODE_64BIT
6628 && t
->base_opcode
== 0xa0
6629 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6630 && i
.types
[0].bitfield
.instance
== Accum
6631 && (i
.flags
[1] & Operand_Mem
))
6636 if (!(size_match
& MATCH_STRAIGHT
))
6638 /* Reverse direction of operands if swapping is possible in the first
6639 place (operands need to be symmetric) and
6640 - the load form is requested, and the template is a store form,
6641 - the store form is requested, and the template is a load form,
6642 - the non-default (swapped) form is requested. */
6643 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6644 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6645 && !operand_type_all_zero (&overlap1
))
6646 switch (i
.dir_encoding
)
6648 case dir_encoding_load
:
6649 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6650 || t
->opcode_modifier
.regmem
)
6654 case dir_encoding_store
:
6655 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6656 && !t
->opcode_modifier
.regmem
)
6660 case dir_encoding_swap
:
6663 case dir_encoding_default
:
6666 /* If we want store form, we skip the current load. */
6667 if ((i
.dir_encoding
== dir_encoding_store
6668 || i
.dir_encoding
== dir_encoding_swap
)
6669 && i
.mem_operands
== 0
6670 && t
->opcode_modifier
.load
)
6675 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6676 if (!operand_type_match (overlap0
, i
.types
[0])
6677 || !operand_type_match (overlap1
, i
.types
[1])
6678 || ((check_register
& 3) == 3
6679 && !operand_type_register_match (i
.types
[0],
6684 /* Check if other direction is valid ... */
6685 if (!t
->opcode_modifier
.d
)
6689 if (!(size_match
& MATCH_REVERSE
))
6691 /* Try reversing direction of operands. */
6692 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6693 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6694 if (!operand_type_match (overlap0
, i
.types
[0])
6695 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6697 && !operand_type_register_match (i
.types
[0],
6698 operand_types
[i
.operands
- 1],
6699 i
.types
[i
.operands
- 1],
6702 /* Does not match either direction. */
6705 /* found_reverse_match holds which of D or FloatR
6707 if (!t
->opcode_modifier
.d
)
6708 found_reverse_match
= 0;
6709 else if (operand_types
[0].bitfield
.tbyte
)
6710 found_reverse_match
= Opcode_FloatD
;
6711 else if (operand_types
[0].bitfield
.xmmword
6712 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6713 || operand_types
[0].bitfield
.class == RegMMX
6714 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6715 || is_any_vex_encoding(t
))
6716 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6717 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6719 found_reverse_match
= Opcode_D
;
6720 if (t
->opcode_modifier
.floatr
)
6721 found_reverse_match
|= Opcode_FloatR
;
6725 /* Found a forward 2 operand match here. */
6726 switch (t
->operands
)
6729 overlap4
= operand_type_and (i
.types
[4],
6733 overlap3
= operand_type_and (i
.types
[3],
6737 overlap2
= operand_type_and (i
.types
[2],
6742 switch (t
->operands
)
6745 if (!operand_type_match (overlap4
, i
.types
[4])
6746 || !operand_type_register_match (i
.types
[3],
6753 if (!operand_type_match (overlap3
, i
.types
[3])
6754 || ((check_register
& 0xa) == 0xa
6755 && !operand_type_register_match (i
.types
[1],
6759 || ((check_register
& 0xc) == 0xc
6760 && !operand_type_register_match (i
.types
[2],
6767 /* Here we make use of the fact that there are no
6768 reverse match 3 operand instructions. */
6769 if (!operand_type_match (overlap2
, i
.types
[2])
6770 || ((check_register
& 5) == 5
6771 && !operand_type_register_match (i
.types
[0],
6775 || ((check_register
& 6) == 6
6776 && !operand_type_register_match (i
.types
[1],
6784 /* Found either forward/reverse 2, 3 or 4 operand match here:
6785 slip through to break. */
6788 /* Check if vector operands are valid. */
6789 if (check_VecOperands (t
))
6791 specific_error
= i
.error
;
6795 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6796 if (VEX_check_encoding (t
))
6798 specific_error
= i
.error
;
6802 /* We've found a match; break out of loop. */
6806 if (t
== current_templates
->end
)
6808 /* We found no match. */
6809 const char *err_msg
;
6810 switch (specific_error
? specific_error
: i
.error
)
6814 case operand_size_mismatch
:
6815 err_msg
= _("operand size mismatch");
6817 case operand_type_mismatch
:
6818 err_msg
= _("operand type mismatch");
6820 case register_type_mismatch
:
6821 err_msg
= _("register type mismatch");
6823 case number_of_operands_mismatch
:
6824 err_msg
= _("number of operands mismatch");
6826 case invalid_instruction_suffix
:
6827 err_msg
= _("invalid instruction suffix");
6830 err_msg
= _("constant doesn't fit in 4 bits");
6832 case unsupported_with_intel_mnemonic
:
6833 err_msg
= _("unsupported with Intel mnemonic");
6835 case unsupported_syntax
:
6836 err_msg
= _("unsupported syntax");
6839 as_bad (_("unsupported instruction `%s'"),
6840 current_templates
->start
->name
);
6842 case invalid_sib_address
:
6843 err_msg
= _("invalid SIB address");
6845 case invalid_vsib_address
:
6846 err_msg
= _("invalid VSIB address");
6848 case invalid_vector_register_set
:
6849 err_msg
= _("mask, index, and destination registers must be distinct");
6851 case invalid_tmm_register_set
:
6852 err_msg
= _("all tmm registers must be distinct");
6854 case unsupported_vector_index_register
:
6855 err_msg
= _("unsupported vector index register");
6857 case unsupported_broadcast
:
6858 err_msg
= _("unsupported broadcast");
6860 case broadcast_needed
:
6861 err_msg
= _("broadcast is needed for operand of such type");
6863 case unsupported_masking
:
6864 err_msg
= _("unsupported masking");
6866 case mask_not_on_destination
:
6867 err_msg
= _("mask not on destination operand");
6869 case no_default_mask
:
6870 err_msg
= _("default mask isn't allowed");
6872 case unsupported_rc_sae
:
6873 err_msg
= _("unsupported static rounding/sae");
6875 case rc_sae_operand_not_last_imm
:
6877 err_msg
= _("RC/SAE operand must precede immediate operands");
6879 err_msg
= _("RC/SAE operand must follow immediate operands");
6881 case invalid_register_operand
:
6882 err_msg
= _("invalid register operand");
6885 as_bad (_("%s for `%s'"), err_msg
,
6886 current_templates
->start
->name
);
6890 if (!quiet_warnings
)
6893 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6894 as_warn (_("indirect %s without `*'"), t
->name
);
6896 if (t
->opcode_modifier
.isprefix
6897 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6899 /* Warn them that a data or address size prefix doesn't
6900 affect assembly of the next line of code. */
6901 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6905 /* Copy the template we found. */
6906 install_template (t
);
6908 if (addr_prefix_disp
!= -1)
6909 i
.tm
.operand_types
[addr_prefix_disp
]
6910 = operand_types
[addr_prefix_disp
];
6912 if (found_reverse_match
)
6914 /* If we found a reverse match we must alter the opcode direction
6915 bit and clear/flip the regmem modifier one. found_reverse_match
6916 holds bits to change (different for int & float insns). */
6918 i
.tm
.base_opcode
^= found_reverse_match
;
6920 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6921 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6923 /* Certain SIMD insns have their load forms specified in the opcode
6924 table, and hence we need to _set_ RegMem instead of clearing it.
6925 We need to avoid setting the bit though on insns like KMOVW. */
6926 i
.tm
.opcode_modifier
.regmem
6927 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6928 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6929 && !i
.tm
.opcode_modifier
.regmem
;
6938 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6939 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6941 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
6943 as_bad (_("`%s' operand %u must use `%ses' segment"),
6945 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6950 /* There's only ever one segment override allowed per instruction.
6951 This instruction possibly has a legal segment override on the
6952 second operand, so copy the segment to where non-string
6953 instructions store it, allowing common code. */
6954 i
.seg
[op
] = i
.seg
[1];
6960 process_suffix (void)
6962 bool is_crc32
= false, is_movx
= false;
6964 /* If matched instruction specifies an explicit instruction mnemonic
6966 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6967 i
.suffix
= WORD_MNEM_SUFFIX
;
6968 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6969 i
.suffix
= LONG_MNEM_SUFFIX
;
6970 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6971 i
.suffix
= QWORD_MNEM_SUFFIX
;
6972 else if (i
.reg_operands
6973 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6974 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6976 unsigned int numop
= i
.operands
;
6979 is_movx
= (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
6980 && (i
.tm
.base_opcode
| 8) == 0xbe)
6981 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
6982 && i
.tm
.base_opcode
== 0x63
6983 && i
.tm
.cpu_flags
.bitfield
.cpu64
);
6986 is_crc32
= (i
.tm
.base_opcode
== 0xf0
6987 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
6988 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
);
6990 /* movsx/movzx want only their source operand considered here, for the
6991 ambiguity checking below. The suffix will be replaced afterwards
6992 to represent the destination (register). */
6993 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
6996 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6997 if (is_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7000 /* If there's no instruction mnemonic suffix we try to invent one
7001 based on GPR operands. */
7004 /* We take i.suffix from the last register operand specified,
7005 Destination register type is more significant than source
7006 register type. crc32 in SSE4.2 prefers source register
7008 unsigned int op
= is_crc32
? 1 : i
.operands
;
7011 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7012 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7014 if (i
.types
[op
].bitfield
.class != Reg
)
7016 if (i
.types
[op
].bitfield
.byte
)
7017 i
.suffix
= BYTE_MNEM_SUFFIX
;
7018 else if (i
.types
[op
].bitfield
.word
)
7019 i
.suffix
= WORD_MNEM_SUFFIX
;
7020 else if (i
.types
[op
].bitfield
.dword
)
7021 i
.suffix
= LONG_MNEM_SUFFIX
;
7022 else if (i
.types
[op
].bitfield
.qword
)
7023 i
.suffix
= QWORD_MNEM_SUFFIX
;
7029 /* As an exception, movsx/movzx silently default to a byte source
7031 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7032 i
.suffix
= BYTE_MNEM_SUFFIX
;
7034 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7037 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7038 && i
.tm
.opcode_modifier
.no_bsuf
)
7040 else if (!check_byte_reg ())
7043 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7046 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7047 && i
.tm
.opcode_modifier
.no_lsuf
7048 && !i
.tm
.opcode_modifier
.todword
7049 && !i
.tm
.opcode_modifier
.toqword
)
7051 else if (!check_long_reg ())
7054 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7057 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7058 && i
.tm
.opcode_modifier
.no_qsuf
7059 && !i
.tm
.opcode_modifier
.todword
7060 && !i
.tm
.opcode_modifier
.toqword
)
7062 else if (!check_qword_reg ())
7065 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7068 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
7069 && i
.tm
.opcode_modifier
.no_wsuf
)
7071 else if (!check_word_reg ())
7074 else if (intel_syntax
7075 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7076 /* Do nothing if the instruction is going to ignore the prefix. */
7081 /* Undo the movsx/movzx change done above. */
7084 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7087 i
.suffix
= stackop_size
;
7088 if (stackop_size
== LONG_MNEM_SUFFIX
)
7090 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7091 .code16gcc directive to support 16-bit mode with
7092 32-bit address. For IRET without a suffix, generate
7093 16-bit IRET (opcode 0xcf) to return from an interrupt
7095 if (i
.tm
.base_opcode
== 0xcf)
7097 i
.suffix
= WORD_MNEM_SUFFIX
;
7098 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7100 /* Warn about changed behavior for segment register push/pop. */
7101 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7102 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7107 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7108 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7109 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7110 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
7111 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7112 && i
.tm
.extension_opcode
<= 3)))
7117 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7119 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7120 || i
.tm
.opcode_modifier
.no_lsuf
)
7121 i
.suffix
= QWORD_MNEM_SUFFIX
;
7126 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7127 i
.suffix
= LONG_MNEM_SUFFIX
;
7130 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7131 i
.suffix
= WORD_MNEM_SUFFIX
;
7137 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7138 /* Also cover lret/retf/iret in 64-bit mode. */
7139 || (flag_code
== CODE_64BIT
7140 && !i
.tm
.opcode_modifier
.no_lsuf
7141 && !i
.tm
.opcode_modifier
.no_qsuf
))
7142 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7143 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7144 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7145 /* Accept FLDENV et al without suffix. */
7146 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7148 unsigned int suffixes
, evex
= 0;
7150 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7151 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7153 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7155 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
7157 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7159 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7162 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7163 also suitable for AT&T syntax mode, it was requested that this be
7164 restricted to just Intel syntax. */
7165 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
.type
)
7169 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7171 if (is_evex_encoding (&i
.tm
)
7172 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7174 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7175 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7176 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7177 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7178 if (!i
.tm
.opcode_modifier
.evex
7179 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7180 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7183 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7184 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7185 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7188 /* Any properly sized operand disambiguates the insn. */
7189 if (i
.types
[op
].bitfield
.xmmword
7190 || i
.types
[op
].bitfield
.ymmword
7191 || i
.types
[op
].bitfield
.zmmword
)
7193 suffixes
&= ~(7 << 6);
7198 if ((i
.flags
[op
] & Operand_Mem
)
7199 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7201 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7203 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7205 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7207 if (is_evex_encoding (&i
.tm
))
7213 /* Are multiple suffixes / operand sizes allowed? */
7214 if (suffixes
& (suffixes
- 1))
7217 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7218 || operand_check
== check_error
))
7220 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
7223 if (operand_check
== check_error
)
7225 as_bad (_("no instruction mnemonic suffix given and "
7226 "no register operands; can't size `%s'"), i
.tm
.name
);
7229 if (operand_check
== check_warning
)
7230 as_warn (_("%s; using default for `%s'"),
7232 ? _("ambiguous operand size")
7233 : _("no instruction mnemonic suffix given and "
7234 "no register operands"),
7237 if (i
.tm
.opcode_modifier
.floatmf
)
7238 i
.suffix
= SHORT_MNEM_SUFFIX
;
7240 /* handled below */;
7242 i
.tm
.opcode_modifier
.evex
= evex
;
7243 else if (flag_code
== CODE_16BIT
)
7244 i
.suffix
= WORD_MNEM_SUFFIX
;
7245 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7246 i
.suffix
= LONG_MNEM_SUFFIX
;
7248 i
.suffix
= QWORD_MNEM_SUFFIX
;
7254 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7255 In AT&T syntax, if there is no suffix (warned about above), the default
7256 will be byte extension. */
7257 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7258 i
.tm
.base_opcode
|= 1;
7260 /* For further processing, the suffix should represent the destination
7261 (register). This is already the case when one was used with
7262 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7263 no suffix to begin with. */
7264 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7266 if (i
.types
[1].bitfield
.word
)
7267 i
.suffix
= WORD_MNEM_SUFFIX
;
7268 else if (i
.types
[1].bitfield
.qword
)
7269 i
.suffix
= QWORD_MNEM_SUFFIX
;
7271 i
.suffix
= LONG_MNEM_SUFFIX
;
7273 i
.tm
.opcode_modifier
.w
= 0;
7277 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7278 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7279 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7281 /* Change the opcode based on the operand size given by i.suffix. */
7284 /* Size floating point instruction. */
7285 case LONG_MNEM_SUFFIX
:
7286 if (i
.tm
.opcode_modifier
.floatmf
)
7288 i
.tm
.base_opcode
^= 4;
7292 case WORD_MNEM_SUFFIX
:
7293 case QWORD_MNEM_SUFFIX
:
7294 /* It's not a byte, select word/dword operation. */
7295 if (i
.tm
.opcode_modifier
.w
)
7298 i
.tm
.base_opcode
|= 8;
7300 i
.tm
.base_opcode
|= 1;
7303 case SHORT_MNEM_SUFFIX
:
7304 /* Now select between word & dword operations via the operand
7305 size prefix, except for instructions that will ignore this
7307 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7308 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7309 && !i
.tm
.opcode_modifier
.floatmf
7310 && !is_any_vex_encoding (&i
.tm
)
7311 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7312 || (flag_code
== CODE_64BIT
7313 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7315 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7317 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7318 prefix
= ADDR_PREFIX_OPCODE
;
7320 if (!add_prefix (prefix
))
7324 /* Set mode64 for an operand. */
7325 if (i
.suffix
== QWORD_MNEM_SUFFIX
7326 && flag_code
== CODE_64BIT
7327 && !i
.tm
.opcode_modifier
.norex64
7328 && !i
.tm
.opcode_modifier
.vexw
7329 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7331 && ! (i
.operands
== 2
7332 && i
.tm
.base_opcode
== 0x90
7333 && i
.tm
.extension_opcode
== None
7334 && i
.types
[0].bitfield
.instance
== Accum
7335 && i
.types
[0].bitfield
.qword
7336 && i
.types
[1].bitfield
.instance
== Accum
7337 && i
.types
[1].bitfield
.qword
))
7343 /* Select word/dword/qword operation with explicit data sizing prefix
7344 when there are no suitable register operands. */
7345 if (i
.tm
.opcode_modifier
.w
7346 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7348 || (i
.reg_operands
== 1
7350 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7352 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7353 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7356 i
.tm
.base_opcode
|= 1;
7360 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7362 gas_assert (!i
.suffix
);
7363 gas_assert (i
.reg_operands
);
7365 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7368 /* The address size override prefix changes the size of the
7370 if (flag_code
== CODE_64BIT
7371 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7373 as_bad (_("16-bit addressing unavailable for `%s'"),
7378 if ((flag_code
== CODE_32BIT
7379 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7380 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7381 && !add_prefix (ADDR_PREFIX_OPCODE
))
7386 /* Check invalid register operand when the address size override
7387 prefix changes the size of register operands. */
7389 enum { need_word
, need_dword
, need_qword
} need
;
7391 /* Check the register operand for the address size prefix if
7392 the memory operand has no real registers, like symbol, DISP
7393 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7394 if (i
.mem_operands
== 1
7395 && i
.reg_operands
== 1
7397 && i
.types
[1].bitfield
.class == Reg
7398 && (flag_code
== CODE_32BIT
7399 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7400 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7401 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7402 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7403 || (x86_elf_abi
== X86_64_X32_ABI
7405 && i
.base_reg
->reg_num
== RegIP
7406 && i
.base_reg
->reg_type
.bitfield
.qword
))
7410 && !add_prefix (ADDR_PREFIX_OPCODE
))
7413 if (flag_code
== CODE_32BIT
)
7414 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7415 else if (i
.prefix
[ADDR_PREFIX
])
7418 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7420 for (op
= 0; op
< i
.operands
; op
++)
7422 if (i
.types
[op
].bitfield
.class != Reg
)
7428 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7432 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7436 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7441 as_bad (_("invalid register operand size for `%s'"),
7452 check_byte_reg (void)
7456 for (op
= i
.operands
; --op
>= 0;)
7458 /* Skip non-register operands. */
7459 if (i
.types
[op
].bitfield
.class != Reg
)
7462 /* If this is an eight bit register, it's OK. If it's the 16 or
7463 32 bit version of an eight bit register, we will just use the
7464 low portion, and that's OK too. */
7465 if (i
.types
[op
].bitfield
.byte
)
7468 /* I/O port address operands are OK too. */
7469 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7470 && i
.tm
.operand_types
[op
].bitfield
.word
)
7473 /* crc32 only wants its source operand checked here. */
7474 if (i
.tm
.base_opcode
== 0xf0
7475 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
7476 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
7480 /* Any other register is bad. */
7481 as_bad (_("`%s%s' not allowed with `%s%c'"),
7482 register_prefix
, i
.op
[op
].regs
->reg_name
,
7483 i
.tm
.name
, i
.suffix
);
7490 check_long_reg (void)
7494 for (op
= i
.operands
; --op
>= 0;)
7495 /* Skip non-register operands. */
7496 if (i
.types
[op
].bitfield
.class != Reg
)
7498 /* Reject eight bit registers, except where the template requires
7499 them. (eg. movzb) */
7500 else if (i
.types
[op
].bitfield
.byte
7501 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7502 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7503 && (i
.tm
.operand_types
[op
].bitfield
.word
7504 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7506 as_bad (_("`%s%s' not allowed with `%s%c'"),
7508 i
.op
[op
].regs
->reg_name
,
7513 /* Error if the e prefix on a general reg is missing. */
7514 else if (i
.types
[op
].bitfield
.word
7515 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7516 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7517 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7519 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7520 register_prefix
, i
.op
[op
].regs
->reg_name
,
7524 /* Warn if the r prefix on a general reg is present. */
7525 else if (i
.types
[op
].bitfield
.qword
7526 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7527 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7528 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7531 && i
.tm
.opcode_modifier
.toqword
7532 && i
.types
[0].bitfield
.class != RegSIMD
)
7534 /* Convert to QWORD. We want REX byte. */
7535 i
.suffix
= QWORD_MNEM_SUFFIX
;
7539 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7540 register_prefix
, i
.op
[op
].regs
->reg_name
,
7549 check_qword_reg (void)
7553 for (op
= i
.operands
; --op
>= 0; )
7554 /* Skip non-register operands. */
7555 if (i
.types
[op
].bitfield
.class != Reg
)
7557 /* Reject eight bit registers, except where the template requires
7558 them. (eg. movzb) */
7559 else if (i
.types
[op
].bitfield
.byte
7560 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7561 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7562 && (i
.tm
.operand_types
[op
].bitfield
.word
7563 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7565 as_bad (_("`%s%s' not allowed with `%s%c'"),
7567 i
.op
[op
].regs
->reg_name
,
7572 /* Warn if the r prefix on a general reg is missing. */
7573 else if ((i
.types
[op
].bitfield
.word
7574 || i
.types
[op
].bitfield
.dword
)
7575 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7576 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7577 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7579 /* Prohibit these changes in the 64bit mode, since the
7580 lowering is more complicated. */
7582 && i
.tm
.opcode_modifier
.todword
7583 && i
.types
[0].bitfield
.class != RegSIMD
)
7585 /* Convert to DWORD. We don't want REX byte. */
7586 i
.suffix
= LONG_MNEM_SUFFIX
;
7590 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7591 register_prefix
, i
.op
[op
].regs
->reg_name
,
7600 check_word_reg (void)
7603 for (op
= i
.operands
; --op
>= 0;)
7604 /* Skip non-register operands. */
7605 if (i
.types
[op
].bitfield
.class != Reg
)
7607 /* Reject eight bit registers, except where the template requires
7608 them. (eg. movzb) */
7609 else if (i
.types
[op
].bitfield
.byte
7610 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7611 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7612 && (i
.tm
.operand_types
[op
].bitfield
.word
7613 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7615 as_bad (_("`%s%s' not allowed with `%s%c'"),
7617 i
.op
[op
].regs
->reg_name
,
7622 /* Error if the e or r prefix on a general reg is present. */
7623 else if ((i
.types
[op
].bitfield
.dword
7624 || i
.types
[op
].bitfield
.qword
)
7625 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7626 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7627 && i
.tm
.operand_types
[op
].bitfield
.word
)
7629 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7630 register_prefix
, i
.op
[op
].regs
->reg_name
,
7638 update_imm (unsigned int j
)
7640 i386_operand_type overlap
= i
.types
[j
];
7641 if ((overlap
.bitfield
.imm8
7642 || overlap
.bitfield
.imm8s
7643 || overlap
.bitfield
.imm16
7644 || overlap
.bitfield
.imm32
7645 || overlap
.bitfield
.imm32s
7646 || overlap
.bitfield
.imm64
)
7647 && !operand_type_equal (&overlap
, &imm8
)
7648 && !operand_type_equal (&overlap
, &imm8s
)
7649 && !operand_type_equal (&overlap
, &imm16
)
7650 && !operand_type_equal (&overlap
, &imm32
)
7651 && !operand_type_equal (&overlap
, &imm32s
)
7652 && !operand_type_equal (&overlap
, &imm64
))
7656 i386_operand_type temp
;
7658 operand_type_set (&temp
, 0);
7659 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7661 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7662 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7664 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7665 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7666 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7668 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7669 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7672 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7675 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7676 || operand_type_equal (&overlap
, &imm16_32
)
7677 || operand_type_equal (&overlap
, &imm16_32s
))
7679 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7684 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7685 overlap
= operand_type_and (overlap
, imm32s
);
7686 else if (i
.prefix
[DATA_PREFIX
])
7687 overlap
= operand_type_and (overlap
,
7688 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7689 if (!operand_type_equal (&overlap
, &imm8
)
7690 && !operand_type_equal (&overlap
, &imm8s
)
7691 && !operand_type_equal (&overlap
, &imm16
)
7692 && !operand_type_equal (&overlap
, &imm32
)
7693 && !operand_type_equal (&overlap
, &imm32s
)
7694 && !operand_type_equal (&overlap
, &imm64
))
7696 as_bad (_("no instruction mnemonic suffix given; "
7697 "can't determine immediate size"));
7701 i
.types
[j
] = overlap
;
7711 /* Update the first 2 immediate operands. */
7712 n
= i
.operands
> 2 ? 2 : i
.operands
;
7715 for (j
= 0; j
< n
; j
++)
7716 if (update_imm (j
) == 0)
7719 /* The 3rd operand can't be immediate operand. */
7720 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7727 process_operands (void)
7729 /* Default segment register this instruction will use for memory
7730 accesses. 0 means unknown. This is only for optimizing out
7731 unnecessary segment overrides. */
7732 const reg_entry
*default_seg
= NULL
;
7734 if (i
.tm
.opcode_modifier
.sse2avx
)
7736 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7738 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7739 i
.prefix
[REX_PREFIX
] = 0;
7742 /* ImmExt should be processed after SSE2AVX. */
7743 else if (i
.tm
.opcode_modifier
.immext
)
7746 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7748 unsigned int dupl
= i
.operands
;
7749 unsigned int dest
= dupl
- 1;
7752 /* The destination must be an xmm register. */
7753 gas_assert (i
.reg_operands
7754 && MAX_OPERANDS
> dupl
7755 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7757 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7758 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7760 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7762 /* Keep xmm0 for instructions with VEX prefix and 3
7764 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7765 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7770 /* We remove the first xmm0 and keep the number of
7771 operands unchanged, which in fact duplicates the
7773 for (j
= 1; j
< i
.operands
; j
++)
7775 i
.op
[j
- 1] = i
.op
[j
];
7776 i
.types
[j
- 1] = i
.types
[j
];
7777 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7778 i
.flags
[j
- 1] = i
.flags
[j
];
7782 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7784 gas_assert ((MAX_OPERANDS
- 1) > dupl
7785 && (i
.tm
.opcode_modifier
.vexsources
7788 /* Add the implicit xmm0 for instructions with VEX prefix
7790 for (j
= i
.operands
; j
> 0; j
--)
7792 i
.op
[j
] = i
.op
[j
- 1];
7793 i
.types
[j
] = i
.types
[j
- 1];
7794 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7795 i
.flags
[j
] = i
.flags
[j
- 1];
7798 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7799 i
.types
[0] = regxmm
;
7800 i
.tm
.operand_types
[0] = regxmm
;
7803 i
.reg_operands
+= 2;
7808 i
.op
[dupl
] = i
.op
[dest
];
7809 i
.types
[dupl
] = i
.types
[dest
];
7810 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7811 i
.flags
[dupl
] = i
.flags
[dest
];
7820 i
.op
[dupl
] = i
.op
[dest
];
7821 i
.types
[dupl
] = i
.types
[dest
];
7822 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7823 i
.flags
[dupl
] = i
.flags
[dest
];
7826 if (i
.tm
.opcode_modifier
.immext
)
7829 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7830 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7834 for (j
= 1; j
< i
.operands
; j
++)
7836 i
.op
[j
- 1] = i
.op
[j
];
7837 i
.types
[j
- 1] = i
.types
[j
];
7839 /* We need to adjust fields in i.tm since they are used by
7840 build_modrm_byte. */
7841 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7843 i
.flags
[j
- 1] = i
.flags
[j
];
7850 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7852 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7854 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7855 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7856 regnum
= register_number (i
.op
[1].regs
);
7857 first_reg_in_group
= regnum
& ~3;
7858 last_reg_in_group
= first_reg_in_group
+ 3;
7859 if (regnum
!= first_reg_in_group
)
7860 as_warn (_("source register `%s%s' implicitly denotes"
7861 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7862 register_prefix
, i
.op
[1].regs
->reg_name
,
7863 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7864 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7867 else if (i
.tm
.opcode_modifier
.regkludge
)
7869 /* The imul $imm, %reg instruction is converted into
7870 imul $imm, %reg, %reg, and the clr %reg instruction
7871 is converted into xor %reg, %reg. */
7873 unsigned int first_reg_op
;
7875 if (operand_type_check (i
.types
[0], reg
))
7879 /* Pretend we saw the extra register operand. */
7880 gas_assert (i
.reg_operands
== 1
7881 && i
.op
[first_reg_op
+ 1].regs
== 0);
7882 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7883 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7888 if (i
.tm
.opcode_modifier
.modrm
)
7890 /* The opcode is completed (modulo i.tm.extension_opcode which
7891 must be put into the modrm byte). Now, we make the modrm and
7892 index base bytes based on all the info we've collected. */
7894 default_seg
= build_modrm_byte ();
7896 else if (i
.types
[0].bitfield
.class == SReg
)
7898 if (flag_code
!= CODE_64BIT
7899 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7900 && i
.op
[0].regs
->reg_num
== 1
7901 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
7902 && i
.op
[0].regs
->reg_num
< 4)
7904 as_bad (_("you can't `%s %s%s'"),
7905 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7908 if (i
.op
[0].regs
->reg_num
> 3
7909 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
)
7911 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
7912 i
.tm
.opcode_modifier
.opcodespace
= SPACE_0F
;
7914 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7916 else if (i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7917 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
7919 default_seg
= reg_ds
;
7921 else if (i
.tm
.opcode_modifier
.isstring
)
7923 /* For the string instructions that allow a segment override
7924 on one of their operands, the default segment is ds. */
7925 default_seg
= reg_ds
;
7927 else if (i
.short_form
)
7929 /* The register or float register operand is in operand
7931 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7933 /* Register goes in low 3 bits of opcode. */
7934 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7935 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7937 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7939 /* Warn about some common errors, but press on regardless.
7940 The first case can be generated by gcc (<= 2.8.1). */
7941 if (i
.operands
== 2)
7943 /* Reversed arguments on faddp, fsubp, etc. */
7944 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7945 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7946 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7950 /* Extraneous `l' suffix on fp insn. */
7951 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7952 register_prefix
, i
.op
[0].regs
->reg_name
);
7957 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7958 && i
.tm
.base_opcode
== 0x8d /* lea */
7959 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7960 && !is_any_vex_encoding(&i
.tm
))
7962 if (!quiet_warnings
)
7963 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7967 i
.prefix
[SEG_PREFIX
] = 0;
7971 /* If a segment was explicitly specified, and the specified segment
7972 is neither the default nor the one already recorded from a prefix,
7973 use an opcode prefix to select it. If we never figured out what
7974 the default segment is, then default_seg will be zero at this
7975 point, and the specified segment prefix will always be used. */
7977 && i
.seg
[0] != default_seg
7978 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
7980 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
7986 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7989 if (r
->reg_flags
& RegRex
)
7991 if (i
.rex
& rex_bit
)
7992 as_bad (_("same type of prefix used twice"));
7995 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7997 gas_assert (i
.vex
.register_specifier
== r
);
7998 i
.vex
.register_specifier
+= 8;
8001 if (r
->reg_flags
& RegVRex
)
8005 static const reg_entry
*
8006 build_modrm_byte (void)
8008 const reg_entry
*default_seg
= NULL
;
8009 unsigned int source
, dest
;
8012 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
8015 unsigned int nds
, reg_slot
;
8018 dest
= i
.operands
- 1;
8021 /* There are 2 kinds of instructions:
8022 1. 5 operands: 4 register operands or 3 register operands
8023 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8024 VexW0 or VexW1. The destination must be either XMM, YMM or
8026 2. 4 operands: 4 register operands or 3 register operands
8027 plus 1 memory operand, with VexXDS. */
8028 gas_assert ((i
.reg_operands
== 4
8029 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
8030 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8031 && i
.tm
.opcode_modifier
.vexw
8032 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8034 /* If VexW1 is set, the first non-immediate operand is the source and
8035 the second non-immediate one is encoded in the immediate operand. */
8036 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
8038 source
= i
.imm_operands
;
8039 reg_slot
= i
.imm_operands
+ 1;
8043 source
= i
.imm_operands
+ 1;
8044 reg_slot
= i
.imm_operands
;
8047 if (i
.imm_operands
== 0)
8049 /* When there is no immediate operand, generate an 8bit
8050 immediate operand to encode the first operand. */
8051 exp
= &im_expressions
[i
.imm_operands
++];
8052 i
.op
[i
.operands
].imms
= exp
;
8053 i
.types
[i
.operands
] = imm8
;
8056 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8057 exp
->X_op
= O_constant
;
8058 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
8059 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
8063 gas_assert (i
.imm_operands
== 1);
8064 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8065 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8067 /* Turn on Imm8 again so that output_imm will generate it. */
8068 i
.types
[0].bitfield
.imm8
= 1;
8070 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8071 i
.op
[0].imms
->X_add_number
8072 |= register_number (i
.op
[reg_slot
].regs
) << 4;
8073 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
8076 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
8077 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
8082 /* i.reg_operands MUST be the number of real register operands;
8083 implicit registers do not count. If there are 3 register
8084 operands, it must be a instruction with VexNDS. For a
8085 instruction with VexNDD, the destination register is encoded
8086 in VEX prefix. If there are 4 register operands, it must be
8087 a instruction with VEX prefix and 3 sources. */
8088 if (i
.mem_operands
== 0
8089 && ((i
.reg_operands
== 2
8090 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
8091 || (i
.reg_operands
== 3
8092 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8093 || (i
.reg_operands
== 4 && vex_3_sources
)))
8101 /* When there are 3 operands, one of them may be immediate,
8102 which may be the first or the last operand. Otherwise,
8103 the first operand must be shift count register (cl) or it
8104 is an instruction with VexNDS. */
8105 gas_assert (i
.imm_operands
== 1
8106 || (i
.imm_operands
== 0
8107 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8108 || (i
.types
[0].bitfield
.instance
== RegC
8109 && i
.types
[0].bitfield
.byte
))));
8110 if (operand_type_check (i
.types
[0], imm
)
8111 || (i
.types
[0].bitfield
.instance
== RegC
8112 && i
.types
[0].bitfield
.byte
))
8118 /* When there are 4 operands, the first two must be 8bit
8119 immediate operands. The source operand will be the 3rd
8122 For instructions with VexNDS, if the first operand
8123 an imm8, the source operand is the 2nd one. If the last
8124 operand is imm8, the source operand is the first one. */
8125 gas_assert ((i
.imm_operands
== 2
8126 && i
.types
[0].bitfield
.imm8
8127 && i
.types
[1].bitfield
.imm8
)
8128 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
8129 && i
.imm_operands
== 1
8130 && (i
.types
[0].bitfield
.imm8
8131 || i
.types
[i
.operands
- 1].bitfield
.imm8
8132 || i
.rounding
.type
!= rc_none
)));
8133 if (i
.imm_operands
== 2)
8137 if (i
.types
[0].bitfield
.imm8
)
8144 if (is_evex_encoding (&i
.tm
))
8146 /* For EVEX instructions, when there are 5 operands, the
8147 first one must be immediate operand. If the second one
8148 is immediate operand, the source operand is the 3th
8149 one. If the last one is immediate operand, the source
8150 operand is the 2nd one. */
8151 gas_assert (i
.imm_operands
== 2
8152 && i
.tm
.opcode_modifier
.sae
8153 && operand_type_check (i
.types
[0], imm
));
8154 if (operand_type_check (i
.types
[1], imm
))
8156 else if (operand_type_check (i
.types
[4], imm
))
8170 /* RC/SAE operand could be between DEST and SRC. That happens
8171 when one operand is GPR and the other one is XMM/YMM/ZMM
8173 if (i
.rounding
.type
!= rc_none
&& i
.rounding
.operand
== dest
)
8176 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8178 /* For instructions with VexNDS, the register-only source
8179 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
8180 register. It is encoded in VEX prefix. */
8182 i386_operand_type op
;
8185 /* Swap two source operands if needed. */
8186 if (i
.tm
.opcode_modifier
.swapsources
)
8194 op
= i
.tm
.operand_types
[vvvv
];
8195 if ((dest
+ 1) >= i
.operands
8196 || ((op
.bitfield
.class != Reg
8197 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
8198 && op
.bitfield
.class != RegSIMD
8199 && !operand_type_equal (&op
, ®mask
)))
8201 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
8207 /* One of the register operands will be encoded in the i.rm.reg
8208 field, the other in the combined i.rm.mode and i.rm.regmem
8209 fields. If no form of this instruction supports a memory
8210 destination operand, then we assume the source operand may
8211 sometimes be a memory operand and so we need to store the
8212 destination in the i.rm.reg field. */
8213 if (!i
.tm
.opcode_modifier
.regmem
8214 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
8216 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8217 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8218 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8219 set_rex_vrex (i
.op
[source
].regs
, REX_B
, false);
8223 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8224 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8225 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8226 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
8228 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8230 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8233 add_prefix (LOCK_PREFIX_OPCODE
);
8237 { /* If it's not 2 reg operands... */
8242 unsigned int fake_zero_displacement
= 0;
8245 for (op
= 0; op
< i
.operands
; op
++)
8246 if (i
.flags
[op
] & Operand_Mem
)
8248 gas_assert (op
< i
.operands
);
8250 if (i
.tm
.opcode_modifier
.sib
)
8252 /* The index register of VSIB shouldn't be RegIZ. */
8253 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8254 && i
.index_reg
->reg_num
== RegIZ
)
8257 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8260 i
.sib
.base
= NO_BASE_REGISTER
;
8261 i
.sib
.scale
= i
.log2_scale_factor
;
8262 i
.types
[op
].bitfield
.disp8
= 0;
8263 i
.types
[op
].bitfield
.disp16
= 0;
8264 i
.types
[op
].bitfield
.disp64
= 0;
8265 if (want_disp32 (&i
.tm
))
8267 /* Must be 32 bit */
8268 i
.types
[op
].bitfield
.disp32
= 1;
8269 i
.types
[op
].bitfield
.disp32s
= 0;
8273 i
.types
[op
].bitfield
.disp32
= 0;
8274 i
.types
[op
].bitfield
.disp32s
= 1;
8278 /* Since the mandatory SIB always has index register, so
8279 the code logic remains unchanged. The non-mandatory SIB
8280 without index register is allowed and will be handled
8284 if (i
.index_reg
->reg_num
== RegIZ
)
8285 i
.sib
.index
= NO_INDEX_REGISTER
;
8287 i
.sib
.index
= i
.index_reg
->reg_num
;
8288 set_rex_vrex (i
.index_reg
, REX_X
, false);
8292 default_seg
= reg_ds
;
8294 if (i
.base_reg
== 0)
8297 if (!i
.disp_operands
)
8298 fake_zero_displacement
= 1;
8299 if (i
.index_reg
== 0)
8301 i386_operand_type newdisp
;
8303 /* Both check for VSIB and mandatory non-vector SIB. */
8304 gas_assert (!i
.tm
.opcode_modifier
.sib
8305 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8306 /* Operand is just <disp> */
8307 if (flag_code
== CODE_64BIT
)
8309 /* 64bit mode overwrites the 32bit absolute
8310 addressing by RIP relative addressing and
8311 absolute addressing is encoded by one of the
8312 redundant SIB forms. */
8313 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8314 i
.sib
.base
= NO_BASE_REGISTER
;
8315 i
.sib
.index
= NO_INDEX_REGISTER
;
8316 newdisp
= (want_disp32(&i
.tm
) ? disp32
: disp32s
);
8318 else if ((flag_code
== CODE_16BIT
)
8319 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8321 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8326 i
.rm
.regmem
= NO_BASE_REGISTER
;
8329 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8330 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8332 else if (!i
.tm
.opcode_modifier
.sib
)
8334 /* !i.base_reg && i.index_reg */
8335 if (i
.index_reg
->reg_num
== RegIZ
)
8336 i
.sib
.index
= NO_INDEX_REGISTER
;
8338 i
.sib
.index
= i
.index_reg
->reg_num
;
8339 i
.sib
.base
= NO_BASE_REGISTER
;
8340 i
.sib
.scale
= i
.log2_scale_factor
;
8341 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8342 i
.types
[op
].bitfield
.disp8
= 0;
8343 i
.types
[op
].bitfield
.disp16
= 0;
8344 i
.types
[op
].bitfield
.disp64
= 0;
8345 if (want_disp32 (&i
.tm
))
8347 /* Must be 32 bit */
8348 i
.types
[op
].bitfield
.disp32
= 1;
8349 i
.types
[op
].bitfield
.disp32s
= 0;
8353 i
.types
[op
].bitfield
.disp32
= 0;
8354 i
.types
[op
].bitfield
.disp32s
= 1;
8356 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8360 /* RIP addressing for 64bit mode. */
8361 else if (i
.base_reg
->reg_num
== RegIP
)
8363 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8364 i
.rm
.regmem
= NO_BASE_REGISTER
;
8365 i
.types
[op
].bitfield
.disp8
= 0;
8366 i
.types
[op
].bitfield
.disp16
= 0;
8367 i
.types
[op
].bitfield
.disp32
= 0;
8368 i
.types
[op
].bitfield
.disp32s
= 1;
8369 i
.types
[op
].bitfield
.disp64
= 0;
8370 i
.flags
[op
] |= Operand_PCrel
;
8371 if (! i
.disp_operands
)
8372 fake_zero_displacement
= 1;
8374 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8376 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8377 switch (i
.base_reg
->reg_num
)
8380 if (i
.index_reg
== 0)
8382 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8383 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8386 default_seg
= reg_ss
;
8387 if (i
.index_reg
== 0)
8390 if (operand_type_check (i
.types
[op
], disp
) == 0)
8392 /* fake (%bp) into 0(%bp) */
8393 if (i
.disp_encoding
== disp_encoding_16bit
)
8394 i
.types
[op
].bitfield
.disp16
= 1;
8396 i
.types
[op
].bitfield
.disp8
= 1;
8397 fake_zero_displacement
= 1;
8400 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8401 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8403 default: /* (%si) -> 4 or (%di) -> 5 */
8404 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8406 if (!fake_zero_displacement
8410 fake_zero_displacement
= 1;
8411 if (i
.disp_encoding
== disp_encoding_8bit
)
8412 i
.types
[op
].bitfield
.disp8
= 1;
8414 i
.types
[op
].bitfield
.disp16
= 1;
8416 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8418 else /* i.base_reg and 32/64 bit mode */
8420 if (operand_type_check (i
.types
[op
], disp
))
8422 i
.types
[op
].bitfield
.disp16
= 0;
8423 i
.types
[op
].bitfield
.disp64
= 0;
8424 if (!want_disp32 (&i
.tm
))
8426 i
.types
[op
].bitfield
.disp32
= 0;
8427 i
.types
[op
].bitfield
.disp32s
= 1;
8431 i
.types
[op
].bitfield
.disp32
= 1;
8432 i
.types
[op
].bitfield
.disp32s
= 0;
8436 if (!i
.tm
.opcode_modifier
.sib
)
8437 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8438 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8440 i
.sib
.base
= i
.base_reg
->reg_num
;
8441 /* x86-64 ignores REX prefix bit here to avoid decoder
8443 if (!(i
.base_reg
->reg_flags
& RegRex
)
8444 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8445 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8446 default_seg
= reg_ss
;
8447 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8449 fake_zero_displacement
= 1;
8450 if (i
.disp_encoding
== disp_encoding_32bit
)
8451 i
.types
[op
].bitfield
.disp32
= 1;
8453 i
.types
[op
].bitfield
.disp8
= 1;
8455 i
.sib
.scale
= i
.log2_scale_factor
;
8456 if (i
.index_reg
== 0)
8458 /* Only check for VSIB. */
8459 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8460 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8461 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8463 /* <disp>(%esp) becomes two byte modrm with no index
8464 register. We've already stored the code for esp
8465 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8466 Any base register besides %esp will not use the
8467 extra modrm byte. */
8468 i
.sib
.index
= NO_INDEX_REGISTER
;
8470 else if (!i
.tm
.opcode_modifier
.sib
)
8472 if (i
.index_reg
->reg_num
== RegIZ
)
8473 i
.sib
.index
= NO_INDEX_REGISTER
;
8475 i
.sib
.index
= i
.index_reg
->reg_num
;
8476 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8477 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8482 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8483 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8487 if (!fake_zero_displacement
8491 fake_zero_displacement
= 1;
8492 if (i
.disp_encoding
== disp_encoding_8bit
)
8493 i
.types
[op
].bitfield
.disp8
= 1;
8495 i
.types
[op
].bitfield
.disp32
= 1;
8497 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8501 if (fake_zero_displacement
)
8503 /* Fakes a zero displacement assuming that i.types[op]
8504 holds the correct displacement size. */
8507 gas_assert (i
.op
[op
].disps
== 0);
8508 exp
= &disp_expressions
[i
.disp_operands
++];
8509 i
.op
[op
].disps
= exp
;
8510 exp
->X_op
= O_constant
;
8511 exp
->X_add_number
= 0;
8512 exp
->X_add_symbol
= (symbolS
*) 0;
8513 exp
->X_op_symbol
= (symbolS
*) 0;
8521 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8523 if (operand_type_check (i
.types
[0], imm
))
8524 i
.vex
.register_specifier
= NULL
;
8527 /* VEX.vvvv encodes one of the sources when the first
8528 operand is not an immediate. */
8529 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8530 i
.vex
.register_specifier
= i
.op
[0].regs
;
8532 i
.vex
.register_specifier
= i
.op
[1].regs
;
8535 /* Destination is a XMM register encoded in the ModRM.reg
8537 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8538 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8541 /* ModRM.rm and VEX.B encodes the other source. */
8542 if (!i
.mem_operands
)
8546 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8547 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8549 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8551 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8555 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8557 i
.vex
.register_specifier
= i
.op
[2].regs
;
8558 if (!i
.mem_operands
)
8561 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8562 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8566 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8567 (if any) based on i.tm.extension_opcode. Again, we must be
8568 careful to make sure that segment/control/debug/test/MMX
8569 registers are coded into the i.rm.reg field. */
8570 else if (i
.reg_operands
)
8573 unsigned int vex_reg
= ~0;
8575 for (op
= 0; op
< i
.operands
; op
++)
8576 if (i
.types
[op
].bitfield
.class == Reg
8577 || i
.types
[op
].bitfield
.class == RegBND
8578 || i
.types
[op
].bitfield
.class == RegMask
8579 || i
.types
[op
].bitfield
.class == SReg
8580 || i
.types
[op
].bitfield
.class == RegCR
8581 || i
.types
[op
].bitfield
.class == RegDR
8582 || i
.types
[op
].bitfield
.class == RegTR
8583 || i
.types
[op
].bitfield
.class == RegSIMD
8584 || i
.types
[op
].bitfield
.class == RegMMX
)
8589 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8591 /* For instructions with VexNDS, the register-only
8592 source operand is encoded in VEX prefix. */
8593 gas_assert (mem
!= (unsigned int) ~0);
8598 gas_assert (op
< i
.operands
);
8602 /* Check register-only source operand when two source
8603 operands are swapped. */
8604 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8605 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8609 gas_assert (mem
== (vex_reg
+ 1)
8610 && op
< i
.operands
);
8615 gas_assert (vex_reg
< i
.operands
);
8619 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8621 /* For instructions with VexNDD, the register destination
8622 is encoded in VEX prefix. */
8623 if (i
.mem_operands
== 0)
8625 /* There is no memory operand. */
8626 gas_assert ((op
+ 2) == i
.operands
);
8631 /* There are only 2 non-immediate operands. */
8632 gas_assert (op
< i
.imm_operands
+ 2
8633 && i
.operands
== i
.imm_operands
+ 2);
8634 vex_reg
= i
.imm_operands
+ 1;
8638 gas_assert (op
< i
.operands
);
8640 if (vex_reg
!= (unsigned int) ~0)
8642 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8644 if ((type
->bitfield
.class != Reg
8645 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8646 && type
->bitfield
.class != RegSIMD
8647 && !operand_type_equal (type
, ®mask
))
8650 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8653 /* Don't set OP operand twice. */
8656 /* If there is an extension opcode to put here, the
8657 register number must be put into the regmem field. */
8658 if (i
.tm
.extension_opcode
!= None
)
8660 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8661 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8662 i
.tm
.opcode_modifier
.sse2avx
);
8666 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8667 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8668 i
.tm
.opcode_modifier
.sse2avx
);
8672 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8673 must set it to 3 to indicate this is a register operand
8674 in the regmem field. */
8675 if (!i
.mem_operands
)
8679 /* Fill in i.rm.reg field with extension opcode (if any). */
8680 if (i
.tm
.extension_opcode
!= None
)
8681 i
.rm
.reg
= i
.tm
.extension_opcode
;
8687 frag_opcode_byte (unsigned char byte
)
8689 if (now_seg
!= absolute_section
)
8690 FRAG_APPEND_1_CHAR (byte
);
8692 ++abs_section_offset
;
8696 flip_code16 (unsigned int code16
)
8698 gas_assert (i
.tm
.operands
== 1);
8700 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8701 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8702 || i
.tm
.operand_types
[0].bitfield
.disp32s
8703 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8708 output_branch (void)
8714 relax_substateT subtype
;
8718 if (now_seg
== absolute_section
)
8720 as_bad (_("relaxable branches not supported in absolute section"));
8724 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8725 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8728 if (i
.prefix
[DATA_PREFIX
] != 0)
8732 code16
^= flip_code16(code16
);
8734 /* Pentium4 branch hints. */
8735 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8736 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8741 if (i
.prefix
[REX_PREFIX
] != 0)
8747 /* BND prefixed jump. */
8748 if (i
.prefix
[BND_PREFIX
] != 0)
8754 if (i
.prefixes
!= 0)
8755 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8757 /* It's always a symbol; End frag & setup for relax.
8758 Make sure there is enough room in this frag for the largest
8759 instruction we may generate in md_convert_frag. This is 2
8760 bytes for the opcode and room for the prefix and largest
8762 frag_grow (prefix
+ 2 + 4);
8763 /* Prefix and 1 opcode byte go in fr_fix. */
8764 p
= frag_more (prefix
+ 1);
8765 if (i
.prefix
[DATA_PREFIX
] != 0)
8766 *p
++ = DATA_PREFIX_OPCODE
;
8767 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8768 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8769 *p
++ = i
.prefix
[SEG_PREFIX
];
8770 if (i
.prefix
[BND_PREFIX
] != 0)
8771 *p
++ = BND_PREFIX_OPCODE
;
8772 if (i
.prefix
[REX_PREFIX
] != 0)
8773 *p
++ = i
.prefix
[REX_PREFIX
];
8774 *p
= i
.tm
.base_opcode
;
8776 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8777 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8778 else if (cpu_arch_flags
.bitfield
.cpui386
)
8779 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8781 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8784 sym
= i
.op
[0].disps
->X_add_symbol
;
8785 off
= i
.op
[0].disps
->X_add_number
;
8787 if (i
.op
[0].disps
->X_op
!= O_constant
8788 && i
.op
[0].disps
->X_op
!= O_symbol
)
8790 /* Handle complex expressions. */
8791 sym
= make_expr_symbol (i
.op
[0].disps
);
8795 /* 1 possible extra opcode + 4 byte displacement go in var part.
8796 Pass reloc in fr_var. */
8797 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8800 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8801 /* Return TRUE iff PLT32 relocation should be used for branching to
8805 need_plt32_p (symbolS
*s
)
8807 /* PLT32 relocation is ELF only. */
8812 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8813 krtld support it. */
8817 /* Since there is no need to prepare for PLT branch on x86-64, we
8818 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8819 be used as a marker for 32-bit PC-relative branches. */
8826 /* Weak or undefined symbol need PLT32 relocation. */
8827 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8830 /* Non-global symbol doesn't need PLT32 relocation. */
8831 if (! S_IS_EXTERNAL (s
))
8834 /* Other global symbols need PLT32 relocation. NB: Symbol with
8835 non-default visibilities are treated as normal global symbol
8836 so that PLT32 relocation can be used as a marker for 32-bit
8837 PC-relative branches. It is useful for linker relaxation. */
8848 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8850 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8852 /* This is a loop or jecxz type instruction. */
8854 if (i
.prefix
[ADDR_PREFIX
] != 0)
8856 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8859 /* Pentium4 branch hints. */
8860 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8861 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8863 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8872 if (flag_code
== CODE_16BIT
)
8875 if (i
.prefix
[DATA_PREFIX
] != 0)
8877 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8879 code16
^= flip_code16(code16
);
8887 /* BND prefixed jump. */
8888 if (i
.prefix
[BND_PREFIX
] != 0)
8890 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8894 if (i
.prefix
[REX_PREFIX
] != 0)
8896 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8900 if (i
.prefixes
!= 0)
8901 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8903 if (now_seg
== absolute_section
)
8905 abs_section_offset
+= i
.opcode_length
+ size
;
8909 p
= frag_more (i
.opcode_length
+ size
);
8910 switch (i
.opcode_length
)
8913 *p
++ = i
.tm
.base_opcode
>> 8;
8916 *p
++ = i
.tm
.base_opcode
;
8922 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8924 && jump_reloc
== NO_RELOC
8925 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8926 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8929 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8931 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8932 i
.op
[0].disps
, 1, jump_reloc
);
8934 /* All jumps handled here are signed, but don't unconditionally use a
8935 signed limit check for 32 and 16 bit jumps as we want to allow wrap
8936 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
8941 fixP
->fx_signed
= 1;
8945 if (i
.tm
.base_opcode
== 0xc7f8)
8946 fixP
->fx_signed
= 1;
8950 if (flag_code
== CODE_64BIT
)
8951 fixP
->fx_signed
= 1;
8957 output_interseg_jump (void)
8965 if (flag_code
== CODE_16BIT
)
8969 if (i
.prefix
[DATA_PREFIX
] != 0)
8976 gas_assert (!i
.prefix
[REX_PREFIX
]);
8982 if (i
.prefixes
!= 0)
8983 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8985 if (now_seg
== absolute_section
)
8987 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8991 /* 1 opcode; 2 segment; offset */
8992 p
= frag_more (prefix
+ 1 + 2 + size
);
8994 if (i
.prefix
[DATA_PREFIX
] != 0)
8995 *p
++ = DATA_PREFIX_OPCODE
;
8997 if (i
.prefix
[REX_PREFIX
] != 0)
8998 *p
++ = i
.prefix
[REX_PREFIX
];
9000 *p
++ = i
.tm
.base_opcode
;
9001 if (i
.op
[1].imms
->X_op
== O_constant
)
9003 offsetT n
= i
.op
[1].imms
->X_add_number
;
9006 && !fits_in_unsigned_word (n
)
9007 && !fits_in_signed_word (n
))
9009 as_bad (_("16-bit jump out of range"));
9012 md_number_to_chars (p
, n
, size
);
9015 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9016 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9019 if (i
.op
[0].imms
->X_op
== O_constant
)
9020 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9022 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9023 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9031 asection
*seg
= now_seg
;
9032 subsegT subseg
= now_subseg
;
9034 unsigned int alignment
, align_size_1
;
9035 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9036 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9037 unsigned int padding
;
9039 if (!IS_ELF
|| !x86_used_note
)
9042 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9044 /* The .note.gnu.property section layout:
9046 Field Length Contents
9049 n_descsz 4 The note descriptor size
9050 n_type 4 NT_GNU_PROPERTY_TYPE_0
9052 n_desc n_descsz The program property array
9056 /* Create the .note.gnu.property section. */
9057 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9058 bfd_set_section_flags (sec
,
9065 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9076 bfd_set_section_alignment (sec
, alignment
);
9077 elf_section_type (sec
) = SHT_NOTE
;
9079 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9081 isa_1_descsz_raw
= 4 + 4 + 4;
9082 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9083 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9085 feature_2_descsz_raw
= isa_1_descsz
;
9086 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9088 feature_2_descsz_raw
+= 4 + 4 + 4;
9089 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9090 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9093 descsz
= feature_2_descsz
;
9094 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9095 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9097 /* Write n_namsz. */
9098 md_number_to_chars (p
, (valueT
) 4, 4);
9100 /* Write n_descsz. */
9101 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9104 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9107 memcpy (p
+ 4 * 3, "GNU", 4);
9109 /* Write 4-byte type. */
9110 md_number_to_chars (p
+ 4 * 4,
9111 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9113 /* Write 4-byte data size. */
9114 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9116 /* Write 4-byte data. */
9117 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9119 /* Zero out paddings. */
9120 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9122 memset (p
+ 4 * 7, 0, padding
);
9124 /* Write 4-byte type. */
9125 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9126 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9128 /* Write 4-byte data size. */
9129 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9131 /* Write 4-byte data. */
9132 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9133 (valueT
) x86_feature_2_used
, 4);
9135 /* Zero out paddings. */
9136 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9138 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9140 /* We probably can't restore the current segment, for there likely
9143 subseg_set (seg
, subseg
);
9148 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9149 const char *frag_now_ptr
)
9151 unsigned int len
= 0;
9153 if (start_frag
!= frag_now
)
9155 const fragS
*fr
= start_frag
;
9160 } while (fr
&& fr
!= frag_now
);
9163 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9166 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9167 be macro-fused with conditional jumps.
9168 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9169 or is one of the following format:
9182 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9184 /* No RIP address. */
9185 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9188 /* No opcodes outside of base encoding space. */
9189 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9192 /* add, sub without add/sub m, imm. */
9193 if (i
.tm
.base_opcode
<= 5
9194 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9195 || ((i
.tm
.base_opcode
| 3) == 0x83
9196 && (i
.tm
.extension_opcode
== 0x5
9197 || i
.tm
.extension_opcode
== 0x0)))
9199 *mf_cmp_p
= mf_cmp_alu_cmp
;
9200 return !(i
.mem_operands
&& i
.imm_operands
);
9203 /* and without and m, imm. */
9204 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9205 || ((i
.tm
.base_opcode
| 3) == 0x83
9206 && i
.tm
.extension_opcode
== 0x4))
9208 *mf_cmp_p
= mf_cmp_test_and
;
9209 return !(i
.mem_operands
&& i
.imm_operands
);
9212 /* test without test m imm. */
9213 if ((i
.tm
.base_opcode
| 1) == 0x85
9214 || (i
.tm
.base_opcode
| 1) == 0xa9
9215 || ((i
.tm
.base_opcode
| 1) == 0xf7
9216 && i
.tm
.extension_opcode
== 0))
9218 *mf_cmp_p
= mf_cmp_test_and
;
9219 return !(i
.mem_operands
&& i
.imm_operands
);
9222 /* cmp without cmp m, imm. */
9223 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9224 || ((i
.tm
.base_opcode
| 3) == 0x83
9225 && (i
.tm
.extension_opcode
== 0x7)))
9227 *mf_cmp_p
= mf_cmp_alu_cmp
;
9228 return !(i
.mem_operands
&& i
.imm_operands
);
9231 /* inc, dec without inc/dec m. */
9232 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
9233 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9234 || ((i
.tm
.base_opcode
| 1) == 0xff
9235 && i
.tm
.extension_opcode
<= 0x1))
9237 *mf_cmp_p
= mf_cmp_incdec
;
9238 return !i
.mem_operands
;
9244 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9247 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9249 /* NB: Don't work with COND_JUMP86 without i386. */
9250 if (!align_branch_power
9251 || now_seg
== absolute_section
9252 || !cpu_arch_flags
.bitfield
.cpui386
9253 || !(align_branch
& align_branch_fused_bit
))
9256 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9258 if (last_insn
.kind
== last_insn_other
9259 || last_insn
.seg
!= now_seg
)
9262 as_warn_where (last_insn
.file
, last_insn
.line
,
9263 _("`%s` skips -malign-branch-boundary on `%s`"),
9264 last_insn
.name
, i
.tm
.name
);
9270 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9273 add_branch_prefix_frag_p (void)
9275 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9276 to PadLock instructions since they include prefixes in opcode. */
9277 if (!align_branch_power
9278 || !align_branch_prefix_size
9279 || now_seg
== absolute_section
9280 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9281 || !cpu_arch_flags
.bitfield
.cpui386
)
9284 /* Don't add prefix if it is a prefix or there is no operand in case
9285 that segment prefix is special. */
9286 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9289 if (last_insn
.kind
== last_insn_other
9290 || last_insn
.seg
!= now_seg
)
9294 as_warn_where (last_insn
.file
, last_insn
.line
,
9295 _("`%s` skips -malign-branch-boundary on `%s`"),
9296 last_insn
.name
, i
.tm
.name
);
9301 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9304 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9305 enum mf_jcc_kind
*mf_jcc_p
)
9309 /* NB: Don't work with COND_JUMP86 without i386. */
9310 if (!align_branch_power
9311 || now_seg
== absolute_section
9312 || !cpu_arch_flags
.bitfield
.cpui386
9313 || i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9318 /* Check for jcc and direct jmp. */
9319 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9321 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9323 *branch_p
= align_branch_jmp
;
9324 add_padding
= align_branch
& align_branch_jmp_bit
;
9328 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9329 igore the lowest bit. */
9330 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9331 *branch_p
= align_branch_jcc
;
9332 if ((align_branch
& align_branch_jcc_bit
))
9336 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9339 *branch_p
= align_branch_ret
;
9340 if ((align_branch
& align_branch_ret_bit
))
9345 /* Check for indirect jmp, direct and indirect calls. */
9346 if (i
.tm
.base_opcode
== 0xe8)
9349 *branch_p
= align_branch_call
;
9350 if ((align_branch
& align_branch_call_bit
))
9353 else if (i
.tm
.base_opcode
== 0xff
9354 && (i
.tm
.extension_opcode
== 2
9355 || i
.tm
.extension_opcode
== 4))
9357 /* Indirect call and jmp. */
9358 *branch_p
= align_branch_indirect
;
9359 if ((align_branch
& align_branch_indirect_bit
))
9366 && (i
.op
[0].disps
->X_op
== O_symbol
9367 || (i
.op
[0].disps
->X_op
== O_subtract
9368 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9370 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9371 /* No padding to call to global or undefined tls_get_addr. */
9372 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9373 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9379 && last_insn
.kind
!= last_insn_other
9380 && last_insn
.seg
== now_seg
)
9383 as_warn_where (last_insn
.file
, last_insn
.line
,
9384 _("`%s` skips -malign-branch-boundary on `%s`"),
9385 last_insn
.name
, i
.tm
.name
);
9395 fragS
*insn_start_frag
;
9396 offsetT insn_start_off
;
9397 fragS
*fragP
= NULL
;
9398 enum align_branch_kind branch
= align_branch_none
;
9399 /* The initializer is arbitrary just to avoid uninitialized error.
9400 it's actually either assigned in add_branch_padding_frag_p
9401 or never be used. */
9402 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9404 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9405 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9407 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9408 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9409 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9411 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9412 || i
.tm
.cpu_flags
.bitfield
.cpu287
9413 || i
.tm
.cpu_flags
.bitfield
.cpu387
9414 || i
.tm
.cpu_flags
.bitfield
.cpu687
9415 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9416 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9418 if ((i
.xstate
& xstate_mmx
)
9419 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
9420 && !is_any_vex_encoding (&i
.tm
)
9421 && (i
.tm
.base_opcode
== 0x77 /* emms */
9422 || i
.tm
.base_opcode
== 0x0e /* femms */)))
9423 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9427 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9428 i
.xstate
|= xstate_zmm
;
9429 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9430 i
.xstate
|= xstate_ymm
;
9431 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9432 i
.xstate
|= xstate_xmm
;
9435 /* vzeroall / vzeroupper */
9436 if (i
.tm
.base_opcode
== 0x77 && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9437 i
.xstate
|= xstate_ymm
;
9439 if ((i
.xstate
& xstate_xmm
)
9440 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9441 || (i
.tm
.base_opcode
== 0xae
9442 && (i
.tm
.cpu_flags
.bitfield
.cpusse
9443 || i
.tm
.cpu_flags
.bitfield
.cpuavx
))
9444 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9445 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9446 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9448 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9449 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9450 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9451 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9452 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9453 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9454 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9455 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9456 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9457 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9458 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9459 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9460 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9461 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9463 if (x86_feature_2_used
9464 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9465 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9466 || (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
9467 && i
.tm
.base_opcode
== 0xc7
9468 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
9469 && i
.tm
.extension_opcode
== 1) /* cmpxchg8b */)
9470 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9471 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9472 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9473 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9474 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9475 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9476 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9477 /* LAHF-SAHF insns in 64-bit mode. */
9478 || (flag_code
== CODE_64BIT
9479 && (i
.tm
.base_opcode
| 1) == 0x9f
9480 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
))
9481 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9482 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9483 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9484 /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW,
9485 CpuAVX512DQ, LPW, TBM and AMX. */
9486 || (i
.tm
.opcode_modifier
.vex
9487 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9488 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9489 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9490 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9491 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9492 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9493 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9494 || i
.tm
.cpu_flags
.bitfield
.cpufma
9495 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9496 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9497 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9498 || (x86_feature_2_used
9499 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9500 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9501 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9502 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9503 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9504 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9505 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9506 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9507 /* Any EVEX encoded insns except for AVX512ER, AVX512PF and
9509 || (i
.tm
.opcode_modifier
.evex
9510 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9511 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9512 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9513 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9517 /* Tie dwarf2 debug info to the address at the start of the insn.
9518 We can't do this after the insn has been output as the current
9519 frag may have been closed off. eg. by frag_var. */
9520 dwarf2_emit_insn (0);
9522 insn_start_frag
= frag_now
;
9523 insn_start_off
= frag_now_fix ();
9525 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9528 /* Branch can be 8 bytes. Leave some room for prefixes. */
9529 unsigned int max_branch_padding_size
= 14;
9531 /* Align section to boundary. */
9532 record_alignment (now_seg
, align_branch_power
);
9534 /* Make room for padding. */
9535 frag_grow (max_branch_padding_size
);
9537 /* Start of the padding. */
9542 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9543 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9546 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9547 fragP
->tc_frag_data
.branch_type
= branch
;
9548 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9552 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9554 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9555 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9557 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9558 output_interseg_jump ();
9561 /* Output normal instructions here. */
9565 enum mf_cmp_kind mf_cmp
;
9568 && (i
.tm
.base_opcode
== 0xaee8
9569 || i
.tm
.base_opcode
== 0xaef0
9570 || i
.tm
.base_opcode
== 0xaef8))
9572 /* Encode lfence, mfence, and sfence as
9573 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9574 if (now_seg
!= absolute_section
)
9576 offsetT val
= 0x240483f0ULL
;
9579 md_number_to_chars (p
, val
, 5);
9582 abs_section_offset
+= 5;
9586 /* Some processors fail on LOCK prefix. This options makes
9587 assembler ignore LOCK prefix and serves as a workaround. */
9588 if (omit_lock_prefix
)
9590 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9591 && i
.tm
.opcode_modifier
.isprefix
)
9593 i
.prefix
[LOCK_PREFIX
] = 0;
9597 /* Skip if this is a branch. */
9599 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9601 /* Make room for padding. */
9602 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9607 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9608 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9611 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9612 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9613 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9615 else if (add_branch_prefix_frag_p ())
9617 unsigned int max_prefix_size
= align_branch_prefix_size
;
9619 /* Make room for padding. */
9620 frag_grow (max_prefix_size
);
9625 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9626 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9629 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9632 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9633 don't need the explicit prefix. */
9634 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9636 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9645 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9646 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9650 switch (i
.opcode_length
)
9655 /* Check for pseudo prefixes. */
9656 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
9658 as_bad_where (insn_start_frag
->fr_file
,
9659 insn_start_frag
->fr_line
,
9660 _("pseudo prefix without instruction"));
9670 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9671 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9672 R_X86_64_GOTTPOFF relocation so that linker can safely
9673 perform IE->LE optimization. A dummy REX_OPCODE prefix
9674 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9675 relocation for GDesc -> IE/LE optimization. */
9676 if (x86_elf_abi
== X86_64_X32_ABI
9678 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9679 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9680 && i
.prefix
[REX_PREFIX
] == 0)
9681 add_prefix (REX_OPCODE
);
9684 /* The prefix bytes. */
9685 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9687 frag_opcode_byte (*q
);
9691 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9697 frag_opcode_byte (*q
);
9700 /* There should be no other prefixes for instructions
9705 /* For EVEX instructions i.vrex should become 0 after
9706 build_evex_prefix. For VEX instructions upper 16 registers
9707 aren't available, so VREX should be 0. */
9710 /* Now the VEX prefix. */
9711 if (now_seg
!= absolute_section
)
9713 p
= frag_more (i
.vex
.length
);
9714 for (j
= 0; j
< i
.vex
.length
; j
++)
9715 p
[j
] = i
.vex
.bytes
[j
];
9718 abs_section_offset
+= i
.vex
.length
;
9721 /* Now the opcode; be careful about word order here! */
9722 j
= i
.opcode_length
;
9724 switch (i
.tm
.opcode_modifier
.opcodespace
)
9739 if (now_seg
== absolute_section
)
9740 abs_section_offset
+= j
;
9743 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9749 && i
.tm
.opcode_modifier
.opcodespace
!= SPACE_BASE
)
9752 if (i
.tm
.opcode_modifier
.opcodespace
!= SPACE_0F
)
9753 *p
++ = i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F38
9757 switch (i
.opcode_length
)
9760 /* Put out high byte first: can't use md_number_to_chars! */
9761 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9764 *p
= i
.tm
.base_opcode
& 0xff;
9773 /* Now the modrm byte and sib byte (if present). */
9774 if (i
.tm
.opcode_modifier
.modrm
)
9776 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9778 | (i
.rm
.mode
<< 6));
9779 /* If i.rm.regmem == ESP (4)
9780 && i.rm.mode != (Register mode)
9782 ==> need second modrm byte. */
9783 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9785 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9786 frag_opcode_byte ((i
.sib
.base
<< 0)
9787 | (i
.sib
.index
<< 3)
9788 | (i
.sib
.scale
<< 6));
9791 if (i
.disp_operands
)
9792 output_disp (insn_start_frag
, insn_start_off
);
9795 output_imm (insn_start_frag
, insn_start_off
);
9798 * frag_now_fix () returning plain abs_section_offset when we're in the
9799 * absolute section, and abs_section_offset not getting updated as data
9800 * gets added to the frag breaks the logic below.
9802 if (now_seg
!= absolute_section
)
9804 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9806 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9810 /* NB: Don't add prefix with GOTPC relocation since
9811 output_disp() above depends on the fixed encoding
9812 length. Can't add prefix with TLS relocation since
9813 it breaks TLS linker optimization. */
9814 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9815 /* Prefix count on the current instruction. */
9816 unsigned int count
= i
.vex
.length
;
9818 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9819 /* REX byte is encoded in VEX/EVEX prefix. */
9820 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9823 /* Count prefixes for extended opcode maps. */
9825 switch (i
.tm
.opcode_modifier
.opcodespace
)
9840 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9843 /* Set the maximum prefix size in BRANCH_PREFIX
9845 if (fragP
->tc_frag_data
.max_bytes
> max
)
9846 fragP
->tc_frag_data
.max_bytes
= max
;
9847 if (fragP
->tc_frag_data
.max_bytes
> count
)
9848 fragP
->tc_frag_data
.max_bytes
-= count
;
9850 fragP
->tc_frag_data
.max_bytes
= 0;
9854 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9856 unsigned int max_prefix_size
;
9857 if (align_branch_prefix_size
> max
)
9858 max_prefix_size
= max
;
9860 max_prefix_size
= align_branch_prefix_size
;
9861 if (max_prefix_size
> count
)
9862 fragP
->tc_frag_data
.max_prefix_length
9863 = max_prefix_size
- count
;
9866 /* Use existing segment prefix if possible. Use CS
9867 segment prefix in 64-bit mode. In 32-bit mode, use SS
9868 segment prefix with ESP/EBP base register and use DS
9869 segment prefix without ESP/EBP base register. */
9870 if (i
.prefix
[SEG_PREFIX
])
9871 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9872 else if (flag_code
== CODE_64BIT
)
9873 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9875 && (i
.base_reg
->reg_num
== 4
9876 || i
.base_reg
->reg_num
== 5))
9877 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9879 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9884 /* NB: Don't work with COND_JUMP86 without i386. */
9885 if (align_branch_power
9886 && now_seg
!= absolute_section
9887 && cpu_arch_flags
.bitfield
.cpui386
)
9889 /* Terminate each frag so that we can add prefix and check for
9891 frag_wane (frag_now
);
9898 pi ("" /*line*/, &i
);
9900 #endif /* DEBUG386 */
9903 /* Return the size of the displacement operand N. */
9906 disp_size (unsigned int n
)
9910 if (i
.types
[n
].bitfield
.disp64
)
9912 else if (i
.types
[n
].bitfield
.disp8
)
9914 else if (i
.types
[n
].bitfield
.disp16
)
9919 /* Return the size of the immediate operand N. */
9922 imm_size (unsigned int n
)
9925 if (i
.types
[n
].bitfield
.imm64
)
9927 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9929 else if (i
.types
[n
].bitfield
.imm16
)
9935 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9940 for (n
= 0; n
< i
.operands
; n
++)
9942 if (operand_type_check (i
.types
[n
], disp
))
9944 int size
= disp_size (n
);
9946 if (now_seg
== absolute_section
)
9947 abs_section_offset
+= size
;
9948 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9950 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9952 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9954 p
= frag_more (size
);
9955 md_number_to_chars (p
, val
, size
);
9959 enum bfd_reloc_code_real reloc_type
;
9960 int sign
= i
.types
[n
].bitfield
.disp32s
;
9961 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9964 /* We can't have 8 bit displacement here. */
9965 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9967 /* The PC relative address is computed relative
9968 to the instruction boundary, so in case immediate
9969 fields follows, we need to adjust the value. */
9970 if (pcrel
&& i
.imm_operands
)
9975 for (n1
= 0; n1
< i
.operands
; n1
++)
9976 if (operand_type_check (i
.types
[n1
], imm
))
9978 /* Only one immediate is allowed for PC
9979 relative address. */
9980 gas_assert (sz
== 0);
9982 i
.op
[n
].disps
->X_add_number
-= sz
;
9984 /* We should find the immediate. */
9985 gas_assert (sz
!= 0);
9988 p
= frag_more (size
);
9989 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9991 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9992 && (((reloc_type
== BFD_RELOC_32
9993 || reloc_type
== BFD_RELOC_X86_64_32S
9994 || (reloc_type
== BFD_RELOC_64
9996 && (i
.op
[n
].disps
->X_op
== O_symbol
9997 || (i
.op
[n
].disps
->X_op
== O_add
9998 && ((symbol_get_value_expression
9999 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10001 || reloc_type
== BFD_RELOC_32_PCREL
))
10005 reloc_type
= BFD_RELOC_386_GOTPC
;
10006 i
.has_gotpc_tls_reloc
= true;
10007 i
.op
[n
].disps
->X_add_number
+=
10008 encoding_length (insn_start_frag
, insn_start_off
, p
);
10010 else if (reloc_type
== BFD_RELOC_64
)
10011 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10013 /* Don't do the adjustment for x86-64, as there
10014 the pcrel addressing is relative to the _next_
10015 insn, and that is taken care of in other code. */
10016 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10018 else if (align_branch_power
)
10020 switch (reloc_type
)
10022 case BFD_RELOC_386_TLS_GD
:
10023 case BFD_RELOC_386_TLS_LDM
:
10024 case BFD_RELOC_386_TLS_IE
:
10025 case BFD_RELOC_386_TLS_IE_32
:
10026 case BFD_RELOC_386_TLS_GOTIE
:
10027 case BFD_RELOC_386_TLS_GOTDESC
:
10028 case BFD_RELOC_386_TLS_DESC_CALL
:
10029 case BFD_RELOC_X86_64_TLSGD
:
10030 case BFD_RELOC_X86_64_TLSLD
:
10031 case BFD_RELOC_X86_64_GOTTPOFF
:
10032 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10033 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10034 i
.has_gotpc_tls_reloc
= true;
10039 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10040 size
, i
.op
[n
].disps
, pcrel
,
10043 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10044 && !i
.prefix
[ADDR_PREFIX
])
10045 fixP
->fx_signed
= 1;
10047 /* Check for "call/jmp *mem", "mov mem, %reg",
10048 "test %reg, mem" and "binop mem, %reg" where binop
10049 is one of adc, add, and, cmp, or, sbb, sub, xor
10050 instructions without data prefix. Always generate
10051 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10052 if (i
.prefix
[DATA_PREFIX
] == 0
10053 && (generate_relax_relocations
10056 && i
.rm
.regmem
== 5))
10058 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10059 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
10060 && ((i
.operands
== 1
10061 && i
.tm
.base_opcode
== 0xff
10062 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10063 || (i
.operands
== 2
10064 && (i
.tm
.base_opcode
== 0x8b
10065 || i
.tm
.base_opcode
== 0x85
10066 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10070 fixP
->fx_tcbit
= i
.rex
!= 0;
10072 && (i
.base_reg
->reg_num
== RegIP
))
10073 fixP
->fx_tcbit2
= 1;
10076 fixP
->fx_tcbit2
= 1;
10084 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10089 for (n
= 0; n
< i
.operands
; n
++)
10091 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
10092 if (i
.rounding
.type
!= rc_none
&& n
== i
.rounding
.operand
)
10095 if (operand_type_check (i
.types
[n
], imm
))
10097 int size
= imm_size (n
);
10099 if (now_seg
== absolute_section
)
10100 abs_section_offset
+= size
;
10101 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10105 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10107 p
= frag_more (size
);
10108 md_number_to_chars (p
, val
, size
);
10112 /* Not absolute_section.
10113 Need a 32-bit fixup (don't support 8bit
10114 non-absolute imms). Try to support other
10116 enum bfd_reloc_code_real reloc_type
;
10119 if (i
.types
[n
].bitfield
.imm32s
10120 && (i
.suffix
== QWORD_MNEM_SUFFIX
10121 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
10126 p
= frag_more (size
);
10127 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10129 /* This is tough to explain. We end up with this one if we
10130 * have operands that look like
10131 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10132 * obtain the absolute address of the GOT, and it is strongly
10133 * preferable from a performance point of view to avoid using
10134 * a runtime relocation for this. The actual sequence of
10135 * instructions often look something like:
10140 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10142 * The call and pop essentially return the absolute address
10143 * of the label .L66 and store it in %ebx. The linker itself
10144 * will ultimately change the first operand of the addl so
10145 * that %ebx points to the GOT, but to keep things simple, the
10146 * .o file must have this operand set so that it generates not
10147 * the absolute address of .L66, but the absolute address of
10148 * itself. This allows the linker itself simply treat a GOTPC
10149 * relocation as asking for a pcrel offset to the GOT to be
10150 * added in, and the addend of the relocation is stored in the
10151 * operand field for the instruction itself.
10153 * Our job here is to fix the operand so that it would add
10154 * the correct offset so that %ebx would point to itself. The
10155 * thing that is tricky is that .-.L66 will point to the
10156 * beginning of the instruction, so we need to further modify
10157 * the operand so that it will point to itself. There are
10158 * other cases where you have something like:
10160 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10162 * and here no correction would be required. Internally in
10163 * the assembler we treat operands of this form as not being
10164 * pcrel since the '.' is explicitly mentioned, and I wonder
10165 * whether it would simplify matters to do it this way. Who
10166 * knows. In earlier versions of the PIC patches, the
10167 * pcrel_adjust field was used to store the correction, but
10168 * since the expression is not pcrel, I felt it would be
10169 * confusing to do it this way. */
10171 if ((reloc_type
== BFD_RELOC_32
10172 || reloc_type
== BFD_RELOC_X86_64_32S
10173 || reloc_type
== BFD_RELOC_64
)
10175 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10176 && (i
.op
[n
].imms
->X_op
== O_symbol
10177 || (i
.op
[n
].imms
->X_op
== O_add
10178 && ((symbol_get_value_expression
10179 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10183 reloc_type
= BFD_RELOC_386_GOTPC
;
10184 else if (size
== 4)
10185 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10186 else if (size
== 8)
10187 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10188 i
.has_gotpc_tls_reloc
= true;
10189 i
.op
[n
].imms
->X_add_number
+=
10190 encoding_length (insn_start_frag
, insn_start_off
, p
);
10192 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10193 i
.op
[n
].imms
, 0, reloc_type
);
10199 /* x86_cons_fix_new is called via the expression parsing code when a
10200 reloc is needed. We use this hook to get the correct .got reloc. */
10201 static int cons_sign
= -1;
10204 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10205 expressionS
*exp
, bfd_reloc_code_real_type r
)
10207 r
= reloc (len
, 0, cons_sign
, r
);
10210 if (exp
->X_op
== O_secrel
)
10212 exp
->X_op
= O_symbol
;
10213 r
= BFD_RELOC_32_SECREL
;
10217 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10220 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10221 purpose of the `.dc.a' internal pseudo-op. */
10224 x86_address_bytes (void)
10226 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10228 return stdoutput
->arch_info
->bits_per_address
/ 8;
10231 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10232 || defined (LEX_AT)) && !defined (TE_PE)
10233 # define lex_got(reloc, adjust, types) NULL
10235 /* Parse operands of the form
10236 <symbol>@GOTOFF+<nnn>
10237 and similar .plt or .got references.
10239 If we find one, set up the correct relocation in RELOC and copy the
10240 input string, minus the `@GOTOFF' into a malloc'd buffer for
10241 parsing by the calling routine. Return this buffer, and if ADJUST
10242 is non-null set it to the length of the string we removed from the
10243 input line. Otherwise return NULL. */
10245 lex_got (enum bfd_reloc_code_real
*rel
,
10247 i386_operand_type
*types
)
10249 /* Some of the relocations depend on the size of what field is to
10250 be relocated. But in our callers i386_immediate and i386_displacement
10251 we don't yet know the operand size (this will be set by insn
10252 matching). Hence we record the word32 relocation here,
10253 and adjust the reloc according to the real size in reloc(). */
10254 static const struct {
10257 const enum bfd_reloc_code_real rel
[2];
10258 const i386_operand_type types64
;
10259 bool need_GOT_symbol
;
10262 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10263 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10264 BFD_RELOC_SIZE32
},
10265 OPERAND_TYPE_IMM32_64
, false },
10267 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10268 BFD_RELOC_X86_64_PLTOFF64
},
10269 OPERAND_TYPE_IMM64
, true },
10270 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10271 BFD_RELOC_X86_64_PLT32
},
10272 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10273 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10274 BFD_RELOC_X86_64_GOTPLT64
},
10275 OPERAND_TYPE_IMM64_DISP64
, true },
10276 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10277 BFD_RELOC_X86_64_GOTOFF64
},
10278 OPERAND_TYPE_IMM64_DISP64
, true },
10279 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10280 BFD_RELOC_X86_64_GOTPCREL
},
10281 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10282 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10283 BFD_RELOC_X86_64_TLSGD
},
10284 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10285 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10286 _dummy_first_bfd_reloc_code_real
},
10287 OPERAND_TYPE_NONE
, true },
10288 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10289 BFD_RELOC_X86_64_TLSLD
},
10290 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10291 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10292 BFD_RELOC_X86_64_GOTTPOFF
},
10293 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10294 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10295 BFD_RELOC_X86_64_TPOFF32
},
10296 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10297 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10298 _dummy_first_bfd_reloc_code_real
},
10299 OPERAND_TYPE_NONE
, true },
10300 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10301 BFD_RELOC_X86_64_DTPOFF32
},
10302 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10303 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10304 _dummy_first_bfd_reloc_code_real
},
10305 OPERAND_TYPE_NONE
, true },
10306 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10307 _dummy_first_bfd_reloc_code_real
},
10308 OPERAND_TYPE_NONE
, true },
10309 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10310 BFD_RELOC_X86_64_GOT32
},
10311 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10312 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10313 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10314 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10315 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10316 BFD_RELOC_X86_64_TLSDESC_CALL
},
10317 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10319 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10320 BFD_RELOC_32_SECREL
},
10321 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10327 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10332 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10333 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10336 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10338 int len
= gotrel
[j
].len
;
10339 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10341 if (gotrel
[j
].rel
[object_64bit
] != 0)
10344 char *tmpbuf
, *past_reloc
;
10346 *rel
= gotrel
[j
].rel
[object_64bit
];
10350 if (flag_code
!= CODE_64BIT
)
10352 types
->bitfield
.imm32
= 1;
10353 types
->bitfield
.disp32
= 1;
10356 *types
= gotrel
[j
].types64
;
10359 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10360 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10362 /* The length of the first part of our input line. */
10363 first
= cp
- input_line_pointer
;
10365 /* The second part goes from after the reloc token until
10366 (and including) an end_of_line char or comma. */
10367 past_reloc
= cp
+ 1 + len
;
10369 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10371 second
= cp
+ 1 - past_reloc
;
10373 /* Allocate and copy string. The trailing NUL shouldn't
10374 be necessary, but be safe. */
10375 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10376 memcpy (tmpbuf
, input_line_pointer
, first
);
10377 if (second
!= 0 && *past_reloc
!= ' ')
10378 /* Replace the relocation token with ' ', so that
10379 errors like foo@GOTOFF1 will be detected. */
10380 tmpbuf
[first
++] = ' ';
10382 /* Increment length by 1 if the relocation token is
10387 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10388 tmpbuf
[first
+ second
] = '\0';
10392 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10393 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10398 /* Might be a symbol version string. Don't as_bad here. */
10403 bfd_reloc_code_real_type
10404 x86_cons (expressionS
*exp
, int size
)
10406 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10408 intel_syntax
= -intel_syntax
;
10411 if (size
== 4 || (object_64bit
&& size
== 8))
10413 /* Handle @GOTOFF and the like in an expression. */
10415 char *gotfree_input_line
;
10418 save
= input_line_pointer
;
10419 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10420 if (gotfree_input_line
)
10421 input_line_pointer
= gotfree_input_line
;
10425 if (gotfree_input_line
)
10427 /* expression () has merrily parsed up to the end of line,
10428 or a comma - in the wrong buffer. Transfer how far
10429 input_line_pointer has moved to the right buffer. */
10430 input_line_pointer
= (save
10431 + (input_line_pointer
- gotfree_input_line
)
10433 free (gotfree_input_line
);
10434 if (exp
->X_op
== O_constant
10435 || exp
->X_op
== O_absent
10436 || exp
->X_op
== O_illegal
10437 || exp
->X_op
== O_register
10438 || exp
->X_op
== O_big
)
10440 char c
= *input_line_pointer
;
10441 *input_line_pointer
= 0;
10442 as_bad (_("missing or invalid expression `%s'"), save
);
10443 *input_line_pointer
= c
;
10445 else if ((got_reloc
== BFD_RELOC_386_PLT32
10446 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10447 && exp
->X_op
!= O_symbol
)
10449 char c
= *input_line_pointer
;
10450 *input_line_pointer
= 0;
10451 as_bad (_("invalid PLT expression `%s'"), save
);
10452 *input_line_pointer
= c
;
10459 intel_syntax
= -intel_syntax
;
10462 i386_intel_simplify (exp
);
10464 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10465 if (size
== 4 && exp
->X_op
== O_constant
&& !object_64bit
)
10466 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10472 signed_cons (int size
)
10482 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10489 if (exp
.X_op
== O_symbol
)
10490 exp
.X_op
= O_secrel
;
10492 emit_expr (&exp
, 4);
10494 while (*input_line_pointer
++ == ',');
10496 input_line_pointer
--;
10497 demand_empty_rest_of_line ();
10501 /* Handle Vector operations. */
10504 check_VecOperations (char *op_string
)
10506 const reg_entry
*mask
;
10513 if (*op_string
== '{')
10517 /* Check broadcasts. */
10518 if (startswith (op_string
, "1to"))
10520 unsigned int bcst_type
;
10522 if (i
.broadcast
.type
)
10523 goto duplicated_vec_op
;
10526 if (*op_string
== '8')
10528 else if (*op_string
== '4')
10530 else if (*op_string
== '2')
10532 else if (*op_string
== '1'
10533 && *(op_string
+1) == '6')
10540 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10545 i
.broadcast
.type
= bcst_type
;
10546 i
.broadcast
.operand
= this_operand
;
10548 /* Check masking operation. */
10549 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10551 if (mask
== &bad_reg
)
10554 /* k0 can't be used for write mask. */
10555 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10557 as_bad (_("`%s%s' can't be used for write mask"),
10558 register_prefix
, mask
->reg_name
);
10565 i
.mask
.operand
= this_operand
;
10567 else if (i
.mask
.reg
->reg_num
)
10568 goto duplicated_vec_op
;
10573 /* Only "{z}" is allowed here. No need to check
10574 zeroing mask explicitly. */
10575 if (i
.mask
.operand
!= (unsigned int) this_operand
)
10577 as_bad (_("invalid write mask `%s'"), saved
);
10582 op_string
= end_op
;
10584 /* Check zeroing-flag for masking operation. */
10585 else if (*op_string
== 'z')
10589 i
.mask
.reg
= reg_k0
;
10590 i
.mask
.zeroing
= 1;
10591 i
.mask
.operand
= this_operand
;
10595 if (i
.mask
.zeroing
)
10598 as_bad (_("duplicated `%s'"), saved
);
10602 i
.mask
.zeroing
= 1;
10604 /* Only "{%k}" is allowed here. No need to check mask
10605 register explicitly. */
10606 if (i
.mask
.operand
!= (unsigned int) this_operand
)
10608 as_bad (_("invalid zeroing-masking `%s'"),
10617 goto unknown_vec_op
;
10619 if (*op_string
!= '}')
10621 as_bad (_("missing `}' in `%s'"), saved
);
10626 /* Strip whitespace since the addition of pseudo prefixes
10627 changed how the scrubber treats '{'. */
10628 if (is_space_char (*op_string
))
10634 /* We don't know this one. */
10635 as_bad (_("unknown vector operation: `%s'"), saved
);
10639 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
10641 as_bad (_("zeroing-masking only allowed with write mask"));
10649 i386_immediate (char *imm_start
)
10651 char *save_input_line_pointer
;
10652 char *gotfree_input_line
;
10655 i386_operand_type types
;
10657 operand_type_set (&types
, ~0);
10659 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10661 as_bad (_("at most %d immediate operands are allowed"),
10662 MAX_IMMEDIATE_OPERANDS
);
10666 exp
= &im_expressions
[i
.imm_operands
++];
10667 i
.op
[this_operand
].imms
= exp
;
10669 if (is_space_char (*imm_start
))
10672 save_input_line_pointer
= input_line_pointer
;
10673 input_line_pointer
= imm_start
;
10675 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10676 if (gotfree_input_line
)
10677 input_line_pointer
= gotfree_input_line
;
10679 exp_seg
= expression (exp
);
10681 SKIP_WHITESPACE ();
10682 if (*input_line_pointer
)
10683 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10685 input_line_pointer
= save_input_line_pointer
;
10686 if (gotfree_input_line
)
10688 free (gotfree_input_line
);
10690 if (exp
->X_op
== O_constant
)
10691 exp
->X_op
= O_illegal
;
10694 if (exp_seg
== reg_section
)
10696 as_bad (_("illegal immediate register operand %s"), imm_start
);
10700 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10704 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10705 i386_operand_type types
, const char *imm_start
)
10707 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10710 as_bad (_("missing or invalid immediate expression `%s'"),
10714 else if (exp
->X_op
== O_constant
)
10716 /* Size it properly later. */
10717 i
.types
[this_operand
].bitfield
.imm64
= 1;
10719 /* If not 64bit, sign/zero extend val, to account for wraparound
10721 if (flag_code
!= CODE_64BIT
)
10722 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10724 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10725 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10726 && exp_seg
!= absolute_section
10727 && exp_seg
!= text_section
10728 && exp_seg
!= data_section
10729 && exp_seg
!= bss_section
10730 && exp_seg
!= undefined_section
10731 && !bfd_is_com_section (exp_seg
))
10733 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10739 /* This is an address. The size of the address will be
10740 determined later, depending on destination register,
10741 suffix, or the default for the section. */
10742 i
.types
[this_operand
].bitfield
.imm8
= 1;
10743 i
.types
[this_operand
].bitfield
.imm16
= 1;
10744 i
.types
[this_operand
].bitfield
.imm32
= 1;
10745 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10746 i
.types
[this_operand
].bitfield
.imm64
= 1;
10747 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10755 i386_scale (char *scale
)
10758 char *save
= input_line_pointer
;
10760 input_line_pointer
= scale
;
10761 val
= get_absolute_expression ();
10766 i
.log2_scale_factor
= 0;
10769 i
.log2_scale_factor
= 1;
10772 i
.log2_scale_factor
= 2;
10775 i
.log2_scale_factor
= 3;
10779 char sep
= *input_line_pointer
;
10781 *input_line_pointer
= '\0';
10782 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10784 *input_line_pointer
= sep
;
10785 input_line_pointer
= save
;
10789 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10791 as_warn (_("scale factor of %d without an index register"),
10792 1 << i
.log2_scale_factor
);
10793 i
.log2_scale_factor
= 0;
10795 scale
= input_line_pointer
;
10796 input_line_pointer
= save
;
10801 i386_displacement (char *disp_start
, char *disp_end
)
10805 char *save_input_line_pointer
;
10806 char *gotfree_input_line
;
10808 i386_operand_type bigdisp
, types
= anydisp
;
10811 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10813 as_bad (_("at most %d displacement operands are allowed"),
10814 MAX_MEMORY_OPERANDS
);
10818 operand_type_set (&bigdisp
, 0);
10820 || i
.types
[this_operand
].bitfield
.baseindex
10821 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10822 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10824 i386_addressing_mode ();
10825 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10826 if (flag_code
== CODE_64BIT
)
10830 bigdisp
.bitfield
.disp32s
= 1;
10831 bigdisp
.bitfield
.disp64
= 1;
10834 bigdisp
.bitfield
.disp32
= 1;
10836 else if ((flag_code
== CODE_16BIT
) ^ override
)
10837 bigdisp
.bitfield
.disp16
= 1;
10839 bigdisp
.bitfield
.disp32
= 1;
10843 /* For PC-relative branches, the width of the displacement may be
10844 dependent upon data size, but is never dependent upon address size.
10845 Also make sure to not unintentionally match against a non-PC-relative
10846 branch template. */
10847 static templates aux_templates
;
10848 const insn_template
*t
= current_templates
->start
;
10849 bool has_intel64
= false;
10851 aux_templates
.start
= t
;
10852 while (++t
< current_templates
->end
)
10854 if (t
->opcode_modifier
.jump
10855 != current_templates
->start
->opcode_modifier
.jump
)
10857 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10858 has_intel64
= true;
10860 if (t
< current_templates
->end
)
10862 aux_templates
.end
= t
;
10863 current_templates
= &aux_templates
;
10866 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10867 if (flag_code
== CODE_64BIT
)
10869 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10870 && (!intel64
|| !has_intel64
))
10871 bigdisp
.bitfield
.disp16
= 1;
10873 bigdisp
.bitfield
.disp32s
= 1;
10878 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10880 : LONG_MNEM_SUFFIX
));
10881 bigdisp
.bitfield
.disp32
= 1;
10882 if ((flag_code
== CODE_16BIT
) ^ override
)
10884 bigdisp
.bitfield
.disp32
= 0;
10885 bigdisp
.bitfield
.disp16
= 1;
10889 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10892 exp
= &disp_expressions
[i
.disp_operands
];
10893 i
.op
[this_operand
].disps
= exp
;
10895 save_input_line_pointer
= input_line_pointer
;
10896 input_line_pointer
= disp_start
;
10897 END_STRING_AND_SAVE (disp_end
);
10899 #ifndef GCC_ASM_O_HACK
10900 #define GCC_ASM_O_HACK 0
10903 END_STRING_AND_SAVE (disp_end
+ 1);
10904 if (i
.types
[this_operand
].bitfield
.baseIndex
10905 && displacement_string_end
[-1] == '+')
10907 /* This hack is to avoid a warning when using the "o"
10908 constraint within gcc asm statements.
10911 #define _set_tssldt_desc(n,addr,limit,type) \
10912 __asm__ __volatile__ ( \
10913 "movw %w2,%0\n\t" \
10914 "movw %w1,2+%0\n\t" \
10915 "rorl $16,%1\n\t" \
10916 "movb %b1,4+%0\n\t" \
10917 "movb %4,5+%0\n\t" \
10918 "movb $0,6+%0\n\t" \
10919 "movb %h1,7+%0\n\t" \
10921 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10923 This works great except that the output assembler ends
10924 up looking a bit weird if it turns out that there is
10925 no offset. You end up producing code that looks like:
10938 So here we provide the missing zero. */
10940 *displacement_string_end
= '0';
10943 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10944 if (gotfree_input_line
)
10945 input_line_pointer
= gotfree_input_line
;
10947 exp_seg
= expression (exp
);
10949 SKIP_WHITESPACE ();
10950 if (*input_line_pointer
)
10951 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10953 RESTORE_END_STRING (disp_end
+ 1);
10955 input_line_pointer
= save_input_line_pointer
;
10956 if (gotfree_input_line
)
10958 free (gotfree_input_line
);
10960 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10961 exp
->X_op
= O_illegal
;
10964 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10966 RESTORE_END_STRING (disp_end
);
10972 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10973 i386_operand_type types
, const char *disp_start
)
10975 i386_operand_type bigdisp
;
10978 /* We do this to make sure that the section symbol is in
10979 the symbol table. We will ultimately change the relocation
10980 to be relative to the beginning of the section. */
10981 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10982 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10983 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10985 if (exp
->X_op
!= O_symbol
)
10988 if (S_IS_LOCAL (exp
->X_add_symbol
)
10989 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10990 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10991 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10992 exp
->X_op
= O_subtract
;
10993 exp
->X_op_symbol
= GOT_symbol
;
10994 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10995 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10996 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10997 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10999 i
.reloc
[this_operand
] = BFD_RELOC_32
;
11002 else if (exp
->X_op
== O_absent
11003 || exp
->X_op
== O_illegal
11004 || exp
->X_op
== O_big
)
11007 as_bad (_("missing or invalid displacement expression `%s'"),
11012 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11013 else if (exp
->X_op
!= O_constant
11014 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
11015 && exp_seg
!= absolute_section
11016 && exp_seg
!= text_section
11017 && exp_seg
!= data_section
11018 && exp_seg
!= bss_section
11019 && exp_seg
!= undefined_section
11020 && !bfd_is_com_section (exp_seg
))
11022 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
11027 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
11028 /* Constants get taken care of by optimize_disp(). */
11029 && exp
->X_op
!= O_constant
)
11030 i
.types
[this_operand
].bitfield
.disp8
= 1;
11032 /* Check if this is a displacement only operand. */
11033 bigdisp
= i
.types
[this_operand
];
11034 bigdisp
.bitfield
.disp8
= 0;
11035 bigdisp
.bitfield
.disp16
= 0;
11036 bigdisp
.bitfield
.disp32
= 0;
11037 bigdisp
.bitfield
.disp32s
= 0;
11038 bigdisp
.bitfield
.disp64
= 0;
11039 if (operand_type_all_zero (&bigdisp
))
11040 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
11046 /* Return the active addressing mode, taking address override and
11047 registers forming the address into consideration. Update the
11048 address override prefix if necessary. */
11050 static enum flag_code
11051 i386_addressing_mode (void)
11053 enum flag_code addr_mode
;
11055 if (i
.prefix
[ADDR_PREFIX
])
11056 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
11057 else if (flag_code
== CODE_16BIT
11058 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
11059 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
11060 from md_assemble() by "is not a valid base/index expression"
11061 when there is a base and/or index. */
11062 && !i
.types
[this_operand
].bitfield
.baseindex
)
11064 /* MPX insn memory operands with neither base nor index must be forced
11065 to use 32-bit addressing in 16-bit mode. */
11066 addr_mode
= CODE_32BIT
;
11067 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11069 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
11070 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
11074 addr_mode
= flag_code
;
11076 #if INFER_ADDR_PREFIX
11077 if (i
.mem_operands
== 0)
11079 /* Infer address prefix from the first memory operand. */
11080 const reg_entry
*addr_reg
= i
.base_reg
;
11082 if (addr_reg
== NULL
)
11083 addr_reg
= i
.index_reg
;
11087 if (addr_reg
->reg_type
.bitfield
.dword
)
11088 addr_mode
= CODE_32BIT
;
11089 else if (flag_code
!= CODE_64BIT
11090 && addr_reg
->reg_type
.bitfield
.word
)
11091 addr_mode
= CODE_16BIT
;
11093 if (addr_mode
!= flag_code
)
11095 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
11097 /* Change the size of any displacement too. At most one
11098 of Disp16 or Disp32 is set.
11099 FIXME. There doesn't seem to be any real need for
11100 separate Disp16 and Disp32 flags. The same goes for
11101 Imm16 and Imm32. Removing them would probably clean
11102 up the code quite a lot. */
11103 if (flag_code
!= CODE_64BIT
11104 && (i
.types
[this_operand
].bitfield
.disp16
11105 || i
.types
[this_operand
].bitfield
.disp32
))
11106 i
.types
[this_operand
]
11107 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
11117 /* Make sure the memory operand we've been dealt is valid.
11118 Return 1 on success, 0 on a failure. */
11121 i386_index_check (const char *operand_string
)
11123 const char *kind
= "base/index";
11124 enum flag_code addr_mode
= i386_addressing_mode ();
11125 const insn_template
*t
= current_templates
->start
;
11127 if (t
->opcode_modifier
.isstring
11128 && !t
->cpu_flags
.bitfield
.cpupadlock
11129 && (current_templates
->end
[-1].opcode_modifier
.isstring
11130 || i
.mem_operands
))
11132 /* Memory operands of string insns are special in that they only allow
11133 a single register (rDI, rSI, or rBX) as their memory address. */
11134 const reg_entry
*expected_reg
;
11135 static const char *di_si
[][2] =
11141 static const char *bx
[] = { "ebx", "bx", "rbx" };
11143 kind
= "string address";
11145 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
11147 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
11148 - IS_STRING_ES_OP0
;
11151 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
11152 || ((!i
.mem_operands
!= !intel_syntax
)
11153 && current_templates
->end
[-1].operand_types
[1]
11154 .bitfield
.baseindex
))
11157 = (const reg_entry
*) str_hash_find (reg_hash
,
11158 di_si
[addr_mode
][op
== es_op
]);
11162 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11164 if (i
.base_reg
!= expected_reg
11166 || operand_type_check (i
.types
[this_operand
], disp
))
11168 /* The second memory operand must have the same size as
11172 && !((addr_mode
== CODE_64BIT
11173 && i
.base_reg
->reg_type
.bitfield
.qword
)
11174 || (addr_mode
== CODE_32BIT
11175 ? i
.base_reg
->reg_type
.bitfield
.dword
11176 : i
.base_reg
->reg_type
.bitfield
.word
)))
11179 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11181 intel_syntax
? '[' : '(',
11183 expected_reg
->reg_name
,
11184 intel_syntax
? ']' : ')');
11191 as_bad (_("`%s' is not a valid %s expression"),
11192 operand_string
, kind
);
11197 if (addr_mode
!= CODE_16BIT
)
11199 /* 32-bit/64-bit checks. */
11200 if (i
.disp_encoding
== disp_encoding_16bit
)
11203 as_bad (_("invalid `%s' prefix"),
11204 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11209 && ((addr_mode
== CODE_64BIT
11210 ? !i
.base_reg
->reg_type
.bitfield
.qword
11211 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11212 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11213 || i
.base_reg
->reg_num
== RegIZ
))
11215 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11216 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11217 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11218 && ((addr_mode
== CODE_64BIT
11219 ? !i
.index_reg
->reg_type
.bitfield
.qword
11220 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11221 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11224 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11225 if ((t
->opcode_modifier
.opcodeprefix
== PREFIX_0XF3
11226 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11227 && t
->base_opcode
== 0x1b)
11228 || (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11229 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11230 && (t
->base_opcode
& ~1) == 0x1a)
11231 || t
->opcode_modifier
.sib
== SIBMEM
)
11233 /* They cannot use RIP-relative addressing. */
11234 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11236 as_bad (_("`%s' cannot be used here"), operand_string
);
11240 /* bndldx and bndstx ignore their scale factor. */
11241 if (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11242 && t
->opcode_modifier
.opcodespace
== SPACE_0F
11243 && (t
->base_opcode
& ~1) == 0x1a
11244 && i
.log2_scale_factor
)
11245 as_warn (_("register scaling is being ignored here"));
11250 /* 16-bit checks. */
11251 if (i
.disp_encoding
== disp_encoding_32bit
)
11255 && (!i
.base_reg
->reg_type
.bitfield
.word
11256 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11258 && (!i
.index_reg
->reg_type
.bitfield
.word
11259 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11261 && i
.base_reg
->reg_num
< 6
11262 && i
.index_reg
->reg_num
>= 6
11263 && i
.log2_scale_factor
== 0))))
11270 /* Handle vector immediates. */
11273 RC_SAE_immediate (const char *imm_start
)
11275 unsigned int match_found
, j
;
11276 const char *pstr
= imm_start
;
11284 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11286 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11288 if (i
.rounding
.type
!= rc_none
)
11290 as_bad (_("duplicated `%s'"), imm_start
);
11294 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11295 i
.rounding
.operand
= this_operand
;
11297 pstr
+= RC_NamesTable
[j
].len
;
11305 if (*pstr
++ != '}')
11307 as_bad (_("Missing '}': '%s'"), imm_start
);
11310 /* RC/SAE immediate string should contain nothing more. */;
11313 as_bad (_("Junk after '}': '%s'"), imm_start
);
11317 exp
= &im_expressions
[i
.imm_operands
++];
11318 i
.op
[this_operand
].imms
= exp
;
11320 exp
->X_op
= O_constant
;
11321 exp
->X_add_number
= 0;
11322 exp
->X_add_symbol
= (symbolS
*) 0;
11323 exp
->X_op_symbol
= (symbolS
*) 0;
11325 i
.types
[this_operand
].bitfield
.imm8
= 1;
11329 /* Only string instructions can have a second memory operand, so
11330 reduce current_templates to just those if it contains any. */
11332 maybe_adjust_templates (void)
11334 const insn_template
*t
;
11336 gas_assert (i
.mem_operands
== 1);
11338 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11339 if (t
->opcode_modifier
.isstring
)
11342 if (t
< current_templates
->end
)
11344 static templates aux_templates
;
11347 aux_templates
.start
= t
;
11348 for (; t
< current_templates
->end
; ++t
)
11349 if (!t
->opcode_modifier
.isstring
)
11351 aux_templates
.end
= t
;
11353 /* Determine whether to re-check the first memory operand. */
11354 recheck
= (aux_templates
.start
!= current_templates
->start
11355 || t
!= current_templates
->end
);
11357 current_templates
= &aux_templates
;
11361 i
.mem_operands
= 0;
11362 if (i
.memop1_string
!= NULL
11363 && i386_index_check (i
.memop1_string
) == 0)
11365 i
.mem_operands
= 1;
11372 static INLINE
bool starts_memory_operand (char c
)
11375 || is_identifier_char (c
)
11376 || strchr ("([\"+-!~", c
);
11379 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11383 i386_att_operand (char *operand_string
)
11385 const reg_entry
*r
;
11387 char *op_string
= operand_string
;
11389 if (is_space_char (*op_string
))
11392 /* We check for an absolute prefix (differentiating,
11393 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11394 if (*op_string
== ABSOLUTE_PREFIX
)
11397 if (is_space_char (*op_string
))
11399 i
.jumpabsolute
= true;
11402 /* Check if operand is a register. */
11403 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11405 i386_operand_type temp
;
11410 /* Check for a segment override by searching for ':' after a
11411 segment register. */
11412 op_string
= end_op
;
11413 if (is_space_char (*op_string
))
11415 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11417 i
.seg
[i
.mem_operands
] = r
;
11419 /* Skip the ':' and whitespace. */
11421 if (is_space_char (*op_string
))
11424 /* Handle case of %es:*foo. */
11425 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
)
11428 if (is_space_char (*op_string
))
11430 i
.jumpabsolute
= true;
11433 if (!starts_memory_operand (*op_string
))
11435 as_bad (_("bad memory operand `%s'"), op_string
);
11438 goto do_memory_reference
;
11441 /* Handle vector operations. */
11442 if (*op_string
== '{')
11444 op_string
= check_VecOperations (op_string
);
11445 if (op_string
== NULL
)
11451 as_bad (_("junk `%s' after register"), op_string
);
11454 temp
= r
->reg_type
;
11455 temp
.bitfield
.baseindex
= 0;
11456 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11458 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11459 i
.op
[this_operand
].regs
= r
;
11462 else if (*op_string
== REGISTER_PREFIX
)
11464 as_bad (_("bad register name `%s'"), op_string
);
11467 else if (*op_string
== IMMEDIATE_PREFIX
)
11470 if (i
.jumpabsolute
)
11472 as_bad (_("immediate operand illegal with absolute jump"));
11475 if (!i386_immediate (op_string
))
11478 else if (RC_SAE_immediate (operand_string
))
11480 /* If it is a RC or SAE immediate, do nothing. */
11483 else if (starts_memory_operand (*op_string
))
11485 /* This is a memory reference of some sort. */
11488 /* Start and end of displacement string expression (if found). */
11489 char *displacement_string_start
;
11490 char *displacement_string_end
;
11492 do_memory_reference
:
11493 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11495 if ((i
.mem_operands
== 1
11496 && !current_templates
->start
->opcode_modifier
.isstring
)
11497 || i
.mem_operands
== 2)
11499 as_bad (_("too many memory references for `%s'"),
11500 current_templates
->start
->name
);
11504 /* Check for base index form. We detect the base index form by
11505 looking for an ')' at the end of the operand, searching
11506 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11508 base_string
= op_string
+ strlen (op_string
);
11510 /* Handle vector operations. */
11512 if (is_space_char (*base_string
))
11515 if (*base_string
== '}')
11517 char *vop_start
= NULL
;
11519 while (base_string
-- > op_string
)
11521 if (*base_string
== '"')
11523 if (*base_string
!= '{')
11526 vop_start
= base_string
;
11529 if (is_space_char (*base_string
))
11532 if (*base_string
!= '}')
11540 as_bad (_("unbalanced figure braces"));
11544 if (check_VecOperations (vop_start
) == NULL
)
11548 /* If we only have a displacement, set-up for it to be parsed later. */
11549 displacement_string_start
= op_string
;
11550 displacement_string_end
= base_string
+ 1;
11552 if (*base_string
== ')')
11556 /* We've already checked that the number of left & right ()'s are
11557 equal, so this loop will not be infinite. */
11562 while (*base_string
!= '(' && *base_string
!= ')'
11563 && *base_string
!= '"');
11565 temp_string
= base_string
;
11567 /* Skip past '(' and whitespace. */
11568 if (*base_string
== '(')
11570 if (is_space_char (*base_string
))
11573 if (*base_string
== ','
11574 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11577 displacement_string_end
= temp_string
;
11579 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11583 if (i
.base_reg
== &bad_reg
)
11585 base_string
= end_op
;
11586 if (is_space_char (*base_string
))
11590 /* There may be an index reg or scale factor here. */
11591 if (*base_string
== ',')
11594 if (is_space_char (*base_string
))
11597 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11600 if (i
.index_reg
== &bad_reg
)
11602 base_string
= end_op
;
11603 if (is_space_char (*base_string
))
11605 if (*base_string
== ',')
11608 if (is_space_char (*base_string
))
11611 else if (*base_string
!= ')')
11613 as_bad (_("expecting `,' or `)' "
11614 "after index register in `%s'"),
11619 else if (*base_string
== REGISTER_PREFIX
)
11621 end_op
= strchr (base_string
, ',');
11624 as_bad (_("bad register name `%s'"), base_string
);
11628 /* Check for scale factor. */
11629 if (*base_string
!= ')')
11631 char *end_scale
= i386_scale (base_string
);
11636 base_string
= end_scale
;
11637 if (is_space_char (*base_string
))
11639 if (*base_string
!= ')')
11641 as_bad (_("expecting `)' "
11642 "after scale factor in `%s'"),
11647 else if (!i
.index_reg
)
11649 as_bad (_("expecting index register or scale factor "
11650 "after `,'; got '%c'"),
11655 else if (*base_string
!= ')')
11657 as_bad (_("expecting `,' or `)' "
11658 "after base register in `%s'"),
11663 else if (*base_string
== REGISTER_PREFIX
)
11665 end_op
= strchr (base_string
, ',');
11668 as_bad (_("bad register name `%s'"), base_string
);
11673 /* If there's an expression beginning the operand, parse it,
11674 assuming displacement_string_start and
11675 displacement_string_end are meaningful. */
11676 if (displacement_string_start
!= displacement_string_end
)
11678 if (!i386_displacement (displacement_string_start
,
11679 displacement_string_end
))
11683 /* Special case for (%dx) while doing input/output op. */
11685 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11686 && i
.base_reg
->reg_type
.bitfield
.word
11687 && i
.index_reg
== 0
11688 && i
.log2_scale_factor
== 0
11689 && i
.seg
[i
.mem_operands
] == 0
11690 && !operand_type_check (i
.types
[this_operand
], disp
))
11692 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11696 if (i386_index_check (operand_string
) == 0)
11698 i
.flags
[this_operand
] |= Operand_Mem
;
11699 if (i
.mem_operands
== 0)
11700 i
.memop1_string
= xstrdup (operand_string
);
11705 /* It's not a memory operand; argh! */
11706 as_bad (_("invalid char %s beginning operand %d `%s'"),
11707 output_invalid (*op_string
),
11712 return 1; /* Normal return. */
11715 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11716 that an rs_machine_dependent frag may reach. */
11719 i386_frag_max_var (fragS
*frag
)
11721 /* The only relaxable frags are for jumps.
11722 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11723 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11724 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11727 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11729 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11731 /* STT_GNU_IFUNC symbol must go through PLT. */
11732 if ((symbol_get_bfdsym (fr_symbol
)->flags
11733 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11736 if (!S_IS_EXTERNAL (fr_symbol
))
11737 /* Symbol may be weak or local. */
11738 return !S_IS_WEAK (fr_symbol
);
11740 /* Global symbols with non-default visibility can't be preempted. */
11741 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11744 if (fr_var
!= NO_RELOC
)
11745 switch ((enum bfd_reloc_code_real
) fr_var
)
11747 case BFD_RELOC_386_PLT32
:
11748 case BFD_RELOC_X86_64_PLT32
:
11749 /* Symbol with PLT relocation may be preempted. */
11755 /* Global symbols with default visibility in a shared library may be
11756 preempted by another definition. */
11761 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11762 Note also work for Skylake and Cascadelake.
11763 ---------------------------------------------------------------------
11764 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11765 | ------ | ----------- | ------- | -------- |
11767 | Jno | N | N | Y |
11768 | Jc/Jb | Y | N | Y |
11769 | Jae/Jnb | Y | N | Y |
11770 | Je/Jz | Y | Y | Y |
11771 | Jne/Jnz | Y | Y | Y |
11772 | Jna/Jbe | Y | N | Y |
11773 | Ja/Jnbe | Y | N | Y |
11775 | Jns | N | N | Y |
11776 | Jp/Jpe | N | N | Y |
11777 | Jnp/Jpo | N | N | Y |
11778 | Jl/Jnge | Y | Y | Y |
11779 | Jge/Jnl | Y | Y | Y |
11780 | Jle/Jng | Y | Y | Y |
11781 | Jg/Jnle | Y | Y | Y |
11782 --------------------------------------------------------------------- */
11784 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11786 if (mf_cmp
== mf_cmp_alu_cmp
)
11787 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11788 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11789 if (mf_cmp
== mf_cmp_incdec
)
11790 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11791 || mf_jcc
== mf_jcc_jle
);
11792 if (mf_cmp
== mf_cmp_test_and
)
11797 /* Return the next non-empty frag. */
11800 i386_next_non_empty_frag (fragS
*fragP
)
11802 /* There may be a frag with a ".fill 0" when there is no room in
11803 the current frag for frag_grow in output_insn. */
11804 for (fragP
= fragP
->fr_next
;
11806 && fragP
->fr_type
== rs_fill
11807 && fragP
->fr_fix
== 0);
11808 fragP
= fragP
->fr_next
)
11813 /* Return the next jcc frag after BRANCH_PADDING. */
11816 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11818 fragS
*branch_fragP
;
11822 if (pad_fragP
->fr_type
== rs_machine_dependent
11823 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11824 == BRANCH_PADDING
))
11826 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11827 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11829 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11830 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11831 pad_fragP
->tc_frag_data
.mf_type
))
11832 return branch_fragP
;
11838 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11841 i386_classify_machine_dependent_frag (fragS
*fragP
)
11845 fragS
*branch_fragP
;
11847 unsigned int max_prefix_length
;
11849 if (fragP
->tc_frag_data
.classified
)
11852 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11853 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11854 for (next_fragP
= fragP
;
11855 next_fragP
!= NULL
;
11856 next_fragP
= next_fragP
->fr_next
)
11858 next_fragP
->tc_frag_data
.classified
= 1;
11859 if (next_fragP
->fr_type
== rs_machine_dependent
)
11860 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11862 case BRANCH_PADDING
:
11863 /* The BRANCH_PADDING frag must be followed by a branch
11865 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11866 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11868 case FUSED_JCC_PADDING
:
11869 /* Check if this is a fused jcc:
11871 CMP like instruction
11875 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11876 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11877 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11880 /* The BRANCH_PADDING frag is merged with the
11881 FUSED_JCC_PADDING frag. */
11882 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11883 /* CMP like instruction size. */
11884 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11885 frag_wane (pad_fragP
);
11886 /* Skip to branch_fragP. */
11887 next_fragP
= branch_fragP
;
11889 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11891 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11893 next_fragP
->fr_subtype
11894 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11895 next_fragP
->tc_frag_data
.max_bytes
11896 = next_fragP
->tc_frag_data
.max_prefix_length
;
11897 /* This will be updated in the BRANCH_PREFIX scan. */
11898 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11901 frag_wane (next_fragP
);
11906 /* Stop if there is no BRANCH_PREFIX. */
11907 if (!align_branch_prefix_size
)
11910 /* Scan for BRANCH_PREFIX. */
11911 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11913 if (fragP
->fr_type
!= rs_machine_dependent
11914 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11918 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11919 COND_JUMP_PREFIX. */
11920 max_prefix_length
= 0;
11921 for (next_fragP
= fragP
;
11922 next_fragP
!= NULL
;
11923 next_fragP
= next_fragP
->fr_next
)
11925 if (next_fragP
->fr_type
== rs_fill
)
11926 /* Skip rs_fill frags. */
11928 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11929 /* Stop for all other frags. */
11932 /* rs_machine_dependent frags. */
11933 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11936 /* Count BRANCH_PREFIX frags. */
11937 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11939 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11940 frag_wane (next_fragP
);
11944 += next_fragP
->tc_frag_data
.max_bytes
;
11946 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11948 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11949 == FUSED_JCC_PADDING
))
11951 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11952 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11956 /* Stop for other rs_machine_dependent frags. */
11960 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11962 /* Skip to the next frag. */
11963 fragP
= next_fragP
;
11967 /* Compute padding size for
11970 CMP like instruction
11972 COND_JUMP/UNCOND_JUMP
11977 COND_JUMP/UNCOND_JUMP
11981 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11983 unsigned int offset
, size
, padding_size
;
11984 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11986 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11988 address
= fragP
->fr_address
;
11989 address
+= fragP
->fr_fix
;
11991 /* CMP like instrunction size. */
11992 size
= fragP
->tc_frag_data
.cmp_size
;
11994 /* The base size of the branch frag. */
11995 size
+= branch_fragP
->fr_fix
;
11997 /* Add opcode and displacement bytes for the rs_machine_dependent
11999 if (branch_fragP
->fr_type
== rs_machine_dependent
)
12000 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
12002 /* Check if branch is within boundary and doesn't end at the last
12004 offset
= address
& ((1U << align_branch_power
) - 1);
12005 if ((offset
+ size
) >= (1U << align_branch_power
))
12006 /* Padding needed to avoid crossing boundary. */
12007 padding_size
= (1U << align_branch_power
) - offset
;
12009 /* No padding needed. */
12012 /* The return value may be saved in tc_frag_data.length which is
12014 if (!fits_in_unsigned_byte (padding_size
))
12017 return padding_size
;
12020 /* i386_generic_table_relax_frag()
12022 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
12023 grow/shrink padding to align branch frags. Hand others to
12027 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
12029 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12030 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12032 long padding_size
= i386_branch_padding_size (fragP
, 0);
12033 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
12035 /* When the BRANCH_PREFIX frag is used, the computed address
12036 must match the actual address and there should be no padding. */
12037 if (fragP
->tc_frag_data
.padding_address
12038 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
12042 /* Update the padding size. */
12044 fragP
->tc_frag_data
.length
= padding_size
;
12048 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12050 fragS
*padding_fragP
, *next_fragP
;
12051 long padding_size
, left_size
, last_size
;
12053 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12054 if (!padding_fragP
)
12055 /* Use the padding set by the leading BRANCH_PREFIX frag. */
12056 return (fragP
->tc_frag_data
.length
12057 - fragP
->tc_frag_data
.last_length
);
12059 /* Compute the relative address of the padding frag in the very
12060 first time where the BRANCH_PREFIX frag sizes are zero. */
12061 if (!fragP
->tc_frag_data
.padding_address
)
12062 fragP
->tc_frag_data
.padding_address
12063 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
12065 /* First update the last length from the previous interation. */
12066 left_size
= fragP
->tc_frag_data
.prefix_length
;
12067 for (next_fragP
= fragP
;
12068 next_fragP
!= padding_fragP
;
12069 next_fragP
= next_fragP
->fr_next
)
12070 if (next_fragP
->fr_type
== rs_machine_dependent
12071 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12076 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12080 if (max
> left_size
)
12085 next_fragP
->tc_frag_data
.last_length
= size
;
12089 next_fragP
->tc_frag_data
.last_length
= 0;
12092 /* Check the padding size for the padding frag. */
12093 padding_size
= i386_branch_padding_size
12094 (padding_fragP
, (fragP
->fr_address
12095 + fragP
->tc_frag_data
.padding_address
));
12097 last_size
= fragP
->tc_frag_data
.prefix_length
;
12098 /* Check if there is change from the last interation. */
12099 if (padding_size
== last_size
)
12101 /* Update the expected address of the padding frag. */
12102 padding_fragP
->tc_frag_data
.padding_address
12103 = (fragP
->fr_address
+ padding_size
12104 + fragP
->tc_frag_data
.padding_address
);
12108 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
12110 /* No padding if there is no sufficient room. Clear the
12111 expected address of the padding frag. */
12112 padding_fragP
->tc_frag_data
.padding_address
= 0;
12116 /* Store the expected address of the padding frag. */
12117 padding_fragP
->tc_frag_data
.padding_address
12118 = (fragP
->fr_address
+ padding_size
12119 + fragP
->tc_frag_data
.padding_address
);
12121 fragP
->tc_frag_data
.prefix_length
= padding_size
;
12123 /* Update the length for the current interation. */
12124 left_size
= padding_size
;
12125 for (next_fragP
= fragP
;
12126 next_fragP
!= padding_fragP
;
12127 next_fragP
= next_fragP
->fr_next
)
12128 if (next_fragP
->fr_type
== rs_machine_dependent
12129 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12134 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12138 if (max
> left_size
)
12143 next_fragP
->tc_frag_data
.length
= size
;
12147 next_fragP
->tc_frag_data
.length
= 0;
12150 return (fragP
->tc_frag_data
.length
12151 - fragP
->tc_frag_data
.last_length
);
12153 return relax_frag (segment
, fragP
, stretch
);
12156 /* md_estimate_size_before_relax()
12158 Called just before relax() for rs_machine_dependent frags. The x86
12159 assembler uses these frags to handle variable size jump
12162 Any symbol that is now undefined will not become defined.
12163 Return the correct fr_subtype in the frag.
12164 Return the initial "guess for variable size of frag" to caller.
12165 The guess is actually the growth beyond the fixed part. Whatever
12166 we do to grow the fixed or variable part contributes to our
12170 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12172 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12173 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12174 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12176 i386_classify_machine_dependent_frag (fragP
);
12177 return fragP
->tc_frag_data
.length
;
12180 /* We've already got fragP->fr_subtype right; all we have to do is
12181 check for un-relaxable symbols. On an ELF system, we can't relax
12182 an externally visible symbol, because it may be overridden by a
12184 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12187 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12190 #if defined (OBJ_COFF) && defined (TE_PE)
12191 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12192 && S_IS_WEAK (fragP
->fr_symbol
))
12196 /* Symbol is undefined in this segment, or we need to keep a
12197 reloc so that weak symbols can be overridden. */
12198 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12199 enum bfd_reloc_code_real reloc_type
;
12200 unsigned char *opcode
;
12204 if (fragP
->fr_var
!= NO_RELOC
)
12205 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12206 else if (size
== 2)
12207 reloc_type
= BFD_RELOC_16_PCREL
;
12208 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12209 else if (need_plt32_p (fragP
->fr_symbol
))
12210 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12213 reloc_type
= BFD_RELOC_32_PCREL
;
12215 old_fr_fix
= fragP
->fr_fix
;
12216 opcode
= (unsigned char *) fragP
->fr_opcode
;
12218 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12221 /* Make jmp (0xeb) a (d)word displacement jump. */
12223 fragP
->fr_fix
+= size
;
12224 fixP
= fix_new (fragP
, old_fr_fix
, size
,
12226 fragP
->fr_offset
, 1,
12232 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12234 /* Negate the condition, and branch past an
12235 unconditional jump. */
12238 /* Insert an unconditional jump. */
12240 /* We added two extra opcode bytes, and have a two byte
12242 fragP
->fr_fix
+= 2 + 2;
12243 fix_new (fragP
, old_fr_fix
+ 2, 2,
12245 fragP
->fr_offset
, 1,
12249 /* Fall through. */
12252 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12254 fragP
->fr_fix
+= 1;
12255 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12257 fragP
->fr_offset
, 1,
12258 BFD_RELOC_8_PCREL
);
12259 fixP
->fx_signed
= 1;
12263 /* This changes the byte-displacement jump 0x7N
12264 to the (d)word-displacement jump 0x0f,0x8N. */
12265 opcode
[1] = opcode
[0] + 0x10;
12266 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12267 /* We've added an opcode byte. */
12268 fragP
->fr_fix
+= 1 + size
;
12269 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
12271 fragP
->fr_offset
, 1,
12276 BAD_CASE (fragP
->fr_subtype
);
12280 /* All jumps handled here are signed, but don't unconditionally use a
12281 signed limit check for 32 and 16 bit jumps as we want to allow wrap
12282 around at 4G (outside of 64-bit mode) and 64k. */
12283 if (size
== 4 && flag_code
== CODE_64BIT
)
12284 fixP
->fx_signed
= 1;
12287 return fragP
->fr_fix
- old_fr_fix
;
12290 /* Guess size depending on current relax state. Initially the relax
12291 state will correspond to a short jump and we return 1, because
12292 the variable part of the frag (the branch offset) is one byte
12293 long. However, we can relax a section more than once and in that
12294 case we must either set fr_subtype back to the unrelaxed state,
12295 or return the value for the appropriate branch. */
12296 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12299 /* Called after relax() is finished.
12301 In: Address of frag.
12302 fr_type == rs_machine_dependent.
12303 fr_subtype is what the address relaxed to.
12305 Out: Any fixSs and constants are set up.
12306 Caller will turn frag into a ".space 0". */
12309 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12312 unsigned char *opcode
;
12313 unsigned char *where_to_put_displacement
= NULL
;
12314 offsetT target_address
;
12315 offsetT opcode_address
;
12316 unsigned int extension
= 0;
12317 offsetT displacement_from_opcode_start
;
12319 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12320 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12321 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12323 /* Generate nop padding. */
12324 unsigned int size
= fragP
->tc_frag_data
.length
;
12327 if (size
> fragP
->tc_frag_data
.max_bytes
)
12333 const char *branch
= "branch";
12334 const char *prefix
= "";
12335 fragS
*padding_fragP
;
12336 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12339 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12340 switch (fragP
->tc_frag_data
.default_prefix
)
12345 case CS_PREFIX_OPCODE
:
12348 case DS_PREFIX_OPCODE
:
12351 case ES_PREFIX_OPCODE
:
12354 case FS_PREFIX_OPCODE
:
12357 case GS_PREFIX_OPCODE
:
12360 case SS_PREFIX_OPCODE
:
12365 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12366 "%s within %d-byte boundary\n");
12368 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12369 "align %s within %d-byte boundary\n");
12373 padding_fragP
= fragP
;
12374 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12375 "%s within %d-byte boundary\n");
12379 switch (padding_fragP
->tc_frag_data
.branch_type
)
12381 case align_branch_jcc
:
12384 case align_branch_fused
:
12385 branch
= "fused jcc";
12387 case align_branch_jmp
:
12390 case align_branch_call
:
12393 case align_branch_indirect
:
12394 branch
= "indiret branch";
12396 case align_branch_ret
:
12403 fprintf (stdout
, msg
,
12404 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12405 (long long) fragP
->fr_address
, branch
,
12406 1 << align_branch_power
);
12408 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12409 memset (fragP
->fr_opcode
,
12410 fragP
->tc_frag_data
.default_prefix
, size
);
12412 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12414 fragP
->fr_fix
+= size
;
12419 opcode
= (unsigned char *) fragP
->fr_opcode
;
12421 /* Address we want to reach in file space. */
12422 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12424 /* Address opcode resides at in file space. */
12425 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12427 /* Displacement from opcode start to fill into instruction. */
12428 displacement_from_opcode_start
= target_address
- opcode_address
;
12430 if ((fragP
->fr_subtype
& BIG
) == 0)
12432 /* Don't have to change opcode. */
12433 extension
= 1; /* 1 opcode + 1 displacement */
12434 where_to_put_displacement
= &opcode
[1];
12438 if (no_cond_jump_promotion
12439 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12440 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12441 _("long jump required"));
12443 switch (fragP
->fr_subtype
)
12445 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12446 extension
= 4; /* 1 opcode + 4 displacement */
12448 where_to_put_displacement
= &opcode
[1];
12451 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12452 extension
= 2; /* 1 opcode + 2 displacement */
12454 where_to_put_displacement
= &opcode
[1];
12457 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12458 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12459 extension
= 5; /* 2 opcode + 4 displacement */
12460 opcode
[1] = opcode
[0] + 0x10;
12461 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12462 where_to_put_displacement
= &opcode
[2];
12465 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12466 extension
= 3; /* 2 opcode + 2 displacement */
12467 opcode
[1] = opcode
[0] + 0x10;
12468 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12469 where_to_put_displacement
= &opcode
[2];
12472 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12477 where_to_put_displacement
= &opcode
[3];
12481 BAD_CASE (fragP
->fr_subtype
);
12486 /* If size if less then four we are sure that the operand fits,
12487 but if it's 4, then it could be that the displacement is larger
12489 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12491 && ((addressT
) (displacement_from_opcode_start
- extension
12492 + ((addressT
) 1 << 31))
12493 > (((addressT
) 2 << 31) - 1)))
12495 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12496 _("jump target out of range"));
12497 /* Make us emit 0. */
12498 displacement_from_opcode_start
= extension
;
12500 /* Now put displacement after opcode. */
12501 md_number_to_chars ((char *) where_to_put_displacement
,
12502 (valueT
) (displacement_from_opcode_start
- extension
),
12503 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12504 fragP
->fr_fix
+= extension
;
12507 /* Apply a fixup (fixP) to segment data, once it has been determined
12508 by our caller that we have all the info we need to fix it up.
12510 Parameter valP is the pointer to the value of the bits.
12512 On the 386, immediates, displacements, and data pointers are all in
12513 the same (little-endian) format, so we don't need to care about which
12514 we are handling. */
12517 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12519 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12520 valueT value
= *valP
;
12522 #if !defined (TE_Mach)
12523 if (fixP
->fx_pcrel
)
12525 switch (fixP
->fx_r_type
)
12531 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12534 case BFD_RELOC_X86_64_32S
:
12535 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12538 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12541 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12546 if (fixP
->fx_addsy
!= NULL
12547 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12548 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12549 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12550 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12551 && !use_rela_relocations
)
12553 /* This is a hack. There should be a better way to handle this.
12554 This covers for the fact that bfd_install_relocation will
12555 subtract the current location (for partial_inplace, PC relative
12556 relocations); see more below. */
12560 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12563 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12565 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12568 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12570 if ((sym_seg
== seg
12571 || (symbol_section_p (fixP
->fx_addsy
)
12572 && sym_seg
!= absolute_section
))
12573 && !generic_force_reloc (fixP
))
12575 /* Yes, we add the values in twice. This is because
12576 bfd_install_relocation subtracts them out again. I think
12577 bfd_install_relocation is broken, but I don't dare change
12579 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12583 #if defined (OBJ_COFF) && defined (TE_PE)
12584 /* For some reason, the PE format does not store a
12585 section address offset for a PC relative symbol. */
12586 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12587 || S_IS_WEAK (fixP
->fx_addsy
))
12588 value
+= md_pcrel_from (fixP
);
12591 #if defined (OBJ_COFF) && defined (TE_PE)
12592 if (fixP
->fx_addsy
!= NULL
12593 && S_IS_WEAK (fixP
->fx_addsy
)
12594 /* PR 16858: Do not modify weak function references. */
12595 && ! fixP
->fx_pcrel
)
12597 #if !defined (TE_PEP)
12598 /* For x86 PE weak function symbols are neither PC-relative
12599 nor do they set S_IS_FUNCTION. So the only reliable way
12600 to detect them is to check the flags of their containing
12602 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12603 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12607 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12611 /* Fix a few things - the dynamic linker expects certain values here,
12612 and we must not disappoint it. */
12613 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12614 if (IS_ELF
&& fixP
->fx_addsy
)
12615 switch (fixP
->fx_r_type
)
12617 case BFD_RELOC_386_PLT32
:
12618 case BFD_RELOC_X86_64_PLT32
:
12619 /* Make the jump instruction point to the address of the operand.
12620 At runtime we merely add the offset to the actual PLT entry.
12621 NB: Subtract the offset size only for jump instructions. */
12622 if (fixP
->fx_pcrel
)
12626 case BFD_RELOC_386_TLS_GD
:
12627 case BFD_RELOC_386_TLS_LDM
:
12628 case BFD_RELOC_386_TLS_IE_32
:
12629 case BFD_RELOC_386_TLS_IE
:
12630 case BFD_RELOC_386_TLS_GOTIE
:
12631 case BFD_RELOC_386_TLS_GOTDESC
:
12632 case BFD_RELOC_X86_64_TLSGD
:
12633 case BFD_RELOC_X86_64_TLSLD
:
12634 case BFD_RELOC_X86_64_GOTTPOFF
:
12635 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12636 value
= 0; /* Fully resolved at runtime. No addend. */
12638 case BFD_RELOC_386_TLS_LE
:
12639 case BFD_RELOC_386_TLS_LDO_32
:
12640 case BFD_RELOC_386_TLS_LE_32
:
12641 case BFD_RELOC_X86_64_DTPOFF32
:
12642 case BFD_RELOC_X86_64_DTPOFF64
:
12643 case BFD_RELOC_X86_64_TPOFF32
:
12644 case BFD_RELOC_X86_64_TPOFF64
:
12645 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12648 case BFD_RELOC_386_TLS_DESC_CALL
:
12649 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12650 value
= 0; /* Fully resolved at runtime. No addend. */
12651 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12655 case BFD_RELOC_VTABLE_INHERIT
:
12656 case BFD_RELOC_VTABLE_ENTRY
:
12663 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12665 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
12667 value
= extend_to_32bit_address (value
);
12670 #endif /* !defined (TE_Mach) */
12672 /* Are we finished with this relocation now? */
12673 if (fixP
->fx_addsy
== NULL
)
12676 switch (fixP
->fx_r_type
)
12678 case BFD_RELOC_X86_64_32S
:
12679 fixP
->fx_signed
= 1;
12686 #if defined (OBJ_COFF) && defined (TE_PE)
12687 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12690 /* Remember value for tc_gen_reloc. */
12691 fixP
->fx_addnumber
= value
;
12692 /* Clear out the frag for now. */
12696 else if (use_rela_relocations
)
12698 fixP
->fx_no_overflow
= 1;
12699 /* Remember value for tc_gen_reloc. */
12700 fixP
->fx_addnumber
= value
;
12704 md_number_to_chars (p
, value
, fixP
->fx_size
);
12708 md_atof (int type
, char *litP
, int *sizeP
)
12710 /* This outputs the LITTLENUMs in REVERSE order;
12711 in accord with the bigendian 386. */
12712 return ieee_md_atof (type
, litP
, sizeP
, false);
12715 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12718 output_invalid (int c
)
12721 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12724 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12725 "(0x%x)", (unsigned char) c
);
12726 return output_invalid_buf
;
12729 /* Verify that @r can be used in the current context. */
12731 static bool check_register (const reg_entry
*r
)
12733 if (allow_pseudo_reg
)
12736 if (operand_type_all_zero (&r
->reg_type
))
12739 if ((r
->reg_type
.bitfield
.dword
12740 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12741 || r
->reg_type
.bitfield
.class == RegCR
12742 || r
->reg_type
.bitfield
.class == RegDR
)
12743 && !cpu_arch_flags
.bitfield
.cpui386
)
12746 if (r
->reg_type
.bitfield
.class == RegTR
12747 && (flag_code
== CODE_64BIT
12748 || !cpu_arch_flags
.bitfield
.cpui386
12749 || cpu_arch_isa_flags
.bitfield
.cpui586
12750 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12753 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12756 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12758 if (r
->reg_type
.bitfield
.zmmword
12759 || r
->reg_type
.bitfield
.class == RegMask
)
12762 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12764 if (r
->reg_type
.bitfield
.ymmword
)
12767 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12772 if (r
->reg_type
.bitfield
.tmmword
12773 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12774 || flag_code
!= CODE_64BIT
))
12777 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12780 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12781 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12784 /* Upper 16 vector registers are only available with VREX in 64bit
12785 mode, and require EVEX encoding. */
12786 if (r
->reg_flags
& RegVRex
)
12788 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12789 || flag_code
!= CODE_64BIT
)
12792 if (i
.vec_encoding
== vex_encoding_default
)
12793 i
.vec_encoding
= vex_encoding_evex
;
12794 else if (i
.vec_encoding
!= vex_encoding_evex
)
12795 i
.vec_encoding
= vex_encoding_error
;
12798 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12799 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12800 && flag_code
!= CODE_64BIT
)
12803 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12810 /* REG_STRING starts *before* REGISTER_PREFIX. */
12812 static const reg_entry
*
12813 parse_real_register (char *reg_string
, char **end_op
)
12815 char *s
= reg_string
;
12817 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12818 const reg_entry
*r
;
12820 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12821 if (*s
== REGISTER_PREFIX
)
12824 if (is_space_char (*s
))
12827 p
= reg_name_given
;
12828 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12830 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12831 return (const reg_entry
*) NULL
;
12835 /* For naked regs, make sure that we are not dealing with an identifier.
12836 This prevents confusing an identifier like `eax_var' with register
12838 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12839 return (const reg_entry
*) NULL
;
12843 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12845 /* Handle floating point regs, allowing spaces in the (i) part. */
12848 if (!cpu_arch_flags
.bitfield
.cpu8087
12849 && !cpu_arch_flags
.bitfield
.cpu287
12850 && !cpu_arch_flags
.bitfield
.cpu387
12851 && !allow_pseudo_reg
)
12852 return (const reg_entry
*) NULL
;
12854 if (is_space_char (*s
))
12859 if (is_space_char (*s
))
12861 if (*s
>= '0' && *s
<= '7')
12863 int fpr
= *s
- '0';
12865 if (is_space_char (*s
))
12870 know (r
[fpr
].reg_num
== fpr
);
12874 /* We have "%st(" then garbage. */
12875 return (const reg_entry
*) NULL
;
12879 return r
&& check_register (r
) ? r
: NULL
;
12882 /* REG_STRING starts *before* REGISTER_PREFIX. */
12884 static const reg_entry
*
12885 parse_register (char *reg_string
, char **end_op
)
12887 const reg_entry
*r
;
12889 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12890 r
= parse_real_register (reg_string
, end_op
);
12895 char *save
= input_line_pointer
;
12899 input_line_pointer
= reg_string
;
12900 c
= get_symbol_name (®_string
);
12901 symbolP
= symbol_find (reg_string
);
12902 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12904 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12906 know (e
->X_op
== O_register
);
12907 know (e
->X_add_number
>= 0
12908 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12909 r
= i386_regtab
+ e
->X_add_number
;
12910 if (!check_register (r
))
12912 as_bad (_("register '%s%s' cannot be used here"),
12913 register_prefix
, r
->reg_name
);
12916 *end_op
= input_line_pointer
;
12918 *input_line_pointer
= c
;
12919 input_line_pointer
= save
;
12925 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12927 const reg_entry
*r
;
12928 char *end
= input_line_pointer
;
12931 r
= parse_register (name
, &input_line_pointer
);
12932 if (r
&& end
<= input_line_pointer
)
12934 *nextcharP
= *input_line_pointer
;
12935 *input_line_pointer
= 0;
12938 e
->X_op
= O_register
;
12939 e
->X_add_number
= r
- i386_regtab
;
12942 e
->X_op
= O_illegal
;
12945 input_line_pointer
= end
;
12947 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12951 md_operand (expressionS
*e
)
12954 const reg_entry
*r
;
12956 switch (*input_line_pointer
)
12958 case REGISTER_PREFIX
:
12959 r
= parse_real_register (input_line_pointer
, &end
);
12962 e
->X_op
= O_register
;
12963 e
->X_add_number
= r
- i386_regtab
;
12964 input_line_pointer
= end
;
12969 gas_assert (intel_syntax
);
12970 end
= input_line_pointer
++;
12972 if (*input_line_pointer
== ']')
12974 ++input_line_pointer
;
12975 e
->X_op_symbol
= make_expr_symbol (e
);
12976 e
->X_add_symbol
= NULL
;
12977 e
->X_add_number
= 0;
12982 e
->X_op
= O_absent
;
12983 input_line_pointer
= end
;
12990 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12991 const char *md_shortopts
= "kVQ:sqnO::";
12993 const char *md_shortopts
= "qnO::";
12996 #define OPTION_32 (OPTION_MD_BASE + 0)
12997 #define OPTION_64 (OPTION_MD_BASE + 1)
12998 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12999 #define OPTION_MARCH (OPTION_MD_BASE + 3)
13000 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
13001 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
13002 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
13003 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
13004 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
13005 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
13006 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
13007 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
13008 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
13009 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
13010 #define OPTION_X32 (OPTION_MD_BASE + 14)
13011 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
13012 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
13013 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
13014 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
13015 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
13016 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
13017 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
13018 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
13019 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
13020 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
13021 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
13022 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
13023 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
13024 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
13025 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
13026 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
13027 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
13028 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
13029 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
13031 struct option md_longopts
[] =
13033 {"32", no_argument
, NULL
, OPTION_32
},
13034 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13035 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13036 {"64", no_argument
, NULL
, OPTION_64
},
13038 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13039 {"x32", no_argument
, NULL
, OPTION_X32
},
13040 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
13041 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
13043 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
13044 {"march", required_argument
, NULL
, OPTION_MARCH
},
13045 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
13046 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
13047 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
13048 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
13049 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
13050 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
13051 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
13052 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
13053 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
13054 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
13055 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
13056 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
13057 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
13058 # if defined (TE_PE) || defined (TE_PEP)
13059 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
13061 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
13062 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
13063 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
13064 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
13065 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
13066 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
13067 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
13068 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
13069 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
13070 {"mlfence-before-indirect-branch", required_argument
, NULL
,
13071 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
13072 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
13073 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
13074 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
13075 {NULL
, no_argument
, NULL
, 0}
13077 size_t md_longopts_size
= sizeof (md_longopts
);
13080 md_parse_option (int c
, const char *arg
)
13083 char *arch
, *next
, *saved
, *type
;
13088 optimize_align_code
= 0;
13092 quiet_warnings
= 1;
13095 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13096 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
13097 should be emitted or not. FIXME: Not implemented. */
13099 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
13103 /* -V: SVR4 argument to print version ID. */
13105 print_version_id ();
13108 /* -k: Ignore for FreeBSD compatibility. */
13113 /* -s: On i386 Solaris, this tells the native assembler to use
13114 .stab instead of .stab.excl. We always use .stab anyhow. */
13117 case OPTION_MSHARED
:
13121 case OPTION_X86_USED_NOTE
:
13122 if (strcasecmp (arg
, "yes") == 0)
13124 else if (strcasecmp (arg
, "no") == 0)
13127 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
13132 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13133 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13136 const char **list
, **l
;
13138 list
= bfd_target_list ();
13139 for (l
= list
; *l
!= NULL
; l
++)
13140 if (startswith (*l
, "elf64-x86-64")
13141 || strcmp (*l
, "coff-x86-64") == 0
13142 || strcmp (*l
, "pe-x86-64") == 0
13143 || strcmp (*l
, "pei-x86-64") == 0
13144 || strcmp (*l
, "mach-o-x86-64") == 0)
13146 default_arch
= "x86_64";
13150 as_fatal (_("no compiled in support for x86_64"));
13156 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13160 const char **list
, **l
;
13162 list
= bfd_target_list ();
13163 for (l
= list
; *l
!= NULL
; l
++)
13164 if (startswith (*l
, "elf32-x86-64"))
13166 default_arch
= "x86_64:32";
13170 as_fatal (_("no compiled in support for 32bit x86_64"));
13174 as_fatal (_("32bit x86_64 is only supported for ELF"));
13179 default_arch
= "i386";
13182 case OPTION_DIVIDE
:
13183 #ifdef SVR4_COMMENT_CHARS
13188 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13190 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13194 i386_comment_chars
= n
;
13200 saved
= xstrdup (arg
);
13202 /* Allow -march=+nosse. */
13208 as_fatal (_("invalid -march= option: `%s'"), arg
);
13209 next
= strchr (arch
, '+');
13212 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13214 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13217 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13220 cpu_arch_name
= cpu_arch
[j
].name
;
13221 cpu_sub_arch_name
= NULL
;
13222 cpu_arch_flags
= cpu_arch
[j
].flags
;
13223 cpu_arch_isa
= cpu_arch
[j
].type
;
13224 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13225 if (!cpu_arch_tune_set
)
13227 cpu_arch_tune
= cpu_arch_isa
;
13228 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13232 else if (*cpu_arch
[j
].name
== '.'
13233 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13235 /* ISA extension. */
13236 i386_cpu_flags flags
;
13238 flags
= cpu_flags_or (cpu_arch_flags
,
13239 cpu_arch
[j
].flags
);
13241 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13243 if (cpu_sub_arch_name
)
13245 char *name
= cpu_sub_arch_name
;
13246 cpu_sub_arch_name
= concat (name
,
13248 (const char *) NULL
);
13252 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13253 cpu_arch_flags
= flags
;
13254 cpu_arch_isa_flags
= flags
;
13258 = cpu_flags_or (cpu_arch_isa_flags
,
13259 cpu_arch
[j
].flags
);
13264 if (j
>= ARRAY_SIZE (cpu_arch
))
13266 /* Disable an ISA extension. */
13267 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13268 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13270 i386_cpu_flags flags
;
13272 flags
= cpu_flags_and_not (cpu_arch_flags
,
13273 cpu_noarch
[j
].flags
);
13274 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13276 if (cpu_sub_arch_name
)
13278 char *name
= cpu_sub_arch_name
;
13279 cpu_sub_arch_name
= concat (arch
,
13280 (const char *) NULL
);
13284 cpu_sub_arch_name
= xstrdup (arch
);
13285 cpu_arch_flags
= flags
;
13286 cpu_arch_isa_flags
= flags
;
13291 if (j
>= ARRAY_SIZE (cpu_noarch
))
13292 j
= ARRAY_SIZE (cpu_arch
);
13295 if (j
>= ARRAY_SIZE (cpu_arch
))
13296 as_fatal (_("invalid -march= option: `%s'"), arg
);
13300 while (next
!= NULL
);
13306 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13307 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13309 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13311 cpu_arch_tune_set
= 1;
13312 cpu_arch_tune
= cpu_arch
[j
].type
;
13313 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13317 if (j
>= ARRAY_SIZE (cpu_arch
))
13318 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13321 case OPTION_MMNEMONIC
:
13322 if (strcasecmp (arg
, "att") == 0)
13323 intel_mnemonic
= 0;
13324 else if (strcasecmp (arg
, "intel") == 0)
13325 intel_mnemonic
= 1;
13327 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13330 case OPTION_MSYNTAX
:
13331 if (strcasecmp (arg
, "att") == 0)
13333 else if (strcasecmp (arg
, "intel") == 0)
13336 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13339 case OPTION_MINDEX_REG
:
13340 allow_index_reg
= 1;
13343 case OPTION_MNAKED_REG
:
13344 allow_naked_reg
= 1;
13347 case OPTION_MSSE2AVX
:
13351 case OPTION_MSSE_CHECK
:
13352 if (strcasecmp (arg
, "error") == 0)
13353 sse_check
= check_error
;
13354 else if (strcasecmp (arg
, "warning") == 0)
13355 sse_check
= check_warning
;
13356 else if (strcasecmp (arg
, "none") == 0)
13357 sse_check
= check_none
;
13359 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13362 case OPTION_MOPERAND_CHECK
:
13363 if (strcasecmp (arg
, "error") == 0)
13364 operand_check
= check_error
;
13365 else if (strcasecmp (arg
, "warning") == 0)
13366 operand_check
= check_warning
;
13367 else if (strcasecmp (arg
, "none") == 0)
13368 operand_check
= check_none
;
13370 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13373 case OPTION_MAVXSCALAR
:
13374 if (strcasecmp (arg
, "128") == 0)
13375 avxscalar
= vex128
;
13376 else if (strcasecmp (arg
, "256") == 0)
13377 avxscalar
= vex256
;
13379 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13382 case OPTION_MVEXWIG
:
13383 if (strcmp (arg
, "0") == 0)
13385 else if (strcmp (arg
, "1") == 0)
13388 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13391 case OPTION_MADD_BND_PREFIX
:
13392 add_bnd_prefix
= 1;
13395 case OPTION_MEVEXLIG
:
13396 if (strcmp (arg
, "128") == 0)
13397 evexlig
= evexl128
;
13398 else if (strcmp (arg
, "256") == 0)
13399 evexlig
= evexl256
;
13400 else if (strcmp (arg
, "512") == 0)
13401 evexlig
= evexl512
;
13403 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13406 case OPTION_MEVEXRCIG
:
13407 if (strcmp (arg
, "rne") == 0)
13409 else if (strcmp (arg
, "rd") == 0)
13411 else if (strcmp (arg
, "ru") == 0)
13413 else if (strcmp (arg
, "rz") == 0)
13416 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13419 case OPTION_MEVEXWIG
:
13420 if (strcmp (arg
, "0") == 0)
13422 else if (strcmp (arg
, "1") == 0)
13425 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13428 # if defined (TE_PE) || defined (TE_PEP)
13429 case OPTION_MBIG_OBJ
:
13434 case OPTION_MOMIT_LOCK_PREFIX
:
13435 if (strcasecmp (arg
, "yes") == 0)
13436 omit_lock_prefix
= 1;
13437 else if (strcasecmp (arg
, "no") == 0)
13438 omit_lock_prefix
= 0;
13440 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13443 case OPTION_MFENCE_AS_LOCK_ADD
:
13444 if (strcasecmp (arg
, "yes") == 0)
13446 else if (strcasecmp (arg
, "no") == 0)
13449 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13452 case OPTION_MLFENCE_AFTER_LOAD
:
13453 if (strcasecmp (arg
, "yes") == 0)
13454 lfence_after_load
= 1;
13455 else if (strcasecmp (arg
, "no") == 0)
13456 lfence_after_load
= 0;
13458 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13461 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13462 if (strcasecmp (arg
, "all") == 0)
13464 lfence_before_indirect_branch
= lfence_branch_all
;
13465 if (lfence_before_ret
== lfence_before_ret_none
)
13466 lfence_before_ret
= lfence_before_ret_shl
;
13468 else if (strcasecmp (arg
, "memory") == 0)
13469 lfence_before_indirect_branch
= lfence_branch_memory
;
13470 else if (strcasecmp (arg
, "register") == 0)
13471 lfence_before_indirect_branch
= lfence_branch_register
;
13472 else if (strcasecmp (arg
, "none") == 0)
13473 lfence_before_indirect_branch
= lfence_branch_none
;
13475 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13479 case OPTION_MLFENCE_BEFORE_RET
:
13480 if (strcasecmp (arg
, "or") == 0)
13481 lfence_before_ret
= lfence_before_ret_or
;
13482 else if (strcasecmp (arg
, "not") == 0)
13483 lfence_before_ret
= lfence_before_ret_not
;
13484 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13485 lfence_before_ret
= lfence_before_ret_shl
;
13486 else if (strcasecmp (arg
, "none") == 0)
13487 lfence_before_ret
= lfence_before_ret_none
;
13489 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13493 case OPTION_MRELAX_RELOCATIONS
:
13494 if (strcasecmp (arg
, "yes") == 0)
13495 generate_relax_relocations
= 1;
13496 else if (strcasecmp (arg
, "no") == 0)
13497 generate_relax_relocations
= 0;
13499 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13502 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13505 long int align
= strtoul (arg
, &end
, 0);
13510 align_branch_power
= 0;
13513 else if (align
>= 16)
13516 for (align_power
= 0;
13518 align
>>= 1, align_power
++)
13520 /* Limit alignment power to 31. */
13521 if (align
== 1 && align_power
< 32)
13523 align_branch_power
= align_power
;
13528 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13532 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13535 int align
= strtoul (arg
, &end
, 0);
13536 /* Some processors only support 5 prefixes. */
13537 if (*end
== '\0' && align
>= 0 && align
< 6)
13539 align_branch_prefix_size
= align
;
13542 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13547 case OPTION_MALIGN_BRANCH
:
13549 saved
= xstrdup (arg
);
13553 next
= strchr (type
, '+');
13556 if (strcasecmp (type
, "jcc") == 0)
13557 align_branch
|= align_branch_jcc_bit
;
13558 else if (strcasecmp (type
, "fused") == 0)
13559 align_branch
|= align_branch_fused_bit
;
13560 else if (strcasecmp (type
, "jmp") == 0)
13561 align_branch
|= align_branch_jmp_bit
;
13562 else if (strcasecmp (type
, "call") == 0)
13563 align_branch
|= align_branch_call_bit
;
13564 else if (strcasecmp (type
, "ret") == 0)
13565 align_branch
|= align_branch_ret_bit
;
13566 else if (strcasecmp (type
, "indirect") == 0)
13567 align_branch
|= align_branch_indirect_bit
;
13569 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13572 while (next
!= NULL
);
13576 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13577 align_branch_power
= 5;
13578 align_branch_prefix_size
= 5;
13579 align_branch
= (align_branch_jcc_bit
13580 | align_branch_fused_bit
13581 | align_branch_jmp_bit
);
13584 case OPTION_MAMD64
:
13588 case OPTION_MINTEL64
:
13596 /* Turn off -Os. */
13597 optimize_for_space
= 0;
13599 else if (*arg
== 's')
13601 optimize_for_space
= 1;
13602 /* Turn on all encoding optimizations. */
13603 optimize
= INT_MAX
;
13607 optimize
= atoi (arg
);
13608 /* Turn off -Os. */
13609 optimize_for_space
= 0;
13619 #define MESSAGE_TEMPLATE \
13623 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13624 int *left_p
, const char *name
, int len
)
13626 int size
= sizeof (MESSAGE_TEMPLATE
);
13627 int left
= *left_p
;
13629 /* Reserve 2 spaces for ", " or ",\0" */
13632 /* Check if there is any room. */
13640 p
= mempcpy (p
, name
, len
);
13644 /* Output the current message now and start a new one. */
13647 fprintf (stream
, "%s\n", message
);
13649 left
= size
- (start
- message
) - len
- 2;
13651 gas_assert (left
>= 0);
13653 p
= mempcpy (p
, name
, len
);
13661 show_arch (FILE *stream
, int ext
, int check
)
13663 static char message
[] = MESSAGE_TEMPLATE
;
13664 char *start
= message
+ 27;
13666 int size
= sizeof (MESSAGE_TEMPLATE
);
13673 left
= size
- (start
- message
);
13674 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13676 /* Should it be skipped? */
13677 if (cpu_arch
[j
].skip
)
13680 name
= cpu_arch
[j
].name
;
13681 len
= cpu_arch
[j
].len
;
13684 /* It is an extension. Skip if we aren't asked to show it. */
13695 /* It is an processor. Skip if we show only extension. */
13698 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13700 /* It is an impossible processor - skip. */
13704 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13707 /* Display disabled extensions. */
13709 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13711 name
= cpu_noarch
[j
].name
;
13712 len
= cpu_noarch
[j
].len
;
13713 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13718 fprintf (stream
, "%s\n", message
);
13722 md_show_usage (FILE *stream
)
13724 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13725 fprintf (stream
, _("\
13726 -Qy, -Qn ignored\n\
13727 -V print assembler version number\n\
13730 fprintf (stream
, _("\
13731 -n Do not optimize code alignment\n\
13732 -q quieten some warnings\n"));
13733 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13734 fprintf (stream
, _("\
13737 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13738 || defined (TE_PE) || defined (TE_PEP))
13739 fprintf (stream
, _("\
13740 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13742 #ifdef SVR4_COMMENT_CHARS
13743 fprintf (stream
, _("\
13744 --divide do not treat `/' as a comment character\n"));
13746 fprintf (stream
, _("\
13747 --divide ignored\n"));
13749 fprintf (stream
, _("\
13750 -march=CPU[,+EXTENSION...]\n\
13751 generate code for CPU and EXTENSION, CPU is one of:\n"));
13752 show_arch (stream
, 0, 1);
13753 fprintf (stream
, _("\
13754 EXTENSION is combination of:\n"));
13755 show_arch (stream
, 1, 0);
13756 fprintf (stream
, _("\
13757 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13758 show_arch (stream
, 0, 0);
13759 fprintf (stream
, _("\
13760 -msse2avx encode SSE instructions with VEX prefix\n"));
13761 fprintf (stream
, _("\
13762 -msse-check=[none|error|warning] (default: warning)\n\
13763 check SSE instructions\n"));
13764 fprintf (stream
, _("\
13765 -moperand-check=[none|error|warning] (default: warning)\n\
13766 check operand combinations for validity\n"));
13767 fprintf (stream
, _("\
13768 -mavxscalar=[128|256] (default: 128)\n\
13769 encode scalar AVX instructions with specific vector\n\
13771 fprintf (stream
, _("\
13772 -mvexwig=[0|1] (default: 0)\n\
13773 encode VEX instructions with specific VEX.W value\n\
13774 for VEX.W bit ignored instructions\n"));
13775 fprintf (stream
, _("\
13776 -mevexlig=[128|256|512] (default: 128)\n\
13777 encode scalar EVEX instructions with specific vector\n\
13779 fprintf (stream
, _("\
13780 -mevexwig=[0|1] (default: 0)\n\
13781 encode EVEX instructions with specific EVEX.W value\n\
13782 for EVEX.W bit ignored instructions\n"));
13783 fprintf (stream
, _("\
13784 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13785 encode EVEX instructions with specific EVEX.RC value\n\
13786 for SAE-only ignored instructions\n"));
13787 fprintf (stream
, _("\
13788 -mmnemonic=[att|intel] "));
13789 if (SYSV386_COMPAT
)
13790 fprintf (stream
, _("(default: att)\n"));
13792 fprintf (stream
, _("(default: intel)\n"));
13793 fprintf (stream
, _("\
13794 use AT&T/Intel mnemonic\n"));
13795 fprintf (stream
, _("\
13796 -msyntax=[att|intel] (default: att)\n\
13797 use AT&T/Intel syntax\n"));
13798 fprintf (stream
, _("\
13799 -mindex-reg support pseudo index registers\n"));
13800 fprintf (stream
, _("\
13801 -mnaked-reg don't require `%%' prefix for registers\n"));
13802 fprintf (stream
, _("\
13803 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13804 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13805 fprintf (stream
, _("\
13806 -mshared disable branch optimization for shared code\n"));
13807 fprintf (stream
, _("\
13808 -mx86-used-note=[no|yes] "));
13809 if (DEFAULT_X86_USED_NOTE
)
13810 fprintf (stream
, _("(default: yes)\n"));
13812 fprintf (stream
, _("(default: no)\n"));
13813 fprintf (stream
, _("\
13814 generate x86 used ISA and feature properties\n"));
13816 #if defined (TE_PE) || defined (TE_PEP)
13817 fprintf (stream
, _("\
13818 -mbig-obj generate big object files\n"));
13820 fprintf (stream
, _("\
13821 -momit-lock-prefix=[no|yes] (default: no)\n\
13822 strip all lock prefixes\n"));
13823 fprintf (stream
, _("\
13824 -mfence-as-lock-add=[no|yes] (default: no)\n\
13825 encode lfence, mfence and sfence as\n\
13826 lock addl $0x0, (%%{re}sp)\n"));
13827 fprintf (stream
, _("\
13828 -mrelax-relocations=[no|yes] "));
13829 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13830 fprintf (stream
, _("(default: yes)\n"));
13832 fprintf (stream
, _("(default: no)\n"));
13833 fprintf (stream
, _("\
13834 generate relax relocations\n"));
13835 fprintf (stream
, _("\
13836 -malign-branch-boundary=NUM (default: 0)\n\
13837 align branches within NUM byte boundary\n"));
13838 fprintf (stream
, _("\
13839 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13840 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13842 specify types of branches to align\n"));
13843 fprintf (stream
, _("\
13844 -malign-branch-prefix-size=NUM (default: 5)\n\
13845 align branches with NUM prefixes per instruction\n"));
13846 fprintf (stream
, _("\
13847 -mbranches-within-32B-boundaries\n\
13848 align branches within 32 byte boundary\n"));
13849 fprintf (stream
, _("\
13850 -mlfence-after-load=[no|yes] (default: no)\n\
13851 generate lfence after load\n"));
13852 fprintf (stream
, _("\
13853 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13854 generate lfence before indirect near branch\n"));
13855 fprintf (stream
, _("\
13856 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13857 generate lfence before ret\n"));
13858 fprintf (stream
, _("\
13859 -mamd64 accept only AMD64 ISA [default]\n"));
13860 fprintf (stream
, _("\
13861 -mintel64 accept only Intel64 ISA\n"));
13864 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13865 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13866 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13868 /* Pick the target format to use. */
13871 i386_target_format (void)
13873 if (startswith (default_arch
, "x86_64"))
13875 update_code_flag (CODE_64BIT
, 1);
13876 if (default_arch
[6] == '\0')
13877 x86_elf_abi
= X86_64_ABI
;
13879 x86_elf_abi
= X86_64_X32_ABI
;
13881 else if (!strcmp (default_arch
, "i386"))
13882 update_code_flag (CODE_32BIT
, 1);
13883 else if (!strcmp (default_arch
, "iamcu"))
13885 update_code_flag (CODE_32BIT
, 1);
13886 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13888 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13889 cpu_arch_name
= "iamcu";
13890 cpu_sub_arch_name
= NULL
;
13891 cpu_arch_flags
= iamcu_flags
;
13892 cpu_arch_isa
= PROCESSOR_IAMCU
;
13893 cpu_arch_isa_flags
= iamcu_flags
;
13894 if (!cpu_arch_tune_set
)
13896 cpu_arch_tune
= cpu_arch_isa
;
13897 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13900 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13901 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13905 as_fatal (_("unknown architecture"));
13907 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13908 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13909 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13910 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13912 switch (OUTPUT_FLAVOR
)
13914 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13915 case bfd_target_aout_flavour
:
13916 return AOUT_TARGET_FORMAT
;
13918 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13919 # if defined (TE_PE) || defined (TE_PEP)
13920 case bfd_target_coff_flavour
:
13921 if (flag_code
== CODE_64BIT
)
13924 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13926 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13927 # elif defined (TE_GO32)
13928 case bfd_target_coff_flavour
:
13929 return "coff-go32";
13931 case bfd_target_coff_flavour
:
13932 return "coff-i386";
13935 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13936 case bfd_target_elf_flavour
:
13938 const char *format
;
13940 switch (x86_elf_abi
)
13943 format
= ELF_TARGET_FORMAT
;
13945 tls_get_addr
= "___tls_get_addr";
13949 use_rela_relocations
= 1;
13952 tls_get_addr
= "__tls_get_addr";
13954 format
= ELF_TARGET_FORMAT64
;
13956 case X86_64_X32_ABI
:
13957 use_rela_relocations
= 1;
13960 tls_get_addr
= "__tls_get_addr";
13962 disallow_64bit_reloc
= 1;
13963 format
= ELF_TARGET_FORMAT32
;
13966 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13968 if (x86_elf_abi
!= X86_64_ABI
)
13969 as_fatal (_("Intel L1OM is 64bit only"));
13970 return ELF_TARGET_L1OM_FORMAT
;
13972 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13974 if (x86_elf_abi
!= X86_64_ABI
)
13975 as_fatal (_("Intel K1OM is 64bit only"));
13976 return ELF_TARGET_K1OM_FORMAT
;
13978 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13980 if (x86_elf_abi
!= I386_ABI
)
13981 as_fatal (_("Intel MCU is 32bit only"));
13982 return ELF_TARGET_IAMCU_FORMAT
;
13988 #if defined (OBJ_MACH_O)
13989 case bfd_target_mach_o_flavour
:
13990 if (flag_code
== CODE_64BIT
)
13992 use_rela_relocations
= 1;
13994 return "mach-o-x86-64";
13997 return "mach-o-i386";
14005 #endif /* OBJ_MAYBE_ more than one */
14008 md_undefined_symbol (char *name
)
14010 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
14011 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
14012 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
14013 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
14017 if (symbol_find (name
))
14018 as_bad (_("GOT already in symbol table"));
14019 GOT_symbol
= symbol_new (name
, undefined_section
,
14020 &zero_address_frag
, 0);
14027 /* Round up a section size to the appropriate boundary. */
14030 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
14032 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
14033 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
14035 /* For a.out, force the section size to be aligned. If we don't do
14036 this, BFD will align it for us, but it will not write out the
14037 final bytes of the section. This may be a bug in BFD, but it is
14038 easier to fix it here since that is how the other a.out targets
14042 align
= bfd_section_alignment (segment
);
14043 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
14050 /* On the i386, PC-relative offsets are relative to the start of the
14051 next instruction. That is, the address of the offset, plus its
14052 size, since the offset is always the last part of the insn. */
14055 md_pcrel_from (fixS
*fixP
)
14057 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14063 s_bss (int ignore ATTRIBUTE_UNUSED
)
14067 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14069 obj_elf_section_change_hook ();
14071 temp
= get_absolute_expression ();
14072 subseg_set (bss_section
, (subsegT
) temp
);
14073 demand_empty_rest_of_line ();
14078 /* Remember constant directive. */
14081 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
14083 if (last_insn
.kind
!= last_insn_directive
14084 && (bfd_section_flags (now_seg
) & SEC_CODE
))
14086 last_insn
.seg
= now_seg
;
14087 last_insn
.kind
= last_insn_directive
;
14088 last_insn
.name
= "constant directive";
14089 last_insn
.file
= as_where (&last_insn
.line
);
14090 if (lfence_before_ret
!= lfence_before_ret_none
)
14092 if (lfence_before_indirect_branch
!= lfence_branch_none
)
14093 as_warn (_("constant directive skips -mlfence-before-ret "
14094 "and -mlfence-before-indirect-branch"));
14096 as_warn (_("constant directive skips -mlfence-before-ret"));
14098 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
14099 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
14104 i386_validate_fix (fixS
*fixp
)
14106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14107 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14108 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
14109 return IS_ELF
&& fixp
->fx_addsy
14110 && (!S_IS_DEFINED (fixp
->fx_addsy
)
14111 || S_IS_EXTERNAL (fixp
->fx_addsy
));
14114 if (fixp
->fx_subsy
)
14116 if (fixp
->fx_subsy
== GOT_symbol
)
14118 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
14122 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14123 if (fixp
->fx_tcbit2
)
14124 fixp
->fx_r_type
= (fixp
->fx_tcbit
14125 ? BFD_RELOC_X86_64_REX_GOTPCRELX
14126 : BFD_RELOC_X86_64_GOTPCRELX
);
14129 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
14134 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
14136 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
14138 fixp
->fx_subsy
= 0;
14141 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14144 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
14145 to section. Since PLT32 relocation must be against symbols,
14146 turn such PLT32 relocation into PC32 relocation. */
14148 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
14149 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
14150 && symbol_section_p (fixp
->fx_addsy
))
14151 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
14154 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
14155 && fixp
->fx_tcbit2
)
14156 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
14165 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14168 bfd_reloc_code_real_type code
;
14170 switch (fixp
->fx_r_type
)
14172 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14175 case BFD_RELOC_SIZE32
:
14176 case BFD_RELOC_SIZE64
:
14178 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
14179 && (!fixp
->fx_subsy
14180 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
14181 sym
= fixp
->fx_addsy
;
14182 else if (fixp
->fx_subsy
14183 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
14184 && (!fixp
->fx_addsy
14185 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
14186 sym
= fixp
->fx_subsy
;
14189 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
14191 /* Resolve size relocation against local symbol to size of
14192 the symbol plus addend. */
14193 valueT value
= S_GET_SIZE (sym
);
14195 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
14196 value
= bfd_section_size (S_GET_SEGMENT (sym
));
14197 if (sym
== fixp
->fx_subsy
)
14200 if (fixp
->fx_addsy
)
14201 value
+= S_GET_VALUE (fixp
->fx_addsy
);
14203 else if (fixp
->fx_subsy
)
14204 value
-= S_GET_VALUE (fixp
->fx_subsy
);
14205 value
+= fixp
->fx_offset
;
14206 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14208 && !fits_in_unsigned_long (value
))
14209 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14210 _("symbol size computation overflow"));
14211 fixp
->fx_addsy
= NULL
;
14212 fixp
->fx_subsy
= NULL
;
14213 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14216 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
14218 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14219 "unsupported expression involving @size");
14223 /* Fall through. */
14225 case BFD_RELOC_X86_64_PLT32
:
14226 case BFD_RELOC_X86_64_GOT32
:
14227 case BFD_RELOC_X86_64_GOTPCREL
:
14228 case BFD_RELOC_X86_64_GOTPCRELX
:
14229 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14230 case BFD_RELOC_386_PLT32
:
14231 case BFD_RELOC_386_GOT32
:
14232 case BFD_RELOC_386_GOT32X
:
14233 case BFD_RELOC_386_GOTOFF
:
14234 case BFD_RELOC_386_GOTPC
:
14235 case BFD_RELOC_386_TLS_GD
:
14236 case BFD_RELOC_386_TLS_LDM
:
14237 case BFD_RELOC_386_TLS_LDO_32
:
14238 case BFD_RELOC_386_TLS_IE_32
:
14239 case BFD_RELOC_386_TLS_IE
:
14240 case BFD_RELOC_386_TLS_GOTIE
:
14241 case BFD_RELOC_386_TLS_LE_32
:
14242 case BFD_RELOC_386_TLS_LE
:
14243 case BFD_RELOC_386_TLS_GOTDESC
:
14244 case BFD_RELOC_386_TLS_DESC_CALL
:
14245 case BFD_RELOC_X86_64_TLSGD
:
14246 case BFD_RELOC_X86_64_TLSLD
:
14247 case BFD_RELOC_X86_64_DTPOFF32
:
14248 case BFD_RELOC_X86_64_DTPOFF64
:
14249 case BFD_RELOC_X86_64_GOTTPOFF
:
14250 case BFD_RELOC_X86_64_TPOFF32
:
14251 case BFD_RELOC_X86_64_TPOFF64
:
14252 case BFD_RELOC_X86_64_GOTOFF64
:
14253 case BFD_RELOC_X86_64_GOTPC32
:
14254 case BFD_RELOC_X86_64_GOT64
:
14255 case BFD_RELOC_X86_64_GOTPCREL64
:
14256 case BFD_RELOC_X86_64_GOTPC64
:
14257 case BFD_RELOC_X86_64_GOTPLT64
:
14258 case BFD_RELOC_X86_64_PLTOFF64
:
14259 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14260 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14261 case BFD_RELOC_RVA
:
14262 case BFD_RELOC_VTABLE_ENTRY
:
14263 case BFD_RELOC_VTABLE_INHERIT
:
14265 case BFD_RELOC_32_SECREL
:
14267 code
= fixp
->fx_r_type
;
14269 case BFD_RELOC_X86_64_32S
:
14270 if (!fixp
->fx_pcrel
)
14272 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14273 code
= fixp
->fx_r_type
;
14276 /* Fall through. */
14278 if (fixp
->fx_pcrel
)
14280 switch (fixp
->fx_size
)
14283 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14284 _("can not do %d byte pc-relative relocation"),
14286 code
= BFD_RELOC_32_PCREL
;
14288 case 1: code
= BFD_RELOC_8_PCREL
; break;
14289 case 2: code
= BFD_RELOC_16_PCREL
; break;
14290 case 4: code
= BFD_RELOC_32_PCREL
; break;
14292 case 8: code
= BFD_RELOC_64_PCREL
; break;
14298 switch (fixp
->fx_size
)
14301 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14302 _("can not do %d byte relocation"),
14304 code
= BFD_RELOC_32
;
14306 case 1: code
= BFD_RELOC_8
; break;
14307 case 2: code
= BFD_RELOC_16
; break;
14308 case 4: code
= BFD_RELOC_32
; break;
14310 case 8: code
= BFD_RELOC_64
; break;
14317 if ((code
== BFD_RELOC_32
14318 || code
== BFD_RELOC_32_PCREL
14319 || code
== BFD_RELOC_X86_64_32S
)
14321 && fixp
->fx_addsy
== GOT_symbol
)
14324 code
= BFD_RELOC_386_GOTPC
;
14326 code
= BFD_RELOC_X86_64_GOTPC32
;
14328 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14330 && fixp
->fx_addsy
== GOT_symbol
)
14332 code
= BFD_RELOC_X86_64_GOTPC64
;
14335 rel
= XNEW (arelent
);
14336 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14337 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14339 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14341 if (!use_rela_relocations
)
14343 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14344 vtable entry to be used in the relocation's section offset. */
14345 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14346 rel
->address
= fixp
->fx_offset
;
14347 #if defined (OBJ_COFF) && defined (TE_PE)
14348 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14349 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14354 /* Use the rela in 64bit mode. */
14357 if (disallow_64bit_reloc
)
14360 case BFD_RELOC_X86_64_DTPOFF64
:
14361 case BFD_RELOC_X86_64_TPOFF64
:
14362 case BFD_RELOC_64_PCREL
:
14363 case BFD_RELOC_X86_64_GOTOFF64
:
14364 case BFD_RELOC_X86_64_GOT64
:
14365 case BFD_RELOC_X86_64_GOTPCREL64
:
14366 case BFD_RELOC_X86_64_GOTPC64
:
14367 case BFD_RELOC_X86_64_GOTPLT64
:
14368 case BFD_RELOC_X86_64_PLTOFF64
:
14369 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14370 _("cannot represent relocation type %s in x32 mode"),
14371 bfd_get_reloc_code_name (code
));
14377 if (!fixp
->fx_pcrel
)
14378 rel
->addend
= fixp
->fx_offset
;
14382 case BFD_RELOC_X86_64_PLT32
:
14383 case BFD_RELOC_X86_64_GOT32
:
14384 case BFD_RELOC_X86_64_GOTPCREL
:
14385 case BFD_RELOC_X86_64_GOTPCRELX
:
14386 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14387 case BFD_RELOC_X86_64_TLSGD
:
14388 case BFD_RELOC_X86_64_TLSLD
:
14389 case BFD_RELOC_X86_64_GOTTPOFF
:
14390 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14391 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14392 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14395 rel
->addend
= (section
->vma
14397 + fixp
->fx_addnumber
14398 + md_pcrel_from (fixp
));
14403 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14404 if (rel
->howto
== NULL
)
14406 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14407 _("cannot represent relocation type %s"),
14408 bfd_get_reloc_code_name (code
));
14409 /* Set howto to a garbage value so that we can keep going. */
14410 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14411 gas_assert (rel
->howto
!= NULL
);
14417 #include "tc-i386-intel.c"
14420 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14422 int saved_naked_reg
;
14423 char saved_register_dot
;
14425 saved_naked_reg
= allow_naked_reg
;
14426 allow_naked_reg
= 1;
14427 saved_register_dot
= register_chars
['.'];
14428 register_chars
['.'] = '.';
14429 allow_pseudo_reg
= 1;
14430 expression_and_evaluate (exp
);
14431 allow_pseudo_reg
= 0;
14432 register_chars
['.'] = saved_register_dot
;
14433 allow_naked_reg
= saved_naked_reg
;
14435 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14437 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14439 exp
->X_op
= O_constant
;
14440 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14441 .dw2_regnum
[flag_code
>> 1];
14444 exp
->X_op
= O_illegal
;
14449 tc_x86_frame_initial_instructions (void)
14451 static unsigned int sp_regno
[2];
14453 if (!sp_regno
[flag_code
>> 1])
14455 char *saved_input
= input_line_pointer
;
14456 char sp
[][4] = {"esp", "rsp"};
14459 input_line_pointer
= sp
[flag_code
>> 1];
14460 tc_x86_parse_to_dw2regnum (&exp
);
14461 gas_assert (exp
.X_op
== O_constant
);
14462 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14463 input_line_pointer
= saved_input
;
14466 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14467 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14471 x86_dwarf2_addr_size (void)
14473 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14474 if (x86_elf_abi
== X86_64_X32_ABI
)
14477 return bfd_arch_bits_per_address (stdoutput
) / 8;
14481 i386_elf_section_type (const char *str
, size_t len
)
14483 if (flag_code
== CODE_64BIT
14484 && len
== sizeof ("unwind") - 1
14485 && startswith (str
, "unwind"))
14486 return SHT_X86_64_UNWIND
;
14493 i386_solaris_fix_up_eh_frame (segT sec
)
14495 if (flag_code
== CODE_64BIT
)
14496 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14502 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14506 exp
.X_op
= O_secrel
;
14507 exp
.X_add_symbol
= symbol
;
14508 exp
.X_add_number
= 0;
14509 emit_expr (&exp
, size
);
14513 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14514 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14517 x86_64_section_letter (int letter
, const char **ptr_msg
)
14519 if (flag_code
== CODE_64BIT
)
14522 return SHF_X86_64_LARGE
;
14524 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14527 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14532 x86_64_section_word (char *str
, size_t len
)
14534 if (len
== 5 && flag_code
== CODE_64BIT
&& startswith (str
, "large"))
14535 return SHF_X86_64_LARGE
;
14541 handle_large_common (int small ATTRIBUTE_UNUSED
)
14543 if (flag_code
!= CODE_64BIT
)
14545 s_comm_internal (0, elf_common_parse
);
14546 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14550 static segT lbss_section
;
14551 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14552 asection
*saved_bss_section
= bss_section
;
14554 if (lbss_section
== NULL
)
14556 flagword applicable
;
14557 segT seg
= now_seg
;
14558 subsegT subseg
= now_subseg
;
14560 /* The .lbss section is for local .largecomm symbols. */
14561 lbss_section
= subseg_new (".lbss", 0);
14562 applicable
= bfd_applicable_section_flags (stdoutput
);
14563 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14564 seg_info (lbss_section
)->bss
= 1;
14566 subseg_set (seg
, subseg
);
14569 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14570 bss_section
= lbss_section
;
14572 s_comm_internal (0, elf_common_parse
);
14574 elf_com_section_ptr
= saved_com_section_ptr
;
14575 bss_section
= saved_bss_section
;
14578 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */