1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static void optimize_imm (void);
186 static void optimize_disp (void);
187 static const insn_template
*match_template (char);
188 static int check_string (void);
189 static int process_suffix (void);
190 static int check_byte_reg (void);
191 static int check_long_reg (void);
192 static int check_qword_reg (void);
193 static int check_word_reg (void);
194 static int finalize_imm (void);
195 static int process_operands (void);
196 static const seg_entry
*build_modrm_byte (void);
197 static void output_insn (void);
198 static void output_imm (fragS
*, offsetT
);
199 static void output_disp (fragS
*, offsetT
);
201 static void s_bss (int);
203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
204 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
206 /* GNU_PROPERTY_X86_ISA_1_USED. */
207 static unsigned int x86_isa_1_used
;
208 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
209 static unsigned int x86_feature_2_used
;
210 /* Generate x86 used ISA and feature properties. */
211 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
214 static const char *default_arch
= DEFAULT_ARCH
;
216 /* This struct describes rounding control and SAE in the instruction. */
230 static struct RC_Operation rc_op
;
232 /* The struct describes masking, applied to OPERAND in the instruction.
233 MASK is a pointer to the corresponding mask register. ZEROING tells
234 whether merging or zeroing mask is used. */
235 struct Mask_Operation
237 const reg_entry
*mask
;
238 unsigned int zeroing
;
239 /* The operand where this operation is associated. */
243 static struct Mask_Operation mask_op
;
245 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
247 struct Broadcast_Operation
249 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
252 /* Index of broadcasted operand. */
255 /* Number of bytes to broadcast. */
259 static struct Broadcast_Operation broadcast_op
;
264 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
265 unsigned char bytes
[4];
267 /* Destination or source register specifier. */
268 const reg_entry
*register_specifier
;
271 /* 'md_assemble ()' gathers together information and puts it into a
278 const reg_entry
*regs
;
283 operand_size_mismatch
,
284 operand_type_mismatch
,
285 register_type_mismatch
,
286 number_of_operands_mismatch
,
287 invalid_instruction_suffix
,
289 unsupported_with_intel_mnemonic
,
292 invalid_vsib_address
,
293 invalid_vector_register_set
,
294 unsupported_vector_index_register
,
295 unsupported_broadcast
,
298 mask_not_on_destination
,
301 rc_sae_operand_not_last_imm
,
302 invalid_register_operand
,
307 /* TM holds the template for the insn were currently assembling. */
310 /* SUFFIX holds the instruction size suffix for byte, word, dword
311 or qword, if given. */
314 /* OPERANDS gives the number of given operands. */
315 unsigned int operands
;
317 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
318 of given register, displacement, memory operands and immediate
320 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
322 /* TYPES [i] is the type (see above #defines) which tells us how to
323 use OP[i] for the corresponding operand. */
324 i386_operand_type types
[MAX_OPERANDS
];
326 /* Displacement expression, immediate expression, or register for each
328 union i386_op op
[MAX_OPERANDS
];
330 /* Flags for operands. */
331 unsigned int flags
[MAX_OPERANDS
];
332 #define Operand_PCrel 1
333 #define Operand_Mem 2
335 /* Relocation type for operand */
336 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
338 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
339 the base index byte below. */
340 const reg_entry
*base_reg
;
341 const reg_entry
*index_reg
;
342 unsigned int log2_scale_factor
;
344 /* SEG gives the seg_entries of this insn. They are zero unless
345 explicit segment overrides are given. */
346 const seg_entry
*seg
[2];
348 /* Copied first memory operand string, for re-checking. */
351 /* PREFIX holds all the given prefix opcodes (usually null).
352 PREFIXES is the number of prefix opcodes. */
353 unsigned int prefixes
;
354 unsigned char prefix
[MAX_PREFIXES
];
356 /* The operand to a branch insn indicates an absolute branch. */
357 bfd_boolean jumpabsolute
;
359 /* Has MMX register operands. */
360 bfd_boolean has_regmmx
;
362 /* Has XMM register operands. */
363 bfd_boolean has_regxmm
;
365 /* Has YMM register operands. */
366 bfd_boolean has_regymm
;
368 /* Has ZMM register operands. */
369 bfd_boolean has_regzmm
;
371 /* RM and SIB are the modrm byte and the sib byte where the
372 addressing modes of this insn are encoded. */
379 /* Masking attributes. */
380 struct Mask_Operation
*mask
;
382 /* Rounding control and SAE attributes. */
383 struct RC_Operation
*rounding
;
385 /* Broadcasting attributes. */
386 struct Broadcast_Operation
*broadcast
;
388 /* Compressed disp8*N attribute. */
389 unsigned int memshift
;
391 /* Prefer load or store in encoding. */
394 dir_encoding_default
= 0,
400 /* Prefer 8bit or 32bit displacement in encoding. */
403 disp_encoding_default
= 0,
408 /* Prefer the REX byte in encoding. */
409 bfd_boolean rex_encoding
;
411 /* Disable instruction size optimization. */
412 bfd_boolean no_optimize
;
414 /* How to encode vector instructions. */
417 vex_encoding_default
= 0,
424 const char *rep_prefix
;
427 const char *hle_prefix
;
429 /* Have BND prefix. */
430 const char *bnd_prefix
;
432 /* Have NOTRACK prefix. */
433 const char *notrack_prefix
;
436 enum i386_error error
;
439 typedef struct _i386_insn i386_insn
;
441 /* Link RC type with corresponding string, that'll be looked for in
450 static const struct RC_name RC_NamesTable
[] =
452 { rne
, STRING_COMMA_LEN ("rn-sae") },
453 { rd
, STRING_COMMA_LEN ("rd-sae") },
454 { ru
, STRING_COMMA_LEN ("ru-sae") },
455 { rz
, STRING_COMMA_LEN ("rz-sae") },
456 { saeonly
, STRING_COMMA_LEN ("sae") },
459 /* List of chars besides those in app.c:symbol_chars that can start an
460 operand. Used to prevent the scrubber eating vital white-space. */
461 const char extra_symbol_chars
[] = "*%-([{}"
470 #if (defined (TE_I386AIX) \
471 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
472 && !defined (TE_GNU) \
473 && !defined (TE_LINUX) \
474 && !defined (TE_NACL) \
475 && !defined (TE_FreeBSD) \
476 && !defined (TE_DragonFly) \
477 && !defined (TE_NetBSD)))
478 /* This array holds the chars that always start a comment. If the
479 pre-processor is disabled, these aren't very useful. The option
480 --divide will remove '/' from this list. */
481 const char *i386_comment_chars
= "#/";
482 #define SVR4_COMMENT_CHARS 1
483 #define PREFIX_SEPARATOR '\\'
486 const char *i386_comment_chars
= "#";
487 #define PREFIX_SEPARATOR '/'
490 /* This array holds the chars that only start a comment at the beginning of
491 a line. If the line seems to have the form '# 123 filename'
492 .line and .file directives will appear in the pre-processed output.
493 Note that input_file.c hand checks for '#' at the beginning of the
494 first line of the input file. This is because the compiler outputs
495 #NO_APP at the beginning of its output.
496 Also note that comments started like this one will always work if
497 '/' isn't otherwise defined. */
498 const char line_comment_chars
[] = "#/";
500 const char line_separator_chars
[] = ";";
502 /* Chars that can be used to separate mant from exp in floating point
504 const char EXP_CHARS
[] = "eE";
506 /* Chars that mean this number is a floating point constant
509 const char FLT_CHARS
[] = "fFdDxX";
511 /* Tables for lexical analysis. */
512 static char mnemonic_chars
[256];
513 static char register_chars
[256];
514 static char operand_chars
[256];
515 static char identifier_chars
[256];
516 static char digit_chars
[256];
518 /* Lexical macros. */
519 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
520 #define is_operand_char(x) (operand_chars[(unsigned char) x])
521 #define is_register_char(x) (register_chars[(unsigned char) x])
522 #define is_space_char(x) ((x) == ' ')
523 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
524 #define is_digit_char(x) (digit_chars[(unsigned char) x])
526 /* All non-digit non-letter characters that may occur in an operand. */
527 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
529 /* md_assemble() always leaves the strings it's passed unaltered. To
530 effect this we maintain a stack of saved characters that we've smashed
531 with '\0's (indicating end of strings for various sub-fields of the
532 assembler instruction). */
533 static char save_stack
[32];
534 static char *save_stack_p
;
535 #define END_STRING_AND_SAVE(s) \
536 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
537 #define RESTORE_END_STRING(s) \
538 do { *(s) = *--save_stack_p; } while (0)
540 /* The instruction we're assembling. */
543 /* Possible templates for current insn. */
544 static const templates
*current_templates
;
546 /* Per instruction expressionS buffers: max displacements & immediates. */
547 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
548 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
550 /* Current operand we are working on. */
551 static int this_operand
= -1;
553 /* We support four different modes. FLAG_CODE variable is used to distinguish
561 static enum flag_code flag_code
;
562 static unsigned int object_64bit
;
563 static unsigned int disallow_64bit_reloc
;
564 static int use_rela_relocations
= 0;
566 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
567 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
568 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
570 /* The ELF ABI to use. */
578 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
581 #if defined (TE_PE) || defined (TE_PEP)
582 /* Use big object file format. */
583 static int use_big_obj
= 0;
586 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
587 /* 1 if generating code for a shared library. */
588 static int shared
= 0;
591 /* 1 for intel syntax,
593 static int intel_syntax
= 0;
595 /* 1 for Intel64 ISA,
599 /* 1 for intel mnemonic,
600 0 if att mnemonic. */
601 static int intel_mnemonic
= !SYSV386_COMPAT
;
603 /* 1 if pseudo registers are permitted. */
604 static int allow_pseudo_reg
= 0;
606 /* 1 if register prefix % not required. */
607 static int allow_naked_reg
= 0;
609 /* 1 if the assembler should add BND prefix for all control-transferring
610 instructions supporting it, even if this prefix wasn't specified
612 static int add_bnd_prefix
= 0;
614 /* 1 if pseudo index register, eiz/riz, is allowed . */
615 static int allow_index_reg
= 0;
617 /* 1 if the assembler should ignore LOCK prefix, even if it was
618 specified explicitly. */
619 static int omit_lock_prefix
= 0;
621 /* 1 if the assembler should encode lfence, mfence, and sfence as
622 "lock addl $0, (%{re}sp)". */
623 static int avoid_fence
= 0;
625 /* 1 if the assembler should generate relax relocations. */
627 static int generate_relax_relocations
628 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
630 static enum check_kind
636 sse_check
, operand_check
= check_warning
;
639 1. Clear the REX_W bit with register operand if possible.
640 2. Above plus use 128bit vector instruction to clear the full vector
643 static int optimize
= 0;
646 1. Clear the REX_W bit with register operand if possible.
647 2. Above plus use 128bit vector instruction to clear the full vector
649 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
652 static int optimize_for_space
= 0;
654 /* Register prefix used for error message. */
655 static const char *register_prefix
= "%";
657 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
658 leave, push, and pop instructions so that gcc has the same stack
659 frame as in 32 bit mode. */
660 static char stackop_size
= '\0';
662 /* Non-zero to optimize code alignment. */
663 int optimize_align_code
= 1;
665 /* Non-zero to quieten some warnings. */
666 static int quiet_warnings
= 0;
669 static const char *cpu_arch_name
= NULL
;
670 static char *cpu_sub_arch_name
= NULL
;
672 /* CPU feature flags. */
673 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
675 /* If we have selected a cpu we are generating instructions for. */
676 static int cpu_arch_tune_set
= 0;
678 /* Cpu we are generating instructions for. */
679 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
681 /* CPU feature flags of cpu we are generating instructions for. */
682 static i386_cpu_flags cpu_arch_tune_flags
;
684 /* CPU instruction set architecture used. */
685 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
687 /* CPU feature flags of instruction set architecture used. */
688 i386_cpu_flags cpu_arch_isa_flags
;
690 /* If set, conditional jumps are not automatically promoted to handle
691 larger than a byte offset. */
692 static unsigned int no_cond_jump_promotion
= 0;
694 /* Encode SSE instructions with VEX prefix. */
695 static unsigned int sse2avx
;
697 /* Encode scalar AVX instructions with specific vector length. */
704 /* Encode VEX WIG instructions with specific vex.w. */
711 /* Encode scalar EVEX LIG instructions with specific vector length. */
719 /* Encode EVEX WIG instructions with specific evex.w. */
726 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
727 static enum rc_type evexrcig
= rne
;
729 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
730 static symbolS
*GOT_symbol
;
732 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
733 unsigned int x86_dwarf2_return_column
;
735 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
736 int x86_cie_data_alignment
;
738 /* Interface to relax_segment.
739 There are 3 major relax states for 386 jump insns because the
740 different types of jumps add different sizes to frags when we're
741 figuring out what sort of jump to choose to reach a given label. */
744 #define UNCOND_JUMP 0
746 #define COND_JUMP86 2
751 #define SMALL16 (SMALL | CODE16)
753 #define BIG16 (BIG | CODE16)
757 #define INLINE __inline__
763 #define ENCODE_RELAX_STATE(type, size) \
764 ((relax_substateT) (((type) << 2) | (size)))
765 #define TYPE_FROM_RELAX_STATE(s) \
767 #define DISP_SIZE_FROM_RELAX_STATE(s) \
768 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
770 /* This table is used by relax_frag to promote short jumps to long
771 ones where necessary. SMALL (short) jumps may be promoted to BIG
772 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
773 don't allow a short jump in a 32 bit code segment to be promoted to
774 a 16 bit offset jump because it's slower (requires data size
775 prefix), and doesn't work, unless the destination is in the bottom
776 64k of the code segment (The top 16 bits of eip are zeroed). */
778 const relax_typeS md_relax_table
[] =
781 1) most positive reach of this state,
782 2) most negative reach of this state,
783 3) how many bytes this mode will have in the variable part of the frag
784 4) which index into the table to try if we can't fit into this one. */
786 /* UNCOND_JUMP states. */
787 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
788 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
789 /* dword jmp adds 4 bytes to frag:
790 0 extra opcode bytes, 4 displacement bytes. */
792 /* word jmp adds 2 byte2 to frag:
793 0 extra opcode bytes, 2 displacement bytes. */
796 /* COND_JUMP states. */
797 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
798 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
799 /* dword conditionals adds 5 bytes to frag:
800 1 extra opcode byte, 4 displacement bytes. */
802 /* word conditionals add 3 bytes to frag:
803 1 extra opcode byte, 2 displacement bytes. */
806 /* COND_JUMP86 states. */
807 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
808 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
809 /* dword conditionals adds 5 bytes to frag:
810 1 extra opcode byte, 4 displacement bytes. */
812 /* word conditionals add 4 bytes to frag:
813 1 displacement byte and a 3 byte long branch insn. */
817 static const arch_entry cpu_arch
[] =
819 /* Do not replace the first two entries - i386_target_format()
820 relies on them being there in this order. */
821 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
822 CPU_GENERIC32_FLAGS
, 0 },
823 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
824 CPU_GENERIC64_FLAGS
, 0 },
825 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
827 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
829 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
831 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
833 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
835 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
837 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
839 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
841 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
842 CPU_PENTIUMPRO_FLAGS
, 0 },
843 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
845 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
847 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
849 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
851 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
852 CPU_NOCONA_FLAGS
, 0 },
853 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
855 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
857 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
858 CPU_CORE2_FLAGS
, 1 },
859 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
860 CPU_CORE2_FLAGS
, 0 },
861 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
862 CPU_COREI7_FLAGS
, 0 },
863 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
865 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
867 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
868 CPU_IAMCU_FLAGS
, 0 },
869 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
871 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
873 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
874 CPU_ATHLON_FLAGS
, 0 },
875 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
877 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
879 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
881 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
882 CPU_AMDFAM10_FLAGS
, 0 },
883 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
884 CPU_BDVER1_FLAGS
, 0 },
885 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
886 CPU_BDVER2_FLAGS
, 0 },
887 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
888 CPU_BDVER3_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
890 CPU_BDVER4_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
892 CPU_ZNVER1_FLAGS
, 0 },
893 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
894 CPU_ZNVER2_FLAGS
, 0 },
895 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
896 CPU_BTVER1_FLAGS
, 0 },
897 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
898 CPU_BTVER2_FLAGS
, 0 },
899 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
915 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
917 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
920 CPU_SSSE3_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
922 CPU_SSE4_1_FLAGS
, 0 },
923 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
924 CPU_SSE4_2_FLAGS
, 0 },
925 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
926 CPU_SSE4_2_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
929 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
931 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
932 CPU_AVX512F_FLAGS
, 0 },
933 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
934 CPU_AVX512CD_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
936 CPU_AVX512ER_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
938 CPU_AVX512PF_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
940 CPU_AVX512DQ_FLAGS
, 0 },
941 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
942 CPU_AVX512BW_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
944 CPU_AVX512VL_FLAGS
, 0 },
945 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
948 CPU_VMFUNC_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
952 CPU_XSAVE_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
954 CPU_XSAVEOPT_FLAGS
, 0 },
955 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
956 CPU_XSAVEC_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
958 CPU_XSAVES_FLAGS
, 0 },
959 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
961 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
962 CPU_PCLMUL_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
964 CPU_PCLMUL_FLAGS
, 1 },
965 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
966 CPU_FSGSBASE_FLAGS
, 0 },
967 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
968 CPU_RDRND_FLAGS
, 0 },
969 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
977 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
982 CPU_MOVBE_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
988 CPU_LZCNT_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
991 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
994 CPU_INVPCID_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
996 CPU_CLFLUSH_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
999 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1000 CPU_SYSCALL_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1002 CPU_RDTSCP_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1004 CPU_3DNOW_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1006 CPU_3DNOWA_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1008 CPU_PADLOCK_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1010 CPU_SVME_FLAGS
, 1 },
1011 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1012 CPU_SVME_FLAGS
, 0 },
1013 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1014 CPU_SSE4A_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1019 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1021 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1023 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1024 CPU_RDSEED_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1026 CPU_PRFCHW_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1028 CPU_SMAP_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1031 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1034 CPU_CLFLUSHOPT_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1036 CPU_PREFETCHWT1_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1039 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1040 CPU_CLWB_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1042 CPU_AVX512IFMA_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1044 CPU_AVX512VBMI_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1046 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1052 CPU_AVX512_VBMI2_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX512_VNNI_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512_BITALG_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1058 CPU_CLZERO_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1060 CPU_MWAITX_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1062 CPU_OSPKE_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1064 CPU_RDPID_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1066 CPU_PTWRITE_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1070 CPU_SHSTK_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1072 CPU_GFNI_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1074 CPU_VAES_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1076 CPU_VPCLMULQDQ_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1078 CPU_WBNOINVD_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1080 CPU_PCONFIG_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1082 CPU_WAITPKG_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1084 CPU_CLDEMOTE_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1086 CPU_MOVDIRI_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1088 CPU_MOVDIR64B_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1090 CPU_AVX512_BF16_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1092 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1094 CPU_ENQCMD_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1096 CPU_RDPRU_FLAGS
, 0 },
1097 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1098 CPU_MCOMMIT_FLAGS
, 0 },
1101 static const noarch_entry cpu_noarch
[] =
1103 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1104 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1105 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1106 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1107 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1108 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1109 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1110 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1111 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1112 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1113 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1114 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1115 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1116 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1120 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1121 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1122 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1123 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1124 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1125 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1126 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1127 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1128 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1129 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1130 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1131 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1132 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1133 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1134 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1135 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1136 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1137 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1138 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1139 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1140 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1144 /* Like s_lcomm_internal in gas/read.c but the alignment string
1145 is allowed to be optional. */
1148 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1155 && *input_line_pointer
== ',')
1157 align
= parse_align (needs_align
- 1);
1159 if (align
== (addressT
) -1)
1174 bss_alloc (symbolP
, size
, align
);
1179 pe_lcomm (int needs_align
)
1181 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1185 const pseudo_typeS md_pseudo_table
[] =
1187 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1188 {"align", s_align_bytes
, 0},
1190 {"align", s_align_ptwo
, 0},
1192 {"arch", set_cpu_arch
, 0},
1196 {"lcomm", pe_lcomm
, 1},
1198 {"ffloat", float_cons
, 'f'},
1199 {"dfloat", float_cons
, 'd'},
1200 {"tfloat", float_cons
, 'x'},
1202 {"slong", signed_cons
, 4},
1203 {"noopt", s_ignore
, 0},
1204 {"optim", s_ignore
, 0},
1205 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1206 {"code16", set_code_flag
, CODE_16BIT
},
1207 {"code32", set_code_flag
, CODE_32BIT
},
1209 {"code64", set_code_flag
, CODE_64BIT
},
1211 {"intel_syntax", set_intel_syntax
, 1},
1212 {"att_syntax", set_intel_syntax
, 0},
1213 {"intel_mnemonic", set_intel_mnemonic
, 1},
1214 {"att_mnemonic", set_intel_mnemonic
, 0},
1215 {"allow_index_reg", set_allow_index_reg
, 1},
1216 {"disallow_index_reg", set_allow_index_reg
, 0},
1217 {"sse_check", set_check
, 0},
1218 {"operand_check", set_check
, 1},
1219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1220 {"largecomm", handle_large_common
, 0},
1222 {"file", dwarf2_directive_file
, 0},
1223 {"loc", dwarf2_directive_loc
, 0},
1224 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1227 {"secrel32", pe_directive_secrel
, 0},
1232 /* For interface with expression (). */
1233 extern char *input_line_pointer
;
1235 /* Hash table for instruction mnemonic lookup. */
1236 static struct hash_control
*op_hash
;
1238 /* Hash table for register lookup. */
1239 static struct hash_control
*reg_hash
;
1241 /* Various efficient no-op patterns for aligning code labels.
1242 Note: Don't try to assemble the instructions in the comments.
1243 0L and 0w are not legal. */
1244 static const unsigned char f32_1
[] =
1246 static const unsigned char f32_2
[] =
1247 {0x66,0x90}; /* xchg %ax,%ax */
1248 static const unsigned char f32_3
[] =
1249 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1250 static const unsigned char f32_4
[] =
1251 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1252 static const unsigned char f32_6
[] =
1253 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1254 static const unsigned char f32_7
[] =
1255 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1256 static const unsigned char f16_3
[] =
1257 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1258 static const unsigned char f16_4
[] =
1259 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1260 static const unsigned char jump_disp8
[] =
1261 {0xeb}; /* jmp disp8 */
1262 static const unsigned char jump32_disp32
[] =
1263 {0xe9}; /* jmp disp32 */
1264 static const unsigned char jump16_disp32
[] =
1265 {0x66,0xe9}; /* jmp disp32 */
1266 /* 32-bit NOPs patterns. */
1267 static const unsigned char *const f32_patt
[] = {
1268 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1270 /* 16-bit NOPs patterns. */
1271 static const unsigned char *const f16_patt
[] = {
1272 f32_1
, f32_2
, f16_3
, f16_4
1274 /* nopl (%[re]ax) */
1275 static const unsigned char alt_3
[] =
1277 /* nopl 0(%[re]ax) */
1278 static const unsigned char alt_4
[] =
1279 {0x0f,0x1f,0x40,0x00};
1280 /* nopl 0(%[re]ax,%[re]ax,1) */
1281 static const unsigned char alt_5
[] =
1282 {0x0f,0x1f,0x44,0x00,0x00};
1283 /* nopw 0(%[re]ax,%[re]ax,1) */
1284 static const unsigned char alt_6
[] =
1285 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1286 /* nopl 0L(%[re]ax) */
1287 static const unsigned char alt_7
[] =
1288 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1289 /* nopl 0L(%[re]ax,%[re]ax,1) */
1290 static const unsigned char alt_8
[] =
1291 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1292 /* nopw 0L(%[re]ax,%[re]ax,1) */
1293 static const unsigned char alt_9
[] =
1294 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1295 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1296 static const unsigned char alt_10
[] =
1297 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1298 /* data16 nopw %cs:0L(%eax,%eax,1) */
1299 static const unsigned char alt_11
[] =
1300 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1301 /* 32-bit and 64-bit NOPs patterns. */
1302 static const unsigned char *const alt_patt
[] = {
1303 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1304 alt_9
, alt_10
, alt_11
1307 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1308 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1311 i386_output_nops (char *where
, const unsigned char *const *patt
,
1312 int count
, int max_single_nop_size
)
1315 /* Place the longer NOP first. */
1318 const unsigned char *nops
;
1320 if (max_single_nop_size
< 1)
1322 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1323 max_single_nop_size
);
1327 nops
= patt
[max_single_nop_size
- 1];
1329 /* Use the smaller one if the requsted one isn't available. */
1332 max_single_nop_size
--;
1333 nops
= patt
[max_single_nop_size
- 1];
1336 last
= count
% max_single_nop_size
;
1339 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1340 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1344 nops
= patt
[last
- 1];
1347 /* Use the smaller one plus one-byte NOP if the needed one
1350 nops
= patt
[last
- 1];
1351 memcpy (where
+ offset
, nops
, last
);
1352 where
[offset
+ last
] = *patt
[0];
1355 memcpy (where
+ offset
, nops
, last
);
1360 fits_in_imm7 (offsetT num
)
1362 return (num
& 0x7f) == num
;
1366 fits_in_imm31 (offsetT num
)
1368 return (num
& 0x7fffffff) == num
;
1371 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1372 single NOP instruction LIMIT. */
1375 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1377 const unsigned char *const *patt
= NULL
;
1378 int max_single_nop_size
;
1379 /* Maximum number of NOPs before switching to jump over NOPs. */
1380 int max_number_of_nops
;
1382 switch (fragP
->fr_type
)
1391 /* We need to decide which NOP sequence to use for 32bit and
1392 64bit. When -mtune= is used:
1394 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1395 PROCESSOR_GENERIC32, f32_patt will be used.
1396 2. For the rest, alt_patt will be used.
1398 When -mtune= isn't used, alt_patt will be used if
1399 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1402 When -march= or .arch is used, we can't use anything beyond
1403 cpu_arch_isa_flags. */
1405 if (flag_code
== CODE_16BIT
)
1408 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1409 /* Limit number of NOPs to 2 in 16-bit mode. */
1410 max_number_of_nops
= 2;
1414 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1416 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1417 switch (cpu_arch_tune
)
1419 case PROCESSOR_UNKNOWN
:
1420 /* We use cpu_arch_isa_flags to check if we SHOULD
1421 optimize with nops. */
1422 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1427 case PROCESSOR_PENTIUM4
:
1428 case PROCESSOR_NOCONA
:
1429 case PROCESSOR_CORE
:
1430 case PROCESSOR_CORE2
:
1431 case PROCESSOR_COREI7
:
1432 case PROCESSOR_L1OM
:
1433 case PROCESSOR_K1OM
:
1434 case PROCESSOR_GENERIC64
:
1436 case PROCESSOR_ATHLON
:
1438 case PROCESSOR_AMDFAM10
:
1440 case PROCESSOR_ZNVER
:
1444 case PROCESSOR_I386
:
1445 case PROCESSOR_I486
:
1446 case PROCESSOR_PENTIUM
:
1447 case PROCESSOR_PENTIUMPRO
:
1448 case PROCESSOR_IAMCU
:
1449 case PROCESSOR_GENERIC32
:
1456 switch (fragP
->tc_frag_data
.tune
)
1458 case PROCESSOR_UNKNOWN
:
1459 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1460 PROCESSOR_UNKNOWN. */
1464 case PROCESSOR_I386
:
1465 case PROCESSOR_I486
:
1466 case PROCESSOR_PENTIUM
:
1467 case PROCESSOR_IAMCU
:
1469 case PROCESSOR_ATHLON
:
1471 case PROCESSOR_AMDFAM10
:
1473 case PROCESSOR_ZNVER
:
1475 case PROCESSOR_GENERIC32
:
1476 /* We use cpu_arch_isa_flags to check if we CAN optimize
1478 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1483 case PROCESSOR_PENTIUMPRO
:
1484 case PROCESSOR_PENTIUM4
:
1485 case PROCESSOR_NOCONA
:
1486 case PROCESSOR_CORE
:
1487 case PROCESSOR_CORE2
:
1488 case PROCESSOR_COREI7
:
1489 case PROCESSOR_L1OM
:
1490 case PROCESSOR_K1OM
:
1491 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1496 case PROCESSOR_GENERIC64
:
1502 if (patt
== f32_patt
)
1504 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1505 /* Limit number of NOPs to 2 for older processors. */
1506 max_number_of_nops
= 2;
1510 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1511 /* Limit number of NOPs to 7 for newer processors. */
1512 max_number_of_nops
= 7;
1517 limit
= max_single_nop_size
;
1519 if (fragP
->fr_type
== rs_fill_nop
)
1521 /* Output NOPs for .nop directive. */
1522 if (limit
> max_single_nop_size
)
1524 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1525 _("invalid single nop size: %d "
1526 "(expect within [0, %d])"),
1527 limit
, max_single_nop_size
);
1532 fragP
->fr_var
= count
;
1534 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1536 /* Generate jump over NOPs. */
1537 offsetT disp
= count
- 2;
1538 if (fits_in_imm7 (disp
))
1540 /* Use "jmp disp8" if possible. */
1542 where
[0] = jump_disp8
[0];
1548 unsigned int size_of_jump
;
1550 if (flag_code
== CODE_16BIT
)
1552 where
[0] = jump16_disp32
[0];
1553 where
[1] = jump16_disp32
[1];
1558 where
[0] = jump32_disp32
[0];
1562 count
-= size_of_jump
+ 4;
1563 if (!fits_in_imm31 (count
))
1565 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1566 _("jump over nop padding out of range"));
1570 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1571 where
+= size_of_jump
+ 4;
1575 /* Generate multiple NOPs. */
1576 i386_output_nops (where
, patt
, count
, limit
);
1580 operand_type_all_zero (const union i386_operand_type
*x
)
1582 switch (ARRAY_SIZE(x
->array
))
1593 return !x
->array
[0];
1600 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1602 switch (ARRAY_SIZE(x
->array
))
1618 x
->bitfield
.class = ClassNone
;
1619 x
->bitfield
.instance
= InstanceNone
;
1623 operand_type_equal (const union i386_operand_type
*x
,
1624 const union i386_operand_type
*y
)
1626 switch (ARRAY_SIZE(x
->array
))
1629 if (x
->array
[2] != y
->array
[2])
1633 if (x
->array
[1] != y
->array
[1])
1637 return x
->array
[0] == y
->array
[0];
1645 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1647 switch (ARRAY_SIZE(x
->array
))
1662 return !x
->array
[0];
1669 cpu_flags_equal (const union i386_cpu_flags
*x
,
1670 const union i386_cpu_flags
*y
)
1672 switch (ARRAY_SIZE(x
->array
))
1675 if (x
->array
[3] != y
->array
[3])
1679 if (x
->array
[2] != y
->array
[2])
1683 if (x
->array
[1] != y
->array
[1])
1687 return x
->array
[0] == y
->array
[0];
1695 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1697 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1698 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1701 static INLINE i386_cpu_flags
1702 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1704 switch (ARRAY_SIZE (x
.array
))
1707 x
.array
[3] &= y
.array
[3];
1710 x
.array
[2] &= y
.array
[2];
1713 x
.array
[1] &= y
.array
[1];
1716 x
.array
[0] &= y
.array
[0];
1724 static INLINE i386_cpu_flags
1725 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1727 switch (ARRAY_SIZE (x
.array
))
1730 x
.array
[3] |= y
.array
[3];
1733 x
.array
[2] |= y
.array
[2];
1736 x
.array
[1] |= y
.array
[1];
1739 x
.array
[0] |= y
.array
[0];
1747 static INLINE i386_cpu_flags
1748 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1750 switch (ARRAY_SIZE (x
.array
))
1753 x
.array
[3] &= ~y
.array
[3];
1756 x
.array
[2] &= ~y
.array
[2];
1759 x
.array
[1] &= ~y
.array
[1];
1762 x
.array
[0] &= ~y
.array
[0];
1770 #define CPU_FLAGS_ARCH_MATCH 0x1
1771 #define CPU_FLAGS_64BIT_MATCH 0x2
1773 #define CPU_FLAGS_PERFECT_MATCH \
1774 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1776 /* Return CPU flags match bits. */
1779 cpu_flags_match (const insn_template
*t
)
1781 i386_cpu_flags x
= t
->cpu_flags
;
1782 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1784 x
.bitfield
.cpu64
= 0;
1785 x
.bitfield
.cpuno64
= 0;
1787 if (cpu_flags_all_zero (&x
))
1789 /* This instruction is available on all archs. */
1790 match
|= CPU_FLAGS_ARCH_MATCH
;
1794 /* This instruction is available only on some archs. */
1795 i386_cpu_flags cpu
= cpu_arch_flags
;
1797 /* AVX512VL is no standalone feature - match it and then strip it. */
1798 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1800 x
.bitfield
.cpuavx512vl
= 0;
1802 cpu
= cpu_flags_and (x
, cpu
);
1803 if (!cpu_flags_all_zero (&cpu
))
1805 if (x
.bitfield
.cpuavx
)
1807 /* We need to check a few extra flags with AVX. */
1808 if (cpu
.bitfield
.cpuavx
1809 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1810 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1811 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1812 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1813 match
|= CPU_FLAGS_ARCH_MATCH
;
1815 else if (x
.bitfield
.cpuavx512f
)
1817 /* We need to check a few extra flags with AVX512F. */
1818 if (cpu
.bitfield
.cpuavx512f
1819 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1820 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1821 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1822 match
|= CPU_FLAGS_ARCH_MATCH
;
1825 match
|= CPU_FLAGS_ARCH_MATCH
;
1831 static INLINE i386_operand_type
1832 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1834 if (x
.bitfield
.class != y
.bitfield
.class)
1835 x
.bitfield
.class = ClassNone
;
1836 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1837 x
.bitfield
.instance
= InstanceNone
;
1839 switch (ARRAY_SIZE (x
.array
))
1842 x
.array
[2] &= y
.array
[2];
1845 x
.array
[1] &= y
.array
[1];
1848 x
.array
[0] &= y
.array
[0];
1856 static INLINE i386_operand_type
1857 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1859 gas_assert (y
.bitfield
.class == ClassNone
);
1860 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1862 switch (ARRAY_SIZE (x
.array
))
1865 x
.array
[2] &= ~y
.array
[2];
1868 x
.array
[1] &= ~y
.array
[1];
1871 x
.array
[0] &= ~y
.array
[0];
1879 static INLINE i386_operand_type
1880 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1882 gas_assert (x
.bitfield
.class == ClassNone
||
1883 y
.bitfield
.class == ClassNone
||
1884 x
.bitfield
.class == y
.bitfield
.class);
1885 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1886 y
.bitfield
.instance
== InstanceNone
||
1887 x
.bitfield
.instance
== y
.bitfield
.instance
);
1889 switch (ARRAY_SIZE (x
.array
))
1892 x
.array
[2] |= y
.array
[2];
1895 x
.array
[1] |= y
.array
[1];
1898 x
.array
[0] |= y
.array
[0];
1906 static INLINE i386_operand_type
1907 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1909 gas_assert (y
.bitfield
.class == ClassNone
);
1910 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1912 switch (ARRAY_SIZE (x
.array
))
1915 x
.array
[2] ^= y
.array
[2];
1918 x
.array
[1] ^= y
.array
[1];
1921 x
.array
[0] ^= y
.array
[0];
1929 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1930 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1931 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1932 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1933 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
1934 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
1935 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1936 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1937 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1938 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1939 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1940 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1941 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1942 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1943 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1944 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1945 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1956 operand_type_check (i386_operand_type t
, enum operand_type c
)
1961 return t
.bitfield
.class == Reg
;
1964 return (t
.bitfield
.imm8
1968 || t
.bitfield
.imm32s
1969 || t
.bitfield
.imm64
);
1972 return (t
.bitfield
.disp8
1973 || t
.bitfield
.disp16
1974 || t
.bitfield
.disp32
1975 || t
.bitfield
.disp32s
1976 || t
.bitfield
.disp64
);
1979 return (t
.bitfield
.disp8
1980 || t
.bitfield
.disp16
1981 || t
.bitfield
.disp32
1982 || t
.bitfield
.disp32s
1983 || t
.bitfield
.disp64
1984 || t
.bitfield
.baseindex
);
1993 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1994 between operand GIVEN and opeand WANTED for instruction template T. */
1997 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2000 return !((i
.types
[given
].bitfield
.byte
2001 && !t
->operand_types
[wanted
].bitfield
.byte
)
2002 || (i
.types
[given
].bitfield
.word
2003 && !t
->operand_types
[wanted
].bitfield
.word
)
2004 || (i
.types
[given
].bitfield
.dword
2005 && !t
->operand_types
[wanted
].bitfield
.dword
)
2006 || (i
.types
[given
].bitfield
.qword
2007 && !t
->operand_types
[wanted
].bitfield
.qword
)
2008 || (i
.types
[given
].bitfield
.tbyte
2009 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2012 /* Return 1 if there is no conflict in SIMD register between operand
2013 GIVEN and opeand WANTED for instruction template T. */
2016 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2019 return !((i
.types
[given
].bitfield
.xmmword
2020 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2021 || (i
.types
[given
].bitfield
.ymmword
2022 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2023 || (i
.types
[given
].bitfield
.zmmword
2024 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2027 /* Return 1 if there is no conflict in any size between operand GIVEN
2028 and opeand WANTED for instruction template T. */
2031 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2034 return (match_operand_size (t
, wanted
, given
)
2035 && !((i
.types
[given
].bitfield
.unspecified
2037 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2038 || (i
.types
[given
].bitfield
.fword
2039 && !t
->operand_types
[wanted
].bitfield
.fword
)
2040 /* For scalar opcode templates to allow register and memory
2041 operands at the same time, some special casing is needed
2042 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2043 down-conversion vpmov*. */
2044 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2045 && !t
->opcode_modifier
.broadcast
2046 && (t
->operand_types
[wanted
].bitfield
.byte
2047 || t
->operand_types
[wanted
].bitfield
.word
2048 || t
->operand_types
[wanted
].bitfield
.dword
2049 || t
->operand_types
[wanted
].bitfield
.qword
))
2050 ? (i
.types
[given
].bitfield
.xmmword
2051 || i
.types
[given
].bitfield
.ymmword
2052 || i
.types
[given
].bitfield
.zmmword
)
2053 : !match_simd_size(t
, wanted
, given
))));
2056 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2057 operands for instruction template T, and it has MATCH_REVERSE set if there
2058 is no size conflict on any operands for the template with operands reversed
2059 (and the template allows for reversing in the first place). */
2061 #define MATCH_STRAIGHT 1
2062 #define MATCH_REVERSE 2
2064 static INLINE
unsigned int
2065 operand_size_match (const insn_template
*t
)
2067 unsigned int j
, match
= MATCH_STRAIGHT
;
2069 /* Don't check non-absolute jump instructions. */
2070 if (t
->opcode_modifier
.jump
2071 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2074 /* Check memory and accumulator operand size. */
2075 for (j
= 0; j
< i
.operands
; j
++)
2077 if (i
.types
[j
].bitfield
.class != Reg
2078 && i
.types
[j
].bitfield
.class != RegSIMD
2079 && t
->opcode_modifier
.anysize
)
2082 if (t
->operand_types
[j
].bitfield
.class == Reg
2083 && !match_operand_size (t
, j
, j
))
2089 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2090 && !match_simd_size (t
, j
, j
))
2096 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2097 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2103 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2110 if (!t
->opcode_modifier
.d
)
2114 i
.error
= operand_size_mismatch
;
2118 /* Check reverse. */
2119 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2121 for (j
= 0; j
< i
.operands
; j
++)
2123 unsigned int given
= i
.operands
- j
- 1;
2125 if (t
->operand_types
[j
].bitfield
.class == Reg
2126 && !match_operand_size (t
, j
, given
))
2129 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2130 && !match_simd_size (t
, j
, given
))
2133 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2134 && (!match_operand_size (t
, j
, given
)
2135 || !match_simd_size (t
, j
, given
)))
2138 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2142 return match
| MATCH_REVERSE
;
2146 operand_type_match (i386_operand_type overlap
,
2147 i386_operand_type given
)
2149 i386_operand_type temp
= overlap
;
2151 temp
.bitfield
.unspecified
= 0;
2152 temp
.bitfield
.byte
= 0;
2153 temp
.bitfield
.word
= 0;
2154 temp
.bitfield
.dword
= 0;
2155 temp
.bitfield
.fword
= 0;
2156 temp
.bitfield
.qword
= 0;
2157 temp
.bitfield
.tbyte
= 0;
2158 temp
.bitfield
.xmmword
= 0;
2159 temp
.bitfield
.ymmword
= 0;
2160 temp
.bitfield
.zmmword
= 0;
2161 if (operand_type_all_zero (&temp
))
2164 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2168 i
.error
= operand_type_mismatch
;
2172 /* If given types g0 and g1 are registers they must be of the same type
2173 unless the expected operand type register overlap is null.
2174 Memory operand size of certain SIMD instructions is also being checked
2178 operand_type_register_match (i386_operand_type g0
,
2179 i386_operand_type t0
,
2180 i386_operand_type g1
,
2181 i386_operand_type t1
)
2183 if (g0
.bitfield
.class != Reg
2184 && g0
.bitfield
.class != RegSIMD
2185 && (!operand_type_check (g0
, anymem
)
2186 || g0
.bitfield
.unspecified
2187 || t0
.bitfield
.class != RegSIMD
))
2190 if (g1
.bitfield
.class != Reg
2191 && g1
.bitfield
.class != RegSIMD
2192 && (!operand_type_check (g1
, anymem
)
2193 || g1
.bitfield
.unspecified
2194 || t1
.bitfield
.class != RegSIMD
))
2197 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2198 && g0
.bitfield
.word
== g1
.bitfield
.word
2199 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2200 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2201 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2202 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2203 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2206 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2207 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2208 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2209 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2210 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2211 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2212 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2215 i
.error
= register_type_mismatch
;
2220 static INLINE
unsigned int
2221 register_number (const reg_entry
*r
)
2223 unsigned int nr
= r
->reg_num
;
2225 if (r
->reg_flags
& RegRex
)
2228 if (r
->reg_flags
& RegVRex
)
2234 static INLINE
unsigned int
2235 mode_from_disp_size (i386_operand_type t
)
2237 if (t
.bitfield
.disp8
)
2239 else if (t
.bitfield
.disp16
2240 || t
.bitfield
.disp32
2241 || t
.bitfield
.disp32s
)
2248 fits_in_signed_byte (addressT num
)
2250 return num
+ 0x80 <= 0xff;
2254 fits_in_unsigned_byte (addressT num
)
2260 fits_in_unsigned_word (addressT num
)
2262 return num
<= 0xffff;
2266 fits_in_signed_word (addressT num
)
2268 return num
+ 0x8000 <= 0xffff;
2272 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2277 return num
+ 0x80000000 <= 0xffffffff;
2279 } /* fits_in_signed_long() */
2282 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2287 return num
<= 0xffffffff;
2289 } /* fits_in_unsigned_long() */
2292 fits_in_disp8 (offsetT num
)
2294 int shift
= i
.memshift
;
2300 mask
= (1 << shift
) - 1;
2302 /* Return 0 if NUM isn't properly aligned. */
2306 /* Check if NUM will fit in 8bit after shift. */
2307 return fits_in_signed_byte (num
>> shift
);
2311 fits_in_imm4 (offsetT num
)
2313 return (num
& 0xf) == num
;
2316 static i386_operand_type
2317 smallest_imm_type (offsetT num
)
2319 i386_operand_type t
;
2321 operand_type_set (&t
, 0);
2322 t
.bitfield
.imm64
= 1;
2324 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2326 /* This code is disabled on the 486 because all the Imm1 forms
2327 in the opcode table are slower on the i486. They're the
2328 versions with the implicitly specified single-position
2329 displacement, which has another syntax if you really want to
2331 t
.bitfield
.imm1
= 1;
2332 t
.bitfield
.imm8
= 1;
2333 t
.bitfield
.imm8s
= 1;
2334 t
.bitfield
.imm16
= 1;
2335 t
.bitfield
.imm32
= 1;
2336 t
.bitfield
.imm32s
= 1;
2338 else if (fits_in_signed_byte (num
))
2340 t
.bitfield
.imm8
= 1;
2341 t
.bitfield
.imm8s
= 1;
2342 t
.bitfield
.imm16
= 1;
2343 t
.bitfield
.imm32
= 1;
2344 t
.bitfield
.imm32s
= 1;
2346 else if (fits_in_unsigned_byte (num
))
2348 t
.bitfield
.imm8
= 1;
2349 t
.bitfield
.imm16
= 1;
2350 t
.bitfield
.imm32
= 1;
2351 t
.bitfield
.imm32s
= 1;
2353 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2355 t
.bitfield
.imm16
= 1;
2356 t
.bitfield
.imm32
= 1;
2357 t
.bitfield
.imm32s
= 1;
2359 else if (fits_in_signed_long (num
))
2361 t
.bitfield
.imm32
= 1;
2362 t
.bitfield
.imm32s
= 1;
2364 else if (fits_in_unsigned_long (num
))
2365 t
.bitfield
.imm32
= 1;
2371 offset_in_range (offsetT val
, int size
)
2377 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2378 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2379 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2381 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2387 /* If BFD64, sign extend val for 32bit address mode. */
2388 if (flag_code
!= CODE_64BIT
2389 || i
.prefix
[ADDR_PREFIX
])
2390 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2391 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2394 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2396 char buf1
[40], buf2
[40];
2398 sprint_value (buf1
, val
);
2399 sprint_value (buf2
, val
& mask
);
2400 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2415 a. PREFIX_EXIST if attempting to add a prefix where one from the
2416 same class already exists.
2417 b. PREFIX_LOCK if lock prefix is added.
2418 c. PREFIX_REP if rep/repne prefix is added.
2419 d. PREFIX_DS if ds prefix is added.
2420 e. PREFIX_OTHER if other prefix is added.
2423 static enum PREFIX_GROUP
2424 add_prefix (unsigned int prefix
)
2426 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2429 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2430 && flag_code
== CODE_64BIT
)
2432 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2433 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2434 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2435 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2446 case DS_PREFIX_OPCODE
:
2449 case CS_PREFIX_OPCODE
:
2450 case ES_PREFIX_OPCODE
:
2451 case FS_PREFIX_OPCODE
:
2452 case GS_PREFIX_OPCODE
:
2453 case SS_PREFIX_OPCODE
:
2457 case REPNE_PREFIX_OPCODE
:
2458 case REPE_PREFIX_OPCODE
:
2463 case LOCK_PREFIX_OPCODE
:
2472 case ADDR_PREFIX_OPCODE
:
2476 case DATA_PREFIX_OPCODE
:
2480 if (i
.prefix
[q
] != 0)
2488 i
.prefix
[q
] |= prefix
;
2491 as_bad (_("same type of prefix used twice"));
2497 update_code_flag (int value
, int check
)
2499 PRINTF_LIKE ((*as_error
));
2501 flag_code
= (enum flag_code
) value
;
2502 if (flag_code
== CODE_64BIT
)
2504 cpu_arch_flags
.bitfield
.cpu64
= 1;
2505 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2509 cpu_arch_flags
.bitfield
.cpu64
= 0;
2510 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2512 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2515 as_error
= as_fatal
;
2518 (*as_error
) (_("64bit mode not supported on `%s'."),
2519 cpu_arch_name
? cpu_arch_name
: default_arch
);
2521 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2524 as_error
= as_fatal
;
2527 (*as_error
) (_("32bit mode not supported on `%s'."),
2528 cpu_arch_name
? cpu_arch_name
: default_arch
);
2530 stackop_size
= '\0';
2534 set_code_flag (int value
)
2536 update_code_flag (value
, 0);
2540 set_16bit_gcc_code_flag (int new_code_flag
)
2542 flag_code
= (enum flag_code
) new_code_flag
;
2543 if (flag_code
!= CODE_16BIT
)
2545 cpu_arch_flags
.bitfield
.cpu64
= 0;
2546 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2547 stackop_size
= LONG_MNEM_SUFFIX
;
2551 set_intel_syntax (int syntax_flag
)
2553 /* Find out if register prefixing is specified. */
2554 int ask_naked_reg
= 0;
2557 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2560 int e
= get_symbol_name (&string
);
2562 if (strcmp (string
, "prefix") == 0)
2564 else if (strcmp (string
, "noprefix") == 0)
2567 as_bad (_("bad argument to syntax directive."));
2568 (void) restore_line_pointer (e
);
2570 demand_empty_rest_of_line ();
2572 intel_syntax
= syntax_flag
;
2574 if (ask_naked_reg
== 0)
2575 allow_naked_reg
= (intel_syntax
2576 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2578 allow_naked_reg
= (ask_naked_reg
< 0);
2580 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2582 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2583 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2584 register_prefix
= allow_naked_reg
? "" : "%";
2588 set_intel_mnemonic (int mnemonic_flag
)
2590 intel_mnemonic
= mnemonic_flag
;
2594 set_allow_index_reg (int flag
)
2596 allow_index_reg
= flag
;
2600 set_check (int what
)
2602 enum check_kind
*kind
;
2607 kind
= &operand_check
;
2618 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2621 int e
= get_symbol_name (&string
);
2623 if (strcmp (string
, "none") == 0)
2625 else if (strcmp (string
, "warning") == 0)
2626 *kind
= check_warning
;
2627 else if (strcmp (string
, "error") == 0)
2628 *kind
= check_error
;
2630 as_bad (_("bad argument to %s_check directive."), str
);
2631 (void) restore_line_pointer (e
);
2634 as_bad (_("missing argument for %s_check directive"), str
);
2636 demand_empty_rest_of_line ();
2640 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2641 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2643 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2644 static const char *arch
;
2646 /* Intel LIOM is only supported on ELF. */
2652 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2653 use default_arch. */
2654 arch
= cpu_arch_name
;
2656 arch
= default_arch
;
2659 /* If we are targeting Intel MCU, we must enable it. */
2660 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2661 || new_flag
.bitfield
.cpuiamcu
)
2664 /* If we are targeting Intel L1OM, we must enable it. */
2665 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2666 || new_flag
.bitfield
.cpul1om
)
2669 /* If we are targeting Intel K1OM, we must enable it. */
2670 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2671 || new_flag
.bitfield
.cpuk1om
)
2674 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2679 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2683 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2686 int e
= get_symbol_name (&string
);
2688 i386_cpu_flags flags
;
2690 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2692 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2694 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2698 cpu_arch_name
= cpu_arch
[j
].name
;
2699 cpu_sub_arch_name
= NULL
;
2700 cpu_arch_flags
= cpu_arch
[j
].flags
;
2701 if (flag_code
== CODE_64BIT
)
2703 cpu_arch_flags
.bitfield
.cpu64
= 1;
2704 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2708 cpu_arch_flags
.bitfield
.cpu64
= 0;
2709 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2711 cpu_arch_isa
= cpu_arch
[j
].type
;
2712 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2713 if (!cpu_arch_tune_set
)
2715 cpu_arch_tune
= cpu_arch_isa
;
2716 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2721 flags
= cpu_flags_or (cpu_arch_flags
,
2724 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2726 if (cpu_sub_arch_name
)
2728 char *name
= cpu_sub_arch_name
;
2729 cpu_sub_arch_name
= concat (name
,
2731 (const char *) NULL
);
2735 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2736 cpu_arch_flags
= flags
;
2737 cpu_arch_isa_flags
= flags
;
2741 = cpu_flags_or (cpu_arch_isa_flags
,
2743 (void) restore_line_pointer (e
);
2744 demand_empty_rest_of_line ();
2749 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2751 /* Disable an ISA extension. */
2752 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2753 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2755 flags
= cpu_flags_and_not (cpu_arch_flags
,
2756 cpu_noarch
[j
].flags
);
2757 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2759 if (cpu_sub_arch_name
)
2761 char *name
= cpu_sub_arch_name
;
2762 cpu_sub_arch_name
= concat (name
, string
,
2763 (const char *) NULL
);
2767 cpu_sub_arch_name
= xstrdup (string
);
2768 cpu_arch_flags
= flags
;
2769 cpu_arch_isa_flags
= flags
;
2771 (void) restore_line_pointer (e
);
2772 demand_empty_rest_of_line ();
2776 j
= ARRAY_SIZE (cpu_arch
);
2779 if (j
>= ARRAY_SIZE (cpu_arch
))
2780 as_bad (_("no such architecture: `%s'"), string
);
2782 *input_line_pointer
= e
;
2785 as_bad (_("missing cpu architecture"));
2787 no_cond_jump_promotion
= 0;
2788 if (*input_line_pointer
== ','
2789 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2794 ++input_line_pointer
;
2795 e
= get_symbol_name (&string
);
2797 if (strcmp (string
, "nojumps") == 0)
2798 no_cond_jump_promotion
= 1;
2799 else if (strcmp (string
, "jumps") == 0)
2802 as_bad (_("no such architecture modifier: `%s'"), string
);
2804 (void) restore_line_pointer (e
);
2807 demand_empty_rest_of_line ();
2810 enum bfd_architecture
2813 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2815 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2816 || flag_code
!= CODE_64BIT
)
2817 as_fatal (_("Intel L1OM is 64bit ELF only"));
2818 return bfd_arch_l1om
;
2820 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2822 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2823 || flag_code
!= CODE_64BIT
)
2824 as_fatal (_("Intel K1OM is 64bit ELF only"));
2825 return bfd_arch_k1om
;
2827 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2829 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2830 || flag_code
== CODE_64BIT
)
2831 as_fatal (_("Intel MCU is 32bit ELF only"));
2832 return bfd_arch_iamcu
;
2835 return bfd_arch_i386
;
2841 if (!strncmp (default_arch
, "x86_64", 6))
2843 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2845 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2846 || default_arch
[6] != '\0')
2847 as_fatal (_("Intel L1OM is 64bit ELF only"));
2848 return bfd_mach_l1om
;
2850 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2852 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2853 || default_arch
[6] != '\0')
2854 as_fatal (_("Intel K1OM is 64bit ELF only"));
2855 return bfd_mach_k1om
;
2857 else if (default_arch
[6] == '\0')
2858 return bfd_mach_x86_64
;
2860 return bfd_mach_x64_32
;
2862 else if (!strcmp (default_arch
, "i386")
2863 || !strcmp (default_arch
, "iamcu"))
2865 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2867 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2868 as_fatal (_("Intel MCU is 32bit ELF only"));
2869 return bfd_mach_i386_iamcu
;
2872 return bfd_mach_i386_i386
;
2875 as_fatal (_("unknown architecture"));
2881 const char *hash_err
;
2883 /* Support pseudo prefixes like {disp32}. */
2884 lex_type
['{'] = LEX_BEGIN_NAME
;
2886 /* Initialize op_hash hash table. */
2887 op_hash
= hash_new ();
2890 const insn_template
*optab
;
2891 templates
*core_optab
;
2893 /* Setup for loop. */
2895 core_optab
= XNEW (templates
);
2896 core_optab
->start
= optab
;
2901 if (optab
->name
== NULL
2902 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2904 /* different name --> ship out current template list;
2905 add to hash table; & begin anew. */
2906 core_optab
->end
= optab
;
2907 hash_err
= hash_insert (op_hash
,
2909 (void *) core_optab
);
2912 as_fatal (_("can't hash %s: %s"),
2916 if (optab
->name
== NULL
)
2918 core_optab
= XNEW (templates
);
2919 core_optab
->start
= optab
;
2924 /* Initialize reg_hash hash table. */
2925 reg_hash
= hash_new ();
2927 const reg_entry
*regtab
;
2928 unsigned int regtab_size
= i386_regtab_size
;
2930 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2932 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2934 as_fatal (_("can't hash %s: %s"),
2940 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2945 for (c
= 0; c
< 256; c
++)
2950 mnemonic_chars
[c
] = c
;
2951 register_chars
[c
] = c
;
2952 operand_chars
[c
] = c
;
2954 else if (ISLOWER (c
))
2956 mnemonic_chars
[c
] = c
;
2957 register_chars
[c
] = c
;
2958 operand_chars
[c
] = c
;
2960 else if (ISUPPER (c
))
2962 mnemonic_chars
[c
] = TOLOWER (c
);
2963 register_chars
[c
] = mnemonic_chars
[c
];
2964 operand_chars
[c
] = c
;
2966 else if (c
== '{' || c
== '}')
2968 mnemonic_chars
[c
] = c
;
2969 operand_chars
[c
] = c
;
2972 if (ISALPHA (c
) || ISDIGIT (c
))
2973 identifier_chars
[c
] = c
;
2976 identifier_chars
[c
] = c
;
2977 operand_chars
[c
] = c
;
2982 identifier_chars
['@'] = '@';
2985 identifier_chars
['?'] = '?';
2986 operand_chars
['?'] = '?';
2988 digit_chars
['-'] = '-';
2989 mnemonic_chars
['_'] = '_';
2990 mnemonic_chars
['-'] = '-';
2991 mnemonic_chars
['.'] = '.';
2992 identifier_chars
['_'] = '_';
2993 identifier_chars
['.'] = '.';
2995 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2996 operand_chars
[(unsigned char) *p
] = *p
;
2999 if (flag_code
== CODE_64BIT
)
3001 #if defined (OBJ_COFF) && defined (TE_PE)
3002 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3005 x86_dwarf2_return_column
= 16;
3007 x86_cie_data_alignment
= -8;
3011 x86_dwarf2_return_column
= 8;
3012 x86_cie_data_alignment
= -4;
3017 i386_print_statistics (FILE *file
)
3019 hash_print_statistics (file
, "i386 opcode", op_hash
);
3020 hash_print_statistics (file
, "i386 register", reg_hash
);
3025 /* Debugging routines for md_assemble. */
3026 static void pte (insn_template
*);
3027 static void pt (i386_operand_type
);
3028 static void pe (expressionS
*);
3029 static void ps (symbolS
*);
3032 pi (const char *line
, i386_insn
*x
)
3036 fprintf (stdout
, "%s: template ", line
);
3038 fprintf (stdout
, " address: base %s index %s scale %x\n",
3039 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3040 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3041 x
->log2_scale_factor
);
3042 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3043 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3044 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3045 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3046 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3047 (x
->rex
& REX_W
) != 0,
3048 (x
->rex
& REX_R
) != 0,
3049 (x
->rex
& REX_X
) != 0,
3050 (x
->rex
& REX_B
) != 0);
3051 for (j
= 0; j
< x
->operands
; j
++)
3053 fprintf (stdout
, " #%d: ", j
+ 1);
3055 fprintf (stdout
, "\n");
3056 if (x
->types
[j
].bitfield
.class == Reg
3057 || x
->types
[j
].bitfield
.class == RegMMX
3058 || x
->types
[j
].bitfield
.class == RegSIMD
3059 || x
->types
[j
].bitfield
.class == SReg
3060 || x
->types
[j
].bitfield
.class == RegCR
3061 || x
->types
[j
].bitfield
.class == RegDR
3062 || x
->types
[j
].bitfield
.class == RegTR
)
3063 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3064 if (operand_type_check (x
->types
[j
], imm
))
3066 if (operand_type_check (x
->types
[j
], disp
))
3067 pe (x
->op
[j
].disps
);
3072 pte (insn_template
*t
)
3075 fprintf (stdout
, " %d operands ", t
->operands
);
3076 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3077 if (t
->extension_opcode
!= None
)
3078 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3079 if (t
->opcode_modifier
.d
)
3080 fprintf (stdout
, "D");
3081 if (t
->opcode_modifier
.w
)
3082 fprintf (stdout
, "W");
3083 fprintf (stdout
, "\n");
3084 for (j
= 0; j
< t
->operands
; j
++)
3086 fprintf (stdout
, " #%d type ", j
+ 1);
3087 pt (t
->operand_types
[j
]);
3088 fprintf (stdout
, "\n");
3095 fprintf (stdout
, " operation %d\n", e
->X_op
);
3096 fprintf (stdout
, " add_number %ld (%lx)\n",
3097 (long) e
->X_add_number
, (long) e
->X_add_number
);
3098 if (e
->X_add_symbol
)
3100 fprintf (stdout
, " add_symbol ");
3101 ps (e
->X_add_symbol
);
3102 fprintf (stdout
, "\n");
3106 fprintf (stdout
, " op_symbol ");
3107 ps (e
->X_op_symbol
);
3108 fprintf (stdout
, "\n");
3115 fprintf (stdout
, "%s type %s%s",
3117 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3118 segment_name (S_GET_SEGMENT (s
)));
3121 static struct type_name
3123 i386_operand_type mask
;
3126 const type_names
[] =
3128 { OPERAND_TYPE_REG8
, "r8" },
3129 { OPERAND_TYPE_REG16
, "r16" },
3130 { OPERAND_TYPE_REG32
, "r32" },
3131 { OPERAND_TYPE_REG64
, "r64" },
3132 { OPERAND_TYPE_ACC8
, "acc8" },
3133 { OPERAND_TYPE_ACC16
, "acc16" },
3134 { OPERAND_TYPE_ACC32
, "acc32" },
3135 { OPERAND_TYPE_ACC64
, "acc64" },
3136 { OPERAND_TYPE_IMM8
, "i8" },
3137 { OPERAND_TYPE_IMM8
, "i8s" },
3138 { OPERAND_TYPE_IMM16
, "i16" },
3139 { OPERAND_TYPE_IMM32
, "i32" },
3140 { OPERAND_TYPE_IMM32S
, "i32s" },
3141 { OPERAND_TYPE_IMM64
, "i64" },
3142 { OPERAND_TYPE_IMM1
, "i1" },
3143 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3144 { OPERAND_TYPE_DISP8
, "d8" },
3145 { OPERAND_TYPE_DISP16
, "d16" },
3146 { OPERAND_TYPE_DISP32
, "d32" },
3147 { OPERAND_TYPE_DISP32S
, "d32s" },
3148 { OPERAND_TYPE_DISP64
, "d64" },
3149 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3150 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3151 { OPERAND_TYPE_CONTROL
, "control reg" },
3152 { OPERAND_TYPE_TEST
, "test reg" },
3153 { OPERAND_TYPE_DEBUG
, "debug reg" },
3154 { OPERAND_TYPE_FLOATREG
, "FReg" },
3155 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3156 { OPERAND_TYPE_SREG
, "SReg" },
3157 { OPERAND_TYPE_REGMMX
, "rMMX" },
3158 { OPERAND_TYPE_REGXMM
, "rXMM" },
3159 { OPERAND_TYPE_REGYMM
, "rYMM" },
3160 { OPERAND_TYPE_REGZMM
, "rZMM" },
3161 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3165 pt (i386_operand_type t
)
3168 i386_operand_type a
;
3170 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3172 a
= operand_type_and (t
, type_names
[j
].mask
);
3173 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3174 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3179 #endif /* DEBUG386 */
3181 static bfd_reloc_code_real_type
3182 reloc (unsigned int size
,
3185 bfd_reloc_code_real_type other
)
3187 if (other
!= NO_RELOC
)
3189 reloc_howto_type
*rel
;
3194 case BFD_RELOC_X86_64_GOT32
:
3195 return BFD_RELOC_X86_64_GOT64
;
3197 case BFD_RELOC_X86_64_GOTPLT64
:
3198 return BFD_RELOC_X86_64_GOTPLT64
;
3200 case BFD_RELOC_X86_64_PLTOFF64
:
3201 return BFD_RELOC_X86_64_PLTOFF64
;
3203 case BFD_RELOC_X86_64_GOTPC32
:
3204 other
= BFD_RELOC_X86_64_GOTPC64
;
3206 case BFD_RELOC_X86_64_GOTPCREL
:
3207 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3209 case BFD_RELOC_X86_64_TPOFF32
:
3210 other
= BFD_RELOC_X86_64_TPOFF64
;
3212 case BFD_RELOC_X86_64_DTPOFF32
:
3213 other
= BFD_RELOC_X86_64_DTPOFF64
;
3219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3220 if (other
== BFD_RELOC_SIZE32
)
3223 other
= BFD_RELOC_SIZE64
;
3226 as_bad (_("there are no pc-relative size relocations"));
3232 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3233 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3236 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3238 as_bad (_("unknown relocation (%u)"), other
);
3239 else if (size
!= bfd_get_reloc_size (rel
))
3240 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3241 bfd_get_reloc_size (rel
),
3243 else if (pcrel
&& !rel
->pc_relative
)
3244 as_bad (_("non-pc-relative relocation for pc-relative field"));
3245 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3247 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3249 as_bad (_("relocated field and relocation type differ in signedness"));
3258 as_bad (_("there are no unsigned pc-relative relocations"));
3261 case 1: return BFD_RELOC_8_PCREL
;
3262 case 2: return BFD_RELOC_16_PCREL
;
3263 case 4: return BFD_RELOC_32_PCREL
;
3264 case 8: return BFD_RELOC_64_PCREL
;
3266 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3273 case 4: return BFD_RELOC_X86_64_32S
;
3278 case 1: return BFD_RELOC_8
;
3279 case 2: return BFD_RELOC_16
;
3280 case 4: return BFD_RELOC_32
;
3281 case 8: return BFD_RELOC_64
;
3283 as_bad (_("cannot do %s %u byte relocation"),
3284 sign
> 0 ? "signed" : "unsigned", size
);
3290 /* Here we decide which fixups can be adjusted to make them relative to
3291 the beginning of the section instead of the symbol. Basically we need
3292 to make sure that the dynamic relocations are done correctly, so in
3293 some cases we force the original symbol to be used. */
3296 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3298 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3302 /* Don't adjust pc-relative references to merge sections in 64-bit
3304 if (use_rela_relocations
3305 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3309 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3310 and changed later by validate_fix. */
3311 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3312 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3315 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3316 for size relocations. */
3317 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3318 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3319 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3320 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3321 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3322 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3323 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3324 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3325 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3326 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3327 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3328 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3329 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3330 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3331 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3332 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3333 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3334 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3335 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3336 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3337 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3338 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3339 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3340 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3341 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3342 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3343 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3344 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3345 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3346 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3347 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3348 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3349 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3356 intel_float_operand (const char *mnemonic
)
3358 /* Note that the value returned is meaningful only for opcodes with (memory)
3359 operands, hence the code here is free to improperly handle opcodes that
3360 have no operands (for better performance and smaller code). */
3362 if (mnemonic
[0] != 'f')
3363 return 0; /* non-math */
3365 switch (mnemonic
[1])
3367 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3368 the fs segment override prefix not currently handled because no
3369 call path can make opcodes without operands get here */
3371 return 2 /* integer op */;
3373 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3374 return 3; /* fldcw/fldenv */
3377 if (mnemonic
[2] != 'o' /* fnop */)
3378 return 3; /* non-waiting control op */
3381 if (mnemonic
[2] == 's')
3382 return 3; /* frstor/frstpm */
3385 if (mnemonic
[2] == 'a')
3386 return 3; /* fsave */
3387 if (mnemonic
[2] == 't')
3389 switch (mnemonic
[3])
3391 case 'c': /* fstcw */
3392 case 'd': /* fstdw */
3393 case 'e': /* fstenv */
3394 case 's': /* fsts[gw] */
3400 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3401 return 0; /* fxsave/fxrstor are not really math ops */
3408 /* Build the VEX prefix. */
3411 build_vex_prefix (const insn_template
*t
)
3413 unsigned int register_specifier
;
3414 unsigned int implied_prefix
;
3415 unsigned int vector_length
;
3418 /* Check register specifier. */
3419 if (i
.vex
.register_specifier
)
3421 register_specifier
=
3422 ~register_number (i
.vex
.register_specifier
) & 0xf;
3423 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3426 register_specifier
= 0xf;
3428 /* Use 2-byte VEX prefix by swapping destination and source operand
3429 if there are more than 1 register operand. */
3430 if (i
.reg_operands
> 1
3431 && i
.vec_encoding
!= vex_encoding_vex3
3432 && i
.dir_encoding
== dir_encoding_default
3433 && i
.operands
== i
.reg_operands
3434 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3435 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3436 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3439 unsigned int xchg
= i
.operands
- 1;
3440 union i386_op temp_op
;
3441 i386_operand_type temp_type
;
3443 temp_type
= i
.types
[xchg
];
3444 i
.types
[xchg
] = i
.types
[0];
3445 i
.types
[0] = temp_type
;
3446 temp_op
= i
.op
[xchg
];
3447 i
.op
[xchg
] = i
.op
[0];
3450 gas_assert (i
.rm
.mode
== 3);
3454 i
.rm
.regmem
= i
.rm
.reg
;
3457 if (i
.tm
.opcode_modifier
.d
)
3458 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3459 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3460 else /* Use the next insn. */
3464 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3465 are no memory operands and at least 3 register ones. */
3466 if (i
.reg_operands
>= 3
3467 && i
.vec_encoding
!= vex_encoding_vex3
3468 && i
.reg_operands
== i
.operands
- i
.imm_operands
3469 && i
.tm
.opcode_modifier
.vex
3470 && i
.tm
.opcode_modifier
.commutative
3471 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3473 && i
.vex
.register_specifier
3474 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3476 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3477 union i386_op temp_op
;
3478 i386_operand_type temp_type
;
3480 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3481 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3482 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3483 &i
.types
[i
.operands
- 3]));
3484 gas_assert (i
.rm
.mode
== 3);
3486 temp_type
= i
.types
[xchg
];
3487 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3488 i
.types
[xchg
+ 1] = temp_type
;
3489 temp_op
= i
.op
[xchg
];
3490 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3491 i
.op
[xchg
+ 1] = temp_op
;
3494 xchg
= i
.rm
.regmem
| 8;
3495 i
.rm
.regmem
= ~register_specifier
& 0xf;
3496 gas_assert (!(i
.rm
.regmem
& 8));
3497 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3498 register_specifier
= ~xchg
& 0xf;
3501 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3502 vector_length
= avxscalar
;
3503 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3509 /* Determine vector length from the last multi-length vector
3512 for (op
= t
->operands
; op
--;)
3513 if (t
->operand_types
[op
].bitfield
.xmmword
3514 && t
->operand_types
[op
].bitfield
.ymmword
3515 && i
.types
[op
].bitfield
.ymmword
)
3522 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3527 case DATA_PREFIX_OPCODE
:
3530 case REPE_PREFIX_OPCODE
:
3533 case REPNE_PREFIX_OPCODE
:
3540 /* Check the REX.W bit and VEXW. */
3541 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3542 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3543 else if (i
.tm
.opcode_modifier
.vexw
)
3544 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3546 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3548 /* Use 2-byte VEX prefix if possible. */
3550 && i
.vec_encoding
!= vex_encoding_vex3
3551 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3552 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3554 /* 2-byte VEX prefix. */
3558 i
.vex
.bytes
[0] = 0xc5;
3560 /* Check the REX.R bit. */
3561 r
= (i
.rex
& REX_R
) ? 0 : 1;
3562 i
.vex
.bytes
[1] = (r
<< 7
3563 | register_specifier
<< 3
3564 | vector_length
<< 2
3569 /* 3-byte VEX prefix. */
3574 switch (i
.tm
.opcode_modifier
.vexopcode
)
3578 i
.vex
.bytes
[0] = 0xc4;
3582 i
.vex
.bytes
[0] = 0xc4;
3586 i
.vex
.bytes
[0] = 0xc4;
3590 i
.vex
.bytes
[0] = 0x8f;
3594 i
.vex
.bytes
[0] = 0x8f;
3598 i
.vex
.bytes
[0] = 0x8f;
3604 /* The high 3 bits of the second VEX byte are 1's compliment
3605 of RXB bits from REX. */
3606 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3608 i
.vex
.bytes
[2] = (w
<< 7
3609 | register_specifier
<< 3
3610 | vector_length
<< 2
3615 static INLINE bfd_boolean
3616 is_evex_encoding (const insn_template
*t
)
3618 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3619 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3620 || t
->opcode_modifier
.sae
;
3623 static INLINE bfd_boolean
3624 is_any_vex_encoding (const insn_template
*t
)
3626 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3627 || is_evex_encoding (t
);
3630 /* Build the EVEX prefix. */
3633 build_evex_prefix (void)
3635 unsigned int register_specifier
;
3636 unsigned int implied_prefix
;
3638 rex_byte vrex_used
= 0;
3640 /* Check register specifier. */
3641 if (i
.vex
.register_specifier
)
3643 gas_assert ((i
.vrex
& REX_X
) == 0);
3645 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3646 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3647 register_specifier
+= 8;
3648 /* The upper 16 registers are encoded in the fourth byte of the
3650 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3651 i
.vex
.bytes
[3] = 0x8;
3652 register_specifier
= ~register_specifier
& 0xf;
3656 register_specifier
= 0xf;
3658 /* Encode upper 16 vector index register in the fourth byte of
3660 if (!(i
.vrex
& REX_X
))
3661 i
.vex
.bytes
[3] = 0x8;
3666 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3671 case DATA_PREFIX_OPCODE
:
3674 case REPE_PREFIX_OPCODE
:
3677 case REPNE_PREFIX_OPCODE
:
3684 /* 4 byte EVEX prefix. */
3686 i
.vex
.bytes
[0] = 0x62;
3689 switch (i
.tm
.opcode_modifier
.vexopcode
)
3705 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3707 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3709 /* The fifth bit of the second EVEX byte is 1's compliment of the
3710 REX_R bit in VREX. */
3711 if (!(i
.vrex
& REX_R
))
3712 i
.vex
.bytes
[1] |= 0x10;
3716 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3718 /* When all operands are registers, the REX_X bit in REX is not
3719 used. We reuse it to encode the upper 16 registers, which is
3720 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3721 as 1's compliment. */
3722 if ((i
.vrex
& REX_B
))
3725 i
.vex
.bytes
[1] &= ~0x40;
3729 /* EVEX instructions shouldn't need the REX prefix. */
3730 i
.vrex
&= ~vrex_used
;
3731 gas_assert (i
.vrex
== 0);
3733 /* Check the REX.W bit and VEXW. */
3734 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3735 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3736 else if (i
.tm
.opcode_modifier
.vexw
)
3737 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3739 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3741 /* Encode the U bit. */
3742 implied_prefix
|= 0x4;
3744 /* The third byte of the EVEX prefix. */
3745 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3747 /* The fourth byte of the EVEX prefix. */
3748 /* The zeroing-masking bit. */
3749 if (i
.mask
&& i
.mask
->zeroing
)
3750 i
.vex
.bytes
[3] |= 0x80;
3752 /* Don't always set the broadcast bit if there is no RC. */
3755 /* Encode the vector length. */
3756 unsigned int vec_length
;
3758 if (!i
.tm
.opcode_modifier
.evex
3759 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3763 /* Determine vector length from the last multi-length vector
3766 for (op
= i
.operands
; op
--;)
3767 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3768 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3769 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3771 if (i
.types
[op
].bitfield
.zmmword
)
3773 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3776 else if (i
.types
[op
].bitfield
.ymmword
)
3778 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3781 else if (i
.types
[op
].bitfield
.xmmword
)
3783 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3786 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3788 switch (i
.broadcast
->bytes
)
3791 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3794 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3797 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3806 if (op
>= MAX_OPERANDS
)
3810 switch (i
.tm
.opcode_modifier
.evex
)
3812 case EVEXLIG
: /* LL' is ignored */
3813 vec_length
= evexlig
<< 5;
3816 vec_length
= 0 << 5;
3819 vec_length
= 1 << 5;
3822 vec_length
= 2 << 5;
3828 i
.vex
.bytes
[3] |= vec_length
;
3829 /* Encode the broadcast bit. */
3831 i
.vex
.bytes
[3] |= 0x10;
3835 if (i
.rounding
->type
!= saeonly
)
3836 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3838 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3841 if (i
.mask
&& i
.mask
->mask
)
3842 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3846 process_immext (void)
3850 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3851 which is coded in the same place as an 8-bit immediate field
3852 would be. Here we fake an 8-bit immediate operand from the
3853 opcode suffix stored in tm.extension_opcode.
3855 AVX instructions also use this encoding, for some of
3856 3 argument instructions. */
3858 gas_assert (i
.imm_operands
<= 1
3860 || (is_any_vex_encoding (&i
.tm
)
3861 && i
.operands
<= 4)));
3863 exp
= &im_expressions
[i
.imm_operands
++];
3864 i
.op
[i
.operands
].imms
= exp
;
3865 i
.types
[i
.operands
] = imm8
;
3867 exp
->X_op
= O_constant
;
3868 exp
->X_add_number
= i
.tm
.extension_opcode
;
3869 i
.tm
.extension_opcode
= None
;
3876 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3881 as_bad (_("invalid instruction `%s' after `%s'"),
3882 i
.tm
.name
, i
.hle_prefix
);
3885 if (i
.prefix
[LOCK_PREFIX
])
3887 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3891 case HLEPrefixRelease
:
3892 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3894 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3898 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3900 as_bad (_("memory destination needed for instruction `%s'"
3901 " after `xrelease'"), i
.tm
.name
);
3908 /* Try the shortest encoding by shortening operand size. */
3911 optimize_encoding (void)
3915 if (optimize_for_space
3916 && i
.reg_operands
== 1
3917 && i
.imm_operands
== 1
3918 && !i
.types
[1].bitfield
.byte
3919 && i
.op
[0].imms
->X_op
== O_constant
3920 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3921 && ((i
.tm
.base_opcode
== 0xa8
3922 && i
.tm
.extension_opcode
== None
)
3923 || (i
.tm
.base_opcode
== 0xf6
3924 && i
.tm
.extension_opcode
== 0x0)))
3927 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3929 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3930 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3932 i
.types
[1].bitfield
.byte
= 1;
3933 /* Ignore the suffix. */
3935 if (base_regnum
>= 4
3936 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3938 /* Handle SP, BP, SI and DI registers. */
3939 if (i
.types
[1].bitfield
.word
)
3941 else if (i
.types
[1].bitfield
.dword
)
3949 else if (flag_code
== CODE_64BIT
3950 && ((i
.types
[1].bitfield
.qword
3951 && i
.reg_operands
== 1
3952 && i
.imm_operands
== 1
3953 && i
.op
[0].imms
->X_op
== O_constant
3954 && ((i
.tm
.base_opcode
== 0xb8
3955 && i
.tm
.extension_opcode
== None
3956 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3957 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3958 && (((i
.tm
.base_opcode
== 0x24
3959 || i
.tm
.base_opcode
== 0xa8)
3960 && i
.tm
.extension_opcode
== None
)
3961 || (i
.tm
.base_opcode
== 0x80
3962 && i
.tm
.extension_opcode
== 0x4)
3963 || ((i
.tm
.base_opcode
== 0xf6
3964 || (i
.tm
.base_opcode
| 1) == 0xc7)
3965 && i
.tm
.extension_opcode
== 0x0)))
3966 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3967 && i
.tm
.base_opcode
== 0x83
3968 && i
.tm
.extension_opcode
== 0x4)))
3969 || (i
.types
[0].bitfield
.qword
3970 && ((i
.reg_operands
== 2
3971 && i
.op
[0].regs
== i
.op
[1].regs
3972 && ((i
.tm
.base_opcode
== 0x30
3973 || i
.tm
.base_opcode
== 0x28)
3974 && i
.tm
.extension_opcode
== None
))
3975 || (i
.reg_operands
== 1
3977 && i
.tm
.base_opcode
== 0x30
3978 && i
.tm
.extension_opcode
== None
)))))
3981 andq $imm31, %r64 -> andl $imm31, %r32
3982 andq $imm7, %r64 -> andl $imm7, %r32
3983 testq $imm31, %r64 -> testl $imm31, %r32
3984 xorq %r64, %r64 -> xorl %r32, %r32
3985 subq %r64, %r64 -> subl %r32, %r32
3986 movq $imm31, %r64 -> movl $imm31, %r32
3987 movq $imm32, %r64 -> movl $imm32, %r32
3989 i
.tm
.opcode_modifier
.norex64
= 1;
3990 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
3993 movq $imm31, %r64 -> movl $imm31, %r32
3994 movq $imm32, %r64 -> movl $imm32, %r32
3996 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3997 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3998 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3999 i
.types
[0].bitfield
.imm32
= 1;
4000 i
.types
[0].bitfield
.imm32s
= 0;
4001 i
.types
[0].bitfield
.imm64
= 0;
4002 i
.types
[1].bitfield
.dword
= 1;
4003 i
.types
[1].bitfield
.qword
= 0;
4004 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4007 movq $imm31, %r64 -> movl $imm31, %r32
4009 i
.tm
.base_opcode
= 0xb8;
4010 i
.tm
.extension_opcode
= None
;
4011 i
.tm
.opcode_modifier
.w
= 0;
4012 i
.tm
.opcode_modifier
.shortform
= 1;
4013 i
.tm
.opcode_modifier
.modrm
= 0;
4017 else if (optimize
> 1
4018 && !optimize_for_space
4019 && i
.reg_operands
== 2
4020 && i
.op
[0].regs
== i
.op
[1].regs
4021 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4022 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4023 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4026 andb %rN, %rN -> testb %rN, %rN
4027 andw %rN, %rN -> testw %rN, %rN
4028 andq %rN, %rN -> testq %rN, %rN
4029 orb %rN, %rN -> testb %rN, %rN
4030 orw %rN, %rN -> testw %rN, %rN
4031 orq %rN, %rN -> testq %rN, %rN
4033 and outside of 64-bit mode
4035 andl %rN, %rN -> testl %rN, %rN
4036 orl %rN, %rN -> testl %rN, %rN
4038 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4040 else if (i
.reg_operands
== 3
4041 && i
.op
[0].regs
== i
.op
[1].regs
4042 && !i
.types
[2].bitfield
.xmmword
4043 && (i
.tm
.opcode_modifier
.vex
4044 || ((!i
.mask
|| i
.mask
->zeroing
)
4046 && is_evex_encoding (&i
.tm
)
4047 && (i
.vec_encoding
!= vex_encoding_evex
4048 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4049 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4050 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4051 && i
.types
[2].bitfield
.ymmword
))))
4052 && ((i
.tm
.base_opcode
== 0x55
4053 || i
.tm
.base_opcode
== 0x6655
4054 || i
.tm
.base_opcode
== 0x66df
4055 || i
.tm
.base_opcode
== 0x57
4056 || i
.tm
.base_opcode
== 0x6657
4057 || i
.tm
.base_opcode
== 0x66ef
4058 || i
.tm
.base_opcode
== 0x66f8
4059 || i
.tm
.base_opcode
== 0x66f9
4060 || i
.tm
.base_opcode
== 0x66fa
4061 || i
.tm
.base_opcode
== 0x66fb
4062 || i
.tm
.base_opcode
== 0x42
4063 || i
.tm
.base_opcode
== 0x6642
4064 || i
.tm
.base_opcode
== 0x47
4065 || i
.tm
.base_opcode
== 0x6647)
4066 && i
.tm
.extension_opcode
== None
))
4069 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4071 EVEX VOP %zmmM, %zmmM, %zmmN
4072 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4073 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4074 EVEX VOP %ymmM, %ymmM, %ymmN
4075 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4076 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4077 VEX VOP %ymmM, %ymmM, %ymmN
4078 -> VEX VOP %xmmM, %xmmM, %xmmN
4079 VOP, one of vpandn and vpxor:
4080 VEX VOP %ymmM, %ymmM, %ymmN
4081 -> VEX VOP %xmmM, %xmmM, %xmmN
4082 VOP, one of vpandnd and vpandnq:
4083 EVEX VOP %zmmM, %zmmM, %zmmN
4084 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4085 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4086 EVEX VOP %ymmM, %ymmM, %ymmN
4087 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4088 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4089 VOP, one of vpxord and vpxorq:
4090 EVEX VOP %zmmM, %zmmM, %zmmN
4091 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4092 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4093 EVEX VOP %ymmM, %ymmM, %ymmN
4094 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4095 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4096 VOP, one of kxord and kxorq:
4097 VEX VOP %kM, %kM, %kN
4098 -> VEX kxorw %kM, %kM, %kN
4099 VOP, one of kandnd and kandnq:
4100 VEX VOP %kM, %kM, %kN
4101 -> VEX kandnw %kM, %kM, %kN
4103 if (is_evex_encoding (&i
.tm
))
4105 if (i
.vec_encoding
!= vex_encoding_evex
)
4107 i
.tm
.opcode_modifier
.vex
= VEX128
;
4108 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4109 i
.tm
.opcode_modifier
.evex
= 0;
4111 else if (optimize
> 1)
4112 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4116 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4118 i
.tm
.base_opcode
&= 0xff;
4119 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4122 i
.tm
.opcode_modifier
.vex
= VEX128
;
4124 if (i
.tm
.opcode_modifier
.vex
)
4125 for (j
= 0; j
< 3; j
++)
4127 i
.types
[j
].bitfield
.xmmword
= 1;
4128 i
.types
[j
].bitfield
.ymmword
= 0;
4131 else if (i
.vec_encoding
!= vex_encoding_evex
4132 && !i
.types
[0].bitfield
.zmmword
4133 && !i
.types
[1].bitfield
.zmmword
4136 && is_evex_encoding (&i
.tm
)
4137 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4138 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4139 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4140 || (i
.tm
.base_opcode
& ~4) == 0x66db
4141 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4142 && i
.tm
.extension_opcode
== None
)
4145 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4146 vmovdqu32 and vmovdqu64:
4147 EVEX VOP %xmmM, %xmmN
4148 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4149 EVEX VOP %ymmM, %ymmN
4150 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4152 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4154 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4156 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4158 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4159 VOP, one of vpand, vpandn, vpor, vpxor:
4160 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4161 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4162 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4163 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4164 EVEX VOP{d,q} mem, %xmmM, %xmmN
4165 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4166 EVEX VOP{d,q} mem, %ymmM, %ymmN
4167 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4169 for (j
= 0; j
< i
.operands
; j
++)
4170 if (operand_type_check (i
.types
[j
], disp
)
4171 && i
.op
[j
].disps
->X_op
== O_constant
)
4173 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4174 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4175 bytes, we choose EVEX Disp8 over VEX Disp32. */
4176 int evex_disp8
, vex_disp8
;
4177 unsigned int memshift
= i
.memshift
;
4178 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4180 evex_disp8
= fits_in_disp8 (n
);
4182 vex_disp8
= fits_in_disp8 (n
);
4183 if (evex_disp8
!= vex_disp8
)
4185 i
.memshift
= memshift
;
4189 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4192 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4193 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4194 i
.tm
.opcode_modifier
.vex
4195 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4196 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4197 /* VPAND, VPOR, and VPXOR are commutative. */
4198 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4199 i
.tm
.opcode_modifier
.commutative
= 1;
4200 i
.tm
.opcode_modifier
.evex
= 0;
4201 i
.tm
.opcode_modifier
.masking
= 0;
4202 i
.tm
.opcode_modifier
.broadcast
= 0;
4203 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4206 i
.types
[j
].bitfield
.disp8
4207 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4211 /* This is the guts of the machine-dependent assembler. LINE points to a
4212 machine dependent instruction. This function is supposed to emit
4213 the frags/bytes it assembles to. */
4216 md_assemble (char *line
)
4219 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4220 const insn_template
*t
;
4222 /* Initialize globals. */
4223 memset (&i
, '\0', sizeof (i
));
4224 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4225 i
.reloc
[j
] = NO_RELOC
;
4226 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4227 memset (im_expressions
, '\0', sizeof (im_expressions
));
4228 save_stack_p
= save_stack
;
4230 /* First parse an instruction mnemonic & call i386_operand for the operands.
4231 We assume that the scrubber has arranged it so that line[0] is the valid
4232 start of a (possibly prefixed) mnemonic. */
4234 line
= parse_insn (line
, mnemonic
);
4237 mnem_suffix
= i
.suffix
;
4239 line
= parse_operands (line
, mnemonic
);
4241 xfree (i
.memop1_string
);
4242 i
.memop1_string
= NULL
;
4246 /* Now we've parsed the mnemonic into a set of templates, and have the
4247 operands at hand. */
4249 /* All intel opcodes have reversed operands except for "bound" and
4250 "enter". We also don't reverse intersegment "jmp" and "call"
4251 instructions with 2 immediate operands so that the immediate segment
4252 precedes the offset, as it does when in AT&T mode. */
4255 && (strcmp (mnemonic
, "bound") != 0)
4256 && (strcmp (mnemonic
, "invlpga") != 0)
4257 && !(operand_type_check (i
.types
[0], imm
)
4258 && operand_type_check (i
.types
[1], imm
)))
4261 /* The order of the immediates should be reversed
4262 for 2 immediates extrq and insertq instructions */
4263 if (i
.imm_operands
== 2
4264 && (strcmp (mnemonic
, "extrq") == 0
4265 || strcmp (mnemonic
, "insertq") == 0))
4266 swap_2_operands (0, 1);
4271 /* Don't optimize displacement for movabs since it only takes 64bit
4274 && i
.disp_encoding
!= disp_encoding_32bit
4275 && (flag_code
!= CODE_64BIT
4276 || strcmp (mnemonic
, "movabs") != 0))
4279 /* Next, we find a template that matches the given insn,
4280 making sure the overlap of the given operands types is consistent
4281 with the template operand types. */
4283 if (!(t
= match_template (mnem_suffix
)))
4286 if (sse_check
!= check_none
4287 && !i
.tm
.opcode_modifier
.noavx
4288 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4289 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4290 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4291 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4292 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4293 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4294 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4295 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4296 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4297 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4299 (sse_check
== check_warning
4301 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4304 /* Zap movzx and movsx suffix. The suffix has been set from
4305 "word ptr" or "byte ptr" on the source operand in Intel syntax
4306 or extracted from mnemonic in AT&T syntax. But we'll use
4307 the destination register to choose the suffix for encoding. */
4308 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4310 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4311 there is no suffix, the default will be byte extension. */
4312 if (i
.reg_operands
!= 2
4315 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4320 if (i
.tm
.opcode_modifier
.fwait
)
4321 if (!add_prefix (FWAIT_OPCODE
))
4324 /* Check if REP prefix is OK. */
4325 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4327 as_bad (_("invalid instruction `%s' after `%s'"),
4328 i
.tm
.name
, i
.rep_prefix
);
4332 /* Check for lock without a lockable instruction. Destination operand
4333 must be memory unless it is xchg (0x86). */
4334 if (i
.prefix
[LOCK_PREFIX
]
4335 && (!i
.tm
.opcode_modifier
.islockable
4336 || i
.mem_operands
== 0
4337 || (i
.tm
.base_opcode
!= 0x86
4338 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4340 as_bad (_("expecting lockable instruction after `lock'"));
4344 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4345 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4347 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4351 /* Check if HLE prefix is OK. */
4352 if (i
.hle_prefix
&& !check_hle ())
4355 /* Check BND prefix. */
4356 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4357 as_bad (_("expecting valid branch instruction after `bnd'"));
4359 /* Check NOTRACK prefix. */
4360 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4361 as_bad (_("expecting indirect branch instruction after `notrack'"));
4363 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4365 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4366 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4367 else if (flag_code
!= CODE_16BIT
4368 ? i
.prefix
[ADDR_PREFIX
]
4369 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4370 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4373 /* Insert BND prefix. */
4374 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4376 if (!i
.prefix
[BND_PREFIX
])
4377 add_prefix (BND_PREFIX_OPCODE
);
4378 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4380 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4381 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4385 /* Check string instruction segment overrides. */
4386 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4388 gas_assert (i
.mem_operands
);
4389 if (!check_string ())
4391 i
.disp_operands
= 0;
4394 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4395 optimize_encoding ();
4397 if (!process_suffix ())
4400 /* Update operand types. */
4401 for (j
= 0; j
< i
.operands
; j
++)
4402 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4404 /* Make still unresolved immediate matches conform to size of immediate
4405 given in i.suffix. */
4406 if (!finalize_imm ())
4409 if (i
.types
[0].bitfield
.imm1
)
4410 i
.imm_operands
= 0; /* kludge for shift insns. */
4412 /* We only need to check those implicit registers for instructions
4413 with 3 operands or less. */
4414 if (i
.operands
<= 3)
4415 for (j
= 0; j
< i
.operands
; j
++)
4416 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4417 && !i
.types
[j
].bitfield
.xmmword
)
4420 /* ImmExt should be processed after SSE2AVX. */
4421 if (!i
.tm
.opcode_modifier
.sse2avx
4422 && i
.tm
.opcode_modifier
.immext
)
4425 /* For insns with operands there are more diddles to do to the opcode. */
4428 if (!process_operands ())
4431 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4433 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4434 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4437 if (is_any_vex_encoding (&i
.tm
))
4439 if (!cpu_arch_flags
.bitfield
.cpui286
)
4441 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4446 if (i
.tm
.opcode_modifier
.vex
)
4447 build_vex_prefix (t
);
4449 build_evex_prefix ();
4452 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4453 instructions may define INT_OPCODE as well, so avoid this corner
4454 case for those instructions that use MODRM. */
4455 if (i
.tm
.base_opcode
== INT_OPCODE
4456 && !i
.tm
.opcode_modifier
.modrm
4457 && i
.op
[0].imms
->X_add_number
== 3)
4459 i
.tm
.base_opcode
= INT3_OPCODE
;
4463 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4464 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4465 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4466 && i
.op
[0].disps
->X_op
== O_constant
)
4468 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4469 the absolute address given by the constant. Since ix86 jumps and
4470 calls are pc relative, we need to generate a reloc. */
4471 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4472 i
.op
[0].disps
->X_op
= O_symbol
;
4475 if (i
.tm
.opcode_modifier
.rex64
)
4478 /* For 8 bit registers we need an empty rex prefix. Also if the
4479 instruction already has a prefix, we need to convert old
4480 registers to new ones. */
4482 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4483 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4484 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4485 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4486 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4487 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4492 i
.rex
|= REX_OPCODE
;
4493 for (x
= 0; x
< 2; x
++)
4495 /* Look for 8 bit operand that uses old registers. */
4496 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4497 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4499 /* In case it is "hi" register, give up. */
4500 if (i
.op
[x
].regs
->reg_num
> 3)
4501 as_bad (_("can't encode register '%s%s' in an "
4502 "instruction requiring REX prefix."),
4503 register_prefix
, i
.op
[x
].regs
->reg_name
);
4505 /* Otherwise it is equivalent to the extended register.
4506 Since the encoding doesn't change this is merely
4507 cosmetic cleanup for debug output. */
4509 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4514 if (i
.rex
== 0 && i
.rex_encoding
)
4516 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4517 that uses legacy register. If it is "hi" register, don't add
4518 the REX_OPCODE byte. */
4520 for (x
= 0; x
< 2; x
++)
4521 if (i
.types
[x
].bitfield
.class == Reg
4522 && i
.types
[x
].bitfield
.byte
4523 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4524 && i
.op
[x
].regs
->reg_num
> 3)
4526 i
.rex_encoding
= FALSE
;
4535 add_prefix (REX_OPCODE
| i
.rex
);
4537 /* We are ready to output the insn. */
4542 parse_insn (char *line
, char *mnemonic
)
4545 char *token_start
= l
;
4548 const insn_template
*t
;
4554 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4559 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4561 as_bad (_("no such instruction: `%s'"), token_start
);
4566 if (!is_space_char (*l
)
4567 && *l
!= END_OF_INSN
4569 || (*l
!= PREFIX_SEPARATOR
4572 as_bad (_("invalid character %s in mnemonic"),
4573 output_invalid (*l
));
4576 if (token_start
== l
)
4578 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4579 as_bad (_("expecting prefix; got nothing"));
4581 as_bad (_("expecting mnemonic; got nothing"));
4585 /* Look up instruction (or prefix) via hash table. */
4586 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4588 if (*l
!= END_OF_INSN
4589 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4590 && current_templates
4591 && current_templates
->start
->opcode_modifier
.isprefix
)
4593 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4595 as_bad ((flag_code
!= CODE_64BIT
4596 ? _("`%s' is only supported in 64-bit mode")
4597 : _("`%s' is not supported in 64-bit mode")),
4598 current_templates
->start
->name
);
4601 /* If we are in 16-bit mode, do not allow addr16 or data16.
4602 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4603 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4604 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4605 && flag_code
!= CODE_64BIT
4606 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4607 ^ (flag_code
== CODE_16BIT
)))
4609 as_bad (_("redundant %s prefix"),
4610 current_templates
->start
->name
);
4613 if (current_templates
->start
->opcode_length
== 0)
4615 /* Handle pseudo prefixes. */
4616 switch (current_templates
->start
->base_opcode
)
4620 i
.disp_encoding
= disp_encoding_8bit
;
4624 i
.disp_encoding
= disp_encoding_32bit
;
4628 i
.dir_encoding
= dir_encoding_load
;
4632 i
.dir_encoding
= dir_encoding_store
;
4636 i
.vec_encoding
= vex_encoding_vex2
;
4640 i
.vec_encoding
= vex_encoding_vex3
;
4644 i
.vec_encoding
= vex_encoding_evex
;
4648 i
.rex_encoding
= TRUE
;
4652 i
.no_optimize
= TRUE
;
4660 /* Add prefix, checking for repeated prefixes. */
4661 switch (add_prefix (current_templates
->start
->base_opcode
))
4666 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4667 i
.notrack_prefix
= current_templates
->start
->name
;
4670 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4671 i
.hle_prefix
= current_templates
->start
->name
;
4672 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4673 i
.bnd_prefix
= current_templates
->start
->name
;
4675 i
.rep_prefix
= current_templates
->start
->name
;
4681 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4688 if (!current_templates
)
4690 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4691 Check if we should swap operand or force 32bit displacement in
4693 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4694 i
.dir_encoding
= dir_encoding_swap
;
4695 else if (mnem_p
- 3 == dot_p
4698 i
.disp_encoding
= disp_encoding_8bit
;
4699 else if (mnem_p
- 4 == dot_p
4703 i
.disp_encoding
= disp_encoding_32bit
;
4708 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4711 if (!current_templates
)
4714 if (mnem_p
> mnemonic
)
4716 /* See if we can get a match by trimming off a suffix. */
4719 case WORD_MNEM_SUFFIX
:
4720 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4721 i
.suffix
= SHORT_MNEM_SUFFIX
;
4724 case BYTE_MNEM_SUFFIX
:
4725 case QWORD_MNEM_SUFFIX
:
4726 i
.suffix
= mnem_p
[-1];
4728 current_templates
= (const templates
*) hash_find (op_hash
,
4731 case SHORT_MNEM_SUFFIX
:
4732 case LONG_MNEM_SUFFIX
:
4735 i
.suffix
= mnem_p
[-1];
4737 current_templates
= (const templates
*) hash_find (op_hash
,
4746 if (intel_float_operand (mnemonic
) == 1)
4747 i
.suffix
= SHORT_MNEM_SUFFIX
;
4749 i
.suffix
= LONG_MNEM_SUFFIX
;
4751 current_templates
= (const templates
*) hash_find (op_hash
,
4758 if (!current_templates
)
4760 as_bad (_("no such instruction: `%s'"), token_start
);
4765 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4766 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4768 /* Check for a branch hint. We allow ",pt" and ",pn" for
4769 predict taken and predict not taken respectively.
4770 I'm not sure that branch hints actually do anything on loop
4771 and jcxz insns (JumpByte) for current Pentium4 chips. They
4772 may work in the future and it doesn't hurt to accept them
4774 if (l
[0] == ',' && l
[1] == 'p')
4778 if (!add_prefix (DS_PREFIX_OPCODE
))
4782 else if (l
[2] == 'n')
4784 if (!add_prefix (CS_PREFIX_OPCODE
))
4790 /* Any other comma loses. */
4793 as_bad (_("invalid character %s in mnemonic"),
4794 output_invalid (*l
));
4798 /* Check if instruction is supported on specified architecture. */
4800 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4802 supported
|= cpu_flags_match (t
);
4803 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4805 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4806 as_warn (_("use .code16 to ensure correct addressing mode"));
4812 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4813 as_bad (flag_code
== CODE_64BIT
4814 ? _("`%s' is not supported in 64-bit mode")
4815 : _("`%s' is only supported in 64-bit mode"),
4816 current_templates
->start
->name
);
4818 as_bad (_("`%s' is not supported on `%s%s'"),
4819 current_templates
->start
->name
,
4820 cpu_arch_name
? cpu_arch_name
: default_arch
,
4821 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4827 parse_operands (char *l
, const char *mnemonic
)
4831 /* 1 if operand is pending after ','. */
4832 unsigned int expecting_operand
= 0;
4834 /* Non-zero if operand parens not balanced. */
4835 unsigned int paren_not_balanced
;
4837 while (*l
!= END_OF_INSN
)
4839 /* Skip optional white space before operand. */
4840 if (is_space_char (*l
))
4842 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4844 as_bad (_("invalid character %s before operand %d"),
4845 output_invalid (*l
),
4849 token_start
= l
; /* After white space. */
4850 paren_not_balanced
= 0;
4851 while (paren_not_balanced
|| *l
!= ',')
4853 if (*l
== END_OF_INSN
)
4855 if (paren_not_balanced
)
4858 as_bad (_("unbalanced parenthesis in operand %d."),
4861 as_bad (_("unbalanced brackets in operand %d."),
4866 break; /* we are done */
4868 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4870 as_bad (_("invalid character %s in operand %d"),
4871 output_invalid (*l
),
4878 ++paren_not_balanced
;
4880 --paren_not_balanced
;
4885 ++paren_not_balanced
;
4887 --paren_not_balanced
;
4891 if (l
!= token_start
)
4892 { /* Yes, we've read in another operand. */
4893 unsigned int operand_ok
;
4894 this_operand
= i
.operands
++;
4895 if (i
.operands
> MAX_OPERANDS
)
4897 as_bad (_("spurious operands; (%d operands/instruction max)"),
4901 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4902 /* Now parse operand adding info to 'i' as we go along. */
4903 END_STRING_AND_SAVE (l
);
4905 if (i
.mem_operands
> 1)
4907 as_bad (_("too many memory references for `%s'"),
4914 i386_intel_operand (token_start
,
4915 intel_float_operand (mnemonic
));
4917 operand_ok
= i386_att_operand (token_start
);
4919 RESTORE_END_STRING (l
);
4925 if (expecting_operand
)
4927 expecting_operand_after_comma
:
4928 as_bad (_("expecting operand after ','; got nothing"));
4933 as_bad (_("expecting operand before ','; got nothing"));
4938 /* Now *l must be either ',' or END_OF_INSN. */
4941 if (*++l
== END_OF_INSN
)
4943 /* Just skip it, if it's \n complain. */
4944 goto expecting_operand_after_comma
;
4946 expecting_operand
= 1;
4953 swap_2_operands (int xchg1
, int xchg2
)
4955 union i386_op temp_op
;
4956 i386_operand_type temp_type
;
4957 unsigned int temp_flags
;
4958 enum bfd_reloc_code_real temp_reloc
;
4960 temp_type
= i
.types
[xchg2
];
4961 i
.types
[xchg2
] = i
.types
[xchg1
];
4962 i
.types
[xchg1
] = temp_type
;
4964 temp_flags
= i
.flags
[xchg2
];
4965 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4966 i
.flags
[xchg1
] = temp_flags
;
4968 temp_op
= i
.op
[xchg2
];
4969 i
.op
[xchg2
] = i
.op
[xchg1
];
4970 i
.op
[xchg1
] = temp_op
;
4972 temp_reloc
= i
.reloc
[xchg2
];
4973 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4974 i
.reloc
[xchg1
] = temp_reloc
;
4978 if (i
.mask
->operand
== xchg1
)
4979 i
.mask
->operand
= xchg2
;
4980 else if (i
.mask
->operand
== xchg2
)
4981 i
.mask
->operand
= xchg1
;
4985 if (i
.broadcast
->operand
== xchg1
)
4986 i
.broadcast
->operand
= xchg2
;
4987 else if (i
.broadcast
->operand
== xchg2
)
4988 i
.broadcast
->operand
= xchg1
;
4992 if (i
.rounding
->operand
== xchg1
)
4993 i
.rounding
->operand
= xchg2
;
4994 else if (i
.rounding
->operand
== xchg2
)
4995 i
.rounding
->operand
= xchg1
;
5000 swap_operands (void)
5006 swap_2_operands (1, i
.operands
- 2);
5010 swap_2_operands (0, i
.operands
- 1);
5016 if (i
.mem_operands
== 2)
5018 const seg_entry
*temp_seg
;
5019 temp_seg
= i
.seg
[0];
5020 i
.seg
[0] = i
.seg
[1];
5021 i
.seg
[1] = temp_seg
;
5025 /* Try to ensure constant immediates are represented in the smallest
5030 char guess_suffix
= 0;
5034 guess_suffix
= i
.suffix
;
5035 else if (i
.reg_operands
)
5037 /* Figure out a suffix from the last register operand specified.
5038 We can't do this properly yet, i.e. excluding special register
5039 instances, but the following works for instructions with
5040 immediates. In any case, we can't set i.suffix yet. */
5041 for (op
= i
.operands
; --op
>= 0;)
5042 if (i
.types
[op
].bitfield
.class != Reg
)
5044 else if (i
.types
[op
].bitfield
.byte
)
5046 guess_suffix
= BYTE_MNEM_SUFFIX
;
5049 else if (i
.types
[op
].bitfield
.word
)
5051 guess_suffix
= WORD_MNEM_SUFFIX
;
5054 else if (i
.types
[op
].bitfield
.dword
)
5056 guess_suffix
= LONG_MNEM_SUFFIX
;
5059 else if (i
.types
[op
].bitfield
.qword
)
5061 guess_suffix
= QWORD_MNEM_SUFFIX
;
5065 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5066 guess_suffix
= WORD_MNEM_SUFFIX
;
5068 for (op
= i
.operands
; --op
>= 0;)
5069 if (operand_type_check (i
.types
[op
], imm
))
5071 switch (i
.op
[op
].imms
->X_op
)
5074 /* If a suffix is given, this operand may be shortened. */
5075 switch (guess_suffix
)
5077 case LONG_MNEM_SUFFIX
:
5078 i
.types
[op
].bitfield
.imm32
= 1;
5079 i
.types
[op
].bitfield
.imm64
= 1;
5081 case WORD_MNEM_SUFFIX
:
5082 i
.types
[op
].bitfield
.imm16
= 1;
5083 i
.types
[op
].bitfield
.imm32
= 1;
5084 i
.types
[op
].bitfield
.imm32s
= 1;
5085 i
.types
[op
].bitfield
.imm64
= 1;
5087 case BYTE_MNEM_SUFFIX
:
5088 i
.types
[op
].bitfield
.imm8
= 1;
5089 i
.types
[op
].bitfield
.imm8s
= 1;
5090 i
.types
[op
].bitfield
.imm16
= 1;
5091 i
.types
[op
].bitfield
.imm32
= 1;
5092 i
.types
[op
].bitfield
.imm32s
= 1;
5093 i
.types
[op
].bitfield
.imm64
= 1;
5097 /* If this operand is at most 16 bits, convert it
5098 to a signed 16 bit number before trying to see
5099 whether it will fit in an even smaller size.
5100 This allows a 16-bit operand such as $0xffe0 to
5101 be recognised as within Imm8S range. */
5102 if ((i
.types
[op
].bitfield
.imm16
)
5103 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5105 i
.op
[op
].imms
->X_add_number
=
5106 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5109 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5110 if ((i
.types
[op
].bitfield
.imm32
)
5111 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5114 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5115 ^ ((offsetT
) 1 << 31))
5116 - ((offsetT
) 1 << 31));
5120 = operand_type_or (i
.types
[op
],
5121 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5123 /* We must avoid matching of Imm32 templates when 64bit
5124 only immediate is available. */
5125 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5126 i
.types
[op
].bitfield
.imm32
= 0;
5133 /* Symbols and expressions. */
5135 /* Convert symbolic operand to proper sizes for matching, but don't
5136 prevent matching a set of insns that only supports sizes other
5137 than those matching the insn suffix. */
5139 i386_operand_type mask
, allowed
;
5140 const insn_template
*t
;
5142 operand_type_set (&mask
, 0);
5143 operand_type_set (&allowed
, 0);
5145 for (t
= current_templates
->start
;
5146 t
< current_templates
->end
;
5149 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5150 allowed
= operand_type_and (allowed
, anyimm
);
5152 switch (guess_suffix
)
5154 case QWORD_MNEM_SUFFIX
:
5155 mask
.bitfield
.imm64
= 1;
5156 mask
.bitfield
.imm32s
= 1;
5158 case LONG_MNEM_SUFFIX
:
5159 mask
.bitfield
.imm32
= 1;
5161 case WORD_MNEM_SUFFIX
:
5162 mask
.bitfield
.imm16
= 1;
5164 case BYTE_MNEM_SUFFIX
:
5165 mask
.bitfield
.imm8
= 1;
5170 allowed
= operand_type_and (mask
, allowed
);
5171 if (!operand_type_all_zero (&allowed
))
5172 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5179 /* Try to use the smallest displacement type too. */
5181 optimize_disp (void)
5185 for (op
= i
.operands
; --op
>= 0;)
5186 if (operand_type_check (i
.types
[op
], disp
))
5188 if (i
.op
[op
].disps
->X_op
== O_constant
)
5190 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5192 if (i
.types
[op
].bitfield
.disp16
5193 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5195 /* If this operand is at most 16 bits, convert
5196 to a signed 16 bit number and don't use 64bit
5198 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5199 i
.types
[op
].bitfield
.disp64
= 0;
5202 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5203 if (i
.types
[op
].bitfield
.disp32
5204 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5206 /* If this operand is at most 32 bits, convert
5207 to a signed 32 bit number and don't use 64bit
5209 op_disp
&= (((offsetT
) 2 << 31) - 1);
5210 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5211 i
.types
[op
].bitfield
.disp64
= 0;
5214 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5216 i
.types
[op
].bitfield
.disp8
= 0;
5217 i
.types
[op
].bitfield
.disp16
= 0;
5218 i
.types
[op
].bitfield
.disp32
= 0;
5219 i
.types
[op
].bitfield
.disp32s
= 0;
5220 i
.types
[op
].bitfield
.disp64
= 0;
5224 else if (flag_code
== CODE_64BIT
)
5226 if (fits_in_signed_long (op_disp
))
5228 i
.types
[op
].bitfield
.disp64
= 0;
5229 i
.types
[op
].bitfield
.disp32s
= 1;
5231 if (i
.prefix
[ADDR_PREFIX
]
5232 && fits_in_unsigned_long (op_disp
))
5233 i
.types
[op
].bitfield
.disp32
= 1;
5235 if ((i
.types
[op
].bitfield
.disp32
5236 || i
.types
[op
].bitfield
.disp32s
5237 || i
.types
[op
].bitfield
.disp16
)
5238 && fits_in_disp8 (op_disp
))
5239 i
.types
[op
].bitfield
.disp8
= 1;
5241 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5242 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5244 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5245 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5246 i
.types
[op
].bitfield
.disp8
= 0;
5247 i
.types
[op
].bitfield
.disp16
= 0;
5248 i
.types
[op
].bitfield
.disp32
= 0;
5249 i
.types
[op
].bitfield
.disp32s
= 0;
5250 i
.types
[op
].bitfield
.disp64
= 0;
5253 /* We only support 64bit displacement on constants. */
5254 i
.types
[op
].bitfield
.disp64
= 0;
5258 /* Return 1 if there is a match in broadcast bytes between operand
5259 GIVEN and instruction template T. */
5262 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5264 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5265 && i
.types
[given
].bitfield
.byte
)
5266 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5267 && i
.types
[given
].bitfield
.word
)
5268 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5269 && i
.types
[given
].bitfield
.dword
)
5270 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5271 && i
.types
[given
].bitfield
.qword
));
5274 /* Check if operands are valid for the instruction. */
5277 check_VecOperands (const insn_template
*t
)
5281 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5283 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5284 any one operand are implicity requiring AVX512VL support if the actual
5285 operand size is YMMword or XMMword. Since this function runs after
5286 template matching, there's no need to check for YMMword/XMMword in
5288 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5289 if (!cpu_flags_all_zero (&cpu
)
5290 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5291 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5293 for (op
= 0; op
< t
->operands
; ++op
)
5295 if (t
->operand_types
[op
].bitfield
.zmmword
5296 && (i
.types
[op
].bitfield
.ymmword
5297 || i
.types
[op
].bitfield
.xmmword
))
5299 i
.error
= unsupported
;
5305 /* Without VSIB byte, we can't have a vector register for index. */
5306 if (!t
->opcode_modifier
.vecsib
5308 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5309 || i
.index_reg
->reg_type
.bitfield
.ymmword
5310 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5312 i
.error
= unsupported_vector_index_register
;
5316 /* Check if default mask is allowed. */
5317 if (t
->opcode_modifier
.nodefmask
5318 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5320 i
.error
= no_default_mask
;
5324 /* For VSIB byte, we need a vector register for index, and all vector
5325 registers must be distinct. */
5326 if (t
->opcode_modifier
.vecsib
)
5329 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5330 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5331 || (t
->opcode_modifier
.vecsib
== VecSIB256
5332 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5333 || (t
->opcode_modifier
.vecsib
== VecSIB512
5334 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5336 i
.error
= invalid_vsib_address
;
5340 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5341 if (i
.reg_operands
== 2 && !i
.mask
)
5343 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5344 gas_assert (i
.types
[0].bitfield
.xmmword
5345 || i
.types
[0].bitfield
.ymmword
);
5346 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5347 gas_assert (i
.types
[2].bitfield
.xmmword
5348 || i
.types
[2].bitfield
.ymmword
);
5349 if (operand_check
== check_none
)
5351 if (register_number (i
.op
[0].regs
)
5352 != register_number (i
.index_reg
)
5353 && register_number (i
.op
[2].regs
)
5354 != register_number (i
.index_reg
)
5355 && register_number (i
.op
[0].regs
)
5356 != register_number (i
.op
[2].regs
))
5358 if (operand_check
== check_error
)
5360 i
.error
= invalid_vector_register_set
;
5363 as_warn (_("mask, index, and destination registers should be distinct"));
5365 else if (i
.reg_operands
== 1 && i
.mask
)
5367 if (i
.types
[1].bitfield
.class == RegSIMD
5368 && (i
.types
[1].bitfield
.xmmword
5369 || i
.types
[1].bitfield
.ymmword
5370 || i
.types
[1].bitfield
.zmmword
)
5371 && (register_number (i
.op
[1].regs
)
5372 == register_number (i
.index_reg
)))
5374 if (operand_check
== check_error
)
5376 i
.error
= invalid_vector_register_set
;
5379 if (operand_check
!= check_none
)
5380 as_warn (_("index and destination registers should be distinct"));
5385 /* Check if broadcast is supported by the instruction and is applied
5386 to the memory operand. */
5389 i386_operand_type type
, overlap
;
5391 /* Check if specified broadcast is supported in this instruction,
5392 and its broadcast bytes match the memory operand. */
5393 op
= i
.broadcast
->operand
;
5394 if (!t
->opcode_modifier
.broadcast
5395 || !(i
.flags
[op
] & Operand_Mem
)
5396 || (!i
.types
[op
].bitfield
.unspecified
5397 && !match_broadcast_size (t
, op
)))
5400 i
.error
= unsupported_broadcast
;
5404 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5405 * i
.broadcast
->type
);
5406 operand_type_set (&type
, 0);
5407 switch (i
.broadcast
->bytes
)
5410 type
.bitfield
.word
= 1;
5413 type
.bitfield
.dword
= 1;
5416 type
.bitfield
.qword
= 1;
5419 type
.bitfield
.xmmword
= 1;
5422 type
.bitfield
.ymmword
= 1;
5425 type
.bitfield
.zmmword
= 1;
5431 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5432 if (operand_type_all_zero (&overlap
))
5435 if (t
->opcode_modifier
.checkregsize
)
5439 type
.bitfield
.baseindex
= 1;
5440 for (j
= 0; j
< i
.operands
; ++j
)
5443 && !operand_type_register_match(i
.types
[j
],
5444 t
->operand_types
[j
],
5446 t
->operand_types
[op
]))
5451 /* If broadcast is supported in this instruction, we need to check if
5452 operand of one-element size isn't specified without broadcast. */
5453 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5455 /* Find memory operand. */
5456 for (op
= 0; op
< i
.operands
; op
++)
5457 if (i
.flags
[op
] & Operand_Mem
)
5459 gas_assert (op
< i
.operands
);
5460 /* Check size of the memory operand. */
5461 if (match_broadcast_size (t
, op
))
5463 i
.error
= broadcast_needed
;
5468 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5470 /* Check if requested masking is supported. */
5473 switch (t
->opcode_modifier
.masking
)
5477 case MERGING_MASKING
:
5478 if (i
.mask
->zeroing
)
5481 i
.error
= unsupported_masking
;
5485 case DYNAMIC_MASKING
:
5486 /* Memory destinations allow only merging masking. */
5487 if (i
.mask
->zeroing
&& i
.mem_operands
)
5489 /* Find memory operand. */
5490 for (op
= 0; op
< i
.operands
; op
++)
5491 if (i
.flags
[op
] & Operand_Mem
)
5493 gas_assert (op
< i
.operands
);
5494 if (op
== i
.operands
- 1)
5496 i
.error
= unsupported_masking
;
5506 /* Check if masking is applied to dest operand. */
5507 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5509 i
.error
= mask_not_on_destination
;
5516 if (!t
->opcode_modifier
.sae
5517 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5519 i
.error
= unsupported_rc_sae
;
5522 /* If the instruction has several immediate operands and one of
5523 them is rounding, the rounding operand should be the last
5524 immediate operand. */
5525 if (i
.imm_operands
> 1
5526 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5528 i
.error
= rc_sae_operand_not_last_imm
;
5533 /* Check vector Disp8 operand. */
5534 if (t
->opcode_modifier
.disp8memshift
5535 && i
.disp_encoding
!= disp_encoding_32bit
)
5538 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5539 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5540 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5543 const i386_operand_type
*type
= NULL
;
5546 for (op
= 0; op
< i
.operands
; op
++)
5547 if (i
.flags
[op
] & Operand_Mem
)
5549 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5550 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5551 else if (t
->operand_types
[op
].bitfield
.xmmword
5552 + t
->operand_types
[op
].bitfield
.ymmword
5553 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5554 type
= &t
->operand_types
[op
];
5555 else if (!i
.types
[op
].bitfield
.unspecified
)
5556 type
= &i
.types
[op
];
5558 else if (i
.types
[op
].bitfield
.class == RegSIMD
5559 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5561 if (i
.types
[op
].bitfield
.zmmword
)
5563 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5565 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5571 if (type
->bitfield
.zmmword
)
5573 else if (type
->bitfield
.ymmword
)
5575 else if (type
->bitfield
.xmmword
)
5579 /* For the check in fits_in_disp8(). */
5580 if (i
.memshift
== 0)
5584 for (op
= 0; op
< i
.operands
; op
++)
5585 if (operand_type_check (i
.types
[op
], disp
)
5586 && i
.op
[op
].disps
->X_op
== O_constant
)
5588 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5590 i
.types
[op
].bitfield
.disp8
= 1;
5593 i
.types
[op
].bitfield
.disp8
= 0;
5602 /* Check if operands are valid for the instruction. Update VEX
5606 VEX_check_operands (const insn_template
*t
)
5608 if (i
.vec_encoding
== vex_encoding_evex
)
5610 /* This instruction must be encoded with EVEX prefix. */
5611 if (!is_evex_encoding (t
))
5613 i
.error
= unsupported
;
5619 if (!t
->opcode_modifier
.vex
)
5621 /* This instruction template doesn't have VEX prefix. */
5622 if (i
.vec_encoding
!= vex_encoding_default
)
5624 i
.error
= unsupported
;
5630 /* Check the special Imm4 cases; must be the first operand. */
5631 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5633 if (i
.op
[0].imms
->X_op
!= O_constant
5634 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5640 /* Turn off Imm<N> so that update_imm won't complain. */
5641 operand_type_set (&i
.types
[0], 0);
5647 static const insn_template
*
5648 match_template (char mnem_suffix
)
5650 /* Points to template once we've found it. */
5651 const insn_template
*t
;
5652 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5653 i386_operand_type overlap4
;
5654 unsigned int found_reverse_match
;
5655 i386_opcode_modifier suffix_check
;
5656 i386_operand_type operand_types
[MAX_OPERANDS
];
5657 int addr_prefix_disp
;
5659 unsigned int found_cpu_match
, size_match
;
5660 unsigned int check_register
;
5661 enum i386_error specific_error
= 0;
5663 #if MAX_OPERANDS != 5
5664 # error "MAX_OPERANDS must be 5."
5667 found_reverse_match
= 0;
5668 addr_prefix_disp
= -1;
5670 /* Prepare for mnemonic suffix check. */
5671 memset (&suffix_check
, 0, sizeof (suffix_check
));
5672 switch (mnem_suffix
)
5674 case BYTE_MNEM_SUFFIX
:
5675 suffix_check
.no_bsuf
= 1;
5677 case WORD_MNEM_SUFFIX
:
5678 suffix_check
.no_wsuf
= 1;
5680 case SHORT_MNEM_SUFFIX
:
5681 suffix_check
.no_ssuf
= 1;
5683 case LONG_MNEM_SUFFIX
:
5684 suffix_check
.no_lsuf
= 1;
5686 case QWORD_MNEM_SUFFIX
:
5687 suffix_check
.no_qsuf
= 1;
5690 /* NB: In Intel syntax, normally we can check for memory operand
5691 size when there is no mnemonic suffix. But jmp and call have
5692 2 different encodings with Dword memory operand size, one with
5693 No_ldSuf and the other without. i.suffix is set to
5694 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5695 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5696 suffix_check
.no_ldsuf
= 1;
5699 /* Must have right number of operands. */
5700 i
.error
= number_of_operands_mismatch
;
5702 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5704 addr_prefix_disp
= -1;
5705 found_reverse_match
= 0;
5707 if (i
.operands
!= t
->operands
)
5710 /* Check processor support. */
5711 i
.error
= unsupported
;
5712 found_cpu_match
= (cpu_flags_match (t
)
5713 == CPU_FLAGS_PERFECT_MATCH
);
5714 if (!found_cpu_match
)
5717 /* Check AT&T mnemonic. */
5718 i
.error
= unsupported_with_intel_mnemonic
;
5719 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5722 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5723 i
.error
= unsupported_syntax
;
5724 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5725 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5726 || (intel64
&& t
->opcode_modifier
.amd64
)
5727 || (!intel64
&& t
->opcode_modifier
.intel64
))
5730 /* Check the suffix. */
5731 i
.error
= invalid_instruction_suffix
;
5732 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5733 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5734 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5735 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5736 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5737 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5740 size_match
= operand_size_match (t
);
5744 /* This is intentionally not
5746 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5748 as the case of a missing * on the operand is accepted (perhaps with
5749 a warning, issued further down). */
5750 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5752 i
.error
= operand_type_mismatch
;
5756 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5757 operand_types
[j
] = t
->operand_types
[j
];
5759 /* In general, don't allow 64-bit operands in 32-bit mode. */
5760 if (i
.suffix
== QWORD_MNEM_SUFFIX
5761 && flag_code
!= CODE_64BIT
5763 ? (!t
->opcode_modifier
.ignoresize
5764 && !t
->opcode_modifier
.broadcast
5765 && !intel_float_operand (t
->name
))
5766 : intel_float_operand (t
->name
) != 2)
5767 && ((operand_types
[0].bitfield
.class != RegMMX
5768 && operand_types
[0].bitfield
.class != RegSIMD
)
5769 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5770 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5771 && (t
->base_opcode
!= 0x0fc7
5772 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5775 /* In general, don't allow 32-bit operands on pre-386. */
5776 else if (i
.suffix
== LONG_MNEM_SUFFIX
5777 && !cpu_arch_flags
.bitfield
.cpui386
5779 ? (!t
->opcode_modifier
.ignoresize
5780 && !intel_float_operand (t
->name
))
5781 : intel_float_operand (t
->name
) != 2)
5782 && ((operand_types
[0].bitfield
.class != RegMMX
5783 && operand_types
[0].bitfield
.class != RegSIMD
)
5784 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5785 && operand_types
[t
->operands
> 1].bitfield
.class
5789 /* Do not verify operands when there are none. */
5793 /* We've found a match; break out of loop. */
5797 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5798 into Disp32/Disp16/Disp32 operand. */
5799 if (i
.prefix
[ADDR_PREFIX
] != 0)
5801 /* There should be only one Disp operand. */
5805 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5807 if (operand_types
[j
].bitfield
.disp16
)
5809 addr_prefix_disp
= j
;
5810 operand_types
[j
].bitfield
.disp32
= 1;
5811 operand_types
[j
].bitfield
.disp16
= 0;
5817 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5819 if (operand_types
[j
].bitfield
.disp32
)
5821 addr_prefix_disp
= j
;
5822 operand_types
[j
].bitfield
.disp32
= 0;
5823 operand_types
[j
].bitfield
.disp16
= 1;
5829 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5831 if (operand_types
[j
].bitfield
.disp64
)
5833 addr_prefix_disp
= j
;
5834 operand_types
[j
].bitfield
.disp64
= 0;
5835 operand_types
[j
].bitfield
.disp32
= 1;
5843 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5844 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5847 /* We check register size if needed. */
5848 if (t
->opcode_modifier
.checkregsize
)
5850 check_register
= (1 << t
->operands
) - 1;
5852 check_register
&= ~(1 << i
.broadcast
->operand
);
5857 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5858 switch (t
->operands
)
5861 if (!operand_type_match (overlap0
, i
.types
[0]))
5865 /* xchg %eax, %eax is a special case. It is an alias for nop
5866 only in 32bit mode and we can use opcode 0x90. In 64bit
5867 mode, we can't use 0x90 for xchg %eax, %eax since it should
5868 zero-extend %eax to %rax. */
5869 if (flag_code
== CODE_64BIT
5870 && t
->base_opcode
== 0x90
5871 && i
.types
[0].bitfield
.instance
== Accum
5872 && i
.types
[0].bitfield
.dword
5873 && i
.types
[1].bitfield
.instance
== Accum
5874 && i
.types
[1].bitfield
.dword
)
5876 /* xrelease mov %eax, <disp> is another special case. It must not
5877 match the accumulator-only encoding of mov. */
5878 if (flag_code
!= CODE_64BIT
5880 && t
->base_opcode
== 0xa0
5881 && i
.types
[0].bitfield
.instance
== Accum
5882 && (i
.flags
[1] & Operand_Mem
))
5887 if (!(size_match
& MATCH_STRAIGHT
))
5889 /* Reverse direction of operands if swapping is possible in the first
5890 place (operands need to be symmetric) and
5891 - the load form is requested, and the template is a store form,
5892 - the store form is requested, and the template is a load form,
5893 - the non-default (swapped) form is requested. */
5894 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5895 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5896 && !operand_type_all_zero (&overlap1
))
5897 switch (i
.dir_encoding
)
5899 case dir_encoding_load
:
5900 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5901 || t
->opcode_modifier
.regmem
)
5905 case dir_encoding_store
:
5906 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5907 && !t
->opcode_modifier
.regmem
)
5911 case dir_encoding_swap
:
5914 case dir_encoding_default
:
5917 /* If we want store form, we skip the current load. */
5918 if ((i
.dir_encoding
== dir_encoding_store
5919 || i
.dir_encoding
== dir_encoding_swap
)
5920 && i
.mem_operands
== 0
5921 && t
->opcode_modifier
.load
)
5926 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5927 if (!operand_type_match (overlap0
, i
.types
[0])
5928 || !operand_type_match (overlap1
, i
.types
[1])
5929 || ((check_register
& 3) == 3
5930 && !operand_type_register_match (i
.types
[0],
5935 /* Check if other direction is valid ... */
5936 if (!t
->opcode_modifier
.d
)
5940 if (!(size_match
& MATCH_REVERSE
))
5942 /* Try reversing direction of operands. */
5943 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5944 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5945 if (!operand_type_match (overlap0
, i
.types
[0])
5946 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5948 && !operand_type_register_match (i
.types
[0],
5949 operand_types
[i
.operands
- 1],
5950 i
.types
[i
.operands
- 1],
5953 /* Does not match either direction. */
5956 /* found_reverse_match holds which of D or FloatR
5958 if (!t
->opcode_modifier
.d
)
5959 found_reverse_match
= 0;
5960 else if (operand_types
[0].bitfield
.tbyte
)
5961 found_reverse_match
= Opcode_FloatD
;
5962 else if (operand_types
[0].bitfield
.xmmword
5963 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5964 || operand_types
[0].bitfield
.class == RegMMX
5965 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
5966 || is_any_vex_encoding(t
))
5967 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5968 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5970 found_reverse_match
= Opcode_D
;
5971 if (t
->opcode_modifier
.floatr
)
5972 found_reverse_match
|= Opcode_FloatR
;
5976 /* Found a forward 2 operand match here. */
5977 switch (t
->operands
)
5980 overlap4
= operand_type_and (i
.types
[4],
5984 overlap3
= operand_type_and (i
.types
[3],
5988 overlap2
= operand_type_and (i
.types
[2],
5993 switch (t
->operands
)
5996 if (!operand_type_match (overlap4
, i
.types
[4])
5997 || !operand_type_register_match (i
.types
[3],
6004 if (!operand_type_match (overlap3
, i
.types
[3])
6005 || ((check_register
& 0xa) == 0xa
6006 && !operand_type_register_match (i
.types
[1],
6010 || ((check_register
& 0xc) == 0xc
6011 && !operand_type_register_match (i
.types
[2],
6018 /* Here we make use of the fact that there are no
6019 reverse match 3 operand instructions. */
6020 if (!operand_type_match (overlap2
, i
.types
[2])
6021 || ((check_register
& 5) == 5
6022 && !operand_type_register_match (i
.types
[0],
6026 || ((check_register
& 6) == 6
6027 && !operand_type_register_match (i
.types
[1],
6035 /* Found either forward/reverse 2, 3 or 4 operand match here:
6036 slip through to break. */
6038 if (!found_cpu_match
)
6041 /* Check if vector and VEX operands are valid. */
6042 if (check_VecOperands (t
) || VEX_check_operands (t
))
6044 specific_error
= i
.error
;
6048 /* We've found a match; break out of loop. */
6052 if (t
== current_templates
->end
)
6054 /* We found no match. */
6055 const char *err_msg
;
6056 switch (specific_error
? specific_error
: i
.error
)
6060 case operand_size_mismatch
:
6061 err_msg
= _("operand size mismatch");
6063 case operand_type_mismatch
:
6064 err_msg
= _("operand type mismatch");
6066 case register_type_mismatch
:
6067 err_msg
= _("register type mismatch");
6069 case number_of_operands_mismatch
:
6070 err_msg
= _("number of operands mismatch");
6072 case invalid_instruction_suffix
:
6073 err_msg
= _("invalid instruction suffix");
6076 err_msg
= _("constant doesn't fit in 4 bits");
6078 case unsupported_with_intel_mnemonic
:
6079 err_msg
= _("unsupported with Intel mnemonic");
6081 case unsupported_syntax
:
6082 err_msg
= _("unsupported syntax");
6085 as_bad (_("unsupported instruction `%s'"),
6086 current_templates
->start
->name
);
6088 case invalid_vsib_address
:
6089 err_msg
= _("invalid VSIB address");
6091 case invalid_vector_register_set
:
6092 err_msg
= _("mask, index, and destination registers must be distinct");
6094 case unsupported_vector_index_register
:
6095 err_msg
= _("unsupported vector index register");
6097 case unsupported_broadcast
:
6098 err_msg
= _("unsupported broadcast");
6100 case broadcast_needed
:
6101 err_msg
= _("broadcast is needed for operand of such type");
6103 case unsupported_masking
:
6104 err_msg
= _("unsupported masking");
6106 case mask_not_on_destination
:
6107 err_msg
= _("mask not on destination operand");
6109 case no_default_mask
:
6110 err_msg
= _("default mask isn't allowed");
6112 case unsupported_rc_sae
:
6113 err_msg
= _("unsupported static rounding/sae");
6115 case rc_sae_operand_not_last_imm
:
6117 err_msg
= _("RC/SAE operand must precede immediate operands");
6119 err_msg
= _("RC/SAE operand must follow immediate operands");
6121 case invalid_register_operand
:
6122 err_msg
= _("invalid register operand");
6125 as_bad (_("%s for `%s'"), err_msg
,
6126 current_templates
->start
->name
);
6130 if (!quiet_warnings
)
6133 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6134 as_warn (_("indirect %s without `*'"), t
->name
);
6136 if (t
->opcode_modifier
.isprefix
6137 && t
->opcode_modifier
.ignoresize
)
6139 /* Warn them that a data or address size prefix doesn't
6140 affect assembly of the next line of code. */
6141 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6145 /* Copy the template we found. */
6148 if (addr_prefix_disp
!= -1)
6149 i
.tm
.operand_types
[addr_prefix_disp
]
6150 = operand_types
[addr_prefix_disp
];
6152 if (found_reverse_match
)
6154 /* If we found a reverse match we must alter the opcode direction
6155 bit and clear/flip the regmem modifier one. found_reverse_match
6156 holds bits to change (different for int & float insns). */
6158 i
.tm
.base_opcode
^= found_reverse_match
;
6160 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6161 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6163 /* Certain SIMD insns have their load forms specified in the opcode
6164 table, and hence we need to _set_ RegMem instead of clearing it.
6165 We need to avoid setting the bit though on insns like KMOVW. */
6166 i
.tm
.opcode_modifier
.regmem
6167 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6168 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6169 && !i
.tm
.opcode_modifier
.regmem
;
6178 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6179 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6181 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6183 as_bad (_("`%s' operand %u must use `%ses' segment"),
6185 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6190 /* There's only ever one segment override allowed per instruction.
6191 This instruction possibly has a legal segment override on the
6192 second operand, so copy the segment to where non-string
6193 instructions store it, allowing common code. */
6194 i
.seg
[op
] = i
.seg
[1];
6200 process_suffix (void)
6202 /* If matched instruction specifies an explicit instruction mnemonic
6204 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6205 i
.suffix
= WORD_MNEM_SUFFIX
;
6206 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6207 i
.suffix
= LONG_MNEM_SUFFIX
;
6208 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6209 i
.suffix
= QWORD_MNEM_SUFFIX
;
6210 else if (i
.reg_operands
6211 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
))
6213 /* If there's no instruction mnemonic suffix we try to invent one
6214 based on GPR operands. */
6217 /* We take i.suffix from the last register operand specified,
6218 Destination register type is more significant than source
6219 register type. crc32 in SSE4.2 prefers source register
6221 if (i
.tm
.base_opcode
== 0xf20f38f0
6222 && i
.types
[0].bitfield
.class == Reg
)
6224 if (i
.types
[0].bitfield
.byte
)
6225 i
.suffix
= BYTE_MNEM_SUFFIX
;
6226 else if (i
.types
[0].bitfield
.word
)
6227 i
.suffix
= WORD_MNEM_SUFFIX
;
6228 else if (i
.types
[0].bitfield
.dword
)
6229 i
.suffix
= LONG_MNEM_SUFFIX
;
6230 else if (i
.types
[0].bitfield
.qword
)
6231 i
.suffix
= QWORD_MNEM_SUFFIX
;
6238 if (i
.tm
.base_opcode
== 0xf20f38f0)
6240 /* We have to know the operand size for crc32. */
6241 as_bad (_("ambiguous memory operand size for `%s`"),
6246 for (op
= i
.operands
; --op
>= 0;)
6247 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6248 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6250 if (i
.types
[op
].bitfield
.class != Reg
)
6252 if (i
.types
[op
].bitfield
.byte
)
6253 i
.suffix
= BYTE_MNEM_SUFFIX
;
6254 else if (i
.types
[op
].bitfield
.word
)
6255 i
.suffix
= WORD_MNEM_SUFFIX
;
6256 else if (i
.types
[op
].bitfield
.dword
)
6257 i
.suffix
= LONG_MNEM_SUFFIX
;
6258 else if (i
.types
[op
].bitfield
.qword
)
6259 i
.suffix
= QWORD_MNEM_SUFFIX
;
6266 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6269 && i
.tm
.opcode_modifier
.ignoresize
6270 && i
.tm
.opcode_modifier
.no_bsuf
)
6272 else if (!check_byte_reg ())
6275 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6278 && i
.tm
.opcode_modifier
.ignoresize
6279 && i
.tm
.opcode_modifier
.no_lsuf
6280 && !i
.tm
.opcode_modifier
.todword
6281 && !i
.tm
.opcode_modifier
.toqword
)
6283 else if (!check_long_reg ())
6286 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6289 && i
.tm
.opcode_modifier
.ignoresize
6290 && i
.tm
.opcode_modifier
.no_qsuf
6291 && !i
.tm
.opcode_modifier
.todword
6292 && !i
.tm
.opcode_modifier
.toqword
)
6294 else if (!check_qword_reg ())
6297 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6300 && i
.tm
.opcode_modifier
.ignoresize
6301 && i
.tm
.opcode_modifier
.no_wsuf
)
6303 else if (!check_word_reg ())
6306 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6307 /* Do nothing if the instruction is going to ignore the prefix. */
6312 else if (i
.tm
.opcode_modifier
.defaultsize
6314 /* exclude fldenv/frstor/fsave/fstenv */
6315 && i
.tm
.opcode_modifier
.no_ssuf
6316 /* exclude sysret */
6317 && i
.tm
.base_opcode
!= 0x0f07)
6319 i
.suffix
= stackop_size
;
6320 if (stackop_size
== LONG_MNEM_SUFFIX
)
6322 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6323 .code16gcc directive to support 16-bit mode with
6324 32-bit address. For IRET without a suffix, generate
6325 16-bit IRET (opcode 0xcf) to return from an interrupt
6327 if (i
.tm
.base_opcode
== 0xcf)
6329 i
.suffix
= WORD_MNEM_SUFFIX
;
6330 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6332 /* Warn about changed behavior for segment register push/pop. */
6333 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6334 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6338 else if (intel_syntax
6340 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6341 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6342 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6343 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6344 && i
.tm
.extension_opcode
<= 3)))
6349 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6351 i
.suffix
= QWORD_MNEM_SUFFIX
;
6356 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6357 i
.suffix
= LONG_MNEM_SUFFIX
;
6360 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6361 i
.suffix
= WORD_MNEM_SUFFIX
;
6370 if (i
.tm
.opcode_modifier
.w
)
6372 as_bad (_("no instruction mnemonic suffix given and "
6373 "no register operands; can't size instruction"));
6379 unsigned int suffixes
;
6381 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6382 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6384 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6386 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6388 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6390 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6393 /* There are more than suffix matches. */
6394 if (i
.tm
.opcode_modifier
.w
6395 || ((suffixes
& (suffixes
- 1))
6396 && !i
.tm
.opcode_modifier
.defaultsize
6397 && !i
.tm
.opcode_modifier
.ignoresize
))
6399 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6405 /* Change the opcode based on the operand size given by i.suffix. */
6408 /* Size floating point instruction. */
6409 case LONG_MNEM_SUFFIX
:
6410 if (i
.tm
.opcode_modifier
.floatmf
)
6412 i
.tm
.base_opcode
^= 4;
6416 case WORD_MNEM_SUFFIX
:
6417 case QWORD_MNEM_SUFFIX
:
6418 /* It's not a byte, select word/dword operation. */
6419 if (i
.tm
.opcode_modifier
.w
)
6421 if (i
.tm
.opcode_modifier
.shortform
)
6422 i
.tm
.base_opcode
|= 8;
6424 i
.tm
.base_opcode
|= 1;
6427 case SHORT_MNEM_SUFFIX
:
6428 /* Now select between word & dword operations via the operand
6429 size prefix, except for instructions that will ignore this
6431 if (i
.reg_operands
> 0
6432 && i
.types
[0].bitfield
.class == Reg
6433 && i
.tm
.opcode_modifier
.addrprefixopreg
6434 && (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6435 || i
.operands
== 1))
6437 /* The address size override prefix changes the size of the
6439 if ((flag_code
== CODE_32BIT
6440 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6441 || (flag_code
!= CODE_32BIT
6442 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6443 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6446 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6447 && !i
.tm
.opcode_modifier
.ignoresize
6448 && !i
.tm
.opcode_modifier
.floatmf
6449 && !is_any_vex_encoding (&i
.tm
)
6450 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6451 || (flag_code
== CODE_64BIT
6452 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6454 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6456 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6457 prefix
= ADDR_PREFIX_OPCODE
;
6459 if (!add_prefix (prefix
))
6463 /* Set mode64 for an operand. */
6464 if (i
.suffix
== QWORD_MNEM_SUFFIX
6465 && flag_code
== CODE_64BIT
6466 && !i
.tm
.opcode_modifier
.norex64
6467 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6469 && ! (i
.operands
== 2
6470 && i
.tm
.base_opcode
== 0x90
6471 && i
.tm
.extension_opcode
== None
6472 && i
.types
[0].bitfield
.instance
== Accum
6473 && i
.types
[0].bitfield
.qword
6474 && i
.types
[1].bitfield
.instance
== Accum
6475 && i
.types
[1].bitfield
.qword
))
6481 if (i
.reg_operands
!= 0
6483 && i
.tm
.opcode_modifier
.addrprefixopreg
6484 && i
.tm
.operand_types
[0].bitfield
.instance
!= Accum
)
6486 /* Check invalid register operand when the address size override
6487 prefix changes the size of register operands. */
6489 enum { need_word
, need_dword
, need_qword
} need
;
6491 if (flag_code
== CODE_32BIT
)
6492 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6495 if (i
.prefix
[ADDR_PREFIX
])
6498 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6501 for (op
= 0; op
< i
.operands
; op
++)
6502 if (i
.types
[op
].bitfield
.class == Reg
6503 && ((need
== need_word
6504 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6505 || (need
== need_dword
6506 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6507 || (need
== need_qword
6508 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6510 as_bad (_("invalid register operand size for `%s'"),
6520 check_byte_reg (void)
6524 for (op
= i
.operands
; --op
>= 0;)
6526 /* Skip non-register operands. */
6527 if (i
.types
[op
].bitfield
.class != Reg
)
6530 /* If this is an eight bit register, it's OK. If it's the 16 or
6531 32 bit version of an eight bit register, we will just use the
6532 low portion, and that's OK too. */
6533 if (i
.types
[op
].bitfield
.byte
)
6536 /* I/O port address operands are OK too. */
6537 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6538 && i
.tm
.operand_types
[op
].bitfield
.word
)
6541 /* crc32 doesn't generate this warning. */
6542 if (i
.tm
.base_opcode
== 0xf20f38f0)
6545 if ((i
.types
[op
].bitfield
.word
6546 || i
.types
[op
].bitfield
.dword
6547 || i
.types
[op
].bitfield
.qword
)
6548 && i
.op
[op
].regs
->reg_num
< 4
6549 /* Prohibit these changes in 64bit mode, since the lowering
6550 would be more complicated. */
6551 && flag_code
!= CODE_64BIT
)
6553 #if REGISTER_WARNINGS
6554 if (!quiet_warnings
)
6555 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6557 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6558 ? REGNAM_AL
- REGNAM_AX
6559 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6561 i
.op
[op
].regs
->reg_name
,
6566 /* Any other register is bad. */
6567 if (i
.types
[op
].bitfield
.class == Reg
6568 || i
.types
[op
].bitfield
.class == RegMMX
6569 || i
.types
[op
].bitfield
.class == RegSIMD
6570 || i
.types
[op
].bitfield
.class == SReg
6571 || i
.types
[op
].bitfield
.class == RegCR
6572 || i
.types
[op
].bitfield
.class == RegDR
6573 || i
.types
[op
].bitfield
.class == RegTR
)
6575 as_bad (_("`%s%s' not allowed with `%s%c'"),
6577 i
.op
[op
].regs
->reg_name
,
6587 check_long_reg (void)
6591 for (op
= i
.operands
; --op
>= 0;)
6592 /* Skip non-register operands. */
6593 if (i
.types
[op
].bitfield
.class != Reg
)
6595 /* Reject eight bit registers, except where the template requires
6596 them. (eg. movzb) */
6597 else if (i
.types
[op
].bitfield
.byte
6598 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6599 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6600 && (i
.tm
.operand_types
[op
].bitfield
.word
6601 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6603 as_bad (_("`%s%s' not allowed with `%s%c'"),
6605 i
.op
[op
].regs
->reg_name
,
6610 /* Warn if the e prefix on a general reg is missing. */
6611 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6612 && i
.types
[op
].bitfield
.word
6613 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6614 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6615 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6617 /* Prohibit these changes in the 64bit mode, since the
6618 lowering is more complicated. */
6619 if (flag_code
== CODE_64BIT
)
6621 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6622 register_prefix
, i
.op
[op
].regs
->reg_name
,
6626 #if REGISTER_WARNINGS
6627 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6629 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6630 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6633 /* Warn if the r prefix on a general reg is present. */
6634 else if (i
.types
[op
].bitfield
.qword
6635 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6636 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6637 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6640 && i
.tm
.opcode_modifier
.toqword
6641 && i
.types
[0].bitfield
.class != RegSIMD
)
6643 /* Convert to QWORD. We want REX byte. */
6644 i
.suffix
= QWORD_MNEM_SUFFIX
;
6648 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6649 register_prefix
, i
.op
[op
].regs
->reg_name
,
6658 check_qword_reg (void)
6662 for (op
= i
.operands
; --op
>= 0; )
6663 /* Skip non-register operands. */
6664 if (i
.types
[op
].bitfield
.class != Reg
)
6666 /* Reject eight bit registers, except where the template requires
6667 them. (eg. movzb) */
6668 else if (i
.types
[op
].bitfield
.byte
6669 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6670 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6671 && (i
.tm
.operand_types
[op
].bitfield
.word
6672 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6674 as_bad (_("`%s%s' not allowed with `%s%c'"),
6676 i
.op
[op
].regs
->reg_name
,
6681 /* Warn if the r prefix on a general reg is missing. */
6682 else if ((i
.types
[op
].bitfield
.word
6683 || i
.types
[op
].bitfield
.dword
)
6684 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6685 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6686 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6688 /* Prohibit these changes in the 64bit mode, since the
6689 lowering is more complicated. */
6691 && i
.tm
.opcode_modifier
.todword
6692 && i
.types
[0].bitfield
.class != RegSIMD
)
6694 /* Convert to DWORD. We don't want REX byte. */
6695 i
.suffix
= LONG_MNEM_SUFFIX
;
6699 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6700 register_prefix
, i
.op
[op
].regs
->reg_name
,
6709 check_word_reg (void)
6712 for (op
= i
.operands
; --op
>= 0;)
6713 /* Skip non-register operands. */
6714 if (i
.types
[op
].bitfield
.class != Reg
)
6716 /* Reject eight bit registers, except where the template requires
6717 them. (eg. movzb) */
6718 else if (i
.types
[op
].bitfield
.byte
6719 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6720 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6721 && (i
.tm
.operand_types
[op
].bitfield
.word
6722 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6724 as_bad (_("`%s%s' not allowed with `%s%c'"),
6726 i
.op
[op
].regs
->reg_name
,
6731 /* Warn if the e or r prefix on a general reg is present. */
6732 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6733 && (i
.types
[op
].bitfield
.dword
6734 || i
.types
[op
].bitfield
.qword
)
6735 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6736 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6737 && i
.tm
.operand_types
[op
].bitfield
.word
)
6739 /* Prohibit these changes in the 64bit mode, since the
6740 lowering is more complicated. */
6741 if (flag_code
== CODE_64BIT
)
6743 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6744 register_prefix
, i
.op
[op
].regs
->reg_name
,
6748 #if REGISTER_WARNINGS
6749 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6751 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6752 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6759 update_imm (unsigned int j
)
6761 i386_operand_type overlap
= i
.types
[j
];
6762 if ((overlap
.bitfield
.imm8
6763 || overlap
.bitfield
.imm8s
6764 || overlap
.bitfield
.imm16
6765 || overlap
.bitfield
.imm32
6766 || overlap
.bitfield
.imm32s
6767 || overlap
.bitfield
.imm64
)
6768 && !operand_type_equal (&overlap
, &imm8
)
6769 && !operand_type_equal (&overlap
, &imm8s
)
6770 && !operand_type_equal (&overlap
, &imm16
)
6771 && !operand_type_equal (&overlap
, &imm32
)
6772 && !operand_type_equal (&overlap
, &imm32s
)
6773 && !operand_type_equal (&overlap
, &imm64
))
6777 i386_operand_type temp
;
6779 operand_type_set (&temp
, 0);
6780 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6782 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6783 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6785 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6786 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6787 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6789 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6790 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6793 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6796 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6797 || operand_type_equal (&overlap
, &imm16_32
)
6798 || operand_type_equal (&overlap
, &imm16_32s
))
6800 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6805 if (!operand_type_equal (&overlap
, &imm8
)
6806 && !operand_type_equal (&overlap
, &imm8s
)
6807 && !operand_type_equal (&overlap
, &imm16
)
6808 && !operand_type_equal (&overlap
, &imm32
)
6809 && !operand_type_equal (&overlap
, &imm32s
)
6810 && !operand_type_equal (&overlap
, &imm64
))
6812 as_bad (_("no instruction mnemonic suffix given; "
6813 "can't determine immediate size"));
6817 i
.types
[j
] = overlap
;
6827 /* Update the first 2 immediate operands. */
6828 n
= i
.operands
> 2 ? 2 : i
.operands
;
6831 for (j
= 0; j
< n
; j
++)
6832 if (update_imm (j
) == 0)
6835 /* The 3rd operand can't be immediate operand. */
6836 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6843 process_operands (void)
6845 /* Default segment register this instruction will use for memory
6846 accesses. 0 means unknown. This is only for optimizing out
6847 unnecessary segment overrides. */
6848 const seg_entry
*default_seg
= 0;
6850 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6852 unsigned int dupl
= i
.operands
;
6853 unsigned int dest
= dupl
- 1;
6856 /* The destination must be an xmm register. */
6857 gas_assert (i
.reg_operands
6858 && MAX_OPERANDS
> dupl
6859 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6861 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6862 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6864 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6866 /* Keep xmm0 for instructions with VEX prefix and 3
6868 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
6869 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
6874 /* We remove the first xmm0 and keep the number of
6875 operands unchanged, which in fact duplicates the
6877 for (j
= 1; j
< i
.operands
; j
++)
6879 i
.op
[j
- 1] = i
.op
[j
];
6880 i
.types
[j
- 1] = i
.types
[j
];
6881 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6882 i
.flags
[j
- 1] = i
.flags
[j
];
6886 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6888 gas_assert ((MAX_OPERANDS
- 1) > dupl
6889 && (i
.tm
.opcode_modifier
.vexsources
6892 /* Add the implicit xmm0 for instructions with VEX prefix
6894 for (j
= i
.operands
; j
> 0; j
--)
6896 i
.op
[j
] = i
.op
[j
- 1];
6897 i
.types
[j
] = i
.types
[j
- 1];
6898 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6899 i
.flags
[j
] = i
.flags
[j
- 1];
6902 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6903 i
.types
[0] = regxmm
;
6904 i
.tm
.operand_types
[0] = regxmm
;
6907 i
.reg_operands
+= 2;
6912 i
.op
[dupl
] = i
.op
[dest
];
6913 i
.types
[dupl
] = i
.types
[dest
];
6914 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6915 i
.flags
[dupl
] = i
.flags
[dest
];
6924 i
.op
[dupl
] = i
.op
[dest
];
6925 i
.types
[dupl
] = i
.types
[dest
];
6926 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6927 i
.flags
[dupl
] = i
.flags
[dest
];
6930 if (i
.tm
.opcode_modifier
.immext
)
6933 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6934 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6938 for (j
= 1; j
< i
.operands
; j
++)
6940 i
.op
[j
- 1] = i
.op
[j
];
6941 i
.types
[j
- 1] = i
.types
[j
];
6943 /* We need to adjust fields in i.tm since they are used by
6944 build_modrm_byte. */
6945 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6947 i
.flags
[j
- 1] = i
.flags
[j
];
6954 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6956 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6958 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6959 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
6960 regnum
= register_number (i
.op
[1].regs
);
6961 first_reg_in_group
= regnum
& ~3;
6962 last_reg_in_group
= first_reg_in_group
+ 3;
6963 if (regnum
!= first_reg_in_group
)
6964 as_warn (_("source register `%s%s' implicitly denotes"
6965 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6966 register_prefix
, i
.op
[1].regs
->reg_name
,
6967 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6968 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6971 else if (i
.tm
.opcode_modifier
.regkludge
)
6973 /* The imul $imm, %reg instruction is converted into
6974 imul $imm, %reg, %reg, and the clr %reg instruction
6975 is converted into xor %reg, %reg. */
6977 unsigned int first_reg_op
;
6979 if (operand_type_check (i
.types
[0], reg
))
6983 /* Pretend we saw the extra register operand. */
6984 gas_assert (i
.reg_operands
== 1
6985 && i
.op
[first_reg_op
+ 1].regs
== 0);
6986 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6987 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6992 if (i
.tm
.opcode_modifier
.modrm
)
6994 /* The opcode is completed (modulo i.tm.extension_opcode which
6995 must be put into the modrm byte). Now, we make the modrm and
6996 index base bytes based on all the info we've collected. */
6998 default_seg
= build_modrm_byte ();
7000 else if (i
.types
[0].bitfield
.class == SReg
)
7002 if (flag_code
!= CODE_64BIT
7003 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7004 && i
.op
[0].regs
->reg_num
== 1
7005 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7006 && i
.op
[0].regs
->reg_num
< 4)
7008 as_bad (_("you can't `%s %s%s'"),
7009 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7012 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7014 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7015 i
.tm
.opcode_length
= 2;
7017 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7019 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7023 else if (i
.tm
.opcode_modifier
.isstring
)
7025 /* For the string instructions that allow a segment override
7026 on one of their operands, the default segment is ds. */
7029 else if (i
.tm
.opcode_modifier
.shortform
)
7031 /* The register or float register operand is in operand
7033 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7035 /* Register goes in low 3 bits of opcode. */
7036 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7037 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7039 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7041 /* Warn about some common errors, but press on regardless.
7042 The first case can be generated by gcc (<= 2.8.1). */
7043 if (i
.operands
== 2)
7045 /* Reversed arguments on faddp, fsubp, etc. */
7046 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7047 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7048 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7052 /* Extraneous `l' suffix on fp insn. */
7053 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7054 register_prefix
, i
.op
[0].regs
->reg_name
);
7059 if (i
.tm
.base_opcode
== 0x8d /* lea */
7062 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7064 /* If a segment was explicitly specified, and the specified segment
7065 is not the default, use an opcode prefix to select it. If we
7066 never figured out what the default segment is, then default_seg
7067 will be zero at this point, and the specified segment prefix will
7069 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7071 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7077 static const seg_entry
*
7078 build_modrm_byte (void)
7080 const seg_entry
*default_seg
= 0;
7081 unsigned int source
, dest
;
7084 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7087 unsigned int nds
, reg_slot
;
7090 dest
= i
.operands
- 1;
7093 /* There are 2 kinds of instructions:
7094 1. 5 operands: 4 register operands or 3 register operands
7095 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7096 VexW0 or VexW1. The destination must be either XMM, YMM or
7098 2. 4 operands: 4 register operands or 3 register operands
7099 plus 1 memory operand, with VexXDS. */
7100 gas_assert ((i
.reg_operands
== 4
7101 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7102 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7103 && i
.tm
.opcode_modifier
.vexw
7104 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7106 /* If VexW1 is set, the first non-immediate operand is the source and
7107 the second non-immediate one is encoded in the immediate operand. */
7108 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7110 source
= i
.imm_operands
;
7111 reg_slot
= i
.imm_operands
+ 1;
7115 source
= i
.imm_operands
+ 1;
7116 reg_slot
= i
.imm_operands
;
7119 if (i
.imm_operands
== 0)
7121 /* When there is no immediate operand, generate an 8bit
7122 immediate operand to encode the first operand. */
7123 exp
= &im_expressions
[i
.imm_operands
++];
7124 i
.op
[i
.operands
].imms
= exp
;
7125 i
.types
[i
.operands
] = imm8
;
7128 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7129 exp
->X_op
= O_constant
;
7130 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7131 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7135 gas_assert (i
.imm_operands
== 1);
7136 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7137 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7139 /* Turn on Imm8 again so that output_imm will generate it. */
7140 i
.types
[0].bitfield
.imm8
= 1;
7142 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7143 i
.op
[0].imms
->X_add_number
7144 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7145 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7148 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7149 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7154 /* i.reg_operands MUST be the number of real register operands;
7155 implicit registers do not count. If there are 3 register
7156 operands, it must be a instruction with VexNDS. For a
7157 instruction with VexNDD, the destination register is encoded
7158 in VEX prefix. If there are 4 register operands, it must be
7159 a instruction with VEX prefix and 3 sources. */
7160 if (i
.mem_operands
== 0
7161 && ((i
.reg_operands
== 2
7162 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7163 || (i
.reg_operands
== 3
7164 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7165 || (i
.reg_operands
== 4 && vex_3_sources
)))
7173 /* When there are 3 operands, one of them may be immediate,
7174 which may be the first or the last operand. Otherwise,
7175 the first operand must be shift count register (cl) or it
7176 is an instruction with VexNDS. */
7177 gas_assert (i
.imm_operands
== 1
7178 || (i
.imm_operands
== 0
7179 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7180 || (i
.types
[0].bitfield
.instance
== RegC
7181 && i
.types
[0].bitfield
.byte
))));
7182 if (operand_type_check (i
.types
[0], imm
)
7183 || (i
.types
[0].bitfield
.instance
== RegC
7184 && i
.types
[0].bitfield
.byte
))
7190 /* When there are 4 operands, the first two must be 8bit
7191 immediate operands. The source operand will be the 3rd
7194 For instructions with VexNDS, if the first operand
7195 an imm8, the source operand is the 2nd one. If the last
7196 operand is imm8, the source operand is the first one. */
7197 gas_assert ((i
.imm_operands
== 2
7198 && i
.types
[0].bitfield
.imm8
7199 && i
.types
[1].bitfield
.imm8
)
7200 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7201 && i
.imm_operands
== 1
7202 && (i
.types
[0].bitfield
.imm8
7203 || i
.types
[i
.operands
- 1].bitfield
.imm8
7205 if (i
.imm_operands
== 2)
7209 if (i
.types
[0].bitfield
.imm8
)
7216 if (is_evex_encoding (&i
.tm
))
7218 /* For EVEX instructions, when there are 5 operands, the
7219 first one must be immediate operand. If the second one
7220 is immediate operand, the source operand is the 3th
7221 one. If the last one is immediate operand, the source
7222 operand is the 2nd one. */
7223 gas_assert (i
.imm_operands
== 2
7224 && i
.tm
.opcode_modifier
.sae
7225 && operand_type_check (i
.types
[0], imm
));
7226 if (operand_type_check (i
.types
[1], imm
))
7228 else if (operand_type_check (i
.types
[4], imm
))
7242 /* RC/SAE operand could be between DEST and SRC. That happens
7243 when one operand is GPR and the other one is XMM/YMM/ZMM
7245 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7248 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7250 /* For instructions with VexNDS, the register-only source
7251 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7252 register. It is encoded in VEX prefix. */
7254 i386_operand_type op
;
7257 /* Check register-only source operand when two source
7258 operands are swapped. */
7259 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7260 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7268 op
= i
.tm
.operand_types
[vvvv
];
7269 if ((dest
+ 1) >= i
.operands
7270 || ((op
.bitfield
.class != Reg
7271 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7272 && op
.bitfield
.class != RegSIMD
7273 && !operand_type_equal (&op
, ®mask
)))
7275 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7281 /* One of the register operands will be encoded in the i.rm.reg
7282 field, the other in the combined i.rm.mode and i.rm.regmem
7283 fields. If no form of this instruction supports a memory
7284 destination operand, then we assume the source operand may
7285 sometimes be a memory operand and so we need to store the
7286 destination in the i.rm.reg field. */
7287 if (!i
.tm
.opcode_modifier
.regmem
7288 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7290 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7291 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7292 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7293 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7294 i
.has_regmmx
= TRUE
;
7295 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7296 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7298 if (i
.types
[dest
].bitfield
.zmmword
7299 || i
.types
[source
].bitfield
.zmmword
)
7300 i
.has_regzmm
= TRUE
;
7301 else if (i
.types
[dest
].bitfield
.ymmword
7302 || i
.types
[source
].bitfield
.ymmword
)
7303 i
.has_regymm
= TRUE
;
7305 i
.has_regxmm
= TRUE
;
7307 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7309 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7311 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7313 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7318 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7319 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7320 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7322 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7324 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7326 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7329 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7331 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7334 add_prefix (LOCK_PREFIX_OPCODE
);
7338 { /* If it's not 2 reg operands... */
7343 unsigned int fake_zero_displacement
= 0;
7346 for (op
= 0; op
< i
.operands
; op
++)
7347 if (i
.flags
[op
] & Operand_Mem
)
7349 gas_assert (op
< i
.operands
);
7351 if (i
.tm
.opcode_modifier
.vecsib
)
7353 if (i
.index_reg
->reg_num
== RegIZ
)
7356 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7359 i
.sib
.base
= NO_BASE_REGISTER
;
7360 i
.sib
.scale
= i
.log2_scale_factor
;
7361 i
.types
[op
].bitfield
.disp8
= 0;
7362 i
.types
[op
].bitfield
.disp16
= 0;
7363 i
.types
[op
].bitfield
.disp64
= 0;
7364 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7366 /* Must be 32 bit */
7367 i
.types
[op
].bitfield
.disp32
= 1;
7368 i
.types
[op
].bitfield
.disp32s
= 0;
7372 i
.types
[op
].bitfield
.disp32
= 0;
7373 i
.types
[op
].bitfield
.disp32s
= 1;
7376 i
.sib
.index
= i
.index_reg
->reg_num
;
7377 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7379 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7385 if (i
.base_reg
== 0)
7388 if (!i
.disp_operands
)
7389 fake_zero_displacement
= 1;
7390 if (i
.index_reg
== 0)
7392 i386_operand_type newdisp
;
7394 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7395 /* Operand is just <disp> */
7396 if (flag_code
== CODE_64BIT
)
7398 /* 64bit mode overwrites the 32bit absolute
7399 addressing by RIP relative addressing and
7400 absolute addressing is encoded by one of the
7401 redundant SIB forms. */
7402 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7403 i
.sib
.base
= NO_BASE_REGISTER
;
7404 i
.sib
.index
= NO_INDEX_REGISTER
;
7405 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7407 else if ((flag_code
== CODE_16BIT
)
7408 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7410 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7415 i
.rm
.regmem
= NO_BASE_REGISTER
;
7418 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7419 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7421 else if (!i
.tm
.opcode_modifier
.vecsib
)
7423 /* !i.base_reg && i.index_reg */
7424 if (i
.index_reg
->reg_num
== RegIZ
)
7425 i
.sib
.index
= NO_INDEX_REGISTER
;
7427 i
.sib
.index
= i
.index_reg
->reg_num
;
7428 i
.sib
.base
= NO_BASE_REGISTER
;
7429 i
.sib
.scale
= i
.log2_scale_factor
;
7430 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7431 i
.types
[op
].bitfield
.disp8
= 0;
7432 i
.types
[op
].bitfield
.disp16
= 0;
7433 i
.types
[op
].bitfield
.disp64
= 0;
7434 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7436 /* Must be 32 bit */
7437 i
.types
[op
].bitfield
.disp32
= 1;
7438 i
.types
[op
].bitfield
.disp32s
= 0;
7442 i
.types
[op
].bitfield
.disp32
= 0;
7443 i
.types
[op
].bitfield
.disp32s
= 1;
7445 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7449 /* RIP addressing for 64bit mode. */
7450 else if (i
.base_reg
->reg_num
== RegIP
)
7452 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7453 i
.rm
.regmem
= NO_BASE_REGISTER
;
7454 i
.types
[op
].bitfield
.disp8
= 0;
7455 i
.types
[op
].bitfield
.disp16
= 0;
7456 i
.types
[op
].bitfield
.disp32
= 0;
7457 i
.types
[op
].bitfield
.disp32s
= 1;
7458 i
.types
[op
].bitfield
.disp64
= 0;
7459 i
.flags
[op
] |= Operand_PCrel
;
7460 if (! i
.disp_operands
)
7461 fake_zero_displacement
= 1;
7463 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7465 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7466 switch (i
.base_reg
->reg_num
)
7469 if (i
.index_reg
== 0)
7471 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7472 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7476 if (i
.index_reg
== 0)
7479 if (operand_type_check (i
.types
[op
], disp
) == 0)
7481 /* fake (%bp) into 0(%bp) */
7482 i
.types
[op
].bitfield
.disp8
= 1;
7483 fake_zero_displacement
= 1;
7486 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7487 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7489 default: /* (%si) -> 4 or (%di) -> 5 */
7490 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7492 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7494 else /* i.base_reg and 32/64 bit mode */
7496 if (flag_code
== CODE_64BIT
7497 && operand_type_check (i
.types
[op
], disp
))
7499 i
.types
[op
].bitfield
.disp16
= 0;
7500 i
.types
[op
].bitfield
.disp64
= 0;
7501 if (i
.prefix
[ADDR_PREFIX
] == 0)
7503 i
.types
[op
].bitfield
.disp32
= 0;
7504 i
.types
[op
].bitfield
.disp32s
= 1;
7508 i
.types
[op
].bitfield
.disp32
= 1;
7509 i
.types
[op
].bitfield
.disp32s
= 0;
7513 if (!i
.tm
.opcode_modifier
.vecsib
)
7514 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7515 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7517 i
.sib
.base
= i
.base_reg
->reg_num
;
7518 /* x86-64 ignores REX prefix bit here to avoid decoder
7520 if (!(i
.base_reg
->reg_flags
& RegRex
)
7521 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7522 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7524 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7526 fake_zero_displacement
= 1;
7527 i
.types
[op
].bitfield
.disp8
= 1;
7529 i
.sib
.scale
= i
.log2_scale_factor
;
7530 if (i
.index_reg
== 0)
7532 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7533 /* <disp>(%esp) becomes two byte modrm with no index
7534 register. We've already stored the code for esp
7535 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7536 Any base register besides %esp will not use the
7537 extra modrm byte. */
7538 i
.sib
.index
= NO_INDEX_REGISTER
;
7540 else if (!i
.tm
.opcode_modifier
.vecsib
)
7542 if (i
.index_reg
->reg_num
== RegIZ
)
7543 i
.sib
.index
= NO_INDEX_REGISTER
;
7545 i
.sib
.index
= i
.index_reg
->reg_num
;
7546 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7547 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7552 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7553 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7557 if (!fake_zero_displacement
7561 fake_zero_displacement
= 1;
7562 if (i
.disp_encoding
== disp_encoding_8bit
)
7563 i
.types
[op
].bitfield
.disp8
= 1;
7565 i
.types
[op
].bitfield
.disp32
= 1;
7567 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7571 if (fake_zero_displacement
)
7573 /* Fakes a zero displacement assuming that i.types[op]
7574 holds the correct displacement size. */
7577 gas_assert (i
.op
[op
].disps
== 0);
7578 exp
= &disp_expressions
[i
.disp_operands
++];
7579 i
.op
[op
].disps
= exp
;
7580 exp
->X_op
= O_constant
;
7581 exp
->X_add_number
= 0;
7582 exp
->X_add_symbol
= (symbolS
*) 0;
7583 exp
->X_op_symbol
= (symbolS
*) 0;
7591 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7593 if (operand_type_check (i
.types
[0], imm
))
7594 i
.vex
.register_specifier
= NULL
;
7597 /* VEX.vvvv encodes one of the sources when the first
7598 operand is not an immediate. */
7599 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7600 i
.vex
.register_specifier
= i
.op
[0].regs
;
7602 i
.vex
.register_specifier
= i
.op
[1].regs
;
7605 /* Destination is a XMM register encoded in the ModRM.reg
7607 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7608 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7611 /* ModRM.rm and VEX.B encodes the other source. */
7612 if (!i
.mem_operands
)
7616 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7617 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7619 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7621 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7625 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7627 i
.vex
.register_specifier
= i
.op
[2].regs
;
7628 if (!i
.mem_operands
)
7631 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7632 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7636 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7637 (if any) based on i.tm.extension_opcode. Again, we must be
7638 careful to make sure that segment/control/debug/test/MMX
7639 registers are coded into the i.rm.reg field. */
7640 else if (i
.reg_operands
)
7643 unsigned int vex_reg
= ~0;
7645 for (op
= 0; op
< i
.operands
; op
++)
7647 if (i
.types
[op
].bitfield
.class == Reg
7648 || i
.types
[op
].bitfield
.class == RegBND
7649 || i
.types
[op
].bitfield
.class == RegMask
7650 || i
.types
[op
].bitfield
.class == SReg
7651 || i
.types
[op
].bitfield
.class == RegCR
7652 || i
.types
[op
].bitfield
.class == RegDR
7653 || i
.types
[op
].bitfield
.class == RegTR
)
7655 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7657 if (i
.types
[op
].bitfield
.zmmword
)
7658 i
.has_regzmm
= TRUE
;
7659 else if (i
.types
[op
].bitfield
.ymmword
)
7660 i
.has_regymm
= TRUE
;
7662 i
.has_regxmm
= TRUE
;
7665 if (i
.types
[op
].bitfield
.class == RegMMX
)
7667 i
.has_regmmx
= TRUE
;
7674 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7676 /* For instructions with VexNDS, the register-only
7677 source operand is encoded in VEX prefix. */
7678 gas_assert (mem
!= (unsigned int) ~0);
7683 gas_assert (op
< i
.operands
);
7687 /* Check register-only source operand when two source
7688 operands are swapped. */
7689 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7690 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7694 gas_assert (mem
== (vex_reg
+ 1)
7695 && op
< i
.operands
);
7700 gas_assert (vex_reg
< i
.operands
);
7704 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7706 /* For instructions with VexNDD, the register destination
7707 is encoded in VEX prefix. */
7708 if (i
.mem_operands
== 0)
7710 /* There is no memory operand. */
7711 gas_assert ((op
+ 2) == i
.operands
);
7716 /* There are only 2 non-immediate operands. */
7717 gas_assert (op
< i
.imm_operands
+ 2
7718 && i
.operands
== i
.imm_operands
+ 2);
7719 vex_reg
= i
.imm_operands
+ 1;
7723 gas_assert (op
< i
.operands
);
7725 if (vex_reg
!= (unsigned int) ~0)
7727 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7729 if ((type
->bitfield
.class != Reg
7730 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7731 && type
->bitfield
.class != RegSIMD
7732 && !operand_type_equal (type
, ®mask
))
7735 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7738 /* Don't set OP operand twice. */
7741 /* If there is an extension opcode to put here, the
7742 register number must be put into the regmem field. */
7743 if (i
.tm
.extension_opcode
!= None
)
7745 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7746 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7748 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7753 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7754 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7756 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7761 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7762 must set it to 3 to indicate this is a register operand
7763 in the regmem field. */
7764 if (!i
.mem_operands
)
7768 /* Fill in i.rm.reg field with extension opcode (if any). */
7769 if (i
.tm
.extension_opcode
!= None
)
7770 i
.rm
.reg
= i
.tm
.extension_opcode
;
7776 output_branch (void)
7782 relax_substateT subtype
;
7786 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7787 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7790 if (i
.prefix
[DATA_PREFIX
] != 0)
7796 /* Pentium4 branch hints. */
7797 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7798 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7803 if (i
.prefix
[REX_PREFIX
] != 0)
7809 /* BND prefixed jump. */
7810 if (i
.prefix
[BND_PREFIX
] != 0)
7812 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7816 if (i
.prefixes
!= 0 && !intel_syntax
)
7817 as_warn (_("skipping prefixes on this instruction"));
7819 /* It's always a symbol; End frag & setup for relax.
7820 Make sure there is enough room in this frag for the largest
7821 instruction we may generate in md_convert_frag. This is 2
7822 bytes for the opcode and room for the prefix and largest
7824 frag_grow (prefix
+ 2 + 4);
7825 /* Prefix and 1 opcode byte go in fr_fix. */
7826 p
= frag_more (prefix
+ 1);
7827 if (i
.prefix
[DATA_PREFIX
] != 0)
7828 *p
++ = DATA_PREFIX_OPCODE
;
7829 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7830 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7831 *p
++ = i
.prefix
[SEG_PREFIX
];
7832 if (i
.prefix
[REX_PREFIX
] != 0)
7833 *p
++ = i
.prefix
[REX_PREFIX
];
7834 *p
= i
.tm
.base_opcode
;
7836 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7837 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7838 else if (cpu_arch_flags
.bitfield
.cpui386
)
7839 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7841 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7844 sym
= i
.op
[0].disps
->X_add_symbol
;
7845 off
= i
.op
[0].disps
->X_add_number
;
7847 if (i
.op
[0].disps
->X_op
!= O_constant
7848 && i
.op
[0].disps
->X_op
!= O_symbol
)
7850 /* Handle complex expressions. */
7851 sym
= make_expr_symbol (i
.op
[0].disps
);
7855 /* 1 possible extra opcode + 4 byte displacement go in var part.
7856 Pass reloc in fr_var. */
7857 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7860 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7861 /* Return TRUE iff PLT32 relocation should be used for branching to
7865 need_plt32_p (symbolS
*s
)
7867 /* PLT32 relocation is ELF only. */
7872 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7873 krtld support it. */
7877 /* Since there is no need to prepare for PLT branch on x86-64, we
7878 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7879 be used as a marker for 32-bit PC-relative branches. */
7883 /* Weak or undefined symbol need PLT32 relocation. */
7884 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7887 /* Non-global symbol doesn't need PLT32 relocation. */
7888 if (! S_IS_EXTERNAL (s
))
7891 /* Other global symbols need PLT32 relocation. NB: Symbol with
7892 non-default visibilities are treated as normal global symbol
7893 so that PLT32 relocation can be used as a marker for 32-bit
7894 PC-relative branches. It is useful for linker relaxation. */
7905 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7907 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
7909 /* This is a loop or jecxz type instruction. */
7911 if (i
.prefix
[ADDR_PREFIX
] != 0)
7913 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7916 /* Pentium4 branch hints. */
7917 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7918 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7920 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7929 if (flag_code
== CODE_16BIT
)
7932 if (i
.prefix
[DATA_PREFIX
] != 0)
7934 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7944 if (i
.prefix
[REX_PREFIX
] != 0)
7946 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7950 /* BND prefixed jump. */
7951 if (i
.prefix
[BND_PREFIX
] != 0)
7953 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7957 if (i
.prefixes
!= 0 && !intel_syntax
)
7958 as_warn (_("skipping prefixes on this instruction"));
7960 p
= frag_more (i
.tm
.opcode_length
+ size
);
7961 switch (i
.tm
.opcode_length
)
7964 *p
++ = i
.tm
.base_opcode
>> 8;
7967 *p
++ = i
.tm
.base_opcode
;
7973 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7975 && jump_reloc
== NO_RELOC
7976 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7977 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7980 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7982 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7983 i
.op
[0].disps
, 1, jump_reloc
);
7985 /* All jumps handled here are signed, but don't use a signed limit
7986 check for 32 and 16 bit jumps as we want to allow wrap around at
7987 4G and 64k respectively. */
7989 fixP
->fx_signed
= 1;
7993 output_interseg_jump (void)
8001 if (flag_code
== CODE_16BIT
)
8005 if (i
.prefix
[DATA_PREFIX
] != 0)
8011 if (i
.prefix
[REX_PREFIX
] != 0)
8021 if (i
.prefixes
!= 0 && !intel_syntax
)
8022 as_warn (_("skipping prefixes on this instruction"));
8024 /* 1 opcode; 2 segment; offset */
8025 p
= frag_more (prefix
+ 1 + 2 + size
);
8027 if (i
.prefix
[DATA_PREFIX
] != 0)
8028 *p
++ = DATA_PREFIX_OPCODE
;
8030 if (i
.prefix
[REX_PREFIX
] != 0)
8031 *p
++ = i
.prefix
[REX_PREFIX
];
8033 *p
++ = i
.tm
.base_opcode
;
8034 if (i
.op
[1].imms
->X_op
== O_constant
)
8036 offsetT n
= i
.op
[1].imms
->X_add_number
;
8039 && !fits_in_unsigned_word (n
)
8040 && !fits_in_signed_word (n
))
8042 as_bad (_("16-bit jump out of range"));
8045 md_number_to_chars (p
, n
, size
);
8048 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8049 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8050 if (i
.op
[0].imms
->X_op
!= O_constant
)
8051 as_bad (_("can't handle non absolute segment in `%s'"),
8053 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8056 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8061 asection
*seg
= now_seg
;
8062 subsegT subseg
= now_subseg
;
8064 unsigned int alignment
, align_size_1
;
8065 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8066 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8067 unsigned int padding
;
8069 if (!IS_ELF
|| !x86_used_note
)
8072 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8074 /* The .note.gnu.property section layout:
8076 Field Length Contents
8079 n_descsz 4 The note descriptor size
8080 n_type 4 NT_GNU_PROPERTY_TYPE_0
8082 n_desc n_descsz The program property array
8086 /* Create the .note.gnu.property section. */
8087 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8088 bfd_set_section_flags (sec
,
8095 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8106 bfd_set_section_alignment (sec
, alignment
);
8107 elf_section_type (sec
) = SHT_NOTE
;
8109 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8111 isa_1_descsz_raw
= 4 + 4 + 4;
8112 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8113 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8115 feature_2_descsz_raw
= isa_1_descsz
;
8116 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8118 feature_2_descsz_raw
+= 4 + 4 + 4;
8119 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8120 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8123 descsz
= feature_2_descsz
;
8124 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8125 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8127 /* Write n_namsz. */
8128 md_number_to_chars (p
, (valueT
) 4, 4);
8130 /* Write n_descsz. */
8131 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8134 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8137 memcpy (p
+ 4 * 3, "GNU", 4);
8139 /* Write 4-byte type. */
8140 md_number_to_chars (p
+ 4 * 4,
8141 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8143 /* Write 4-byte data size. */
8144 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8146 /* Write 4-byte data. */
8147 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8149 /* Zero out paddings. */
8150 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8152 memset (p
+ 4 * 7, 0, padding
);
8154 /* Write 4-byte type. */
8155 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8156 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8158 /* Write 4-byte data size. */
8159 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8161 /* Write 4-byte data. */
8162 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8163 (valueT
) x86_feature_2_used
, 4);
8165 /* Zero out paddings. */
8166 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8168 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8170 /* We probably can't restore the current segment, for there likely
8173 subseg_set (seg
, subseg
);
8178 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8179 const char *frag_now_ptr
)
8181 unsigned int len
= 0;
8183 if (start_frag
!= frag_now
)
8185 const fragS
*fr
= start_frag
;
8190 } while (fr
&& fr
!= frag_now
);
8193 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8199 fragS
*insn_start_frag
;
8200 offsetT insn_start_off
;
8202 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8203 if (IS_ELF
&& x86_used_note
)
8205 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8206 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8207 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8208 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8209 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8210 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8211 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8212 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8213 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8214 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8215 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8216 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8217 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8218 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8219 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8220 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8221 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8222 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8223 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8224 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8225 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8226 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8227 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8228 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8229 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8230 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8231 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8232 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8233 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8234 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8235 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8236 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8237 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8238 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8239 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8240 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8241 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8242 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8243 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8244 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8245 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8246 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8247 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8248 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8249 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8250 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8251 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8252 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8253 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8254 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8256 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8257 || i
.tm
.cpu_flags
.bitfield
.cpu287
8258 || i
.tm
.cpu_flags
.bitfield
.cpu387
8259 || i
.tm
.cpu_flags
.bitfield
.cpu687
8260 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8261 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8262 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8263 Xfence instructions. */
8264 if (i
.tm
.base_opcode
!= 0xf18
8265 && i
.tm
.base_opcode
!= 0xf0d
8266 && i
.tm
.base_opcode
!= 0xfaef8
8268 || i
.tm
.cpu_flags
.bitfield
.cpummx
8269 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8270 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8271 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8273 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8275 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8277 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8278 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8279 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8280 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8281 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8282 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8283 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8284 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8285 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8289 /* Tie dwarf2 debug info to the address at the start of the insn.
8290 We can't do this after the insn has been output as the current
8291 frag may have been closed off. eg. by frag_var. */
8292 dwarf2_emit_insn (0);
8294 insn_start_frag
= frag_now
;
8295 insn_start_off
= frag_now_fix ();
8298 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8300 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8301 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8303 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8304 output_interseg_jump ();
8307 /* Output normal instructions here. */
8311 unsigned int prefix
;
8314 && (i
.tm
.base_opcode
== 0xfaee8
8315 || i
.tm
.base_opcode
== 0xfaef0
8316 || i
.tm
.base_opcode
== 0xfaef8))
8318 /* Encode lfence, mfence, and sfence as
8319 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8320 offsetT val
= 0x240483f0ULL
;
8322 md_number_to_chars (p
, val
, 5);
8326 /* Some processors fail on LOCK prefix. This options makes
8327 assembler ignore LOCK prefix and serves as a workaround. */
8328 if (omit_lock_prefix
)
8330 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8332 i
.prefix
[LOCK_PREFIX
] = 0;
8335 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8336 don't need the explicit prefix. */
8337 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8339 switch (i
.tm
.opcode_length
)
8342 if (i
.tm
.base_opcode
& 0xff000000)
8344 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8345 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8346 || prefix
!= REPE_PREFIX_OPCODE
8347 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8348 add_prefix (prefix
);
8352 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8354 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8355 add_prefix (prefix
);
8361 /* Check for pseudo prefixes. */
8362 as_bad_where (insn_start_frag
->fr_file
,
8363 insn_start_frag
->fr_line
,
8364 _("pseudo prefix without instruction"));
8370 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8371 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8372 R_X86_64_GOTTPOFF relocation so that linker can safely
8373 perform IE->LE optimization. */
8374 if (x86_elf_abi
== X86_64_X32_ABI
8376 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8377 && i
.prefix
[REX_PREFIX
] == 0)
8378 add_prefix (REX_OPCODE
);
8381 /* The prefix bytes. */
8382 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8384 FRAG_APPEND_1_CHAR (*q
);
8388 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8393 /* REX byte is encoded in VEX prefix. */
8397 FRAG_APPEND_1_CHAR (*q
);
8400 /* There should be no other prefixes for instructions
8405 /* For EVEX instructions i.vrex should become 0 after
8406 build_evex_prefix. For VEX instructions upper 16 registers
8407 aren't available, so VREX should be 0. */
8410 /* Now the VEX prefix. */
8411 p
= frag_more (i
.vex
.length
);
8412 for (j
= 0; j
< i
.vex
.length
; j
++)
8413 p
[j
] = i
.vex
.bytes
[j
];
8416 /* Now the opcode; be careful about word order here! */
8417 if (i
.tm
.opcode_length
== 1)
8419 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8423 switch (i
.tm
.opcode_length
)
8427 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8428 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8432 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8442 /* Put out high byte first: can't use md_number_to_chars! */
8443 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8444 *p
= i
.tm
.base_opcode
& 0xff;
8447 /* Now the modrm byte and sib byte (if present). */
8448 if (i
.tm
.opcode_modifier
.modrm
)
8450 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8453 /* If i.rm.regmem == ESP (4)
8454 && i.rm.mode != (Register mode)
8456 ==> need second modrm byte. */
8457 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8459 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8460 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8462 | i
.sib
.scale
<< 6));
8465 if (i
.disp_operands
)
8466 output_disp (insn_start_frag
, insn_start_off
);
8469 output_imm (insn_start_frag
, insn_start_off
);
8472 * frag_now_fix () returning plain abs_section_offset when we're in the
8473 * absolute section, and abs_section_offset not getting updated as data
8474 * gets added to the frag breaks the logic below.
8476 if (now_seg
!= absolute_section
)
8478 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8480 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8488 pi ("" /*line*/, &i
);
8490 #endif /* DEBUG386 */
8493 /* Return the size of the displacement operand N. */
8496 disp_size (unsigned int n
)
8500 if (i
.types
[n
].bitfield
.disp64
)
8502 else if (i
.types
[n
].bitfield
.disp8
)
8504 else if (i
.types
[n
].bitfield
.disp16
)
8509 /* Return the size of the immediate operand N. */
8512 imm_size (unsigned int n
)
8515 if (i
.types
[n
].bitfield
.imm64
)
8517 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8519 else if (i
.types
[n
].bitfield
.imm16
)
8525 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8530 for (n
= 0; n
< i
.operands
; n
++)
8532 if (operand_type_check (i
.types
[n
], disp
))
8534 if (i
.op
[n
].disps
->X_op
== O_constant
)
8536 int size
= disp_size (n
);
8537 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8539 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8541 p
= frag_more (size
);
8542 md_number_to_chars (p
, val
, size
);
8546 enum bfd_reloc_code_real reloc_type
;
8547 int size
= disp_size (n
);
8548 int sign
= i
.types
[n
].bitfield
.disp32s
;
8549 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8552 /* We can't have 8 bit displacement here. */
8553 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8555 /* The PC relative address is computed relative
8556 to the instruction boundary, so in case immediate
8557 fields follows, we need to adjust the value. */
8558 if (pcrel
&& i
.imm_operands
)
8563 for (n1
= 0; n1
< i
.operands
; n1
++)
8564 if (operand_type_check (i
.types
[n1
], imm
))
8566 /* Only one immediate is allowed for PC
8567 relative address. */
8568 gas_assert (sz
== 0);
8570 i
.op
[n
].disps
->X_add_number
-= sz
;
8572 /* We should find the immediate. */
8573 gas_assert (sz
!= 0);
8576 p
= frag_more (size
);
8577 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8579 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8580 && (((reloc_type
== BFD_RELOC_32
8581 || reloc_type
== BFD_RELOC_X86_64_32S
8582 || (reloc_type
== BFD_RELOC_64
8584 && (i
.op
[n
].disps
->X_op
== O_symbol
8585 || (i
.op
[n
].disps
->X_op
== O_add
8586 && ((symbol_get_value_expression
8587 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8589 || reloc_type
== BFD_RELOC_32_PCREL
))
8593 reloc_type
= BFD_RELOC_386_GOTPC
;
8594 i
.op
[n
].imms
->X_add_number
+=
8595 encoding_length (insn_start_frag
, insn_start_off
, p
);
8597 else if (reloc_type
== BFD_RELOC_64
)
8598 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8600 /* Don't do the adjustment for x86-64, as there
8601 the pcrel addressing is relative to the _next_
8602 insn, and that is taken care of in other code. */
8603 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8605 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8606 size
, i
.op
[n
].disps
, pcrel
,
8608 /* Check for "call/jmp *mem", "mov mem, %reg",
8609 "test %reg, mem" and "binop mem, %reg" where binop
8610 is one of adc, add, and, cmp, or, sbb, sub, xor
8611 instructions without data prefix. Always generate
8612 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8613 if (i
.prefix
[DATA_PREFIX
] == 0
8614 && (generate_relax_relocations
8617 && i
.rm
.regmem
== 5))
8619 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8620 && ((i
.operands
== 1
8621 && i
.tm
.base_opcode
== 0xff
8622 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8624 && (i
.tm
.base_opcode
== 0x8b
8625 || i
.tm
.base_opcode
== 0x85
8626 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8630 fixP
->fx_tcbit
= i
.rex
!= 0;
8632 && (i
.base_reg
->reg_num
== RegIP
))
8633 fixP
->fx_tcbit2
= 1;
8636 fixP
->fx_tcbit2
= 1;
8644 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8649 for (n
= 0; n
< i
.operands
; n
++)
8651 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8652 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8655 if (operand_type_check (i
.types
[n
], imm
))
8657 if (i
.op
[n
].imms
->X_op
== O_constant
)
8659 int size
= imm_size (n
);
8662 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8664 p
= frag_more (size
);
8665 md_number_to_chars (p
, val
, size
);
8669 /* Not absolute_section.
8670 Need a 32-bit fixup (don't support 8bit
8671 non-absolute imms). Try to support other
8673 enum bfd_reloc_code_real reloc_type
;
8674 int size
= imm_size (n
);
8677 if (i
.types
[n
].bitfield
.imm32s
8678 && (i
.suffix
== QWORD_MNEM_SUFFIX
8679 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8684 p
= frag_more (size
);
8685 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8687 /* This is tough to explain. We end up with this one if we
8688 * have operands that look like
8689 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8690 * obtain the absolute address of the GOT, and it is strongly
8691 * preferable from a performance point of view to avoid using
8692 * a runtime relocation for this. The actual sequence of
8693 * instructions often look something like:
8698 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8700 * The call and pop essentially return the absolute address
8701 * of the label .L66 and store it in %ebx. The linker itself
8702 * will ultimately change the first operand of the addl so
8703 * that %ebx points to the GOT, but to keep things simple, the
8704 * .o file must have this operand set so that it generates not
8705 * the absolute address of .L66, but the absolute address of
8706 * itself. This allows the linker itself simply treat a GOTPC
8707 * relocation as asking for a pcrel offset to the GOT to be
8708 * added in, and the addend of the relocation is stored in the
8709 * operand field for the instruction itself.
8711 * Our job here is to fix the operand so that it would add
8712 * the correct offset so that %ebx would point to itself. The
8713 * thing that is tricky is that .-.L66 will point to the
8714 * beginning of the instruction, so we need to further modify
8715 * the operand so that it will point to itself. There are
8716 * other cases where you have something like:
8718 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8720 * and here no correction would be required. Internally in
8721 * the assembler we treat operands of this form as not being
8722 * pcrel since the '.' is explicitly mentioned, and I wonder
8723 * whether it would simplify matters to do it this way. Who
8724 * knows. In earlier versions of the PIC patches, the
8725 * pcrel_adjust field was used to store the correction, but
8726 * since the expression is not pcrel, I felt it would be
8727 * confusing to do it this way. */
8729 if ((reloc_type
== BFD_RELOC_32
8730 || reloc_type
== BFD_RELOC_X86_64_32S
8731 || reloc_type
== BFD_RELOC_64
)
8733 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8734 && (i
.op
[n
].imms
->X_op
== O_symbol
8735 || (i
.op
[n
].imms
->X_op
== O_add
8736 && ((symbol_get_value_expression
8737 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8741 reloc_type
= BFD_RELOC_386_GOTPC
;
8743 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8745 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8746 i
.op
[n
].imms
->X_add_number
+=
8747 encoding_length (insn_start_frag
, insn_start_off
, p
);
8749 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8750 i
.op
[n
].imms
, 0, reloc_type
);
8756 /* x86_cons_fix_new is called via the expression parsing code when a
8757 reloc is needed. We use this hook to get the correct .got reloc. */
8758 static int cons_sign
= -1;
8761 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8762 expressionS
*exp
, bfd_reloc_code_real_type r
)
8764 r
= reloc (len
, 0, cons_sign
, r
);
8767 if (exp
->X_op
== O_secrel
)
8769 exp
->X_op
= O_symbol
;
8770 r
= BFD_RELOC_32_SECREL
;
8774 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8777 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8778 purpose of the `.dc.a' internal pseudo-op. */
8781 x86_address_bytes (void)
8783 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8785 return stdoutput
->arch_info
->bits_per_address
/ 8;
8788 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8790 # define lex_got(reloc, adjust, types) NULL
8792 /* Parse operands of the form
8793 <symbol>@GOTOFF+<nnn>
8794 and similar .plt or .got references.
8796 If we find one, set up the correct relocation in RELOC and copy the
8797 input string, minus the `@GOTOFF' into a malloc'd buffer for
8798 parsing by the calling routine. Return this buffer, and if ADJUST
8799 is non-null set it to the length of the string we removed from the
8800 input line. Otherwise return NULL. */
8802 lex_got (enum bfd_reloc_code_real
*rel
,
8804 i386_operand_type
*types
)
8806 /* Some of the relocations depend on the size of what field is to
8807 be relocated. But in our callers i386_immediate and i386_displacement
8808 we don't yet know the operand size (this will be set by insn
8809 matching). Hence we record the word32 relocation here,
8810 and adjust the reloc according to the real size in reloc(). */
8811 static const struct {
8814 const enum bfd_reloc_code_real rel
[2];
8815 const i386_operand_type types64
;
8817 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8818 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8820 OPERAND_TYPE_IMM32_64
},
8822 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8823 BFD_RELOC_X86_64_PLTOFF64
},
8824 OPERAND_TYPE_IMM64
},
8825 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8826 BFD_RELOC_X86_64_PLT32
},
8827 OPERAND_TYPE_IMM32_32S_DISP32
},
8828 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8829 BFD_RELOC_X86_64_GOTPLT64
},
8830 OPERAND_TYPE_IMM64_DISP64
},
8831 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8832 BFD_RELOC_X86_64_GOTOFF64
},
8833 OPERAND_TYPE_IMM64_DISP64
},
8834 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8835 BFD_RELOC_X86_64_GOTPCREL
},
8836 OPERAND_TYPE_IMM32_32S_DISP32
},
8837 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8838 BFD_RELOC_X86_64_TLSGD
},
8839 OPERAND_TYPE_IMM32_32S_DISP32
},
8840 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8841 _dummy_first_bfd_reloc_code_real
},
8842 OPERAND_TYPE_NONE
},
8843 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8844 BFD_RELOC_X86_64_TLSLD
},
8845 OPERAND_TYPE_IMM32_32S_DISP32
},
8846 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8847 BFD_RELOC_X86_64_GOTTPOFF
},
8848 OPERAND_TYPE_IMM32_32S_DISP32
},
8849 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8850 BFD_RELOC_X86_64_TPOFF32
},
8851 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8852 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8853 _dummy_first_bfd_reloc_code_real
},
8854 OPERAND_TYPE_NONE
},
8855 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8856 BFD_RELOC_X86_64_DTPOFF32
},
8857 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8858 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8859 _dummy_first_bfd_reloc_code_real
},
8860 OPERAND_TYPE_NONE
},
8861 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8862 _dummy_first_bfd_reloc_code_real
},
8863 OPERAND_TYPE_NONE
},
8864 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8865 BFD_RELOC_X86_64_GOT32
},
8866 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8867 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8868 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8869 OPERAND_TYPE_IMM32_32S_DISP32
},
8870 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8871 BFD_RELOC_X86_64_TLSDESC_CALL
},
8872 OPERAND_TYPE_IMM32_32S_DISP32
},
8877 #if defined (OBJ_MAYBE_ELF)
8882 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8883 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8886 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8888 int len
= gotrel
[j
].len
;
8889 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8891 if (gotrel
[j
].rel
[object_64bit
] != 0)
8894 char *tmpbuf
, *past_reloc
;
8896 *rel
= gotrel
[j
].rel
[object_64bit
];
8900 if (flag_code
!= CODE_64BIT
)
8902 types
->bitfield
.imm32
= 1;
8903 types
->bitfield
.disp32
= 1;
8906 *types
= gotrel
[j
].types64
;
8909 if (j
!= 0 && GOT_symbol
== NULL
)
8910 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8912 /* The length of the first part of our input line. */
8913 first
= cp
- input_line_pointer
;
8915 /* The second part goes from after the reloc token until
8916 (and including) an end_of_line char or comma. */
8917 past_reloc
= cp
+ 1 + len
;
8919 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8921 second
= cp
+ 1 - past_reloc
;
8923 /* Allocate and copy string. The trailing NUL shouldn't
8924 be necessary, but be safe. */
8925 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8926 memcpy (tmpbuf
, input_line_pointer
, first
);
8927 if (second
!= 0 && *past_reloc
!= ' ')
8928 /* Replace the relocation token with ' ', so that
8929 errors like foo@GOTOFF1 will be detected. */
8930 tmpbuf
[first
++] = ' ';
8932 /* Increment length by 1 if the relocation token is
8937 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8938 tmpbuf
[first
+ second
] = '\0';
8942 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8943 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8948 /* Might be a symbol version string. Don't as_bad here. */
8957 /* Parse operands of the form
8958 <symbol>@SECREL32+<nnn>
8960 If we find one, set up the correct relocation in RELOC and copy the
8961 input string, minus the `@SECREL32' into a malloc'd buffer for
8962 parsing by the calling routine. Return this buffer, and if ADJUST
8963 is non-null set it to the length of the string we removed from the
8964 input line. Otherwise return NULL.
8966 This function is copied from the ELF version above adjusted for PE targets. */
8969 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8970 int *adjust ATTRIBUTE_UNUSED
,
8971 i386_operand_type
*types
)
8977 const enum bfd_reloc_code_real rel
[2];
8978 const i386_operand_type types64
;
8982 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8983 BFD_RELOC_32_SECREL
},
8984 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8990 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8991 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8994 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8996 int len
= gotrel
[j
].len
;
8998 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9000 if (gotrel
[j
].rel
[object_64bit
] != 0)
9003 char *tmpbuf
, *past_reloc
;
9005 *rel
= gotrel
[j
].rel
[object_64bit
];
9011 if (flag_code
!= CODE_64BIT
)
9013 types
->bitfield
.imm32
= 1;
9014 types
->bitfield
.disp32
= 1;
9017 *types
= gotrel
[j
].types64
;
9020 /* The length of the first part of our input line. */
9021 first
= cp
- input_line_pointer
;
9023 /* The second part goes from after the reloc token until
9024 (and including) an end_of_line char or comma. */
9025 past_reloc
= cp
+ 1 + len
;
9027 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9029 second
= cp
+ 1 - past_reloc
;
9031 /* Allocate and copy string. The trailing NUL shouldn't
9032 be necessary, but be safe. */
9033 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9034 memcpy (tmpbuf
, input_line_pointer
, first
);
9035 if (second
!= 0 && *past_reloc
!= ' ')
9036 /* Replace the relocation token with ' ', so that
9037 errors like foo@SECLREL321 will be detected. */
9038 tmpbuf
[first
++] = ' ';
9039 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9040 tmpbuf
[first
+ second
] = '\0';
9044 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9045 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9050 /* Might be a symbol version string. Don't as_bad here. */
9056 bfd_reloc_code_real_type
9057 x86_cons (expressionS
*exp
, int size
)
9059 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9061 intel_syntax
= -intel_syntax
;
9064 if (size
== 4 || (object_64bit
&& size
== 8))
9066 /* Handle @GOTOFF and the like in an expression. */
9068 char *gotfree_input_line
;
9071 save
= input_line_pointer
;
9072 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9073 if (gotfree_input_line
)
9074 input_line_pointer
= gotfree_input_line
;
9078 if (gotfree_input_line
)
9080 /* expression () has merrily parsed up to the end of line,
9081 or a comma - in the wrong buffer. Transfer how far
9082 input_line_pointer has moved to the right buffer. */
9083 input_line_pointer
= (save
9084 + (input_line_pointer
- gotfree_input_line
)
9086 free (gotfree_input_line
);
9087 if (exp
->X_op
== O_constant
9088 || exp
->X_op
== O_absent
9089 || exp
->X_op
== O_illegal
9090 || exp
->X_op
== O_register
9091 || exp
->X_op
== O_big
)
9093 char c
= *input_line_pointer
;
9094 *input_line_pointer
= 0;
9095 as_bad (_("missing or invalid expression `%s'"), save
);
9096 *input_line_pointer
= c
;
9098 else if ((got_reloc
== BFD_RELOC_386_PLT32
9099 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9100 && exp
->X_op
!= O_symbol
)
9102 char c
= *input_line_pointer
;
9103 *input_line_pointer
= 0;
9104 as_bad (_("invalid PLT expression `%s'"), save
);
9105 *input_line_pointer
= c
;
9112 intel_syntax
= -intel_syntax
;
9115 i386_intel_simplify (exp
);
9121 signed_cons (int size
)
9123 if (flag_code
== CODE_64BIT
)
9131 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9138 if (exp
.X_op
== O_symbol
)
9139 exp
.X_op
= O_secrel
;
9141 emit_expr (&exp
, 4);
9143 while (*input_line_pointer
++ == ',');
9145 input_line_pointer
--;
9146 demand_empty_rest_of_line ();
9150 /* Handle Vector operations. */
9153 check_VecOperations (char *op_string
, char *op_end
)
9155 const reg_entry
*mask
;
9160 && (op_end
== NULL
|| op_string
< op_end
))
9163 if (*op_string
== '{')
9167 /* Check broadcasts. */
9168 if (strncmp (op_string
, "1to", 3) == 0)
9173 goto duplicated_vec_op
;
9176 if (*op_string
== '8')
9178 else if (*op_string
== '4')
9180 else if (*op_string
== '2')
9182 else if (*op_string
== '1'
9183 && *(op_string
+1) == '6')
9190 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9195 broadcast_op
.type
= bcst_type
;
9196 broadcast_op
.operand
= this_operand
;
9197 broadcast_op
.bytes
= 0;
9198 i
.broadcast
= &broadcast_op
;
9200 /* Check masking operation. */
9201 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9203 /* k0 can't be used for write mask. */
9204 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9206 as_bad (_("`%s%s' can't be used for write mask"),
9207 register_prefix
, mask
->reg_name
);
9213 mask_op
.mask
= mask
;
9214 mask_op
.zeroing
= 0;
9215 mask_op
.operand
= this_operand
;
9221 goto duplicated_vec_op
;
9223 i
.mask
->mask
= mask
;
9225 /* Only "{z}" is allowed here. No need to check
9226 zeroing mask explicitly. */
9227 if (i
.mask
->operand
!= this_operand
)
9229 as_bad (_("invalid write mask `%s'"), saved
);
9236 /* Check zeroing-flag for masking operation. */
9237 else if (*op_string
== 'z')
9241 mask_op
.mask
= NULL
;
9242 mask_op
.zeroing
= 1;
9243 mask_op
.operand
= this_operand
;
9248 if (i
.mask
->zeroing
)
9251 as_bad (_("duplicated `%s'"), saved
);
9255 i
.mask
->zeroing
= 1;
9257 /* Only "{%k}" is allowed here. No need to check mask
9258 register explicitly. */
9259 if (i
.mask
->operand
!= this_operand
)
9261 as_bad (_("invalid zeroing-masking `%s'"),
9270 goto unknown_vec_op
;
9272 if (*op_string
!= '}')
9274 as_bad (_("missing `}' in `%s'"), saved
);
9279 /* Strip whitespace since the addition of pseudo prefixes
9280 changed how the scrubber treats '{'. */
9281 if (is_space_char (*op_string
))
9287 /* We don't know this one. */
9288 as_bad (_("unknown vector operation: `%s'"), saved
);
9292 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9294 as_bad (_("zeroing-masking only allowed with write mask"));
9302 i386_immediate (char *imm_start
)
9304 char *save_input_line_pointer
;
9305 char *gotfree_input_line
;
9308 i386_operand_type types
;
9310 operand_type_set (&types
, ~0);
9312 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9314 as_bad (_("at most %d immediate operands are allowed"),
9315 MAX_IMMEDIATE_OPERANDS
);
9319 exp
= &im_expressions
[i
.imm_operands
++];
9320 i
.op
[this_operand
].imms
= exp
;
9322 if (is_space_char (*imm_start
))
9325 save_input_line_pointer
= input_line_pointer
;
9326 input_line_pointer
= imm_start
;
9328 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9329 if (gotfree_input_line
)
9330 input_line_pointer
= gotfree_input_line
;
9332 exp_seg
= expression (exp
);
9336 /* Handle vector operations. */
9337 if (*input_line_pointer
== '{')
9339 input_line_pointer
= check_VecOperations (input_line_pointer
,
9341 if (input_line_pointer
== NULL
)
9345 if (*input_line_pointer
)
9346 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9348 input_line_pointer
= save_input_line_pointer
;
9349 if (gotfree_input_line
)
9351 free (gotfree_input_line
);
9353 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9354 exp
->X_op
= O_illegal
;
9357 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9361 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9362 i386_operand_type types
, const char *imm_start
)
9364 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9367 as_bad (_("missing or invalid immediate expression `%s'"),
9371 else if (exp
->X_op
== O_constant
)
9373 /* Size it properly later. */
9374 i
.types
[this_operand
].bitfield
.imm64
= 1;
9375 /* If not 64bit, sign extend val. */
9376 if (flag_code
!= CODE_64BIT
9377 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9379 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9381 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9382 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9383 && exp_seg
!= absolute_section
9384 && exp_seg
!= text_section
9385 && exp_seg
!= data_section
9386 && exp_seg
!= bss_section
9387 && exp_seg
!= undefined_section
9388 && !bfd_is_com_section (exp_seg
))
9390 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9394 else if (!intel_syntax
&& exp_seg
== reg_section
)
9397 as_bad (_("illegal immediate register operand %s"), imm_start
);
9402 /* This is an address. The size of the address will be
9403 determined later, depending on destination register,
9404 suffix, or the default for the section. */
9405 i
.types
[this_operand
].bitfield
.imm8
= 1;
9406 i
.types
[this_operand
].bitfield
.imm16
= 1;
9407 i
.types
[this_operand
].bitfield
.imm32
= 1;
9408 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9409 i
.types
[this_operand
].bitfield
.imm64
= 1;
9410 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9418 i386_scale (char *scale
)
9421 char *save
= input_line_pointer
;
9423 input_line_pointer
= scale
;
9424 val
= get_absolute_expression ();
9429 i
.log2_scale_factor
= 0;
9432 i
.log2_scale_factor
= 1;
9435 i
.log2_scale_factor
= 2;
9438 i
.log2_scale_factor
= 3;
9442 char sep
= *input_line_pointer
;
9444 *input_line_pointer
= '\0';
9445 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9447 *input_line_pointer
= sep
;
9448 input_line_pointer
= save
;
9452 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9454 as_warn (_("scale factor of %d without an index register"),
9455 1 << i
.log2_scale_factor
);
9456 i
.log2_scale_factor
= 0;
9458 scale
= input_line_pointer
;
9459 input_line_pointer
= save
;
9464 i386_displacement (char *disp_start
, char *disp_end
)
9468 char *save_input_line_pointer
;
9469 char *gotfree_input_line
;
9471 i386_operand_type bigdisp
, types
= anydisp
;
9474 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9476 as_bad (_("at most %d displacement operands are allowed"),
9477 MAX_MEMORY_OPERANDS
);
9481 operand_type_set (&bigdisp
, 0);
9483 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
9484 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
9486 bigdisp
.bitfield
.disp32
= 1;
9487 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9488 if (flag_code
== CODE_64BIT
)
9492 bigdisp
.bitfield
.disp32s
= 1;
9493 bigdisp
.bitfield
.disp64
= 1;
9496 else if ((flag_code
== CODE_16BIT
) ^ override
)
9498 bigdisp
.bitfield
.disp32
= 0;
9499 bigdisp
.bitfield
.disp16
= 1;
9504 /* For PC-relative branches, the width of the displacement
9505 is dependent upon data size, not address size. */
9506 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9507 if (flag_code
== CODE_64BIT
)
9509 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9510 bigdisp
.bitfield
.disp16
= 1;
9513 bigdisp
.bitfield
.disp32
= 1;
9514 bigdisp
.bitfield
.disp32s
= 1;
9520 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9522 : LONG_MNEM_SUFFIX
));
9523 bigdisp
.bitfield
.disp32
= 1;
9524 if ((flag_code
== CODE_16BIT
) ^ override
)
9526 bigdisp
.bitfield
.disp32
= 0;
9527 bigdisp
.bitfield
.disp16
= 1;
9531 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9534 exp
= &disp_expressions
[i
.disp_operands
];
9535 i
.op
[this_operand
].disps
= exp
;
9537 save_input_line_pointer
= input_line_pointer
;
9538 input_line_pointer
= disp_start
;
9539 END_STRING_AND_SAVE (disp_end
);
9541 #ifndef GCC_ASM_O_HACK
9542 #define GCC_ASM_O_HACK 0
9545 END_STRING_AND_SAVE (disp_end
+ 1);
9546 if (i
.types
[this_operand
].bitfield
.baseIndex
9547 && displacement_string_end
[-1] == '+')
9549 /* This hack is to avoid a warning when using the "o"
9550 constraint within gcc asm statements.
9553 #define _set_tssldt_desc(n,addr,limit,type) \
9554 __asm__ __volatile__ ( \
9556 "movw %w1,2+%0\n\t" \
9558 "movb %b1,4+%0\n\t" \
9559 "movb %4,5+%0\n\t" \
9560 "movb $0,6+%0\n\t" \
9561 "movb %h1,7+%0\n\t" \
9563 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9565 This works great except that the output assembler ends
9566 up looking a bit weird if it turns out that there is
9567 no offset. You end up producing code that looks like:
9580 So here we provide the missing zero. */
9582 *displacement_string_end
= '0';
9585 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9586 if (gotfree_input_line
)
9587 input_line_pointer
= gotfree_input_line
;
9589 exp_seg
= expression (exp
);
9592 if (*input_line_pointer
)
9593 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9595 RESTORE_END_STRING (disp_end
+ 1);
9597 input_line_pointer
= save_input_line_pointer
;
9598 if (gotfree_input_line
)
9600 free (gotfree_input_line
);
9602 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9603 exp
->X_op
= O_illegal
;
9606 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9608 RESTORE_END_STRING (disp_end
);
9614 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9615 i386_operand_type types
, const char *disp_start
)
9617 i386_operand_type bigdisp
;
9620 /* We do this to make sure that the section symbol is in
9621 the symbol table. We will ultimately change the relocation
9622 to be relative to the beginning of the section. */
9623 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9624 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9625 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9627 if (exp
->X_op
!= O_symbol
)
9630 if (S_IS_LOCAL (exp
->X_add_symbol
)
9631 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9632 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9633 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9634 exp
->X_op
= O_subtract
;
9635 exp
->X_op_symbol
= GOT_symbol
;
9636 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9637 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9638 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9639 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9641 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9644 else if (exp
->X_op
== O_absent
9645 || exp
->X_op
== O_illegal
9646 || exp
->X_op
== O_big
)
9649 as_bad (_("missing or invalid displacement expression `%s'"),
9654 else if (flag_code
== CODE_64BIT
9655 && !i
.prefix
[ADDR_PREFIX
]
9656 && exp
->X_op
== O_constant
)
9658 /* Since displacement is signed extended to 64bit, don't allow
9659 disp32 and turn off disp32s if they are out of range. */
9660 i
.types
[this_operand
].bitfield
.disp32
= 0;
9661 if (!fits_in_signed_long (exp
->X_add_number
))
9663 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9664 if (i
.types
[this_operand
].bitfield
.baseindex
)
9666 as_bad (_("0x%lx out range of signed 32bit displacement"),
9667 (long) exp
->X_add_number
);
9673 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9674 else if (exp
->X_op
!= O_constant
9675 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9676 && exp_seg
!= absolute_section
9677 && exp_seg
!= text_section
9678 && exp_seg
!= data_section
9679 && exp_seg
!= bss_section
9680 && exp_seg
!= undefined_section
9681 && !bfd_is_com_section (exp_seg
))
9683 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9688 /* Check if this is a displacement only operand. */
9689 bigdisp
= i
.types
[this_operand
];
9690 bigdisp
.bitfield
.disp8
= 0;
9691 bigdisp
.bitfield
.disp16
= 0;
9692 bigdisp
.bitfield
.disp32
= 0;
9693 bigdisp
.bitfield
.disp32s
= 0;
9694 bigdisp
.bitfield
.disp64
= 0;
9695 if (operand_type_all_zero (&bigdisp
))
9696 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9702 /* Return the active addressing mode, taking address override and
9703 registers forming the address into consideration. Update the
9704 address override prefix if necessary. */
9706 static enum flag_code
9707 i386_addressing_mode (void)
9709 enum flag_code addr_mode
;
9711 if (i
.prefix
[ADDR_PREFIX
])
9712 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9715 addr_mode
= flag_code
;
9717 #if INFER_ADDR_PREFIX
9718 if (i
.mem_operands
== 0)
9720 /* Infer address prefix from the first memory operand. */
9721 const reg_entry
*addr_reg
= i
.base_reg
;
9723 if (addr_reg
== NULL
)
9724 addr_reg
= i
.index_reg
;
9728 if (addr_reg
->reg_type
.bitfield
.dword
)
9729 addr_mode
= CODE_32BIT
;
9730 else if (flag_code
!= CODE_64BIT
9731 && addr_reg
->reg_type
.bitfield
.word
)
9732 addr_mode
= CODE_16BIT
;
9734 if (addr_mode
!= flag_code
)
9736 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9738 /* Change the size of any displacement too. At most one
9739 of Disp16 or Disp32 is set.
9740 FIXME. There doesn't seem to be any real need for
9741 separate Disp16 and Disp32 flags. The same goes for
9742 Imm16 and Imm32. Removing them would probably clean
9743 up the code quite a lot. */
9744 if (flag_code
!= CODE_64BIT
9745 && (i
.types
[this_operand
].bitfield
.disp16
9746 || i
.types
[this_operand
].bitfield
.disp32
))
9747 i
.types
[this_operand
]
9748 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9758 /* Make sure the memory operand we've been dealt is valid.
9759 Return 1 on success, 0 on a failure. */
9762 i386_index_check (const char *operand_string
)
9764 const char *kind
= "base/index";
9765 enum flag_code addr_mode
= i386_addressing_mode ();
9767 if (current_templates
->start
->opcode_modifier
.isstring
9768 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
9769 && (current_templates
->end
[-1].opcode_modifier
.isstring
9772 /* Memory operands of string insns are special in that they only allow
9773 a single register (rDI, rSI, or rBX) as their memory address. */
9774 const reg_entry
*expected_reg
;
9775 static const char *di_si
[][2] =
9781 static const char *bx
[] = { "ebx", "bx", "rbx" };
9783 kind
= "string address";
9785 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9787 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
9791 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
9792 || ((!i
.mem_operands
!= !intel_syntax
)
9793 && current_templates
->end
[-1].operand_types
[1]
9794 .bitfield
.baseindex
))
9796 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
9799 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9801 if (i
.base_reg
!= expected_reg
9803 || operand_type_check (i
.types
[this_operand
], disp
))
9805 /* The second memory operand must have the same size as
9809 && !((addr_mode
== CODE_64BIT
9810 && i
.base_reg
->reg_type
.bitfield
.qword
)
9811 || (addr_mode
== CODE_32BIT
9812 ? i
.base_reg
->reg_type
.bitfield
.dword
9813 : i
.base_reg
->reg_type
.bitfield
.word
)))
9816 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9818 intel_syntax
? '[' : '(',
9820 expected_reg
->reg_name
,
9821 intel_syntax
? ']' : ')');
9828 as_bad (_("`%s' is not a valid %s expression"),
9829 operand_string
, kind
);
9834 if (addr_mode
!= CODE_16BIT
)
9836 /* 32-bit/64-bit checks. */
9838 && ((addr_mode
== CODE_64BIT
9839 ? !i
.base_reg
->reg_type
.bitfield
.qword
9840 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9841 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9842 || i
.base_reg
->reg_num
== RegIZ
))
9844 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9845 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9846 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9847 && ((addr_mode
== CODE_64BIT
9848 ? !i
.index_reg
->reg_type
.bitfield
.qword
9849 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9850 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9853 /* bndmk, bndldx, and bndstx have special restrictions. */
9854 if (current_templates
->start
->base_opcode
== 0xf30f1b
9855 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9857 /* They cannot use RIP-relative addressing. */
9858 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9860 as_bad (_("`%s' cannot be used here"), operand_string
);
9864 /* bndldx and bndstx ignore their scale factor. */
9865 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9866 && i
.log2_scale_factor
)
9867 as_warn (_("register scaling is being ignored here"));
9872 /* 16-bit checks. */
9874 && (!i
.base_reg
->reg_type
.bitfield
.word
9875 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9877 && (!i
.index_reg
->reg_type
.bitfield
.word
9878 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9880 && i
.base_reg
->reg_num
< 6
9881 && i
.index_reg
->reg_num
>= 6
9882 && i
.log2_scale_factor
== 0))))
9889 /* Handle vector immediates. */
9892 RC_SAE_immediate (const char *imm_start
)
9894 unsigned int match_found
, j
;
9895 const char *pstr
= imm_start
;
9903 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9905 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9909 rc_op
.type
= RC_NamesTable
[j
].type
;
9910 rc_op
.operand
= this_operand
;
9911 i
.rounding
= &rc_op
;
9915 as_bad (_("duplicated `%s'"), imm_start
);
9918 pstr
+= RC_NamesTable
[j
].len
;
9928 as_bad (_("Missing '}': '%s'"), imm_start
);
9931 /* RC/SAE immediate string should contain nothing more. */;
9934 as_bad (_("Junk after '}': '%s'"), imm_start
);
9938 exp
= &im_expressions
[i
.imm_operands
++];
9939 i
.op
[this_operand
].imms
= exp
;
9941 exp
->X_op
= O_constant
;
9942 exp
->X_add_number
= 0;
9943 exp
->X_add_symbol
= (symbolS
*) 0;
9944 exp
->X_op_symbol
= (symbolS
*) 0;
9946 i
.types
[this_operand
].bitfield
.imm8
= 1;
9950 /* Only string instructions can have a second memory operand, so
9951 reduce current_templates to just those if it contains any. */
9953 maybe_adjust_templates (void)
9955 const insn_template
*t
;
9957 gas_assert (i
.mem_operands
== 1);
9959 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9960 if (t
->opcode_modifier
.isstring
)
9963 if (t
< current_templates
->end
)
9965 static templates aux_templates
;
9966 bfd_boolean recheck
;
9968 aux_templates
.start
= t
;
9969 for (; t
< current_templates
->end
; ++t
)
9970 if (!t
->opcode_modifier
.isstring
)
9972 aux_templates
.end
= t
;
9974 /* Determine whether to re-check the first memory operand. */
9975 recheck
= (aux_templates
.start
!= current_templates
->start
9976 || t
!= current_templates
->end
);
9978 current_templates
= &aux_templates
;
9983 if (i
.memop1_string
!= NULL
9984 && i386_index_check (i
.memop1_string
) == 0)
9993 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9997 i386_att_operand (char *operand_string
)
10001 char *op_string
= operand_string
;
10003 if (is_space_char (*op_string
))
10006 /* We check for an absolute prefix (differentiating,
10007 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10008 if (*op_string
== ABSOLUTE_PREFIX
)
10011 if (is_space_char (*op_string
))
10013 i
.jumpabsolute
= TRUE
;
10016 /* Check if operand is a register. */
10017 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10019 i386_operand_type temp
;
10021 /* Check for a segment override by searching for ':' after a
10022 segment register. */
10023 op_string
= end_op
;
10024 if (is_space_char (*op_string
))
10026 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10028 switch (r
->reg_num
)
10031 i
.seg
[i
.mem_operands
] = &es
;
10034 i
.seg
[i
.mem_operands
] = &cs
;
10037 i
.seg
[i
.mem_operands
] = &ss
;
10040 i
.seg
[i
.mem_operands
] = &ds
;
10043 i
.seg
[i
.mem_operands
] = &fs
;
10046 i
.seg
[i
.mem_operands
] = &gs
;
10050 /* Skip the ':' and whitespace. */
10052 if (is_space_char (*op_string
))
10055 if (!is_digit_char (*op_string
)
10056 && !is_identifier_char (*op_string
)
10057 && *op_string
!= '('
10058 && *op_string
!= ABSOLUTE_PREFIX
)
10060 as_bad (_("bad memory operand `%s'"), op_string
);
10063 /* Handle case of %es:*foo. */
10064 if (*op_string
== ABSOLUTE_PREFIX
)
10067 if (is_space_char (*op_string
))
10069 i
.jumpabsolute
= TRUE
;
10071 goto do_memory_reference
;
10074 /* Handle vector operations. */
10075 if (*op_string
== '{')
10077 op_string
= check_VecOperations (op_string
, NULL
);
10078 if (op_string
== NULL
)
10084 as_bad (_("junk `%s' after register"), op_string
);
10087 temp
= r
->reg_type
;
10088 temp
.bitfield
.baseindex
= 0;
10089 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10091 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10092 i
.op
[this_operand
].regs
= r
;
10095 else if (*op_string
== REGISTER_PREFIX
)
10097 as_bad (_("bad register name `%s'"), op_string
);
10100 else if (*op_string
== IMMEDIATE_PREFIX
)
10103 if (i
.jumpabsolute
)
10105 as_bad (_("immediate operand illegal with absolute jump"));
10108 if (!i386_immediate (op_string
))
10111 else if (RC_SAE_immediate (operand_string
))
10113 /* If it is a RC or SAE immediate, do nothing. */
10116 else if (is_digit_char (*op_string
)
10117 || is_identifier_char (*op_string
)
10118 || *op_string
== '"'
10119 || *op_string
== '(')
10121 /* This is a memory reference of some sort. */
10124 /* Start and end of displacement string expression (if found). */
10125 char *displacement_string_start
;
10126 char *displacement_string_end
;
10129 do_memory_reference
:
10130 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10132 if ((i
.mem_operands
== 1
10133 && !current_templates
->start
->opcode_modifier
.isstring
)
10134 || i
.mem_operands
== 2)
10136 as_bad (_("too many memory references for `%s'"),
10137 current_templates
->start
->name
);
10141 /* Check for base index form. We detect the base index form by
10142 looking for an ')' at the end of the operand, searching
10143 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10145 base_string
= op_string
+ strlen (op_string
);
10147 /* Handle vector operations. */
10148 vop_start
= strchr (op_string
, '{');
10149 if (vop_start
&& vop_start
< base_string
)
10151 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10153 base_string
= vop_start
;
10157 if (is_space_char (*base_string
))
10160 /* If we only have a displacement, set-up for it to be parsed later. */
10161 displacement_string_start
= op_string
;
10162 displacement_string_end
= base_string
+ 1;
10164 if (*base_string
== ')')
10167 unsigned int parens_balanced
= 1;
10168 /* We've already checked that the number of left & right ()'s are
10169 equal, so this loop will not be infinite. */
10173 if (*base_string
== ')')
10175 if (*base_string
== '(')
10178 while (parens_balanced
);
10180 temp_string
= base_string
;
10182 /* Skip past '(' and whitespace. */
10184 if (is_space_char (*base_string
))
10187 if (*base_string
== ','
10188 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10191 displacement_string_end
= temp_string
;
10193 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10197 base_string
= end_op
;
10198 if (is_space_char (*base_string
))
10202 /* There may be an index reg or scale factor here. */
10203 if (*base_string
== ',')
10206 if (is_space_char (*base_string
))
10209 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10212 base_string
= end_op
;
10213 if (is_space_char (*base_string
))
10215 if (*base_string
== ',')
10218 if (is_space_char (*base_string
))
10221 else if (*base_string
!= ')')
10223 as_bad (_("expecting `,' or `)' "
10224 "after index register in `%s'"),
10229 else if (*base_string
== REGISTER_PREFIX
)
10231 end_op
= strchr (base_string
, ',');
10234 as_bad (_("bad register name `%s'"), base_string
);
10238 /* Check for scale factor. */
10239 if (*base_string
!= ')')
10241 char *end_scale
= i386_scale (base_string
);
10246 base_string
= end_scale
;
10247 if (is_space_char (*base_string
))
10249 if (*base_string
!= ')')
10251 as_bad (_("expecting `)' "
10252 "after scale factor in `%s'"),
10257 else if (!i
.index_reg
)
10259 as_bad (_("expecting index register or scale factor "
10260 "after `,'; got '%c'"),
10265 else if (*base_string
!= ')')
10267 as_bad (_("expecting `,' or `)' "
10268 "after base register in `%s'"),
10273 else if (*base_string
== REGISTER_PREFIX
)
10275 end_op
= strchr (base_string
, ',');
10278 as_bad (_("bad register name `%s'"), base_string
);
10283 /* If there's an expression beginning the operand, parse it,
10284 assuming displacement_string_start and
10285 displacement_string_end are meaningful. */
10286 if (displacement_string_start
!= displacement_string_end
)
10288 if (!i386_displacement (displacement_string_start
,
10289 displacement_string_end
))
10293 /* Special case for (%dx) while doing input/output op. */
10295 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10296 && i
.base_reg
->reg_type
.bitfield
.word
10297 && i
.index_reg
== 0
10298 && i
.log2_scale_factor
== 0
10299 && i
.seg
[i
.mem_operands
] == 0
10300 && !operand_type_check (i
.types
[this_operand
], disp
))
10302 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10306 if (i386_index_check (operand_string
) == 0)
10308 i
.flags
[this_operand
] |= Operand_Mem
;
10309 if (i
.mem_operands
== 0)
10310 i
.memop1_string
= xstrdup (operand_string
);
10315 /* It's not a memory operand; argh! */
10316 as_bad (_("invalid char %s beginning operand %d `%s'"),
10317 output_invalid (*op_string
),
10322 return 1; /* Normal return. */
10325 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10326 that an rs_machine_dependent frag may reach. */
10329 i386_frag_max_var (fragS
*frag
)
10331 /* The only relaxable frags are for jumps.
10332 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10333 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10334 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10337 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10339 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10341 /* STT_GNU_IFUNC symbol must go through PLT. */
10342 if ((symbol_get_bfdsym (fr_symbol
)->flags
10343 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10346 if (!S_IS_EXTERNAL (fr_symbol
))
10347 /* Symbol may be weak or local. */
10348 return !S_IS_WEAK (fr_symbol
);
10350 /* Global symbols with non-default visibility can't be preempted. */
10351 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10354 if (fr_var
!= NO_RELOC
)
10355 switch ((enum bfd_reloc_code_real
) fr_var
)
10357 case BFD_RELOC_386_PLT32
:
10358 case BFD_RELOC_X86_64_PLT32
:
10359 /* Symbol with PLT relocation may be preempted. */
10365 /* Global symbols with default visibility in a shared library may be
10366 preempted by another definition. */
10371 /* md_estimate_size_before_relax()
10373 Called just before relax() for rs_machine_dependent frags. The x86
10374 assembler uses these frags to handle variable size jump
10377 Any symbol that is now undefined will not become defined.
10378 Return the correct fr_subtype in the frag.
10379 Return the initial "guess for variable size of frag" to caller.
10380 The guess is actually the growth beyond the fixed part. Whatever
10381 we do to grow the fixed or variable part contributes to our
10385 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10387 /* We've already got fragP->fr_subtype right; all we have to do is
10388 check for un-relaxable symbols. On an ELF system, we can't relax
10389 an externally visible symbol, because it may be overridden by a
10391 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10392 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10394 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10397 #if defined (OBJ_COFF) && defined (TE_PE)
10398 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10399 && S_IS_WEAK (fragP
->fr_symbol
))
10403 /* Symbol is undefined in this segment, or we need to keep a
10404 reloc so that weak symbols can be overridden. */
10405 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10406 enum bfd_reloc_code_real reloc_type
;
10407 unsigned char *opcode
;
10410 if (fragP
->fr_var
!= NO_RELOC
)
10411 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10412 else if (size
== 2)
10413 reloc_type
= BFD_RELOC_16_PCREL
;
10414 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10415 else if (need_plt32_p (fragP
->fr_symbol
))
10416 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10419 reloc_type
= BFD_RELOC_32_PCREL
;
10421 old_fr_fix
= fragP
->fr_fix
;
10422 opcode
= (unsigned char *) fragP
->fr_opcode
;
10424 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10427 /* Make jmp (0xeb) a (d)word displacement jump. */
10429 fragP
->fr_fix
+= size
;
10430 fix_new (fragP
, old_fr_fix
, size
,
10432 fragP
->fr_offset
, 1,
10438 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10440 /* Negate the condition, and branch past an
10441 unconditional jump. */
10444 /* Insert an unconditional jump. */
10446 /* We added two extra opcode bytes, and have a two byte
10448 fragP
->fr_fix
+= 2 + 2;
10449 fix_new (fragP
, old_fr_fix
+ 2, 2,
10451 fragP
->fr_offset
, 1,
10455 /* Fall through. */
10458 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10462 fragP
->fr_fix
+= 1;
10463 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10465 fragP
->fr_offset
, 1,
10466 BFD_RELOC_8_PCREL
);
10467 fixP
->fx_signed
= 1;
10471 /* This changes the byte-displacement jump 0x7N
10472 to the (d)word-displacement jump 0x0f,0x8N. */
10473 opcode
[1] = opcode
[0] + 0x10;
10474 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10475 /* We've added an opcode byte. */
10476 fragP
->fr_fix
+= 1 + size
;
10477 fix_new (fragP
, old_fr_fix
+ 1, size
,
10479 fragP
->fr_offset
, 1,
10484 BAD_CASE (fragP
->fr_subtype
);
10488 return fragP
->fr_fix
- old_fr_fix
;
10491 /* Guess size depending on current relax state. Initially the relax
10492 state will correspond to a short jump and we return 1, because
10493 the variable part of the frag (the branch offset) is one byte
10494 long. However, we can relax a section more than once and in that
10495 case we must either set fr_subtype back to the unrelaxed state,
10496 or return the value for the appropriate branch. */
10497 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10500 /* Called after relax() is finished.
10502 In: Address of frag.
10503 fr_type == rs_machine_dependent.
10504 fr_subtype is what the address relaxed to.
10506 Out: Any fixSs and constants are set up.
10507 Caller will turn frag into a ".space 0". */
10510 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10513 unsigned char *opcode
;
10514 unsigned char *where_to_put_displacement
= NULL
;
10515 offsetT target_address
;
10516 offsetT opcode_address
;
10517 unsigned int extension
= 0;
10518 offsetT displacement_from_opcode_start
;
10520 opcode
= (unsigned char *) fragP
->fr_opcode
;
10522 /* Address we want to reach in file space. */
10523 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10525 /* Address opcode resides at in file space. */
10526 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10528 /* Displacement from opcode start to fill into instruction. */
10529 displacement_from_opcode_start
= target_address
- opcode_address
;
10531 if ((fragP
->fr_subtype
& BIG
) == 0)
10533 /* Don't have to change opcode. */
10534 extension
= 1; /* 1 opcode + 1 displacement */
10535 where_to_put_displacement
= &opcode
[1];
10539 if (no_cond_jump_promotion
10540 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10541 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10542 _("long jump required"));
10544 switch (fragP
->fr_subtype
)
10546 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10547 extension
= 4; /* 1 opcode + 4 displacement */
10549 where_to_put_displacement
= &opcode
[1];
10552 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10553 extension
= 2; /* 1 opcode + 2 displacement */
10555 where_to_put_displacement
= &opcode
[1];
10558 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10559 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10560 extension
= 5; /* 2 opcode + 4 displacement */
10561 opcode
[1] = opcode
[0] + 0x10;
10562 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10563 where_to_put_displacement
= &opcode
[2];
10566 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10567 extension
= 3; /* 2 opcode + 2 displacement */
10568 opcode
[1] = opcode
[0] + 0x10;
10569 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10570 where_to_put_displacement
= &opcode
[2];
10573 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10578 where_to_put_displacement
= &opcode
[3];
10582 BAD_CASE (fragP
->fr_subtype
);
10587 /* If size if less then four we are sure that the operand fits,
10588 but if it's 4, then it could be that the displacement is larger
10590 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10592 && ((addressT
) (displacement_from_opcode_start
- extension
10593 + ((addressT
) 1 << 31))
10594 > (((addressT
) 2 << 31) - 1)))
10596 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10597 _("jump target out of range"));
10598 /* Make us emit 0. */
10599 displacement_from_opcode_start
= extension
;
10601 /* Now put displacement after opcode. */
10602 md_number_to_chars ((char *) where_to_put_displacement
,
10603 (valueT
) (displacement_from_opcode_start
- extension
),
10604 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10605 fragP
->fr_fix
+= extension
;
10608 /* Apply a fixup (fixP) to segment data, once it has been determined
10609 by our caller that we have all the info we need to fix it up.
10611 Parameter valP is the pointer to the value of the bits.
10613 On the 386, immediates, displacements, and data pointers are all in
10614 the same (little-endian) format, so we don't need to care about which
10615 we are handling. */
10618 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10620 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10621 valueT value
= *valP
;
10623 #if !defined (TE_Mach)
10624 if (fixP
->fx_pcrel
)
10626 switch (fixP
->fx_r_type
)
10632 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10635 case BFD_RELOC_X86_64_32S
:
10636 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10639 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10642 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10647 if (fixP
->fx_addsy
!= NULL
10648 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10649 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10650 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10651 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10652 && !use_rela_relocations
)
10654 /* This is a hack. There should be a better way to handle this.
10655 This covers for the fact that bfd_install_relocation will
10656 subtract the current location (for partial_inplace, PC relative
10657 relocations); see more below. */
10661 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10664 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10666 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10669 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10671 if ((sym_seg
== seg
10672 || (symbol_section_p (fixP
->fx_addsy
)
10673 && sym_seg
!= absolute_section
))
10674 && !generic_force_reloc (fixP
))
10676 /* Yes, we add the values in twice. This is because
10677 bfd_install_relocation subtracts them out again. I think
10678 bfd_install_relocation is broken, but I don't dare change
10680 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10684 #if defined (OBJ_COFF) && defined (TE_PE)
10685 /* For some reason, the PE format does not store a
10686 section address offset for a PC relative symbol. */
10687 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10688 || S_IS_WEAK (fixP
->fx_addsy
))
10689 value
+= md_pcrel_from (fixP
);
10692 #if defined (OBJ_COFF) && defined (TE_PE)
10693 if (fixP
->fx_addsy
!= NULL
10694 && S_IS_WEAK (fixP
->fx_addsy
)
10695 /* PR 16858: Do not modify weak function references. */
10696 && ! fixP
->fx_pcrel
)
10698 #if !defined (TE_PEP)
10699 /* For x86 PE weak function symbols are neither PC-relative
10700 nor do they set S_IS_FUNCTION. So the only reliable way
10701 to detect them is to check the flags of their containing
10703 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10704 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10708 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10712 /* Fix a few things - the dynamic linker expects certain values here,
10713 and we must not disappoint it. */
10714 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10715 if (IS_ELF
&& fixP
->fx_addsy
)
10716 switch (fixP
->fx_r_type
)
10718 case BFD_RELOC_386_PLT32
:
10719 case BFD_RELOC_X86_64_PLT32
:
10720 /* Make the jump instruction point to the address of the operand.
10721 At runtime we merely add the offset to the actual PLT entry.
10722 NB: Subtract the offset size only for jump instructions. */
10723 if (fixP
->fx_pcrel
)
10727 case BFD_RELOC_386_TLS_GD
:
10728 case BFD_RELOC_386_TLS_LDM
:
10729 case BFD_RELOC_386_TLS_IE_32
:
10730 case BFD_RELOC_386_TLS_IE
:
10731 case BFD_RELOC_386_TLS_GOTIE
:
10732 case BFD_RELOC_386_TLS_GOTDESC
:
10733 case BFD_RELOC_X86_64_TLSGD
:
10734 case BFD_RELOC_X86_64_TLSLD
:
10735 case BFD_RELOC_X86_64_GOTTPOFF
:
10736 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10737 value
= 0; /* Fully resolved at runtime. No addend. */
10739 case BFD_RELOC_386_TLS_LE
:
10740 case BFD_RELOC_386_TLS_LDO_32
:
10741 case BFD_RELOC_386_TLS_LE_32
:
10742 case BFD_RELOC_X86_64_DTPOFF32
:
10743 case BFD_RELOC_X86_64_DTPOFF64
:
10744 case BFD_RELOC_X86_64_TPOFF32
:
10745 case BFD_RELOC_X86_64_TPOFF64
:
10746 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10749 case BFD_RELOC_386_TLS_DESC_CALL
:
10750 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10751 value
= 0; /* Fully resolved at runtime. No addend. */
10752 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10756 case BFD_RELOC_VTABLE_INHERIT
:
10757 case BFD_RELOC_VTABLE_ENTRY
:
10764 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10766 #endif /* !defined (TE_Mach) */
10768 /* Are we finished with this relocation now? */
10769 if (fixP
->fx_addsy
== NULL
)
10771 #if defined (OBJ_COFF) && defined (TE_PE)
10772 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10775 /* Remember value for tc_gen_reloc. */
10776 fixP
->fx_addnumber
= value
;
10777 /* Clear out the frag for now. */
10781 else if (use_rela_relocations
)
10783 fixP
->fx_no_overflow
= 1;
10784 /* Remember value for tc_gen_reloc. */
10785 fixP
->fx_addnumber
= value
;
10789 md_number_to_chars (p
, value
, fixP
->fx_size
);
10793 md_atof (int type
, char *litP
, int *sizeP
)
10795 /* This outputs the LITTLENUMs in REVERSE order;
10796 in accord with the bigendian 386. */
10797 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10800 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10803 output_invalid (int c
)
10806 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10809 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10810 "(0x%x)", (unsigned char) c
);
10811 return output_invalid_buf
;
10814 /* REG_STRING starts *before* REGISTER_PREFIX. */
10816 static const reg_entry
*
10817 parse_real_register (char *reg_string
, char **end_op
)
10819 char *s
= reg_string
;
10821 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10822 const reg_entry
*r
;
10824 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10825 if (*s
== REGISTER_PREFIX
)
10828 if (is_space_char (*s
))
10831 p
= reg_name_given
;
10832 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10834 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10835 return (const reg_entry
*) NULL
;
10839 /* For naked regs, make sure that we are not dealing with an identifier.
10840 This prevents confusing an identifier like `eax_var' with register
10842 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10843 return (const reg_entry
*) NULL
;
10847 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10849 /* Handle floating point regs, allowing spaces in the (i) part. */
10850 if (r
== i386_regtab
/* %st is first entry of table */)
10852 if (!cpu_arch_flags
.bitfield
.cpu8087
10853 && !cpu_arch_flags
.bitfield
.cpu287
10854 && !cpu_arch_flags
.bitfield
.cpu387
)
10855 return (const reg_entry
*) NULL
;
10857 if (is_space_char (*s
))
10862 if (is_space_char (*s
))
10864 if (*s
>= '0' && *s
<= '7')
10866 int fpr
= *s
- '0';
10868 if (is_space_char (*s
))
10873 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10878 /* We have "%st(" then garbage. */
10879 return (const reg_entry
*) NULL
;
10883 if (r
== NULL
|| allow_pseudo_reg
)
10886 if (operand_type_all_zero (&r
->reg_type
))
10887 return (const reg_entry
*) NULL
;
10889 if ((r
->reg_type
.bitfield
.dword
10890 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
10891 || r
->reg_type
.bitfield
.class == RegCR
10892 || r
->reg_type
.bitfield
.class == RegDR
10893 || r
->reg_type
.bitfield
.class == RegTR
)
10894 && !cpu_arch_flags
.bitfield
.cpui386
)
10895 return (const reg_entry
*) NULL
;
10897 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
10898 return (const reg_entry
*) NULL
;
10900 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10902 if (r
->reg_type
.bitfield
.zmmword
10903 || r
->reg_type
.bitfield
.class == RegMask
)
10904 return (const reg_entry
*) NULL
;
10906 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10908 if (r
->reg_type
.bitfield
.ymmword
)
10909 return (const reg_entry
*) NULL
;
10911 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10912 return (const reg_entry
*) NULL
;
10916 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10917 return (const reg_entry
*) NULL
;
10919 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10920 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10921 return (const reg_entry
*) NULL
;
10923 /* Upper 16 vector registers are only available with VREX in 64bit
10924 mode, and require EVEX encoding. */
10925 if (r
->reg_flags
& RegVRex
)
10927 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10928 || flag_code
!= CODE_64BIT
)
10929 return (const reg_entry
*) NULL
;
10931 i
.vec_encoding
= vex_encoding_evex
;
10934 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10935 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
10936 && flag_code
!= CODE_64BIT
)
10937 return (const reg_entry
*) NULL
;
10939 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
10941 return (const reg_entry
*) NULL
;
10946 /* REG_STRING starts *before* REGISTER_PREFIX. */
10948 static const reg_entry
*
10949 parse_register (char *reg_string
, char **end_op
)
10951 const reg_entry
*r
;
10953 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10954 r
= parse_real_register (reg_string
, end_op
);
10959 char *save
= input_line_pointer
;
10963 input_line_pointer
= reg_string
;
10964 c
= get_symbol_name (®_string
);
10965 symbolP
= symbol_find (reg_string
);
10966 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10968 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10970 know (e
->X_op
== O_register
);
10971 know (e
->X_add_number
>= 0
10972 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10973 r
= i386_regtab
+ e
->X_add_number
;
10974 if ((r
->reg_flags
& RegVRex
))
10975 i
.vec_encoding
= vex_encoding_evex
;
10976 *end_op
= input_line_pointer
;
10978 *input_line_pointer
= c
;
10979 input_line_pointer
= save
;
10985 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10987 const reg_entry
*r
;
10988 char *end
= input_line_pointer
;
10991 r
= parse_register (name
, &input_line_pointer
);
10992 if (r
&& end
<= input_line_pointer
)
10994 *nextcharP
= *input_line_pointer
;
10995 *input_line_pointer
= 0;
10996 e
->X_op
= O_register
;
10997 e
->X_add_number
= r
- i386_regtab
;
11000 input_line_pointer
= end
;
11002 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11006 md_operand (expressionS
*e
)
11009 const reg_entry
*r
;
11011 switch (*input_line_pointer
)
11013 case REGISTER_PREFIX
:
11014 r
= parse_real_register (input_line_pointer
, &end
);
11017 e
->X_op
= O_register
;
11018 e
->X_add_number
= r
- i386_regtab
;
11019 input_line_pointer
= end
;
11024 gas_assert (intel_syntax
);
11025 end
= input_line_pointer
++;
11027 if (*input_line_pointer
== ']')
11029 ++input_line_pointer
;
11030 e
->X_op_symbol
= make_expr_symbol (e
);
11031 e
->X_add_symbol
= NULL
;
11032 e
->X_add_number
= 0;
11037 e
->X_op
= O_absent
;
11038 input_line_pointer
= end
;
11045 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11046 const char *md_shortopts
= "kVQ:sqnO::";
11048 const char *md_shortopts
= "qnO::";
11051 #define OPTION_32 (OPTION_MD_BASE + 0)
11052 #define OPTION_64 (OPTION_MD_BASE + 1)
11053 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11054 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11055 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11056 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11057 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11058 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11059 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11060 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11061 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11062 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11063 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11064 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11065 #define OPTION_X32 (OPTION_MD_BASE + 14)
11066 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11067 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11068 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11069 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11070 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11071 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11072 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11073 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11074 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11075 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11076 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11077 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11079 struct option md_longopts
[] =
11081 {"32", no_argument
, NULL
, OPTION_32
},
11082 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11083 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11084 {"64", no_argument
, NULL
, OPTION_64
},
11086 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11087 {"x32", no_argument
, NULL
, OPTION_X32
},
11088 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11089 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11091 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11092 {"march", required_argument
, NULL
, OPTION_MARCH
},
11093 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11094 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11095 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11096 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11097 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11098 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11099 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11100 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11101 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11102 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11103 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11104 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11105 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11106 # if defined (TE_PE) || defined (TE_PEP)
11107 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11109 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11110 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11111 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11112 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11113 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11114 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11115 {NULL
, no_argument
, NULL
, 0}
11117 size_t md_longopts_size
= sizeof (md_longopts
);
11120 md_parse_option (int c
, const char *arg
)
11123 char *arch
, *next
, *saved
;
11128 optimize_align_code
= 0;
11132 quiet_warnings
= 1;
11135 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11136 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11137 should be emitted or not. FIXME: Not implemented. */
11139 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
11143 /* -V: SVR4 argument to print version ID. */
11145 print_version_id ();
11148 /* -k: Ignore for FreeBSD compatibility. */
11153 /* -s: On i386 Solaris, this tells the native assembler to use
11154 .stab instead of .stab.excl. We always use .stab anyhow. */
11157 case OPTION_MSHARED
:
11161 case OPTION_X86_USED_NOTE
:
11162 if (strcasecmp (arg
, "yes") == 0)
11164 else if (strcasecmp (arg
, "no") == 0)
11167 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11172 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11173 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11176 const char **list
, **l
;
11178 list
= bfd_target_list ();
11179 for (l
= list
; *l
!= NULL
; l
++)
11180 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11181 || strcmp (*l
, "coff-x86-64") == 0
11182 || strcmp (*l
, "pe-x86-64") == 0
11183 || strcmp (*l
, "pei-x86-64") == 0
11184 || strcmp (*l
, "mach-o-x86-64") == 0)
11186 default_arch
= "x86_64";
11190 as_fatal (_("no compiled in support for x86_64"));
11196 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11200 const char **list
, **l
;
11202 list
= bfd_target_list ();
11203 for (l
= list
; *l
!= NULL
; l
++)
11204 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11206 default_arch
= "x86_64:32";
11210 as_fatal (_("no compiled in support for 32bit x86_64"));
11214 as_fatal (_("32bit x86_64 is only supported for ELF"));
11219 default_arch
= "i386";
11222 case OPTION_DIVIDE
:
11223 #ifdef SVR4_COMMENT_CHARS
11228 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11230 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11234 i386_comment_chars
= n
;
11240 saved
= xstrdup (arg
);
11242 /* Allow -march=+nosse. */
11248 as_fatal (_("invalid -march= option: `%s'"), arg
);
11249 next
= strchr (arch
, '+');
11252 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11254 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11257 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11260 cpu_arch_name
= cpu_arch
[j
].name
;
11261 cpu_sub_arch_name
= NULL
;
11262 cpu_arch_flags
= cpu_arch
[j
].flags
;
11263 cpu_arch_isa
= cpu_arch
[j
].type
;
11264 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11265 if (!cpu_arch_tune_set
)
11267 cpu_arch_tune
= cpu_arch_isa
;
11268 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11272 else if (*cpu_arch
[j
].name
== '.'
11273 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11275 /* ISA extension. */
11276 i386_cpu_flags flags
;
11278 flags
= cpu_flags_or (cpu_arch_flags
,
11279 cpu_arch
[j
].flags
);
11281 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11283 if (cpu_sub_arch_name
)
11285 char *name
= cpu_sub_arch_name
;
11286 cpu_sub_arch_name
= concat (name
,
11288 (const char *) NULL
);
11292 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11293 cpu_arch_flags
= flags
;
11294 cpu_arch_isa_flags
= flags
;
11298 = cpu_flags_or (cpu_arch_isa_flags
,
11299 cpu_arch
[j
].flags
);
11304 if (j
>= ARRAY_SIZE (cpu_arch
))
11306 /* Disable an ISA extension. */
11307 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11308 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11310 i386_cpu_flags flags
;
11312 flags
= cpu_flags_and_not (cpu_arch_flags
,
11313 cpu_noarch
[j
].flags
);
11314 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11316 if (cpu_sub_arch_name
)
11318 char *name
= cpu_sub_arch_name
;
11319 cpu_sub_arch_name
= concat (arch
,
11320 (const char *) NULL
);
11324 cpu_sub_arch_name
= xstrdup (arch
);
11325 cpu_arch_flags
= flags
;
11326 cpu_arch_isa_flags
= flags
;
11331 if (j
>= ARRAY_SIZE (cpu_noarch
))
11332 j
= ARRAY_SIZE (cpu_arch
);
11335 if (j
>= ARRAY_SIZE (cpu_arch
))
11336 as_fatal (_("invalid -march= option: `%s'"), arg
);
11340 while (next
!= NULL
);
11346 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11347 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11349 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11351 cpu_arch_tune_set
= 1;
11352 cpu_arch_tune
= cpu_arch
[j
].type
;
11353 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11357 if (j
>= ARRAY_SIZE (cpu_arch
))
11358 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11361 case OPTION_MMNEMONIC
:
11362 if (strcasecmp (arg
, "att") == 0)
11363 intel_mnemonic
= 0;
11364 else if (strcasecmp (arg
, "intel") == 0)
11365 intel_mnemonic
= 1;
11367 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11370 case OPTION_MSYNTAX
:
11371 if (strcasecmp (arg
, "att") == 0)
11373 else if (strcasecmp (arg
, "intel") == 0)
11376 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11379 case OPTION_MINDEX_REG
:
11380 allow_index_reg
= 1;
11383 case OPTION_MNAKED_REG
:
11384 allow_naked_reg
= 1;
11387 case OPTION_MSSE2AVX
:
11391 case OPTION_MSSE_CHECK
:
11392 if (strcasecmp (arg
, "error") == 0)
11393 sse_check
= check_error
;
11394 else if (strcasecmp (arg
, "warning") == 0)
11395 sse_check
= check_warning
;
11396 else if (strcasecmp (arg
, "none") == 0)
11397 sse_check
= check_none
;
11399 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11402 case OPTION_MOPERAND_CHECK
:
11403 if (strcasecmp (arg
, "error") == 0)
11404 operand_check
= check_error
;
11405 else if (strcasecmp (arg
, "warning") == 0)
11406 operand_check
= check_warning
;
11407 else if (strcasecmp (arg
, "none") == 0)
11408 operand_check
= check_none
;
11410 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11413 case OPTION_MAVXSCALAR
:
11414 if (strcasecmp (arg
, "128") == 0)
11415 avxscalar
= vex128
;
11416 else if (strcasecmp (arg
, "256") == 0)
11417 avxscalar
= vex256
;
11419 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11422 case OPTION_MVEXWIG
:
11423 if (strcmp (arg
, "0") == 0)
11425 else if (strcmp (arg
, "1") == 0)
11428 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11431 case OPTION_MADD_BND_PREFIX
:
11432 add_bnd_prefix
= 1;
11435 case OPTION_MEVEXLIG
:
11436 if (strcmp (arg
, "128") == 0)
11437 evexlig
= evexl128
;
11438 else if (strcmp (arg
, "256") == 0)
11439 evexlig
= evexl256
;
11440 else if (strcmp (arg
, "512") == 0)
11441 evexlig
= evexl512
;
11443 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11446 case OPTION_MEVEXRCIG
:
11447 if (strcmp (arg
, "rne") == 0)
11449 else if (strcmp (arg
, "rd") == 0)
11451 else if (strcmp (arg
, "ru") == 0)
11453 else if (strcmp (arg
, "rz") == 0)
11456 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11459 case OPTION_MEVEXWIG
:
11460 if (strcmp (arg
, "0") == 0)
11462 else if (strcmp (arg
, "1") == 0)
11465 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11468 # if defined (TE_PE) || defined (TE_PEP)
11469 case OPTION_MBIG_OBJ
:
11474 case OPTION_MOMIT_LOCK_PREFIX
:
11475 if (strcasecmp (arg
, "yes") == 0)
11476 omit_lock_prefix
= 1;
11477 else if (strcasecmp (arg
, "no") == 0)
11478 omit_lock_prefix
= 0;
11480 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11483 case OPTION_MFENCE_AS_LOCK_ADD
:
11484 if (strcasecmp (arg
, "yes") == 0)
11486 else if (strcasecmp (arg
, "no") == 0)
11489 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11492 case OPTION_MRELAX_RELOCATIONS
:
11493 if (strcasecmp (arg
, "yes") == 0)
11494 generate_relax_relocations
= 1;
11495 else if (strcasecmp (arg
, "no") == 0)
11496 generate_relax_relocations
= 0;
11498 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11501 case OPTION_MAMD64
:
11505 case OPTION_MINTEL64
:
11513 /* Turn off -Os. */
11514 optimize_for_space
= 0;
11516 else if (*arg
== 's')
11518 optimize_for_space
= 1;
11519 /* Turn on all encoding optimizations. */
11520 optimize
= INT_MAX
;
11524 optimize
= atoi (arg
);
11525 /* Turn off -Os. */
11526 optimize_for_space
= 0;
11536 #define MESSAGE_TEMPLATE \
11540 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11541 int *left_p
, const char *name
, int len
)
11543 int size
= sizeof (MESSAGE_TEMPLATE
);
11544 int left
= *left_p
;
11546 /* Reserve 2 spaces for ", " or ",\0" */
11549 /* Check if there is any room. */
11557 p
= mempcpy (p
, name
, len
);
11561 /* Output the current message now and start a new one. */
11564 fprintf (stream
, "%s\n", message
);
11566 left
= size
- (start
- message
) - len
- 2;
11568 gas_assert (left
>= 0);
11570 p
= mempcpy (p
, name
, len
);
11578 show_arch (FILE *stream
, int ext
, int check
)
11580 static char message
[] = MESSAGE_TEMPLATE
;
11581 char *start
= message
+ 27;
11583 int size
= sizeof (MESSAGE_TEMPLATE
);
11590 left
= size
- (start
- message
);
11591 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11593 /* Should it be skipped? */
11594 if (cpu_arch
[j
].skip
)
11597 name
= cpu_arch
[j
].name
;
11598 len
= cpu_arch
[j
].len
;
11601 /* It is an extension. Skip if we aren't asked to show it. */
11612 /* It is an processor. Skip if we show only extension. */
11615 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11617 /* It is an impossible processor - skip. */
11621 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11624 /* Display disabled extensions. */
11626 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11628 name
= cpu_noarch
[j
].name
;
11629 len
= cpu_noarch
[j
].len
;
11630 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11635 fprintf (stream
, "%s\n", message
);
11639 md_show_usage (FILE *stream
)
11641 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11642 fprintf (stream
, _("\
11643 -Qy, -Qn ignored\n\
11644 -V print assembler version number\n\
11647 fprintf (stream
, _("\
11648 -n Do not optimize code alignment\n\
11649 -q quieten some warnings\n"));
11650 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11651 fprintf (stream
, _("\
11654 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11655 || defined (TE_PE) || defined (TE_PEP))
11656 fprintf (stream
, _("\
11657 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11659 #ifdef SVR4_COMMENT_CHARS
11660 fprintf (stream
, _("\
11661 --divide do not treat `/' as a comment character\n"));
11663 fprintf (stream
, _("\
11664 --divide ignored\n"));
11666 fprintf (stream
, _("\
11667 -march=CPU[,+EXTENSION...]\n\
11668 generate code for CPU and EXTENSION, CPU is one of:\n"));
11669 show_arch (stream
, 0, 1);
11670 fprintf (stream
, _("\
11671 EXTENSION is combination of:\n"));
11672 show_arch (stream
, 1, 0);
11673 fprintf (stream
, _("\
11674 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11675 show_arch (stream
, 0, 0);
11676 fprintf (stream
, _("\
11677 -msse2avx encode SSE instructions with VEX prefix\n"));
11678 fprintf (stream
, _("\
11679 -msse-check=[none|error|warning] (default: warning)\n\
11680 check SSE instructions\n"));
11681 fprintf (stream
, _("\
11682 -moperand-check=[none|error|warning] (default: warning)\n\
11683 check operand combinations for validity\n"));
11684 fprintf (stream
, _("\
11685 -mavxscalar=[128|256] (default: 128)\n\
11686 encode scalar AVX instructions with specific vector\n\
11688 fprintf (stream
, _("\
11689 -mvexwig=[0|1] (default: 0)\n\
11690 encode VEX instructions with specific VEX.W value\n\
11691 for VEX.W bit ignored instructions\n"));
11692 fprintf (stream
, _("\
11693 -mevexlig=[128|256|512] (default: 128)\n\
11694 encode scalar EVEX instructions with specific vector\n\
11696 fprintf (stream
, _("\
11697 -mevexwig=[0|1] (default: 0)\n\
11698 encode EVEX instructions with specific EVEX.W value\n\
11699 for EVEX.W bit ignored instructions\n"));
11700 fprintf (stream
, _("\
11701 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11702 encode EVEX instructions with specific EVEX.RC value\n\
11703 for SAE-only ignored instructions\n"));
11704 fprintf (stream
, _("\
11705 -mmnemonic=[att|intel] "));
11706 if (SYSV386_COMPAT
)
11707 fprintf (stream
, _("(default: att)\n"));
11709 fprintf (stream
, _("(default: intel)\n"));
11710 fprintf (stream
, _("\
11711 use AT&T/Intel mnemonic\n"));
11712 fprintf (stream
, _("\
11713 -msyntax=[att|intel] (default: att)\n\
11714 use AT&T/Intel syntax\n"));
11715 fprintf (stream
, _("\
11716 -mindex-reg support pseudo index registers\n"));
11717 fprintf (stream
, _("\
11718 -mnaked-reg don't require `%%' prefix for registers\n"));
11719 fprintf (stream
, _("\
11720 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11721 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11722 fprintf (stream
, _("\
11723 -mshared disable branch optimization for shared code\n"));
11724 fprintf (stream
, _("\
11725 -mx86-used-note=[no|yes] "));
11726 if (DEFAULT_X86_USED_NOTE
)
11727 fprintf (stream
, _("(default: yes)\n"));
11729 fprintf (stream
, _("(default: no)\n"));
11730 fprintf (stream
, _("\
11731 generate x86 used ISA and feature properties\n"));
11733 #if defined (TE_PE) || defined (TE_PEP)
11734 fprintf (stream
, _("\
11735 -mbig-obj generate big object files\n"));
11737 fprintf (stream
, _("\
11738 -momit-lock-prefix=[no|yes] (default: no)\n\
11739 strip all lock prefixes\n"));
11740 fprintf (stream
, _("\
11741 -mfence-as-lock-add=[no|yes] (default: no)\n\
11742 encode lfence, mfence and sfence as\n\
11743 lock addl $0x0, (%%{re}sp)\n"));
11744 fprintf (stream
, _("\
11745 -mrelax-relocations=[no|yes] "));
11746 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11747 fprintf (stream
, _("(default: yes)\n"));
11749 fprintf (stream
, _("(default: no)\n"));
11750 fprintf (stream
, _("\
11751 generate relax relocations\n"));
11752 fprintf (stream
, _("\
11753 -mamd64 accept only AMD64 ISA [default]\n"));
11754 fprintf (stream
, _("\
11755 -mintel64 accept only Intel64 ISA\n"));
11758 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11759 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11760 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11762 /* Pick the target format to use. */
11765 i386_target_format (void)
11767 if (!strncmp (default_arch
, "x86_64", 6))
11769 update_code_flag (CODE_64BIT
, 1);
11770 if (default_arch
[6] == '\0')
11771 x86_elf_abi
= X86_64_ABI
;
11773 x86_elf_abi
= X86_64_X32_ABI
;
11775 else if (!strcmp (default_arch
, "i386"))
11776 update_code_flag (CODE_32BIT
, 1);
11777 else if (!strcmp (default_arch
, "iamcu"))
11779 update_code_flag (CODE_32BIT
, 1);
11780 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11782 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11783 cpu_arch_name
= "iamcu";
11784 cpu_sub_arch_name
= NULL
;
11785 cpu_arch_flags
= iamcu_flags
;
11786 cpu_arch_isa
= PROCESSOR_IAMCU
;
11787 cpu_arch_isa_flags
= iamcu_flags
;
11788 if (!cpu_arch_tune_set
)
11790 cpu_arch_tune
= cpu_arch_isa
;
11791 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11794 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11795 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11799 as_fatal (_("unknown architecture"));
11801 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11802 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11803 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11804 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11806 switch (OUTPUT_FLAVOR
)
11808 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11809 case bfd_target_aout_flavour
:
11810 return AOUT_TARGET_FORMAT
;
11812 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11813 # if defined (TE_PE) || defined (TE_PEP)
11814 case bfd_target_coff_flavour
:
11815 if (flag_code
== CODE_64BIT
)
11816 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11819 # elif defined (TE_GO32)
11820 case bfd_target_coff_flavour
:
11821 return "coff-go32";
11823 case bfd_target_coff_flavour
:
11824 return "coff-i386";
11827 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11828 case bfd_target_elf_flavour
:
11830 const char *format
;
11832 switch (x86_elf_abi
)
11835 format
= ELF_TARGET_FORMAT
;
11838 use_rela_relocations
= 1;
11840 format
= ELF_TARGET_FORMAT64
;
11842 case X86_64_X32_ABI
:
11843 use_rela_relocations
= 1;
11845 disallow_64bit_reloc
= 1;
11846 format
= ELF_TARGET_FORMAT32
;
11849 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11851 if (x86_elf_abi
!= X86_64_ABI
)
11852 as_fatal (_("Intel L1OM is 64bit only"));
11853 return ELF_TARGET_L1OM_FORMAT
;
11855 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11857 if (x86_elf_abi
!= X86_64_ABI
)
11858 as_fatal (_("Intel K1OM is 64bit only"));
11859 return ELF_TARGET_K1OM_FORMAT
;
11861 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11863 if (x86_elf_abi
!= I386_ABI
)
11864 as_fatal (_("Intel MCU is 32bit only"));
11865 return ELF_TARGET_IAMCU_FORMAT
;
11871 #if defined (OBJ_MACH_O)
11872 case bfd_target_mach_o_flavour
:
11873 if (flag_code
== CODE_64BIT
)
11875 use_rela_relocations
= 1;
11877 return "mach-o-x86-64";
11880 return "mach-o-i386";
11888 #endif /* OBJ_MAYBE_ more than one */
11891 md_undefined_symbol (char *name
)
11893 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11894 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11895 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11896 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11900 if (symbol_find (name
))
11901 as_bad (_("GOT already in symbol table"));
11902 GOT_symbol
= symbol_new (name
, undefined_section
,
11903 (valueT
) 0, &zero_address_frag
);
11910 /* Round up a section size to the appropriate boundary. */
11913 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11915 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11916 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11918 /* For a.out, force the section size to be aligned. If we don't do
11919 this, BFD will align it for us, but it will not write out the
11920 final bytes of the section. This may be a bug in BFD, but it is
11921 easier to fix it here since that is how the other a.out targets
11925 align
= bfd_section_alignment (segment
);
11926 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11933 /* On the i386, PC-relative offsets are relative to the start of the
11934 next instruction. That is, the address of the offset, plus its
11935 size, since the offset is always the last part of the insn. */
11938 md_pcrel_from (fixS
*fixP
)
11940 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11946 s_bss (int ignore ATTRIBUTE_UNUSED
)
11950 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11952 obj_elf_section_change_hook ();
11954 temp
= get_absolute_expression ();
11955 subseg_set (bss_section
, (subsegT
) temp
);
11956 demand_empty_rest_of_line ();
11962 i386_validate_fix (fixS
*fixp
)
11964 if (fixp
->fx_subsy
)
11966 if (fixp
->fx_subsy
== GOT_symbol
)
11968 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11972 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11973 if (fixp
->fx_tcbit2
)
11974 fixp
->fx_r_type
= (fixp
->fx_tcbit
11975 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11976 : BFD_RELOC_X86_64_GOTPCRELX
);
11979 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11984 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11986 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11988 fixp
->fx_subsy
= 0;
11991 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11992 else if (!object_64bit
)
11994 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11995 && fixp
->fx_tcbit2
)
11996 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
12002 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12005 bfd_reloc_code_real_type code
;
12007 switch (fixp
->fx_r_type
)
12009 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12010 case BFD_RELOC_SIZE32
:
12011 case BFD_RELOC_SIZE64
:
12012 if (S_IS_DEFINED (fixp
->fx_addsy
)
12013 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
12015 /* Resolve size relocation against local symbol to size of
12016 the symbol plus addend. */
12017 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
12018 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
12019 && !fits_in_unsigned_long (value
))
12020 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12021 _("symbol size computation overflow"));
12022 fixp
->fx_addsy
= NULL
;
12023 fixp
->fx_subsy
= NULL
;
12024 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
12028 /* Fall through. */
12030 case BFD_RELOC_X86_64_PLT32
:
12031 case BFD_RELOC_X86_64_GOT32
:
12032 case BFD_RELOC_X86_64_GOTPCREL
:
12033 case BFD_RELOC_X86_64_GOTPCRELX
:
12034 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12035 case BFD_RELOC_386_PLT32
:
12036 case BFD_RELOC_386_GOT32
:
12037 case BFD_RELOC_386_GOT32X
:
12038 case BFD_RELOC_386_GOTOFF
:
12039 case BFD_RELOC_386_GOTPC
:
12040 case BFD_RELOC_386_TLS_GD
:
12041 case BFD_RELOC_386_TLS_LDM
:
12042 case BFD_RELOC_386_TLS_LDO_32
:
12043 case BFD_RELOC_386_TLS_IE_32
:
12044 case BFD_RELOC_386_TLS_IE
:
12045 case BFD_RELOC_386_TLS_GOTIE
:
12046 case BFD_RELOC_386_TLS_LE_32
:
12047 case BFD_RELOC_386_TLS_LE
:
12048 case BFD_RELOC_386_TLS_GOTDESC
:
12049 case BFD_RELOC_386_TLS_DESC_CALL
:
12050 case BFD_RELOC_X86_64_TLSGD
:
12051 case BFD_RELOC_X86_64_TLSLD
:
12052 case BFD_RELOC_X86_64_DTPOFF32
:
12053 case BFD_RELOC_X86_64_DTPOFF64
:
12054 case BFD_RELOC_X86_64_GOTTPOFF
:
12055 case BFD_RELOC_X86_64_TPOFF32
:
12056 case BFD_RELOC_X86_64_TPOFF64
:
12057 case BFD_RELOC_X86_64_GOTOFF64
:
12058 case BFD_RELOC_X86_64_GOTPC32
:
12059 case BFD_RELOC_X86_64_GOT64
:
12060 case BFD_RELOC_X86_64_GOTPCREL64
:
12061 case BFD_RELOC_X86_64_GOTPC64
:
12062 case BFD_RELOC_X86_64_GOTPLT64
:
12063 case BFD_RELOC_X86_64_PLTOFF64
:
12064 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12065 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12066 case BFD_RELOC_RVA
:
12067 case BFD_RELOC_VTABLE_ENTRY
:
12068 case BFD_RELOC_VTABLE_INHERIT
:
12070 case BFD_RELOC_32_SECREL
:
12072 code
= fixp
->fx_r_type
;
12074 case BFD_RELOC_X86_64_32S
:
12075 if (!fixp
->fx_pcrel
)
12077 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12078 code
= fixp
->fx_r_type
;
12081 /* Fall through. */
12083 if (fixp
->fx_pcrel
)
12085 switch (fixp
->fx_size
)
12088 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12089 _("can not do %d byte pc-relative relocation"),
12091 code
= BFD_RELOC_32_PCREL
;
12093 case 1: code
= BFD_RELOC_8_PCREL
; break;
12094 case 2: code
= BFD_RELOC_16_PCREL
; break;
12095 case 4: code
= BFD_RELOC_32_PCREL
; break;
12097 case 8: code
= BFD_RELOC_64_PCREL
; break;
12103 switch (fixp
->fx_size
)
12106 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12107 _("can not do %d byte relocation"),
12109 code
= BFD_RELOC_32
;
12111 case 1: code
= BFD_RELOC_8
; break;
12112 case 2: code
= BFD_RELOC_16
; break;
12113 case 4: code
= BFD_RELOC_32
; break;
12115 case 8: code
= BFD_RELOC_64
; break;
12122 if ((code
== BFD_RELOC_32
12123 || code
== BFD_RELOC_32_PCREL
12124 || code
== BFD_RELOC_X86_64_32S
)
12126 && fixp
->fx_addsy
== GOT_symbol
)
12129 code
= BFD_RELOC_386_GOTPC
;
12131 code
= BFD_RELOC_X86_64_GOTPC32
;
12133 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12135 && fixp
->fx_addsy
== GOT_symbol
)
12137 code
= BFD_RELOC_X86_64_GOTPC64
;
12140 rel
= XNEW (arelent
);
12141 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12142 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12144 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12146 if (!use_rela_relocations
)
12148 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12149 vtable entry to be used in the relocation's section offset. */
12150 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12151 rel
->address
= fixp
->fx_offset
;
12152 #if defined (OBJ_COFF) && defined (TE_PE)
12153 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12154 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12159 /* Use the rela in 64bit mode. */
12162 if (disallow_64bit_reloc
)
12165 case BFD_RELOC_X86_64_DTPOFF64
:
12166 case BFD_RELOC_X86_64_TPOFF64
:
12167 case BFD_RELOC_64_PCREL
:
12168 case BFD_RELOC_X86_64_GOTOFF64
:
12169 case BFD_RELOC_X86_64_GOT64
:
12170 case BFD_RELOC_X86_64_GOTPCREL64
:
12171 case BFD_RELOC_X86_64_GOTPC64
:
12172 case BFD_RELOC_X86_64_GOTPLT64
:
12173 case BFD_RELOC_X86_64_PLTOFF64
:
12174 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12175 _("cannot represent relocation type %s in x32 mode"),
12176 bfd_get_reloc_code_name (code
));
12182 if (!fixp
->fx_pcrel
)
12183 rel
->addend
= fixp
->fx_offset
;
12187 case BFD_RELOC_X86_64_PLT32
:
12188 case BFD_RELOC_X86_64_GOT32
:
12189 case BFD_RELOC_X86_64_GOTPCREL
:
12190 case BFD_RELOC_X86_64_GOTPCRELX
:
12191 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12192 case BFD_RELOC_X86_64_TLSGD
:
12193 case BFD_RELOC_X86_64_TLSLD
:
12194 case BFD_RELOC_X86_64_GOTTPOFF
:
12195 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12196 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12197 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12200 rel
->addend
= (section
->vma
12202 + fixp
->fx_addnumber
12203 + md_pcrel_from (fixp
));
12208 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12209 if (rel
->howto
== NULL
)
12211 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12212 _("cannot represent relocation type %s"),
12213 bfd_get_reloc_code_name (code
));
12214 /* Set howto to a garbage value so that we can keep going. */
12215 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12216 gas_assert (rel
->howto
!= NULL
);
12222 #include "tc-i386-intel.c"
12225 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12227 int saved_naked_reg
;
12228 char saved_register_dot
;
12230 saved_naked_reg
= allow_naked_reg
;
12231 allow_naked_reg
= 1;
12232 saved_register_dot
= register_chars
['.'];
12233 register_chars
['.'] = '.';
12234 allow_pseudo_reg
= 1;
12235 expression_and_evaluate (exp
);
12236 allow_pseudo_reg
= 0;
12237 register_chars
['.'] = saved_register_dot
;
12238 allow_naked_reg
= saved_naked_reg
;
12240 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12242 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12244 exp
->X_op
= O_constant
;
12245 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12246 .dw2_regnum
[flag_code
>> 1];
12249 exp
->X_op
= O_illegal
;
12254 tc_x86_frame_initial_instructions (void)
12256 static unsigned int sp_regno
[2];
12258 if (!sp_regno
[flag_code
>> 1])
12260 char *saved_input
= input_line_pointer
;
12261 char sp
[][4] = {"esp", "rsp"};
12264 input_line_pointer
= sp
[flag_code
>> 1];
12265 tc_x86_parse_to_dw2regnum (&exp
);
12266 gas_assert (exp
.X_op
== O_constant
);
12267 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12268 input_line_pointer
= saved_input
;
12271 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12272 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12276 x86_dwarf2_addr_size (void)
12278 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12279 if (x86_elf_abi
== X86_64_X32_ABI
)
12282 return bfd_arch_bits_per_address (stdoutput
) / 8;
12286 i386_elf_section_type (const char *str
, size_t len
)
12288 if (flag_code
== CODE_64BIT
12289 && len
== sizeof ("unwind") - 1
12290 && strncmp (str
, "unwind", 6) == 0)
12291 return SHT_X86_64_UNWIND
;
12298 i386_solaris_fix_up_eh_frame (segT sec
)
12300 if (flag_code
== CODE_64BIT
)
12301 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12307 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12311 exp
.X_op
= O_secrel
;
12312 exp
.X_add_symbol
= symbol
;
12313 exp
.X_add_number
= 0;
12314 emit_expr (&exp
, size
);
12318 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12319 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12322 x86_64_section_letter (int letter
, const char **ptr_msg
)
12324 if (flag_code
== CODE_64BIT
)
12327 return SHF_X86_64_LARGE
;
12329 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12332 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12337 x86_64_section_word (char *str
, size_t len
)
12339 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12340 return SHF_X86_64_LARGE
;
12346 handle_large_common (int small ATTRIBUTE_UNUSED
)
12348 if (flag_code
!= CODE_64BIT
)
12350 s_comm_internal (0, elf_common_parse
);
12351 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12355 static segT lbss_section
;
12356 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12357 asection
*saved_bss_section
= bss_section
;
12359 if (lbss_section
== NULL
)
12361 flagword applicable
;
12362 segT seg
= now_seg
;
12363 subsegT subseg
= now_subseg
;
12365 /* The .lbss section is for local .largecomm symbols. */
12366 lbss_section
= subseg_new (".lbss", 0);
12367 applicable
= bfd_applicable_section_flags (stdoutput
);
12368 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
12369 seg_info (lbss_section
)->bss
= 1;
12371 subseg_set (seg
, subseg
);
12374 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12375 bss_section
= lbss_section
;
12377 s_comm_internal (0, elf_common_parse
);
12379 elf_com_section_ptr
= saved_com_section_ptr
;
12380 bss_section
= saved_bss_section
;
12383 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */