1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 static void set_code_flag (int);
59 static void set_16bit_gcc_code_flag (int);
60 static void set_intel_syntax (int);
61 static void set_intel_mnemonic (int);
62 static void set_allow_index_reg (int);
63 static void set_cpu_arch (int);
65 static void pe_directive_secrel (int);
67 static void signed_cons (int);
68 static char *output_invalid (int c
);
69 static int i386_att_operand (char *);
70 static int i386_intel_operand (char *, int);
71 static const reg_entry
*parse_register (char *, char **);
72 static char *parse_insn (char *, char *);
73 static char *parse_operands (char *, const char *);
74 static void swap_operands (void);
75 static void swap_2_operands (int, int);
76 static void optimize_imm (void);
77 static void optimize_disp (void);
78 static int match_template (void);
79 static int check_string (void);
80 static int process_suffix (void);
81 static int check_byte_reg (void);
82 static int check_long_reg (void);
83 static int check_qword_reg (void);
84 static int check_word_reg (void);
85 static int finalize_imm (void);
86 static void process_drex (void);
87 static int process_operands (void);
88 static const seg_entry
*build_modrm_byte (void);
89 static void output_insn (void);
90 static void output_imm (fragS
*, offsetT
);
91 static void output_disp (fragS
*, offsetT
);
93 static void s_bss (int);
95 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
96 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
99 static const char *default_arch
= DEFAULT_ARCH
;
101 /* 'md_assemble ()' gathers together information and puts it into a
108 const reg_entry
*regs
;
113 /* TM holds the template for the insn were currently assembling. */
116 /* SUFFIX holds the instruction size suffix for byte, word, dword
117 or qword, if given. */
120 /* OPERANDS gives the number of given operands. */
121 unsigned int operands
;
123 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
124 of given register, displacement, memory operands and immediate
126 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
128 /* TYPES [i] is the type (see above #defines) which tells us how to
129 use OP[i] for the corresponding operand. */
130 i386_operand_type types
[MAX_OPERANDS
];
132 /* Displacement expression, immediate expression, or register for each
134 union i386_op op
[MAX_OPERANDS
];
136 /* Flags for operands. */
137 unsigned int flags
[MAX_OPERANDS
];
138 #define Operand_PCrel 1
140 /* Relocation type for operand */
141 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
143 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
144 the base index byte below. */
145 const reg_entry
*base_reg
;
146 const reg_entry
*index_reg
;
147 unsigned int log2_scale_factor
;
149 /* SEG gives the seg_entries of this insn. They are zero unless
150 explicit segment overrides are given. */
151 const seg_entry
*seg
[2];
153 /* PREFIX holds all the given prefix opcodes (usually null).
154 PREFIXES is the number of prefix opcodes. */
155 unsigned int prefixes
;
156 unsigned char prefix
[MAX_PREFIXES
];
158 /* RM and SIB are the modrm byte and the sib byte where the
159 addressing modes of this insn are encoded. DREX is the byte
160 added by the SSE5 instructions. */
168 typedef struct _i386_insn i386_insn
;
170 /* List of chars besides those in app.c:symbol_chars that can start an
171 operand. Used to prevent the scrubber eating vital white-space. */
172 const char extra_symbol_chars
[] = "*%-(["
181 #if (defined (TE_I386AIX) \
182 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
183 && !defined (TE_GNU) \
184 && !defined (TE_LINUX) \
185 && !defined (TE_NETWARE) \
186 && !defined (TE_FreeBSD) \
187 && !defined (TE_NetBSD)))
188 /* This array holds the chars that always start a comment. If the
189 pre-processor is disabled, these aren't very useful. The option
190 --divide will remove '/' from this list. */
191 const char *i386_comment_chars
= "#/";
192 #define SVR4_COMMENT_CHARS 1
193 #define PREFIX_SEPARATOR '\\'
196 const char *i386_comment_chars
= "#";
197 #define PREFIX_SEPARATOR '/'
200 /* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
204 first line of the input file. This is because the compiler outputs
205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
207 '/' isn't otherwise defined. */
208 const char line_comment_chars
[] = "#/";
210 const char line_separator_chars
[] = ";";
212 /* Chars that can be used to separate mant from exp in floating point
214 const char EXP_CHARS
[] = "eE";
216 /* Chars that mean this number is a floating point constant
219 const char FLT_CHARS
[] = "fFdDxX";
221 /* Tables for lexical analysis. */
222 static char mnemonic_chars
[256];
223 static char register_chars
[256];
224 static char operand_chars
[256];
225 static char identifier_chars
[256];
226 static char digit_chars
[256];
228 /* Lexical macros. */
229 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
230 #define is_operand_char(x) (operand_chars[(unsigned char) x])
231 #define is_register_char(x) (register_chars[(unsigned char) x])
232 #define is_space_char(x) ((x) == ' ')
233 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
234 #define is_digit_char(x) (digit_chars[(unsigned char) x])
236 /* All non-digit non-letter characters that may occur in an operand. */
237 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
239 /* md_assemble() always leaves the strings it's passed unaltered. To
240 effect this we maintain a stack of saved characters that we've smashed
241 with '\0's (indicating end of strings for various sub-fields of the
242 assembler instruction). */
243 static char save_stack
[32];
244 static char *save_stack_p
;
245 #define END_STRING_AND_SAVE(s) \
246 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
247 #define RESTORE_END_STRING(s) \
248 do { *(s) = *--save_stack_p; } while (0)
250 /* The instruction we're assembling. */
253 /* Possible templates for current insn. */
254 static const templates
*current_templates
;
256 /* Per instruction expressionS buffers: max displacements & immediates. */
257 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
258 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
260 /* Current operand we are working on. */
261 static int this_operand
;
263 /* We support four different modes. FLAG_CODE variable is used to distinguish
271 static enum flag_code flag_code
;
272 static unsigned int object_64bit
;
273 static int use_rela_relocations
= 0;
275 /* The names used to print error messages. */
276 static const char *flag_code_names
[] =
283 /* 1 for intel syntax,
285 static int intel_syntax
= 0;
287 /* 1 for intel mnemonic,
288 0 if att mnemonic. */
289 static int intel_mnemonic
= !SYSV386_COMPAT
;
291 /* 1 if support old (<= 2.8.1) versions of gcc. */
292 static int old_gcc
= OLDGCC_COMPAT
;
294 /* 1 if register prefix % not required. */
295 static int allow_naked_reg
= 0;
297 /* 1 if pseudo index register, eiz/riz, is allowed . */
298 static int allow_index_reg
= 0;
300 /* Register prefix used for error message. */
301 static const char *register_prefix
= "%";
303 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306 static char stackop_size
= '\0';
308 /* Non-zero to optimize code alignment. */
309 int optimize_align_code
= 1;
311 /* Non-zero to quieten some warnings. */
312 static int quiet_warnings
= 0;
315 static const char *cpu_arch_name
= NULL
;
316 static const char *cpu_sub_arch_name
= NULL
;
318 /* CPU feature flags. */
319 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
321 /* If we have selected a cpu we are generating instructions for. */
322 static int cpu_arch_tune_set
= 0;
324 /* Cpu we are generating instructions for. */
325 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
327 /* CPU feature flags of cpu we are generating instructions for. */
328 static i386_cpu_flags cpu_arch_tune_flags
;
330 /* CPU instruction set architecture used. */
331 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
333 /* CPU feature flags of instruction set architecture used. */
334 static i386_cpu_flags cpu_arch_isa_flags
;
336 /* If set, conditional jumps are not automatically promoted to handle
337 larger than a byte offset. */
338 static unsigned int no_cond_jump_promotion
= 0;
340 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
341 static symbolS
*GOT_symbol
;
343 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
344 unsigned int x86_dwarf2_return_column
;
346 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
347 int x86_cie_data_alignment
;
349 /* Interface to relax_segment.
350 There are 3 major relax states for 386 jump insns because the
351 different types of jumps add different sizes to frags when we're
352 figuring out what sort of jump to choose to reach a given label. */
355 #define UNCOND_JUMP 0
357 #define COND_JUMP86 2
362 #define SMALL16 (SMALL | CODE16)
364 #define BIG16 (BIG | CODE16)
368 #define INLINE __inline__
374 #define ENCODE_RELAX_STATE(type, size) \
375 ((relax_substateT) (((type) << 2) | (size)))
376 #define TYPE_FROM_RELAX_STATE(s) \
378 #define DISP_SIZE_FROM_RELAX_STATE(s) \
379 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
381 /* This table is used by relax_frag to promote short jumps to long
382 ones where necessary. SMALL (short) jumps may be promoted to BIG
383 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
384 don't allow a short jump in a 32 bit code segment to be promoted to
385 a 16 bit offset jump because it's slower (requires data size
386 prefix), and doesn't work, unless the destination is in the bottom
387 64k of the code segment (The top 16 bits of eip are zeroed). */
389 const relax_typeS md_relax_table
[] =
392 1) most positive reach of this state,
393 2) most negative reach of this state,
394 3) how many bytes this mode will have in the variable part of the frag
395 4) which index into the table to try if we can't fit into this one. */
397 /* UNCOND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
400 /* dword jmp adds 4 bytes to frag:
401 0 extra opcode bytes, 4 displacement bytes. */
403 /* word jmp adds 2 byte2 to frag:
404 0 extra opcode bytes, 2 displacement bytes. */
407 /* COND_JUMP states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
413 /* word conditionals add 3 bytes to frag:
414 1 extra opcode byte, 2 displacement bytes. */
417 /* COND_JUMP86 states. */
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
419 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
420 /* dword conditionals adds 5 bytes to frag:
421 1 extra opcode byte, 4 displacement bytes. */
423 /* word conditionals add 4 bytes to frag:
424 1 displacement byte and a 3 byte long branch insn. */
428 static const arch_entry cpu_arch
[] =
430 {"generic32", PROCESSOR_GENERIC32
,
431 CPU_GENERIC32_FLAGS
},
432 {"generic64", PROCESSOR_GENERIC64
,
433 CPU_GENERIC64_FLAGS
},
434 {"i8086", PROCESSOR_UNKNOWN
,
436 {"i186", PROCESSOR_UNKNOWN
,
438 {"i286", PROCESSOR_UNKNOWN
,
440 {"i386", PROCESSOR_I386
,
442 {"i486", PROCESSOR_I486
,
444 {"i586", PROCESSOR_PENTIUM
,
446 {"i686", PROCESSOR_PENTIUMPRO
,
448 {"pentium", PROCESSOR_PENTIUM
,
450 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
452 {"pentiumii", PROCESSOR_PENTIUMPRO
,
454 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
456 {"pentium4", PROCESSOR_PENTIUM4
,
458 {"prescott", PROCESSOR_NOCONA
,
460 {"nocona", PROCESSOR_NOCONA
,
462 {"yonah", PROCESSOR_CORE
,
464 {"core", PROCESSOR_CORE
,
466 {"merom", PROCESSOR_CORE2
,
468 {"core2", PROCESSOR_CORE2
,
472 {"k6_2", PROCESSOR_K6
,
474 {"athlon", PROCESSOR_ATHLON
,
476 {"sledgehammer", PROCESSOR_K8
,
478 {"opteron", PROCESSOR_K8
,
482 {"amdfam10", PROCESSOR_AMDFAM10
,
483 CPU_AMDFAM10_FLAGS
},
484 {".mmx", PROCESSOR_UNKNOWN
,
486 {".sse", PROCESSOR_UNKNOWN
,
488 {".sse2", PROCESSOR_UNKNOWN
,
490 {".sse3", PROCESSOR_UNKNOWN
,
492 {".ssse3", PROCESSOR_UNKNOWN
,
494 {".sse4.1", PROCESSOR_UNKNOWN
,
496 {".sse4.2", PROCESSOR_UNKNOWN
,
498 {".sse4", PROCESSOR_UNKNOWN
,
500 {".3dnow", PROCESSOR_UNKNOWN
,
502 {".3dnowa", PROCESSOR_UNKNOWN
,
504 {".padlock", PROCESSOR_UNKNOWN
,
506 {".pacifica", PROCESSOR_UNKNOWN
,
508 {".svme", PROCESSOR_UNKNOWN
,
510 {".sse4a", PROCESSOR_UNKNOWN
,
512 {".abm", PROCESSOR_UNKNOWN
,
514 {".sse5", PROCESSOR_UNKNOWN
,
518 const pseudo_typeS md_pseudo_table
[] =
520 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes
, 0},
523 {"align", s_align_ptwo
, 0},
525 {"arch", set_cpu_arch
, 0},
529 {"ffloat", float_cons
, 'f'},
530 {"dfloat", float_cons
, 'd'},
531 {"tfloat", float_cons
, 'x'},
533 {"slong", signed_cons
, 4},
534 {"noopt", s_ignore
, 0},
535 {"optim", s_ignore
, 0},
536 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
537 {"code16", set_code_flag
, CODE_16BIT
},
538 {"code32", set_code_flag
, CODE_32BIT
},
539 {"code64", set_code_flag
, CODE_64BIT
},
540 {"intel_syntax", set_intel_syntax
, 1},
541 {"att_syntax", set_intel_syntax
, 0},
542 {"intel_mnemonic", set_intel_mnemonic
, 1},
543 {"att_mnemonic", set_intel_mnemonic
, 0},
544 {"allow_index_reg", set_allow_index_reg
, 1},
545 {"disallow_index_reg", set_allow_index_reg
, 0},
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common
, 0},
549 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
550 {"loc", dwarf2_directive_loc
, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
554 {"secrel32", pe_directive_secrel
, 0},
559 /* For interface with expression (). */
560 extern char *input_line_pointer
;
562 /* Hash table for instruction mnemonic lookup. */
563 static struct hash_control
*op_hash
;
565 /* Hash table for register lookup. */
566 static struct hash_control
*reg_hash
;
569 i386_align_code (fragS
*fragP
, int count
)
571 /* Various efficient no-op patterns for aligning code labels.
572 Note: Don't try to assemble the instructions in the comments.
573 0L and 0w are not legal. */
574 static const char f32_1
[] =
576 static const char f32_2
[] =
577 {0x66,0x90}; /* xchg %ax,%ax */
578 static const char f32_3
[] =
579 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
580 static const char f32_4
[] =
581 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
582 static const char f32_5
[] =
584 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
585 static const char f32_6
[] =
586 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
587 static const char f32_7
[] =
588 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
589 static const char f32_8
[] =
591 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
592 static const char f32_9
[] =
593 {0x89,0xf6, /* movl %esi,%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_10
[] =
596 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_11
[] =
599 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_12
[] =
602 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
603 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
604 static const char f32_13
[] =
605 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
606 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
607 static const char f32_14
[] =
608 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
609 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
610 static const char f16_3
[] =
611 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
612 static const char f16_4
[] =
613 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
614 static const char f16_5
[] =
616 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_6
[] =
618 {0x89,0xf6, /* mov %si,%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char f16_7
[] =
621 {0x8d,0x74,0x00, /* lea 0(%si),%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_8
[] =
624 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
626 static const char jump_31
[] =
627 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
628 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
631 static const char *const f32_patt
[] = {
632 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
633 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
635 static const char *const f16_patt
[] = {
636 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
639 static const char alt_3
[] =
641 /* nopl 0(%[re]ax) */
642 static const char alt_4
[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5
[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6
[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7
[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8
[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9
[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10
[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11
[] =
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12
[] =
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13
[] =
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14
[] =
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15
[] =
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11
[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12
[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
719 static const char alt_short_13
[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
724 static const char alt_short_14
[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15
[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt
[] = {
733 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
734 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
735 alt_short_14
, alt_short_15
737 static const char *const alt_long_patt
[] = {
738 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
739 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
740 alt_long_14
, alt_long_15
743 /* Only align for at least a positive non-zero boundary. */
744 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
750 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
751 PROCESSOR_GENERIC32, f32_patt will be used.
752 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
753 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
754 alt_long_patt will be used.
755 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
756 PROCESSOR_AMDFAM10, alt_short_patt will be used.
758 When -mtune= isn't used, alt_long_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
762 When -march= or .arch is used, we can't use anything beyond
763 cpu_arch_isa_flags. */
765 if (flag_code
== CODE_16BIT
)
769 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
771 /* Adjust jump offset. */
772 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
775 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
776 f16_patt
[count
- 1], count
);
780 const char *const *patt
= NULL
;
782 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
784 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
785 switch (cpu_arch_tune
)
787 case PROCESSOR_UNKNOWN
:
788 /* We use cpu_arch_isa_flags to check if we SHOULD
789 optimize for Cpu686. */
790 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
791 patt
= alt_long_patt
;
795 case PROCESSOR_PENTIUMPRO
:
796 case PROCESSOR_PENTIUM4
:
797 case PROCESSOR_NOCONA
:
799 case PROCESSOR_CORE2
:
800 case PROCESSOR_GENERIC64
:
801 patt
= alt_long_patt
;
804 case PROCESSOR_ATHLON
:
806 case PROCESSOR_AMDFAM10
:
807 patt
= alt_short_patt
;
811 case PROCESSOR_PENTIUM
:
812 case PROCESSOR_GENERIC32
:
819 switch (cpu_arch_tune
)
821 case PROCESSOR_UNKNOWN
:
822 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
823 PROCESSOR_UNKNOWN. */
829 case PROCESSOR_PENTIUM
:
831 case PROCESSOR_ATHLON
:
833 case PROCESSOR_AMDFAM10
:
834 case PROCESSOR_GENERIC32
:
835 /* We use cpu_arch_isa_flags to check if we CAN optimize
837 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
838 patt
= alt_short_patt
;
842 case PROCESSOR_PENTIUMPRO
:
843 case PROCESSOR_PENTIUM4
:
844 case PROCESSOR_NOCONA
:
846 case PROCESSOR_CORE2
:
847 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
848 patt
= alt_long_patt
;
852 case PROCESSOR_GENERIC64
:
853 patt
= alt_long_patt
;
858 if (patt
== f32_patt
)
860 /* If the padding is less than 15 bytes, we use the normal
861 ones. Otherwise, we use a jump instruction and adjust
864 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
865 patt
[count
- 1], count
);
868 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
870 /* Adjust jump offset. */
871 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
876 /* Maximum length of an instruction is 15 byte. If the
877 padding is greater than 15 bytes and we don't use jump,
878 we have to break it into smaller pieces. */
883 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
888 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
889 patt
[padding
- 1], padding
);
892 fragP
->fr_var
= count
;
896 uints_all_zero (const unsigned int *x
, unsigned int size
)
914 uints_set (unsigned int *x
, unsigned int v
, unsigned int size
)
931 uints_equal (const unsigned int *x
, const unsigned int *y
,
943 return x
[0] == y
[0];
950 #define UINTS_ALL_ZERO(x) \
951 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
952 #define UINTS_SET(x, v) \
953 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
954 #define UINTS_CLEAR(x) \
955 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
956 #define UINTS_EQUAL(x, y) \
957 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
960 cpu_flags_check_cpu64 (i386_cpu_flags f
)
962 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
963 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
966 static INLINE i386_cpu_flags
967 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
969 switch (ARRAY_SIZE (x
.array
))
972 x
.array
[2] &= y
.array
[2];
974 x
.array
[1] &= y
.array
[1];
976 x
.array
[0] &= y
.array
[0];
984 static INLINE i386_cpu_flags
985 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
987 switch (ARRAY_SIZE (x
.array
))
990 x
.array
[2] |= y
.array
[2];
992 x
.array
[1] |= y
.array
[1];
994 x
.array
[0] |= y
.array
[0];
1002 /* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1003 1 if compatible with arch, 0 if there is no match. */
1006 cpu_flags_match (i386_cpu_flags x
)
1008 int overlap
= cpu_flags_check_cpu64 (x
) ? 2 : 0;
1010 x
.bitfield
.cpu64
= 0;
1011 x
.bitfield
.cpuno64
= 0;
1013 if (UINTS_ALL_ZERO (x
))
1017 i386_cpu_flags cpu
= cpu_arch_flags
;
1019 cpu
.bitfield
.cpu64
= 0;
1020 cpu
.bitfield
.cpuno64
= 0;
1021 cpu
= cpu_flags_and (x
, cpu
);
1022 overlap
|= UINTS_ALL_ZERO (cpu
) ? 0 : 1;
1027 static INLINE i386_operand_type
1028 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1030 switch (ARRAY_SIZE (x
.array
))
1033 x
.array
[2] &= y
.array
[2];
1035 x
.array
[1] &= y
.array
[1];
1037 x
.array
[0] &= y
.array
[0];
1045 static INLINE i386_operand_type
1046 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1048 switch (ARRAY_SIZE (x
.array
))
1051 x
.array
[2] |= y
.array
[2];
1053 x
.array
[1] |= y
.array
[1];
1055 x
.array
[0] |= y
.array
[0];
1063 static INLINE i386_operand_type
1064 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1066 switch (ARRAY_SIZE (x
.array
))
1069 x
.array
[2] ^= y
.array
[2];
1071 x
.array
[1] ^= y
.array
[1];
1073 x
.array
[0] ^= y
.array
[0];
1081 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1082 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1083 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1084 static const i386_operand_type reg16_inoutportreg
1085 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1086 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1087 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1088 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1089 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1090 static const i386_operand_type anydisp
1091 = OPERAND_TYPE_ANYDISP
;
1092 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1093 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1094 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1095 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1096 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1097 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1098 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1099 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1100 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1101 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1112 operand_type_check (i386_operand_type t
, enum operand_type c
)
1117 return (t
.bitfield
.reg8
1120 || t
.bitfield
.reg64
);
1123 return (t
.bitfield
.imm8
1127 || t
.bitfield
.imm32s
1128 || t
.bitfield
.imm64
);
1131 return (t
.bitfield
.disp8
1132 || t
.bitfield
.disp16
1133 || t
.bitfield
.disp32
1134 || t
.bitfield
.disp32s
1135 || t
.bitfield
.disp64
);
1138 return (t
.bitfield
.disp8
1139 || t
.bitfield
.disp16
1140 || t
.bitfield
.disp32
1141 || t
.bitfield
.disp32s
1142 || t
.bitfield
.disp64
1143 || t
.bitfield
.baseindex
);
1150 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1151 operand J for instruction template T. */
1154 match_reg_size (const template *t
, unsigned int j
)
1156 return !((i
.types
[j
].bitfield
.byte
1157 && !t
->operand_types
[j
].bitfield
.byte
)
1158 || (i
.types
[j
].bitfield
.word
1159 && !t
->operand_types
[j
].bitfield
.word
)
1160 || (i
.types
[j
].bitfield
.dword
1161 && !t
->operand_types
[j
].bitfield
.dword
)
1162 || (i
.types
[j
].bitfield
.qword
1163 && !t
->operand_types
[j
].bitfield
.qword
));
1166 /* Return 1 if there is no conflict in any size on operand J for
1167 instruction template T. */
1170 match_mem_size (const template *t
, unsigned int j
)
1172 return (match_reg_size (t
, j
)
1173 && !((i
.types
[j
].bitfield
.unspecified
1174 && !t
->operand_types
[j
].bitfield
.unspecified
)
1175 || (i
.types
[j
].bitfield
.fword
1176 && !t
->operand_types
[j
].bitfield
.fword
)
1177 || (i
.types
[j
].bitfield
.tbyte
1178 && !t
->operand_types
[j
].bitfield
.tbyte
)
1179 || (i
.types
[j
].bitfield
.xmmword
1180 && !t
->operand_types
[j
].bitfield
.xmmword
)));
1183 /* Return 1 if there is no size conflict on any operands for
1184 instruction template T. */
1187 operand_size_match (const template *t
)
1192 /* Don't check jump instructions. */
1193 if (t
->opcode_modifier
.jump
1194 || t
->opcode_modifier
.jumpbyte
1195 || t
->opcode_modifier
.jumpdword
1196 || t
->opcode_modifier
.jumpintersegment
)
1199 /* Check memory and accumulator operand size. */
1200 for (j
= 0; j
< i
.operands
; j
++)
1202 if (t
->operand_types
[j
].bitfield
.anysize
)
1205 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1211 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1219 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1222 /* Check reverse. */
1223 assert (i
.operands
== 2);
1226 for (j
= 0; j
< 2; j
++)
1228 if (t
->operand_types
[j
].bitfield
.acc
1229 && !match_reg_size (t
, j
? 0 : 1))
1235 if (i
.types
[j
].bitfield
.mem
1236 && !match_mem_size (t
, j
? 0 : 1))
1247 operand_type_match (i386_operand_type overlap
,
1248 i386_operand_type given
)
1250 i386_operand_type temp
= overlap
;
1252 temp
.bitfield
.jumpabsolute
= 0;
1253 temp
.bitfield
.unspecified
= 0;
1254 temp
.bitfield
.byte
= 0;
1255 temp
.bitfield
.word
= 0;
1256 temp
.bitfield
.dword
= 0;
1257 temp
.bitfield
.fword
= 0;
1258 temp
.bitfield
.qword
= 0;
1259 temp
.bitfield
.tbyte
= 0;
1260 temp
.bitfield
.xmmword
= 0;
1261 if (UINTS_ALL_ZERO (temp
))
1264 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1265 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1268 /* If given types g0 and g1 are registers they must be of the same type
1269 unless the expected operand type register overlap is null.
1270 Note that Acc in a template matches every size of reg. */
1273 operand_type_register_match (i386_operand_type m0
,
1274 i386_operand_type g0
,
1275 i386_operand_type t0
,
1276 i386_operand_type m1
,
1277 i386_operand_type g1
,
1278 i386_operand_type t1
)
1280 if (!operand_type_check (g0
, reg
))
1283 if (!operand_type_check (g1
, reg
))
1286 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1287 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1288 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1289 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1292 if (m0
.bitfield
.acc
)
1294 t0
.bitfield
.reg8
= 1;
1295 t0
.bitfield
.reg16
= 1;
1296 t0
.bitfield
.reg32
= 1;
1297 t0
.bitfield
.reg64
= 1;
1300 if (m1
.bitfield
.acc
)
1302 t1
.bitfield
.reg8
= 1;
1303 t1
.bitfield
.reg16
= 1;
1304 t1
.bitfield
.reg32
= 1;
1305 t1
.bitfield
.reg64
= 1;
1308 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1309 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1310 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1311 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1314 static INLINE
unsigned int
1315 mode_from_disp_size (i386_operand_type t
)
1317 if (t
.bitfield
.disp8
)
1319 else if (t
.bitfield
.disp16
1320 || t
.bitfield
.disp32
1321 || t
.bitfield
.disp32s
)
1328 fits_in_signed_byte (offsetT num
)
1330 return (num
>= -128) && (num
<= 127);
1334 fits_in_unsigned_byte (offsetT num
)
1336 return (num
& 0xff) == num
;
1340 fits_in_unsigned_word (offsetT num
)
1342 return (num
& 0xffff) == num
;
1346 fits_in_signed_word (offsetT num
)
1348 return (-32768 <= num
) && (num
<= 32767);
1352 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1357 return (!(((offsetT
) -1 << 31) & num
)
1358 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1360 } /* fits_in_signed_long() */
1363 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1368 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1370 } /* fits_in_unsigned_long() */
1372 static i386_operand_type
1373 smallest_imm_type (offsetT num
)
1375 i386_operand_type t
;
1378 t
.bitfield
.imm64
= 1;
1380 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1382 /* This code is disabled on the 486 because all the Imm1 forms
1383 in the opcode table are slower on the i486. They're the
1384 versions with the implicitly specified single-position
1385 displacement, which has another syntax if you really want to
1387 t
.bitfield
.imm1
= 1;
1388 t
.bitfield
.imm8
= 1;
1389 t
.bitfield
.imm8s
= 1;
1390 t
.bitfield
.imm16
= 1;
1391 t
.bitfield
.imm32
= 1;
1392 t
.bitfield
.imm32s
= 1;
1394 else if (fits_in_signed_byte (num
))
1396 t
.bitfield
.imm8
= 1;
1397 t
.bitfield
.imm8s
= 1;
1398 t
.bitfield
.imm16
= 1;
1399 t
.bitfield
.imm32
= 1;
1400 t
.bitfield
.imm32s
= 1;
1402 else if (fits_in_unsigned_byte (num
))
1404 t
.bitfield
.imm8
= 1;
1405 t
.bitfield
.imm16
= 1;
1406 t
.bitfield
.imm32
= 1;
1407 t
.bitfield
.imm32s
= 1;
1409 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1411 t
.bitfield
.imm16
= 1;
1412 t
.bitfield
.imm32
= 1;
1413 t
.bitfield
.imm32s
= 1;
1415 else if (fits_in_signed_long (num
))
1417 t
.bitfield
.imm32
= 1;
1418 t
.bitfield
.imm32s
= 1;
1420 else if (fits_in_unsigned_long (num
))
1421 t
.bitfield
.imm32
= 1;
1427 offset_in_range (offsetT val
, int size
)
1433 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1434 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1435 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1437 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1442 /* If BFD64, sign extend val. */
1443 if (!use_rela_relocations
)
1444 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1445 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1447 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1449 char buf1
[40], buf2
[40];
1451 sprint_value (buf1
, val
);
1452 sprint_value (buf2
, val
& mask
);
1453 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1458 /* Returns 0 if attempting to add a prefix where one from the same
1459 class already exists, 1 if non rep/repne added, 2 if rep/repne
1462 add_prefix (unsigned int prefix
)
1467 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1468 && flag_code
== CODE_64BIT
)
1470 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1471 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1472 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1483 case CS_PREFIX_OPCODE
:
1484 case DS_PREFIX_OPCODE
:
1485 case ES_PREFIX_OPCODE
:
1486 case FS_PREFIX_OPCODE
:
1487 case GS_PREFIX_OPCODE
:
1488 case SS_PREFIX_OPCODE
:
1492 case REPNE_PREFIX_OPCODE
:
1493 case REPE_PREFIX_OPCODE
:
1496 case LOCK_PREFIX_OPCODE
:
1504 case ADDR_PREFIX_OPCODE
:
1508 case DATA_PREFIX_OPCODE
:
1512 if (i
.prefix
[q
] != 0)
1520 i
.prefix
[q
] |= prefix
;
1523 as_bad (_("same type of prefix used twice"));
1529 set_code_flag (int value
)
1532 if (flag_code
== CODE_64BIT
)
1534 cpu_arch_flags
.bitfield
.cpu64
= 1;
1535 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1539 cpu_arch_flags
.bitfield
.cpu64
= 0;
1540 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1542 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1544 as_bad (_("64bit mode not supported on this CPU."));
1546 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1548 as_bad (_("32bit mode not supported on this CPU."));
1550 stackop_size
= '\0';
1554 set_16bit_gcc_code_flag (int new_code_flag
)
1556 flag_code
= new_code_flag
;
1557 if (flag_code
!= CODE_16BIT
)
1559 cpu_arch_flags
.bitfield
.cpu64
= 0;
1560 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1561 stackop_size
= LONG_MNEM_SUFFIX
;
1565 set_intel_syntax (int syntax_flag
)
1567 /* Find out if register prefixing is specified. */
1568 int ask_naked_reg
= 0;
1571 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1573 char *string
= input_line_pointer
;
1574 int e
= get_symbol_end ();
1576 if (strcmp (string
, "prefix") == 0)
1578 else if (strcmp (string
, "noprefix") == 0)
1581 as_bad (_("bad argument to syntax directive."));
1582 *input_line_pointer
= e
;
1584 demand_empty_rest_of_line ();
1586 intel_syntax
= syntax_flag
;
1588 if (ask_naked_reg
== 0)
1589 allow_naked_reg
= (intel_syntax
1590 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1592 allow_naked_reg
= (ask_naked_reg
< 0);
1594 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1595 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1596 register_prefix
= allow_naked_reg
? "" : "%";
1600 set_intel_mnemonic (int mnemonic_flag
)
1602 intel_mnemonic
= mnemonic_flag
;
1606 set_allow_index_reg (int flag
)
1608 allow_index_reg
= flag
;
1612 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1616 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1618 char *string
= input_line_pointer
;
1619 int e
= get_symbol_end ();
1621 i386_cpu_flags flags
;
1623 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1625 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1629 cpu_arch_name
= cpu_arch
[i
].name
;
1630 cpu_sub_arch_name
= NULL
;
1631 cpu_arch_flags
= cpu_arch
[i
].flags
;
1632 if (flag_code
== CODE_64BIT
)
1634 cpu_arch_flags
.bitfield
.cpu64
= 1;
1635 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1639 cpu_arch_flags
.bitfield
.cpu64
= 0;
1640 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1642 cpu_arch_isa
= cpu_arch
[i
].type
;
1643 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1644 if (!cpu_arch_tune_set
)
1646 cpu_arch_tune
= cpu_arch_isa
;
1647 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1652 flags
= cpu_flags_or (cpu_arch_flags
,
1654 if (!UINTS_EQUAL (flags
, cpu_arch_flags
))
1656 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1657 cpu_arch_flags
= flags
;
1659 *input_line_pointer
= e
;
1660 demand_empty_rest_of_line ();
1664 if (i
>= ARRAY_SIZE (cpu_arch
))
1665 as_bad (_("no such architecture: `%s'"), string
);
1667 *input_line_pointer
= e
;
1670 as_bad (_("missing cpu architecture"));
1672 no_cond_jump_promotion
= 0;
1673 if (*input_line_pointer
== ','
1674 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1676 char *string
= ++input_line_pointer
;
1677 int e
= get_symbol_end ();
1679 if (strcmp (string
, "nojumps") == 0)
1680 no_cond_jump_promotion
= 1;
1681 else if (strcmp (string
, "jumps") == 0)
1684 as_bad (_("no such architecture modifier: `%s'"), string
);
1686 *input_line_pointer
= e
;
1689 demand_empty_rest_of_line ();
1695 if (!strcmp (default_arch
, "x86_64"))
1696 return bfd_mach_x86_64
;
1697 else if (!strcmp (default_arch
, "i386"))
1698 return bfd_mach_i386_i386
;
1700 as_fatal (_("Unknown architecture"));
1706 const char *hash_err
;
1708 /* Initialize op_hash hash table. */
1709 op_hash
= hash_new ();
1712 const template *optab
;
1713 templates
*core_optab
;
1715 /* Setup for loop. */
1717 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1718 core_optab
->start
= optab
;
1723 if (optab
->name
== NULL
1724 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1726 /* different name --> ship out current template list;
1727 add to hash table; & begin anew. */
1728 core_optab
->end
= optab
;
1729 hash_err
= hash_insert (op_hash
,
1734 as_fatal (_("Internal Error: Can't hash %s: %s"),
1738 if (optab
->name
== NULL
)
1740 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1741 core_optab
->start
= optab
;
1746 /* Initialize reg_hash hash table. */
1747 reg_hash
= hash_new ();
1749 const reg_entry
*regtab
;
1750 unsigned int regtab_size
= i386_regtab_size
;
1752 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
1754 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1756 as_fatal (_("Internal Error: Can't hash %s: %s"),
1762 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1767 for (c
= 0; c
< 256; c
++)
1772 mnemonic_chars
[c
] = c
;
1773 register_chars
[c
] = c
;
1774 operand_chars
[c
] = c
;
1776 else if (ISLOWER (c
))
1778 mnemonic_chars
[c
] = c
;
1779 register_chars
[c
] = c
;
1780 operand_chars
[c
] = c
;
1782 else if (ISUPPER (c
))
1784 mnemonic_chars
[c
] = TOLOWER (c
);
1785 register_chars
[c
] = mnemonic_chars
[c
];
1786 operand_chars
[c
] = c
;
1789 if (ISALPHA (c
) || ISDIGIT (c
))
1790 identifier_chars
[c
] = c
;
1793 identifier_chars
[c
] = c
;
1794 operand_chars
[c
] = c
;
1799 identifier_chars
['@'] = '@';
1802 identifier_chars
['?'] = '?';
1803 operand_chars
['?'] = '?';
1805 digit_chars
['-'] = '-';
1806 mnemonic_chars
['-'] = '-';
1807 mnemonic_chars
['.'] = '.';
1808 identifier_chars
['_'] = '_';
1809 identifier_chars
['.'] = '.';
1811 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1812 operand_chars
[(unsigned char) *p
] = *p
;
1815 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1818 record_alignment (text_section
, 2);
1819 record_alignment (data_section
, 2);
1820 record_alignment (bss_section
, 2);
1824 if (flag_code
== CODE_64BIT
)
1826 x86_dwarf2_return_column
= 16;
1827 x86_cie_data_alignment
= -8;
1831 x86_dwarf2_return_column
= 8;
1832 x86_cie_data_alignment
= -4;
1837 i386_print_statistics (FILE *file
)
1839 hash_print_statistics (file
, "i386 opcode", op_hash
);
1840 hash_print_statistics (file
, "i386 register", reg_hash
);
1845 /* Debugging routines for md_assemble. */
1846 static void pte (template *);
1847 static void pt (i386_operand_type
);
1848 static void pe (expressionS
*);
1849 static void ps (symbolS
*);
1852 pi (char *line
, i386_insn
*x
)
1856 fprintf (stdout
, "%s: template ", line
);
1858 fprintf (stdout
, " address: base %s index %s scale %x\n",
1859 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1860 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1861 x
->log2_scale_factor
);
1862 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1863 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1864 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1865 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1866 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1867 (x
->rex
& REX_W
) != 0,
1868 (x
->rex
& REX_R
) != 0,
1869 (x
->rex
& REX_X
) != 0,
1870 (x
->rex
& REX_B
) != 0);
1871 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
1872 x
->drex
.reg
, x
->drex
.rex
);
1873 for (i
= 0; i
< x
->operands
; i
++)
1875 fprintf (stdout
, " #%d: ", i
+ 1);
1877 fprintf (stdout
, "\n");
1878 if (x
->types
[i
].bitfield
.reg8
1879 || x
->types
[i
].bitfield
.reg16
1880 || x
->types
[i
].bitfield
.reg32
1881 || x
->types
[i
].bitfield
.reg64
1882 || x
->types
[i
].bitfield
.regmmx
1883 || x
->types
[i
].bitfield
.regxmm
1884 || x
->types
[i
].bitfield
.sreg2
1885 || x
->types
[i
].bitfield
.sreg3
1886 || x
->types
[i
].bitfield
.control
1887 || x
->types
[i
].bitfield
.debug
1888 || x
->types
[i
].bitfield
.test
)
1889 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1890 if (operand_type_check (x
->types
[i
], imm
))
1892 if (operand_type_check (x
->types
[i
], disp
))
1893 pe (x
->op
[i
].disps
);
1901 fprintf (stdout
, " %d operands ", t
->operands
);
1902 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1903 if (t
->extension_opcode
!= None
)
1904 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1905 if (t
->opcode_modifier
.d
)
1906 fprintf (stdout
, "D");
1907 if (t
->opcode_modifier
.w
)
1908 fprintf (stdout
, "W");
1909 fprintf (stdout
, "\n");
1910 for (i
= 0; i
< t
->operands
; i
++)
1912 fprintf (stdout
, " #%d type ", i
+ 1);
1913 pt (t
->operand_types
[i
]);
1914 fprintf (stdout
, "\n");
1921 fprintf (stdout
, " operation %d\n", e
->X_op
);
1922 fprintf (stdout
, " add_number %ld (%lx)\n",
1923 (long) e
->X_add_number
, (long) e
->X_add_number
);
1924 if (e
->X_add_symbol
)
1926 fprintf (stdout
, " add_symbol ");
1927 ps (e
->X_add_symbol
);
1928 fprintf (stdout
, "\n");
1932 fprintf (stdout
, " op_symbol ");
1933 ps (e
->X_op_symbol
);
1934 fprintf (stdout
, "\n");
1941 fprintf (stdout
, "%s type %s%s",
1943 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1944 segment_name (S_GET_SEGMENT (s
)));
1947 static struct type_name
1949 i386_operand_type mask
;
1952 const type_names
[] =
1954 { OPERAND_TYPE_REG8
, "r8" },
1955 { OPERAND_TYPE_REG16
, "r16" },
1956 { OPERAND_TYPE_REG32
, "r32" },
1957 { OPERAND_TYPE_REG64
, "r64" },
1958 { OPERAND_TYPE_IMM8
, "i8" },
1959 { OPERAND_TYPE_IMM8
, "i8s" },
1960 { OPERAND_TYPE_IMM16
, "i16" },
1961 { OPERAND_TYPE_IMM32
, "i32" },
1962 { OPERAND_TYPE_IMM32S
, "i32s" },
1963 { OPERAND_TYPE_IMM64
, "i64" },
1964 { OPERAND_TYPE_IMM1
, "i1" },
1965 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
1966 { OPERAND_TYPE_DISP8
, "d8" },
1967 { OPERAND_TYPE_DISP16
, "d16" },
1968 { OPERAND_TYPE_DISP32
, "d32" },
1969 { OPERAND_TYPE_DISP32S
, "d32s" },
1970 { OPERAND_TYPE_DISP64
, "d64" },
1971 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
1972 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
1973 { OPERAND_TYPE_CONTROL
, "control reg" },
1974 { OPERAND_TYPE_TEST
, "test reg" },
1975 { OPERAND_TYPE_DEBUG
, "debug reg" },
1976 { OPERAND_TYPE_FLOATREG
, "FReg" },
1977 { OPERAND_TYPE_FLOATACC
, "FAcc" },
1978 { OPERAND_TYPE_SREG2
, "SReg2" },
1979 { OPERAND_TYPE_SREG3
, "SReg3" },
1980 { OPERAND_TYPE_ACC
, "Acc" },
1981 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
1982 { OPERAND_TYPE_REGMMX
, "rMMX" },
1983 { OPERAND_TYPE_REGXMM
, "rXMM" },
1984 { OPERAND_TYPE_ESSEG
, "es" },
1988 pt (i386_operand_type t
)
1991 i386_operand_type a
;
1993 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
1995 a
= operand_type_and (t
, type_names
[j
].mask
);
1996 if (!UINTS_ALL_ZERO (a
))
1997 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2002 #endif /* DEBUG386 */
2004 static bfd_reloc_code_real_type
2005 reloc (unsigned int size
,
2008 bfd_reloc_code_real_type other
)
2010 if (other
!= NO_RELOC
)
2012 reloc_howto_type
*reloc
;
2017 case BFD_RELOC_X86_64_GOT32
:
2018 return BFD_RELOC_X86_64_GOT64
;
2020 case BFD_RELOC_X86_64_PLTOFF64
:
2021 return BFD_RELOC_X86_64_PLTOFF64
;
2023 case BFD_RELOC_X86_64_GOTPC32
:
2024 other
= BFD_RELOC_X86_64_GOTPC64
;
2026 case BFD_RELOC_X86_64_GOTPCREL
:
2027 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2029 case BFD_RELOC_X86_64_TPOFF32
:
2030 other
= BFD_RELOC_X86_64_TPOFF64
;
2032 case BFD_RELOC_X86_64_DTPOFF32
:
2033 other
= BFD_RELOC_X86_64_DTPOFF64
;
2039 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2040 if (size
== 4 && flag_code
!= CODE_64BIT
)
2043 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2045 as_bad (_("unknown relocation (%u)"), other
);
2046 else if (size
!= bfd_get_reloc_size (reloc
))
2047 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2048 bfd_get_reloc_size (reloc
),
2050 else if (pcrel
&& !reloc
->pc_relative
)
2051 as_bad (_("non-pc-relative relocation for pc-relative field"));
2052 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2054 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2056 as_bad (_("relocated field and relocation type differ in signedness"));
2065 as_bad (_("there are no unsigned pc-relative relocations"));
2068 case 1: return BFD_RELOC_8_PCREL
;
2069 case 2: return BFD_RELOC_16_PCREL
;
2070 case 4: return BFD_RELOC_32_PCREL
;
2071 case 8: return BFD_RELOC_64_PCREL
;
2073 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2080 case 4: return BFD_RELOC_X86_64_32S
;
2085 case 1: return BFD_RELOC_8
;
2086 case 2: return BFD_RELOC_16
;
2087 case 4: return BFD_RELOC_32
;
2088 case 8: return BFD_RELOC_64
;
2090 as_bad (_("cannot do %s %u byte relocation"),
2091 sign
> 0 ? "signed" : "unsigned", size
);
2095 return BFD_RELOC_NONE
;
2098 /* Here we decide which fixups can be adjusted to make them relative to
2099 the beginning of the section instead of the symbol. Basically we need
2100 to make sure that the dynamic relocations are done correctly, so in
2101 some cases we force the original symbol to be used. */
2104 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2110 /* Don't adjust pc-relative references to merge sections in 64-bit
2112 if (use_rela_relocations
2113 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2117 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2118 and changed later by validate_fix. */
2119 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2120 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2123 /* adjust_reloc_syms doesn't know about the GOT. */
2124 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2125 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2126 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2127 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2128 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2129 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2130 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2131 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2132 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2133 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2134 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2135 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2136 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2137 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2138 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2139 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2140 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2141 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2142 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2143 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2144 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2145 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2146 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2147 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2148 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2149 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2150 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2151 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2158 intel_float_operand (const char *mnemonic
)
2160 /* Note that the value returned is meaningful only for opcodes with (memory)
2161 operands, hence the code here is free to improperly handle opcodes that
2162 have no operands (for better performance and smaller code). */
2164 if (mnemonic
[0] != 'f')
2165 return 0; /* non-math */
2167 switch (mnemonic
[1])
2169 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2170 the fs segment override prefix not currently handled because no
2171 call path can make opcodes without operands get here */
2173 return 2 /* integer op */;
2175 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2176 return 3; /* fldcw/fldenv */
2179 if (mnemonic
[2] != 'o' /* fnop */)
2180 return 3; /* non-waiting control op */
2183 if (mnemonic
[2] == 's')
2184 return 3; /* frstor/frstpm */
2187 if (mnemonic
[2] == 'a')
2188 return 3; /* fsave */
2189 if (mnemonic
[2] == 't')
2191 switch (mnemonic
[3])
2193 case 'c': /* fstcw */
2194 case 'd': /* fstdw */
2195 case 'e': /* fstenv */
2196 case 's': /* fsts[gw] */
2202 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2203 return 0; /* fxsave/fxrstor are not really math ops */
2210 /* This is the guts of the machine-dependent assembler. LINE points to a
2211 machine dependent instruction. This function is supposed to emit
2212 the frags/bytes it assembles to. */
2219 char mnemonic
[MAX_MNEM_SIZE
];
2221 /* Initialize globals. */
2222 memset (&i
, '\0', sizeof (i
));
2223 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2224 i
.reloc
[j
] = NO_RELOC
;
2225 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2226 memset (im_expressions
, '\0', sizeof (im_expressions
));
2227 save_stack_p
= save_stack
;
2229 /* First parse an instruction mnemonic & call i386_operand for the operands.
2230 We assume that the scrubber has arranged it so that line[0] is the valid
2231 start of a (possibly prefixed) mnemonic. */
2233 line
= parse_insn (line
, mnemonic
);
2237 line
= parse_operands (line
, mnemonic
);
2241 /* Now we've parsed the mnemonic into a set of templates, and have the
2242 operands at hand. */
2244 /* All intel opcodes have reversed operands except for "bound" and
2245 "enter". We also don't reverse intersegment "jmp" and "call"
2246 instructions with 2 immediate operands so that the immediate segment
2247 precedes the offset, as it does when in AT&T mode. */
2250 && (strcmp (mnemonic
, "bound") != 0)
2251 && (strcmp (mnemonic
, "invlpga") != 0)
2252 && !(operand_type_check (i
.types
[0], imm
)
2253 && operand_type_check (i
.types
[1], imm
)))
2256 /* The order of the immediates should be reversed
2257 for 2 immediates extrq and insertq instructions */
2258 if (i
.imm_operands
== 2
2259 && (strcmp (mnemonic
, "extrq") == 0
2260 || strcmp (mnemonic
, "insertq") == 0))
2261 swap_2_operands (0, 1);
2266 /* Don't optimize displacement for movabs since it only takes 64bit
2269 && (flag_code
!= CODE_64BIT
2270 || strcmp (mnemonic
, "movabs") != 0))
2273 /* Next, we find a template that matches the given insn,
2274 making sure the overlap of the given operands types is consistent
2275 with the template operand types. */
2277 if (!match_template ())
2282 /* Zap movzx and movsx suffix. The suffix may have been set from
2283 "word ptr" or "byte ptr" on the source operand, but we'll use
2284 the suffix later to choose the destination register. */
2285 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2287 if (i
.reg_operands
< 2
2289 && (!i
.tm
.opcode_modifier
.no_bsuf
2290 || !i
.tm
.opcode_modifier
.no_wsuf
2291 || !i
.tm
.opcode_modifier
.no_lsuf
2292 || !i
.tm
.opcode_modifier
.no_ssuf
2293 || !i
.tm
.opcode_modifier
.no_ldsuf
2294 || !i
.tm
.opcode_modifier
.no_qsuf
))
2295 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2301 if (i
.tm
.opcode_modifier
.fwait
)
2302 if (!add_prefix (FWAIT_OPCODE
))
2305 /* Check string instruction segment overrides. */
2306 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2308 if (!check_string ())
2312 if (!process_suffix ())
2315 /* Make still unresolved immediate matches conform to size of immediate
2316 given in i.suffix. */
2317 if (!finalize_imm ())
2320 if (i
.types
[0].bitfield
.imm1
)
2321 i
.imm_operands
= 0; /* kludge for shift insns. */
2323 for (j
= 0; j
< 3; j
++)
2324 if (i
.types
[j
].bitfield
.inoutportreg
2325 || i
.types
[j
].bitfield
.shiftcount
2326 || i
.types
[j
].bitfield
.acc
2327 || i
.types
[j
].bitfield
.floatacc
)
2330 if (i
.tm
.opcode_modifier
.immext
)
2334 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2336 /* Streaming SIMD extensions 3 Instructions have the fixed
2337 operands with an opcode suffix which is coded in the same
2338 place as an 8-bit immediate field would be. Here we check
2339 those operands and remove them afterwards. */
2342 for (x
= 0; x
< i
.operands
; x
++)
2343 if (i
.op
[x
].regs
->reg_num
!= x
)
2344 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2346 i
.op
[x
].regs
->reg_name
,
2352 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2353 opcode suffix which is coded in the same place as an 8-bit
2354 immediate field would be. Here we fake an 8-bit immediate
2355 operand from the opcode suffix stored in tm.extension_opcode.
2356 SSE5 also uses this encoding, for some of its 3 argument
2359 assert (i
.imm_operands
== 0
2361 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2362 && i
.operands
<= 3)));
2364 exp
= &im_expressions
[i
.imm_operands
++];
2365 i
.op
[i
.operands
].imms
= exp
;
2366 UINTS_CLEAR (i
.types
[i
.operands
]);
2367 i
.types
[i
.operands
].bitfield
.imm8
= 1;
2369 exp
->X_op
= O_constant
;
2370 exp
->X_add_number
= i
.tm
.extension_opcode
;
2371 i
.tm
.extension_opcode
= None
;
2374 /* For insns with operands there are more diddles to do to the opcode. */
2377 if (!process_operands ())
2380 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2382 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2383 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2386 /* Handle conversion of 'int $3' --> special int3 insn. */
2387 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2389 i
.tm
.base_opcode
= INT3_OPCODE
;
2393 if ((i
.tm
.opcode_modifier
.jump
2394 || i
.tm
.opcode_modifier
.jumpbyte
2395 || i
.tm
.opcode_modifier
.jumpdword
)
2396 && i
.op
[0].disps
->X_op
== O_constant
)
2398 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2399 the absolute address given by the constant. Since ix86 jumps and
2400 calls are pc relative, we need to generate a reloc. */
2401 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2402 i
.op
[0].disps
->X_op
= O_symbol
;
2405 if (i
.tm
.opcode_modifier
.rex64
)
2408 /* For 8 bit registers we need an empty rex prefix. Also if the
2409 instruction already has a prefix, we need to convert old
2410 registers to new ones. */
2412 if ((i
.types
[0].bitfield
.reg8
2413 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2414 || (i
.types
[1].bitfield
.reg8
2415 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2416 || ((i
.types
[0].bitfield
.reg8
2417 || i
.types
[1].bitfield
.reg8
)
2422 i
.rex
|= REX_OPCODE
;
2423 for (x
= 0; x
< 2; x
++)
2425 /* Look for 8 bit operand that uses old registers. */
2426 if (i
.types
[x
].bitfield
.reg8
2427 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2429 /* In case it is "hi" register, give up. */
2430 if (i
.op
[x
].regs
->reg_num
> 3)
2431 as_bad (_("can't encode register '%s%s' in an "
2432 "instruction requiring REX prefix."),
2433 register_prefix
, i
.op
[x
].regs
->reg_name
);
2435 /* Otherwise it is equivalent to the extended register.
2436 Since the encoding doesn't change this is merely
2437 cosmetic cleanup for debug output. */
2439 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2444 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2446 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2451 else if (i
.rex
!= 0)
2452 add_prefix (REX_OPCODE
| i
.rex
);
2454 /* We are ready to output the insn. */
2459 parse_insn (char *line
, char *mnemonic
)
2462 char *token_start
= l
;
2467 /* Non-zero if we found a prefix only acceptable with string insns. */
2468 const char *expecting_string_instruction
= NULL
;
2473 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2476 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2478 as_bad (_("no such instruction: `%s'"), token_start
);
2483 if (!is_space_char (*l
)
2484 && *l
!= END_OF_INSN
2486 || (*l
!= PREFIX_SEPARATOR
2489 as_bad (_("invalid character %s in mnemonic"),
2490 output_invalid (*l
));
2493 if (token_start
== l
)
2495 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2496 as_bad (_("expecting prefix; got nothing"));
2498 as_bad (_("expecting mnemonic; got nothing"));
2502 /* Look up instruction (or prefix) via hash table. */
2503 current_templates
= hash_find (op_hash
, mnemonic
);
2505 if (*l
!= END_OF_INSN
2506 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2507 && current_templates
2508 && current_templates
->start
->opcode_modifier
.isprefix
)
2510 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2512 as_bad ((flag_code
!= CODE_64BIT
2513 ? _("`%s' is only supported in 64-bit mode")
2514 : _("`%s' is not supported in 64-bit mode")),
2515 current_templates
->start
->name
);
2518 /* If we are in 16-bit mode, do not allow addr16 or data16.
2519 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2520 if ((current_templates
->start
->opcode_modifier
.size16
2521 || current_templates
->start
->opcode_modifier
.size32
)
2522 && flag_code
!= CODE_64BIT
2523 && (current_templates
->start
->opcode_modifier
.size32
2524 ^ (flag_code
== CODE_16BIT
)))
2526 as_bad (_("redundant %s prefix"),
2527 current_templates
->start
->name
);
2530 /* Add prefix, checking for repeated prefixes. */
2531 switch (add_prefix (current_templates
->start
->base_opcode
))
2536 expecting_string_instruction
= current_templates
->start
->name
;
2539 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2546 if (!current_templates
)
2548 /* See if we can get a match by trimming off a suffix. */
2551 case WORD_MNEM_SUFFIX
:
2552 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2553 i
.suffix
= SHORT_MNEM_SUFFIX
;
2555 case BYTE_MNEM_SUFFIX
:
2556 case QWORD_MNEM_SUFFIX
:
2557 i
.suffix
= mnem_p
[-1];
2559 current_templates
= hash_find (op_hash
, mnemonic
);
2561 case SHORT_MNEM_SUFFIX
:
2562 case LONG_MNEM_SUFFIX
:
2565 i
.suffix
= mnem_p
[-1];
2567 current_templates
= hash_find (op_hash
, mnemonic
);
2575 if (intel_float_operand (mnemonic
) == 1)
2576 i
.suffix
= SHORT_MNEM_SUFFIX
;
2578 i
.suffix
= LONG_MNEM_SUFFIX
;
2580 current_templates
= hash_find (op_hash
, mnemonic
);
2584 if (!current_templates
)
2586 as_bad (_("no such instruction: `%s'"), token_start
);
2591 if (current_templates
->start
->opcode_modifier
.jump
2592 || current_templates
->start
->opcode_modifier
.jumpbyte
)
2594 /* Check for a branch hint. We allow ",pt" and ",pn" for
2595 predict taken and predict not taken respectively.
2596 I'm not sure that branch hints actually do anything on loop
2597 and jcxz insns (JumpByte) for current Pentium4 chips. They
2598 may work in the future and it doesn't hurt to accept them
2600 if (l
[0] == ',' && l
[1] == 'p')
2604 if (!add_prefix (DS_PREFIX_OPCODE
))
2608 else if (l
[2] == 'n')
2610 if (!add_prefix (CS_PREFIX_OPCODE
))
2616 /* Any other comma loses. */
2619 as_bad (_("invalid character %s in mnemonic"),
2620 output_invalid (*l
));
2624 /* Check if instruction is supported on specified architecture. */
2626 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2628 supported
|= cpu_flags_match (t
->cpu_flags
);
2633 if (!(supported
& 2))
2635 as_bad (flag_code
== CODE_64BIT
2636 ? _("`%s' is not supported in 64-bit mode")
2637 : _("`%s' is only supported in 64-bit mode"),
2638 current_templates
->start
->name
);
2641 if (!(supported
& 1))
2643 as_bad (_("`%s' is not supported on `%s%s'"),
2644 current_templates
->start
->name
, cpu_arch_name
,
2645 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2650 if (!cpu_arch_flags
.bitfield
.cpui386
2651 && (flag_code
!= CODE_16BIT
))
2653 as_warn (_("use .code16 to ensure correct addressing mode"));
2656 /* Check for rep/repne without a string instruction. */
2657 if (expecting_string_instruction
)
2659 static templates override
;
2661 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2662 if (t
->opcode_modifier
.isstring
)
2664 if (t
>= current_templates
->end
)
2666 as_bad (_("expecting string instruction after `%s'"),
2667 expecting_string_instruction
);
2670 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2671 if (!t
->opcode_modifier
.isstring
)
2674 current_templates
= &override
;
2681 parse_operands (char *l
, const char *mnemonic
)
2685 /* 1 if operand is pending after ','. */
2686 unsigned int expecting_operand
= 0;
2688 /* Non-zero if operand parens not balanced. */
2689 unsigned int paren_not_balanced
;
2691 while (*l
!= END_OF_INSN
)
2693 /* Skip optional white space before operand. */
2694 if (is_space_char (*l
))
2696 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2698 as_bad (_("invalid character %s before operand %d"),
2699 output_invalid (*l
),
2703 token_start
= l
; /* after white space */
2704 paren_not_balanced
= 0;
2705 while (paren_not_balanced
|| *l
!= ',')
2707 if (*l
== END_OF_INSN
)
2709 if (paren_not_balanced
)
2712 as_bad (_("unbalanced parenthesis in operand %d."),
2715 as_bad (_("unbalanced brackets in operand %d."),
2720 break; /* we are done */
2722 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2724 as_bad (_("invalid character %s in operand %d"),
2725 output_invalid (*l
),
2732 ++paren_not_balanced
;
2734 --paren_not_balanced
;
2739 ++paren_not_balanced
;
2741 --paren_not_balanced
;
2745 if (l
!= token_start
)
2746 { /* Yes, we've read in another operand. */
2747 unsigned int operand_ok
;
2748 this_operand
= i
.operands
++;
2749 i
.types
[this_operand
].bitfield
.unspecified
= 1;
2750 if (i
.operands
> MAX_OPERANDS
)
2752 as_bad (_("spurious operands; (%d operands/instruction max)"),
2756 /* Now parse operand adding info to 'i' as we go along. */
2757 END_STRING_AND_SAVE (l
);
2761 i386_intel_operand (token_start
,
2762 intel_float_operand (mnemonic
));
2764 operand_ok
= i386_att_operand (token_start
);
2766 RESTORE_END_STRING (l
);
2772 if (expecting_operand
)
2774 expecting_operand_after_comma
:
2775 as_bad (_("expecting operand after ','; got nothing"));
2780 as_bad (_("expecting operand before ','; got nothing"));
2785 /* Now *l must be either ',' or END_OF_INSN. */
2788 if (*++l
== END_OF_INSN
)
2790 /* Just skip it, if it's \n complain. */
2791 goto expecting_operand_after_comma
;
2793 expecting_operand
= 1;
2800 swap_2_operands (int xchg1
, int xchg2
)
2802 union i386_op temp_op
;
2803 i386_operand_type temp_type
;
2804 enum bfd_reloc_code_real temp_reloc
;
2806 temp_type
= i
.types
[xchg2
];
2807 i
.types
[xchg2
] = i
.types
[xchg1
];
2808 i
.types
[xchg1
] = temp_type
;
2809 temp_op
= i
.op
[xchg2
];
2810 i
.op
[xchg2
] = i
.op
[xchg1
];
2811 i
.op
[xchg1
] = temp_op
;
2812 temp_reloc
= i
.reloc
[xchg2
];
2813 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2814 i
.reloc
[xchg1
] = temp_reloc
;
2818 swap_operands (void)
2823 swap_2_operands (1, i
.operands
- 2);
2826 swap_2_operands (0, i
.operands
- 1);
2832 if (i
.mem_operands
== 2)
2834 const seg_entry
*temp_seg
;
2835 temp_seg
= i
.seg
[0];
2836 i
.seg
[0] = i
.seg
[1];
2837 i
.seg
[1] = temp_seg
;
2841 /* Try to ensure constant immediates are represented in the smallest
2846 char guess_suffix
= 0;
2850 guess_suffix
= i
.suffix
;
2851 else if (i
.reg_operands
)
2853 /* Figure out a suffix from the last register operand specified.
2854 We can't do this properly yet, ie. excluding InOutPortReg,
2855 but the following works for instructions with immediates.
2856 In any case, we can't set i.suffix yet. */
2857 for (op
= i
.operands
; --op
>= 0;)
2858 if (i
.types
[op
].bitfield
.reg8
)
2860 guess_suffix
= BYTE_MNEM_SUFFIX
;
2863 else if (i
.types
[op
].bitfield
.reg16
)
2865 guess_suffix
= WORD_MNEM_SUFFIX
;
2868 else if (i
.types
[op
].bitfield
.reg32
)
2870 guess_suffix
= LONG_MNEM_SUFFIX
;
2873 else if (i
.types
[op
].bitfield
.reg64
)
2875 guess_suffix
= QWORD_MNEM_SUFFIX
;
2879 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2880 guess_suffix
= WORD_MNEM_SUFFIX
;
2882 for (op
= i
.operands
; --op
>= 0;)
2883 if (operand_type_check (i
.types
[op
], imm
))
2885 switch (i
.op
[op
].imms
->X_op
)
2888 /* If a suffix is given, this operand may be shortened. */
2889 switch (guess_suffix
)
2891 case LONG_MNEM_SUFFIX
:
2892 i
.types
[op
].bitfield
.imm32
= 1;
2893 i
.types
[op
].bitfield
.imm64
= 1;
2895 case WORD_MNEM_SUFFIX
:
2896 i
.types
[op
].bitfield
.imm16
= 1;
2897 i
.types
[op
].bitfield
.imm32
= 1;
2898 i
.types
[op
].bitfield
.imm32s
= 1;
2899 i
.types
[op
].bitfield
.imm64
= 1;
2901 case BYTE_MNEM_SUFFIX
:
2902 i
.types
[op
].bitfield
.imm8
= 1;
2903 i
.types
[op
].bitfield
.imm8s
= 1;
2904 i
.types
[op
].bitfield
.imm16
= 1;
2905 i
.types
[op
].bitfield
.imm32
= 1;
2906 i
.types
[op
].bitfield
.imm32s
= 1;
2907 i
.types
[op
].bitfield
.imm64
= 1;
2911 /* If this operand is at most 16 bits, convert it
2912 to a signed 16 bit number before trying to see
2913 whether it will fit in an even smaller size.
2914 This allows a 16-bit operand such as $0xffe0 to
2915 be recognised as within Imm8S range. */
2916 if ((i
.types
[op
].bitfield
.imm16
)
2917 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2919 i
.op
[op
].imms
->X_add_number
=
2920 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2922 if ((i
.types
[op
].bitfield
.imm32
)
2923 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2926 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2927 ^ ((offsetT
) 1 << 31))
2928 - ((offsetT
) 1 << 31));
2931 = operand_type_or (i
.types
[op
],
2932 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
2934 /* We must avoid matching of Imm32 templates when 64bit
2935 only immediate is available. */
2936 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2937 i
.types
[op
].bitfield
.imm32
= 0;
2944 /* Symbols and expressions. */
2946 /* Convert symbolic operand to proper sizes for matching, but don't
2947 prevent matching a set of insns that only supports sizes other
2948 than those matching the insn suffix. */
2950 i386_operand_type mask
, allowed
;
2954 UINTS_CLEAR (allowed
);
2956 for (t
= current_templates
->start
;
2957 t
< current_templates
->end
;
2959 allowed
= operand_type_or (allowed
,
2960 t
->operand_types
[op
]);
2961 switch (guess_suffix
)
2963 case QWORD_MNEM_SUFFIX
:
2964 mask
.bitfield
.imm64
= 1;
2965 mask
.bitfield
.imm32s
= 1;
2967 case LONG_MNEM_SUFFIX
:
2968 mask
.bitfield
.imm32
= 1;
2970 case WORD_MNEM_SUFFIX
:
2971 mask
.bitfield
.imm16
= 1;
2973 case BYTE_MNEM_SUFFIX
:
2974 mask
.bitfield
.imm8
= 1;
2979 allowed
= operand_type_and (mask
, allowed
);
2980 if (!UINTS_ALL_ZERO (allowed
))
2981 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
2988 /* Try to use the smallest displacement type too. */
2990 optimize_disp (void)
2994 for (op
= i
.operands
; --op
>= 0;)
2995 if (operand_type_check (i
.types
[op
], disp
))
2997 if (i
.op
[op
].disps
->X_op
== O_constant
)
2999 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3001 if (i
.types
[op
].bitfield
.disp16
3002 && (disp
& ~(offsetT
) 0xffff) == 0)
3004 /* If this operand is at most 16 bits, convert
3005 to a signed 16 bit number and don't use 64bit
3007 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3008 i
.types
[op
].bitfield
.disp64
= 0;
3010 if (i
.types
[op
].bitfield
.disp32
3011 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3013 /* If this operand is at most 32 bits, convert
3014 to a signed 32 bit number and don't use 64bit
3016 disp
&= (((offsetT
) 2 << 31) - 1);
3017 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3018 i
.types
[op
].bitfield
.disp64
= 0;
3020 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3022 i
.types
[op
].bitfield
.disp8
= 0;
3023 i
.types
[op
].bitfield
.disp16
= 0;
3024 i
.types
[op
].bitfield
.disp32
= 0;
3025 i
.types
[op
].bitfield
.disp32s
= 0;
3026 i
.types
[op
].bitfield
.disp64
= 0;
3030 else if (flag_code
== CODE_64BIT
)
3032 if (fits_in_signed_long (disp
))
3034 i
.types
[op
].bitfield
.disp64
= 0;
3035 i
.types
[op
].bitfield
.disp32s
= 1;
3037 if (fits_in_unsigned_long (disp
))
3038 i
.types
[op
].bitfield
.disp32
= 1;
3040 if ((i
.types
[op
].bitfield
.disp32
3041 || i
.types
[op
].bitfield
.disp32s
3042 || i
.types
[op
].bitfield
.disp16
)
3043 && fits_in_signed_byte (disp
))
3044 i
.types
[op
].bitfield
.disp8
= 1;
3046 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3047 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3049 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3050 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3051 i
.types
[op
].bitfield
.disp8
= 0;
3052 i
.types
[op
].bitfield
.disp16
= 0;
3053 i
.types
[op
].bitfield
.disp32
= 0;
3054 i
.types
[op
].bitfield
.disp32s
= 0;
3055 i
.types
[op
].bitfield
.disp64
= 0;
3058 /* We only support 64bit displacement on constants. */
3059 i
.types
[op
].bitfield
.disp64
= 0;
3064 match_template (void)
3066 /* Points to template once we've found it. */
3068 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3069 unsigned int found_reverse_match
;
3070 i386_opcode_modifier suffix_check
;
3071 i386_operand_type operand_types
[MAX_OPERANDS
];
3072 int addr_prefix_disp
;
3074 unsigned int found_cpu_match
;
3075 unsigned int check_register
;
3077 #if MAX_OPERANDS != 4
3078 # error "MAX_OPERANDS must be 4."
3081 found_reverse_match
= 0;
3082 addr_prefix_disp
= -1;
3084 memset (&suffix_check
, 0, sizeof (suffix_check
));
3085 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3086 suffix_check
.no_bsuf
= 1;
3087 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3088 suffix_check
.no_wsuf
= 1;
3089 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3090 suffix_check
.no_ssuf
= 1;
3091 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3092 suffix_check
.no_lsuf
= 1;
3093 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3094 suffix_check
.no_qsuf
= 1;
3095 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3096 suffix_check
.no_ldsuf
= 1;
3098 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3100 addr_prefix_disp
= -1;
3102 /* Must have right number of operands. */
3103 if (i
.operands
!= t
->operands
)
3106 /* Check processor support. */
3107 found_cpu_match
= cpu_flags_match (t
->cpu_flags
) == 3;
3108 if (!found_cpu_match
)
3111 /* Check old gcc support. */
3112 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3115 /* Check AT&T mnemonic. */
3116 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3119 /* Check AT&T syntax Intel syntax. */
3120 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3121 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3124 /* Check the suffix, except for some instructions in intel mode. */
3125 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3126 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3127 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3128 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3129 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3130 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3131 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3134 if (!operand_size_match (t
))
3137 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3138 operand_types
[j
] = t
->operand_types
[j
];
3140 /* In general, don't allow 64-bit operands in 32-bit mode. */
3141 if (i
.suffix
== QWORD_MNEM_SUFFIX
3142 && flag_code
!= CODE_64BIT
3144 ? (!t
->opcode_modifier
.ignoresize
3145 && !intel_float_operand (t
->name
))
3146 : intel_float_operand (t
->name
) != 2)
3147 && ((!operand_types
[0].bitfield
.regmmx
3148 && !operand_types
[0].bitfield
.regxmm
)
3149 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3150 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
))
3151 && (t
->base_opcode
!= 0x0fc7
3152 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3155 /* Do not verify operands when there are none. */
3159 /* We've found a match; break out of loop. */
3163 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3164 into Disp32/Disp16/Disp32 operand. */
3165 if (i
.prefix
[ADDR_PREFIX
] != 0)
3167 /* There should be only one Disp operand. */
3171 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3173 if (operand_types
[j
].bitfield
.disp16
)
3175 addr_prefix_disp
= j
;
3176 operand_types
[j
].bitfield
.disp32
= 1;
3177 operand_types
[j
].bitfield
.disp16
= 0;
3183 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3185 if (operand_types
[j
].bitfield
.disp32
)
3187 addr_prefix_disp
= j
;
3188 operand_types
[j
].bitfield
.disp32
= 0;
3189 operand_types
[j
].bitfield
.disp16
= 1;
3195 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3197 if (operand_types
[j
].bitfield
.disp64
)
3199 addr_prefix_disp
= j
;
3200 operand_types
[j
].bitfield
.disp64
= 0;
3201 operand_types
[j
].bitfield
.disp32
= 1;
3209 /* We check register size only if size of operands can be
3210 encoded the canonical way. */
3211 check_register
= t
->opcode_modifier
.w
;
3212 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3213 switch (t
->operands
)
3216 if (!operand_type_match (overlap0
, i
.types
[0]))
3220 /* xchg %eax, %eax is a special case. It is an aliase for nop
3221 only in 32bit mode and we can use opcode 0x90. In 64bit
3222 mode, we can't use 0x90 for xchg %eax, %eax since it should
3223 zero-extend %eax to %rax. */
3224 if (flag_code
== CODE_64BIT
3225 && t
->base_opcode
== 0x90
3226 && UINTS_EQUAL (i
.types
[0], acc32
)
3227 && UINTS_EQUAL (i
.types
[1], acc32
))
3231 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3232 if (!operand_type_match (overlap0
, i
.types
[0])
3233 || !operand_type_match (overlap1
, i
.types
[1])
3235 && !operand_type_register_match (overlap0
, i
.types
[0],
3237 overlap1
, i
.types
[1],
3240 /* Check if other direction is valid ... */
3241 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3244 /* Try reversing direction of operands. */
3245 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3246 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3247 if (!operand_type_match (overlap0
, i
.types
[0])
3248 || !operand_type_match (overlap1
, i
.types
[1])
3250 && !operand_type_register_match (overlap0
,
3257 /* Does not match either direction. */
3260 /* found_reverse_match holds which of D or FloatDR
3262 if (t
->opcode_modifier
.d
)
3263 found_reverse_match
= Opcode_D
;
3264 else if (t
->opcode_modifier
.floatd
)
3265 found_reverse_match
= Opcode_FloatD
;
3267 found_reverse_match
= 0;
3268 if (t
->opcode_modifier
.floatr
)
3269 found_reverse_match
|= Opcode_FloatR
;
3273 /* Found a forward 2 operand match here. */
3274 switch (t
->operands
)
3277 overlap3
= operand_type_and (i
.types
[3],
3280 overlap2
= operand_type_and (i
.types
[2],
3285 switch (t
->operands
)
3288 if (!operand_type_match (overlap3
, i
.types
[3])
3290 && !operand_type_register_match (overlap2
,
3298 /* Here we make use of the fact that there are no
3299 reverse match 3 operand instructions, and all 3
3300 operand instructions only need to be checked for
3301 register consistency between operands 2 and 3. */
3302 if (!operand_type_match (overlap2
, i
.types
[2])
3304 && !operand_type_register_match (overlap1
,
3314 /* Found either forward/reverse 2, 3 or 4 operand match here:
3315 slip through to break. */
3317 if (!found_cpu_match
)
3319 found_reverse_match
= 0;
3322 /* We've found a match; break out of loop. */
3326 if (t
== current_templates
->end
)
3328 /* We found no match. */
3329 as_bad (_("suffix or operands invalid for `%s'"),
3330 current_templates
->start
->name
);
3334 if (!quiet_warnings
)
3337 && (i
.types
[0].bitfield
.jumpabsolute
3338 != operand_types
[0].bitfield
.jumpabsolute
))
3340 as_warn (_("indirect %s without `*'"), t
->name
);
3343 if (t
->opcode_modifier
.isprefix
3344 && t
->opcode_modifier
.ignoresize
)
3346 /* Warn them that a data or address size prefix doesn't
3347 affect assembly of the next line of code. */
3348 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3352 /* Copy the template we found. */
3355 if (addr_prefix_disp
!= -1)
3356 i
.tm
.operand_types
[addr_prefix_disp
]
3357 = operand_types
[addr_prefix_disp
];
3359 if (found_reverse_match
)
3361 /* If we found a reverse match we must alter the opcode
3362 direction bit. found_reverse_match holds bits to change
3363 (different for int & float insns). */
3365 i
.tm
.base_opcode
^= found_reverse_match
;
3367 i
.tm
.operand_types
[0] = operand_types
[1];
3368 i
.tm
.operand_types
[1] = operand_types
[0];
3377 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3378 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3380 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3382 as_bad (_("`%s' operand %d must use `%%es' segment"),
3387 /* There's only ever one segment override allowed per instruction.
3388 This instruction possibly has a legal segment override on the
3389 second operand, so copy the segment to where non-string
3390 instructions store it, allowing common code. */
3391 i
.seg
[0] = i
.seg
[1];
3393 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3395 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3397 as_bad (_("`%s' operand %d must use `%%es' segment"),
3407 process_suffix (void)
3409 /* If matched instruction specifies an explicit instruction mnemonic
3411 if (i
.tm
.opcode_modifier
.size16
)
3412 i
.suffix
= WORD_MNEM_SUFFIX
;
3413 else if (i
.tm
.opcode_modifier
.size32
)
3414 i
.suffix
= LONG_MNEM_SUFFIX
;
3415 else if (i
.tm
.opcode_modifier
.size64
)
3416 i
.suffix
= QWORD_MNEM_SUFFIX
;
3417 else if (i
.reg_operands
)
3419 /* If there's no instruction mnemonic suffix we try to invent one
3420 based on register operands. */
3423 /* We take i.suffix from the last register operand specified,
3424 Destination register type is more significant than source
3425 register type. crc32 in SSE4.2 prefers source register
3427 if (i
.tm
.base_opcode
== 0xf20f38f1)
3429 if (i
.types
[0].bitfield
.reg16
)
3430 i
.suffix
= WORD_MNEM_SUFFIX
;
3431 else if (i
.types
[0].bitfield
.reg32
)
3432 i
.suffix
= LONG_MNEM_SUFFIX
;
3433 else if (i
.types
[0].bitfield
.reg64
)
3434 i
.suffix
= QWORD_MNEM_SUFFIX
;
3436 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3438 if (i
.types
[0].bitfield
.reg8
)
3439 i
.suffix
= BYTE_MNEM_SUFFIX
;
3446 if (i
.tm
.base_opcode
== 0xf20f38f1
3447 || i
.tm
.base_opcode
== 0xf20f38f0)
3449 /* We have to know the operand size for crc32. */
3450 as_bad (_("ambiguous memory operand size for `%s`"),
3455 for (op
= i
.operands
; --op
>= 0;)
3456 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3458 if (i
.types
[op
].bitfield
.reg8
)
3460 i
.suffix
= BYTE_MNEM_SUFFIX
;
3463 else if (i
.types
[op
].bitfield
.reg16
)
3465 i
.suffix
= WORD_MNEM_SUFFIX
;
3468 else if (i
.types
[op
].bitfield
.reg32
)
3470 i
.suffix
= LONG_MNEM_SUFFIX
;
3473 else if (i
.types
[op
].bitfield
.reg64
)
3475 i
.suffix
= QWORD_MNEM_SUFFIX
;
3481 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3483 if (!check_byte_reg ())
3486 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3488 if (!check_long_reg ())
3491 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3494 && i
.tm
.opcode_modifier
.ignoresize
3495 && i
.tm
.opcode_modifier
.no_qsuf
)
3497 else if (!check_qword_reg ())
3500 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3502 if (!check_word_reg ())
3505 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
)
3507 /* Skip if the instruction has x suffix. match_template
3508 should check if it is a valid suffix. */
3510 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
3511 /* Do nothing if the instruction is going to ignore the prefix. */
3516 else if (i
.tm
.opcode_modifier
.defaultsize
3518 /* exclude fldenv/frstor/fsave/fstenv */
3519 && i
.tm
.opcode_modifier
.no_ssuf
)
3521 i
.suffix
= stackop_size
;
3523 else if (intel_syntax
3525 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
3526 || i
.tm
.opcode_modifier
.jumpbyte
3527 || i
.tm
.opcode_modifier
.jumpintersegment
3528 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
3529 && i
.tm
.extension_opcode
<= 3)))
3534 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3536 i
.suffix
= QWORD_MNEM_SUFFIX
;
3540 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3541 i
.suffix
= LONG_MNEM_SUFFIX
;
3544 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3545 i
.suffix
= WORD_MNEM_SUFFIX
;
3554 if (i
.tm
.opcode_modifier
.w
)
3556 as_bad (_("no instruction mnemonic suffix given and "
3557 "no register operands; can't size instruction"));
3563 unsigned int suffixes
;
3565 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
3566 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3568 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3570 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
3572 if (!i
.tm
.opcode_modifier
.no_ssuf
)
3574 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3577 /* There are more than suffix matches. */
3578 if (i
.tm
.opcode_modifier
.w
3579 || ((suffixes
& (suffixes
- 1))
3580 && !i
.tm
.opcode_modifier
.defaultsize
3581 && !i
.tm
.opcode_modifier
.ignoresize
))
3583 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3589 /* Change the opcode based on the operand size given by i.suffix;
3590 We don't need to change things for byte insns. */
3593 && i
.suffix
!= BYTE_MNEM_SUFFIX
3594 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
)
3596 /* It's not a byte, select word/dword operation. */
3597 if (i
.tm
.opcode_modifier
.w
)
3599 if (i
.tm
.opcode_modifier
.shortform
)
3600 i
.tm
.base_opcode
|= 8;
3602 i
.tm
.base_opcode
|= 1;
3605 /* Now select between word & dword operations via the operand
3606 size prefix, except for instructions that will ignore this
3608 if (i
.tm
.opcode_modifier
.addrprefixop0
)
3610 /* The address size override prefix changes the size of the
3612 if ((flag_code
== CODE_32BIT
3613 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
3614 || (flag_code
!= CODE_32BIT
3615 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
3616 if (!add_prefix (ADDR_PREFIX_OPCODE
))
3619 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
3620 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
3621 && !i
.tm
.opcode_modifier
.ignoresize
3622 && !i
.tm
.opcode_modifier
.floatmf
3623 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
3624 || (flag_code
== CODE_64BIT
3625 && i
.tm
.opcode_modifier
.jumpbyte
)))
3627 unsigned int prefix
= DATA_PREFIX_OPCODE
;
3629 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
3630 prefix
= ADDR_PREFIX_OPCODE
;
3632 if (!add_prefix (prefix
))
3636 /* Set mode64 for an operand. */
3637 if (i
.suffix
== QWORD_MNEM_SUFFIX
3638 && flag_code
== CODE_64BIT
3639 && !i
.tm
.opcode_modifier
.norex64
)
3641 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3642 need rex64. cmpxchg8b is also a special case. */
3643 if (! (i
.operands
== 2
3644 && i
.tm
.base_opcode
== 0x90
3645 && i
.tm
.extension_opcode
== None
3646 && UINTS_EQUAL (i
.types
[0], acc64
)
3647 && UINTS_EQUAL (i
.types
[1], acc64
))
3648 && ! (i
.operands
== 1
3649 && i
.tm
.base_opcode
== 0xfc7
3650 && i
.tm
.extension_opcode
== 1
3651 && !operand_type_check (i
.types
[0], reg
)
3652 && operand_type_check (i
.types
[0], anymem
)))
3656 /* Size floating point instruction. */
3657 if (i
.suffix
== LONG_MNEM_SUFFIX
)
3658 if (i
.tm
.opcode_modifier
.floatmf
)
3659 i
.tm
.base_opcode
^= 4;
3666 check_byte_reg (void)
3670 for (op
= i
.operands
; --op
>= 0;)
3672 /* If this is an eight bit register, it's OK. If it's the 16 or
3673 32 bit version of an eight bit register, we will just use the
3674 low portion, and that's OK too. */
3675 if (i
.types
[op
].bitfield
.reg8
)
3678 /* Don't generate this warning if not needed. */
3679 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
3682 /* crc32 doesn't generate this warning. */
3683 if (i
.tm
.base_opcode
== 0xf20f38f0)
3686 if ((i
.types
[op
].bitfield
.reg16
3687 || i
.types
[op
].bitfield
.reg32
3688 || i
.types
[op
].bitfield
.reg64
)
3689 && i
.op
[op
].regs
->reg_num
< 4)
3691 /* Prohibit these changes in the 64bit mode, since the
3692 lowering is more complicated. */
3693 if (flag_code
== CODE_64BIT
3694 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3696 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3697 register_prefix
, i
.op
[op
].regs
->reg_name
,
3701 #if REGISTER_WARNINGS
3703 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3704 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3706 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
3707 ? REGNAM_AL
- REGNAM_AX
3708 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3710 i
.op
[op
].regs
->reg_name
,
3715 /* Any other register is bad. */
3716 if (i
.types
[op
].bitfield
.reg16
3717 || i
.types
[op
].bitfield
.reg32
3718 || i
.types
[op
].bitfield
.reg64
3719 || i
.types
[op
].bitfield
.regmmx
3720 || i
.types
[op
].bitfield
.regxmm
3721 || i
.types
[op
].bitfield
.sreg2
3722 || i
.types
[op
].bitfield
.sreg3
3723 || i
.types
[op
].bitfield
.control
3724 || i
.types
[op
].bitfield
.debug
3725 || i
.types
[op
].bitfield
.test
3726 || i
.types
[op
].bitfield
.floatreg
3727 || i
.types
[op
].bitfield
.floatacc
)
3729 as_bad (_("`%s%s' not allowed with `%s%c'"),
3731 i
.op
[op
].regs
->reg_name
,
3741 check_long_reg (void)
3745 for (op
= i
.operands
; --op
>= 0;)
3746 /* Reject eight bit registers, except where the template requires
3747 them. (eg. movzb) */
3748 if (i
.types
[op
].bitfield
.reg8
3749 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3750 || i
.tm
.operand_types
[op
].bitfield
.reg32
3751 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3753 as_bad (_("`%s%s' not allowed with `%s%c'"),
3755 i
.op
[op
].regs
->reg_name
,
3760 /* Warn if the e prefix on a general reg is missing. */
3761 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3762 && i
.types
[op
].bitfield
.reg16
3763 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3764 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3766 /* Prohibit these changes in the 64bit mode, since the
3767 lowering is more complicated. */
3768 if (flag_code
== CODE_64BIT
)
3770 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3771 register_prefix
, i
.op
[op
].regs
->reg_name
,
3775 #if REGISTER_WARNINGS
3777 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3779 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3781 i
.op
[op
].regs
->reg_name
,
3785 /* Warn if the r prefix on a general reg is missing. */
3786 else if (i
.types
[op
].bitfield
.reg64
3787 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3788 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3791 && i
.tm
.opcode_modifier
.toqword
3792 && !i
.types
[0].bitfield
.regxmm
)
3794 /* Convert to QWORD. We want REX byte. */
3795 i
.suffix
= QWORD_MNEM_SUFFIX
;
3799 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3800 register_prefix
, i
.op
[op
].regs
->reg_name
,
3809 check_qword_reg (void)
3813 for (op
= i
.operands
; --op
>= 0; )
3814 /* Reject eight bit registers, except where the template requires
3815 them. (eg. movzb) */
3816 if (i
.types
[op
].bitfield
.reg8
3817 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3818 || i
.tm
.operand_types
[op
].bitfield
.reg32
3819 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3821 as_bad (_("`%s%s' not allowed with `%s%c'"),
3823 i
.op
[op
].regs
->reg_name
,
3828 /* Warn if the e prefix on a general reg is missing. */
3829 else if ((i
.types
[op
].bitfield
.reg16
3830 || i
.types
[op
].bitfield
.reg32
)
3831 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3832 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3834 /* Prohibit these changes in the 64bit mode, since the
3835 lowering is more complicated. */
3837 && i
.tm
.opcode_modifier
.todword
3838 && !i
.types
[0].bitfield
.regxmm
)
3840 /* Convert to DWORD. We don't want REX byte. */
3841 i
.suffix
= LONG_MNEM_SUFFIX
;
3845 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3846 register_prefix
, i
.op
[op
].regs
->reg_name
,
3855 check_word_reg (void)
3858 for (op
= i
.operands
; --op
>= 0;)
3859 /* Reject eight bit registers, except where the template requires
3860 them. (eg. movzb) */
3861 if (i
.types
[op
].bitfield
.reg8
3862 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3863 || i
.tm
.operand_types
[op
].bitfield
.reg32
3864 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3866 as_bad (_("`%s%s' not allowed with `%s%c'"),
3868 i
.op
[op
].regs
->reg_name
,
3873 /* Warn if the e prefix on a general reg is present. */
3874 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3875 && i
.types
[op
].bitfield
.reg32
3876 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3877 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3879 /* Prohibit these changes in the 64bit mode, since the
3880 lowering is more complicated. */
3881 if (flag_code
== CODE_64BIT
)
3883 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3884 register_prefix
, i
.op
[op
].regs
->reg_name
,
3889 #if REGISTER_WARNINGS
3890 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3892 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3894 i
.op
[op
].regs
->reg_name
,
3902 update_imm (unsigned int j
)
3904 i386_operand_type overlap
;
3906 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3907 if ((overlap
.bitfield
.imm8
3908 || overlap
.bitfield
.imm8s
3909 || overlap
.bitfield
.imm16
3910 || overlap
.bitfield
.imm32
3911 || overlap
.bitfield
.imm32s
3912 || overlap
.bitfield
.imm64
)
3913 && !UINTS_EQUAL (overlap
, imm8
)
3914 && !UINTS_EQUAL (overlap
, imm8s
)
3915 && !UINTS_EQUAL (overlap
, imm16
)
3916 && !UINTS_EQUAL (overlap
, imm32
)
3917 && !UINTS_EQUAL (overlap
, imm32s
)
3918 && !UINTS_EQUAL (overlap
, imm64
))
3922 i386_operand_type temp
;
3925 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3927 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
3928 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
3930 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3931 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
3932 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3934 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
3935 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
3938 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
3941 else if (UINTS_EQUAL (overlap
, imm16_32_32s
)
3942 || UINTS_EQUAL (overlap
, imm16_32
)
3943 || UINTS_EQUAL (overlap
, imm16_32s
))
3945 UINTS_CLEAR (overlap
);
3946 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3947 overlap
.bitfield
.imm16
= 1;
3949 overlap
.bitfield
.imm32s
= 1;
3951 if (!UINTS_EQUAL (overlap
, imm8
)
3952 && !UINTS_EQUAL (overlap
, imm8s
)
3953 && !UINTS_EQUAL (overlap
, imm16
)
3954 && !UINTS_EQUAL (overlap
, imm32
)
3955 && !UINTS_EQUAL (overlap
, imm32s
)
3956 && !UINTS_EQUAL (overlap
, imm64
))
3958 as_bad (_("no instruction mnemonic suffix given; "
3959 "can't determine immediate size"));
3963 i
.types
[j
] = overlap
;
3973 for (j
= 0; j
< 2; j
++)
3974 if (update_imm (j
) == 0)
3977 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
3978 assert (operand_type_check (i
.types
[2], imm
) == 0);
3986 i
.drex
.modrm_reg
= 0;
3987 i
.drex
.modrm_regmem
= 0;
3989 /* SSE5 4 operand instructions must have the destination the same as
3990 one of the inputs. Figure out the destination register and cache
3991 it away in the drex field, and remember which fields to use for
3993 if (i
.tm
.opcode_modifier
.drex
3994 && i
.tm
.opcode_modifier
.drexv
3997 i
.tm
.extension_opcode
= None
;
3999 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4000 if (i
.types
[0].bitfield
.regxmm
!= 0
4001 && i
.types
[1].bitfield
.regxmm
!= 0
4002 && i
.types
[2].bitfield
.regxmm
!= 0
4003 && i
.types
[3].bitfield
.regxmm
!= 0
4004 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4005 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4007 /* Clear the arguments that are stored in drex. */
4008 UINTS_CLEAR (i
.types
[0]);
4009 UINTS_CLEAR (i
.types
[3]);
4010 i
.reg_operands
-= 2;
4012 /* There are two different ways to encode a 4 operand
4013 instruction with all registers that uses OC1 set to
4014 0 or 1. Favor setting OC1 to 0 since this mimics the
4015 actions of other SSE5 assemblers. Use modrm encoding 2
4016 for register/register. Include the high order bit that
4017 is normally stored in the REX byte in the register
4019 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4020 i
.drex
.modrm_reg
= 2;
4021 i
.drex
.modrm_regmem
= 1;
4022 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4023 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4026 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4027 else if (i
.types
[0].bitfield
.regxmm
!= 0
4028 && i
.types
[1].bitfield
.regxmm
!= 0
4029 && (i
.types
[2].bitfield
.regxmm
4030 || operand_type_check (i
.types
[2], anymem
))
4031 && i
.types
[3].bitfield
.regxmm
!= 0
4032 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4033 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4035 /* clear the arguments that are stored in drex */
4036 UINTS_CLEAR (i
.types
[0]);
4037 UINTS_CLEAR (i
.types
[3]);
4038 i
.reg_operands
-= 2;
4040 /* Specify the modrm encoding for memory addressing. Include
4041 the high order bit that is normally stored in the REX byte
4042 in the register field. */
4043 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4044 i
.drex
.modrm_reg
= 1;
4045 i
.drex
.modrm_regmem
= 2;
4046 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4047 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4050 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4051 else if (i
.types
[0].bitfield
.regxmm
!= 0
4052 && operand_type_check (i
.types
[1], anymem
) != 0
4053 && i
.types
[2].bitfield
.regxmm
!= 0
4054 && i
.types
[3].bitfield
.regxmm
!= 0
4055 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4056 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4058 /* Clear the arguments that are stored in drex. */
4059 UINTS_CLEAR (i
.types
[0]);
4060 UINTS_CLEAR (i
.types
[3]);
4061 i
.reg_operands
-= 2;
4063 /* Specify the modrm encoding for memory addressing. Include
4064 the high order bit that is normally stored in the REX byte
4065 in the register field. */
4066 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4067 i
.drex
.modrm_reg
= 2;
4068 i
.drex
.modrm_regmem
= 1;
4069 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4070 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4073 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4074 else if (i
.types
[0].bitfield
.regxmm
!= 0
4075 && i
.types
[1].bitfield
.regxmm
!= 0
4076 && i
.types
[2].bitfield
.regxmm
!= 0
4077 && i
.types
[3].bitfield
.regxmm
!= 0
4078 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4079 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4081 /* clear the arguments that are stored in drex */
4082 UINTS_CLEAR (i
.types
[2]);
4083 UINTS_CLEAR (i
.types
[3]);
4084 i
.reg_operands
-= 2;
4086 /* There are two different ways to encode a 4 operand
4087 instruction with all registers that uses OC1 set to
4088 0 or 1. Favor setting OC1 to 0 since this mimics the
4089 actions of other SSE5 assemblers. Use modrm encoding
4090 2 for register/register. Include the high order bit that
4091 is normally stored in the REX byte in the register
4093 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4094 i
.drex
.modrm_reg
= 1;
4095 i
.drex
.modrm_regmem
= 0;
4097 /* Remember the register, including the upper bits */
4098 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4099 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4102 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4103 else if (i
.types
[0].bitfield
.regxmm
!= 0
4104 && (i
.types
[1].bitfield
.regxmm
4105 || operand_type_check (i
.types
[1], anymem
))
4106 && i
.types
[2].bitfield
.regxmm
!= 0
4107 && i
.types
[3].bitfield
.regxmm
!= 0
4108 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4109 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4111 /* Clear the arguments that are stored in drex. */
4112 UINTS_CLEAR (i
.types
[2]);
4113 UINTS_CLEAR (i
.types
[3]);
4114 i
.reg_operands
-= 2;
4116 /* Specify the modrm encoding and remember the register
4117 including the bits normally stored in the REX byte. */
4118 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4119 i
.drex
.modrm_reg
= 0;
4120 i
.drex
.modrm_regmem
= 1;
4121 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4122 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4125 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4126 else if (operand_type_check (i
.types
[0], anymem
) != 0
4127 && i
.types
[1].bitfield
.regxmm
!= 0
4128 && i
.types
[2].bitfield
.regxmm
!= 0
4129 && i
.types
[3].bitfield
.regxmm
!= 0
4130 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4131 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4133 /* clear the arguments that are stored in drex */
4134 UINTS_CLEAR (i
.types
[2]);
4135 UINTS_CLEAR (i
.types
[3]);
4136 i
.reg_operands
-= 2;
4138 /* Specify the modrm encoding and remember the register
4139 including the bits normally stored in the REX byte. */
4140 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4141 i
.drex
.modrm_reg
= 1;
4142 i
.drex
.modrm_regmem
= 0;
4143 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4144 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4148 as_bad (_("Incorrect operands for the '%s' instruction"),
4152 /* SSE5 instructions with the DREX byte where the only memory operand
4153 is in the 2nd argument, and the first and last xmm register must
4154 match, and is encoded in the DREX byte. */
4155 else if (i
.tm
.opcode_modifier
.drex
4156 && !i
.tm
.opcode_modifier
.drexv
4159 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4160 if (i
.types
[0].bitfield
.regxmm
!= 0
4161 && (i
.types
[1].bitfield
.regxmm
4162 || operand_type_check(i
.types
[1], anymem
))
4163 && i
.types
[2].bitfield
.regxmm
!= 0
4164 && i
.types
[3].bitfield
.regxmm
!= 0
4165 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4166 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4168 /* clear the arguments that are stored in drex */
4169 UINTS_CLEAR (i
.types
[0]);
4170 UINTS_CLEAR (i
.types
[3]);
4171 i
.reg_operands
-= 2;
4173 /* Specify the modrm encoding and remember the register
4174 including the high bit normally stored in the REX
4176 i
.drex
.modrm_reg
= 2;
4177 i
.drex
.modrm_regmem
= 1;
4178 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4179 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4183 as_bad (_("Incorrect operands for the '%s' instruction"),
4187 /* SSE5 3 operand instructions that the result is a register, being
4188 either operand can be a memory operand, using OC0 to note which
4189 one is the memory. */
4190 else if (i
.tm
.opcode_modifier
.drex
4191 && i
.tm
.opcode_modifier
.drexv
4194 i
.tm
.extension_opcode
= None
;
4196 /* Case 1: 3 operand insn, src1 = register. */
4197 if (i
.types
[0].bitfield
.regxmm
!= 0
4198 && i
.types
[1].bitfield
.regxmm
!= 0
4199 && i
.types
[2].bitfield
.regxmm
!= 0)
4201 /* Clear the arguments that are stored in drex. */
4202 UINTS_CLEAR (i
.types
[2]);
4205 /* Specify the modrm encoding and remember the register
4206 including the high bit normally stored in the REX byte. */
4207 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4208 i
.drex
.modrm_reg
= 1;
4209 i
.drex
.modrm_regmem
= 0;
4210 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4211 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4214 /* Case 2: 3 operand insn, src1 = memory. */
4215 else if (operand_type_check (i
.types
[0], anymem
) != 0
4216 && i
.types
[1].bitfield
.regxmm
!= 0
4217 && i
.types
[2].bitfield
.regxmm
!= 0)
4219 /* Clear the arguments that are stored in drex. */
4220 UINTS_CLEAR (i
.types
[2]);
4223 /* Specify the modrm encoding and remember the register
4224 including the high bit normally stored in the REX
4226 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4227 i
.drex
.modrm_reg
= 1;
4228 i
.drex
.modrm_regmem
= 0;
4229 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4230 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4233 /* Case 3: 3 operand insn, src2 = memory. */
4234 else if (i
.types
[0].bitfield
.regxmm
!= 0
4235 && operand_type_check (i
.types
[1], anymem
) != 0
4236 && i
.types
[2].bitfield
.regxmm
!= 0)
4238 /* Clear the arguments that are stored in drex. */
4239 UINTS_CLEAR (i
.types
[2]);
4242 /* Specify the modrm encoding and remember the register
4243 including the high bit normally stored in the REX byte. */
4244 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4245 i
.drex
.modrm_reg
= 0;
4246 i
.drex
.modrm_regmem
= 1;
4247 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4248 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4252 as_bad (_("Incorrect operands for the '%s' instruction"),
4256 /* SSE5 4 operand instructions that are the comparison instructions
4257 where the first operand is the immediate value of the comparison
4259 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4261 /* Case 1: 4 operand insn, src1 = reg/memory. */
4262 if (operand_type_check (i
.types
[0], imm
) != 0
4263 && (i
.types
[1].bitfield
.regxmm
4264 || operand_type_check (i
.types
[1], anymem
))
4265 && i
.types
[2].bitfield
.regxmm
!= 0
4266 && i
.types
[3].bitfield
.regxmm
!= 0)
4268 /* clear the arguments that are stored in drex */
4269 UINTS_CLEAR (i
.types
[3]);
4272 /* Specify the modrm encoding and remember the register
4273 including the high bit normally stored in the REX byte. */
4274 i
.drex
.modrm_reg
= 2;
4275 i
.drex
.modrm_regmem
= 1;
4276 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4277 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4280 /* Case 2: 3 operand insn with ImmExt that places the
4281 opcode_extension as an immediate argument. This is used for
4282 all of the varients of comparison that supplies the appropriate
4283 value as part of the instruction. */
4284 else if ((i
.types
[0].bitfield
.regxmm
4285 || operand_type_check (i
.types
[0], anymem
))
4286 && i
.types
[1].bitfield
.regxmm
!= 0
4287 && i
.types
[2].bitfield
.regxmm
!= 0
4288 && operand_type_check (i
.types
[3], imm
) != 0)
4290 /* clear the arguments that are stored in drex */
4291 UINTS_CLEAR (i
.types
[2]);
4294 /* Specify the modrm encoding and remember the register
4295 including the high bit normally stored in the REX byte. */
4296 i
.drex
.modrm_reg
= 1;
4297 i
.drex
.modrm_regmem
= 0;
4298 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4299 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4303 as_bad (_("Incorrect operands for the '%s' instruction"),
4307 else if (i
.tm
.opcode_modifier
.drex
4308 || i
.tm
.opcode_modifier
.drexv
4309 || i
.tm
.opcode_modifier
.drexc
)
4310 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4314 process_operands (void)
4316 /* Default segment register this instruction will use for memory
4317 accesses. 0 means unknown. This is only for optimizing out
4318 unnecessary segment overrides. */
4319 const seg_entry
*default_seg
= 0;
4321 /* Handle all of the DREX munging that SSE5 needs. */
4322 if (i
.tm
.opcode_modifier
.drex
4323 || i
.tm
.opcode_modifier
.drexv
4324 || i
.tm
.opcode_modifier
.drexc
)
4327 if (i
.tm
.opcode_modifier
.firstxmm0
)
4331 /* The first operand is implicit and must be xmm0. */
4332 assert (i
.reg_operands
&& UINTS_EQUAL (i
.types
[0], regxmm
));
4333 if (i
.op
[0].regs
->reg_num
!= 0)
4336 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4337 i
.tm
.name
, register_prefix
);
4339 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4340 i
.tm
.name
, register_prefix
);
4344 for (j
= 1; j
< i
.operands
; j
++)
4346 i
.op
[j
- 1] = i
.op
[j
];
4347 i
.types
[j
- 1] = i
.types
[j
];
4349 /* We need to adjust fields in i.tm since they are used by
4350 build_modrm_byte. */
4351 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4358 else if (i
.tm
.opcode_modifier
.regkludge
)
4360 /* The imul $imm, %reg instruction is converted into
4361 imul $imm, %reg, %reg, and the clr %reg instruction
4362 is converted into xor %reg, %reg. */
4364 unsigned int first_reg_op
;
4366 if (operand_type_check (i
.types
[0], reg
))
4370 /* Pretend we saw the extra register operand. */
4371 assert (i
.reg_operands
== 1
4372 && i
.op
[first_reg_op
+ 1].regs
== 0);
4373 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4374 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4379 if (i
.tm
.opcode_modifier
.shortform
)
4381 if (i
.types
[0].bitfield
.sreg2
4382 || i
.types
[0].bitfield
.sreg3
)
4384 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4385 && i
.op
[0].regs
->reg_num
== 1)
4387 as_bad (_("you can't `pop %%cs'"));
4390 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4391 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4396 /* The register or float register operand is in operand
4400 if (i
.types
[0].bitfield
.floatreg
4401 || operand_type_check (i
.types
[0], reg
))
4405 /* Register goes in low 3 bits of opcode. */
4406 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4407 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4409 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4411 /* Warn about some common errors, but press on regardless.
4412 The first case can be generated by gcc (<= 2.8.1). */
4413 if (i
.operands
== 2)
4415 /* Reversed arguments on faddp, fsubp, etc. */
4416 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4417 register_prefix
, i
.op
[1].regs
->reg_name
,
4418 register_prefix
, i
.op
[0].regs
->reg_name
);
4422 /* Extraneous `l' suffix on fp insn. */
4423 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4424 register_prefix
, i
.op
[0].regs
->reg_name
);
4429 else if (i
.tm
.opcode_modifier
.modrm
)
4431 /* The opcode is completed (modulo i.tm.extension_opcode which
4432 must be put into the modrm byte). Now, we make the modrm and
4433 index base bytes based on all the info we've collected. */
4435 default_seg
= build_modrm_byte ();
4437 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4441 else if (i
.tm
.opcode_modifier
.isstring
)
4443 /* For the string instructions that allow a segment override
4444 on one of their operands, the default segment is ds. */
4448 if (i
.tm
.base_opcode
== 0x8d /* lea */
4451 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4453 /* If a segment was explicitly specified, and the specified segment
4454 is not the default, use an opcode prefix to select it. If we
4455 never figured out what the default segment is, then default_seg
4456 will be zero at this point, and the specified segment prefix will
4458 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4460 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4466 static const seg_entry
*
4467 build_modrm_byte (void)
4469 const seg_entry
*default_seg
= 0;
4471 /* SSE5 4 operand instructions are encoded in such a way that one of
4472 the inputs must match the destination register. Process_drex hides
4473 the 3rd argument in the drex field, so that by the time we get
4474 here, it looks to GAS as if this is a 2 operand instruction. */
4475 if ((i
.tm
.opcode_modifier
.drex
4476 || i
.tm
.opcode_modifier
.drexv
4477 || i
.tm
.opcode_modifier
.drexc
)
4478 && i
.reg_operands
== 2)
4480 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
4481 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
4483 i
.rm
.reg
= reg
->reg_num
;
4484 i
.rm
.regmem
= regmem
->reg_num
;
4486 if ((reg
->reg_flags
& RegRex
) != 0)
4488 if ((regmem
->reg_flags
& RegRex
) != 0)
4492 /* i.reg_operands MUST be the number of real register operands;
4493 implicit registers do not count. */
4494 else if (i
.reg_operands
== 2)
4496 unsigned int source
, dest
;
4504 /* When there are 3 operands, one of them may be immediate,
4505 which may be the first or the last operand. Otherwise,
4506 the first operand must be shift count register (cl). */
4507 assert (i
.imm_operands
== 1
4508 || (i
.imm_operands
== 0
4509 && i
.types
[0].bitfield
.shiftcount
));
4510 if (operand_type_check (i
.types
[0], imm
)
4511 || i
.types
[0].bitfield
.shiftcount
)
4517 /* When there are 4 operands, the first two must be 8bit
4518 immediate operands. The source operand will be the 3rd
4520 assert (i
.imm_operands
== 2
4521 && i
.types
[0].bitfield
.imm8
4522 && i
.types
[1].bitfield
.imm8
);
4532 /* One of the register operands will be encoded in the i.tm.reg
4533 field, the other in the combined i.tm.mode and i.tm.regmem
4534 fields. If no form of this instruction supports a memory
4535 destination operand, then we assume the source operand may
4536 sometimes be a memory operand and so we need to store the
4537 destination in the i.rm.reg field. */
4538 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
4539 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
4541 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
4542 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
4543 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4545 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4550 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
4551 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
4552 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4554 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4557 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
4559 if (!i
.types
[0].bitfield
.control
4560 && !i
.types
[1].bitfield
.control
)
4562 i
.rex
&= ~(REX_R
| REX_B
);
4563 add_prefix (LOCK_PREFIX_OPCODE
);
4567 { /* If it's not 2 reg operands... */
4570 unsigned int fake_zero_displacement
= 0;
4573 /* This has been precalculated for SSE5 instructions
4574 that have a DREX field earlier in process_drex. */
4575 if (i
.tm
.opcode_modifier
.drex
4576 || i
.tm
.opcode_modifier
.drexv
4577 || i
.tm
.opcode_modifier
.drexc
)
4578 op
= i
.drex
.modrm_regmem
;
4581 for (op
= 0; op
< i
.operands
; op
++)
4582 if (operand_type_check (i
.types
[op
], anymem
))
4584 assert (op
< i
.operands
);
4589 if (i
.base_reg
== 0)
4592 if (!i
.disp_operands
)
4593 fake_zero_displacement
= 1;
4594 if (i
.index_reg
== 0)
4596 /* Operand is just <disp> */
4597 if (flag_code
== CODE_64BIT
)
4599 /* 64bit mode overwrites the 32bit absolute
4600 addressing by RIP relative addressing and
4601 absolute addressing is encoded by one of the
4602 redundant SIB forms. */
4603 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4604 i
.sib
.base
= NO_BASE_REGISTER
;
4605 i
.sib
.index
= NO_INDEX_REGISTER
;
4606 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
4607 ? disp32s
: disp32
);
4609 else if ((flag_code
== CODE_16BIT
)
4610 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4612 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
4613 i
.types
[op
] = disp16
;
4617 i
.rm
.regmem
= NO_BASE_REGISTER
;
4618 i
.types
[op
] = disp32
;
4621 else /* !i.base_reg && i.index_reg */
4623 if (i
.index_reg
->reg_num
== RegEiz
4624 || i
.index_reg
->reg_num
== RegRiz
)
4625 i
.sib
.index
= NO_INDEX_REGISTER
;
4627 i
.sib
.index
= i
.index_reg
->reg_num
;
4628 i
.sib
.base
= NO_BASE_REGISTER
;
4629 i
.sib
.scale
= i
.log2_scale_factor
;
4630 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4631 i
.types
[op
].bitfield
.disp8
= 0;
4632 i
.types
[op
].bitfield
.disp16
= 0;
4633 i
.types
[op
].bitfield
.disp64
= 0;
4634 if (flag_code
!= CODE_64BIT
)
4636 /* Must be 32 bit */
4637 i
.types
[op
].bitfield
.disp32
= 1;
4638 i
.types
[op
].bitfield
.disp32s
= 0;
4642 i
.types
[op
].bitfield
.disp32
= 0;
4643 i
.types
[op
].bitfield
.disp32s
= 1;
4645 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
4649 /* RIP addressing for 64bit mode. */
4650 else if (i
.base_reg
->reg_num
== RegRip
||
4651 i
.base_reg
->reg_num
== RegEip
)
4653 i
.rm
.regmem
= NO_BASE_REGISTER
;
4654 i
.types
[op
].bitfield
.disp8
= 0;
4655 i
.types
[op
].bitfield
.disp16
= 0;
4656 i
.types
[op
].bitfield
.disp32
= 0;
4657 i
.types
[op
].bitfield
.disp32s
= 1;
4658 i
.types
[op
].bitfield
.disp64
= 0;
4659 i
.flags
[op
] |= Operand_PCrel
;
4660 if (! i
.disp_operands
)
4661 fake_zero_displacement
= 1;
4663 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
4665 switch (i
.base_reg
->reg_num
)
4668 if (i
.index_reg
== 0)
4670 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4671 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
4675 if (i
.index_reg
== 0)
4678 if (operand_type_check (i
.types
[op
], disp
) == 0)
4680 /* fake (%bp) into 0(%bp) */
4681 i
.types
[op
].bitfield
.disp8
= 1;
4682 fake_zero_displacement
= 1;
4685 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4686 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
4688 default: /* (%si) -> 4 or (%di) -> 5 */
4689 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
4691 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
4693 else /* i.base_reg and 32/64 bit mode */
4695 if (flag_code
== CODE_64BIT
4696 && operand_type_check (i
.types
[op
], disp
))
4698 i386_operand_type temp
;
4700 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
4702 if (i
.prefix
[ADDR_PREFIX
] == 0)
4703 i
.types
[op
].bitfield
.disp32s
= 1;
4705 i
.types
[op
].bitfield
.disp32
= 1;
4708 i
.rm
.regmem
= i
.base_reg
->reg_num
;
4709 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
4711 i
.sib
.base
= i
.base_reg
->reg_num
;
4712 /* x86-64 ignores REX prefix bit here to avoid decoder
4714 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
4717 if (i
.disp_operands
== 0)
4719 fake_zero_displacement
= 1;
4720 i
.types
[op
].bitfield
.disp8
= 1;
4723 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
4727 i
.sib
.scale
= i
.log2_scale_factor
;
4728 if (i
.index_reg
== 0)
4730 /* <disp>(%esp) becomes two byte modrm with no index
4731 register. We've already stored the code for esp
4732 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4733 Any base register besides %esp will not use the
4734 extra modrm byte. */
4735 i
.sib
.index
= NO_INDEX_REGISTER
;
4739 if (i
.index_reg
->reg_num
== RegEiz
4740 || i
.index_reg
->reg_num
== RegRiz
)
4741 i
.sib
.index
= NO_INDEX_REGISTER
;
4743 i
.sib
.index
= i
.index_reg
->reg_num
;
4744 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4745 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
4750 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4751 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
4754 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
4757 if (fake_zero_displacement
)
4759 /* Fakes a zero displacement assuming that i.types[op]
4760 holds the correct displacement size. */
4763 assert (i
.op
[op
].disps
== 0);
4764 exp
= &disp_expressions
[i
.disp_operands
++];
4765 i
.op
[op
].disps
= exp
;
4766 exp
->X_op
= O_constant
;
4767 exp
->X_add_number
= 0;
4768 exp
->X_add_symbol
= (symbolS
*) 0;
4769 exp
->X_op_symbol
= (symbolS
*) 0;
4773 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4774 (if any) based on i.tm.extension_opcode. Again, we must be
4775 careful to make sure that segment/control/debug/test/MMX
4776 registers are coded into the i.rm.reg field. */
4781 /* This has been precalculated for SSE5 instructions
4782 that have a DREX field earlier in process_drex. */
4783 if (i
.tm
.opcode_modifier
.drex
4784 || i
.tm
.opcode_modifier
.drexv
4785 || i
.tm
.opcode_modifier
.drexc
)
4787 op
= i
.drex
.modrm_reg
;
4788 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
4789 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4794 for (op
= 0; op
< i
.operands
; op
++)
4795 if (i
.types
[op
].bitfield
.reg8
4796 || i
.types
[op
].bitfield
.reg16
4797 || i
.types
[op
].bitfield
.reg32
4798 || i
.types
[op
].bitfield
.reg64
4799 || i
.types
[op
].bitfield
.regmmx
4800 || i
.types
[op
].bitfield
.regxmm
4801 || i
.types
[op
].bitfield
.sreg2
4802 || i
.types
[op
].bitfield
.sreg3
4803 || i
.types
[op
].bitfield
.control
4804 || i
.types
[op
].bitfield
.debug
4805 || i
.types
[op
].bitfield
.test
)
4808 assert (op
< i
.operands
);
4810 /* If there is an extension opcode to put here, the
4811 register number must be put into the regmem field. */
4812 if (i
.tm
.extension_opcode
!= None
)
4814 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
4815 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4820 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
4821 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4826 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4827 must set it to 3 to indicate this is a register operand
4828 in the regmem field. */
4829 if (!i
.mem_operands
)
4833 /* Fill in i.rm.reg field with extension opcode (if any). */
4834 if (i
.tm
.extension_opcode
!= None
4835 && !(i
.tm
.opcode_modifier
.drex
4836 || i
.tm
.opcode_modifier
.drexv
4837 || i
.tm
.opcode_modifier
.drexc
))
4838 i
.rm
.reg
= i
.tm
.extension_opcode
;
4844 output_branch (void)
4849 relax_substateT subtype
;
4854 if (flag_code
== CODE_16BIT
)
4858 if (i
.prefix
[DATA_PREFIX
] != 0)
4864 /* Pentium4 branch hints. */
4865 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
4866 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
4871 if (i
.prefix
[REX_PREFIX
] != 0)
4877 if (i
.prefixes
!= 0 && !intel_syntax
)
4878 as_warn (_("skipping prefixes on this instruction"));
4880 /* It's always a symbol; End frag & setup for relax.
4881 Make sure there is enough room in this frag for the largest
4882 instruction we may generate in md_convert_frag. This is 2
4883 bytes for the opcode and room for the prefix and largest
4885 frag_grow (prefix
+ 2 + 4);
4886 /* Prefix and 1 opcode byte go in fr_fix. */
4887 p
= frag_more (prefix
+ 1);
4888 if (i
.prefix
[DATA_PREFIX
] != 0)
4889 *p
++ = DATA_PREFIX_OPCODE
;
4890 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
4891 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
4892 *p
++ = i
.prefix
[SEG_PREFIX
];
4893 if (i
.prefix
[REX_PREFIX
] != 0)
4894 *p
++ = i
.prefix
[REX_PREFIX
];
4895 *p
= i
.tm
.base_opcode
;
4897 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
4898 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
4899 else if (cpu_arch_flags
.bitfield
.cpui386
)
4900 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
4902 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
4905 sym
= i
.op
[0].disps
->X_add_symbol
;
4906 off
= i
.op
[0].disps
->X_add_number
;
4908 if (i
.op
[0].disps
->X_op
!= O_constant
4909 && i
.op
[0].disps
->X_op
!= O_symbol
)
4911 /* Handle complex expressions. */
4912 sym
= make_expr_symbol (i
.op
[0].disps
);
4916 /* 1 possible extra opcode + 4 byte displacement go in var part.
4917 Pass reloc in fr_var. */
4918 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
4928 if (i
.tm
.opcode_modifier
.jumpbyte
)
4930 /* This is a loop or jecxz type instruction. */
4932 if (i
.prefix
[ADDR_PREFIX
] != 0)
4934 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
4937 /* Pentium4 branch hints. */
4938 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
4939 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
4941 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
4950 if (flag_code
== CODE_16BIT
)
4953 if (i
.prefix
[DATA_PREFIX
] != 0)
4955 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
4965 if (i
.prefix
[REX_PREFIX
] != 0)
4967 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
4971 if (i
.prefixes
!= 0 && !intel_syntax
)
4972 as_warn (_("skipping prefixes on this instruction"));
4974 p
= frag_more (1 + size
);
4975 *p
++ = i
.tm
.base_opcode
;
4977 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4978 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
4980 /* All jumps handled here are signed, but don't use a signed limit
4981 check for 32 and 16 bit jumps as we want to allow wrap around at
4982 4G and 64k respectively. */
4984 fixP
->fx_signed
= 1;
4988 output_interseg_jump (void)
4996 if (flag_code
== CODE_16BIT
)
5000 if (i
.prefix
[DATA_PREFIX
] != 0)
5006 if (i
.prefix
[REX_PREFIX
] != 0)
5016 if (i
.prefixes
!= 0 && !intel_syntax
)
5017 as_warn (_("skipping prefixes on this instruction"));
5019 /* 1 opcode; 2 segment; offset */
5020 p
= frag_more (prefix
+ 1 + 2 + size
);
5022 if (i
.prefix
[DATA_PREFIX
] != 0)
5023 *p
++ = DATA_PREFIX_OPCODE
;
5025 if (i
.prefix
[REX_PREFIX
] != 0)
5026 *p
++ = i
.prefix
[REX_PREFIX
];
5028 *p
++ = i
.tm
.base_opcode
;
5029 if (i
.op
[1].imms
->X_op
== O_constant
)
5031 offsetT n
= i
.op
[1].imms
->X_add_number
;
5034 && !fits_in_unsigned_word (n
)
5035 && !fits_in_signed_word (n
))
5037 as_bad (_("16-bit jump out of range"));
5040 md_number_to_chars (p
, n
, size
);
5043 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5044 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5045 if (i
.op
[0].imms
->X_op
!= O_constant
)
5046 as_bad (_("can't handle non absolute segment in `%s'"),
5048 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5054 fragS
*insn_start_frag
;
5055 offsetT insn_start_off
;
5057 /* Tie dwarf2 debug info to the address at the start of the insn.
5058 We can't do this after the insn has been output as the current
5059 frag may have been closed off. eg. by frag_var. */
5060 dwarf2_emit_insn (0);
5062 insn_start_frag
= frag_now
;
5063 insn_start_off
= frag_now_fix ();
5066 if (i
.tm
.opcode_modifier
.jump
)
5068 else if (i
.tm
.opcode_modifier
.jumpbyte
5069 || i
.tm
.opcode_modifier
.jumpdword
)
5071 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5072 output_interseg_jump ();
5075 /* Output normal instructions here. */
5079 unsigned int prefix
;
5081 switch (i
.tm
.opcode_length
)
5084 if (i
.tm
.base_opcode
& 0xff000000)
5086 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5091 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5093 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5094 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5097 if (prefix
!= REPE_PREFIX_OPCODE
5098 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
5099 add_prefix (prefix
);
5102 add_prefix (prefix
);
5111 /* The prefix bytes. */
5112 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5114 FRAG_APPEND_1_CHAR (*q
);
5116 /* Now the opcode; be careful about word order here! */
5117 if (i
.tm
.opcode_length
== 1)
5119 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5123 switch (i
.tm
.opcode_length
)
5127 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5137 /* Put out high byte first: can't use md_number_to_chars! */
5138 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5139 *p
= i
.tm
.base_opcode
& 0xff;
5141 /* On SSE5, encode the OC1 bit in the DREX field if this
5142 encoding has multiple formats. */
5143 if (i
.tm
.opcode_modifier
.drex
5144 && i
.tm
.opcode_modifier
.drexv
5145 && DREX_OC1 (i
.tm
.extension_opcode
))
5146 *p
|= DREX_OC1_MASK
;
5149 /* Now the modrm byte and sib byte (if present). */
5150 if (i
.tm
.opcode_modifier
.modrm
)
5152 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5155 /* If i.rm.regmem == ESP (4)
5156 && i.rm.mode != (Register mode)
5158 ==> need second modrm byte. */
5159 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5161 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5162 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5164 | i
.sib
.scale
<< 6));
5167 /* Write the DREX byte if needed. */
5168 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
5171 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
5173 /* Encode the OC0 bit if this encoding has multiple
5175 if ((i
.tm
.opcode_modifier
.drex
5176 || i
.tm
.opcode_modifier
.drexv
)
5177 && DREX_OC0 (i
.tm
.extension_opcode
))
5178 *p
|= DREX_OC0_MASK
;
5181 if (i
.disp_operands
)
5182 output_disp (insn_start_frag
, insn_start_off
);
5185 output_imm (insn_start_frag
, insn_start_off
);
5191 pi ("" /*line*/, &i
);
5193 #endif /* DEBUG386 */
5196 /* Return the size of the displacement operand N. */
5199 disp_size (unsigned int n
)
5202 if (i
.types
[n
].bitfield
.disp64
)
5204 else if (i
.types
[n
].bitfield
.disp8
)
5206 else if (i
.types
[n
].bitfield
.disp16
)
5211 /* Return the size of the immediate operand N. */
5214 imm_size (unsigned int n
)
5217 if (i
.types
[n
].bitfield
.imm64
)
5219 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5221 else if (i
.types
[n
].bitfield
.imm16
)
5227 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5232 for (n
= 0; n
< i
.operands
; n
++)
5234 if (operand_type_check (i
.types
[n
], disp
))
5236 if (i
.op
[n
].disps
->X_op
== O_constant
)
5238 int size
= disp_size (n
);
5241 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5243 p
= frag_more (size
);
5244 md_number_to_chars (p
, val
, size
);
5248 enum bfd_reloc_code_real reloc_type
;
5249 int size
= disp_size (n
);
5250 int sign
= i
.types
[n
].bitfield
.disp32s
;
5251 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5253 /* We can't have 8 bit displacement here. */
5254 assert (!i
.types
[n
].bitfield
.disp8
);
5256 /* The PC relative address is computed relative
5257 to the instruction boundary, so in case immediate
5258 fields follows, we need to adjust the value. */
5259 if (pcrel
&& i
.imm_operands
)
5264 for (n1
= 0; n1
< i
.operands
; n1
++)
5265 if (operand_type_check (i
.types
[n1
], imm
))
5267 /* Only one immediate is allowed for PC
5268 relative address. */
5271 i
.op
[n
].disps
->X_add_number
-= sz
;
5273 /* We should find the immediate. */
5277 p
= frag_more (size
);
5278 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5280 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5281 && (((reloc_type
== BFD_RELOC_32
5282 || reloc_type
== BFD_RELOC_X86_64_32S
5283 || (reloc_type
== BFD_RELOC_64
5285 && (i
.op
[n
].disps
->X_op
== O_symbol
5286 || (i
.op
[n
].disps
->X_op
== O_add
5287 && ((symbol_get_value_expression
5288 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5290 || reloc_type
== BFD_RELOC_32_PCREL
))
5294 if (insn_start_frag
== frag_now
)
5295 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5300 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5301 for (fr
= insn_start_frag
->fr_next
;
5302 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5304 add
+= p
- frag_now
->fr_literal
;
5309 reloc_type
= BFD_RELOC_386_GOTPC
;
5310 i
.op
[n
].imms
->X_add_number
+= add
;
5312 else if (reloc_type
== BFD_RELOC_64
)
5313 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5315 /* Don't do the adjustment for x86-64, as there
5316 the pcrel addressing is relative to the _next_
5317 insn, and that is taken care of in other code. */
5318 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5320 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5321 i
.op
[n
].disps
, pcrel
, reloc_type
);
5328 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5333 for (n
= 0; n
< i
.operands
; n
++)
5335 if (operand_type_check (i
.types
[n
], imm
))
5337 if (i
.op
[n
].imms
->X_op
== O_constant
)
5339 int size
= imm_size (n
);
5342 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5344 p
= frag_more (size
);
5345 md_number_to_chars (p
, val
, size
);
5349 /* Not absolute_section.
5350 Need a 32-bit fixup (don't support 8bit
5351 non-absolute imms). Try to support other
5353 enum bfd_reloc_code_real reloc_type
;
5354 int size
= imm_size (n
);
5357 if (i
.types
[n
].bitfield
.imm32s
5358 && (i
.suffix
== QWORD_MNEM_SUFFIX
5359 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5364 p
= frag_more (size
);
5365 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5367 /* This is tough to explain. We end up with this one if we
5368 * have operands that look like
5369 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5370 * obtain the absolute address of the GOT, and it is strongly
5371 * preferable from a performance point of view to avoid using
5372 * a runtime relocation for this. The actual sequence of
5373 * instructions often look something like:
5378 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5380 * The call and pop essentially return the absolute address
5381 * of the label .L66 and store it in %ebx. The linker itself
5382 * will ultimately change the first operand of the addl so
5383 * that %ebx points to the GOT, but to keep things simple, the
5384 * .o file must have this operand set so that it generates not
5385 * the absolute address of .L66, but the absolute address of
5386 * itself. This allows the linker itself simply treat a GOTPC
5387 * relocation as asking for a pcrel offset to the GOT to be
5388 * added in, and the addend of the relocation is stored in the
5389 * operand field for the instruction itself.
5391 * Our job here is to fix the operand so that it would add
5392 * the correct offset so that %ebx would point to itself. The
5393 * thing that is tricky is that .-.L66 will point to the
5394 * beginning of the instruction, so we need to further modify
5395 * the operand so that it will point to itself. There are
5396 * other cases where you have something like:
5398 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5400 * and here no correction would be required. Internally in
5401 * the assembler we treat operands of this form as not being
5402 * pcrel since the '.' is explicitly mentioned, and I wonder
5403 * whether it would simplify matters to do it this way. Who
5404 * knows. In earlier versions of the PIC patches, the
5405 * pcrel_adjust field was used to store the correction, but
5406 * since the expression is not pcrel, I felt it would be
5407 * confusing to do it this way. */
5409 if ((reloc_type
== BFD_RELOC_32
5410 || reloc_type
== BFD_RELOC_X86_64_32S
5411 || reloc_type
== BFD_RELOC_64
)
5413 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5414 && (i
.op
[n
].imms
->X_op
== O_symbol
5415 || (i
.op
[n
].imms
->X_op
== O_add
5416 && ((symbol_get_value_expression
5417 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5422 if (insn_start_frag
== frag_now
)
5423 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5428 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5429 for (fr
= insn_start_frag
->fr_next
;
5430 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5432 add
+= p
- frag_now
->fr_literal
;
5436 reloc_type
= BFD_RELOC_386_GOTPC
;
5438 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5440 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5441 i
.op
[n
].imms
->X_add_number
+= add
;
5443 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5444 i
.op
[n
].imms
, 0, reloc_type
);
5450 /* x86_cons_fix_new is called via the expression parsing code when a
5451 reloc is needed. We use this hook to get the correct .got reloc. */
5452 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5453 static int cons_sign
= -1;
5456 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5459 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5461 got_reloc
= NO_RELOC
;
5464 if (exp
->X_op
== O_secrel
)
5466 exp
->X_op
= O_symbol
;
5467 r
= BFD_RELOC_32_SECREL
;
5471 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
5474 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5475 # define lex_got(reloc, adjust, types) NULL
5477 /* Parse operands of the form
5478 <symbol>@GOTOFF+<nnn>
5479 and similar .plt or .got references.
5481 If we find one, set up the correct relocation in RELOC and copy the
5482 input string, minus the `@GOTOFF' into a malloc'd buffer for
5483 parsing by the calling routine. Return this buffer, and if ADJUST
5484 is non-null set it to the length of the string we removed from the
5485 input line. Otherwise return NULL. */
5487 lex_got (enum bfd_reloc_code_real
*reloc
,
5489 i386_operand_type
*types
)
5491 /* Some of the relocations depend on the size of what field is to
5492 be relocated. But in our callers i386_immediate and i386_displacement
5493 we don't yet know the operand size (this will be set by insn
5494 matching). Hence we record the word32 relocation here,
5495 and adjust the reloc according to the real size in reloc(). */
5496 static const struct {
5498 const enum bfd_reloc_code_real rel
[2];
5499 const i386_operand_type types64
;
5502 BFD_RELOC_X86_64_PLTOFF64
},
5503 OPERAND_TYPE_IMM64
},
5504 { "PLT", { BFD_RELOC_386_PLT32
,
5505 BFD_RELOC_X86_64_PLT32
},
5506 OPERAND_TYPE_IMM32_32S_DISP32
},
5508 BFD_RELOC_X86_64_GOTPLT64
},
5509 OPERAND_TYPE_IMM64_DISP64
},
5510 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
5511 BFD_RELOC_X86_64_GOTOFF64
},
5512 OPERAND_TYPE_IMM64_DISP64
},
5514 BFD_RELOC_X86_64_GOTPCREL
},
5515 OPERAND_TYPE_IMM32_32S_DISP32
},
5516 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
5517 BFD_RELOC_X86_64_TLSGD
},
5518 OPERAND_TYPE_IMM32_32S_DISP32
},
5519 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
5521 OPERAND_TYPE_NONE
},
5523 BFD_RELOC_X86_64_TLSLD
},
5524 OPERAND_TYPE_IMM32_32S_DISP32
},
5525 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
5526 BFD_RELOC_X86_64_GOTTPOFF
},
5527 OPERAND_TYPE_IMM32_32S_DISP32
},
5528 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
5529 BFD_RELOC_X86_64_TPOFF32
},
5530 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5531 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
5533 OPERAND_TYPE_NONE
},
5534 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
5535 BFD_RELOC_X86_64_DTPOFF32
},
5537 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5538 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
5540 OPERAND_TYPE_NONE
},
5541 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
5543 OPERAND_TYPE_NONE
},
5544 { "GOT", { BFD_RELOC_386_GOT32
,
5545 BFD_RELOC_X86_64_GOT32
},
5546 OPERAND_TYPE_IMM32_32S_64_DISP32
},
5547 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
5548 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
5549 OPERAND_TYPE_IMM32_32S_DISP32
},
5550 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
5551 BFD_RELOC_X86_64_TLSDESC_CALL
},
5552 OPERAND_TYPE_IMM32_32S_DISP32
},
5560 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
5561 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
5564 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
5568 len
= strlen (gotrel
[j
].str
);
5569 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
5571 if (gotrel
[j
].rel
[object_64bit
] != 0)
5574 char *tmpbuf
, *past_reloc
;
5576 *reloc
= gotrel
[j
].rel
[object_64bit
];
5582 if (flag_code
!= CODE_64BIT
)
5584 types
->bitfield
.imm32
= 1;
5585 types
->bitfield
.disp32
= 1;
5588 *types
= gotrel
[j
].types64
;
5591 if (GOT_symbol
== NULL
)
5592 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
5594 /* The length of the first part of our input line. */
5595 first
= cp
- input_line_pointer
;
5597 /* The second part goes from after the reloc token until
5598 (and including) an end_of_line char or comma. */
5599 past_reloc
= cp
+ 1 + len
;
5601 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
5603 second
= cp
+ 1 - past_reloc
;
5605 /* Allocate and copy string. The trailing NUL shouldn't
5606 be necessary, but be safe. */
5607 tmpbuf
= xmalloc (first
+ second
+ 2);
5608 memcpy (tmpbuf
, input_line_pointer
, first
);
5609 if (second
!= 0 && *past_reloc
!= ' ')
5610 /* Replace the relocation token with ' ', so that
5611 errors like foo@GOTOFF1 will be detected. */
5612 tmpbuf
[first
++] = ' ';
5613 memcpy (tmpbuf
+ first
, past_reloc
, second
);
5614 tmpbuf
[first
+ second
] = '\0';
5618 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5619 gotrel
[j
].str
, 1 << (5 + object_64bit
));
5624 /* Might be a symbol version string. Don't as_bad here. */
5629 x86_cons (expressionS
*exp
, int size
)
5631 if (size
== 4 || (object_64bit
&& size
== 8))
5633 /* Handle @GOTOFF and the like in an expression. */
5635 char *gotfree_input_line
;
5638 save
= input_line_pointer
;
5639 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
5640 if (gotfree_input_line
)
5641 input_line_pointer
= gotfree_input_line
;
5645 if (gotfree_input_line
)
5647 /* expression () has merrily parsed up to the end of line,
5648 or a comma - in the wrong buffer. Transfer how far
5649 input_line_pointer has moved to the right buffer. */
5650 input_line_pointer
= (save
5651 + (input_line_pointer
- gotfree_input_line
)
5653 free (gotfree_input_line
);
5654 if (exp
->X_op
== O_constant
5655 || exp
->X_op
== O_absent
5656 || exp
->X_op
== O_illegal
5657 || exp
->X_op
== O_register
5658 || exp
->X_op
== O_big
)
5660 char c
= *input_line_pointer
;
5661 *input_line_pointer
= 0;
5662 as_bad (_("missing or invalid expression `%s'"), save
);
5663 *input_line_pointer
= c
;
5672 static void signed_cons (int size
)
5674 if (flag_code
== CODE_64BIT
)
5682 pe_directive_secrel (dummy
)
5683 int dummy ATTRIBUTE_UNUSED
;
5690 if (exp
.X_op
== O_symbol
)
5691 exp
.X_op
= O_secrel
;
5693 emit_expr (&exp
, 4);
5695 while (*input_line_pointer
++ == ',');
5697 input_line_pointer
--;
5698 demand_empty_rest_of_line ();
5703 i386_immediate (char *imm_start
)
5705 char *save_input_line_pointer
;
5706 char *gotfree_input_line
;
5709 i386_operand_type types
;
5711 UINTS_SET (types
, ~0);
5713 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
5715 as_bad (_("at most %d immediate operands are allowed"),
5716 MAX_IMMEDIATE_OPERANDS
);
5720 exp
= &im_expressions
[i
.imm_operands
++];
5721 i
.op
[this_operand
].imms
= exp
;
5723 if (is_space_char (*imm_start
))
5726 save_input_line_pointer
= input_line_pointer
;
5727 input_line_pointer
= imm_start
;
5729 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
5730 if (gotfree_input_line
)
5731 input_line_pointer
= gotfree_input_line
;
5733 exp_seg
= expression (exp
);
5736 if (*input_line_pointer
)
5737 as_bad (_("junk `%s' after expression"), input_line_pointer
);
5739 input_line_pointer
= save_input_line_pointer
;
5740 if (gotfree_input_line
)
5741 free (gotfree_input_line
);
5743 if (exp
->X_op
== O_absent
5744 || exp
->X_op
== O_illegal
5745 || exp
->X_op
== O_big
5746 || (gotfree_input_line
5747 && (exp
->X_op
== O_constant
5748 || exp
->X_op
== O_register
)))
5750 as_bad (_("missing or invalid immediate expression `%s'"),
5754 else if (exp
->X_op
== O_constant
)
5756 /* Size it properly later. */
5757 i
.types
[this_operand
].bitfield
.imm64
= 1;
5758 /* If BFD64, sign extend val. */
5759 if (!use_rela_relocations
5760 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
5762 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
5764 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5765 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
5766 && exp_seg
!= absolute_section
5767 && exp_seg
!= text_section
5768 && exp_seg
!= data_section
5769 && exp_seg
!= bss_section
5770 && exp_seg
!= undefined_section
5771 && !bfd_is_com_section (exp_seg
))
5773 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
5777 else if (!intel_syntax
&& exp
->X_op
== O_register
)
5779 as_bad (_("illegal immediate register operand %s"), imm_start
);
5784 /* This is an address. The size of the address will be
5785 determined later, depending on destination register,
5786 suffix, or the default for the section. */
5787 i
.types
[this_operand
].bitfield
.imm8
= 1;
5788 i
.types
[this_operand
].bitfield
.imm16
= 1;
5789 i
.types
[this_operand
].bitfield
.imm32
= 1;
5790 i
.types
[this_operand
].bitfield
.imm32s
= 1;
5791 i
.types
[this_operand
].bitfield
.imm64
= 1;
5792 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
5800 i386_scale (char *scale
)
5803 char *save
= input_line_pointer
;
5805 input_line_pointer
= scale
;
5806 val
= get_absolute_expression ();
5811 i
.log2_scale_factor
= 0;
5814 i
.log2_scale_factor
= 1;
5817 i
.log2_scale_factor
= 2;
5820 i
.log2_scale_factor
= 3;
5824 char sep
= *input_line_pointer
;
5826 *input_line_pointer
= '\0';
5827 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5829 *input_line_pointer
= sep
;
5830 input_line_pointer
= save
;
5834 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
5836 as_warn (_("scale factor of %d without an index register"),
5837 1 << i
.log2_scale_factor
);
5838 i
.log2_scale_factor
= 0;
5840 scale
= input_line_pointer
;
5841 input_line_pointer
= save
;
5846 i386_displacement (char *disp_start
, char *disp_end
)
5850 char *save_input_line_pointer
;
5851 char *gotfree_input_line
;
5853 i386_operand_type bigdisp
, types
= anydisp
;
5856 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
5858 as_bad (_("at most %d displacement operands are allowed"),
5859 MAX_MEMORY_OPERANDS
);
5863 UINTS_CLEAR (bigdisp
);
5864 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
5865 || (!current_templates
->start
->opcode_modifier
.jump
5866 && !current_templates
->start
->opcode_modifier
.jumpdword
))
5868 bigdisp
.bitfield
.disp32
= 1;
5869 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5870 if (flag_code
== CODE_64BIT
)
5874 bigdisp
.bitfield
.disp32s
= 1;
5875 bigdisp
.bitfield
.disp64
= 1;
5878 else if ((flag_code
== CODE_16BIT
) ^ override
)
5880 bigdisp
.bitfield
.disp32
= 0;
5881 bigdisp
.bitfield
.disp16
= 1;
5886 /* For PC-relative branches, the width of the displacement
5887 is dependent upon data size, not address size. */
5888 override
= (i
.prefix
[DATA_PREFIX
] != 0);
5889 if (flag_code
== CODE_64BIT
)
5891 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
5892 bigdisp
.bitfield
.disp16
= 1;
5895 bigdisp
.bitfield
.disp32
= 1;
5896 bigdisp
.bitfield
.disp32s
= 1;
5902 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
5904 : LONG_MNEM_SUFFIX
));
5905 bigdisp
.bitfield
.disp32
= 1;
5906 if ((flag_code
== CODE_16BIT
) ^ override
)
5908 bigdisp
.bitfield
.disp32
= 0;
5909 bigdisp
.bitfield
.disp16
= 1;
5913 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
5916 exp
= &disp_expressions
[i
.disp_operands
];
5917 i
.op
[this_operand
].disps
= exp
;
5919 save_input_line_pointer
= input_line_pointer
;
5920 input_line_pointer
= disp_start
;
5921 END_STRING_AND_SAVE (disp_end
);
5923 #ifndef GCC_ASM_O_HACK
5924 #define GCC_ASM_O_HACK 0
5927 END_STRING_AND_SAVE (disp_end
+ 1);
5928 if (i
.types
[this_operand
].bitfield
.baseIndex
5929 && displacement_string_end
[-1] == '+')
5931 /* This hack is to avoid a warning when using the "o"
5932 constraint within gcc asm statements.
5935 #define _set_tssldt_desc(n,addr,limit,type) \
5936 __asm__ __volatile__ ( \
5938 "movw %w1,2+%0\n\t" \
5940 "movb %b1,4+%0\n\t" \
5941 "movb %4,5+%0\n\t" \
5942 "movb $0,6+%0\n\t" \
5943 "movb %h1,7+%0\n\t" \
5945 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5947 This works great except that the output assembler ends
5948 up looking a bit weird if it turns out that there is
5949 no offset. You end up producing code that looks like:
5962 So here we provide the missing zero. */
5964 *displacement_string_end
= '0';
5967 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
5968 if (gotfree_input_line
)
5969 input_line_pointer
= gotfree_input_line
;
5971 exp_seg
= expression (exp
);
5974 if (*input_line_pointer
)
5975 as_bad (_("junk `%s' after expression"), input_line_pointer
);
5977 RESTORE_END_STRING (disp_end
+ 1);
5979 input_line_pointer
= save_input_line_pointer
;
5980 if (gotfree_input_line
)
5981 free (gotfree_input_line
);
5984 /* We do this to make sure that the section symbol is in
5985 the symbol table. We will ultimately change the relocation
5986 to be relative to the beginning of the section. */
5987 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
5988 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
5989 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
5991 if (exp
->X_op
!= O_symbol
)
5994 if (S_IS_LOCAL (exp
->X_add_symbol
)
5995 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
5996 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
5997 exp
->X_op
= O_subtract
;
5998 exp
->X_op_symbol
= GOT_symbol
;
5999 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6000 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6001 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6002 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6004 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6007 else if (exp
->X_op
== O_absent
6008 || exp
->X_op
== O_illegal
6009 || exp
->X_op
== O_big
6010 || (gotfree_input_line
6011 && (exp
->X_op
== O_constant
6012 || exp
->X_op
== O_register
)))
6015 as_bad (_("missing or invalid displacement expression `%s'"),
6020 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6021 else if (exp
->X_op
!= O_constant
6022 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6023 && exp_seg
!= absolute_section
6024 && exp_seg
!= text_section
6025 && exp_seg
!= data_section
6026 && exp_seg
!= bss_section
6027 && exp_seg
!= undefined_section
6028 && !bfd_is_com_section (exp_seg
))
6030 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6035 RESTORE_END_STRING (disp_end
);
6037 /* Check if this is a displacement only operand. */
6038 bigdisp
= i
.types
[this_operand
];
6039 bigdisp
.bitfield
.disp8
= 0;
6040 bigdisp
.bitfield
.disp16
= 0;
6041 bigdisp
.bitfield
.disp32
= 0;
6042 bigdisp
.bitfield
.disp32s
= 0;
6043 bigdisp
.bitfield
.disp64
= 0;
6044 if (UINTS_ALL_ZERO (bigdisp
))
6045 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6051 /* Make sure the memory operand we've been dealt is valid.
6052 Return 1 on success, 0 on a failure. */
6055 i386_index_check (const char *operand_string
)
6058 #if INFER_ADDR_PREFIX
6064 if (flag_code
== CODE_64BIT
)
6067 && ((i
.prefix
[ADDR_PREFIX
] == 0
6068 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6069 || (i
.prefix
[ADDR_PREFIX
]
6070 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6072 || i
.base_reg
->reg_num
!=
6073 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6075 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6076 || (i
.prefix
[ADDR_PREFIX
] == 0
6077 && i
.index_reg
->reg_num
!= RegRiz
6078 && !i
.index_reg
->reg_type
.bitfield
.reg64
6080 || (i
.prefix
[ADDR_PREFIX
]
6081 && i
.index_reg
->reg_num
!= RegEiz
6082 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6087 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6091 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6092 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6094 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6095 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6097 && i
.base_reg
->reg_num
< 6
6098 && i
.index_reg
->reg_num
>= 6
6099 && i
.log2_scale_factor
== 0))))
6106 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6108 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6109 && i
.index_reg
->reg_num
!= RegEiz
)
6110 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6116 #if INFER_ADDR_PREFIX
6117 if (i
.prefix
[ADDR_PREFIX
] == 0)
6119 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6121 /* Change the size of any displacement too. At most one of
6122 Disp16 or Disp32 is set.
6123 FIXME. There doesn't seem to be any real need for separate
6124 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6125 Removing them would probably clean up the code quite a lot. */
6126 if (flag_code
!= CODE_64BIT
6127 && (i
.types
[this_operand
].bitfield
.disp16
6128 || i
.types
[this_operand
].bitfield
.disp32
))
6129 i
.types
[this_operand
]
6130 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6135 as_bad (_("`%s' is not a valid base/index expression"),
6139 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6141 flag_code_names
[flag_code
]);
6146 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6150 i386_att_operand (char *operand_string
)
6154 char *op_string
= operand_string
;
6156 if (is_space_char (*op_string
))
6159 /* We check for an absolute prefix (differentiating,
6160 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6161 if (*op_string
== ABSOLUTE_PREFIX
)
6164 if (is_space_char (*op_string
))
6166 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6169 /* Check if operand is a register. */
6170 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6172 i386_operand_type temp
;
6174 /* Check for a segment override by searching for ':' after a
6175 segment register. */
6177 if (is_space_char (*op_string
))
6179 if (*op_string
== ':'
6180 && (r
->reg_type
.bitfield
.sreg2
6181 || r
->reg_type
.bitfield
.sreg3
))
6186 i
.seg
[i
.mem_operands
] = &es
;
6189 i
.seg
[i
.mem_operands
] = &cs
;
6192 i
.seg
[i
.mem_operands
] = &ss
;
6195 i
.seg
[i
.mem_operands
] = &ds
;
6198 i
.seg
[i
.mem_operands
] = &fs
;
6201 i
.seg
[i
.mem_operands
] = &gs
;
6205 /* Skip the ':' and whitespace. */
6207 if (is_space_char (*op_string
))
6210 if (!is_digit_char (*op_string
)
6211 && !is_identifier_char (*op_string
)
6212 && *op_string
!= '('
6213 && *op_string
!= ABSOLUTE_PREFIX
)
6215 as_bad (_("bad memory operand `%s'"), op_string
);
6218 /* Handle case of %es:*foo. */
6219 if (*op_string
== ABSOLUTE_PREFIX
)
6222 if (is_space_char (*op_string
))
6224 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6226 goto do_memory_reference
;
6230 as_bad (_("junk `%s' after register"), op_string
);
6234 temp
.bitfield
.baseindex
= 0;
6235 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6237 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6238 i
.op
[this_operand
].regs
= r
;
6241 else if (*op_string
== REGISTER_PREFIX
)
6243 as_bad (_("bad register name `%s'"), op_string
);
6246 else if (*op_string
== IMMEDIATE_PREFIX
)
6249 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6251 as_bad (_("immediate operand illegal with absolute jump"));
6254 if (!i386_immediate (op_string
))
6257 else if (is_digit_char (*op_string
)
6258 || is_identifier_char (*op_string
)
6259 || *op_string
== '(')
6261 /* This is a memory reference of some sort. */
6264 /* Start and end of displacement string expression (if found). */
6265 char *displacement_string_start
;
6266 char *displacement_string_end
;
6268 do_memory_reference
:
6269 if ((i
.mem_operands
== 1
6270 && !current_templates
->start
->opcode_modifier
.isstring
)
6271 || i
.mem_operands
== 2)
6273 as_bad (_("too many memory references for `%s'"),
6274 current_templates
->start
->name
);
6278 /* Check for base index form. We detect the base index form by
6279 looking for an ')' at the end of the operand, searching
6280 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6282 base_string
= op_string
+ strlen (op_string
);
6285 if (is_space_char (*base_string
))
6288 /* If we only have a displacement, set-up for it to be parsed later. */
6289 displacement_string_start
= op_string
;
6290 displacement_string_end
= base_string
+ 1;
6292 if (*base_string
== ')')
6295 unsigned int parens_balanced
= 1;
6296 /* We've already checked that the number of left & right ()'s are
6297 equal, so this loop will not be infinite. */
6301 if (*base_string
== ')')
6303 if (*base_string
== '(')
6306 while (parens_balanced
);
6308 temp_string
= base_string
;
6310 /* Skip past '(' and whitespace. */
6312 if (is_space_char (*base_string
))
6315 if (*base_string
== ','
6316 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6319 displacement_string_end
= temp_string
;
6321 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6325 base_string
= end_op
;
6326 if (is_space_char (*base_string
))
6330 /* There may be an index reg or scale factor here. */
6331 if (*base_string
== ',')
6334 if (is_space_char (*base_string
))
6337 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6340 base_string
= end_op
;
6341 if (is_space_char (*base_string
))
6343 if (*base_string
== ',')
6346 if (is_space_char (*base_string
))
6349 else if (*base_string
!= ')')
6351 as_bad (_("expecting `,' or `)' "
6352 "after index register in `%s'"),
6357 else if (*base_string
== REGISTER_PREFIX
)
6359 as_bad (_("bad register name `%s'"), base_string
);
6363 /* Check for scale factor. */
6364 if (*base_string
!= ')')
6366 char *end_scale
= i386_scale (base_string
);
6371 base_string
= end_scale
;
6372 if (is_space_char (*base_string
))
6374 if (*base_string
!= ')')
6376 as_bad (_("expecting `)' "
6377 "after scale factor in `%s'"),
6382 else if (!i
.index_reg
)
6384 as_bad (_("expecting index register or scale factor "
6385 "after `,'; got '%c'"),
6390 else if (*base_string
!= ')')
6392 as_bad (_("expecting `,' or `)' "
6393 "after base register in `%s'"),
6398 else if (*base_string
== REGISTER_PREFIX
)
6400 as_bad (_("bad register name `%s'"), base_string
);
6405 /* If there's an expression beginning the operand, parse it,
6406 assuming displacement_string_start and
6407 displacement_string_end are meaningful. */
6408 if (displacement_string_start
!= displacement_string_end
)
6410 if (!i386_displacement (displacement_string_start
,
6411 displacement_string_end
))
6415 /* Special case for (%dx) while doing input/output op. */
6417 && UINTS_EQUAL (i
.base_reg
->reg_type
, reg16_inoutportreg
)
6419 && i
.log2_scale_factor
== 0
6420 && i
.seg
[i
.mem_operands
] == 0
6421 && !operand_type_check (i
.types
[this_operand
], disp
))
6423 UINTS_CLEAR (i
.types
[this_operand
]);
6424 i
.types
[this_operand
].bitfield
.inoutportreg
= 1;
6428 if (i386_index_check (operand_string
) == 0)
6430 i
.types
[this_operand
].bitfield
.mem
= 1;
6435 /* It's not a memory operand; argh! */
6436 as_bad (_("invalid char %s beginning operand %d `%s'"),
6437 output_invalid (*op_string
),
6442 return 1; /* Normal return. */
6445 /* md_estimate_size_before_relax()
6447 Called just before relax() for rs_machine_dependent frags. The x86
6448 assembler uses these frags to handle variable size jump
6451 Any symbol that is now undefined will not become defined.
6452 Return the correct fr_subtype in the frag.
6453 Return the initial "guess for variable size of frag" to caller.
6454 The guess is actually the growth beyond the fixed part. Whatever
6455 we do to grow the fixed or variable part contributes to our
6459 md_estimate_size_before_relax (fragP
, segment
)
6463 /* We've already got fragP->fr_subtype right; all we have to do is
6464 check for un-relaxable symbols. On an ELF system, we can't relax
6465 an externally visible symbol, because it may be overridden by a
6467 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
6468 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6470 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
6471 || S_IS_WEAK (fragP
->fr_symbol
)))
6475 /* Symbol is undefined in this segment, or we need to keep a
6476 reloc so that weak symbols can be overridden. */
6477 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
6478 enum bfd_reloc_code_real reloc_type
;
6479 unsigned char *opcode
;
6482 if (fragP
->fr_var
!= NO_RELOC
)
6483 reloc_type
= fragP
->fr_var
;
6485 reloc_type
= BFD_RELOC_16_PCREL
;
6487 reloc_type
= BFD_RELOC_32_PCREL
;
6489 old_fr_fix
= fragP
->fr_fix
;
6490 opcode
= (unsigned char *) fragP
->fr_opcode
;
6492 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
6495 /* Make jmp (0xeb) a (d)word displacement jump. */
6497 fragP
->fr_fix
+= size
;
6498 fix_new (fragP
, old_fr_fix
, size
,
6500 fragP
->fr_offset
, 1,
6506 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
6508 /* Negate the condition, and branch past an
6509 unconditional jump. */
6512 /* Insert an unconditional jump. */
6514 /* We added two extra opcode bytes, and have a two byte
6516 fragP
->fr_fix
+= 2 + 2;
6517 fix_new (fragP
, old_fr_fix
+ 2, 2,
6519 fragP
->fr_offset
, 1,
6526 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
6531 fixP
= fix_new (fragP
, old_fr_fix
, 1,
6533 fragP
->fr_offset
, 1,
6535 fixP
->fx_signed
= 1;
6539 /* This changes the byte-displacement jump 0x7N
6540 to the (d)word-displacement jump 0x0f,0x8N. */
6541 opcode
[1] = opcode
[0] + 0x10;
6542 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6543 /* We've added an opcode byte. */
6544 fragP
->fr_fix
+= 1 + size
;
6545 fix_new (fragP
, old_fr_fix
+ 1, size
,
6547 fragP
->fr_offset
, 1,
6552 BAD_CASE (fragP
->fr_subtype
);
6556 return fragP
->fr_fix
- old_fr_fix
;
6559 /* Guess size depending on current relax state. Initially the relax
6560 state will correspond to a short jump and we return 1, because
6561 the variable part of the frag (the branch offset) is one byte
6562 long. However, we can relax a section more than once and in that
6563 case we must either set fr_subtype back to the unrelaxed state,
6564 or return the value for the appropriate branch. */
6565 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
6568 /* Called after relax() is finished.
6570 In: Address of frag.
6571 fr_type == rs_machine_dependent.
6572 fr_subtype is what the address relaxed to.
6574 Out: Any fixSs and constants are set up.
6575 Caller will turn frag into a ".space 0". */
6578 md_convert_frag (abfd
, sec
, fragP
)
6579 bfd
*abfd ATTRIBUTE_UNUSED
;
6580 segT sec ATTRIBUTE_UNUSED
;
6583 unsigned char *opcode
;
6584 unsigned char *where_to_put_displacement
= NULL
;
6585 offsetT target_address
;
6586 offsetT opcode_address
;
6587 unsigned int extension
= 0;
6588 offsetT displacement_from_opcode_start
;
6590 opcode
= (unsigned char *) fragP
->fr_opcode
;
6592 /* Address we want to reach in file space. */
6593 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
6595 /* Address opcode resides at in file space. */
6596 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
6598 /* Displacement from opcode start to fill into instruction. */
6599 displacement_from_opcode_start
= target_address
- opcode_address
;
6601 if ((fragP
->fr_subtype
& BIG
) == 0)
6603 /* Don't have to change opcode. */
6604 extension
= 1; /* 1 opcode + 1 displacement */
6605 where_to_put_displacement
= &opcode
[1];
6609 if (no_cond_jump_promotion
6610 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
6611 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
6612 _("long jump required"));
6614 switch (fragP
->fr_subtype
)
6616 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
6617 extension
= 4; /* 1 opcode + 4 displacement */
6619 where_to_put_displacement
= &opcode
[1];
6622 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
6623 extension
= 2; /* 1 opcode + 2 displacement */
6625 where_to_put_displacement
= &opcode
[1];
6628 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
6629 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
6630 extension
= 5; /* 2 opcode + 4 displacement */
6631 opcode
[1] = opcode
[0] + 0x10;
6632 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6633 where_to_put_displacement
= &opcode
[2];
6636 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
6637 extension
= 3; /* 2 opcode + 2 displacement */
6638 opcode
[1] = opcode
[0] + 0x10;
6639 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6640 where_to_put_displacement
= &opcode
[2];
6643 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
6648 where_to_put_displacement
= &opcode
[3];
6652 BAD_CASE (fragP
->fr_subtype
);
6657 /* If size if less then four we are sure that the operand fits,
6658 but if it's 4, then it could be that the displacement is larger
6660 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
6662 && ((addressT
) (displacement_from_opcode_start
- extension
6663 + ((addressT
) 1 << 31))
6664 > (((addressT
) 2 << 31) - 1)))
6666 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
6667 _("jump target out of range"));
6668 /* Make us emit 0. */
6669 displacement_from_opcode_start
= extension
;
6671 /* Now put displacement after opcode. */
6672 md_number_to_chars ((char *) where_to_put_displacement
,
6673 (valueT
) (displacement_from_opcode_start
- extension
),
6674 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
6675 fragP
->fr_fix
+= extension
;
6678 /* Apply a fixup (fixS) to segment data, once it has been determined
6679 by our caller that we have all the info we need to fix it up.
6681 On the 386, immediates, displacements, and data pointers are all in
6682 the same (little-endian) format, so we don't need to care about which
6686 md_apply_fix (fixP
, valP
, seg
)
6687 /* The fix we're to put in. */
6689 /* Pointer to the value of the bits. */
6691 /* Segment fix is from. */
6692 segT seg ATTRIBUTE_UNUSED
;
6694 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6695 valueT value
= *valP
;
6697 #if !defined (TE_Mach)
6700 switch (fixP
->fx_r_type
)
6706 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
6709 case BFD_RELOC_X86_64_32S
:
6710 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
6713 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
6716 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
6721 if (fixP
->fx_addsy
!= NULL
6722 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
6723 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
6724 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
6725 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
6726 && !use_rela_relocations
)
6728 /* This is a hack. There should be a better way to handle this.
6729 This covers for the fact that bfd_install_relocation will
6730 subtract the current location (for partial_inplace, PC relative
6731 relocations); see more below. */
6735 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
6738 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6740 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6743 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
6746 || (symbol_section_p (fixP
->fx_addsy
)
6747 && sym_seg
!= absolute_section
))
6748 && !generic_force_reloc (fixP
))
6750 /* Yes, we add the values in twice. This is because
6751 bfd_install_relocation subtracts them out again. I think
6752 bfd_install_relocation is broken, but I don't dare change
6754 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6758 #if defined (OBJ_COFF) && defined (TE_PE)
6759 /* For some reason, the PE format does not store a
6760 section address offset for a PC relative symbol. */
6761 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
6762 || S_IS_WEAK (fixP
->fx_addsy
))
6763 value
+= md_pcrel_from (fixP
);
6767 /* Fix a few things - the dynamic linker expects certain values here,
6768 and we must not disappoint it. */
6769 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6770 if (IS_ELF
&& fixP
->fx_addsy
)
6771 switch (fixP
->fx_r_type
)
6773 case BFD_RELOC_386_PLT32
:
6774 case BFD_RELOC_X86_64_PLT32
:
6775 /* Make the jump instruction point to the address of the operand. At
6776 runtime we merely add the offset to the actual PLT entry. */
6780 case BFD_RELOC_386_TLS_GD
:
6781 case BFD_RELOC_386_TLS_LDM
:
6782 case BFD_RELOC_386_TLS_IE_32
:
6783 case BFD_RELOC_386_TLS_IE
:
6784 case BFD_RELOC_386_TLS_GOTIE
:
6785 case BFD_RELOC_386_TLS_GOTDESC
:
6786 case BFD_RELOC_X86_64_TLSGD
:
6787 case BFD_RELOC_X86_64_TLSLD
:
6788 case BFD_RELOC_X86_64_GOTTPOFF
:
6789 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6790 value
= 0; /* Fully resolved at runtime. No addend. */
6792 case BFD_RELOC_386_TLS_LE
:
6793 case BFD_RELOC_386_TLS_LDO_32
:
6794 case BFD_RELOC_386_TLS_LE_32
:
6795 case BFD_RELOC_X86_64_DTPOFF32
:
6796 case BFD_RELOC_X86_64_DTPOFF64
:
6797 case BFD_RELOC_X86_64_TPOFF32
:
6798 case BFD_RELOC_X86_64_TPOFF64
:
6799 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6802 case BFD_RELOC_386_TLS_DESC_CALL
:
6803 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6804 value
= 0; /* Fully resolved at runtime. No addend. */
6805 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6809 case BFD_RELOC_386_GOT32
:
6810 case BFD_RELOC_X86_64_GOT32
:
6811 value
= 0; /* Fully resolved at runtime. No addend. */
6814 case BFD_RELOC_VTABLE_INHERIT
:
6815 case BFD_RELOC_VTABLE_ENTRY
:
6822 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6824 #endif /* !defined (TE_Mach) */
6826 /* Are we finished with this relocation now? */
6827 if (fixP
->fx_addsy
== NULL
)
6829 else if (use_rela_relocations
)
6831 fixP
->fx_no_overflow
= 1;
6832 /* Remember value for tc_gen_reloc. */
6833 fixP
->fx_addnumber
= value
;
6837 md_number_to_chars (p
, value
, fixP
->fx_size
);
6841 md_atof (int type
, char *litP
, int *sizeP
)
6843 /* This outputs the LITTLENUMs in REVERSE order;
6844 in accord with the bigendian 386. */
6845 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
6848 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
6851 output_invalid (int c
)
6854 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
6857 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
6858 "(0x%x)", (unsigned char) c
);
6859 return output_invalid_buf
;
6862 /* REG_STRING starts *before* REGISTER_PREFIX. */
6864 static const reg_entry
*
6865 parse_real_register (char *reg_string
, char **end_op
)
6867 char *s
= reg_string
;
6869 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
6872 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6873 if (*s
== REGISTER_PREFIX
)
6876 if (is_space_char (*s
))
6880 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
6882 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
6883 return (const reg_entry
*) NULL
;
6887 /* For naked regs, make sure that we are not dealing with an identifier.
6888 This prevents confusing an identifier like `eax_var' with register
6890 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
6891 return (const reg_entry
*) NULL
;
6895 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
6897 /* Handle floating point regs, allowing spaces in the (i) part. */
6898 if (r
== i386_regtab
/* %st is first entry of table */)
6900 if (is_space_char (*s
))
6905 if (is_space_char (*s
))
6907 if (*s
>= '0' && *s
<= '7')
6911 if (is_space_char (*s
))
6916 r
= hash_find (reg_hash
, "st(0)");
6921 /* We have "%st(" then garbage. */
6922 return (const reg_entry
*) NULL
;
6926 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6929 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
6930 return (const reg_entry
*) NULL
;
6933 && ((r
->reg_flags
& (RegRex64
| RegRex
))
6934 || r
->reg_type
.bitfield
.reg64
)
6935 && (!cpu_arch_flags
.bitfield
.cpulm
6936 || !UINTS_EQUAL (r
->reg_type
, control
))
6937 && flag_code
!= CODE_64BIT
)
6938 return (const reg_entry
*) NULL
;
6943 /* REG_STRING starts *before* REGISTER_PREFIX. */
6945 static const reg_entry
*
6946 parse_register (char *reg_string
, char **end_op
)
6950 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6951 r
= parse_real_register (reg_string
, end_op
);
6956 char *save
= input_line_pointer
;
6960 input_line_pointer
= reg_string
;
6961 c
= get_symbol_end ();
6962 symbolP
= symbol_find (reg_string
);
6963 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
6965 const expressionS
*e
= symbol_get_value_expression (symbolP
);
6967 know (e
->X_op
== O_register
);
6968 know (e
->X_add_number
>= 0
6969 && (valueT
) e
->X_add_number
< i386_regtab_size
);
6970 r
= i386_regtab
+ e
->X_add_number
;
6971 *end_op
= input_line_pointer
;
6973 *input_line_pointer
= c
;
6974 input_line_pointer
= save
;
6980 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
6983 char *end
= input_line_pointer
;
6986 r
= parse_register (name
, &input_line_pointer
);
6987 if (r
&& end
<= input_line_pointer
)
6989 *nextcharP
= *input_line_pointer
;
6990 *input_line_pointer
= 0;
6991 e
->X_op
= O_register
;
6992 e
->X_add_number
= r
- i386_regtab
;
6995 input_line_pointer
= end
;
7001 md_operand (expressionS
*e
)
7003 if (*input_line_pointer
== REGISTER_PREFIX
)
7006 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
7010 e
->X_op
= O_register
;
7011 e
->X_add_number
= r
- i386_regtab
;
7012 input_line_pointer
= end
;
7018 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7019 const char *md_shortopts
= "kVQ:sqn";
7021 const char *md_shortopts
= "qn";
7024 #define OPTION_32 (OPTION_MD_BASE + 0)
7025 #define OPTION_64 (OPTION_MD_BASE + 1)
7026 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7027 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7028 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7029 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7030 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7031 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7032 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7033 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7035 struct option md_longopts
[] =
7037 {"32", no_argument
, NULL
, OPTION_32
},
7038 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7039 {"64", no_argument
, NULL
, OPTION_64
},
7041 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7042 {"march", required_argument
, NULL
, OPTION_MARCH
},
7043 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7044 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7045 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7046 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7047 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7048 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7049 {NULL
, no_argument
, NULL
, 0}
7051 size_t md_longopts_size
= sizeof (md_longopts
);
7054 md_parse_option (int c
, char *arg
)
7061 optimize_align_code
= 0;
7068 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7069 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7070 should be emitted or not. FIXME: Not implemented. */
7074 /* -V: SVR4 argument to print version ID. */
7076 print_version_id ();
7079 /* -k: Ignore for FreeBSD compatibility. */
7084 /* -s: On i386 Solaris, this tells the native assembler to use
7085 .stab instead of .stab.excl. We always use .stab anyhow. */
7088 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7091 const char **list
, **l
;
7093 list
= bfd_target_list ();
7094 for (l
= list
; *l
!= NULL
; l
++)
7095 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7096 || strcmp (*l
, "coff-x86-64") == 0
7097 || strcmp (*l
, "pe-x86-64") == 0
7098 || strcmp (*l
, "pei-x86-64") == 0)
7100 default_arch
= "x86_64";
7104 as_fatal (_("No compiled in support for x86_64"));
7111 default_arch
= "i386";
7115 #ifdef SVR4_COMMENT_CHARS
7120 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7122 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7126 i386_comment_chars
= n
;
7133 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7134 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7136 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7138 cpu_arch_isa
= cpu_arch
[i
].type
;
7139 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7140 if (!cpu_arch_tune_set
)
7142 cpu_arch_tune
= cpu_arch_isa
;
7143 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7148 if (i
>= ARRAY_SIZE (cpu_arch
))
7149 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7154 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7155 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7157 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7159 cpu_arch_tune_set
= 1;
7160 cpu_arch_tune
= cpu_arch
[i
].type
;
7161 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7165 if (i
>= ARRAY_SIZE (cpu_arch
))
7166 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7169 case OPTION_MMNEMONIC
:
7170 if (strcasecmp (arg
, "att") == 0)
7172 else if (strcasecmp (arg
, "intel") == 0)
7175 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7178 case OPTION_MSYNTAX
:
7179 if (strcasecmp (arg
, "att") == 0)
7181 else if (strcasecmp (arg
, "intel") == 0)
7184 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7187 case OPTION_MINDEX_REG
:
7188 allow_index_reg
= 1;
7191 case OPTION_MNAKED_REG
:
7192 allow_naked_reg
= 1;
7195 case OPTION_MOLD_GCC
:
7206 md_show_usage (stream
)
7209 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7210 fprintf (stream
, _("\
7212 -V print assembler version number\n\
7215 fprintf (stream
, _("\
7216 -n Do not optimize code alignment\n\
7217 -q quieten some warnings\n"));
7218 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7219 fprintf (stream
, _("\
7222 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7223 fprintf (stream
, _("\
7224 --32/--64 generate 32bit/64bit code\n"));
7226 #ifdef SVR4_COMMENT_CHARS
7227 fprintf (stream
, _("\
7228 --divide do not treat `/' as a comment character\n"));
7230 fprintf (stream
, _("\
7231 --divide ignored\n"));
7233 fprintf (stream
, _("\
7234 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7235 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7236 core, core2, k6, athlon, k8, generic32, generic64\n"));
7237 fprintf (stream
, _("\
7238 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7239 fprintf (stream
, _("\
7240 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7241 fprintf (stream
, _("\
7242 -mindex-reg support pseudo index registers\n"));
7243 fprintf (stream
, _("\
7244 -mnaked-reg don't require `%%' prefix for registers\n"));
7245 fprintf (stream
, _("\
7246 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7249 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7250 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7252 /* Pick the target format to use. */
7255 i386_target_format (void)
7257 if (!strcmp (default_arch
, "x86_64"))
7259 set_code_flag (CODE_64BIT
);
7260 if (UINTS_ALL_ZERO (cpu_arch_isa_flags
))
7262 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7263 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7264 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7265 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
7266 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
7267 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
7268 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
7269 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
7270 cpu_arch_isa_flags
.bitfield
.cpummx2
= 1;
7271 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
7272 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
7274 if (UINTS_ALL_ZERO (cpu_arch_tune_flags
))
7276 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7277 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7278 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7279 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
7280 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
7281 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
7282 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
7283 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
7284 cpu_arch_tune_flags
.bitfield
.cpummx2
= 1;
7285 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
7286 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
7289 else if (!strcmp (default_arch
, "i386"))
7291 set_code_flag (CODE_32BIT
);
7292 if (UINTS_ALL_ZERO (cpu_arch_isa_flags
))
7294 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7295 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7296 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7298 if (UINTS_ALL_ZERO (cpu_arch_tune_flags
))
7300 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7301 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7302 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7306 as_fatal (_("Unknown architecture"));
7307 switch (OUTPUT_FLAVOR
)
7310 case bfd_target_coff_flavour
:
7311 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "coff-i386";
7314 #ifdef OBJ_MAYBE_AOUT
7315 case bfd_target_aout_flavour
:
7316 return AOUT_TARGET_FORMAT
;
7318 #ifdef OBJ_MAYBE_COFF
7319 case bfd_target_coff_flavour
:
7322 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7323 case bfd_target_elf_flavour
:
7325 if (flag_code
== CODE_64BIT
)
7328 use_rela_relocations
= 1;
7330 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
7339 #endif /* OBJ_MAYBE_ more than one */
7341 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7343 i386_elf_emit_arch_note (void)
7345 if (IS_ELF
&& cpu_arch_name
!= NULL
)
7348 asection
*seg
= now_seg
;
7349 subsegT subseg
= now_subseg
;
7350 Elf_Internal_Note i_note
;
7351 Elf_External_Note e_note
;
7352 asection
*note_secp
;
7355 /* Create the .note section. */
7356 note_secp
= subseg_new (".note", 0);
7357 bfd_set_section_flags (stdoutput
,
7359 SEC_HAS_CONTENTS
| SEC_READONLY
);
7361 /* Process the arch string. */
7362 len
= strlen (cpu_arch_name
);
7364 i_note
.namesz
= len
+ 1;
7366 i_note
.type
= NT_ARCH
;
7367 p
= frag_more (sizeof (e_note
.namesz
));
7368 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
7369 p
= frag_more (sizeof (e_note
.descsz
));
7370 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
7371 p
= frag_more (sizeof (e_note
.type
));
7372 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
7373 p
= frag_more (len
+ 1);
7374 strcpy (p
, cpu_arch_name
);
7376 frag_align (2, 0, 0);
7378 subseg_set (seg
, subseg
);
7384 md_undefined_symbol (name
)
7387 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
7388 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
7389 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
7390 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
7394 if (symbol_find (name
))
7395 as_bad (_("GOT already in symbol table"));
7396 GOT_symbol
= symbol_new (name
, undefined_section
,
7397 (valueT
) 0, &zero_address_frag
);
7404 /* Round up a section size to the appropriate boundary. */
7407 md_section_align (segment
, size
)
7408 segT segment ATTRIBUTE_UNUSED
;
7411 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7412 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
7414 /* For a.out, force the section size to be aligned. If we don't do
7415 this, BFD will align it for us, but it will not write out the
7416 final bytes of the section. This may be a bug in BFD, but it is
7417 easier to fix it here since that is how the other a.out targets
7421 align
= bfd_get_section_alignment (stdoutput
, segment
);
7422 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7429 /* On the i386, PC-relative offsets are relative to the start of the
7430 next instruction. That is, the address of the offset, plus its
7431 size, since the offset is always the last part of the insn. */
7434 md_pcrel_from (fixS
*fixP
)
7436 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7442 s_bss (int ignore ATTRIBUTE_UNUSED
)
7446 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7448 obj_elf_section_change_hook ();
7450 temp
= get_absolute_expression ();
7451 subseg_set (bss_section
, (subsegT
) temp
);
7452 demand_empty_rest_of_line ();
7458 i386_validate_fix (fixS
*fixp
)
7460 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
7462 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
7466 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
7471 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
7473 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
7480 tc_gen_reloc (section
, fixp
)
7481 asection
*section ATTRIBUTE_UNUSED
;
7485 bfd_reloc_code_real_type code
;
7487 switch (fixp
->fx_r_type
)
7489 case BFD_RELOC_X86_64_PLT32
:
7490 case BFD_RELOC_X86_64_GOT32
:
7491 case BFD_RELOC_X86_64_GOTPCREL
:
7492 case BFD_RELOC_386_PLT32
:
7493 case BFD_RELOC_386_GOT32
:
7494 case BFD_RELOC_386_GOTOFF
:
7495 case BFD_RELOC_386_GOTPC
:
7496 case BFD_RELOC_386_TLS_GD
:
7497 case BFD_RELOC_386_TLS_LDM
:
7498 case BFD_RELOC_386_TLS_LDO_32
:
7499 case BFD_RELOC_386_TLS_IE_32
:
7500 case BFD_RELOC_386_TLS_IE
:
7501 case BFD_RELOC_386_TLS_GOTIE
:
7502 case BFD_RELOC_386_TLS_LE_32
:
7503 case BFD_RELOC_386_TLS_LE
:
7504 case BFD_RELOC_386_TLS_GOTDESC
:
7505 case BFD_RELOC_386_TLS_DESC_CALL
:
7506 case BFD_RELOC_X86_64_TLSGD
:
7507 case BFD_RELOC_X86_64_TLSLD
:
7508 case BFD_RELOC_X86_64_DTPOFF32
:
7509 case BFD_RELOC_X86_64_DTPOFF64
:
7510 case BFD_RELOC_X86_64_GOTTPOFF
:
7511 case BFD_RELOC_X86_64_TPOFF32
:
7512 case BFD_RELOC_X86_64_TPOFF64
:
7513 case BFD_RELOC_X86_64_GOTOFF64
:
7514 case BFD_RELOC_X86_64_GOTPC32
:
7515 case BFD_RELOC_X86_64_GOT64
:
7516 case BFD_RELOC_X86_64_GOTPCREL64
:
7517 case BFD_RELOC_X86_64_GOTPC64
:
7518 case BFD_RELOC_X86_64_GOTPLT64
:
7519 case BFD_RELOC_X86_64_PLTOFF64
:
7520 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7521 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7523 case BFD_RELOC_VTABLE_ENTRY
:
7524 case BFD_RELOC_VTABLE_INHERIT
:
7526 case BFD_RELOC_32_SECREL
:
7528 code
= fixp
->fx_r_type
;
7530 case BFD_RELOC_X86_64_32S
:
7531 if (!fixp
->fx_pcrel
)
7533 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7534 code
= fixp
->fx_r_type
;
7540 switch (fixp
->fx_size
)
7543 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7544 _("can not do %d byte pc-relative relocation"),
7546 code
= BFD_RELOC_32_PCREL
;
7548 case 1: code
= BFD_RELOC_8_PCREL
; break;
7549 case 2: code
= BFD_RELOC_16_PCREL
; break;
7550 case 4: code
= BFD_RELOC_32_PCREL
; break;
7552 case 8: code
= BFD_RELOC_64_PCREL
; break;
7558 switch (fixp
->fx_size
)
7561 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7562 _("can not do %d byte relocation"),
7564 code
= BFD_RELOC_32
;
7566 case 1: code
= BFD_RELOC_8
; break;
7567 case 2: code
= BFD_RELOC_16
; break;
7568 case 4: code
= BFD_RELOC_32
; break;
7570 case 8: code
= BFD_RELOC_64
; break;
7577 if ((code
== BFD_RELOC_32
7578 || code
== BFD_RELOC_32_PCREL
7579 || code
== BFD_RELOC_X86_64_32S
)
7581 && fixp
->fx_addsy
== GOT_symbol
)
7584 code
= BFD_RELOC_386_GOTPC
;
7586 code
= BFD_RELOC_X86_64_GOTPC32
;
7588 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
7590 && fixp
->fx_addsy
== GOT_symbol
)
7592 code
= BFD_RELOC_X86_64_GOTPC64
;
7595 rel
= (arelent
*) xmalloc (sizeof (arelent
));
7596 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
7597 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7599 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7601 if (!use_rela_relocations
)
7603 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7604 vtable entry to be used in the relocation's section offset. */
7605 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
7606 rel
->address
= fixp
->fx_offset
;
7610 /* Use the rela in 64bit mode. */
7613 if (!fixp
->fx_pcrel
)
7614 rel
->addend
= fixp
->fx_offset
;
7618 case BFD_RELOC_X86_64_PLT32
:
7619 case BFD_RELOC_X86_64_GOT32
:
7620 case BFD_RELOC_X86_64_GOTPCREL
:
7621 case BFD_RELOC_X86_64_TLSGD
:
7622 case BFD_RELOC_X86_64_TLSLD
:
7623 case BFD_RELOC_X86_64_GOTTPOFF
:
7624 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7625 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7626 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
7629 rel
->addend
= (section
->vma
7631 + fixp
->fx_addnumber
7632 + md_pcrel_from (fixp
));
7637 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7638 if (rel
->howto
== NULL
)
7640 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7641 _("cannot represent relocation type %s"),
7642 bfd_get_reloc_code_name (code
));
7643 /* Set howto to a garbage value so that we can keep going. */
7644 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
7645 assert (rel
->howto
!= NULL
);
7652 /* Parse operands using Intel syntax. This implements a recursive descent
7653 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7656 FIXME: We do not recognize the full operand grammar defined in the MASM
7657 documentation. In particular, all the structure/union and
7658 high-level macro operands are missing.
7660 Uppercase words are terminals, lower case words are non-terminals.
7661 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7662 bars '|' denote choices. Most grammar productions are implemented in
7663 functions called 'intel_<production>'.
7665 Initial production is 'expr'.
7671 binOp & | AND | \| | OR | ^ | XOR
7673 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7675 constant digits [[ radixOverride ]]
7677 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7715 => expr expr cmpOp e04
7718 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7719 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7721 hexdigit a | b | c | d | e | f
7722 | A | B | C | D | E | F
7728 mulOp * | / | % | MOD | << | SHL | >> | SHR
7732 register specialRegister
7736 segmentRegister CS | DS | ES | FS | GS | SS
7738 specialRegister CR0 | CR2 | CR3 | CR4
7739 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7740 | TR3 | TR4 | TR5 | TR6 | TR7
7742 We simplify the grammar in obvious places (e.g., register parsing is
7743 done by calling parse_register) and eliminate immediate left recursion
7744 to implement a recursive-descent parser.
7748 expr' cmpOp e04 expr'
7799 /* Parsing structure for the intel syntax parser. Used to implement the
7800 semantic actions for the operand grammar. */
7801 struct intel_parser_s
7803 char *op_string
; /* The string being parsed. */
7804 int got_a_float
; /* Whether the operand is a float. */
7805 int op_modifier
; /* Operand modifier. */
7806 int is_mem
; /* 1 if operand is memory reference. */
7807 int in_offset
; /* >=1 if parsing operand of offset. */
7808 int in_bracket
; /* >=1 if parsing operand in brackets. */
7809 const reg_entry
*reg
; /* Last register reference found. */
7810 char *disp
; /* Displacement string being built. */
7811 char *next_operand
; /* Resume point when splitting operands. */
7814 static struct intel_parser_s intel_parser
;
7816 /* Token structure for parsing intel syntax. */
7819 int code
; /* Token code. */
7820 const reg_entry
*reg
; /* Register entry for register tokens. */
7821 char *str
; /* String representation. */
7824 static struct intel_token cur_token
, prev_token
;
7826 /* Token codes for the intel parser. Since T_SHORT is already used
7827 by COFF, undefine it first to prevent a warning. */
7846 /* Prototypes for intel parser functions. */
7847 static int intel_match_token (int);
7848 static void intel_putback_token (void);
7849 static void intel_get_token (void);
7850 static int intel_expr (void);
7851 static int intel_e04 (void);
7852 static int intel_e05 (void);
7853 static int intel_e06 (void);
7854 static int intel_e09 (void);
7855 static int intel_e10 (void);
7856 static int intel_e11 (void);
7859 i386_intel_operand (char *operand_string
, int got_a_float
)
7864 p
= intel_parser
.op_string
= xstrdup (operand_string
);
7865 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
7869 /* Initialize token holders. */
7870 cur_token
.code
= prev_token
.code
= T_NIL
;
7871 cur_token
.reg
= prev_token
.reg
= NULL
;
7872 cur_token
.str
= prev_token
.str
= NULL
;
7874 /* Initialize parser structure. */
7875 intel_parser
.got_a_float
= got_a_float
;
7876 intel_parser
.op_modifier
= 0;
7877 intel_parser
.is_mem
= 0;
7878 intel_parser
.in_offset
= 0;
7879 intel_parser
.in_bracket
= 0;
7880 intel_parser
.reg
= NULL
;
7881 intel_parser
.disp
[0] = '\0';
7882 intel_parser
.next_operand
= NULL
;
7884 /* Read the first token and start the parser. */
7886 ret
= intel_expr ();
7891 if (cur_token
.code
!= T_NIL
)
7893 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7894 current_templates
->start
->name
, cur_token
.str
);
7897 /* If we found a memory reference, hand it over to i386_displacement
7898 to fill in the rest of the operand fields. */
7899 else if (intel_parser
.is_mem
)
7901 if ((i
.mem_operands
== 1
7902 && !current_templates
->start
->opcode_modifier
.isstring
)
7903 || i
.mem_operands
== 2)
7905 as_bad (_("too many memory references for '%s'"),
7906 current_templates
->start
->name
);
7911 char *s
= intel_parser
.disp
;
7912 i
.types
[this_operand
].bitfield
.mem
= 1;
7915 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
7916 /* See the comments in intel_bracket_expr. */
7917 as_warn (_("Treating `%s' as memory reference"), operand_string
);
7919 /* Add the displacement expression. */
7921 ret
= i386_displacement (s
, s
+ strlen (s
));
7924 /* Swap base and index in 16-bit memory operands like
7925 [si+bx]. Since i386_index_check is also used in AT&T
7926 mode we have to do that here. */
7929 && i
.base_reg
->reg_type
.bitfield
.reg16
7930 && i
.index_reg
->reg_type
.bitfield
.reg16
7931 && i
.base_reg
->reg_num
>= 6
7932 && i
.index_reg
->reg_num
< 6)
7934 const reg_entry
*base
= i
.index_reg
;
7936 i
.index_reg
= i
.base_reg
;
7939 ret
= i386_index_check (operand_string
);
7944 /* Constant and OFFSET expressions are handled by i386_immediate. */
7945 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
7946 || intel_parser
.reg
== NULL
)
7947 ret
= i386_immediate (intel_parser
.disp
);
7949 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
7951 if (!ret
|| !intel_parser
.next_operand
)
7953 intel_parser
.op_string
= intel_parser
.next_operand
;
7954 this_operand
= i
.operands
++;
7955 i
.types
[this_operand
].bitfield
.unspecified
= 1;
7959 free (intel_parser
.disp
);
7964 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7968 expr' cmpOp e04 expr'
7973 /* XXX Implement the comparison operators. */
7974 return intel_e04 ();
7991 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7992 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
7994 if (cur_token
.code
== '+')
7996 else if (cur_token
.code
== '-')
7997 nregs
= NUM_ADDRESS_REGS
;
8001 strcat (intel_parser
.disp
, cur_token
.str
);
8002 intel_match_token (cur_token
.code
);
8013 int nregs
= ~NUM_ADDRESS_REGS
;
8020 if (cur_token
.code
== '&'
8021 || cur_token
.code
== '|'
8022 || cur_token
.code
== '^')
8026 str
[0] = cur_token
.code
;
8028 strcat (intel_parser
.disp
, str
);
8033 intel_match_token (cur_token
.code
);
8038 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8039 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
8050 int nregs
= ~NUM_ADDRESS_REGS
;
8057 if (cur_token
.code
== '*'
8058 || cur_token
.code
== '/'
8059 || cur_token
.code
== '%')
8063 str
[0] = cur_token
.code
;
8065 strcat (intel_parser
.disp
, str
);
8067 else if (cur_token
.code
== T_SHL
)
8068 strcat (intel_parser
.disp
, "<<");
8069 else if (cur_token
.code
== T_SHR
)
8070 strcat (intel_parser
.disp
, ">>");
8074 intel_match_token (cur_token
.code
);
8079 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8080 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
8098 int nregs
= ~NUM_ADDRESS_REGS
;
8103 /* Don't consume constants here. */
8104 if (cur_token
.code
== '+' || cur_token
.code
== '-')
8106 /* Need to look one token ahead - if the next token
8107 is a constant, the current token is its sign. */
8110 intel_match_token (cur_token
.code
);
8111 next_code
= cur_token
.code
;
8112 intel_putback_token ();
8113 if (next_code
== T_CONST
)
8117 /* e09 OFFSET e09 */
8118 if (cur_token
.code
== T_OFFSET
)
8121 ++intel_parser
.in_offset
;
8125 else if (cur_token
.code
== T_SHORT
)
8126 intel_parser
.op_modifier
|= 1 << T_SHORT
;
8129 else if (cur_token
.code
== '+')
8130 strcat (intel_parser
.disp
, "+");
8135 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
8141 str
[0] = cur_token
.code
;
8143 strcat (intel_parser
.disp
, str
);
8150 intel_match_token (cur_token
.code
);
8158 /* e09' PTR e10 e09' */
8159 if (cur_token
.code
== T_PTR
)
8163 if (prev_token
.code
== T_BYTE
)
8165 suffix
= BYTE_MNEM_SUFFIX
;
8166 i
.types
[this_operand
].bitfield
.byte
= 1;
8169 else if (prev_token
.code
== T_WORD
)
8171 if (current_templates
->start
->name
[0] == 'l'
8172 && current_templates
->start
->name
[2] == 's'
8173 && current_templates
->start
->name
[3] == 0)
8174 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8175 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
8176 suffix
= SHORT_MNEM_SUFFIX
;
8178 suffix
= WORD_MNEM_SUFFIX
;
8179 i
.types
[this_operand
].bitfield
.word
= 1;
8182 else if (prev_token
.code
== T_DWORD
)
8184 if (current_templates
->start
->name
[0] == 'l'
8185 && current_templates
->start
->name
[2] == 's'
8186 && current_templates
->start
->name
[3] == 0)
8187 suffix
= WORD_MNEM_SUFFIX
;
8188 else if (flag_code
== CODE_16BIT
8189 && (current_templates
->start
->opcode_modifier
.jump
8190 || current_templates
->start
->opcode_modifier
.jumpdword
))
8191 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8192 else if (intel_parser
.got_a_float
== 1) /* "f..." */
8193 suffix
= SHORT_MNEM_SUFFIX
;
8195 suffix
= LONG_MNEM_SUFFIX
;
8196 i
.types
[this_operand
].bitfield
.dword
= 1;
8199 else if (prev_token
.code
== T_FWORD
)
8201 if (current_templates
->start
->name
[0] == 'l'
8202 && current_templates
->start
->name
[2] == 's'
8203 && current_templates
->start
->name
[3] == 0)
8204 suffix
= LONG_MNEM_SUFFIX
;
8205 else if (!intel_parser
.got_a_float
)
8207 if (flag_code
== CODE_16BIT
)
8208 add_prefix (DATA_PREFIX_OPCODE
);
8209 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8212 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8213 i
.types
[this_operand
].bitfield
.fword
= 1;
8216 else if (prev_token
.code
== T_QWORD
)
8218 if (intel_parser
.got_a_float
== 1) /* "f..." */
8219 suffix
= LONG_MNEM_SUFFIX
;
8221 suffix
= QWORD_MNEM_SUFFIX
;
8222 i
.types
[this_operand
].bitfield
.qword
= 1;
8225 else if (prev_token
.code
== T_TBYTE
)
8227 if (intel_parser
.got_a_float
== 1)
8228 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
8230 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
8233 else if (prev_token
.code
== T_XMMWORD
)
8235 suffix
= XMMWORD_MNEM_SUFFIX
;
8236 i
.types
[this_operand
].bitfield
.xmmword
= 1;
8241 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
8245 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8247 /* Operands for jump/call using 'ptr' notation denote absolute
8249 if (current_templates
->start
->opcode_modifier
.jump
8250 || current_templates
->start
->opcode_modifier
.jumpdword
)
8251 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8253 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
8257 else if (i
.suffix
!= suffix
)
8259 as_bad (_("Conflicting operand modifiers"));
8265 /* e09' : e10 e09' */
8266 else if (cur_token
.code
== ':')
8268 if (prev_token
.code
!= T_REG
)
8270 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8271 segment/group identifier (which we don't have), using comma
8272 as the operand separator there is even less consistent, since
8273 there all branches only have a single operand. */
8274 if (this_operand
!= 0
8275 || intel_parser
.in_offset
8276 || intel_parser
.in_bracket
8277 || (!current_templates
->start
->opcode_modifier
.jump
8278 && !current_templates
->start
->opcode_modifier
.jumpdword
8279 && !current_templates
->start
->opcode_modifier
.jumpintersegment
8280 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
8281 return intel_match_token (T_NIL
);
8282 /* Remember the start of the 2nd operand and terminate 1st
8284 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8285 another expression), but it gets at least the simplest case
8286 (a plain number or symbol on the left side) right. */
8287 intel_parser
.next_operand
= intel_parser
.op_string
;
8288 *--intel_parser
.op_string
= '\0';
8289 return intel_match_token (':');
8297 intel_match_token (cur_token
.code
);
8303 --intel_parser
.in_offset
;
8306 if (NUM_ADDRESS_REGS
> nregs
)
8308 as_bad (_("Invalid operand to `OFFSET'"));
8311 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
8314 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8315 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
8320 intel_bracket_expr (void)
8322 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
8323 const char *start
= intel_parser
.op_string
;
8326 if (i
.op
[this_operand
].regs
)
8327 return intel_match_token (T_NIL
);
8329 intel_match_token ('[');
8331 /* Mark as a memory operand only if it's not already known to be an
8332 offset expression. If it's an offset expression, we need to keep
8334 if (!intel_parser
.in_offset
)
8336 ++intel_parser
.in_bracket
;
8338 /* Operands for jump/call inside brackets denote absolute addresses. */
8339 if (current_templates
->start
->opcode_modifier
.jump
8340 || current_templates
->start
->opcode_modifier
.jumpdword
)
8341 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8343 /* Unfortunately gas always diverged from MASM in a respect that can't
8344 be easily fixed without risking to break code sequences likely to be
8345 encountered (the testsuite even check for this): MASM doesn't consider
8346 an expression inside brackets unconditionally as a memory reference.
8347 When that is e.g. a constant, an offset expression, or the sum of the
8348 two, this is still taken as a constant load. gas, however, always
8349 treated these as memory references. As a compromise, we'll try to make
8350 offset expressions inside brackets work the MASM way (since that's
8351 less likely to be found in real world code), but make constants alone
8352 continue to work the traditional gas way. In either case, issue a
8354 intel_parser
.op_modifier
&= ~was_offset
;
8357 strcat (intel_parser
.disp
, "[");
8359 /* Add a '+' to the displacement string if necessary. */
8360 if (*intel_parser
.disp
!= '\0'
8361 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
8362 strcat (intel_parser
.disp
, "+");
8365 && (len
= intel_parser
.op_string
- start
- 1,
8366 intel_match_token (']')))
8368 /* Preserve brackets when the operand is an offset expression. */
8369 if (intel_parser
.in_offset
)
8370 strcat (intel_parser
.disp
, "]");
8373 --intel_parser
.in_bracket
;
8374 if (i
.base_reg
|| i
.index_reg
)
8375 intel_parser
.is_mem
= 1;
8376 if (!intel_parser
.is_mem
)
8378 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8379 /* Defer the warning until all of the operand was parsed. */
8380 intel_parser
.is_mem
= -1;
8381 else if (!quiet_warnings
)
8382 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8383 len
, start
, len
, start
);
8386 intel_parser
.op_modifier
|= was_offset
;
8403 while (cur_token
.code
== '[')
8405 if (!intel_bracket_expr ())
8430 switch (cur_token
.code
)
8434 intel_match_token ('(');
8435 strcat (intel_parser
.disp
, "(");
8437 if (intel_expr () && intel_match_token (')'))
8439 strcat (intel_parser
.disp
, ")");
8446 return intel_bracket_expr ();
8451 strcat (intel_parser
.disp
, cur_token
.str
);
8452 intel_match_token (cur_token
.code
);
8454 /* Mark as a memory operand only if it's not already known to be an
8455 offset expression. */
8456 if (!intel_parser
.in_offset
)
8457 intel_parser
.is_mem
= 1;
8464 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
8466 intel_match_token (T_REG
);
8468 /* Check for segment change. */
8469 if (cur_token
.code
== ':')
8471 if (!reg
->reg_type
.bitfield
.sreg2
8472 && !reg
->reg_type
.bitfield
.sreg3
)
8474 as_bad (_("`%s' is not a valid segment register"),
8478 else if (i
.seg
[i
.mem_operands
])
8479 as_warn (_("Extra segment override ignored"));
8482 if (!intel_parser
.in_offset
)
8483 intel_parser
.is_mem
= 1;
8484 switch (reg
->reg_num
)
8487 i
.seg
[i
.mem_operands
] = &es
;
8490 i
.seg
[i
.mem_operands
] = &cs
;
8493 i
.seg
[i
.mem_operands
] = &ss
;
8496 i
.seg
[i
.mem_operands
] = &ds
;
8499 i
.seg
[i
.mem_operands
] = &fs
;
8502 i
.seg
[i
.mem_operands
] = &gs
;
8508 /* Not a segment register. Check for register scaling. */
8509 else if (cur_token
.code
== '*')
8511 if (!intel_parser
.in_bracket
)
8513 as_bad (_("Register scaling only allowed in memory operands"));
8517 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
8518 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
8519 else if (i
.index_reg
)
8520 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
8522 /* What follows must be a valid scale. */
8523 intel_match_token ('*');
8525 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8527 /* Set the scale after setting the register (otherwise,
8528 i386_scale will complain) */
8529 if (cur_token
.code
== '+' || cur_token
.code
== '-')
8531 char *str
, sign
= cur_token
.code
;
8532 intel_match_token (cur_token
.code
);
8533 if (cur_token
.code
!= T_CONST
)
8535 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8539 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
8540 strcpy (str
+ 1, cur_token
.str
);
8542 if (!i386_scale (str
))
8546 else if (!i386_scale (cur_token
.str
))
8548 intel_match_token (cur_token
.code
);
8551 /* No scaling. If this is a memory operand, the register is either a
8552 base register (first occurrence) or an index register (second
8554 else if (intel_parser
.in_bracket
)
8559 else if (!i
.index_reg
)
8563 as_bad (_("Too many register references in memory operand"));
8567 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8570 /* It's neither base nor index. */
8571 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
8573 i386_operand_type temp
= reg
->reg_type
;
8574 temp
.bitfield
.baseindex
= 0;
8575 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8577 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8578 i
.op
[this_operand
].regs
= reg
;
8583 as_bad (_("Invalid use of register"));
8587 /* Since registers are not part of the displacement string (except
8588 when we're parsing offset operands), we may need to remove any
8589 preceding '+' from the displacement string. */
8590 if (*intel_parser
.disp
!= '\0'
8591 && !intel_parser
.in_offset
)
8593 char *s
= intel_parser
.disp
;
8594 s
+= strlen (s
) - 1;
8617 intel_match_token (cur_token
.code
);
8619 if (cur_token
.code
== T_PTR
)
8622 /* It must have been an identifier. */
8623 intel_putback_token ();
8624 cur_token
.code
= T_ID
;
8630 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
8634 /* The identifier represents a memory reference only if it's not
8635 preceded by an offset modifier and if it's not an equate. */
8636 symbolP
= symbol_find(cur_token
.str
);
8637 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
8638 intel_parser
.is_mem
= 1;
8646 char *save_str
, sign
= 0;
8648 /* Allow constants that start with `+' or `-'. */
8649 if (cur_token
.code
== '-' || cur_token
.code
== '+')
8651 sign
= cur_token
.code
;
8652 intel_match_token (cur_token
.code
);
8653 if (cur_token
.code
!= T_CONST
)
8655 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8661 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
8662 strcpy (save_str
+ !!sign
, cur_token
.str
);
8666 /* Get the next token to check for register scaling. */
8667 intel_match_token (cur_token
.code
);
8669 /* Check if this constant is a scaling factor for an
8671 if (cur_token
.code
== '*')
8673 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
8675 const reg_entry
*reg
= cur_token
.reg
;
8677 if (!intel_parser
.in_bracket
)
8679 as_bad (_("Register scaling only allowed "
8680 "in memory operands"));
8684 /* Disallow things like [1*si].
8685 sp and esp are invalid as index. */
8686 if (reg
->reg_type
.bitfield
.reg16
)
8687 reg
= i386_regtab
+ REGNAM_AX
+ 4;
8688 else if (i
.index_reg
)
8689 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
8691 /* The constant is followed by `* reg', so it must be
8694 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8696 /* Set the scale after setting the register (otherwise,
8697 i386_scale will complain) */
8698 if (!i386_scale (save_str
))
8700 intel_match_token (T_REG
);
8702 /* Since registers are not part of the displacement
8703 string, we may need to remove any preceding '+' from
8704 the displacement string. */
8705 if (*intel_parser
.disp
!= '\0')
8707 char *s
= intel_parser
.disp
;
8708 s
+= strlen (s
) - 1;
8718 /* The constant was not used for register scaling. Since we have
8719 already consumed the token following `*' we now need to put it
8720 back in the stream. */
8721 intel_putback_token ();
8724 /* Add the constant to the displacement string. */
8725 strcat (intel_parser
.disp
, save_str
);
8732 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
8736 /* Match the given token against cur_token. If they match, read the next
8737 token from the operand string. */
8739 intel_match_token (int code
)
8741 if (cur_token
.code
== code
)
8748 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
8753 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8755 intel_get_token (void)
8758 const reg_entry
*reg
;
8759 struct intel_token new_token
;
8761 new_token
.code
= T_NIL
;
8762 new_token
.reg
= NULL
;
8763 new_token
.str
= NULL
;
8765 /* Free the memory allocated to the previous token and move
8766 cur_token to prev_token. */
8768 free (prev_token
.str
);
8770 prev_token
= cur_token
;
8772 /* Skip whitespace. */
8773 while (is_space_char (*intel_parser
.op_string
))
8774 intel_parser
.op_string
++;
8776 /* Return an empty token if we find nothing else on the line. */
8777 if (*intel_parser
.op_string
== '\0')
8779 cur_token
= new_token
;
8783 /* The new token cannot be larger than the remainder of the operand
8785 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
8786 new_token
.str
[0] = '\0';
8788 if (strchr ("0123456789", *intel_parser
.op_string
))
8790 char *p
= new_token
.str
;
8791 char *q
= intel_parser
.op_string
;
8792 new_token
.code
= T_CONST
;
8794 /* Allow any kind of identifier char to encompass floating point and
8795 hexadecimal numbers. */
8796 while (is_identifier_char (*q
))
8800 /* Recognize special symbol names [0-9][bf]. */
8801 if (strlen (intel_parser
.op_string
) == 2
8802 && (intel_parser
.op_string
[1] == 'b'
8803 || intel_parser
.op_string
[1] == 'f'))
8804 new_token
.code
= T_ID
;
8807 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
8809 size_t len
= end_op
- intel_parser
.op_string
;
8811 new_token
.code
= T_REG
;
8812 new_token
.reg
= reg
;
8814 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
8815 new_token
.str
[len
] = '\0';
8818 else if (is_identifier_char (*intel_parser
.op_string
))
8820 char *p
= new_token
.str
;
8821 char *q
= intel_parser
.op_string
;
8823 /* A '.' or '$' followed by an identifier char is an identifier.
8824 Otherwise, it's operator '.' followed by an expression. */
8825 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
8827 new_token
.code
= '.';
8828 new_token
.str
[0] = '.';
8829 new_token
.str
[1] = '\0';
8833 while (is_identifier_char (*q
) || *q
== '@')
8837 if (strcasecmp (new_token
.str
, "NOT") == 0)
8838 new_token
.code
= '~';
8840 else if (strcasecmp (new_token
.str
, "MOD") == 0)
8841 new_token
.code
= '%';
8843 else if (strcasecmp (new_token
.str
, "AND") == 0)
8844 new_token
.code
= '&';
8846 else if (strcasecmp (new_token
.str
, "OR") == 0)
8847 new_token
.code
= '|';
8849 else if (strcasecmp (new_token
.str
, "XOR") == 0)
8850 new_token
.code
= '^';
8852 else if (strcasecmp (new_token
.str
, "SHL") == 0)
8853 new_token
.code
= T_SHL
;
8855 else if (strcasecmp (new_token
.str
, "SHR") == 0)
8856 new_token
.code
= T_SHR
;
8858 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
8859 new_token
.code
= T_BYTE
;
8861 else if (strcasecmp (new_token
.str
, "WORD") == 0)
8862 new_token
.code
= T_WORD
;
8864 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
8865 new_token
.code
= T_DWORD
;
8867 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
8868 new_token
.code
= T_FWORD
;
8870 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
8871 new_token
.code
= T_QWORD
;
8873 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
8874 /* XXX remove (gcc still uses it) */
8875 || strcasecmp (new_token
.str
, "XWORD") == 0)
8876 new_token
.code
= T_TBYTE
;
8878 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
8879 || strcasecmp (new_token
.str
, "OWORD") == 0)
8880 new_token
.code
= T_XMMWORD
;
8882 else if (strcasecmp (new_token
.str
, "PTR") == 0)
8883 new_token
.code
= T_PTR
;
8885 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
8886 new_token
.code
= T_SHORT
;
8888 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
8890 new_token
.code
= T_OFFSET
;
8892 /* ??? This is not mentioned in the MASM grammar but gcc
8893 makes use of it with -mintel-syntax. OFFSET may be
8894 followed by FLAT: */
8895 if (strncasecmp (q
, " FLAT:", 6) == 0)
8896 strcat (new_token
.str
, " FLAT:");
8899 /* ??? This is not mentioned in the MASM grammar. */
8900 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
8902 new_token
.code
= T_OFFSET
;
8904 strcat (new_token
.str
, ":");
8906 as_bad (_("`:' expected"));
8910 new_token
.code
= T_ID
;
8914 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
8916 new_token
.code
= *intel_parser
.op_string
;
8917 new_token
.str
[0] = *intel_parser
.op_string
;
8918 new_token
.str
[1] = '\0';
8921 else if (strchr ("<>", *intel_parser
.op_string
)
8922 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
8924 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
8925 new_token
.str
[0] = *intel_parser
.op_string
;
8926 new_token
.str
[1] = *intel_parser
.op_string
;
8927 new_token
.str
[2] = '\0';
8931 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
8933 intel_parser
.op_string
+= strlen (new_token
.str
);
8934 cur_token
= new_token
;
8937 /* Put cur_token back into the token stream and make cur_token point to
8940 intel_putback_token (void)
8942 if (cur_token
.code
!= T_NIL
)
8944 intel_parser
.op_string
-= strlen (cur_token
.str
);
8945 free (cur_token
.str
);
8947 cur_token
= prev_token
;
8949 /* Forget prev_token. */
8950 prev_token
.code
= T_NIL
;
8951 prev_token
.reg
= NULL
;
8952 prev_token
.str
= NULL
;
8956 tc_x86_regname_to_dw2regnum (char *regname
)
8958 unsigned int regnum
;
8959 unsigned int regnames_count
;
8960 static const char *const regnames_32
[] =
8962 "eax", "ecx", "edx", "ebx",
8963 "esp", "ebp", "esi", "edi",
8964 "eip", "eflags", NULL
,
8965 "st0", "st1", "st2", "st3",
8966 "st4", "st5", "st6", "st7",
8968 "xmm0", "xmm1", "xmm2", "xmm3",
8969 "xmm4", "xmm5", "xmm6", "xmm7",
8970 "mm0", "mm1", "mm2", "mm3",
8971 "mm4", "mm5", "mm6", "mm7",
8972 "fcw", "fsw", "mxcsr",
8973 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
8976 static const char *const regnames_64
[] =
8978 "rax", "rdx", "rcx", "rbx",
8979 "rsi", "rdi", "rbp", "rsp",
8980 "r8", "r9", "r10", "r11",
8981 "r12", "r13", "r14", "r15",
8983 "xmm0", "xmm1", "xmm2", "xmm3",
8984 "xmm4", "xmm5", "xmm6", "xmm7",
8985 "xmm8", "xmm9", "xmm10", "xmm11",
8986 "xmm12", "xmm13", "xmm14", "xmm15",
8987 "st0", "st1", "st2", "st3",
8988 "st4", "st5", "st6", "st7",
8989 "mm0", "mm1", "mm2", "mm3",
8990 "mm4", "mm5", "mm6", "mm7",
8992 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
8993 "fs.base", "gs.base", NULL
, NULL
,
8995 "mxcsr", "fcw", "fsw"
8997 const char *const *regnames
;
8999 if (flag_code
== CODE_64BIT
)
9001 regnames
= regnames_64
;
9002 regnames_count
= ARRAY_SIZE (regnames_64
);
9006 regnames
= regnames_32
;
9007 regnames_count
= ARRAY_SIZE (regnames_32
);
9010 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
9011 if (regnames
[regnum
] != NULL
9012 && strcmp (regname
, regnames
[regnum
]) == 0)
9019 tc_x86_frame_initial_instructions (void)
9021 static unsigned int sp_regno
;
9024 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
9027 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
9028 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9032 i386_elf_section_type (const char *str
, size_t len
)
9034 if (flag_code
== CODE_64BIT
9035 && len
== sizeof ("unwind") - 1
9036 && strncmp (str
, "unwind", 6) == 0)
9037 return SHT_X86_64_UNWIND
;
9044 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9048 expr
.X_op
= O_secrel
;
9049 expr
.X_add_symbol
= symbol
;
9050 expr
.X_add_number
= 0;
9051 emit_expr (&expr
, size
);
9055 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9056 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9059 x86_64_section_letter (int letter
, char **ptr_msg
)
9061 if (flag_code
== CODE_64BIT
)
9064 return SHF_X86_64_LARGE
;
9066 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9069 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
9074 x86_64_section_word (char *str
, size_t len
)
9076 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9077 return SHF_X86_64_LARGE
;
9083 handle_large_common (int small ATTRIBUTE_UNUSED
)
9085 if (flag_code
!= CODE_64BIT
)
9087 s_comm_internal (0, elf_common_parse
);
9088 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9092 static segT lbss_section
;
9093 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9094 asection
*saved_bss_section
= bss_section
;
9096 if (lbss_section
== NULL
)
9098 flagword applicable
;
9100 subsegT subseg
= now_subseg
;
9102 /* The .lbss section is for local .largecomm symbols. */
9103 lbss_section
= subseg_new (".lbss", 0);
9104 applicable
= bfd_applicable_section_flags (stdoutput
);
9105 bfd_set_section_flags (stdoutput
, lbss_section
,
9106 applicable
& SEC_ALLOC
);
9107 seg_info (lbss_section
)->bss
= 1;
9109 subseg_set (seg
, subseg
);
9112 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9113 bss_section
= lbss_section
;
9115 s_comm_internal (0, elf_common_parse
);
9117 elf_com_section_ptr
= saved_com_section_ptr
;
9118 bss_section
= saved_bss_section
;
9121 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */