1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 /* 1 for intel syntax,
523 static int intel_syntax
= 0;
525 /* 1 for intel mnemonic,
526 0 if att mnemonic. */
527 static int intel_mnemonic
= !SYSV386_COMPAT
;
529 /* 1 if support old (<= 2.8.1) versions of gcc. */
530 static int old_gcc
= OLDGCC_COMPAT
;
532 /* 1 if pseudo registers are permitted. */
533 static int allow_pseudo_reg
= 0;
535 /* 1 if register prefix % not required. */
536 static int allow_naked_reg
= 0;
538 /* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
541 static int add_bnd_prefix
= 0;
543 /* 1 if pseudo index register, eiz/riz, is allowed . */
544 static int allow_index_reg
= 0;
546 static enum check_kind
552 sse_check
, operand_check
= check_warning
;
554 /* Register prefix used for error message. */
555 static const char *register_prefix
= "%";
557 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
558 leave, push, and pop instructions so that gcc has the same stack
559 frame as in 32 bit mode. */
560 static char stackop_size
= '\0';
562 /* Non-zero to optimize code alignment. */
563 int optimize_align_code
= 1;
565 /* Non-zero to quieten some warnings. */
566 static int quiet_warnings
= 0;
569 static const char *cpu_arch_name
= NULL
;
570 static char *cpu_sub_arch_name
= NULL
;
572 /* CPU feature flags. */
573 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
575 /* If we have selected a cpu we are generating instructions for. */
576 static int cpu_arch_tune_set
= 0;
578 /* Cpu we are generating instructions for. */
579 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
581 /* CPU feature flags of cpu we are generating instructions for. */
582 static i386_cpu_flags cpu_arch_tune_flags
;
584 /* CPU instruction set architecture used. */
585 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
587 /* CPU feature flags of instruction set architecture used. */
588 i386_cpu_flags cpu_arch_isa_flags
;
590 /* If set, conditional jumps are not automatically promoted to handle
591 larger than a byte offset. */
592 static unsigned int no_cond_jump_promotion
= 0;
594 /* Encode SSE instructions with VEX prefix. */
595 static unsigned int sse2avx
;
597 /* Encode scalar AVX instructions with specific vector length. */
604 /* Encode scalar EVEX LIG instructions with specific vector length. */
612 /* Encode EVEX WIG instructions with specific evex.w. */
619 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
620 static symbolS
*GOT_symbol
;
622 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
623 unsigned int x86_dwarf2_return_column
;
625 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
626 int x86_cie_data_alignment
;
628 /* Interface to relax_segment.
629 There are 3 major relax states for 386 jump insns because the
630 different types of jumps add different sizes to frags when we're
631 figuring out what sort of jump to choose to reach a given label. */
634 #define UNCOND_JUMP 0
636 #define COND_JUMP86 2
641 #define SMALL16 (SMALL | CODE16)
643 #define BIG16 (BIG | CODE16)
647 #define INLINE __inline__
653 #define ENCODE_RELAX_STATE(type, size) \
654 ((relax_substateT) (((type) << 2) | (size)))
655 #define TYPE_FROM_RELAX_STATE(s) \
657 #define DISP_SIZE_FROM_RELAX_STATE(s) \
658 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
660 /* This table is used by relax_frag to promote short jumps to long
661 ones where necessary. SMALL (short) jumps may be promoted to BIG
662 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
663 don't allow a short jump in a 32 bit code segment to be promoted to
664 a 16 bit offset jump because it's slower (requires data size
665 prefix), and doesn't work, unless the destination is in the bottom
666 64k of the code segment (The top 16 bits of eip are zeroed). */
668 const relax_typeS md_relax_table
[] =
671 1) most positive reach of this state,
672 2) most negative reach of this state,
673 3) how many bytes this mode will have in the variable part of the frag
674 4) which index into the table to try if we can't fit into this one. */
676 /* UNCOND_JUMP states. */
677 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
678 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
679 /* dword jmp adds 4 bytes to frag:
680 0 extra opcode bytes, 4 displacement bytes. */
682 /* word jmp adds 2 byte2 to frag:
683 0 extra opcode bytes, 2 displacement bytes. */
686 /* COND_JUMP states. */
687 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
688 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
689 /* dword conditionals adds 5 bytes to frag:
690 1 extra opcode byte, 4 displacement bytes. */
692 /* word conditionals add 3 bytes to frag:
693 1 extra opcode byte, 2 displacement bytes. */
696 /* COND_JUMP86 states. */
697 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
698 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
699 /* dword conditionals adds 5 bytes to frag:
700 1 extra opcode byte, 4 displacement bytes. */
702 /* word conditionals add 4 bytes to frag:
703 1 displacement byte and a 3 byte long branch insn. */
707 static const arch_entry cpu_arch
[] =
709 /* Do not replace the first two entries - i386_target_format()
710 relies on them being there in this order. */
711 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
712 CPU_GENERIC32_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
714 CPU_GENERIC64_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
716 CPU_NONE_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
718 CPU_I186_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
720 CPU_I286_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
722 CPU_I386_FLAGS
, 0, 0 },
723 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
724 CPU_I486_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
726 CPU_I586_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
728 CPU_I686_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
730 CPU_I586_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
732 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
734 CPU_P2_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
736 CPU_P3_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
738 CPU_P4_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
740 CPU_CORE_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
742 CPU_NOCONA_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
744 CPU_CORE_FLAGS
, 1, 0 },
745 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
746 CPU_CORE_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
748 CPU_CORE2_FLAGS
, 1, 0 },
749 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
750 CPU_CORE2_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
752 CPU_COREI7_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
754 CPU_L1OM_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
756 CPU_K1OM_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
758 CPU_K6_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
760 CPU_K6_2_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
762 CPU_ATHLON_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
764 CPU_K8_FLAGS
, 1, 0 },
765 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
766 CPU_K8_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
768 CPU_K8_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
770 CPU_AMDFAM10_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
772 CPU_BDVER1_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
774 CPU_BDVER2_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
776 CPU_BDVER3_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
778 CPU_BDVER4_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
780 CPU_BTVER1_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
782 CPU_BTVER2_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
784 CPU_8087_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
786 CPU_287_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
788 CPU_387_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
790 CPU_ANY87_FLAGS
, 0, 1 },
791 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
792 CPU_MMX_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
794 CPU_3DNOWA_FLAGS
, 0, 1 },
795 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
796 CPU_SSE_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
798 CPU_SSE2_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
800 CPU_SSE3_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
802 CPU_SSSE3_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
804 CPU_SSE4_1_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
806 CPU_SSE4_2_FLAGS
, 0, 0 },
807 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
808 CPU_SSE4_2_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
810 CPU_ANY_SSE_FLAGS
, 0, 1 },
811 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
812 CPU_AVX_FLAGS
, 0, 0 },
813 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
814 CPU_AVX2_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
816 CPU_AVX512F_FLAGS
, 0, 0 },
817 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
818 CPU_AVX512CD_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
820 CPU_AVX512ER_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
822 CPU_AVX512PF_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
824 CPU_ANY_AVX_FLAGS
, 0, 1 },
825 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
826 CPU_VMX_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
828 CPU_VMFUNC_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
830 CPU_SMX_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
832 CPU_XSAVE_FLAGS
, 0, 0 },
833 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
834 CPU_XSAVEOPT_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
836 CPU_AES_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
838 CPU_PCLMUL_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
840 CPU_PCLMUL_FLAGS
, 1, 0 },
841 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
842 CPU_FSGSBASE_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
844 CPU_RDRND_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
846 CPU_F16C_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
848 CPU_BMI2_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
850 CPU_FMA_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
852 CPU_FMA4_FLAGS
, 0, 0 },
853 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
854 CPU_XOP_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
856 CPU_LWP_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
858 CPU_MOVBE_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
860 CPU_CX16_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
862 CPU_EPT_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
864 CPU_LZCNT_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
866 CPU_HLE_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
868 CPU_RTM_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
870 CPU_INVPCID_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
872 CPU_CLFLUSH_FLAGS
, 0, 0 },
873 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
874 CPU_NOP_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
876 CPU_SYSCALL_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
878 CPU_RDTSCP_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
880 CPU_3DNOW_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
882 CPU_3DNOWA_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
884 CPU_PADLOCK_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
886 CPU_SVME_FLAGS
, 1, 0 },
887 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
888 CPU_SVME_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
890 CPU_SSE4A_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
892 CPU_ABM_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
894 CPU_BMI_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
896 CPU_TBM_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
898 CPU_ADX_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
900 CPU_RDSEED_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
902 CPU_PRFCHW_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
904 CPU_SMAP_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
906 CPU_MPX_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
908 CPU_SHA_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
910 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
912 CPU_XSAVEC_FLAGS
, 0, 0 },
913 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
914 CPU_XSAVES_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
916 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
917 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
918 CPU_SE1_FLAGS
, 0, 0 },
922 /* Like s_lcomm_internal in gas/read.c but the alignment string
923 is allowed to be optional. */
926 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
933 && *input_line_pointer
== ',')
935 align
= parse_align (needs_align
- 1);
937 if (align
== (addressT
) -1)
952 bss_alloc (symbolP
, size
, align
);
957 pe_lcomm (int needs_align
)
959 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
963 const pseudo_typeS md_pseudo_table
[] =
965 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
966 {"align", s_align_bytes
, 0},
968 {"align", s_align_ptwo
, 0},
970 {"arch", set_cpu_arch
, 0},
974 {"lcomm", pe_lcomm
, 1},
976 {"ffloat", float_cons
, 'f'},
977 {"dfloat", float_cons
, 'd'},
978 {"tfloat", float_cons
, 'x'},
980 {"slong", signed_cons
, 4},
981 {"noopt", s_ignore
, 0},
982 {"optim", s_ignore
, 0},
983 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
984 {"code16", set_code_flag
, CODE_16BIT
},
985 {"code32", set_code_flag
, CODE_32BIT
},
986 {"code64", set_code_flag
, CODE_64BIT
},
987 {"intel_syntax", set_intel_syntax
, 1},
988 {"att_syntax", set_intel_syntax
, 0},
989 {"intel_mnemonic", set_intel_mnemonic
, 1},
990 {"att_mnemonic", set_intel_mnemonic
, 0},
991 {"allow_index_reg", set_allow_index_reg
, 1},
992 {"disallow_index_reg", set_allow_index_reg
, 0},
993 {"sse_check", set_check
, 0},
994 {"operand_check", set_check
, 1},
995 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
996 {"largecomm", handle_large_common
, 0},
998 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
999 {"loc", dwarf2_directive_loc
, 0},
1000 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1003 {"secrel32", pe_directive_secrel
, 0},
1008 /* For interface with expression (). */
1009 extern char *input_line_pointer
;
1011 /* Hash table for instruction mnemonic lookup. */
1012 static struct hash_control
*op_hash
;
1014 /* Hash table for register lookup. */
1015 static struct hash_control
*reg_hash
;
1018 i386_align_code (fragS
*fragP
, int count
)
1020 /* Various efficient no-op patterns for aligning code labels.
1021 Note: Don't try to assemble the instructions in the comments.
1022 0L and 0w are not legal. */
1023 static const char f32_1
[] =
1025 static const char f32_2
[] =
1026 {0x66,0x90}; /* xchg %ax,%ax */
1027 static const char f32_3
[] =
1028 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1029 static const char f32_4
[] =
1030 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1031 static const char f32_5
[] =
1033 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1034 static const char f32_6
[] =
1035 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1036 static const char f32_7
[] =
1037 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1038 static const char f32_8
[] =
1040 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1041 static const char f32_9
[] =
1042 {0x89,0xf6, /* movl %esi,%esi */
1043 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1044 static const char f32_10
[] =
1045 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1046 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1047 static const char f32_11
[] =
1048 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1049 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1050 static const char f32_12
[] =
1051 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1052 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1053 static const char f32_13
[] =
1054 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1055 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1056 static const char f32_14
[] =
1057 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1058 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1059 static const char f16_3
[] =
1060 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1061 static const char f16_4
[] =
1062 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1063 static const char f16_5
[] =
1065 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1066 static const char f16_6
[] =
1067 {0x89,0xf6, /* mov %si,%si */
1068 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1069 static const char f16_7
[] =
1070 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1071 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1072 static const char f16_8
[] =
1073 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1074 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1075 static const char jump_31
[] =
1076 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1077 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1078 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1079 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1080 static const char *const f32_patt
[] = {
1081 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1082 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1084 static const char *const f16_patt
[] = {
1085 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1087 /* nopl (%[re]ax) */
1088 static const char alt_3
[] =
1090 /* nopl 0(%[re]ax) */
1091 static const char alt_4
[] =
1092 {0x0f,0x1f,0x40,0x00};
1093 /* nopl 0(%[re]ax,%[re]ax,1) */
1094 static const char alt_5
[] =
1095 {0x0f,0x1f,0x44,0x00,0x00};
1096 /* nopw 0(%[re]ax,%[re]ax,1) */
1097 static const char alt_6
[] =
1098 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1099 /* nopl 0L(%[re]ax) */
1100 static const char alt_7
[] =
1101 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1102 /* nopl 0L(%[re]ax,%[re]ax,1) */
1103 static const char alt_8
[] =
1104 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1105 /* nopw 0L(%[re]ax,%[re]ax,1) */
1106 static const char alt_9
[] =
1107 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1108 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1109 static const char alt_10
[] =
1110 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1112 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1113 static const char alt_long_11
[] =
1115 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1118 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1119 static const char alt_long_12
[] =
1122 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1126 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1127 static const char alt_long_13
[] =
1131 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1136 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_long_14
[] =
1142 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1148 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1149 static const char alt_long_15
[] =
1155 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1156 /* nopl 0(%[re]ax,%[re]ax,1)
1157 nopw 0(%[re]ax,%[re]ax,1) */
1158 static const char alt_short_11
[] =
1159 {0x0f,0x1f,0x44,0x00,0x00,
1160 0x66,0x0f,0x1f,0x44,0x00,0x00};
1161 /* nopw 0(%[re]ax,%[re]ax,1)
1162 nopw 0(%[re]ax,%[re]ax,1) */
1163 static const char alt_short_12
[] =
1164 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1165 0x66,0x0f,0x1f,0x44,0x00,0x00};
1166 /* nopw 0(%[re]ax,%[re]ax,1)
1168 static const char alt_short_13
[] =
1169 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1170 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1173 static const char alt_short_14
[] =
1174 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1175 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1177 nopl 0L(%[re]ax,%[re]ax,1) */
1178 static const char alt_short_15
[] =
1179 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1180 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1181 static const char *const alt_short_patt
[] = {
1182 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1183 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1184 alt_short_14
, alt_short_15
1186 static const char *const alt_long_patt
[] = {
1187 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1188 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1189 alt_long_14
, alt_long_15
1192 /* Only align for at least a positive non-zero boundary. */
1193 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1196 /* We need to decide which NOP sequence to use for 32bit and
1197 64bit. When -mtune= is used:
1199 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1200 PROCESSOR_GENERIC32, f32_patt will be used.
1201 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1202 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1203 PROCESSOR_GENERIC64, alt_long_patt will be used.
1204 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1205 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1208 When -mtune= isn't used, alt_long_patt will be used if
1209 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1212 When -march= or .arch is used, we can't use anything beyond
1213 cpu_arch_isa_flags. */
1215 if (flag_code
== CODE_16BIT
)
1219 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1221 /* Adjust jump offset. */
1222 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1225 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1226 f16_patt
[count
- 1], count
);
1230 const char *const *patt
= NULL
;
1232 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1234 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1235 switch (cpu_arch_tune
)
1237 case PROCESSOR_UNKNOWN
:
1238 /* We use cpu_arch_isa_flags to check if we SHOULD
1239 optimize with nops. */
1240 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1241 patt
= alt_long_patt
;
1245 case PROCESSOR_PENTIUM4
:
1246 case PROCESSOR_NOCONA
:
1247 case PROCESSOR_CORE
:
1248 case PROCESSOR_CORE2
:
1249 case PROCESSOR_COREI7
:
1250 case PROCESSOR_L1OM
:
1251 case PROCESSOR_K1OM
:
1252 case PROCESSOR_GENERIC64
:
1253 patt
= alt_long_patt
;
1256 case PROCESSOR_ATHLON
:
1258 case PROCESSOR_AMDFAM10
:
1261 patt
= alt_short_patt
;
1263 case PROCESSOR_I386
:
1264 case PROCESSOR_I486
:
1265 case PROCESSOR_PENTIUM
:
1266 case PROCESSOR_PENTIUMPRO
:
1267 case PROCESSOR_GENERIC32
:
1274 switch (fragP
->tc_frag_data
.tune
)
1276 case PROCESSOR_UNKNOWN
:
1277 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1278 PROCESSOR_UNKNOWN. */
1282 case PROCESSOR_I386
:
1283 case PROCESSOR_I486
:
1284 case PROCESSOR_PENTIUM
:
1286 case PROCESSOR_ATHLON
:
1288 case PROCESSOR_AMDFAM10
:
1291 case PROCESSOR_GENERIC32
:
1292 /* We use cpu_arch_isa_flags to check if we CAN optimize
1294 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1295 patt
= alt_short_patt
;
1299 case PROCESSOR_PENTIUMPRO
:
1300 case PROCESSOR_PENTIUM4
:
1301 case PROCESSOR_NOCONA
:
1302 case PROCESSOR_CORE
:
1303 case PROCESSOR_CORE2
:
1304 case PROCESSOR_COREI7
:
1305 case PROCESSOR_L1OM
:
1306 case PROCESSOR_K1OM
:
1307 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1308 patt
= alt_long_patt
;
1312 case PROCESSOR_GENERIC64
:
1313 patt
= alt_long_patt
;
1318 if (patt
== f32_patt
)
1320 /* If the padding is less than 15 bytes, we use the normal
1321 ones. Otherwise, we use a jump instruction and adjust
1325 /* For 64bit, the limit is 3 bytes. */
1326 if (flag_code
== CODE_64BIT
1327 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1332 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1333 patt
[count
- 1], count
);
1336 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1338 /* Adjust jump offset. */
1339 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1344 /* Maximum length of an instruction is 15 byte. If the
1345 padding is greater than 15 bytes and we don't use jump,
1346 we have to break it into smaller pieces. */
1347 int padding
= count
;
1348 while (padding
> 15)
1351 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1356 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1357 patt
[padding
- 1], padding
);
1360 fragP
->fr_var
= count
;
1364 operand_type_all_zero (const union i386_operand_type
*x
)
1366 switch (ARRAY_SIZE(x
->array
))
1375 return !x
->array
[0];
1382 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1384 switch (ARRAY_SIZE(x
->array
))
1399 operand_type_equal (const union i386_operand_type
*x
,
1400 const union i386_operand_type
*y
)
1402 switch (ARRAY_SIZE(x
->array
))
1405 if (x
->array
[2] != y
->array
[2])
1408 if (x
->array
[1] != y
->array
[1])
1411 return x
->array
[0] == y
->array
[0];
1419 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1421 switch (ARRAY_SIZE(x
->array
))
1430 return !x
->array
[0];
1437 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1439 switch (ARRAY_SIZE(x
->array
))
1454 cpu_flags_equal (const union i386_cpu_flags
*x
,
1455 const union i386_cpu_flags
*y
)
1457 switch (ARRAY_SIZE(x
->array
))
1460 if (x
->array
[2] != y
->array
[2])
1463 if (x
->array
[1] != y
->array
[1])
1466 return x
->array
[0] == y
->array
[0];
1474 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1476 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1477 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1480 static INLINE i386_cpu_flags
1481 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1483 switch (ARRAY_SIZE (x
.array
))
1486 x
.array
[2] &= y
.array
[2];
1488 x
.array
[1] &= y
.array
[1];
1490 x
.array
[0] &= y
.array
[0];
1498 static INLINE i386_cpu_flags
1499 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1501 switch (ARRAY_SIZE (x
.array
))
1504 x
.array
[2] |= y
.array
[2];
1506 x
.array
[1] |= y
.array
[1];
1508 x
.array
[0] |= y
.array
[0];
1516 static INLINE i386_cpu_flags
1517 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1519 switch (ARRAY_SIZE (x
.array
))
1522 x
.array
[2] &= ~y
.array
[2];
1524 x
.array
[1] &= ~y
.array
[1];
1526 x
.array
[0] &= ~y
.array
[0];
1534 #define CPU_FLAGS_ARCH_MATCH 0x1
1535 #define CPU_FLAGS_64BIT_MATCH 0x2
1536 #define CPU_FLAGS_AES_MATCH 0x4
1537 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1538 #define CPU_FLAGS_AVX_MATCH 0x10
1540 #define CPU_FLAGS_32BIT_MATCH \
1541 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1542 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1543 #define CPU_FLAGS_PERFECT_MATCH \
1544 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1546 /* Return CPU flags match bits. */
1549 cpu_flags_match (const insn_template
*t
)
1551 i386_cpu_flags x
= t
->cpu_flags
;
1552 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1554 x
.bitfield
.cpu64
= 0;
1555 x
.bitfield
.cpuno64
= 0;
1557 if (cpu_flags_all_zero (&x
))
1559 /* This instruction is available on all archs. */
1560 match
|= CPU_FLAGS_32BIT_MATCH
;
1564 /* This instruction is available only on some archs. */
1565 i386_cpu_flags cpu
= cpu_arch_flags
;
1567 cpu
.bitfield
.cpu64
= 0;
1568 cpu
.bitfield
.cpuno64
= 0;
1569 cpu
= cpu_flags_and (x
, cpu
);
1570 if (!cpu_flags_all_zero (&cpu
))
1572 if (x
.bitfield
.cpuavx
)
1574 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1575 if (cpu
.bitfield
.cpuavx
)
1577 /* Check SSE2AVX. */
1578 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1580 match
|= (CPU_FLAGS_ARCH_MATCH
1581 | CPU_FLAGS_AVX_MATCH
);
1583 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1584 match
|= CPU_FLAGS_AES_MATCH
;
1586 if (!x
.bitfield
.cpupclmul
1587 || cpu
.bitfield
.cpupclmul
)
1588 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1592 match
|= CPU_FLAGS_ARCH_MATCH
;
1595 match
|= CPU_FLAGS_32BIT_MATCH
;
1601 static INLINE i386_operand_type
1602 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1604 switch (ARRAY_SIZE (x
.array
))
1607 x
.array
[2] &= y
.array
[2];
1609 x
.array
[1] &= y
.array
[1];
1611 x
.array
[0] &= y
.array
[0];
1619 static INLINE i386_operand_type
1620 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1622 switch (ARRAY_SIZE (x
.array
))
1625 x
.array
[2] |= y
.array
[2];
1627 x
.array
[1] |= y
.array
[1];
1629 x
.array
[0] |= y
.array
[0];
1637 static INLINE i386_operand_type
1638 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1640 switch (ARRAY_SIZE (x
.array
))
1643 x
.array
[2] ^= y
.array
[2];
1645 x
.array
[1] ^= y
.array
[1];
1647 x
.array
[0] ^= y
.array
[0];
1655 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1656 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1657 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1658 static const i386_operand_type inoutportreg
1659 = OPERAND_TYPE_INOUTPORTREG
;
1660 static const i386_operand_type reg16_inoutportreg
1661 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1662 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1663 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1664 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1665 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1666 static const i386_operand_type anydisp
1667 = OPERAND_TYPE_ANYDISP
;
1668 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1669 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1670 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1671 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1672 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1673 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1674 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1675 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1676 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1677 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1678 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1679 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1680 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1681 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1692 operand_type_check (i386_operand_type t
, enum operand_type c
)
1697 return (t
.bitfield
.reg8
1700 || t
.bitfield
.reg64
);
1703 return (t
.bitfield
.imm8
1707 || t
.bitfield
.imm32s
1708 || t
.bitfield
.imm64
);
1711 return (t
.bitfield
.disp8
1712 || t
.bitfield
.disp16
1713 || t
.bitfield
.disp32
1714 || t
.bitfield
.disp32s
1715 || t
.bitfield
.disp64
);
1718 return (t
.bitfield
.disp8
1719 || t
.bitfield
.disp16
1720 || t
.bitfield
.disp32
1721 || t
.bitfield
.disp32s
1722 || t
.bitfield
.disp64
1723 || t
.bitfield
.baseindex
);
1732 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1733 operand J for instruction template T. */
1736 match_reg_size (const insn_template
*t
, unsigned int j
)
1738 return !((i
.types
[j
].bitfield
.byte
1739 && !t
->operand_types
[j
].bitfield
.byte
)
1740 || (i
.types
[j
].bitfield
.word
1741 && !t
->operand_types
[j
].bitfield
.word
)
1742 || (i
.types
[j
].bitfield
.dword
1743 && !t
->operand_types
[j
].bitfield
.dword
)
1744 || (i
.types
[j
].bitfield
.qword
1745 && !t
->operand_types
[j
].bitfield
.qword
));
1748 /* Return 1 if there is no conflict in any size on operand J for
1749 instruction template T. */
1752 match_mem_size (const insn_template
*t
, unsigned int j
)
1754 return (match_reg_size (t
, j
)
1755 && !((i
.types
[j
].bitfield
.unspecified
1756 && !t
->operand_types
[j
].bitfield
.unspecified
)
1757 || (i
.types
[j
].bitfield
.fword
1758 && !t
->operand_types
[j
].bitfield
.fword
)
1759 || (i
.types
[j
].bitfield
.tbyte
1760 && !t
->operand_types
[j
].bitfield
.tbyte
)
1761 || (i
.types
[j
].bitfield
.xmmword
1762 && !t
->operand_types
[j
].bitfield
.xmmword
)
1763 || (i
.types
[j
].bitfield
.ymmword
1764 && !t
->operand_types
[j
].bitfield
.ymmword
)
1765 || (i
.types
[j
].bitfield
.zmmword
1766 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1769 /* Return 1 if there is no size conflict on any operands for
1770 instruction template T. */
1773 operand_size_match (const insn_template
*t
)
1778 /* Don't check jump instructions. */
1779 if (t
->opcode_modifier
.jump
1780 || t
->opcode_modifier
.jumpbyte
1781 || t
->opcode_modifier
.jumpdword
1782 || t
->opcode_modifier
.jumpintersegment
)
1785 /* Check memory and accumulator operand size. */
1786 for (j
= 0; j
< i
.operands
; j
++)
1788 if (t
->operand_types
[j
].bitfield
.anysize
)
1791 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1797 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1806 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1809 i
.error
= operand_size_mismatch
;
1813 /* Check reverse. */
1814 gas_assert (i
.operands
== 2);
1817 for (j
= 0; j
< 2; j
++)
1819 if (t
->operand_types
[j
].bitfield
.acc
1820 && !match_reg_size (t
, j
? 0 : 1))
1823 if (i
.types
[j
].bitfield
.mem
1824 && !match_mem_size (t
, j
? 0 : 1))
1832 operand_type_match (i386_operand_type overlap
,
1833 i386_operand_type given
)
1835 i386_operand_type temp
= overlap
;
1837 temp
.bitfield
.jumpabsolute
= 0;
1838 temp
.bitfield
.unspecified
= 0;
1839 temp
.bitfield
.byte
= 0;
1840 temp
.bitfield
.word
= 0;
1841 temp
.bitfield
.dword
= 0;
1842 temp
.bitfield
.fword
= 0;
1843 temp
.bitfield
.qword
= 0;
1844 temp
.bitfield
.tbyte
= 0;
1845 temp
.bitfield
.xmmword
= 0;
1846 temp
.bitfield
.ymmword
= 0;
1847 temp
.bitfield
.zmmword
= 0;
1848 if (operand_type_all_zero (&temp
))
1851 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1852 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1856 i
.error
= operand_type_mismatch
;
1860 /* If given types g0 and g1 are registers they must be of the same type
1861 unless the expected operand type register overlap is null.
1862 Note that Acc in a template matches every size of reg. */
1865 operand_type_register_match (i386_operand_type m0
,
1866 i386_operand_type g0
,
1867 i386_operand_type t0
,
1868 i386_operand_type m1
,
1869 i386_operand_type g1
,
1870 i386_operand_type t1
)
1872 if (!operand_type_check (g0
, reg
))
1875 if (!operand_type_check (g1
, reg
))
1878 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1879 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1880 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1881 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1884 if (m0
.bitfield
.acc
)
1886 t0
.bitfield
.reg8
= 1;
1887 t0
.bitfield
.reg16
= 1;
1888 t0
.bitfield
.reg32
= 1;
1889 t0
.bitfield
.reg64
= 1;
1892 if (m1
.bitfield
.acc
)
1894 t1
.bitfield
.reg8
= 1;
1895 t1
.bitfield
.reg16
= 1;
1896 t1
.bitfield
.reg32
= 1;
1897 t1
.bitfield
.reg64
= 1;
1900 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1901 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1902 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1903 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1906 i
.error
= register_type_mismatch
;
1911 static INLINE
unsigned int
1912 register_number (const reg_entry
*r
)
1914 unsigned int nr
= r
->reg_num
;
1916 if (r
->reg_flags
& RegRex
)
1922 static INLINE
unsigned int
1923 mode_from_disp_size (i386_operand_type t
)
1925 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1927 else if (t
.bitfield
.disp16
1928 || t
.bitfield
.disp32
1929 || t
.bitfield
.disp32s
)
1936 fits_in_signed_byte (offsetT num
)
1938 return (num
>= -128) && (num
<= 127);
1942 fits_in_unsigned_byte (offsetT num
)
1944 return (num
& 0xff) == num
;
1948 fits_in_unsigned_word (offsetT num
)
1950 return (num
& 0xffff) == num
;
1954 fits_in_signed_word (offsetT num
)
1956 return (-32768 <= num
) && (num
<= 32767);
1960 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1965 return (!(((offsetT
) -1 << 31) & num
)
1966 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1968 } /* fits_in_signed_long() */
1971 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1976 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1978 } /* fits_in_unsigned_long() */
1981 fits_in_vec_disp8 (offsetT num
)
1983 int shift
= i
.memshift
;
1989 mask
= (1 << shift
) - 1;
1991 /* Return 0 if NUM isn't properly aligned. */
1995 /* Check if NUM will fit in 8bit after shift. */
1996 return fits_in_signed_byte (num
>> shift
);
2000 fits_in_imm4 (offsetT num
)
2002 return (num
& 0xf) == num
;
2005 static i386_operand_type
2006 smallest_imm_type (offsetT num
)
2008 i386_operand_type t
;
2010 operand_type_set (&t
, 0);
2011 t
.bitfield
.imm64
= 1;
2013 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2015 /* This code is disabled on the 486 because all the Imm1 forms
2016 in the opcode table are slower on the i486. They're the
2017 versions with the implicitly specified single-position
2018 displacement, which has another syntax if you really want to
2020 t
.bitfield
.imm1
= 1;
2021 t
.bitfield
.imm8
= 1;
2022 t
.bitfield
.imm8s
= 1;
2023 t
.bitfield
.imm16
= 1;
2024 t
.bitfield
.imm32
= 1;
2025 t
.bitfield
.imm32s
= 1;
2027 else if (fits_in_signed_byte (num
))
2029 t
.bitfield
.imm8
= 1;
2030 t
.bitfield
.imm8s
= 1;
2031 t
.bitfield
.imm16
= 1;
2032 t
.bitfield
.imm32
= 1;
2033 t
.bitfield
.imm32s
= 1;
2035 else if (fits_in_unsigned_byte (num
))
2037 t
.bitfield
.imm8
= 1;
2038 t
.bitfield
.imm16
= 1;
2039 t
.bitfield
.imm32
= 1;
2040 t
.bitfield
.imm32s
= 1;
2042 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2044 t
.bitfield
.imm16
= 1;
2045 t
.bitfield
.imm32
= 1;
2046 t
.bitfield
.imm32s
= 1;
2048 else if (fits_in_signed_long (num
))
2050 t
.bitfield
.imm32
= 1;
2051 t
.bitfield
.imm32s
= 1;
2053 else if (fits_in_unsigned_long (num
))
2054 t
.bitfield
.imm32
= 1;
2060 offset_in_range (offsetT val
, int size
)
2066 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2067 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2068 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2070 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2076 /* If BFD64, sign extend val for 32bit address mode. */
2077 if (flag_code
!= CODE_64BIT
2078 || i
.prefix
[ADDR_PREFIX
])
2079 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2080 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2083 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2085 char buf1
[40], buf2
[40];
2087 sprint_value (buf1
, val
);
2088 sprint_value (buf2
, val
& mask
);
2089 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2103 a. PREFIX_EXIST if attempting to add a prefix where one from the
2104 same class already exists.
2105 b. PREFIX_LOCK if lock prefix is added.
2106 c. PREFIX_REP if rep/repne prefix is added.
2107 d. PREFIX_OTHER if other prefix is added.
2110 static enum PREFIX_GROUP
2111 add_prefix (unsigned int prefix
)
2113 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2116 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2117 && flag_code
== CODE_64BIT
)
2119 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2120 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2121 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2132 case CS_PREFIX_OPCODE
:
2133 case DS_PREFIX_OPCODE
:
2134 case ES_PREFIX_OPCODE
:
2135 case FS_PREFIX_OPCODE
:
2136 case GS_PREFIX_OPCODE
:
2137 case SS_PREFIX_OPCODE
:
2141 case REPNE_PREFIX_OPCODE
:
2142 case REPE_PREFIX_OPCODE
:
2147 case LOCK_PREFIX_OPCODE
:
2156 case ADDR_PREFIX_OPCODE
:
2160 case DATA_PREFIX_OPCODE
:
2164 if (i
.prefix
[q
] != 0)
2172 i
.prefix
[q
] |= prefix
;
2175 as_bad (_("same type of prefix used twice"));
2181 update_code_flag (int value
, int check
)
2183 PRINTF_LIKE ((*as_error
));
2185 flag_code
= (enum flag_code
) value
;
2186 if (flag_code
== CODE_64BIT
)
2188 cpu_arch_flags
.bitfield
.cpu64
= 1;
2189 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2193 cpu_arch_flags
.bitfield
.cpu64
= 0;
2194 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2196 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2199 as_error
= as_fatal
;
2202 (*as_error
) (_("64bit mode not supported on `%s'."),
2203 cpu_arch_name
? cpu_arch_name
: default_arch
);
2205 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2208 as_error
= as_fatal
;
2211 (*as_error
) (_("32bit mode not supported on `%s'."),
2212 cpu_arch_name
? cpu_arch_name
: default_arch
);
2214 stackop_size
= '\0';
2218 set_code_flag (int value
)
2220 update_code_flag (value
, 0);
2224 set_16bit_gcc_code_flag (int new_code_flag
)
2226 flag_code
= (enum flag_code
) new_code_flag
;
2227 if (flag_code
!= CODE_16BIT
)
2229 cpu_arch_flags
.bitfield
.cpu64
= 0;
2230 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2231 stackop_size
= LONG_MNEM_SUFFIX
;
2235 set_intel_syntax (int syntax_flag
)
2237 /* Find out if register prefixing is specified. */
2238 int ask_naked_reg
= 0;
2241 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2243 char *string
= input_line_pointer
;
2244 int e
= get_symbol_end ();
2246 if (strcmp (string
, "prefix") == 0)
2248 else if (strcmp (string
, "noprefix") == 0)
2251 as_bad (_("bad argument to syntax directive."));
2252 *input_line_pointer
= e
;
2254 demand_empty_rest_of_line ();
2256 intel_syntax
= syntax_flag
;
2258 if (ask_naked_reg
== 0)
2259 allow_naked_reg
= (intel_syntax
2260 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2262 allow_naked_reg
= (ask_naked_reg
< 0);
2264 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2266 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2267 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2268 register_prefix
= allow_naked_reg
? "" : "%";
2272 set_intel_mnemonic (int mnemonic_flag
)
2274 intel_mnemonic
= mnemonic_flag
;
2278 set_allow_index_reg (int flag
)
2280 allow_index_reg
= flag
;
2284 set_check (int what
)
2286 enum check_kind
*kind
;
2291 kind
= &operand_check
;
2302 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2304 char *string
= input_line_pointer
;
2305 int e
= get_symbol_end ();
2307 if (strcmp (string
, "none") == 0)
2309 else if (strcmp (string
, "warning") == 0)
2310 *kind
= check_warning
;
2311 else if (strcmp (string
, "error") == 0)
2312 *kind
= check_error
;
2314 as_bad (_("bad argument to %s_check directive."), str
);
2315 *input_line_pointer
= e
;
2318 as_bad (_("missing argument for %s_check directive"), str
);
2320 demand_empty_rest_of_line ();
2324 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2325 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2327 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2328 static const char *arch
;
2330 /* Intel LIOM is only supported on ELF. */
2336 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2337 use default_arch. */
2338 arch
= cpu_arch_name
;
2340 arch
= default_arch
;
2343 /* If we are targeting Intel L1OM, we must enable it. */
2344 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2345 || new_flag
.bitfield
.cpul1om
)
2348 /* If we are targeting Intel K1OM, we must enable it. */
2349 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2350 || new_flag
.bitfield
.cpuk1om
)
2353 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2358 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2362 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2364 char *string
= input_line_pointer
;
2365 int e
= get_symbol_end ();
2367 i386_cpu_flags flags
;
2369 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2371 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2373 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2377 cpu_arch_name
= cpu_arch
[j
].name
;
2378 cpu_sub_arch_name
= NULL
;
2379 cpu_arch_flags
= cpu_arch
[j
].flags
;
2380 if (flag_code
== CODE_64BIT
)
2382 cpu_arch_flags
.bitfield
.cpu64
= 1;
2383 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2387 cpu_arch_flags
.bitfield
.cpu64
= 0;
2388 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2390 cpu_arch_isa
= cpu_arch
[j
].type
;
2391 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2392 if (!cpu_arch_tune_set
)
2394 cpu_arch_tune
= cpu_arch_isa
;
2395 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2400 if (!cpu_arch
[j
].negated
)
2401 flags
= cpu_flags_or (cpu_arch_flags
,
2404 flags
= cpu_flags_and_not (cpu_arch_flags
,
2406 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2408 if (cpu_sub_arch_name
)
2410 char *name
= cpu_sub_arch_name
;
2411 cpu_sub_arch_name
= concat (name
,
2413 (const char *) NULL
);
2417 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2418 cpu_arch_flags
= flags
;
2419 cpu_arch_isa_flags
= flags
;
2421 *input_line_pointer
= e
;
2422 demand_empty_rest_of_line ();
2426 if (j
>= ARRAY_SIZE (cpu_arch
))
2427 as_bad (_("no such architecture: `%s'"), string
);
2429 *input_line_pointer
= e
;
2432 as_bad (_("missing cpu architecture"));
2434 no_cond_jump_promotion
= 0;
2435 if (*input_line_pointer
== ','
2436 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2438 char *string
= ++input_line_pointer
;
2439 int e
= get_symbol_end ();
2441 if (strcmp (string
, "nojumps") == 0)
2442 no_cond_jump_promotion
= 1;
2443 else if (strcmp (string
, "jumps") == 0)
2446 as_bad (_("no such architecture modifier: `%s'"), string
);
2448 *input_line_pointer
= e
;
2451 demand_empty_rest_of_line ();
2454 enum bfd_architecture
2457 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2459 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2460 || flag_code
!= CODE_64BIT
)
2461 as_fatal (_("Intel L1OM is 64bit ELF only"));
2462 return bfd_arch_l1om
;
2464 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2466 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2467 || flag_code
!= CODE_64BIT
)
2468 as_fatal (_("Intel K1OM is 64bit ELF only"));
2469 return bfd_arch_k1om
;
2472 return bfd_arch_i386
;
2478 if (!strncmp (default_arch
, "x86_64", 6))
2480 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2482 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2483 || default_arch
[6] != '\0')
2484 as_fatal (_("Intel L1OM is 64bit ELF only"));
2485 return bfd_mach_l1om
;
2487 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2489 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2490 || default_arch
[6] != '\0')
2491 as_fatal (_("Intel K1OM is 64bit ELF only"));
2492 return bfd_mach_k1om
;
2494 else if (default_arch
[6] == '\0')
2495 return bfd_mach_x86_64
;
2497 return bfd_mach_x64_32
;
2499 else if (!strcmp (default_arch
, "i386"))
2500 return bfd_mach_i386_i386
;
2502 as_fatal (_("unknown architecture"));
2508 const char *hash_err
;
2510 /* Initialize op_hash hash table. */
2511 op_hash
= hash_new ();
2514 const insn_template
*optab
;
2515 templates
*core_optab
;
2517 /* Setup for loop. */
2519 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2520 core_optab
->start
= optab
;
2525 if (optab
->name
== NULL
2526 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2528 /* different name --> ship out current template list;
2529 add to hash table; & begin anew. */
2530 core_optab
->end
= optab
;
2531 hash_err
= hash_insert (op_hash
,
2533 (void *) core_optab
);
2536 as_fatal (_("can't hash %s: %s"),
2540 if (optab
->name
== NULL
)
2542 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2543 core_optab
->start
= optab
;
2548 /* Initialize reg_hash hash table. */
2549 reg_hash
= hash_new ();
2551 const reg_entry
*regtab
;
2552 unsigned int regtab_size
= i386_regtab_size
;
2554 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2556 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2558 as_fatal (_("can't hash %s: %s"),
2564 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2569 for (c
= 0; c
< 256; c
++)
2574 mnemonic_chars
[c
] = c
;
2575 register_chars
[c
] = c
;
2576 operand_chars
[c
] = c
;
2578 else if (ISLOWER (c
))
2580 mnemonic_chars
[c
] = c
;
2581 register_chars
[c
] = c
;
2582 operand_chars
[c
] = c
;
2584 else if (ISUPPER (c
))
2586 mnemonic_chars
[c
] = TOLOWER (c
);
2587 register_chars
[c
] = mnemonic_chars
[c
];
2588 operand_chars
[c
] = c
;
2590 else if (c
== '{' || c
== '}')
2591 operand_chars
[c
] = c
;
2593 if (ISALPHA (c
) || ISDIGIT (c
))
2594 identifier_chars
[c
] = c
;
2597 identifier_chars
[c
] = c
;
2598 operand_chars
[c
] = c
;
2603 identifier_chars
['@'] = '@';
2606 identifier_chars
['?'] = '?';
2607 operand_chars
['?'] = '?';
2609 digit_chars
['-'] = '-';
2610 mnemonic_chars
['_'] = '_';
2611 mnemonic_chars
['-'] = '-';
2612 mnemonic_chars
['.'] = '.';
2613 identifier_chars
['_'] = '_';
2614 identifier_chars
['.'] = '.';
2616 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2617 operand_chars
[(unsigned char) *p
] = *p
;
2620 if (flag_code
== CODE_64BIT
)
2622 #if defined (OBJ_COFF) && defined (TE_PE)
2623 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2626 x86_dwarf2_return_column
= 16;
2628 x86_cie_data_alignment
= -8;
2632 x86_dwarf2_return_column
= 8;
2633 x86_cie_data_alignment
= -4;
2638 i386_print_statistics (FILE *file
)
2640 hash_print_statistics (file
, "i386 opcode", op_hash
);
2641 hash_print_statistics (file
, "i386 register", reg_hash
);
2646 /* Debugging routines for md_assemble. */
2647 static void pte (insn_template
*);
2648 static void pt (i386_operand_type
);
2649 static void pe (expressionS
*);
2650 static void ps (symbolS
*);
2653 pi (char *line
, i386_insn
*x
)
2657 fprintf (stdout
, "%s: template ", line
);
2659 fprintf (stdout
, " address: base %s index %s scale %x\n",
2660 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2661 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2662 x
->log2_scale_factor
);
2663 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2664 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2665 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2666 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2667 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2668 (x
->rex
& REX_W
) != 0,
2669 (x
->rex
& REX_R
) != 0,
2670 (x
->rex
& REX_X
) != 0,
2671 (x
->rex
& REX_B
) != 0);
2672 for (j
= 0; j
< x
->operands
; j
++)
2674 fprintf (stdout
, " #%d: ", j
+ 1);
2676 fprintf (stdout
, "\n");
2677 if (x
->types
[j
].bitfield
.reg8
2678 || x
->types
[j
].bitfield
.reg16
2679 || x
->types
[j
].bitfield
.reg32
2680 || x
->types
[j
].bitfield
.reg64
2681 || x
->types
[j
].bitfield
.regmmx
2682 || x
->types
[j
].bitfield
.regxmm
2683 || x
->types
[j
].bitfield
.regymm
2684 || x
->types
[j
].bitfield
.regzmm
2685 || x
->types
[j
].bitfield
.sreg2
2686 || x
->types
[j
].bitfield
.sreg3
2687 || x
->types
[j
].bitfield
.control
2688 || x
->types
[j
].bitfield
.debug
2689 || x
->types
[j
].bitfield
.test
)
2690 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2691 if (operand_type_check (x
->types
[j
], imm
))
2693 if (operand_type_check (x
->types
[j
], disp
))
2694 pe (x
->op
[j
].disps
);
2699 pte (insn_template
*t
)
2702 fprintf (stdout
, " %d operands ", t
->operands
);
2703 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2704 if (t
->extension_opcode
!= None
)
2705 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2706 if (t
->opcode_modifier
.d
)
2707 fprintf (stdout
, "D");
2708 if (t
->opcode_modifier
.w
)
2709 fprintf (stdout
, "W");
2710 fprintf (stdout
, "\n");
2711 for (j
= 0; j
< t
->operands
; j
++)
2713 fprintf (stdout
, " #%d type ", j
+ 1);
2714 pt (t
->operand_types
[j
]);
2715 fprintf (stdout
, "\n");
2722 fprintf (stdout
, " operation %d\n", e
->X_op
);
2723 fprintf (stdout
, " add_number %ld (%lx)\n",
2724 (long) e
->X_add_number
, (long) e
->X_add_number
);
2725 if (e
->X_add_symbol
)
2727 fprintf (stdout
, " add_symbol ");
2728 ps (e
->X_add_symbol
);
2729 fprintf (stdout
, "\n");
2733 fprintf (stdout
, " op_symbol ");
2734 ps (e
->X_op_symbol
);
2735 fprintf (stdout
, "\n");
2742 fprintf (stdout
, "%s type %s%s",
2744 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2745 segment_name (S_GET_SEGMENT (s
)));
2748 static struct type_name
2750 i386_operand_type mask
;
2753 const type_names
[] =
2755 { OPERAND_TYPE_REG8
, "r8" },
2756 { OPERAND_TYPE_REG16
, "r16" },
2757 { OPERAND_TYPE_REG32
, "r32" },
2758 { OPERAND_TYPE_REG64
, "r64" },
2759 { OPERAND_TYPE_IMM8
, "i8" },
2760 { OPERAND_TYPE_IMM8
, "i8s" },
2761 { OPERAND_TYPE_IMM16
, "i16" },
2762 { OPERAND_TYPE_IMM32
, "i32" },
2763 { OPERAND_TYPE_IMM32S
, "i32s" },
2764 { OPERAND_TYPE_IMM64
, "i64" },
2765 { OPERAND_TYPE_IMM1
, "i1" },
2766 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2767 { OPERAND_TYPE_DISP8
, "d8" },
2768 { OPERAND_TYPE_DISP16
, "d16" },
2769 { OPERAND_TYPE_DISP32
, "d32" },
2770 { OPERAND_TYPE_DISP32S
, "d32s" },
2771 { OPERAND_TYPE_DISP64
, "d64" },
2772 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2773 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2774 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2775 { OPERAND_TYPE_CONTROL
, "control reg" },
2776 { OPERAND_TYPE_TEST
, "test reg" },
2777 { OPERAND_TYPE_DEBUG
, "debug reg" },
2778 { OPERAND_TYPE_FLOATREG
, "FReg" },
2779 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2780 { OPERAND_TYPE_SREG2
, "SReg2" },
2781 { OPERAND_TYPE_SREG3
, "SReg3" },
2782 { OPERAND_TYPE_ACC
, "Acc" },
2783 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2784 { OPERAND_TYPE_REGMMX
, "rMMX" },
2785 { OPERAND_TYPE_REGXMM
, "rXMM" },
2786 { OPERAND_TYPE_REGYMM
, "rYMM" },
2787 { OPERAND_TYPE_REGZMM
, "rZMM" },
2788 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2789 { OPERAND_TYPE_ESSEG
, "es" },
2793 pt (i386_operand_type t
)
2796 i386_operand_type a
;
2798 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2800 a
= operand_type_and (t
, type_names
[j
].mask
);
2801 if (!operand_type_all_zero (&a
))
2802 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2807 #endif /* DEBUG386 */
2809 static bfd_reloc_code_real_type
2810 reloc (unsigned int size
,
2814 bfd_reloc_code_real_type other
)
2816 if (other
!= NO_RELOC
)
2818 reloc_howto_type
*rel
;
2823 case BFD_RELOC_X86_64_GOT32
:
2824 return BFD_RELOC_X86_64_GOT64
;
2826 case BFD_RELOC_X86_64_PLTOFF64
:
2827 return BFD_RELOC_X86_64_PLTOFF64
;
2829 case BFD_RELOC_X86_64_GOTPC32
:
2830 other
= BFD_RELOC_X86_64_GOTPC64
;
2832 case BFD_RELOC_X86_64_GOTPCREL
:
2833 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2835 case BFD_RELOC_X86_64_TPOFF32
:
2836 other
= BFD_RELOC_X86_64_TPOFF64
;
2838 case BFD_RELOC_X86_64_DTPOFF32
:
2839 other
= BFD_RELOC_X86_64_DTPOFF64
;
2845 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2846 if (other
== BFD_RELOC_SIZE32
)
2849 other
= BFD_RELOC_SIZE64
;
2852 as_bad (_("there are no pc-relative size relocations"));
2858 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2859 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2862 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2864 as_bad (_("unknown relocation (%u)"), other
);
2865 else if (size
!= bfd_get_reloc_size (rel
))
2866 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2867 bfd_get_reloc_size (rel
),
2869 else if (pcrel
&& !rel
->pc_relative
)
2870 as_bad (_("non-pc-relative relocation for pc-relative field"));
2871 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2873 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2875 as_bad (_("relocated field and relocation type differ in signedness"));
2884 as_bad (_("there are no unsigned pc-relative relocations"));
2887 case 1: return BFD_RELOC_8_PCREL
;
2888 case 2: return BFD_RELOC_16_PCREL
;
2889 case 4: return (bnd_prefix
&& object_64bit
2890 ? BFD_RELOC_X86_64_PC32_BND
2891 : BFD_RELOC_32_PCREL
);
2892 case 8: return BFD_RELOC_64_PCREL
;
2894 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2901 case 4: return BFD_RELOC_X86_64_32S
;
2906 case 1: return BFD_RELOC_8
;
2907 case 2: return BFD_RELOC_16
;
2908 case 4: return BFD_RELOC_32
;
2909 case 8: return BFD_RELOC_64
;
2911 as_bad (_("cannot do %s %u byte relocation"),
2912 sign
> 0 ? "signed" : "unsigned", size
);
2918 /* Here we decide which fixups can be adjusted to make them relative to
2919 the beginning of the section instead of the symbol. Basically we need
2920 to make sure that the dynamic relocations are done correctly, so in
2921 some cases we force the original symbol to be used. */
2924 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2926 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2930 /* Don't adjust pc-relative references to merge sections in 64-bit
2932 if (use_rela_relocations
2933 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2937 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2938 and changed later by validate_fix. */
2939 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2940 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2943 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2944 for size relocations. */
2945 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2946 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2947 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2948 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2949 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2950 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2951 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2952 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2953 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2954 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2955 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2956 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2957 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2958 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2959 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2960 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2961 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2962 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2963 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2964 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2965 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2966 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2967 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2968 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2969 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2970 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2971 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2972 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2973 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2974 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2981 intel_float_operand (const char *mnemonic
)
2983 /* Note that the value returned is meaningful only for opcodes with (memory)
2984 operands, hence the code here is free to improperly handle opcodes that
2985 have no operands (for better performance and smaller code). */
2987 if (mnemonic
[0] != 'f')
2988 return 0; /* non-math */
2990 switch (mnemonic
[1])
2992 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2993 the fs segment override prefix not currently handled because no
2994 call path can make opcodes without operands get here */
2996 return 2 /* integer op */;
2998 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2999 return 3; /* fldcw/fldenv */
3002 if (mnemonic
[2] != 'o' /* fnop */)
3003 return 3; /* non-waiting control op */
3006 if (mnemonic
[2] == 's')
3007 return 3; /* frstor/frstpm */
3010 if (mnemonic
[2] == 'a')
3011 return 3; /* fsave */
3012 if (mnemonic
[2] == 't')
3014 switch (mnemonic
[3])
3016 case 'c': /* fstcw */
3017 case 'd': /* fstdw */
3018 case 'e': /* fstenv */
3019 case 's': /* fsts[gw] */
3025 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3026 return 0; /* fxsave/fxrstor are not really math ops */
3033 /* Build the VEX prefix. */
3036 build_vex_prefix (const insn_template
*t
)
3038 unsigned int register_specifier
;
3039 unsigned int implied_prefix
;
3040 unsigned int vector_length
;
3042 /* Check register specifier. */
3043 if (i
.vex
.register_specifier
)
3045 register_specifier
=
3046 ~register_number (i
.vex
.register_specifier
) & 0xf;
3047 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3050 register_specifier
= 0xf;
3052 /* Use 2-byte VEX prefix by swappping destination and source
3055 && i
.operands
== i
.reg_operands
3056 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3057 && i
.tm
.opcode_modifier
.s
3060 unsigned int xchg
= i
.operands
- 1;
3061 union i386_op temp_op
;
3062 i386_operand_type temp_type
;
3064 temp_type
= i
.types
[xchg
];
3065 i
.types
[xchg
] = i
.types
[0];
3066 i
.types
[0] = temp_type
;
3067 temp_op
= i
.op
[xchg
];
3068 i
.op
[xchg
] = i
.op
[0];
3071 gas_assert (i
.rm
.mode
== 3);
3075 i
.rm
.regmem
= i
.rm
.reg
;
3078 /* Use the next insn. */
3082 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3083 vector_length
= avxscalar
;
3085 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3087 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3092 case DATA_PREFIX_OPCODE
:
3095 case REPE_PREFIX_OPCODE
:
3098 case REPNE_PREFIX_OPCODE
:
3105 /* Use 2-byte VEX prefix if possible. */
3106 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3107 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3108 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3110 /* 2-byte VEX prefix. */
3114 i
.vex
.bytes
[0] = 0xc5;
3116 /* Check the REX.R bit. */
3117 r
= (i
.rex
& REX_R
) ? 0 : 1;
3118 i
.vex
.bytes
[1] = (r
<< 7
3119 | register_specifier
<< 3
3120 | vector_length
<< 2
3125 /* 3-byte VEX prefix. */
3130 switch (i
.tm
.opcode_modifier
.vexopcode
)
3134 i
.vex
.bytes
[0] = 0xc4;
3138 i
.vex
.bytes
[0] = 0xc4;
3142 i
.vex
.bytes
[0] = 0xc4;
3146 i
.vex
.bytes
[0] = 0x8f;
3150 i
.vex
.bytes
[0] = 0x8f;
3154 i
.vex
.bytes
[0] = 0x8f;
3160 /* The high 3 bits of the second VEX byte are 1's compliment
3161 of RXB bits from REX. */
3162 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3164 /* Check the REX.W bit. */
3165 w
= (i
.rex
& REX_W
) ? 1 : 0;
3166 if (i
.tm
.opcode_modifier
.vexw
)
3171 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3175 i
.vex
.bytes
[2] = (w
<< 7
3176 | register_specifier
<< 3
3177 | vector_length
<< 2
3182 /* Build the EVEX prefix. */
3185 build_evex_prefix (void)
3187 unsigned int register_specifier
;
3188 unsigned int implied_prefix
;
3190 rex_byte vrex_used
= 0;
3192 /* Check register specifier. */
3193 if (i
.vex
.register_specifier
)
3195 gas_assert ((i
.vrex
& REX_X
) == 0);
3197 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3198 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3199 register_specifier
+= 8;
3200 /* The upper 16 registers are encoded in the fourth byte of the
3202 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3203 i
.vex
.bytes
[3] = 0x8;
3204 register_specifier
= ~register_specifier
& 0xf;
3208 register_specifier
= 0xf;
3210 /* Encode upper 16 vector index register in the fourth byte of
3212 if (!(i
.vrex
& REX_X
))
3213 i
.vex
.bytes
[3] = 0x8;
3218 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3223 case DATA_PREFIX_OPCODE
:
3226 case REPE_PREFIX_OPCODE
:
3229 case REPNE_PREFIX_OPCODE
:
3236 /* 4 byte EVEX prefix. */
3238 i
.vex
.bytes
[0] = 0x62;
3241 switch (i
.tm
.opcode_modifier
.vexopcode
)
3257 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3259 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3261 /* The fifth bit of the second EVEX byte is 1's compliment of the
3262 REX_R bit in VREX. */
3263 if (!(i
.vrex
& REX_R
))
3264 i
.vex
.bytes
[1] |= 0x10;
3268 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3270 /* When all operands are registers, the REX_X bit in REX is not
3271 used. We reuse it to encode the upper 16 registers, which is
3272 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3273 as 1's compliment. */
3274 if ((i
.vrex
& REX_B
))
3277 i
.vex
.bytes
[1] &= ~0x40;
3281 /* EVEX instructions shouldn't need the REX prefix. */
3282 i
.vrex
&= ~vrex_used
;
3283 gas_assert (i
.vrex
== 0);
3285 /* Check the REX.W bit. */
3286 w
= (i
.rex
& REX_W
) ? 1 : 0;
3287 if (i
.tm
.opcode_modifier
.vexw
)
3289 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3292 /* If w is not set it means we are dealing with WIG instruction. */
3295 if (evexwig
== evexw1
)
3299 /* Encode the U bit. */
3300 implied_prefix
|= 0x4;
3302 /* The third byte of the EVEX prefix. */
3303 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3305 /* The fourth byte of the EVEX prefix. */
3306 /* The zeroing-masking bit. */
3307 if (i
.mask
&& i
.mask
->zeroing
)
3308 i
.vex
.bytes
[3] |= 0x80;
3310 /* Don't always set the broadcast bit if there is no RC. */
3313 /* Encode the vector length. */
3314 unsigned int vec_length
;
3316 switch (i
.tm
.opcode_modifier
.evex
)
3318 case EVEXLIG
: /* LL' is ignored */
3319 vec_length
= evexlig
<< 5;
3322 vec_length
= 0 << 5;
3325 vec_length
= 1 << 5;
3328 vec_length
= 2 << 5;
3334 i
.vex
.bytes
[3] |= vec_length
;
3335 /* Encode the broadcast bit. */
3337 i
.vex
.bytes
[3] |= 0x10;
3341 if (i
.rounding
->type
!= saeonly
)
3342 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3344 i
.vex
.bytes
[3] |= 0x10;
3347 if (i
.mask
&& i
.mask
->mask
)
3348 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3352 process_immext (void)
3356 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3359 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3360 with an opcode suffix which is coded in the same place as an
3361 8-bit immediate field would be.
3362 Here we check those operands and remove them afterwards. */
3365 for (x
= 0; x
< i
.operands
; x
++)
3366 if (register_number (i
.op
[x
].regs
) != x
)
3367 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3368 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3374 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3375 which is coded in the same place as an 8-bit immediate field
3376 would be. Here we fake an 8-bit immediate operand from the
3377 opcode suffix stored in tm.extension_opcode.
3379 AVX instructions also use this encoding, for some of
3380 3 argument instructions. */
3382 gas_assert (i
.imm_operands
<= 1
3384 || ((i
.tm
.opcode_modifier
.vex
3385 || i
.tm
.opcode_modifier
.evex
)
3386 && i
.operands
<= 4)));
3388 exp
= &im_expressions
[i
.imm_operands
++];
3389 i
.op
[i
.operands
].imms
= exp
;
3390 i
.types
[i
.operands
] = imm8
;
3392 exp
->X_op
= O_constant
;
3393 exp
->X_add_number
= i
.tm
.extension_opcode
;
3394 i
.tm
.extension_opcode
= None
;
3401 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3406 as_bad (_("invalid instruction `%s' after `%s'"),
3407 i
.tm
.name
, i
.hle_prefix
);
3410 if (i
.prefix
[LOCK_PREFIX
])
3412 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3416 case HLEPrefixRelease
:
3417 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3419 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3423 if (i
.mem_operands
== 0
3424 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3426 as_bad (_("memory destination needed for instruction `%s'"
3427 " after `xrelease'"), i
.tm
.name
);
3434 /* This is the guts of the machine-dependent assembler. LINE points to a
3435 machine dependent instruction. This function is supposed to emit
3436 the frags/bytes it assembles to. */
3439 md_assemble (char *line
)
3442 char mnemonic
[MAX_MNEM_SIZE
];
3443 const insn_template
*t
;
3445 /* Initialize globals. */
3446 memset (&i
, '\0', sizeof (i
));
3447 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3448 i
.reloc
[j
] = NO_RELOC
;
3449 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3450 memset (im_expressions
, '\0', sizeof (im_expressions
));
3451 save_stack_p
= save_stack
;
3453 /* First parse an instruction mnemonic & call i386_operand for the operands.
3454 We assume that the scrubber has arranged it so that line[0] is the valid
3455 start of a (possibly prefixed) mnemonic. */
3457 line
= parse_insn (line
, mnemonic
);
3461 line
= parse_operands (line
, mnemonic
);
3466 /* Now we've parsed the mnemonic into a set of templates, and have the
3467 operands at hand. */
3469 /* All intel opcodes have reversed operands except for "bound" and
3470 "enter". We also don't reverse intersegment "jmp" and "call"
3471 instructions with 2 immediate operands so that the immediate segment
3472 precedes the offset, as it does when in AT&T mode. */
3475 && (strcmp (mnemonic
, "bound") != 0)
3476 && (strcmp (mnemonic
, "invlpga") != 0)
3477 && !(operand_type_check (i
.types
[0], imm
)
3478 && operand_type_check (i
.types
[1], imm
)))
3481 /* The order of the immediates should be reversed
3482 for 2 immediates extrq and insertq instructions */
3483 if (i
.imm_operands
== 2
3484 && (strcmp (mnemonic
, "extrq") == 0
3485 || strcmp (mnemonic
, "insertq") == 0))
3486 swap_2_operands (0, 1);
3491 /* Don't optimize displacement for movabs since it only takes 64bit
3494 && i
.disp_encoding
!= disp_encoding_32bit
3495 && (flag_code
!= CODE_64BIT
3496 || strcmp (mnemonic
, "movabs") != 0))
3499 /* Next, we find a template that matches the given insn,
3500 making sure the overlap of the given operands types is consistent
3501 with the template operand types. */
3503 if (!(t
= match_template ()))
3506 if (sse_check
!= check_none
3507 && !i
.tm
.opcode_modifier
.noavx
3508 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3509 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3510 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3511 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3512 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3513 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3515 (sse_check
== check_warning
3517 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3520 /* Zap movzx and movsx suffix. The suffix has been set from
3521 "word ptr" or "byte ptr" on the source operand in Intel syntax
3522 or extracted from mnemonic in AT&T syntax. But we'll use
3523 the destination register to choose the suffix for encoding. */
3524 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3526 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3527 there is no suffix, the default will be byte extension. */
3528 if (i
.reg_operands
!= 2
3531 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3536 if (i
.tm
.opcode_modifier
.fwait
)
3537 if (!add_prefix (FWAIT_OPCODE
))
3540 /* Check if REP prefix is OK. */
3541 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3543 as_bad (_("invalid instruction `%s' after `%s'"),
3544 i
.tm
.name
, i
.rep_prefix
);
3548 /* Check for lock without a lockable instruction. Destination operand
3549 must be memory unless it is xchg (0x86). */
3550 if (i
.prefix
[LOCK_PREFIX
]
3551 && (!i
.tm
.opcode_modifier
.islockable
3552 || i
.mem_operands
== 0
3553 || (i
.tm
.base_opcode
!= 0x86
3554 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3556 as_bad (_("expecting lockable instruction after `lock'"));
3560 /* Check if HLE prefix is OK. */
3561 if (i
.hle_prefix
&& !check_hle ())
3564 /* Check BND prefix. */
3565 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3566 as_bad (_("expecting valid branch instruction after `bnd'"));
3568 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3569 && flag_code
== CODE_64BIT
3570 && i
.prefix
[ADDR_PREFIX
])
3571 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3573 /* Insert BND prefix. */
3575 && i
.tm
.opcode_modifier
.bndprefixok
3576 && !i
.prefix
[BND_PREFIX
])
3577 add_prefix (BND_PREFIX_OPCODE
);
3579 /* Check string instruction segment overrides. */
3580 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3582 if (!check_string ())
3584 i
.disp_operands
= 0;
3587 if (!process_suffix ())
3590 /* Update operand types. */
3591 for (j
= 0; j
< i
.operands
; j
++)
3592 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3594 /* Make still unresolved immediate matches conform to size of immediate
3595 given in i.suffix. */
3596 if (!finalize_imm ())
3599 if (i
.types
[0].bitfield
.imm1
)
3600 i
.imm_operands
= 0; /* kludge for shift insns. */
3602 /* We only need to check those implicit registers for instructions
3603 with 3 operands or less. */
3604 if (i
.operands
<= 3)
3605 for (j
= 0; j
< i
.operands
; j
++)
3606 if (i
.types
[j
].bitfield
.inoutportreg
3607 || i
.types
[j
].bitfield
.shiftcount
3608 || i
.types
[j
].bitfield
.acc
3609 || i
.types
[j
].bitfield
.floatacc
)
3612 /* ImmExt should be processed after SSE2AVX. */
3613 if (!i
.tm
.opcode_modifier
.sse2avx
3614 && i
.tm
.opcode_modifier
.immext
)
3617 /* For insns with operands there are more diddles to do to the opcode. */
3620 if (!process_operands ())
3623 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3625 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3626 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3629 if (i
.tm
.opcode_modifier
.vex
)
3630 build_vex_prefix (t
);
3632 if (i
.tm
.opcode_modifier
.evex
)
3633 build_evex_prefix ();
3635 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3636 instructions may define INT_OPCODE as well, so avoid this corner
3637 case for those instructions that use MODRM. */
3638 if (i
.tm
.base_opcode
== INT_OPCODE
3639 && !i
.tm
.opcode_modifier
.modrm
3640 && i
.op
[0].imms
->X_add_number
== 3)
3642 i
.tm
.base_opcode
= INT3_OPCODE
;
3646 if ((i
.tm
.opcode_modifier
.jump
3647 || i
.tm
.opcode_modifier
.jumpbyte
3648 || i
.tm
.opcode_modifier
.jumpdword
)
3649 && i
.op
[0].disps
->X_op
== O_constant
)
3651 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3652 the absolute address given by the constant. Since ix86 jumps and
3653 calls are pc relative, we need to generate a reloc. */
3654 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3655 i
.op
[0].disps
->X_op
= O_symbol
;
3658 if (i
.tm
.opcode_modifier
.rex64
)
3661 /* For 8 bit registers we need an empty rex prefix. Also if the
3662 instruction already has a prefix, we need to convert old
3663 registers to new ones. */
3665 if ((i
.types
[0].bitfield
.reg8
3666 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3667 || (i
.types
[1].bitfield
.reg8
3668 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3669 || ((i
.types
[0].bitfield
.reg8
3670 || i
.types
[1].bitfield
.reg8
)
3675 i
.rex
|= REX_OPCODE
;
3676 for (x
= 0; x
< 2; x
++)
3678 /* Look for 8 bit operand that uses old registers. */
3679 if (i
.types
[x
].bitfield
.reg8
3680 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3682 /* In case it is "hi" register, give up. */
3683 if (i
.op
[x
].regs
->reg_num
> 3)
3684 as_bad (_("can't encode register '%s%s' in an "
3685 "instruction requiring REX prefix."),
3686 register_prefix
, i
.op
[x
].regs
->reg_name
);
3688 /* Otherwise it is equivalent to the extended register.
3689 Since the encoding doesn't change this is merely
3690 cosmetic cleanup for debug output. */
3692 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3698 add_prefix (REX_OPCODE
| i
.rex
);
3700 /* We are ready to output the insn. */
3705 parse_insn (char *line
, char *mnemonic
)
3708 char *token_start
= l
;
3711 const insn_template
*t
;
3717 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3722 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3724 as_bad (_("no such instruction: `%s'"), token_start
);
3729 if (!is_space_char (*l
)
3730 && *l
!= END_OF_INSN
3732 || (*l
!= PREFIX_SEPARATOR
3735 as_bad (_("invalid character %s in mnemonic"),
3736 output_invalid (*l
));
3739 if (token_start
== l
)
3741 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3742 as_bad (_("expecting prefix; got nothing"));
3744 as_bad (_("expecting mnemonic; got nothing"));
3748 /* Look up instruction (or prefix) via hash table. */
3749 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3751 if (*l
!= END_OF_INSN
3752 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3753 && current_templates
3754 && current_templates
->start
->opcode_modifier
.isprefix
)
3756 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3758 as_bad ((flag_code
!= CODE_64BIT
3759 ? _("`%s' is only supported in 64-bit mode")
3760 : _("`%s' is not supported in 64-bit mode")),
3761 current_templates
->start
->name
);
3764 /* If we are in 16-bit mode, do not allow addr16 or data16.
3765 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3766 if ((current_templates
->start
->opcode_modifier
.size16
3767 || current_templates
->start
->opcode_modifier
.size32
)
3768 && flag_code
!= CODE_64BIT
3769 && (current_templates
->start
->opcode_modifier
.size32
3770 ^ (flag_code
== CODE_16BIT
)))
3772 as_bad (_("redundant %s prefix"),
3773 current_templates
->start
->name
);
3776 /* Add prefix, checking for repeated prefixes. */
3777 switch (add_prefix (current_templates
->start
->base_opcode
))
3782 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3783 i
.hle_prefix
= current_templates
->start
->name
;
3784 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3785 i
.bnd_prefix
= current_templates
->start
->name
;
3787 i
.rep_prefix
= current_templates
->start
->name
;
3792 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3799 if (!current_templates
)
3801 /* Check if we should swap operand or force 32bit displacement in
3803 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3805 else if (mnem_p
- 3 == dot_p
3808 i
.disp_encoding
= disp_encoding_8bit
;
3809 else if (mnem_p
- 4 == dot_p
3813 i
.disp_encoding
= disp_encoding_32bit
;
3818 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3821 if (!current_templates
)
3824 /* See if we can get a match by trimming off a suffix. */
3827 case WORD_MNEM_SUFFIX
:
3828 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3829 i
.suffix
= SHORT_MNEM_SUFFIX
;
3831 case BYTE_MNEM_SUFFIX
:
3832 case QWORD_MNEM_SUFFIX
:
3833 i
.suffix
= mnem_p
[-1];
3835 current_templates
= (const templates
*) hash_find (op_hash
,
3838 case SHORT_MNEM_SUFFIX
:
3839 case LONG_MNEM_SUFFIX
:
3842 i
.suffix
= mnem_p
[-1];
3844 current_templates
= (const templates
*) hash_find (op_hash
,
3853 if (intel_float_operand (mnemonic
) == 1)
3854 i
.suffix
= SHORT_MNEM_SUFFIX
;
3856 i
.suffix
= LONG_MNEM_SUFFIX
;
3858 current_templates
= (const templates
*) hash_find (op_hash
,
3863 if (!current_templates
)
3865 as_bad (_("no such instruction: `%s'"), token_start
);
3870 if (current_templates
->start
->opcode_modifier
.jump
3871 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3873 /* Check for a branch hint. We allow ",pt" and ",pn" for
3874 predict taken and predict not taken respectively.
3875 I'm not sure that branch hints actually do anything on loop
3876 and jcxz insns (JumpByte) for current Pentium4 chips. They
3877 may work in the future and it doesn't hurt to accept them
3879 if (l
[0] == ',' && l
[1] == 'p')
3883 if (!add_prefix (DS_PREFIX_OPCODE
))
3887 else if (l
[2] == 'n')
3889 if (!add_prefix (CS_PREFIX_OPCODE
))
3895 /* Any other comma loses. */
3898 as_bad (_("invalid character %s in mnemonic"),
3899 output_invalid (*l
));
3903 /* Check if instruction is supported on specified architecture. */
3905 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3907 supported
|= cpu_flags_match (t
);
3908 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3912 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3914 as_bad (flag_code
== CODE_64BIT
3915 ? _("`%s' is not supported in 64-bit mode")
3916 : _("`%s' is only supported in 64-bit mode"),
3917 current_templates
->start
->name
);
3920 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3922 as_bad (_("`%s' is not supported on `%s%s'"),
3923 current_templates
->start
->name
,
3924 cpu_arch_name
? cpu_arch_name
: default_arch
,
3925 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3930 if (!cpu_arch_flags
.bitfield
.cpui386
3931 && (flag_code
!= CODE_16BIT
))
3933 as_warn (_("use .code16 to ensure correct addressing mode"));
3940 parse_operands (char *l
, const char *mnemonic
)
3944 /* 1 if operand is pending after ','. */
3945 unsigned int expecting_operand
= 0;
3947 /* Non-zero if operand parens not balanced. */
3948 unsigned int paren_not_balanced
;
3950 while (*l
!= END_OF_INSN
)
3952 /* Skip optional white space before operand. */
3953 if (is_space_char (*l
))
3955 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3957 as_bad (_("invalid character %s before operand %d"),
3958 output_invalid (*l
),
3962 token_start
= l
; /* after white space */
3963 paren_not_balanced
= 0;
3964 while (paren_not_balanced
|| *l
!= ',')
3966 if (*l
== END_OF_INSN
)
3968 if (paren_not_balanced
)
3971 as_bad (_("unbalanced parenthesis in operand %d."),
3974 as_bad (_("unbalanced brackets in operand %d."),
3979 break; /* we are done */
3981 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3983 as_bad (_("invalid character %s in operand %d"),
3984 output_invalid (*l
),
3991 ++paren_not_balanced
;
3993 --paren_not_balanced
;
3998 ++paren_not_balanced
;
4000 --paren_not_balanced
;
4004 if (l
!= token_start
)
4005 { /* Yes, we've read in another operand. */
4006 unsigned int operand_ok
;
4007 this_operand
= i
.operands
++;
4008 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4009 if (i
.operands
> MAX_OPERANDS
)
4011 as_bad (_("spurious operands; (%d operands/instruction max)"),
4015 /* Now parse operand adding info to 'i' as we go along. */
4016 END_STRING_AND_SAVE (l
);
4020 i386_intel_operand (token_start
,
4021 intel_float_operand (mnemonic
));
4023 operand_ok
= i386_att_operand (token_start
);
4025 RESTORE_END_STRING (l
);
4031 if (expecting_operand
)
4033 expecting_operand_after_comma
:
4034 as_bad (_("expecting operand after ','; got nothing"));
4039 as_bad (_("expecting operand before ','; got nothing"));
4044 /* Now *l must be either ',' or END_OF_INSN. */
4047 if (*++l
== END_OF_INSN
)
4049 /* Just skip it, if it's \n complain. */
4050 goto expecting_operand_after_comma
;
4052 expecting_operand
= 1;
4059 swap_2_operands (int xchg1
, int xchg2
)
4061 union i386_op temp_op
;
4062 i386_operand_type temp_type
;
4063 enum bfd_reloc_code_real temp_reloc
;
4065 temp_type
= i
.types
[xchg2
];
4066 i
.types
[xchg2
] = i
.types
[xchg1
];
4067 i
.types
[xchg1
] = temp_type
;
4068 temp_op
= i
.op
[xchg2
];
4069 i
.op
[xchg2
] = i
.op
[xchg1
];
4070 i
.op
[xchg1
] = temp_op
;
4071 temp_reloc
= i
.reloc
[xchg2
];
4072 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4073 i
.reloc
[xchg1
] = temp_reloc
;
4077 if (i
.mask
->operand
== xchg1
)
4078 i
.mask
->operand
= xchg2
;
4079 else if (i
.mask
->operand
== xchg2
)
4080 i
.mask
->operand
= xchg1
;
4084 if (i
.broadcast
->operand
== xchg1
)
4085 i
.broadcast
->operand
= xchg2
;
4086 else if (i
.broadcast
->operand
== xchg2
)
4087 i
.broadcast
->operand
= xchg1
;
4091 if (i
.rounding
->operand
== xchg1
)
4092 i
.rounding
->operand
= xchg2
;
4093 else if (i
.rounding
->operand
== xchg2
)
4094 i
.rounding
->operand
= xchg1
;
4099 swap_operands (void)
4105 swap_2_operands (1, i
.operands
- 2);
4108 swap_2_operands (0, i
.operands
- 1);
4114 if (i
.mem_operands
== 2)
4116 const seg_entry
*temp_seg
;
4117 temp_seg
= i
.seg
[0];
4118 i
.seg
[0] = i
.seg
[1];
4119 i
.seg
[1] = temp_seg
;
4123 /* Try to ensure constant immediates are represented in the smallest
4128 char guess_suffix
= 0;
4132 guess_suffix
= i
.suffix
;
4133 else if (i
.reg_operands
)
4135 /* Figure out a suffix from the last register operand specified.
4136 We can't do this properly yet, ie. excluding InOutPortReg,
4137 but the following works for instructions with immediates.
4138 In any case, we can't set i.suffix yet. */
4139 for (op
= i
.operands
; --op
>= 0;)
4140 if (i
.types
[op
].bitfield
.reg8
)
4142 guess_suffix
= BYTE_MNEM_SUFFIX
;
4145 else if (i
.types
[op
].bitfield
.reg16
)
4147 guess_suffix
= WORD_MNEM_SUFFIX
;
4150 else if (i
.types
[op
].bitfield
.reg32
)
4152 guess_suffix
= LONG_MNEM_SUFFIX
;
4155 else if (i
.types
[op
].bitfield
.reg64
)
4157 guess_suffix
= QWORD_MNEM_SUFFIX
;
4161 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4162 guess_suffix
= WORD_MNEM_SUFFIX
;
4164 for (op
= i
.operands
; --op
>= 0;)
4165 if (operand_type_check (i
.types
[op
], imm
))
4167 switch (i
.op
[op
].imms
->X_op
)
4170 /* If a suffix is given, this operand may be shortened. */
4171 switch (guess_suffix
)
4173 case LONG_MNEM_SUFFIX
:
4174 i
.types
[op
].bitfield
.imm32
= 1;
4175 i
.types
[op
].bitfield
.imm64
= 1;
4177 case WORD_MNEM_SUFFIX
:
4178 i
.types
[op
].bitfield
.imm16
= 1;
4179 i
.types
[op
].bitfield
.imm32
= 1;
4180 i
.types
[op
].bitfield
.imm32s
= 1;
4181 i
.types
[op
].bitfield
.imm64
= 1;
4183 case BYTE_MNEM_SUFFIX
:
4184 i
.types
[op
].bitfield
.imm8
= 1;
4185 i
.types
[op
].bitfield
.imm8s
= 1;
4186 i
.types
[op
].bitfield
.imm16
= 1;
4187 i
.types
[op
].bitfield
.imm32
= 1;
4188 i
.types
[op
].bitfield
.imm32s
= 1;
4189 i
.types
[op
].bitfield
.imm64
= 1;
4193 /* If this operand is at most 16 bits, convert it
4194 to a signed 16 bit number before trying to see
4195 whether it will fit in an even smaller size.
4196 This allows a 16-bit operand such as $0xffe0 to
4197 be recognised as within Imm8S range. */
4198 if ((i
.types
[op
].bitfield
.imm16
)
4199 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4201 i
.op
[op
].imms
->X_add_number
=
4202 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4204 if ((i
.types
[op
].bitfield
.imm32
)
4205 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4208 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4209 ^ ((offsetT
) 1 << 31))
4210 - ((offsetT
) 1 << 31));
4213 = operand_type_or (i
.types
[op
],
4214 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4216 /* We must avoid matching of Imm32 templates when 64bit
4217 only immediate is available. */
4218 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4219 i
.types
[op
].bitfield
.imm32
= 0;
4226 /* Symbols and expressions. */
4228 /* Convert symbolic operand to proper sizes for matching, but don't
4229 prevent matching a set of insns that only supports sizes other
4230 than those matching the insn suffix. */
4232 i386_operand_type mask
, allowed
;
4233 const insn_template
*t
;
4235 operand_type_set (&mask
, 0);
4236 operand_type_set (&allowed
, 0);
4238 for (t
= current_templates
->start
;
4239 t
< current_templates
->end
;
4241 allowed
= operand_type_or (allowed
,
4242 t
->operand_types
[op
]);
4243 switch (guess_suffix
)
4245 case QWORD_MNEM_SUFFIX
:
4246 mask
.bitfield
.imm64
= 1;
4247 mask
.bitfield
.imm32s
= 1;
4249 case LONG_MNEM_SUFFIX
:
4250 mask
.bitfield
.imm32
= 1;
4252 case WORD_MNEM_SUFFIX
:
4253 mask
.bitfield
.imm16
= 1;
4255 case BYTE_MNEM_SUFFIX
:
4256 mask
.bitfield
.imm8
= 1;
4261 allowed
= operand_type_and (mask
, allowed
);
4262 if (!operand_type_all_zero (&allowed
))
4263 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4270 /* Try to use the smallest displacement type too. */
4272 optimize_disp (void)
4276 for (op
= i
.operands
; --op
>= 0;)
4277 if (operand_type_check (i
.types
[op
], disp
))
4279 if (i
.op
[op
].disps
->X_op
== O_constant
)
4281 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4283 if (i
.types
[op
].bitfield
.disp16
4284 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4286 /* If this operand is at most 16 bits, convert
4287 to a signed 16 bit number and don't use 64bit
4289 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4290 i
.types
[op
].bitfield
.disp64
= 0;
4292 if (i
.types
[op
].bitfield
.disp32
4293 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4295 /* If this operand is at most 32 bits, convert
4296 to a signed 32 bit number and don't use 64bit
4298 op_disp
&= (((offsetT
) 2 << 31) - 1);
4299 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4300 i
.types
[op
].bitfield
.disp64
= 0;
4302 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4304 i
.types
[op
].bitfield
.disp8
= 0;
4305 i
.types
[op
].bitfield
.disp16
= 0;
4306 i
.types
[op
].bitfield
.disp32
= 0;
4307 i
.types
[op
].bitfield
.disp32s
= 0;
4308 i
.types
[op
].bitfield
.disp64
= 0;
4312 else if (flag_code
== CODE_64BIT
)
4314 if (fits_in_signed_long (op_disp
))
4316 i
.types
[op
].bitfield
.disp64
= 0;
4317 i
.types
[op
].bitfield
.disp32s
= 1;
4319 if (i
.prefix
[ADDR_PREFIX
]
4320 && fits_in_unsigned_long (op_disp
))
4321 i
.types
[op
].bitfield
.disp32
= 1;
4323 if ((i
.types
[op
].bitfield
.disp32
4324 || i
.types
[op
].bitfield
.disp32s
4325 || i
.types
[op
].bitfield
.disp16
)
4326 && fits_in_signed_byte (op_disp
))
4327 i
.types
[op
].bitfield
.disp8
= 1;
4329 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4330 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4332 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4333 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4334 i
.types
[op
].bitfield
.disp8
= 0;
4335 i
.types
[op
].bitfield
.disp16
= 0;
4336 i
.types
[op
].bitfield
.disp32
= 0;
4337 i
.types
[op
].bitfield
.disp32s
= 0;
4338 i
.types
[op
].bitfield
.disp64
= 0;
4341 /* We only support 64bit displacement on constants. */
4342 i
.types
[op
].bitfield
.disp64
= 0;
4346 /* Check if operands are valid for the instruction. */
4349 check_VecOperands (const insn_template
*t
)
4353 /* Without VSIB byte, we can't have a vector register for index. */
4354 if (!t
->opcode_modifier
.vecsib
4356 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4357 || i
.index_reg
->reg_type
.bitfield
.regymm
4358 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4360 i
.error
= unsupported_vector_index_register
;
4364 /* Check if default mask is allowed. */
4365 if (t
->opcode_modifier
.nodefmask
4366 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4368 i
.error
= no_default_mask
;
4372 /* For VSIB byte, we need a vector register for index, and all vector
4373 registers must be distinct. */
4374 if (t
->opcode_modifier
.vecsib
)
4377 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4378 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4379 || (t
->opcode_modifier
.vecsib
== VecSIB256
4380 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4381 || (t
->opcode_modifier
.vecsib
== VecSIB512
4382 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4384 i
.error
= invalid_vsib_address
;
4388 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4389 if (i
.reg_operands
== 2 && !i
.mask
)
4391 gas_assert (i
.types
[0].bitfield
.regxmm
4392 || i
.types
[0].bitfield
.regymm
);
4393 gas_assert (i
.types
[2].bitfield
.regxmm
4394 || i
.types
[2].bitfield
.regymm
);
4395 if (operand_check
== check_none
)
4397 if (register_number (i
.op
[0].regs
)
4398 != register_number (i
.index_reg
)
4399 && register_number (i
.op
[2].regs
)
4400 != register_number (i
.index_reg
)
4401 && register_number (i
.op
[0].regs
)
4402 != register_number (i
.op
[2].regs
))
4404 if (operand_check
== check_error
)
4406 i
.error
= invalid_vector_register_set
;
4409 as_warn (_("mask, index, and destination registers should be distinct"));
4411 else if (i
.reg_operands
== 1 && i
.mask
)
4413 if ((i
.types
[1].bitfield
.regymm
4414 || i
.types
[1].bitfield
.regzmm
)
4415 && (register_number (i
.op
[1].regs
)
4416 == register_number (i
.index_reg
)))
4418 if (operand_check
== check_error
)
4420 i
.error
= invalid_vector_register_set
;
4423 if (operand_check
!= check_none
)
4424 as_warn (_("index and destination registers should be distinct"));
4429 /* Check if broadcast is supported by the instruction and is applied
4430 to the memory operand. */
4433 int broadcasted_opnd_size
;
4435 /* Check if specified broadcast is supported in this instruction,
4436 and it's applied to memory operand of DWORD or QWORD type,
4437 depending on VecESize. */
4438 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4439 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4440 || (t
->opcode_modifier
.vecesize
== 0
4441 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4442 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4443 || (t
->opcode_modifier
.vecesize
== 1
4444 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4445 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4448 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4449 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4450 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4451 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4452 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4456 if ((broadcasted_opnd_size
== 256
4457 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4458 || (broadcasted_opnd_size
== 512
4459 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4462 i
.error
= unsupported_broadcast
;
4466 /* If broadcast is supported in this instruction, we need to check if
4467 operand of one-element size isn't specified without broadcast. */
4468 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4470 /* Find memory operand. */
4471 for (op
= 0; op
< i
.operands
; op
++)
4472 if (operand_type_check (i
.types
[op
], anymem
))
4474 gas_assert (op
< i
.operands
);
4475 /* Check size of the memory operand. */
4476 if ((t
->opcode_modifier
.vecesize
== 0
4477 && i
.types
[op
].bitfield
.dword
)
4478 || (t
->opcode_modifier
.vecesize
== 1
4479 && i
.types
[op
].bitfield
.qword
))
4481 i
.error
= broadcast_needed
;
4486 /* Check if requested masking is supported. */
4488 && (!t
->opcode_modifier
.masking
4490 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4492 i
.error
= unsupported_masking
;
4496 /* Check if masking is applied to dest operand. */
4497 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4499 i
.error
= mask_not_on_destination
;
4506 if ((i
.rounding
->type
!= saeonly
4507 && !t
->opcode_modifier
.staticrounding
)
4508 || (i
.rounding
->type
== saeonly
4509 && (t
->opcode_modifier
.staticrounding
4510 || !t
->opcode_modifier
.sae
)))
4512 i
.error
= unsupported_rc_sae
;
4515 /* If the instruction has several immediate operands and one of
4516 them is rounding, the rounding operand should be the last
4517 immediate operand. */
4518 if (i
.imm_operands
> 1
4519 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4521 i
.error
= rc_sae_operand_not_last_imm
;
4526 /* Check vector Disp8 operand. */
4527 if (t
->opcode_modifier
.disp8memshift
)
4530 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4532 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4534 for (op
= 0; op
< i
.operands
; op
++)
4535 if (operand_type_check (i
.types
[op
], disp
)
4536 && i
.op
[op
].disps
->X_op
== O_constant
)
4538 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4539 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4540 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4543 i
.types
[op
].bitfield
.vec_disp8
= 1;
4546 /* Vector insn can only have Vec_Disp8/Disp32 in
4547 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4549 i
.types
[op
].bitfield
.disp8
= 0;
4550 if (flag_code
!= CODE_16BIT
)
4551 i
.types
[op
].bitfield
.disp16
= 0;
4554 else if (flag_code
!= CODE_16BIT
)
4556 /* One form of this instruction supports vector Disp8.
4557 Try vector Disp8 if we need to use Disp32. */
4558 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4560 i
.error
= try_vector_disp8
;
4572 /* Check if operands are valid for the instruction. Update VEX
4576 VEX_check_operands (const insn_template
*t
)
4578 /* VREX is only valid with EVEX prefix. */
4579 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4581 i
.error
= invalid_register_operand
;
4585 if (!t
->opcode_modifier
.vex
)
4588 /* Only check VEX_Imm4, which must be the first operand. */
4589 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4591 if (i
.op
[0].imms
->X_op
!= O_constant
4592 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4598 /* Turn off Imm8 so that update_imm won't complain. */
4599 i
.types
[0] = vec_imm4
;
4605 static const insn_template
*
4606 match_template (void)
4608 /* Points to template once we've found it. */
4609 const insn_template
*t
;
4610 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4611 i386_operand_type overlap4
;
4612 unsigned int found_reverse_match
;
4613 i386_opcode_modifier suffix_check
;
4614 i386_operand_type operand_types
[MAX_OPERANDS
];
4615 int addr_prefix_disp
;
4617 unsigned int found_cpu_match
;
4618 unsigned int check_register
;
4619 enum i386_error specific_error
= 0;
4621 #if MAX_OPERANDS != 5
4622 # error "MAX_OPERANDS must be 5."
4625 found_reverse_match
= 0;
4626 addr_prefix_disp
= -1;
4628 memset (&suffix_check
, 0, sizeof (suffix_check
));
4629 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4630 suffix_check
.no_bsuf
= 1;
4631 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4632 suffix_check
.no_wsuf
= 1;
4633 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4634 suffix_check
.no_ssuf
= 1;
4635 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4636 suffix_check
.no_lsuf
= 1;
4637 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4638 suffix_check
.no_qsuf
= 1;
4639 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4640 suffix_check
.no_ldsuf
= 1;
4642 /* Must have right number of operands. */
4643 i
.error
= number_of_operands_mismatch
;
4645 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4647 addr_prefix_disp
= -1;
4649 if (i
.operands
!= t
->operands
)
4652 /* Check processor support. */
4653 i
.error
= unsupported
;
4654 found_cpu_match
= (cpu_flags_match (t
)
4655 == CPU_FLAGS_PERFECT_MATCH
);
4656 if (!found_cpu_match
)
4659 /* Check old gcc support. */
4660 i
.error
= old_gcc_only
;
4661 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4664 /* Check AT&T mnemonic. */
4665 i
.error
= unsupported_with_intel_mnemonic
;
4666 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4669 /* Check AT&T/Intel syntax. */
4670 i
.error
= unsupported_syntax
;
4671 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4672 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4675 /* Check the suffix, except for some instructions in intel mode. */
4676 i
.error
= invalid_instruction_suffix
;
4677 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4678 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4679 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4680 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4681 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4682 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4683 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4686 if (!operand_size_match (t
))
4689 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4690 operand_types
[j
] = t
->operand_types
[j
];
4692 /* In general, don't allow 64-bit operands in 32-bit mode. */
4693 if (i
.suffix
== QWORD_MNEM_SUFFIX
4694 && flag_code
!= CODE_64BIT
4696 ? (!t
->opcode_modifier
.ignoresize
4697 && !intel_float_operand (t
->name
))
4698 : intel_float_operand (t
->name
) != 2)
4699 && ((!operand_types
[0].bitfield
.regmmx
4700 && !operand_types
[0].bitfield
.regxmm
4701 && !operand_types
[0].bitfield
.regymm
4702 && !operand_types
[0].bitfield
.regzmm
)
4703 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4704 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4705 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
4706 && !!operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4707 && (t
->base_opcode
!= 0x0fc7
4708 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4711 /* In general, don't allow 32-bit operands on pre-386. */
4712 else if (i
.suffix
== LONG_MNEM_SUFFIX
4713 && !cpu_arch_flags
.bitfield
.cpui386
4715 ? (!t
->opcode_modifier
.ignoresize
4716 && !intel_float_operand (t
->name
))
4717 : intel_float_operand (t
->name
) != 2)
4718 && ((!operand_types
[0].bitfield
.regmmx
4719 && !operand_types
[0].bitfield
.regxmm
)
4720 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4721 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4724 /* Do not verify operands when there are none. */
4728 /* We've found a match; break out of loop. */
4732 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4733 into Disp32/Disp16/Disp32 operand. */
4734 if (i
.prefix
[ADDR_PREFIX
] != 0)
4736 /* There should be only one Disp operand. */
4740 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4742 if (operand_types
[j
].bitfield
.disp16
)
4744 addr_prefix_disp
= j
;
4745 operand_types
[j
].bitfield
.disp32
= 1;
4746 operand_types
[j
].bitfield
.disp16
= 0;
4752 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4754 if (operand_types
[j
].bitfield
.disp32
)
4756 addr_prefix_disp
= j
;
4757 operand_types
[j
].bitfield
.disp32
= 0;
4758 operand_types
[j
].bitfield
.disp16
= 1;
4764 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4766 if (operand_types
[j
].bitfield
.disp64
)
4768 addr_prefix_disp
= j
;
4769 operand_types
[j
].bitfield
.disp64
= 0;
4770 operand_types
[j
].bitfield
.disp32
= 1;
4778 /* We check register size if needed. */
4779 check_register
= t
->opcode_modifier
.checkregsize
;
4780 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4781 switch (t
->operands
)
4784 if (!operand_type_match (overlap0
, i
.types
[0]))
4788 /* xchg %eax, %eax is a special case. It is an aliase for nop
4789 only in 32bit mode and we can use opcode 0x90. In 64bit
4790 mode, we can't use 0x90 for xchg %eax, %eax since it should
4791 zero-extend %eax to %rax. */
4792 if (flag_code
== CODE_64BIT
4793 && t
->base_opcode
== 0x90
4794 && operand_type_equal (&i
.types
[0], &acc32
)
4795 && operand_type_equal (&i
.types
[1], &acc32
))
4799 /* If we swap operand in encoding, we either match
4800 the next one or reverse direction of operands. */
4801 if (t
->opcode_modifier
.s
)
4803 else if (t
->opcode_modifier
.d
)
4808 /* If we swap operand in encoding, we match the next one. */
4809 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4813 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4814 if (!operand_type_match (overlap0
, i
.types
[0])
4815 || !operand_type_match (overlap1
, i
.types
[1])
4817 && !operand_type_register_match (overlap0
, i
.types
[0],
4819 overlap1
, i
.types
[1],
4822 /* Check if other direction is valid ... */
4823 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4827 /* Try reversing direction of operands. */
4828 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4829 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4830 if (!operand_type_match (overlap0
, i
.types
[0])
4831 || !operand_type_match (overlap1
, i
.types
[1])
4833 && !operand_type_register_match (overlap0
,
4840 /* Does not match either direction. */
4843 /* found_reverse_match holds which of D or FloatDR
4845 if (t
->opcode_modifier
.d
)
4846 found_reverse_match
= Opcode_D
;
4847 else if (t
->opcode_modifier
.floatd
)
4848 found_reverse_match
= Opcode_FloatD
;
4850 found_reverse_match
= 0;
4851 if (t
->opcode_modifier
.floatr
)
4852 found_reverse_match
|= Opcode_FloatR
;
4856 /* Found a forward 2 operand match here. */
4857 switch (t
->operands
)
4860 overlap4
= operand_type_and (i
.types
[4],
4863 overlap3
= operand_type_and (i
.types
[3],
4866 overlap2
= operand_type_and (i
.types
[2],
4871 switch (t
->operands
)
4874 if (!operand_type_match (overlap4
, i
.types
[4])
4875 || !operand_type_register_match (overlap3
,
4883 if (!operand_type_match (overlap3
, i
.types
[3])
4885 && !operand_type_register_match (overlap2
,
4893 /* Here we make use of the fact that there are no
4894 reverse match 3 operand instructions, and all 3
4895 operand instructions only need to be checked for
4896 register consistency between operands 2 and 3. */
4897 if (!operand_type_match (overlap2
, i
.types
[2])
4899 && !operand_type_register_match (overlap1
,
4909 /* Found either forward/reverse 2, 3 or 4 operand match here:
4910 slip through to break. */
4912 if (!found_cpu_match
)
4914 found_reverse_match
= 0;
4918 /* Check if vector and VEX operands are valid. */
4919 if (check_VecOperands (t
) || VEX_check_operands (t
))
4921 specific_error
= i
.error
;
4925 /* We've found a match; break out of loop. */
4929 if (t
== current_templates
->end
)
4931 /* We found no match. */
4932 const char *err_msg
;
4933 switch (specific_error
? specific_error
: i
.error
)
4937 case operand_size_mismatch
:
4938 err_msg
= _("operand size mismatch");
4940 case operand_type_mismatch
:
4941 err_msg
= _("operand type mismatch");
4943 case register_type_mismatch
:
4944 err_msg
= _("register type mismatch");
4946 case number_of_operands_mismatch
:
4947 err_msg
= _("number of operands mismatch");
4949 case invalid_instruction_suffix
:
4950 err_msg
= _("invalid instruction suffix");
4953 err_msg
= _("constant doesn't fit in 4 bits");
4956 err_msg
= _("only supported with old gcc");
4958 case unsupported_with_intel_mnemonic
:
4959 err_msg
= _("unsupported with Intel mnemonic");
4961 case unsupported_syntax
:
4962 err_msg
= _("unsupported syntax");
4965 as_bad (_("unsupported instruction `%s'"),
4966 current_templates
->start
->name
);
4968 case invalid_vsib_address
:
4969 err_msg
= _("invalid VSIB address");
4971 case invalid_vector_register_set
:
4972 err_msg
= _("mask, index, and destination registers must be distinct");
4974 case unsupported_vector_index_register
:
4975 err_msg
= _("unsupported vector index register");
4977 case unsupported_broadcast
:
4978 err_msg
= _("unsupported broadcast");
4980 case broadcast_not_on_src_operand
:
4981 err_msg
= _("broadcast not on source memory operand");
4983 case broadcast_needed
:
4984 err_msg
= _("broadcast is needed for operand of such type");
4986 case unsupported_masking
:
4987 err_msg
= _("unsupported masking");
4989 case mask_not_on_destination
:
4990 err_msg
= _("mask not on destination operand");
4992 case no_default_mask
:
4993 err_msg
= _("default mask isn't allowed");
4995 case unsupported_rc_sae
:
4996 err_msg
= _("unsupported static rounding/sae");
4998 case rc_sae_operand_not_last_imm
:
5000 err_msg
= _("RC/SAE operand must precede immediate operands");
5002 err_msg
= _("RC/SAE operand must follow immediate operands");
5004 case invalid_register_operand
:
5005 err_msg
= _("invalid register operand");
5008 as_bad (_("%s for `%s'"), err_msg
,
5009 current_templates
->start
->name
);
5013 if (!quiet_warnings
)
5016 && (i
.types
[0].bitfield
.jumpabsolute
5017 != operand_types
[0].bitfield
.jumpabsolute
))
5019 as_warn (_("indirect %s without `*'"), t
->name
);
5022 if (t
->opcode_modifier
.isprefix
5023 && t
->opcode_modifier
.ignoresize
)
5025 /* Warn them that a data or address size prefix doesn't
5026 affect assembly of the next line of code. */
5027 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5031 /* Copy the template we found. */
5034 if (addr_prefix_disp
!= -1)
5035 i
.tm
.operand_types
[addr_prefix_disp
]
5036 = operand_types
[addr_prefix_disp
];
5038 if (found_reverse_match
)
5040 /* If we found a reverse match we must alter the opcode
5041 direction bit. found_reverse_match holds bits to change
5042 (different for int & float insns). */
5044 i
.tm
.base_opcode
^= found_reverse_match
;
5046 i
.tm
.operand_types
[0] = operand_types
[1];
5047 i
.tm
.operand_types
[1] = operand_types
[0];
5056 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5057 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5059 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5061 as_bad (_("`%s' operand %d must use `%ses' segment"),
5067 /* There's only ever one segment override allowed per instruction.
5068 This instruction possibly has a legal segment override on the
5069 second operand, so copy the segment to where non-string
5070 instructions store it, allowing common code. */
5071 i
.seg
[0] = i
.seg
[1];
5073 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5075 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5077 as_bad (_("`%s' operand %d must use `%ses' segment"),
5088 process_suffix (void)
5090 /* If matched instruction specifies an explicit instruction mnemonic
5092 if (i
.tm
.opcode_modifier
.size16
)
5093 i
.suffix
= WORD_MNEM_SUFFIX
;
5094 else if (i
.tm
.opcode_modifier
.size32
)
5095 i
.suffix
= LONG_MNEM_SUFFIX
;
5096 else if (i
.tm
.opcode_modifier
.size64
)
5097 i
.suffix
= QWORD_MNEM_SUFFIX
;
5098 else if (i
.reg_operands
)
5100 /* If there's no instruction mnemonic suffix we try to invent one
5101 based on register operands. */
5104 /* We take i.suffix from the last register operand specified,
5105 Destination register type is more significant than source
5106 register type. crc32 in SSE4.2 prefers source register
5108 if (i
.tm
.base_opcode
== 0xf20f38f1)
5110 if (i
.types
[0].bitfield
.reg16
)
5111 i
.suffix
= WORD_MNEM_SUFFIX
;
5112 else if (i
.types
[0].bitfield
.reg32
)
5113 i
.suffix
= LONG_MNEM_SUFFIX
;
5114 else if (i
.types
[0].bitfield
.reg64
)
5115 i
.suffix
= QWORD_MNEM_SUFFIX
;
5117 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5119 if (i
.types
[0].bitfield
.reg8
)
5120 i
.suffix
= BYTE_MNEM_SUFFIX
;
5127 if (i
.tm
.base_opcode
== 0xf20f38f1
5128 || i
.tm
.base_opcode
== 0xf20f38f0)
5130 /* We have to know the operand size for crc32. */
5131 as_bad (_("ambiguous memory operand size for `%s`"),
5136 for (op
= i
.operands
; --op
>= 0;)
5137 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5139 if (i
.types
[op
].bitfield
.reg8
)
5141 i
.suffix
= BYTE_MNEM_SUFFIX
;
5144 else if (i
.types
[op
].bitfield
.reg16
)
5146 i
.suffix
= WORD_MNEM_SUFFIX
;
5149 else if (i
.types
[op
].bitfield
.reg32
)
5151 i
.suffix
= LONG_MNEM_SUFFIX
;
5154 else if (i
.types
[op
].bitfield
.reg64
)
5156 i
.suffix
= QWORD_MNEM_SUFFIX
;
5162 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5165 && i
.tm
.opcode_modifier
.ignoresize
5166 && i
.tm
.opcode_modifier
.no_bsuf
)
5168 else if (!check_byte_reg ())
5171 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5174 && i
.tm
.opcode_modifier
.ignoresize
5175 && i
.tm
.opcode_modifier
.no_lsuf
)
5177 else if (!check_long_reg ())
5180 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5183 && i
.tm
.opcode_modifier
.ignoresize
5184 && i
.tm
.opcode_modifier
.no_qsuf
)
5186 else if (!check_qword_reg ())
5189 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5192 && i
.tm
.opcode_modifier
.ignoresize
5193 && i
.tm
.opcode_modifier
.no_wsuf
)
5195 else if (!check_word_reg ())
5198 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5199 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5200 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5202 /* Skip if the instruction has x/y/z suffix. match_template
5203 should check if it is a valid suffix. */
5205 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5206 /* Do nothing if the instruction is going to ignore the prefix. */
5211 else if (i
.tm
.opcode_modifier
.defaultsize
5213 /* exclude fldenv/frstor/fsave/fstenv */
5214 && i
.tm
.opcode_modifier
.no_ssuf
)
5216 i
.suffix
= stackop_size
;
5218 else if (intel_syntax
5220 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5221 || i
.tm
.opcode_modifier
.jumpbyte
5222 || i
.tm
.opcode_modifier
.jumpintersegment
5223 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5224 && i
.tm
.extension_opcode
<= 3)))
5229 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5231 i
.suffix
= QWORD_MNEM_SUFFIX
;
5235 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5236 i
.suffix
= LONG_MNEM_SUFFIX
;
5239 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5240 i
.suffix
= WORD_MNEM_SUFFIX
;
5249 if (i
.tm
.opcode_modifier
.w
)
5251 as_bad (_("no instruction mnemonic suffix given and "
5252 "no register operands; can't size instruction"));
5258 unsigned int suffixes
;
5260 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5261 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5263 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5265 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5267 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5269 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5272 /* There are more than suffix matches. */
5273 if (i
.tm
.opcode_modifier
.w
5274 || ((suffixes
& (suffixes
- 1))
5275 && !i
.tm
.opcode_modifier
.defaultsize
5276 && !i
.tm
.opcode_modifier
.ignoresize
))
5278 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5284 /* Change the opcode based on the operand size given by i.suffix;
5285 We don't need to change things for byte insns. */
5288 && i
.suffix
!= BYTE_MNEM_SUFFIX
5289 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5290 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5291 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5293 /* It's not a byte, select word/dword operation. */
5294 if (i
.tm
.opcode_modifier
.w
)
5296 if (i
.tm
.opcode_modifier
.shortform
)
5297 i
.tm
.base_opcode
|= 8;
5299 i
.tm
.base_opcode
|= 1;
5302 /* Now select between word & dword operations via the operand
5303 size prefix, except for instructions that will ignore this
5305 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5307 /* The address size override prefix changes the size of the
5309 if ((flag_code
== CODE_32BIT
5310 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5311 || (flag_code
!= CODE_32BIT
5312 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5313 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5316 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5317 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5318 && !i
.tm
.opcode_modifier
.ignoresize
5319 && !i
.tm
.opcode_modifier
.floatmf
5320 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5321 || (flag_code
== CODE_64BIT
5322 && i
.tm
.opcode_modifier
.jumpbyte
)))
5324 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5326 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5327 prefix
= ADDR_PREFIX_OPCODE
;
5329 if (!add_prefix (prefix
))
5333 /* Set mode64 for an operand. */
5334 if (i
.suffix
== QWORD_MNEM_SUFFIX
5335 && flag_code
== CODE_64BIT
5336 && !i
.tm
.opcode_modifier
.norex64
)
5338 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5339 need rex64. cmpxchg8b is also a special case. */
5340 if (! (i
.operands
== 2
5341 && i
.tm
.base_opcode
== 0x90
5342 && i
.tm
.extension_opcode
== None
5343 && operand_type_equal (&i
.types
[0], &acc64
)
5344 && operand_type_equal (&i
.types
[1], &acc64
))
5345 && ! (i
.operands
== 1
5346 && i
.tm
.base_opcode
== 0xfc7
5347 && i
.tm
.extension_opcode
== 1
5348 && !operand_type_check (i
.types
[0], reg
)
5349 && operand_type_check (i
.types
[0], anymem
)))
5353 /* Size floating point instruction. */
5354 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5355 if (i
.tm
.opcode_modifier
.floatmf
)
5356 i
.tm
.base_opcode
^= 4;
5363 check_byte_reg (void)
5367 for (op
= i
.operands
; --op
>= 0;)
5369 /* If this is an eight bit register, it's OK. If it's the 16 or
5370 32 bit version of an eight bit register, we will just use the
5371 low portion, and that's OK too. */
5372 if (i
.types
[op
].bitfield
.reg8
)
5375 /* I/O port address operands are OK too. */
5376 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5379 /* crc32 doesn't generate this warning. */
5380 if (i
.tm
.base_opcode
== 0xf20f38f0)
5383 if ((i
.types
[op
].bitfield
.reg16
5384 || i
.types
[op
].bitfield
.reg32
5385 || i
.types
[op
].bitfield
.reg64
)
5386 && i
.op
[op
].regs
->reg_num
< 4
5387 /* Prohibit these changes in 64bit mode, since the lowering
5388 would be more complicated. */
5389 && flag_code
!= CODE_64BIT
)
5391 #if REGISTER_WARNINGS
5392 if (!quiet_warnings
)
5393 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5395 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5396 ? REGNAM_AL
- REGNAM_AX
5397 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5399 i
.op
[op
].regs
->reg_name
,
5404 /* Any other register is bad. */
5405 if (i
.types
[op
].bitfield
.reg16
5406 || i
.types
[op
].bitfield
.reg32
5407 || i
.types
[op
].bitfield
.reg64
5408 || i
.types
[op
].bitfield
.regmmx
5409 || i
.types
[op
].bitfield
.regxmm
5410 || i
.types
[op
].bitfield
.regymm
5411 || i
.types
[op
].bitfield
.regzmm
5412 || i
.types
[op
].bitfield
.sreg2
5413 || i
.types
[op
].bitfield
.sreg3
5414 || i
.types
[op
].bitfield
.control
5415 || i
.types
[op
].bitfield
.debug
5416 || i
.types
[op
].bitfield
.test
5417 || i
.types
[op
].bitfield
.floatreg
5418 || i
.types
[op
].bitfield
.floatacc
)
5420 as_bad (_("`%s%s' not allowed with `%s%c'"),
5422 i
.op
[op
].regs
->reg_name
,
5432 check_long_reg (void)
5436 for (op
= i
.operands
; --op
>= 0;)
5437 /* Reject eight bit registers, except where the template requires
5438 them. (eg. movzb) */
5439 if (i
.types
[op
].bitfield
.reg8
5440 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5441 || i
.tm
.operand_types
[op
].bitfield
.reg32
5442 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5444 as_bad (_("`%s%s' not allowed with `%s%c'"),
5446 i
.op
[op
].regs
->reg_name
,
5451 /* Warn if the e prefix on a general reg is missing. */
5452 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5453 && i
.types
[op
].bitfield
.reg16
5454 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5455 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5457 /* Prohibit these changes in the 64bit mode, since the
5458 lowering is more complicated. */
5459 if (flag_code
== CODE_64BIT
)
5461 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5462 register_prefix
, i
.op
[op
].regs
->reg_name
,
5466 #if REGISTER_WARNINGS
5467 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5469 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5470 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5473 /* Warn if the r prefix on a general reg is present. */
5474 else if (i
.types
[op
].bitfield
.reg64
5475 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5476 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5479 && i
.tm
.opcode_modifier
.toqword
5480 && !i
.types
[0].bitfield
.regxmm
)
5482 /* Convert to QWORD. We want REX byte. */
5483 i
.suffix
= QWORD_MNEM_SUFFIX
;
5487 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5488 register_prefix
, i
.op
[op
].regs
->reg_name
,
5497 check_qword_reg (void)
5501 for (op
= i
.operands
; --op
>= 0; )
5502 /* Reject eight bit registers, except where the template requires
5503 them. (eg. movzb) */
5504 if (i
.types
[op
].bitfield
.reg8
5505 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5506 || i
.tm
.operand_types
[op
].bitfield
.reg32
5507 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5509 as_bad (_("`%s%s' not allowed with `%s%c'"),
5511 i
.op
[op
].regs
->reg_name
,
5516 /* Warn if the r prefix on a general reg is missing. */
5517 else if ((i
.types
[op
].bitfield
.reg16
5518 || i
.types
[op
].bitfield
.reg32
)
5519 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5520 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5522 /* Prohibit these changes in the 64bit mode, since the
5523 lowering is more complicated. */
5525 && i
.tm
.opcode_modifier
.todword
5526 && !i
.types
[0].bitfield
.regxmm
)
5528 /* Convert to DWORD. We don't want REX byte. */
5529 i
.suffix
= LONG_MNEM_SUFFIX
;
5533 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5534 register_prefix
, i
.op
[op
].regs
->reg_name
,
5543 check_word_reg (void)
5546 for (op
= i
.operands
; --op
>= 0;)
5547 /* Reject eight bit registers, except where the template requires
5548 them. (eg. movzb) */
5549 if (i
.types
[op
].bitfield
.reg8
5550 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5551 || i
.tm
.operand_types
[op
].bitfield
.reg32
5552 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5554 as_bad (_("`%s%s' not allowed with `%s%c'"),
5556 i
.op
[op
].regs
->reg_name
,
5561 /* Warn if the e or r prefix on a general reg is present. */
5562 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5563 && (i
.types
[op
].bitfield
.reg32
5564 || i
.types
[op
].bitfield
.reg64
)
5565 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5566 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5568 /* Prohibit these changes in the 64bit mode, since the
5569 lowering is more complicated. */
5570 if (flag_code
== CODE_64BIT
)
5572 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5573 register_prefix
, i
.op
[op
].regs
->reg_name
,
5577 #if REGISTER_WARNINGS
5578 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5580 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5581 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5588 update_imm (unsigned int j
)
5590 i386_operand_type overlap
= i
.types
[j
];
5591 if ((overlap
.bitfield
.imm8
5592 || overlap
.bitfield
.imm8s
5593 || overlap
.bitfield
.imm16
5594 || overlap
.bitfield
.imm32
5595 || overlap
.bitfield
.imm32s
5596 || overlap
.bitfield
.imm64
)
5597 && !operand_type_equal (&overlap
, &imm8
)
5598 && !operand_type_equal (&overlap
, &imm8s
)
5599 && !operand_type_equal (&overlap
, &imm16
)
5600 && !operand_type_equal (&overlap
, &imm32
)
5601 && !operand_type_equal (&overlap
, &imm32s
)
5602 && !operand_type_equal (&overlap
, &imm64
))
5606 i386_operand_type temp
;
5608 operand_type_set (&temp
, 0);
5609 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5611 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5612 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5614 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5615 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5616 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5618 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5619 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5622 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5625 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5626 || operand_type_equal (&overlap
, &imm16_32
)
5627 || operand_type_equal (&overlap
, &imm16_32s
))
5629 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5634 if (!operand_type_equal (&overlap
, &imm8
)
5635 && !operand_type_equal (&overlap
, &imm8s
)
5636 && !operand_type_equal (&overlap
, &imm16
)
5637 && !operand_type_equal (&overlap
, &imm32
)
5638 && !operand_type_equal (&overlap
, &imm32s
)
5639 && !operand_type_equal (&overlap
, &imm64
))
5641 as_bad (_("no instruction mnemonic suffix given; "
5642 "can't determine immediate size"));
5646 i
.types
[j
] = overlap
;
5656 /* Update the first 2 immediate operands. */
5657 n
= i
.operands
> 2 ? 2 : i
.operands
;
5660 for (j
= 0; j
< n
; j
++)
5661 if (update_imm (j
) == 0)
5664 /* The 3rd operand can't be immediate operand. */
5665 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5672 bad_implicit_operand (int xmm
)
5674 const char *ireg
= xmm
? "xmm0" : "ymm0";
5677 as_bad (_("the last operand of `%s' must be `%s%s'"),
5678 i
.tm
.name
, register_prefix
, ireg
);
5680 as_bad (_("the first operand of `%s' must be `%s%s'"),
5681 i
.tm
.name
, register_prefix
, ireg
);
5686 process_operands (void)
5688 /* Default segment register this instruction will use for memory
5689 accesses. 0 means unknown. This is only for optimizing out
5690 unnecessary segment overrides. */
5691 const seg_entry
*default_seg
= 0;
5693 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5695 unsigned int dupl
= i
.operands
;
5696 unsigned int dest
= dupl
- 1;
5699 /* The destination must be an xmm register. */
5700 gas_assert (i
.reg_operands
5701 && MAX_OPERANDS
> dupl
5702 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5704 if (i
.tm
.opcode_modifier
.firstxmm0
)
5706 /* The first operand is implicit and must be xmm0. */
5707 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5708 if (register_number (i
.op
[0].regs
) != 0)
5709 return bad_implicit_operand (1);
5711 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5713 /* Keep xmm0 for instructions with VEX prefix and 3
5719 /* We remove the first xmm0 and keep the number of
5720 operands unchanged, which in fact duplicates the
5722 for (j
= 1; j
< i
.operands
; j
++)
5724 i
.op
[j
- 1] = i
.op
[j
];
5725 i
.types
[j
- 1] = i
.types
[j
];
5726 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5730 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5732 gas_assert ((MAX_OPERANDS
- 1) > dupl
5733 && (i
.tm
.opcode_modifier
.vexsources
5736 /* Add the implicit xmm0 for instructions with VEX prefix
5738 for (j
= i
.operands
; j
> 0; j
--)
5740 i
.op
[j
] = i
.op
[j
- 1];
5741 i
.types
[j
] = i
.types
[j
- 1];
5742 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5745 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5746 i
.types
[0] = regxmm
;
5747 i
.tm
.operand_types
[0] = regxmm
;
5750 i
.reg_operands
+= 2;
5755 i
.op
[dupl
] = i
.op
[dest
];
5756 i
.types
[dupl
] = i
.types
[dest
];
5757 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5766 i
.op
[dupl
] = i
.op
[dest
];
5767 i
.types
[dupl
] = i
.types
[dest
];
5768 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5771 if (i
.tm
.opcode_modifier
.immext
)
5774 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5778 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5779 gas_assert (i
.reg_operands
5780 && (operand_type_equal (&i
.types
[0], ®xmm
)
5781 || operand_type_equal (&i
.types
[0], ®ymm
)
5782 || operand_type_equal (&i
.types
[0], ®zmm
)));
5783 if (register_number (i
.op
[0].regs
) != 0)
5784 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5786 for (j
= 1; j
< i
.operands
; j
++)
5788 i
.op
[j
- 1] = i
.op
[j
];
5789 i
.types
[j
- 1] = i
.types
[j
];
5791 /* We need to adjust fields in i.tm since they are used by
5792 build_modrm_byte. */
5793 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5800 else if (i
.tm
.opcode_modifier
.regkludge
)
5802 /* The imul $imm, %reg instruction is converted into
5803 imul $imm, %reg, %reg, and the clr %reg instruction
5804 is converted into xor %reg, %reg. */
5806 unsigned int first_reg_op
;
5808 if (operand_type_check (i
.types
[0], reg
))
5812 /* Pretend we saw the extra register operand. */
5813 gas_assert (i
.reg_operands
== 1
5814 && i
.op
[first_reg_op
+ 1].regs
== 0);
5815 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5816 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5821 if (i
.tm
.opcode_modifier
.shortform
)
5823 if (i
.types
[0].bitfield
.sreg2
5824 || i
.types
[0].bitfield
.sreg3
)
5826 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5827 && i
.op
[0].regs
->reg_num
== 1)
5829 as_bad (_("you can't `pop %scs'"), register_prefix
);
5832 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5833 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5838 /* The register or float register operand is in operand
5842 if (i
.types
[0].bitfield
.floatreg
5843 || operand_type_check (i
.types
[0], reg
))
5847 /* Register goes in low 3 bits of opcode. */
5848 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5849 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5851 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5853 /* Warn about some common errors, but press on regardless.
5854 The first case can be generated by gcc (<= 2.8.1). */
5855 if (i
.operands
== 2)
5857 /* Reversed arguments on faddp, fsubp, etc. */
5858 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5859 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5860 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5864 /* Extraneous `l' suffix on fp insn. */
5865 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5866 register_prefix
, i
.op
[0].regs
->reg_name
);
5871 else if (i
.tm
.opcode_modifier
.modrm
)
5873 /* The opcode is completed (modulo i.tm.extension_opcode which
5874 must be put into the modrm byte). Now, we make the modrm and
5875 index base bytes based on all the info we've collected. */
5877 default_seg
= build_modrm_byte ();
5879 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5883 else if (i
.tm
.opcode_modifier
.isstring
)
5885 /* For the string instructions that allow a segment override
5886 on one of their operands, the default segment is ds. */
5890 if (i
.tm
.base_opcode
== 0x8d /* lea */
5893 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5895 /* If a segment was explicitly specified, and the specified segment
5896 is not the default, use an opcode prefix to select it. If we
5897 never figured out what the default segment is, then default_seg
5898 will be zero at this point, and the specified segment prefix will
5900 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5902 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5908 static const seg_entry
*
5909 build_modrm_byte (void)
5911 const seg_entry
*default_seg
= 0;
5912 unsigned int source
, dest
;
5915 /* The first operand of instructions with VEX prefix and 3 sources
5916 must be VEX_Imm4. */
5917 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5920 unsigned int nds
, reg_slot
;
5923 if (i
.tm
.opcode_modifier
.veximmext
5924 && i
.tm
.opcode_modifier
.immext
)
5926 dest
= i
.operands
- 2;
5927 gas_assert (dest
== 3);
5930 dest
= i
.operands
- 1;
5933 /* There are 2 kinds of instructions:
5934 1. 5 operands: 4 register operands or 3 register operands
5935 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5936 VexW0 or VexW1. The destination must be either XMM, YMM or
5938 2. 4 operands: 4 register operands or 3 register operands
5939 plus 1 memory operand, VexXDS, and VexImmExt */
5940 gas_assert ((i
.reg_operands
== 4
5941 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5942 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5943 && (i
.tm
.opcode_modifier
.veximmext
5944 || (i
.imm_operands
== 1
5945 && i
.types
[0].bitfield
.vec_imm4
5946 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5947 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5948 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5949 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5950 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5952 if (i
.imm_operands
== 0)
5954 /* When there is no immediate operand, generate an 8bit
5955 immediate operand to encode the first operand. */
5956 exp
= &im_expressions
[i
.imm_operands
++];
5957 i
.op
[i
.operands
].imms
= exp
;
5958 i
.types
[i
.operands
] = imm8
;
5960 /* If VexW1 is set, the first operand is the source and
5961 the second operand is encoded in the immediate operand. */
5962 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5973 /* FMA swaps REG and NDS. */
5974 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5982 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5984 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5986 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5988 exp
->X_op
= O_constant
;
5989 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5990 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5994 unsigned int imm_slot
;
5996 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5998 /* If VexW0 is set, the third operand is the source and
5999 the second operand is encoded in the immediate
6006 /* VexW1 is set, the second operand is the source and
6007 the third operand is encoded in the immediate
6013 if (i
.tm
.opcode_modifier
.immext
)
6015 /* When ImmExt is set, the immdiate byte is the last
6017 imm_slot
= i
.operands
- 1;
6025 /* Turn on Imm8 so that output_imm will generate it. */
6026 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6029 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6031 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6033 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6035 i
.op
[imm_slot
].imms
->X_add_number
6036 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6037 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6040 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6041 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6043 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6045 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6050 /* i.reg_operands MUST be the number of real register operands;
6051 implicit registers do not count. If there are 3 register
6052 operands, it must be a instruction with VexNDS. For a
6053 instruction with VexNDD, the destination register is encoded
6054 in VEX prefix. If there are 4 register operands, it must be
6055 a instruction with VEX prefix and 3 sources. */
6056 if (i
.mem_operands
== 0
6057 && ((i
.reg_operands
== 2
6058 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6059 || (i
.reg_operands
== 3
6060 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6061 || (i
.reg_operands
== 4 && vex_3_sources
)))
6069 /* When there are 3 operands, one of them may be immediate,
6070 which may be the first or the last operand. Otherwise,
6071 the first operand must be shift count register (cl) or it
6072 is an instruction with VexNDS. */
6073 gas_assert (i
.imm_operands
== 1
6074 || (i
.imm_operands
== 0
6075 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6076 || i
.types
[0].bitfield
.shiftcount
)));
6077 if (operand_type_check (i
.types
[0], imm
)
6078 || i
.types
[0].bitfield
.shiftcount
)
6084 /* When there are 4 operands, the first two must be 8bit
6085 immediate operands. The source operand will be the 3rd
6088 For instructions with VexNDS, if the first operand
6089 an imm8, the source operand is the 2nd one. If the last
6090 operand is imm8, the source operand is the first one. */
6091 gas_assert ((i
.imm_operands
== 2
6092 && i
.types
[0].bitfield
.imm8
6093 && i
.types
[1].bitfield
.imm8
)
6094 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6095 && i
.imm_operands
== 1
6096 && (i
.types
[0].bitfield
.imm8
6097 || i
.types
[i
.operands
- 1].bitfield
.imm8
6099 if (i
.imm_operands
== 2)
6103 if (i
.types
[0].bitfield
.imm8
)
6110 if (i
.tm
.opcode_modifier
.evex
)
6112 /* For EVEX instructions, when there are 5 operands, the
6113 first one must be immediate operand. If the second one
6114 is immediate operand, the source operand is the 3th
6115 one. If the last one is immediate operand, the source
6116 operand is the 2nd one. */
6117 gas_assert (i
.imm_operands
== 2
6118 && i
.tm
.opcode_modifier
.sae
6119 && operand_type_check (i
.types
[0], imm
));
6120 if (operand_type_check (i
.types
[1], imm
))
6122 else if (operand_type_check (i
.types
[4], imm
))
6136 /* RC/SAE operand could be between DEST and SRC. That happens
6137 when one operand is GPR and the other one is XMM/YMM/ZMM
6139 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6142 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6144 /* For instructions with VexNDS, the register-only source
6145 operand must be 32/64bit integer, XMM, YMM or ZMM
6146 register. It is encoded in VEX prefix. We need to
6147 clear RegMem bit before calling operand_type_equal. */
6149 i386_operand_type op
;
6152 /* Check register-only source operand when two source
6153 operands are swapped. */
6154 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6155 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6163 op
= i
.tm
.operand_types
[vvvv
];
6164 op
.bitfield
.regmem
= 0;
6165 if ((dest
+ 1) >= i
.operands
6166 || (op
.bitfield
.reg32
!= 1
6167 && !op
.bitfield
.reg64
!= 1
6168 && !operand_type_equal (&op
, ®xmm
)
6169 && !operand_type_equal (&op
, ®ymm
)
6170 && !operand_type_equal (&op
, ®zmm
)
6171 && !operand_type_equal (&op
, ®mask
)))
6173 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6179 /* One of the register operands will be encoded in the i.tm.reg
6180 field, the other in the combined i.tm.mode and i.tm.regmem
6181 fields. If no form of this instruction supports a memory
6182 destination operand, then we assume the source operand may
6183 sometimes be a memory operand and so we need to store the
6184 destination in the i.rm.reg field. */
6185 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6186 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6188 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6189 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6190 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6192 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6194 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6196 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6201 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6202 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6203 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6205 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6207 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6209 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6212 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6214 if (!i
.types
[0].bitfield
.control
6215 && !i
.types
[1].bitfield
.control
)
6217 i
.rex
&= ~(REX_R
| REX_B
);
6218 add_prefix (LOCK_PREFIX_OPCODE
);
6222 { /* If it's not 2 reg operands... */
6227 unsigned int fake_zero_displacement
= 0;
6230 for (op
= 0; op
< i
.operands
; op
++)
6231 if (operand_type_check (i
.types
[op
], anymem
))
6233 gas_assert (op
< i
.operands
);
6235 if (i
.tm
.opcode_modifier
.vecsib
)
6237 if (i
.index_reg
->reg_num
== RegEiz
6238 || i
.index_reg
->reg_num
== RegRiz
)
6241 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6244 i
.sib
.base
= NO_BASE_REGISTER
;
6245 i
.sib
.scale
= i
.log2_scale_factor
;
6246 /* No Vec_Disp8 if there is no base. */
6247 i
.types
[op
].bitfield
.vec_disp8
= 0;
6248 i
.types
[op
].bitfield
.disp8
= 0;
6249 i
.types
[op
].bitfield
.disp16
= 0;
6250 i
.types
[op
].bitfield
.disp64
= 0;
6251 if (flag_code
!= CODE_64BIT
)
6253 /* Must be 32 bit */
6254 i
.types
[op
].bitfield
.disp32
= 1;
6255 i
.types
[op
].bitfield
.disp32s
= 0;
6259 i
.types
[op
].bitfield
.disp32
= 0;
6260 i
.types
[op
].bitfield
.disp32s
= 1;
6263 i
.sib
.index
= i
.index_reg
->reg_num
;
6264 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6266 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6272 if (i
.base_reg
== 0)
6275 if (!i
.disp_operands
)
6277 fake_zero_displacement
= 1;
6278 /* Instructions with VSIB byte need 32bit displacement
6279 if there is no base register. */
6280 if (i
.tm
.opcode_modifier
.vecsib
)
6281 i
.types
[op
].bitfield
.disp32
= 1;
6283 if (i
.index_reg
== 0)
6285 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6286 /* Operand is just <disp> */
6287 if (flag_code
== CODE_64BIT
)
6289 /* 64bit mode overwrites the 32bit absolute
6290 addressing by RIP relative addressing and
6291 absolute addressing is encoded by one of the
6292 redundant SIB forms. */
6293 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6294 i
.sib
.base
= NO_BASE_REGISTER
;
6295 i
.sib
.index
= NO_INDEX_REGISTER
;
6296 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6297 ? disp32s
: disp32
);
6299 else if ((flag_code
== CODE_16BIT
)
6300 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6302 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6303 i
.types
[op
] = disp16
;
6307 i
.rm
.regmem
= NO_BASE_REGISTER
;
6308 i
.types
[op
] = disp32
;
6311 else if (!i
.tm
.opcode_modifier
.vecsib
)
6313 /* !i.base_reg && i.index_reg */
6314 if (i
.index_reg
->reg_num
== RegEiz
6315 || i
.index_reg
->reg_num
== RegRiz
)
6316 i
.sib
.index
= NO_INDEX_REGISTER
;
6318 i
.sib
.index
= i
.index_reg
->reg_num
;
6319 i
.sib
.base
= NO_BASE_REGISTER
;
6320 i
.sib
.scale
= i
.log2_scale_factor
;
6321 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6322 /* No Vec_Disp8 if there is no base. */
6323 i
.types
[op
].bitfield
.vec_disp8
= 0;
6324 i
.types
[op
].bitfield
.disp8
= 0;
6325 i
.types
[op
].bitfield
.disp16
= 0;
6326 i
.types
[op
].bitfield
.disp64
= 0;
6327 if (flag_code
!= CODE_64BIT
)
6329 /* Must be 32 bit */
6330 i
.types
[op
].bitfield
.disp32
= 1;
6331 i
.types
[op
].bitfield
.disp32s
= 0;
6335 i
.types
[op
].bitfield
.disp32
= 0;
6336 i
.types
[op
].bitfield
.disp32s
= 1;
6338 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6342 /* RIP addressing for 64bit mode. */
6343 else if (i
.base_reg
->reg_num
== RegRip
||
6344 i
.base_reg
->reg_num
== RegEip
)
6346 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6347 i
.rm
.regmem
= NO_BASE_REGISTER
;
6348 i
.types
[op
].bitfield
.disp8
= 0;
6349 i
.types
[op
].bitfield
.disp16
= 0;
6350 i
.types
[op
].bitfield
.disp32
= 0;
6351 i
.types
[op
].bitfield
.disp32s
= 1;
6352 i
.types
[op
].bitfield
.disp64
= 0;
6353 i
.types
[op
].bitfield
.vec_disp8
= 0;
6354 i
.flags
[op
] |= Operand_PCrel
;
6355 if (! i
.disp_operands
)
6356 fake_zero_displacement
= 1;
6358 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6360 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6361 switch (i
.base_reg
->reg_num
)
6364 if (i
.index_reg
== 0)
6366 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6367 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6371 if (i
.index_reg
== 0)
6374 if (operand_type_check (i
.types
[op
], disp
) == 0)
6376 /* fake (%bp) into 0(%bp) */
6377 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6378 i
.types
[op
].bitfield
.vec_disp8
= 1;
6380 i
.types
[op
].bitfield
.disp8
= 1;
6381 fake_zero_displacement
= 1;
6384 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6385 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6387 default: /* (%si) -> 4 or (%di) -> 5 */
6388 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6390 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6392 else /* i.base_reg and 32/64 bit mode */
6394 if (flag_code
== CODE_64BIT
6395 && operand_type_check (i
.types
[op
], disp
))
6397 i386_operand_type temp
;
6398 operand_type_set (&temp
, 0);
6399 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6400 temp
.bitfield
.vec_disp8
6401 = i
.types
[op
].bitfield
.vec_disp8
;
6403 if (i
.prefix
[ADDR_PREFIX
] == 0)
6404 i
.types
[op
].bitfield
.disp32s
= 1;
6406 i
.types
[op
].bitfield
.disp32
= 1;
6409 if (!i
.tm
.opcode_modifier
.vecsib
)
6410 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6411 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6413 i
.sib
.base
= i
.base_reg
->reg_num
;
6414 /* x86-64 ignores REX prefix bit here to avoid decoder
6416 if (!(i
.base_reg
->reg_flags
& RegRex
)
6417 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6418 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6420 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6422 fake_zero_displacement
= 1;
6423 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6424 i
.types
[op
].bitfield
.vec_disp8
= 1;
6426 i
.types
[op
].bitfield
.disp8
= 1;
6428 i
.sib
.scale
= i
.log2_scale_factor
;
6429 if (i
.index_reg
== 0)
6431 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6432 /* <disp>(%esp) becomes two byte modrm with no index
6433 register. We've already stored the code for esp
6434 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6435 Any base register besides %esp will not use the
6436 extra modrm byte. */
6437 i
.sib
.index
= NO_INDEX_REGISTER
;
6439 else if (!i
.tm
.opcode_modifier
.vecsib
)
6441 if (i
.index_reg
->reg_num
== RegEiz
6442 || i
.index_reg
->reg_num
== RegRiz
)
6443 i
.sib
.index
= NO_INDEX_REGISTER
;
6445 i
.sib
.index
= i
.index_reg
->reg_num
;
6446 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6447 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6452 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6453 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6457 if (!fake_zero_displacement
6461 fake_zero_displacement
= 1;
6462 if (i
.disp_encoding
== disp_encoding_8bit
)
6463 i
.types
[op
].bitfield
.disp8
= 1;
6465 i
.types
[op
].bitfield
.disp32
= 1;
6467 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6471 if (fake_zero_displacement
)
6473 /* Fakes a zero displacement assuming that i.types[op]
6474 holds the correct displacement size. */
6477 gas_assert (i
.op
[op
].disps
== 0);
6478 exp
= &disp_expressions
[i
.disp_operands
++];
6479 i
.op
[op
].disps
= exp
;
6480 exp
->X_op
= O_constant
;
6481 exp
->X_add_number
= 0;
6482 exp
->X_add_symbol
= (symbolS
*) 0;
6483 exp
->X_op_symbol
= (symbolS
*) 0;
6491 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6493 if (operand_type_check (i
.types
[0], imm
))
6494 i
.vex
.register_specifier
= NULL
;
6497 /* VEX.vvvv encodes one of the sources when the first
6498 operand is not an immediate. */
6499 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6500 i
.vex
.register_specifier
= i
.op
[0].regs
;
6502 i
.vex
.register_specifier
= i
.op
[1].regs
;
6505 /* Destination is a XMM register encoded in the ModRM.reg
6507 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6508 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6511 /* ModRM.rm and VEX.B encodes the other source. */
6512 if (!i
.mem_operands
)
6516 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6517 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6519 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6521 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6525 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6527 i
.vex
.register_specifier
= i
.op
[2].regs
;
6528 if (!i
.mem_operands
)
6531 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6532 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6536 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6537 (if any) based on i.tm.extension_opcode. Again, we must be
6538 careful to make sure that segment/control/debug/test/MMX
6539 registers are coded into the i.rm.reg field. */
6540 else if (i
.reg_operands
)
6543 unsigned int vex_reg
= ~0;
6545 for (op
= 0; op
< i
.operands
; op
++)
6546 if (i
.types
[op
].bitfield
.reg8
6547 || i
.types
[op
].bitfield
.reg16
6548 || i
.types
[op
].bitfield
.reg32
6549 || i
.types
[op
].bitfield
.reg64
6550 || i
.types
[op
].bitfield
.regmmx
6551 || i
.types
[op
].bitfield
.regxmm
6552 || i
.types
[op
].bitfield
.regymm
6553 || i
.types
[op
].bitfield
.regbnd
6554 || i
.types
[op
].bitfield
.regzmm
6555 || i
.types
[op
].bitfield
.regmask
6556 || i
.types
[op
].bitfield
.sreg2
6557 || i
.types
[op
].bitfield
.sreg3
6558 || i
.types
[op
].bitfield
.control
6559 || i
.types
[op
].bitfield
.debug
6560 || i
.types
[op
].bitfield
.test
)
6565 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6567 /* For instructions with VexNDS, the register-only
6568 source operand is encoded in VEX prefix. */
6569 gas_assert (mem
!= (unsigned int) ~0);
6574 gas_assert (op
< i
.operands
);
6578 /* Check register-only source operand when two source
6579 operands are swapped. */
6580 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6581 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6585 gas_assert (mem
== (vex_reg
+ 1)
6586 && op
< i
.operands
);
6591 gas_assert (vex_reg
< i
.operands
);
6595 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6597 /* For instructions with VexNDD, the register destination
6598 is encoded in VEX prefix. */
6599 if (i
.mem_operands
== 0)
6601 /* There is no memory operand. */
6602 gas_assert ((op
+ 2) == i
.operands
);
6607 /* There are only 2 operands. */
6608 gas_assert (op
< 2 && i
.operands
== 2);
6613 gas_assert (op
< i
.operands
);
6615 if (vex_reg
!= (unsigned int) ~0)
6617 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6619 if (type
->bitfield
.reg32
!= 1
6620 && type
->bitfield
.reg64
!= 1
6621 && !operand_type_equal (type
, ®xmm
)
6622 && !operand_type_equal (type
, ®ymm
)
6623 && !operand_type_equal (type
, ®zmm
)
6624 && !operand_type_equal (type
, ®mask
))
6627 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6630 /* Don't set OP operand twice. */
6633 /* If there is an extension opcode to put here, the
6634 register number must be put into the regmem field. */
6635 if (i
.tm
.extension_opcode
!= None
)
6637 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6638 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6640 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6645 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6646 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6648 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6653 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6654 must set it to 3 to indicate this is a register operand
6655 in the regmem field. */
6656 if (!i
.mem_operands
)
6660 /* Fill in i.rm.reg field with extension opcode (if any). */
6661 if (i
.tm
.extension_opcode
!= None
)
6662 i
.rm
.reg
= i
.tm
.extension_opcode
;
6668 output_branch (void)
6674 relax_substateT subtype
;
6678 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6679 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6682 if (i
.prefix
[DATA_PREFIX
] != 0)
6688 /* Pentium4 branch hints. */
6689 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6690 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6695 if (i
.prefix
[REX_PREFIX
] != 0)
6701 /* BND prefixed jump. */
6702 if (i
.prefix
[BND_PREFIX
] != 0)
6704 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6708 if (i
.prefixes
!= 0 && !intel_syntax
)
6709 as_warn (_("skipping prefixes on this instruction"));
6711 /* It's always a symbol; End frag & setup for relax.
6712 Make sure there is enough room in this frag for the largest
6713 instruction we may generate in md_convert_frag. This is 2
6714 bytes for the opcode and room for the prefix and largest
6716 frag_grow (prefix
+ 2 + 4);
6717 /* Prefix and 1 opcode byte go in fr_fix. */
6718 p
= frag_more (prefix
+ 1);
6719 if (i
.prefix
[DATA_PREFIX
] != 0)
6720 *p
++ = DATA_PREFIX_OPCODE
;
6721 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6722 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6723 *p
++ = i
.prefix
[SEG_PREFIX
];
6724 if (i
.prefix
[REX_PREFIX
] != 0)
6725 *p
++ = i
.prefix
[REX_PREFIX
];
6726 *p
= i
.tm
.base_opcode
;
6728 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6729 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6730 else if (cpu_arch_flags
.bitfield
.cpui386
)
6731 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6733 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6736 sym
= i
.op
[0].disps
->X_add_symbol
;
6737 off
= i
.op
[0].disps
->X_add_number
;
6739 if (i
.op
[0].disps
->X_op
!= O_constant
6740 && i
.op
[0].disps
->X_op
!= O_symbol
)
6742 /* Handle complex expressions. */
6743 sym
= make_expr_symbol (i
.op
[0].disps
);
6747 /* 1 possible extra opcode + 4 byte displacement go in var part.
6748 Pass reloc in fr_var. */
6749 frag_var (rs_machine_dependent
, 5,
6751 || i
.reloc
[0] != NO_RELOC
6752 || (i
.bnd_prefix
== NULL
&& !add_bnd_prefix
))
6754 : BFD_RELOC_X86_64_PC32_BND
),
6755 subtype
, sym
, off
, p
);
6765 if (i
.tm
.opcode_modifier
.jumpbyte
)
6767 /* This is a loop or jecxz type instruction. */
6769 if (i
.prefix
[ADDR_PREFIX
] != 0)
6771 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6774 /* Pentium4 branch hints. */
6775 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6776 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6778 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6787 if (flag_code
== CODE_16BIT
)
6790 if (i
.prefix
[DATA_PREFIX
] != 0)
6792 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6802 if (i
.prefix
[REX_PREFIX
] != 0)
6804 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6808 /* BND prefixed jump. */
6809 if (i
.prefix
[BND_PREFIX
] != 0)
6811 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6815 if (i
.prefixes
!= 0 && !intel_syntax
)
6816 as_warn (_("skipping prefixes on this instruction"));
6818 p
= frag_more (i
.tm
.opcode_length
+ size
);
6819 switch (i
.tm
.opcode_length
)
6822 *p
++ = i
.tm
.base_opcode
>> 8;
6824 *p
++ = i
.tm
.base_opcode
;
6830 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6831 i
.op
[0].disps
, 1, reloc (size
, 1, 1,
6832 (i
.bnd_prefix
!= NULL
6836 /* All jumps handled here are signed, but don't use a signed limit
6837 check for 32 and 16 bit jumps as we want to allow wrap around at
6838 4G and 64k respectively. */
6840 fixP
->fx_signed
= 1;
6844 output_interseg_jump (void)
6852 if (flag_code
== CODE_16BIT
)
6856 if (i
.prefix
[DATA_PREFIX
] != 0)
6862 if (i
.prefix
[REX_PREFIX
] != 0)
6872 if (i
.prefixes
!= 0 && !intel_syntax
)
6873 as_warn (_("skipping prefixes on this instruction"));
6875 /* 1 opcode; 2 segment; offset */
6876 p
= frag_more (prefix
+ 1 + 2 + size
);
6878 if (i
.prefix
[DATA_PREFIX
] != 0)
6879 *p
++ = DATA_PREFIX_OPCODE
;
6881 if (i
.prefix
[REX_PREFIX
] != 0)
6882 *p
++ = i
.prefix
[REX_PREFIX
];
6884 *p
++ = i
.tm
.base_opcode
;
6885 if (i
.op
[1].imms
->X_op
== O_constant
)
6887 offsetT n
= i
.op
[1].imms
->X_add_number
;
6890 && !fits_in_unsigned_word (n
)
6891 && !fits_in_signed_word (n
))
6893 as_bad (_("16-bit jump out of range"));
6896 md_number_to_chars (p
, n
, size
);
6899 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6900 i
.op
[1].imms
, 0, reloc (size
, 0, 0, 0, i
.reloc
[1]));
6901 if (i
.op
[0].imms
->X_op
!= O_constant
)
6902 as_bad (_("can't handle non absolute segment in `%s'"),
6904 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6910 fragS
*insn_start_frag
;
6911 offsetT insn_start_off
;
6913 /* Tie dwarf2 debug info to the address at the start of the insn.
6914 We can't do this after the insn has been output as the current
6915 frag may have been closed off. eg. by frag_var. */
6916 dwarf2_emit_insn (0);
6918 insn_start_frag
= frag_now
;
6919 insn_start_off
= frag_now_fix ();
6922 if (i
.tm
.opcode_modifier
.jump
)
6924 else if (i
.tm
.opcode_modifier
.jumpbyte
6925 || i
.tm
.opcode_modifier
.jumpdword
)
6927 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6928 output_interseg_jump ();
6931 /* Output normal instructions here. */
6935 unsigned int prefix
;
6937 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6938 don't need the explicit prefix. */
6939 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6941 switch (i
.tm
.opcode_length
)
6944 if (i
.tm
.base_opcode
& 0xff000000)
6946 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6951 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6953 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6954 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6957 if (prefix
!= REPE_PREFIX_OPCODE
6958 || (i
.prefix
[REP_PREFIX
]
6959 != REPE_PREFIX_OPCODE
))
6960 add_prefix (prefix
);
6963 add_prefix (prefix
);
6972 /* The prefix bytes. */
6973 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6975 FRAG_APPEND_1_CHAR (*q
);
6979 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6984 /* REX byte is encoded in VEX prefix. */
6988 FRAG_APPEND_1_CHAR (*q
);
6991 /* There should be no other prefixes for instructions
6996 /* For EVEX instructions i.vrex should become 0 after
6997 build_evex_prefix. For VEX instructions upper 16 registers
6998 aren't available, so VREX should be 0. */
7001 /* Now the VEX prefix. */
7002 p
= frag_more (i
.vex
.length
);
7003 for (j
= 0; j
< i
.vex
.length
; j
++)
7004 p
[j
] = i
.vex
.bytes
[j
];
7007 /* Now the opcode; be careful about word order here! */
7008 if (i
.tm
.opcode_length
== 1)
7010 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7014 switch (i
.tm
.opcode_length
)
7018 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7019 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7023 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7033 /* Put out high byte first: can't use md_number_to_chars! */
7034 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7035 *p
= i
.tm
.base_opcode
& 0xff;
7038 /* Now the modrm byte and sib byte (if present). */
7039 if (i
.tm
.opcode_modifier
.modrm
)
7041 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7044 /* If i.rm.regmem == ESP (4)
7045 && i.rm.mode != (Register mode)
7047 ==> need second modrm byte. */
7048 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7050 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7051 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7053 | i
.sib
.scale
<< 6));
7056 if (i
.disp_operands
)
7057 output_disp (insn_start_frag
, insn_start_off
);
7060 output_imm (insn_start_frag
, insn_start_off
);
7066 pi ("" /*line*/, &i
);
7068 #endif /* DEBUG386 */
7071 /* Return the size of the displacement operand N. */
7074 disp_size (unsigned int n
)
7078 /* Vec_Disp8 has to be 8bit. */
7079 if (i
.types
[n
].bitfield
.vec_disp8
)
7081 else if (i
.types
[n
].bitfield
.disp64
)
7083 else if (i
.types
[n
].bitfield
.disp8
)
7085 else if (i
.types
[n
].bitfield
.disp16
)
7090 /* Return the size of the immediate operand N. */
7093 imm_size (unsigned int n
)
7096 if (i
.types
[n
].bitfield
.imm64
)
7098 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7100 else if (i
.types
[n
].bitfield
.imm16
)
7106 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7111 for (n
= 0; n
< i
.operands
; n
++)
7113 if (i
.types
[n
].bitfield
.vec_disp8
7114 || operand_type_check (i
.types
[n
], disp
))
7116 if (i
.op
[n
].disps
->X_op
== O_constant
)
7118 int size
= disp_size (n
);
7119 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7121 if (i
.types
[n
].bitfield
.vec_disp8
)
7123 val
= offset_in_range (val
, size
);
7124 p
= frag_more (size
);
7125 md_number_to_chars (p
, val
, size
);
7129 enum bfd_reloc_code_real reloc_type
;
7130 int size
= disp_size (n
);
7131 int sign
= i
.types
[n
].bitfield
.disp32s
;
7132 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7134 /* We can't have 8 bit displacement here. */
7135 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7137 /* The PC relative address is computed relative
7138 to the instruction boundary, so in case immediate
7139 fields follows, we need to adjust the value. */
7140 if (pcrel
&& i
.imm_operands
)
7145 for (n1
= 0; n1
< i
.operands
; n1
++)
7146 if (operand_type_check (i
.types
[n1
], imm
))
7148 /* Only one immediate is allowed for PC
7149 relative address. */
7150 gas_assert (sz
== 0);
7152 i
.op
[n
].disps
->X_add_number
-= sz
;
7154 /* We should find the immediate. */
7155 gas_assert (sz
!= 0);
7158 p
= frag_more (size
);
7159 reloc_type
= reloc (size
, pcrel
, sign
,
7160 (i
.bnd_prefix
!= NULL
7164 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7165 && (((reloc_type
== BFD_RELOC_32
7166 || reloc_type
== BFD_RELOC_X86_64_32S
7167 || (reloc_type
== BFD_RELOC_64
7169 && (i
.op
[n
].disps
->X_op
== O_symbol
7170 || (i
.op
[n
].disps
->X_op
== O_add
7171 && ((symbol_get_value_expression
7172 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7174 || reloc_type
== BFD_RELOC_32_PCREL
))
7178 if (insn_start_frag
== frag_now
)
7179 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7184 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7185 for (fr
= insn_start_frag
->fr_next
;
7186 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7188 add
+= p
- frag_now
->fr_literal
;
7193 reloc_type
= BFD_RELOC_386_GOTPC
;
7194 i
.op
[n
].imms
->X_add_number
+= add
;
7196 else if (reloc_type
== BFD_RELOC_64
)
7197 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7199 /* Don't do the adjustment for x86-64, as there
7200 the pcrel addressing is relative to the _next_
7201 insn, and that is taken care of in other code. */
7202 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7204 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7205 i
.op
[n
].disps
, pcrel
, reloc_type
);
7212 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7217 for (n
= 0; n
< i
.operands
; n
++)
7219 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7220 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7223 if (operand_type_check (i
.types
[n
], imm
))
7225 if (i
.op
[n
].imms
->X_op
== O_constant
)
7227 int size
= imm_size (n
);
7230 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7232 p
= frag_more (size
);
7233 md_number_to_chars (p
, val
, size
);
7237 /* Not absolute_section.
7238 Need a 32-bit fixup (don't support 8bit
7239 non-absolute imms). Try to support other
7241 enum bfd_reloc_code_real reloc_type
;
7242 int size
= imm_size (n
);
7245 if (i
.types
[n
].bitfield
.imm32s
7246 && (i
.suffix
== QWORD_MNEM_SUFFIX
7247 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7252 p
= frag_more (size
);
7253 reloc_type
= reloc (size
, 0, sign
, 0, i
.reloc
[n
]);
7255 /* This is tough to explain. We end up with this one if we
7256 * have operands that look like
7257 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7258 * obtain the absolute address of the GOT, and it is strongly
7259 * preferable from a performance point of view to avoid using
7260 * a runtime relocation for this. The actual sequence of
7261 * instructions often look something like:
7266 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7268 * The call and pop essentially return the absolute address
7269 * of the label .L66 and store it in %ebx. The linker itself
7270 * will ultimately change the first operand of the addl so
7271 * that %ebx points to the GOT, but to keep things simple, the
7272 * .o file must have this operand set so that it generates not
7273 * the absolute address of .L66, but the absolute address of
7274 * itself. This allows the linker itself simply treat a GOTPC
7275 * relocation as asking for a pcrel offset to the GOT to be
7276 * added in, and the addend of the relocation is stored in the
7277 * operand field for the instruction itself.
7279 * Our job here is to fix the operand so that it would add
7280 * the correct offset so that %ebx would point to itself. The
7281 * thing that is tricky is that .-.L66 will point to the
7282 * beginning of the instruction, so we need to further modify
7283 * the operand so that it will point to itself. There are
7284 * other cases where you have something like:
7286 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7288 * and here no correction would be required. Internally in
7289 * the assembler we treat operands of this form as not being
7290 * pcrel since the '.' is explicitly mentioned, and I wonder
7291 * whether it would simplify matters to do it this way. Who
7292 * knows. In earlier versions of the PIC patches, the
7293 * pcrel_adjust field was used to store the correction, but
7294 * since the expression is not pcrel, I felt it would be
7295 * confusing to do it this way. */
7297 if ((reloc_type
== BFD_RELOC_32
7298 || reloc_type
== BFD_RELOC_X86_64_32S
7299 || reloc_type
== BFD_RELOC_64
)
7301 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7302 && (i
.op
[n
].imms
->X_op
== O_symbol
7303 || (i
.op
[n
].imms
->X_op
== O_add
7304 && ((symbol_get_value_expression
7305 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7310 if (insn_start_frag
== frag_now
)
7311 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7316 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7317 for (fr
= insn_start_frag
->fr_next
;
7318 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7320 add
+= p
- frag_now
->fr_literal
;
7324 reloc_type
= BFD_RELOC_386_GOTPC
;
7326 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7328 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7329 i
.op
[n
].imms
->X_add_number
+= add
;
7331 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7332 i
.op
[n
].imms
, 0, reloc_type
);
7338 /* x86_cons_fix_new is called via the expression parsing code when a
7339 reloc is needed. We use this hook to get the correct .got reloc. */
7340 static int cons_sign
= -1;
7343 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7344 expressionS
*exp
, bfd_reloc_code_real_type r
)
7346 r
= reloc (len
, 0, cons_sign
, 0, r
);
7349 if (exp
->X_op
== O_secrel
)
7351 exp
->X_op
= O_symbol
;
7352 r
= BFD_RELOC_32_SECREL
;
7356 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7359 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7360 purpose of the `.dc.a' internal pseudo-op. */
7363 x86_address_bytes (void)
7365 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7367 return stdoutput
->arch_info
->bits_per_address
/ 8;
7370 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7372 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7374 /* Parse operands of the form
7375 <symbol>@GOTOFF+<nnn>
7376 and similar .plt or .got references.
7378 If we find one, set up the correct relocation in RELOC and copy the
7379 input string, minus the `@GOTOFF' into a malloc'd buffer for
7380 parsing by the calling routine. Return this buffer, and if ADJUST
7381 is non-null set it to the length of the string we removed from the
7382 input line. Otherwise return NULL. */
7384 lex_got (enum bfd_reloc_code_real
*rel
,
7386 i386_operand_type
*types
,
7389 /* Some of the relocations depend on the size of what field is to
7390 be relocated. But in our callers i386_immediate and i386_displacement
7391 we don't yet know the operand size (this will be set by insn
7392 matching). Hence we record the word32 relocation here,
7393 and adjust the reloc according to the real size in reloc(). */
7394 static const struct {
7397 const enum bfd_reloc_code_real rel
[2];
7398 const i386_operand_type types64
;
7400 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7401 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7403 OPERAND_TYPE_IMM32_64
},
7405 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7406 BFD_RELOC_X86_64_PLTOFF64
},
7407 OPERAND_TYPE_IMM64
},
7408 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7409 BFD_RELOC_X86_64_PLT32
},
7410 OPERAND_TYPE_IMM32_32S_DISP32
},
7411 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7412 BFD_RELOC_X86_64_GOTPLT64
},
7413 OPERAND_TYPE_IMM64_DISP64
},
7414 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7415 BFD_RELOC_X86_64_GOTOFF64
},
7416 OPERAND_TYPE_IMM64_DISP64
},
7417 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7418 BFD_RELOC_X86_64_GOTPCREL
},
7419 OPERAND_TYPE_IMM32_32S_DISP32
},
7420 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7421 BFD_RELOC_X86_64_TLSGD
},
7422 OPERAND_TYPE_IMM32_32S_DISP32
},
7423 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7424 _dummy_first_bfd_reloc_code_real
},
7425 OPERAND_TYPE_NONE
},
7426 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7427 BFD_RELOC_X86_64_TLSLD
},
7428 OPERAND_TYPE_IMM32_32S_DISP32
},
7429 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7430 BFD_RELOC_X86_64_GOTTPOFF
},
7431 OPERAND_TYPE_IMM32_32S_DISP32
},
7432 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7433 BFD_RELOC_X86_64_TPOFF32
},
7434 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7435 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7436 _dummy_first_bfd_reloc_code_real
},
7437 OPERAND_TYPE_NONE
},
7438 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7439 BFD_RELOC_X86_64_DTPOFF32
},
7440 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7441 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7442 _dummy_first_bfd_reloc_code_real
},
7443 OPERAND_TYPE_NONE
},
7444 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7445 _dummy_first_bfd_reloc_code_real
},
7446 OPERAND_TYPE_NONE
},
7447 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7448 BFD_RELOC_X86_64_GOT32
},
7449 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7450 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7451 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7452 OPERAND_TYPE_IMM32_32S_DISP32
},
7453 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7454 BFD_RELOC_X86_64_TLSDESC_CALL
},
7455 OPERAND_TYPE_IMM32_32S_DISP32
},
7460 #if defined (OBJ_MAYBE_ELF)
7465 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7466 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7469 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7471 int len
= gotrel
[j
].len
;
7472 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7474 if (gotrel
[j
].rel
[object_64bit
] != 0)
7477 char *tmpbuf
, *past_reloc
;
7479 *rel
= gotrel
[j
].rel
[object_64bit
];
7483 if (flag_code
!= CODE_64BIT
)
7485 types
->bitfield
.imm32
= 1;
7486 types
->bitfield
.disp32
= 1;
7489 *types
= gotrel
[j
].types64
;
7492 if (j
!= 0 && GOT_symbol
== NULL
)
7493 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7495 /* The length of the first part of our input line. */
7496 first
= cp
- input_line_pointer
;
7498 /* The second part goes from after the reloc token until
7499 (and including) an end_of_line char or comma. */
7500 past_reloc
= cp
+ 1 + len
;
7502 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7504 second
= cp
+ 1 - past_reloc
;
7506 /* Allocate and copy string. The trailing NUL shouldn't
7507 be necessary, but be safe. */
7508 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7509 memcpy (tmpbuf
, input_line_pointer
, first
);
7510 if (second
!= 0 && *past_reloc
!= ' ')
7511 /* Replace the relocation token with ' ', so that
7512 errors like foo@GOTOFF1 will be detected. */
7513 tmpbuf
[first
++] = ' ';
7515 /* Increment length by 1 if the relocation token is
7520 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7521 tmpbuf
[first
+ second
] = '\0';
7522 if (bnd_prefix
&& *rel
== BFD_RELOC_X86_64_PLT32
)
7523 *rel
= BFD_RELOC_X86_64_PLT32_BND
;
7527 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7528 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7533 /* Might be a symbol version string. Don't as_bad here. */
7542 /* Parse operands of the form
7543 <symbol>@SECREL32+<nnn>
7545 If we find one, set up the correct relocation in RELOC and copy the
7546 input string, minus the `@SECREL32' into a malloc'd buffer for
7547 parsing by the calling routine. Return this buffer, and if ADJUST
7548 is non-null set it to the length of the string we removed from the
7549 input line. Otherwise return NULL.
7551 This function is copied from the ELF version above adjusted for PE targets. */
7554 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7555 int *adjust ATTRIBUTE_UNUSED
,
7556 i386_operand_type
*types
,
7557 int bnd_prefix ATTRIBUTE_UNUSED
)
7563 const enum bfd_reloc_code_real rel
[2];
7564 const i386_operand_type types64
;
7568 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7569 BFD_RELOC_32_SECREL
},
7570 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7576 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7577 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7580 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7582 int len
= gotrel
[j
].len
;
7584 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7586 if (gotrel
[j
].rel
[object_64bit
] != 0)
7589 char *tmpbuf
, *past_reloc
;
7591 *rel
= gotrel
[j
].rel
[object_64bit
];
7597 if (flag_code
!= CODE_64BIT
)
7599 types
->bitfield
.imm32
= 1;
7600 types
->bitfield
.disp32
= 1;
7603 *types
= gotrel
[j
].types64
;
7606 /* The length of the first part of our input line. */
7607 first
= cp
- input_line_pointer
;
7609 /* The second part goes from after the reloc token until
7610 (and including) an end_of_line char or comma. */
7611 past_reloc
= cp
+ 1 + len
;
7613 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7615 second
= cp
+ 1 - past_reloc
;
7617 /* Allocate and copy string. The trailing NUL shouldn't
7618 be necessary, but be safe. */
7619 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7620 memcpy (tmpbuf
, input_line_pointer
, first
);
7621 if (second
!= 0 && *past_reloc
!= ' ')
7622 /* Replace the relocation token with ' ', so that
7623 errors like foo@SECLREL321 will be detected. */
7624 tmpbuf
[first
++] = ' ';
7625 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7626 tmpbuf
[first
+ second
] = '\0';
7630 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7631 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7636 /* Might be a symbol version string. Don't as_bad here. */
7642 bfd_reloc_code_real_type
7643 x86_cons (expressionS
*exp
, int size
)
7645 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7647 intel_syntax
= -intel_syntax
;
7650 if (size
== 4 || (object_64bit
&& size
== 8))
7652 /* Handle @GOTOFF and the like in an expression. */
7654 char *gotfree_input_line
;
7657 save
= input_line_pointer
;
7658 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
, 0);
7659 if (gotfree_input_line
)
7660 input_line_pointer
= gotfree_input_line
;
7664 if (gotfree_input_line
)
7666 /* expression () has merrily parsed up to the end of line,
7667 or a comma - in the wrong buffer. Transfer how far
7668 input_line_pointer has moved to the right buffer. */
7669 input_line_pointer
= (save
7670 + (input_line_pointer
- gotfree_input_line
)
7672 free (gotfree_input_line
);
7673 if (exp
->X_op
== O_constant
7674 || exp
->X_op
== O_absent
7675 || exp
->X_op
== O_illegal
7676 || exp
->X_op
== O_register
7677 || exp
->X_op
== O_big
)
7679 char c
= *input_line_pointer
;
7680 *input_line_pointer
= 0;
7681 as_bad (_("missing or invalid expression `%s'"), save
);
7682 *input_line_pointer
= c
;
7689 intel_syntax
= -intel_syntax
;
7692 i386_intel_simplify (exp
);
7698 signed_cons (int size
)
7700 if (flag_code
== CODE_64BIT
)
7708 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7715 if (exp
.X_op
== O_symbol
)
7716 exp
.X_op
= O_secrel
;
7718 emit_expr (&exp
, 4);
7720 while (*input_line_pointer
++ == ',');
7722 input_line_pointer
--;
7723 demand_empty_rest_of_line ();
7727 /* Handle Vector operations. */
7730 check_VecOperations (char *op_string
, char *op_end
)
7732 const reg_entry
*mask
;
7737 && (op_end
== NULL
|| op_string
< op_end
))
7740 if (*op_string
== '{')
7744 /* Check broadcasts. */
7745 if (strncmp (op_string
, "1to", 3) == 0)
7750 goto duplicated_vec_op
;
7753 if (*op_string
== '8')
7754 bcst_type
= BROADCAST_1TO8
;
7755 else if (*op_string
== '1'
7756 && *(op_string
+1) == '6')
7758 bcst_type
= BROADCAST_1TO16
;
7763 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7768 broadcast_op
.type
= bcst_type
;
7769 broadcast_op
.operand
= this_operand
;
7770 i
.broadcast
= &broadcast_op
;
7772 /* Check masking operation. */
7773 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7775 /* k0 can't be used for write mask. */
7776 if (mask
->reg_num
== 0)
7778 as_bad (_("`%s' can't be used for write mask"),
7785 mask_op
.mask
= mask
;
7786 mask_op
.zeroing
= 0;
7787 mask_op
.operand
= this_operand
;
7793 goto duplicated_vec_op
;
7795 i
.mask
->mask
= mask
;
7797 /* Only "{z}" is allowed here. No need to check
7798 zeroing mask explicitly. */
7799 if (i
.mask
->operand
!= this_operand
)
7801 as_bad (_("invalid write mask `%s'"), saved
);
7808 /* Check zeroing-flag for masking operation. */
7809 else if (*op_string
== 'z')
7813 mask_op
.mask
= NULL
;
7814 mask_op
.zeroing
= 1;
7815 mask_op
.operand
= this_operand
;
7820 if (i
.mask
->zeroing
)
7823 as_bad (_("duplicated `%s'"), saved
);
7827 i
.mask
->zeroing
= 1;
7829 /* Only "{%k}" is allowed here. No need to check mask
7830 register explicitly. */
7831 if (i
.mask
->operand
!= this_operand
)
7833 as_bad (_("invalid zeroing-masking `%s'"),
7842 goto unknown_vec_op
;
7844 if (*op_string
!= '}')
7846 as_bad (_("missing `}' in `%s'"), saved
);
7853 /* We don't know this one. */
7854 as_bad (_("unknown vector operation: `%s'"), saved
);
7862 i386_immediate (char *imm_start
)
7864 char *save_input_line_pointer
;
7865 char *gotfree_input_line
;
7868 i386_operand_type types
;
7870 operand_type_set (&types
, ~0);
7872 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7874 as_bad (_("at most %d immediate operands are allowed"),
7875 MAX_IMMEDIATE_OPERANDS
);
7879 exp
= &im_expressions
[i
.imm_operands
++];
7880 i
.op
[this_operand
].imms
= exp
;
7882 if (is_space_char (*imm_start
))
7885 save_input_line_pointer
= input_line_pointer
;
7886 input_line_pointer
= imm_start
;
7888 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
7889 (i
.bnd_prefix
!= NULL
7890 || add_bnd_prefix
));
7891 if (gotfree_input_line
)
7892 input_line_pointer
= gotfree_input_line
;
7894 exp_seg
= expression (exp
);
7898 /* Handle vector operations. */
7899 if (*input_line_pointer
== '{')
7901 input_line_pointer
= check_VecOperations (input_line_pointer
,
7903 if (input_line_pointer
== NULL
)
7907 if (*input_line_pointer
)
7908 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7910 input_line_pointer
= save_input_line_pointer
;
7911 if (gotfree_input_line
)
7913 free (gotfree_input_line
);
7915 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7916 exp
->X_op
= O_illegal
;
7919 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7923 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7924 i386_operand_type types
, const char *imm_start
)
7926 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7929 as_bad (_("missing or invalid immediate expression `%s'"),
7933 else if (exp
->X_op
== O_constant
)
7935 /* Size it properly later. */
7936 i
.types
[this_operand
].bitfield
.imm64
= 1;
7937 /* If not 64bit, sign extend val. */
7938 if (flag_code
!= CODE_64BIT
7939 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7941 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7943 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7944 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7945 && exp_seg
!= absolute_section
7946 && exp_seg
!= text_section
7947 && exp_seg
!= data_section
7948 && exp_seg
!= bss_section
7949 && exp_seg
!= undefined_section
7950 && !bfd_is_com_section (exp_seg
))
7952 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7956 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7959 as_bad (_("illegal immediate register operand %s"), imm_start
);
7964 /* This is an address. The size of the address will be
7965 determined later, depending on destination register,
7966 suffix, or the default for the section. */
7967 i
.types
[this_operand
].bitfield
.imm8
= 1;
7968 i
.types
[this_operand
].bitfield
.imm16
= 1;
7969 i
.types
[this_operand
].bitfield
.imm32
= 1;
7970 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7971 i
.types
[this_operand
].bitfield
.imm64
= 1;
7972 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7980 i386_scale (char *scale
)
7983 char *save
= input_line_pointer
;
7985 input_line_pointer
= scale
;
7986 val
= get_absolute_expression ();
7991 i
.log2_scale_factor
= 0;
7994 i
.log2_scale_factor
= 1;
7997 i
.log2_scale_factor
= 2;
8000 i
.log2_scale_factor
= 3;
8004 char sep
= *input_line_pointer
;
8006 *input_line_pointer
= '\0';
8007 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8009 *input_line_pointer
= sep
;
8010 input_line_pointer
= save
;
8014 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8016 as_warn (_("scale factor of %d without an index register"),
8017 1 << i
.log2_scale_factor
);
8018 i
.log2_scale_factor
= 0;
8020 scale
= input_line_pointer
;
8021 input_line_pointer
= save
;
8026 i386_displacement (char *disp_start
, char *disp_end
)
8030 char *save_input_line_pointer
;
8031 char *gotfree_input_line
;
8033 i386_operand_type bigdisp
, types
= anydisp
;
8036 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8038 as_bad (_("at most %d displacement operands are allowed"),
8039 MAX_MEMORY_OPERANDS
);
8043 operand_type_set (&bigdisp
, 0);
8044 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8045 || (!current_templates
->start
->opcode_modifier
.jump
8046 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8048 bigdisp
.bitfield
.disp32
= 1;
8049 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8050 if (flag_code
== CODE_64BIT
)
8054 bigdisp
.bitfield
.disp32s
= 1;
8055 bigdisp
.bitfield
.disp64
= 1;
8058 else if ((flag_code
== CODE_16BIT
) ^ override
)
8060 bigdisp
.bitfield
.disp32
= 0;
8061 bigdisp
.bitfield
.disp16
= 1;
8066 /* For PC-relative branches, the width of the displacement
8067 is dependent upon data size, not address size. */
8068 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8069 if (flag_code
== CODE_64BIT
)
8071 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8072 bigdisp
.bitfield
.disp16
= 1;
8075 bigdisp
.bitfield
.disp32
= 1;
8076 bigdisp
.bitfield
.disp32s
= 1;
8082 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8084 : LONG_MNEM_SUFFIX
));
8085 bigdisp
.bitfield
.disp32
= 1;
8086 if ((flag_code
== CODE_16BIT
) ^ override
)
8088 bigdisp
.bitfield
.disp32
= 0;
8089 bigdisp
.bitfield
.disp16
= 1;
8093 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8096 exp
= &disp_expressions
[i
.disp_operands
];
8097 i
.op
[this_operand
].disps
= exp
;
8099 save_input_line_pointer
= input_line_pointer
;
8100 input_line_pointer
= disp_start
;
8101 END_STRING_AND_SAVE (disp_end
);
8103 #ifndef GCC_ASM_O_HACK
8104 #define GCC_ASM_O_HACK 0
8107 END_STRING_AND_SAVE (disp_end
+ 1);
8108 if (i
.types
[this_operand
].bitfield
.baseIndex
8109 && displacement_string_end
[-1] == '+')
8111 /* This hack is to avoid a warning when using the "o"
8112 constraint within gcc asm statements.
8115 #define _set_tssldt_desc(n,addr,limit,type) \
8116 __asm__ __volatile__ ( \
8118 "movw %w1,2+%0\n\t" \
8120 "movb %b1,4+%0\n\t" \
8121 "movb %4,5+%0\n\t" \
8122 "movb $0,6+%0\n\t" \
8123 "movb %h1,7+%0\n\t" \
8125 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8127 This works great except that the output assembler ends
8128 up looking a bit weird if it turns out that there is
8129 no offset. You end up producing code that looks like:
8142 So here we provide the missing zero. */
8144 *displacement_string_end
= '0';
8147 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
8148 (i
.bnd_prefix
!= NULL
8149 || add_bnd_prefix
));
8150 if (gotfree_input_line
)
8151 input_line_pointer
= gotfree_input_line
;
8153 exp_seg
= expression (exp
);
8156 if (*input_line_pointer
)
8157 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8159 RESTORE_END_STRING (disp_end
+ 1);
8161 input_line_pointer
= save_input_line_pointer
;
8162 if (gotfree_input_line
)
8164 free (gotfree_input_line
);
8166 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8167 exp
->X_op
= O_illegal
;
8170 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8172 RESTORE_END_STRING (disp_end
);
8178 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8179 i386_operand_type types
, const char *disp_start
)
8181 i386_operand_type bigdisp
;
8184 /* We do this to make sure that the section symbol is in
8185 the symbol table. We will ultimately change the relocation
8186 to be relative to the beginning of the section. */
8187 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8188 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8189 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8191 if (exp
->X_op
!= O_symbol
)
8194 if (S_IS_LOCAL (exp
->X_add_symbol
)
8195 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8196 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8197 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8198 exp
->X_op
= O_subtract
;
8199 exp
->X_op_symbol
= GOT_symbol
;
8200 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8201 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8202 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8203 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8205 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8208 else if (exp
->X_op
== O_absent
8209 || exp
->X_op
== O_illegal
8210 || exp
->X_op
== O_big
)
8213 as_bad (_("missing or invalid displacement expression `%s'"),
8218 else if (flag_code
== CODE_64BIT
8219 && !i
.prefix
[ADDR_PREFIX
]
8220 && exp
->X_op
== O_constant
)
8222 /* Since displacement is signed extended to 64bit, don't allow
8223 disp32 and turn off disp32s if they are out of range. */
8224 i
.types
[this_operand
].bitfield
.disp32
= 0;
8225 if (!fits_in_signed_long (exp
->X_add_number
))
8227 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8228 if (i
.types
[this_operand
].bitfield
.baseindex
)
8230 as_bad (_("0x%lx out range of signed 32bit displacement"),
8231 (long) exp
->X_add_number
);
8237 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8238 else if (exp
->X_op
!= O_constant
8239 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8240 && exp_seg
!= absolute_section
8241 && exp_seg
!= text_section
8242 && exp_seg
!= data_section
8243 && exp_seg
!= bss_section
8244 && exp_seg
!= undefined_section
8245 && !bfd_is_com_section (exp_seg
))
8247 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8252 /* Check if this is a displacement only operand. */
8253 bigdisp
= i
.types
[this_operand
];
8254 bigdisp
.bitfield
.disp8
= 0;
8255 bigdisp
.bitfield
.disp16
= 0;
8256 bigdisp
.bitfield
.disp32
= 0;
8257 bigdisp
.bitfield
.disp32s
= 0;
8258 bigdisp
.bitfield
.disp64
= 0;
8259 if (operand_type_all_zero (&bigdisp
))
8260 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8266 /* Make sure the memory operand we've been dealt is valid.
8267 Return 1 on success, 0 on a failure. */
8270 i386_index_check (const char *operand_string
)
8272 const char *kind
= "base/index";
8273 enum flag_code addr_mode
;
8275 if (i
.prefix
[ADDR_PREFIX
])
8276 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8279 addr_mode
= flag_code
;
8281 #if INFER_ADDR_PREFIX
8282 if (i
.mem_operands
== 0)
8284 /* Infer address prefix from the first memory operand. */
8285 const reg_entry
*addr_reg
= i
.base_reg
;
8287 if (addr_reg
== NULL
)
8288 addr_reg
= i
.index_reg
;
8292 if (addr_reg
->reg_num
== RegEip
8293 || addr_reg
->reg_num
== RegEiz
8294 || addr_reg
->reg_type
.bitfield
.reg32
)
8295 addr_mode
= CODE_32BIT
;
8296 else if (flag_code
!= CODE_64BIT
8297 && addr_reg
->reg_type
.bitfield
.reg16
)
8298 addr_mode
= CODE_16BIT
;
8300 if (addr_mode
!= flag_code
)
8302 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8304 /* Change the size of any displacement too. At most one
8305 of Disp16 or Disp32 is set.
8306 FIXME. There doesn't seem to be any real need for
8307 separate Disp16 and Disp32 flags. The same goes for
8308 Imm16 and Imm32. Removing them would probably clean
8309 up the code quite a lot. */
8310 if (flag_code
!= CODE_64BIT
8311 && (i
.types
[this_operand
].bitfield
.disp16
8312 || i
.types
[this_operand
].bitfield
.disp32
))
8313 i
.types
[this_operand
]
8314 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8321 if (current_templates
->start
->opcode_modifier
.isstring
8322 && !current_templates
->start
->opcode_modifier
.immext
8323 && (current_templates
->end
[-1].opcode_modifier
.isstring
8326 /* Memory operands of string insns are special in that they only allow
8327 a single register (rDI, rSI, or rBX) as their memory address. */
8328 const reg_entry
*expected_reg
;
8329 static const char *di_si
[][2] =
8335 static const char *bx
[] = { "ebx", "bx", "rbx" };
8337 kind
= "string address";
8339 if (current_templates
->start
->opcode_modifier
.w
)
8341 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8343 if (!type
.bitfield
.baseindex
8344 || ((!i
.mem_operands
!= !intel_syntax
)
8345 && current_templates
->end
[-1].operand_types
[1]
8346 .bitfield
.baseindex
))
8347 type
= current_templates
->end
[-1].operand_types
[1];
8348 expected_reg
= hash_find (reg_hash
,
8349 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8353 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8355 if (i
.base_reg
!= expected_reg
8357 || operand_type_check (i
.types
[this_operand
], disp
))
8359 /* The second memory operand must have the same size as
8363 && !((addr_mode
== CODE_64BIT
8364 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8365 || (addr_mode
== CODE_32BIT
8366 ? i
.base_reg
->reg_type
.bitfield
.reg32
8367 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8370 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8372 intel_syntax
? '[' : '(',
8374 expected_reg
->reg_name
,
8375 intel_syntax
? ']' : ')');
8382 as_bad (_("`%s' is not a valid %s expression"),
8383 operand_string
, kind
);
8388 if (addr_mode
!= CODE_16BIT
)
8390 /* 32-bit/64-bit checks. */
8392 && (addr_mode
== CODE_64BIT
8393 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8394 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8396 || (i
.base_reg
->reg_num
8397 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8399 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8400 && !i
.index_reg
->reg_type
.bitfield
.regymm
8401 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8402 && ((addr_mode
== CODE_64BIT
8403 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8404 || i
.index_reg
->reg_num
== RegRiz
)
8405 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8406 || i
.index_reg
->reg_num
== RegEiz
))
8407 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8412 /* 16-bit checks. */
8414 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8415 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8417 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8418 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8420 && i
.base_reg
->reg_num
< 6
8421 && i
.index_reg
->reg_num
>= 6
8422 && i
.log2_scale_factor
== 0))))
8429 /* Handle vector immediates. */
8432 RC_SAE_immediate (const char *imm_start
)
8434 unsigned int match_found
, j
;
8435 const char *pstr
= imm_start
;
8443 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8445 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8449 rc_op
.type
= RC_NamesTable
[j
].type
;
8450 rc_op
.operand
= this_operand
;
8451 i
.rounding
= &rc_op
;
8455 as_bad (_("duplicated `%s'"), imm_start
);
8458 pstr
+= RC_NamesTable
[j
].len
;
8468 as_bad (_("Missing '}': '%s'"), imm_start
);
8471 /* RC/SAE immediate string should contain nothing more. */;
8474 as_bad (_("Junk after '}': '%s'"), imm_start
);
8478 exp
= &im_expressions
[i
.imm_operands
++];
8479 i
.op
[this_operand
].imms
= exp
;
8481 exp
->X_op
= O_constant
;
8482 exp
->X_add_number
= 0;
8483 exp
->X_add_symbol
= (symbolS
*) 0;
8484 exp
->X_op_symbol
= (symbolS
*) 0;
8486 i
.types
[this_operand
].bitfield
.imm8
= 1;
8490 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8494 i386_att_operand (char *operand_string
)
8498 char *op_string
= operand_string
;
8500 if (is_space_char (*op_string
))
8503 /* We check for an absolute prefix (differentiating,
8504 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8505 if (*op_string
== ABSOLUTE_PREFIX
)
8508 if (is_space_char (*op_string
))
8510 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8513 /* Check if operand is a register. */
8514 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8516 i386_operand_type temp
;
8518 /* Check for a segment override by searching for ':' after a
8519 segment register. */
8521 if (is_space_char (*op_string
))
8523 if (*op_string
== ':'
8524 && (r
->reg_type
.bitfield
.sreg2
8525 || r
->reg_type
.bitfield
.sreg3
))
8530 i
.seg
[i
.mem_operands
] = &es
;
8533 i
.seg
[i
.mem_operands
] = &cs
;
8536 i
.seg
[i
.mem_operands
] = &ss
;
8539 i
.seg
[i
.mem_operands
] = &ds
;
8542 i
.seg
[i
.mem_operands
] = &fs
;
8545 i
.seg
[i
.mem_operands
] = &gs
;
8549 /* Skip the ':' and whitespace. */
8551 if (is_space_char (*op_string
))
8554 if (!is_digit_char (*op_string
)
8555 && !is_identifier_char (*op_string
)
8556 && *op_string
!= '('
8557 && *op_string
!= ABSOLUTE_PREFIX
)
8559 as_bad (_("bad memory operand `%s'"), op_string
);
8562 /* Handle case of %es:*foo. */
8563 if (*op_string
== ABSOLUTE_PREFIX
)
8566 if (is_space_char (*op_string
))
8568 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8570 goto do_memory_reference
;
8573 /* Handle vector operations. */
8574 if (*op_string
== '{')
8576 op_string
= check_VecOperations (op_string
, NULL
);
8577 if (op_string
== NULL
)
8583 as_bad (_("junk `%s' after register"), op_string
);
8587 temp
.bitfield
.baseindex
= 0;
8588 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8590 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8591 i
.op
[this_operand
].regs
= r
;
8594 else if (*op_string
== REGISTER_PREFIX
)
8596 as_bad (_("bad register name `%s'"), op_string
);
8599 else if (*op_string
== IMMEDIATE_PREFIX
)
8602 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8604 as_bad (_("immediate operand illegal with absolute jump"));
8607 if (!i386_immediate (op_string
))
8610 else if (RC_SAE_immediate (operand_string
))
8612 /* If it is a RC or SAE immediate, do nothing. */
8615 else if (is_digit_char (*op_string
)
8616 || is_identifier_char (*op_string
)
8617 || *op_string
== '(')
8619 /* This is a memory reference of some sort. */
8622 /* Start and end of displacement string expression (if found). */
8623 char *displacement_string_start
;
8624 char *displacement_string_end
;
8627 do_memory_reference
:
8628 if ((i
.mem_operands
== 1
8629 && !current_templates
->start
->opcode_modifier
.isstring
)
8630 || i
.mem_operands
== 2)
8632 as_bad (_("too many memory references for `%s'"),
8633 current_templates
->start
->name
);
8637 /* Check for base index form. We detect the base index form by
8638 looking for an ')' at the end of the operand, searching
8639 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8641 base_string
= op_string
+ strlen (op_string
);
8643 /* Handle vector operations. */
8644 vop_start
= strchr (op_string
, '{');
8645 if (vop_start
&& vop_start
< base_string
)
8647 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8649 base_string
= vop_start
;
8653 if (is_space_char (*base_string
))
8656 /* If we only have a displacement, set-up for it to be parsed later. */
8657 displacement_string_start
= op_string
;
8658 displacement_string_end
= base_string
+ 1;
8660 if (*base_string
== ')')
8663 unsigned int parens_balanced
= 1;
8664 /* We've already checked that the number of left & right ()'s are
8665 equal, so this loop will not be infinite. */
8669 if (*base_string
== ')')
8671 if (*base_string
== '(')
8674 while (parens_balanced
);
8676 temp_string
= base_string
;
8678 /* Skip past '(' and whitespace. */
8680 if (is_space_char (*base_string
))
8683 if (*base_string
== ','
8684 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8687 displacement_string_end
= temp_string
;
8689 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8693 base_string
= end_op
;
8694 if (is_space_char (*base_string
))
8698 /* There may be an index reg or scale factor here. */
8699 if (*base_string
== ',')
8702 if (is_space_char (*base_string
))
8705 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8708 base_string
= end_op
;
8709 if (is_space_char (*base_string
))
8711 if (*base_string
== ',')
8714 if (is_space_char (*base_string
))
8717 else if (*base_string
!= ')')
8719 as_bad (_("expecting `,' or `)' "
8720 "after index register in `%s'"),
8725 else if (*base_string
== REGISTER_PREFIX
)
8727 end_op
= strchr (base_string
, ',');
8730 as_bad (_("bad register name `%s'"), base_string
);
8734 /* Check for scale factor. */
8735 if (*base_string
!= ')')
8737 char *end_scale
= i386_scale (base_string
);
8742 base_string
= end_scale
;
8743 if (is_space_char (*base_string
))
8745 if (*base_string
!= ')')
8747 as_bad (_("expecting `)' "
8748 "after scale factor in `%s'"),
8753 else if (!i
.index_reg
)
8755 as_bad (_("expecting index register or scale factor "
8756 "after `,'; got '%c'"),
8761 else if (*base_string
!= ')')
8763 as_bad (_("expecting `,' or `)' "
8764 "after base register in `%s'"),
8769 else if (*base_string
== REGISTER_PREFIX
)
8771 end_op
= strchr (base_string
, ',');
8774 as_bad (_("bad register name `%s'"), base_string
);
8779 /* If there's an expression beginning the operand, parse it,
8780 assuming displacement_string_start and
8781 displacement_string_end are meaningful. */
8782 if (displacement_string_start
!= displacement_string_end
)
8784 if (!i386_displacement (displacement_string_start
,
8785 displacement_string_end
))
8789 /* Special case for (%dx) while doing input/output op. */
8791 && operand_type_equal (&i
.base_reg
->reg_type
,
8792 ®16_inoutportreg
)
8794 && i
.log2_scale_factor
== 0
8795 && i
.seg
[i
.mem_operands
] == 0
8796 && !operand_type_check (i
.types
[this_operand
], disp
))
8798 i
.types
[this_operand
] = inoutportreg
;
8802 if (i386_index_check (operand_string
) == 0)
8804 i
.types
[this_operand
].bitfield
.mem
= 1;
8809 /* It's not a memory operand; argh! */
8810 as_bad (_("invalid char %s beginning operand %d `%s'"),
8811 output_invalid (*op_string
),
8816 return 1; /* Normal return. */
8819 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8820 that an rs_machine_dependent frag may reach. */
8823 i386_frag_max_var (fragS
*frag
)
8825 /* The only relaxable frags are for jumps.
8826 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8827 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8828 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8831 /* md_estimate_size_before_relax()
8833 Called just before relax() for rs_machine_dependent frags. The x86
8834 assembler uses these frags to handle variable size jump
8837 Any symbol that is now undefined will not become defined.
8838 Return the correct fr_subtype in the frag.
8839 Return the initial "guess for variable size of frag" to caller.
8840 The guess is actually the growth beyond the fixed part. Whatever
8841 we do to grow the fixed or variable part contributes to our
8845 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8847 /* We've already got fragP->fr_subtype right; all we have to do is
8848 check for un-relaxable symbols. On an ELF system, we can't relax
8849 an externally visible symbol, because it may be overridden by a
8851 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8852 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8854 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8855 || S_IS_WEAK (fragP
->fr_symbol
)
8856 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8857 & BSF_GNU_INDIRECT_FUNCTION
))))
8859 #if defined (OBJ_COFF) && defined (TE_PE)
8860 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8861 && S_IS_WEAK (fragP
->fr_symbol
))
8865 /* Symbol is undefined in this segment, or we need to keep a
8866 reloc so that weak symbols can be overridden. */
8867 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8868 enum bfd_reloc_code_real reloc_type
;
8869 unsigned char *opcode
;
8872 if (fragP
->fr_var
!= NO_RELOC
)
8873 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8875 reloc_type
= BFD_RELOC_16_PCREL
;
8877 reloc_type
= BFD_RELOC_32_PCREL
;
8879 old_fr_fix
= fragP
->fr_fix
;
8880 opcode
= (unsigned char *) fragP
->fr_opcode
;
8882 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8885 /* Make jmp (0xeb) a (d)word displacement jump. */
8887 fragP
->fr_fix
+= size
;
8888 fix_new (fragP
, old_fr_fix
, size
,
8890 fragP
->fr_offset
, 1,
8896 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8898 /* Negate the condition, and branch past an
8899 unconditional jump. */
8902 /* Insert an unconditional jump. */
8904 /* We added two extra opcode bytes, and have a two byte
8906 fragP
->fr_fix
+= 2 + 2;
8907 fix_new (fragP
, old_fr_fix
+ 2, 2,
8909 fragP
->fr_offset
, 1,
8916 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8921 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8923 fragP
->fr_offset
, 1,
8925 fixP
->fx_signed
= 1;
8929 /* This changes the byte-displacement jump 0x7N
8930 to the (d)word-displacement jump 0x0f,0x8N. */
8931 opcode
[1] = opcode
[0] + 0x10;
8932 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8933 /* We've added an opcode byte. */
8934 fragP
->fr_fix
+= 1 + size
;
8935 fix_new (fragP
, old_fr_fix
+ 1, size
,
8937 fragP
->fr_offset
, 1,
8942 BAD_CASE (fragP
->fr_subtype
);
8946 return fragP
->fr_fix
- old_fr_fix
;
8949 /* Guess size depending on current relax state. Initially the relax
8950 state will correspond to a short jump and we return 1, because
8951 the variable part of the frag (the branch offset) is one byte
8952 long. However, we can relax a section more than once and in that
8953 case we must either set fr_subtype back to the unrelaxed state,
8954 or return the value for the appropriate branch. */
8955 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8958 /* Called after relax() is finished.
8960 In: Address of frag.
8961 fr_type == rs_machine_dependent.
8962 fr_subtype is what the address relaxed to.
8964 Out: Any fixSs and constants are set up.
8965 Caller will turn frag into a ".space 0". */
8968 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8971 unsigned char *opcode
;
8972 unsigned char *where_to_put_displacement
= NULL
;
8973 offsetT target_address
;
8974 offsetT opcode_address
;
8975 unsigned int extension
= 0;
8976 offsetT displacement_from_opcode_start
;
8978 opcode
= (unsigned char *) fragP
->fr_opcode
;
8980 /* Address we want to reach in file space. */
8981 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8983 /* Address opcode resides at in file space. */
8984 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8986 /* Displacement from opcode start to fill into instruction. */
8987 displacement_from_opcode_start
= target_address
- opcode_address
;
8989 if ((fragP
->fr_subtype
& BIG
) == 0)
8991 /* Don't have to change opcode. */
8992 extension
= 1; /* 1 opcode + 1 displacement */
8993 where_to_put_displacement
= &opcode
[1];
8997 if (no_cond_jump_promotion
8998 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8999 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9000 _("long jump required"));
9002 switch (fragP
->fr_subtype
)
9004 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9005 extension
= 4; /* 1 opcode + 4 displacement */
9007 where_to_put_displacement
= &opcode
[1];
9010 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9011 extension
= 2; /* 1 opcode + 2 displacement */
9013 where_to_put_displacement
= &opcode
[1];
9016 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9017 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9018 extension
= 5; /* 2 opcode + 4 displacement */
9019 opcode
[1] = opcode
[0] + 0x10;
9020 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9021 where_to_put_displacement
= &opcode
[2];
9024 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9025 extension
= 3; /* 2 opcode + 2 displacement */
9026 opcode
[1] = opcode
[0] + 0x10;
9027 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9028 where_to_put_displacement
= &opcode
[2];
9031 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9036 where_to_put_displacement
= &opcode
[3];
9040 BAD_CASE (fragP
->fr_subtype
);
9045 /* If size if less then four we are sure that the operand fits,
9046 but if it's 4, then it could be that the displacement is larger
9048 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9050 && ((addressT
) (displacement_from_opcode_start
- extension
9051 + ((addressT
) 1 << 31))
9052 > (((addressT
) 2 << 31) - 1)))
9054 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9055 _("jump target out of range"));
9056 /* Make us emit 0. */
9057 displacement_from_opcode_start
= extension
;
9059 /* Now put displacement after opcode. */
9060 md_number_to_chars ((char *) where_to_put_displacement
,
9061 (valueT
) (displacement_from_opcode_start
- extension
),
9062 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9063 fragP
->fr_fix
+= extension
;
9066 /* Apply a fixup (fixP) to segment data, once it has been determined
9067 by our caller that we have all the info we need to fix it up.
9069 Parameter valP is the pointer to the value of the bits.
9071 On the 386, immediates, displacements, and data pointers are all in
9072 the same (little-endian) format, so we don't need to care about which
9076 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9078 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9079 valueT value
= *valP
;
9081 #if !defined (TE_Mach)
9084 switch (fixP
->fx_r_type
)
9090 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9093 case BFD_RELOC_X86_64_32S
:
9094 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9097 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9100 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9105 if (fixP
->fx_addsy
!= NULL
9106 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9107 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9108 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9109 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
9110 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
)
9111 && !use_rela_relocations
)
9113 /* This is a hack. There should be a better way to handle this.
9114 This covers for the fact that bfd_install_relocation will
9115 subtract the current location (for partial_inplace, PC relative
9116 relocations); see more below. */
9120 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9123 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9125 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9128 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9131 || (symbol_section_p (fixP
->fx_addsy
)
9132 && sym_seg
!= absolute_section
))
9133 && !generic_force_reloc (fixP
))
9135 /* Yes, we add the values in twice. This is because
9136 bfd_install_relocation subtracts them out again. I think
9137 bfd_install_relocation is broken, but I don't dare change
9139 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9143 #if defined (OBJ_COFF) && defined (TE_PE)
9144 /* For some reason, the PE format does not store a
9145 section address offset for a PC relative symbol. */
9146 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9147 || S_IS_WEAK (fixP
->fx_addsy
))
9148 value
+= md_pcrel_from (fixP
);
9151 #if defined (OBJ_COFF) && defined (TE_PE)
9152 if (fixP
->fx_addsy
!= NULL
9153 && S_IS_WEAK (fixP
->fx_addsy
)
9154 /* PR 16858: Do not modify weak function references. */
9155 && ! fixP
->fx_pcrel
)
9157 #if !defined (TE_PEP)
9158 /* For x86 PE weak function symbols are neither PC-relative
9159 nor do they set S_IS_FUNCTION. So the only reliable way
9160 to detect them is to check the flags of their containing
9162 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9163 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9167 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9171 /* Fix a few things - the dynamic linker expects certain values here,
9172 and we must not disappoint it. */
9173 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9174 if (IS_ELF
&& fixP
->fx_addsy
)
9175 switch (fixP
->fx_r_type
)
9177 case BFD_RELOC_386_PLT32
:
9178 case BFD_RELOC_X86_64_PLT32
:
9179 case BFD_RELOC_X86_64_PLT32_BND
:
9180 /* Make the jump instruction point to the address of the operand. At
9181 runtime we merely add the offset to the actual PLT entry. */
9185 case BFD_RELOC_386_TLS_GD
:
9186 case BFD_RELOC_386_TLS_LDM
:
9187 case BFD_RELOC_386_TLS_IE_32
:
9188 case BFD_RELOC_386_TLS_IE
:
9189 case BFD_RELOC_386_TLS_GOTIE
:
9190 case BFD_RELOC_386_TLS_GOTDESC
:
9191 case BFD_RELOC_X86_64_TLSGD
:
9192 case BFD_RELOC_X86_64_TLSLD
:
9193 case BFD_RELOC_X86_64_GOTTPOFF
:
9194 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9195 value
= 0; /* Fully resolved at runtime. No addend. */
9197 case BFD_RELOC_386_TLS_LE
:
9198 case BFD_RELOC_386_TLS_LDO_32
:
9199 case BFD_RELOC_386_TLS_LE_32
:
9200 case BFD_RELOC_X86_64_DTPOFF32
:
9201 case BFD_RELOC_X86_64_DTPOFF64
:
9202 case BFD_RELOC_X86_64_TPOFF32
:
9203 case BFD_RELOC_X86_64_TPOFF64
:
9204 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9207 case BFD_RELOC_386_TLS_DESC_CALL
:
9208 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9209 value
= 0; /* Fully resolved at runtime. No addend. */
9210 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9214 case BFD_RELOC_386_GOT32
:
9215 case BFD_RELOC_X86_64_GOT32
:
9216 value
= 0; /* Fully resolved at runtime. No addend. */
9219 case BFD_RELOC_VTABLE_INHERIT
:
9220 case BFD_RELOC_VTABLE_ENTRY
:
9227 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9229 #endif /* !defined (TE_Mach) */
9231 /* Are we finished with this relocation now? */
9232 if (fixP
->fx_addsy
== NULL
)
9234 #if defined (OBJ_COFF) && defined (TE_PE)
9235 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9238 /* Remember value for tc_gen_reloc. */
9239 fixP
->fx_addnumber
= value
;
9240 /* Clear out the frag for now. */
9244 else if (use_rela_relocations
)
9246 fixP
->fx_no_overflow
= 1;
9247 /* Remember value for tc_gen_reloc. */
9248 fixP
->fx_addnumber
= value
;
9252 md_number_to_chars (p
, value
, fixP
->fx_size
);
9256 md_atof (int type
, char *litP
, int *sizeP
)
9258 /* This outputs the LITTLENUMs in REVERSE order;
9259 in accord with the bigendian 386. */
9260 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9263 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9266 output_invalid (int c
)
9269 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9272 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9273 "(0x%x)", (unsigned char) c
);
9274 return output_invalid_buf
;
9277 /* REG_STRING starts *before* REGISTER_PREFIX. */
9279 static const reg_entry
*
9280 parse_real_register (char *reg_string
, char **end_op
)
9282 char *s
= reg_string
;
9284 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9287 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9288 if (*s
== REGISTER_PREFIX
)
9291 if (is_space_char (*s
))
9295 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9297 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9298 return (const reg_entry
*) NULL
;
9302 /* For naked regs, make sure that we are not dealing with an identifier.
9303 This prevents confusing an identifier like `eax_var' with register
9305 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9306 return (const reg_entry
*) NULL
;
9310 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9312 /* Handle floating point regs, allowing spaces in the (i) part. */
9313 if (r
== i386_regtab
/* %st is first entry of table */)
9315 if (is_space_char (*s
))
9320 if (is_space_char (*s
))
9322 if (*s
>= '0' && *s
<= '7')
9326 if (is_space_char (*s
))
9331 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9336 /* We have "%st(" then garbage. */
9337 return (const reg_entry
*) NULL
;
9341 if (r
== NULL
|| allow_pseudo_reg
)
9344 if (operand_type_all_zero (&r
->reg_type
))
9345 return (const reg_entry
*) NULL
;
9347 if ((r
->reg_type
.bitfield
.reg32
9348 || r
->reg_type
.bitfield
.sreg3
9349 || r
->reg_type
.bitfield
.control
9350 || r
->reg_type
.bitfield
.debug
9351 || r
->reg_type
.bitfield
.test
)
9352 && !cpu_arch_flags
.bitfield
.cpui386
)
9353 return (const reg_entry
*) NULL
;
9355 if (r
->reg_type
.bitfield
.floatreg
9356 && !cpu_arch_flags
.bitfield
.cpu8087
9357 && !cpu_arch_flags
.bitfield
.cpu287
9358 && !cpu_arch_flags
.bitfield
.cpu387
)
9359 return (const reg_entry
*) NULL
;
9361 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9362 return (const reg_entry
*) NULL
;
9364 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9365 return (const reg_entry
*) NULL
;
9367 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9368 return (const reg_entry
*) NULL
;
9370 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9371 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9372 return (const reg_entry
*) NULL
;
9374 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9375 if (!allow_index_reg
9376 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9377 return (const reg_entry
*) NULL
;
9379 /* Upper 16 vector register is only available with VREX in 64bit
9381 if ((r
->reg_flags
& RegVRex
))
9383 if (!cpu_arch_flags
.bitfield
.cpuvrex
9384 || flag_code
!= CODE_64BIT
)
9385 return (const reg_entry
*) NULL
;
9390 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9391 || r
->reg_type
.bitfield
.reg64
)
9392 && (!cpu_arch_flags
.bitfield
.cpulm
9393 || !operand_type_equal (&r
->reg_type
, &control
))
9394 && flag_code
!= CODE_64BIT
)
9395 return (const reg_entry
*) NULL
;
9397 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9398 return (const reg_entry
*) NULL
;
9403 /* REG_STRING starts *before* REGISTER_PREFIX. */
9405 static const reg_entry
*
9406 parse_register (char *reg_string
, char **end_op
)
9410 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9411 r
= parse_real_register (reg_string
, end_op
);
9416 char *save
= input_line_pointer
;
9420 input_line_pointer
= reg_string
;
9421 c
= get_symbol_end ();
9422 symbolP
= symbol_find (reg_string
);
9423 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9425 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9427 know (e
->X_op
== O_register
);
9428 know (e
->X_add_number
>= 0
9429 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9430 r
= i386_regtab
+ e
->X_add_number
;
9431 *end_op
= input_line_pointer
;
9433 *input_line_pointer
= c
;
9434 input_line_pointer
= save
;
9440 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9443 char *end
= input_line_pointer
;
9446 r
= parse_register (name
, &input_line_pointer
);
9447 if (r
&& end
<= input_line_pointer
)
9449 *nextcharP
= *input_line_pointer
;
9450 *input_line_pointer
= 0;
9451 e
->X_op
= O_register
;
9452 e
->X_add_number
= r
- i386_regtab
;
9455 input_line_pointer
= end
;
9457 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9461 md_operand (expressionS
*e
)
9466 switch (*input_line_pointer
)
9468 case REGISTER_PREFIX
:
9469 r
= parse_real_register (input_line_pointer
, &end
);
9472 e
->X_op
= O_register
;
9473 e
->X_add_number
= r
- i386_regtab
;
9474 input_line_pointer
= end
;
9479 gas_assert (intel_syntax
);
9480 end
= input_line_pointer
++;
9482 if (*input_line_pointer
== ']')
9484 ++input_line_pointer
;
9485 e
->X_op_symbol
= make_expr_symbol (e
);
9486 e
->X_add_symbol
= NULL
;
9487 e
->X_add_number
= 0;
9493 input_line_pointer
= end
;
9500 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9501 const char *md_shortopts
= "kVQ:sqn";
9503 const char *md_shortopts
= "qn";
9506 #define OPTION_32 (OPTION_MD_BASE + 0)
9507 #define OPTION_64 (OPTION_MD_BASE + 1)
9508 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9509 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9510 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9511 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9512 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9513 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9514 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9515 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9516 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9517 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9518 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9519 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9520 #define OPTION_X32 (OPTION_MD_BASE + 14)
9521 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9522 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9523 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9524 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9526 struct option md_longopts
[] =
9528 {"32", no_argument
, NULL
, OPTION_32
},
9529 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9530 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9531 {"64", no_argument
, NULL
, OPTION_64
},
9533 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9534 {"x32", no_argument
, NULL
, OPTION_X32
},
9536 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9537 {"march", required_argument
, NULL
, OPTION_MARCH
},
9538 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9539 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9540 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9541 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9542 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9543 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9544 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9545 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9546 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9547 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9548 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9549 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9550 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9551 # if defined (TE_PE) || defined (TE_PEP)
9552 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9554 {NULL
, no_argument
, NULL
, 0}
9556 size_t md_longopts_size
= sizeof (md_longopts
);
9559 md_parse_option (int c
, char *arg
)
9567 optimize_align_code
= 0;
9574 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9575 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9576 should be emitted or not. FIXME: Not implemented. */
9580 /* -V: SVR4 argument to print version ID. */
9582 print_version_id ();
9585 /* -k: Ignore for FreeBSD compatibility. */
9590 /* -s: On i386 Solaris, this tells the native assembler to use
9591 .stab instead of .stab.excl. We always use .stab anyhow. */
9594 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9595 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9598 const char **list
, **l
;
9600 list
= bfd_target_list ();
9601 for (l
= list
; *l
!= NULL
; l
++)
9602 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9603 || strcmp (*l
, "coff-x86-64") == 0
9604 || strcmp (*l
, "pe-x86-64") == 0
9605 || strcmp (*l
, "pei-x86-64") == 0
9606 || strcmp (*l
, "mach-o-x86-64") == 0)
9608 default_arch
= "x86_64";
9612 as_fatal (_("no compiled in support for x86_64"));
9618 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9622 const char **list
, **l
;
9624 list
= bfd_target_list ();
9625 for (l
= list
; *l
!= NULL
; l
++)
9626 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9628 default_arch
= "x86_64:32";
9632 as_fatal (_("no compiled in support for 32bit x86_64"));
9636 as_fatal (_("32bit x86_64 is only supported for ELF"));
9641 default_arch
= "i386";
9645 #ifdef SVR4_COMMENT_CHARS
9650 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9652 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9656 i386_comment_chars
= n
;
9662 arch
= xstrdup (arg
);
9666 as_fatal (_("invalid -march= option: `%s'"), arg
);
9667 next
= strchr (arch
, '+');
9670 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9672 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9675 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9678 cpu_arch_name
= cpu_arch
[j
].name
;
9679 cpu_sub_arch_name
= NULL
;
9680 cpu_arch_flags
= cpu_arch
[j
].flags
;
9681 cpu_arch_isa
= cpu_arch
[j
].type
;
9682 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9683 if (!cpu_arch_tune_set
)
9685 cpu_arch_tune
= cpu_arch_isa
;
9686 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9690 else if (*cpu_arch
[j
].name
== '.'
9691 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9693 /* ISA entension. */
9694 i386_cpu_flags flags
;
9696 if (!cpu_arch
[j
].negated
)
9697 flags
= cpu_flags_or (cpu_arch_flags
,
9700 flags
= cpu_flags_and_not (cpu_arch_flags
,
9702 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9704 if (cpu_sub_arch_name
)
9706 char *name
= cpu_sub_arch_name
;
9707 cpu_sub_arch_name
= concat (name
,
9709 (const char *) NULL
);
9713 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9714 cpu_arch_flags
= flags
;
9715 cpu_arch_isa_flags
= flags
;
9721 if (j
>= ARRAY_SIZE (cpu_arch
))
9722 as_fatal (_("invalid -march= option: `%s'"), arg
);
9726 while (next
!= NULL
);
9731 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9732 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9734 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9736 cpu_arch_tune_set
= 1;
9737 cpu_arch_tune
= cpu_arch
[j
].type
;
9738 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9742 if (j
>= ARRAY_SIZE (cpu_arch
))
9743 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9746 case OPTION_MMNEMONIC
:
9747 if (strcasecmp (arg
, "att") == 0)
9749 else if (strcasecmp (arg
, "intel") == 0)
9752 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9755 case OPTION_MSYNTAX
:
9756 if (strcasecmp (arg
, "att") == 0)
9758 else if (strcasecmp (arg
, "intel") == 0)
9761 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9764 case OPTION_MINDEX_REG
:
9765 allow_index_reg
= 1;
9768 case OPTION_MNAKED_REG
:
9769 allow_naked_reg
= 1;
9772 case OPTION_MOLD_GCC
:
9776 case OPTION_MSSE2AVX
:
9780 case OPTION_MSSE_CHECK
:
9781 if (strcasecmp (arg
, "error") == 0)
9782 sse_check
= check_error
;
9783 else if (strcasecmp (arg
, "warning") == 0)
9784 sse_check
= check_warning
;
9785 else if (strcasecmp (arg
, "none") == 0)
9786 sse_check
= check_none
;
9788 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9791 case OPTION_MOPERAND_CHECK
:
9792 if (strcasecmp (arg
, "error") == 0)
9793 operand_check
= check_error
;
9794 else if (strcasecmp (arg
, "warning") == 0)
9795 operand_check
= check_warning
;
9796 else if (strcasecmp (arg
, "none") == 0)
9797 operand_check
= check_none
;
9799 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9802 case OPTION_MAVXSCALAR
:
9803 if (strcasecmp (arg
, "128") == 0)
9805 else if (strcasecmp (arg
, "256") == 0)
9808 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9811 case OPTION_MADD_BND_PREFIX
:
9815 case OPTION_MEVEXLIG
:
9816 if (strcmp (arg
, "128") == 0)
9818 else if (strcmp (arg
, "256") == 0)
9820 else if (strcmp (arg
, "512") == 0)
9823 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9826 case OPTION_MEVEXWIG
:
9827 if (strcmp (arg
, "0") == 0)
9829 else if (strcmp (arg
, "1") == 0)
9832 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9835 # if defined (TE_PE) || defined (TE_PEP)
9836 case OPTION_MBIG_OBJ
:
9847 #define MESSAGE_TEMPLATE \
9851 show_arch (FILE *stream
, int ext
, int check
)
9853 static char message
[] = MESSAGE_TEMPLATE
;
9854 char *start
= message
+ 27;
9856 int size
= sizeof (MESSAGE_TEMPLATE
);
9863 left
= size
- (start
- message
);
9864 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9866 /* Should it be skipped? */
9867 if (cpu_arch
[j
].skip
)
9870 name
= cpu_arch
[j
].name
;
9871 len
= cpu_arch
[j
].len
;
9874 /* It is an extension. Skip if we aren't asked to show it. */
9885 /* It is an processor. Skip if we show only extension. */
9888 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9890 /* It is an impossible processor - skip. */
9894 /* Reserve 2 spaces for ", " or ",\0" */
9897 /* Check if there is any room. */
9905 p
= mempcpy (p
, name
, len
);
9909 /* Output the current message now and start a new one. */
9912 fprintf (stream
, "%s\n", message
);
9914 left
= size
- (start
- message
) - len
- 2;
9916 gas_assert (left
>= 0);
9918 p
= mempcpy (p
, name
, len
);
9923 fprintf (stream
, "%s\n", message
);
9927 md_show_usage (FILE *stream
)
9929 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9930 fprintf (stream
, _("\
9932 -V print assembler version number\n\
9935 fprintf (stream
, _("\
9936 -n Do not optimize code alignment\n\
9937 -q quieten some warnings\n"));
9938 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9939 fprintf (stream
, _("\
9942 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9943 || defined (TE_PE) || defined (TE_PEP))
9944 fprintf (stream
, _("\
9945 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9947 #ifdef SVR4_COMMENT_CHARS
9948 fprintf (stream
, _("\
9949 --divide do not treat `/' as a comment character\n"));
9951 fprintf (stream
, _("\
9952 --divide ignored\n"));
9954 fprintf (stream
, _("\
9955 -march=CPU[,+EXTENSION...]\n\
9956 generate code for CPU and EXTENSION, CPU is one of:\n"));
9957 show_arch (stream
, 0, 1);
9958 fprintf (stream
, _("\
9959 EXTENSION is combination of:\n"));
9960 show_arch (stream
, 1, 0);
9961 fprintf (stream
, _("\
9962 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9963 show_arch (stream
, 0, 0);
9964 fprintf (stream
, _("\
9965 -msse2avx encode SSE instructions with VEX prefix\n"));
9966 fprintf (stream
, _("\
9967 -msse-check=[none|error|warning]\n\
9968 check SSE instructions\n"));
9969 fprintf (stream
, _("\
9970 -moperand-check=[none|error|warning]\n\
9971 check operand combinations for validity\n"));
9972 fprintf (stream
, _("\
9973 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9975 fprintf (stream
, _("\
9976 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9978 fprintf (stream
, _("\
9979 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9980 for EVEX.W bit ignored instructions\n"));
9981 fprintf (stream
, _("\
9982 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9983 fprintf (stream
, _("\
9984 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9985 fprintf (stream
, _("\
9986 -mindex-reg support pseudo index registers\n"));
9987 fprintf (stream
, _("\
9988 -mnaked-reg don't require `%%' prefix for registers\n"));
9989 fprintf (stream
, _("\
9990 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9991 fprintf (stream
, _("\
9992 -madd-bnd-prefix add BND prefix for all valid branches\n"));
9993 # if defined (TE_PE) || defined (TE_PEP)
9994 fprintf (stream
, _("\
9995 -mbig-obj generate big object files\n"));
9999 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10000 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10001 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10003 /* Pick the target format to use. */
10006 i386_target_format (void)
10008 if (!strncmp (default_arch
, "x86_64", 6))
10010 update_code_flag (CODE_64BIT
, 1);
10011 if (default_arch
[6] == '\0')
10012 x86_elf_abi
= X86_64_ABI
;
10014 x86_elf_abi
= X86_64_X32_ABI
;
10016 else if (!strcmp (default_arch
, "i386"))
10017 update_code_flag (CODE_32BIT
, 1);
10019 as_fatal (_("unknown architecture"));
10021 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10022 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10023 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10024 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10026 switch (OUTPUT_FLAVOR
)
10028 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10029 case bfd_target_aout_flavour
:
10030 return AOUT_TARGET_FORMAT
;
10032 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10033 # if defined (TE_PE) || defined (TE_PEP)
10034 case bfd_target_coff_flavour
:
10035 if (flag_code
== CODE_64BIT
)
10036 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10039 # elif defined (TE_GO32)
10040 case bfd_target_coff_flavour
:
10041 return "coff-go32";
10043 case bfd_target_coff_flavour
:
10044 return "coff-i386";
10047 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10048 case bfd_target_elf_flavour
:
10050 const char *format
;
10052 switch (x86_elf_abi
)
10055 format
= ELF_TARGET_FORMAT
;
10058 use_rela_relocations
= 1;
10060 format
= ELF_TARGET_FORMAT64
;
10062 case X86_64_X32_ABI
:
10063 use_rela_relocations
= 1;
10065 disallow_64bit_reloc
= 1;
10066 format
= ELF_TARGET_FORMAT32
;
10069 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10071 if (x86_elf_abi
!= X86_64_ABI
)
10072 as_fatal (_("Intel L1OM is 64bit only"));
10073 return ELF_TARGET_L1OM_FORMAT
;
10075 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10077 if (x86_elf_abi
!= X86_64_ABI
)
10078 as_fatal (_("Intel K1OM is 64bit only"));
10079 return ELF_TARGET_K1OM_FORMAT
;
10085 #if defined (OBJ_MACH_O)
10086 case bfd_target_mach_o_flavour
:
10087 if (flag_code
== CODE_64BIT
)
10089 use_rela_relocations
= 1;
10091 return "mach-o-x86-64";
10094 return "mach-o-i386";
10102 #endif /* OBJ_MAYBE_ more than one */
10104 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10106 i386_elf_emit_arch_note (void)
10108 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10111 asection
*seg
= now_seg
;
10112 subsegT subseg
= now_subseg
;
10113 Elf_Internal_Note i_note
;
10114 Elf_External_Note e_note
;
10115 asection
*note_secp
;
10118 /* Create the .note section. */
10119 note_secp
= subseg_new (".note", 0);
10120 bfd_set_section_flags (stdoutput
,
10122 SEC_HAS_CONTENTS
| SEC_READONLY
);
10124 /* Process the arch string. */
10125 len
= strlen (cpu_arch_name
);
10127 i_note
.namesz
= len
+ 1;
10129 i_note
.type
= NT_ARCH
;
10130 p
= frag_more (sizeof (e_note
.namesz
));
10131 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10132 p
= frag_more (sizeof (e_note
.descsz
));
10133 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10134 p
= frag_more (sizeof (e_note
.type
));
10135 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10136 p
= frag_more (len
+ 1);
10137 strcpy (p
, cpu_arch_name
);
10139 frag_align (2, 0, 0);
10141 subseg_set (seg
, subseg
);
10147 md_undefined_symbol (char *name
)
10149 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10150 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10151 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10152 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10156 if (symbol_find (name
))
10157 as_bad (_("GOT already in symbol table"));
10158 GOT_symbol
= symbol_new (name
, undefined_section
,
10159 (valueT
) 0, &zero_address_frag
);
10166 /* Round up a section size to the appropriate boundary. */
10169 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10171 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10172 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10174 /* For a.out, force the section size to be aligned. If we don't do
10175 this, BFD will align it for us, but it will not write out the
10176 final bytes of the section. This may be a bug in BFD, but it is
10177 easier to fix it here since that is how the other a.out targets
10181 align
= bfd_get_section_alignment (stdoutput
, segment
);
10182 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10189 /* On the i386, PC-relative offsets are relative to the start of the
10190 next instruction. That is, the address of the offset, plus its
10191 size, since the offset is always the last part of the insn. */
10194 md_pcrel_from (fixS
*fixP
)
10196 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10202 s_bss (int ignore ATTRIBUTE_UNUSED
)
10206 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10208 obj_elf_section_change_hook ();
10210 temp
= get_absolute_expression ();
10211 subseg_set (bss_section
, (subsegT
) temp
);
10212 demand_empty_rest_of_line ();
10218 i386_validate_fix (fixS
*fixp
)
10220 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10222 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10226 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10231 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10233 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10235 fixp
->fx_subsy
= 0;
10240 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10243 bfd_reloc_code_real_type code
;
10245 switch (fixp
->fx_r_type
)
10247 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10248 case BFD_RELOC_SIZE32
:
10249 case BFD_RELOC_SIZE64
:
10250 if (S_IS_DEFINED (fixp
->fx_addsy
)
10251 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10253 /* Resolve size relocation against local symbol to size of
10254 the symbol plus addend. */
10255 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10256 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10257 && !fits_in_unsigned_long (value
))
10258 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10259 _("symbol size computation overflow"));
10260 fixp
->fx_addsy
= NULL
;
10261 fixp
->fx_subsy
= NULL
;
10262 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10267 case BFD_RELOC_X86_64_PLT32
:
10268 case BFD_RELOC_X86_64_PLT32_BND
:
10269 case BFD_RELOC_X86_64_GOT32
:
10270 case BFD_RELOC_X86_64_GOTPCREL
:
10271 case BFD_RELOC_386_PLT32
:
10272 case BFD_RELOC_386_GOT32
:
10273 case BFD_RELOC_386_GOTOFF
:
10274 case BFD_RELOC_386_GOTPC
:
10275 case BFD_RELOC_386_TLS_GD
:
10276 case BFD_RELOC_386_TLS_LDM
:
10277 case BFD_RELOC_386_TLS_LDO_32
:
10278 case BFD_RELOC_386_TLS_IE_32
:
10279 case BFD_RELOC_386_TLS_IE
:
10280 case BFD_RELOC_386_TLS_GOTIE
:
10281 case BFD_RELOC_386_TLS_LE_32
:
10282 case BFD_RELOC_386_TLS_LE
:
10283 case BFD_RELOC_386_TLS_GOTDESC
:
10284 case BFD_RELOC_386_TLS_DESC_CALL
:
10285 case BFD_RELOC_X86_64_TLSGD
:
10286 case BFD_RELOC_X86_64_TLSLD
:
10287 case BFD_RELOC_X86_64_DTPOFF32
:
10288 case BFD_RELOC_X86_64_DTPOFF64
:
10289 case BFD_RELOC_X86_64_GOTTPOFF
:
10290 case BFD_RELOC_X86_64_TPOFF32
:
10291 case BFD_RELOC_X86_64_TPOFF64
:
10292 case BFD_RELOC_X86_64_GOTOFF64
:
10293 case BFD_RELOC_X86_64_GOTPC32
:
10294 case BFD_RELOC_X86_64_GOT64
:
10295 case BFD_RELOC_X86_64_GOTPCREL64
:
10296 case BFD_RELOC_X86_64_GOTPC64
:
10297 case BFD_RELOC_X86_64_GOTPLT64
:
10298 case BFD_RELOC_X86_64_PLTOFF64
:
10299 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10300 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10301 case BFD_RELOC_RVA
:
10302 case BFD_RELOC_VTABLE_ENTRY
:
10303 case BFD_RELOC_VTABLE_INHERIT
:
10305 case BFD_RELOC_32_SECREL
:
10307 code
= fixp
->fx_r_type
;
10309 case BFD_RELOC_X86_64_32S
:
10310 if (!fixp
->fx_pcrel
)
10312 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10313 code
= fixp
->fx_r_type
;
10317 if (fixp
->fx_pcrel
)
10319 switch (fixp
->fx_size
)
10322 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10323 _("can not do %d byte pc-relative relocation"),
10325 code
= BFD_RELOC_32_PCREL
;
10327 case 1: code
= BFD_RELOC_8_PCREL
; break;
10328 case 2: code
= BFD_RELOC_16_PCREL
; break;
10330 code
= (fixp
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
10331 ? fixp
-> fx_r_type
: BFD_RELOC_32_PCREL
);
10334 case 8: code
= BFD_RELOC_64_PCREL
; break;
10340 switch (fixp
->fx_size
)
10343 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10344 _("can not do %d byte relocation"),
10346 code
= BFD_RELOC_32
;
10348 case 1: code
= BFD_RELOC_8
; break;
10349 case 2: code
= BFD_RELOC_16
; break;
10350 case 4: code
= BFD_RELOC_32
; break;
10352 case 8: code
= BFD_RELOC_64
; break;
10359 if ((code
== BFD_RELOC_32
10360 || code
== BFD_RELOC_32_PCREL
10361 || code
== BFD_RELOC_X86_64_32S
)
10363 && fixp
->fx_addsy
== GOT_symbol
)
10366 code
= BFD_RELOC_386_GOTPC
;
10368 code
= BFD_RELOC_X86_64_GOTPC32
;
10370 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10372 && fixp
->fx_addsy
== GOT_symbol
)
10374 code
= BFD_RELOC_X86_64_GOTPC64
;
10377 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10378 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10379 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10381 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10383 if (!use_rela_relocations
)
10385 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10386 vtable entry to be used in the relocation's section offset. */
10387 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10388 rel
->address
= fixp
->fx_offset
;
10389 #if defined (OBJ_COFF) && defined (TE_PE)
10390 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10391 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10396 /* Use the rela in 64bit mode. */
10399 if (disallow_64bit_reloc
)
10402 case BFD_RELOC_X86_64_DTPOFF64
:
10403 case BFD_RELOC_X86_64_TPOFF64
:
10404 case BFD_RELOC_64_PCREL
:
10405 case BFD_RELOC_X86_64_GOTOFF64
:
10406 case BFD_RELOC_X86_64_GOT64
:
10407 case BFD_RELOC_X86_64_GOTPCREL64
:
10408 case BFD_RELOC_X86_64_GOTPC64
:
10409 case BFD_RELOC_X86_64_GOTPLT64
:
10410 case BFD_RELOC_X86_64_PLTOFF64
:
10411 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10412 _("cannot represent relocation type %s in x32 mode"),
10413 bfd_get_reloc_code_name (code
));
10419 if (!fixp
->fx_pcrel
)
10420 rel
->addend
= fixp
->fx_offset
;
10424 case BFD_RELOC_X86_64_PLT32
:
10425 case BFD_RELOC_X86_64_PLT32_BND
:
10426 case BFD_RELOC_X86_64_GOT32
:
10427 case BFD_RELOC_X86_64_GOTPCREL
:
10428 case BFD_RELOC_X86_64_TLSGD
:
10429 case BFD_RELOC_X86_64_TLSLD
:
10430 case BFD_RELOC_X86_64_GOTTPOFF
:
10431 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10432 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10433 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10436 rel
->addend
= (section
->vma
10438 + fixp
->fx_addnumber
10439 + md_pcrel_from (fixp
));
10444 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10445 if (rel
->howto
== NULL
)
10447 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10448 _("cannot represent relocation type %s"),
10449 bfd_get_reloc_code_name (code
));
10450 /* Set howto to a garbage value so that we can keep going. */
10451 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10452 gas_assert (rel
->howto
!= NULL
);
10458 #include "tc-i386-intel.c"
10461 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10463 int saved_naked_reg
;
10464 char saved_register_dot
;
10466 saved_naked_reg
= allow_naked_reg
;
10467 allow_naked_reg
= 1;
10468 saved_register_dot
= register_chars
['.'];
10469 register_chars
['.'] = '.';
10470 allow_pseudo_reg
= 1;
10471 expression_and_evaluate (exp
);
10472 allow_pseudo_reg
= 0;
10473 register_chars
['.'] = saved_register_dot
;
10474 allow_naked_reg
= saved_naked_reg
;
10476 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10478 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10480 exp
->X_op
= O_constant
;
10481 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10482 .dw2_regnum
[flag_code
>> 1];
10485 exp
->X_op
= O_illegal
;
10490 tc_x86_frame_initial_instructions (void)
10492 static unsigned int sp_regno
[2];
10494 if (!sp_regno
[flag_code
>> 1])
10496 char *saved_input
= input_line_pointer
;
10497 char sp
[][4] = {"esp", "rsp"};
10500 input_line_pointer
= sp
[flag_code
>> 1];
10501 tc_x86_parse_to_dw2regnum (&exp
);
10502 gas_assert (exp
.X_op
== O_constant
);
10503 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10504 input_line_pointer
= saved_input
;
10507 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10508 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10512 x86_dwarf2_addr_size (void)
10514 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10515 if (x86_elf_abi
== X86_64_X32_ABI
)
10518 return bfd_arch_bits_per_address (stdoutput
) / 8;
10522 i386_elf_section_type (const char *str
, size_t len
)
10524 if (flag_code
== CODE_64BIT
10525 && len
== sizeof ("unwind") - 1
10526 && strncmp (str
, "unwind", 6) == 0)
10527 return SHT_X86_64_UNWIND
;
10534 i386_solaris_fix_up_eh_frame (segT sec
)
10536 if (flag_code
== CODE_64BIT
)
10537 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10543 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10547 exp
.X_op
= O_secrel
;
10548 exp
.X_add_symbol
= symbol
;
10549 exp
.X_add_number
= 0;
10550 emit_expr (&exp
, size
);
10554 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10555 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10558 x86_64_section_letter (int letter
, char **ptr_msg
)
10560 if (flag_code
== CODE_64BIT
)
10563 return SHF_X86_64_LARGE
;
10565 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10568 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10573 x86_64_section_word (char *str
, size_t len
)
10575 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10576 return SHF_X86_64_LARGE
;
10582 handle_large_common (int small ATTRIBUTE_UNUSED
)
10584 if (flag_code
!= CODE_64BIT
)
10586 s_comm_internal (0, elf_common_parse
);
10587 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10591 static segT lbss_section
;
10592 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10593 asection
*saved_bss_section
= bss_section
;
10595 if (lbss_section
== NULL
)
10597 flagword applicable
;
10598 segT seg
= now_seg
;
10599 subsegT subseg
= now_subseg
;
10601 /* The .lbss section is for local .largecomm symbols. */
10602 lbss_section
= subseg_new (".lbss", 0);
10603 applicable
= bfd_applicable_section_flags (stdoutput
);
10604 bfd_set_section_flags (stdoutput
, lbss_section
,
10605 applicable
& SEC_ALLOC
);
10606 seg_info (lbss_section
)->bss
= 1;
10608 subseg_set (seg
, subseg
);
10611 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10612 bss_section
= lbss_section
;
10614 s_comm_internal (0, elf_common_parse
);
10616 elf_com_section_ptr
= saved_com_section_ptr
;
10617 bss_section
= saved_bss_section
;
10620 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */