1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static enum flag_code
i386_addressing_mode (void);
186 static void optimize_imm (void);
187 static void optimize_disp (void);
188 static const insn_template
*match_template (char);
189 static int check_string (void);
190 static int process_suffix (void);
191 static int check_byte_reg (void);
192 static int check_long_reg (void);
193 static int check_qword_reg (void);
194 static int check_word_reg (void);
195 static int finalize_imm (void);
196 static int process_operands (void);
197 static const seg_entry
*build_modrm_byte (void);
198 static void output_insn (void);
199 static void output_imm (fragS
*, offsetT
);
200 static void output_disp (fragS
*, offsetT
);
202 static void s_bss (int);
204 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
205 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
207 /* GNU_PROPERTY_X86_ISA_1_USED. */
208 static unsigned int x86_isa_1_used
;
209 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
210 static unsigned int x86_feature_2_used
;
211 /* Generate x86 used ISA and feature properties. */
212 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
215 static const char *default_arch
= DEFAULT_ARCH
;
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
293 invalid_vsib_address
,
294 invalid_vector_register_set
,
295 unsupported_vector_index_register
,
296 unsupported_broadcast
,
299 mask_not_on_destination
,
302 rc_sae_operand_not_last_imm
,
303 invalid_register_operand
,
308 /* TM holds the template for the insn were currently assembling. */
311 /* SUFFIX holds the instruction size suffix for byte, word, dword
312 or qword, if given. */
315 /* OPERANDS gives the number of given operands. */
316 unsigned int operands
;
318 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
319 of given register, displacement, memory operands and immediate
321 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
323 /* TYPES [i] is the type (see above #defines) which tells us how to
324 use OP[i] for the corresponding operand. */
325 i386_operand_type types
[MAX_OPERANDS
];
327 /* Displacement expression, immediate expression, or register for each
329 union i386_op op
[MAX_OPERANDS
];
331 /* Flags for operands. */
332 unsigned int flags
[MAX_OPERANDS
];
333 #define Operand_PCrel 1
334 #define Operand_Mem 2
336 /* Relocation type for operand */
337 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
339 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
340 the base index byte below. */
341 const reg_entry
*base_reg
;
342 const reg_entry
*index_reg
;
343 unsigned int log2_scale_factor
;
345 /* SEG gives the seg_entries of this insn. They are zero unless
346 explicit segment overrides are given. */
347 const seg_entry
*seg
[2];
349 /* Copied first memory operand string, for re-checking. */
352 /* PREFIX holds all the given prefix opcodes (usually null).
353 PREFIXES is the number of prefix opcodes. */
354 unsigned int prefixes
;
355 unsigned char prefix
[MAX_PREFIXES
];
357 /* Register is in low 3 bits of opcode. */
358 bfd_boolean short_form
;
360 /* The operand to a branch insn indicates an absolute branch. */
361 bfd_boolean jumpabsolute
;
363 /* Has MMX register operands. */
364 bfd_boolean has_regmmx
;
366 /* Has XMM register operands. */
367 bfd_boolean has_regxmm
;
369 /* Has YMM register operands. */
370 bfd_boolean has_regymm
;
372 /* Has ZMM register operands. */
373 bfd_boolean has_regzmm
;
375 /* Has GOTPC or TLS relocation. */
376 bfd_boolean has_gotpc_tls_reloc
;
378 /* RM and SIB are the modrm byte and the sib byte where the
379 addressing modes of this insn are encoded. */
386 /* Masking attributes. */
387 struct Mask_Operation
*mask
;
389 /* Rounding control and SAE attributes. */
390 struct RC_Operation
*rounding
;
392 /* Broadcasting attributes. */
393 struct Broadcast_Operation
*broadcast
;
395 /* Compressed disp8*N attribute. */
396 unsigned int memshift
;
398 /* Prefer load or store in encoding. */
401 dir_encoding_default
= 0,
407 /* Prefer 8bit or 32bit displacement in encoding. */
410 disp_encoding_default
= 0,
415 /* Prefer the REX byte in encoding. */
416 bfd_boolean rex_encoding
;
418 /* Disable instruction size optimization. */
419 bfd_boolean no_optimize
;
421 /* How to encode vector instructions. */
424 vex_encoding_default
= 0,
431 const char *rep_prefix
;
434 const char *hle_prefix
;
436 /* Have BND prefix. */
437 const char *bnd_prefix
;
439 /* Have NOTRACK prefix. */
440 const char *notrack_prefix
;
443 enum i386_error error
;
446 typedef struct _i386_insn i386_insn
;
448 /* Link RC type with corresponding string, that'll be looked for in
457 static const struct RC_name RC_NamesTable
[] =
459 { rne
, STRING_COMMA_LEN ("rn-sae") },
460 { rd
, STRING_COMMA_LEN ("rd-sae") },
461 { ru
, STRING_COMMA_LEN ("ru-sae") },
462 { rz
, STRING_COMMA_LEN ("rz-sae") },
463 { saeonly
, STRING_COMMA_LEN ("sae") },
466 /* List of chars besides those in app.c:symbol_chars that can start an
467 operand. Used to prevent the scrubber eating vital white-space. */
468 const char extra_symbol_chars
[] = "*%-([{}"
477 #if (defined (TE_I386AIX) \
478 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
479 && !defined (TE_GNU) \
480 && !defined (TE_LINUX) \
481 && !defined (TE_NACL) \
482 && !defined (TE_FreeBSD) \
483 && !defined (TE_DragonFly) \
484 && !defined (TE_NetBSD)))
485 /* This array holds the chars that always start a comment. If the
486 pre-processor is disabled, these aren't very useful. The option
487 --divide will remove '/' from this list. */
488 const char *i386_comment_chars
= "#/";
489 #define SVR4_COMMENT_CHARS 1
490 #define PREFIX_SEPARATOR '\\'
493 const char *i386_comment_chars
= "#";
494 #define PREFIX_SEPARATOR '/'
497 /* This array holds the chars that only start a comment at the beginning of
498 a line. If the line seems to have the form '# 123 filename'
499 .line and .file directives will appear in the pre-processed output.
500 Note that input_file.c hand checks for '#' at the beginning of the
501 first line of the input file. This is because the compiler outputs
502 #NO_APP at the beginning of its output.
503 Also note that comments started like this one will always work if
504 '/' isn't otherwise defined. */
505 const char line_comment_chars
[] = "#/";
507 const char line_separator_chars
[] = ";";
509 /* Chars that can be used to separate mant from exp in floating point
511 const char EXP_CHARS
[] = "eE";
513 /* Chars that mean this number is a floating point constant
516 const char FLT_CHARS
[] = "fFdDxX";
518 /* Tables for lexical analysis. */
519 static char mnemonic_chars
[256];
520 static char register_chars
[256];
521 static char operand_chars
[256];
522 static char identifier_chars
[256];
523 static char digit_chars
[256];
525 /* Lexical macros. */
526 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
527 #define is_operand_char(x) (operand_chars[(unsigned char) x])
528 #define is_register_char(x) (register_chars[(unsigned char) x])
529 #define is_space_char(x) ((x) == ' ')
530 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
531 #define is_digit_char(x) (digit_chars[(unsigned char) x])
533 /* All non-digit non-letter characters that may occur in an operand. */
534 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
536 /* md_assemble() always leaves the strings it's passed unaltered. To
537 effect this we maintain a stack of saved characters that we've smashed
538 with '\0's (indicating end of strings for various sub-fields of the
539 assembler instruction). */
540 static char save_stack
[32];
541 static char *save_stack_p
;
542 #define END_STRING_AND_SAVE(s) \
543 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
544 #define RESTORE_END_STRING(s) \
545 do { *(s) = *--save_stack_p; } while (0)
547 /* The instruction we're assembling. */
550 /* Possible templates for current insn. */
551 static const templates
*current_templates
;
553 /* Per instruction expressionS buffers: max displacements & immediates. */
554 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
555 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
557 /* Current operand we are working on. */
558 static int this_operand
= -1;
560 /* We support four different modes. FLAG_CODE variable is used to distinguish
568 static enum flag_code flag_code
;
569 static unsigned int object_64bit
;
570 static unsigned int disallow_64bit_reloc
;
571 static int use_rela_relocations
= 0;
572 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
573 static const char *tls_get_addr
;
575 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
576 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
577 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
579 /* The ELF ABI to use. */
587 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
590 #if defined (TE_PE) || defined (TE_PEP)
591 /* Use big object file format. */
592 static int use_big_obj
= 0;
595 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
596 /* 1 if generating code for a shared library. */
597 static int shared
= 0;
600 /* 1 for intel syntax,
602 static int intel_syntax
= 0;
604 static enum x86_64_isa
606 amd64
= 1, /* AMD64 ISA. */
607 intel64
/* Intel64 ISA. */
610 /* 1 for intel mnemonic,
611 0 if att mnemonic. */
612 static int intel_mnemonic
= !SYSV386_COMPAT
;
614 /* 1 if pseudo registers are permitted. */
615 static int allow_pseudo_reg
= 0;
617 /* 1 if register prefix % not required. */
618 static int allow_naked_reg
= 0;
620 /* 1 if the assembler should add BND prefix for all control-transferring
621 instructions supporting it, even if this prefix wasn't specified
623 static int add_bnd_prefix
= 0;
625 /* 1 if pseudo index register, eiz/riz, is allowed . */
626 static int allow_index_reg
= 0;
628 /* 1 if the assembler should ignore LOCK prefix, even if it was
629 specified explicitly. */
630 static int omit_lock_prefix
= 0;
632 /* 1 if the assembler should encode lfence, mfence, and sfence as
633 "lock addl $0, (%{re}sp)". */
634 static int avoid_fence
= 0;
636 /* Type of the previous instruction. */
651 /* 1 if the assembler should generate relax relocations. */
653 static int generate_relax_relocations
654 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
656 static enum check_kind
662 sse_check
, operand_check
= check_warning
;
664 /* Non-zero if branches should be aligned within power of 2 boundary. */
665 static int align_branch_power
= 0;
667 /* Types of branches to align. */
668 enum align_branch_kind
670 align_branch_none
= 0,
671 align_branch_jcc
= 1,
672 align_branch_fused
= 2,
673 align_branch_jmp
= 3,
674 align_branch_call
= 4,
675 align_branch_indirect
= 5,
679 /* Type bits of branches to align. */
680 enum align_branch_bit
682 align_branch_jcc_bit
= 1 << align_branch_jcc
,
683 align_branch_fused_bit
= 1 << align_branch_fused
,
684 align_branch_jmp_bit
= 1 << align_branch_jmp
,
685 align_branch_call_bit
= 1 << align_branch_call
,
686 align_branch_indirect_bit
= 1 << align_branch_indirect
,
687 align_branch_ret_bit
= 1 << align_branch_ret
690 static unsigned int align_branch
= (align_branch_jcc_bit
691 | align_branch_fused_bit
692 | align_branch_jmp_bit
);
694 /* The maximum padding size for fused jcc. CMP like instruction can
695 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
697 #define MAX_FUSED_JCC_PADDING_SIZE 20
699 /* The maximum number of prefixes added for an instruction. */
700 static unsigned int align_branch_prefix_size
= 5;
703 1. Clear the REX_W bit with register operand if possible.
704 2. Above plus use 128bit vector instruction to clear the full vector
707 static int optimize
= 0;
710 1. Clear the REX_W bit with register operand if possible.
711 2. Above plus use 128bit vector instruction to clear the full vector
713 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
716 static int optimize_for_space
= 0;
718 /* Register prefix used for error message. */
719 static const char *register_prefix
= "%";
721 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
722 leave, push, and pop instructions so that gcc has the same stack
723 frame as in 32 bit mode. */
724 static char stackop_size
= '\0';
726 /* Non-zero to optimize code alignment. */
727 int optimize_align_code
= 1;
729 /* Non-zero to quieten some warnings. */
730 static int quiet_warnings
= 0;
733 static const char *cpu_arch_name
= NULL
;
734 static char *cpu_sub_arch_name
= NULL
;
736 /* CPU feature flags. */
737 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
739 /* If we have selected a cpu we are generating instructions for. */
740 static int cpu_arch_tune_set
= 0;
742 /* Cpu we are generating instructions for. */
743 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
745 /* CPU feature flags of cpu we are generating instructions for. */
746 static i386_cpu_flags cpu_arch_tune_flags
;
748 /* CPU instruction set architecture used. */
749 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
751 /* CPU feature flags of instruction set architecture used. */
752 i386_cpu_flags cpu_arch_isa_flags
;
754 /* If set, conditional jumps are not automatically promoted to handle
755 larger than a byte offset. */
756 static unsigned int no_cond_jump_promotion
= 0;
758 /* Encode SSE instructions with VEX prefix. */
759 static unsigned int sse2avx
;
761 /* Encode scalar AVX instructions with specific vector length. */
768 /* Encode VEX WIG instructions with specific vex.w. */
775 /* Encode scalar EVEX LIG instructions with specific vector length. */
783 /* Encode EVEX WIG instructions with specific evex.w. */
790 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
791 static enum rc_type evexrcig
= rne
;
793 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
794 static symbolS
*GOT_symbol
;
796 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
797 unsigned int x86_dwarf2_return_column
;
799 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
800 int x86_cie_data_alignment
;
802 /* Interface to relax_segment.
803 There are 3 major relax states for 386 jump insns because the
804 different types of jumps add different sizes to frags when we're
805 figuring out what sort of jump to choose to reach a given label.
807 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
808 branches which are handled by md_estimate_size_before_relax() and
809 i386_generic_table_relax_frag(). */
812 #define UNCOND_JUMP 0
814 #define COND_JUMP86 2
815 #define BRANCH_PADDING 3
816 #define BRANCH_PREFIX 4
817 #define FUSED_JCC_PADDING 5
822 #define SMALL16 (SMALL | CODE16)
824 #define BIG16 (BIG | CODE16)
828 #define INLINE __inline__
834 #define ENCODE_RELAX_STATE(type, size) \
835 ((relax_substateT) (((type) << 2) | (size)))
836 #define TYPE_FROM_RELAX_STATE(s) \
838 #define DISP_SIZE_FROM_RELAX_STATE(s) \
839 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
841 /* This table is used by relax_frag to promote short jumps to long
842 ones where necessary. SMALL (short) jumps may be promoted to BIG
843 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
844 don't allow a short jump in a 32 bit code segment to be promoted to
845 a 16 bit offset jump because it's slower (requires data size
846 prefix), and doesn't work, unless the destination is in the bottom
847 64k of the code segment (The top 16 bits of eip are zeroed). */
849 const relax_typeS md_relax_table
[] =
852 1) most positive reach of this state,
853 2) most negative reach of this state,
854 3) how many bytes this mode will have in the variable part of the frag
855 4) which index into the table to try if we can't fit into this one. */
857 /* UNCOND_JUMP states. */
858 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
859 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
860 /* dword jmp adds 4 bytes to frag:
861 0 extra opcode bytes, 4 displacement bytes. */
863 /* word jmp adds 2 byte2 to frag:
864 0 extra opcode bytes, 2 displacement bytes. */
867 /* COND_JUMP states. */
868 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
869 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
870 /* dword conditionals adds 5 bytes to frag:
871 1 extra opcode byte, 4 displacement bytes. */
873 /* word conditionals add 3 bytes to frag:
874 1 extra opcode byte, 2 displacement bytes. */
877 /* COND_JUMP86 states. */
878 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
879 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
880 /* dword conditionals adds 5 bytes to frag:
881 1 extra opcode byte, 4 displacement bytes. */
883 /* word conditionals add 4 bytes to frag:
884 1 displacement byte and a 3 byte long branch insn. */
888 static const arch_entry cpu_arch
[] =
890 /* Do not replace the first two entries - i386_target_format()
891 relies on them being there in this order. */
892 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
893 CPU_GENERIC32_FLAGS
, 0 },
894 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
895 CPU_GENERIC64_FLAGS
, 0 },
896 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
904 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
906 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
908 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
910 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
912 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
913 CPU_PENTIUMPRO_FLAGS
, 0 },
914 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
916 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
918 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
920 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
922 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
923 CPU_NOCONA_FLAGS
, 0 },
924 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
926 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
928 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
929 CPU_CORE2_FLAGS
, 1 },
930 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
931 CPU_CORE2_FLAGS
, 0 },
932 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
933 CPU_COREI7_FLAGS
, 0 },
934 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
936 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
938 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
939 CPU_IAMCU_FLAGS
, 0 },
940 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
942 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
944 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
945 CPU_ATHLON_FLAGS
, 0 },
946 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
948 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
950 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
952 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
953 CPU_AMDFAM10_FLAGS
, 0 },
954 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
955 CPU_BDVER1_FLAGS
, 0 },
956 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
957 CPU_BDVER2_FLAGS
, 0 },
958 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
959 CPU_BDVER3_FLAGS
, 0 },
960 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
961 CPU_BDVER4_FLAGS
, 0 },
962 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
963 CPU_ZNVER1_FLAGS
, 0 },
964 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
965 CPU_ZNVER2_FLAGS
, 0 },
966 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
967 CPU_BTVER1_FLAGS
, 0 },
968 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
969 CPU_BTVER2_FLAGS
, 0 },
970 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
980 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
986 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
991 CPU_SSSE3_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
993 CPU_SSE4_1_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
995 CPU_SSE4_2_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
997 CPU_SSE4_2_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1000 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX2_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512F_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1005 CPU_AVX512CD_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1007 CPU_AVX512ER_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1009 CPU_AVX512PF_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1011 CPU_AVX512DQ_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1013 CPU_AVX512BW_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1015 CPU_AVX512VL_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1019 CPU_VMFUNC_FLAGS
, 0 },
1020 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1022 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1023 CPU_XSAVE_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1025 CPU_XSAVEOPT_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1027 CPU_XSAVEC_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1029 CPU_XSAVES_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1032 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1033 CPU_PCLMUL_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1035 CPU_PCLMUL_FLAGS
, 1 },
1036 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1037 CPU_FSGSBASE_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1039 CPU_RDRND_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1041 CPU_F16C_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1043 CPU_BMI2_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1046 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1047 CPU_FMA4_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1050 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1052 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1053 CPU_MOVBE_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1055 CPU_CX16_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1058 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1059 CPU_LZCNT_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1062 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1064 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1065 CPU_INVPCID_FLAGS
, 0 },
1066 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1067 CPU_CLFLUSH_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1070 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1071 CPU_SYSCALL_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1073 CPU_RDTSCP_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1075 CPU_3DNOW_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1077 CPU_3DNOWA_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1079 CPU_PADLOCK_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1081 CPU_SVME_FLAGS
, 1 },
1082 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1083 CPU_SVME_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1085 CPU_SSE4A_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1088 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1090 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1092 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1094 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1095 CPU_RDSEED_FLAGS
, 0 },
1096 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1097 CPU_PRFCHW_FLAGS
, 0 },
1098 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1099 CPU_SMAP_FLAGS
, 0 },
1100 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1102 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1104 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1105 CPU_CLFLUSHOPT_FLAGS
, 0 },
1106 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1107 CPU_PREFETCHWT1_FLAGS
, 0 },
1108 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1110 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1111 CPU_CLWB_FLAGS
, 0 },
1112 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1113 CPU_AVX512IFMA_FLAGS
, 0 },
1114 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1115 CPU_AVX512VBMI_FLAGS
, 0 },
1116 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1117 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1118 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1119 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1120 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1121 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1122 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1123 CPU_AVX512_VBMI2_FLAGS
, 0 },
1124 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1125 CPU_AVX512_VNNI_FLAGS
, 0 },
1126 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1127 CPU_AVX512_BITALG_FLAGS
, 0 },
1128 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1129 CPU_CLZERO_FLAGS
, 0 },
1130 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1131 CPU_MWAITX_FLAGS
, 0 },
1132 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1133 CPU_OSPKE_FLAGS
, 0 },
1134 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1135 CPU_RDPID_FLAGS
, 0 },
1136 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1137 CPU_PTWRITE_FLAGS
, 0 },
1138 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1140 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1141 CPU_SHSTK_FLAGS
, 0 },
1142 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1143 CPU_GFNI_FLAGS
, 0 },
1144 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1145 CPU_VAES_FLAGS
, 0 },
1146 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1147 CPU_VPCLMULQDQ_FLAGS
, 0 },
1148 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1149 CPU_WBNOINVD_FLAGS
, 0 },
1150 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1151 CPU_PCONFIG_FLAGS
, 0 },
1152 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1153 CPU_WAITPKG_FLAGS
, 0 },
1154 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1155 CPU_CLDEMOTE_FLAGS
, 0 },
1156 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1157 CPU_MOVDIRI_FLAGS
, 0 },
1158 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1159 CPU_MOVDIR64B_FLAGS
, 0 },
1160 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1161 CPU_AVX512_BF16_FLAGS
, 0 },
1162 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1163 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1164 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1165 CPU_ENQCMD_FLAGS
, 0 },
1166 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1167 CPU_RDPRU_FLAGS
, 0 },
1168 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1169 CPU_MCOMMIT_FLAGS
, 0 },
1172 static const noarch_entry cpu_noarch
[] =
1174 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1175 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1176 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1177 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1178 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1179 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1180 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1181 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1182 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1183 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1184 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1185 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1186 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1187 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1188 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1189 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1190 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1191 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1192 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1193 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1194 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1195 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1196 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1197 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1198 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1199 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1200 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1201 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1202 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1203 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1204 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1205 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1206 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1207 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1208 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1209 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1210 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1211 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1215 /* Like s_lcomm_internal in gas/read.c but the alignment string
1216 is allowed to be optional. */
1219 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1226 && *input_line_pointer
== ',')
1228 align
= parse_align (needs_align
- 1);
1230 if (align
== (addressT
) -1)
1245 bss_alloc (symbolP
, size
, align
);
1250 pe_lcomm (int needs_align
)
1252 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1256 const pseudo_typeS md_pseudo_table
[] =
1258 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1259 {"align", s_align_bytes
, 0},
1261 {"align", s_align_ptwo
, 0},
1263 {"arch", set_cpu_arch
, 0},
1267 {"lcomm", pe_lcomm
, 1},
1269 {"ffloat", float_cons
, 'f'},
1270 {"dfloat", float_cons
, 'd'},
1271 {"tfloat", float_cons
, 'x'},
1273 {"slong", signed_cons
, 4},
1274 {"noopt", s_ignore
, 0},
1275 {"optim", s_ignore
, 0},
1276 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1277 {"code16", set_code_flag
, CODE_16BIT
},
1278 {"code32", set_code_flag
, CODE_32BIT
},
1280 {"code64", set_code_flag
, CODE_64BIT
},
1282 {"intel_syntax", set_intel_syntax
, 1},
1283 {"att_syntax", set_intel_syntax
, 0},
1284 {"intel_mnemonic", set_intel_mnemonic
, 1},
1285 {"att_mnemonic", set_intel_mnemonic
, 0},
1286 {"allow_index_reg", set_allow_index_reg
, 1},
1287 {"disallow_index_reg", set_allow_index_reg
, 0},
1288 {"sse_check", set_check
, 0},
1289 {"operand_check", set_check
, 1},
1290 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1291 {"largecomm", handle_large_common
, 0},
1293 {"file", dwarf2_directive_file
, 0},
1294 {"loc", dwarf2_directive_loc
, 0},
1295 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1298 {"secrel32", pe_directive_secrel
, 0},
1303 /* For interface with expression (). */
1304 extern char *input_line_pointer
;
1306 /* Hash table for instruction mnemonic lookup. */
1307 static struct hash_control
*op_hash
;
1309 /* Hash table for register lookup. */
1310 static struct hash_control
*reg_hash
;
1312 /* Various efficient no-op patterns for aligning code labels.
1313 Note: Don't try to assemble the instructions in the comments.
1314 0L and 0w are not legal. */
1315 static const unsigned char f32_1
[] =
1317 static const unsigned char f32_2
[] =
1318 {0x66,0x90}; /* xchg %ax,%ax */
1319 static const unsigned char f32_3
[] =
1320 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1321 static const unsigned char f32_4
[] =
1322 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1323 static const unsigned char f32_6
[] =
1324 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1325 static const unsigned char f32_7
[] =
1326 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1327 static const unsigned char f16_3
[] =
1328 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1329 static const unsigned char f16_4
[] =
1330 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1331 static const unsigned char jump_disp8
[] =
1332 {0xeb}; /* jmp disp8 */
1333 static const unsigned char jump32_disp32
[] =
1334 {0xe9}; /* jmp disp32 */
1335 static const unsigned char jump16_disp32
[] =
1336 {0x66,0xe9}; /* jmp disp32 */
1337 /* 32-bit NOPs patterns. */
1338 static const unsigned char *const f32_patt
[] = {
1339 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1341 /* 16-bit NOPs patterns. */
1342 static const unsigned char *const f16_patt
[] = {
1343 f32_1
, f32_2
, f16_3
, f16_4
1345 /* nopl (%[re]ax) */
1346 static const unsigned char alt_3
[] =
1348 /* nopl 0(%[re]ax) */
1349 static const unsigned char alt_4
[] =
1350 {0x0f,0x1f,0x40,0x00};
1351 /* nopl 0(%[re]ax,%[re]ax,1) */
1352 static const unsigned char alt_5
[] =
1353 {0x0f,0x1f,0x44,0x00,0x00};
1354 /* nopw 0(%[re]ax,%[re]ax,1) */
1355 static const unsigned char alt_6
[] =
1356 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1357 /* nopl 0L(%[re]ax) */
1358 static const unsigned char alt_7
[] =
1359 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1360 /* nopl 0L(%[re]ax,%[re]ax,1) */
1361 static const unsigned char alt_8
[] =
1362 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1363 /* nopw 0L(%[re]ax,%[re]ax,1) */
1364 static const unsigned char alt_9
[] =
1365 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1366 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1367 static const unsigned char alt_10
[] =
1368 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1369 /* data16 nopw %cs:0L(%eax,%eax,1) */
1370 static const unsigned char alt_11
[] =
1371 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1372 /* 32-bit and 64-bit NOPs patterns. */
1373 static const unsigned char *const alt_patt
[] = {
1374 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1375 alt_9
, alt_10
, alt_11
1378 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1379 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1382 i386_output_nops (char *where
, const unsigned char *const *patt
,
1383 int count
, int max_single_nop_size
)
1386 /* Place the longer NOP first. */
1389 const unsigned char *nops
;
1391 if (max_single_nop_size
< 1)
1393 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1394 max_single_nop_size
);
1398 nops
= patt
[max_single_nop_size
- 1];
1400 /* Use the smaller one if the requsted one isn't available. */
1403 max_single_nop_size
--;
1404 nops
= patt
[max_single_nop_size
- 1];
1407 last
= count
% max_single_nop_size
;
1410 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1411 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1415 nops
= patt
[last
- 1];
1418 /* Use the smaller one plus one-byte NOP if the needed one
1421 nops
= patt
[last
- 1];
1422 memcpy (where
+ offset
, nops
, last
);
1423 where
[offset
+ last
] = *patt
[0];
1426 memcpy (where
+ offset
, nops
, last
);
1431 fits_in_imm7 (offsetT num
)
1433 return (num
& 0x7f) == num
;
1437 fits_in_imm31 (offsetT num
)
1439 return (num
& 0x7fffffff) == num
;
1442 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1443 single NOP instruction LIMIT. */
1446 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1448 const unsigned char *const *patt
= NULL
;
1449 int max_single_nop_size
;
1450 /* Maximum number of NOPs before switching to jump over NOPs. */
1451 int max_number_of_nops
;
1453 switch (fragP
->fr_type
)
1458 case rs_machine_dependent
:
1459 /* Allow NOP padding for jumps and calls. */
1460 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1461 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1468 /* We need to decide which NOP sequence to use for 32bit and
1469 64bit. When -mtune= is used:
1471 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1472 PROCESSOR_GENERIC32, f32_patt will be used.
1473 2. For the rest, alt_patt will be used.
1475 When -mtune= isn't used, alt_patt will be used if
1476 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1479 When -march= or .arch is used, we can't use anything beyond
1480 cpu_arch_isa_flags. */
1482 if (flag_code
== CODE_16BIT
)
1485 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1486 /* Limit number of NOPs to 2 in 16-bit mode. */
1487 max_number_of_nops
= 2;
1491 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1493 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1494 switch (cpu_arch_tune
)
1496 case PROCESSOR_UNKNOWN
:
1497 /* We use cpu_arch_isa_flags to check if we SHOULD
1498 optimize with nops. */
1499 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1504 case PROCESSOR_PENTIUM4
:
1505 case PROCESSOR_NOCONA
:
1506 case PROCESSOR_CORE
:
1507 case PROCESSOR_CORE2
:
1508 case PROCESSOR_COREI7
:
1509 case PROCESSOR_L1OM
:
1510 case PROCESSOR_K1OM
:
1511 case PROCESSOR_GENERIC64
:
1513 case PROCESSOR_ATHLON
:
1515 case PROCESSOR_AMDFAM10
:
1517 case PROCESSOR_ZNVER
:
1521 case PROCESSOR_I386
:
1522 case PROCESSOR_I486
:
1523 case PROCESSOR_PENTIUM
:
1524 case PROCESSOR_PENTIUMPRO
:
1525 case PROCESSOR_IAMCU
:
1526 case PROCESSOR_GENERIC32
:
1533 switch (fragP
->tc_frag_data
.tune
)
1535 case PROCESSOR_UNKNOWN
:
1536 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1537 PROCESSOR_UNKNOWN. */
1541 case PROCESSOR_I386
:
1542 case PROCESSOR_I486
:
1543 case PROCESSOR_PENTIUM
:
1544 case PROCESSOR_IAMCU
:
1546 case PROCESSOR_ATHLON
:
1548 case PROCESSOR_AMDFAM10
:
1550 case PROCESSOR_ZNVER
:
1552 case PROCESSOR_GENERIC32
:
1553 /* We use cpu_arch_isa_flags to check if we CAN optimize
1555 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1560 case PROCESSOR_PENTIUMPRO
:
1561 case PROCESSOR_PENTIUM4
:
1562 case PROCESSOR_NOCONA
:
1563 case PROCESSOR_CORE
:
1564 case PROCESSOR_CORE2
:
1565 case PROCESSOR_COREI7
:
1566 case PROCESSOR_L1OM
:
1567 case PROCESSOR_K1OM
:
1568 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1573 case PROCESSOR_GENERIC64
:
1579 if (patt
== f32_patt
)
1581 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1582 /* Limit number of NOPs to 2 for older processors. */
1583 max_number_of_nops
= 2;
1587 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1588 /* Limit number of NOPs to 7 for newer processors. */
1589 max_number_of_nops
= 7;
1594 limit
= max_single_nop_size
;
1596 if (fragP
->fr_type
== rs_fill_nop
)
1598 /* Output NOPs for .nop directive. */
1599 if (limit
> max_single_nop_size
)
1601 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1602 _("invalid single nop size: %d "
1603 "(expect within [0, %d])"),
1604 limit
, max_single_nop_size
);
1608 else if (fragP
->fr_type
!= rs_machine_dependent
)
1609 fragP
->fr_var
= count
;
1611 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1613 /* Generate jump over NOPs. */
1614 offsetT disp
= count
- 2;
1615 if (fits_in_imm7 (disp
))
1617 /* Use "jmp disp8" if possible. */
1619 where
[0] = jump_disp8
[0];
1625 unsigned int size_of_jump
;
1627 if (flag_code
== CODE_16BIT
)
1629 where
[0] = jump16_disp32
[0];
1630 where
[1] = jump16_disp32
[1];
1635 where
[0] = jump32_disp32
[0];
1639 count
-= size_of_jump
+ 4;
1640 if (!fits_in_imm31 (count
))
1642 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1643 _("jump over nop padding out of range"));
1647 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1648 where
+= size_of_jump
+ 4;
1652 /* Generate multiple NOPs. */
1653 i386_output_nops (where
, patt
, count
, limit
);
1657 operand_type_all_zero (const union i386_operand_type
*x
)
1659 switch (ARRAY_SIZE(x
->array
))
1670 return !x
->array
[0];
1677 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1679 switch (ARRAY_SIZE(x
->array
))
1695 x
->bitfield
.class = ClassNone
;
1696 x
->bitfield
.instance
= InstanceNone
;
1700 operand_type_equal (const union i386_operand_type
*x
,
1701 const union i386_operand_type
*y
)
1703 switch (ARRAY_SIZE(x
->array
))
1706 if (x
->array
[2] != y
->array
[2])
1710 if (x
->array
[1] != y
->array
[1])
1714 return x
->array
[0] == y
->array
[0];
1722 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1724 switch (ARRAY_SIZE(x
->array
))
1739 return !x
->array
[0];
1746 cpu_flags_equal (const union i386_cpu_flags
*x
,
1747 const union i386_cpu_flags
*y
)
1749 switch (ARRAY_SIZE(x
->array
))
1752 if (x
->array
[3] != y
->array
[3])
1756 if (x
->array
[2] != y
->array
[2])
1760 if (x
->array
[1] != y
->array
[1])
1764 return x
->array
[0] == y
->array
[0];
1772 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1774 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1775 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1778 static INLINE i386_cpu_flags
1779 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1781 switch (ARRAY_SIZE (x
.array
))
1784 x
.array
[3] &= y
.array
[3];
1787 x
.array
[2] &= y
.array
[2];
1790 x
.array
[1] &= y
.array
[1];
1793 x
.array
[0] &= y
.array
[0];
1801 static INLINE i386_cpu_flags
1802 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1804 switch (ARRAY_SIZE (x
.array
))
1807 x
.array
[3] |= y
.array
[3];
1810 x
.array
[2] |= y
.array
[2];
1813 x
.array
[1] |= y
.array
[1];
1816 x
.array
[0] |= y
.array
[0];
1824 static INLINE i386_cpu_flags
1825 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1827 switch (ARRAY_SIZE (x
.array
))
1830 x
.array
[3] &= ~y
.array
[3];
1833 x
.array
[2] &= ~y
.array
[2];
1836 x
.array
[1] &= ~y
.array
[1];
1839 x
.array
[0] &= ~y
.array
[0];
1847 #define CPU_FLAGS_ARCH_MATCH 0x1
1848 #define CPU_FLAGS_64BIT_MATCH 0x2
1850 #define CPU_FLAGS_PERFECT_MATCH \
1851 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1853 /* Return CPU flags match bits. */
1856 cpu_flags_match (const insn_template
*t
)
1858 i386_cpu_flags x
= t
->cpu_flags
;
1859 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1861 x
.bitfield
.cpu64
= 0;
1862 x
.bitfield
.cpuno64
= 0;
1864 if (cpu_flags_all_zero (&x
))
1866 /* This instruction is available on all archs. */
1867 match
|= CPU_FLAGS_ARCH_MATCH
;
1871 /* This instruction is available only on some archs. */
1872 i386_cpu_flags cpu
= cpu_arch_flags
;
1874 /* AVX512VL is no standalone feature - match it and then strip it. */
1875 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1877 x
.bitfield
.cpuavx512vl
= 0;
1879 cpu
= cpu_flags_and (x
, cpu
);
1880 if (!cpu_flags_all_zero (&cpu
))
1882 if (x
.bitfield
.cpuavx
)
1884 /* We need to check a few extra flags with AVX. */
1885 if (cpu
.bitfield
.cpuavx
1886 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1887 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1888 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1889 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1890 match
|= CPU_FLAGS_ARCH_MATCH
;
1892 else if (x
.bitfield
.cpuavx512f
)
1894 /* We need to check a few extra flags with AVX512F. */
1895 if (cpu
.bitfield
.cpuavx512f
1896 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1897 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1898 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1899 match
|= CPU_FLAGS_ARCH_MATCH
;
1902 match
|= CPU_FLAGS_ARCH_MATCH
;
1908 static INLINE i386_operand_type
1909 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1911 if (x
.bitfield
.class != y
.bitfield
.class)
1912 x
.bitfield
.class = ClassNone
;
1913 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1914 x
.bitfield
.instance
= InstanceNone
;
1916 switch (ARRAY_SIZE (x
.array
))
1919 x
.array
[2] &= y
.array
[2];
1922 x
.array
[1] &= y
.array
[1];
1925 x
.array
[0] &= y
.array
[0];
1933 static INLINE i386_operand_type
1934 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1936 gas_assert (y
.bitfield
.class == ClassNone
);
1937 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1939 switch (ARRAY_SIZE (x
.array
))
1942 x
.array
[2] &= ~y
.array
[2];
1945 x
.array
[1] &= ~y
.array
[1];
1948 x
.array
[0] &= ~y
.array
[0];
1956 static INLINE i386_operand_type
1957 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1959 gas_assert (x
.bitfield
.class == ClassNone
||
1960 y
.bitfield
.class == ClassNone
||
1961 x
.bitfield
.class == y
.bitfield
.class);
1962 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1963 y
.bitfield
.instance
== InstanceNone
||
1964 x
.bitfield
.instance
== y
.bitfield
.instance
);
1966 switch (ARRAY_SIZE (x
.array
))
1969 x
.array
[2] |= y
.array
[2];
1972 x
.array
[1] |= y
.array
[1];
1975 x
.array
[0] |= y
.array
[0];
1983 static INLINE i386_operand_type
1984 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1986 gas_assert (y
.bitfield
.class == ClassNone
);
1987 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1989 switch (ARRAY_SIZE (x
.array
))
1992 x
.array
[2] ^= y
.array
[2];
1995 x
.array
[1] ^= y
.array
[1];
1998 x
.array
[0] ^= y
.array
[0];
2006 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2007 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2008 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2009 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2010 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2011 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2012 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2013 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2014 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2015 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2016 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2017 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2018 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2019 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2020 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2021 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2022 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2033 operand_type_check (i386_operand_type t
, enum operand_type c
)
2038 return t
.bitfield
.class == Reg
;
2041 return (t
.bitfield
.imm8
2045 || t
.bitfield
.imm32s
2046 || t
.bitfield
.imm64
);
2049 return (t
.bitfield
.disp8
2050 || t
.bitfield
.disp16
2051 || t
.bitfield
.disp32
2052 || t
.bitfield
.disp32s
2053 || t
.bitfield
.disp64
);
2056 return (t
.bitfield
.disp8
2057 || t
.bitfield
.disp16
2058 || t
.bitfield
.disp32
2059 || t
.bitfield
.disp32s
2060 || t
.bitfield
.disp64
2061 || t
.bitfield
.baseindex
);
2070 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2071 between operand GIVEN and opeand WANTED for instruction template T. */
2074 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2077 return !((i
.types
[given
].bitfield
.byte
2078 && !t
->operand_types
[wanted
].bitfield
.byte
)
2079 || (i
.types
[given
].bitfield
.word
2080 && !t
->operand_types
[wanted
].bitfield
.word
)
2081 || (i
.types
[given
].bitfield
.dword
2082 && !t
->operand_types
[wanted
].bitfield
.dword
)
2083 || (i
.types
[given
].bitfield
.qword
2084 && !t
->operand_types
[wanted
].bitfield
.qword
)
2085 || (i
.types
[given
].bitfield
.tbyte
2086 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2089 /* Return 1 if there is no conflict in SIMD register between operand
2090 GIVEN and opeand WANTED for instruction template T. */
2093 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2096 return !((i
.types
[given
].bitfield
.xmmword
2097 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2098 || (i
.types
[given
].bitfield
.ymmword
2099 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2100 || (i
.types
[given
].bitfield
.zmmword
2101 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2104 /* Return 1 if there is no conflict in any size between operand GIVEN
2105 and opeand WANTED for instruction template T. */
2108 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2111 return (match_operand_size (t
, wanted
, given
)
2112 && !((i
.types
[given
].bitfield
.unspecified
2114 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2115 || (i
.types
[given
].bitfield
.fword
2116 && !t
->operand_types
[wanted
].bitfield
.fword
)
2117 /* For scalar opcode templates to allow register and memory
2118 operands at the same time, some special casing is needed
2119 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2120 down-conversion vpmov*. */
2121 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2122 && !t
->opcode_modifier
.broadcast
2123 && (t
->operand_types
[wanted
].bitfield
.byte
2124 || t
->operand_types
[wanted
].bitfield
.word
2125 || t
->operand_types
[wanted
].bitfield
.dword
2126 || t
->operand_types
[wanted
].bitfield
.qword
))
2127 ? (i
.types
[given
].bitfield
.xmmword
2128 || i
.types
[given
].bitfield
.ymmword
2129 || i
.types
[given
].bitfield
.zmmword
)
2130 : !match_simd_size(t
, wanted
, given
))));
2133 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2134 operands for instruction template T, and it has MATCH_REVERSE set if there
2135 is no size conflict on any operands for the template with operands reversed
2136 (and the template allows for reversing in the first place). */
2138 #define MATCH_STRAIGHT 1
2139 #define MATCH_REVERSE 2
2141 static INLINE
unsigned int
2142 operand_size_match (const insn_template
*t
)
2144 unsigned int j
, match
= MATCH_STRAIGHT
;
2146 /* Don't check non-absolute jump instructions. */
2147 if (t
->opcode_modifier
.jump
2148 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2151 /* Check memory and accumulator operand size. */
2152 for (j
= 0; j
< i
.operands
; j
++)
2154 if (i
.types
[j
].bitfield
.class != Reg
2155 && i
.types
[j
].bitfield
.class != RegSIMD
2156 && t
->opcode_modifier
.anysize
)
2159 if (t
->operand_types
[j
].bitfield
.class == Reg
2160 && !match_operand_size (t
, j
, j
))
2166 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2167 && !match_simd_size (t
, j
, j
))
2173 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2174 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2180 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2187 if (!t
->opcode_modifier
.d
)
2191 i
.error
= operand_size_mismatch
;
2195 /* Check reverse. */
2196 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2198 for (j
= 0; j
< i
.operands
; j
++)
2200 unsigned int given
= i
.operands
- j
- 1;
2202 if (t
->operand_types
[j
].bitfield
.class == Reg
2203 && !match_operand_size (t
, j
, given
))
2206 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2207 && !match_simd_size (t
, j
, given
))
2210 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2211 && (!match_operand_size (t
, j
, given
)
2212 || !match_simd_size (t
, j
, given
)))
2215 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2219 return match
| MATCH_REVERSE
;
2223 operand_type_match (i386_operand_type overlap
,
2224 i386_operand_type given
)
2226 i386_operand_type temp
= overlap
;
2228 temp
.bitfield
.unspecified
= 0;
2229 temp
.bitfield
.byte
= 0;
2230 temp
.bitfield
.word
= 0;
2231 temp
.bitfield
.dword
= 0;
2232 temp
.bitfield
.fword
= 0;
2233 temp
.bitfield
.qword
= 0;
2234 temp
.bitfield
.tbyte
= 0;
2235 temp
.bitfield
.xmmword
= 0;
2236 temp
.bitfield
.ymmword
= 0;
2237 temp
.bitfield
.zmmword
= 0;
2238 if (operand_type_all_zero (&temp
))
2241 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2245 i
.error
= operand_type_mismatch
;
2249 /* If given types g0 and g1 are registers they must be of the same type
2250 unless the expected operand type register overlap is null.
2251 Some Intel syntax memory operand size checking also happens here. */
2254 operand_type_register_match (i386_operand_type g0
,
2255 i386_operand_type t0
,
2256 i386_operand_type g1
,
2257 i386_operand_type t1
)
2259 if (g0
.bitfield
.class != Reg
2260 && g0
.bitfield
.class != RegSIMD
2261 && (!operand_type_check (g0
, anymem
)
2262 || g0
.bitfield
.unspecified
2263 || (t0
.bitfield
.class != Reg
2264 && t0
.bitfield
.class != RegSIMD
)))
2267 if (g1
.bitfield
.class != Reg
2268 && g1
.bitfield
.class != RegSIMD
2269 && (!operand_type_check (g1
, anymem
)
2270 || g1
.bitfield
.unspecified
2271 || (t1
.bitfield
.class != Reg
2272 && t1
.bitfield
.class != RegSIMD
)))
2275 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2276 && g0
.bitfield
.word
== g1
.bitfield
.word
2277 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2278 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2279 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2280 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2281 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2284 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2285 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2286 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2287 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2288 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2289 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2290 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2293 i
.error
= register_type_mismatch
;
2298 static INLINE
unsigned int
2299 register_number (const reg_entry
*r
)
2301 unsigned int nr
= r
->reg_num
;
2303 if (r
->reg_flags
& RegRex
)
2306 if (r
->reg_flags
& RegVRex
)
2312 static INLINE
unsigned int
2313 mode_from_disp_size (i386_operand_type t
)
2315 if (t
.bitfield
.disp8
)
2317 else if (t
.bitfield
.disp16
2318 || t
.bitfield
.disp32
2319 || t
.bitfield
.disp32s
)
2326 fits_in_signed_byte (addressT num
)
2328 return num
+ 0x80 <= 0xff;
2332 fits_in_unsigned_byte (addressT num
)
2338 fits_in_unsigned_word (addressT num
)
2340 return num
<= 0xffff;
2344 fits_in_signed_word (addressT num
)
2346 return num
+ 0x8000 <= 0xffff;
2350 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2355 return num
+ 0x80000000 <= 0xffffffff;
2357 } /* fits_in_signed_long() */
2360 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2365 return num
<= 0xffffffff;
2367 } /* fits_in_unsigned_long() */
2370 fits_in_disp8 (offsetT num
)
2372 int shift
= i
.memshift
;
2378 mask
= (1 << shift
) - 1;
2380 /* Return 0 if NUM isn't properly aligned. */
2384 /* Check if NUM will fit in 8bit after shift. */
2385 return fits_in_signed_byte (num
>> shift
);
2389 fits_in_imm4 (offsetT num
)
2391 return (num
& 0xf) == num
;
2394 static i386_operand_type
2395 smallest_imm_type (offsetT num
)
2397 i386_operand_type t
;
2399 operand_type_set (&t
, 0);
2400 t
.bitfield
.imm64
= 1;
2402 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2404 /* This code is disabled on the 486 because all the Imm1 forms
2405 in the opcode table are slower on the i486. They're the
2406 versions with the implicitly specified single-position
2407 displacement, which has another syntax if you really want to
2409 t
.bitfield
.imm1
= 1;
2410 t
.bitfield
.imm8
= 1;
2411 t
.bitfield
.imm8s
= 1;
2412 t
.bitfield
.imm16
= 1;
2413 t
.bitfield
.imm32
= 1;
2414 t
.bitfield
.imm32s
= 1;
2416 else if (fits_in_signed_byte (num
))
2418 t
.bitfield
.imm8
= 1;
2419 t
.bitfield
.imm8s
= 1;
2420 t
.bitfield
.imm16
= 1;
2421 t
.bitfield
.imm32
= 1;
2422 t
.bitfield
.imm32s
= 1;
2424 else if (fits_in_unsigned_byte (num
))
2426 t
.bitfield
.imm8
= 1;
2427 t
.bitfield
.imm16
= 1;
2428 t
.bitfield
.imm32
= 1;
2429 t
.bitfield
.imm32s
= 1;
2431 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2433 t
.bitfield
.imm16
= 1;
2434 t
.bitfield
.imm32
= 1;
2435 t
.bitfield
.imm32s
= 1;
2437 else if (fits_in_signed_long (num
))
2439 t
.bitfield
.imm32
= 1;
2440 t
.bitfield
.imm32s
= 1;
2442 else if (fits_in_unsigned_long (num
))
2443 t
.bitfield
.imm32
= 1;
2449 offset_in_range (offsetT val
, int size
)
2455 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2456 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2457 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2459 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2465 /* If BFD64, sign extend val for 32bit address mode. */
2466 if (flag_code
!= CODE_64BIT
2467 || i
.prefix
[ADDR_PREFIX
])
2468 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2469 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2472 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2474 char buf1
[40], buf2
[40];
2476 sprint_value (buf1
, val
);
2477 sprint_value (buf2
, val
& mask
);
2478 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2493 a. PREFIX_EXIST if attempting to add a prefix where one from the
2494 same class already exists.
2495 b. PREFIX_LOCK if lock prefix is added.
2496 c. PREFIX_REP if rep/repne prefix is added.
2497 d. PREFIX_DS if ds prefix is added.
2498 e. PREFIX_OTHER if other prefix is added.
2501 static enum PREFIX_GROUP
2502 add_prefix (unsigned int prefix
)
2504 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2507 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2508 && flag_code
== CODE_64BIT
)
2510 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2511 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2512 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2513 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2524 case DS_PREFIX_OPCODE
:
2527 case CS_PREFIX_OPCODE
:
2528 case ES_PREFIX_OPCODE
:
2529 case FS_PREFIX_OPCODE
:
2530 case GS_PREFIX_OPCODE
:
2531 case SS_PREFIX_OPCODE
:
2535 case REPNE_PREFIX_OPCODE
:
2536 case REPE_PREFIX_OPCODE
:
2541 case LOCK_PREFIX_OPCODE
:
2550 case ADDR_PREFIX_OPCODE
:
2554 case DATA_PREFIX_OPCODE
:
2558 if (i
.prefix
[q
] != 0)
2566 i
.prefix
[q
] |= prefix
;
2569 as_bad (_("same type of prefix used twice"));
2575 update_code_flag (int value
, int check
)
2577 PRINTF_LIKE ((*as_error
));
2579 flag_code
= (enum flag_code
) value
;
2580 if (flag_code
== CODE_64BIT
)
2582 cpu_arch_flags
.bitfield
.cpu64
= 1;
2583 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2587 cpu_arch_flags
.bitfield
.cpu64
= 0;
2588 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2590 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2593 as_error
= as_fatal
;
2596 (*as_error
) (_("64bit mode not supported on `%s'."),
2597 cpu_arch_name
? cpu_arch_name
: default_arch
);
2599 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2602 as_error
= as_fatal
;
2605 (*as_error
) (_("32bit mode not supported on `%s'."),
2606 cpu_arch_name
? cpu_arch_name
: default_arch
);
2608 stackop_size
= '\0';
2612 set_code_flag (int value
)
2614 update_code_flag (value
, 0);
2618 set_16bit_gcc_code_flag (int new_code_flag
)
2620 flag_code
= (enum flag_code
) new_code_flag
;
2621 if (flag_code
!= CODE_16BIT
)
2623 cpu_arch_flags
.bitfield
.cpu64
= 0;
2624 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2625 stackop_size
= LONG_MNEM_SUFFIX
;
2629 set_intel_syntax (int syntax_flag
)
2631 /* Find out if register prefixing is specified. */
2632 int ask_naked_reg
= 0;
2635 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2638 int e
= get_symbol_name (&string
);
2640 if (strcmp (string
, "prefix") == 0)
2642 else if (strcmp (string
, "noprefix") == 0)
2645 as_bad (_("bad argument to syntax directive."));
2646 (void) restore_line_pointer (e
);
2648 demand_empty_rest_of_line ();
2650 intel_syntax
= syntax_flag
;
2652 if (ask_naked_reg
== 0)
2653 allow_naked_reg
= (intel_syntax
2654 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2656 allow_naked_reg
= (ask_naked_reg
< 0);
2658 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2660 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2661 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2662 register_prefix
= allow_naked_reg
? "" : "%";
2666 set_intel_mnemonic (int mnemonic_flag
)
2668 intel_mnemonic
= mnemonic_flag
;
2672 set_allow_index_reg (int flag
)
2674 allow_index_reg
= flag
;
2678 set_check (int what
)
2680 enum check_kind
*kind
;
2685 kind
= &operand_check
;
2696 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2699 int e
= get_symbol_name (&string
);
2701 if (strcmp (string
, "none") == 0)
2703 else if (strcmp (string
, "warning") == 0)
2704 *kind
= check_warning
;
2705 else if (strcmp (string
, "error") == 0)
2706 *kind
= check_error
;
2708 as_bad (_("bad argument to %s_check directive."), str
);
2709 (void) restore_line_pointer (e
);
2712 as_bad (_("missing argument for %s_check directive"), str
);
2714 demand_empty_rest_of_line ();
2718 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2719 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2721 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2722 static const char *arch
;
2724 /* Intel LIOM is only supported on ELF. */
2730 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2731 use default_arch. */
2732 arch
= cpu_arch_name
;
2734 arch
= default_arch
;
2737 /* If we are targeting Intel MCU, we must enable it. */
2738 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2739 || new_flag
.bitfield
.cpuiamcu
)
2742 /* If we are targeting Intel L1OM, we must enable it. */
2743 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2744 || new_flag
.bitfield
.cpul1om
)
2747 /* If we are targeting Intel K1OM, we must enable it. */
2748 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2749 || new_flag
.bitfield
.cpuk1om
)
2752 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2757 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2761 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2764 int e
= get_symbol_name (&string
);
2766 i386_cpu_flags flags
;
2768 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2770 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2772 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2776 cpu_arch_name
= cpu_arch
[j
].name
;
2777 cpu_sub_arch_name
= NULL
;
2778 cpu_arch_flags
= cpu_arch
[j
].flags
;
2779 if (flag_code
== CODE_64BIT
)
2781 cpu_arch_flags
.bitfield
.cpu64
= 1;
2782 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2786 cpu_arch_flags
.bitfield
.cpu64
= 0;
2787 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2789 cpu_arch_isa
= cpu_arch
[j
].type
;
2790 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2791 if (!cpu_arch_tune_set
)
2793 cpu_arch_tune
= cpu_arch_isa
;
2794 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2799 flags
= cpu_flags_or (cpu_arch_flags
,
2802 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2804 if (cpu_sub_arch_name
)
2806 char *name
= cpu_sub_arch_name
;
2807 cpu_sub_arch_name
= concat (name
,
2809 (const char *) NULL
);
2813 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2814 cpu_arch_flags
= flags
;
2815 cpu_arch_isa_flags
= flags
;
2819 = cpu_flags_or (cpu_arch_isa_flags
,
2821 (void) restore_line_pointer (e
);
2822 demand_empty_rest_of_line ();
2827 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2829 /* Disable an ISA extension. */
2830 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2831 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2833 flags
= cpu_flags_and_not (cpu_arch_flags
,
2834 cpu_noarch
[j
].flags
);
2835 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2837 if (cpu_sub_arch_name
)
2839 char *name
= cpu_sub_arch_name
;
2840 cpu_sub_arch_name
= concat (name
, string
,
2841 (const char *) NULL
);
2845 cpu_sub_arch_name
= xstrdup (string
);
2846 cpu_arch_flags
= flags
;
2847 cpu_arch_isa_flags
= flags
;
2849 (void) restore_line_pointer (e
);
2850 demand_empty_rest_of_line ();
2854 j
= ARRAY_SIZE (cpu_arch
);
2857 if (j
>= ARRAY_SIZE (cpu_arch
))
2858 as_bad (_("no such architecture: `%s'"), string
);
2860 *input_line_pointer
= e
;
2863 as_bad (_("missing cpu architecture"));
2865 no_cond_jump_promotion
= 0;
2866 if (*input_line_pointer
== ','
2867 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2872 ++input_line_pointer
;
2873 e
= get_symbol_name (&string
);
2875 if (strcmp (string
, "nojumps") == 0)
2876 no_cond_jump_promotion
= 1;
2877 else if (strcmp (string
, "jumps") == 0)
2880 as_bad (_("no such architecture modifier: `%s'"), string
);
2882 (void) restore_line_pointer (e
);
2885 demand_empty_rest_of_line ();
2888 enum bfd_architecture
2891 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2893 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2894 || flag_code
!= CODE_64BIT
)
2895 as_fatal (_("Intel L1OM is 64bit ELF only"));
2896 return bfd_arch_l1om
;
2898 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2900 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2901 || flag_code
!= CODE_64BIT
)
2902 as_fatal (_("Intel K1OM is 64bit ELF only"));
2903 return bfd_arch_k1om
;
2905 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2907 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2908 || flag_code
== CODE_64BIT
)
2909 as_fatal (_("Intel MCU is 32bit ELF only"));
2910 return bfd_arch_iamcu
;
2913 return bfd_arch_i386
;
2919 if (!strncmp (default_arch
, "x86_64", 6))
2921 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2923 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2924 || default_arch
[6] != '\0')
2925 as_fatal (_("Intel L1OM is 64bit ELF only"));
2926 return bfd_mach_l1om
;
2928 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2930 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2931 || default_arch
[6] != '\0')
2932 as_fatal (_("Intel K1OM is 64bit ELF only"));
2933 return bfd_mach_k1om
;
2935 else if (default_arch
[6] == '\0')
2936 return bfd_mach_x86_64
;
2938 return bfd_mach_x64_32
;
2940 else if (!strcmp (default_arch
, "i386")
2941 || !strcmp (default_arch
, "iamcu"))
2943 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2945 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2946 as_fatal (_("Intel MCU is 32bit ELF only"));
2947 return bfd_mach_i386_iamcu
;
2950 return bfd_mach_i386_i386
;
2953 as_fatal (_("unknown architecture"));
2959 const char *hash_err
;
2961 /* Support pseudo prefixes like {disp32}. */
2962 lex_type
['{'] = LEX_BEGIN_NAME
;
2964 /* Initialize op_hash hash table. */
2965 op_hash
= hash_new ();
2968 const insn_template
*optab
;
2969 templates
*core_optab
;
2971 /* Setup for loop. */
2973 core_optab
= XNEW (templates
);
2974 core_optab
->start
= optab
;
2979 if (optab
->name
== NULL
2980 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2982 /* different name --> ship out current template list;
2983 add to hash table; & begin anew. */
2984 core_optab
->end
= optab
;
2985 hash_err
= hash_insert (op_hash
,
2987 (void *) core_optab
);
2990 as_fatal (_("can't hash %s: %s"),
2994 if (optab
->name
== NULL
)
2996 core_optab
= XNEW (templates
);
2997 core_optab
->start
= optab
;
3002 /* Initialize reg_hash hash table. */
3003 reg_hash
= hash_new ();
3005 const reg_entry
*regtab
;
3006 unsigned int regtab_size
= i386_regtab_size
;
3008 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3010 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3012 as_fatal (_("can't hash %s: %s"),
3018 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3023 for (c
= 0; c
< 256; c
++)
3028 mnemonic_chars
[c
] = c
;
3029 register_chars
[c
] = c
;
3030 operand_chars
[c
] = c
;
3032 else if (ISLOWER (c
))
3034 mnemonic_chars
[c
] = c
;
3035 register_chars
[c
] = c
;
3036 operand_chars
[c
] = c
;
3038 else if (ISUPPER (c
))
3040 mnemonic_chars
[c
] = TOLOWER (c
);
3041 register_chars
[c
] = mnemonic_chars
[c
];
3042 operand_chars
[c
] = c
;
3044 else if (c
== '{' || c
== '}')
3046 mnemonic_chars
[c
] = c
;
3047 operand_chars
[c
] = c
;
3050 if (ISALPHA (c
) || ISDIGIT (c
))
3051 identifier_chars
[c
] = c
;
3054 identifier_chars
[c
] = c
;
3055 operand_chars
[c
] = c
;
3060 identifier_chars
['@'] = '@';
3063 identifier_chars
['?'] = '?';
3064 operand_chars
['?'] = '?';
3066 digit_chars
['-'] = '-';
3067 mnemonic_chars
['_'] = '_';
3068 mnemonic_chars
['-'] = '-';
3069 mnemonic_chars
['.'] = '.';
3070 identifier_chars
['_'] = '_';
3071 identifier_chars
['.'] = '.';
3073 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3074 operand_chars
[(unsigned char) *p
] = *p
;
3077 if (flag_code
== CODE_64BIT
)
3079 #if defined (OBJ_COFF) && defined (TE_PE)
3080 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3083 x86_dwarf2_return_column
= 16;
3085 x86_cie_data_alignment
= -8;
3089 x86_dwarf2_return_column
= 8;
3090 x86_cie_data_alignment
= -4;
3093 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3094 can be turned into BRANCH_PREFIX frag. */
3095 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3100 i386_print_statistics (FILE *file
)
3102 hash_print_statistics (file
, "i386 opcode", op_hash
);
3103 hash_print_statistics (file
, "i386 register", reg_hash
);
3108 /* Debugging routines for md_assemble. */
3109 static void pte (insn_template
*);
3110 static void pt (i386_operand_type
);
3111 static void pe (expressionS
*);
3112 static void ps (symbolS
*);
3115 pi (const char *line
, i386_insn
*x
)
3119 fprintf (stdout
, "%s: template ", line
);
3121 fprintf (stdout
, " address: base %s index %s scale %x\n",
3122 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3123 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3124 x
->log2_scale_factor
);
3125 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3126 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3127 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3128 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3129 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3130 (x
->rex
& REX_W
) != 0,
3131 (x
->rex
& REX_R
) != 0,
3132 (x
->rex
& REX_X
) != 0,
3133 (x
->rex
& REX_B
) != 0);
3134 for (j
= 0; j
< x
->operands
; j
++)
3136 fprintf (stdout
, " #%d: ", j
+ 1);
3138 fprintf (stdout
, "\n");
3139 if (x
->types
[j
].bitfield
.class == Reg
3140 || x
->types
[j
].bitfield
.class == RegMMX
3141 || x
->types
[j
].bitfield
.class == RegSIMD
3142 || x
->types
[j
].bitfield
.class == SReg
3143 || x
->types
[j
].bitfield
.class == RegCR
3144 || x
->types
[j
].bitfield
.class == RegDR
3145 || x
->types
[j
].bitfield
.class == RegTR
)
3146 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3147 if (operand_type_check (x
->types
[j
], imm
))
3149 if (operand_type_check (x
->types
[j
], disp
))
3150 pe (x
->op
[j
].disps
);
3155 pte (insn_template
*t
)
3158 fprintf (stdout
, " %d operands ", t
->operands
);
3159 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3160 if (t
->extension_opcode
!= None
)
3161 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3162 if (t
->opcode_modifier
.d
)
3163 fprintf (stdout
, "D");
3164 if (t
->opcode_modifier
.w
)
3165 fprintf (stdout
, "W");
3166 fprintf (stdout
, "\n");
3167 for (j
= 0; j
< t
->operands
; j
++)
3169 fprintf (stdout
, " #%d type ", j
+ 1);
3170 pt (t
->operand_types
[j
]);
3171 fprintf (stdout
, "\n");
3178 fprintf (stdout
, " operation %d\n", e
->X_op
);
3179 fprintf (stdout
, " add_number %ld (%lx)\n",
3180 (long) e
->X_add_number
, (long) e
->X_add_number
);
3181 if (e
->X_add_symbol
)
3183 fprintf (stdout
, " add_symbol ");
3184 ps (e
->X_add_symbol
);
3185 fprintf (stdout
, "\n");
3189 fprintf (stdout
, " op_symbol ");
3190 ps (e
->X_op_symbol
);
3191 fprintf (stdout
, "\n");
3198 fprintf (stdout
, "%s type %s%s",
3200 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3201 segment_name (S_GET_SEGMENT (s
)));
3204 static struct type_name
3206 i386_operand_type mask
;
3209 const type_names
[] =
3211 { OPERAND_TYPE_REG8
, "r8" },
3212 { OPERAND_TYPE_REG16
, "r16" },
3213 { OPERAND_TYPE_REG32
, "r32" },
3214 { OPERAND_TYPE_REG64
, "r64" },
3215 { OPERAND_TYPE_ACC8
, "acc8" },
3216 { OPERAND_TYPE_ACC16
, "acc16" },
3217 { OPERAND_TYPE_ACC32
, "acc32" },
3218 { OPERAND_TYPE_ACC64
, "acc64" },
3219 { OPERAND_TYPE_IMM8
, "i8" },
3220 { OPERAND_TYPE_IMM8
, "i8s" },
3221 { OPERAND_TYPE_IMM16
, "i16" },
3222 { OPERAND_TYPE_IMM32
, "i32" },
3223 { OPERAND_TYPE_IMM32S
, "i32s" },
3224 { OPERAND_TYPE_IMM64
, "i64" },
3225 { OPERAND_TYPE_IMM1
, "i1" },
3226 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3227 { OPERAND_TYPE_DISP8
, "d8" },
3228 { OPERAND_TYPE_DISP16
, "d16" },
3229 { OPERAND_TYPE_DISP32
, "d32" },
3230 { OPERAND_TYPE_DISP32S
, "d32s" },
3231 { OPERAND_TYPE_DISP64
, "d64" },
3232 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3233 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3234 { OPERAND_TYPE_CONTROL
, "control reg" },
3235 { OPERAND_TYPE_TEST
, "test reg" },
3236 { OPERAND_TYPE_DEBUG
, "debug reg" },
3237 { OPERAND_TYPE_FLOATREG
, "FReg" },
3238 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3239 { OPERAND_TYPE_SREG
, "SReg" },
3240 { OPERAND_TYPE_REGMMX
, "rMMX" },
3241 { OPERAND_TYPE_REGXMM
, "rXMM" },
3242 { OPERAND_TYPE_REGYMM
, "rYMM" },
3243 { OPERAND_TYPE_REGZMM
, "rZMM" },
3244 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3248 pt (i386_operand_type t
)
3251 i386_operand_type a
;
3253 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3255 a
= operand_type_and (t
, type_names
[j
].mask
);
3256 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3257 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3262 #endif /* DEBUG386 */
3264 static bfd_reloc_code_real_type
3265 reloc (unsigned int size
,
3268 bfd_reloc_code_real_type other
)
3270 if (other
!= NO_RELOC
)
3272 reloc_howto_type
*rel
;
3277 case BFD_RELOC_X86_64_GOT32
:
3278 return BFD_RELOC_X86_64_GOT64
;
3280 case BFD_RELOC_X86_64_GOTPLT64
:
3281 return BFD_RELOC_X86_64_GOTPLT64
;
3283 case BFD_RELOC_X86_64_PLTOFF64
:
3284 return BFD_RELOC_X86_64_PLTOFF64
;
3286 case BFD_RELOC_X86_64_GOTPC32
:
3287 other
= BFD_RELOC_X86_64_GOTPC64
;
3289 case BFD_RELOC_X86_64_GOTPCREL
:
3290 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3292 case BFD_RELOC_X86_64_TPOFF32
:
3293 other
= BFD_RELOC_X86_64_TPOFF64
;
3295 case BFD_RELOC_X86_64_DTPOFF32
:
3296 other
= BFD_RELOC_X86_64_DTPOFF64
;
3302 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3303 if (other
== BFD_RELOC_SIZE32
)
3306 other
= BFD_RELOC_SIZE64
;
3309 as_bad (_("there are no pc-relative size relocations"));
3315 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3316 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3319 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3321 as_bad (_("unknown relocation (%u)"), other
);
3322 else if (size
!= bfd_get_reloc_size (rel
))
3323 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3324 bfd_get_reloc_size (rel
),
3326 else if (pcrel
&& !rel
->pc_relative
)
3327 as_bad (_("non-pc-relative relocation for pc-relative field"));
3328 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3330 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3332 as_bad (_("relocated field and relocation type differ in signedness"));
3341 as_bad (_("there are no unsigned pc-relative relocations"));
3344 case 1: return BFD_RELOC_8_PCREL
;
3345 case 2: return BFD_RELOC_16_PCREL
;
3346 case 4: return BFD_RELOC_32_PCREL
;
3347 case 8: return BFD_RELOC_64_PCREL
;
3349 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3356 case 4: return BFD_RELOC_X86_64_32S
;
3361 case 1: return BFD_RELOC_8
;
3362 case 2: return BFD_RELOC_16
;
3363 case 4: return BFD_RELOC_32
;
3364 case 8: return BFD_RELOC_64
;
3366 as_bad (_("cannot do %s %u byte relocation"),
3367 sign
> 0 ? "signed" : "unsigned", size
);
3373 /* Here we decide which fixups can be adjusted to make them relative to
3374 the beginning of the section instead of the symbol. Basically we need
3375 to make sure that the dynamic relocations are done correctly, so in
3376 some cases we force the original symbol to be used. */
3379 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3381 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3385 /* Don't adjust pc-relative references to merge sections in 64-bit
3387 if (use_rela_relocations
3388 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3392 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3393 and changed later by validate_fix. */
3394 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3395 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3398 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3399 for size relocations. */
3400 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3401 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3402 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3403 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3404 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3405 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3406 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3407 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3408 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3409 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3410 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3411 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3412 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3413 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3414 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3415 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3416 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3417 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3418 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3419 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3420 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3421 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3422 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3423 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3424 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3425 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3426 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3427 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3428 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3429 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3430 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3431 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3432 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3439 intel_float_operand (const char *mnemonic
)
3441 /* Note that the value returned is meaningful only for opcodes with (memory)
3442 operands, hence the code here is free to improperly handle opcodes that
3443 have no operands (for better performance and smaller code). */
3445 if (mnemonic
[0] != 'f')
3446 return 0; /* non-math */
3448 switch (mnemonic
[1])
3450 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3451 the fs segment override prefix not currently handled because no
3452 call path can make opcodes without operands get here */
3454 return 2 /* integer op */;
3456 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3457 return 3; /* fldcw/fldenv */
3460 if (mnemonic
[2] != 'o' /* fnop */)
3461 return 3; /* non-waiting control op */
3464 if (mnemonic
[2] == 's')
3465 return 3; /* frstor/frstpm */
3468 if (mnemonic
[2] == 'a')
3469 return 3; /* fsave */
3470 if (mnemonic
[2] == 't')
3472 switch (mnemonic
[3])
3474 case 'c': /* fstcw */
3475 case 'd': /* fstdw */
3476 case 'e': /* fstenv */
3477 case 's': /* fsts[gw] */
3483 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3484 return 0; /* fxsave/fxrstor are not really math ops */
3491 /* Build the VEX prefix. */
3494 build_vex_prefix (const insn_template
*t
)
3496 unsigned int register_specifier
;
3497 unsigned int implied_prefix
;
3498 unsigned int vector_length
;
3501 /* Check register specifier. */
3502 if (i
.vex
.register_specifier
)
3504 register_specifier
=
3505 ~register_number (i
.vex
.register_specifier
) & 0xf;
3506 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3509 register_specifier
= 0xf;
3511 /* Use 2-byte VEX prefix by swapping destination and source operand
3512 if there are more than 1 register operand. */
3513 if (i
.reg_operands
> 1
3514 && i
.vec_encoding
!= vex_encoding_vex3
3515 && i
.dir_encoding
== dir_encoding_default
3516 && i
.operands
== i
.reg_operands
3517 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3518 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3519 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3522 unsigned int xchg
= i
.operands
- 1;
3523 union i386_op temp_op
;
3524 i386_operand_type temp_type
;
3526 temp_type
= i
.types
[xchg
];
3527 i
.types
[xchg
] = i
.types
[0];
3528 i
.types
[0] = temp_type
;
3529 temp_op
= i
.op
[xchg
];
3530 i
.op
[xchg
] = i
.op
[0];
3533 gas_assert (i
.rm
.mode
== 3);
3537 i
.rm
.regmem
= i
.rm
.reg
;
3540 if (i
.tm
.opcode_modifier
.d
)
3541 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3542 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3543 else /* Use the next insn. */
3547 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3548 are no memory operands and at least 3 register ones. */
3549 if (i
.reg_operands
>= 3
3550 && i
.vec_encoding
!= vex_encoding_vex3
3551 && i
.reg_operands
== i
.operands
- i
.imm_operands
3552 && i
.tm
.opcode_modifier
.vex
3553 && i
.tm
.opcode_modifier
.commutative
3554 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3556 && i
.vex
.register_specifier
3557 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3559 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3560 union i386_op temp_op
;
3561 i386_operand_type temp_type
;
3563 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3564 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3565 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3566 &i
.types
[i
.operands
- 3]));
3567 gas_assert (i
.rm
.mode
== 3);
3569 temp_type
= i
.types
[xchg
];
3570 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3571 i
.types
[xchg
+ 1] = temp_type
;
3572 temp_op
= i
.op
[xchg
];
3573 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3574 i
.op
[xchg
+ 1] = temp_op
;
3577 xchg
= i
.rm
.regmem
| 8;
3578 i
.rm
.regmem
= ~register_specifier
& 0xf;
3579 gas_assert (!(i
.rm
.regmem
& 8));
3580 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3581 register_specifier
= ~xchg
& 0xf;
3584 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3585 vector_length
= avxscalar
;
3586 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3592 /* Determine vector length from the last multi-length vector
3595 for (op
= t
->operands
; op
--;)
3596 if (t
->operand_types
[op
].bitfield
.xmmword
3597 && t
->operand_types
[op
].bitfield
.ymmword
3598 && i
.types
[op
].bitfield
.ymmword
)
3605 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3610 case DATA_PREFIX_OPCODE
:
3613 case REPE_PREFIX_OPCODE
:
3616 case REPNE_PREFIX_OPCODE
:
3623 /* Check the REX.W bit and VEXW. */
3624 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3625 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3626 else if (i
.tm
.opcode_modifier
.vexw
)
3627 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3629 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3631 /* Use 2-byte VEX prefix if possible. */
3633 && i
.vec_encoding
!= vex_encoding_vex3
3634 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3635 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3637 /* 2-byte VEX prefix. */
3641 i
.vex
.bytes
[0] = 0xc5;
3643 /* Check the REX.R bit. */
3644 r
= (i
.rex
& REX_R
) ? 0 : 1;
3645 i
.vex
.bytes
[1] = (r
<< 7
3646 | register_specifier
<< 3
3647 | vector_length
<< 2
3652 /* 3-byte VEX prefix. */
3657 switch (i
.tm
.opcode_modifier
.vexopcode
)
3661 i
.vex
.bytes
[0] = 0xc4;
3665 i
.vex
.bytes
[0] = 0xc4;
3669 i
.vex
.bytes
[0] = 0xc4;
3673 i
.vex
.bytes
[0] = 0x8f;
3677 i
.vex
.bytes
[0] = 0x8f;
3681 i
.vex
.bytes
[0] = 0x8f;
3687 /* The high 3 bits of the second VEX byte are 1's compliment
3688 of RXB bits from REX. */
3689 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3691 i
.vex
.bytes
[2] = (w
<< 7
3692 | register_specifier
<< 3
3693 | vector_length
<< 2
3698 static INLINE bfd_boolean
3699 is_evex_encoding (const insn_template
*t
)
3701 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3702 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3703 || t
->opcode_modifier
.sae
;
3706 static INLINE bfd_boolean
3707 is_any_vex_encoding (const insn_template
*t
)
3709 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3710 || is_evex_encoding (t
);
3713 /* Build the EVEX prefix. */
3716 build_evex_prefix (void)
3718 unsigned int register_specifier
;
3719 unsigned int implied_prefix
;
3721 rex_byte vrex_used
= 0;
3723 /* Check register specifier. */
3724 if (i
.vex
.register_specifier
)
3726 gas_assert ((i
.vrex
& REX_X
) == 0);
3728 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3729 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3730 register_specifier
+= 8;
3731 /* The upper 16 registers are encoded in the fourth byte of the
3733 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3734 i
.vex
.bytes
[3] = 0x8;
3735 register_specifier
= ~register_specifier
& 0xf;
3739 register_specifier
= 0xf;
3741 /* Encode upper 16 vector index register in the fourth byte of
3743 if (!(i
.vrex
& REX_X
))
3744 i
.vex
.bytes
[3] = 0x8;
3749 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3754 case DATA_PREFIX_OPCODE
:
3757 case REPE_PREFIX_OPCODE
:
3760 case REPNE_PREFIX_OPCODE
:
3767 /* 4 byte EVEX prefix. */
3769 i
.vex
.bytes
[0] = 0x62;
3772 switch (i
.tm
.opcode_modifier
.vexopcode
)
3788 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3790 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3792 /* The fifth bit of the second EVEX byte is 1's compliment of the
3793 REX_R bit in VREX. */
3794 if (!(i
.vrex
& REX_R
))
3795 i
.vex
.bytes
[1] |= 0x10;
3799 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3801 /* When all operands are registers, the REX_X bit in REX is not
3802 used. We reuse it to encode the upper 16 registers, which is
3803 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3804 as 1's compliment. */
3805 if ((i
.vrex
& REX_B
))
3808 i
.vex
.bytes
[1] &= ~0x40;
3812 /* EVEX instructions shouldn't need the REX prefix. */
3813 i
.vrex
&= ~vrex_used
;
3814 gas_assert (i
.vrex
== 0);
3816 /* Check the REX.W bit and VEXW. */
3817 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3818 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3819 else if (i
.tm
.opcode_modifier
.vexw
)
3820 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3822 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3824 /* Encode the U bit. */
3825 implied_prefix
|= 0x4;
3827 /* The third byte of the EVEX prefix. */
3828 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3830 /* The fourth byte of the EVEX prefix. */
3831 /* The zeroing-masking bit. */
3832 if (i
.mask
&& i
.mask
->zeroing
)
3833 i
.vex
.bytes
[3] |= 0x80;
3835 /* Don't always set the broadcast bit if there is no RC. */
3838 /* Encode the vector length. */
3839 unsigned int vec_length
;
3841 if (!i
.tm
.opcode_modifier
.evex
3842 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3846 /* Determine vector length from the last multi-length vector
3849 for (op
= i
.operands
; op
--;)
3850 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3851 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3852 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3854 if (i
.types
[op
].bitfield
.zmmword
)
3856 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3859 else if (i
.types
[op
].bitfield
.ymmword
)
3861 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3864 else if (i
.types
[op
].bitfield
.xmmword
)
3866 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3869 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3871 switch (i
.broadcast
->bytes
)
3874 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3877 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3880 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3889 if (op
>= MAX_OPERANDS
)
3893 switch (i
.tm
.opcode_modifier
.evex
)
3895 case EVEXLIG
: /* LL' is ignored */
3896 vec_length
= evexlig
<< 5;
3899 vec_length
= 0 << 5;
3902 vec_length
= 1 << 5;
3905 vec_length
= 2 << 5;
3911 i
.vex
.bytes
[3] |= vec_length
;
3912 /* Encode the broadcast bit. */
3914 i
.vex
.bytes
[3] |= 0x10;
3918 if (i
.rounding
->type
!= saeonly
)
3919 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3921 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3924 if (i
.mask
&& i
.mask
->mask
)
3925 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3929 process_immext (void)
3933 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3934 which is coded in the same place as an 8-bit immediate field
3935 would be. Here we fake an 8-bit immediate operand from the
3936 opcode suffix stored in tm.extension_opcode.
3938 AVX instructions also use this encoding, for some of
3939 3 argument instructions. */
3941 gas_assert (i
.imm_operands
<= 1
3943 || (is_any_vex_encoding (&i
.tm
)
3944 && i
.operands
<= 4)));
3946 exp
= &im_expressions
[i
.imm_operands
++];
3947 i
.op
[i
.operands
].imms
= exp
;
3948 i
.types
[i
.operands
] = imm8
;
3950 exp
->X_op
= O_constant
;
3951 exp
->X_add_number
= i
.tm
.extension_opcode
;
3952 i
.tm
.extension_opcode
= None
;
3959 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3964 as_bad (_("invalid instruction `%s' after `%s'"),
3965 i
.tm
.name
, i
.hle_prefix
);
3968 if (i
.prefix
[LOCK_PREFIX
])
3970 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3974 case HLEPrefixRelease
:
3975 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3977 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3981 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3983 as_bad (_("memory destination needed for instruction `%s'"
3984 " after `xrelease'"), i
.tm
.name
);
3991 /* Try the shortest encoding by shortening operand size. */
3994 optimize_encoding (void)
3998 if (optimize_for_space
3999 && !is_any_vex_encoding (&i
.tm
)
4000 && i
.reg_operands
== 1
4001 && i
.imm_operands
== 1
4002 && !i
.types
[1].bitfield
.byte
4003 && i
.op
[0].imms
->X_op
== O_constant
4004 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4005 && (i
.tm
.base_opcode
== 0xa8
4006 || (i
.tm
.base_opcode
== 0xf6
4007 && i
.tm
.extension_opcode
== 0x0)))
4010 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4012 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4013 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4015 i
.types
[1].bitfield
.byte
= 1;
4016 /* Ignore the suffix. */
4018 /* Convert to byte registers. */
4019 if (i
.types
[1].bitfield
.word
)
4021 else if (i
.types
[1].bitfield
.dword
)
4025 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4030 else if (flag_code
== CODE_64BIT
4031 && !is_any_vex_encoding (&i
.tm
)
4032 && ((i
.types
[1].bitfield
.qword
4033 && i
.reg_operands
== 1
4034 && i
.imm_operands
== 1
4035 && i
.op
[0].imms
->X_op
== O_constant
4036 && ((i
.tm
.base_opcode
== 0xb8
4037 && i
.tm
.extension_opcode
== None
4038 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4039 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4040 && ((i
.tm
.base_opcode
== 0x24
4041 || i
.tm
.base_opcode
== 0xa8)
4042 || (i
.tm
.base_opcode
== 0x80
4043 && i
.tm
.extension_opcode
== 0x4)
4044 || ((i
.tm
.base_opcode
== 0xf6
4045 || (i
.tm
.base_opcode
| 1) == 0xc7)
4046 && i
.tm
.extension_opcode
== 0x0)))
4047 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4048 && i
.tm
.base_opcode
== 0x83
4049 && i
.tm
.extension_opcode
== 0x4)))
4050 || (i
.types
[0].bitfield
.qword
4051 && ((i
.reg_operands
== 2
4052 && i
.op
[0].regs
== i
.op
[1].regs
4053 && (i
.tm
.base_opcode
== 0x30
4054 || i
.tm
.base_opcode
== 0x28))
4055 || (i
.reg_operands
== 1
4057 && i
.tm
.base_opcode
== 0x30)))))
4060 andq $imm31, %r64 -> andl $imm31, %r32
4061 andq $imm7, %r64 -> andl $imm7, %r32
4062 testq $imm31, %r64 -> testl $imm31, %r32
4063 xorq %r64, %r64 -> xorl %r32, %r32
4064 subq %r64, %r64 -> subl %r32, %r32
4065 movq $imm31, %r64 -> movl $imm31, %r32
4066 movq $imm32, %r64 -> movl $imm32, %r32
4068 i
.tm
.opcode_modifier
.norex64
= 1;
4069 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4072 movq $imm31, %r64 -> movl $imm31, %r32
4073 movq $imm32, %r64 -> movl $imm32, %r32
4075 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4076 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4077 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4078 i
.types
[0].bitfield
.imm32
= 1;
4079 i
.types
[0].bitfield
.imm32s
= 0;
4080 i
.types
[0].bitfield
.imm64
= 0;
4081 i
.types
[1].bitfield
.dword
= 1;
4082 i
.types
[1].bitfield
.qword
= 0;
4083 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4086 movq $imm31, %r64 -> movl $imm31, %r32
4088 i
.tm
.base_opcode
= 0xb8;
4089 i
.tm
.extension_opcode
= None
;
4090 i
.tm
.opcode_modifier
.w
= 0;
4091 i
.tm
.opcode_modifier
.modrm
= 0;
4095 else if (optimize
> 1
4096 && !optimize_for_space
4097 && !is_any_vex_encoding (&i
.tm
)
4098 && i
.reg_operands
== 2
4099 && i
.op
[0].regs
== i
.op
[1].regs
4100 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4101 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4102 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4105 andb %rN, %rN -> testb %rN, %rN
4106 andw %rN, %rN -> testw %rN, %rN
4107 andq %rN, %rN -> testq %rN, %rN
4108 orb %rN, %rN -> testb %rN, %rN
4109 orw %rN, %rN -> testw %rN, %rN
4110 orq %rN, %rN -> testq %rN, %rN
4112 and outside of 64-bit mode
4114 andl %rN, %rN -> testl %rN, %rN
4115 orl %rN, %rN -> testl %rN, %rN
4117 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4119 else if (i
.reg_operands
== 3
4120 && i
.op
[0].regs
== i
.op
[1].regs
4121 && !i
.types
[2].bitfield
.xmmword
4122 && (i
.tm
.opcode_modifier
.vex
4123 || ((!i
.mask
|| i
.mask
->zeroing
)
4125 && is_evex_encoding (&i
.tm
)
4126 && (i
.vec_encoding
!= vex_encoding_evex
4127 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4128 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4129 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4130 && i
.types
[2].bitfield
.ymmword
))))
4131 && ((i
.tm
.base_opcode
== 0x55
4132 || i
.tm
.base_opcode
== 0x6655
4133 || i
.tm
.base_opcode
== 0x66df
4134 || i
.tm
.base_opcode
== 0x57
4135 || i
.tm
.base_opcode
== 0x6657
4136 || i
.tm
.base_opcode
== 0x66ef
4137 || i
.tm
.base_opcode
== 0x66f8
4138 || i
.tm
.base_opcode
== 0x66f9
4139 || i
.tm
.base_opcode
== 0x66fa
4140 || i
.tm
.base_opcode
== 0x66fb
4141 || i
.tm
.base_opcode
== 0x42
4142 || i
.tm
.base_opcode
== 0x6642
4143 || i
.tm
.base_opcode
== 0x47
4144 || i
.tm
.base_opcode
== 0x6647)
4145 && i
.tm
.extension_opcode
== None
))
4148 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4150 EVEX VOP %zmmM, %zmmM, %zmmN
4151 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4152 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4153 EVEX VOP %ymmM, %ymmM, %ymmN
4154 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4155 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4156 VEX VOP %ymmM, %ymmM, %ymmN
4157 -> VEX VOP %xmmM, %xmmM, %xmmN
4158 VOP, one of vpandn and vpxor:
4159 VEX VOP %ymmM, %ymmM, %ymmN
4160 -> VEX VOP %xmmM, %xmmM, %xmmN
4161 VOP, one of vpandnd and vpandnq:
4162 EVEX VOP %zmmM, %zmmM, %zmmN
4163 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4164 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4165 EVEX VOP %ymmM, %ymmM, %ymmN
4166 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4167 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4168 VOP, one of vpxord and vpxorq:
4169 EVEX VOP %zmmM, %zmmM, %zmmN
4170 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4171 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4172 EVEX VOP %ymmM, %ymmM, %ymmN
4173 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4174 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4175 VOP, one of kxord and kxorq:
4176 VEX VOP %kM, %kM, %kN
4177 -> VEX kxorw %kM, %kM, %kN
4178 VOP, one of kandnd and kandnq:
4179 VEX VOP %kM, %kM, %kN
4180 -> VEX kandnw %kM, %kM, %kN
4182 if (is_evex_encoding (&i
.tm
))
4184 if (i
.vec_encoding
!= vex_encoding_evex
)
4186 i
.tm
.opcode_modifier
.vex
= VEX128
;
4187 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4188 i
.tm
.opcode_modifier
.evex
= 0;
4190 else if (optimize
> 1)
4191 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4195 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4197 i
.tm
.base_opcode
&= 0xff;
4198 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4201 i
.tm
.opcode_modifier
.vex
= VEX128
;
4203 if (i
.tm
.opcode_modifier
.vex
)
4204 for (j
= 0; j
< 3; j
++)
4206 i
.types
[j
].bitfield
.xmmword
= 1;
4207 i
.types
[j
].bitfield
.ymmword
= 0;
4210 else if (i
.vec_encoding
!= vex_encoding_evex
4211 && !i
.types
[0].bitfield
.zmmword
4212 && !i
.types
[1].bitfield
.zmmword
4215 && is_evex_encoding (&i
.tm
)
4216 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4217 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4218 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4219 || (i
.tm
.base_opcode
& ~4) == 0x66db
4220 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4221 && i
.tm
.extension_opcode
== None
)
4224 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4225 vmovdqu32 and vmovdqu64:
4226 EVEX VOP %xmmM, %xmmN
4227 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4228 EVEX VOP %ymmM, %ymmN
4229 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4231 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4233 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4235 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4237 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4238 VOP, one of vpand, vpandn, vpor, vpxor:
4239 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4240 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4241 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4242 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4243 EVEX VOP{d,q} mem, %xmmM, %xmmN
4244 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4245 EVEX VOP{d,q} mem, %ymmM, %ymmN
4246 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4248 for (j
= 0; j
< i
.operands
; j
++)
4249 if (operand_type_check (i
.types
[j
], disp
)
4250 && i
.op
[j
].disps
->X_op
== O_constant
)
4252 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4253 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4254 bytes, we choose EVEX Disp8 over VEX Disp32. */
4255 int evex_disp8
, vex_disp8
;
4256 unsigned int memshift
= i
.memshift
;
4257 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4259 evex_disp8
= fits_in_disp8 (n
);
4261 vex_disp8
= fits_in_disp8 (n
);
4262 if (evex_disp8
!= vex_disp8
)
4264 i
.memshift
= memshift
;
4268 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4271 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4272 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4273 i
.tm
.opcode_modifier
.vex
4274 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4275 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4276 /* VPAND, VPOR, and VPXOR are commutative. */
4277 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4278 i
.tm
.opcode_modifier
.commutative
= 1;
4279 i
.tm
.opcode_modifier
.evex
= 0;
4280 i
.tm
.opcode_modifier
.masking
= 0;
4281 i
.tm
.opcode_modifier
.broadcast
= 0;
4282 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4285 i
.types
[j
].bitfield
.disp8
4286 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4290 /* This is the guts of the machine-dependent assembler. LINE points to a
4291 machine dependent instruction. This function is supposed to emit
4292 the frags/bytes it assembles to. */
4295 md_assemble (char *line
)
4298 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4299 const insn_template
*t
;
4301 /* Initialize globals. */
4302 memset (&i
, '\0', sizeof (i
));
4303 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4304 i
.reloc
[j
] = NO_RELOC
;
4305 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4306 memset (im_expressions
, '\0', sizeof (im_expressions
));
4307 save_stack_p
= save_stack
;
4309 /* First parse an instruction mnemonic & call i386_operand for the operands.
4310 We assume that the scrubber has arranged it so that line[0] is the valid
4311 start of a (possibly prefixed) mnemonic. */
4313 line
= parse_insn (line
, mnemonic
);
4316 mnem_suffix
= i
.suffix
;
4318 line
= parse_operands (line
, mnemonic
);
4320 xfree (i
.memop1_string
);
4321 i
.memop1_string
= NULL
;
4325 /* Now we've parsed the mnemonic into a set of templates, and have the
4326 operands at hand. */
4328 /* All intel opcodes have reversed operands except for "bound" and
4329 "enter". We also don't reverse intersegment "jmp" and "call"
4330 instructions with 2 immediate operands so that the immediate segment
4331 precedes the offset, as it does when in AT&T mode. */
4334 && (strcmp (mnemonic
, "bound") != 0)
4335 && (strcmp (mnemonic
, "invlpga") != 0)
4336 && !(operand_type_check (i
.types
[0], imm
)
4337 && operand_type_check (i
.types
[1], imm
)))
4340 /* The order of the immediates should be reversed
4341 for 2 immediates extrq and insertq instructions */
4342 if (i
.imm_operands
== 2
4343 && (strcmp (mnemonic
, "extrq") == 0
4344 || strcmp (mnemonic
, "insertq") == 0))
4345 swap_2_operands (0, 1);
4350 /* Don't optimize displacement for movabs since it only takes 64bit
4353 && i
.disp_encoding
!= disp_encoding_32bit
4354 && (flag_code
!= CODE_64BIT
4355 || strcmp (mnemonic
, "movabs") != 0))
4358 /* Next, we find a template that matches the given insn,
4359 making sure the overlap of the given operands types is consistent
4360 with the template operand types. */
4362 if (!(t
= match_template (mnem_suffix
)))
4365 if (sse_check
!= check_none
4366 && !i
.tm
.opcode_modifier
.noavx
4367 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4368 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4369 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4370 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4371 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4372 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4373 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4374 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4375 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4376 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4377 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4378 || i
.tm
.cpu_flags
.bitfield
.cpusha
4379 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4381 (sse_check
== check_warning
4383 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4386 /* Zap movzx and movsx suffix. The suffix has been set from
4387 "word ptr" or "byte ptr" on the source operand in Intel syntax
4388 or extracted from mnemonic in AT&T syntax. But we'll use
4389 the destination register to choose the suffix for encoding. */
4390 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4392 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4393 there is no suffix, the default will be byte extension. */
4394 if (i
.reg_operands
!= 2
4397 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4402 if (i
.tm
.opcode_modifier
.fwait
)
4403 if (!add_prefix (FWAIT_OPCODE
))
4406 /* Check if REP prefix is OK. */
4407 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4409 as_bad (_("invalid instruction `%s' after `%s'"),
4410 i
.tm
.name
, i
.rep_prefix
);
4414 /* Check for lock without a lockable instruction. Destination operand
4415 must be memory unless it is xchg (0x86). */
4416 if (i
.prefix
[LOCK_PREFIX
]
4417 && (!i
.tm
.opcode_modifier
.islockable
4418 || i
.mem_operands
== 0
4419 || (i
.tm
.base_opcode
!= 0x86
4420 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4422 as_bad (_("expecting lockable instruction after `lock'"));
4426 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4427 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4429 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4433 /* Check if HLE prefix is OK. */
4434 if (i
.hle_prefix
&& !check_hle ())
4437 /* Check BND prefix. */
4438 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4439 as_bad (_("expecting valid branch instruction after `bnd'"));
4441 /* Check NOTRACK prefix. */
4442 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4443 as_bad (_("expecting indirect branch instruction after `notrack'"));
4445 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4447 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4448 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4449 else if (flag_code
!= CODE_16BIT
4450 ? i
.prefix
[ADDR_PREFIX
]
4451 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4452 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4455 /* Insert BND prefix. */
4456 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4458 if (!i
.prefix
[BND_PREFIX
])
4459 add_prefix (BND_PREFIX_OPCODE
);
4460 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4462 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4463 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4467 /* Check string instruction segment overrides. */
4468 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4470 gas_assert (i
.mem_operands
);
4471 if (!check_string ())
4473 i
.disp_operands
= 0;
4476 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4477 optimize_encoding ();
4479 if (!process_suffix ())
4482 /* Update operand types. */
4483 for (j
= 0; j
< i
.operands
; j
++)
4484 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4486 /* Make still unresolved immediate matches conform to size of immediate
4487 given in i.suffix. */
4488 if (!finalize_imm ())
4491 if (i
.types
[0].bitfield
.imm1
)
4492 i
.imm_operands
= 0; /* kludge for shift insns. */
4494 /* We only need to check those implicit registers for instructions
4495 with 3 operands or less. */
4496 if (i
.operands
<= 3)
4497 for (j
= 0; j
< i
.operands
; j
++)
4498 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4499 && !i
.types
[j
].bitfield
.xmmword
)
4502 /* ImmExt should be processed after SSE2AVX. */
4503 if (!i
.tm
.opcode_modifier
.sse2avx
4504 && i
.tm
.opcode_modifier
.immext
)
4507 /* For insns with operands there are more diddles to do to the opcode. */
4510 if (!process_operands ())
4513 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4515 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4516 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4519 if (is_any_vex_encoding (&i
.tm
))
4521 if (!cpu_arch_flags
.bitfield
.cpui286
)
4523 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4528 if (i
.tm
.opcode_modifier
.vex
)
4529 build_vex_prefix (t
);
4531 build_evex_prefix ();
4534 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4535 instructions may define INT_OPCODE as well, so avoid this corner
4536 case for those instructions that use MODRM. */
4537 if (i
.tm
.base_opcode
== INT_OPCODE
4538 && !i
.tm
.opcode_modifier
.modrm
4539 && i
.op
[0].imms
->X_add_number
== 3)
4541 i
.tm
.base_opcode
= INT3_OPCODE
;
4545 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4546 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4547 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4548 && i
.op
[0].disps
->X_op
== O_constant
)
4550 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4551 the absolute address given by the constant. Since ix86 jumps and
4552 calls are pc relative, we need to generate a reloc. */
4553 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4554 i
.op
[0].disps
->X_op
= O_symbol
;
4557 if (i
.tm
.opcode_modifier
.rex64
)
4560 /* For 8 bit registers we need an empty rex prefix. Also if the
4561 instruction already has a prefix, we need to convert old
4562 registers to new ones. */
4564 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4565 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4566 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4567 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4568 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4569 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4574 i
.rex
|= REX_OPCODE
;
4575 for (x
= 0; x
< 2; x
++)
4577 /* Look for 8 bit operand that uses old registers. */
4578 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4579 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4581 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4582 /* In case it is "hi" register, give up. */
4583 if (i
.op
[x
].regs
->reg_num
> 3)
4584 as_bad (_("can't encode register '%s%s' in an "
4585 "instruction requiring REX prefix."),
4586 register_prefix
, i
.op
[x
].regs
->reg_name
);
4588 /* Otherwise it is equivalent to the extended register.
4589 Since the encoding doesn't change this is merely
4590 cosmetic cleanup for debug output. */
4592 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4597 if (i
.rex
== 0 && i
.rex_encoding
)
4599 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4600 that uses legacy register. If it is "hi" register, don't add
4601 the REX_OPCODE byte. */
4603 for (x
= 0; x
< 2; x
++)
4604 if (i
.types
[x
].bitfield
.class == Reg
4605 && i
.types
[x
].bitfield
.byte
4606 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4607 && i
.op
[x
].regs
->reg_num
> 3)
4609 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4610 i
.rex_encoding
= FALSE
;
4619 add_prefix (REX_OPCODE
| i
.rex
);
4621 /* We are ready to output the insn. */
4624 last_insn
.seg
= now_seg
;
4626 if (i
.tm
.opcode_modifier
.isprefix
)
4628 last_insn
.kind
= last_insn_prefix
;
4629 last_insn
.name
= i
.tm
.name
;
4630 last_insn
.file
= as_where (&last_insn
.line
);
4633 last_insn
.kind
= last_insn_other
;
4637 parse_insn (char *line
, char *mnemonic
)
4640 char *token_start
= l
;
4643 const insn_template
*t
;
4649 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4654 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4656 as_bad (_("no such instruction: `%s'"), token_start
);
4661 if (!is_space_char (*l
)
4662 && *l
!= END_OF_INSN
4664 || (*l
!= PREFIX_SEPARATOR
4667 as_bad (_("invalid character %s in mnemonic"),
4668 output_invalid (*l
));
4671 if (token_start
== l
)
4673 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4674 as_bad (_("expecting prefix; got nothing"));
4676 as_bad (_("expecting mnemonic; got nothing"));
4680 /* Look up instruction (or prefix) via hash table. */
4681 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4683 if (*l
!= END_OF_INSN
4684 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4685 && current_templates
4686 && current_templates
->start
->opcode_modifier
.isprefix
)
4688 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4690 as_bad ((flag_code
!= CODE_64BIT
4691 ? _("`%s' is only supported in 64-bit mode")
4692 : _("`%s' is not supported in 64-bit mode")),
4693 current_templates
->start
->name
);
4696 /* If we are in 16-bit mode, do not allow addr16 or data16.
4697 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4698 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4699 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4700 && flag_code
!= CODE_64BIT
4701 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4702 ^ (flag_code
== CODE_16BIT
)))
4704 as_bad (_("redundant %s prefix"),
4705 current_templates
->start
->name
);
4708 if (current_templates
->start
->opcode_length
== 0)
4710 /* Handle pseudo prefixes. */
4711 switch (current_templates
->start
->base_opcode
)
4715 i
.disp_encoding
= disp_encoding_8bit
;
4719 i
.disp_encoding
= disp_encoding_32bit
;
4723 i
.dir_encoding
= dir_encoding_load
;
4727 i
.dir_encoding
= dir_encoding_store
;
4731 i
.vec_encoding
= vex_encoding_vex
;
4735 i
.vec_encoding
= vex_encoding_vex3
;
4739 i
.vec_encoding
= vex_encoding_evex
;
4743 i
.rex_encoding
= TRUE
;
4747 i
.no_optimize
= TRUE
;
4755 /* Add prefix, checking for repeated prefixes. */
4756 switch (add_prefix (current_templates
->start
->base_opcode
))
4761 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4762 i
.notrack_prefix
= current_templates
->start
->name
;
4765 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4766 i
.hle_prefix
= current_templates
->start
->name
;
4767 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4768 i
.bnd_prefix
= current_templates
->start
->name
;
4770 i
.rep_prefix
= current_templates
->start
->name
;
4776 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4783 if (!current_templates
)
4785 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4786 Check if we should swap operand or force 32bit displacement in
4788 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4789 i
.dir_encoding
= dir_encoding_swap
;
4790 else if (mnem_p
- 3 == dot_p
4793 i
.disp_encoding
= disp_encoding_8bit
;
4794 else if (mnem_p
- 4 == dot_p
4798 i
.disp_encoding
= disp_encoding_32bit
;
4803 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4806 if (!current_templates
)
4809 if (mnem_p
> mnemonic
)
4811 /* See if we can get a match by trimming off a suffix. */
4814 case WORD_MNEM_SUFFIX
:
4815 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4816 i
.suffix
= SHORT_MNEM_SUFFIX
;
4819 case BYTE_MNEM_SUFFIX
:
4820 case QWORD_MNEM_SUFFIX
:
4821 i
.suffix
= mnem_p
[-1];
4823 current_templates
= (const templates
*) hash_find (op_hash
,
4826 case SHORT_MNEM_SUFFIX
:
4827 case LONG_MNEM_SUFFIX
:
4830 i
.suffix
= mnem_p
[-1];
4832 current_templates
= (const templates
*) hash_find (op_hash
,
4841 if (intel_float_operand (mnemonic
) == 1)
4842 i
.suffix
= SHORT_MNEM_SUFFIX
;
4844 i
.suffix
= LONG_MNEM_SUFFIX
;
4846 current_templates
= (const templates
*) hash_find (op_hash
,
4853 if (!current_templates
)
4855 as_bad (_("no such instruction: `%s'"), token_start
);
4860 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4861 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4863 /* Check for a branch hint. We allow ",pt" and ",pn" for
4864 predict taken and predict not taken respectively.
4865 I'm not sure that branch hints actually do anything on loop
4866 and jcxz insns (JumpByte) for current Pentium4 chips. They
4867 may work in the future and it doesn't hurt to accept them
4869 if (l
[0] == ',' && l
[1] == 'p')
4873 if (!add_prefix (DS_PREFIX_OPCODE
))
4877 else if (l
[2] == 'n')
4879 if (!add_prefix (CS_PREFIX_OPCODE
))
4885 /* Any other comma loses. */
4888 as_bad (_("invalid character %s in mnemonic"),
4889 output_invalid (*l
));
4893 /* Check if instruction is supported on specified architecture. */
4895 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4897 supported
|= cpu_flags_match (t
);
4898 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4900 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4901 as_warn (_("use .code16 to ensure correct addressing mode"));
4907 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4908 as_bad (flag_code
== CODE_64BIT
4909 ? _("`%s' is not supported in 64-bit mode")
4910 : _("`%s' is only supported in 64-bit mode"),
4911 current_templates
->start
->name
);
4913 as_bad (_("`%s' is not supported on `%s%s'"),
4914 current_templates
->start
->name
,
4915 cpu_arch_name
? cpu_arch_name
: default_arch
,
4916 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4922 parse_operands (char *l
, const char *mnemonic
)
4926 /* 1 if operand is pending after ','. */
4927 unsigned int expecting_operand
= 0;
4929 /* Non-zero if operand parens not balanced. */
4930 unsigned int paren_not_balanced
;
4932 while (*l
!= END_OF_INSN
)
4934 /* Skip optional white space before operand. */
4935 if (is_space_char (*l
))
4937 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4939 as_bad (_("invalid character %s before operand %d"),
4940 output_invalid (*l
),
4944 token_start
= l
; /* After white space. */
4945 paren_not_balanced
= 0;
4946 while (paren_not_balanced
|| *l
!= ',')
4948 if (*l
== END_OF_INSN
)
4950 if (paren_not_balanced
)
4953 as_bad (_("unbalanced parenthesis in operand %d."),
4956 as_bad (_("unbalanced brackets in operand %d."),
4961 break; /* we are done */
4963 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4965 as_bad (_("invalid character %s in operand %d"),
4966 output_invalid (*l
),
4973 ++paren_not_balanced
;
4975 --paren_not_balanced
;
4980 ++paren_not_balanced
;
4982 --paren_not_balanced
;
4986 if (l
!= token_start
)
4987 { /* Yes, we've read in another operand. */
4988 unsigned int operand_ok
;
4989 this_operand
= i
.operands
++;
4990 if (i
.operands
> MAX_OPERANDS
)
4992 as_bad (_("spurious operands; (%d operands/instruction max)"),
4996 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4997 /* Now parse operand adding info to 'i' as we go along. */
4998 END_STRING_AND_SAVE (l
);
5000 if (i
.mem_operands
> 1)
5002 as_bad (_("too many memory references for `%s'"),
5009 i386_intel_operand (token_start
,
5010 intel_float_operand (mnemonic
));
5012 operand_ok
= i386_att_operand (token_start
);
5014 RESTORE_END_STRING (l
);
5020 if (expecting_operand
)
5022 expecting_operand_after_comma
:
5023 as_bad (_("expecting operand after ','; got nothing"));
5028 as_bad (_("expecting operand before ','; got nothing"));
5033 /* Now *l must be either ',' or END_OF_INSN. */
5036 if (*++l
== END_OF_INSN
)
5038 /* Just skip it, if it's \n complain. */
5039 goto expecting_operand_after_comma
;
5041 expecting_operand
= 1;
5048 swap_2_operands (int xchg1
, int xchg2
)
5050 union i386_op temp_op
;
5051 i386_operand_type temp_type
;
5052 unsigned int temp_flags
;
5053 enum bfd_reloc_code_real temp_reloc
;
5055 temp_type
= i
.types
[xchg2
];
5056 i
.types
[xchg2
] = i
.types
[xchg1
];
5057 i
.types
[xchg1
] = temp_type
;
5059 temp_flags
= i
.flags
[xchg2
];
5060 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5061 i
.flags
[xchg1
] = temp_flags
;
5063 temp_op
= i
.op
[xchg2
];
5064 i
.op
[xchg2
] = i
.op
[xchg1
];
5065 i
.op
[xchg1
] = temp_op
;
5067 temp_reloc
= i
.reloc
[xchg2
];
5068 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5069 i
.reloc
[xchg1
] = temp_reloc
;
5073 if (i
.mask
->operand
== xchg1
)
5074 i
.mask
->operand
= xchg2
;
5075 else if (i
.mask
->operand
== xchg2
)
5076 i
.mask
->operand
= xchg1
;
5080 if (i
.broadcast
->operand
== xchg1
)
5081 i
.broadcast
->operand
= xchg2
;
5082 else if (i
.broadcast
->operand
== xchg2
)
5083 i
.broadcast
->operand
= xchg1
;
5087 if (i
.rounding
->operand
== xchg1
)
5088 i
.rounding
->operand
= xchg2
;
5089 else if (i
.rounding
->operand
== xchg2
)
5090 i
.rounding
->operand
= xchg1
;
5095 swap_operands (void)
5101 swap_2_operands (1, i
.operands
- 2);
5105 swap_2_operands (0, i
.operands
- 1);
5111 if (i
.mem_operands
== 2)
5113 const seg_entry
*temp_seg
;
5114 temp_seg
= i
.seg
[0];
5115 i
.seg
[0] = i
.seg
[1];
5116 i
.seg
[1] = temp_seg
;
5120 /* Try to ensure constant immediates are represented in the smallest
5125 char guess_suffix
= 0;
5129 guess_suffix
= i
.suffix
;
5130 else if (i
.reg_operands
)
5132 /* Figure out a suffix from the last register operand specified.
5133 We can't do this properly yet, i.e. excluding special register
5134 instances, but the following works for instructions with
5135 immediates. In any case, we can't set i.suffix yet. */
5136 for (op
= i
.operands
; --op
>= 0;)
5137 if (i
.types
[op
].bitfield
.class != Reg
)
5139 else if (i
.types
[op
].bitfield
.byte
)
5141 guess_suffix
= BYTE_MNEM_SUFFIX
;
5144 else if (i
.types
[op
].bitfield
.word
)
5146 guess_suffix
= WORD_MNEM_SUFFIX
;
5149 else if (i
.types
[op
].bitfield
.dword
)
5151 guess_suffix
= LONG_MNEM_SUFFIX
;
5154 else if (i
.types
[op
].bitfield
.qword
)
5156 guess_suffix
= QWORD_MNEM_SUFFIX
;
5160 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5161 guess_suffix
= WORD_MNEM_SUFFIX
;
5163 for (op
= i
.operands
; --op
>= 0;)
5164 if (operand_type_check (i
.types
[op
], imm
))
5166 switch (i
.op
[op
].imms
->X_op
)
5169 /* If a suffix is given, this operand may be shortened. */
5170 switch (guess_suffix
)
5172 case LONG_MNEM_SUFFIX
:
5173 i
.types
[op
].bitfield
.imm32
= 1;
5174 i
.types
[op
].bitfield
.imm64
= 1;
5176 case WORD_MNEM_SUFFIX
:
5177 i
.types
[op
].bitfield
.imm16
= 1;
5178 i
.types
[op
].bitfield
.imm32
= 1;
5179 i
.types
[op
].bitfield
.imm32s
= 1;
5180 i
.types
[op
].bitfield
.imm64
= 1;
5182 case BYTE_MNEM_SUFFIX
:
5183 i
.types
[op
].bitfield
.imm8
= 1;
5184 i
.types
[op
].bitfield
.imm8s
= 1;
5185 i
.types
[op
].bitfield
.imm16
= 1;
5186 i
.types
[op
].bitfield
.imm32
= 1;
5187 i
.types
[op
].bitfield
.imm32s
= 1;
5188 i
.types
[op
].bitfield
.imm64
= 1;
5192 /* If this operand is at most 16 bits, convert it
5193 to a signed 16 bit number before trying to see
5194 whether it will fit in an even smaller size.
5195 This allows a 16-bit operand such as $0xffe0 to
5196 be recognised as within Imm8S range. */
5197 if ((i
.types
[op
].bitfield
.imm16
)
5198 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5200 i
.op
[op
].imms
->X_add_number
=
5201 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5204 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5205 if ((i
.types
[op
].bitfield
.imm32
)
5206 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5209 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5210 ^ ((offsetT
) 1 << 31))
5211 - ((offsetT
) 1 << 31));
5215 = operand_type_or (i
.types
[op
],
5216 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5218 /* We must avoid matching of Imm32 templates when 64bit
5219 only immediate is available. */
5220 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5221 i
.types
[op
].bitfield
.imm32
= 0;
5228 /* Symbols and expressions. */
5230 /* Convert symbolic operand to proper sizes for matching, but don't
5231 prevent matching a set of insns that only supports sizes other
5232 than those matching the insn suffix. */
5234 i386_operand_type mask
, allowed
;
5235 const insn_template
*t
;
5237 operand_type_set (&mask
, 0);
5238 operand_type_set (&allowed
, 0);
5240 for (t
= current_templates
->start
;
5241 t
< current_templates
->end
;
5244 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5245 allowed
= operand_type_and (allowed
, anyimm
);
5247 switch (guess_suffix
)
5249 case QWORD_MNEM_SUFFIX
:
5250 mask
.bitfield
.imm64
= 1;
5251 mask
.bitfield
.imm32s
= 1;
5253 case LONG_MNEM_SUFFIX
:
5254 mask
.bitfield
.imm32
= 1;
5256 case WORD_MNEM_SUFFIX
:
5257 mask
.bitfield
.imm16
= 1;
5259 case BYTE_MNEM_SUFFIX
:
5260 mask
.bitfield
.imm8
= 1;
5265 allowed
= operand_type_and (mask
, allowed
);
5266 if (!operand_type_all_zero (&allowed
))
5267 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5274 /* Try to use the smallest displacement type too. */
5276 optimize_disp (void)
5280 for (op
= i
.operands
; --op
>= 0;)
5281 if (operand_type_check (i
.types
[op
], disp
))
5283 if (i
.op
[op
].disps
->X_op
== O_constant
)
5285 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5287 if (i
.types
[op
].bitfield
.disp16
5288 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5290 /* If this operand is at most 16 bits, convert
5291 to a signed 16 bit number and don't use 64bit
5293 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5294 i
.types
[op
].bitfield
.disp64
= 0;
5297 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5298 if (i
.types
[op
].bitfield
.disp32
5299 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5301 /* If this operand is at most 32 bits, convert
5302 to a signed 32 bit number and don't use 64bit
5304 op_disp
&= (((offsetT
) 2 << 31) - 1);
5305 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5306 i
.types
[op
].bitfield
.disp64
= 0;
5309 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5311 i
.types
[op
].bitfield
.disp8
= 0;
5312 i
.types
[op
].bitfield
.disp16
= 0;
5313 i
.types
[op
].bitfield
.disp32
= 0;
5314 i
.types
[op
].bitfield
.disp32s
= 0;
5315 i
.types
[op
].bitfield
.disp64
= 0;
5319 else if (flag_code
== CODE_64BIT
)
5321 if (fits_in_signed_long (op_disp
))
5323 i
.types
[op
].bitfield
.disp64
= 0;
5324 i
.types
[op
].bitfield
.disp32s
= 1;
5326 if (i
.prefix
[ADDR_PREFIX
]
5327 && fits_in_unsigned_long (op_disp
))
5328 i
.types
[op
].bitfield
.disp32
= 1;
5330 if ((i
.types
[op
].bitfield
.disp32
5331 || i
.types
[op
].bitfield
.disp32s
5332 || i
.types
[op
].bitfield
.disp16
)
5333 && fits_in_disp8 (op_disp
))
5334 i
.types
[op
].bitfield
.disp8
= 1;
5336 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5337 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5339 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5340 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5341 i
.types
[op
].bitfield
.disp8
= 0;
5342 i
.types
[op
].bitfield
.disp16
= 0;
5343 i
.types
[op
].bitfield
.disp32
= 0;
5344 i
.types
[op
].bitfield
.disp32s
= 0;
5345 i
.types
[op
].bitfield
.disp64
= 0;
5348 /* We only support 64bit displacement on constants. */
5349 i
.types
[op
].bitfield
.disp64
= 0;
5353 /* Return 1 if there is a match in broadcast bytes between operand
5354 GIVEN and instruction template T. */
5357 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5359 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5360 && i
.types
[given
].bitfield
.byte
)
5361 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5362 && i
.types
[given
].bitfield
.word
)
5363 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5364 && i
.types
[given
].bitfield
.dword
)
5365 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5366 && i
.types
[given
].bitfield
.qword
));
5369 /* Check if operands are valid for the instruction. */
5372 check_VecOperands (const insn_template
*t
)
5376 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5378 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5379 any one operand are implicity requiring AVX512VL support if the actual
5380 operand size is YMMword or XMMword. Since this function runs after
5381 template matching, there's no need to check for YMMword/XMMword in
5383 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5384 if (!cpu_flags_all_zero (&cpu
)
5385 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5386 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5388 for (op
= 0; op
< t
->operands
; ++op
)
5390 if (t
->operand_types
[op
].bitfield
.zmmword
5391 && (i
.types
[op
].bitfield
.ymmword
5392 || i
.types
[op
].bitfield
.xmmword
))
5394 i
.error
= unsupported
;
5400 /* Without VSIB byte, we can't have a vector register for index. */
5401 if (!t
->opcode_modifier
.vecsib
5403 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5404 || i
.index_reg
->reg_type
.bitfield
.ymmword
5405 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5407 i
.error
= unsupported_vector_index_register
;
5411 /* Check if default mask is allowed. */
5412 if (t
->opcode_modifier
.nodefmask
5413 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5415 i
.error
= no_default_mask
;
5419 /* For VSIB byte, we need a vector register for index, and all vector
5420 registers must be distinct. */
5421 if (t
->opcode_modifier
.vecsib
)
5424 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5425 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5426 || (t
->opcode_modifier
.vecsib
== VecSIB256
5427 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5428 || (t
->opcode_modifier
.vecsib
== VecSIB512
5429 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5431 i
.error
= invalid_vsib_address
;
5435 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5436 if (i
.reg_operands
== 2 && !i
.mask
)
5438 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5439 gas_assert (i
.types
[0].bitfield
.xmmword
5440 || i
.types
[0].bitfield
.ymmword
);
5441 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5442 gas_assert (i
.types
[2].bitfield
.xmmword
5443 || i
.types
[2].bitfield
.ymmword
);
5444 if (operand_check
== check_none
)
5446 if (register_number (i
.op
[0].regs
)
5447 != register_number (i
.index_reg
)
5448 && register_number (i
.op
[2].regs
)
5449 != register_number (i
.index_reg
)
5450 && register_number (i
.op
[0].regs
)
5451 != register_number (i
.op
[2].regs
))
5453 if (operand_check
== check_error
)
5455 i
.error
= invalid_vector_register_set
;
5458 as_warn (_("mask, index, and destination registers should be distinct"));
5460 else if (i
.reg_operands
== 1 && i
.mask
)
5462 if (i
.types
[1].bitfield
.class == RegSIMD
5463 && (i
.types
[1].bitfield
.xmmword
5464 || i
.types
[1].bitfield
.ymmword
5465 || i
.types
[1].bitfield
.zmmword
)
5466 && (register_number (i
.op
[1].regs
)
5467 == register_number (i
.index_reg
)))
5469 if (operand_check
== check_error
)
5471 i
.error
= invalid_vector_register_set
;
5474 if (operand_check
!= check_none
)
5475 as_warn (_("index and destination registers should be distinct"));
5480 /* Check if broadcast is supported by the instruction and is applied
5481 to the memory operand. */
5484 i386_operand_type type
, overlap
;
5486 /* Check if specified broadcast is supported in this instruction,
5487 and its broadcast bytes match the memory operand. */
5488 op
= i
.broadcast
->operand
;
5489 if (!t
->opcode_modifier
.broadcast
5490 || !(i
.flags
[op
] & Operand_Mem
)
5491 || (!i
.types
[op
].bitfield
.unspecified
5492 && !match_broadcast_size (t
, op
)))
5495 i
.error
= unsupported_broadcast
;
5499 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5500 * i
.broadcast
->type
);
5501 operand_type_set (&type
, 0);
5502 switch (i
.broadcast
->bytes
)
5505 type
.bitfield
.word
= 1;
5508 type
.bitfield
.dword
= 1;
5511 type
.bitfield
.qword
= 1;
5514 type
.bitfield
.xmmword
= 1;
5517 type
.bitfield
.ymmword
= 1;
5520 type
.bitfield
.zmmword
= 1;
5526 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5527 if (operand_type_all_zero (&overlap
))
5530 if (t
->opcode_modifier
.checkregsize
)
5534 type
.bitfield
.baseindex
= 1;
5535 for (j
= 0; j
< i
.operands
; ++j
)
5538 && !operand_type_register_match(i
.types
[j
],
5539 t
->operand_types
[j
],
5541 t
->operand_types
[op
]))
5546 /* If broadcast is supported in this instruction, we need to check if
5547 operand of one-element size isn't specified without broadcast. */
5548 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5550 /* Find memory operand. */
5551 for (op
= 0; op
< i
.operands
; op
++)
5552 if (i
.flags
[op
] & Operand_Mem
)
5554 gas_assert (op
< i
.operands
);
5555 /* Check size of the memory operand. */
5556 if (match_broadcast_size (t
, op
))
5558 i
.error
= broadcast_needed
;
5563 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5565 /* Check if requested masking is supported. */
5568 switch (t
->opcode_modifier
.masking
)
5572 case MERGING_MASKING
:
5573 if (i
.mask
->zeroing
)
5576 i
.error
= unsupported_masking
;
5580 case DYNAMIC_MASKING
:
5581 /* Memory destinations allow only merging masking. */
5582 if (i
.mask
->zeroing
&& i
.mem_operands
)
5584 /* Find memory operand. */
5585 for (op
= 0; op
< i
.operands
; op
++)
5586 if (i
.flags
[op
] & Operand_Mem
)
5588 gas_assert (op
< i
.operands
);
5589 if (op
== i
.operands
- 1)
5591 i
.error
= unsupported_masking
;
5601 /* Check if masking is applied to dest operand. */
5602 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5604 i
.error
= mask_not_on_destination
;
5611 if (!t
->opcode_modifier
.sae
5612 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5614 i
.error
= unsupported_rc_sae
;
5617 /* If the instruction has several immediate operands and one of
5618 them is rounding, the rounding operand should be the last
5619 immediate operand. */
5620 if (i
.imm_operands
> 1
5621 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5623 i
.error
= rc_sae_operand_not_last_imm
;
5628 /* Check vector Disp8 operand. */
5629 if (t
->opcode_modifier
.disp8memshift
5630 && i
.disp_encoding
!= disp_encoding_32bit
)
5633 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5634 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5635 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5638 const i386_operand_type
*type
= NULL
;
5641 for (op
= 0; op
< i
.operands
; op
++)
5642 if (i
.flags
[op
] & Operand_Mem
)
5644 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5645 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5646 else if (t
->operand_types
[op
].bitfield
.xmmword
5647 + t
->operand_types
[op
].bitfield
.ymmword
5648 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5649 type
= &t
->operand_types
[op
];
5650 else if (!i
.types
[op
].bitfield
.unspecified
)
5651 type
= &i
.types
[op
];
5653 else if (i
.types
[op
].bitfield
.class == RegSIMD
5654 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5656 if (i
.types
[op
].bitfield
.zmmword
)
5658 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5660 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5666 if (type
->bitfield
.zmmword
)
5668 else if (type
->bitfield
.ymmword
)
5670 else if (type
->bitfield
.xmmword
)
5674 /* For the check in fits_in_disp8(). */
5675 if (i
.memshift
== 0)
5679 for (op
= 0; op
< i
.operands
; op
++)
5680 if (operand_type_check (i
.types
[op
], disp
)
5681 && i
.op
[op
].disps
->X_op
== O_constant
)
5683 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5685 i
.types
[op
].bitfield
.disp8
= 1;
5688 i
.types
[op
].bitfield
.disp8
= 0;
5697 /* Check if operands are valid for the instruction. Update VEX
5701 VEX_check_operands (const insn_template
*t
)
5703 if (i
.vec_encoding
== vex_encoding_evex
)
5705 /* This instruction must be encoded with EVEX prefix. */
5706 if (!is_evex_encoding (t
))
5708 i
.error
= unsupported
;
5714 if (!t
->opcode_modifier
.vex
)
5716 /* This instruction template doesn't have VEX prefix. */
5717 if (i
.vec_encoding
!= vex_encoding_default
)
5719 i
.error
= unsupported
;
5725 /* Check the special Imm4 cases; must be the first operand. */
5726 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5728 if (i
.op
[0].imms
->X_op
!= O_constant
5729 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5735 /* Turn off Imm<N> so that update_imm won't complain. */
5736 operand_type_set (&i
.types
[0], 0);
5742 static const insn_template
*
5743 match_template (char mnem_suffix
)
5745 /* Points to template once we've found it. */
5746 const insn_template
*t
;
5747 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5748 i386_operand_type overlap4
;
5749 unsigned int found_reverse_match
;
5750 i386_opcode_modifier suffix_check
;
5751 i386_operand_type operand_types
[MAX_OPERANDS
];
5752 int addr_prefix_disp
;
5753 unsigned int j
, size_match
, check_register
;
5754 enum i386_error specific_error
= 0;
5756 #if MAX_OPERANDS != 5
5757 # error "MAX_OPERANDS must be 5."
5760 found_reverse_match
= 0;
5761 addr_prefix_disp
= -1;
5763 /* Prepare for mnemonic suffix check. */
5764 memset (&suffix_check
, 0, sizeof (suffix_check
));
5765 switch (mnem_suffix
)
5767 case BYTE_MNEM_SUFFIX
:
5768 suffix_check
.no_bsuf
= 1;
5770 case WORD_MNEM_SUFFIX
:
5771 suffix_check
.no_wsuf
= 1;
5773 case SHORT_MNEM_SUFFIX
:
5774 suffix_check
.no_ssuf
= 1;
5776 case LONG_MNEM_SUFFIX
:
5777 suffix_check
.no_lsuf
= 1;
5779 case QWORD_MNEM_SUFFIX
:
5780 suffix_check
.no_qsuf
= 1;
5783 /* NB: In Intel syntax, normally we can check for memory operand
5784 size when there is no mnemonic suffix. But jmp and call have
5785 2 different encodings with Dword memory operand size, one with
5786 No_ldSuf and the other without. i.suffix is set to
5787 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5788 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5789 suffix_check
.no_ldsuf
= 1;
5792 /* Must have right number of operands. */
5793 i
.error
= number_of_operands_mismatch
;
5795 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5797 addr_prefix_disp
= -1;
5798 found_reverse_match
= 0;
5800 if (i
.operands
!= t
->operands
)
5803 /* Check processor support. */
5804 i
.error
= unsupported
;
5805 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
5808 /* Check AT&T mnemonic. */
5809 i
.error
= unsupported_with_intel_mnemonic
;
5810 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5813 /* Check AT&T/Intel syntax. */
5814 i
.error
= unsupported_syntax
;
5815 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5816 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
5819 /* Check Intel64/AMD64 ISA. */
5823 /* Default: Don't accept Intel64. */
5824 if (t
->opcode_modifier
.isa64
== INTEL64
)
5828 /* -mamd64: Don't accept Intel64 and Intel64 only. */
5829 if (t
->opcode_modifier
.isa64
>= INTEL64
)
5833 /* -mintel64: Don't accept AMD64. */
5834 if (t
->opcode_modifier
.isa64
== AMD64
)
5839 /* Check the suffix. */
5840 i
.error
= invalid_instruction_suffix
;
5841 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5842 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5843 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5844 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5845 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5846 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5849 size_match
= operand_size_match (t
);
5853 /* This is intentionally not
5855 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5857 as the case of a missing * on the operand is accepted (perhaps with
5858 a warning, issued further down). */
5859 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5861 i
.error
= operand_type_mismatch
;
5865 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5866 operand_types
[j
] = t
->operand_types
[j
];
5868 /* In general, don't allow 64-bit operands in 32-bit mode. */
5869 if (i
.suffix
== QWORD_MNEM_SUFFIX
5870 && flag_code
!= CODE_64BIT
5872 ? (!t
->opcode_modifier
.ignoresize
5873 && !t
->opcode_modifier
.broadcast
5874 && !intel_float_operand (t
->name
))
5875 : intel_float_operand (t
->name
) != 2)
5876 && ((operand_types
[0].bitfield
.class != RegMMX
5877 && operand_types
[0].bitfield
.class != RegSIMD
)
5878 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5879 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5880 && (t
->base_opcode
!= 0x0fc7
5881 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5884 /* In general, don't allow 32-bit operands on pre-386. */
5885 else if (i
.suffix
== LONG_MNEM_SUFFIX
5886 && !cpu_arch_flags
.bitfield
.cpui386
5888 ? (!t
->opcode_modifier
.ignoresize
5889 && !intel_float_operand (t
->name
))
5890 : intel_float_operand (t
->name
) != 2)
5891 && ((operand_types
[0].bitfield
.class != RegMMX
5892 && operand_types
[0].bitfield
.class != RegSIMD
)
5893 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5894 && operand_types
[t
->operands
> 1].bitfield
.class
5898 /* Do not verify operands when there are none. */
5902 /* We've found a match; break out of loop. */
5906 if (!t
->opcode_modifier
.jump
5907 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
5909 /* There should be only one Disp operand. */
5910 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5911 if (operand_type_check (operand_types
[j
], disp
))
5913 if (j
< MAX_OPERANDS
)
5915 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5917 addr_prefix_disp
= j
;
5919 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
5920 operand into Disp32/Disp32/Disp16/Disp32 operand. */
5924 override
= !override
;
5927 if (operand_types
[j
].bitfield
.disp32
5928 && operand_types
[j
].bitfield
.disp16
)
5930 operand_types
[j
].bitfield
.disp16
= override
;
5931 operand_types
[j
].bitfield
.disp32
= !override
;
5933 operand_types
[j
].bitfield
.disp32s
= 0;
5934 operand_types
[j
].bitfield
.disp64
= 0;
5938 if (operand_types
[j
].bitfield
.disp32s
5939 || operand_types
[j
].bitfield
.disp64
)
5941 operand_types
[j
].bitfield
.disp64
&= !override
;
5942 operand_types
[j
].bitfield
.disp32s
&= !override
;
5943 operand_types
[j
].bitfield
.disp32
= override
;
5945 operand_types
[j
].bitfield
.disp16
= 0;
5951 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5952 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5955 /* We check register size if needed. */
5956 if (t
->opcode_modifier
.checkregsize
)
5958 check_register
= (1 << t
->operands
) - 1;
5960 check_register
&= ~(1 << i
.broadcast
->operand
);
5965 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5966 switch (t
->operands
)
5969 if (!operand_type_match (overlap0
, i
.types
[0]))
5973 /* xchg %eax, %eax is a special case. It is an alias for nop
5974 only in 32bit mode and we can use opcode 0x90. In 64bit
5975 mode, we can't use 0x90 for xchg %eax, %eax since it should
5976 zero-extend %eax to %rax. */
5977 if (flag_code
== CODE_64BIT
5978 && t
->base_opcode
== 0x90
5979 && i
.types
[0].bitfield
.instance
== Accum
5980 && i
.types
[0].bitfield
.dword
5981 && i
.types
[1].bitfield
.instance
== Accum
5982 && i
.types
[1].bitfield
.dword
)
5984 /* xrelease mov %eax, <disp> is another special case. It must not
5985 match the accumulator-only encoding of mov. */
5986 if (flag_code
!= CODE_64BIT
5988 && t
->base_opcode
== 0xa0
5989 && i
.types
[0].bitfield
.instance
== Accum
5990 && (i
.flags
[1] & Operand_Mem
))
5995 if (!(size_match
& MATCH_STRAIGHT
))
5997 /* Reverse direction of operands if swapping is possible in the first
5998 place (operands need to be symmetric) and
5999 - the load form is requested, and the template is a store form,
6000 - the store form is requested, and the template is a load form,
6001 - the non-default (swapped) form is requested. */
6002 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6003 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6004 && !operand_type_all_zero (&overlap1
))
6005 switch (i
.dir_encoding
)
6007 case dir_encoding_load
:
6008 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6009 || t
->opcode_modifier
.regmem
)
6013 case dir_encoding_store
:
6014 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6015 && !t
->opcode_modifier
.regmem
)
6019 case dir_encoding_swap
:
6022 case dir_encoding_default
:
6025 /* If we want store form, we skip the current load. */
6026 if ((i
.dir_encoding
== dir_encoding_store
6027 || i
.dir_encoding
== dir_encoding_swap
)
6028 && i
.mem_operands
== 0
6029 && t
->opcode_modifier
.load
)
6034 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6035 if (!operand_type_match (overlap0
, i
.types
[0])
6036 || !operand_type_match (overlap1
, i
.types
[1])
6037 || ((check_register
& 3) == 3
6038 && !operand_type_register_match (i
.types
[0],
6043 /* Check if other direction is valid ... */
6044 if (!t
->opcode_modifier
.d
)
6048 if (!(size_match
& MATCH_REVERSE
))
6050 /* Try reversing direction of operands. */
6051 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6052 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6053 if (!operand_type_match (overlap0
, i
.types
[0])
6054 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6056 && !operand_type_register_match (i
.types
[0],
6057 operand_types
[i
.operands
- 1],
6058 i
.types
[i
.operands
- 1],
6061 /* Does not match either direction. */
6064 /* found_reverse_match holds which of D or FloatR
6066 if (!t
->opcode_modifier
.d
)
6067 found_reverse_match
= 0;
6068 else if (operand_types
[0].bitfield
.tbyte
)
6069 found_reverse_match
= Opcode_FloatD
;
6070 else if (operand_types
[0].bitfield
.xmmword
6071 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6072 || operand_types
[0].bitfield
.class == RegMMX
6073 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6074 || is_any_vex_encoding(t
))
6075 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6076 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6078 found_reverse_match
= Opcode_D
;
6079 if (t
->opcode_modifier
.floatr
)
6080 found_reverse_match
|= Opcode_FloatR
;
6084 /* Found a forward 2 operand match here. */
6085 switch (t
->operands
)
6088 overlap4
= operand_type_and (i
.types
[4],
6092 overlap3
= operand_type_and (i
.types
[3],
6096 overlap2
= operand_type_and (i
.types
[2],
6101 switch (t
->operands
)
6104 if (!operand_type_match (overlap4
, i
.types
[4])
6105 || !operand_type_register_match (i
.types
[3],
6112 if (!operand_type_match (overlap3
, i
.types
[3])
6113 || ((check_register
& 0xa) == 0xa
6114 && !operand_type_register_match (i
.types
[1],
6118 || ((check_register
& 0xc) == 0xc
6119 && !operand_type_register_match (i
.types
[2],
6126 /* Here we make use of the fact that there are no
6127 reverse match 3 operand instructions. */
6128 if (!operand_type_match (overlap2
, i
.types
[2])
6129 || ((check_register
& 5) == 5
6130 && !operand_type_register_match (i
.types
[0],
6134 || ((check_register
& 6) == 6
6135 && !operand_type_register_match (i
.types
[1],
6143 /* Found either forward/reverse 2, 3 or 4 operand match here:
6144 slip through to break. */
6147 /* Check if vector and VEX operands are valid. */
6148 if (check_VecOperands (t
) || VEX_check_operands (t
))
6150 specific_error
= i
.error
;
6154 /* We've found a match; break out of loop. */
6158 if (t
== current_templates
->end
)
6160 /* We found no match. */
6161 const char *err_msg
;
6162 switch (specific_error
? specific_error
: i
.error
)
6166 case operand_size_mismatch
:
6167 err_msg
= _("operand size mismatch");
6169 case operand_type_mismatch
:
6170 err_msg
= _("operand type mismatch");
6172 case register_type_mismatch
:
6173 err_msg
= _("register type mismatch");
6175 case number_of_operands_mismatch
:
6176 err_msg
= _("number of operands mismatch");
6178 case invalid_instruction_suffix
:
6179 err_msg
= _("invalid instruction suffix");
6182 err_msg
= _("constant doesn't fit in 4 bits");
6184 case unsupported_with_intel_mnemonic
:
6185 err_msg
= _("unsupported with Intel mnemonic");
6187 case unsupported_syntax
:
6188 err_msg
= _("unsupported syntax");
6191 as_bad (_("unsupported instruction `%s'"),
6192 current_templates
->start
->name
);
6194 case invalid_vsib_address
:
6195 err_msg
= _("invalid VSIB address");
6197 case invalid_vector_register_set
:
6198 err_msg
= _("mask, index, and destination registers must be distinct");
6200 case unsupported_vector_index_register
:
6201 err_msg
= _("unsupported vector index register");
6203 case unsupported_broadcast
:
6204 err_msg
= _("unsupported broadcast");
6206 case broadcast_needed
:
6207 err_msg
= _("broadcast is needed for operand of such type");
6209 case unsupported_masking
:
6210 err_msg
= _("unsupported masking");
6212 case mask_not_on_destination
:
6213 err_msg
= _("mask not on destination operand");
6215 case no_default_mask
:
6216 err_msg
= _("default mask isn't allowed");
6218 case unsupported_rc_sae
:
6219 err_msg
= _("unsupported static rounding/sae");
6221 case rc_sae_operand_not_last_imm
:
6223 err_msg
= _("RC/SAE operand must precede immediate operands");
6225 err_msg
= _("RC/SAE operand must follow immediate operands");
6227 case invalid_register_operand
:
6228 err_msg
= _("invalid register operand");
6231 as_bad (_("%s for `%s'"), err_msg
,
6232 current_templates
->start
->name
);
6236 if (!quiet_warnings
)
6239 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6240 as_warn (_("indirect %s without `*'"), t
->name
);
6242 if (t
->opcode_modifier
.isprefix
6243 && t
->opcode_modifier
.ignoresize
)
6245 /* Warn them that a data or address size prefix doesn't
6246 affect assembly of the next line of code. */
6247 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6251 /* Copy the template we found. */
6254 if (addr_prefix_disp
!= -1)
6255 i
.tm
.operand_types
[addr_prefix_disp
]
6256 = operand_types
[addr_prefix_disp
];
6258 if (found_reverse_match
)
6260 /* If we found a reverse match we must alter the opcode direction
6261 bit and clear/flip the regmem modifier one. found_reverse_match
6262 holds bits to change (different for int & float insns). */
6264 i
.tm
.base_opcode
^= found_reverse_match
;
6266 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6267 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6269 /* Certain SIMD insns have their load forms specified in the opcode
6270 table, and hence we need to _set_ RegMem instead of clearing it.
6271 We need to avoid setting the bit though on insns like KMOVW. */
6272 i
.tm
.opcode_modifier
.regmem
6273 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6274 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6275 && !i
.tm
.opcode_modifier
.regmem
;
6284 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6285 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6287 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6289 as_bad (_("`%s' operand %u must use `%ses' segment"),
6291 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6296 /* There's only ever one segment override allowed per instruction.
6297 This instruction possibly has a legal segment override on the
6298 second operand, so copy the segment to where non-string
6299 instructions store it, allowing common code. */
6300 i
.seg
[op
] = i
.seg
[1];
6306 process_suffix (void)
6308 /* If matched instruction specifies an explicit instruction mnemonic
6310 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6311 i
.suffix
= WORD_MNEM_SUFFIX
;
6312 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6313 i
.suffix
= LONG_MNEM_SUFFIX
;
6314 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6315 i
.suffix
= QWORD_MNEM_SUFFIX
;
6316 else if (i
.reg_operands
6317 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
))
6319 /* If there's no instruction mnemonic suffix we try to invent one
6320 based on GPR operands. */
6323 /* We take i.suffix from the last register operand specified,
6324 Destination register type is more significant than source
6325 register type. crc32 in SSE4.2 prefers source register
6327 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6330 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6331 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6333 if (i
.types
[op
].bitfield
.class != Reg
)
6335 if (i
.types
[op
].bitfield
.byte
)
6336 i
.suffix
= BYTE_MNEM_SUFFIX
;
6337 else if (i
.types
[op
].bitfield
.word
)
6338 i
.suffix
= WORD_MNEM_SUFFIX
;
6339 else if (i
.types
[op
].bitfield
.dword
)
6340 i
.suffix
= LONG_MNEM_SUFFIX
;
6341 else if (i
.types
[op
].bitfield
.qword
)
6342 i
.suffix
= QWORD_MNEM_SUFFIX
;
6348 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6351 && i
.tm
.opcode_modifier
.ignoresize
6352 && i
.tm
.opcode_modifier
.no_bsuf
)
6354 else if (!check_byte_reg ())
6357 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6360 && i
.tm
.opcode_modifier
.ignoresize
6361 && i
.tm
.opcode_modifier
.no_lsuf
6362 && !i
.tm
.opcode_modifier
.todword
6363 && !i
.tm
.opcode_modifier
.toqword
)
6365 else if (!check_long_reg ())
6368 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6371 && i
.tm
.opcode_modifier
.ignoresize
6372 && i
.tm
.opcode_modifier
.no_qsuf
6373 && !i
.tm
.opcode_modifier
.todword
6374 && !i
.tm
.opcode_modifier
.toqword
)
6376 else if (!check_qword_reg ())
6379 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6382 && i
.tm
.opcode_modifier
.ignoresize
6383 && i
.tm
.opcode_modifier
.no_wsuf
)
6385 else if (!check_word_reg ())
6388 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6389 /* Do nothing if the instruction is going to ignore the prefix. */
6394 else if (i
.tm
.opcode_modifier
.defaultsize
&& !i
.suffix
)
6396 i
.suffix
= stackop_size
;
6397 if (stackop_size
== LONG_MNEM_SUFFIX
)
6399 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6400 .code16gcc directive to support 16-bit mode with
6401 32-bit address. For IRET without a suffix, generate
6402 16-bit IRET (opcode 0xcf) to return from an interrupt
6404 if (i
.tm
.base_opcode
== 0xcf)
6406 i
.suffix
= WORD_MNEM_SUFFIX
;
6407 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6409 /* Warn about changed behavior for segment register push/pop. */
6410 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6411 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6416 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6417 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6418 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6419 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6420 && i
.tm
.extension_opcode
<= 3)))
6425 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6427 i
.suffix
= QWORD_MNEM_SUFFIX
;
6432 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6433 i
.suffix
= LONG_MNEM_SUFFIX
;
6436 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6437 i
.suffix
= WORD_MNEM_SUFFIX
;
6443 && (!i
.tm
.opcode_modifier
.defaultsize
6444 /* Also cover lret/retf/iret in 64-bit mode. */
6445 || (flag_code
== CODE_64BIT
6446 && !i
.tm
.opcode_modifier
.no_lsuf
6447 && !i
.tm
.opcode_modifier
.no_qsuf
))
6448 && !i
.tm
.opcode_modifier
.ignoresize
6449 /* Accept FLDENV et al without suffix. */
6450 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6452 unsigned int suffixes
;
6454 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6455 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6457 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6459 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6461 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6463 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6466 /* Are multiple suffixes allowed? */
6467 if (suffixes
& (suffixes
- 1))
6470 && (!i
.tm
.opcode_modifier
.defaultsize
6471 || operand_check
== check_error
))
6473 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6476 if (operand_check
== check_error
)
6478 as_bad (_("no instruction mnemonic suffix given and "
6479 "no register operands; can't size `%s'"), i
.tm
.name
);
6482 if (operand_check
== check_warning
)
6483 as_warn (_("%s; using default for `%s'"),
6485 ? _("ambiguous operand size")
6486 : _("no instruction mnemonic suffix given and "
6487 "no register operands"),
6490 if (i
.tm
.opcode_modifier
.floatmf
)
6491 i
.suffix
= SHORT_MNEM_SUFFIX
;
6492 else if (flag_code
== CODE_16BIT
)
6493 i
.suffix
= WORD_MNEM_SUFFIX
;
6494 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6495 i
.suffix
= LONG_MNEM_SUFFIX
;
6497 i
.suffix
= QWORD_MNEM_SUFFIX
;
6501 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
6502 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
6503 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
6505 /* Change the opcode based on the operand size given by i.suffix. */
6508 /* Size floating point instruction. */
6509 case LONG_MNEM_SUFFIX
:
6510 if (i
.tm
.opcode_modifier
.floatmf
)
6512 i
.tm
.base_opcode
^= 4;
6516 case WORD_MNEM_SUFFIX
:
6517 case QWORD_MNEM_SUFFIX
:
6518 /* It's not a byte, select word/dword operation. */
6519 if (i
.tm
.opcode_modifier
.w
)
6522 i
.tm
.base_opcode
|= 8;
6524 i
.tm
.base_opcode
|= 1;
6527 case SHORT_MNEM_SUFFIX
:
6528 /* Now select between word & dword operations via the operand
6529 size prefix, except for instructions that will ignore this
6531 if (i
.reg_operands
> 0
6532 && i
.types
[0].bitfield
.class == Reg
6533 && i
.tm
.opcode_modifier
.addrprefixopreg
6534 && (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6535 || i
.operands
== 1))
6537 /* The address size override prefix changes the size of the
6539 if ((flag_code
== CODE_32BIT
6540 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6541 || (flag_code
!= CODE_32BIT
6542 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6543 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6546 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6547 && !i
.tm
.opcode_modifier
.ignoresize
6548 && !i
.tm
.opcode_modifier
.floatmf
6549 && !is_any_vex_encoding (&i
.tm
)
6550 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6551 || (flag_code
== CODE_64BIT
6552 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6554 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6556 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6557 prefix
= ADDR_PREFIX_OPCODE
;
6559 if (!add_prefix (prefix
))
6563 /* Set mode64 for an operand. */
6564 if (i
.suffix
== QWORD_MNEM_SUFFIX
6565 && flag_code
== CODE_64BIT
6566 && !i
.tm
.opcode_modifier
.norex64
6567 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6569 && ! (i
.operands
== 2
6570 && i
.tm
.base_opcode
== 0x90
6571 && i
.tm
.extension_opcode
== None
6572 && i
.types
[0].bitfield
.instance
== Accum
6573 && i
.types
[0].bitfield
.qword
6574 && i
.types
[1].bitfield
.instance
== Accum
6575 && i
.types
[1].bitfield
.qword
))
6581 if (i
.reg_operands
!= 0
6583 && i
.tm
.opcode_modifier
.addrprefixopreg
6584 && i
.tm
.operand_types
[0].bitfield
.instance
!= Accum
)
6586 /* Check invalid register operand when the address size override
6587 prefix changes the size of register operands. */
6589 enum { need_word
, need_dword
, need_qword
} need
;
6591 if (flag_code
== CODE_32BIT
)
6592 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6595 if (i
.prefix
[ADDR_PREFIX
])
6598 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6601 for (op
= 0; op
< i
.operands
; op
++)
6602 if (i
.types
[op
].bitfield
.class == Reg
6603 && ((need
== need_word
6604 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6605 || (need
== need_dword
6606 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6607 || (need
== need_qword
6608 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6610 as_bad (_("invalid register operand size for `%s'"),
6620 check_byte_reg (void)
6624 for (op
= i
.operands
; --op
>= 0;)
6626 /* Skip non-register operands. */
6627 if (i
.types
[op
].bitfield
.class != Reg
)
6630 /* If this is an eight bit register, it's OK. If it's the 16 or
6631 32 bit version of an eight bit register, we will just use the
6632 low portion, and that's OK too. */
6633 if (i
.types
[op
].bitfield
.byte
)
6636 /* I/O port address operands are OK too. */
6637 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6638 && i
.tm
.operand_types
[op
].bitfield
.word
)
6641 /* crc32 doesn't generate this warning. */
6642 if (i
.tm
.base_opcode
== 0xf20f38f0)
6645 if ((i
.types
[op
].bitfield
.word
6646 || i
.types
[op
].bitfield
.dword
6647 || i
.types
[op
].bitfield
.qword
)
6648 && i
.op
[op
].regs
->reg_num
< 4
6649 /* Prohibit these changes in 64bit mode, since the lowering
6650 would be more complicated. */
6651 && flag_code
!= CODE_64BIT
)
6653 #if REGISTER_WARNINGS
6654 if (!quiet_warnings
)
6655 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6657 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6658 ? REGNAM_AL
- REGNAM_AX
6659 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6661 i
.op
[op
].regs
->reg_name
,
6666 /* Any other register is bad. */
6667 if (i
.types
[op
].bitfield
.class == Reg
6668 || i
.types
[op
].bitfield
.class == RegMMX
6669 || i
.types
[op
].bitfield
.class == RegSIMD
6670 || i
.types
[op
].bitfield
.class == SReg
6671 || i
.types
[op
].bitfield
.class == RegCR
6672 || i
.types
[op
].bitfield
.class == RegDR
6673 || i
.types
[op
].bitfield
.class == RegTR
)
6675 as_bad (_("`%s%s' not allowed with `%s%c'"),
6677 i
.op
[op
].regs
->reg_name
,
6687 check_long_reg (void)
6691 for (op
= i
.operands
; --op
>= 0;)
6692 /* Skip non-register operands. */
6693 if (i
.types
[op
].bitfield
.class != Reg
)
6695 /* Reject eight bit registers, except where the template requires
6696 them. (eg. movzb) */
6697 else if (i
.types
[op
].bitfield
.byte
6698 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6699 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6700 && (i
.tm
.operand_types
[op
].bitfield
.word
6701 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6703 as_bad (_("`%s%s' not allowed with `%s%c'"),
6705 i
.op
[op
].regs
->reg_name
,
6710 /* Error if the e prefix on a general reg is missing. */
6711 else if (i
.types
[op
].bitfield
.word
6712 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6713 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6714 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6716 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6717 register_prefix
, i
.op
[op
].regs
->reg_name
,
6721 /* Warn if the r prefix on a general reg is present. */
6722 else if (i
.types
[op
].bitfield
.qword
6723 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6724 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6725 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6728 && (i
.tm
.opcode_modifier
.toqword
6729 /* Also convert to QWORD for MOVSXD. */
6730 || i
.tm
.base_opcode
== 0x63)
6731 && i
.types
[0].bitfield
.class != RegSIMD
)
6733 /* Convert to QWORD. We want REX byte. */
6734 i
.suffix
= QWORD_MNEM_SUFFIX
;
6738 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6739 register_prefix
, i
.op
[op
].regs
->reg_name
,
6748 check_qword_reg (void)
6752 for (op
= i
.operands
; --op
>= 0; )
6753 /* Skip non-register operands. */
6754 if (i
.types
[op
].bitfield
.class != Reg
)
6756 /* Reject eight bit registers, except where the template requires
6757 them. (eg. movzb) */
6758 else if (i
.types
[op
].bitfield
.byte
6759 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6760 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6761 && (i
.tm
.operand_types
[op
].bitfield
.word
6762 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6764 as_bad (_("`%s%s' not allowed with `%s%c'"),
6766 i
.op
[op
].regs
->reg_name
,
6771 /* Warn if the r prefix on a general reg is missing. */
6772 else if ((i
.types
[op
].bitfield
.word
6773 || i
.types
[op
].bitfield
.dword
)
6774 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6775 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6776 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6778 /* Prohibit these changes in the 64bit mode, since the
6779 lowering is more complicated. */
6781 && i
.tm
.opcode_modifier
.todword
6782 && i
.types
[0].bitfield
.class != RegSIMD
)
6784 /* Convert to DWORD. We don't want REX byte. */
6785 i
.suffix
= LONG_MNEM_SUFFIX
;
6789 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6790 register_prefix
, i
.op
[op
].regs
->reg_name
,
6799 check_word_reg (void)
6802 for (op
= i
.operands
; --op
>= 0;)
6803 /* Skip non-register operands. */
6804 if (i
.types
[op
].bitfield
.class != Reg
)
6806 /* Reject eight bit registers, except where the template requires
6807 them. (eg. movzb) */
6808 else if (i
.types
[op
].bitfield
.byte
6809 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6810 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6811 && (i
.tm
.operand_types
[op
].bitfield
.word
6812 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6814 as_bad (_("`%s%s' not allowed with `%s%c'"),
6816 i
.op
[op
].regs
->reg_name
,
6821 /* Warn if the e or r prefix on a general reg is present. */
6822 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6823 && (i
.types
[op
].bitfield
.dword
6824 || i
.types
[op
].bitfield
.qword
)
6825 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6826 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6827 && i
.tm
.operand_types
[op
].bitfield
.word
)
6829 /* Prohibit these changes in the 64bit mode, since the
6830 lowering is more complicated. */
6831 if (flag_code
== CODE_64BIT
)
6833 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6834 register_prefix
, i
.op
[op
].regs
->reg_name
,
6838 #if REGISTER_WARNINGS
6839 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6841 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6842 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6849 update_imm (unsigned int j
)
6851 i386_operand_type overlap
= i
.types
[j
];
6852 if ((overlap
.bitfield
.imm8
6853 || overlap
.bitfield
.imm8s
6854 || overlap
.bitfield
.imm16
6855 || overlap
.bitfield
.imm32
6856 || overlap
.bitfield
.imm32s
6857 || overlap
.bitfield
.imm64
)
6858 && !operand_type_equal (&overlap
, &imm8
)
6859 && !operand_type_equal (&overlap
, &imm8s
)
6860 && !operand_type_equal (&overlap
, &imm16
)
6861 && !operand_type_equal (&overlap
, &imm32
)
6862 && !operand_type_equal (&overlap
, &imm32s
)
6863 && !operand_type_equal (&overlap
, &imm64
))
6867 i386_operand_type temp
;
6869 operand_type_set (&temp
, 0);
6870 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6872 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6873 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6875 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6876 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6877 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6879 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6880 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6883 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6886 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6887 || operand_type_equal (&overlap
, &imm16_32
)
6888 || operand_type_equal (&overlap
, &imm16_32s
))
6890 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6895 if (!operand_type_equal (&overlap
, &imm8
)
6896 && !operand_type_equal (&overlap
, &imm8s
)
6897 && !operand_type_equal (&overlap
, &imm16
)
6898 && !operand_type_equal (&overlap
, &imm32
)
6899 && !operand_type_equal (&overlap
, &imm32s
)
6900 && !operand_type_equal (&overlap
, &imm64
))
6902 as_bad (_("no instruction mnemonic suffix given; "
6903 "can't determine immediate size"));
6907 i
.types
[j
] = overlap
;
6917 /* Update the first 2 immediate operands. */
6918 n
= i
.operands
> 2 ? 2 : i
.operands
;
6921 for (j
= 0; j
< n
; j
++)
6922 if (update_imm (j
) == 0)
6925 /* The 3rd operand can't be immediate operand. */
6926 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6933 process_operands (void)
6935 /* Default segment register this instruction will use for memory
6936 accesses. 0 means unknown. This is only for optimizing out
6937 unnecessary segment overrides. */
6938 const seg_entry
*default_seg
= 0;
6940 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6942 unsigned int dupl
= i
.operands
;
6943 unsigned int dest
= dupl
- 1;
6946 /* The destination must be an xmm register. */
6947 gas_assert (i
.reg_operands
6948 && MAX_OPERANDS
> dupl
6949 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6951 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6952 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6954 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6956 /* Keep xmm0 for instructions with VEX prefix and 3
6958 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
6959 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
6964 /* We remove the first xmm0 and keep the number of
6965 operands unchanged, which in fact duplicates the
6967 for (j
= 1; j
< i
.operands
; j
++)
6969 i
.op
[j
- 1] = i
.op
[j
];
6970 i
.types
[j
- 1] = i
.types
[j
];
6971 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6972 i
.flags
[j
- 1] = i
.flags
[j
];
6976 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6978 gas_assert ((MAX_OPERANDS
- 1) > dupl
6979 && (i
.tm
.opcode_modifier
.vexsources
6982 /* Add the implicit xmm0 for instructions with VEX prefix
6984 for (j
= i
.operands
; j
> 0; j
--)
6986 i
.op
[j
] = i
.op
[j
- 1];
6987 i
.types
[j
] = i
.types
[j
- 1];
6988 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6989 i
.flags
[j
] = i
.flags
[j
- 1];
6992 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6993 i
.types
[0] = regxmm
;
6994 i
.tm
.operand_types
[0] = regxmm
;
6997 i
.reg_operands
+= 2;
7002 i
.op
[dupl
] = i
.op
[dest
];
7003 i
.types
[dupl
] = i
.types
[dest
];
7004 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7005 i
.flags
[dupl
] = i
.flags
[dest
];
7014 i
.op
[dupl
] = i
.op
[dest
];
7015 i
.types
[dupl
] = i
.types
[dest
];
7016 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7017 i
.flags
[dupl
] = i
.flags
[dest
];
7020 if (i
.tm
.opcode_modifier
.immext
)
7023 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7024 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7028 for (j
= 1; j
< i
.operands
; j
++)
7030 i
.op
[j
- 1] = i
.op
[j
];
7031 i
.types
[j
- 1] = i
.types
[j
];
7033 /* We need to adjust fields in i.tm since they are used by
7034 build_modrm_byte. */
7035 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7037 i
.flags
[j
- 1] = i
.flags
[j
];
7044 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7046 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7048 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7049 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7050 regnum
= register_number (i
.op
[1].regs
);
7051 first_reg_in_group
= regnum
& ~3;
7052 last_reg_in_group
= first_reg_in_group
+ 3;
7053 if (regnum
!= first_reg_in_group
)
7054 as_warn (_("source register `%s%s' implicitly denotes"
7055 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7056 register_prefix
, i
.op
[1].regs
->reg_name
,
7057 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7058 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7061 else if (i
.tm
.opcode_modifier
.regkludge
)
7063 /* The imul $imm, %reg instruction is converted into
7064 imul $imm, %reg, %reg, and the clr %reg instruction
7065 is converted into xor %reg, %reg. */
7067 unsigned int first_reg_op
;
7069 if (operand_type_check (i
.types
[0], reg
))
7073 /* Pretend we saw the extra register operand. */
7074 gas_assert (i
.reg_operands
== 1
7075 && i
.op
[first_reg_op
+ 1].regs
== 0);
7076 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7077 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7082 if (i
.tm
.opcode_modifier
.modrm
)
7084 /* The opcode is completed (modulo i.tm.extension_opcode which
7085 must be put into the modrm byte). Now, we make the modrm and
7086 index base bytes based on all the info we've collected. */
7088 default_seg
= build_modrm_byte ();
7090 else if (i
.types
[0].bitfield
.class == SReg
)
7092 if (flag_code
!= CODE_64BIT
7093 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7094 && i
.op
[0].regs
->reg_num
== 1
7095 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7096 && i
.op
[0].regs
->reg_num
< 4)
7098 as_bad (_("you can't `%s %s%s'"),
7099 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7102 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7104 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7105 i
.tm
.opcode_length
= 2;
7107 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7109 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7113 else if (i
.tm
.opcode_modifier
.isstring
)
7115 /* For the string instructions that allow a segment override
7116 on one of their operands, the default segment is ds. */
7119 else if (i
.short_form
)
7121 /* The register or float register operand is in operand
7123 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7125 /* Register goes in low 3 bits of opcode. */
7126 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7127 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7129 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7131 /* Warn about some common errors, but press on regardless.
7132 The first case can be generated by gcc (<= 2.8.1). */
7133 if (i
.operands
== 2)
7135 /* Reversed arguments on faddp, fsubp, etc. */
7136 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7137 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7138 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7142 /* Extraneous `l' suffix on fp insn. */
7143 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7144 register_prefix
, i
.op
[0].regs
->reg_name
);
7149 if (i
.tm
.base_opcode
== 0x8d /* lea */
7152 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7154 /* If a segment was explicitly specified, and the specified segment
7155 is not the default, use an opcode prefix to select it. If we
7156 never figured out what the default segment is, then default_seg
7157 will be zero at this point, and the specified segment prefix will
7159 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7161 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7167 static const seg_entry
*
7168 build_modrm_byte (void)
7170 const seg_entry
*default_seg
= 0;
7171 unsigned int source
, dest
;
7174 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7177 unsigned int nds
, reg_slot
;
7180 dest
= i
.operands
- 1;
7183 /* There are 2 kinds of instructions:
7184 1. 5 operands: 4 register operands or 3 register operands
7185 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7186 VexW0 or VexW1. The destination must be either XMM, YMM or
7188 2. 4 operands: 4 register operands or 3 register operands
7189 plus 1 memory operand, with VexXDS. */
7190 gas_assert ((i
.reg_operands
== 4
7191 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7192 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7193 && i
.tm
.opcode_modifier
.vexw
7194 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7196 /* If VexW1 is set, the first non-immediate operand is the source and
7197 the second non-immediate one is encoded in the immediate operand. */
7198 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7200 source
= i
.imm_operands
;
7201 reg_slot
= i
.imm_operands
+ 1;
7205 source
= i
.imm_operands
+ 1;
7206 reg_slot
= i
.imm_operands
;
7209 if (i
.imm_operands
== 0)
7211 /* When there is no immediate operand, generate an 8bit
7212 immediate operand to encode the first operand. */
7213 exp
= &im_expressions
[i
.imm_operands
++];
7214 i
.op
[i
.operands
].imms
= exp
;
7215 i
.types
[i
.operands
] = imm8
;
7218 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7219 exp
->X_op
= O_constant
;
7220 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7221 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7225 gas_assert (i
.imm_operands
== 1);
7226 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7227 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7229 /* Turn on Imm8 again so that output_imm will generate it. */
7230 i
.types
[0].bitfield
.imm8
= 1;
7232 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7233 i
.op
[0].imms
->X_add_number
7234 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7235 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7238 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7239 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7244 /* i.reg_operands MUST be the number of real register operands;
7245 implicit registers do not count. If there are 3 register
7246 operands, it must be a instruction with VexNDS. For a
7247 instruction with VexNDD, the destination register is encoded
7248 in VEX prefix. If there are 4 register operands, it must be
7249 a instruction with VEX prefix and 3 sources. */
7250 if (i
.mem_operands
== 0
7251 && ((i
.reg_operands
== 2
7252 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7253 || (i
.reg_operands
== 3
7254 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7255 || (i
.reg_operands
== 4 && vex_3_sources
)))
7263 /* When there are 3 operands, one of them may be immediate,
7264 which may be the first or the last operand. Otherwise,
7265 the first operand must be shift count register (cl) or it
7266 is an instruction with VexNDS. */
7267 gas_assert (i
.imm_operands
== 1
7268 || (i
.imm_operands
== 0
7269 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7270 || (i
.types
[0].bitfield
.instance
== RegC
7271 && i
.types
[0].bitfield
.byte
))));
7272 if (operand_type_check (i
.types
[0], imm
)
7273 || (i
.types
[0].bitfield
.instance
== RegC
7274 && i
.types
[0].bitfield
.byte
))
7280 /* When there are 4 operands, the first two must be 8bit
7281 immediate operands. The source operand will be the 3rd
7284 For instructions with VexNDS, if the first operand
7285 an imm8, the source operand is the 2nd one. If the last
7286 operand is imm8, the source operand is the first one. */
7287 gas_assert ((i
.imm_operands
== 2
7288 && i
.types
[0].bitfield
.imm8
7289 && i
.types
[1].bitfield
.imm8
)
7290 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7291 && i
.imm_operands
== 1
7292 && (i
.types
[0].bitfield
.imm8
7293 || i
.types
[i
.operands
- 1].bitfield
.imm8
7295 if (i
.imm_operands
== 2)
7299 if (i
.types
[0].bitfield
.imm8
)
7306 if (is_evex_encoding (&i
.tm
))
7308 /* For EVEX instructions, when there are 5 operands, the
7309 first one must be immediate operand. If the second one
7310 is immediate operand, the source operand is the 3th
7311 one. If the last one is immediate operand, the source
7312 operand is the 2nd one. */
7313 gas_assert (i
.imm_operands
== 2
7314 && i
.tm
.opcode_modifier
.sae
7315 && operand_type_check (i
.types
[0], imm
));
7316 if (operand_type_check (i
.types
[1], imm
))
7318 else if (operand_type_check (i
.types
[4], imm
))
7332 /* RC/SAE operand could be between DEST and SRC. That happens
7333 when one operand is GPR and the other one is XMM/YMM/ZMM
7335 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7338 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7340 /* For instructions with VexNDS, the register-only source
7341 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7342 register. It is encoded in VEX prefix. */
7344 i386_operand_type op
;
7347 /* Check register-only source operand when two source
7348 operands are swapped. */
7349 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7350 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7358 op
= i
.tm
.operand_types
[vvvv
];
7359 if ((dest
+ 1) >= i
.operands
7360 || ((op
.bitfield
.class != Reg
7361 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7362 && op
.bitfield
.class != RegSIMD
7363 && !operand_type_equal (&op
, ®mask
)))
7365 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7371 /* One of the register operands will be encoded in the i.rm.reg
7372 field, the other in the combined i.rm.mode and i.rm.regmem
7373 fields. If no form of this instruction supports a memory
7374 destination operand, then we assume the source operand may
7375 sometimes be a memory operand and so we need to store the
7376 destination in the i.rm.reg field. */
7377 if (!i
.tm
.opcode_modifier
.regmem
7378 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7380 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7381 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7382 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7383 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7384 i
.has_regmmx
= TRUE
;
7385 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7386 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7388 if (i
.types
[dest
].bitfield
.zmmword
7389 || i
.types
[source
].bitfield
.zmmword
)
7390 i
.has_regzmm
= TRUE
;
7391 else if (i
.types
[dest
].bitfield
.ymmword
7392 || i
.types
[source
].bitfield
.ymmword
)
7393 i
.has_regymm
= TRUE
;
7395 i
.has_regxmm
= TRUE
;
7397 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7399 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7401 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7403 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7408 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7409 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7410 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7412 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7414 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7416 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7419 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7421 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7424 add_prefix (LOCK_PREFIX_OPCODE
);
7428 { /* If it's not 2 reg operands... */
7433 unsigned int fake_zero_displacement
= 0;
7436 for (op
= 0; op
< i
.operands
; op
++)
7437 if (i
.flags
[op
] & Operand_Mem
)
7439 gas_assert (op
< i
.operands
);
7441 if (i
.tm
.opcode_modifier
.vecsib
)
7443 if (i
.index_reg
->reg_num
== RegIZ
)
7446 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7449 i
.sib
.base
= NO_BASE_REGISTER
;
7450 i
.sib
.scale
= i
.log2_scale_factor
;
7451 i
.types
[op
].bitfield
.disp8
= 0;
7452 i
.types
[op
].bitfield
.disp16
= 0;
7453 i
.types
[op
].bitfield
.disp64
= 0;
7454 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7456 /* Must be 32 bit */
7457 i
.types
[op
].bitfield
.disp32
= 1;
7458 i
.types
[op
].bitfield
.disp32s
= 0;
7462 i
.types
[op
].bitfield
.disp32
= 0;
7463 i
.types
[op
].bitfield
.disp32s
= 1;
7466 i
.sib
.index
= i
.index_reg
->reg_num
;
7467 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7469 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7475 if (i
.base_reg
== 0)
7478 if (!i
.disp_operands
)
7479 fake_zero_displacement
= 1;
7480 if (i
.index_reg
== 0)
7482 i386_operand_type newdisp
;
7484 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7485 /* Operand is just <disp> */
7486 if (flag_code
== CODE_64BIT
)
7488 /* 64bit mode overwrites the 32bit absolute
7489 addressing by RIP relative addressing and
7490 absolute addressing is encoded by one of the
7491 redundant SIB forms. */
7492 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7493 i
.sib
.base
= NO_BASE_REGISTER
;
7494 i
.sib
.index
= NO_INDEX_REGISTER
;
7495 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7497 else if ((flag_code
== CODE_16BIT
)
7498 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7500 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7505 i
.rm
.regmem
= NO_BASE_REGISTER
;
7508 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7509 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7511 else if (!i
.tm
.opcode_modifier
.vecsib
)
7513 /* !i.base_reg && i.index_reg */
7514 if (i
.index_reg
->reg_num
== RegIZ
)
7515 i
.sib
.index
= NO_INDEX_REGISTER
;
7517 i
.sib
.index
= i
.index_reg
->reg_num
;
7518 i
.sib
.base
= NO_BASE_REGISTER
;
7519 i
.sib
.scale
= i
.log2_scale_factor
;
7520 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7521 i
.types
[op
].bitfield
.disp8
= 0;
7522 i
.types
[op
].bitfield
.disp16
= 0;
7523 i
.types
[op
].bitfield
.disp64
= 0;
7524 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7526 /* Must be 32 bit */
7527 i
.types
[op
].bitfield
.disp32
= 1;
7528 i
.types
[op
].bitfield
.disp32s
= 0;
7532 i
.types
[op
].bitfield
.disp32
= 0;
7533 i
.types
[op
].bitfield
.disp32s
= 1;
7535 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7539 /* RIP addressing for 64bit mode. */
7540 else if (i
.base_reg
->reg_num
== RegIP
)
7542 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7543 i
.rm
.regmem
= NO_BASE_REGISTER
;
7544 i
.types
[op
].bitfield
.disp8
= 0;
7545 i
.types
[op
].bitfield
.disp16
= 0;
7546 i
.types
[op
].bitfield
.disp32
= 0;
7547 i
.types
[op
].bitfield
.disp32s
= 1;
7548 i
.types
[op
].bitfield
.disp64
= 0;
7549 i
.flags
[op
] |= Operand_PCrel
;
7550 if (! i
.disp_operands
)
7551 fake_zero_displacement
= 1;
7553 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7555 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7556 switch (i
.base_reg
->reg_num
)
7559 if (i
.index_reg
== 0)
7561 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7562 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7566 if (i
.index_reg
== 0)
7569 if (operand_type_check (i
.types
[op
], disp
) == 0)
7571 /* fake (%bp) into 0(%bp) */
7572 i
.types
[op
].bitfield
.disp8
= 1;
7573 fake_zero_displacement
= 1;
7576 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7577 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7579 default: /* (%si) -> 4 or (%di) -> 5 */
7580 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7582 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7584 else /* i.base_reg and 32/64 bit mode */
7586 if (flag_code
== CODE_64BIT
7587 && operand_type_check (i
.types
[op
], disp
))
7589 i
.types
[op
].bitfield
.disp16
= 0;
7590 i
.types
[op
].bitfield
.disp64
= 0;
7591 if (i
.prefix
[ADDR_PREFIX
] == 0)
7593 i
.types
[op
].bitfield
.disp32
= 0;
7594 i
.types
[op
].bitfield
.disp32s
= 1;
7598 i
.types
[op
].bitfield
.disp32
= 1;
7599 i
.types
[op
].bitfield
.disp32s
= 0;
7603 if (!i
.tm
.opcode_modifier
.vecsib
)
7604 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7605 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7607 i
.sib
.base
= i
.base_reg
->reg_num
;
7608 /* x86-64 ignores REX prefix bit here to avoid decoder
7610 if (!(i
.base_reg
->reg_flags
& RegRex
)
7611 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7612 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7614 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7616 fake_zero_displacement
= 1;
7617 i
.types
[op
].bitfield
.disp8
= 1;
7619 i
.sib
.scale
= i
.log2_scale_factor
;
7620 if (i
.index_reg
== 0)
7622 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7623 /* <disp>(%esp) becomes two byte modrm with no index
7624 register. We've already stored the code for esp
7625 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7626 Any base register besides %esp will not use the
7627 extra modrm byte. */
7628 i
.sib
.index
= NO_INDEX_REGISTER
;
7630 else if (!i
.tm
.opcode_modifier
.vecsib
)
7632 if (i
.index_reg
->reg_num
== RegIZ
)
7633 i
.sib
.index
= NO_INDEX_REGISTER
;
7635 i
.sib
.index
= i
.index_reg
->reg_num
;
7636 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7637 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7642 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7643 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7647 if (!fake_zero_displacement
7651 fake_zero_displacement
= 1;
7652 if (i
.disp_encoding
== disp_encoding_8bit
)
7653 i
.types
[op
].bitfield
.disp8
= 1;
7655 i
.types
[op
].bitfield
.disp32
= 1;
7657 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7661 if (fake_zero_displacement
)
7663 /* Fakes a zero displacement assuming that i.types[op]
7664 holds the correct displacement size. */
7667 gas_assert (i
.op
[op
].disps
== 0);
7668 exp
= &disp_expressions
[i
.disp_operands
++];
7669 i
.op
[op
].disps
= exp
;
7670 exp
->X_op
= O_constant
;
7671 exp
->X_add_number
= 0;
7672 exp
->X_add_symbol
= (symbolS
*) 0;
7673 exp
->X_op_symbol
= (symbolS
*) 0;
7681 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7683 if (operand_type_check (i
.types
[0], imm
))
7684 i
.vex
.register_specifier
= NULL
;
7687 /* VEX.vvvv encodes one of the sources when the first
7688 operand is not an immediate. */
7689 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7690 i
.vex
.register_specifier
= i
.op
[0].regs
;
7692 i
.vex
.register_specifier
= i
.op
[1].regs
;
7695 /* Destination is a XMM register encoded in the ModRM.reg
7697 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7698 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7701 /* ModRM.rm and VEX.B encodes the other source. */
7702 if (!i
.mem_operands
)
7706 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7707 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7709 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7711 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7715 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7717 i
.vex
.register_specifier
= i
.op
[2].regs
;
7718 if (!i
.mem_operands
)
7721 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7722 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7726 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7727 (if any) based on i.tm.extension_opcode. Again, we must be
7728 careful to make sure that segment/control/debug/test/MMX
7729 registers are coded into the i.rm.reg field. */
7730 else if (i
.reg_operands
)
7733 unsigned int vex_reg
= ~0;
7735 for (op
= 0; op
< i
.operands
; op
++)
7737 if (i
.types
[op
].bitfield
.class == Reg
7738 || i
.types
[op
].bitfield
.class == RegBND
7739 || i
.types
[op
].bitfield
.class == RegMask
7740 || i
.types
[op
].bitfield
.class == SReg
7741 || i
.types
[op
].bitfield
.class == RegCR
7742 || i
.types
[op
].bitfield
.class == RegDR
7743 || i
.types
[op
].bitfield
.class == RegTR
)
7745 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7747 if (i
.types
[op
].bitfield
.zmmword
)
7748 i
.has_regzmm
= TRUE
;
7749 else if (i
.types
[op
].bitfield
.ymmword
)
7750 i
.has_regymm
= TRUE
;
7752 i
.has_regxmm
= TRUE
;
7755 if (i
.types
[op
].bitfield
.class == RegMMX
)
7757 i
.has_regmmx
= TRUE
;
7764 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7766 /* For instructions with VexNDS, the register-only
7767 source operand is encoded in VEX prefix. */
7768 gas_assert (mem
!= (unsigned int) ~0);
7773 gas_assert (op
< i
.operands
);
7777 /* Check register-only source operand when two source
7778 operands are swapped. */
7779 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7780 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7784 gas_assert (mem
== (vex_reg
+ 1)
7785 && op
< i
.operands
);
7790 gas_assert (vex_reg
< i
.operands
);
7794 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7796 /* For instructions with VexNDD, the register destination
7797 is encoded in VEX prefix. */
7798 if (i
.mem_operands
== 0)
7800 /* There is no memory operand. */
7801 gas_assert ((op
+ 2) == i
.operands
);
7806 /* There are only 2 non-immediate operands. */
7807 gas_assert (op
< i
.imm_operands
+ 2
7808 && i
.operands
== i
.imm_operands
+ 2);
7809 vex_reg
= i
.imm_operands
+ 1;
7813 gas_assert (op
< i
.operands
);
7815 if (vex_reg
!= (unsigned int) ~0)
7817 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7819 if ((type
->bitfield
.class != Reg
7820 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7821 && type
->bitfield
.class != RegSIMD
7822 && !operand_type_equal (type
, ®mask
))
7825 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7828 /* Don't set OP operand twice. */
7831 /* If there is an extension opcode to put here, the
7832 register number must be put into the regmem field. */
7833 if (i
.tm
.extension_opcode
!= None
)
7835 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7836 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7838 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7843 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7844 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7846 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7851 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7852 must set it to 3 to indicate this is a register operand
7853 in the regmem field. */
7854 if (!i
.mem_operands
)
7858 /* Fill in i.rm.reg field with extension opcode (if any). */
7859 if (i
.tm
.extension_opcode
!= None
)
7860 i
.rm
.reg
= i
.tm
.extension_opcode
;
7866 flip_code16 (unsigned int code16
)
7868 gas_assert (i
.tm
.operands
== 1);
7870 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
7871 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
7872 || i
.tm
.operand_types
[0].bitfield
.disp32s
7873 : i
.tm
.operand_types
[0].bitfield
.disp16
)
7878 output_branch (void)
7884 relax_substateT subtype
;
7888 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7889 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7892 if (i
.prefix
[DATA_PREFIX
] != 0)
7896 code16
^= flip_code16(code16
);
7898 /* Pentium4 branch hints. */
7899 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7900 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7905 if (i
.prefix
[REX_PREFIX
] != 0)
7911 /* BND prefixed jump. */
7912 if (i
.prefix
[BND_PREFIX
] != 0)
7918 if (i
.prefixes
!= 0)
7919 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
7921 /* It's always a symbol; End frag & setup for relax.
7922 Make sure there is enough room in this frag for the largest
7923 instruction we may generate in md_convert_frag. This is 2
7924 bytes for the opcode and room for the prefix and largest
7926 frag_grow (prefix
+ 2 + 4);
7927 /* Prefix and 1 opcode byte go in fr_fix. */
7928 p
= frag_more (prefix
+ 1);
7929 if (i
.prefix
[DATA_PREFIX
] != 0)
7930 *p
++ = DATA_PREFIX_OPCODE
;
7931 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7932 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7933 *p
++ = i
.prefix
[SEG_PREFIX
];
7934 if (i
.prefix
[BND_PREFIX
] != 0)
7935 *p
++ = BND_PREFIX_OPCODE
;
7936 if (i
.prefix
[REX_PREFIX
] != 0)
7937 *p
++ = i
.prefix
[REX_PREFIX
];
7938 *p
= i
.tm
.base_opcode
;
7940 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7941 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7942 else if (cpu_arch_flags
.bitfield
.cpui386
)
7943 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7945 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7948 sym
= i
.op
[0].disps
->X_add_symbol
;
7949 off
= i
.op
[0].disps
->X_add_number
;
7951 if (i
.op
[0].disps
->X_op
!= O_constant
7952 && i
.op
[0].disps
->X_op
!= O_symbol
)
7954 /* Handle complex expressions. */
7955 sym
= make_expr_symbol (i
.op
[0].disps
);
7959 /* 1 possible extra opcode + 4 byte displacement go in var part.
7960 Pass reloc in fr_var. */
7961 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7964 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7965 /* Return TRUE iff PLT32 relocation should be used for branching to
7969 need_plt32_p (symbolS
*s
)
7971 /* PLT32 relocation is ELF only. */
7976 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7977 krtld support it. */
7981 /* Since there is no need to prepare for PLT branch on x86-64, we
7982 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7983 be used as a marker for 32-bit PC-relative branches. */
7987 /* Weak or undefined symbol need PLT32 relocation. */
7988 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7991 /* Non-global symbol doesn't need PLT32 relocation. */
7992 if (! S_IS_EXTERNAL (s
))
7995 /* Other global symbols need PLT32 relocation. NB: Symbol with
7996 non-default visibilities are treated as normal global symbol
7997 so that PLT32 relocation can be used as a marker for 32-bit
7998 PC-relative branches. It is useful for linker relaxation. */
8009 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8011 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8013 /* This is a loop or jecxz type instruction. */
8015 if (i
.prefix
[ADDR_PREFIX
] != 0)
8017 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8020 /* Pentium4 branch hints. */
8021 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8022 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8024 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8033 if (flag_code
== CODE_16BIT
)
8036 if (i
.prefix
[DATA_PREFIX
] != 0)
8038 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8040 code16
^= flip_code16(code16
);
8048 /* BND prefixed jump. */
8049 if (i
.prefix
[BND_PREFIX
] != 0)
8051 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8055 if (i
.prefix
[REX_PREFIX
] != 0)
8057 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8061 if (i
.prefixes
!= 0)
8062 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8064 p
= frag_more (i
.tm
.opcode_length
+ size
);
8065 switch (i
.tm
.opcode_length
)
8068 *p
++ = i
.tm
.base_opcode
>> 8;
8071 *p
++ = i
.tm
.base_opcode
;
8077 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8079 && jump_reloc
== NO_RELOC
8080 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8081 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8084 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8086 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8087 i
.op
[0].disps
, 1, jump_reloc
);
8089 /* All jumps handled here are signed, but don't use a signed limit
8090 check for 32 and 16 bit jumps as we want to allow wrap around at
8091 4G and 64k respectively. */
8093 fixP
->fx_signed
= 1;
8097 output_interseg_jump (void)
8105 if (flag_code
== CODE_16BIT
)
8109 if (i
.prefix
[DATA_PREFIX
] != 0)
8116 gas_assert (!i
.prefix
[REX_PREFIX
]);
8122 if (i
.prefixes
!= 0)
8123 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8125 /* 1 opcode; 2 segment; offset */
8126 p
= frag_more (prefix
+ 1 + 2 + size
);
8128 if (i
.prefix
[DATA_PREFIX
] != 0)
8129 *p
++ = DATA_PREFIX_OPCODE
;
8131 if (i
.prefix
[REX_PREFIX
] != 0)
8132 *p
++ = i
.prefix
[REX_PREFIX
];
8134 *p
++ = i
.tm
.base_opcode
;
8135 if (i
.op
[1].imms
->X_op
== O_constant
)
8137 offsetT n
= i
.op
[1].imms
->X_add_number
;
8140 && !fits_in_unsigned_word (n
)
8141 && !fits_in_signed_word (n
))
8143 as_bad (_("16-bit jump out of range"));
8146 md_number_to_chars (p
, n
, size
);
8149 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8150 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8151 if (i
.op
[0].imms
->X_op
!= O_constant
)
8152 as_bad (_("can't handle non absolute segment in `%s'"),
8154 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8157 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8162 asection
*seg
= now_seg
;
8163 subsegT subseg
= now_subseg
;
8165 unsigned int alignment
, align_size_1
;
8166 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8167 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8168 unsigned int padding
;
8170 if (!IS_ELF
|| !x86_used_note
)
8173 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8175 /* The .note.gnu.property section layout:
8177 Field Length Contents
8180 n_descsz 4 The note descriptor size
8181 n_type 4 NT_GNU_PROPERTY_TYPE_0
8183 n_desc n_descsz The program property array
8187 /* Create the .note.gnu.property section. */
8188 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8189 bfd_set_section_flags (sec
,
8196 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8207 bfd_set_section_alignment (sec
, alignment
);
8208 elf_section_type (sec
) = SHT_NOTE
;
8210 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8212 isa_1_descsz_raw
= 4 + 4 + 4;
8213 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8214 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8216 feature_2_descsz_raw
= isa_1_descsz
;
8217 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8219 feature_2_descsz_raw
+= 4 + 4 + 4;
8220 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8221 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8224 descsz
= feature_2_descsz
;
8225 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8226 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8228 /* Write n_namsz. */
8229 md_number_to_chars (p
, (valueT
) 4, 4);
8231 /* Write n_descsz. */
8232 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8235 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8238 memcpy (p
+ 4 * 3, "GNU", 4);
8240 /* Write 4-byte type. */
8241 md_number_to_chars (p
+ 4 * 4,
8242 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8244 /* Write 4-byte data size. */
8245 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8247 /* Write 4-byte data. */
8248 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8250 /* Zero out paddings. */
8251 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8253 memset (p
+ 4 * 7, 0, padding
);
8255 /* Write 4-byte type. */
8256 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8257 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8259 /* Write 4-byte data size. */
8260 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8262 /* Write 4-byte data. */
8263 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8264 (valueT
) x86_feature_2_used
, 4);
8266 /* Zero out paddings. */
8267 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8269 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8271 /* We probably can't restore the current segment, for there likely
8274 subseg_set (seg
, subseg
);
8279 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8280 const char *frag_now_ptr
)
8282 unsigned int len
= 0;
8284 if (start_frag
!= frag_now
)
8286 const fragS
*fr
= start_frag
;
8291 } while (fr
&& fr
!= frag_now
);
8294 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8297 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8298 be macro-fused with conditional jumps. */
8301 maybe_fused_with_jcc_p (void)
8303 /* No RIP address. */
8304 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8307 /* No VEX/EVEX encoding. */
8308 if (is_any_vex_encoding (&i
.tm
))
8311 /* and, add, sub with destination register. */
8312 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8313 || i
.tm
.base_opcode
<= 5
8314 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8315 || ((i
.tm
.base_opcode
| 3) == 0x83
8316 && ((i
.tm
.extension_opcode
| 1) == 0x5
8317 || i
.tm
.extension_opcode
== 0x0)))
8318 return (i
.types
[1].bitfield
.class == Reg
8319 || i
.types
[1].bitfield
.instance
== Accum
);
8321 /* test, cmp with any register. */
8322 if ((i
.tm
.base_opcode
| 1) == 0x85
8323 || (i
.tm
.base_opcode
| 1) == 0xa9
8324 || ((i
.tm
.base_opcode
| 1) == 0xf7
8325 && i
.tm
.extension_opcode
== 0)
8326 || (i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8327 || ((i
.tm
.base_opcode
| 3) == 0x83
8328 && (i
.tm
.extension_opcode
== 0x7)))
8329 return (i
.types
[0].bitfield
.class == Reg
8330 || i
.types
[0].bitfield
.instance
== Accum
8331 || i
.types
[1].bitfield
.class == Reg
8332 || i
.types
[1].bitfield
.instance
== Accum
);
8334 /* inc, dec with any register. */
8335 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8336 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8337 || ((i
.tm
.base_opcode
| 1) == 0xff
8338 && i
.tm
.extension_opcode
<= 0x1))
8339 return (i
.types
[0].bitfield
.class == Reg
8340 || i
.types
[0].bitfield
.instance
== Accum
);
8345 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8348 add_fused_jcc_padding_frag_p (void)
8350 /* NB: Don't work with COND_JUMP86 without i386. */
8351 if (!align_branch_power
8352 || now_seg
== absolute_section
8353 || !cpu_arch_flags
.bitfield
.cpui386
8354 || !(align_branch
& align_branch_fused_bit
))
8357 if (maybe_fused_with_jcc_p ())
8359 if (last_insn
.kind
== last_insn_other
8360 || last_insn
.seg
!= now_seg
)
8363 as_warn_where (last_insn
.file
, last_insn
.line
,
8364 _("`%s` skips -malign-branch-boundary on `%s`"),
8365 last_insn
.name
, i
.tm
.name
);
8371 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8374 add_branch_prefix_frag_p (void)
8376 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8377 to PadLock instructions since they include prefixes in opcode. */
8378 if (!align_branch_power
8379 || !align_branch_prefix_size
8380 || now_seg
== absolute_section
8381 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8382 || !cpu_arch_flags
.bitfield
.cpui386
)
8385 /* Don't add prefix if it is a prefix or there is no operand in case
8386 that segment prefix is special. */
8387 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8390 if (last_insn
.kind
== last_insn_other
8391 || last_insn
.seg
!= now_seg
)
8395 as_warn_where (last_insn
.file
, last_insn
.line
,
8396 _("`%s` skips -malign-branch-boundary on `%s`"),
8397 last_insn
.name
, i
.tm
.name
);
8402 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8405 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
)
8409 /* NB: Don't work with COND_JUMP86 without i386. */
8410 if (!align_branch_power
8411 || now_seg
== absolute_section
8412 || !cpu_arch_flags
.bitfield
.cpui386
)
8417 /* Check for jcc and direct jmp. */
8418 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8420 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8422 *branch_p
= align_branch_jmp
;
8423 add_padding
= align_branch
& align_branch_jmp_bit
;
8427 *branch_p
= align_branch_jcc
;
8428 if ((align_branch
& align_branch_jcc_bit
))
8432 else if (is_any_vex_encoding (&i
.tm
))
8434 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8437 *branch_p
= align_branch_ret
;
8438 if ((align_branch
& align_branch_ret_bit
))
8443 /* Check for indirect jmp, direct and indirect calls. */
8444 if (i
.tm
.base_opcode
== 0xe8)
8447 *branch_p
= align_branch_call
;
8448 if ((align_branch
& align_branch_call_bit
))
8451 else if (i
.tm
.base_opcode
== 0xff
8452 && (i
.tm
.extension_opcode
== 2
8453 || i
.tm
.extension_opcode
== 4))
8455 /* Indirect call and jmp. */
8456 *branch_p
= align_branch_indirect
;
8457 if ((align_branch
& align_branch_indirect_bit
))
8464 && (i
.op
[0].disps
->X_op
== O_symbol
8465 || (i
.op
[0].disps
->X_op
== O_subtract
8466 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8468 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8469 /* No padding to call to global or undefined tls_get_addr. */
8470 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8471 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8477 && last_insn
.kind
!= last_insn_other
8478 && last_insn
.seg
== now_seg
)
8481 as_warn_where (last_insn
.file
, last_insn
.line
,
8482 _("`%s` skips -malign-branch-boundary on `%s`"),
8483 last_insn
.name
, i
.tm
.name
);
8493 fragS
*insn_start_frag
;
8494 offsetT insn_start_off
;
8495 fragS
*fragP
= NULL
;
8496 enum align_branch_kind branch
= align_branch_none
;
8498 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8499 if (IS_ELF
&& x86_used_note
)
8501 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8502 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8503 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8504 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8505 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8506 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8507 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8508 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8509 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8510 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8511 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8512 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8513 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8514 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8515 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8516 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8517 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8518 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8519 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8520 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8521 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8522 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8523 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8524 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8525 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8526 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8527 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8528 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8529 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8530 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8531 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8532 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8533 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8534 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8535 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8536 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8537 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8538 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8539 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8540 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8541 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8542 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8543 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8544 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8545 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8546 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8547 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8548 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8549 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8550 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8552 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8553 || i
.tm
.cpu_flags
.bitfield
.cpu287
8554 || i
.tm
.cpu_flags
.bitfield
.cpu387
8555 || i
.tm
.cpu_flags
.bitfield
.cpu687
8556 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8557 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8559 || i
.tm
.base_opcode
== 0xf77 /* emms */
8560 || i
.tm
.base_opcode
== 0xf0e /* femms */)
8561 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8563 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8565 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8567 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8568 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8569 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8570 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8571 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8572 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8573 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8574 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8575 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8579 /* Tie dwarf2 debug info to the address at the start of the insn.
8580 We can't do this after the insn has been output as the current
8581 frag may have been closed off. eg. by frag_var. */
8582 dwarf2_emit_insn (0);
8584 insn_start_frag
= frag_now
;
8585 insn_start_off
= frag_now_fix ();
8587 if (add_branch_padding_frag_p (&branch
))
8590 /* Branch can be 8 bytes. Leave some room for prefixes. */
8591 unsigned int max_branch_padding_size
= 14;
8593 /* Align section to boundary. */
8594 record_alignment (now_seg
, align_branch_power
);
8596 /* Make room for padding. */
8597 frag_grow (max_branch_padding_size
);
8599 /* Start of the padding. */
8604 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
8605 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
8608 fragP
->tc_frag_data
.branch_type
= branch
;
8609 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
8613 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8615 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8616 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8618 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8619 output_interseg_jump ();
8622 /* Output normal instructions here. */
8626 unsigned int prefix
;
8629 && (i
.tm
.base_opcode
== 0xfaee8
8630 || i
.tm
.base_opcode
== 0xfaef0
8631 || i
.tm
.base_opcode
== 0xfaef8))
8633 /* Encode lfence, mfence, and sfence as
8634 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8635 offsetT val
= 0x240483f0ULL
;
8637 md_number_to_chars (p
, val
, 5);
8641 /* Some processors fail on LOCK prefix. This options makes
8642 assembler ignore LOCK prefix and serves as a workaround. */
8643 if (omit_lock_prefix
)
8645 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8647 i
.prefix
[LOCK_PREFIX
] = 0;
8651 /* Skip if this is a branch. */
8653 else if (add_fused_jcc_padding_frag_p ())
8655 /* Make room for padding. */
8656 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
8661 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
8662 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
8665 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
8666 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
8668 else if (add_branch_prefix_frag_p ())
8670 unsigned int max_prefix_size
= align_branch_prefix_size
;
8672 /* Make room for padding. */
8673 frag_grow (max_prefix_size
);
8678 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
8679 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
8682 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
8685 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8686 don't need the explicit prefix. */
8687 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8689 switch (i
.tm
.opcode_length
)
8692 if (i
.tm
.base_opcode
& 0xff000000)
8694 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8695 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8696 || prefix
!= REPE_PREFIX_OPCODE
8697 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8698 add_prefix (prefix
);
8702 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8704 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8705 add_prefix (prefix
);
8711 /* Check for pseudo prefixes. */
8712 as_bad_where (insn_start_frag
->fr_file
,
8713 insn_start_frag
->fr_line
,
8714 _("pseudo prefix without instruction"));
8720 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8721 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8722 R_X86_64_GOTTPOFF relocation so that linker can safely
8723 perform IE->LE optimization. A dummy REX_OPCODE prefix
8724 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
8725 relocation for GDesc -> IE/LE optimization. */
8726 if (x86_elf_abi
== X86_64_X32_ABI
8728 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8729 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
8730 && i
.prefix
[REX_PREFIX
] == 0)
8731 add_prefix (REX_OPCODE
);
8734 /* The prefix bytes. */
8735 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8737 FRAG_APPEND_1_CHAR (*q
);
8741 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8746 /* REX byte is encoded in VEX prefix. */
8750 FRAG_APPEND_1_CHAR (*q
);
8753 /* There should be no other prefixes for instructions
8758 /* For EVEX instructions i.vrex should become 0 after
8759 build_evex_prefix. For VEX instructions upper 16 registers
8760 aren't available, so VREX should be 0. */
8763 /* Now the VEX prefix. */
8764 p
= frag_more (i
.vex
.length
);
8765 for (j
= 0; j
< i
.vex
.length
; j
++)
8766 p
[j
] = i
.vex
.bytes
[j
];
8769 /* Now the opcode; be careful about word order here! */
8770 if (i
.tm
.opcode_length
== 1)
8772 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8776 switch (i
.tm
.opcode_length
)
8780 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8781 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8785 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8795 /* Put out high byte first: can't use md_number_to_chars! */
8796 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8797 *p
= i
.tm
.base_opcode
& 0xff;
8800 /* Now the modrm byte and sib byte (if present). */
8801 if (i
.tm
.opcode_modifier
.modrm
)
8803 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8806 /* If i.rm.regmem == ESP (4)
8807 && i.rm.mode != (Register mode)
8809 ==> need second modrm byte. */
8810 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8812 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8813 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8815 | i
.sib
.scale
<< 6));
8818 if (i
.disp_operands
)
8819 output_disp (insn_start_frag
, insn_start_off
);
8822 output_imm (insn_start_frag
, insn_start_off
);
8825 * frag_now_fix () returning plain abs_section_offset when we're in the
8826 * absolute section, and abs_section_offset not getting updated as data
8827 * gets added to the frag breaks the logic below.
8829 if (now_seg
!= absolute_section
)
8831 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8833 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8837 /* NB: Don't add prefix with GOTPC relocation since
8838 output_disp() above depends on the fixed encoding
8839 length. Can't add prefix with TLS relocation since
8840 it breaks TLS linker optimization. */
8841 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
8842 /* Prefix count on the current instruction. */
8843 unsigned int count
= i
.vex
.length
;
8845 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
8846 /* REX byte is encoded in VEX/EVEX prefix. */
8847 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
8850 /* Count prefixes for extended opcode maps. */
8852 switch (i
.tm
.opcode_length
)
8855 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
8858 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
8870 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
8879 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
8882 /* Set the maximum prefix size in BRANCH_PREFIX
8884 if (fragP
->tc_frag_data
.max_bytes
> max
)
8885 fragP
->tc_frag_data
.max_bytes
= max
;
8886 if (fragP
->tc_frag_data
.max_bytes
> count
)
8887 fragP
->tc_frag_data
.max_bytes
-= count
;
8889 fragP
->tc_frag_data
.max_bytes
= 0;
8893 /* Remember the maximum prefix size in FUSED_JCC_PADDING
8895 unsigned int max_prefix_size
;
8896 if (align_branch_prefix_size
> max
)
8897 max_prefix_size
= max
;
8899 max_prefix_size
= align_branch_prefix_size
;
8900 if (max_prefix_size
> count
)
8901 fragP
->tc_frag_data
.max_prefix_length
8902 = max_prefix_size
- count
;
8905 /* Use existing segment prefix if possible. Use CS
8906 segment prefix in 64-bit mode. In 32-bit mode, use SS
8907 segment prefix with ESP/EBP base register and use DS
8908 segment prefix without ESP/EBP base register. */
8909 if (i
.prefix
[SEG_PREFIX
])
8910 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
8911 else if (flag_code
== CODE_64BIT
)
8912 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
8914 && (i
.base_reg
->reg_num
== 4
8915 || i
.base_reg
->reg_num
== 5))
8916 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
8918 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
8923 /* NB: Don't work with COND_JUMP86 without i386. */
8924 if (align_branch_power
8925 && now_seg
!= absolute_section
8926 && cpu_arch_flags
.bitfield
.cpui386
)
8928 /* Terminate each frag so that we can add prefix and check for
8930 frag_wane (frag_now
);
8937 pi ("" /*line*/, &i
);
8939 #endif /* DEBUG386 */
8942 /* Return the size of the displacement operand N. */
8945 disp_size (unsigned int n
)
8949 if (i
.types
[n
].bitfield
.disp64
)
8951 else if (i
.types
[n
].bitfield
.disp8
)
8953 else if (i
.types
[n
].bitfield
.disp16
)
8958 /* Return the size of the immediate operand N. */
8961 imm_size (unsigned int n
)
8964 if (i
.types
[n
].bitfield
.imm64
)
8966 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8968 else if (i
.types
[n
].bitfield
.imm16
)
8974 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8979 for (n
= 0; n
< i
.operands
; n
++)
8981 if (operand_type_check (i
.types
[n
], disp
))
8983 if (i
.op
[n
].disps
->X_op
== O_constant
)
8985 int size
= disp_size (n
);
8986 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8988 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8990 p
= frag_more (size
);
8991 md_number_to_chars (p
, val
, size
);
8995 enum bfd_reloc_code_real reloc_type
;
8996 int size
= disp_size (n
);
8997 int sign
= i
.types
[n
].bitfield
.disp32s
;
8998 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9001 /* We can't have 8 bit displacement here. */
9002 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9004 /* The PC relative address is computed relative
9005 to the instruction boundary, so in case immediate
9006 fields follows, we need to adjust the value. */
9007 if (pcrel
&& i
.imm_operands
)
9012 for (n1
= 0; n1
< i
.operands
; n1
++)
9013 if (operand_type_check (i
.types
[n1
], imm
))
9015 /* Only one immediate is allowed for PC
9016 relative address. */
9017 gas_assert (sz
== 0);
9019 i
.op
[n
].disps
->X_add_number
-= sz
;
9021 /* We should find the immediate. */
9022 gas_assert (sz
!= 0);
9025 p
= frag_more (size
);
9026 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9028 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9029 && (((reloc_type
== BFD_RELOC_32
9030 || reloc_type
== BFD_RELOC_X86_64_32S
9031 || (reloc_type
== BFD_RELOC_64
9033 && (i
.op
[n
].disps
->X_op
== O_symbol
9034 || (i
.op
[n
].disps
->X_op
== O_add
9035 && ((symbol_get_value_expression
9036 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9038 || reloc_type
== BFD_RELOC_32_PCREL
))
9042 reloc_type
= BFD_RELOC_386_GOTPC
;
9043 i
.has_gotpc_tls_reloc
= TRUE
;
9044 i
.op
[n
].imms
->X_add_number
+=
9045 encoding_length (insn_start_frag
, insn_start_off
, p
);
9047 else if (reloc_type
== BFD_RELOC_64
)
9048 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9050 /* Don't do the adjustment for x86-64, as there
9051 the pcrel addressing is relative to the _next_
9052 insn, and that is taken care of in other code. */
9053 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9055 else if (align_branch_power
)
9059 case BFD_RELOC_386_TLS_GD
:
9060 case BFD_RELOC_386_TLS_LDM
:
9061 case BFD_RELOC_386_TLS_IE
:
9062 case BFD_RELOC_386_TLS_IE_32
:
9063 case BFD_RELOC_386_TLS_GOTIE
:
9064 case BFD_RELOC_386_TLS_GOTDESC
:
9065 case BFD_RELOC_386_TLS_DESC_CALL
:
9066 case BFD_RELOC_X86_64_TLSGD
:
9067 case BFD_RELOC_X86_64_TLSLD
:
9068 case BFD_RELOC_X86_64_GOTTPOFF
:
9069 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9070 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9071 i
.has_gotpc_tls_reloc
= TRUE
;
9076 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9077 size
, i
.op
[n
].disps
, pcrel
,
9079 /* Check for "call/jmp *mem", "mov mem, %reg",
9080 "test %reg, mem" and "binop mem, %reg" where binop
9081 is one of adc, add, and, cmp, or, sbb, sub, xor
9082 instructions without data prefix. Always generate
9083 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9084 if (i
.prefix
[DATA_PREFIX
] == 0
9085 && (generate_relax_relocations
9088 && i
.rm
.regmem
== 5))
9090 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9091 && !is_any_vex_encoding(&i
.tm
)
9092 && ((i
.operands
== 1
9093 && i
.tm
.base_opcode
== 0xff
9094 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9096 && (i
.tm
.base_opcode
== 0x8b
9097 || i
.tm
.base_opcode
== 0x85
9098 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9102 fixP
->fx_tcbit
= i
.rex
!= 0;
9104 && (i
.base_reg
->reg_num
== RegIP
))
9105 fixP
->fx_tcbit2
= 1;
9108 fixP
->fx_tcbit2
= 1;
9116 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9121 for (n
= 0; n
< i
.operands
; n
++)
9123 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9124 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9127 if (operand_type_check (i
.types
[n
], imm
))
9129 if (i
.op
[n
].imms
->X_op
== O_constant
)
9131 int size
= imm_size (n
);
9134 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9136 p
= frag_more (size
);
9137 md_number_to_chars (p
, val
, size
);
9141 /* Not absolute_section.
9142 Need a 32-bit fixup (don't support 8bit
9143 non-absolute imms). Try to support other
9145 enum bfd_reloc_code_real reloc_type
;
9146 int size
= imm_size (n
);
9149 if (i
.types
[n
].bitfield
.imm32s
9150 && (i
.suffix
== QWORD_MNEM_SUFFIX
9151 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9156 p
= frag_more (size
);
9157 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9159 /* This is tough to explain. We end up with this one if we
9160 * have operands that look like
9161 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9162 * obtain the absolute address of the GOT, and it is strongly
9163 * preferable from a performance point of view to avoid using
9164 * a runtime relocation for this. The actual sequence of
9165 * instructions often look something like:
9170 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9172 * The call and pop essentially return the absolute address
9173 * of the label .L66 and store it in %ebx. The linker itself
9174 * will ultimately change the first operand of the addl so
9175 * that %ebx points to the GOT, but to keep things simple, the
9176 * .o file must have this operand set so that it generates not
9177 * the absolute address of .L66, but the absolute address of
9178 * itself. This allows the linker itself simply treat a GOTPC
9179 * relocation as asking for a pcrel offset to the GOT to be
9180 * added in, and the addend of the relocation is stored in the
9181 * operand field for the instruction itself.
9183 * Our job here is to fix the operand so that it would add
9184 * the correct offset so that %ebx would point to itself. The
9185 * thing that is tricky is that .-.L66 will point to the
9186 * beginning of the instruction, so we need to further modify
9187 * the operand so that it will point to itself. There are
9188 * other cases where you have something like:
9190 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9192 * and here no correction would be required. Internally in
9193 * the assembler we treat operands of this form as not being
9194 * pcrel since the '.' is explicitly mentioned, and I wonder
9195 * whether it would simplify matters to do it this way. Who
9196 * knows. In earlier versions of the PIC patches, the
9197 * pcrel_adjust field was used to store the correction, but
9198 * since the expression is not pcrel, I felt it would be
9199 * confusing to do it this way. */
9201 if ((reloc_type
== BFD_RELOC_32
9202 || reloc_type
== BFD_RELOC_X86_64_32S
9203 || reloc_type
== BFD_RELOC_64
)
9205 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9206 && (i
.op
[n
].imms
->X_op
== O_symbol
9207 || (i
.op
[n
].imms
->X_op
== O_add
9208 && ((symbol_get_value_expression
9209 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9213 reloc_type
= BFD_RELOC_386_GOTPC
;
9215 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9217 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9218 i
.has_gotpc_tls_reloc
= TRUE
;
9219 i
.op
[n
].imms
->X_add_number
+=
9220 encoding_length (insn_start_frag
, insn_start_off
, p
);
9222 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9223 i
.op
[n
].imms
, 0, reloc_type
);
9229 /* x86_cons_fix_new is called via the expression parsing code when a
9230 reloc is needed. We use this hook to get the correct .got reloc. */
9231 static int cons_sign
= -1;
9234 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9235 expressionS
*exp
, bfd_reloc_code_real_type r
)
9237 r
= reloc (len
, 0, cons_sign
, r
);
9240 if (exp
->X_op
== O_secrel
)
9242 exp
->X_op
= O_symbol
;
9243 r
= BFD_RELOC_32_SECREL
;
9247 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9250 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9251 purpose of the `.dc.a' internal pseudo-op. */
9254 x86_address_bytes (void)
9256 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9258 return stdoutput
->arch_info
->bits_per_address
/ 8;
9261 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9263 # define lex_got(reloc, adjust, types) NULL
9265 /* Parse operands of the form
9266 <symbol>@GOTOFF+<nnn>
9267 and similar .plt or .got references.
9269 If we find one, set up the correct relocation in RELOC and copy the
9270 input string, minus the `@GOTOFF' into a malloc'd buffer for
9271 parsing by the calling routine. Return this buffer, and if ADJUST
9272 is non-null set it to the length of the string we removed from the
9273 input line. Otherwise return NULL. */
9275 lex_got (enum bfd_reloc_code_real
*rel
,
9277 i386_operand_type
*types
)
9279 /* Some of the relocations depend on the size of what field is to
9280 be relocated. But in our callers i386_immediate and i386_displacement
9281 we don't yet know the operand size (this will be set by insn
9282 matching). Hence we record the word32 relocation here,
9283 and adjust the reloc according to the real size in reloc(). */
9284 static const struct {
9287 const enum bfd_reloc_code_real rel
[2];
9288 const i386_operand_type types64
;
9290 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9291 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9293 OPERAND_TYPE_IMM32_64
},
9295 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9296 BFD_RELOC_X86_64_PLTOFF64
},
9297 OPERAND_TYPE_IMM64
},
9298 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9299 BFD_RELOC_X86_64_PLT32
},
9300 OPERAND_TYPE_IMM32_32S_DISP32
},
9301 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9302 BFD_RELOC_X86_64_GOTPLT64
},
9303 OPERAND_TYPE_IMM64_DISP64
},
9304 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9305 BFD_RELOC_X86_64_GOTOFF64
},
9306 OPERAND_TYPE_IMM64_DISP64
},
9307 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9308 BFD_RELOC_X86_64_GOTPCREL
},
9309 OPERAND_TYPE_IMM32_32S_DISP32
},
9310 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9311 BFD_RELOC_X86_64_TLSGD
},
9312 OPERAND_TYPE_IMM32_32S_DISP32
},
9313 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9314 _dummy_first_bfd_reloc_code_real
},
9315 OPERAND_TYPE_NONE
},
9316 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9317 BFD_RELOC_X86_64_TLSLD
},
9318 OPERAND_TYPE_IMM32_32S_DISP32
},
9319 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9320 BFD_RELOC_X86_64_GOTTPOFF
},
9321 OPERAND_TYPE_IMM32_32S_DISP32
},
9322 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9323 BFD_RELOC_X86_64_TPOFF32
},
9324 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9325 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9326 _dummy_first_bfd_reloc_code_real
},
9327 OPERAND_TYPE_NONE
},
9328 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9329 BFD_RELOC_X86_64_DTPOFF32
},
9330 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9331 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9332 _dummy_first_bfd_reloc_code_real
},
9333 OPERAND_TYPE_NONE
},
9334 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9335 _dummy_first_bfd_reloc_code_real
},
9336 OPERAND_TYPE_NONE
},
9337 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9338 BFD_RELOC_X86_64_GOT32
},
9339 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9340 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9341 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9342 OPERAND_TYPE_IMM32_32S_DISP32
},
9343 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9344 BFD_RELOC_X86_64_TLSDESC_CALL
},
9345 OPERAND_TYPE_IMM32_32S_DISP32
},
9350 #if defined (OBJ_MAYBE_ELF)
9355 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9356 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9359 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9361 int len
= gotrel
[j
].len
;
9362 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9364 if (gotrel
[j
].rel
[object_64bit
] != 0)
9367 char *tmpbuf
, *past_reloc
;
9369 *rel
= gotrel
[j
].rel
[object_64bit
];
9373 if (flag_code
!= CODE_64BIT
)
9375 types
->bitfield
.imm32
= 1;
9376 types
->bitfield
.disp32
= 1;
9379 *types
= gotrel
[j
].types64
;
9382 if (j
!= 0 && GOT_symbol
== NULL
)
9383 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9385 /* The length of the first part of our input line. */
9386 first
= cp
- input_line_pointer
;
9388 /* The second part goes from after the reloc token until
9389 (and including) an end_of_line char or comma. */
9390 past_reloc
= cp
+ 1 + len
;
9392 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9394 second
= cp
+ 1 - past_reloc
;
9396 /* Allocate and copy string. The trailing NUL shouldn't
9397 be necessary, but be safe. */
9398 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9399 memcpy (tmpbuf
, input_line_pointer
, first
);
9400 if (second
!= 0 && *past_reloc
!= ' ')
9401 /* Replace the relocation token with ' ', so that
9402 errors like foo@GOTOFF1 will be detected. */
9403 tmpbuf
[first
++] = ' ';
9405 /* Increment length by 1 if the relocation token is
9410 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9411 tmpbuf
[first
+ second
] = '\0';
9415 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9416 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9421 /* Might be a symbol version string. Don't as_bad here. */
9430 /* Parse operands of the form
9431 <symbol>@SECREL32+<nnn>
9433 If we find one, set up the correct relocation in RELOC and copy the
9434 input string, minus the `@SECREL32' into a malloc'd buffer for
9435 parsing by the calling routine. Return this buffer, and if ADJUST
9436 is non-null set it to the length of the string we removed from the
9437 input line. Otherwise return NULL.
9439 This function is copied from the ELF version above adjusted for PE targets. */
9442 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9443 int *adjust ATTRIBUTE_UNUSED
,
9444 i386_operand_type
*types
)
9450 const enum bfd_reloc_code_real rel
[2];
9451 const i386_operand_type types64
;
9455 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9456 BFD_RELOC_32_SECREL
},
9457 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9463 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9464 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9467 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9469 int len
= gotrel
[j
].len
;
9471 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9473 if (gotrel
[j
].rel
[object_64bit
] != 0)
9476 char *tmpbuf
, *past_reloc
;
9478 *rel
= gotrel
[j
].rel
[object_64bit
];
9484 if (flag_code
!= CODE_64BIT
)
9486 types
->bitfield
.imm32
= 1;
9487 types
->bitfield
.disp32
= 1;
9490 *types
= gotrel
[j
].types64
;
9493 /* The length of the first part of our input line. */
9494 first
= cp
- input_line_pointer
;
9496 /* The second part goes from after the reloc token until
9497 (and including) an end_of_line char or comma. */
9498 past_reloc
= cp
+ 1 + len
;
9500 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9502 second
= cp
+ 1 - past_reloc
;
9504 /* Allocate and copy string. The trailing NUL shouldn't
9505 be necessary, but be safe. */
9506 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9507 memcpy (tmpbuf
, input_line_pointer
, first
);
9508 if (second
!= 0 && *past_reloc
!= ' ')
9509 /* Replace the relocation token with ' ', so that
9510 errors like foo@SECLREL321 will be detected. */
9511 tmpbuf
[first
++] = ' ';
9512 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9513 tmpbuf
[first
+ second
] = '\0';
9517 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9518 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9523 /* Might be a symbol version string. Don't as_bad here. */
9529 bfd_reloc_code_real_type
9530 x86_cons (expressionS
*exp
, int size
)
9532 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9534 intel_syntax
= -intel_syntax
;
9537 if (size
== 4 || (object_64bit
&& size
== 8))
9539 /* Handle @GOTOFF and the like in an expression. */
9541 char *gotfree_input_line
;
9544 save
= input_line_pointer
;
9545 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9546 if (gotfree_input_line
)
9547 input_line_pointer
= gotfree_input_line
;
9551 if (gotfree_input_line
)
9553 /* expression () has merrily parsed up to the end of line,
9554 or a comma - in the wrong buffer. Transfer how far
9555 input_line_pointer has moved to the right buffer. */
9556 input_line_pointer
= (save
9557 + (input_line_pointer
- gotfree_input_line
)
9559 free (gotfree_input_line
);
9560 if (exp
->X_op
== O_constant
9561 || exp
->X_op
== O_absent
9562 || exp
->X_op
== O_illegal
9563 || exp
->X_op
== O_register
9564 || exp
->X_op
== O_big
)
9566 char c
= *input_line_pointer
;
9567 *input_line_pointer
= 0;
9568 as_bad (_("missing or invalid expression `%s'"), save
);
9569 *input_line_pointer
= c
;
9571 else if ((got_reloc
== BFD_RELOC_386_PLT32
9572 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9573 && exp
->X_op
!= O_symbol
)
9575 char c
= *input_line_pointer
;
9576 *input_line_pointer
= 0;
9577 as_bad (_("invalid PLT expression `%s'"), save
);
9578 *input_line_pointer
= c
;
9585 intel_syntax
= -intel_syntax
;
9588 i386_intel_simplify (exp
);
9594 signed_cons (int size
)
9596 if (flag_code
== CODE_64BIT
)
9604 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9611 if (exp
.X_op
== O_symbol
)
9612 exp
.X_op
= O_secrel
;
9614 emit_expr (&exp
, 4);
9616 while (*input_line_pointer
++ == ',');
9618 input_line_pointer
--;
9619 demand_empty_rest_of_line ();
9623 /* Handle Vector operations. */
9626 check_VecOperations (char *op_string
, char *op_end
)
9628 const reg_entry
*mask
;
9633 && (op_end
== NULL
|| op_string
< op_end
))
9636 if (*op_string
== '{')
9640 /* Check broadcasts. */
9641 if (strncmp (op_string
, "1to", 3) == 0)
9646 goto duplicated_vec_op
;
9649 if (*op_string
== '8')
9651 else if (*op_string
== '4')
9653 else if (*op_string
== '2')
9655 else if (*op_string
== '1'
9656 && *(op_string
+1) == '6')
9663 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9668 broadcast_op
.type
= bcst_type
;
9669 broadcast_op
.operand
= this_operand
;
9670 broadcast_op
.bytes
= 0;
9671 i
.broadcast
= &broadcast_op
;
9673 /* Check masking operation. */
9674 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9676 /* k0 can't be used for write mask. */
9677 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9679 as_bad (_("`%s%s' can't be used for write mask"),
9680 register_prefix
, mask
->reg_name
);
9686 mask_op
.mask
= mask
;
9687 mask_op
.zeroing
= 0;
9688 mask_op
.operand
= this_operand
;
9694 goto duplicated_vec_op
;
9696 i
.mask
->mask
= mask
;
9698 /* Only "{z}" is allowed here. No need to check
9699 zeroing mask explicitly. */
9700 if (i
.mask
->operand
!= this_operand
)
9702 as_bad (_("invalid write mask `%s'"), saved
);
9709 /* Check zeroing-flag for masking operation. */
9710 else if (*op_string
== 'z')
9714 mask_op
.mask
= NULL
;
9715 mask_op
.zeroing
= 1;
9716 mask_op
.operand
= this_operand
;
9721 if (i
.mask
->zeroing
)
9724 as_bad (_("duplicated `%s'"), saved
);
9728 i
.mask
->zeroing
= 1;
9730 /* Only "{%k}" is allowed here. No need to check mask
9731 register explicitly. */
9732 if (i
.mask
->operand
!= this_operand
)
9734 as_bad (_("invalid zeroing-masking `%s'"),
9743 goto unknown_vec_op
;
9745 if (*op_string
!= '}')
9747 as_bad (_("missing `}' in `%s'"), saved
);
9752 /* Strip whitespace since the addition of pseudo prefixes
9753 changed how the scrubber treats '{'. */
9754 if (is_space_char (*op_string
))
9760 /* We don't know this one. */
9761 as_bad (_("unknown vector operation: `%s'"), saved
);
9765 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9767 as_bad (_("zeroing-masking only allowed with write mask"));
9775 i386_immediate (char *imm_start
)
9777 char *save_input_line_pointer
;
9778 char *gotfree_input_line
;
9781 i386_operand_type types
;
9783 operand_type_set (&types
, ~0);
9785 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9787 as_bad (_("at most %d immediate operands are allowed"),
9788 MAX_IMMEDIATE_OPERANDS
);
9792 exp
= &im_expressions
[i
.imm_operands
++];
9793 i
.op
[this_operand
].imms
= exp
;
9795 if (is_space_char (*imm_start
))
9798 save_input_line_pointer
= input_line_pointer
;
9799 input_line_pointer
= imm_start
;
9801 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9802 if (gotfree_input_line
)
9803 input_line_pointer
= gotfree_input_line
;
9805 exp_seg
= expression (exp
);
9809 /* Handle vector operations. */
9810 if (*input_line_pointer
== '{')
9812 input_line_pointer
= check_VecOperations (input_line_pointer
,
9814 if (input_line_pointer
== NULL
)
9818 if (*input_line_pointer
)
9819 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9821 input_line_pointer
= save_input_line_pointer
;
9822 if (gotfree_input_line
)
9824 free (gotfree_input_line
);
9826 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9827 exp
->X_op
= O_illegal
;
9830 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9834 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9835 i386_operand_type types
, const char *imm_start
)
9837 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9840 as_bad (_("missing or invalid immediate expression `%s'"),
9844 else if (exp
->X_op
== O_constant
)
9846 /* Size it properly later. */
9847 i
.types
[this_operand
].bitfield
.imm64
= 1;
9848 /* If not 64bit, sign extend val. */
9849 if (flag_code
!= CODE_64BIT
9850 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9852 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9854 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9855 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9856 && exp_seg
!= absolute_section
9857 && exp_seg
!= text_section
9858 && exp_seg
!= data_section
9859 && exp_seg
!= bss_section
9860 && exp_seg
!= undefined_section
9861 && !bfd_is_com_section (exp_seg
))
9863 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9867 else if (!intel_syntax
&& exp_seg
== reg_section
)
9870 as_bad (_("illegal immediate register operand %s"), imm_start
);
9875 /* This is an address. The size of the address will be
9876 determined later, depending on destination register,
9877 suffix, or the default for the section. */
9878 i
.types
[this_operand
].bitfield
.imm8
= 1;
9879 i
.types
[this_operand
].bitfield
.imm16
= 1;
9880 i
.types
[this_operand
].bitfield
.imm32
= 1;
9881 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9882 i
.types
[this_operand
].bitfield
.imm64
= 1;
9883 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9891 i386_scale (char *scale
)
9894 char *save
= input_line_pointer
;
9896 input_line_pointer
= scale
;
9897 val
= get_absolute_expression ();
9902 i
.log2_scale_factor
= 0;
9905 i
.log2_scale_factor
= 1;
9908 i
.log2_scale_factor
= 2;
9911 i
.log2_scale_factor
= 3;
9915 char sep
= *input_line_pointer
;
9917 *input_line_pointer
= '\0';
9918 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9920 *input_line_pointer
= sep
;
9921 input_line_pointer
= save
;
9925 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9927 as_warn (_("scale factor of %d without an index register"),
9928 1 << i
.log2_scale_factor
);
9929 i
.log2_scale_factor
= 0;
9931 scale
= input_line_pointer
;
9932 input_line_pointer
= save
;
9937 i386_displacement (char *disp_start
, char *disp_end
)
9941 char *save_input_line_pointer
;
9942 char *gotfree_input_line
;
9944 i386_operand_type bigdisp
, types
= anydisp
;
9947 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9949 as_bad (_("at most %d displacement operands are allowed"),
9950 MAX_MEMORY_OPERANDS
);
9954 operand_type_set (&bigdisp
, 0);
9956 || i
.types
[this_operand
].bitfield
.baseindex
9957 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
9958 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
9960 i386_addressing_mode ();
9961 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9962 if (flag_code
== CODE_64BIT
)
9966 bigdisp
.bitfield
.disp32s
= 1;
9967 bigdisp
.bitfield
.disp64
= 1;
9970 bigdisp
.bitfield
.disp32
= 1;
9972 else if ((flag_code
== CODE_16BIT
) ^ override
)
9973 bigdisp
.bitfield
.disp16
= 1;
9975 bigdisp
.bitfield
.disp32
= 1;
9979 /* For PC-relative branches, the width of the displacement may be
9980 dependent upon data size, but is never dependent upon address size.
9981 Also make sure to not unintentionally match against a non-PC-relative
9983 static templates aux_templates
;
9984 const insn_template
*t
= current_templates
->start
;
9985 bfd_boolean has_intel64
= FALSE
;
9987 aux_templates
.start
= t
;
9988 while (++t
< current_templates
->end
)
9990 if (t
->opcode_modifier
.jump
9991 != current_templates
->start
->opcode_modifier
.jump
)
9993 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
9996 if (t
< current_templates
->end
)
9998 aux_templates
.end
= t
;
9999 current_templates
= &aux_templates
;
10002 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10003 if (flag_code
== CODE_64BIT
)
10005 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10006 && (!intel64
|| !has_intel64
))
10007 bigdisp
.bitfield
.disp16
= 1;
10009 bigdisp
.bitfield
.disp32s
= 1;
10014 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10016 : LONG_MNEM_SUFFIX
));
10017 bigdisp
.bitfield
.disp32
= 1;
10018 if ((flag_code
== CODE_16BIT
) ^ override
)
10020 bigdisp
.bitfield
.disp32
= 0;
10021 bigdisp
.bitfield
.disp16
= 1;
10025 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10028 exp
= &disp_expressions
[i
.disp_operands
];
10029 i
.op
[this_operand
].disps
= exp
;
10031 save_input_line_pointer
= input_line_pointer
;
10032 input_line_pointer
= disp_start
;
10033 END_STRING_AND_SAVE (disp_end
);
10035 #ifndef GCC_ASM_O_HACK
10036 #define GCC_ASM_O_HACK 0
10039 END_STRING_AND_SAVE (disp_end
+ 1);
10040 if (i
.types
[this_operand
].bitfield
.baseIndex
10041 && displacement_string_end
[-1] == '+')
10043 /* This hack is to avoid a warning when using the "o"
10044 constraint within gcc asm statements.
10047 #define _set_tssldt_desc(n,addr,limit,type) \
10048 __asm__ __volatile__ ( \
10049 "movw %w2,%0\n\t" \
10050 "movw %w1,2+%0\n\t" \
10051 "rorl $16,%1\n\t" \
10052 "movb %b1,4+%0\n\t" \
10053 "movb %4,5+%0\n\t" \
10054 "movb $0,6+%0\n\t" \
10055 "movb %h1,7+%0\n\t" \
10057 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10059 This works great except that the output assembler ends
10060 up looking a bit weird if it turns out that there is
10061 no offset. You end up producing code that looks like:
10074 So here we provide the missing zero. */
10076 *displacement_string_end
= '0';
10079 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10080 if (gotfree_input_line
)
10081 input_line_pointer
= gotfree_input_line
;
10083 exp_seg
= expression (exp
);
10085 SKIP_WHITESPACE ();
10086 if (*input_line_pointer
)
10087 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10089 RESTORE_END_STRING (disp_end
+ 1);
10091 input_line_pointer
= save_input_line_pointer
;
10092 if (gotfree_input_line
)
10094 free (gotfree_input_line
);
10096 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10097 exp
->X_op
= O_illegal
;
10100 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10102 RESTORE_END_STRING (disp_end
);
10108 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10109 i386_operand_type types
, const char *disp_start
)
10111 i386_operand_type bigdisp
;
10114 /* We do this to make sure that the section symbol is in
10115 the symbol table. We will ultimately change the relocation
10116 to be relative to the beginning of the section. */
10117 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10118 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10119 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10121 if (exp
->X_op
!= O_symbol
)
10124 if (S_IS_LOCAL (exp
->X_add_symbol
)
10125 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10126 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10127 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10128 exp
->X_op
= O_subtract
;
10129 exp
->X_op_symbol
= GOT_symbol
;
10130 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10131 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10132 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10133 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10135 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10138 else if (exp
->X_op
== O_absent
10139 || exp
->X_op
== O_illegal
10140 || exp
->X_op
== O_big
)
10143 as_bad (_("missing or invalid displacement expression `%s'"),
10148 else if (flag_code
== CODE_64BIT
10149 && !i
.prefix
[ADDR_PREFIX
]
10150 && exp
->X_op
== O_constant
)
10152 /* Since displacement is signed extended to 64bit, don't allow
10153 disp32 and turn off disp32s if they are out of range. */
10154 i
.types
[this_operand
].bitfield
.disp32
= 0;
10155 if (!fits_in_signed_long (exp
->X_add_number
))
10157 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10158 if (i
.types
[this_operand
].bitfield
.baseindex
)
10160 as_bad (_("0x%lx out range of signed 32bit displacement"),
10161 (long) exp
->X_add_number
);
10167 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10168 else if (exp
->X_op
!= O_constant
10169 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10170 && exp_seg
!= absolute_section
10171 && exp_seg
!= text_section
10172 && exp_seg
!= data_section
10173 && exp_seg
!= bss_section
10174 && exp_seg
!= undefined_section
10175 && !bfd_is_com_section (exp_seg
))
10177 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10182 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10183 /* Constants get taken care of by optimize_disp(). */
10184 && exp
->X_op
!= O_constant
)
10185 i
.types
[this_operand
].bitfield
.disp8
= 1;
10187 /* Check if this is a displacement only operand. */
10188 bigdisp
= i
.types
[this_operand
];
10189 bigdisp
.bitfield
.disp8
= 0;
10190 bigdisp
.bitfield
.disp16
= 0;
10191 bigdisp
.bitfield
.disp32
= 0;
10192 bigdisp
.bitfield
.disp32s
= 0;
10193 bigdisp
.bitfield
.disp64
= 0;
10194 if (operand_type_all_zero (&bigdisp
))
10195 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10201 /* Return the active addressing mode, taking address override and
10202 registers forming the address into consideration. Update the
10203 address override prefix if necessary. */
10205 static enum flag_code
10206 i386_addressing_mode (void)
10208 enum flag_code addr_mode
;
10210 if (i
.prefix
[ADDR_PREFIX
])
10211 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10214 addr_mode
= flag_code
;
10216 #if INFER_ADDR_PREFIX
10217 if (i
.mem_operands
== 0)
10219 /* Infer address prefix from the first memory operand. */
10220 const reg_entry
*addr_reg
= i
.base_reg
;
10222 if (addr_reg
== NULL
)
10223 addr_reg
= i
.index_reg
;
10227 if (addr_reg
->reg_type
.bitfield
.dword
)
10228 addr_mode
= CODE_32BIT
;
10229 else if (flag_code
!= CODE_64BIT
10230 && addr_reg
->reg_type
.bitfield
.word
)
10231 addr_mode
= CODE_16BIT
;
10233 if (addr_mode
!= flag_code
)
10235 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10237 /* Change the size of any displacement too. At most one
10238 of Disp16 or Disp32 is set.
10239 FIXME. There doesn't seem to be any real need for
10240 separate Disp16 and Disp32 flags. The same goes for
10241 Imm16 and Imm32. Removing them would probably clean
10242 up the code quite a lot. */
10243 if (flag_code
!= CODE_64BIT
10244 && (i
.types
[this_operand
].bitfield
.disp16
10245 || i
.types
[this_operand
].bitfield
.disp32
))
10246 i
.types
[this_operand
]
10247 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10257 /* Make sure the memory operand we've been dealt is valid.
10258 Return 1 on success, 0 on a failure. */
10261 i386_index_check (const char *operand_string
)
10263 const char *kind
= "base/index";
10264 enum flag_code addr_mode
= i386_addressing_mode ();
10266 if (current_templates
->start
->opcode_modifier
.isstring
10267 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10268 && (current_templates
->end
[-1].opcode_modifier
.isstring
10269 || i
.mem_operands
))
10271 /* Memory operands of string insns are special in that they only allow
10272 a single register (rDI, rSI, or rBX) as their memory address. */
10273 const reg_entry
*expected_reg
;
10274 static const char *di_si
[][2] =
10280 static const char *bx
[] = { "ebx", "bx", "rbx" };
10282 kind
= "string address";
10284 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10286 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10287 - IS_STRING_ES_OP0
;
10290 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10291 || ((!i
.mem_operands
!= !intel_syntax
)
10292 && current_templates
->end
[-1].operand_types
[1]
10293 .bitfield
.baseindex
))
10295 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10298 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10300 if (i
.base_reg
!= expected_reg
10302 || operand_type_check (i
.types
[this_operand
], disp
))
10304 /* The second memory operand must have the same size as
10308 && !((addr_mode
== CODE_64BIT
10309 && i
.base_reg
->reg_type
.bitfield
.qword
)
10310 || (addr_mode
== CODE_32BIT
10311 ? i
.base_reg
->reg_type
.bitfield
.dword
10312 : i
.base_reg
->reg_type
.bitfield
.word
)))
10315 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10317 intel_syntax
? '[' : '(',
10319 expected_reg
->reg_name
,
10320 intel_syntax
? ']' : ')');
10327 as_bad (_("`%s' is not a valid %s expression"),
10328 operand_string
, kind
);
10333 if (addr_mode
!= CODE_16BIT
)
10335 /* 32-bit/64-bit checks. */
10337 && ((addr_mode
== CODE_64BIT
10338 ? !i
.base_reg
->reg_type
.bitfield
.qword
10339 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10340 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10341 || i
.base_reg
->reg_num
== RegIZ
))
10343 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10344 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10345 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10346 && ((addr_mode
== CODE_64BIT
10347 ? !i
.index_reg
->reg_type
.bitfield
.qword
10348 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10349 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10352 /* bndmk, bndldx, and bndstx have special restrictions. */
10353 if (current_templates
->start
->base_opcode
== 0xf30f1b
10354 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10356 /* They cannot use RIP-relative addressing. */
10357 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10359 as_bad (_("`%s' cannot be used here"), operand_string
);
10363 /* bndldx and bndstx ignore their scale factor. */
10364 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10365 && i
.log2_scale_factor
)
10366 as_warn (_("register scaling is being ignored here"));
10371 /* 16-bit checks. */
10373 && (!i
.base_reg
->reg_type
.bitfield
.word
10374 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10376 && (!i
.index_reg
->reg_type
.bitfield
.word
10377 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10379 && i
.base_reg
->reg_num
< 6
10380 && i
.index_reg
->reg_num
>= 6
10381 && i
.log2_scale_factor
== 0))))
10388 /* Handle vector immediates. */
10391 RC_SAE_immediate (const char *imm_start
)
10393 unsigned int match_found
, j
;
10394 const char *pstr
= imm_start
;
10402 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10404 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10408 rc_op
.type
= RC_NamesTable
[j
].type
;
10409 rc_op
.operand
= this_operand
;
10410 i
.rounding
= &rc_op
;
10414 as_bad (_("duplicated `%s'"), imm_start
);
10417 pstr
+= RC_NamesTable
[j
].len
;
10425 if (*pstr
++ != '}')
10427 as_bad (_("Missing '}': '%s'"), imm_start
);
10430 /* RC/SAE immediate string should contain nothing more. */;
10433 as_bad (_("Junk after '}': '%s'"), imm_start
);
10437 exp
= &im_expressions
[i
.imm_operands
++];
10438 i
.op
[this_operand
].imms
= exp
;
10440 exp
->X_op
= O_constant
;
10441 exp
->X_add_number
= 0;
10442 exp
->X_add_symbol
= (symbolS
*) 0;
10443 exp
->X_op_symbol
= (symbolS
*) 0;
10445 i
.types
[this_operand
].bitfield
.imm8
= 1;
10449 /* Only string instructions can have a second memory operand, so
10450 reduce current_templates to just those if it contains any. */
10452 maybe_adjust_templates (void)
10454 const insn_template
*t
;
10456 gas_assert (i
.mem_operands
== 1);
10458 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10459 if (t
->opcode_modifier
.isstring
)
10462 if (t
< current_templates
->end
)
10464 static templates aux_templates
;
10465 bfd_boolean recheck
;
10467 aux_templates
.start
= t
;
10468 for (; t
< current_templates
->end
; ++t
)
10469 if (!t
->opcode_modifier
.isstring
)
10471 aux_templates
.end
= t
;
10473 /* Determine whether to re-check the first memory operand. */
10474 recheck
= (aux_templates
.start
!= current_templates
->start
10475 || t
!= current_templates
->end
);
10477 current_templates
= &aux_templates
;
10481 i
.mem_operands
= 0;
10482 if (i
.memop1_string
!= NULL
10483 && i386_index_check (i
.memop1_string
) == 0)
10485 i
.mem_operands
= 1;
10492 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10496 i386_att_operand (char *operand_string
)
10498 const reg_entry
*r
;
10500 char *op_string
= operand_string
;
10502 if (is_space_char (*op_string
))
10505 /* We check for an absolute prefix (differentiating,
10506 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10507 if (*op_string
== ABSOLUTE_PREFIX
)
10510 if (is_space_char (*op_string
))
10512 i
.jumpabsolute
= TRUE
;
10515 /* Check if operand is a register. */
10516 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10518 i386_operand_type temp
;
10520 /* Check for a segment override by searching for ':' after a
10521 segment register. */
10522 op_string
= end_op
;
10523 if (is_space_char (*op_string
))
10525 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10527 switch (r
->reg_num
)
10530 i
.seg
[i
.mem_operands
] = &es
;
10533 i
.seg
[i
.mem_operands
] = &cs
;
10536 i
.seg
[i
.mem_operands
] = &ss
;
10539 i
.seg
[i
.mem_operands
] = &ds
;
10542 i
.seg
[i
.mem_operands
] = &fs
;
10545 i
.seg
[i
.mem_operands
] = &gs
;
10549 /* Skip the ':' and whitespace. */
10551 if (is_space_char (*op_string
))
10554 if (!is_digit_char (*op_string
)
10555 && !is_identifier_char (*op_string
)
10556 && *op_string
!= '('
10557 && *op_string
!= ABSOLUTE_PREFIX
)
10559 as_bad (_("bad memory operand `%s'"), op_string
);
10562 /* Handle case of %es:*foo. */
10563 if (*op_string
== ABSOLUTE_PREFIX
)
10566 if (is_space_char (*op_string
))
10568 i
.jumpabsolute
= TRUE
;
10570 goto do_memory_reference
;
10573 /* Handle vector operations. */
10574 if (*op_string
== '{')
10576 op_string
= check_VecOperations (op_string
, NULL
);
10577 if (op_string
== NULL
)
10583 as_bad (_("junk `%s' after register"), op_string
);
10586 temp
= r
->reg_type
;
10587 temp
.bitfield
.baseindex
= 0;
10588 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10590 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10591 i
.op
[this_operand
].regs
= r
;
10594 else if (*op_string
== REGISTER_PREFIX
)
10596 as_bad (_("bad register name `%s'"), op_string
);
10599 else if (*op_string
== IMMEDIATE_PREFIX
)
10602 if (i
.jumpabsolute
)
10604 as_bad (_("immediate operand illegal with absolute jump"));
10607 if (!i386_immediate (op_string
))
10610 else if (RC_SAE_immediate (operand_string
))
10612 /* If it is a RC or SAE immediate, do nothing. */
10615 else if (is_digit_char (*op_string
)
10616 || is_identifier_char (*op_string
)
10617 || *op_string
== '"'
10618 || *op_string
== '(')
10620 /* This is a memory reference of some sort. */
10623 /* Start and end of displacement string expression (if found). */
10624 char *displacement_string_start
;
10625 char *displacement_string_end
;
10628 do_memory_reference
:
10629 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10631 if ((i
.mem_operands
== 1
10632 && !current_templates
->start
->opcode_modifier
.isstring
)
10633 || i
.mem_operands
== 2)
10635 as_bad (_("too many memory references for `%s'"),
10636 current_templates
->start
->name
);
10640 /* Check for base index form. We detect the base index form by
10641 looking for an ')' at the end of the operand, searching
10642 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10644 base_string
= op_string
+ strlen (op_string
);
10646 /* Handle vector operations. */
10647 vop_start
= strchr (op_string
, '{');
10648 if (vop_start
&& vop_start
< base_string
)
10650 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10652 base_string
= vop_start
;
10656 if (is_space_char (*base_string
))
10659 /* If we only have a displacement, set-up for it to be parsed later. */
10660 displacement_string_start
= op_string
;
10661 displacement_string_end
= base_string
+ 1;
10663 if (*base_string
== ')')
10666 unsigned int parens_balanced
= 1;
10667 /* We've already checked that the number of left & right ()'s are
10668 equal, so this loop will not be infinite. */
10672 if (*base_string
== ')')
10674 if (*base_string
== '(')
10677 while (parens_balanced
);
10679 temp_string
= base_string
;
10681 /* Skip past '(' and whitespace. */
10683 if (is_space_char (*base_string
))
10686 if (*base_string
== ','
10687 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10690 displacement_string_end
= temp_string
;
10692 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10696 base_string
= end_op
;
10697 if (is_space_char (*base_string
))
10701 /* There may be an index reg or scale factor here. */
10702 if (*base_string
== ',')
10705 if (is_space_char (*base_string
))
10708 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10711 base_string
= end_op
;
10712 if (is_space_char (*base_string
))
10714 if (*base_string
== ',')
10717 if (is_space_char (*base_string
))
10720 else if (*base_string
!= ')')
10722 as_bad (_("expecting `,' or `)' "
10723 "after index register in `%s'"),
10728 else if (*base_string
== REGISTER_PREFIX
)
10730 end_op
= strchr (base_string
, ',');
10733 as_bad (_("bad register name `%s'"), base_string
);
10737 /* Check for scale factor. */
10738 if (*base_string
!= ')')
10740 char *end_scale
= i386_scale (base_string
);
10745 base_string
= end_scale
;
10746 if (is_space_char (*base_string
))
10748 if (*base_string
!= ')')
10750 as_bad (_("expecting `)' "
10751 "after scale factor in `%s'"),
10756 else if (!i
.index_reg
)
10758 as_bad (_("expecting index register or scale factor "
10759 "after `,'; got '%c'"),
10764 else if (*base_string
!= ')')
10766 as_bad (_("expecting `,' or `)' "
10767 "after base register in `%s'"),
10772 else if (*base_string
== REGISTER_PREFIX
)
10774 end_op
= strchr (base_string
, ',');
10777 as_bad (_("bad register name `%s'"), base_string
);
10782 /* If there's an expression beginning the operand, parse it,
10783 assuming displacement_string_start and
10784 displacement_string_end are meaningful. */
10785 if (displacement_string_start
!= displacement_string_end
)
10787 if (!i386_displacement (displacement_string_start
,
10788 displacement_string_end
))
10792 /* Special case for (%dx) while doing input/output op. */
10794 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10795 && i
.base_reg
->reg_type
.bitfield
.word
10796 && i
.index_reg
== 0
10797 && i
.log2_scale_factor
== 0
10798 && i
.seg
[i
.mem_operands
] == 0
10799 && !operand_type_check (i
.types
[this_operand
], disp
))
10801 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10805 if (i386_index_check (operand_string
) == 0)
10807 i
.flags
[this_operand
] |= Operand_Mem
;
10808 if (i
.mem_operands
== 0)
10809 i
.memop1_string
= xstrdup (operand_string
);
10814 /* It's not a memory operand; argh! */
10815 as_bad (_("invalid char %s beginning operand %d `%s'"),
10816 output_invalid (*op_string
),
10821 return 1; /* Normal return. */
10824 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10825 that an rs_machine_dependent frag may reach. */
10828 i386_frag_max_var (fragS
*frag
)
10830 /* The only relaxable frags are for jumps.
10831 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10832 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10833 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10836 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10838 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10840 /* STT_GNU_IFUNC symbol must go through PLT. */
10841 if ((symbol_get_bfdsym (fr_symbol
)->flags
10842 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10845 if (!S_IS_EXTERNAL (fr_symbol
))
10846 /* Symbol may be weak or local. */
10847 return !S_IS_WEAK (fr_symbol
);
10849 /* Global symbols with non-default visibility can't be preempted. */
10850 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10853 if (fr_var
!= NO_RELOC
)
10854 switch ((enum bfd_reloc_code_real
) fr_var
)
10856 case BFD_RELOC_386_PLT32
:
10857 case BFD_RELOC_X86_64_PLT32
:
10858 /* Symbol with PLT relocation may be preempted. */
10864 /* Global symbols with default visibility in a shared library may be
10865 preempted by another definition. */
10870 /* Return the next non-empty frag. */
10873 i386_next_non_empty_frag (fragS
*fragP
)
10875 /* There may be a frag with a ".fill 0" when there is no room in
10876 the current frag for frag_grow in output_insn. */
10877 for (fragP
= fragP
->fr_next
;
10879 && fragP
->fr_type
== rs_fill
10880 && fragP
->fr_fix
== 0);
10881 fragP
= fragP
->fr_next
)
10886 /* Return the next jcc frag after BRANCH_PADDING. */
10889 i386_next_jcc_frag (fragS
*fragP
)
10894 if (fragP
->fr_type
== rs_machine_dependent
10895 && (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10896 == BRANCH_PADDING
))
10898 fragP
= i386_next_non_empty_frag (fragP
);
10899 if (fragP
->fr_type
!= rs_machine_dependent
)
10901 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == COND_JUMP
)
10908 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
10911 i386_classify_machine_dependent_frag (fragS
*fragP
)
10915 fragS
*branch_fragP
;
10917 unsigned int max_prefix_length
;
10919 if (fragP
->tc_frag_data
.classified
)
10922 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
10923 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
10924 for (next_fragP
= fragP
;
10925 next_fragP
!= NULL
;
10926 next_fragP
= next_fragP
->fr_next
)
10928 next_fragP
->tc_frag_data
.classified
= 1;
10929 if (next_fragP
->fr_type
== rs_machine_dependent
)
10930 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
10932 case BRANCH_PADDING
:
10933 /* The BRANCH_PADDING frag must be followed by a branch
10935 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
10936 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10938 case FUSED_JCC_PADDING
:
10939 /* Check if this is a fused jcc:
10941 CMP like instruction
10945 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
10946 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
10947 branch_fragP
= i386_next_jcc_frag (pad_fragP
);
10950 /* The BRANCH_PADDING frag is merged with the
10951 FUSED_JCC_PADDING frag. */
10952 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10953 /* CMP like instruction size. */
10954 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
10955 frag_wane (pad_fragP
);
10956 /* Skip to branch_fragP. */
10957 next_fragP
= branch_fragP
;
10959 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
10961 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
10963 next_fragP
->fr_subtype
10964 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
10965 next_fragP
->tc_frag_data
.max_bytes
10966 = next_fragP
->tc_frag_data
.max_prefix_length
;
10967 /* This will be updated in the BRANCH_PREFIX scan. */
10968 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
10971 frag_wane (next_fragP
);
10976 /* Stop if there is no BRANCH_PREFIX. */
10977 if (!align_branch_prefix_size
)
10980 /* Scan for BRANCH_PREFIX. */
10981 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
10983 if (fragP
->fr_type
!= rs_machine_dependent
10984 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10988 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
10989 COND_JUMP_PREFIX. */
10990 max_prefix_length
= 0;
10991 for (next_fragP
= fragP
;
10992 next_fragP
!= NULL
;
10993 next_fragP
= next_fragP
->fr_next
)
10995 if (next_fragP
->fr_type
== rs_fill
)
10996 /* Skip rs_fill frags. */
10998 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
10999 /* Stop for all other frags. */
11002 /* rs_machine_dependent frags. */
11003 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11006 /* Count BRANCH_PREFIX frags. */
11007 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11009 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11010 frag_wane (next_fragP
);
11014 += next_fragP
->tc_frag_data
.max_bytes
;
11016 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11018 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11019 == FUSED_JCC_PADDING
))
11021 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11022 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11026 /* Stop for other rs_machine_dependent frags. */
11030 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11032 /* Skip to the next frag. */
11033 fragP
= next_fragP
;
11037 /* Compute padding size for
11040 CMP like instruction
11042 COND_JUMP/UNCOND_JUMP
11047 COND_JUMP/UNCOND_JUMP
11051 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11053 unsigned int offset
, size
, padding_size
;
11054 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11056 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11058 address
= fragP
->fr_address
;
11059 address
+= fragP
->fr_fix
;
11061 /* CMP like instrunction size. */
11062 size
= fragP
->tc_frag_data
.cmp_size
;
11064 /* The base size of the branch frag. */
11065 size
+= branch_fragP
->fr_fix
;
11067 /* Add opcode and displacement bytes for the rs_machine_dependent
11069 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11070 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11072 /* Check if branch is within boundary and doesn't end at the last
11074 offset
= address
& ((1U << align_branch_power
) - 1);
11075 if ((offset
+ size
) >= (1U << align_branch_power
))
11076 /* Padding needed to avoid crossing boundary. */
11077 padding_size
= (1U << align_branch_power
) - offset
;
11079 /* No padding needed. */
11082 /* The return value may be saved in tc_frag_data.length which is
11084 if (!fits_in_unsigned_byte (padding_size
))
11087 return padding_size
;
11090 /* i386_generic_table_relax_frag()
11092 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11093 grow/shrink padding to align branch frags. Hand others to
11097 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11099 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11100 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11102 long padding_size
= i386_branch_padding_size (fragP
, 0);
11103 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11105 /* When the BRANCH_PREFIX frag is used, the computed address
11106 must match the actual address and there should be no padding. */
11107 if (fragP
->tc_frag_data
.padding_address
11108 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11112 /* Update the padding size. */
11114 fragP
->tc_frag_data
.length
= padding_size
;
11118 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11120 fragS
*padding_fragP
, *next_fragP
;
11121 long padding_size
, left_size
, last_size
;
11123 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11124 if (!padding_fragP
)
11125 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11126 return (fragP
->tc_frag_data
.length
11127 - fragP
->tc_frag_data
.last_length
);
11129 /* Compute the relative address of the padding frag in the very
11130 first time where the BRANCH_PREFIX frag sizes are zero. */
11131 if (!fragP
->tc_frag_data
.padding_address
)
11132 fragP
->tc_frag_data
.padding_address
11133 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11135 /* First update the last length from the previous interation. */
11136 left_size
= fragP
->tc_frag_data
.prefix_length
;
11137 for (next_fragP
= fragP
;
11138 next_fragP
!= padding_fragP
;
11139 next_fragP
= next_fragP
->fr_next
)
11140 if (next_fragP
->fr_type
== rs_machine_dependent
11141 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11146 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11150 if (max
> left_size
)
11155 next_fragP
->tc_frag_data
.last_length
= size
;
11159 next_fragP
->tc_frag_data
.last_length
= 0;
11162 /* Check the padding size for the padding frag. */
11163 padding_size
= i386_branch_padding_size
11164 (padding_fragP
, (fragP
->fr_address
11165 + fragP
->tc_frag_data
.padding_address
));
11167 last_size
= fragP
->tc_frag_data
.prefix_length
;
11168 /* Check if there is change from the last interation. */
11169 if (padding_size
== last_size
)
11171 /* Update the expected address of the padding frag. */
11172 padding_fragP
->tc_frag_data
.padding_address
11173 = (fragP
->fr_address
+ padding_size
11174 + fragP
->tc_frag_data
.padding_address
);
11178 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11180 /* No padding if there is no sufficient room. Clear the
11181 expected address of the padding frag. */
11182 padding_fragP
->tc_frag_data
.padding_address
= 0;
11186 /* Store the expected address of the padding frag. */
11187 padding_fragP
->tc_frag_data
.padding_address
11188 = (fragP
->fr_address
+ padding_size
11189 + fragP
->tc_frag_data
.padding_address
);
11191 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11193 /* Update the length for the current interation. */
11194 left_size
= padding_size
;
11195 for (next_fragP
= fragP
;
11196 next_fragP
!= padding_fragP
;
11197 next_fragP
= next_fragP
->fr_next
)
11198 if (next_fragP
->fr_type
== rs_machine_dependent
11199 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11204 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11208 if (max
> left_size
)
11213 next_fragP
->tc_frag_data
.length
= size
;
11217 next_fragP
->tc_frag_data
.length
= 0;
11220 return (fragP
->tc_frag_data
.length
11221 - fragP
->tc_frag_data
.last_length
);
11223 return relax_frag (segment
, fragP
, stretch
);
11226 /* md_estimate_size_before_relax()
11228 Called just before relax() for rs_machine_dependent frags. The x86
11229 assembler uses these frags to handle variable size jump
11232 Any symbol that is now undefined will not become defined.
11233 Return the correct fr_subtype in the frag.
11234 Return the initial "guess for variable size of frag" to caller.
11235 The guess is actually the growth beyond the fixed part. Whatever
11236 we do to grow the fixed or variable part contributes to our
11240 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11242 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11243 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11244 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11246 i386_classify_machine_dependent_frag (fragP
);
11247 return fragP
->tc_frag_data
.length
;
11250 /* We've already got fragP->fr_subtype right; all we have to do is
11251 check for un-relaxable symbols. On an ELF system, we can't relax
11252 an externally visible symbol, because it may be overridden by a
11254 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11255 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11257 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11260 #if defined (OBJ_COFF) && defined (TE_PE)
11261 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11262 && S_IS_WEAK (fragP
->fr_symbol
))
11266 /* Symbol is undefined in this segment, or we need to keep a
11267 reloc so that weak symbols can be overridden. */
11268 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11269 enum bfd_reloc_code_real reloc_type
;
11270 unsigned char *opcode
;
11273 if (fragP
->fr_var
!= NO_RELOC
)
11274 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11275 else if (size
== 2)
11276 reloc_type
= BFD_RELOC_16_PCREL
;
11277 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11278 else if (need_plt32_p (fragP
->fr_symbol
))
11279 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11282 reloc_type
= BFD_RELOC_32_PCREL
;
11284 old_fr_fix
= fragP
->fr_fix
;
11285 opcode
= (unsigned char *) fragP
->fr_opcode
;
11287 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11290 /* Make jmp (0xeb) a (d)word displacement jump. */
11292 fragP
->fr_fix
+= size
;
11293 fix_new (fragP
, old_fr_fix
, size
,
11295 fragP
->fr_offset
, 1,
11301 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11303 /* Negate the condition, and branch past an
11304 unconditional jump. */
11307 /* Insert an unconditional jump. */
11309 /* We added two extra opcode bytes, and have a two byte
11311 fragP
->fr_fix
+= 2 + 2;
11312 fix_new (fragP
, old_fr_fix
+ 2, 2,
11314 fragP
->fr_offset
, 1,
11318 /* Fall through. */
11321 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11325 fragP
->fr_fix
+= 1;
11326 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11328 fragP
->fr_offset
, 1,
11329 BFD_RELOC_8_PCREL
);
11330 fixP
->fx_signed
= 1;
11334 /* This changes the byte-displacement jump 0x7N
11335 to the (d)word-displacement jump 0x0f,0x8N. */
11336 opcode
[1] = opcode
[0] + 0x10;
11337 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11338 /* We've added an opcode byte. */
11339 fragP
->fr_fix
+= 1 + size
;
11340 fix_new (fragP
, old_fr_fix
+ 1, size
,
11342 fragP
->fr_offset
, 1,
11347 BAD_CASE (fragP
->fr_subtype
);
11351 return fragP
->fr_fix
- old_fr_fix
;
11354 /* Guess size depending on current relax state. Initially the relax
11355 state will correspond to a short jump and we return 1, because
11356 the variable part of the frag (the branch offset) is one byte
11357 long. However, we can relax a section more than once and in that
11358 case we must either set fr_subtype back to the unrelaxed state,
11359 or return the value for the appropriate branch. */
11360 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11363 /* Called after relax() is finished.
11365 In: Address of frag.
11366 fr_type == rs_machine_dependent.
11367 fr_subtype is what the address relaxed to.
11369 Out: Any fixSs and constants are set up.
11370 Caller will turn frag into a ".space 0". */
11373 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11376 unsigned char *opcode
;
11377 unsigned char *where_to_put_displacement
= NULL
;
11378 offsetT target_address
;
11379 offsetT opcode_address
;
11380 unsigned int extension
= 0;
11381 offsetT displacement_from_opcode_start
;
11383 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11384 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11385 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11387 /* Generate nop padding. */
11388 unsigned int size
= fragP
->tc_frag_data
.length
;
11391 if (size
> fragP
->tc_frag_data
.max_bytes
)
11397 const char *branch
= "branch";
11398 const char *prefix
= "";
11399 fragS
*padding_fragP
;
11400 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11403 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11404 switch (fragP
->tc_frag_data
.default_prefix
)
11409 case CS_PREFIX_OPCODE
:
11412 case DS_PREFIX_OPCODE
:
11415 case ES_PREFIX_OPCODE
:
11418 case FS_PREFIX_OPCODE
:
11421 case GS_PREFIX_OPCODE
:
11424 case SS_PREFIX_OPCODE
:
11429 msg
= _("%s:%u: add %d%s at 0x%llx to align "
11430 "%s within %d-byte boundary\n");
11432 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
11433 "align %s within %d-byte boundary\n");
11437 padding_fragP
= fragP
;
11438 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11439 "%s within %d-byte boundary\n");
11443 switch (padding_fragP
->tc_frag_data
.branch_type
)
11445 case align_branch_jcc
:
11448 case align_branch_fused
:
11449 branch
= "fused jcc";
11451 case align_branch_jmp
:
11454 case align_branch_call
:
11457 case align_branch_indirect
:
11458 branch
= "indiret branch";
11460 case align_branch_ret
:
11467 fprintf (stdout
, msg
,
11468 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
11469 (long long) fragP
->fr_address
, branch
,
11470 1 << align_branch_power
);
11472 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11473 memset (fragP
->fr_opcode
,
11474 fragP
->tc_frag_data
.default_prefix
, size
);
11476 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
11478 fragP
->fr_fix
+= size
;
11483 opcode
= (unsigned char *) fragP
->fr_opcode
;
11485 /* Address we want to reach in file space. */
11486 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
11488 /* Address opcode resides at in file space. */
11489 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
11491 /* Displacement from opcode start to fill into instruction. */
11492 displacement_from_opcode_start
= target_address
- opcode_address
;
11494 if ((fragP
->fr_subtype
& BIG
) == 0)
11496 /* Don't have to change opcode. */
11497 extension
= 1; /* 1 opcode + 1 displacement */
11498 where_to_put_displacement
= &opcode
[1];
11502 if (no_cond_jump_promotion
11503 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
11504 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
11505 _("long jump required"));
11507 switch (fragP
->fr_subtype
)
11509 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
11510 extension
= 4; /* 1 opcode + 4 displacement */
11512 where_to_put_displacement
= &opcode
[1];
11515 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
11516 extension
= 2; /* 1 opcode + 2 displacement */
11518 where_to_put_displacement
= &opcode
[1];
11521 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
11522 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
11523 extension
= 5; /* 2 opcode + 4 displacement */
11524 opcode
[1] = opcode
[0] + 0x10;
11525 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11526 where_to_put_displacement
= &opcode
[2];
11529 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
11530 extension
= 3; /* 2 opcode + 2 displacement */
11531 opcode
[1] = opcode
[0] + 0x10;
11532 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11533 where_to_put_displacement
= &opcode
[2];
11536 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
11541 where_to_put_displacement
= &opcode
[3];
11545 BAD_CASE (fragP
->fr_subtype
);
11550 /* If size if less then four we are sure that the operand fits,
11551 but if it's 4, then it could be that the displacement is larger
11553 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
11555 && ((addressT
) (displacement_from_opcode_start
- extension
11556 + ((addressT
) 1 << 31))
11557 > (((addressT
) 2 << 31) - 1)))
11559 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11560 _("jump target out of range"));
11561 /* Make us emit 0. */
11562 displacement_from_opcode_start
= extension
;
11564 /* Now put displacement after opcode. */
11565 md_number_to_chars ((char *) where_to_put_displacement
,
11566 (valueT
) (displacement_from_opcode_start
- extension
),
11567 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
11568 fragP
->fr_fix
+= extension
;
11571 /* Apply a fixup (fixP) to segment data, once it has been determined
11572 by our caller that we have all the info we need to fix it up.
11574 Parameter valP is the pointer to the value of the bits.
11576 On the 386, immediates, displacements, and data pointers are all in
11577 the same (little-endian) format, so we don't need to care about which
11578 we are handling. */
11581 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11583 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11584 valueT value
= *valP
;
11586 #if !defined (TE_Mach)
11587 if (fixP
->fx_pcrel
)
11589 switch (fixP
->fx_r_type
)
11595 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
11598 case BFD_RELOC_X86_64_32S
:
11599 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
11602 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
11605 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
11610 if (fixP
->fx_addsy
!= NULL
11611 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
11612 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
11613 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
11614 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
11615 && !use_rela_relocations
)
11617 /* This is a hack. There should be a better way to handle this.
11618 This covers for the fact that bfd_install_relocation will
11619 subtract the current location (for partial_inplace, PC relative
11620 relocations); see more below. */
11624 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
11627 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11629 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11632 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
11634 if ((sym_seg
== seg
11635 || (symbol_section_p (fixP
->fx_addsy
)
11636 && sym_seg
!= absolute_section
))
11637 && !generic_force_reloc (fixP
))
11639 /* Yes, we add the values in twice. This is because
11640 bfd_install_relocation subtracts them out again. I think
11641 bfd_install_relocation is broken, but I don't dare change
11643 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11647 #if defined (OBJ_COFF) && defined (TE_PE)
11648 /* For some reason, the PE format does not store a
11649 section address offset for a PC relative symbol. */
11650 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
11651 || S_IS_WEAK (fixP
->fx_addsy
))
11652 value
+= md_pcrel_from (fixP
);
11655 #if defined (OBJ_COFF) && defined (TE_PE)
11656 if (fixP
->fx_addsy
!= NULL
11657 && S_IS_WEAK (fixP
->fx_addsy
)
11658 /* PR 16858: Do not modify weak function references. */
11659 && ! fixP
->fx_pcrel
)
11661 #if !defined (TE_PEP)
11662 /* For x86 PE weak function symbols are neither PC-relative
11663 nor do they set S_IS_FUNCTION. So the only reliable way
11664 to detect them is to check the flags of their containing
11666 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
11667 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
11671 value
-= S_GET_VALUE (fixP
->fx_addsy
);
11675 /* Fix a few things - the dynamic linker expects certain values here,
11676 and we must not disappoint it. */
11677 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11678 if (IS_ELF
&& fixP
->fx_addsy
)
11679 switch (fixP
->fx_r_type
)
11681 case BFD_RELOC_386_PLT32
:
11682 case BFD_RELOC_X86_64_PLT32
:
11683 /* Make the jump instruction point to the address of the operand.
11684 At runtime we merely add the offset to the actual PLT entry.
11685 NB: Subtract the offset size only for jump instructions. */
11686 if (fixP
->fx_pcrel
)
11690 case BFD_RELOC_386_TLS_GD
:
11691 case BFD_RELOC_386_TLS_LDM
:
11692 case BFD_RELOC_386_TLS_IE_32
:
11693 case BFD_RELOC_386_TLS_IE
:
11694 case BFD_RELOC_386_TLS_GOTIE
:
11695 case BFD_RELOC_386_TLS_GOTDESC
:
11696 case BFD_RELOC_X86_64_TLSGD
:
11697 case BFD_RELOC_X86_64_TLSLD
:
11698 case BFD_RELOC_X86_64_GOTTPOFF
:
11699 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11700 value
= 0; /* Fully resolved at runtime. No addend. */
11702 case BFD_RELOC_386_TLS_LE
:
11703 case BFD_RELOC_386_TLS_LDO_32
:
11704 case BFD_RELOC_386_TLS_LE_32
:
11705 case BFD_RELOC_X86_64_DTPOFF32
:
11706 case BFD_RELOC_X86_64_DTPOFF64
:
11707 case BFD_RELOC_X86_64_TPOFF32
:
11708 case BFD_RELOC_X86_64_TPOFF64
:
11709 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11712 case BFD_RELOC_386_TLS_DESC_CALL
:
11713 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11714 value
= 0; /* Fully resolved at runtime. No addend. */
11715 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11719 case BFD_RELOC_VTABLE_INHERIT
:
11720 case BFD_RELOC_VTABLE_ENTRY
:
11727 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
11729 #endif /* !defined (TE_Mach) */
11731 /* Are we finished with this relocation now? */
11732 if (fixP
->fx_addsy
== NULL
)
11734 #if defined (OBJ_COFF) && defined (TE_PE)
11735 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
11738 /* Remember value for tc_gen_reloc. */
11739 fixP
->fx_addnumber
= value
;
11740 /* Clear out the frag for now. */
11744 else if (use_rela_relocations
)
11746 fixP
->fx_no_overflow
= 1;
11747 /* Remember value for tc_gen_reloc. */
11748 fixP
->fx_addnumber
= value
;
11752 md_number_to_chars (p
, value
, fixP
->fx_size
);
11756 md_atof (int type
, char *litP
, int *sizeP
)
11758 /* This outputs the LITTLENUMs in REVERSE order;
11759 in accord with the bigendian 386. */
11760 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
11763 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
11766 output_invalid (int c
)
11769 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11772 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11773 "(0x%x)", (unsigned char) c
);
11774 return output_invalid_buf
;
11777 /* REG_STRING starts *before* REGISTER_PREFIX. */
11779 static const reg_entry
*
11780 parse_real_register (char *reg_string
, char **end_op
)
11782 char *s
= reg_string
;
11784 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
11785 const reg_entry
*r
;
11787 /* Skip possible REGISTER_PREFIX and possible whitespace. */
11788 if (*s
== REGISTER_PREFIX
)
11791 if (is_space_char (*s
))
11794 p
= reg_name_given
;
11795 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
11797 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
11798 return (const reg_entry
*) NULL
;
11802 /* For naked regs, make sure that we are not dealing with an identifier.
11803 This prevents confusing an identifier like `eax_var' with register
11805 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
11806 return (const reg_entry
*) NULL
;
11810 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
11812 /* Handle floating point regs, allowing spaces in the (i) part. */
11813 if (r
== i386_regtab
/* %st is first entry of table */)
11815 if (!cpu_arch_flags
.bitfield
.cpu8087
11816 && !cpu_arch_flags
.bitfield
.cpu287
11817 && !cpu_arch_flags
.bitfield
.cpu387
)
11818 return (const reg_entry
*) NULL
;
11820 if (is_space_char (*s
))
11825 if (is_space_char (*s
))
11827 if (*s
>= '0' && *s
<= '7')
11829 int fpr
= *s
- '0';
11831 if (is_space_char (*s
))
11836 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
11841 /* We have "%st(" then garbage. */
11842 return (const reg_entry
*) NULL
;
11846 if (r
== NULL
|| allow_pseudo_reg
)
11849 if (operand_type_all_zero (&r
->reg_type
))
11850 return (const reg_entry
*) NULL
;
11852 if ((r
->reg_type
.bitfield
.dword
11853 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
11854 || r
->reg_type
.bitfield
.class == RegCR
11855 || r
->reg_type
.bitfield
.class == RegDR
11856 || r
->reg_type
.bitfield
.class == RegTR
)
11857 && !cpu_arch_flags
.bitfield
.cpui386
)
11858 return (const reg_entry
*) NULL
;
11860 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
11861 return (const reg_entry
*) NULL
;
11863 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
11865 if (r
->reg_type
.bitfield
.zmmword
11866 || r
->reg_type
.bitfield
.class == RegMask
)
11867 return (const reg_entry
*) NULL
;
11869 if (!cpu_arch_flags
.bitfield
.cpuavx
)
11871 if (r
->reg_type
.bitfield
.ymmword
)
11872 return (const reg_entry
*) NULL
;
11874 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
11875 return (const reg_entry
*) NULL
;
11879 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
11880 return (const reg_entry
*) NULL
;
11882 /* Don't allow fake index register unless allow_index_reg isn't 0. */
11883 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
11884 return (const reg_entry
*) NULL
;
11886 /* Upper 16 vector registers are only available with VREX in 64bit
11887 mode, and require EVEX encoding. */
11888 if (r
->reg_flags
& RegVRex
)
11890 if (!cpu_arch_flags
.bitfield
.cpuavx512f
11891 || flag_code
!= CODE_64BIT
)
11892 return (const reg_entry
*) NULL
;
11894 i
.vec_encoding
= vex_encoding_evex
;
11897 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
11898 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
11899 && flag_code
!= CODE_64BIT
)
11900 return (const reg_entry
*) NULL
;
11902 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
11904 return (const reg_entry
*) NULL
;
11909 /* REG_STRING starts *before* REGISTER_PREFIX. */
11911 static const reg_entry
*
11912 parse_register (char *reg_string
, char **end_op
)
11914 const reg_entry
*r
;
11916 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
11917 r
= parse_real_register (reg_string
, end_op
);
11922 char *save
= input_line_pointer
;
11926 input_line_pointer
= reg_string
;
11927 c
= get_symbol_name (®_string
);
11928 symbolP
= symbol_find (reg_string
);
11929 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
11931 const expressionS
*e
= symbol_get_value_expression (symbolP
);
11933 know (e
->X_op
== O_register
);
11934 know (e
->X_add_number
>= 0
11935 && (valueT
) e
->X_add_number
< i386_regtab_size
);
11936 r
= i386_regtab
+ e
->X_add_number
;
11937 if ((r
->reg_flags
& RegVRex
))
11938 i
.vec_encoding
= vex_encoding_evex
;
11939 *end_op
= input_line_pointer
;
11941 *input_line_pointer
= c
;
11942 input_line_pointer
= save
;
11948 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
11950 const reg_entry
*r
;
11951 char *end
= input_line_pointer
;
11954 r
= parse_register (name
, &input_line_pointer
);
11955 if (r
&& end
<= input_line_pointer
)
11957 *nextcharP
= *input_line_pointer
;
11958 *input_line_pointer
= 0;
11959 e
->X_op
= O_register
;
11960 e
->X_add_number
= r
- i386_regtab
;
11963 input_line_pointer
= end
;
11965 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11969 md_operand (expressionS
*e
)
11972 const reg_entry
*r
;
11974 switch (*input_line_pointer
)
11976 case REGISTER_PREFIX
:
11977 r
= parse_real_register (input_line_pointer
, &end
);
11980 e
->X_op
= O_register
;
11981 e
->X_add_number
= r
- i386_regtab
;
11982 input_line_pointer
= end
;
11987 gas_assert (intel_syntax
);
11988 end
= input_line_pointer
++;
11990 if (*input_line_pointer
== ']')
11992 ++input_line_pointer
;
11993 e
->X_op_symbol
= make_expr_symbol (e
);
11994 e
->X_add_symbol
= NULL
;
11995 e
->X_add_number
= 0;
12000 e
->X_op
= O_absent
;
12001 input_line_pointer
= end
;
12008 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12009 const char *md_shortopts
= "kVQ:sqnO::";
12011 const char *md_shortopts
= "qnO::";
12014 #define OPTION_32 (OPTION_MD_BASE + 0)
12015 #define OPTION_64 (OPTION_MD_BASE + 1)
12016 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12017 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12018 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12019 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12020 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12021 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12022 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12023 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12024 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12025 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12026 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12027 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12028 #define OPTION_X32 (OPTION_MD_BASE + 14)
12029 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12030 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12031 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12032 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12033 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12034 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12035 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12036 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12037 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12038 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12039 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12040 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12041 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12042 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12043 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12044 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12046 struct option md_longopts
[] =
12048 {"32", no_argument
, NULL
, OPTION_32
},
12049 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12050 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12051 {"64", no_argument
, NULL
, OPTION_64
},
12053 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12054 {"x32", no_argument
, NULL
, OPTION_X32
},
12055 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12056 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12058 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12059 {"march", required_argument
, NULL
, OPTION_MARCH
},
12060 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12061 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12062 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12063 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12064 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12065 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12066 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12067 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12068 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12069 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12070 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12071 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12072 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12073 # if defined (TE_PE) || defined (TE_PEP)
12074 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12076 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12077 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12078 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12079 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12080 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12081 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12082 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12083 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12084 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12085 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12086 {NULL
, no_argument
, NULL
, 0}
12088 size_t md_longopts_size
= sizeof (md_longopts
);
12091 md_parse_option (int c
, const char *arg
)
12094 char *arch
, *next
, *saved
, *type
;
12099 optimize_align_code
= 0;
12103 quiet_warnings
= 1;
12106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12107 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12108 should be emitted or not. FIXME: Not implemented. */
12110 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12114 /* -V: SVR4 argument to print version ID. */
12116 print_version_id ();
12119 /* -k: Ignore for FreeBSD compatibility. */
12124 /* -s: On i386 Solaris, this tells the native assembler to use
12125 .stab instead of .stab.excl. We always use .stab anyhow. */
12128 case OPTION_MSHARED
:
12132 case OPTION_X86_USED_NOTE
:
12133 if (strcasecmp (arg
, "yes") == 0)
12135 else if (strcasecmp (arg
, "no") == 0)
12138 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12143 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12144 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12147 const char **list
, **l
;
12149 list
= bfd_target_list ();
12150 for (l
= list
; *l
!= NULL
; l
++)
12151 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12152 || strcmp (*l
, "coff-x86-64") == 0
12153 || strcmp (*l
, "pe-x86-64") == 0
12154 || strcmp (*l
, "pei-x86-64") == 0
12155 || strcmp (*l
, "mach-o-x86-64") == 0)
12157 default_arch
= "x86_64";
12161 as_fatal (_("no compiled in support for x86_64"));
12167 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12171 const char **list
, **l
;
12173 list
= bfd_target_list ();
12174 for (l
= list
; *l
!= NULL
; l
++)
12175 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12177 default_arch
= "x86_64:32";
12181 as_fatal (_("no compiled in support for 32bit x86_64"));
12185 as_fatal (_("32bit x86_64 is only supported for ELF"));
12190 default_arch
= "i386";
12193 case OPTION_DIVIDE
:
12194 #ifdef SVR4_COMMENT_CHARS
12199 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12201 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12205 i386_comment_chars
= n
;
12211 saved
= xstrdup (arg
);
12213 /* Allow -march=+nosse. */
12219 as_fatal (_("invalid -march= option: `%s'"), arg
);
12220 next
= strchr (arch
, '+');
12223 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12225 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12228 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12231 cpu_arch_name
= cpu_arch
[j
].name
;
12232 cpu_sub_arch_name
= NULL
;
12233 cpu_arch_flags
= cpu_arch
[j
].flags
;
12234 cpu_arch_isa
= cpu_arch
[j
].type
;
12235 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12236 if (!cpu_arch_tune_set
)
12238 cpu_arch_tune
= cpu_arch_isa
;
12239 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12243 else if (*cpu_arch
[j
].name
== '.'
12244 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12246 /* ISA extension. */
12247 i386_cpu_flags flags
;
12249 flags
= cpu_flags_or (cpu_arch_flags
,
12250 cpu_arch
[j
].flags
);
12252 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12254 if (cpu_sub_arch_name
)
12256 char *name
= cpu_sub_arch_name
;
12257 cpu_sub_arch_name
= concat (name
,
12259 (const char *) NULL
);
12263 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12264 cpu_arch_flags
= flags
;
12265 cpu_arch_isa_flags
= flags
;
12269 = cpu_flags_or (cpu_arch_isa_flags
,
12270 cpu_arch
[j
].flags
);
12275 if (j
>= ARRAY_SIZE (cpu_arch
))
12277 /* Disable an ISA extension. */
12278 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12279 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12281 i386_cpu_flags flags
;
12283 flags
= cpu_flags_and_not (cpu_arch_flags
,
12284 cpu_noarch
[j
].flags
);
12285 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12287 if (cpu_sub_arch_name
)
12289 char *name
= cpu_sub_arch_name
;
12290 cpu_sub_arch_name
= concat (arch
,
12291 (const char *) NULL
);
12295 cpu_sub_arch_name
= xstrdup (arch
);
12296 cpu_arch_flags
= flags
;
12297 cpu_arch_isa_flags
= flags
;
12302 if (j
>= ARRAY_SIZE (cpu_noarch
))
12303 j
= ARRAY_SIZE (cpu_arch
);
12306 if (j
>= ARRAY_SIZE (cpu_arch
))
12307 as_fatal (_("invalid -march= option: `%s'"), arg
);
12311 while (next
!= NULL
);
12317 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12318 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12320 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12322 cpu_arch_tune_set
= 1;
12323 cpu_arch_tune
= cpu_arch
[j
].type
;
12324 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12328 if (j
>= ARRAY_SIZE (cpu_arch
))
12329 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12332 case OPTION_MMNEMONIC
:
12333 if (strcasecmp (arg
, "att") == 0)
12334 intel_mnemonic
= 0;
12335 else if (strcasecmp (arg
, "intel") == 0)
12336 intel_mnemonic
= 1;
12338 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12341 case OPTION_MSYNTAX
:
12342 if (strcasecmp (arg
, "att") == 0)
12344 else if (strcasecmp (arg
, "intel") == 0)
12347 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12350 case OPTION_MINDEX_REG
:
12351 allow_index_reg
= 1;
12354 case OPTION_MNAKED_REG
:
12355 allow_naked_reg
= 1;
12358 case OPTION_MSSE2AVX
:
12362 case OPTION_MSSE_CHECK
:
12363 if (strcasecmp (arg
, "error") == 0)
12364 sse_check
= check_error
;
12365 else if (strcasecmp (arg
, "warning") == 0)
12366 sse_check
= check_warning
;
12367 else if (strcasecmp (arg
, "none") == 0)
12368 sse_check
= check_none
;
12370 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12373 case OPTION_MOPERAND_CHECK
:
12374 if (strcasecmp (arg
, "error") == 0)
12375 operand_check
= check_error
;
12376 else if (strcasecmp (arg
, "warning") == 0)
12377 operand_check
= check_warning
;
12378 else if (strcasecmp (arg
, "none") == 0)
12379 operand_check
= check_none
;
12381 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12384 case OPTION_MAVXSCALAR
:
12385 if (strcasecmp (arg
, "128") == 0)
12386 avxscalar
= vex128
;
12387 else if (strcasecmp (arg
, "256") == 0)
12388 avxscalar
= vex256
;
12390 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12393 case OPTION_MVEXWIG
:
12394 if (strcmp (arg
, "0") == 0)
12396 else if (strcmp (arg
, "1") == 0)
12399 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12402 case OPTION_MADD_BND_PREFIX
:
12403 add_bnd_prefix
= 1;
12406 case OPTION_MEVEXLIG
:
12407 if (strcmp (arg
, "128") == 0)
12408 evexlig
= evexl128
;
12409 else if (strcmp (arg
, "256") == 0)
12410 evexlig
= evexl256
;
12411 else if (strcmp (arg
, "512") == 0)
12412 evexlig
= evexl512
;
12414 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
12417 case OPTION_MEVEXRCIG
:
12418 if (strcmp (arg
, "rne") == 0)
12420 else if (strcmp (arg
, "rd") == 0)
12422 else if (strcmp (arg
, "ru") == 0)
12424 else if (strcmp (arg
, "rz") == 0)
12427 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
12430 case OPTION_MEVEXWIG
:
12431 if (strcmp (arg
, "0") == 0)
12433 else if (strcmp (arg
, "1") == 0)
12436 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
12439 # if defined (TE_PE) || defined (TE_PEP)
12440 case OPTION_MBIG_OBJ
:
12445 case OPTION_MOMIT_LOCK_PREFIX
:
12446 if (strcasecmp (arg
, "yes") == 0)
12447 omit_lock_prefix
= 1;
12448 else if (strcasecmp (arg
, "no") == 0)
12449 omit_lock_prefix
= 0;
12451 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
12454 case OPTION_MFENCE_AS_LOCK_ADD
:
12455 if (strcasecmp (arg
, "yes") == 0)
12457 else if (strcasecmp (arg
, "no") == 0)
12460 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
12463 case OPTION_MRELAX_RELOCATIONS
:
12464 if (strcasecmp (arg
, "yes") == 0)
12465 generate_relax_relocations
= 1;
12466 else if (strcasecmp (arg
, "no") == 0)
12467 generate_relax_relocations
= 0;
12469 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
12472 case OPTION_MALIGN_BRANCH_BOUNDARY
:
12475 long int align
= strtoul (arg
, &end
, 0);
12480 align_branch_power
= 0;
12483 else if (align
>= 16)
12486 for (align_power
= 0;
12488 align
>>= 1, align_power
++)
12490 /* Limit alignment power to 31. */
12491 if (align
== 1 && align_power
< 32)
12493 align_branch_power
= align_power
;
12498 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
12502 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
12505 int align
= strtoul (arg
, &end
, 0);
12506 /* Some processors only support 5 prefixes. */
12507 if (*end
== '\0' && align
>= 0 && align
< 6)
12509 align_branch_prefix_size
= align
;
12512 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
12517 case OPTION_MALIGN_BRANCH
:
12519 saved
= xstrdup (arg
);
12523 next
= strchr (type
, '+');
12526 if (strcasecmp (type
, "jcc") == 0)
12527 align_branch
|= align_branch_jcc_bit
;
12528 else if (strcasecmp (type
, "fused") == 0)
12529 align_branch
|= align_branch_fused_bit
;
12530 else if (strcasecmp (type
, "jmp") == 0)
12531 align_branch
|= align_branch_jmp_bit
;
12532 else if (strcasecmp (type
, "call") == 0)
12533 align_branch
|= align_branch_call_bit
;
12534 else if (strcasecmp (type
, "ret") == 0)
12535 align_branch
|= align_branch_ret_bit
;
12536 else if (strcasecmp (type
, "indirect") == 0)
12537 align_branch
|= align_branch_indirect_bit
;
12539 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
12542 while (next
!= NULL
);
12546 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
12547 align_branch_power
= 5;
12548 align_branch_prefix_size
= 5;
12549 align_branch
= (align_branch_jcc_bit
12550 | align_branch_fused_bit
12551 | align_branch_jmp_bit
);
12554 case OPTION_MAMD64
:
12558 case OPTION_MINTEL64
:
12566 /* Turn off -Os. */
12567 optimize_for_space
= 0;
12569 else if (*arg
== 's')
12571 optimize_for_space
= 1;
12572 /* Turn on all encoding optimizations. */
12573 optimize
= INT_MAX
;
12577 optimize
= atoi (arg
);
12578 /* Turn off -Os. */
12579 optimize_for_space
= 0;
12589 #define MESSAGE_TEMPLATE \
12593 output_message (FILE *stream
, char *p
, char *message
, char *start
,
12594 int *left_p
, const char *name
, int len
)
12596 int size
= sizeof (MESSAGE_TEMPLATE
);
12597 int left
= *left_p
;
12599 /* Reserve 2 spaces for ", " or ",\0" */
12602 /* Check if there is any room. */
12610 p
= mempcpy (p
, name
, len
);
12614 /* Output the current message now and start a new one. */
12617 fprintf (stream
, "%s\n", message
);
12619 left
= size
- (start
- message
) - len
- 2;
12621 gas_assert (left
>= 0);
12623 p
= mempcpy (p
, name
, len
);
12631 show_arch (FILE *stream
, int ext
, int check
)
12633 static char message
[] = MESSAGE_TEMPLATE
;
12634 char *start
= message
+ 27;
12636 int size
= sizeof (MESSAGE_TEMPLATE
);
12643 left
= size
- (start
- message
);
12644 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12646 /* Should it be skipped? */
12647 if (cpu_arch
[j
].skip
)
12650 name
= cpu_arch
[j
].name
;
12651 len
= cpu_arch
[j
].len
;
12654 /* It is an extension. Skip if we aren't asked to show it. */
12665 /* It is an processor. Skip if we show only extension. */
12668 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12670 /* It is an impossible processor - skip. */
12674 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
12677 /* Display disabled extensions. */
12679 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12681 name
= cpu_noarch
[j
].name
;
12682 len
= cpu_noarch
[j
].len
;
12683 p
= output_message (stream
, p
, message
, start
, &left
, name
,
12688 fprintf (stream
, "%s\n", message
);
12692 md_show_usage (FILE *stream
)
12694 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12695 fprintf (stream
, _("\
12696 -Qy, -Qn ignored\n\
12697 -V print assembler version number\n\
12700 fprintf (stream
, _("\
12701 -n Do not optimize code alignment\n\
12702 -q quieten some warnings\n"));
12703 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12704 fprintf (stream
, _("\
12707 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12708 || defined (TE_PE) || defined (TE_PEP))
12709 fprintf (stream
, _("\
12710 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
12712 #ifdef SVR4_COMMENT_CHARS
12713 fprintf (stream
, _("\
12714 --divide do not treat `/' as a comment character\n"));
12716 fprintf (stream
, _("\
12717 --divide ignored\n"));
12719 fprintf (stream
, _("\
12720 -march=CPU[,+EXTENSION...]\n\
12721 generate code for CPU and EXTENSION, CPU is one of:\n"));
12722 show_arch (stream
, 0, 1);
12723 fprintf (stream
, _("\
12724 EXTENSION is combination of:\n"));
12725 show_arch (stream
, 1, 0);
12726 fprintf (stream
, _("\
12727 -mtune=CPU optimize for CPU, CPU is one of:\n"));
12728 show_arch (stream
, 0, 0);
12729 fprintf (stream
, _("\
12730 -msse2avx encode SSE instructions with VEX prefix\n"));
12731 fprintf (stream
, _("\
12732 -msse-check=[none|error|warning] (default: warning)\n\
12733 check SSE instructions\n"));
12734 fprintf (stream
, _("\
12735 -moperand-check=[none|error|warning] (default: warning)\n\
12736 check operand combinations for validity\n"));
12737 fprintf (stream
, _("\
12738 -mavxscalar=[128|256] (default: 128)\n\
12739 encode scalar AVX instructions with specific vector\n\
12741 fprintf (stream
, _("\
12742 -mvexwig=[0|1] (default: 0)\n\
12743 encode VEX instructions with specific VEX.W value\n\
12744 for VEX.W bit ignored instructions\n"));
12745 fprintf (stream
, _("\
12746 -mevexlig=[128|256|512] (default: 128)\n\
12747 encode scalar EVEX instructions with specific vector\n\
12749 fprintf (stream
, _("\
12750 -mevexwig=[0|1] (default: 0)\n\
12751 encode EVEX instructions with specific EVEX.W value\n\
12752 for EVEX.W bit ignored instructions\n"));
12753 fprintf (stream
, _("\
12754 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
12755 encode EVEX instructions with specific EVEX.RC value\n\
12756 for SAE-only ignored instructions\n"));
12757 fprintf (stream
, _("\
12758 -mmnemonic=[att|intel] "));
12759 if (SYSV386_COMPAT
)
12760 fprintf (stream
, _("(default: att)\n"));
12762 fprintf (stream
, _("(default: intel)\n"));
12763 fprintf (stream
, _("\
12764 use AT&T/Intel mnemonic\n"));
12765 fprintf (stream
, _("\
12766 -msyntax=[att|intel] (default: att)\n\
12767 use AT&T/Intel syntax\n"));
12768 fprintf (stream
, _("\
12769 -mindex-reg support pseudo index registers\n"));
12770 fprintf (stream
, _("\
12771 -mnaked-reg don't require `%%' prefix for registers\n"));
12772 fprintf (stream
, _("\
12773 -madd-bnd-prefix add BND prefix for all valid branches\n"));
12774 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12775 fprintf (stream
, _("\
12776 -mshared disable branch optimization for shared code\n"));
12777 fprintf (stream
, _("\
12778 -mx86-used-note=[no|yes] "));
12779 if (DEFAULT_X86_USED_NOTE
)
12780 fprintf (stream
, _("(default: yes)\n"));
12782 fprintf (stream
, _("(default: no)\n"));
12783 fprintf (stream
, _("\
12784 generate x86 used ISA and feature properties\n"));
12786 #if defined (TE_PE) || defined (TE_PEP)
12787 fprintf (stream
, _("\
12788 -mbig-obj generate big object files\n"));
12790 fprintf (stream
, _("\
12791 -momit-lock-prefix=[no|yes] (default: no)\n\
12792 strip all lock prefixes\n"));
12793 fprintf (stream
, _("\
12794 -mfence-as-lock-add=[no|yes] (default: no)\n\
12795 encode lfence, mfence and sfence as\n\
12796 lock addl $0x0, (%%{re}sp)\n"));
12797 fprintf (stream
, _("\
12798 -mrelax-relocations=[no|yes] "));
12799 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
12800 fprintf (stream
, _("(default: yes)\n"));
12802 fprintf (stream
, _("(default: no)\n"));
12803 fprintf (stream
, _("\
12804 generate relax relocations\n"));
12805 fprintf (stream
, _("\
12806 -malign-branch-boundary=NUM (default: 0)\n\
12807 align branches within NUM byte boundary\n"));
12808 fprintf (stream
, _("\
12809 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
12810 TYPE is combination of jcc, fused, jmp, call, ret,\n\
12812 specify types of branches to align\n"));
12813 fprintf (stream
, _("\
12814 -malign-branch-prefix-size=NUM (default: 5)\n\
12815 align branches with NUM prefixes per instruction\n"));
12816 fprintf (stream
, _("\
12817 -mbranches-within-32B-boundaries\n\
12818 align branches within 32 byte boundary\n"));
12819 fprintf (stream
, _("\
12820 -mamd64 accept only AMD64 ISA [default]\n"));
12821 fprintf (stream
, _("\
12822 -mintel64 accept only Intel64 ISA\n"));
12825 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
12826 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12827 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12829 /* Pick the target format to use. */
12832 i386_target_format (void)
12834 if (!strncmp (default_arch
, "x86_64", 6))
12836 update_code_flag (CODE_64BIT
, 1);
12837 if (default_arch
[6] == '\0')
12838 x86_elf_abi
= X86_64_ABI
;
12840 x86_elf_abi
= X86_64_X32_ABI
;
12842 else if (!strcmp (default_arch
, "i386"))
12843 update_code_flag (CODE_32BIT
, 1);
12844 else if (!strcmp (default_arch
, "iamcu"))
12846 update_code_flag (CODE_32BIT
, 1);
12847 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
12849 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
12850 cpu_arch_name
= "iamcu";
12851 cpu_sub_arch_name
= NULL
;
12852 cpu_arch_flags
= iamcu_flags
;
12853 cpu_arch_isa
= PROCESSOR_IAMCU
;
12854 cpu_arch_isa_flags
= iamcu_flags
;
12855 if (!cpu_arch_tune_set
)
12857 cpu_arch_tune
= cpu_arch_isa
;
12858 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12861 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
12862 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
12866 as_fatal (_("unknown architecture"));
12868 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
12869 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12870 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
12871 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12873 switch (OUTPUT_FLAVOR
)
12875 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
12876 case bfd_target_aout_flavour
:
12877 return AOUT_TARGET_FORMAT
;
12879 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
12880 # if defined (TE_PE) || defined (TE_PEP)
12881 case bfd_target_coff_flavour
:
12882 if (flag_code
== CODE_64BIT
)
12883 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
12886 # elif defined (TE_GO32)
12887 case bfd_target_coff_flavour
:
12888 return "coff-go32";
12890 case bfd_target_coff_flavour
:
12891 return "coff-i386";
12894 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12895 case bfd_target_elf_flavour
:
12897 const char *format
;
12899 switch (x86_elf_abi
)
12902 format
= ELF_TARGET_FORMAT
;
12904 tls_get_addr
= "___tls_get_addr";
12908 use_rela_relocations
= 1;
12911 tls_get_addr
= "__tls_get_addr";
12913 format
= ELF_TARGET_FORMAT64
;
12915 case X86_64_X32_ABI
:
12916 use_rela_relocations
= 1;
12919 tls_get_addr
= "__tls_get_addr";
12921 disallow_64bit_reloc
= 1;
12922 format
= ELF_TARGET_FORMAT32
;
12925 if (cpu_arch_isa
== PROCESSOR_L1OM
)
12927 if (x86_elf_abi
!= X86_64_ABI
)
12928 as_fatal (_("Intel L1OM is 64bit only"));
12929 return ELF_TARGET_L1OM_FORMAT
;
12931 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
12933 if (x86_elf_abi
!= X86_64_ABI
)
12934 as_fatal (_("Intel K1OM is 64bit only"));
12935 return ELF_TARGET_K1OM_FORMAT
;
12937 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
12939 if (x86_elf_abi
!= I386_ABI
)
12940 as_fatal (_("Intel MCU is 32bit only"));
12941 return ELF_TARGET_IAMCU_FORMAT
;
12947 #if defined (OBJ_MACH_O)
12948 case bfd_target_mach_o_flavour
:
12949 if (flag_code
== CODE_64BIT
)
12951 use_rela_relocations
= 1;
12953 return "mach-o-x86-64";
12956 return "mach-o-i386";
12964 #endif /* OBJ_MAYBE_ more than one */
12967 md_undefined_symbol (char *name
)
12969 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
12970 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
12971 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
12972 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
12976 if (symbol_find (name
))
12977 as_bad (_("GOT already in symbol table"));
12978 GOT_symbol
= symbol_new (name
, undefined_section
,
12979 (valueT
) 0, &zero_address_frag
);
12986 /* Round up a section size to the appropriate boundary. */
12989 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
12991 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12992 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
12994 /* For a.out, force the section size to be aligned. If we don't do
12995 this, BFD will align it for us, but it will not write out the
12996 final bytes of the section. This may be a bug in BFD, but it is
12997 easier to fix it here since that is how the other a.out targets
13001 align
= bfd_section_alignment (segment
);
13002 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13009 /* On the i386, PC-relative offsets are relative to the start of the
13010 next instruction. That is, the address of the offset, plus its
13011 size, since the offset is always the last part of the insn. */
13014 md_pcrel_from (fixS
*fixP
)
13016 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13022 s_bss (int ignore ATTRIBUTE_UNUSED
)
13026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13028 obj_elf_section_change_hook ();
13030 temp
= get_absolute_expression ();
13031 subseg_set (bss_section
, (subsegT
) temp
);
13032 demand_empty_rest_of_line ();
13037 /* Remember constant directive. */
13040 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13042 if (last_insn
.kind
!= last_insn_directive
13043 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13045 last_insn
.seg
= now_seg
;
13046 last_insn
.kind
= last_insn_directive
;
13047 last_insn
.name
= "constant directive";
13048 last_insn
.file
= as_where (&last_insn
.line
);
13053 i386_validate_fix (fixS
*fixp
)
13055 if (fixp
->fx_subsy
)
13057 if (fixp
->fx_subsy
== GOT_symbol
)
13059 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13063 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13064 if (fixp
->fx_tcbit2
)
13065 fixp
->fx_r_type
= (fixp
->fx_tcbit
13066 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13067 : BFD_RELOC_X86_64_GOTPCRELX
);
13070 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13075 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13077 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13079 fixp
->fx_subsy
= 0;
13082 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13083 else if (!object_64bit
)
13085 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13086 && fixp
->fx_tcbit2
)
13087 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13093 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13096 bfd_reloc_code_real_type code
;
13098 switch (fixp
->fx_r_type
)
13100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13101 case BFD_RELOC_SIZE32
:
13102 case BFD_RELOC_SIZE64
:
13103 if (S_IS_DEFINED (fixp
->fx_addsy
)
13104 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13106 /* Resolve size relocation against local symbol to size of
13107 the symbol plus addend. */
13108 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13109 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13110 && !fits_in_unsigned_long (value
))
13111 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13112 _("symbol size computation overflow"));
13113 fixp
->fx_addsy
= NULL
;
13114 fixp
->fx_subsy
= NULL
;
13115 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13119 /* Fall through. */
13121 case BFD_RELOC_X86_64_PLT32
:
13122 case BFD_RELOC_X86_64_GOT32
:
13123 case BFD_RELOC_X86_64_GOTPCREL
:
13124 case BFD_RELOC_X86_64_GOTPCRELX
:
13125 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13126 case BFD_RELOC_386_PLT32
:
13127 case BFD_RELOC_386_GOT32
:
13128 case BFD_RELOC_386_GOT32X
:
13129 case BFD_RELOC_386_GOTOFF
:
13130 case BFD_RELOC_386_GOTPC
:
13131 case BFD_RELOC_386_TLS_GD
:
13132 case BFD_RELOC_386_TLS_LDM
:
13133 case BFD_RELOC_386_TLS_LDO_32
:
13134 case BFD_RELOC_386_TLS_IE_32
:
13135 case BFD_RELOC_386_TLS_IE
:
13136 case BFD_RELOC_386_TLS_GOTIE
:
13137 case BFD_RELOC_386_TLS_LE_32
:
13138 case BFD_RELOC_386_TLS_LE
:
13139 case BFD_RELOC_386_TLS_GOTDESC
:
13140 case BFD_RELOC_386_TLS_DESC_CALL
:
13141 case BFD_RELOC_X86_64_TLSGD
:
13142 case BFD_RELOC_X86_64_TLSLD
:
13143 case BFD_RELOC_X86_64_DTPOFF32
:
13144 case BFD_RELOC_X86_64_DTPOFF64
:
13145 case BFD_RELOC_X86_64_GOTTPOFF
:
13146 case BFD_RELOC_X86_64_TPOFF32
:
13147 case BFD_RELOC_X86_64_TPOFF64
:
13148 case BFD_RELOC_X86_64_GOTOFF64
:
13149 case BFD_RELOC_X86_64_GOTPC32
:
13150 case BFD_RELOC_X86_64_GOT64
:
13151 case BFD_RELOC_X86_64_GOTPCREL64
:
13152 case BFD_RELOC_X86_64_GOTPC64
:
13153 case BFD_RELOC_X86_64_GOTPLT64
:
13154 case BFD_RELOC_X86_64_PLTOFF64
:
13155 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13156 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13157 case BFD_RELOC_RVA
:
13158 case BFD_RELOC_VTABLE_ENTRY
:
13159 case BFD_RELOC_VTABLE_INHERIT
:
13161 case BFD_RELOC_32_SECREL
:
13163 code
= fixp
->fx_r_type
;
13165 case BFD_RELOC_X86_64_32S
:
13166 if (!fixp
->fx_pcrel
)
13168 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13169 code
= fixp
->fx_r_type
;
13172 /* Fall through. */
13174 if (fixp
->fx_pcrel
)
13176 switch (fixp
->fx_size
)
13179 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13180 _("can not do %d byte pc-relative relocation"),
13182 code
= BFD_RELOC_32_PCREL
;
13184 case 1: code
= BFD_RELOC_8_PCREL
; break;
13185 case 2: code
= BFD_RELOC_16_PCREL
; break;
13186 case 4: code
= BFD_RELOC_32_PCREL
; break;
13188 case 8: code
= BFD_RELOC_64_PCREL
; break;
13194 switch (fixp
->fx_size
)
13197 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13198 _("can not do %d byte relocation"),
13200 code
= BFD_RELOC_32
;
13202 case 1: code
= BFD_RELOC_8
; break;
13203 case 2: code
= BFD_RELOC_16
; break;
13204 case 4: code
= BFD_RELOC_32
; break;
13206 case 8: code
= BFD_RELOC_64
; break;
13213 if ((code
== BFD_RELOC_32
13214 || code
== BFD_RELOC_32_PCREL
13215 || code
== BFD_RELOC_X86_64_32S
)
13217 && fixp
->fx_addsy
== GOT_symbol
)
13220 code
= BFD_RELOC_386_GOTPC
;
13222 code
= BFD_RELOC_X86_64_GOTPC32
;
13224 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13226 && fixp
->fx_addsy
== GOT_symbol
)
13228 code
= BFD_RELOC_X86_64_GOTPC64
;
13231 rel
= XNEW (arelent
);
13232 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13233 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13235 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13237 if (!use_rela_relocations
)
13239 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13240 vtable entry to be used in the relocation's section offset. */
13241 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13242 rel
->address
= fixp
->fx_offset
;
13243 #if defined (OBJ_COFF) && defined (TE_PE)
13244 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13245 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13250 /* Use the rela in 64bit mode. */
13253 if (disallow_64bit_reloc
)
13256 case BFD_RELOC_X86_64_DTPOFF64
:
13257 case BFD_RELOC_X86_64_TPOFF64
:
13258 case BFD_RELOC_64_PCREL
:
13259 case BFD_RELOC_X86_64_GOTOFF64
:
13260 case BFD_RELOC_X86_64_GOT64
:
13261 case BFD_RELOC_X86_64_GOTPCREL64
:
13262 case BFD_RELOC_X86_64_GOTPC64
:
13263 case BFD_RELOC_X86_64_GOTPLT64
:
13264 case BFD_RELOC_X86_64_PLTOFF64
:
13265 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13266 _("cannot represent relocation type %s in x32 mode"),
13267 bfd_get_reloc_code_name (code
));
13273 if (!fixp
->fx_pcrel
)
13274 rel
->addend
= fixp
->fx_offset
;
13278 case BFD_RELOC_X86_64_PLT32
:
13279 case BFD_RELOC_X86_64_GOT32
:
13280 case BFD_RELOC_X86_64_GOTPCREL
:
13281 case BFD_RELOC_X86_64_GOTPCRELX
:
13282 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13283 case BFD_RELOC_X86_64_TLSGD
:
13284 case BFD_RELOC_X86_64_TLSLD
:
13285 case BFD_RELOC_X86_64_GOTTPOFF
:
13286 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13287 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13288 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13291 rel
->addend
= (section
->vma
13293 + fixp
->fx_addnumber
13294 + md_pcrel_from (fixp
));
13299 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13300 if (rel
->howto
== NULL
)
13302 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13303 _("cannot represent relocation type %s"),
13304 bfd_get_reloc_code_name (code
));
13305 /* Set howto to a garbage value so that we can keep going. */
13306 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13307 gas_assert (rel
->howto
!= NULL
);
13313 #include "tc-i386-intel.c"
13316 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13318 int saved_naked_reg
;
13319 char saved_register_dot
;
13321 saved_naked_reg
= allow_naked_reg
;
13322 allow_naked_reg
= 1;
13323 saved_register_dot
= register_chars
['.'];
13324 register_chars
['.'] = '.';
13325 allow_pseudo_reg
= 1;
13326 expression_and_evaluate (exp
);
13327 allow_pseudo_reg
= 0;
13328 register_chars
['.'] = saved_register_dot
;
13329 allow_naked_reg
= saved_naked_reg
;
13331 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13333 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13335 exp
->X_op
= O_constant
;
13336 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13337 .dw2_regnum
[flag_code
>> 1];
13340 exp
->X_op
= O_illegal
;
13345 tc_x86_frame_initial_instructions (void)
13347 static unsigned int sp_regno
[2];
13349 if (!sp_regno
[flag_code
>> 1])
13351 char *saved_input
= input_line_pointer
;
13352 char sp
[][4] = {"esp", "rsp"};
13355 input_line_pointer
= sp
[flag_code
>> 1];
13356 tc_x86_parse_to_dw2regnum (&exp
);
13357 gas_assert (exp
.X_op
== O_constant
);
13358 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
13359 input_line_pointer
= saved_input
;
13362 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
13363 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
13367 x86_dwarf2_addr_size (void)
13369 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13370 if (x86_elf_abi
== X86_64_X32_ABI
)
13373 return bfd_arch_bits_per_address (stdoutput
) / 8;
13377 i386_elf_section_type (const char *str
, size_t len
)
13379 if (flag_code
== CODE_64BIT
13380 && len
== sizeof ("unwind") - 1
13381 && strncmp (str
, "unwind", 6) == 0)
13382 return SHT_X86_64_UNWIND
;
13389 i386_solaris_fix_up_eh_frame (segT sec
)
13391 if (flag_code
== CODE_64BIT
)
13392 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
13398 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
13402 exp
.X_op
= O_secrel
;
13403 exp
.X_add_symbol
= symbol
;
13404 exp
.X_add_number
= 0;
13405 emit_expr (&exp
, size
);
13409 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13410 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13413 x86_64_section_letter (int letter
, const char **ptr_msg
)
13415 if (flag_code
== CODE_64BIT
)
13418 return SHF_X86_64_LARGE
;
13420 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13423 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
13428 x86_64_section_word (char *str
, size_t len
)
13430 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
13431 return SHF_X86_64_LARGE
;
13437 handle_large_common (int small ATTRIBUTE_UNUSED
)
13439 if (flag_code
!= CODE_64BIT
)
13441 s_comm_internal (0, elf_common_parse
);
13442 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
13446 static segT lbss_section
;
13447 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
13448 asection
*saved_bss_section
= bss_section
;
13450 if (lbss_section
== NULL
)
13452 flagword applicable
;
13453 segT seg
= now_seg
;
13454 subsegT subseg
= now_subseg
;
13456 /* The .lbss section is for local .largecomm symbols. */
13457 lbss_section
= subseg_new (".lbss", 0);
13458 applicable
= bfd_applicable_section_flags (stdoutput
);
13459 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
13460 seg_info (lbss_section
)->bss
= 1;
13462 subseg_set (seg
, subseg
);
13465 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
13466 bss_section
= lbss_section
;
13468 s_comm_internal (0, elf_common_parse
);
13470 elf_com_section_ptr
= saved_com_section_ptr
;
13471 bss_section
= saved_bss_section
;
13474 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */