1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
294 invalid_vsib_address
,
295 invalid_vector_register_set
,
296 invalid_tmm_register_set
,
297 unsupported_vector_index_register
,
298 unsupported_broadcast
,
301 mask_not_on_destination
,
304 rc_sae_operand_not_last_imm
,
305 invalid_register_operand
,
310 /* TM holds the template for the insn were currently assembling. */
313 /* SUFFIX holds the instruction size suffix for byte, word, dword
314 or qword, if given. */
317 /* OPERANDS gives the number of given operands. */
318 unsigned int operands
;
320 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
321 of given register, displacement, memory operands and immediate
323 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
325 /* TYPES [i] is the type (see above #defines) which tells us how to
326 use OP[i] for the corresponding operand. */
327 i386_operand_type types
[MAX_OPERANDS
];
329 /* Displacement expression, immediate expression, or register for each
331 union i386_op op
[MAX_OPERANDS
];
333 /* Flags for operands. */
334 unsigned int flags
[MAX_OPERANDS
];
335 #define Operand_PCrel 1
336 #define Operand_Mem 2
338 /* Relocation type for operand */
339 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
341 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
342 the base index byte below. */
343 const reg_entry
*base_reg
;
344 const reg_entry
*index_reg
;
345 unsigned int log2_scale_factor
;
347 /* SEG gives the seg_entries of this insn. They are zero unless
348 explicit segment overrides are given. */
349 const seg_entry
*seg
[2];
351 /* Copied first memory operand string, for re-checking. */
354 /* PREFIX holds all the given prefix opcodes (usually null).
355 PREFIXES is the number of prefix opcodes. */
356 unsigned int prefixes
;
357 unsigned char prefix
[MAX_PREFIXES
];
359 /* Register is in low 3 bits of opcode. */
360 bfd_boolean short_form
;
362 /* The operand to a branch insn indicates an absolute branch. */
363 bfd_boolean jumpabsolute
;
365 /* Extended states. */
373 xstate_ymm
= 1 << 2 | xstate_xmm
,
375 xstate_zmm
= 1 << 3 | xstate_ymm
,
380 /* Has GOTPC or TLS relocation. */
381 bfd_boolean has_gotpc_tls_reloc
;
383 /* RM and SIB are the modrm byte and the sib byte where the
384 addressing modes of this insn are encoded. */
391 /* Masking attributes. */
392 struct Mask_Operation
*mask
;
394 /* Rounding control and SAE attributes. */
395 struct RC_Operation
*rounding
;
397 /* Broadcasting attributes. */
398 struct Broadcast_Operation
*broadcast
;
400 /* Compressed disp8*N attribute. */
401 unsigned int memshift
;
403 /* Prefer load or store in encoding. */
406 dir_encoding_default
= 0,
412 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
415 disp_encoding_default
= 0,
421 /* Prefer the REX byte in encoding. */
422 bfd_boolean rex_encoding
;
424 /* Disable instruction size optimization. */
425 bfd_boolean no_optimize
;
427 /* How to encode vector instructions. */
430 vex_encoding_default
= 0,
438 const char *rep_prefix
;
441 const char *hle_prefix
;
443 /* Have BND prefix. */
444 const char *bnd_prefix
;
446 /* Have NOTRACK prefix. */
447 const char *notrack_prefix
;
450 enum i386_error error
;
453 typedef struct _i386_insn i386_insn
;
455 /* Link RC type with corresponding string, that'll be looked for in
464 static const struct RC_name RC_NamesTable
[] =
466 { rne
, STRING_COMMA_LEN ("rn-sae") },
467 { rd
, STRING_COMMA_LEN ("rd-sae") },
468 { ru
, STRING_COMMA_LEN ("ru-sae") },
469 { rz
, STRING_COMMA_LEN ("rz-sae") },
470 { saeonly
, STRING_COMMA_LEN ("sae") },
473 /* List of chars besides those in app.c:symbol_chars that can start an
474 operand. Used to prevent the scrubber eating vital white-space. */
475 const char extra_symbol_chars
[] = "*%-([{}"
484 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
485 && !defined (TE_GNU) \
486 && !defined (TE_LINUX) \
487 && !defined (TE_FreeBSD) \
488 && !defined (TE_DragonFly) \
489 && !defined (TE_NetBSD))
490 /* This array holds the chars that always start a comment. If the
491 pre-processor is disabled, these aren't very useful. The option
492 --divide will remove '/' from this list. */
493 const char *i386_comment_chars
= "#/";
494 #define SVR4_COMMENT_CHARS 1
495 #define PREFIX_SEPARATOR '\\'
498 const char *i386_comment_chars
= "#";
499 #define PREFIX_SEPARATOR '/'
502 /* This array holds the chars that only start a comment at the beginning of
503 a line. If the line seems to have the form '# 123 filename'
504 .line and .file directives will appear in the pre-processed output.
505 Note that input_file.c hand checks for '#' at the beginning of the
506 first line of the input file. This is because the compiler outputs
507 #NO_APP at the beginning of its output.
508 Also note that comments started like this one will always work if
509 '/' isn't otherwise defined. */
510 const char line_comment_chars
[] = "#/";
512 const char line_separator_chars
[] = ";";
514 /* Chars that can be used to separate mant from exp in floating point
516 const char EXP_CHARS
[] = "eE";
518 /* Chars that mean this number is a floating point constant
521 const char FLT_CHARS
[] = "fFdDxX";
523 /* Tables for lexical analysis. */
524 static char mnemonic_chars
[256];
525 static char register_chars
[256];
526 static char operand_chars
[256];
527 static char identifier_chars
[256];
528 static char digit_chars
[256];
530 /* Lexical macros. */
531 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
532 #define is_operand_char(x) (operand_chars[(unsigned char) x])
533 #define is_register_char(x) (register_chars[(unsigned char) x])
534 #define is_space_char(x) ((x) == ' ')
535 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
536 #define is_digit_char(x) (digit_chars[(unsigned char) x])
538 /* All non-digit non-letter characters that may occur in an operand. */
539 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
541 /* md_assemble() always leaves the strings it's passed unaltered. To
542 effect this we maintain a stack of saved characters that we've smashed
543 with '\0's (indicating end of strings for various sub-fields of the
544 assembler instruction). */
545 static char save_stack
[32];
546 static char *save_stack_p
;
547 #define END_STRING_AND_SAVE(s) \
548 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
549 #define RESTORE_END_STRING(s) \
550 do { *(s) = *--save_stack_p; } while (0)
552 /* The instruction we're assembling. */
555 /* Possible templates for current insn. */
556 static const templates
*current_templates
;
558 /* Per instruction expressionS buffers: max displacements & immediates. */
559 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
560 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
562 /* Current operand we are working on. */
563 static int this_operand
= -1;
565 /* We support four different modes. FLAG_CODE variable is used to distinguish
573 static enum flag_code flag_code
;
574 static unsigned int object_64bit
;
575 static unsigned int disallow_64bit_reloc
;
576 static int use_rela_relocations
= 0;
577 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
578 static const char *tls_get_addr
;
580 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
581 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
582 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
584 /* The ELF ABI to use. */
592 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
595 #if defined (TE_PE) || defined (TE_PEP)
596 /* Use big object file format. */
597 static int use_big_obj
= 0;
600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
601 /* 1 if generating code for a shared library. */
602 static int shared
= 0;
605 /* 1 for intel syntax,
607 static int intel_syntax
= 0;
609 static enum x86_64_isa
611 amd64
= 1, /* AMD64 ISA. */
612 intel64
/* Intel64 ISA. */
615 /* 1 for intel mnemonic,
616 0 if att mnemonic. */
617 static int intel_mnemonic
= !SYSV386_COMPAT
;
619 /* 1 if pseudo registers are permitted. */
620 static int allow_pseudo_reg
= 0;
622 /* 1 if register prefix % not required. */
623 static int allow_naked_reg
= 0;
625 /* 1 if the assembler should add BND prefix for all control-transferring
626 instructions supporting it, even if this prefix wasn't specified
628 static int add_bnd_prefix
= 0;
630 /* 1 if pseudo index register, eiz/riz, is allowed . */
631 static int allow_index_reg
= 0;
633 /* 1 if the assembler should ignore LOCK prefix, even if it was
634 specified explicitly. */
635 static int omit_lock_prefix
= 0;
637 /* 1 if the assembler should encode lfence, mfence, and sfence as
638 "lock addl $0, (%{re}sp)". */
639 static int avoid_fence
= 0;
641 /* 1 if lfence should be inserted after every load. */
642 static int lfence_after_load
= 0;
644 /* Non-zero if lfence should be inserted before indirect branch. */
645 static enum lfence_before_indirect_branch_kind
647 lfence_branch_none
= 0,
648 lfence_branch_register
,
649 lfence_branch_memory
,
652 lfence_before_indirect_branch
;
654 /* Non-zero if lfence should be inserted before ret. */
655 static enum lfence_before_ret_kind
657 lfence_before_ret_none
= 0,
658 lfence_before_ret_not
,
659 lfence_before_ret_or
,
660 lfence_before_ret_shl
664 /* Types of previous instruction is .byte or prefix. */
679 /* 1 if the assembler should generate relax relocations. */
681 static int generate_relax_relocations
682 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
684 static enum check_kind
690 sse_check
, operand_check
= check_warning
;
692 /* Non-zero if branches should be aligned within power of 2 boundary. */
693 static int align_branch_power
= 0;
695 /* Types of branches to align. */
696 enum align_branch_kind
698 align_branch_none
= 0,
699 align_branch_jcc
= 1,
700 align_branch_fused
= 2,
701 align_branch_jmp
= 3,
702 align_branch_call
= 4,
703 align_branch_indirect
= 5,
707 /* Type bits of branches to align. */
708 enum align_branch_bit
710 align_branch_jcc_bit
= 1 << align_branch_jcc
,
711 align_branch_fused_bit
= 1 << align_branch_fused
,
712 align_branch_jmp_bit
= 1 << align_branch_jmp
,
713 align_branch_call_bit
= 1 << align_branch_call
,
714 align_branch_indirect_bit
= 1 << align_branch_indirect
,
715 align_branch_ret_bit
= 1 << align_branch_ret
718 static unsigned int align_branch
= (align_branch_jcc_bit
719 | align_branch_fused_bit
720 | align_branch_jmp_bit
);
722 /* Types of condition jump used by macro-fusion. */
725 mf_jcc_jo
= 0, /* base opcode 0x70 */
726 mf_jcc_jc
, /* base opcode 0x72 */
727 mf_jcc_je
, /* base opcode 0x74 */
728 mf_jcc_jna
, /* base opcode 0x76 */
729 mf_jcc_js
, /* base opcode 0x78 */
730 mf_jcc_jp
, /* base opcode 0x7a */
731 mf_jcc_jl
, /* base opcode 0x7c */
732 mf_jcc_jle
, /* base opcode 0x7e */
735 /* Types of compare flag-modifying insntructions used by macro-fusion. */
738 mf_cmp_test_and
, /* test/cmp */
739 mf_cmp_alu_cmp
, /* add/sub/cmp */
740 mf_cmp_incdec
/* inc/dec */
743 /* The maximum padding size for fused jcc. CMP like instruction can
744 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
746 #define MAX_FUSED_JCC_PADDING_SIZE 20
748 /* The maximum number of prefixes added for an instruction. */
749 static unsigned int align_branch_prefix_size
= 5;
752 1. Clear the REX_W bit with register operand if possible.
753 2. Above plus use 128bit vector instruction to clear the full vector
756 static int optimize
= 0;
759 1. Clear the REX_W bit with register operand if possible.
760 2. Above plus use 128bit vector instruction to clear the full vector
762 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
765 static int optimize_for_space
= 0;
767 /* Register prefix used for error message. */
768 static const char *register_prefix
= "%";
770 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
771 leave, push, and pop instructions so that gcc has the same stack
772 frame as in 32 bit mode. */
773 static char stackop_size
= '\0';
775 /* Non-zero to optimize code alignment. */
776 int optimize_align_code
= 1;
778 /* Non-zero to quieten some warnings. */
779 static int quiet_warnings
= 0;
782 static const char *cpu_arch_name
= NULL
;
783 static char *cpu_sub_arch_name
= NULL
;
785 /* CPU feature flags. */
786 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
788 /* If we have selected a cpu we are generating instructions for. */
789 static int cpu_arch_tune_set
= 0;
791 /* Cpu we are generating instructions for. */
792 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
794 /* CPU feature flags of cpu we are generating instructions for. */
795 static i386_cpu_flags cpu_arch_tune_flags
;
797 /* CPU instruction set architecture used. */
798 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
800 /* CPU feature flags of instruction set architecture used. */
801 i386_cpu_flags cpu_arch_isa_flags
;
803 /* If set, conditional jumps are not automatically promoted to handle
804 larger than a byte offset. */
805 static unsigned int no_cond_jump_promotion
= 0;
807 /* Encode SSE instructions with VEX prefix. */
808 static unsigned int sse2avx
;
810 /* Encode scalar AVX instructions with specific vector length. */
817 /* Encode VEX WIG instructions with specific vex.w. */
824 /* Encode scalar EVEX LIG instructions with specific vector length. */
832 /* Encode EVEX WIG instructions with specific evex.w. */
839 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
840 static enum rc_type evexrcig
= rne
;
842 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
843 static symbolS
*GOT_symbol
;
845 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
846 unsigned int x86_dwarf2_return_column
;
848 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
849 int x86_cie_data_alignment
;
851 /* Interface to relax_segment.
852 There are 3 major relax states for 386 jump insns because the
853 different types of jumps add different sizes to frags when we're
854 figuring out what sort of jump to choose to reach a given label.
856 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
857 branches which are handled by md_estimate_size_before_relax() and
858 i386_generic_table_relax_frag(). */
861 #define UNCOND_JUMP 0
863 #define COND_JUMP86 2
864 #define BRANCH_PADDING 3
865 #define BRANCH_PREFIX 4
866 #define FUSED_JCC_PADDING 5
871 #define SMALL16 (SMALL | CODE16)
873 #define BIG16 (BIG | CODE16)
877 #define INLINE __inline__
883 #define ENCODE_RELAX_STATE(type, size) \
884 ((relax_substateT) (((type) << 2) | (size)))
885 #define TYPE_FROM_RELAX_STATE(s) \
887 #define DISP_SIZE_FROM_RELAX_STATE(s) \
888 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
890 /* This table is used by relax_frag to promote short jumps to long
891 ones where necessary. SMALL (short) jumps may be promoted to BIG
892 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
893 don't allow a short jump in a 32 bit code segment to be promoted to
894 a 16 bit offset jump because it's slower (requires data size
895 prefix), and doesn't work, unless the destination is in the bottom
896 64k of the code segment (The top 16 bits of eip are zeroed). */
898 const relax_typeS md_relax_table
[] =
901 1) most positive reach of this state,
902 2) most negative reach of this state,
903 3) how many bytes this mode will have in the variable part of the frag
904 4) which index into the table to try if we can't fit into this one. */
906 /* UNCOND_JUMP states. */
907 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
908 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
909 /* dword jmp adds 4 bytes to frag:
910 0 extra opcode bytes, 4 displacement bytes. */
912 /* word jmp adds 2 byte2 to frag:
913 0 extra opcode bytes, 2 displacement bytes. */
916 /* COND_JUMP states. */
917 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
918 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
919 /* dword conditionals adds 5 bytes to frag:
920 1 extra opcode byte, 4 displacement bytes. */
922 /* word conditionals add 3 bytes to frag:
923 1 extra opcode byte, 2 displacement bytes. */
926 /* COND_JUMP86 states. */
927 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
928 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
929 /* dword conditionals adds 5 bytes to frag:
930 1 extra opcode byte, 4 displacement bytes. */
932 /* word conditionals add 4 bytes to frag:
933 1 displacement byte and a 3 byte long branch insn. */
937 static const arch_entry cpu_arch
[] =
939 /* Do not replace the first two entries - i386_target_format()
940 relies on them being there in this order. */
941 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
942 CPU_GENERIC32_FLAGS
, 0 },
943 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
944 CPU_GENERIC64_FLAGS
, 0 },
945 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
953 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
955 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
957 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
959 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
961 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
962 CPU_PENTIUMPRO_FLAGS
, 0 },
963 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
965 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
967 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
969 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
971 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
972 CPU_NOCONA_FLAGS
, 0 },
973 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
975 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
977 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
978 CPU_CORE2_FLAGS
, 1 },
979 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
980 CPU_CORE2_FLAGS
, 0 },
981 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
982 CPU_COREI7_FLAGS
, 0 },
983 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
985 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
987 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
988 CPU_IAMCU_FLAGS
, 0 },
989 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
991 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
993 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
994 CPU_ATHLON_FLAGS
, 0 },
995 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
997 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
999 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
1001 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
1002 CPU_AMDFAM10_FLAGS
, 0 },
1003 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1004 CPU_BDVER1_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1006 CPU_BDVER2_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1008 CPU_BDVER3_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1010 CPU_BDVER4_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1012 CPU_ZNVER1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1014 CPU_ZNVER2_FLAGS
, 0 },
1015 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1016 CPU_BTVER1_FLAGS
, 0 },
1017 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1018 CPU_BTVER2_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1020 CPU_8087_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1023 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1028 CPU_CMOV_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1030 CPU_FXSR_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1035 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1036 CPU_SSE2_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1038 CPU_SSE3_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE4A_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1042 CPU_SSSE3_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1044 CPU_SSE4_1_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1046 CPU_SSE4_2_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1048 CPU_SSE4_2_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1051 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1052 CPU_AVX2_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX512F_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512CD_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512ER_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512PF_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512DQ_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1064 CPU_AVX512BW_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1066 CPU_AVX512VL_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1070 CPU_VMFUNC_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1073 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1074 CPU_XSAVE_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1076 CPU_XSAVEOPT_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1078 CPU_XSAVEC_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1080 CPU_XSAVES_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1083 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1084 CPU_PCLMUL_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1086 CPU_PCLMUL_FLAGS
, 1 },
1087 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1088 CPU_FSGSBASE_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1090 CPU_RDRND_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1092 CPU_F16C_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1094 CPU_BMI2_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1097 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1098 CPU_FMA4_FLAGS
, 0 },
1099 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1101 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1103 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1104 CPU_MOVBE_FLAGS
, 0 },
1105 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1106 CPU_CX16_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1109 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1110 CPU_LZCNT_FLAGS
, 0 },
1111 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1112 CPU_POPCNT_FLAGS
, 0 },
1113 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1115 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1117 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1118 CPU_INVPCID_FLAGS
, 0 },
1119 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1120 CPU_CLFLUSH_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1123 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1124 CPU_SYSCALL_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1126 CPU_RDTSCP_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1128 CPU_3DNOW_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1130 CPU_3DNOWA_FLAGS
, 0 },
1131 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1132 CPU_PADLOCK_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1134 CPU_SVME_FLAGS
, 1 },
1135 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1136 CPU_SVME_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1138 CPU_SSE4A_FLAGS
, 0 },
1139 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1141 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1143 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1145 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1147 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1148 CPU_RDSEED_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1150 CPU_PRFCHW_FLAGS
, 0 },
1151 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1152 CPU_SMAP_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1155 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1157 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1158 CPU_CLFLUSHOPT_FLAGS
, 0 },
1159 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1160 CPU_PREFETCHWT1_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1163 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1164 CPU_CLWB_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1166 CPU_AVX512IFMA_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1168 CPU_AVX512VBMI_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_VBMI2_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1178 CPU_AVX512_VNNI_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1180 CPU_AVX512_BITALG_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1182 CPU_CLZERO_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1184 CPU_MWAITX_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1186 CPU_OSPKE_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1188 CPU_RDPID_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1190 CPU_PTWRITE_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1193 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1194 CPU_SHSTK_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1196 CPU_GFNI_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1198 CPU_VAES_FLAGS
, 0 },
1199 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1200 CPU_VPCLMULQDQ_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1202 CPU_WBNOINVD_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1204 CPU_PCONFIG_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1206 CPU_WAITPKG_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1208 CPU_CLDEMOTE_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1210 CPU_AMX_INT8_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1212 CPU_AMX_BF16_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1214 CPU_AMX_TILE_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1216 CPU_MOVDIRI_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1218 CPU_MOVDIR64B_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1220 CPU_AVX512_BF16_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1222 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1224 CPU_ENQCMD_FLAGS
, 0 },
1225 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1226 CPU_SERIALIZE_FLAGS
, 0 },
1227 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1228 CPU_RDPRU_FLAGS
, 0 },
1229 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1230 CPU_MCOMMIT_FLAGS
, 0 },
1231 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1232 CPU_SEV_ES_FLAGS
, 0 },
1233 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1234 CPU_TSXLDTRK_FLAGS
, 0 },
1237 static const noarch_entry cpu_noarch
[] =
1239 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1240 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1241 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1242 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1243 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1244 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1245 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1246 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1247 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1248 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1249 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1250 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1251 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1252 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1253 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1254 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1255 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1256 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1257 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1258 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1259 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1260 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1261 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1262 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1263 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1264 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1266 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1267 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1268 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1269 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1270 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1271 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1272 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1273 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1274 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1275 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1276 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1277 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1278 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1279 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1280 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1281 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1282 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1283 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1287 /* Like s_lcomm_internal in gas/read.c but the alignment string
1288 is allowed to be optional. */
1291 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1298 && *input_line_pointer
== ',')
1300 align
= parse_align (needs_align
- 1);
1302 if (align
== (addressT
) -1)
1317 bss_alloc (symbolP
, size
, align
);
1322 pe_lcomm (int needs_align
)
1324 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1328 const pseudo_typeS md_pseudo_table
[] =
1330 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1331 {"align", s_align_bytes
, 0},
1333 {"align", s_align_ptwo
, 0},
1335 {"arch", set_cpu_arch
, 0},
1339 {"lcomm", pe_lcomm
, 1},
1341 {"ffloat", float_cons
, 'f'},
1342 {"dfloat", float_cons
, 'd'},
1343 {"tfloat", float_cons
, 'x'},
1345 {"slong", signed_cons
, 4},
1346 {"noopt", s_ignore
, 0},
1347 {"optim", s_ignore
, 0},
1348 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1349 {"code16", set_code_flag
, CODE_16BIT
},
1350 {"code32", set_code_flag
, CODE_32BIT
},
1352 {"code64", set_code_flag
, CODE_64BIT
},
1354 {"intel_syntax", set_intel_syntax
, 1},
1355 {"att_syntax", set_intel_syntax
, 0},
1356 {"intel_mnemonic", set_intel_mnemonic
, 1},
1357 {"att_mnemonic", set_intel_mnemonic
, 0},
1358 {"allow_index_reg", set_allow_index_reg
, 1},
1359 {"disallow_index_reg", set_allow_index_reg
, 0},
1360 {"sse_check", set_check
, 0},
1361 {"operand_check", set_check
, 1},
1362 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1363 {"largecomm", handle_large_common
, 0},
1365 {"file", dwarf2_directive_file
, 0},
1366 {"loc", dwarf2_directive_loc
, 0},
1367 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1370 {"secrel32", pe_directive_secrel
, 0},
1375 /* For interface with expression (). */
1376 extern char *input_line_pointer
;
1378 /* Hash table for instruction mnemonic lookup. */
1379 static htab_t op_hash
;
1381 /* Hash table for register lookup. */
1382 static htab_t reg_hash
;
1384 /* Various efficient no-op patterns for aligning code labels.
1385 Note: Don't try to assemble the instructions in the comments.
1386 0L and 0w are not legal. */
1387 static const unsigned char f32_1
[] =
1389 static const unsigned char f32_2
[] =
1390 {0x66,0x90}; /* xchg %ax,%ax */
1391 static const unsigned char f32_3
[] =
1392 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1393 static const unsigned char f32_4
[] =
1394 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1395 static const unsigned char f32_6
[] =
1396 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1397 static const unsigned char f32_7
[] =
1398 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1399 static const unsigned char f16_3
[] =
1400 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1401 static const unsigned char f16_4
[] =
1402 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1403 static const unsigned char jump_disp8
[] =
1404 {0xeb}; /* jmp disp8 */
1405 static const unsigned char jump32_disp32
[] =
1406 {0xe9}; /* jmp disp32 */
1407 static const unsigned char jump16_disp32
[] =
1408 {0x66,0xe9}; /* jmp disp32 */
1409 /* 32-bit NOPs patterns. */
1410 static const unsigned char *const f32_patt
[] = {
1411 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1413 /* 16-bit NOPs patterns. */
1414 static const unsigned char *const f16_patt
[] = {
1415 f32_1
, f32_2
, f16_3
, f16_4
1417 /* nopl (%[re]ax) */
1418 static const unsigned char alt_3
[] =
1420 /* nopl 0(%[re]ax) */
1421 static const unsigned char alt_4
[] =
1422 {0x0f,0x1f,0x40,0x00};
1423 /* nopl 0(%[re]ax,%[re]ax,1) */
1424 static const unsigned char alt_5
[] =
1425 {0x0f,0x1f,0x44,0x00,0x00};
1426 /* nopw 0(%[re]ax,%[re]ax,1) */
1427 static const unsigned char alt_6
[] =
1428 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1429 /* nopl 0L(%[re]ax) */
1430 static const unsigned char alt_7
[] =
1431 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1432 /* nopl 0L(%[re]ax,%[re]ax,1) */
1433 static const unsigned char alt_8
[] =
1434 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1435 /* nopw 0L(%[re]ax,%[re]ax,1) */
1436 static const unsigned char alt_9
[] =
1437 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1438 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1439 static const unsigned char alt_10
[] =
1440 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1441 /* data16 nopw %cs:0L(%eax,%eax,1) */
1442 static const unsigned char alt_11
[] =
1443 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1444 /* 32-bit and 64-bit NOPs patterns. */
1445 static const unsigned char *const alt_patt
[] = {
1446 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1447 alt_9
, alt_10
, alt_11
1450 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1451 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1454 i386_output_nops (char *where
, const unsigned char *const *patt
,
1455 int count
, int max_single_nop_size
)
1458 /* Place the longer NOP first. */
1461 const unsigned char *nops
;
1463 if (max_single_nop_size
< 1)
1465 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1466 max_single_nop_size
);
1470 nops
= patt
[max_single_nop_size
- 1];
1472 /* Use the smaller one if the requsted one isn't available. */
1475 max_single_nop_size
--;
1476 nops
= patt
[max_single_nop_size
- 1];
1479 last
= count
% max_single_nop_size
;
1482 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1483 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1487 nops
= patt
[last
- 1];
1490 /* Use the smaller one plus one-byte NOP if the needed one
1493 nops
= patt
[last
- 1];
1494 memcpy (where
+ offset
, nops
, last
);
1495 where
[offset
+ last
] = *patt
[0];
1498 memcpy (where
+ offset
, nops
, last
);
1503 fits_in_imm7 (offsetT num
)
1505 return (num
& 0x7f) == num
;
1509 fits_in_imm31 (offsetT num
)
1511 return (num
& 0x7fffffff) == num
;
1514 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1515 single NOP instruction LIMIT. */
1518 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1520 const unsigned char *const *patt
= NULL
;
1521 int max_single_nop_size
;
1522 /* Maximum number of NOPs before switching to jump over NOPs. */
1523 int max_number_of_nops
;
1525 switch (fragP
->fr_type
)
1530 case rs_machine_dependent
:
1531 /* Allow NOP padding for jumps and calls. */
1532 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1533 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1540 /* We need to decide which NOP sequence to use for 32bit and
1541 64bit. When -mtune= is used:
1543 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1544 PROCESSOR_GENERIC32, f32_patt will be used.
1545 2. For the rest, alt_patt will be used.
1547 When -mtune= isn't used, alt_patt will be used if
1548 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1551 When -march= or .arch is used, we can't use anything beyond
1552 cpu_arch_isa_flags. */
1554 if (flag_code
== CODE_16BIT
)
1557 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1558 /* Limit number of NOPs to 2 in 16-bit mode. */
1559 max_number_of_nops
= 2;
1563 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1565 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1566 switch (cpu_arch_tune
)
1568 case PROCESSOR_UNKNOWN
:
1569 /* We use cpu_arch_isa_flags to check if we SHOULD
1570 optimize with nops. */
1571 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1576 case PROCESSOR_PENTIUM4
:
1577 case PROCESSOR_NOCONA
:
1578 case PROCESSOR_CORE
:
1579 case PROCESSOR_CORE2
:
1580 case PROCESSOR_COREI7
:
1581 case PROCESSOR_L1OM
:
1582 case PROCESSOR_K1OM
:
1583 case PROCESSOR_GENERIC64
:
1585 case PROCESSOR_ATHLON
:
1587 case PROCESSOR_AMDFAM10
:
1589 case PROCESSOR_ZNVER
:
1593 case PROCESSOR_I386
:
1594 case PROCESSOR_I486
:
1595 case PROCESSOR_PENTIUM
:
1596 case PROCESSOR_PENTIUMPRO
:
1597 case PROCESSOR_IAMCU
:
1598 case PROCESSOR_GENERIC32
:
1605 switch (fragP
->tc_frag_data
.tune
)
1607 case PROCESSOR_UNKNOWN
:
1608 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1609 PROCESSOR_UNKNOWN. */
1613 case PROCESSOR_I386
:
1614 case PROCESSOR_I486
:
1615 case PROCESSOR_PENTIUM
:
1616 case PROCESSOR_IAMCU
:
1618 case PROCESSOR_ATHLON
:
1620 case PROCESSOR_AMDFAM10
:
1622 case PROCESSOR_ZNVER
:
1624 case PROCESSOR_GENERIC32
:
1625 /* We use cpu_arch_isa_flags to check if we CAN optimize
1627 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1632 case PROCESSOR_PENTIUMPRO
:
1633 case PROCESSOR_PENTIUM4
:
1634 case PROCESSOR_NOCONA
:
1635 case PROCESSOR_CORE
:
1636 case PROCESSOR_CORE2
:
1637 case PROCESSOR_COREI7
:
1638 case PROCESSOR_L1OM
:
1639 case PROCESSOR_K1OM
:
1640 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1645 case PROCESSOR_GENERIC64
:
1651 if (patt
== f32_patt
)
1653 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1654 /* Limit number of NOPs to 2 for older processors. */
1655 max_number_of_nops
= 2;
1659 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1660 /* Limit number of NOPs to 7 for newer processors. */
1661 max_number_of_nops
= 7;
1666 limit
= max_single_nop_size
;
1668 if (fragP
->fr_type
== rs_fill_nop
)
1670 /* Output NOPs for .nop directive. */
1671 if (limit
> max_single_nop_size
)
1673 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1674 _("invalid single nop size: %d "
1675 "(expect within [0, %d])"),
1676 limit
, max_single_nop_size
);
1680 else if (fragP
->fr_type
!= rs_machine_dependent
)
1681 fragP
->fr_var
= count
;
1683 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1685 /* Generate jump over NOPs. */
1686 offsetT disp
= count
- 2;
1687 if (fits_in_imm7 (disp
))
1689 /* Use "jmp disp8" if possible. */
1691 where
[0] = jump_disp8
[0];
1697 unsigned int size_of_jump
;
1699 if (flag_code
== CODE_16BIT
)
1701 where
[0] = jump16_disp32
[0];
1702 where
[1] = jump16_disp32
[1];
1707 where
[0] = jump32_disp32
[0];
1711 count
-= size_of_jump
+ 4;
1712 if (!fits_in_imm31 (count
))
1714 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1715 _("jump over nop padding out of range"));
1719 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1720 where
+= size_of_jump
+ 4;
1724 /* Generate multiple NOPs. */
1725 i386_output_nops (where
, patt
, count
, limit
);
1729 operand_type_all_zero (const union i386_operand_type
*x
)
1731 switch (ARRAY_SIZE(x
->array
))
1742 return !x
->array
[0];
1749 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1751 switch (ARRAY_SIZE(x
->array
))
1767 x
->bitfield
.class = ClassNone
;
1768 x
->bitfield
.instance
= InstanceNone
;
1772 operand_type_equal (const union i386_operand_type
*x
,
1773 const union i386_operand_type
*y
)
1775 switch (ARRAY_SIZE(x
->array
))
1778 if (x
->array
[2] != y
->array
[2])
1782 if (x
->array
[1] != y
->array
[1])
1786 return x
->array
[0] == y
->array
[0];
1794 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1796 switch (ARRAY_SIZE(x
->array
))
1811 return !x
->array
[0];
1818 cpu_flags_equal (const union i386_cpu_flags
*x
,
1819 const union i386_cpu_flags
*y
)
1821 switch (ARRAY_SIZE(x
->array
))
1824 if (x
->array
[3] != y
->array
[3])
1828 if (x
->array
[2] != y
->array
[2])
1832 if (x
->array
[1] != y
->array
[1])
1836 return x
->array
[0] == y
->array
[0];
1844 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1846 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1847 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1850 static INLINE i386_cpu_flags
1851 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1853 switch (ARRAY_SIZE (x
.array
))
1856 x
.array
[3] &= y
.array
[3];
1859 x
.array
[2] &= y
.array
[2];
1862 x
.array
[1] &= y
.array
[1];
1865 x
.array
[0] &= y
.array
[0];
1873 static INLINE i386_cpu_flags
1874 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1876 switch (ARRAY_SIZE (x
.array
))
1879 x
.array
[3] |= y
.array
[3];
1882 x
.array
[2] |= y
.array
[2];
1885 x
.array
[1] |= y
.array
[1];
1888 x
.array
[0] |= y
.array
[0];
1896 static INLINE i386_cpu_flags
1897 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1899 switch (ARRAY_SIZE (x
.array
))
1902 x
.array
[3] &= ~y
.array
[3];
1905 x
.array
[2] &= ~y
.array
[2];
1908 x
.array
[1] &= ~y
.array
[1];
1911 x
.array
[0] &= ~y
.array
[0];
1919 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1921 #define CPU_FLAGS_ARCH_MATCH 0x1
1922 #define CPU_FLAGS_64BIT_MATCH 0x2
1924 #define CPU_FLAGS_PERFECT_MATCH \
1925 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1927 /* Return CPU flags match bits. */
1930 cpu_flags_match (const insn_template
*t
)
1932 i386_cpu_flags x
= t
->cpu_flags
;
1933 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1935 x
.bitfield
.cpu64
= 0;
1936 x
.bitfield
.cpuno64
= 0;
1938 if (cpu_flags_all_zero (&x
))
1940 /* This instruction is available on all archs. */
1941 match
|= CPU_FLAGS_ARCH_MATCH
;
1945 /* This instruction is available only on some archs. */
1946 i386_cpu_flags cpu
= cpu_arch_flags
;
1948 /* AVX512VL is no standalone feature - match it and then strip it. */
1949 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1951 x
.bitfield
.cpuavx512vl
= 0;
1953 cpu
= cpu_flags_and (x
, cpu
);
1954 if (!cpu_flags_all_zero (&cpu
))
1956 if (x
.bitfield
.cpuavx
)
1958 /* We need to check a few extra flags with AVX. */
1959 if (cpu
.bitfield
.cpuavx
1960 && (!t
->opcode_modifier
.sse2avx
1961 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1962 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1963 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1964 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1965 match
|= CPU_FLAGS_ARCH_MATCH
;
1967 else if (x
.bitfield
.cpuavx512f
)
1969 /* We need to check a few extra flags with AVX512F. */
1970 if (cpu
.bitfield
.cpuavx512f
1971 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1972 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1973 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1974 match
|= CPU_FLAGS_ARCH_MATCH
;
1977 match
|= CPU_FLAGS_ARCH_MATCH
;
1983 static INLINE i386_operand_type
1984 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1986 if (x
.bitfield
.class != y
.bitfield
.class)
1987 x
.bitfield
.class = ClassNone
;
1988 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1989 x
.bitfield
.instance
= InstanceNone
;
1991 switch (ARRAY_SIZE (x
.array
))
1994 x
.array
[2] &= y
.array
[2];
1997 x
.array
[1] &= y
.array
[1];
2000 x
.array
[0] &= y
.array
[0];
2008 static INLINE i386_operand_type
2009 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2011 gas_assert (y
.bitfield
.class == ClassNone
);
2012 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2014 switch (ARRAY_SIZE (x
.array
))
2017 x
.array
[2] &= ~y
.array
[2];
2020 x
.array
[1] &= ~y
.array
[1];
2023 x
.array
[0] &= ~y
.array
[0];
2031 static INLINE i386_operand_type
2032 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2034 gas_assert (x
.bitfield
.class == ClassNone
||
2035 y
.bitfield
.class == ClassNone
||
2036 x
.bitfield
.class == y
.bitfield
.class);
2037 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2038 y
.bitfield
.instance
== InstanceNone
||
2039 x
.bitfield
.instance
== y
.bitfield
.instance
);
2041 switch (ARRAY_SIZE (x
.array
))
2044 x
.array
[2] |= y
.array
[2];
2047 x
.array
[1] |= y
.array
[1];
2050 x
.array
[0] |= y
.array
[0];
2058 static INLINE i386_operand_type
2059 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2061 gas_assert (y
.bitfield
.class == ClassNone
);
2062 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2064 switch (ARRAY_SIZE (x
.array
))
2067 x
.array
[2] ^= y
.array
[2];
2070 x
.array
[1] ^= y
.array
[1];
2073 x
.array
[0] ^= y
.array
[0];
2081 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2082 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2083 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2084 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2085 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2086 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2087 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2088 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2089 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2090 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2091 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2092 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2093 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2094 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2095 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2096 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2097 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2108 operand_type_check (i386_operand_type t
, enum operand_type c
)
2113 return t
.bitfield
.class == Reg
;
2116 return (t
.bitfield
.imm8
2120 || t
.bitfield
.imm32s
2121 || t
.bitfield
.imm64
);
2124 return (t
.bitfield
.disp8
2125 || t
.bitfield
.disp16
2126 || t
.bitfield
.disp32
2127 || t
.bitfield
.disp32s
2128 || t
.bitfield
.disp64
);
2131 return (t
.bitfield
.disp8
2132 || t
.bitfield
.disp16
2133 || t
.bitfield
.disp32
2134 || t
.bitfield
.disp32s
2135 || t
.bitfield
.disp64
2136 || t
.bitfield
.baseindex
);
2145 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2146 between operand GIVEN and opeand WANTED for instruction template T. */
2149 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2152 return !((i
.types
[given
].bitfield
.byte
2153 && !t
->operand_types
[wanted
].bitfield
.byte
)
2154 || (i
.types
[given
].bitfield
.word
2155 && !t
->operand_types
[wanted
].bitfield
.word
)
2156 || (i
.types
[given
].bitfield
.dword
2157 && !t
->operand_types
[wanted
].bitfield
.dword
)
2158 || (i
.types
[given
].bitfield
.qword
2159 && !t
->operand_types
[wanted
].bitfield
.qword
)
2160 || (i
.types
[given
].bitfield
.tbyte
2161 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2164 /* Return 1 if there is no conflict in SIMD register between operand
2165 GIVEN and opeand WANTED for instruction template T. */
2168 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2171 return !((i
.types
[given
].bitfield
.xmmword
2172 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2173 || (i
.types
[given
].bitfield
.ymmword
2174 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2175 || (i
.types
[given
].bitfield
.zmmword
2176 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2177 || (i
.types
[given
].bitfield
.tmmword
2178 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2181 /* Return 1 if there is no conflict in any size between operand GIVEN
2182 and opeand WANTED for instruction template T. */
2185 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2188 return (match_operand_size (t
, wanted
, given
)
2189 && !((i
.types
[given
].bitfield
.unspecified
2191 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2192 || (i
.types
[given
].bitfield
.fword
2193 && !t
->operand_types
[wanted
].bitfield
.fword
)
2194 /* For scalar opcode templates to allow register and memory
2195 operands at the same time, some special casing is needed
2196 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2197 down-conversion vpmov*. */
2198 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2199 && t
->operand_types
[wanted
].bitfield
.byte
2200 + t
->operand_types
[wanted
].bitfield
.word
2201 + t
->operand_types
[wanted
].bitfield
.dword
2202 + t
->operand_types
[wanted
].bitfield
.qword
2203 > !!t
->opcode_modifier
.broadcast
)
2204 ? (i
.types
[given
].bitfield
.xmmword
2205 || i
.types
[given
].bitfield
.ymmword
2206 || i
.types
[given
].bitfield
.zmmword
)
2207 : !match_simd_size(t
, wanted
, given
))));
2210 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2211 operands for instruction template T, and it has MATCH_REVERSE set if there
2212 is no size conflict on any operands for the template with operands reversed
2213 (and the template allows for reversing in the first place). */
2215 #define MATCH_STRAIGHT 1
2216 #define MATCH_REVERSE 2
2218 static INLINE
unsigned int
2219 operand_size_match (const insn_template
*t
)
2221 unsigned int j
, match
= MATCH_STRAIGHT
;
2223 /* Don't check non-absolute jump instructions. */
2224 if (t
->opcode_modifier
.jump
2225 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2228 /* Check memory and accumulator operand size. */
2229 for (j
= 0; j
< i
.operands
; j
++)
2231 if (i
.types
[j
].bitfield
.class != Reg
2232 && i
.types
[j
].bitfield
.class != RegSIMD
2233 && t
->opcode_modifier
.anysize
)
2236 if (t
->operand_types
[j
].bitfield
.class == Reg
2237 && !match_operand_size (t
, j
, j
))
2243 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2244 && !match_simd_size (t
, j
, j
))
2250 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2251 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2257 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2264 if (!t
->opcode_modifier
.d
)
2268 i
.error
= operand_size_mismatch
;
2272 /* Check reverse. */
2273 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2275 for (j
= 0; j
< i
.operands
; j
++)
2277 unsigned int given
= i
.operands
- j
- 1;
2279 if (t
->operand_types
[j
].bitfield
.class == Reg
2280 && !match_operand_size (t
, j
, given
))
2283 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2284 && !match_simd_size (t
, j
, given
))
2287 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2288 && (!match_operand_size (t
, j
, given
)
2289 || !match_simd_size (t
, j
, given
)))
2292 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2296 return match
| MATCH_REVERSE
;
2300 operand_type_match (i386_operand_type overlap
,
2301 i386_operand_type given
)
2303 i386_operand_type temp
= overlap
;
2305 temp
.bitfield
.unspecified
= 0;
2306 temp
.bitfield
.byte
= 0;
2307 temp
.bitfield
.word
= 0;
2308 temp
.bitfield
.dword
= 0;
2309 temp
.bitfield
.fword
= 0;
2310 temp
.bitfield
.qword
= 0;
2311 temp
.bitfield
.tbyte
= 0;
2312 temp
.bitfield
.xmmword
= 0;
2313 temp
.bitfield
.ymmword
= 0;
2314 temp
.bitfield
.zmmword
= 0;
2315 temp
.bitfield
.tmmword
= 0;
2316 if (operand_type_all_zero (&temp
))
2319 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2323 i
.error
= operand_type_mismatch
;
2327 /* If given types g0 and g1 are registers they must be of the same type
2328 unless the expected operand type register overlap is null.
2329 Some Intel syntax memory operand size checking also happens here. */
2332 operand_type_register_match (i386_operand_type g0
,
2333 i386_operand_type t0
,
2334 i386_operand_type g1
,
2335 i386_operand_type t1
)
2337 if (g0
.bitfield
.class != Reg
2338 && g0
.bitfield
.class != RegSIMD
2339 && (!operand_type_check (g0
, anymem
)
2340 || g0
.bitfield
.unspecified
2341 || (t0
.bitfield
.class != Reg
2342 && t0
.bitfield
.class != RegSIMD
)))
2345 if (g1
.bitfield
.class != Reg
2346 && g1
.bitfield
.class != RegSIMD
2347 && (!operand_type_check (g1
, anymem
)
2348 || g1
.bitfield
.unspecified
2349 || (t1
.bitfield
.class != Reg
2350 && t1
.bitfield
.class != RegSIMD
)))
2353 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2354 && g0
.bitfield
.word
== g1
.bitfield
.word
2355 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2356 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2357 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2358 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2359 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2362 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2363 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2364 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2365 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2366 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2367 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2368 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2371 i
.error
= register_type_mismatch
;
2376 static INLINE
unsigned int
2377 register_number (const reg_entry
*r
)
2379 unsigned int nr
= r
->reg_num
;
2381 if (r
->reg_flags
& RegRex
)
2384 if (r
->reg_flags
& RegVRex
)
2390 static INLINE
unsigned int
2391 mode_from_disp_size (i386_operand_type t
)
2393 if (t
.bitfield
.disp8
)
2395 else if (t
.bitfield
.disp16
2396 || t
.bitfield
.disp32
2397 || t
.bitfield
.disp32s
)
2404 fits_in_signed_byte (addressT num
)
2406 return num
+ 0x80 <= 0xff;
2410 fits_in_unsigned_byte (addressT num
)
2416 fits_in_unsigned_word (addressT num
)
2418 return num
<= 0xffff;
2422 fits_in_signed_word (addressT num
)
2424 return num
+ 0x8000 <= 0xffff;
2428 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2433 return num
+ 0x80000000 <= 0xffffffff;
2435 } /* fits_in_signed_long() */
2438 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2443 return num
<= 0xffffffff;
2445 } /* fits_in_unsigned_long() */
2448 fits_in_disp8 (offsetT num
)
2450 int shift
= i
.memshift
;
2456 mask
= (1 << shift
) - 1;
2458 /* Return 0 if NUM isn't properly aligned. */
2462 /* Check if NUM will fit in 8bit after shift. */
2463 return fits_in_signed_byte (num
>> shift
);
2467 fits_in_imm4 (offsetT num
)
2469 return (num
& 0xf) == num
;
2472 static i386_operand_type
2473 smallest_imm_type (offsetT num
)
2475 i386_operand_type t
;
2477 operand_type_set (&t
, 0);
2478 t
.bitfield
.imm64
= 1;
2480 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2482 /* This code is disabled on the 486 because all the Imm1 forms
2483 in the opcode table are slower on the i486. They're the
2484 versions with the implicitly specified single-position
2485 displacement, which has another syntax if you really want to
2487 t
.bitfield
.imm1
= 1;
2488 t
.bitfield
.imm8
= 1;
2489 t
.bitfield
.imm8s
= 1;
2490 t
.bitfield
.imm16
= 1;
2491 t
.bitfield
.imm32
= 1;
2492 t
.bitfield
.imm32s
= 1;
2494 else if (fits_in_signed_byte (num
))
2496 t
.bitfield
.imm8
= 1;
2497 t
.bitfield
.imm8s
= 1;
2498 t
.bitfield
.imm16
= 1;
2499 t
.bitfield
.imm32
= 1;
2500 t
.bitfield
.imm32s
= 1;
2502 else if (fits_in_unsigned_byte (num
))
2504 t
.bitfield
.imm8
= 1;
2505 t
.bitfield
.imm16
= 1;
2506 t
.bitfield
.imm32
= 1;
2507 t
.bitfield
.imm32s
= 1;
2509 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2511 t
.bitfield
.imm16
= 1;
2512 t
.bitfield
.imm32
= 1;
2513 t
.bitfield
.imm32s
= 1;
2515 else if (fits_in_signed_long (num
))
2517 t
.bitfield
.imm32
= 1;
2518 t
.bitfield
.imm32s
= 1;
2520 else if (fits_in_unsigned_long (num
))
2521 t
.bitfield
.imm32
= 1;
2527 offset_in_range (offsetT val
, int size
)
2533 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2534 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2535 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2537 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2542 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2544 char buf1
[40], buf2
[40];
2546 sprint_value (buf1
, val
);
2547 sprint_value (buf2
, val
& mask
);
2548 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2563 a. PREFIX_EXIST if attempting to add a prefix where one from the
2564 same class already exists.
2565 b. PREFIX_LOCK if lock prefix is added.
2566 c. PREFIX_REP if rep/repne prefix is added.
2567 d. PREFIX_DS if ds prefix is added.
2568 e. PREFIX_OTHER if other prefix is added.
2571 static enum PREFIX_GROUP
2572 add_prefix (unsigned int prefix
)
2574 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2577 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2578 && flag_code
== CODE_64BIT
)
2580 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2581 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2582 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2583 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2594 case DS_PREFIX_OPCODE
:
2597 case CS_PREFIX_OPCODE
:
2598 case ES_PREFIX_OPCODE
:
2599 case FS_PREFIX_OPCODE
:
2600 case GS_PREFIX_OPCODE
:
2601 case SS_PREFIX_OPCODE
:
2605 case REPNE_PREFIX_OPCODE
:
2606 case REPE_PREFIX_OPCODE
:
2611 case LOCK_PREFIX_OPCODE
:
2620 case ADDR_PREFIX_OPCODE
:
2624 case DATA_PREFIX_OPCODE
:
2628 if (i
.prefix
[q
] != 0)
2636 i
.prefix
[q
] |= prefix
;
2639 as_bad (_("same type of prefix used twice"));
2645 update_code_flag (int value
, int check
)
2647 PRINTF_LIKE ((*as_error
));
2649 flag_code
= (enum flag_code
) value
;
2650 if (flag_code
== CODE_64BIT
)
2652 cpu_arch_flags
.bitfield
.cpu64
= 1;
2653 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2657 cpu_arch_flags
.bitfield
.cpu64
= 0;
2658 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2660 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2663 as_error
= as_fatal
;
2666 (*as_error
) (_("64bit mode not supported on `%s'."),
2667 cpu_arch_name
? cpu_arch_name
: default_arch
);
2669 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2672 as_error
= as_fatal
;
2675 (*as_error
) (_("32bit mode not supported on `%s'."),
2676 cpu_arch_name
? cpu_arch_name
: default_arch
);
2678 stackop_size
= '\0';
2682 set_code_flag (int value
)
2684 update_code_flag (value
, 0);
2688 set_16bit_gcc_code_flag (int new_code_flag
)
2690 flag_code
= (enum flag_code
) new_code_flag
;
2691 if (flag_code
!= CODE_16BIT
)
2693 cpu_arch_flags
.bitfield
.cpu64
= 0;
2694 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2695 stackop_size
= LONG_MNEM_SUFFIX
;
2699 set_intel_syntax (int syntax_flag
)
2701 /* Find out if register prefixing is specified. */
2702 int ask_naked_reg
= 0;
2705 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2708 int e
= get_symbol_name (&string
);
2710 if (strcmp (string
, "prefix") == 0)
2712 else if (strcmp (string
, "noprefix") == 0)
2715 as_bad (_("bad argument to syntax directive."));
2716 (void) restore_line_pointer (e
);
2718 demand_empty_rest_of_line ();
2720 intel_syntax
= syntax_flag
;
2722 if (ask_naked_reg
== 0)
2723 allow_naked_reg
= (intel_syntax
2724 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2726 allow_naked_reg
= (ask_naked_reg
< 0);
2728 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2730 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2731 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2732 register_prefix
= allow_naked_reg
? "" : "%";
2736 set_intel_mnemonic (int mnemonic_flag
)
2738 intel_mnemonic
= mnemonic_flag
;
2742 set_allow_index_reg (int flag
)
2744 allow_index_reg
= flag
;
2748 set_check (int what
)
2750 enum check_kind
*kind
;
2755 kind
= &operand_check
;
2766 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2769 int e
= get_symbol_name (&string
);
2771 if (strcmp (string
, "none") == 0)
2773 else if (strcmp (string
, "warning") == 0)
2774 *kind
= check_warning
;
2775 else if (strcmp (string
, "error") == 0)
2776 *kind
= check_error
;
2778 as_bad (_("bad argument to %s_check directive."), str
);
2779 (void) restore_line_pointer (e
);
2782 as_bad (_("missing argument for %s_check directive"), str
);
2784 demand_empty_rest_of_line ();
2788 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2789 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2791 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2792 static const char *arch
;
2794 /* Intel LIOM is only supported on ELF. */
2800 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2801 use default_arch. */
2802 arch
= cpu_arch_name
;
2804 arch
= default_arch
;
2807 /* If we are targeting Intel MCU, we must enable it. */
2808 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2809 || new_flag
.bitfield
.cpuiamcu
)
2812 /* If we are targeting Intel L1OM, we must enable it. */
2813 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2814 || new_flag
.bitfield
.cpul1om
)
2817 /* If we are targeting Intel K1OM, we must enable it. */
2818 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2819 || new_flag
.bitfield
.cpuk1om
)
2822 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2827 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2831 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2834 int e
= get_symbol_name (&string
);
2836 i386_cpu_flags flags
;
2838 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2840 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2842 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2846 cpu_arch_name
= cpu_arch
[j
].name
;
2847 cpu_sub_arch_name
= NULL
;
2848 cpu_arch_flags
= cpu_arch
[j
].flags
;
2849 if (flag_code
== CODE_64BIT
)
2851 cpu_arch_flags
.bitfield
.cpu64
= 1;
2852 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2856 cpu_arch_flags
.bitfield
.cpu64
= 0;
2857 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2859 cpu_arch_isa
= cpu_arch
[j
].type
;
2860 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2861 if (!cpu_arch_tune_set
)
2863 cpu_arch_tune
= cpu_arch_isa
;
2864 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2869 flags
= cpu_flags_or (cpu_arch_flags
,
2872 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2874 if (cpu_sub_arch_name
)
2876 char *name
= cpu_sub_arch_name
;
2877 cpu_sub_arch_name
= concat (name
,
2879 (const char *) NULL
);
2883 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2884 cpu_arch_flags
= flags
;
2885 cpu_arch_isa_flags
= flags
;
2889 = cpu_flags_or (cpu_arch_isa_flags
,
2891 (void) restore_line_pointer (e
);
2892 demand_empty_rest_of_line ();
2897 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2899 /* Disable an ISA extension. */
2900 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2901 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2903 flags
= cpu_flags_and_not (cpu_arch_flags
,
2904 cpu_noarch
[j
].flags
);
2905 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2907 if (cpu_sub_arch_name
)
2909 char *name
= cpu_sub_arch_name
;
2910 cpu_sub_arch_name
= concat (name
, string
,
2911 (const char *) NULL
);
2915 cpu_sub_arch_name
= xstrdup (string
);
2916 cpu_arch_flags
= flags
;
2917 cpu_arch_isa_flags
= flags
;
2919 (void) restore_line_pointer (e
);
2920 demand_empty_rest_of_line ();
2924 j
= ARRAY_SIZE (cpu_arch
);
2927 if (j
>= ARRAY_SIZE (cpu_arch
))
2928 as_bad (_("no such architecture: `%s'"), string
);
2930 *input_line_pointer
= e
;
2933 as_bad (_("missing cpu architecture"));
2935 no_cond_jump_promotion
= 0;
2936 if (*input_line_pointer
== ','
2937 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2942 ++input_line_pointer
;
2943 e
= get_symbol_name (&string
);
2945 if (strcmp (string
, "nojumps") == 0)
2946 no_cond_jump_promotion
= 1;
2947 else if (strcmp (string
, "jumps") == 0)
2950 as_bad (_("no such architecture modifier: `%s'"), string
);
2952 (void) restore_line_pointer (e
);
2955 demand_empty_rest_of_line ();
2958 enum bfd_architecture
2961 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2963 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2964 || flag_code
!= CODE_64BIT
)
2965 as_fatal (_("Intel L1OM is 64bit ELF only"));
2966 return bfd_arch_l1om
;
2968 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2970 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2971 || flag_code
!= CODE_64BIT
)
2972 as_fatal (_("Intel K1OM is 64bit ELF only"));
2973 return bfd_arch_k1om
;
2975 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2977 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2978 || flag_code
== CODE_64BIT
)
2979 as_fatal (_("Intel MCU is 32bit ELF only"));
2980 return bfd_arch_iamcu
;
2983 return bfd_arch_i386
;
2989 if (!strncmp (default_arch
, "x86_64", 6))
2991 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2993 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2994 || default_arch
[6] != '\0')
2995 as_fatal (_("Intel L1OM is 64bit ELF only"));
2996 return bfd_mach_l1om
;
2998 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3000 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3001 || default_arch
[6] != '\0')
3002 as_fatal (_("Intel K1OM is 64bit ELF only"));
3003 return bfd_mach_k1om
;
3005 else if (default_arch
[6] == '\0')
3006 return bfd_mach_x86_64
;
3008 return bfd_mach_x64_32
;
3010 else if (!strcmp (default_arch
, "i386")
3011 || !strcmp (default_arch
, "iamcu"))
3013 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3015 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3016 as_fatal (_("Intel MCU is 32bit ELF only"));
3017 return bfd_mach_i386_iamcu
;
3020 return bfd_mach_i386_i386
;
3023 as_fatal (_("unknown architecture"));
3029 /* Support pseudo prefixes like {disp32}. */
3030 lex_type
['{'] = LEX_BEGIN_NAME
;
3032 /* Initialize op_hash hash table. */
3033 op_hash
= str_htab_create ();
3036 const insn_template
*optab
;
3037 templates
*core_optab
;
3039 /* Setup for loop. */
3041 core_optab
= XNEW (templates
);
3042 core_optab
->start
= optab
;
3047 if (optab
->name
== NULL
3048 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3050 /* different name --> ship out current template list;
3051 add to hash table; & begin anew. */
3052 core_optab
->end
= optab
;
3053 if (str_hash_insert (op_hash
, (optab
- 1)->name
, core_optab
, 0))
3054 as_fatal (_("duplicate %s"), (optab
- 1)->name
);
3056 if (optab
->name
== NULL
)
3058 core_optab
= XNEW (templates
);
3059 core_optab
->start
= optab
;
3064 /* Initialize reg_hash hash table. */
3065 reg_hash
= str_htab_create ();
3067 const reg_entry
*regtab
;
3068 unsigned int regtab_size
= i386_regtab_size
;
3070 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3071 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3072 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3075 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3080 for (c
= 0; c
< 256; c
++)
3085 mnemonic_chars
[c
] = c
;
3086 register_chars
[c
] = c
;
3087 operand_chars
[c
] = c
;
3089 else if (ISLOWER (c
))
3091 mnemonic_chars
[c
] = c
;
3092 register_chars
[c
] = c
;
3093 operand_chars
[c
] = c
;
3095 else if (ISUPPER (c
))
3097 mnemonic_chars
[c
] = TOLOWER (c
);
3098 register_chars
[c
] = mnemonic_chars
[c
];
3099 operand_chars
[c
] = c
;
3101 else if (c
== '{' || c
== '}')
3103 mnemonic_chars
[c
] = c
;
3104 operand_chars
[c
] = c
;
3106 #ifdef SVR4_COMMENT_CHARS
3107 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3108 operand_chars
[c
] = c
;
3111 if (ISALPHA (c
) || ISDIGIT (c
))
3112 identifier_chars
[c
] = c
;
3115 identifier_chars
[c
] = c
;
3116 operand_chars
[c
] = c
;
3121 identifier_chars
['@'] = '@';
3124 identifier_chars
['?'] = '?';
3125 operand_chars
['?'] = '?';
3127 digit_chars
['-'] = '-';
3128 mnemonic_chars
['_'] = '_';
3129 mnemonic_chars
['-'] = '-';
3130 mnemonic_chars
['.'] = '.';
3131 identifier_chars
['_'] = '_';
3132 identifier_chars
['.'] = '.';
3134 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3135 operand_chars
[(unsigned char) *p
] = *p
;
3138 if (flag_code
== CODE_64BIT
)
3140 #if defined (OBJ_COFF) && defined (TE_PE)
3141 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3144 x86_dwarf2_return_column
= 16;
3146 x86_cie_data_alignment
= -8;
3150 x86_dwarf2_return_column
= 8;
3151 x86_cie_data_alignment
= -4;
3154 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3155 can be turned into BRANCH_PREFIX frag. */
3156 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3161 i386_print_statistics (FILE *file
)
3163 htab_print_statistics (file
, "i386 opcode", op_hash
);
3164 htab_print_statistics (file
, "i386 register", reg_hash
);
3169 /* Debugging routines for md_assemble. */
3170 static void pte (insn_template
*);
3171 static void pt (i386_operand_type
);
3172 static void pe (expressionS
*);
3173 static void ps (symbolS
*);
3176 pi (const char *line
, i386_insn
*x
)
3180 fprintf (stdout
, "%s: template ", line
);
3182 fprintf (stdout
, " address: base %s index %s scale %x\n",
3183 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3184 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3185 x
->log2_scale_factor
);
3186 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3187 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3188 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3189 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3190 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3191 (x
->rex
& REX_W
) != 0,
3192 (x
->rex
& REX_R
) != 0,
3193 (x
->rex
& REX_X
) != 0,
3194 (x
->rex
& REX_B
) != 0);
3195 for (j
= 0; j
< x
->operands
; j
++)
3197 fprintf (stdout
, " #%d: ", j
+ 1);
3199 fprintf (stdout
, "\n");
3200 if (x
->types
[j
].bitfield
.class == Reg
3201 || x
->types
[j
].bitfield
.class == RegMMX
3202 || x
->types
[j
].bitfield
.class == RegSIMD
3203 || x
->types
[j
].bitfield
.class == RegMask
3204 || x
->types
[j
].bitfield
.class == SReg
3205 || x
->types
[j
].bitfield
.class == RegCR
3206 || x
->types
[j
].bitfield
.class == RegDR
3207 || x
->types
[j
].bitfield
.class == RegTR
3208 || x
->types
[j
].bitfield
.class == RegBND
)
3209 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3210 if (operand_type_check (x
->types
[j
], imm
))
3212 if (operand_type_check (x
->types
[j
], disp
))
3213 pe (x
->op
[j
].disps
);
3218 pte (insn_template
*t
)
3221 fprintf (stdout
, " %d operands ", t
->operands
);
3222 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3223 if (t
->extension_opcode
!= None
)
3224 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3225 if (t
->opcode_modifier
.d
)
3226 fprintf (stdout
, "D");
3227 if (t
->opcode_modifier
.w
)
3228 fprintf (stdout
, "W");
3229 fprintf (stdout
, "\n");
3230 for (j
= 0; j
< t
->operands
; j
++)
3232 fprintf (stdout
, " #%d type ", j
+ 1);
3233 pt (t
->operand_types
[j
]);
3234 fprintf (stdout
, "\n");
3241 fprintf (stdout
, " operation %d\n", e
->X_op
);
3242 fprintf (stdout
, " add_number %ld (%lx)\n",
3243 (long) e
->X_add_number
, (long) e
->X_add_number
);
3244 if (e
->X_add_symbol
)
3246 fprintf (stdout
, " add_symbol ");
3247 ps (e
->X_add_symbol
);
3248 fprintf (stdout
, "\n");
3252 fprintf (stdout
, " op_symbol ");
3253 ps (e
->X_op_symbol
);
3254 fprintf (stdout
, "\n");
3261 fprintf (stdout
, "%s type %s%s",
3263 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3264 segment_name (S_GET_SEGMENT (s
)));
3267 static struct type_name
3269 i386_operand_type mask
;
3272 const type_names
[] =
3274 { OPERAND_TYPE_REG8
, "r8" },
3275 { OPERAND_TYPE_REG16
, "r16" },
3276 { OPERAND_TYPE_REG32
, "r32" },
3277 { OPERAND_TYPE_REG64
, "r64" },
3278 { OPERAND_TYPE_ACC8
, "acc8" },
3279 { OPERAND_TYPE_ACC16
, "acc16" },
3280 { OPERAND_TYPE_ACC32
, "acc32" },
3281 { OPERAND_TYPE_ACC64
, "acc64" },
3282 { OPERAND_TYPE_IMM8
, "i8" },
3283 { OPERAND_TYPE_IMM8
, "i8s" },
3284 { OPERAND_TYPE_IMM16
, "i16" },
3285 { OPERAND_TYPE_IMM32
, "i32" },
3286 { OPERAND_TYPE_IMM32S
, "i32s" },
3287 { OPERAND_TYPE_IMM64
, "i64" },
3288 { OPERAND_TYPE_IMM1
, "i1" },
3289 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3290 { OPERAND_TYPE_DISP8
, "d8" },
3291 { OPERAND_TYPE_DISP16
, "d16" },
3292 { OPERAND_TYPE_DISP32
, "d32" },
3293 { OPERAND_TYPE_DISP32S
, "d32s" },
3294 { OPERAND_TYPE_DISP64
, "d64" },
3295 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3296 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3297 { OPERAND_TYPE_CONTROL
, "control reg" },
3298 { OPERAND_TYPE_TEST
, "test reg" },
3299 { OPERAND_TYPE_DEBUG
, "debug reg" },
3300 { OPERAND_TYPE_FLOATREG
, "FReg" },
3301 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3302 { OPERAND_TYPE_SREG
, "SReg" },
3303 { OPERAND_TYPE_REGMMX
, "rMMX" },
3304 { OPERAND_TYPE_REGXMM
, "rXMM" },
3305 { OPERAND_TYPE_REGYMM
, "rYMM" },
3306 { OPERAND_TYPE_REGZMM
, "rZMM" },
3307 { OPERAND_TYPE_REGTMM
, "rTMM" },
3308 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3312 pt (i386_operand_type t
)
3315 i386_operand_type a
;
3317 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3319 a
= operand_type_and (t
, type_names
[j
].mask
);
3320 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3321 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3326 #endif /* DEBUG386 */
3328 static bfd_reloc_code_real_type
3329 reloc (unsigned int size
,
3332 bfd_reloc_code_real_type other
)
3334 if (other
!= NO_RELOC
)
3336 reloc_howto_type
*rel
;
3341 case BFD_RELOC_X86_64_GOT32
:
3342 return BFD_RELOC_X86_64_GOT64
;
3344 case BFD_RELOC_X86_64_GOTPLT64
:
3345 return BFD_RELOC_X86_64_GOTPLT64
;
3347 case BFD_RELOC_X86_64_PLTOFF64
:
3348 return BFD_RELOC_X86_64_PLTOFF64
;
3350 case BFD_RELOC_X86_64_GOTPC32
:
3351 other
= BFD_RELOC_X86_64_GOTPC64
;
3353 case BFD_RELOC_X86_64_GOTPCREL
:
3354 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3356 case BFD_RELOC_X86_64_TPOFF32
:
3357 other
= BFD_RELOC_X86_64_TPOFF64
;
3359 case BFD_RELOC_X86_64_DTPOFF32
:
3360 other
= BFD_RELOC_X86_64_DTPOFF64
;
3366 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3367 if (other
== BFD_RELOC_SIZE32
)
3370 other
= BFD_RELOC_SIZE64
;
3373 as_bad (_("there are no pc-relative size relocations"));
3379 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3380 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3383 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3385 as_bad (_("unknown relocation (%u)"), other
);
3386 else if (size
!= bfd_get_reloc_size (rel
))
3387 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3388 bfd_get_reloc_size (rel
),
3390 else if (pcrel
&& !rel
->pc_relative
)
3391 as_bad (_("non-pc-relative relocation for pc-relative field"));
3392 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3394 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3396 as_bad (_("relocated field and relocation type differ in signedness"));
3405 as_bad (_("there are no unsigned pc-relative relocations"));
3408 case 1: return BFD_RELOC_8_PCREL
;
3409 case 2: return BFD_RELOC_16_PCREL
;
3410 case 4: return BFD_RELOC_32_PCREL
;
3411 case 8: return BFD_RELOC_64_PCREL
;
3413 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3420 case 4: return BFD_RELOC_X86_64_32S
;
3425 case 1: return BFD_RELOC_8
;
3426 case 2: return BFD_RELOC_16
;
3427 case 4: return BFD_RELOC_32
;
3428 case 8: return BFD_RELOC_64
;
3430 as_bad (_("cannot do %s %u byte relocation"),
3431 sign
> 0 ? "signed" : "unsigned", size
);
3437 /* Here we decide which fixups can be adjusted to make them relative to
3438 the beginning of the section instead of the symbol. Basically we need
3439 to make sure that the dynamic relocations are done correctly, so in
3440 some cases we force the original symbol to be used. */
3443 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3449 /* Don't adjust pc-relative references to merge sections in 64-bit
3451 if (use_rela_relocations
3452 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3456 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3457 and changed later by validate_fix. */
3458 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3459 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3462 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3463 for size relocations. */
3464 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3465 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3466 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3467 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3468 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3470 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3471 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3472 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3473 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3474 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3475 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3476 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3477 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3478 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3483 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3484 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3485 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3487 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3488 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3489 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3490 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3491 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3492 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3493 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3494 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3501 intel_float_operand (const char *mnemonic
)
3503 /* Note that the value returned is meaningful only for opcodes with (memory)
3504 operands, hence the code here is free to improperly handle opcodes that
3505 have no operands (for better performance and smaller code). */
3507 if (mnemonic
[0] != 'f')
3508 return 0; /* non-math */
3510 switch (mnemonic
[1])
3512 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3513 the fs segment override prefix not currently handled because no
3514 call path can make opcodes without operands get here */
3516 return 2 /* integer op */;
3518 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3519 return 3; /* fldcw/fldenv */
3522 if (mnemonic
[2] != 'o' /* fnop */)
3523 return 3; /* non-waiting control op */
3526 if (mnemonic
[2] == 's')
3527 return 3; /* frstor/frstpm */
3530 if (mnemonic
[2] == 'a')
3531 return 3; /* fsave */
3532 if (mnemonic
[2] == 't')
3534 switch (mnemonic
[3])
3536 case 'c': /* fstcw */
3537 case 'd': /* fstdw */
3538 case 'e': /* fstenv */
3539 case 's': /* fsts[gw] */
3545 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3546 return 0; /* fxsave/fxrstor are not really math ops */
3553 /* Build the VEX prefix. */
3556 build_vex_prefix (const insn_template
*t
)
3558 unsigned int register_specifier
;
3559 unsigned int implied_prefix
;
3560 unsigned int vector_length
;
3563 /* Check register specifier. */
3564 if (i
.vex
.register_specifier
)
3566 register_specifier
=
3567 ~register_number (i
.vex
.register_specifier
) & 0xf;
3568 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3571 register_specifier
= 0xf;
3573 /* Use 2-byte VEX prefix by swapping destination and source operand
3574 if there are more than 1 register operand. */
3575 if (i
.reg_operands
> 1
3576 && i
.vec_encoding
!= vex_encoding_vex3
3577 && i
.dir_encoding
== dir_encoding_default
3578 && i
.operands
== i
.reg_operands
3579 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3580 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3581 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3584 unsigned int xchg
= i
.operands
- 1;
3585 union i386_op temp_op
;
3586 i386_operand_type temp_type
;
3588 temp_type
= i
.types
[xchg
];
3589 i
.types
[xchg
] = i
.types
[0];
3590 i
.types
[0] = temp_type
;
3591 temp_op
= i
.op
[xchg
];
3592 i
.op
[xchg
] = i
.op
[0];
3595 gas_assert (i
.rm
.mode
== 3);
3599 i
.rm
.regmem
= i
.rm
.reg
;
3602 if (i
.tm
.opcode_modifier
.d
)
3603 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3604 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3605 else /* Use the next insn. */
3609 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3610 are no memory operands and at least 3 register ones. */
3611 if (i
.reg_operands
>= 3
3612 && i
.vec_encoding
!= vex_encoding_vex3
3613 && i
.reg_operands
== i
.operands
- i
.imm_operands
3614 && i
.tm
.opcode_modifier
.vex
3615 && i
.tm
.opcode_modifier
.commutative
3616 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3618 && i
.vex
.register_specifier
3619 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3621 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3622 union i386_op temp_op
;
3623 i386_operand_type temp_type
;
3625 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3626 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3627 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3628 &i
.types
[i
.operands
- 3]));
3629 gas_assert (i
.rm
.mode
== 3);
3631 temp_type
= i
.types
[xchg
];
3632 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3633 i
.types
[xchg
+ 1] = temp_type
;
3634 temp_op
= i
.op
[xchg
];
3635 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3636 i
.op
[xchg
+ 1] = temp_op
;
3639 xchg
= i
.rm
.regmem
| 8;
3640 i
.rm
.regmem
= ~register_specifier
& 0xf;
3641 gas_assert (!(i
.rm
.regmem
& 8));
3642 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3643 register_specifier
= ~xchg
& 0xf;
3646 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3647 vector_length
= avxscalar
;
3648 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3654 /* Determine vector length from the last multi-length vector
3657 for (op
= t
->operands
; op
--;)
3658 if (t
->operand_types
[op
].bitfield
.xmmword
3659 && t
->operand_types
[op
].bitfield
.ymmword
3660 && i
.types
[op
].bitfield
.ymmword
)
3667 switch ((i
.tm
.base_opcode
>> (i
.tm
.opcode_length
<< 3)) & 0xff)
3672 case DATA_PREFIX_OPCODE
:
3675 case REPE_PREFIX_OPCODE
:
3678 case REPNE_PREFIX_OPCODE
:
3685 /* Check the REX.W bit and VEXW. */
3686 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3687 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3688 else if (i
.tm
.opcode_modifier
.vexw
)
3689 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3691 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3693 /* Use 2-byte VEX prefix if possible. */
3695 && i
.vec_encoding
!= vex_encoding_vex3
3696 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3697 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3699 /* 2-byte VEX prefix. */
3703 i
.vex
.bytes
[0] = 0xc5;
3705 /* Check the REX.R bit. */
3706 r
= (i
.rex
& REX_R
) ? 0 : 1;
3707 i
.vex
.bytes
[1] = (r
<< 7
3708 | register_specifier
<< 3
3709 | vector_length
<< 2
3714 /* 3-byte VEX prefix. */
3719 switch (i
.tm
.opcode_modifier
.vexopcode
)
3723 i
.vex
.bytes
[0] = 0xc4;
3727 i
.vex
.bytes
[0] = 0xc4;
3731 i
.vex
.bytes
[0] = 0xc4;
3735 i
.vex
.bytes
[0] = 0x8f;
3739 i
.vex
.bytes
[0] = 0x8f;
3743 i
.vex
.bytes
[0] = 0x8f;
3749 /* The high 3 bits of the second VEX byte are 1's compliment
3750 of RXB bits from REX. */
3751 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3753 i
.vex
.bytes
[2] = (w
<< 7
3754 | register_specifier
<< 3
3755 | vector_length
<< 2
3760 static INLINE bfd_boolean
3761 is_evex_encoding (const insn_template
*t
)
3763 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3764 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3765 || t
->opcode_modifier
.sae
;
3768 static INLINE bfd_boolean
3769 is_any_vex_encoding (const insn_template
*t
)
3771 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3772 || is_evex_encoding (t
);
3775 /* Build the EVEX prefix. */
3778 build_evex_prefix (void)
3780 unsigned int register_specifier
;
3781 unsigned int implied_prefix
;
3783 rex_byte vrex_used
= 0;
3785 /* Check register specifier. */
3786 if (i
.vex
.register_specifier
)
3788 gas_assert ((i
.vrex
& REX_X
) == 0);
3790 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3791 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3792 register_specifier
+= 8;
3793 /* The upper 16 registers are encoded in the fourth byte of the
3795 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3796 i
.vex
.bytes
[3] = 0x8;
3797 register_specifier
= ~register_specifier
& 0xf;
3801 register_specifier
= 0xf;
3803 /* Encode upper 16 vector index register in the fourth byte of
3805 if (!(i
.vrex
& REX_X
))
3806 i
.vex
.bytes
[3] = 0x8;
3811 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3816 case DATA_PREFIX_OPCODE
:
3819 case REPE_PREFIX_OPCODE
:
3822 case REPNE_PREFIX_OPCODE
:
3829 /* 4 byte EVEX prefix. */
3831 i
.vex
.bytes
[0] = 0x62;
3834 switch (i
.tm
.opcode_modifier
.vexopcode
)
3850 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3852 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3854 /* The fifth bit of the second EVEX byte is 1's compliment of the
3855 REX_R bit in VREX. */
3856 if (!(i
.vrex
& REX_R
))
3857 i
.vex
.bytes
[1] |= 0x10;
3861 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3863 /* When all operands are registers, the REX_X bit in REX is not
3864 used. We reuse it to encode the upper 16 registers, which is
3865 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3866 as 1's compliment. */
3867 if ((i
.vrex
& REX_B
))
3870 i
.vex
.bytes
[1] &= ~0x40;
3874 /* EVEX instructions shouldn't need the REX prefix. */
3875 i
.vrex
&= ~vrex_used
;
3876 gas_assert (i
.vrex
== 0);
3878 /* Check the REX.W bit and VEXW. */
3879 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3880 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3881 else if (i
.tm
.opcode_modifier
.vexw
)
3882 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3884 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3886 /* Encode the U bit. */
3887 implied_prefix
|= 0x4;
3889 /* The third byte of the EVEX prefix. */
3890 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3892 /* The fourth byte of the EVEX prefix. */
3893 /* The zeroing-masking bit. */
3894 if (i
.mask
&& i
.mask
->zeroing
)
3895 i
.vex
.bytes
[3] |= 0x80;
3897 /* Don't always set the broadcast bit if there is no RC. */
3900 /* Encode the vector length. */
3901 unsigned int vec_length
;
3903 if (!i
.tm
.opcode_modifier
.evex
3904 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3908 /* Determine vector length from the last multi-length vector
3910 for (op
= i
.operands
; op
--;)
3911 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3912 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3913 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3915 if (i
.types
[op
].bitfield
.zmmword
)
3917 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3920 else if (i
.types
[op
].bitfield
.ymmword
)
3922 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3925 else if (i
.types
[op
].bitfield
.xmmword
)
3927 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3930 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3932 switch (i
.broadcast
->bytes
)
3935 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3938 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3941 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3950 if (op
>= MAX_OPERANDS
)
3954 switch (i
.tm
.opcode_modifier
.evex
)
3956 case EVEXLIG
: /* LL' is ignored */
3957 vec_length
= evexlig
<< 5;
3960 vec_length
= 0 << 5;
3963 vec_length
= 1 << 5;
3966 vec_length
= 2 << 5;
3972 i
.vex
.bytes
[3] |= vec_length
;
3973 /* Encode the broadcast bit. */
3975 i
.vex
.bytes
[3] |= 0x10;
3979 if (i
.rounding
->type
!= saeonly
)
3980 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3982 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3985 if (i
.mask
&& i
.mask
->mask
)
3986 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3990 process_immext (void)
3994 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3995 which is coded in the same place as an 8-bit immediate field
3996 would be. Here we fake an 8-bit immediate operand from the
3997 opcode suffix stored in tm.extension_opcode.
3999 AVX instructions also use this encoding, for some of
4000 3 argument instructions. */
4002 gas_assert (i
.imm_operands
<= 1
4004 || (is_any_vex_encoding (&i
.tm
)
4005 && i
.operands
<= 4)));
4007 exp
= &im_expressions
[i
.imm_operands
++];
4008 i
.op
[i
.operands
].imms
= exp
;
4009 i
.types
[i
.operands
] = imm8
;
4011 exp
->X_op
= O_constant
;
4012 exp
->X_add_number
= i
.tm
.extension_opcode
;
4013 i
.tm
.extension_opcode
= None
;
4020 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4025 as_bad (_("invalid instruction `%s' after `%s'"),
4026 i
.tm
.name
, i
.hle_prefix
);
4029 if (i
.prefix
[LOCK_PREFIX
])
4031 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4035 case HLEPrefixRelease
:
4036 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4038 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4042 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4044 as_bad (_("memory destination needed for instruction `%s'"
4045 " after `xrelease'"), i
.tm
.name
);
4052 /* Try the shortest encoding by shortening operand size. */
4055 optimize_encoding (void)
4059 if (optimize_for_space
4060 && !is_any_vex_encoding (&i
.tm
)
4061 && i
.reg_operands
== 1
4062 && i
.imm_operands
== 1
4063 && !i
.types
[1].bitfield
.byte
4064 && i
.op
[0].imms
->X_op
== O_constant
4065 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4066 && (i
.tm
.base_opcode
== 0xa8
4067 || (i
.tm
.base_opcode
== 0xf6
4068 && i
.tm
.extension_opcode
== 0x0)))
4071 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4073 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4074 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4076 i
.types
[1].bitfield
.byte
= 1;
4077 /* Ignore the suffix. */
4079 /* Convert to byte registers. */
4080 if (i
.types
[1].bitfield
.word
)
4082 else if (i
.types
[1].bitfield
.dword
)
4086 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4091 else if (flag_code
== CODE_64BIT
4092 && !is_any_vex_encoding (&i
.tm
)
4093 && ((i
.types
[1].bitfield
.qword
4094 && i
.reg_operands
== 1
4095 && i
.imm_operands
== 1
4096 && i
.op
[0].imms
->X_op
== O_constant
4097 && ((i
.tm
.base_opcode
== 0xb8
4098 && i
.tm
.extension_opcode
== None
4099 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4100 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4101 && ((i
.tm
.base_opcode
== 0x24
4102 || i
.tm
.base_opcode
== 0xa8)
4103 || (i
.tm
.base_opcode
== 0x80
4104 && i
.tm
.extension_opcode
== 0x4)
4105 || ((i
.tm
.base_opcode
== 0xf6
4106 || (i
.tm
.base_opcode
| 1) == 0xc7)
4107 && i
.tm
.extension_opcode
== 0x0)))
4108 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4109 && i
.tm
.base_opcode
== 0x83
4110 && i
.tm
.extension_opcode
== 0x4)))
4111 || (i
.types
[0].bitfield
.qword
4112 && ((i
.reg_operands
== 2
4113 && i
.op
[0].regs
== i
.op
[1].regs
4114 && (i
.tm
.base_opcode
== 0x30
4115 || i
.tm
.base_opcode
== 0x28))
4116 || (i
.reg_operands
== 1
4118 && i
.tm
.base_opcode
== 0x30)))))
4121 andq $imm31, %r64 -> andl $imm31, %r32
4122 andq $imm7, %r64 -> andl $imm7, %r32
4123 testq $imm31, %r64 -> testl $imm31, %r32
4124 xorq %r64, %r64 -> xorl %r32, %r32
4125 subq %r64, %r64 -> subl %r32, %r32
4126 movq $imm31, %r64 -> movl $imm31, %r32
4127 movq $imm32, %r64 -> movl $imm32, %r32
4129 i
.tm
.opcode_modifier
.norex64
= 1;
4130 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4133 movq $imm31, %r64 -> movl $imm31, %r32
4134 movq $imm32, %r64 -> movl $imm32, %r32
4136 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4137 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4138 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4139 i
.types
[0].bitfield
.imm32
= 1;
4140 i
.types
[0].bitfield
.imm32s
= 0;
4141 i
.types
[0].bitfield
.imm64
= 0;
4142 i
.types
[1].bitfield
.dword
= 1;
4143 i
.types
[1].bitfield
.qword
= 0;
4144 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4147 movq $imm31, %r64 -> movl $imm31, %r32
4149 i
.tm
.base_opcode
= 0xb8;
4150 i
.tm
.extension_opcode
= None
;
4151 i
.tm
.opcode_modifier
.w
= 0;
4152 i
.tm
.opcode_modifier
.modrm
= 0;
4156 else if (optimize
> 1
4157 && !optimize_for_space
4158 && !is_any_vex_encoding (&i
.tm
)
4159 && i
.reg_operands
== 2
4160 && i
.op
[0].regs
== i
.op
[1].regs
4161 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4162 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4163 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4166 andb %rN, %rN -> testb %rN, %rN
4167 andw %rN, %rN -> testw %rN, %rN
4168 andq %rN, %rN -> testq %rN, %rN
4169 orb %rN, %rN -> testb %rN, %rN
4170 orw %rN, %rN -> testw %rN, %rN
4171 orq %rN, %rN -> testq %rN, %rN
4173 and outside of 64-bit mode
4175 andl %rN, %rN -> testl %rN, %rN
4176 orl %rN, %rN -> testl %rN, %rN
4178 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4180 else if (i
.reg_operands
== 3
4181 && i
.op
[0].regs
== i
.op
[1].regs
4182 && !i
.types
[2].bitfield
.xmmword
4183 && (i
.tm
.opcode_modifier
.vex
4184 || ((!i
.mask
|| i
.mask
->zeroing
)
4186 && is_evex_encoding (&i
.tm
)
4187 && (i
.vec_encoding
!= vex_encoding_evex
4188 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4189 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4190 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4191 && i
.types
[2].bitfield
.ymmword
))))
4192 && ((i
.tm
.base_opcode
== 0x55
4193 || i
.tm
.base_opcode
== 0x6655
4194 || i
.tm
.base_opcode
== 0x66df
4195 || i
.tm
.base_opcode
== 0x57
4196 || i
.tm
.base_opcode
== 0x6657
4197 || i
.tm
.base_opcode
== 0x66ef
4198 || i
.tm
.base_opcode
== 0x66f8
4199 || i
.tm
.base_opcode
== 0x66f9
4200 || i
.tm
.base_opcode
== 0x66fa
4201 || i
.tm
.base_opcode
== 0x66fb
4202 || i
.tm
.base_opcode
== 0x42
4203 || i
.tm
.base_opcode
== 0x6642
4204 || i
.tm
.base_opcode
== 0x47
4205 || i
.tm
.base_opcode
== 0x6647)
4206 && i
.tm
.extension_opcode
== None
))
4209 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4211 EVEX VOP %zmmM, %zmmM, %zmmN
4212 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4213 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4214 EVEX VOP %ymmM, %ymmM, %ymmN
4215 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4216 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4217 VEX VOP %ymmM, %ymmM, %ymmN
4218 -> VEX VOP %xmmM, %xmmM, %xmmN
4219 VOP, one of vpandn and vpxor:
4220 VEX VOP %ymmM, %ymmM, %ymmN
4221 -> VEX VOP %xmmM, %xmmM, %xmmN
4222 VOP, one of vpandnd and vpandnq:
4223 EVEX VOP %zmmM, %zmmM, %zmmN
4224 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4225 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4226 EVEX VOP %ymmM, %ymmM, %ymmN
4227 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4228 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4229 VOP, one of vpxord and vpxorq:
4230 EVEX VOP %zmmM, %zmmM, %zmmN
4231 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4232 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4233 EVEX VOP %ymmM, %ymmM, %ymmN
4234 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4235 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4236 VOP, one of kxord and kxorq:
4237 VEX VOP %kM, %kM, %kN
4238 -> VEX kxorw %kM, %kM, %kN
4239 VOP, one of kandnd and kandnq:
4240 VEX VOP %kM, %kM, %kN
4241 -> VEX kandnw %kM, %kM, %kN
4243 if (is_evex_encoding (&i
.tm
))
4245 if (i
.vec_encoding
!= vex_encoding_evex
)
4247 i
.tm
.opcode_modifier
.vex
= VEX128
;
4248 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4249 i
.tm
.opcode_modifier
.evex
= 0;
4251 else if (optimize
> 1)
4252 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4256 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4258 i
.tm
.base_opcode
&= 0xff;
4259 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4262 i
.tm
.opcode_modifier
.vex
= VEX128
;
4264 if (i
.tm
.opcode_modifier
.vex
)
4265 for (j
= 0; j
< 3; j
++)
4267 i
.types
[j
].bitfield
.xmmword
= 1;
4268 i
.types
[j
].bitfield
.ymmword
= 0;
4271 else if (i
.vec_encoding
!= vex_encoding_evex
4272 && !i
.types
[0].bitfield
.zmmword
4273 && !i
.types
[1].bitfield
.zmmword
4276 && is_evex_encoding (&i
.tm
)
4277 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4278 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4279 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4280 || (i
.tm
.base_opcode
& ~4) == 0x66db
4281 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4282 && i
.tm
.extension_opcode
== None
)
4285 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4286 vmovdqu32 and vmovdqu64:
4287 EVEX VOP %xmmM, %xmmN
4288 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4289 EVEX VOP %ymmM, %ymmN
4290 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4292 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4294 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4296 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4298 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4299 VOP, one of vpand, vpandn, vpor, vpxor:
4300 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4301 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4302 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4303 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4304 EVEX VOP{d,q} mem, %xmmM, %xmmN
4305 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4306 EVEX VOP{d,q} mem, %ymmM, %ymmN
4307 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4309 for (j
= 0; j
< i
.operands
; j
++)
4310 if (operand_type_check (i
.types
[j
], disp
)
4311 && i
.op
[j
].disps
->X_op
== O_constant
)
4313 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4314 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4315 bytes, we choose EVEX Disp8 over VEX Disp32. */
4316 int evex_disp8
, vex_disp8
;
4317 unsigned int memshift
= i
.memshift
;
4318 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4320 evex_disp8
= fits_in_disp8 (n
);
4322 vex_disp8
= fits_in_disp8 (n
);
4323 if (evex_disp8
!= vex_disp8
)
4325 i
.memshift
= memshift
;
4329 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4332 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4333 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4334 i
.tm
.opcode_modifier
.vex
4335 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4336 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4337 /* VPAND, VPOR, and VPXOR are commutative. */
4338 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4339 i
.tm
.opcode_modifier
.commutative
= 1;
4340 i
.tm
.opcode_modifier
.evex
= 0;
4341 i
.tm
.opcode_modifier
.masking
= 0;
4342 i
.tm
.opcode_modifier
.broadcast
= 0;
4343 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4346 i
.types
[j
].bitfield
.disp8
4347 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4351 /* Return non-zero for load instruction. */
4357 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4358 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4362 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4363 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4364 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4365 if (i
.tm
.opcode_modifier
.anysize
)
4368 /* pop, popf, popa. */
4369 if (strcmp (i
.tm
.name
, "pop") == 0
4370 || i
.tm
.base_opcode
== 0x9d
4371 || i
.tm
.base_opcode
== 0x61)
4374 /* movs, cmps, lods, scas. */
4375 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4379 if (base_opcode
== 0x6f
4380 || i
.tm
.base_opcode
== 0xd7)
4382 /* NB: For AMD-specific insns with implicit memory operands,
4383 they're intentionally not covered. */
4386 /* No memory operand. */
4387 if (!i
.mem_operands
)
4393 if (i
.tm
.base_opcode
== 0xae
4394 && i
.tm
.opcode_modifier
.vex
4395 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
4396 && i
.tm
.extension_opcode
== 2)
4401 /* test, not, neg, mul, imul, div, idiv. */
4402 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4403 && i
.tm
.extension_opcode
!= 1)
4407 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4410 /* add, or, adc, sbb, and, sub, xor, cmp. */
4411 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4414 /* bt, bts, btr, btc. */
4415 if (i
.tm
.base_opcode
== 0xfba
4416 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4419 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4420 if ((base_opcode
== 0xc1
4421 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4422 && i
.tm
.extension_opcode
!= 6)
4425 /* cmpxchg8b, cmpxchg16b, xrstors. */
4426 if (i
.tm
.base_opcode
== 0xfc7
4427 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4430 /* fxrstor, ldmxcsr, xrstor. */
4431 if (i
.tm
.base_opcode
== 0xfae
4432 && (i
.tm
.extension_opcode
== 1
4433 || i
.tm
.extension_opcode
== 2
4434 || i
.tm
.extension_opcode
== 5))
4437 /* lgdt, lidt, lmsw. */
4438 if (i
.tm
.base_opcode
== 0xf01
4439 && (i
.tm
.extension_opcode
== 2
4440 || i
.tm
.extension_opcode
== 3
4441 || i
.tm
.extension_opcode
== 6))
4445 if (i
.tm
.base_opcode
== 0xfc7
4446 && i
.tm
.extension_opcode
== 6)
4449 /* Check for x87 instructions. */
4450 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4452 /* Skip fst, fstp, fstenv, fstcw. */
4453 if (i
.tm
.base_opcode
== 0xd9
4454 && (i
.tm
.extension_opcode
== 2
4455 || i
.tm
.extension_opcode
== 3
4456 || i
.tm
.extension_opcode
== 6
4457 || i
.tm
.extension_opcode
== 7))
4460 /* Skip fisttp, fist, fistp, fstp. */
4461 if (i
.tm
.base_opcode
== 0xdb
4462 && (i
.tm
.extension_opcode
== 1
4463 || i
.tm
.extension_opcode
== 2
4464 || i
.tm
.extension_opcode
== 3
4465 || i
.tm
.extension_opcode
== 7))
4468 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4469 if (i
.tm
.base_opcode
== 0xdd
4470 && (i
.tm
.extension_opcode
== 1
4471 || i
.tm
.extension_opcode
== 2
4472 || i
.tm
.extension_opcode
== 3
4473 || i
.tm
.extension_opcode
== 6
4474 || i
.tm
.extension_opcode
== 7))
4477 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4478 if (i
.tm
.base_opcode
== 0xdf
4479 && (i
.tm
.extension_opcode
== 1
4480 || i
.tm
.extension_opcode
== 2
4481 || i
.tm
.extension_opcode
== 3
4482 || i
.tm
.extension_opcode
== 6
4483 || i
.tm
.extension_opcode
== 7))
4490 dest
= i
.operands
- 1;
4492 /* Check fake imm8 operand and 3 source operands. */
4493 if ((i
.tm
.opcode_modifier
.immext
4494 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4495 && i
.types
[dest
].bitfield
.imm8
)
4498 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4500 && (base_opcode
== 0x1
4501 || base_opcode
== 0x9
4502 || base_opcode
== 0x11
4503 || base_opcode
== 0x19
4504 || base_opcode
== 0x21
4505 || base_opcode
== 0x29
4506 || base_opcode
== 0x31
4507 || base_opcode
== 0x39
4508 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4509 || base_opcode
== 0xfc1))
4512 /* Check for load instruction. */
4513 return (i
.types
[dest
].bitfield
.class != ClassNone
4514 || i
.types
[dest
].bitfield
.instance
== Accum
);
4517 /* Output lfence, 0xfaee8, after instruction. */
4520 insert_lfence_after (void)
4522 if (lfence_after_load
&& load_insn_p ())
4524 /* There are also two REP string instructions that require
4525 special treatment. Specifically, the compare string (CMPS)
4526 and scan string (SCAS) instructions set EFLAGS in a manner
4527 that depends on the data being compared/scanned. When used
4528 with a REP prefix, the number of iterations may therefore
4529 vary depending on this data. If the data is a program secret
4530 chosen by the adversary using an LVI method,
4531 then this data-dependent behavior may leak some aspect
4533 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4534 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4535 && i
.prefix
[REP_PREFIX
])
4537 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4540 char *p
= frag_more (3);
4547 /* Output lfence, 0xfaee8, before instruction. */
4550 insert_lfence_before (void)
4554 if (is_any_vex_encoding (&i
.tm
))
4557 if (i
.tm
.base_opcode
== 0xff
4558 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4560 /* Insert lfence before indirect branch if needed. */
4562 if (lfence_before_indirect_branch
== lfence_branch_none
)
4565 if (i
.operands
!= 1)
4568 if (i
.reg_operands
== 1)
4570 /* Indirect branch via register. Don't insert lfence with
4571 -mlfence-after-load=yes. */
4572 if (lfence_after_load
4573 || lfence_before_indirect_branch
== lfence_branch_memory
)
4576 else if (i
.mem_operands
== 1
4577 && lfence_before_indirect_branch
!= lfence_branch_register
)
4579 as_warn (_("indirect `%s` with memory operand should be avoided"),
4586 if (last_insn
.kind
!= last_insn_other
4587 && last_insn
.seg
== now_seg
)
4589 as_warn_where (last_insn
.file
, last_insn
.line
,
4590 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4591 last_insn
.name
, i
.tm
.name
);
4602 /* Output or/not/shl and lfence before near ret. */
4603 if (lfence_before_ret
!= lfence_before_ret_none
4604 && (i
.tm
.base_opcode
== 0xc2
4605 || i
.tm
.base_opcode
== 0xc3))
4607 if (last_insn
.kind
!= last_insn_other
4608 && last_insn
.seg
== now_seg
)
4610 as_warn_where (last_insn
.file
, last_insn
.line
,
4611 _("`%s` skips -mlfence-before-ret on `%s`"),
4612 last_insn
.name
, i
.tm
.name
);
4616 /* Near ret ingore operand size override under CPU64. */
4617 char prefix
= flag_code
== CODE_64BIT
4619 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4621 if (lfence_before_ret
== lfence_before_ret_not
)
4623 /* not: 0xf71424, may add prefix
4624 for operand size override or 64-bit code. */
4625 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4639 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4642 if (lfence_before_ret
== lfence_before_ret_or
)
4644 /* or: 0x830c2400, may add prefix
4645 for operand size override or 64-bit code. */
4651 /* shl: 0xc1242400, may add prefix
4652 for operand size override or 64-bit code. */
4667 /* This is the guts of the machine-dependent assembler. LINE points to a
4668 machine dependent instruction. This function is supposed to emit
4669 the frags/bytes it assembles to. */
4672 md_assemble (char *line
)
4675 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4676 const insn_template
*t
;
4678 /* Initialize globals. */
4679 memset (&i
, '\0', sizeof (i
));
4680 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4681 i
.reloc
[j
] = NO_RELOC
;
4682 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4683 memset (im_expressions
, '\0', sizeof (im_expressions
));
4684 save_stack_p
= save_stack
;
4686 /* First parse an instruction mnemonic & call i386_operand for the operands.
4687 We assume that the scrubber has arranged it so that line[0] is the valid
4688 start of a (possibly prefixed) mnemonic. */
4690 line
= parse_insn (line
, mnemonic
);
4693 mnem_suffix
= i
.suffix
;
4695 line
= parse_operands (line
, mnemonic
);
4697 xfree (i
.memop1_string
);
4698 i
.memop1_string
= NULL
;
4702 /* Now we've parsed the mnemonic into a set of templates, and have the
4703 operands at hand. */
4705 /* All Intel opcodes have reversed operands except for "bound", "enter",
4706 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4707 intersegment "jmp" and "call" instructions with 2 immediate operands so
4708 that the immediate segment precedes the offset, as it does when in AT&T
4712 && (strcmp (mnemonic
, "bound") != 0)
4713 && (strcmp (mnemonic
, "invlpga") != 0)
4714 && (strncmp (mnemonic
, "monitor", 7) != 0)
4715 && (strncmp (mnemonic
, "mwait", 5) != 0)
4716 && (strcmp (mnemonic
, "tpause") != 0)
4717 && (strcmp (mnemonic
, "umwait") != 0)
4718 && !(operand_type_check (i
.types
[0], imm
)
4719 && operand_type_check (i
.types
[1], imm
)))
4722 /* The order of the immediates should be reversed
4723 for 2 immediates extrq and insertq instructions */
4724 if (i
.imm_operands
== 2
4725 && (strcmp (mnemonic
, "extrq") == 0
4726 || strcmp (mnemonic
, "insertq") == 0))
4727 swap_2_operands (0, 1);
4732 /* Don't optimize displacement for movabs since it only takes 64bit
4735 && i
.disp_encoding
!= disp_encoding_32bit
4736 && (flag_code
!= CODE_64BIT
4737 || strcmp (mnemonic
, "movabs") != 0))
4740 /* Next, we find a template that matches the given insn,
4741 making sure the overlap of the given operands types is consistent
4742 with the template operand types. */
4744 if (!(t
= match_template (mnem_suffix
)))
4747 if (sse_check
!= check_none
4748 && !i
.tm
.opcode_modifier
.noavx
4749 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4750 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4751 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4752 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4753 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4754 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4755 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4756 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4757 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4758 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4759 || i
.tm
.cpu_flags
.bitfield
.cpusha
4760 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4762 (sse_check
== check_warning
4764 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4767 if (i
.tm
.opcode_modifier
.fwait
)
4768 if (!add_prefix (FWAIT_OPCODE
))
4771 /* Check if REP prefix is OK. */
4772 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4774 as_bad (_("invalid instruction `%s' after `%s'"),
4775 i
.tm
.name
, i
.rep_prefix
);
4779 /* Check for lock without a lockable instruction. Destination operand
4780 must be memory unless it is xchg (0x86). */
4781 if (i
.prefix
[LOCK_PREFIX
]
4782 && (!i
.tm
.opcode_modifier
.islockable
4783 || i
.mem_operands
== 0
4784 || (i
.tm
.base_opcode
!= 0x86
4785 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4787 as_bad (_("expecting lockable instruction after `lock'"));
4791 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4792 if (i
.prefix
[DATA_PREFIX
]
4793 && (is_any_vex_encoding (&i
.tm
)
4794 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4795 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4797 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4801 /* Check if HLE prefix is OK. */
4802 if (i
.hle_prefix
&& !check_hle ())
4805 /* Check BND prefix. */
4806 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4807 as_bad (_("expecting valid branch instruction after `bnd'"));
4809 /* Check NOTRACK prefix. */
4810 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4811 as_bad (_("expecting indirect branch instruction after `notrack'"));
4813 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4815 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4816 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4817 else if (flag_code
!= CODE_16BIT
4818 ? i
.prefix
[ADDR_PREFIX
]
4819 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4820 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4823 /* Insert BND prefix. */
4824 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4826 if (!i
.prefix
[BND_PREFIX
])
4827 add_prefix (BND_PREFIX_OPCODE
);
4828 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4830 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4831 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4835 /* Check string instruction segment overrides. */
4836 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4838 gas_assert (i
.mem_operands
);
4839 if (!check_string ())
4841 i
.disp_operands
= 0;
4844 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4845 optimize_encoding ();
4847 if (!process_suffix ())
4850 /* Update operand types and check extended states. */
4851 for (j
= 0; j
< i
.operands
; j
++)
4853 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4854 switch (i
.tm
.operand_types
[j
].bitfield
.class)
4859 i
.xstate
|= xstate_mmx
;
4862 i
.xstate
|= xstate_zmm
;
4865 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
4866 i
.xstate
|= xstate_tmm
;
4867 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
4868 i
.xstate
|= xstate_zmm
;
4869 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
4870 i
.xstate
|= xstate_ymm
;
4871 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
4872 i
.xstate
|= xstate_xmm
;
4877 /* Make still unresolved immediate matches conform to size of immediate
4878 given in i.suffix. */
4879 if (!finalize_imm ())
4882 if (i
.types
[0].bitfield
.imm1
)
4883 i
.imm_operands
= 0; /* kludge for shift insns. */
4885 /* We only need to check those implicit registers for instructions
4886 with 3 operands or less. */
4887 if (i
.operands
<= 3)
4888 for (j
= 0; j
< i
.operands
; j
++)
4889 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4890 && !i
.types
[j
].bitfield
.xmmword
)
4893 /* For insns with operands there are more diddles to do to the opcode. */
4896 if (!process_operands ())
4899 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4901 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4902 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4905 if (is_any_vex_encoding (&i
.tm
))
4907 if (!cpu_arch_flags
.bitfield
.cpui286
)
4909 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4914 /* Check for explicit REX prefix. */
4915 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
4917 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
4921 if (i
.tm
.opcode_modifier
.vex
)
4922 build_vex_prefix (t
);
4924 build_evex_prefix ();
4926 /* The individual REX.RXBW bits got consumed. */
4927 i
.rex
&= REX_OPCODE
;
4930 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4931 instructions may define INT_OPCODE as well, so avoid this corner
4932 case for those instructions that use MODRM. */
4933 if (i
.tm
.base_opcode
== INT_OPCODE
4934 && !i
.tm
.opcode_modifier
.modrm
4935 && i
.op
[0].imms
->X_add_number
== 3)
4937 i
.tm
.base_opcode
= INT3_OPCODE
;
4941 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4942 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4943 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4944 && i
.op
[0].disps
->X_op
== O_constant
)
4946 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4947 the absolute address given by the constant. Since ix86 jumps and
4948 calls are pc relative, we need to generate a reloc. */
4949 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4950 i
.op
[0].disps
->X_op
= O_symbol
;
4953 /* For 8 bit registers we need an empty rex prefix. Also if the
4954 instruction already has a prefix, we need to convert old
4955 registers to new ones. */
4957 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4958 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4959 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4960 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4961 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4962 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4967 i
.rex
|= REX_OPCODE
;
4968 for (x
= 0; x
< 2; x
++)
4970 /* Look for 8 bit operand that uses old registers. */
4971 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4972 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4974 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4975 /* In case it is "hi" register, give up. */
4976 if (i
.op
[x
].regs
->reg_num
> 3)
4977 as_bad (_("can't encode register '%s%s' in an "
4978 "instruction requiring REX prefix."),
4979 register_prefix
, i
.op
[x
].regs
->reg_name
);
4981 /* Otherwise it is equivalent to the extended register.
4982 Since the encoding doesn't change this is merely
4983 cosmetic cleanup for debug output. */
4985 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4990 if (i
.rex
== 0 && i
.rex_encoding
)
4992 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4993 that uses legacy register. If it is "hi" register, don't add
4994 the REX_OPCODE byte. */
4996 for (x
= 0; x
< 2; x
++)
4997 if (i
.types
[x
].bitfield
.class == Reg
4998 && i
.types
[x
].bitfield
.byte
4999 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5000 && i
.op
[x
].regs
->reg_num
> 3)
5002 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5003 i
.rex_encoding
= FALSE
;
5012 add_prefix (REX_OPCODE
| i
.rex
);
5014 insert_lfence_before ();
5016 /* We are ready to output the insn. */
5019 insert_lfence_after ();
5021 last_insn
.seg
= now_seg
;
5023 if (i
.tm
.opcode_modifier
.isprefix
)
5025 last_insn
.kind
= last_insn_prefix
;
5026 last_insn
.name
= i
.tm
.name
;
5027 last_insn
.file
= as_where (&last_insn
.line
);
5030 last_insn
.kind
= last_insn_other
;
5034 parse_insn (char *line
, char *mnemonic
)
5037 char *token_start
= l
;
5040 const insn_template
*t
;
5046 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5051 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5053 as_bad (_("no such instruction: `%s'"), token_start
);
5058 if (!is_space_char (*l
)
5059 && *l
!= END_OF_INSN
5061 || (*l
!= PREFIX_SEPARATOR
5064 as_bad (_("invalid character %s in mnemonic"),
5065 output_invalid (*l
));
5068 if (token_start
== l
)
5070 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5071 as_bad (_("expecting prefix; got nothing"));
5073 as_bad (_("expecting mnemonic; got nothing"));
5077 /* Look up instruction (or prefix) via hash table. */
5078 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5080 if (*l
!= END_OF_INSN
5081 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5082 && current_templates
5083 && current_templates
->start
->opcode_modifier
.isprefix
)
5085 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5087 as_bad ((flag_code
!= CODE_64BIT
5088 ? _("`%s' is only supported in 64-bit mode")
5089 : _("`%s' is not supported in 64-bit mode")),
5090 current_templates
->start
->name
);
5093 /* If we are in 16-bit mode, do not allow addr16 or data16.
5094 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5095 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5096 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5097 && flag_code
!= CODE_64BIT
5098 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5099 ^ (flag_code
== CODE_16BIT
)))
5101 as_bad (_("redundant %s prefix"),
5102 current_templates
->start
->name
);
5105 if (current_templates
->start
->opcode_length
== 0)
5107 /* Handle pseudo prefixes. */
5108 switch (current_templates
->start
->base_opcode
)
5112 i
.disp_encoding
= disp_encoding_8bit
;
5116 i
.disp_encoding
= disp_encoding_16bit
;
5120 i
.disp_encoding
= disp_encoding_32bit
;
5124 i
.dir_encoding
= dir_encoding_load
;
5128 i
.dir_encoding
= dir_encoding_store
;
5132 i
.vec_encoding
= vex_encoding_vex
;
5136 i
.vec_encoding
= vex_encoding_vex3
;
5140 i
.vec_encoding
= vex_encoding_evex
;
5144 i
.rex_encoding
= TRUE
;
5146 case Prefix_NoOptimize
:
5148 i
.no_optimize
= TRUE
;
5156 /* Add prefix, checking for repeated prefixes. */
5157 switch (add_prefix (current_templates
->start
->base_opcode
))
5162 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5163 i
.notrack_prefix
= current_templates
->start
->name
;
5166 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5167 i
.hle_prefix
= current_templates
->start
->name
;
5168 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5169 i
.bnd_prefix
= current_templates
->start
->name
;
5171 i
.rep_prefix
= current_templates
->start
->name
;
5177 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5184 if (!current_templates
)
5186 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5187 Check if we should swap operand or force 32bit displacement in
5189 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5190 i
.dir_encoding
= dir_encoding_swap
;
5191 else if (mnem_p
- 3 == dot_p
5194 i
.disp_encoding
= disp_encoding_8bit
;
5195 else if (mnem_p
- 4 == dot_p
5199 i
.disp_encoding
= disp_encoding_32bit
;
5204 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5207 if (!current_templates
)
5210 if (mnem_p
> mnemonic
)
5212 /* See if we can get a match by trimming off a suffix. */
5215 case WORD_MNEM_SUFFIX
:
5216 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5217 i
.suffix
= SHORT_MNEM_SUFFIX
;
5220 case BYTE_MNEM_SUFFIX
:
5221 case QWORD_MNEM_SUFFIX
:
5222 i
.suffix
= mnem_p
[-1];
5225 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5227 case SHORT_MNEM_SUFFIX
:
5228 case LONG_MNEM_SUFFIX
:
5231 i
.suffix
= mnem_p
[-1];
5234 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5242 if (intel_float_operand (mnemonic
) == 1)
5243 i
.suffix
= SHORT_MNEM_SUFFIX
;
5245 i
.suffix
= LONG_MNEM_SUFFIX
;
5248 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5254 if (!current_templates
)
5256 as_bad (_("no such instruction: `%s'"), token_start
);
5261 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5262 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5264 /* Check for a branch hint. We allow ",pt" and ",pn" for
5265 predict taken and predict not taken respectively.
5266 I'm not sure that branch hints actually do anything on loop
5267 and jcxz insns (JumpByte) for current Pentium4 chips. They
5268 may work in the future and it doesn't hurt to accept them
5270 if (l
[0] == ',' && l
[1] == 'p')
5274 if (!add_prefix (DS_PREFIX_OPCODE
))
5278 else if (l
[2] == 'n')
5280 if (!add_prefix (CS_PREFIX_OPCODE
))
5286 /* Any other comma loses. */
5289 as_bad (_("invalid character %s in mnemonic"),
5290 output_invalid (*l
));
5294 /* Check if instruction is supported on specified architecture. */
5296 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5298 supported
|= cpu_flags_match (t
);
5299 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5301 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5302 as_warn (_("use .code16 to ensure correct addressing mode"));
5308 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5309 as_bad (flag_code
== CODE_64BIT
5310 ? _("`%s' is not supported in 64-bit mode")
5311 : _("`%s' is only supported in 64-bit mode"),
5312 current_templates
->start
->name
);
5314 as_bad (_("`%s' is not supported on `%s%s'"),
5315 current_templates
->start
->name
,
5316 cpu_arch_name
? cpu_arch_name
: default_arch
,
5317 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5323 parse_operands (char *l
, const char *mnemonic
)
5327 /* 1 if operand is pending after ','. */
5328 unsigned int expecting_operand
= 0;
5330 /* Non-zero if operand parens not balanced. */
5331 unsigned int paren_not_balanced
;
5333 while (*l
!= END_OF_INSN
)
5335 /* Skip optional white space before operand. */
5336 if (is_space_char (*l
))
5338 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5340 as_bad (_("invalid character %s before operand %d"),
5341 output_invalid (*l
),
5345 token_start
= l
; /* After white space. */
5346 paren_not_balanced
= 0;
5347 while (paren_not_balanced
|| *l
!= ',')
5349 if (*l
== END_OF_INSN
)
5351 if (paren_not_balanced
)
5354 as_bad (_("unbalanced parenthesis in operand %d."),
5357 as_bad (_("unbalanced brackets in operand %d."),
5362 break; /* we are done */
5364 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5366 as_bad (_("invalid character %s in operand %d"),
5367 output_invalid (*l
),
5374 ++paren_not_balanced
;
5376 --paren_not_balanced
;
5381 ++paren_not_balanced
;
5383 --paren_not_balanced
;
5387 if (l
!= token_start
)
5388 { /* Yes, we've read in another operand. */
5389 unsigned int operand_ok
;
5390 this_operand
= i
.operands
++;
5391 if (i
.operands
> MAX_OPERANDS
)
5393 as_bad (_("spurious operands; (%d operands/instruction max)"),
5397 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5398 /* Now parse operand adding info to 'i' as we go along. */
5399 END_STRING_AND_SAVE (l
);
5401 if (i
.mem_operands
> 1)
5403 as_bad (_("too many memory references for `%s'"),
5410 i386_intel_operand (token_start
,
5411 intel_float_operand (mnemonic
));
5413 operand_ok
= i386_att_operand (token_start
);
5415 RESTORE_END_STRING (l
);
5421 if (expecting_operand
)
5423 expecting_operand_after_comma
:
5424 as_bad (_("expecting operand after ','; got nothing"));
5429 as_bad (_("expecting operand before ','; got nothing"));
5434 /* Now *l must be either ',' or END_OF_INSN. */
5437 if (*++l
== END_OF_INSN
)
5439 /* Just skip it, if it's \n complain. */
5440 goto expecting_operand_after_comma
;
5442 expecting_operand
= 1;
5449 swap_2_operands (int xchg1
, int xchg2
)
5451 union i386_op temp_op
;
5452 i386_operand_type temp_type
;
5453 unsigned int temp_flags
;
5454 enum bfd_reloc_code_real temp_reloc
;
5456 temp_type
= i
.types
[xchg2
];
5457 i
.types
[xchg2
] = i
.types
[xchg1
];
5458 i
.types
[xchg1
] = temp_type
;
5460 temp_flags
= i
.flags
[xchg2
];
5461 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5462 i
.flags
[xchg1
] = temp_flags
;
5464 temp_op
= i
.op
[xchg2
];
5465 i
.op
[xchg2
] = i
.op
[xchg1
];
5466 i
.op
[xchg1
] = temp_op
;
5468 temp_reloc
= i
.reloc
[xchg2
];
5469 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5470 i
.reloc
[xchg1
] = temp_reloc
;
5474 if (i
.mask
->operand
== xchg1
)
5475 i
.mask
->operand
= xchg2
;
5476 else if (i
.mask
->operand
== xchg2
)
5477 i
.mask
->operand
= xchg1
;
5481 if (i
.broadcast
->operand
== xchg1
)
5482 i
.broadcast
->operand
= xchg2
;
5483 else if (i
.broadcast
->operand
== xchg2
)
5484 i
.broadcast
->operand
= xchg1
;
5488 if (i
.rounding
->operand
== xchg1
)
5489 i
.rounding
->operand
= xchg2
;
5490 else if (i
.rounding
->operand
== xchg2
)
5491 i
.rounding
->operand
= xchg1
;
5496 swap_operands (void)
5502 swap_2_operands (1, i
.operands
- 2);
5506 swap_2_operands (0, i
.operands
- 1);
5512 if (i
.mem_operands
== 2)
5514 const seg_entry
*temp_seg
;
5515 temp_seg
= i
.seg
[0];
5516 i
.seg
[0] = i
.seg
[1];
5517 i
.seg
[1] = temp_seg
;
5521 /* Try to ensure constant immediates are represented in the smallest
5526 char guess_suffix
= 0;
5530 guess_suffix
= i
.suffix
;
5531 else if (i
.reg_operands
)
5533 /* Figure out a suffix from the last register operand specified.
5534 We can't do this properly yet, i.e. excluding special register
5535 instances, but the following works for instructions with
5536 immediates. In any case, we can't set i.suffix yet. */
5537 for (op
= i
.operands
; --op
>= 0;)
5538 if (i
.types
[op
].bitfield
.class != Reg
)
5540 else if (i
.types
[op
].bitfield
.byte
)
5542 guess_suffix
= BYTE_MNEM_SUFFIX
;
5545 else if (i
.types
[op
].bitfield
.word
)
5547 guess_suffix
= WORD_MNEM_SUFFIX
;
5550 else if (i
.types
[op
].bitfield
.dword
)
5552 guess_suffix
= LONG_MNEM_SUFFIX
;
5555 else if (i
.types
[op
].bitfield
.qword
)
5557 guess_suffix
= QWORD_MNEM_SUFFIX
;
5561 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5562 guess_suffix
= WORD_MNEM_SUFFIX
;
5564 for (op
= i
.operands
; --op
>= 0;)
5565 if (operand_type_check (i
.types
[op
], imm
))
5567 switch (i
.op
[op
].imms
->X_op
)
5570 /* If a suffix is given, this operand may be shortened. */
5571 switch (guess_suffix
)
5573 case LONG_MNEM_SUFFIX
:
5574 i
.types
[op
].bitfield
.imm32
= 1;
5575 i
.types
[op
].bitfield
.imm64
= 1;
5577 case WORD_MNEM_SUFFIX
:
5578 i
.types
[op
].bitfield
.imm16
= 1;
5579 i
.types
[op
].bitfield
.imm32
= 1;
5580 i
.types
[op
].bitfield
.imm32s
= 1;
5581 i
.types
[op
].bitfield
.imm64
= 1;
5583 case BYTE_MNEM_SUFFIX
:
5584 i
.types
[op
].bitfield
.imm8
= 1;
5585 i
.types
[op
].bitfield
.imm8s
= 1;
5586 i
.types
[op
].bitfield
.imm16
= 1;
5587 i
.types
[op
].bitfield
.imm32
= 1;
5588 i
.types
[op
].bitfield
.imm32s
= 1;
5589 i
.types
[op
].bitfield
.imm64
= 1;
5593 /* If this operand is at most 16 bits, convert it
5594 to a signed 16 bit number before trying to see
5595 whether it will fit in an even smaller size.
5596 This allows a 16-bit operand such as $0xffe0 to
5597 be recognised as within Imm8S range. */
5598 if ((i
.types
[op
].bitfield
.imm16
)
5599 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5601 i
.op
[op
].imms
->X_add_number
=
5602 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5605 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5606 if ((i
.types
[op
].bitfield
.imm32
)
5607 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5610 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5611 ^ ((offsetT
) 1 << 31))
5612 - ((offsetT
) 1 << 31));
5616 = operand_type_or (i
.types
[op
],
5617 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5619 /* We must avoid matching of Imm32 templates when 64bit
5620 only immediate is available. */
5621 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5622 i
.types
[op
].bitfield
.imm32
= 0;
5629 /* Symbols and expressions. */
5631 /* Convert symbolic operand to proper sizes for matching, but don't
5632 prevent matching a set of insns that only supports sizes other
5633 than those matching the insn suffix. */
5635 i386_operand_type mask
, allowed
;
5636 const insn_template
*t
;
5638 operand_type_set (&mask
, 0);
5639 operand_type_set (&allowed
, 0);
5641 for (t
= current_templates
->start
;
5642 t
< current_templates
->end
;
5645 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5646 allowed
= operand_type_and (allowed
, anyimm
);
5648 switch (guess_suffix
)
5650 case QWORD_MNEM_SUFFIX
:
5651 mask
.bitfield
.imm64
= 1;
5652 mask
.bitfield
.imm32s
= 1;
5654 case LONG_MNEM_SUFFIX
:
5655 mask
.bitfield
.imm32
= 1;
5657 case WORD_MNEM_SUFFIX
:
5658 mask
.bitfield
.imm16
= 1;
5660 case BYTE_MNEM_SUFFIX
:
5661 mask
.bitfield
.imm8
= 1;
5666 allowed
= operand_type_and (mask
, allowed
);
5667 if (!operand_type_all_zero (&allowed
))
5668 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5675 /* Try to use the smallest displacement type too. */
5677 optimize_disp (void)
5681 for (op
= i
.operands
; --op
>= 0;)
5682 if (operand_type_check (i
.types
[op
], disp
))
5684 if (i
.op
[op
].disps
->X_op
== O_constant
)
5686 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5688 if (i
.types
[op
].bitfield
.disp16
5689 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5691 /* If this operand is at most 16 bits, convert
5692 to a signed 16 bit number and don't use 64bit
5694 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5695 i
.types
[op
].bitfield
.disp64
= 0;
5698 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5699 if (i
.types
[op
].bitfield
.disp32
5700 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5702 /* If this operand is at most 32 bits, convert
5703 to a signed 32 bit number and don't use 64bit
5705 op_disp
&= (((offsetT
) 2 << 31) - 1);
5706 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5707 i
.types
[op
].bitfield
.disp64
= 0;
5710 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5712 i
.types
[op
].bitfield
.disp8
= 0;
5713 i
.types
[op
].bitfield
.disp16
= 0;
5714 i
.types
[op
].bitfield
.disp32
= 0;
5715 i
.types
[op
].bitfield
.disp32s
= 0;
5716 i
.types
[op
].bitfield
.disp64
= 0;
5720 else if (flag_code
== CODE_64BIT
)
5722 if (fits_in_signed_long (op_disp
))
5724 i
.types
[op
].bitfield
.disp64
= 0;
5725 i
.types
[op
].bitfield
.disp32s
= 1;
5727 if (i
.prefix
[ADDR_PREFIX
]
5728 && fits_in_unsigned_long (op_disp
))
5729 i
.types
[op
].bitfield
.disp32
= 1;
5731 if ((i
.types
[op
].bitfield
.disp32
5732 || i
.types
[op
].bitfield
.disp32s
5733 || i
.types
[op
].bitfield
.disp16
)
5734 && fits_in_disp8 (op_disp
))
5735 i
.types
[op
].bitfield
.disp8
= 1;
5737 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5738 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5740 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5741 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5742 i
.types
[op
].bitfield
.disp8
= 0;
5743 i
.types
[op
].bitfield
.disp16
= 0;
5744 i
.types
[op
].bitfield
.disp32
= 0;
5745 i
.types
[op
].bitfield
.disp32s
= 0;
5746 i
.types
[op
].bitfield
.disp64
= 0;
5749 /* We only support 64bit displacement on constants. */
5750 i
.types
[op
].bitfield
.disp64
= 0;
5754 /* Return 1 if there is a match in broadcast bytes between operand
5755 GIVEN and instruction template T. */
5758 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5760 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5761 && i
.types
[given
].bitfield
.byte
)
5762 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5763 && i
.types
[given
].bitfield
.word
)
5764 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5765 && i
.types
[given
].bitfield
.dword
)
5766 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5767 && i
.types
[given
].bitfield
.qword
));
5770 /* Check if operands are valid for the instruction. */
5773 check_VecOperands (const insn_template
*t
)
5778 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5779 any one operand are implicity requiring AVX512VL support if the actual
5780 operand size is YMMword or XMMword. Since this function runs after
5781 template matching, there's no need to check for YMMword/XMMword in
5783 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5784 if (!cpu_flags_all_zero (&cpu
)
5785 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5786 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5788 for (op
= 0; op
< t
->operands
; ++op
)
5790 if (t
->operand_types
[op
].bitfield
.zmmword
5791 && (i
.types
[op
].bitfield
.ymmword
5792 || i
.types
[op
].bitfield
.xmmword
))
5794 i
.error
= unsupported
;
5800 /* Without VSIB byte, we can't have a vector register for index. */
5801 if (!t
->opcode_modifier
.sib
5803 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5804 || i
.index_reg
->reg_type
.bitfield
.ymmword
5805 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5807 i
.error
= unsupported_vector_index_register
;
5811 /* Check if default mask is allowed. */
5812 if (t
->opcode_modifier
.nodefmask
5813 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5815 i
.error
= no_default_mask
;
5819 /* For VSIB byte, we need a vector register for index, and all vector
5820 registers must be distinct. */
5821 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
5824 || !((t
->opcode_modifier
.sib
== VECSIB128
5825 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5826 || (t
->opcode_modifier
.sib
== VECSIB256
5827 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5828 || (t
->opcode_modifier
.sib
== VECSIB512
5829 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5831 i
.error
= invalid_vsib_address
;
5835 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5836 if (i
.reg_operands
== 2 && !i
.mask
)
5838 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5839 gas_assert (i
.types
[0].bitfield
.xmmword
5840 || i
.types
[0].bitfield
.ymmword
);
5841 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5842 gas_assert (i
.types
[2].bitfield
.xmmword
5843 || i
.types
[2].bitfield
.ymmword
);
5844 if (operand_check
== check_none
)
5846 if (register_number (i
.op
[0].regs
)
5847 != register_number (i
.index_reg
)
5848 && register_number (i
.op
[2].regs
)
5849 != register_number (i
.index_reg
)
5850 && register_number (i
.op
[0].regs
)
5851 != register_number (i
.op
[2].regs
))
5853 if (operand_check
== check_error
)
5855 i
.error
= invalid_vector_register_set
;
5858 as_warn (_("mask, index, and destination registers should be distinct"));
5860 else if (i
.reg_operands
== 1 && i
.mask
)
5862 if (i
.types
[1].bitfield
.class == RegSIMD
5863 && (i
.types
[1].bitfield
.xmmword
5864 || i
.types
[1].bitfield
.ymmword
5865 || i
.types
[1].bitfield
.zmmword
)
5866 && (register_number (i
.op
[1].regs
)
5867 == register_number (i
.index_reg
)))
5869 if (operand_check
== check_error
)
5871 i
.error
= invalid_vector_register_set
;
5874 if (operand_check
!= check_none
)
5875 as_warn (_("index and destination registers should be distinct"));
5880 /* For AMX instructions with three tmmword operands, all tmmword operand must be
5882 if (t
->operand_types
[0].bitfield
.tmmword
5883 && i
.reg_operands
== 3)
5885 if (register_number (i
.op
[0].regs
)
5886 == register_number (i
.op
[1].regs
)
5887 || register_number (i
.op
[0].regs
)
5888 == register_number (i
.op
[2].regs
)
5889 || register_number (i
.op
[1].regs
)
5890 == register_number (i
.op
[2].regs
))
5892 i
.error
= invalid_tmm_register_set
;
5897 /* Check if broadcast is supported by the instruction and is applied
5898 to the memory operand. */
5901 i386_operand_type type
, overlap
;
5903 /* Check if specified broadcast is supported in this instruction,
5904 and its broadcast bytes match the memory operand. */
5905 op
= i
.broadcast
->operand
;
5906 if (!t
->opcode_modifier
.broadcast
5907 || !(i
.flags
[op
] & Operand_Mem
)
5908 || (!i
.types
[op
].bitfield
.unspecified
5909 && !match_broadcast_size (t
, op
)))
5912 i
.error
= unsupported_broadcast
;
5916 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5917 * i
.broadcast
->type
);
5918 operand_type_set (&type
, 0);
5919 switch (i
.broadcast
->bytes
)
5922 type
.bitfield
.word
= 1;
5925 type
.bitfield
.dword
= 1;
5928 type
.bitfield
.qword
= 1;
5931 type
.bitfield
.xmmword
= 1;
5934 type
.bitfield
.ymmword
= 1;
5937 type
.bitfield
.zmmword
= 1;
5943 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5944 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5945 && t
->operand_types
[op
].bitfield
.byte
5946 + t
->operand_types
[op
].bitfield
.word
5947 + t
->operand_types
[op
].bitfield
.dword
5948 + t
->operand_types
[op
].bitfield
.qword
> 1)
5950 overlap
.bitfield
.xmmword
= 0;
5951 overlap
.bitfield
.ymmword
= 0;
5952 overlap
.bitfield
.zmmword
= 0;
5954 if (operand_type_all_zero (&overlap
))
5957 if (t
->opcode_modifier
.checkregsize
)
5961 type
.bitfield
.baseindex
= 1;
5962 for (j
= 0; j
< i
.operands
; ++j
)
5965 && !operand_type_register_match(i
.types
[j
],
5966 t
->operand_types
[j
],
5968 t
->operand_types
[op
]))
5973 /* If broadcast is supported in this instruction, we need to check if
5974 operand of one-element size isn't specified without broadcast. */
5975 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5977 /* Find memory operand. */
5978 for (op
= 0; op
< i
.operands
; op
++)
5979 if (i
.flags
[op
] & Operand_Mem
)
5981 gas_assert (op
< i
.operands
);
5982 /* Check size of the memory operand. */
5983 if (match_broadcast_size (t
, op
))
5985 i
.error
= broadcast_needed
;
5990 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5992 /* Check if requested masking is supported. */
5995 switch (t
->opcode_modifier
.masking
)
5999 case MERGING_MASKING
:
6000 if (i
.mask
->zeroing
)
6003 i
.error
= unsupported_masking
;
6007 case DYNAMIC_MASKING
:
6008 /* Memory destinations allow only merging masking. */
6009 if (i
.mask
->zeroing
&& i
.mem_operands
)
6011 /* Find memory operand. */
6012 for (op
= 0; op
< i
.operands
; op
++)
6013 if (i
.flags
[op
] & Operand_Mem
)
6015 gas_assert (op
< i
.operands
);
6016 if (op
== i
.operands
- 1)
6018 i
.error
= unsupported_masking
;
6028 /* Check if masking is applied to dest operand. */
6029 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
6031 i
.error
= mask_not_on_destination
;
6038 if (!t
->opcode_modifier
.sae
6039 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6041 i
.error
= unsupported_rc_sae
;
6044 /* If the instruction has several immediate operands and one of
6045 them is rounding, the rounding operand should be the last
6046 immediate operand. */
6047 if (i
.imm_operands
> 1
6048 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6050 i
.error
= rc_sae_operand_not_last_imm
;
6055 /* Check the special Imm4 cases; must be the first operand. */
6056 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6058 if (i
.op
[0].imms
->X_op
!= O_constant
6059 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6065 /* Turn off Imm<N> so that update_imm won't complain. */
6066 operand_type_set (&i
.types
[0], 0);
6069 /* Check vector Disp8 operand. */
6070 if (t
->opcode_modifier
.disp8memshift
6071 && i
.disp_encoding
!= disp_encoding_32bit
)
6074 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6075 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6076 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6079 const i386_operand_type
*type
= NULL
;
6082 for (op
= 0; op
< i
.operands
; op
++)
6083 if (i
.flags
[op
] & Operand_Mem
)
6085 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6086 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6087 else if (t
->operand_types
[op
].bitfield
.xmmword
6088 + t
->operand_types
[op
].bitfield
.ymmword
6089 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6090 type
= &t
->operand_types
[op
];
6091 else if (!i
.types
[op
].bitfield
.unspecified
)
6092 type
= &i
.types
[op
];
6094 else if (i
.types
[op
].bitfield
.class == RegSIMD
6095 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6097 if (i
.types
[op
].bitfield
.zmmword
)
6099 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6101 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6107 if (type
->bitfield
.zmmword
)
6109 else if (type
->bitfield
.ymmword
)
6111 else if (type
->bitfield
.xmmword
)
6115 /* For the check in fits_in_disp8(). */
6116 if (i
.memshift
== 0)
6120 for (op
= 0; op
< i
.operands
; op
++)
6121 if (operand_type_check (i
.types
[op
], disp
)
6122 && i
.op
[op
].disps
->X_op
== O_constant
)
6124 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6126 i
.types
[op
].bitfield
.disp8
= 1;
6129 i
.types
[op
].bitfield
.disp8
= 0;
6138 /* Check if encoding requirements are met by the instruction. */
6141 VEX_check_encoding (const insn_template
*t
)
6143 if (i
.vec_encoding
== vex_encoding_error
)
6145 i
.error
= unsupported
;
6149 if (i
.vec_encoding
== vex_encoding_evex
)
6151 /* This instruction must be encoded with EVEX prefix. */
6152 if (!is_evex_encoding (t
))
6154 i
.error
= unsupported
;
6160 if (!t
->opcode_modifier
.vex
)
6162 /* This instruction template doesn't have VEX prefix. */
6163 if (i
.vec_encoding
!= vex_encoding_default
)
6165 i
.error
= unsupported
;
6174 static const insn_template
*
6175 match_template (char mnem_suffix
)
6177 /* Points to template once we've found it. */
6178 const insn_template
*t
;
6179 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6180 i386_operand_type overlap4
;
6181 unsigned int found_reverse_match
;
6182 i386_opcode_modifier suffix_check
;
6183 i386_operand_type operand_types
[MAX_OPERANDS
];
6184 int addr_prefix_disp
;
6185 unsigned int j
, size_match
, check_register
;
6186 enum i386_error specific_error
= 0;
6188 #if MAX_OPERANDS != 5
6189 # error "MAX_OPERANDS must be 5."
6192 found_reverse_match
= 0;
6193 addr_prefix_disp
= -1;
6195 /* Prepare for mnemonic suffix check. */
6196 memset (&suffix_check
, 0, sizeof (suffix_check
));
6197 switch (mnem_suffix
)
6199 case BYTE_MNEM_SUFFIX
:
6200 suffix_check
.no_bsuf
= 1;
6202 case WORD_MNEM_SUFFIX
:
6203 suffix_check
.no_wsuf
= 1;
6205 case SHORT_MNEM_SUFFIX
:
6206 suffix_check
.no_ssuf
= 1;
6208 case LONG_MNEM_SUFFIX
:
6209 suffix_check
.no_lsuf
= 1;
6211 case QWORD_MNEM_SUFFIX
:
6212 suffix_check
.no_qsuf
= 1;
6215 /* NB: In Intel syntax, normally we can check for memory operand
6216 size when there is no mnemonic suffix. But jmp and call have
6217 2 different encodings with Dword memory operand size, one with
6218 No_ldSuf and the other without. i.suffix is set to
6219 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6220 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6221 suffix_check
.no_ldsuf
= 1;
6224 /* Must have right number of operands. */
6225 i
.error
= number_of_operands_mismatch
;
6227 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6229 addr_prefix_disp
= -1;
6230 found_reverse_match
= 0;
6232 if (i
.operands
!= t
->operands
)
6235 /* Check processor support. */
6236 i
.error
= unsupported
;
6237 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6240 /* Check AT&T mnemonic. */
6241 i
.error
= unsupported_with_intel_mnemonic
;
6242 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6245 /* Check AT&T/Intel syntax. */
6246 i
.error
= unsupported_syntax
;
6247 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6248 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6251 /* Check Intel64/AMD64 ISA. */
6255 /* Default: Don't accept Intel64. */
6256 if (t
->opcode_modifier
.isa64
== INTEL64
)
6260 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6261 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6265 /* -mintel64: Don't accept AMD64. */
6266 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6271 /* Check the suffix. */
6272 i
.error
= invalid_instruction_suffix
;
6273 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6274 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6275 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6276 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6277 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6278 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6281 size_match
= operand_size_match (t
);
6285 /* This is intentionally not
6287 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6289 as the case of a missing * on the operand is accepted (perhaps with
6290 a warning, issued further down). */
6291 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6293 i
.error
= operand_type_mismatch
;
6297 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6298 operand_types
[j
] = t
->operand_types
[j
];
6300 /* In general, don't allow
6301 - 64-bit operands outside of 64-bit mode,
6302 - 32-bit operands on pre-386. */
6303 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6304 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6305 && flag_code
!= CODE_64BIT
6306 && (t
->base_opcode
!= 0x0fc7
6307 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
6308 || (i
.suffix
== LONG_MNEM_SUFFIX
6309 && !cpu_arch_flags
.bitfield
.cpui386
))
6311 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6312 && !intel_float_operand (t
->name
))
6313 : intel_float_operand (t
->name
) != 2)
6314 && (t
->operands
== i
.imm_operands
6315 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6316 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6317 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6318 || (operand_types
[j
].bitfield
.class != RegMMX
6319 && operand_types
[j
].bitfield
.class != RegSIMD
6320 && operand_types
[j
].bitfield
.class != RegMask
))
6321 && !t
->opcode_modifier
.sib
)
6324 /* Do not verify operands when there are none. */
6327 if (VEX_check_encoding (t
))
6329 specific_error
= i
.error
;
6333 /* We've found a match; break out of loop. */
6337 if (!t
->opcode_modifier
.jump
6338 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6340 /* There should be only one Disp operand. */
6341 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6342 if (operand_type_check (operand_types
[j
], disp
))
6344 if (j
< MAX_OPERANDS
)
6346 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6348 addr_prefix_disp
= j
;
6350 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6351 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6355 override
= !override
;
6358 if (operand_types
[j
].bitfield
.disp32
6359 && operand_types
[j
].bitfield
.disp16
)
6361 operand_types
[j
].bitfield
.disp16
= override
;
6362 operand_types
[j
].bitfield
.disp32
= !override
;
6364 operand_types
[j
].bitfield
.disp32s
= 0;
6365 operand_types
[j
].bitfield
.disp64
= 0;
6369 if (operand_types
[j
].bitfield
.disp32s
6370 || operand_types
[j
].bitfield
.disp64
)
6372 operand_types
[j
].bitfield
.disp64
&= !override
;
6373 operand_types
[j
].bitfield
.disp32s
&= !override
;
6374 operand_types
[j
].bitfield
.disp32
= override
;
6376 operand_types
[j
].bitfield
.disp16
= 0;
6382 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6383 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6386 /* We check register size if needed. */
6387 if (t
->opcode_modifier
.checkregsize
)
6389 check_register
= (1 << t
->operands
) - 1;
6391 check_register
&= ~(1 << i
.broadcast
->operand
);
6396 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6397 switch (t
->operands
)
6400 if (!operand_type_match (overlap0
, i
.types
[0]))
6404 /* xchg %eax, %eax is a special case. It is an alias for nop
6405 only in 32bit mode and we can use opcode 0x90. In 64bit
6406 mode, we can't use 0x90 for xchg %eax, %eax since it should
6407 zero-extend %eax to %rax. */
6408 if (flag_code
== CODE_64BIT
6409 && t
->base_opcode
== 0x90
6410 && i
.types
[0].bitfield
.instance
== Accum
6411 && i
.types
[0].bitfield
.dword
6412 && i
.types
[1].bitfield
.instance
== Accum
6413 && i
.types
[1].bitfield
.dword
)
6415 /* xrelease mov %eax, <disp> is another special case. It must not
6416 match the accumulator-only encoding of mov. */
6417 if (flag_code
!= CODE_64BIT
6419 && t
->base_opcode
== 0xa0
6420 && i
.types
[0].bitfield
.instance
== Accum
6421 && (i
.flags
[1] & Operand_Mem
))
6426 if (!(size_match
& MATCH_STRAIGHT
))
6428 /* Reverse direction of operands if swapping is possible in the first
6429 place (operands need to be symmetric) and
6430 - the load form is requested, and the template is a store form,
6431 - the store form is requested, and the template is a load form,
6432 - the non-default (swapped) form is requested. */
6433 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6434 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6435 && !operand_type_all_zero (&overlap1
))
6436 switch (i
.dir_encoding
)
6438 case dir_encoding_load
:
6439 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6440 || t
->opcode_modifier
.regmem
)
6444 case dir_encoding_store
:
6445 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6446 && !t
->opcode_modifier
.regmem
)
6450 case dir_encoding_swap
:
6453 case dir_encoding_default
:
6456 /* If we want store form, we skip the current load. */
6457 if ((i
.dir_encoding
== dir_encoding_store
6458 || i
.dir_encoding
== dir_encoding_swap
)
6459 && i
.mem_operands
== 0
6460 && t
->opcode_modifier
.load
)
6465 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6466 if (!operand_type_match (overlap0
, i
.types
[0])
6467 || !operand_type_match (overlap1
, i
.types
[1])
6468 || ((check_register
& 3) == 3
6469 && !operand_type_register_match (i
.types
[0],
6474 /* Check if other direction is valid ... */
6475 if (!t
->opcode_modifier
.d
)
6479 if (!(size_match
& MATCH_REVERSE
))
6481 /* Try reversing direction of operands. */
6482 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6483 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6484 if (!operand_type_match (overlap0
, i
.types
[0])
6485 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6487 && !operand_type_register_match (i
.types
[0],
6488 operand_types
[i
.operands
- 1],
6489 i
.types
[i
.operands
- 1],
6492 /* Does not match either direction. */
6495 /* found_reverse_match holds which of D or FloatR
6497 if (!t
->opcode_modifier
.d
)
6498 found_reverse_match
= 0;
6499 else if (operand_types
[0].bitfield
.tbyte
)
6500 found_reverse_match
= Opcode_FloatD
;
6501 else if (operand_types
[0].bitfield
.xmmword
6502 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6503 || operand_types
[0].bitfield
.class == RegMMX
6504 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6505 || is_any_vex_encoding(t
))
6506 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6507 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6509 found_reverse_match
= Opcode_D
;
6510 if (t
->opcode_modifier
.floatr
)
6511 found_reverse_match
|= Opcode_FloatR
;
6515 /* Found a forward 2 operand match here. */
6516 switch (t
->operands
)
6519 overlap4
= operand_type_and (i
.types
[4],
6523 overlap3
= operand_type_and (i
.types
[3],
6527 overlap2
= operand_type_and (i
.types
[2],
6532 switch (t
->operands
)
6535 if (!operand_type_match (overlap4
, i
.types
[4])
6536 || !operand_type_register_match (i
.types
[3],
6543 if (!operand_type_match (overlap3
, i
.types
[3])
6544 || ((check_register
& 0xa) == 0xa
6545 && !operand_type_register_match (i
.types
[1],
6549 || ((check_register
& 0xc) == 0xc
6550 && !operand_type_register_match (i
.types
[2],
6557 /* Here we make use of the fact that there are no
6558 reverse match 3 operand instructions. */
6559 if (!operand_type_match (overlap2
, i
.types
[2])
6560 || ((check_register
& 5) == 5
6561 && !operand_type_register_match (i
.types
[0],
6565 || ((check_register
& 6) == 6
6566 && !operand_type_register_match (i
.types
[1],
6574 /* Found either forward/reverse 2, 3 or 4 operand match here:
6575 slip through to break. */
6578 /* Check if vector operands are valid. */
6579 if (check_VecOperands (t
))
6581 specific_error
= i
.error
;
6585 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6586 if (VEX_check_encoding (t
))
6588 specific_error
= i
.error
;
6592 /* We've found a match; break out of loop. */
6596 if (t
== current_templates
->end
)
6598 /* We found no match. */
6599 const char *err_msg
;
6600 switch (specific_error
? specific_error
: i
.error
)
6604 case operand_size_mismatch
:
6605 err_msg
= _("operand size mismatch");
6607 case operand_type_mismatch
:
6608 err_msg
= _("operand type mismatch");
6610 case register_type_mismatch
:
6611 err_msg
= _("register type mismatch");
6613 case number_of_operands_mismatch
:
6614 err_msg
= _("number of operands mismatch");
6616 case invalid_instruction_suffix
:
6617 err_msg
= _("invalid instruction suffix");
6620 err_msg
= _("constant doesn't fit in 4 bits");
6622 case unsupported_with_intel_mnemonic
:
6623 err_msg
= _("unsupported with Intel mnemonic");
6625 case unsupported_syntax
:
6626 err_msg
= _("unsupported syntax");
6629 as_bad (_("unsupported instruction `%s'"),
6630 current_templates
->start
->name
);
6632 case invalid_sib_address
:
6633 err_msg
= _("invalid SIB address");
6635 case invalid_vsib_address
:
6636 err_msg
= _("invalid VSIB address");
6638 case invalid_vector_register_set
:
6639 err_msg
= _("mask, index, and destination registers must be distinct");
6641 case invalid_tmm_register_set
:
6642 err_msg
= _("all tmm registers must be distinct");
6644 case unsupported_vector_index_register
:
6645 err_msg
= _("unsupported vector index register");
6647 case unsupported_broadcast
:
6648 err_msg
= _("unsupported broadcast");
6650 case broadcast_needed
:
6651 err_msg
= _("broadcast is needed for operand of such type");
6653 case unsupported_masking
:
6654 err_msg
= _("unsupported masking");
6656 case mask_not_on_destination
:
6657 err_msg
= _("mask not on destination operand");
6659 case no_default_mask
:
6660 err_msg
= _("default mask isn't allowed");
6662 case unsupported_rc_sae
:
6663 err_msg
= _("unsupported static rounding/sae");
6665 case rc_sae_operand_not_last_imm
:
6667 err_msg
= _("RC/SAE operand must precede immediate operands");
6669 err_msg
= _("RC/SAE operand must follow immediate operands");
6671 case invalid_register_operand
:
6672 err_msg
= _("invalid register operand");
6675 as_bad (_("%s for `%s'"), err_msg
,
6676 current_templates
->start
->name
);
6680 if (!quiet_warnings
)
6683 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6684 as_warn (_("indirect %s without `*'"), t
->name
);
6686 if (t
->opcode_modifier
.isprefix
6687 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6689 /* Warn them that a data or address size prefix doesn't
6690 affect assembly of the next line of code. */
6691 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6695 /* Copy the template we found. */
6698 if (addr_prefix_disp
!= -1)
6699 i
.tm
.operand_types
[addr_prefix_disp
]
6700 = operand_types
[addr_prefix_disp
];
6702 if (found_reverse_match
)
6704 /* If we found a reverse match we must alter the opcode direction
6705 bit and clear/flip the regmem modifier one. found_reverse_match
6706 holds bits to change (different for int & float insns). */
6708 i
.tm
.base_opcode
^= found_reverse_match
;
6710 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6711 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6713 /* Certain SIMD insns have their load forms specified in the opcode
6714 table, and hence we need to _set_ RegMem instead of clearing it.
6715 We need to avoid setting the bit though on insns like KMOVW. */
6716 i
.tm
.opcode_modifier
.regmem
6717 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6718 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6719 && !i
.tm
.opcode_modifier
.regmem
;
6728 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6729 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6731 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6733 as_bad (_("`%s' operand %u must use `%ses' segment"),
6735 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6740 /* There's only ever one segment override allowed per instruction.
6741 This instruction possibly has a legal segment override on the
6742 second operand, so copy the segment to where non-string
6743 instructions store it, allowing common code. */
6744 i
.seg
[op
] = i
.seg
[1];
6750 process_suffix (void)
6752 /* If matched instruction specifies an explicit instruction mnemonic
6754 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6755 i
.suffix
= WORD_MNEM_SUFFIX
;
6756 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6757 i
.suffix
= LONG_MNEM_SUFFIX
;
6758 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6759 i
.suffix
= QWORD_MNEM_SUFFIX
;
6760 else if (i
.reg_operands
6761 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6762 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6764 unsigned int numop
= i
.operands
;
6766 /* movsx/movzx want only their source operand considered here, for the
6767 ambiguity checking below. The suffix will be replaced afterwards
6768 to represent the destination (register). */
6769 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6770 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6773 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6774 if (i
.tm
.base_opcode
== 0xf20f38f0
6775 && i
.tm
.operand_types
[1].bitfield
.qword
)
6778 /* If there's no instruction mnemonic suffix we try to invent one
6779 based on GPR operands. */
6782 /* We take i.suffix from the last register operand specified,
6783 Destination register type is more significant than source
6784 register type. crc32 in SSE4.2 prefers source register
6786 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6789 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6790 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6792 if (i
.types
[op
].bitfield
.class != Reg
)
6794 if (i
.types
[op
].bitfield
.byte
)
6795 i
.suffix
= BYTE_MNEM_SUFFIX
;
6796 else if (i
.types
[op
].bitfield
.word
)
6797 i
.suffix
= WORD_MNEM_SUFFIX
;
6798 else if (i
.types
[op
].bitfield
.dword
)
6799 i
.suffix
= LONG_MNEM_SUFFIX
;
6800 else if (i
.types
[op
].bitfield
.qword
)
6801 i
.suffix
= QWORD_MNEM_SUFFIX
;
6807 /* As an exception, movsx/movzx silently default to a byte source
6809 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6810 && !i
.suffix
&& !intel_syntax
)
6811 i
.suffix
= BYTE_MNEM_SUFFIX
;
6813 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6816 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6817 && i
.tm
.opcode_modifier
.no_bsuf
)
6819 else if (!check_byte_reg ())
6822 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6825 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6826 && i
.tm
.opcode_modifier
.no_lsuf
6827 && !i
.tm
.opcode_modifier
.todword
6828 && !i
.tm
.opcode_modifier
.toqword
)
6830 else if (!check_long_reg ())
6833 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6836 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6837 && i
.tm
.opcode_modifier
.no_qsuf
6838 && !i
.tm
.opcode_modifier
.todword
6839 && !i
.tm
.opcode_modifier
.toqword
)
6841 else if (!check_qword_reg ())
6844 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6847 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6848 && i
.tm
.opcode_modifier
.no_wsuf
)
6850 else if (!check_word_reg ())
6853 else if (intel_syntax
6854 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6855 /* Do nothing if the instruction is going to ignore the prefix. */
6860 /* Undo the movsx/movzx change done above. */
6863 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6866 i
.suffix
= stackop_size
;
6867 if (stackop_size
== LONG_MNEM_SUFFIX
)
6869 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6870 .code16gcc directive to support 16-bit mode with
6871 32-bit address. For IRET without a suffix, generate
6872 16-bit IRET (opcode 0xcf) to return from an interrupt
6874 if (i
.tm
.base_opcode
== 0xcf)
6876 i
.suffix
= WORD_MNEM_SUFFIX
;
6877 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6879 /* Warn about changed behavior for segment register push/pop. */
6880 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6881 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6886 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6887 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6888 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6889 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6890 && i
.tm
.extension_opcode
<= 3)))
6895 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6897 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6898 || i
.tm
.opcode_modifier
.no_lsuf
)
6899 i
.suffix
= QWORD_MNEM_SUFFIX
;
6904 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6905 i
.suffix
= LONG_MNEM_SUFFIX
;
6908 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6909 i
.suffix
= WORD_MNEM_SUFFIX
;
6915 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6916 /* Also cover lret/retf/iret in 64-bit mode. */
6917 || (flag_code
== CODE_64BIT
6918 && !i
.tm
.opcode_modifier
.no_lsuf
6919 && !i
.tm
.opcode_modifier
.no_qsuf
))
6920 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6921 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6922 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
6923 /* Accept FLDENV et al without suffix. */
6924 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6926 unsigned int suffixes
, evex
= 0;
6928 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6929 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6931 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6933 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6935 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6937 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6940 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6941 also suitable for AT&T syntax mode, it was requested that this be
6942 restricted to just Intel syntax. */
6943 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6947 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6949 if (is_evex_encoding (&i
.tm
)
6950 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6952 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6953 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6954 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6955 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6956 if (!i
.tm
.opcode_modifier
.evex
6957 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6958 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6961 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6962 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6963 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6966 /* Any properly sized operand disambiguates the insn. */
6967 if (i
.types
[op
].bitfield
.xmmword
6968 || i
.types
[op
].bitfield
.ymmword
6969 || i
.types
[op
].bitfield
.zmmword
)
6971 suffixes
&= ~(7 << 6);
6976 if ((i
.flags
[op
] & Operand_Mem
)
6977 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6979 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6981 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6983 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6985 if (is_evex_encoding (&i
.tm
))
6991 /* Are multiple suffixes / operand sizes allowed? */
6992 if (suffixes
& (suffixes
- 1))
6995 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6996 || operand_check
== check_error
))
6998 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
7001 if (operand_check
== check_error
)
7003 as_bad (_("no instruction mnemonic suffix given and "
7004 "no register operands; can't size `%s'"), i
.tm
.name
);
7007 if (operand_check
== check_warning
)
7008 as_warn (_("%s; using default for `%s'"),
7010 ? _("ambiguous operand size")
7011 : _("no instruction mnemonic suffix given and "
7012 "no register operands"),
7015 if (i
.tm
.opcode_modifier
.floatmf
)
7016 i
.suffix
= SHORT_MNEM_SUFFIX
;
7017 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
7018 || (i
.tm
.base_opcode
== 0x63
7019 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7020 /* handled below */;
7022 i
.tm
.opcode_modifier
.evex
= evex
;
7023 else if (flag_code
== CODE_16BIT
)
7024 i
.suffix
= WORD_MNEM_SUFFIX
;
7025 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7026 i
.suffix
= LONG_MNEM_SUFFIX
;
7028 i
.suffix
= QWORD_MNEM_SUFFIX
;
7032 if ((i
.tm
.base_opcode
| 8) == 0xfbe
7033 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7035 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7036 In AT&T syntax, if there is no suffix (warned about above), the default
7037 will be byte extension. */
7038 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7039 i
.tm
.base_opcode
|= 1;
7041 /* For further processing, the suffix should represent the destination
7042 (register). This is already the case when one was used with
7043 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7044 no suffix to begin with. */
7045 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7047 if (i
.types
[1].bitfield
.word
)
7048 i
.suffix
= WORD_MNEM_SUFFIX
;
7049 else if (i
.types
[1].bitfield
.qword
)
7050 i
.suffix
= QWORD_MNEM_SUFFIX
;
7052 i
.suffix
= LONG_MNEM_SUFFIX
;
7054 i
.tm
.opcode_modifier
.w
= 0;
7058 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7059 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7060 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7062 /* Change the opcode based on the operand size given by i.suffix. */
7065 /* Size floating point instruction. */
7066 case LONG_MNEM_SUFFIX
:
7067 if (i
.tm
.opcode_modifier
.floatmf
)
7069 i
.tm
.base_opcode
^= 4;
7073 case WORD_MNEM_SUFFIX
:
7074 case QWORD_MNEM_SUFFIX
:
7075 /* It's not a byte, select word/dword operation. */
7076 if (i
.tm
.opcode_modifier
.w
)
7079 i
.tm
.base_opcode
|= 8;
7081 i
.tm
.base_opcode
|= 1;
7084 case SHORT_MNEM_SUFFIX
:
7085 /* Now select between word & dword operations via the operand
7086 size prefix, except for instructions that will ignore this
7088 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7089 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7090 && !i
.tm
.opcode_modifier
.floatmf
7091 && !is_any_vex_encoding (&i
.tm
)
7092 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7093 || (flag_code
== CODE_64BIT
7094 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7096 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7098 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7099 prefix
= ADDR_PREFIX_OPCODE
;
7101 if (!add_prefix (prefix
))
7105 /* Set mode64 for an operand. */
7106 if (i
.suffix
== QWORD_MNEM_SUFFIX
7107 && flag_code
== CODE_64BIT
7108 && !i
.tm
.opcode_modifier
.norex64
7109 && !i
.tm
.opcode_modifier
.vexw
7110 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7112 && ! (i
.operands
== 2
7113 && i
.tm
.base_opcode
== 0x90
7114 && i
.tm
.extension_opcode
== None
7115 && i
.types
[0].bitfield
.instance
== Accum
7116 && i
.types
[0].bitfield
.qword
7117 && i
.types
[1].bitfield
.instance
== Accum
7118 && i
.types
[1].bitfield
.qword
))
7124 /* Select word/dword/qword operation with explict data sizing prefix
7125 when there are no suitable register operands. */
7126 if (i
.tm
.opcode_modifier
.w
7127 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7129 || (i
.reg_operands
== 1
7131 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7133 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7134 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7136 || i
.tm
.base_opcode
== 0xf20f38f0))))
7137 i
.tm
.base_opcode
|= 1;
7141 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7143 gas_assert (!i
.suffix
);
7144 gas_assert (i
.reg_operands
);
7146 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7149 /* The address size override prefix changes the size of the
7151 if (flag_code
== CODE_64BIT
7152 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7154 as_bad (_("16-bit addressing unavailable for `%s'"),
7159 if ((flag_code
== CODE_32BIT
7160 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7161 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7162 && !add_prefix (ADDR_PREFIX_OPCODE
))
7167 /* Check invalid register operand when the address size override
7168 prefix changes the size of register operands. */
7170 enum { need_word
, need_dword
, need_qword
} need
;
7172 if (flag_code
== CODE_32BIT
)
7173 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7174 else if (i
.prefix
[ADDR_PREFIX
])
7177 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7179 for (op
= 0; op
< i
.operands
; op
++)
7181 if (i
.types
[op
].bitfield
.class != Reg
)
7187 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7191 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7195 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7200 as_bad (_("invalid register operand size for `%s'"),
7211 check_byte_reg (void)
7215 for (op
= i
.operands
; --op
>= 0;)
7217 /* Skip non-register operands. */
7218 if (i
.types
[op
].bitfield
.class != Reg
)
7221 /* If this is an eight bit register, it's OK. If it's the 16 or
7222 32 bit version of an eight bit register, we will just use the
7223 low portion, and that's OK too. */
7224 if (i
.types
[op
].bitfield
.byte
)
7227 /* I/O port address operands are OK too. */
7228 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7229 && i
.tm
.operand_types
[op
].bitfield
.word
)
7232 /* crc32 only wants its source operand checked here. */
7233 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
7236 /* Any other register is bad. */
7237 as_bad (_("`%s%s' not allowed with `%s%c'"),
7238 register_prefix
, i
.op
[op
].regs
->reg_name
,
7239 i
.tm
.name
, i
.suffix
);
7246 check_long_reg (void)
7250 for (op
= i
.operands
; --op
>= 0;)
7251 /* Skip non-register operands. */
7252 if (i
.types
[op
].bitfield
.class != Reg
)
7254 /* Reject eight bit registers, except where the template requires
7255 them. (eg. movzb) */
7256 else if (i
.types
[op
].bitfield
.byte
7257 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7258 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7259 && (i
.tm
.operand_types
[op
].bitfield
.word
7260 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7262 as_bad (_("`%s%s' not allowed with `%s%c'"),
7264 i
.op
[op
].regs
->reg_name
,
7269 /* Error if the e prefix on a general reg is missing. */
7270 else if (i
.types
[op
].bitfield
.word
7271 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7272 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7273 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7275 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7276 register_prefix
, i
.op
[op
].regs
->reg_name
,
7280 /* Warn if the r prefix on a general reg is present. */
7281 else if (i
.types
[op
].bitfield
.qword
7282 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7283 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7284 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7287 && i
.tm
.opcode_modifier
.toqword
7288 && i
.types
[0].bitfield
.class != RegSIMD
)
7290 /* Convert to QWORD. We want REX byte. */
7291 i
.suffix
= QWORD_MNEM_SUFFIX
;
7295 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7296 register_prefix
, i
.op
[op
].regs
->reg_name
,
7305 check_qword_reg (void)
7309 for (op
= i
.operands
; --op
>= 0; )
7310 /* Skip non-register operands. */
7311 if (i
.types
[op
].bitfield
.class != Reg
)
7313 /* Reject eight bit registers, except where the template requires
7314 them. (eg. movzb) */
7315 else if (i
.types
[op
].bitfield
.byte
7316 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7317 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7318 && (i
.tm
.operand_types
[op
].bitfield
.word
7319 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7321 as_bad (_("`%s%s' not allowed with `%s%c'"),
7323 i
.op
[op
].regs
->reg_name
,
7328 /* Warn if the r prefix on a general reg is missing. */
7329 else if ((i
.types
[op
].bitfield
.word
7330 || i
.types
[op
].bitfield
.dword
)
7331 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7332 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7333 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7335 /* Prohibit these changes in the 64bit mode, since the
7336 lowering is more complicated. */
7338 && i
.tm
.opcode_modifier
.todword
7339 && i
.types
[0].bitfield
.class != RegSIMD
)
7341 /* Convert to DWORD. We don't want REX byte. */
7342 i
.suffix
= LONG_MNEM_SUFFIX
;
7346 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7347 register_prefix
, i
.op
[op
].regs
->reg_name
,
7356 check_word_reg (void)
7359 for (op
= i
.operands
; --op
>= 0;)
7360 /* Skip non-register operands. */
7361 if (i
.types
[op
].bitfield
.class != Reg
)
7363 /* Reject eight bit registers, except where the template requires
7364 them. (eg. movzb) */
7365 else if (i
.types
[op
].bitfield
.byte
7366 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7367 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7368 && (i
.tm
.operand_types
[op
].bitfield
.word
7369 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7371 as_bad (_("`%s%s' not allowed with `%s%c'"),
7373 i
.op
[op
].regs
->reg_name
,
7378 /* Error if the e or r prefix on a general reg is present. */
7379 else if ((i
.types
[op
].bitfield
.dword
7380 || i
.types
[op
].bitfield
.qword
)
7381 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7382 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7383 && i
.tm
.operand_types
[op
].bitfield
.word
)
7385 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7386 register_prefix
, i
.op
[op
].regs
->reg_name
,
7394 update_imm (unsigned int j
)
7396 i386_operand_type overlap
= i
.types
[j
];
7397 if ((overlap
.bitfield
.imm8
7398 || overlap
.bitfield
.imm8s
7399 || overlap
.bitfield
.imm16
7400 || overlap
.bitfield
.imm32
7401 || overlap
.bitfield
.imm32s
7402 || overlap
.bitfield
.imm64
)
7403 && !operand_type_equal (&overlap
, &imm8
)
7404 && !operand_type_equal (&overlap
, &imm8s
)
7405 && !operand_type_equal (&overlap
, &imm16
)
7406 && !operand_type_equal (&overlap
, &imm32
)
7407 && !operand_type_equal (&overlap
, &imm32s
)
7408 && !operand_type_equal (&overlap
, &imm64
))
7412 i386_operand_type temp
;
7414 operand_type_set (&temp
, 0);
7415 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7417 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7418 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7420 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7421 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7422 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7424 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7425 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7428 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7431 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7432 || operand_type_equal (&overlap
, &imm16_32
)
7433 || operand_type_equal (&overlap
, &imm16_32s
))
7435 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7440 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7441 overlap
= operand_type_and (overlap
, imm32s
);
7442 else if (i
.prefix
[DATA_PREFIX
])
7443 overlap
= operand_type_and (overlap
,
7444 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7445 if (!operand_type_equal (&overlap
, &imm8
)
7446 && !operand_type_equal (&overlap
, &imm8s
)
7447 && !operand_type_equal (&overlap
, &imm16
)
7448 && !operand_type_equal (&overlap
, &imm32
)
7449 && !operand_type_equal (&overlap
, &imm32s
)
7450 && !operand_type_equal (&overlap
, &imm64
))
7452 as_bad (_("no instruction mnemonic suffix given; "
7453 "can't determine immediate size"));
7457 i
.types
[j
] = overlap
;
7467 /* Update the first 2 immediate operands. */
7468 n
= i
.operands
> 2 ? 2 : i
.operands
;
7471 for (j
= 0; j
< n
; j
++)
7472 if (update_imm (j
) == 0)
7475 /* The 3rd operand can't be immediate operand. */
7476 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7483 process_operands (void)
7485 /* Default segment register this instruction will use for memory
7486 accesses. 0 means unknown. This is only for optimizing out
7487 unnecessary segment overrides. */
7488 const seg_entry
*default_seg
= 0;
7490 if (i
.tm
.opcode_modifier
.sse2avx
)
7492 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7494 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7495 i
.prefix
[REX_PREFIX
] = 0;
7498 /* ImmExt should be processed after SSE2AVX. */
7499 else if (i
.tm
.opcode_modifier
.immext
)
7502 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7504 unsigned int dupl
= i
.operands
;
7505 unsigned int dest
= dupl
- 1;
7508 /* The destination must be an xmm register. */
7509 gas_assert (i
.reg_operands
7510 && MAX_OPERANDS
> dupl
7511 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7513 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7514 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7516 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7518 /* Keep xmm0 for instructions with VEX prefix and 3
7520 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7521 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7526 /* We remove the first xmm0 and keep the number of
7527 operands unchanged, which in fact duplicates the
7529 for (j
= 1; j
< i
.operands
; j
++)
7531 i
.op
[j
- 1] = i
.op
[j
];
7532 i
.types
[j
- 1] = i
.types
[j
];
7533 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7534 i
.flags
[j
- 1] = i
.flags
[j
];
7538 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7540 gas_assert ((MAX_OPERANDS
- 1) > dupl
7541 && (i
.tm
.opcode_modifier
.vexsources
7544 /* Add the implicit xmm0 for instructions with VEX prefix
7546 for (j
= i
.operands
; j
> 0; j
--)
7548 i
.op
[j
] = i
.op
[j
- 1];
7549 i
.types
[j
] = i
.types
[j
- 1];
7550 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7551 i
.flags
[j
] = i
.flags
[j
- 1];
7554 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7555 i
.types
[0] = regxmm
;
7556 i
.tm
.operand_types
[0] = regxmm
;
7559 i
.reg_operands
+= 2;
7564 i
.op
[dupl
] = i
.op
[dest
];
7565 i
.types
[dupl
] = i
.types
[dest
];
7566 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7567 i
.flags
[dupl
] = i
.flags
[dest
];
7576 i
.op
[dupl
] = i
.op
[dest
];
7577 i
.types
[dupl
] = i
.types
[dest
];
7578 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7579 i
.flags
[dupl
] = i
.flags
[dest
];
7582 if (i
.tm
.opcode_modifier
.immext
)
7585 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7586 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7590 for (j
= 1; j
< i
.operands
; j
++)
7592 i
.op
[j
- 1] = i
.op
[j
];
7593 i
.types
[j
- 1] = i
.types
[j
];
7595 /* We need to adjust fields in i.tm since they are used by
7596 build_modrm_byte. */
7597 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7599 i
.flags
[j
- 1] = i
.flags
[j
];
7606 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7608 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7610 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7611 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7612 regnum
= register_number (i
.op
[1].regs
);
7613 first_reg_in_group
= regnum
& ~3;
7614 last_reg_in_group
= first_reg_in_group
+ 3;
7615 if (regnum
!= first_reg_in_group
)
7616 as_warn (_("source register `%s%s' implicitly denotes"
7617 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7618 register_prefix
, i
.op
[1].regs
->reg_name
,
7619 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7620 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7623 else if (i
.tm
.opcode_modifier
.regkludge
)
7625 /* The imul $imm, %reg instruction is converted into
7626 imul $imm, %reg, %reg, and the clr %reg instruction
7627 is converted into xor %reg, %reg. */
7629 unsigned int first_reg_op
;
7631 if (operand_type_check (i
.types
[0], reg
))
7635 /* Pretend we saw the extra register operand. */
7636 gas_assert (i
.reg_operands
== 1
7637 && i
.op
[first_reg_op
+ 1].regs
== 0);
7638 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7639 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7644 if (i
.tm
.opcode_modifier
.modrm
)
7646 /* The opcode is completed (modulo i.tm.extension_opcode which
7647 must be put into the modrm byte). Now, we make the modrm and
7648 index base bytes based on all the info we've collected. */
7650 default_seg
= build_modrm_byte ();
7652 else if (i
.types
[0].bitfield
.class == SReg
)
7654 if (flag_code
!= CODE_64BIT
7655 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7656 && i
.op
[0].regs
->reg_num
== 1
7657 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7658 && i
.op
[0].regs
->reg_num
< 4)
7660 as_bad (_("you can't `%s %s%s'"),
7661 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7664 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7666 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7667 i
.tm
.opcode_length
= 2;
7669 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7671 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7675 else if (i
.tm
.opcode_modifier
.isstring
)
7677 /* For the string instructions that allow a segment override
7678 on one of their operands, the default segment is ds. */
7681 else if (i
.short_form
)
7683 /* The register or float register operand is in operand
7685 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7687 /* Register goes in low 3 bits of opcode. */
7688 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7689 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7691 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7693 /* Warn about some common errors, but press on regardless.
7694 The first case can be generated by gcc (<= 2.8.1). */
7695 if (i
.operands
== 2)
7697 /* Reversed arguments on faddp, fsubp, etc. */
7698 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7699 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7700 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7704 /* Extraneous `l' suffix on fp insn. */
7705 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7706 register_prefix
, i
.op
[0].regs
->reg_name
);
7711 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7712 && i
.tm
.base_opcode
== 0x8d /* lea */
7713 && !is_any_vex_encoding(&i
.tm
))
7715 if (!quiet_warnings
)
7716 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7720 i
.prefix
[SEG_PREFIX
] = 0;
7724 /* If a segment was explicitly specified, and the specified segment
7725 is neither the default nor the one already recorded from a prefix,
7726 use an opcode prefix to select it. If we never figured out what
7727 the default segment is, then default_seg will be zero at this
7728 point, and the specified segment prefix will always be used. */
7730 && i
.seg
[0] != default_seg
7731 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7733 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7739 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7740 bfd_boolean do_sse2avx
)
7742 if (r
->reg_flags
& RegRex
)
7744 if (i
.rex
& rex_bit
)
7745 as_bad (_("same type of prefix used twice"));
7748 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7750 gas_assert (i
.vex
.register_specifier
== r
);
7751 i
.vex
.register_specifier
+= 8;
7754 if (r
->reg_flags
& RegVRex
)
7758 static const seg_entry
*
7759 build_modrm_byte (void)
7761 const seg_entry
*default_seg
= 0;
7762 unsigned int source
, dest
;
7765 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7768 unsigned int nds
, reg_slot
;
7771 dest
= i
.operands
- 1;
7774 /* There are 2 kinds of instructions:
7775 1. 5 operands: 4 register operands or 3 register operands
7776 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7777 VexW0 or VexW1. The destination must be either XMM, YMM or
7779 2. 4 operands: 4 register operands or 3 register operands
7780 plus 1 memory operand, with VexXDS. */
7781 gas_assert ((i
.reg_operands
== 4
7782 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7783 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7784 && i
.tm
.opcode_modifier
.vexw
7785 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7787 /* If VexW1 is set, the first non-immediate operand is the source and
7788 the second non-immediate one is encoded in the immediate operand. */
7789 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7791 source
= i
.imm_operands
;
7792 reg_slot
= i
.imm_operands
+ 1;
7796 source
= i
.imm_operands
+ 1;
7797 reg_slot
= i
.imm_operands
;
7800 if (i
.imm_operands
== 0)
7802 /* When there is no immediate operand, generate an 8bit
7803 immediate operand to encode the first operand. */
7804 exp
= &im_expressions
[i
.imm_operands
++];
7805 i
.op
[i
.operands
].imms
= exp
;
7806 i
.types
[i
.operands
] = imm8
;
7809 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7810 exp
->X_op
= O_constant
;
7811 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7812 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7816 gas_assert (i
.imm_operands
== 1);
7817 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7818 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7820 /* Turn on Imm8 again so that output_imm will generate it. */
7821 i
.types
[0].bitfield
.imm8
= 1;
7823 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7824 i
.op
[0].imms
->X_add_number
7825 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7826 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7829 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7830 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7835 /* i.reg_operands MUST be the number of real register operands;
7836 implicit registers do not count. If there are 3 register
7837 operands, it must be a instruction with VexNDS. For a
7838 instruction with VexNDD, the destination register is encoded
7839 in VEX prefix. If there are 4 register operands, it must be
7840 a instruction with VEX prefix and 3 sources. */
7841 if (i
.mem_operands
== 0
7842 && ((i
.reg_operands
== 2
7843 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7844 || (i
.reg_operands
== 3
7845 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7846 || (i
.reg_operands
== 4 && vex_3_sources
)))
7854 /* When there are 3 operands, one of them may be immediate,
7855 which may be the first or the last operand. Otherwise,
7856 the first operand must be shift count register (cl) or it
7857 is an instruction with VexNDS. */
7858 gas_assert (i
.imm_operands
== 1
7859 || (i
.imm_operands
== 0
7860 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7861 || (i
.types
[0].bitfield
.instance
== RegC
7862 && i
.types
[0].bitfield
.byte
))));
7863 if (operand_type_check (i
.types
[0], imm
)
7864 || (i
.types
[0].bitfield
.instance
== RegC
7865 && i
.types
[0].bitfield
.byte
))
7871 /* When there are 4 operands, the first two must be 8bit
7872 immediate operands. The source operand will be the 3rd
7875 For instructions with VexNDS, if the first operand
7876 an imm8, the source operand is the 2nd one. If the last
7877 operand is imm8, the source operand is the first one. */
7878 gas_assert ((i
.imm_operands
== 2
7879 && i
.types
[0].bitfield
.imm8
7880 && i
.types
[1].bitfield
.imm8
)
7881 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7882 && i
.imm_operands
== 1
7883 && (i
.types
[0].bitfield
.imm8
7884 || i
.types
[i
.operands
- 1].bitfield
.imm8
7886 if (i
.imm_operands
== 2)
7890 if (i
.types
[0].bitfield
.imm8
)
7897 if (is_evex_encoding (&i
.tm
))
7899 /* For EVEX instructions, when there are 5 operands, the
7900 first one must be immediate operand. If the second one
7901 is immediate operand, the source operand is the 3th
7902 one. If the last one is immediate operand, the source
7903 operand is the 2nd one. */
7904 gas_assert (i
.imm_operands
== 2
7905 && i
.tm
.opcode_modifier
.sae
7906 && operand_type_check (i
.types
[0], imm
));
7907 if (operand_type_check (i
.types
[1], imm
))
7909 else if (operand_type_check (i
.types
[4], imm
))
7923 /* RC/SAE operand could be between DEST and SRC. That happens
7924 when one operand is GPR and the other one is XMM/YMM/ZMM
7926 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7929 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7931 /* For instructions with VexNDS, the register-only source
7932 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7933 register. It is encoded in VEX prefix. */
7935 i386_operand_type op
;
7938 /* Swap two source operands if needed. */
7939 if (i
.tm
.opcode_modifier
.swapsources
)
7947 op
= i
.tm
.operand_types
[vvvv
];
7948 if ((dest
+ 1) >= i
.operands
7949 || ((op
.bitfield
.class != Reg
7950 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7951 && op
.bitfield
.class != RegSIMD
7952 && !operand_type_equal (&op
, ®mask
)))
7954 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7960 /* One of the register operands will be encoded in the i.rm.reg
7961 field, the other in the combined i.rm.mode and i.rm.regmem
7962 fields. If no form of this instruction supports a memory
7963 destination operand, then we assume the source operand may
7964 sometimes be a memory operand and so we need to store the
7965 destination in the i.rm.reg field. */
7966 if (!i
.tm
.opcode_modifier
.regmem
7967 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7969 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7970 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7971 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
7972 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
7976 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7977 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7978 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
7979 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
7981 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7983 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7986 add_prefix (LOCK_PREFIX_OPCODE
);
7990 { /* If it's not 2 reg operands... */
7995 unsigned int fake_zero_displacement
= 0;
7998 for (op
= 0; op
< i
.operands
; op
++)
7999 if (i
.flags
[op
] & Operand_Mem
)
8001 gas_assert (op
< i
.operands
);
8003 if (i
.tm
.opcode_modifier
.sib
)
8005 /* The index register of VSIB shouldn't be RegIZ. */
8006 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8007 && i
.index_reg
->reg_num
== RegIZ
)
8010 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8013 i
.sib
.base
= NO_BASE_REGISTER
;
8014 i
.sib
.scale
= i
.log2_scale_factor
;
8015 i
.types
[op
].bitfield
.disp8
= 0;
8016 i
.types
[op
].bitfield
.disp16
= 0;
8017 i
.types
[op
].bitfield
.disp64
= 0;
8018 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8020 /* Must be 32 bit */
8021 i
.types
[op
].bitfield
.disp32
= 1;
8022 i
.types
[op
].bitfield
.disp32s
= 0;
8026 i
.types
[op
].bitfield
.disp32
= 0;
8027 i
.types
[op
].bitfield
.disp32s
= 1;
8031 /* Since the mandatory SIB always has index register, so
8032 the code logic remains unchanged. The non-mandatory SIB
8033 without index register is allowed and will be handled
8037 if (i
.index_reg
->reg_num
== RegIZ
)
8038 i
.sib
.index
= NO_INDEX_REGISTER
;
8040 i
.sib
.index
= i
.index_reg
->reg_num
;
8041 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
8047 if (i
.base_reg
== 0)
8050 if (!i
.disp_operands
)
8051 fake_zero_displacement
= 1;
8052 if (i
.index_reg
== 0)
8054 i386_operand_type newdisp
;
8056 /* Both check for VSIB and mandatory non-vector SIB. */
8057 gas_assert (!i
.tm
.opcode_modifier
.sib
8058 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8059 /* Operand is just <disp> */
8060 if (flag_code
== CODE_64BIT
)
8062 /* 64bit mode overwrites the 32bit absolute
8063 addressing by RIP relative addressing and
8064 absolute addressing is encoded by one of the
8065 redundant SIB forms. */
8066 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8067 i
.sib
.base
= NO_BASE_REGISTER
;
8068 i
.sib
.index
= NO_INDEX_REGISTER
;
8069 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
8071 else if ((flag_code
== CODE_16BIT
)
8072 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8074 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8079 i
.rm
.regmem
= NO_BASE_REGISTER
;
8082 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8083 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8085 else if (!i
.tm
.opcode_modifier
.sib
)
8087 /* !i.base_reg && i.index_reg */
8088 if (i
.index_reg
->reg_num
== RegIZ
)
8089 i
.sib
.index
= NO_INDEX_REGISTER
;
8091 i
.sib
.index
= i
.index_reg
->reg_num
;
8092 i
.sib
.base
= NO_BASE_REGISTER
;
8093 i
.sib
.scale
= i
.log2_scale_factor
;
8094 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8095 i
.types
[op
].bitfield
.disp8
= 0;
8096 i
.types
[op
].bitfield
.disp16
= 0;
8097 i
.types
[op
].bitfield
.disp64
= 0;
8098 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8100 /* Must be 32 bit */
8101 i
.types
[op
].bitfield
.disp32
= 1;
8102 i
.types
[op
].bitfield
.disp32s
= 0;
8106 i
.types
[op
].bitfield
.disp32
= 0;
8107 i
.types
[op
].bitfield
.disp32s
= 1;
8109 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8113 /* RIP addressing for 64bit mode. */
8114 else if (i
.base_reg
->reg_num
== RegIP
)
8116 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8117 i
.rm
.regmem
= NO_BASE_REGISTER
;
8118 i
.types
[op
].bitfield
.disp8
= 0;
8119 i
.types
[op
].bitfield
.disp16
= 0;
8120 i
.types
[op
].bitfield
.disp32
= 0;
8121 i
.types
[op
].bitfield
.disp32s
= 1;
8122 i
.types
[op
].bitfield
.disp64
= 0;
8123 i
.flags
[op
] |= Operand_PCrel
;
8124 if (! i
.disp_operands
)
8125 fake_zero_displacement
= 1;
8127 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8129 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8130 switch (i
.base_reg
->reg_num
)
8133 if (i
.index_reg
== 0)
8135 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8136 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8140 if (i
.index_reg
== 0)
8143 if (operand_type_check (i
.types
[op
], disp
) == 0)
8145 /* fake (%bp) into 0(%bp) */
8146 if (i
.disp_encoding
== disp_encoding_16bit
)
8147 i
.types
[op
].bitfield
.disp16
= 1;
8149 i
.types
[op
].bitfield
.disp8
= 1;
8150 fake_zero_displacement
= 1;
8153 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8154 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8156 default: /* (%si) -> 4 or (%di) -> 5 */
8157 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8159 if (!fake_zero_displacement
8163 fake_zero_displacement
= 1;
8164 if (i
.disp_encoding
== disp_encoding_8bit
)
8165 i
.types
[op
].bitfield
.disp8
= 1;
8167 i
.types
[op
].bitfield
.disp16
= 1;
8169 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8171 else /* i.base_reg and 32/64 bit mode */
8173 if (flag_code
== CODE_64BIT
8174 && operand_type_check (i
.types
[op
], disp
))
8176 i
.types
[op
].bitfield
.disp16
= 0;
8177 i
.types
[op
].bitfield
.disp64
= 0;
8178 if (i
.prefix
[ADDR_PREFIX
] == 0)
8180 i
.types
[op
].bitfield
.disp32
= 0;
8181 i
.types
[op
].bitfield
.disp32s
= 1;
8185 i
.types
[op
].bitfield
.disp32
= 1;
8186 i
.types
[op
].bitfield
.disp32s
= 0;
8190 if (!i
.tm
.opcode_modifier
.sib
)
8191 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8192 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8194 i
.sib
.base
= i
.base_reg
->reg_num
;
8195 /* x86-64 ignores REX prefix bit here to avoid decoder
8197 if (!(i
.base_reg
->reg_flags
& RegRex
)
8198 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8199 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8201 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8203 fake_zero_displacement
= 1;
8204 if (i
.disp_encoding
== disp_encoding_32bit
)
8205 i
.types
[op
].bitfield
.disp32
= 1;
8207 i
.types
[op
].bitfield
.disp8
= 1;
8209 i
.sib
.scale
= i
.log2_scale_factor
;
8210 if (i
.index_reg
== 0)
8212 /* Only check for VSIB. */
8213 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8214 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8215 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8217 /* <disp>(%esp) becomes two byte modrm with no index
8218 register. We've already stored the code for esp
8219 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8220 Any base register besides %esp will not use the
8221 extra modrm byte. */
8222 i
.sib
.index
= NO_INDEX_REGISTER
;
8224 else if (!i
.tm
.opcode_modifier
.sib
)
8226 if (i
.index_reg
->reg_num
== RegIZ
)
8227 i
.sib
.index
= NO_INDEX_REGISTER
;
8229 i
.sib
.index
= i
.index_reg
->reg_num
;
8230 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8231 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8236 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8237 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8241 if (!fake_zero_displacement
8245 fake_zero_displacement
= 1;
8246 if (i
.disp_encoding
== disp_encoding_8bit
)
8247 i
.types
[op
].bitfield
.disp8
= 1;
8249 i
.types
[op
].bitfield
.disp32
= 1;
8251 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8255 if (fake_zero_displacement
)
8257 /* Fakes a zero displacement assuming that i.types[op]
8258 holds the correct displacement size. */
8261 gas_assert (i
.op
[op
].disps
== 0);
8262 exp
= &disp_expressions
[i
.disp_operands
++];
8263 i
.op
[op
].disps
= exp
;
8264 exp
->X_op
= O_constant
;
8265 exp
->X_add_number
= 0;
8266 exp
->X_add_symbol
= (symbolS
*) 0;
8267 exp
->X_op_symbol
= (symbolS
*) 0;
8275 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8277 if (operand_type_check (i
.types
[0], imm
))
8278 i
.vex
.register_specifier
= NULL
;
8281 /* VEX.vvvv encodes one of the sources when the first
8282 operand is not an immediate. */
8283 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8284 i
.vex
.register_specifier
= i
.op
[0].regs
;
8286 i
.vex
.register_specifier
= i
.op
[1].regs
;
8289 /* Destination is a XMM register encoded in the ModRM.reg
8291 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8292 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8295 /* ModRM.rm and VEX.B encodes the other source. */
8296 if (!i
.mem_operands
)
8300 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8301 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8303 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8305 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8309 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8311 i
.vex
.register_specifier
= i
.op
[2].regs
;
8312 if (!i
.mem_operands
)
8315 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8316 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8320 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8321 (if any) based on i.tm.extension_opcode. Again, we must be
8322 careful to make sure that segment/control/debug/test/MMX
8323 registers are coded into the i.rm.reg field. */
8324 else if (i
.reg_operands
)
8327 unsigned int vex_reg
= ~0;
8329 for (op
= 0; op
< i
.operands
; op
++)
8330 if (i
.types
[op
].bitfield
.class == Reg
8331 || i
.types
[op
].bitfield
.class == RegBND
8332 || i
.types
[op
].bitfield
.class == RegMask
8333 || i
.types
[op
].bitfield
.class == SReg
8334 || i
.types
[op
].bitfield
.class == RegCR
8335 || i
.types
[op
].bitfield
.class == RegDR
8336 || i
.types
[op
].bitfield
.class == RegTR
8337 || i
.types
[op
].bitfield
.class == RegSIMD
8338 || i
.types
[op
].bitfield
.class == RegMMX
)
8343 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8345 /* For instructions with VexNDS, the register-only
8346 source operand is encoded in VEX prefix. */
8347 gas_assert (mem
!= (unsigned int) ~0);
8352 gas_assert (op
< i
.operands
);
8356 /* Check register-only source operand when two source
8357 operands are swapped. */
8358 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8359 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8363 gas_assert (mem
== (vex_reg
+ 1)
8364 && op
< i
.operands
);
8369 gas_assert (vex_reg
< i
.operands
);
8373 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8375 /* For instructions with VexNDD, the register destination
8376 is encoded in VEX prefix. */
8377 if (i
.mem_operands
== 0)
8379 /* There is no memory operand. */
8380 gas_assert ((op
+ 2) == i
.operands
);
8385 /* There are only 2 non-immediate operands. */
8386 gas_assert (op
< i
.imm_operands
+ 2
8387 && i
.operands
== i
.imm_operands
+ 2);
8388 vex_reg
= i
.imm_operands
+ 1;
8392 gas_assert (op
< i
.operands
);
8394 if (vex_reg
!= (unsigned int) ~0)
8396 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8398 if ((type
->bitfield
.class != Reg
8399 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8400 && type
->bitfield
.class != RegSIMD
8401 && !operand_type_equal (type
, ®mask
))
8404 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8407 /* Don't set OP operand twice. */
8410 /* If there is an extension opcode to put here, the
8411 register number must be put into the regmem field. */
8412 if (i
.tm
.extension_opcode
!= None
)
8414 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8415 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8416 i
.tm
.opcode_modifier
.sse2avx
);
8420 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8421 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8422 i
.tm
.opcode_modifier
.sse2avx
);
8426 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8427 must set it to 3 to indicate this is a register operand
8428 in the regmem field. */
8429 if (!i
.mem_operands
)
8433 /* Fill in i.rm.reg field with extension opcode (if any). */
8434 if (i
.tm
.extension_opcode
!= None
)
8435 i
.rm
.reg
= i
.tm
.extension_opcode
;
8441 frag_opcode_byte (unsigned char byte
)
8443 if (now_seg
!= absolute_section
)
8444 FRAG_APPEND_1_CHAR (byte
);
8446 ++abs_section_offset
;
8450 flip_code16 (unsigned int code16
)
8452 gas_assert (i
.tm
.operands
== 1);
8454 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8455 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8456 || i
.tm
.operand_types
[0].bitfield
.disp32s
8457 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8462 output_branch (void)
8468 relax_substateT subtype
;
8472 if (now_seg
== absolute_section
)
8474 as_bad (_("relaxable branches not supported in absolute section"));
8478 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8479 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8482 if (i
.prefix
[DATA_PREFIX
] != 0)
8486 code16
^= flip_code16(code16
);
8488 /* Pentium4 branch hints. */
8489 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8490 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8495 if (i
.prefix
[REX_PREFIX
] != 0)
8501 /* BND prefixed jump. */
8502 if (i
.prefix
[BND_PREFIX
] != 0)
8508 if (i
.prefixes
!= 0)
8509 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8511 /* It's always a symbol; End frag & setup for relax.
8512 Make sure there is enough room in this frag for the largest
8513 instruction we may generate in md_convert_frag. This is 2
8514 bytes for the opcode and room for the prefix and largest
8516 frag_grow (prefix
+ 2 + 4);
8517 /* Prefix and 1 opcode byte go in fr_fix. */
8518 p
= frag_more (prefix
+ 1);
8519 if (i
.prefix
[DATA_PREFIX
] != 0)
8520 *p
++ = DATA_PREFIX_OPCODE
;
8521 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8522 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8523 *p
++ = i
.prefix
[SEG_PREFIX
];
8524 if (i
.prefix
[BND_PREFIX
] != 0)
8525 *p
++ = BND_PREFIX_OPCODE
;
8526 if (i
.prefix
[REX_PREFIX
] != 0)
8527 *p
++ = i
.prefix
[REX_PREFIX
];
8528 *p
= i
.tm
.base_opcode
;
8530 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8531 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8532 else if (cpu_arch_flags
.bitfield
.cpui386
)
8533 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8535 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8538 sym
= i
.op
[0].disps
->X_add_symbol
;
8539 off
= i
.op
[0].disps
->X_add_number
;
8541 if (i
.op
[0].disps
->X_op
!= O_constant
8542 && i
.op
[0].disps
->X_op
!= O_symbol
)
8544 /* Handle complex expressions. */
8545 sym
= make_expr_symbol (i
.op
[0].disps
);
8549 /* 1 possible extra opcode + 4 byte displacement go in var part.
8550 Pass reloc in fr_var. */
8551 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8554 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8555 /* Return TRUE iff PLT32 relocation should be used for branching to
8559 need_plt32_p (symbolS
*s
)
8561 /* PLT32 relocation is ELF only. */
8566 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8567 krtld support it. */
8571 /* Since there is no need to prepare for PLT branch on x86-64, we
8572 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8573 be used as a marker for 32-bit PC-relative branches. */
8577 /* Weak or undefined symbol need PLT32 relocation. */
8578 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8581 /* Non-global symbol doesn't need PLT32 relocation. */
8582 if (! S_IS_EXTERNAL (s
))
8585 /* Other global symbols need PLT32 relocation. NB: Symbol with
8586 non-default visibilities are treated as normal global symbol
8587 so that PLT32 relocation can be used as a marker for 32-bit
8588 PC-relative branches. It is useful for linker relaxation. */
8599 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8601 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8603 /* This is a loop or jecxz type instruction. */
8605 if (i
.prefix
[ADDR_PREFIX
] != 0)
8607 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8610 /* Pentium4 branch hints. */
8611 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8612 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8614 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8623 if (flag_code
== CODE_16BIT
)
8626 if (i
.prefix
[DATA_PREFIX
] != 0)
8628 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8630 code16
^= flip_code16(code16
);
8638 /* BND prefixed jump. */
8639 if (i
.prefix
[BND_PREFIX
] != 0)
8641 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8645 if (i
.prefix
[REX_PREFIX
] != 0)
8647 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8651 if (i
.prefixes
!= 0)
8652 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8654 if (now_seg
== absolute_section
)
8656 abs_section_offset
+= i
.tm
.opcode_length
+ size
;
8660 p
= frag_more (i
.tm
.opcode_length
+ size
);
8661 switch (i
.tm
.opcode_length
)
8664 *p
++ = i
.tm
.base_opcode
>> 8;
8667 *p
++ = i
.tm
.base_opcode
;
8673 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8675 && jump_reloc
== NO_RELOC
8676 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8677 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8680 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8682 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8683 i
.op
[0].disps
, 1, jump_reloc
);
8685 /* All jumps handled here are signed, but don't use a signed limit
8686 check for 32 and 16 bit jumps as we want to allow wrap around at
8687 4G and 64k respectively. */
8689 fixP
->fx_signed
= 1;
8693 output_interseg_jump (void)
8701 if (flag_code
== CODE_16BIT
)
8705 if (i
.prefix
[DATA_PREFIX
] != 0)
8712 gas_assert (!i
.prefix
[REX_PREFIX
]);
8718 if (i
.prefixes
!= 0)
8719 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8721 if (now_seg
== absolute_section
)
8723 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8727 /* 1 opcode; 2 segment; offset */
8728 p
= frag_more (prefix
+ 1 + 2 + size
);
8730 if (i
.prefix
[DATA_PREFIX
] != 0)
8731 *p
++ = DATA_PREFIX_OPCODE
;
8733 if (i
.prefix
[REX_PREFIX
] != 0)
8734 *p
++ = i
.prefix
[REX_PREFIX
];
8736 *p
++ = i
.tm
.base_opcode
;
8737 if (i
.op
[1].imms
->X_op
== O_constant
)
8739 offsetT n
= i
.op
[1].imms
->X_add_number
;
8742 && !fits_in_unsigned_word (n
)
8743 && !fits_in_signed_word (n
))
8745 as_bad (_("16-bit jump out of range"));
8748 md_number_to_chars (p
, n
, size
);
8751 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8752 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8753 if (i
.op
[0].imms
->X_op
!= O_constant
)
8754 as_bad (_("can't handle non absolute segment in `%s'"),
8756 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8759 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8764 asection
*seg
= now_seg
;
8765 subsegT subseg
= now_subseg
;
8767 unsigned int alignment
, align_size_1
;
8768 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8769 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8770 unsigned int padding
;
8772 if (!IS_ELF
|| !x86_used_note
)
8775 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8777 /* The .note.gnu.property section layout:
8779 Field Length Contents
8782 n_descsz 4 The note descriptor size
8783 n_type 4 NT_GNU_PROPERTY_TYPE_0
8785 n_desc n_descsz The program property array
8789 /* Create the .note.gnu.property section. */
8790 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8791 bfd_set_section_flags (sec
,
8798 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8809 bfd_set_section_alignment (sec
, alignment
);
8810 elf_section_type (sec
) = SHT_NOTE
;
8812 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8814 isa_1_descsz_raw
= 4 + 4 + 4;
8815 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8816 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8818 feature_2_descsz_raw
= isa_1_descsz
;
8819 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8821 feature_2_descsz_raw
+= 4 + 4 + 4;
8822 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8823 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8826 descsz
= feature_2_descsz
;
8827 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8828 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8830 /* Write n_namsz. */
8831 md_number_to_chars (p
, (valueT
) 4, 4);
8833 /* Write n_descsz. */
8834 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8837 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8840 memcpy (p
+ 4 * 3, "GNU", 4);
8842 /* Write 4-byte type. */
8843 md_number_to_chars (p
+ 4 * 4,
8844 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8846 /* Write 4-byte data size. */
8847 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8849 /* Write 4-byte data. */
8850 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8852 /* Zero out paddings. */
8853 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8855 memset (p
+ 4 * 7, 0, padding
);
8857 /* Write 4-byte type. */
8858 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8859 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8861 /* Write 4-byte data size. */
8862 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8864 /* Write 4-byte data. */
8865 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8866 (valueT
) x86_feature_2_used
, 4);
8868 /* Zero out paddings. */
8869 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8871 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8873 /* We probably can't restore the current segment, for there likely
8876 subseg_set (seg
, subseg
);
8881 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8882 const char *frag_now_ptr
)
8884 unsigned int len
= 0;
8886 if (start_frag
!= frag_now
)
8888 const fragS
*fr
= start_frag
;
8893 } while (fr
&& fr
!= frag_now
);
8896 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8899 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8900 be macro-fused with conditional jumps.
8901 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8902 or is one of the following format:
8915 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8917 /* No RIP address. */
8918 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8921 /* No VEX/EVEX encoding. */
8922 if (is_any_vex_encoding (&i
.tm
))
8925 /* add, sub without add/sub m, imm. */
8926 if (i
.tm
.base_opcode
<= 5
8927 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8928 || ((i
.tm
.base_opcode
| 3) == 0x83
8929 && (i
.tm
.extension_opcode
== 0x5
8930 || i
.tm
.extension_opcode
== 0x0)))
8932 *mf_cmp_p
= mf_cmp_alu_cmp
;
8933 return !(i
.mem_operands
&& i
.imm_operands
);
8936 /* and without and m, imm. */
8937 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8938 || ((i
.tm
.base_opcode
| 3) == 0x83
8939 && i
.tm
.extension_opcode
== 0x4))
8941 *mf_cmp_p
= mf_cmp_test_and
;
8942 return !(i
.mem_operands
&& i
.imm_operands
);
8945 /* test without test m imm. */
8946 if ((i
.tm
.base_opcode
| 1) == 0x85
8947 || (i
.tm
.base_opcode
| 1) == 0xa9
8948 || ((i
.tm
.base_opcode
| 1) == 0xf7
8949 && i
.tm
.extension_opcode
== 0))
8951 *mf_cmp_p
= mf_cmp_test_and
;
8952 return !(i
.mem_operands
&& i
.imm_operands
);
8955 /* cmp without cmp m, imm. */
8956 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8957 || ((i
.tm
.base_opcode
| 3) == 0x83
8958 && (i
.tm
.extension_opcode
== 0x7)))
8960 *mf_cmp_p
= mf_cmp_alu_cmp
;
8961 return !(i
.mem_operands
&& i
.imm_operands
);
8964 /* inc, dec without inc/dec m. */
8965 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8966 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8967 || ((i
.tm
.base_opcode
| 1) == 0xff
8968 && i
.tm
.extension_opcode
<= 0x1))
8970 *mf_cmp_p
= mf_cmp_incdec
;
8971 return !i
.mem_operands
;
8977 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8980 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8982 /* NB: Don't work with COND_JUMP86 without i386. */
8983 if (!align_branch_power
8984 || now_seg
== absolute_section
8985 || !cpu_arch_flags
.bitfield
.cpui386
8986 || !(align_branch
& align_branch_fused_bit
))
8989 if (maybe_fused_with_jcc_p (mf_cmp_p
))
8991 if (last_insn
.kind
== last_insn_other
8992 || last_insn
.seg
!= now_seg
)
8995 as_warn_where (last_insn
.file
, last_insn
.line
,
8996 _("`%s` skips -malign-branch-boundary on `%s`"),
8997 last_insn
.name
, i
.tm
.name
);
9003 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9006 add_branch_prefix_frag_p (void)
9008 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9009 to PadLock instructions since they include prefixes in opcode. */
9010 if (!align_branch_power
9011 || !align_branch_prefix_size
9012 || now_seg
== absolute_section
9013 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9014 || !cpu_arch_flags
.bitfield
.cpui386
)
9017 /* Don't add prefix if it is a prefix or there is no operand in case
9018 that segment prefix is special. */
9019 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9022 if (last_insn
.kind
== last_insn_other
9023 || last_insn
.seg
!= now_seg
)
9027 as_warn_where (last_insn
.file
, last_insn
.line
,
9028 _("`%s` skips -malign-branch-boundary on `%s`"),
9029 last_insn
.name
, i
.tm
.name
);
9034 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9037 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9038 enum mf_jcc_kind
*mf_jcc_p
)
9042 /* NB: Don't work with COND_JUMP86 without i386. */
9043 if (!align_branch_power
9044 || now_seg
== absolute_section
9045 || !cpu_arch_flags
.bitfield
.cpui386
)
9050 /* Check for jcc and direct jmp. */
9051 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9053 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9055 *branch_p
= align_branch_jmp
;
9056 add_padding
= align_branch
& align_branch_jmp_bit
;
9060 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9061 igore the lowest bit. */
9062 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9063 *branch_p
= align_branch_jcc
;
9064 if ((align_branch
& align_branch_jcc_bit
))
9068 else if (is_any_vex_encoding (&i
.tm
))
9070 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9073 *branch_p
= align_branch_ret
;
9074 if ((align_branch
& align_branch_ret_bit
))
9079 /* Check for indirect jmp, direct and indirect calls. */
9080 if (i
.tm
.base_opcode
== 0xe8)
9083 *branch_p
= align_branch_call
;
9084 if ((align_branch
& align_branch_call_bit
))
9087 else if (i
.tm
.base_opcode
== 0xff
9088 && (i
.tm
.extension_opcode
== 2
9089 || i
.tm
.extension_opcode
== 4))
9091 /* Indirect call and jmp. */
9092 *branch_p
= align_branch_indirect
;
9093 if ((align_branch
& align_branch_indirect_bit
))
9100 && (i
.op
[0].disps
->X_op
== O_symbol
9101 || (i
.op
[0].disps
->X_op
== O_subtract
9102 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9104 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9105 /* No padding to call to global or undefined tls_get_addr. */
9106 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9107 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9113 && last_insn
.kind
!= last_insn_other
9114 && last_insn
.seg
== now_seg
)
9117 as_warn_where (last_insn
.file
, last_insn
.line
,
9118 _("`%s` skips -malign-branch-boundary on `%s`"),
9119 last_insn
.name
, i
.tm
.name
);
9129 fragS
*insn_start_frag
;
9130 offsetT insn_start_off
;
9131 fragS
*fragP
= NULL
;
9132 enum align_branch_kind branch
= align_branch_none
;
9133 /* The initializer is arbitrary just to avoid uninitialized error.
9134 it's actually either assigned in add_branch_padding_frag_p
9135 or never be used. */
9136 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9138 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9139 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9141 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
9142 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
9143 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
9144 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
9145 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
9146 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
9147 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
9148 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
9149 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
9150 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
9151 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
9152 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
9153 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
9154 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
9155 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9156 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
9157 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
9158 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
9159 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
9160 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
9161 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
9162 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
9163 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
9164 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
9165 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
9166 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
9167 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
9168 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
9169 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
9170 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
9171 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
9172 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
9173 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
9174 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
9175 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
9176 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
9177 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
9178 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
9179 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
9180 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
9181 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
9182 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
9183 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
9184 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
9185 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
9186 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
9187 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
9188 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
9189 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
9190 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
9192 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9193 || i
.tm
.cpu_flags
.bitfield
.cpu287
9194 || i
.tm
.cpu_flags
.bitfield
.cpu387
9195 || i
.tm
.cpu_flags
.bitfield
.cpu687
9196 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9197 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9198 if ((i
.xstate
& xstate_mmx
)
9199 || i
.tm
.base_opcode
== 0xf77 /* emms */
9200 || i
.tm
.base_opcode
== 0xf0e /* femms */)
9201 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9202 if ((i
.xstate
& xstate_xmm
))
9203 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9204 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9205 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9206 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9207 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9208 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9209 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9210 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9211 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9212 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9213 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9214 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9215 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9217 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9218 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9219 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9223 /* Tie dwarf2 debug info to the address at the start of the insn.
9224 We can't do this after the insn has been output as the current
9225 frag may have been closed off. eg. by frag_var. */
9226 dwarf2_emit_insn (0);
9228 insn_start_frag
= frag_now
;
9229 insn_start_off
= frag_now_fix ();
9231 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9234 /* Branch can be 8 bytes. Leave some room for prefixes. */
9235 unsigned int max_branch_padding_size
= 14;
9237 /* Align section to boundary. */
9238 record_alignment (now_seg
, align_branch_power
);
9240 /* Make room for padding. */
9241 frag_grow (max_branch_padding_size
);
9243 /* Start of the padding. */
9248 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9249 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9252 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9253 fragP
->tc_frag_data
.branch_type
= branch
;
9254 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9258 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9260 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9261 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9263 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9264 output_interseg_jump ();
9267 /* Output normal instructions here. */
9271 unsigned int prefix
;
9272 enum mf_cmp_kind mf_cmp
;
9275 && (i
.tm
.base_opcode
== 0xfaee8
9276 || i
.tm
.base_opcode
== 0xfaef0
9277 || i
.tm
.base_opcode
== 0xfaef8))
9279 /* Encode lfence, mfence, and sfence as
9280 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9281 if (now_seg
!= absolute_section
)
9283 offsetT val
= 0x240483f0ULL
;
9286 md_number_to_chars (p
, val
, 5);
9289 abs_section_offset
+= 5;
9293 /* Some processors fail on LOCK prefix. This options makes
9294 assembler ignore LOCK prefix and serves as a workaround. */
9295 if (omit_lock_prefix
)
9297 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9299 i
.prefix
[LOCK_PREFIX
] = 0;
9303 /* Skip if this is a branch. */
9305 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9307 /* Make room for padding. */
9308 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9313 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9314 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9317 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9318 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9319 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9321 else if (add_branch_prefix_frag_p ())
9323 unsigned int max_prefix_size
= align_branch_prefix_size
;
9325 /* Make room for padding. */
9326 frag_grow (max_prefix_size
);
9331 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9332 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9335 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9338 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9339 don't need the explicit prefix. */
9340 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9342 switch (i
.tm
.opcode_length
)
9345 if (i
.tm
.base_opcode
& 0xff000000)
9347 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
9348 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9349 || prefix
!= REPE_PREFIX_OPCODE
9350 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
9351 add_prefix (prefix
);
9355 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
9357 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
9358 add_prefix (prefix
);
9364 /* Check for pseudo prefixes. */
9365 as_bad_where (insn_start_frag
->fr_file
,
9366 insn_start_frag
->fr_line
,
9367 _("pseudo prefix without instruction"));
9373 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9374 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9375 R_X86_64_GOTTPOFF relocation so that linker can safely
9376 perform IE->LE optimization. A dummy REX_OPCODE prefix
9377 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9378 relocation for GDesc -> IE/LE optimization. */
9379 if (x86_elf_abi
== X86_64_X32_ABI
9381 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9382 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9383 && i
.prefix
[REX_PREFIX
] == 0)
9384 add_prefix (REX_OPCODE
);
9387 /* The prefix bytes. */
9388 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9390 frag_opcode_byte (*q
);
9394 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9400 frag_opcode_byte (*q
);
9403 /* There should be no other prefixes for instructions
9408 /* For EVEX instructions i.vrex should become 0 after
9409 build_evex_prefix. For VEX instructions upper 16 registers
9410 aren't available, so VREX should be 0. */
9413 /* Now the VEX prefix. */
9414 if (now_seg
!= absolute_section
)
9416 p
= frag_more (i
.vex
.length
);
9417 for (j
= 0; j
< i
.vex
.length
; j
++)
9418 p
[j
] = i
.vex
.bytes
[j
];
9421 abs_section_offset
+= i
.vex
.length
;
9424 /* Now the opcode; be careful about word order here! */
9425 if (now_seg
== absolute_section
)
9426 abs_section_offset
+= i
.tm
.opcode_length
;
9427 else if (i
.tm
.opcode_length
== 1)
9429 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9433 switch (i
.tm
.opcode_length
)
9437 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9438 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9442 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9452 /* Put out high byte first: can't use md_number_to_chars! */
9453 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9454 *p
= i
.tm
.base_opcode
& 0xff;
9457 /* Now the modrm byte and sib byte (if present). */
9458 if (i
.tm
.opcode_modifier
.modrm
)
9460 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9462 | (i
.rm
.mode
<< 6));
9463 /* If i.rm.regmem == ESP (4)
9464 && i.rm.mode != (Register mode)
9466 ==> need second modrm byte. */
9467 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9469 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9470 frag_opcode_byte ((i
.sib
.base
<< 0)
9471 | (i
.sib
.index
<< 3)
9472 | (i
.sib
.scale
<< 6));
9475 if (i
.disp_operands
)
9476 output_disp (insn_start_frag
, insn_start_off
);
9479 output_imm (insn_start_frag
, insn_start_off
);
9482 * frag_now_fix () returning plain abs_section_offset when we're in the
9483 * absolute section, and abs_section_offset not getting updated as data
9484 * gets added to the frag breaks the logic below.
9486 if (now_seg
!= absolute_section
)
9488 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9490 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9494 /* NB: Don't add prefix with GOTPC relocation since
9495 output_disp() above depends on the fixed encoding
9496 length. Can't add prefix with TLS relocation since
9497 it breaks TLS linker optimization. */
9498 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9499 /* Prefix count on the current instruction. */
9500 unsigned int count
= i
.vex
.length
;
9502 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9503 /* REX byte is encoded in VEX/EVEX prefix. */
9504 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9507 /* Count prefixes for extended opcode maps. */
9509 switch (i
.tm
.opcode_length
)
9512 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9515 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9527 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9536 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9539 /* Set the maximum prefix size in BRANCH_PREFIX
9541 if (fragP
->tc_frag_data
.max_bytes
> max
)
9542 fragP
->tc_frag_data
.max_bytes
= max
;
9543 if (fragP
->tc_frag_data
.max_bytes
> count
)
9544 fragP
->tc_frag_data
.max_bytes
-= count
;
9546 fragP
->tc_frag_data
.max_bytes
= 0;
9550 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9552 unsigned int max_prefix_size
;
9553 if (align_branch_prefix_size
> max
)
9554 max_prefix_size
= max
;
9556 max_prefix_size
= align_branch_prefix_size
;
9557 if (max_prefix_size
> count
)
9558 fragP
->tc_frag_data
.max_prefix_length
9559 = max_prefix_size
- count
;
9562 /* Use existing segment prefix if possible. Use CS
9563 segment prefix in 64-bit mode. In 32-bit mode, use SS
9564 segment prefix with ESP/EBP base register and use DS
9565 segment prefix without ESP/EBP base register. */
9566 if (i
.prefix
[SEG_PREFIX
])
9567 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9568 else if (flag_code
== CODE_64BIT
)
9569 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9571 && (i
.base_reg
->reg_num
== 4
9572 || i
.base_reg
->reg_num
== 5))
9573 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9575 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9580 /* NB: Don't work with COND_JUMP86 without i386. */
9581 if (align_branch_power
9582 && now_seg
!= absolute_section
9583 && cpu_arch_flags
.bitfield
.cpui386
)
9585 /* Terminate each frag so that we can add prefix and check for
9587 frag_wane (frag_now
);
9594 pi ("" /*line*/, &i
);
9596 #endif /* DEBUG386 */
9599 /* Return the size of the displacement operand N. */
9602 disp_size (unsigned int n
)
9606 if (i
.types
[n
].bitfield
.disp64
)
9608 else if (i
.types
[n
].bitfield
.disp8
)
9610 else if (i
.types
[n
].bitfield
.disp16
)
9615 /* Return the size of the immediate operand N. */
9618 imm_size (unsigned int n
)
9621 if (i
.types
[n
].bitfield
.imm64
)
9623 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9625 else if (i
.types
[n
].bitfield
.imm16
)
9631 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9636 for (n
= 0; n
< i
.operands
; n
++)
9638 if (operand_type_check (i
.types
[n
], disp
))
9640 int size
= disp_size (n
);
9642 if (now_seg
== absolute_section
)
9643 abs_section_offset
+= size
;
9644 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9646 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9648 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9650 p
= frag_more (size
);
9651 md_number_to_chars (p
, val
, size
);
9655 enum bfd_reloc_code_real reloc_type
;
9656 int sign
= i
.types
[n
].bitfield
.disp32s
;
9657 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9660 /* We can't have 8 bit displacement here. */
9661 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9663 /* The PC relative address is computed relative
9664 to the instruction boundary, so in case immediate
9665 fields follows, we need to adjust the value. */
9666 if (pcrel
&& i
.imm_operands
)
9671 for (n1
= 0; n1
< i
.operands
; n1
++)
9672 if (operand_type_check (i
.types
[n1
], imm
))
9674 /* Only one immediate is allowed for PC
9675 relative address. */
9676 gas_assert (sz
== 0);
9678 i
.op
[n
].disps
->X_add_number
-= sz
;
9680 /* We should find the immediate. */
9681 gas_assert (sz
!= 0);
9684 p
= frag_more (size
);
9685 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9687 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9688 && (((reloc_type
== BFD_RELOC_32
9689 || reloc_type
== BFD_RELOC_X86_64_32S
9690 || (reloc_type
== BFD_RELOC_64
9692 && (i
.op
[n
].disps
->X_op
== O_symbol
9693 || (i
.op
[n
].disps
->X_op
== O_add
9694 && ((symbol_get_value_expression
9695 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9697 || reloc_type
== BFD_RELOC_32_PCREL
))
9701 reloc_type
= BFD_RELOC_386_GOTPC
;
9702 i
.has_gotpc_tls_reloc
= TRUE
;
9703 i
.op
[n
].imms
->X_add_number
+=
9704 encoding_length (insn_start_frag
, insn_start_off
, p
);
9706 else if (reloc_type
== BFD_RELOC_64
)
9707 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9709 /* Don't do the adjustment for x86-64, as there
9710 the pcrel addressing is relative to the _next_
9711 insn, and that is taken care of in other code. */
9712 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9714 else if (align_branch_power
)
9718 case BFD_RELOC_386_TLS_GD
:
9719 case BFD_RELOC_386_TLS_LDM
:
9720 case BFD_RELOC_386_TLS_IE
:
9721 case BFD_RELOC_386_TLS_IE_32
:
9722 case BFD_RELOC_386_TLS_GOTIE
:
9723 case BFD_RELOC_386_TLS_GOTDESC
:
9724 case BFD_RELOC_386_TLS_DESC_CALL
:
9725 case BFD_RELOC_X86_64_TLSGD
:
9726 case BFD_RELOC_X86_64_TLSLD
:
9727 case BFD_RELOC_X86_64_GOTTPOFF
:
9728 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9729 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9730 i
.has_gotpc_tls_reloc
= TRUE
;
9735 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9736 size
, i
.op
[n
].disps
, pcrel
,
9738 /* Check for "call/jmp *mem", "mov mem, %reg",
9739 "test %reg, mem" and "binop mem, %reg" where binop
9740 is one of adc, add, and, cmp, or, sbb, sub, xor
9741 instructions without data prefix. Always generate
9742 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9743 if (i
.prefix
[DATA_PREFIX
] == 0
9744 && (generate_relax_relocations
9747 && i
.rm
.regmem
== 5))
9749 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9750 && !is_any_vex_encoding(&i
.tm
)
9751 && ((i
.operands
== 1
9752 && i
.tm
.base_opcode
== 0xff
9753 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9755 && (i
.tm
.base_opcode
== 0x8b
9756 || i
.tm
.base_opcode
== 0x85
9757 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9761 fixP
->fx_tcbit
= i
.rex
!= 0;
9763 && (i
.base_reg
->reg_num
== RegIP
))
9764 fixP
->fx_tcbit2
= 1;
9767 fixP
->fx_tcbit2
= 1;
9775 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9780 for (n
= 0; n
< i
.operands
; n
++)
9782 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9783 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9786 if (operand_type_check (i
.types
[n
], imm
))
9788 int size
= imm_size (n
);
9790 if (now_seg
== absolute_section
)
9791 abs_section_offset
+= size
;
9792 else if (i
.op
[n
].imms
->X_op
== O_constant
)
9796 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9798 p
= frag_more (size
);
9799 md_number_to_chars (p
, val
, size
);
9803 /* Not absolute_section.
9804 Need a 32-bit fixup (don't support 8bit
9805 non-absolute imms). Try to support other
9807 enum bfd_reloc_code_real reloc_type
;
9810 if (i
.types
[n
].bitfield
.imm32s
9811 && (i
.suffix
== QWORD_MNEM_SUFFIX
9812 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9817 p
= frag_more (size
);
9818 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9820 /* This is tough to explain. We end up with this one if we
9821 * have operands that look like
9822 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9823 * obtain the absolute address of the GOT, and it is strongly
9824 * preferable from a performance point of view to avoid using
9825 * a runtime relocation for this. The actual sequence of
9826 * instructions often look something like:
9831 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9833 * The call and pop essentially return the absolute address
9834 * of the label .L66 and store it in %ebx. The linker itself
9835 * will ultimately change the first operand of the addl so
9836 * that %ebx points to the GOT, but to keep things simple, the
9837 * .o file must have this operand set so that it generates not
9838 * the absolute address of .L66, but the absolute address of
9839 * itself. This allows the linker itself simply treat a GOTPC
9840 * relocation as asking for a pcrel offset to the GOT to be
9841 * added in, and the addend of the relocation is stored in the
9842 * operand field for the instruction itself.
9844 * Our job here is to fix the operand so that it would add
9845 * the correct offset so that %ebx would point to itself. The
9846 * thing that is tricky is that .-.L66 will point to the
9847 * beginning of the instruction, so we need to further modify
9848 * the operand so that it will point to itself. There are
9849 * other cases where you have something like:
9851 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9853 * and here no correction would be required. Internally in
9854 * the assembler we treat operands of this form as not being
9855 * pcrel since the '.' is explicitly mentioned, and I wonder
9856 * whether it would simplify matters to do it this way. Who
9857 * knows. In earlier versions of the PIC patches, the
9858 * pcrel_adjust field was used to store the correction, but
9859 * since the expression is not pcrel, I felt it would be
9860 * confusing to do it this way. */
9862 if ((reloc_type
== BFD_RELOC_32
9863 || reloc_type
== BFD_RELOC_X86_64_32S
9864 || reloc_type
== BFD_RELOC_64
)
9866 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9867 && (i
.op
[n
].imms
->X_op
== O_symbol
9868 || (i
.op
[n
].imms
->X_op
== O_add
9869 && ((symbol_get_value_expression
9870 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9874 reloc_type
= BFD_RELOC_386_GOTPC
;
9876 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9878 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9879 i
.has_gotpc_tls_reloc
= TRUE
;
9880 i
.op
[n
].imms
->X_add_number
+=
9881 encoding_length (insn_start_frag
, insn_start_off
, p
);
9883 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9884 i
.op
[n
].imms
, 0, reloc_type
);
9890 /* x86_cons_fix_new is called via the expression parsing code when a
9891 reloc is needed. We use this hook to get the correct .got reloc. */
9892 static int cons_sign
= -1;
9895 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9896 expressionS
*exp
, bfd_reloc_code_real_type r
)
9898 r
= reloc (len
, 0, cons_sign
, r
);
9901 if (exp
->X_op
== O_secrel
)
9903 exp
->X_op
= O_symbol
;
9904 r
= BFD_RELOC_32_SECREL
;
9908 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9911 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9912 purpose of the `.dc.a' internal pseudo-op. */
9915 x86_address_bytes (void)
9917 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9919 return stdoutput
->arch_info
->bits_per_address
/ 8;
9922 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9924 # define lex_got(reloc, adjust, types) NULL
9926 /* Parse operands of the form
9927 <symbol>@GOTOFF+<nnn>
9928 and similar .plt or .got references.
9930 If we find one, set up the correct relocation in RELOC and copy the
9931 input string, minus the `@GOTOFF' into a malloc'd buffer for
9932 parsing by the calling routine. Return this buffer, and if ADJUST
9933 is non-null set it to the length of the string we removed from the
9934 input line. Otherwise return NULL. */
9936 lex_got (enum bfd_reloc_code_real
*rel
,
9938 i386_operand_type
*types
)
9940 /* Some of the relocations depend on the size of what field is to
9941 be relocated. But in our callers i386_immediate and i386_displacement
9942 we don't yet know the operand size (this will be set by insn
9943 matching). Hence we record the word32 relocation here,
9944 and adjust the reloc according to the real size in reloc(). */
9945 static const struct {
9948 const enum bfd_reloc_code_real rel
[2];
9949 const i386_operand_type types64
;
9951 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9952 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9954 OPERAND_TYPE_IMM32_64
},
9956 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9957 BFD_RELOC_X86_64_PLTOFF64
},
9958 OPERAND_TYPE_IMM64
},
9959 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9960 BFD_RELOC_X86_64_PLT32
},
9961 OPERAND_TYPE_IMM32_32S_DISP32
},
9962 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9963 BFD_RELOC_X86_64_GOTPLT64
},
9964 OPERAND_TYPE_IMM64_DISP64
},
9965 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9966 BFD_RELOC_X86_64_GOTOFF64
},
9967 OPERAND_TYPE_IMM64_DISP64
},
9968 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9969 BFD_RELOC_X86_64_GOTPCREL
},
9970 OPERAND_TYPE_IMM32_32S_DISP32
},
9971 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9972 BFD_RELOC_X86_64_TLSGD
},
9973 OPERAND_TYPE_IMM32_32S_DISP32
},
9974 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9975 _dummy_first_bfd_reloc_code_real
},
9976 OPERAND_TYPE_NONE
},
9977 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9978 BFD_RELOC_X86_64_TLSLD
},
9979 OPERAND_TYPE_IMM32_32S_DISP32
},
9980 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9981 BFD_RELOC_X86_64_GOTTPOFF
},
9982 OPERAND_TYPE_IMM32_32S_DISP32
},
9983 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9984 BFD_RELOC_X86_64_TPOFF32
},
9985 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9986 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9987 _dummy_first_bfd_reloc_code_real
},
9988 OPERAND_TYPE_NONE
},
9989 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9990 BFD_RELOC_X86_64_DTPOFF32
},
9991 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9992 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9993 _dummy_first_bfd_reloc_code_real
},
9994 OPERAND_TYPE_NONE
},
9995 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9996 _dummy_first_bfd_reloc_code_real
},
9997 OPERAND_TYPE_NONE
},
9998 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9999 BFD_RELOC_X86_64_GOT32
},
10000 OPERAND_TYPE_IMM32_32S_64_DISP32
},
10001 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10002 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10003 OPERAND_TYPE_IMM32_32S_DISP32
},
10004 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10005 BFD_RELOC_X86_64_TLSDESC_CALL
},
10006 OPERAND_TYPE_IMM32_32S_DISP32
},
10011 #if defined (OBJ_MAYBE_ELF)
10016 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10017 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10020 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10022 int len
= gotrel
[j
].len
;
10023 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10025 if (gotrel
[j
].rel
[object_64bit
] != 0)
10028 char *tmpbuf
, *past_reloc
;
10030 *rel
= gotrel
[j
].rel
[object_64bit
];
10034 if (flag_code
!= CODE_64BIT
)
10036 types
->bitfield
.imm32
= 1;
10037 types
->bitfield
.disp32
= 1;
10040 *types
= gotrel
[j
].types64
;
10043 if (j
!= 0 && GOT_symbol
== NULL
)
10044 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10046 /* The length of the first part of our input line. */
10047 first
= cp
- input_line_pointer
;
10049 /* The second part goes from after the reloc token until
10050 (and including) an end_of_line char or comma. */
10051 past_reloc
= cp
+ 1 + len
;
10053 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10055 second
= cp
+ 1 - past_reloc
;
10057 /* Allocate and copy string. The trailing NUL shouldn't
10058 be necessary, but be safe. */
10059 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10060 memcpy (tmpbuf
, input_line_pointer
, first
);
10061 if (second
!= 0 && *past_reloc
!= ' ')
10062 /* Replace the relocation token with ' ', so that
10063 errors like foo@GOTOFF1 will be detected. */
10064 tmpbuf
[first
++] = ' ';
10066 /* Increment length by 1 if the relocation token is
10071 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10072 tmpbuf
[first
+ second
] = '\0';
10076 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10077 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10082 /* Might be a symbol version string. Don't as_bad here. */
10091 /* Parse operands of the form
10092 <symbol>@SECREL32+<nnn>
10094 If we find one, set up the correct relocation in RELOC and copy the
10095 input string, minus the `@SECREL32' into a malloc'd buffer for
10096 parsing by the calling routine. Return this buffer, and if ADJUST
10097 is non-null set it to the length of the string we removed from the
10098 input line. Otherwise return NULL.
10100 This function is copied from the ELF version above adjusted for PE targets. */
10103 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
10104 int *adjust ATTRIBUTE_UNUSED
,
10105 i386_operand_type
*types
)
10107 static const struct
10111 const enum bfd_reloc_code_real rel
[2];
10112 const i386_operand_type types64
;
10116 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10117 BFD_RELOC_32_SECREL
},
10118 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10124 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10125 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10128 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10130 int len
= gotrel
[j
].len
;
10132 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10134 if (gotrel
[j
].rel
[object_64bit
] != 0)
10137 char *tmpbuf
, *past_reloc
;
10139 *rel
= gotrel
[j
].rel
[object_64bit
];
10145 if (flag_code
!= CODE_64BIT
)
10147 types
->bitfield
.imm32
= 1;
10148 types
->bitfield
.disp32
= 1;
10151 *types
= gotrel
[j
].types64
;
10154 /* The length of the first part of our input line. */
10155 first
= cp
- input_line_pointer
;
10157 /* The second part goes from after the reloc token until
10158 (and including) an end_of_line char or comma. */
10159 past_reloc
= cp
+ 1 + len
;
10161 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10163 second
= cp
+ 1 - past_reloc
;
10165 /* Allocate and copy string. The trailing NUL shouldn't
10166 be necessary, but be safe. */
10167 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10168 memcpy (tmpbuf
, input_line_pointer
, first
);
10169 if (second
!= 0 && *past_reloc
!= ' ')
10170 /* Replace the relocation token with ' ', so that
10171 errors like foo@SECLREL321 will be detected. */
10172 tmpbuf
[first
++] = ' ';
10173 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10174 tmpbuf
[first
+ second
] = '\0';
10178 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10179 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10184 /* Might be a symbol version string. Don't as_bad here. */
10190 bfd_reloc_code_real_type
10191 x86_cons (expressionS
*exp
, int size
)
10193 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10195 intel_syntax
= -intel_syntax
;
10198 if (size
== 4 || (object_64bit
&& size
== 8))
10200 /* Handle @GOTOFF and the like in an expression. */
10202 char *gotfree_input_line
;
10205 save
= input_line_pointer
;
10206 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10207 if (gotfree_input_line
)
10208 input_line_pointer
= gotfree_input_line
;
10212 if (gotfree_input_line
)
10214 /* expression () has merrily parsed up to the end of line,
10215 or a comma - in the wrong buffer. Transfer how far
10216 input_line_pointer has moved to the right buffer. */
10217 input_line_pointer
= (save
10218 + (input_line_pointer
- gotfree_input_line
)
10220 free (gotfree_input_line
);
10221 if (exp
->X_op
== O_constant
10222 || exp
->X_op
== O_absent
10223 || exp
->X_op
== O_illegal
10224 || exp
->X_op
== O_register
10225 || exp
->X_op
== O_big
)
10227 char c
= *input_line_pointer
;
10228 *input_line_pointer
= 0;
10229 as_bad (_("missing or invalid expression `%s'"), save
);
10230 *input_line_pointer
= c
;
10232 else if ((got_reloc
== BFD_RELOC_386_PLT32
10233 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10234 && exp
->X_op
!= O_symbol
)
10236 char c
= *input_line_pointer
;
10237 *input_line_pointer
= 0;
10238 as_bad (_("invalid PLT expression `%s'"), save
);
10239 *input_line_pointer
= c
;
10246 intel_syntax
= -intel_syntax
;
10249 i386_intel_simplify (exp
);
10255 signed_cons (int size
)
10257 if (flag_code
== CODE_64BIT
)
10265 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10272 if (exp
.X_op
== O_symbol
)
10273 exp
.X_op
= O_secrel
;
10275 emit_expr (&exp
, 4);
10277 while (*input_line_pointer
++ == ',');
10279 input_line_pointer
--;
10280 demand_empty_rest_of_line ();
10284 /* Handle Vector operations. */
10287 check_VecOperations (char *op_string
, char *op_end
)
10289 const reg_entry
*mask
;
10294 && (op_end
== NULL
|| op_string
< op_end
))
10297 if (*op_string
== '{')
10301 /* Check broadcasts. */
10302 if (strncmp (op_string
, "1to", 3) == 0)
10307 goto duplicated_vec_op
;
10310 if (*op_string
== '8')
10312 else if (*op_string
== '4')
10314 else if (*op_string
== '2')
10316 else if (*op_string
== '1'
10317 && *(op_string
+1) == '6')
10324 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10329 broadcast_op
.type
= bcst_type
;
10330 broadcast_op
.operand
= this_operand
;
10331 broadcast_op
.bytes
= 0;
10332 i
.broadcast
= &broadcast_op
;
10334 /* Check masking operation. */
10335 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10337 if (mask
== &bad_reg
)
10340 /* k0 can't be used for write mask. */
10341 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10343 as_bad (_("`%s%s' can't be used for write mask"),
10344 register_prefix
, mask
->reg_name
);
10350 mask_op
.mask
= mask
;
10351 mask_op
.zeroing
= 0;
10352 mask_op
.operand
= this_operand
;
10358 goto duplicated_vec_op
;
10360 i
.mask
->mask
= mask
;
10362 /* Only "{z}" is allowed here. No need to check
10363 zeroing mask explicitly. */
10364 if (i
.mask
->operand
!= this_operand
)
10366 as_bad (_("invalid write mask `%s'"), saved
);
10371 op_string
= end_op
;
10373 /* Check zeroing-flag for masking operation. */
10374 else if (*op_string
== 'z')
10378 mask_op
.mask
= NULL
;
10379 mask_op
.zeroing
= 1;
10380 mask_op
.operand
= this_operand
;
10385 if (i
.mask
->zeroing
)
10388 as_bad (_("duplicated `%s'"), saved
);
10392 i
.mask
->zeroing
= 1;
10394 /* Only "{%k}" is allowed here. No need to check mask
10395 register explicitly. */
10396 if (i
.mask
->operand
!= this_operand
)
10398 as_bad (_("invalid zeroing-masking `%s'"),
10407 goto unknown_vec_op
;
10409 if (*op_string
!= '}')
10411 as_bad (_("missing `}' in `%s'"), saved
);
10416 /* Strip whitespace since the addition of pseudo prefixes
10417 changed how the scrubber treats '{'. */
10418 if (is_space_char (*op_string
))
10424 /* We don't know this one. */
10425 as_bad (_("unknown vector operation: `%s'"), saved
);
10429 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10431 as_bad (_("zeroing-masking only allowed with write mask"));
10439 i386_immediate (char *imm_start
)
10441 char *save_input_line_pointer
;
10442 char *gotfree_input_line
;
10445 i386_operand_type types
;
10447 operand_type_set (&types
, ~0);
10449 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10451 as_bad (_("at most %d immediate operands are allowed"),
10452 MAX_IMMEDIATE_OPERANDS
);
10456 exp
= &im_expressions
[i
.imm_operands
++];
10457 i
.op
[this_operand
].imms
= exp
;
10459 if (is_space_char (*imm_start
))
10462 save_input_line_pointer
= input_line_pointer
;
10463 input_line_pointer
= imm_start
;
10465 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10466 if (gotfree_input_line
)
10467 input_line_pointer
= gotfree_input_line
;
10469 exp_seg
= expression (exp
);
10471 SKIP_WHITESPACE ();
10473 /* Handle vector operations. */
10474 if (*input_line_pointer
== '{')
10476 input_line_pointer
= check_VecOperations (input_line_pointer
,
10478 if (input_line_pointer
== NULL
)
10482 if (*input_line_pointer
)
10483 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10485 input_line_pointer
= save_input_line_pointer
;
10486 if (gotfree_input_line
)
10488 free (gotfree_input_line
);
10490 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10491 exp
->X_op
= O_illegal
;
10494 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10498 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10499 i386_operand_type types
, const char *imm_start
)
10501 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10504 as_bad (_("missing or invalid immediate expression `%s'"),
10508 else if (exp
->X_op
== O_constant
)
10510 /* Size it properly later. */
10511 i
.types
[this_operand
].bitfield
.imm64
= 1;
10512 /* If not 64bit, sign extend val. */
10513 if (flag_code
!= CODE_64BIT
10514 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10516 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10518 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10519 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10520 && exp_seg
!= absolute_section
10521 && exp_seg
!= text_section
10522 && exp_seg
!= data_section
10523 && exp_seg
!= bss_section
10524 && exp_seg
!= undefined_section
10525 && !bfd_is_com_section (exp_seg
))
10527 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10531 else if (!intel_syntax
&& exp_seg
== reg_section
)
10534 as_bad (_("illegal immediate register operand %s"), imm_start
);
10539 /* This is an address. The size of the address will be
10540 determined later, depending on destination register,
10541 suffix, or the default for the section. */
10542 i
.types
[this_operand
].bitfield
.imm8
= 1;
10543 i
.types
[this_operand
].bitfield
.imm16
= 1;
10544 i
.types
[this_operand
].bitfield
.imm32
= 1;
10545 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10546 i
.types
[this_operand
].bitfield
.imm64
= 1;
10547 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10555 i386_scale (char *scale
)
10558 char *save
= input_line_pointer
;
10560 input_line_pointer
= scale
;
10561 val
= get_absolute_expression ();
10566 i
.log2_scale_factor
= 0;
10569 i
.log2_scale_factor
= 1;
10572 i
.log2_scale_factor
= 2;
10575 i
.log2_scale_factor
= 3;
10579 char sep
= *input_line_pointer
;
10581 *input_line_pointer
= '\0';
10582 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10584 *input_line_pointer
= sep
;
10585 input_line_pointer
= save
;
10589 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10591 as_warn (_("scale factor of %d without an index register"),
10592 1 << i
.log2_scale_factor
);
10593 i
.log2_scale_factor
= 0;
10595 scale
= input_line_pointer
;
10596 input_line_pointer
= save
;
10601 i386_displacement (char *disp_start
, char *disp_end
)
10605 char *save_input_line_pointer
;
10606 char *gotfree_input_line
;
10608 i386_operand_type bigdisp
, types
= anydisp
;
10611 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10613 as_bad (_("at most %d displacement operands are allowed"),
10614 MAX_MEMORY_OPERANDS
);
10618 operand_type_set (&bigdisp
, 0);
10620 || i
.types
[this_operand
].bitfield
.baseindex
10621 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10622 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10624 i386_addressing_mode ();
10625 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10626 if (flag_code
== CODE_64BIT
)
10630 bigdisp
.bitfield
.disp32s
= 1;
10631 bigdisp
.bitfield
.disp64
= 1;
10634 bigdisp
.bitfield
.disp32
= 1;
10636 else if ((flag_code
== CODE_16BIT
) ^ override
)
10637 bigdisp
.bitfield
.disp16
= 1;
10639 bigdisp
.bitfield
.disp32
= 1;
10643 /* For PC-relative branches, the width of the displacement may be
10644 dependent upon data size, but is never dependent upon address size.
10645 Also make sure to not unintentionally match against a non-PC-relative
10646 branch template. */
10647 static templates aux_templates
;
10648 const insn_template
*t
= current_templates
->start
;
10649 bfd_boolean has_intel64
= FALSE
;
10651 aux_templates
.start
= t
;
10652 while (++t
< current_templates
->end
)
10654 if (t
->opcode_modifier
.jump
10655 != current_templates
->start
->opcode_modifier
.jump
)
10657 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10658 has_intel64
= TRUE
;
10660 if (t
< current_templates
->end
)
10662 aux_templates
.end
= t
;
10663 current_templates
= &aux_templates
;
10666 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10667 if (flag_code
== CODE_64BIT
)
10669 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10670 && (!intel64
|| !has_intel64
))
10671 bigdisp
.bitfield
.disp16
= 1;
10673 bigdisp
.bitfield
.disp32s
= 1;
10678 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10680 : LONG_MNEM_SUFFIX
));
10681 bigdisp
.bitfield
.disp32
= 1;
10682 if ((flag_code
== CODE_16BIT
) ^ override
)
10684 bigdisp
.bitfield
.disp32
= 0;
10685 bigdisp
.bitfield
.disp16
= 1;
10689 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10692 exp
= &disp_expressions
[i
.disp_operands
];
10693 i
.op
[this_operand
].disps
= exp
;
10695 save_input_line_pointer
= input_line_pointer
;
10696 input_line_pointer
= disp_start
;
10697 END_STRING_AND_SAVE (disp_end
);
10699 #ifndef GCC_ASM_O_HACK
10700 #define GCC_ASM_O_HACK 0
10703 END_STRING_AND_SAVE (disp_end
+ 1);
10704 if (i
.types
[this_operand
].bitfield
.baseIndex
10705 && displacement_string_end
[-1] == '+')
10707 /* This hack is to avoid a warning when using the "o"
10708 constraint within gcc asm statements.
10711 #define _set_tssldt_desc(n,addr,limit,type) \
10712 __asm__ __volatile__ ( \
10713 "movw %w2,%0\n\t" \
10714 "movw %w1,2+%0\n\t" \
10715 "rorl $16,%1\n\t" \
10716 "movb %b1,4+%0\n\t" \
10717 "movb %4,5+%0\n\t" \
10718 "movb $0,6+%0\n\t" \
10719 "movb %h1,7+%0\n\t" \
10721 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10723 This works great except that the output assembler ends
10724 up looking a bit weird if it turns out that there is
10725 no offset. You end up producing code that looks like:
10738 So here we provide the missing zero. */
10740 *displacement_string_end
= '0';
10743 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10744 if (gotfree_input_line
)
10745 input_line_pointer
= gotfree_input_line
;
10747 exp_seg
= expression (exp
);
10749 SKIP_WHITESPACE ();
10750 if (*input_line_pointer
)
10751 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10753 RESTORE_END_STRING (disp_end
+ 1);
10755 input_line_pointer
= save_input_line_pointer
;
10756 if (gotfree_input_line
)
10758 free (gotfree_input_line
);
10760 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10761 exp
->X_op
= O_illegal
;
10764 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10766 RESTORE_END_STRING (disp_end
);
10772 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10773 i386_operand_type types
, const char *disp_start
)
10775 i386_operand_type bigdisp
;
10778 /* We do this to make sure that the section symbol is in
10779 the symbol table. We will ultimately change the relocation
10780 to be relative to the beginning of the section. */
10781 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10782 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10783 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10785 if (exp
->X_op
!= O_symbol
)
10788 if (S_IS_LOCAL (exp
->X_add_symbol
)
10789 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10790 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10791 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10792 exp
->X_op
= O_subtract
;
10793 exp
->X_op_symbol
= GOT_symbol
;
10794 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10795 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10796 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10797 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10799 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10802 else if (exp
->X_op
== O_absent
10803 || exp
->X_op
== O_illegal
10804 || exp
->X_op
== O_big
)
10807 as_bad (_("missing or invalid displacement expression `%s'"),
10812 else if (flag_code
== CODE_64BIT
10813 && !i
.prefix
[ADDR_PREFIX
]
10814 && exp
->X_op
== O_constant
)
10816 /* Since displacement is signed extended to 64bit, don't allow
10817 disp32 and turn off disp32s if they are out of range. */
10818 i
.types
[this_operand
].bitfield
.disp32
= 0;
10819 if (!fits_in_signed_long (exp
->X_add_number
))
10821 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10822 if (i
.types
[this_operand
].bitfield
.baseindex
)
10824 as_bad (_("0x%lx out range of signed 32bit displacement"),
10825 (long) exp
->X_add_number
);
10831 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10832 else if (exp
->X_op
!= O_constant
10833 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10834 && exp_seg
!= absolute_section
10835 && exp_seg
!= text_section
10836 && exp_seg
!= data_section
10837 && exp_seg
!= bss_section
10838 && exp_seg
!= undefined_section
10839 && !bfd_is_com_section (exp_seg
))
10841 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10846 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10847 /* Constants get taken care of by optimize_disp(). */
10848 && exp
->X_op
!= O_constant
)
10849 i
.types
[this_operand
].bitfield
.disp8
= 1;
10851 /* Check if this is a displacement only operand. */
10852 bigdisp
= i
.types
[this_operand
];
10853 bigdisp
.bitfield
.disp8
= 0;
10854 bigdisp
.bitfield
.disp16
= 0;
10855 bigdisp
.bitfield
.disp32
= 0;
10856 bigdisp
.bitfield
.disp32s
= 0;
10857 bigdisp
.bitfield
.disp64
= 0;
10858 if (operand_type_all_zero (&bigdisp
))
10859 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10865 /* Return the active addressing mode, taking address override and
10866 registers forming the address into consideration. Update the
10867 address override prefix if necessary. */
10869 static enum flag_code
10870 i386_addressing_mode (void)
10872 enum flag_code addr_mode
;
10874 if (i
.prefix
[ADDR_PREFIX
])
10875 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10876 else if (flag_code
== CODE_16BIT
10877 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10878 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10879 from md_assemble() by "is not a valid base/index expression"
10880 when there is a base and/or index. */
10881 && !i
.types
[this_operand
].bitfield
.baseindex
)
10883 /* MPX insn memory operands with neither base nor index must be forced
10884 to use 32-bit addressing in 16-bit mode. */
10885 addr_mode
= CODE_32BIT
;
10886 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10888 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10889 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10893 addr_mode
= flag_code
;
10895 #if INFER_ADDR_PREFIX
10896 if (i
.mem_operands
== 0)
10898 /* Infer address prefix from the first memory operand. */
10899 const reg_entry
*addr_reg
= i
.base_reg
;
10901 if (addr_reg
== NULL
)
10902 addr_reg
= i
.index_reg
;
10906 if (addr_reg
->reg_type
.bitfield
.dword
)
10907 addr_mode
= CODE_32BIT
;
10908 else if (flag_code
!= CODE_64BIT
10909 && addr_reg
->reg_type
.bitfield
.word
)
10910 addr_mode
= CODE_16BIT
;
10912 if (addr_mode
!= flag_code
)
10914 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10916 /* Change the size of any displacement too. At most one
10917 of Disp16 or Disp32 is set.
10918 FIXME. There doesn't seem to be any real need for
10919 separate Disp16 and Disp32 flags. The same goes for
10920 Imm16 and Imm32. Removing them would probably clean
10921 up the code quite a lot. */
10922 if (flag_code
!= CODE_64BIT
10923 && (i
.types
[this_operand
].bitfield
.disp16
10924 || i
.types
[this_operand
].bitfield
.disp32
))
10925 i
.types
[this_operand
]
10926 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10936 /* Make sure the memory operand we've been dealt is valid.
10937 Return 1 on success, 0 on a failure. */
10940 i386_index_check (const char *operand_string
)
10942 const char *kind
= "base/index";
10943 enum flag_code addr_mode
= i386_addressing_mode ();
10945 if (current_templates
->start
->opcode_modifier
.isstring
10946 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10947 && (current_templates
->end
[-1].opcode_modifier
.isstring
10948 || i
.mem_operands
))
10950 /* Memory operands of string insns are special in that they only allow
10951 a single register (rDI, rSI, or rBX) as their memory address. */
10952 const reg_entry
*expected_reg
;
10953 static const char *di_si
[][2] =
10959 static const char *bx
[] = { "ebx", "bx", "rbx" };
10961 kind
= "string address";
10963 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10965 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10966 - IS_STRING_ES_OP0
;
10969 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10970 || ((!i
.mem_operands
!= !intel_syntax
)
10971 && current_templates
->end
[-1].operand_types
[1]
10972 .bitfield
.baseindex
))
10975 = (const reg_entry
*) str_hash_find (reg_hash
,
10976 di_si
[addr_mode
][op
== es_op
]);
10980 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
10982 if (i
.base_reg
!= expected_reg
10984 || operand_type_check (i
.types
[this_operand
], disp
))
10986 /* The second memory operand must have the same size as
10990 && !((addr_mode
== CODE_64BIT
10991 && i
.base_reg
->reg_type
.bitfield
.qword
)
10992 || (addr_mode
== CODE_32BIT
10993 ? i
.base_reg
->reg_type
.bitfield
.dword
10994 : i
.base_reg
->reg_type
.bitfield
.word
)))
10997 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10999 intel_syntax
? '[' : '(',
11001 expected_reg
->reg_name
,
11002 intel_syntax
? ']' : ')');
11009 as_bad (_("`%s' is not a valid %s expression"),
11010 operand_string
, kind
);
11015 if (addr_mode
!= CODE_16BIT
)
11017 /* 32-bit/64-bit checks. */
11018 if (i
.disp_encoding
== disp_encoding_16bit
)
11021 as_bad (_("invalid `%s' prefix"),
11022 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11027 && ((addr_mode
== CODE_64BIT
11028 ? !i
.base_reg
->reg_type
.bitfield
.qword
11029 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11030 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11031 || i
.base_reg
->reg_num
== RegIZ
))
11033 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11034 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11035 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11036 && ((addr_mode
== CODE_64BIT
11037 ? !i
.index_reg
->reg_type
.bitfield
.qword
11038 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11039 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11042 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11043 if (current_templates
->start
->base_opcode
== 0xf30f1b
11044 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11045 || current_templates
->start
->opcode_modifier
.sib
== SIBMEM
)
11047 /* They cannot use RIP-relative addressing. */
11048 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11050 as_bad (_("`%s' cannot be used here"), operand_string
);
11054 /* bndldx and bndstx ignore their scale factor. */
11055 if ((current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11056 && i
.log2_scale_factor
)
11057 as_warn (_("register scaling is being ignored here"));
11062 /* 16-bit checks. */
11063 if (i
.disp_encoding
== disp_encoding_32bit
)
11067 && (!i
.base_reg
->reg_type
.bitfield
.word
11068 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11070 && (!i
.index_reg
->reg_type
.bitfield
.word
11071 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11073 && i
.base_reg
->reg_num
< 6
11074 && i
.index_reg
->reg_num
>= 6
11075 && i
.log2_scale_factor
== 0))))
11082 /* Handle vector immediates. */
11085 RC_SAE_immediate (const char *imm_start
)
11087 unsigned int match_found
, j
;
11088 const char *pstr
= imm_start
;
11096 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11098 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11102 rc_op
.type
= RC_NamesTable
[j
].type
;
11103 rc_op
.operand
= this_operand
;
11104 i
.rounding
= &rc_op
;
11108 as_bad (_("duplicated `%s'"), imm_start
);
11111 pstr
+= RC_NamesTable
[j
].len
;
11119 if (*pstr
++ != '}')
11121 as_bad (_("Missing '}': '%s'"), imm_start
);
11124 /* RC/SAE immediate string should contain nothing more. */;
11127 as_bad (_("Junk after '}': '%s'"), imm_start
);
11131 exp
= &im_expressions
[i
.imm_operands
++];
11132 i
.op
[this_operand
].imms
= exp
;
11134 exp
->X_op
= O_constant
;
11135 exp
->X_add_number
= 0;
11136 exp
->X_add_symbol
= (symbolS
*) 0;
11137 exp
->X_op_symbol
= (symbolS
*) 0;
11139 i
.types
[this_operand
].bitfield
.imm8
= 1;
11143 /* Only string instructions can have a second memory operand, so
11144 reduce current_templates to just those if it contains any. */
11146 maybe_adjust_templates (void)
11148 const insn_template
*t
;
11150 gas_assert (i
.mem_operands
== 1);
11152 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11153 if (t
->opcode_modifier
.isstring
)
11156 if (t
< current_templates
->end
)
11158 static templates aux_templates
;
11159 bfd_boolean recheck
;
11161 aux_templates
.start
= t
;
11162 for (; t
< current_templates
->end
; ++t
)
11163 if (!t
->opcode_modifier
.isstring
)
11165 aux_templates
.end
= t
;
11167 /* Determine whether to re-check the first memory operand. */
11168 recheck
= (aux_templates
.start
!= current_templates
->start
11169 || t
!= current_templates
->end
);
11171 current_templates
= &aux_templates
;
11175 i
.mem_operands
= 0;
11176 if (i
.memop1_string
!= NULL
11177 && i386_index_check (i
.memop1_string
) == 0)
11179 i
.mem_operands
= 1;
11186 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11190 i386_att_operand (char *operand_string
)
11192 const reg_entry
*r
;
11194 char *op_string
= operand_string
;
11196 if (is_space_char (*op_string
))
11199 /* We check for an absolute prefix (differentiating,
11200 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11201 if (*op_string
== ABSOLUTE_PREFIX
)
11204 if (is_space_char (*op_string
))
11206 i
.jumpabsolute
= TRUE
;
11209 /* Check if operand is a register. */
11210 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11212 i386_operand_type temp
;
11217 /* Check for a segment override by searching for ':' after a
11218 segment register. */
11219 op_string
= end_op
;
11220 if (is_space_char (*op_string
))
11222 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11224 switch (r
->reg_num
)
11227 i
.seg
[i
.mem_operands
] = &es
;
11230 i
.seg
[i
.mem_operands
] = &cs
;
11233 i
.seg
[i
.mem_operands
] = &ss
;
11236 i
.seg
[i
.mem_operands
] = &ds
;
11239 i
.seg
[i
.mem_operands
] = &fs
;
11242 i
.seg
[i
.mem_operands
] = &gs
;
11246 /* Skip the ':' and whitespace. */
11248 if (is_space_char (*op_string
))
11251 if (!is_digit_char (*op_string
)
11252 && !is_identifier_char (*op_string
)
11253 && *op_string
!= '('
11254 && *op_string
!= ABSOLUTE_PREFIX
)
11256 as_bad (_("bad memory operand `%s'"), op_string
);
11259 /* Handle case of %es:*foo. */
11260 if (*op_string
== ABSOLUTE_PREFIX
)
11263 if (is_space_char (*op_string
))
11265 i
.jumpabsolute
= TRUE
;
11267 goto do_memory_reference
;
11270 /* Handle vector operations. */
11271 if (*op_string
== '{')
11273 op_string
= check_VecOperations (op_string
, NULL
);
11274 if (op_string
== NULL
)
11280 as_bad (_("junk `%s' after register"), op_string
);
11283 temp
= r
->reg_type
;
11284 temp
.bitfield
.baseindex
= 0;
11285 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11287 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11288 i
.op
[this_operand
].regs
= r
;
11291 else if (*op_string
== REGISTER_PREFIX
)
11293 as_bad (_("bad register name `%s'"), op_string
);
11296 else if (*op_string
== IMMEDIATE_PREFIX
)
11299 if (i
.jumpabsolute
)
11301 as_bad (_("immediate operand illegal with absolute jump"));
11304 if (!i386_immediate (op_string
))
11307 else if (RC_SAE_immediate (operand_string
))
11309 /* If it is a RC or SAE immediate, do nothing. */
11312 else if (is_digit_char (*op_string
)
11313 || is_identifier_char (*op_string
)
11314 || *op_string
== '"'
11315 || *op_string
== '(')
11317 /* This is a memory reference of some sort. */
11320 /* Start and end of displacement string expression (if found). */
11321 char *displacement_string_start
;
11322 char *displacement_string_end
;
11325 do_memory_reference
:
11326 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11328 if ((i
.mem_operands
== 1
11329 && !current_templates
->start
->opcode_modifier
.isstring
)
11330 || i
.mem_operands
== 2)
11332 as_bad (_("too many memory references for `%s'"),
11333 current_templates
->start
->name
);
11337 /* Check for base index form. We detect the base index form by
11338 looking for an ')' at the end of the operand, searching
11339 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11341 base_string
= op_string
+ strlen (op_string
);
11343 /* Handle vector operations. */
11344 vop_start
= strchr (op_string
, '{');
11345 if (vop_start
&& vop_start
< base_string
)
11347 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11349 base_string
= vop_start
;
11353 if (is_space_char (*base_string
))
11356 /* If we only have a displacement, set-up for it to be parsed later. */
11357 displacement_string_start
= op_string
;
11358 displacement_string_end
= base_string
+ 1;
11360 if (*base_string
== ')')
11363 unsigned int parens_balanced
= 1;
11364 /* We've already checked that the number of left & right ()'s are
11365 equal, so this loop will not be infinite. */
11369 if (*base_string
== ')')
11371 if (*base_string
== '(')
11374 while (parens_balanced
);
11376 temp_string
= base_string
;
11378 /* Skip past '(' and whitespace. */
11380 if (is_space_char (*base_string
))
11383 if (*base_string
== ','
11384 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11387 displacement_string_end
= temp_string
;
11389 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11393 if (i
.base_reg
== &bad_reg
)
11395 base_string
= end_op
;
11396 if (is_space_char (*base_string
))
11400 /* There may be an index reg or scale factor here. */
11401 if (*base_string
== ',')
11404 if (is_space_char (*base_string
))
11407 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11410 if (i
.index_reg
== &bad_reg
)
11412 base_string
= end_op
;
11413 if (is_space_char (*base_string
))
11415 if (*base_string
== ',')
11418 if (is_space_char (*base_string
))
11421 else if (*base_string
!= ')')
11423 as_bad (_("expecting `,' or `)' "
11424 "after index register in `%s'"),
11429 else if (*base_string
== REGISTER_PREFIX
)
11431 end_op
= strchr (base_string
, ',');
11434 as_bad (_("bad register name `%s'"), base_string
);
11438 /* Check for scale factor. */
11439 if (*base_string
!= ')')
11441 char *end_scale
= i386_scale (base_string
);
11446 base_string
= end_scale
;
11447 if (is_space_char (*base_string
))
11449 if (*base_string
!= ')')
11451 as_bad (_("expecting `)' "
11452 "after scale factor in `%s'"),
11457 else if (!i
.index_reg
)
11459 as_bad (_("expecting index register or scale factor "
11460 "after `,'; got '%c'"),
11465 else if (*base_string
!= ')')
11467 as_bad (_("expecting `,' or `)' "
11468 "after base register in `%s'"),
11473 else if (*base_string
== REGISTER_PREFIX
)
11475 end_op
= strchr (base_string
, ',');
11478 as_bad (_("bad register name `%s'"), base_string
);
11483 /* If there's an expression beginning the operand, parse it,
11484 assuming displacement_string_start and
11485 displacement_string_end are meaningful. */
11486 if (displacement_string_start
!= displacement_string_end
)
11488 if (!i386_displacement (displacement_string_start
,
11489 displacement_string_end
))
11493 /* Special case for (%dx) while doing input/output op. */
11495 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11496 && i
.base_reg
->reg_type
.bitfield
.word
11497 && i
.index_reg
== 0
11498 && i
.log2_scale_factor
== 0
11499 && i
.seg
[i
.mem_operands
] == 0
11500 && !operand_type_check (i
.types
[this_operand
], disp
))
11502 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11506 if (i386_index_check (operand_string
) == 0)
11508 i
.flags
[this_operand
] |= Operand_Mem
;
11509 if (i
.mem_operands
== 0)
11510 i
.memop1_string
= xstrdup (operand_string
);
11515 /* It's not a memory operand; argh! */
11516 as_bad (_("invalid char %s beginning operand %d `%s'"),
11517 output_invalid (*op_string
),
11522 return 1; /* Normal return. */
11525 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11526 that an rs_machine_dependent frag may reach. */
11529 i386_frag_max_var (fragS
*frag
)
11531 /* The only relaxable frags are for jumps.
11532 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11533 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11534 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11537 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11539 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11541 /* STT_GNU_IFUNC symbol must go through PLT. */
11542 if ((symbol_get_bfdsym (fr_symbol
)->flags
11543 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11546 if (!S_IS_EXTERNAL (fr_symbol
))
11547 /* Symbol may be weak or local. */
11548 return !S_IS_WEAK (fr_symbol
);
11550 /* Global symbols with non-default visibility can't be preempted. */
11551 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11554 if (fr_var
!= NO_RELOC
)
11555 switch ((enum bfd_reloc_code_real
) fr_var
)
11557 case BFD_RELOC_386_PLT32
:
11558 case BFD_RELOC_X86_64_PLT32
:
11559 /* Symbol with PLT relocation may be preempted. */
11565 /* Global symbols with default visibility in a shared library may be
11566 preempted by another definition. */
11571 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11572 Note also work for Skylake and Cascadelake.
11573 ---------------------------------------------------------------------
11574 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11575 | ------ | ----------- | ------- | -------- |
11577 | Jno | N | N | Y |
11578 | Jc/Jb | Y | N | Y |
11579 | Jae/Jnb | Y | N | Y |
11580 | Je/Jz | Y | Y | Y |
11581 | Jne/Jnz | Y | Y | Y |
11582 | Jna/Jbe | Y | N | Y |
11583 | Ja/Jnbe | Y | N | Y |
11585 | Jns | N | N | Y |
11586 | Jp/Jpe | N | N | Y |
11587 | Jnp/Jpo | N | N | Y |
11588 | Jl/Jnge | Y | Y | Y |
11589 | Jge/Jnl | Y | Y | Y |
11590 | Jle/Jng | Y | Y | Y |
11591 | Jg/Jnle | Y | Y | Y |
11592 --------------------------------------------------------------------- */
11594 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11596 if (mf_cmp
== mf_cmp_alu_cmp
)
11597 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11598 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11599 if (mf_cmp
== mf_cmp_incdec
)
11600 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11601 || mf_jcc
== mf_jcc_jle
);
11602 if (mf_cmp
== mf_cmp_test_and
)
11607 /* Return the next non-empty frag. */
11610 i386_next_non_empty_frag (fragS
*fragP
)
11612 /* There may be a frag with a ".fill 0" when there is no room in
11613 the current frag for frag_grow in output_insn. */
11614 for (fragP
= fragP
->fr_next
;
11616 && fragP
->fr_type
== rs_fill
11617 && fragP
->fr_fix
== 0);
11618 fragP
= fragP
->fr_next
)
11623 /* Return the next jcc frag after BRANCH_PADDING. */
11626 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11628 fragS
*branch_fragP
;
11632 if (pad_fragP
->fr_type
== rs_machine_dependent
11633 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11634 == BRANCH_PADDING
))
11636 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11637 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11639 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11640 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11641 pad_fragP
->tc_frag_data
.mf_type
))
11642 return branch_fragP
;
11648 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11651 i386_classify_machine_dependent_frag (fragS
*fragP
)
11655 fragS
*branch_fragP
;
11657 unsigned int max_prefix_length
;
11659 if (fragP
->tc_frag_data
.classified
)
11662 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11663 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11664 for (next_fragP
= fragP
;
11665 next_fragP
!= NULL
;
11666 next_fragP
= next_fragP
->fr_next
)
11668 next_fragP
->tc_frag_data
.classified
= 1;
11669 if (next_fragP
->fr_type
== rs_machine_dependent
)
11670 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11672 case BRANCH_PADDING
:
11673 /* The BRANCH_PADDING frag must be followed by a branch
11675 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11676 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11678 case FUSED_JCC_PADDING
:
11679 /* Check if this is a fused jcc:
11681 CMP like instruction
11685 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11686 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11687 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11690 /* The BRANCH_PADDING frag is merged with the
11691 FUSED_JCC_PADDING frag. */
11692 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11693 /* CMP like instruction size. */
11694 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11695 frag_wane (pad_fragP
);
11696 /* Skip to branch_fragP. */
11697 next_fragP
= branch_fragP
;
11699 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11701 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11703 next_fragP
->fr_subtype
11704 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11705 next_fragP
->tc_frag_data
.max_bytes
11706 = next_fragP
->tc_frag_data
.max_prefix_length
;
11707 /* This will be updated in the BRANCH_PREFIX scan. */
11708 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11711 frag_wane (next_fragP
);
11716 /* Stop if there is no BRANCH_PREFIX. */
11717 if (!align_branch_prefix_size
)
11720 /* Scan for BRANCH_PREFIX. */
11721 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11723 if (fragP
->fr_type
!= rs_machine_dependent
11724 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11728 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11729 COND_JUMP_PREFIX. */
11730 max_prefix_length
= 0;
11731 for (next_fragP
= fragP
;
11732 next_fragP
!= NULL
;
11733 next_fragP
= next_fragP
->fr_next
)
11735 if (next_fragP
->fr_type
== rs_fill
)
11736 /* Skip rs_fill frags. */
11738 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11739 /* Stop for all other frags. */
11742 /* rs_machine_dependent frags. */
11743 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11746 /* Count BRANCH_PREFIX frags. */
11747 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11749 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11750 frag_wane (next_fragP
);
11754 += next_fragP
->tc_frag_data
.max_bytes
;
11756 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11758 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11759 == FUSED_JCC_PADDING
))
11761 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11762 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11766 /* Stop for other rs_machine_dependent frags. */
11770 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11772 /* Skip to the next frag. */
11773 fragP
= next_fragP
;
11777 /* Compute padding size for
11780 CMP like instruction
11782 COND_JUMP/UNCOND_JUMP
11787 COND_JUMP/UNCOND_JUMP
11791 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11793 unsigned int offset
, size
, padding_size
;
11794 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11796 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11798 address
= fragP
->fr_address
;
11799 address
+= fragP
->fr_fix
;
11801 /* CMP like instrunction size. */
11802 size
= fragP
->tc_frag_data
.cmp_size
;
11804 /* The base size of the branch frag. */
11805 size
+= branch_fragP
->fr_fix
;
11807 /* Add opcode and displacement bytes for the rs_machine_dependent
11809 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11810 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11812 /* Check if branch is within boundary and doesn't end at the last
11814 offset
= address
& ((1U << align_branch_power
) - 1);
11815 if ((offset
+ size
) >= (1U << align_branch_power
))
11816 /* Padding needed to avoid crossing boundary. */
11817 padding_size
= (1U << align_branch_power
) - offset
;
11819 /* No padding needed. */
11822 /* The return value may be saved in tc_frag_data.length which is
11824 if (!fits_in_unsigned_byte (padding_size
))
11827 return padding_size
;
11830 /* i386_generic_table_relax_frag()
11832 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11833 grow/shrink padding to align branch frags. Hand others to
11837 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11839 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11840 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11842 long padding_size
= i386_branch_padding_size (fragP
, 0);
11843 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11845 /* When the BRANCH_PREFIX frag is used, the computed address
11846 must match the actual address and there should be no padding. */
11847 if (fragP
->tc_frag_data
.padding_address
11848 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11852 /* Update the padding size. */
11854 fragP
->tc_frag_data
.length
= padding_size
;
11858 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11860 fragS
*padding_fragP
, *next_fragP
;
11861 long padding_size
, left_size
, last_size
;
11863 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11864 if (!padding_fragP
)
11865 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11866 return (fragP
->tc_frag_data
.length
11867 - fragP
->tc_frag_data
.last_length
);
11869 /* Compute the relative address of the padding frag in the very
11870 first time where the BRANCH_PREFIX frag sizes are zero. */
11871 if (!fragP
->tc_frag_data
.padding_address
)
11872 fragP
->tc_frag_data
.padding_address
11873 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11875 /* First update the last length from the previous interation. */
11876 left_size
= fragP
->tc_frag_data
.prefix_length
;
11877 for (next_fragP
= fragP
;
11878 next_fragP
!= padding_fragP
;
11879 next_fragP
= next_fragP
->fr_next
)
11880 if (next_fragP
->fr_type
== rs_machine_dependent
11881 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11886 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11890 if (max
> left_size
)
11895 next_fragP
->tc_frag_data
.last_length
= size
;
11899 next_fragP
->tc_frag_data
.last_length
= 0;
11902 /* Check the padding size for the padding frag. */
11903 padding_size
= i386_branch_padding_size
11904 (padding_fragP
, (fragP
->fr_address
11905 + fragP
->tc_frag_data
.padding_address
));
11907 last_size
= fragP
->tc_frag_data
.prefix_length
;
11908 /* Check if there is change from the last interation. */
11909 if (padding_size
== last_size
)
11911 /* Update the expected address of the padding frag. */
11912 padding_fragP
->tc_frag_data
.padding_address
11913 = (fragP
->fr_address
+ padding_size
11914 + fragP
->tc_frag_data
.padding_address
);
11918 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11920 /* No padding if there is no sufficient room. Clear the
11921 expected address of the padding frag. */
11922 padding_fragP
->tc_frag_data
.padding_address
= 0;
11926 /* Store the expected address of the padding frag. */
11927 padding_fragP
->tc_frag_data
.padding_address
11928 = (fragP
->fr_address
+ padding_size
11929 + fragP
->tc_frag_data
.padding_address
);
11931 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11933 /* Update the length for the current interation. */
11934 left_size
= padding_size
;
11935 for (next_fragP
= fragP
;
11936 next_fragP
!= padding_fragP
;
11937 next_fragP
= next_fragP
->fr_next
)
11938 if (next_fragP
->fr_type
== rs_machine_dependent
11939 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11944 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11948 if (max
> left_size
)
11953 next_fragP
->tc_frag_data
.length
= size
;
11957 next_fragP
->tc_frag_data
.length
= 0;
11960 return (fragP
->tc_frag_data
.length
11961 - fragP
->tc_frag_data
.last_length
);
11963 return relax_frag (segment
, fragP
, stretch
);
11966 /* md_estimate_size_before_relax()
11968 Called just before relax() for rs_machine_dependent frags. The x86
11969 assembler uses these frags to handle variable size jump
11972 Any symbol that is now undefined will not become defined.
11973 Return the correct fr_subtype in the frag.
11974 Return the initial "guess for variable size of frag" to caller.
11975 The guess is actually the growth beyond the fixed part. Whatever
11976 we do to grow the fixed or variable part contributes to our
11980 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11982 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11983 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11984 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11986 i386_classify_machine_dependent_frag (fragP
);
11987 return fragP
->tc_frag_data
.length
;
11990 /* We've already got fragP->fr_subtype right; all we have to do is
11991 check for un-relaxable symbols. On an ELF system, we can't relax
11992 an externally visible symbol, because it may be overridden by a
11994 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11995 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11997 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12000 #if defined (OBJ_COFF) && defined (TE_PE)
12001 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12002 && S_IS_WEAK (fragP
->fr_symbol
))
12006 /* Symbol is undefined in this segment, or we need to keep a
12007 reloc so that weak symbols can be overridden. */
12008 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12009 enum bfd_reloc_code_real reloc_type
;
12010 unsigned char *opcode
;
12013 if (fragP
->fr_var
!= NO_RELOC
)
12014 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12015 else if (size
== 2)
12016 reloc_type
= BFD_RELOC_16_PCREL
;
12017 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12018 else if (need_plt32_p (fragP
->fr_symbol
))
12019 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12022 reloc_type
= BFD_RELOC_32_PCREL
;
12024 old_fr_fix
= fragP
->fr_fix
;
12025 opcode
= (unsigned char *) fragP
->fr_opcode
;
12027 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12030 /* Make jmp (0xeb) a (d)word displacement jump. */
12032 fragP
->fr_fix
+= size
;
12033 fix_new (fragP
, old_fr_fix
, size
,
12035 fragP
->fr_offset
, 1,
12041 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12043 /* Negate the condition, and branch past an
12044 unconditional jump. */
12047 /* Insert an unconditional jump. */
12049 /* We added two extra opcode bytes, and have a two byte
12051 fragP
->fr_fix
+= 2 + 2;
12052 fix_new (fragP
, old_fr_fix
+ 2, 2,
12054 fragP
->fr_offset
, 1,
12058 /* Fall through. */
12061 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12065 fragP
->fr_fix
+= 1;
12066 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12068 fragP
->fr_offset
, 1,
12069 BFD_RELOC_8_PCREL
);
12070 fixP
->fx_signed
= 1;
12074 /* This changes the byte-displacement jump 0x7N
12075 to the (d)word-displacement jump 0x0f,0x8N. */
12076 opcode
[1] = opcode
[0] + 0x10;
12077 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12078 /* We've added an opcode byte. */
12079 fragP
->fr_fix
+= 1 + size
;
12080 fix_new (fragP
, old_fr_fix
+ 1, size
,
12082 fragP
->fr_offset
, 1,
12087 BAD_CASE (fragP
->fr_subtype
);
12091 return fragP
->fr_fix
- old_fr_fix
;
12094 /* Guess size depending on current relax state. Initially the relax
12095 state will correspond to a short jump and we return 1, because
12096 the variable part of the frag (the branch offset) is one byte
12097 long. However, we can relax a section more than once and in that
12098 case we must either set fr_subtype back to the unrelaxed state,
12099 or return the value for the appropriate branch. */
12100 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12103 /* Called after relax() is finished.
12105 In: Address of frag.
12106 fr_type == rs_machine_dependent.
12107 fr_subtype is what the address relaxed to.
12109 Out: Any fixSs and constants are set up.
12110 Caller will turn frag into a ".space 0". */
12113 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12116 unsigned char *opcode
;
12117 unsigned char *where_to_put_displacement
= NULL
;
12118 offsetT target_address
;
12119 offsetT opcode_address
;
12120 unsigned int extension
= 0;
12121 offsetT displacement_from_opcode_start
;
12123 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12124 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12125 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12127 /* Generate nop padding. */
12128 unsigned int size
= fragP
->tc_frag_data
.length
;
12131 if (size
> fragP
->tc_frag_data
.max_bytes
)
12137 const char *branch
= "branch";
12138 const char *prefix
= "";
12139 fragS
*padding_fragP
;
12140 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12143 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12144 switch (fragP
->tc_frag_data
.default_prefix
)
12149 case CS_PREFIX_OPCODE
:
12152 case DS_PREFIX_OPCODE
:
12155 case ES_PREFIX_OPCODE
:
12158 case FS_PREFIX_OPCODE
:
12161 case GS_PREFIX_OPCODE
:
12164 case SS_PREFIX_OPCODE
:
12169 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12170 "%s within %d-byte boundary\n");
12172 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12173 "align %s within %d-byte boundary\n");
12177 padding_fragP
= fragP
;
12178 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12179 "%s within %d-byte boundary\n");
12183 switch (padding_fragP
->tc_frag_data
.branch_type
)
12185 case align_branch_jcc
:
12188 case align_branch_fused
:
12189 branch
= "fused jcc";
12191 case align_branch_jmp
:
12194 case align_branch_call
:
12197 case align_branch_indirect
:
12198 branch
= "indiret branch";
12200 case align_branch_ret
:
12207 fprintf (stdout
, msg
,
12208 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12209 (long long) fragP
->fr_address
, branch
,
12210 1 << align_branch_power
);
12212 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12213 memset (fragP
->fr_opcode
,
12214 fragP
->tc_frag_data
.default_prefix
, size
);
12216 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12218 fragP
->fr_fix
+= size
;
12223 opcode
= (unsigned char *) fragP
->fr_opcode
;
12225 /* Address we want to reach in file space. */
12226 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12228 /* Address opcode resides at in file space. */
12229 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12231 /* Displacement from opcode start to fill into instruction. */
12232 displacement_from_opcode_start
= target_address
- opcode_address
;
12234 if ((fragP
->fr_subtype
& BIG
) == 0)
12236 /* Don't have to change opcode. */
12237 extension
= 1; /* 1 opcode + 1 displacement */
12238 where_to_put_displacement
= &opcode
[1];
12242 if (no_cond_jump_promotion
12243 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12244 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12245 _("long jump required"));
12247 switch (fragP
->fr_subtype
)
12249 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12250 extension
= 4; /* 1 opcode + 4 displacement */
12252 where_to_put_displacement
= &opcode
[1];
12255 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12256 extension
= 2; /* 1 opcode + 2 displacement */
12258 where_to_put_displacement
= &opcode
[1];
12261 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12262 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12263 extension
= 5; /* 2 opcode + 4 displacement */
12264 opcode
[1] = opcode
[0] + 0x10;
12265 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12266 where_to_put_displacement
= &opcode
[2];
12269 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12270 extension
= 3; /* 2 opcode + 2 displacement */
12271 opcode
[1] = opcode
[0] + 0x10;
12272 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12273 where_to_put_displacement
= &opcode
[2];
12276 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12281 where_to_put_displacement
= &opcode
[3];
12285 BAD_CASE (fragP
->fr_subtype
);
12290 /* If size if less then four we are sure that the operand fits,
12291 but if it's 4, then it could be that the displacement is larger
12293 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12295 && ((addressT
) (displacement_from_opcode_start
- extension
12296 + ((addressT
) 1 << 31))
12297 > (((addressT
) 2 << 31) - 1)))
12299 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12300 _("jump target out of range"));
12301 /* Make us emit 0. */
12302 displacement_from_opcode_start
= extension
;
12304 /* Now put displacement after opcode. */
12305 md_number_to_chars ((char *) where_to_put_displacement
,
12306 (valueT
) (displacement_from_opcode_start
- extension
),
12307 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12308 fragP
->fr_fix
+= extension
;
12311 /* Apply a fixup (fixP) to segment data, once it has been determined
12312 by our caller that we have all the info we need to fix it up.
12314 Parameter valP is the pointer to the value of the bits.
12316 On the 386, immediates, displacements, and data pointers are all in
12317 the same (little-endian) format, so we don't need to care about which
12318 we are handling. */
12321 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12323 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12324 valueT value
= *valP
;
12326 #if !defined (TE_Mach)
12327 if (fixP
->fx_pcrel
)
12329 switch (fixP
->fx_r_type
)
12335 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12338 case BFD_RELOC_X86_64_32S
:
12339 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12342 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12345 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12350 if (fixP
->fx_addsy
!= NULL
12351 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12352 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12353 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12354 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12355 && !use_rela_relocations
)
12357 /* This is a hack. There should be a better way to handle this.
12358 This covers for the fact that bfd_install_relocation will
12359 subtract the current location (for partial_inplace, PC relative
12360 relocations); see more below. */
12364 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12367 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12369 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12372 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12374 if ((sym_seg
== seg
12375 || (symbol_section_p (fixP
->fx_addsy
)
12376 && sym_seg
!= absolute_section
))
12377 && !generic_force_reloc (fixP
))
12379 /* Yes, we add the values in twice. This is because
12380 bfd_install_relocation subtracts them out again. I think
12381 bfd_install_relocation is broken, but I don't dare change
12383 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12387 #if defined (OBJ_COFF) && defined (TE_PE)
12388 /* For some reason, the PE format does not store a
12389 section address offset for a PC relative symbol. */
12390 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12391 || S_IS_WEAK (fixP
->fx_addsy
))
12392 value
+= md_pcrel_from (fixP
);
12395 #if defined (OBJ_COFF) && defined (TE_PE)
12396 if (fixP
->fx_addsy
!= NULL
12397 && S_IS_WEAK (fixP
->fx_addsy
)
12398 /* PR 16858: Do not modify weak function references. */
12399 && ! fixP
->fx_pcrel
)
12401 #if !defined (TE_PEP)
12402 /* For x86 PE weak function symbols are neither PC-relative
12403 nor do they set S_IS_FUNCTION. So the only reliable way
12404 to detect them is to check the flags of their containing
12406 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12407 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12411 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12415 /* Fix a few things - the dynamic linker expects certain values here,
12416 and we must not disappoint it. */
12417 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12418 if (IS_ELF
&& fixP
->fx_addsy
)
12419 switch (fixP
->fx_r_type
)
12421 case BFD_RELOC_386_PLT32
:
12422 case BFD_RELOC_X86_64_PLT32
:
12423 /* Make the jump instruction point to the address of the operand.
12424 At runtime we merely add the offset to the actual PLT entry.
12425 NB: Subtract the offset size only for jump instructions. */
12426 if (fixP
->fx_pcrel
)
12430 case BFD_RELOC_386_TLS_GD
:
12431 case BFD_RELOC_386_TLS_LDM
:
12432 case BFD_RELOC_386_TLS_IE_32
:
12433 case BFD_RELOC_386_TLS_IE
:
12434 case BFD_RELOC_386_TLS_GOTIE
:
12435 case BFD_RELOC_386_TLS_GOTDESC
:
12436 case BFD_RELOC_X86_64_TLSGD
:
12437 case BFD_RELOC_X86_64_TLSLD
:
12438 case BFD_RELOC_X86_64_GOTTPOFF
:
12439 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12440 value
= 0; /* Fully resolved at runtime. No addend. */
12442 case BFD_RELOC_386_TLS_LE
:
12443 case BFD_RELOC_386_TLS_LDO_32
:
12444 case BFD_RELOC_386_TLS_LE_32
:
12445 case BFD_RELOC_X86_64_DTPOFF32
:
12446 case BFD_RELOC_X86_64_DTPOFF64
:
12447 case BFD_RELOC_X86_64_TPOFF32
:
12448 case BFD_RELOC_X86_64_TPOFF64
:
12449 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12452 case BFD_RELOC_386_TLS_DESC_CALL
:
12453 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12454 value
= 0; /* Fully resolved at runtime. No addend. */
12455 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12459 case BFD_RELOC_VTABLE_INHERIT
:
12460 case BFD_RELOC_VTABLE_ENTRY
:
12467 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12469 #endif /* !defined (TE_Mach) */
12471 /* Are we finished with this relocation now? */
12472 if (fixP
->fx_addsy
== NULL
)
12474 #if defined (OBJ_COFF) && defined (TE_PE)
12475 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12478 /* Remember value for tc_gen_reloc. */
12479 fixP
->fx_addnumber
= value
;
12480 /* Clear out the frag for now. */
12484 else if (use_rela_relocations
)
12486 fixP
->fx_no_overflow
= 1;
12487 /* Remember value for tc_gen_reloc. */
12488 fixP
->fx_addnumber
= value
;
12492 md_number_to_chars (p
, value
, fixP
->fx_size
);
12496 md_atof (int type
, char *litP
, int *sizeP
)
12498 /* This outputs the LITTLENUMs in REVERSE order;
12499 in accord with the bigendian 386. */
12500 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12503 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12506 output_invalid (int c
)
12509 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12512 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12513 "(0x%x)", (unsigned char) c
);
12514 return output_invalid_buf
;
12517 /* Verify that @r can be used in the current context. */
12519 static bfd_boolean
check_register (const reg_entry
*r
)
12521 if (allow_pseudo_reg
)
12524 if (operand_type_all_zero (&r
->reg_type
))
12527 if ((r
->reg_type
.bitfield
.dword
12528 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12529 || r
->reg_type
.bitfield
.class == RegCR
12530 || r
->reg_type
.bitfield
.class == RegDR
)
12531 && !cpu_arch_flags
.bitfield
.cpui386
)
12534 if (r
->reg_type
.bitfield
.class == RegTR
12535 && (flag_code
== CODE_64BIT
12536 || !cpu_arch_flags
.bitfield
.cpui386
12537 || cpu_arch_isa_flags
.bitfield
.cpui586
12538 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12541 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12544 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12546 if (r
->reg_type
.bitfield
.zmmword
12547 || r
->reg_type
.bitfield
.class == RegMask
)
12550 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12552 if (r
->reg_type
.bitfield
.ymmword
)
12555 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12560 if (r
->reg_type
.bitfield
.tmmword
12561 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12562 || flag_code
!= CODE_64BIT
))
12565 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12568 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12569 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12572 /* Upper 16 vector registers are only available with VREX in 64bit
12573 mode, and require EVEX encoding. */
12574 if (r
->reg_flags
& RegVRex
)
12576 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12577 || flag_code
!= CODE_64BIT
)
12580 if (i
.vec_encoding
== vex_encoding_default
)
12581 i
.vec_encoding
= vex_encoding_evex
;
12582 else if (i
.vec_encoding
!= vex_encoding_evex
)
12583 i
.vec_encoding
= vex_encoding_error
;
12586 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12587 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12588 && flag_code
!= CODE_64BIT
)
12591 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12598 /* REG_STRING starts *before* REGISTER_PREFIX. */
12600 static const reg_entry
*
12601 parse_real_register (char *reg_string
, char **end_op
)
12603 char *s
= reg_string
;
12605 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12606 const reg_entry
*r
;
12608 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12609 if (*s
== REGISTER_PREFIX
)
12612 if (is_space_char (*s
))
12615 p
= reg_name_given
;
12616 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12618 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12619 return (const reg_entry
*) NULL
;
12623 /* For naked regs, make sure that we are not dealing with an identifier.
12624 This prevents confusing an identifier like `eax_var' with register
12626 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12627 return (const reg_entry
*) NULL
;
12631 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12633 /* Handle floating point regs, allowing spaces in the (i) part. */
12634 if (r
== i386_regtab
/* %st is first entry of table */)
12636 if (!cpu_arch_flags
.bitfield
.cpu8087
12637 && !cpu_arch_flags
.bitfield
.cpu287
12638 && !cpu_arch_flags
.bitfield
.cpu387
12639 && !allow_pseudo_reg
)
12640 return (const reg_entry
*) NULL
;
12642 if (is_space_char (*s
))
12647 if (is_space_char (*s
))
12649 if (*s
>= '0' && *s
<= '7')
12651 int fpr
= *s
- '0';
12653 if (is_space_char (*s
))
12658 r
= (const reg_entry
*) str_hash_find (reg_hash
, "st(0)");
12663 /* We have "%st(" then garbage. */
12664 return (const reg_entry
*) NULL
;
12668 return r
&& check_register (r
) ? r
: NULL
;
12671 /* REG_STRING starts *before* REGISTER_PREFIX. */
12673 static const reg_entry
*
12674 parse_register (char *reg_string
, char **end_op
)
12676 const reg_entry
*r
;
12678 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12679 r
= parse_real_register (reg_string
, end_op
);
12684 char *save
= input_line_pointer
;
12688 input_line_pointer
= reg_string
;
12689 c
= get_symbol_name (®_string
);
12690 symbolP
= symbol_find (reg_string
);
12691 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12693 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12695 know (e
->X_op
== O_register
);
12696 know (e
->X_add_number
>= 0
12697 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12698 r
= i386_regtab
+ e
->X_add_number
;
12699 if (!check_register (r
))
12701 as_bad (_("register '%s%s' cannot be used here"),
12702 register_prefix
, r
->reg_name
);
12705 *end_op
= input_line_pointer
;
12707 *input_line_pointer
= c
;
12708 input_line_pointer
= save
;
12714 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12716 const reg_entry
*r
;
12717 char *end
= input_line_pointer
;
12720 r
= parse_register (name
, &input_line_pointer
);
12721 if (r
&& end
<= input_line_pointer
)
12723 *nextcharP
= *input_line_pointer
;
12724 *input_line_pointer
= 0;
12727 e
->X_op
= O_register
;
12728 e
->X_add_number
= r
- i386_regtab
;
12731 e
->X_op
= O_illegal
;
12734 input_line_pointer
= end
;
12736 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12740 md_operand (expressionS
*e
)
12743 const reg_entry
*r
;
12745 switch (*input_line_pointer
)
12747 case REGISTER_PREFIX
:
12748 r
= parse_real_register (input_line_pointer
, &end
);
12751 e
->X_op
= O_register
;
12752 e
->X_add_number
= r
- i386_regtab
;
12753 input_line_pointer
= end
;
12758 gas_assert (intel_syntax
);
12759 end
= input_line_pointer
++;
12761 if (*input_line_pointer
== ']')
12763 ++input_line_pointer
;
12764 e
->X_op_symbol
= make_expr_symbol (e
);
12765 e
->X_add_symbol
= NULL
;
12766 e
->X_add_number
= 0;
12771 e
->X_op
= O_absent
;
12772 input_line_pointer
= end
;
12779 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12780 const char *md_shortopts
= "kVQ:sqnO::";
12782 const char *md_shortopts
= "qnO::";
12785 #define OPTION_32 (OPTION_MD_BASE + 0)
12786 #define OPTION_64 (OPTION_MD_BASE + 1)
12787 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12788 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12789 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12790 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12791 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12792 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12793 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12794 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12795 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12796 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12797 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12798 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12799 #define OPTION_X32 (OPTION_MD_BASE + 14)
12800 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12801 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12802 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12803 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12804 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12805 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12806 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12807 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12808 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12809 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12810 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12811 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12812 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12813 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12814 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12815 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12816 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12817 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12818 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12820 struct option md_longopts
[] =
12822 {"32", no_argument
, NULL
, OPTION_32
},
12823 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12824 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12825 {"64", no_argument
, NULL
, OPTION_64
},
12827 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12828 {"x32", no_argument
, NULL
, OPTION_X32
},
12829 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12830 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12832 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12833 {"march", required_argument
, NULL
, OPTION_MARCH
},
12834 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12835 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12836 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12837 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12838 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12839 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12840 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12841 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12842 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12843 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12844 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12845 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12846 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12847 # if defined (TE_PE) || defined (TE_PEP)
12848 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12850 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12851 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12852 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12853 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12854 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12855 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12856 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12857 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12858 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12859 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12860 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12861 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12862 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12863 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12864 {NULL
, no_argument
, NULL
, 0}
12866 size_t md_longopts_size
= sizeof (md_longopts
);
12869 md_parse_option (int c
, const char *arg
)
12872 char *arch
, *next
, *saved
, *type
;
12877 optimize_align_code
= 0;
12881 quiet_warnings
= 1;
12884 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12885 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12886 should be emitted or not. FIXME: Not implemented. */
12888 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12892 /* -V: SVR4 argument to print version ID. */
12894 print_version_id ();
12897 /* -k: Ignore for FreeBSD compatibility. */
12902 /* -s: On i386 Solaris, this tells the native assembler to use
12903 .stab instead of .stab.excl. We always use .stab anyhow. */
12906 case OPTION_MSHARED
:
12910 case OPTION_X86_USED_NOTE
:
12911 if (strcasecmp (arg
, "yes") == 0)
12913 else if (strcasecmp (arg
, "no") == 0)
12916 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12921 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12922 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12925 const char **list
, **l
;
12927 list
= bfd_target_list ();
12928 for (l
= list
; *l
!= NULL
; l
++)
12929 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12930 || strcmp (*l
, "coff-x86-64") == 0
12931 || strcmp (*l
, "pe-x86-64") == 0
12932 || strcmp (*l
, "pei-x86-64") == 0
12933 || strcmp (*l
, "mach-o-x86-64") == 0)
12935 default_arch
= "x86_64";
12939 as_fatal (_("no compiled in support for x86_64"));
12945 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12949 const char **list
, **l
;
12951 list
= bfd_target_list ();
12952 for (l
= list
; *l
!= NULL
; l
++)
12953 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12955 default_arch
= "x86_64:32";
12959 as_fatal (_("no compiled in support for 32bit x86_64"));
12963 as_fatal (_("32bit x86_64 is only supported for ELF"));
12968 default_arch
= "i386";
12971 case OPTION_DIVIDE
:
12972 #ifdef SVR4_COMMENT_CHARS
12977 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12979 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12983 i386_comment_chars
= n
;
12989 saved
= xstrdup (arg
);
12991 /* Allow -march=+nosse. */
12997 as_fatal (_("invalid -march= option: `%s'"), arg
);
12998 next
= strchr (arch
, '+');
13001 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13003 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13006 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13009 cpu_arch_name
= cpu_arch
[j
].name
;
13010 cpu_sub_arch_name
= NULL
;
13011 cpu_arch_flags
= cpu_arch
[j
].flags
;
13012 cpu_arch_isa
= cpu_arch
[j
].type
;
13013 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13014 if (!cpu_arch_tune_set
)
13016 cpu_arch_tune
= cpu_arch_isa
;
13017 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13021 else if (*cpu_arch
[j
].name
== '.'
13022 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13024 /* ISA extension. */
13025 i386_cpu_flags flags
;
13027 flags
= cpu_flags_or (cpu_arch_flags
,
13028 cpu_arch
[j
].flags
);
13030 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13032 if (cpu_sub_arch_name
)
13034 char *name
= cpu_sub_arch_name
;
13035 cpu_sub_arch_name
= concat (name
,
13037 (const char *) NULL
);
13041 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13042 cpu_arch_flags
= flags
;
13043 cpu_arch_isa_flags
= flags
;
13047 = cpu_flags_or (cpu_arch_isa_flags
,
13048 cpu_arch
[j
].flags
);
13053 if (j
>= ARRAY_SIZE (cpu_arch
))
13055 /* Disable an ISA extension. */
13056 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13057 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13059 i386_cpu_flags flags
;
13061 flags
= cpu_flags_and_not (cpu_arch_flags
,
13062 cpu_noarch
[j
].flags
);
13063 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13065 if (cpu_sub_arch_name
)
13067 char *name
= cpu_sub_arch_name
;
13068 cpu_sub_arch_name
= concat (arch
,
13069 (const char *) NULL
);
13073 cpu_sub_arch_name
= xstrdup (arch
);
13074 cpu_arch_flags
= flags
;
13075 cpu_arch_isa_flags
= flags
;
13080 if (j
>= ARRAY_SIZE (cpu_noarch
))
13081 j
= ARRAY_SIZE (cpu_arch
);
13084 if (j
>= ARRAY_SIZE (cpu_arch
))
13085 as_fatal (_("invalid -march= option: `%s'"), arg
);
13089 while (next
!= NULL
);
13095 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13096 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13098 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13100 cpu_arch_tune_set
= 1;
13101 cpu_arch_tune
= cpu_arch
[j
].type
;
13102 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13106 if (j
>= ARRAY_SIZE (cpu_arch
))
13107 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13110 case OPTION_MMNEMONIC
:
13111 if (strcasecmp (arg
, "att") == 0)
13112 intel_mnemonic
= 0;
13113 else if (strcasecmp (arg
, "intel") == 0)
13114 intel_mnemonic
= 1;
13116 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13119 case OPTION_MSYNTAX
:
13120 if (strcasecmp (arg
, "att") == 0)
13122 else if (strcasecmp (arg
, "intel") == 0)
13125 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13128 case OPTION_MINDEX_REG
:
13129 allow_index_reg
= 1;
13132 case OPTION_MNAKED_REG
:
13133 allow_naked_reg
= 1;
13136 case OPTION_MSSE2AVX
:
13140 case OPTION_MSSE_CHECK
:
13141 if (strcasecmp (arg
, "error") == 0)
13142 sse_check
= check_error
;
13143 else if (strcasecmp (arg
, "warning") == 0)
13144 sse_check
= check_warning
;
13145 else if (strcasecmp (arg
, "none") == 0)
13146 sse_check
= check_none
;
13148 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13151 case OPTION_MOPERAND_CHECK
:
13152 if (strcasecmp (arg
, "error") == 0)
13153 operand_check
= check_error
;
13154 else if (strcasecmp (arg
, "warning") == 0)
13155 operand_check
= check_warning
;
13156 else if (strcasecmp (arg
, "none") == 0)
13157 operand_check
= check_none
;
13159 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13162 case OPTION_MAVXSCALAR
:
13163 if (strcasecmp (arg
, "128") == 0)
13164 avxscalar
= vex128
;
13165 else if (strcasecmp (arg
, "256") == 0)
13166 avxscalar
= vex256
;
13168 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13171 case OPTION_MVEXWIG
:
13172 if (strcmp (arg
, "0") == 0)
13174 else if (strcmp (arg
, "1") == 0)
13177 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13180 case OPTION_MADD_BND_PREFIX
:
13181 add_bnd_prefix
= 1;
13184 case OPTION_MEVEXLIG
:
13185 if (strcmp (arg
, "128") == 0)
13186 evexlig
= evexl128
;
13187 else if (strcmp (arg
, "256") == 0)
13188 evexlig
= evexl256
;
13189 else if (strcmp (arg
, "512") == 0)
13190 evexlig
= evexl512
;
13192 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13195 case OPTION_MEVEXRCIG
:
13196 if (strcmp (arg
, "rne") == 0)
13198 else if (strcmp (arg
, "rd") == 0)
13200 else if (strcmp (arg
, "ru") == 0)
13202 else if (strcmp (arg
, "rz") == 0)
13205 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13208 case OPTION_MEVEXWIG
:
13209 if (strcmp (arg
, "0") == 0)
13211 else if (strcmp (arg
, "1") == 0)
13214 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13217 # if defined (TE_PE) || defined (TE_PEP)
13218 case OPTION_MBIG_OBJ
:
13223 case OPTION_MOMIT_LOCK_PREFIX
:
13224 if (strcasecmp (arg
, "yes") == 0)
13225 omit_lock_prefix
= 1;
13226 else if (strcasecmp (arg
, "no") == 0)
13227 omit_lock_prefix
= 0;
13229 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13232 case OPTION_MFENCE_AS_LOCK_ADD
:
13233 if (strcasecmp (arg
, "yes") == 0)
13235 else if (strcasecmp (arg
, "no") == 0)
13238 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13241 case OPTION_MLFENCE_AFTER_LOAD
:
13242 if (strcasecmp (arg
, "yes") == 0)
13243 lfence_after_load
= 1;
13244 else if (strcasecmp (arg
, "no") == 0)
13245 lfence_after_load
= 0;
13247 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13250 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13251 if (strcasecmp (arg
, "all") == 0)
13253 lfence_before_indirect_branch
= lfence_branch_all
;
13254 if (lfence_before_ret
== lfence_before_ret_none
)
13255 lfence_before_ret
= lfence_before_ret_shl
;
13257 else if (strcasecmp (arg
, "memory") == 0)
13258 lfence_before_indirect_branch
= lfence_branch_memory
;
13259 else if (strcasecmp (arg
, "register") == 0)
13260 lfence_before_indirect_branch
= lfence_branch_register
;
13261 else if (strcasecmp (arg
, "none") == 0)
13262 lfence_before_indirect_branch
= lfence_branch_none
;
13264 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13268 case OPTION_MLFENCE_BEFORE_RET
:
13269 if (strcasecmp (arg
, "or") == 0)
13270 lfence_before_ret
= lfence_before_ret_or
;
13271 else if (strcasecmp (arg
, "not") == 0)
13272 lfence_before_ret
= lfence_before_ret_not
;
13273 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13274 lfence_before_ret
= lfence_before_ret_shl
;
13275 else if (strcasecmp (arg
, "none") == 0)
13276 lfence_before_ret
= lfence_before_ret_none
;
13278 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13282 case OPTION_MRELAX_RELOCATIONS
:
13283 if (strcasecmp (arg
, "yes") == 0)
13284 generate_relax_relocations
= 1;
13285 else if (strcasecmp (arg
, "no") == 0)
13286 generate_relax_relocations
= 0;
13288 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13291 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13294 long int align
= strtoul (arg
, &end
, 0);
13299 align_branch_power
= 0;
13302 else if (align
>= 16)
13305 for (align_power
= 0;
13307 align
>>= 1, align_power
++)
13309 /* Limit alignment power to 31. */
13310 if (align
== 1 && align_power
< 32)
13312 align_branch_power
= align_power
;
13317 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13321 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13324 int align
= strtoul (arg
, &end
, 0);
13325 /* Some processors only support 5 prefixes. */
13326 if (*end
== '\0' && align
>= 0 && align
< 6)
13328 align_branch_prefix_size
= align
;
13331 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13336 case OPTION_MALIGN_BRANCH
:
13338 saved
= xstrdup (arg
);
13342 next
= strchr (type
, '+');
13345 if (strcasecmp (type
, "jcc") == 0)
13346 align_branch
|= align_branch_jcc_bit
;
13347 else if (strcasecmp (type
, "fused") == 0)
13348 align_branch
|= align_branch_fused_bit
;
13349 else if (strcasecmp (type
, "jmp") == 0)
13350 align_branch
|= align_branch_jmp_bit
;
13351 else if (strcasecmp (type
, "call") == 0)
13352 align_branch
|= align_branch_call_bit
;
13353 else if (strcasecmp (type
, "ret") == 0)
13354 align_branch
|= align_branch_ret_bit
;
13355 else if (strcasecmp (type
, "indirect") == 0)
13356 align_branch
|= align_branch_indirect_bit
;
13358 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13361 while (next
!= NULL
);
13365 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13366 align_branch_power
= 5;
13367 align_branch_prefix_size
= 5;
13368 align_branch
= (align_branch_jcc_bit
13369 | align_branch_fused_bit
13370 | align_branch_jmp_bit
);
13373 case OPTION_MAMD64
:
13377 case OPTION_MINTEL64
:
13385 /* Turn off -Os. */
13386 optimize_for_space
= 0;
13388 else if (*arg
== 's')
13390 optimize_for_space
= 1;
13391 /* Turn on all encoding optimizations. */
13392 optimize
= INT_MAX
;
13396 optimize
= atoi (arg
);
13397 /* Turn off -Os. */
13398 optimize_for_space
= 0;
13408 #define MESSAGE_TEMPLATE \
13412 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13413 int *left_p
, const char *name
, int len
)
13415 int size
= sizeof (MESSAGE_TEMPLATE
);
13416 int left
= *left_p
;
13418 /* Reserve 2 spaces for ", " or ",\0" */
13421 /* Check if there is any room. */
13429 p
= mempcpy (p
, name
, len
);
13433 /* Output the current message now and start a new one. */
13436 fprintf (stream
, "%s\n", message
);
13438 left
= size
- (start
- message
) - len
- 2;
13440 gas_assert (left
>= 0);
13442 p
= mempcpy (p
, name
, len
);
13450 show_arch (FILE *stream
, int ext
, int check
)
13452 static char message
[] = MESSAGE_TEMPLATE
;
13453 char *start
= message
+ 27;
13455 int size
= sizeof (MESSAGE_TEMPLATE
);
13462 left
= size
- (start
- message
);
13463 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13465 /* Should it be skipped? */
13466 if (cpu_arch
[j
].skip
)
13469 name
= cpu_arch
[j
].name
;
13470 len
= cpu_arch
[j
].len
;
13473 /* It is an extension. Skip if we aren't asked to show it. */
13484 /* It is an processor. Skip if we show only extension. */
13487 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13489 /* It is an impossible processor - skip. */
13493 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13496 /* Display disabled extensions. */
13498 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13500 name
= cpu_noarch
[j
].name
;
13501 len
= cpu_noarch
[j
].len
;
13502 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13507 fprintf (stream
, "%s\n", message
);
13511 md_show_usage (FILE *stream
)
13513 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13514 fprintf (stream
, _("\
13515 -Qy, -Qn ignored\n\
13516 -V print assembler version number\n\
13519 fprintf (stream
, _("\
13520 -n Do not optimize code alignment\n\
13521 -q quieten some warnings\n"));
13522 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13523 fprintf (stream
, _("\
13526 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13527 || defined (TE_PE) || defined (TE_PEP))
13528 fprintf (stream
, _("\
13529 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13531 #ifdef SVR4_COMMENT_CHARS
13532 fprintf (stream
, _("\
13533 --divide do not treat `/' as a comment character\n"));
13535 fprintf (stream
, _("\
13536 --divide ignored\n"));
13538 fprintf (stream
, _("\
13539 -march=CPU[,+EXTENSION...]\n\
13540 generate code for CPU and EXTENSION, CPU is one of:\n"));
13541 show_arch (stream
, 0, 1);
13542 fprintf (stream
, _("\
13543 EXTENSION is combination of:\n"));
13544 show_arch (stream
, 1, 0);
13545 fprintf (stream
, _("\
13546 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13547 show_arch (stream
, 0, 0);
13548 fprintf (stream
, _("\
13549 -msse2avx encode SSE instructions with VEX prefix\n"));
13550 fprintf (stream
, _("\
13551 -msse-check=[none|error|warning] (default: warning)\n\
13552 check SSE instructions\n"));
13553 fprintf (stream
, _("\
13554 -moperand-check=[none|error|warning] (default: warning)\n\
13555 check operand combinations for validity\n"));
13556 fprintf (stream
, _("\
13557 -mavxscalar=[128|256] (default: 128)\n\
13558 encode scalar AVX instructions with specific vector\n\
13560 fprintf (stream
, _("\
13561 -mvexwig=[0|1] (default: 0)\n\
13562 encode VEX instructions with specific VEX.W value\n\
13563 for VEX.W bit ignored instructions\n"));
13564 fprintf (stream
, _("\
13565 -mevexlig=[128|256|512] (default: 128)\n\
13566 encode scalar EVEX instructions with specific vector\n\
13568 fprintf (stream
, _("\
13569 -mevexwig=[0|1] (default: 0)\n\
13570 encode EVEX instructions with specific EVEX.W value\n\
13571 for EVEX.W bit ignored instructions\n"));
13572 fprintf (stream
, _("\
13573 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13574 encode EVEX instructions with specific EVEX.RC value\n\
13575 for SAE-only ignored instructions\n"));
13576 fprintf (stream
, _("\
13577 -mmnemonic=[att|intel] "));
13578 if (SYSV386_COMPAT
)
13579 fprintf (stream
, _("(default: att)\n"));
13581 fprintf (stream
, _("(default: intel)\n"));
13582 fprintf (stream
, _("\
13583 use AT&T/Intel mnemonic\n"));
13584 fprintf (stream
, _("\
13585 -msyntax=[att|intel] (default: att)\n\
13586 use AT&T/Intel syntax\n"));
13587 fprintf (stream
, _("\
13588 -mindex-reg support pseudo index registers\n"));
13589 fprintf (stream
, _("\
13590 -mnaked-reg don't require `%%' prefix for registers\n"));
13591 fprintf (stream
, _("\
13592 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13593 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13594 fprintf (stream
, _("\
13595 -mshared disable branch optimization for shared code\n"));
13596 fprintf (stream
, _("\
13597 -mx86-used-note=[no|yes] "));
13598 if (DEFAULT_X86_USED_NOTE
)
13599 fprintf (stream
, _("(default: yes)\n"));
13601 fprintf (stream
, _("(default: no)\n"));
13602 fprintf (stream
, _("\
13603 generate x86 used ISA and feature properties\n"));
13605 #if defined (TE_PE) || defined (TE_PEP)
13606 fprintf (stream
, _("\
13607 -mbig-obj generate big object files\n"));
13609 fprintf (stream
, _("\
13610 -momit-lock-prefix=[no|yes] (default: no)\n\
13611 strip all lock prefixes\n"));
13612 fprintf (stream
, _("\
13613 -mfence-as-lock-add=[no|yes] (default: no)\n\
13614 encode lfence, mfence and sfence as\n\
13615 lock addl $0x0, (%%{re}sp)\n"));
13616 fprintf (stream
, _("\
13617 -mrelax-relocations=[no|yes] "));
13618 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13619 fprintf (stream
, _("(default: yes)\n"));
13621 fprintf (stream
, _("(default: no)\n"));
13622 fprintf (stream
, _("\
13623 generate relax relocations\n"));
13624 fprintf (stream
, _("\
13625 -malign-branch-boundary=NUM (default: 0)\n\
13626 align branches within NUM byte boundary\n"));
13627 fprintf (stream
, _("\
13628 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13629 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13631 specify types of branches to align\n"));
13632 fprintf (stream
, _("\
13633 -malign-branch-prefix-size=NUM (default: 5)\n\
13634 align branches with NUM prefixes per instruction\n"));
13635 fprintf (stream
, _("\
13636 -mbranches-within-32B-boundaries\n\
13637 align branches within 32 byte boundary\n"));
13638 fprintf (stream
, _("\
13639 -mlfence-after-load=[no|yes] (default: no)\n\
13640 generate lfence after load\n"));
13641 fprintf (stream
, _("\
13642 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13643 generate lfence before indirect near branch\n"));
13644 fprintf (stream
, _("\
13645 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13646 generate lfence before ret\n"));
13647 fprintf (stream
, _("\
13648 -mamd64 accept only AMD64 ISA [default]\n"));
13649 fprintf (stream
, _("\
13650 -mintel64 accept only Intel64 ISA\n"));
13653 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13654 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13655 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13657 /* Pick the target format to use. */
13660 i386_target_format (void)
13662 if (!strncmp (default_arch
, "x86_64", 6))
13664 update_code_flag (CODE_64BIT
, 1);
13665 if (default_arch
[6] == '\0')
13666 x86_elf_abi
= X86_64_ABI
;
13668 x86_elf_abi
= X86_64_X32_ABI
;
13670 else if (!strcmp (default_arch
, "i386"))
13671 update_code_flag (CODE_32BIT
, 1);
13672 else if (!strcmp (default_arch
, "iamcu"))
13674 update_code_flag (CODE_32BIT
, 1);
13675 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13677 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13678 cpu_arch_name
= "iamcu";
13679 cpu_sub_arch_name
= NULL
;
13680 cpu_arch_flags
= iamcu_flags
;
13681 cpu_arch_isa
= PROCESSOR_IAMCU
;
13682 cpu_arch_isa_flags
= iamcu_flags
;
13683 if (!cpu_arch_tune_set
)
13685 cpu_arch_tune
= cpu_arch_isa
;
13686 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13689 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13690 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13694 as_fatal (_("unknown architecture"));
13696 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13697 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13698 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13699 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13701 switch (OUTPUT_FLAVOR
)
13703 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13704 case bfd_target_aout_flavour
:
13705 return AOUT_TARGET_FORMAT
;
13707 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13708 # if defined (TE_PE) || defined (TE_PEP)
13709 case bfd_target_coff_flavour
:
13710 if (flag_code
== CODE_64BIT
)
13711 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13713 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13714 # elif defined (TE_GO32)
13715 case bfd_target_coff_flavour
:
13716 return "coff-go32";
13718 case bfd_target_coff_flavour
:
13719 return "coff-i386";
13722 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13723 case bfd_target_elf_flavour
:
13725 const char *format
;
13727 switch (x86_elf_abi
)
13730 format
= ELF_TARGET_FORMAT
;
13732 tls_get_addr
= "___tls_get_addr";
13736 use_rela_relocations
= 1;
13739 tls_get_addr
= "__tls_get_addr";
13741 format
= ELF_TARGET_FORMAT64
;
13743 case X86_64_X32_ABI
:
13744 use_rela_relocations
= 1;
13747 tls_get_addr
= "__tls_get_addr";
13749 disallow_64bit_reloc
= 1;
13750 format
= ELF_TARGET_FORMAT32
;
13753 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13755 if (x86_elf_abi
!= X86_64_ABI
)
13756 as_fatal (_("Intel L1OM is 64bit only"));
13757 return ELF_TARGET_L1OM_FORMAT
;
13759 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13761 if (x86_elf_abi
!= X86_64_ABI
)
13762 as_fatal (_("Intel K1OM is 64bit only"));
13763 return ELF_TARGET_K1OM_FORMAT
;
13765 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13767 if (x86_elf_abi
!= I386_ABI
)
13768 as_fatal (_("Intel MCU is 32bit only"));
13769 return ELF_TARGET_IAMCU_FORMAT
;
13775 #if defined (OBJ_MACH_O)
13776 case bfd_target_mach_o_flavour
:
13777 if (flag_code
== CODE_64BIT
)
13779 use_rela_relocations
= 1;
13781 return "mach-o-x86-64";
13784 return "mach-o-i386";
13792 #endif /* OBJ_MAYBE_ more than one */
13795 md_undefined_symbol (char *name
)
13797 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13798 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13799 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13800 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13804 if (symbol_find (name
))
13805 as_bad (_("GOT already in symbol table"));
13806 GOT_symbol
= symbol_new (name
, undefined_section
,
13807 &zero_address_frag
, 0);
13814 /* Round up a section size to the appropriate boundary. */
13817 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13819 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13820 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13822 /* For a.out, force the section size to be aligned. If we don't do
13823 this, BFD will align it for us, but it will not write out the
13824 final bytes of the section. This may be a bug in BFD, but it is
13825 easier to fix it here since that is how the other a.out targets
13829 align
= bfd_section_alignment (segment
);
13830 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13837 /* On the i386, PC-relative offsets are relative to the start of the
13838 next instruction. That is, the address of the offset, plus its
13839 size, since the offset is always the last part of the insn. */
13842 md_pcrel_from (fixS
*fixP
)
13844 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13850 s_bss (int ignore ATTRIBUTE_UNUSED
)
13854 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13856 obj_elf_section_change_hook ();
13858 temp
= get_absolute_expression ();
13859 subseg_set (bss_section
, (subsegT
) temp
);
13860 demand_empty_rest_of_line ();
13865 /* Remember constant directive. */
13868 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13870 if (last_insn
.kind
!= last_insn_directive
13871 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13873 last_insn
.seg
= now_seg
;
13874 last_insn
.kind
= last_insn_directive
;
13875 last_insn
.name
= "constant directive";
13876 last_insn
.file
= as_where (&last_insn
.line
);
13877 if (lfence_before_ret
!= lfence_before_ret_none
)
13879 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13880 as_warn (_("constant directive skips -mlfence-before-ret "
13881 "and -mlfence-before-indirect-branch"));
13883 as_warn (_("constant directive skips -mlfence-before-ret"));
13885 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13886 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13891 i386_validate_fix (fixS
*fixp
)
13893 if (fixp
->fx_subsy
)
13895 if (fixp
->fx_subsy
== GOT_symbol
)
13897 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13901 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13902 if (fixp
->fx_tcbit2
)
13903 fixp
->fx_r_type
= (fixp
->fx_tcbit
13904 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13905 : BFD_RELOC_X86_64_GOTPCRELX
);
13908 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13913 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13915 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13917 fixp
->fx_subsy
= 0;
13920 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13923 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
13924 to section. Since PLT32 relocation must be against symbols,
13925 turn such PLT32 relocation into PC32 relocation. */
13927 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
13928 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
13929 && symbol_section_p (fixp
->fx_addsy
))
13930 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
13933 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13934 && fixp
->fx_tcbit2
)
13935 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13942 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13945 bfd_reloc_code_real_type code
;
13947 switch (fixp
->fx_r_type
)
13949 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13950 case BFD_RELOC_SIZE32
:
13951 case BFD_RELOC_SIZE64
:
13952 if (S_IS_DEFINED (fixp
->fx_addsy
)
13953 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13955 /* Resolve size relocation against local symbol to size of
13956 the symbol plus addend. */
13957 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13958 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13959 && !fits_in_unsigned_long (value
))
13960 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13961 _("symbol size computation overflow"));
13962 fixp
->fx_addsy
= NULL
;
13963 fixp
->fx_subsy
= NULL
;
13964 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13968 /* Fall through. */
13970 case BFD_RELOC_X86_64_PLT32
:
13971 case BFD_RELOC_X86_64_GOT32
:
13972 case BFD_RELOC_X86_64_GOTPCREL
:
13973 case BFD_RELOC_X86_64_GOTPCRELX
:
13974 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13975 case BFD_RELOC_386_PLT32
:
13976 case BFD_RELOC_386_GOT32
:
13977 case BFD_RELOC_386_GOT32X
:
13978 case BFD_RELOC_386_GOTOFF
:
13979 case BFD_RELOC_386_GOTPC
:
13980 case BFD_RELOC_386_TLS_GD
:
13981 case BFD_RELOC_386_TLS_LDM
:
13982 case BFD_RELOC_386_TLS_LDO_32
:
13983 case BFD_RELOC_386_TLS_IE_32
:
13984 case BFD_RELOC_386_TLS_IE
:
13985 case BFD_RELOC_386_TLS_GOTIE
:
13986 case BFD_RELOC_386_TLS_LE_32
:
13987 case BFD_RELOC_386_TLS_LE
:
13988 case BFD_RELOC_386_TLS_GOTDESC
:
13989 case BFD_RELOC_386_TLS_DESC_CALL
:
13990 case BFD_RELOC_X86_64_TLSGD
:
13991 case BFD_RELOC_X86_64_TLSLD
:
13992 case BFD_RELOC_X86_64_DTPOFF32
:
13993 case BFD_RELOC_X86_64_DTPOFF64
:
13994 case BFD_RELOC_X86_64_GOTTPOFF
:
13995 case BFD_RELOC_X86_64_TPOFF32
:
13996 case BFD_RELOC_X86_64_TPOFF64
:
13997 case BFD_RELOC_X86_64_GOTOFF64
:
13998 case BFD_RELOC_X86_64_GOTPC32
:
13999 case BFD_RELOC_X86_64_GOT64
:
14000 case BFD_RELOC_X86_64_GOTPCREL64
:
14001 case BFD_RELOC_X86_64_GOTPC64
:
14002 case BFD_RELOC_X86_64_GOTPLT64
:
14003 case BFD_RELOC_X86_64_PLTOFF64
:
14004 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14005 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14006 case BFD_RELOC_RVA
:
14007 case BFD_RELOC_VTABLE_ENTRY
:
14008 case BFD_RELOC_VTABLE_INHERIT
:
14010 case BFD_RELOC_32_SECREL
:
14012 code
= fixp
->fx_r_type
;
14014 case BFD_RELOC_X86_64_32S
:
14015 if (!fixp
->fx_pcrel
)
14017 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14018 code
= fixp
->fx_r_type
;
14021 /* Fall through. */
14023 if (fixp
->fx_pcrel
)
14025 switch (fixp
->fx_size
)
14028 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14029 _("can not do %d byte pc-relative relocation"),
14031 code
= BFD_RELOC_32_PCREL
;
14033 case 1: code
= BFD_RELOC_8_PCREL
; break;
14034 case 2: code
= BFD_RELOC_16_PCREL
; break;
14035 case 4: code
= BFD_RELOC_32_PCREL
; break;
14037 case 8: code
= BFD_RELOC_64_PCREL
; break;
14043 switch (fixp
->fx_size
)
14046 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14047 _("can not do %d byte relocation"),
14049 code
= BFD_RELOC_32
;
14051 case 1: code
= BFD_RELOC_8
; break;
14052 case 2: code
= BFD_RELOC_16
; break;
14053 case 4: code
= BFD_RELOC_32
; break;
14055 case 8: code
= BFD_RELOC_64
; break;
14062 if ((code
== BFD_RELOC_32
14063 || code
== BFD_RELOC_32_PCREL
14064 || code
== BFD_RELOC_X86_64_32S
)
14066 && fixp
->fx_addsy
== GOT_symbol
)
14069 code
= BFD_RELOC_386_GOTPC
;
14071 code
= BFD_RELOC_X86_64_GOTPC32
;
14073 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14075 && fixp
->fx_addsy
== GOT_symbol
)
14077 code
= BFD_RELOC_X86_64_GOTPC64
;
14080 rel
= XNEW (arelent
);
14081 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14082 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14084 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14086 if (!use_rela_relocations
)
14088 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14089 vtable entry to be used in the relocation's section offset. */
14090 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14091 rel
->address
= fixp
->fx_offset
;
14092 #if defined (OBJ_COFF) && defined (TE_PE)
14093 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14094 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14099 /* Use the rela in 64bit mode. */
14102 if (disallow_64bit_reloc
)
14105 case BFD_RELOC_X86_64_DTPOFF64
:
14106 case BFD_RELOC_X86_64_TPOFF64
:
14107 case BFD_RELOC_64_PCREL
:
14108 case BFD_RELOC_X86_64_GOTOFF64
:
14109 case BFD_RELOC_X86_64_GOT64
:
14110 case BFD_RELOC_X86_64_GOTPCREL64
:
14111 case BFD_RELOC_X86_64_GOTPC64
:
14112 case BFD_RELOC_X86_64_GOTPLT64
:
14113 case BFD_RELOC_X86_64_PLTOFF64
:
14114 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14115 _("cannot represent relocation type %s in x32 mode"),
14116 bfd_get_reloc_code_name (code
));
14122 if (!fixp
->fx_pcrel
)
14123 rel
->addend
= fixp
->fx_offset
;
14127 case BFD_RELOC_X86_64_PLT32
:
14128 case BFD_RELOC_X86_64_GOT32
:
14129 case BFD_RELOC_X86_64_GOTPCREL
:
14130 case BFD_RELOC_X86_64_GOTPCRELX
:
14131 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14132 case BFD_RELOC_X86_64_TLSGD
:
14133 case BFD_RELOC_X86_64_TLSLD
:
14134 case BFD_RELOC_X86_64_GOTTPOFF
:
14135 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14136 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14137 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14140 rel
->addend
= (section
->vma
14142 + fixp
->fx_addnumber
14143 + md_pcrel_from (fixp
));
14148 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14149 if (rel
->howto
== NULL
)
14151 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14152 _("cannot represent relocation type %s"),
14153 bfd_get_reloc_code_name (code
));
14154 /* Set howto to a garbage value so that we can keep going. */
14155 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14156 gas_assert (rel
->howto
!= NULL
);
14162 #include "tc-i386-intel.c"
14165 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14167 int saved_naked_reg
;
14168 char saved_register_dot
;
14170 saved_naked_reg
= allow_naked_reg
;
14171 allow_naked_reg
= 1;
14172 saved_register_dot
= register_chars
['.'];
14173 register_chars
['.'] = '.';
14174 allow_pseudo_reg
= 1;
14175 expression_and_evaluate (exp
);
14176 allow_pseudo_reg
= 0;
14177 register_chars
['.'] = saved_register_dot
;
14178 allow_naked_reg
= saved_naked_reg
;
14180 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14182 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14184 exp
->X_op
= O_constant
;
14185 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14186 .dw2_regnum
[flag_code
>> 1];
14189 exp
->X_op
= O_illegal
;
14194 tc_x86_frame_initial_instructions (void)
14196 static unsigned int sp_regno
[2];
14198 if (!sp_regno
[flag_code
>> 1])
14200 char *saved_input
= input_line_pointer
;
14201 char sp
[][4] = {"esp", "rsp"};
14204 input_line_pointer
= sp
[flag_code
>> 1];
14205 tc_x86_parse_to_dw2regnum (&exp
);
14206 gas_assert (exp
.X_op
== O_constant
);
14207 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14208 input_line_pointer
= saved_input
;
14211 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14212 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14216 x86_dwarf2_addr_size (void)
14218 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14219 if (x86_elf_abi
== X86_64_X32_ABI
)
14222 return bfd_arch_bits_per_address (stdoutput
) / 8;
14226 i386_elf_section_type (const char *str
, size_t len
)
14228 if (flag_code
== CODE_64BIT
14229 && len
== sizeof ("unwind") - 1
14230 && strncmp (str
, "unwind", 6) == 0)
14231 return SHT_X86_64_UNWIND
;
14238 i386_solaris_fix_up_eh_frame (segT sec
)
14240 if (flag_code
== CODE_64BIT
)
14241 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14247 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14251 exp
.X_op
= O_secrel
;
14252 exp
.X_add_symbol
= symbol
;
14253 exp
.X_add_number
= 0;
14254 emit_expr (&exp
, size
);
14258 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14259 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14262 x86_64_section_letter (int letter
, const char **ptr_msg
)
14264 if (flag_code
== CODE_64BIT
)
14267 return SHF_X86_64_LARGE
;
14269 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14272 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14277 x86_64_section_word (char *str
, size_t len
)
14279 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14280 return SHF_X86_64_LARGE
;
14286 handle_large_common (int small ATTRIBUTE_UNUSED
)
14288 if (flag_code
!= CODE_64BIT
)
14290 s_comm_internal (0, elf_common_parse
);
14291 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14295 static segT lbss_section
;
14296 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14297 asection
*saved_bss_section
= bss_section
;
14299 if (lbss_section
== NULL
)
14301 flagword applicable
;
14302 segT seg
= now_seg
;
14303 subsegT subseg
= now_subseg
;
14305 /* The .lbss section is for local .largecomm symbols. */
14306 lbss_section
= subseg_new (".lbss", 0);
14307 applicable
= bfd_applicable_section_flags (stdoutput
);
14308 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14309 seg_info (lbss_section
)->bss
= 1;
14311 subseg_set (seg
, subseg
);
14314 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14315 bss_section
= lbss_section
;
14317 s_comm_internal (0, elf_common_parse
);
14319 elf_com_section_ptr
= saved_com_section_ptr
;
14320 bss_section
= saved_bss_section
;
14323 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */