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Fix spelling mistakes and typos in the GAS sources.
[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 #include "as.h"
22 #include "safe-ctype.h"
23 #include "obstack.h"
24 #include "subsegs.h"
25 #include "dwarf2dbg.h"
26 #include "dw2gencfi.h"
27
28 #include "opcode/m68k.h"
29 #include "m68k-parse.h"
30
31 #if defined (OBJ_ELF)
32 #include "elf/m68k.h"
33 #endif
34
35 #ifdef M68KCOFF
36 #include "obj-coff.h"
37 #endif
38
39 #ifdef OBJ_ELF
40 static void m68k_elf_cons (int);
41 #endif
42
43 /* This string holds the chars that always start a comment. If the
44 pre-processor is disabled, these aren't very useful. The macro
45 tc_comment_chars points to this. We use this, rather than the
46 usual comment_chars, so that the --bitwise-or option will work. */
47 #if defined (TE_SVR4) || defined (TE_DELTA)
48 const char *m68k_comment_chars = "|#";
49 #else
50 const char *m68k_comment_chars = "|";
51 #endif
52
53 /* This array holds the chars that only start a comment at the beginning of
54 a line. If the line seems to have the form '# 123 filename'
55 .line and .file directives will appear in the pre-processed output */
56 /* Note that input_file.c hand checks for '#' at the beginning of the
57 first line of the input file. This is because the compiler outputs
58 #NO_APP at the beginning of its output. */
59 /* Also note that comments like this one will always work. */
60 const char line_comment_chars[] = "#*";
61
62 const char line_separator_chars[] = ";";
63
64 /* Chars that can be used to separate mant from exp in floating point nums. */
65 const char EXP_CHARS[] = "eE";
66
67 /* Chars that mean this number is a floating point constant, as
68 in "0f12.456" or "0d1.2345e12". */
69
70 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
71
72 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
73 changed in read.c . Ideally it shouldn't have to know about it at all,
74 but nothing is ideal around here. */
75
76 /* Are we trying to generate PIC code? If so, absolute references
77 ought to be made into linkage table references or pc-relative
78 references. Not implemented. For ELF there are other means
79 to denote pic relocations. */
80 int flag_want_pic;
81
82 static int flag_short_refs; /* -l option. */
83 static int flag_long_jumps; /* -S option. */
84 static int flag_keep_pcrel; /* --pcrel option. */
85
86 #ifdef REGISTER_PREFIX_OPTIONAL
87 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
88 #else
89 int flag_reg_prefix_optional;
90 #endif
91
92 /* Whether --register-prefix-optional was used on the command line. */
93 static int reg_prefix_optional_seen;
94
95 /* The floating point coprocessor to use by default. */
96 static enum m68k_register m68k_float_copnum = COP1;
97
98 /* If this is non-zero, then references to number(%pc) will be taken
99 to refer to number, rather than to %pc + number. */
100 static int m68k_abspcadd;
101
102 /* If this is non-zero, then the quick forms of the move, add, and sub
103 instructions are used when possible. */
104 static int m68k_quick = 1;
105
106 /* If this is non-zero, then if the size is not specified for a base
107 or outer displacement, the assembler assumes that the size should
108 be 32 bits. */
109 static int m68k_rel32 = 1;
110
111 /* This is non-zero if m68k_rel32 was set from the command line. */
112 static int m68k_rel32_from_cmdline;
113
114 /* The default width to use for an index register when using a base
115 displacement. */
116 static enum m68k_size m68k_index_width_default = SIZE_LONG;
117
118 /* We want to warn if any text labels are misaligned. In order to get
119 the right line number, we need to record the line number for each
120 label. */
121 struct label_line
122 {
123 struct label_line *next;
124 symbolS *label;
125 const char *file;
126 unsigned int line;
127 int text;
128 };
129
130 /* The list of labels. */
131
132 static struct label_line *labels;
133
134 /* The current label. */
135
136 static struct label_line *current_label;
137
138 /* Pointer to list holding the opcodes sorted by name. */
139 static struct m68k_opcode const ** m68k_sorted_opcodes;
140
141 /* It's an arbitrary name: This means I don't approve of it.
142 See flames below. */
143 static struct obstack robyn;
144
145 struct m68k_incant
146 {
147 const char *m_operands;
148 unsigned long m_opcode;
149 short m_opnum;
150 short m_codenum;
151 int m_arch;
152 struct m68k_incant *m_next;
153 };
154
155 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
156 #define gettwo(x) (((x)->m_opcode)&0xffff)
157
158 static const enum m68k_register m68000_ctrl[] = { 0 };
159 static const enum m68k_register m68010_ctrl[] = {
160 SFC, DFC, USP, VBR,
161 0
162 };
163 static const enum m68k_register m68020_ctrl[] = {
164 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
165 0
166 };
167 static const enum m68k_register m68040_ctrl[] = {
168 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
169 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
170 0
171 };
172 static const enum m68k_register m68060_ctrl[] = {
173 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
174 USP, VBR, URP, SRP, PCR,
175 0
176 };
177 static const enum m68k_register mcf_ctrl[] = {
178 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
179 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
180 0
181 };
182 static const enum m68k_register mcf51_ctrl[] = {
183 VBR, CPUCR,
184 0
185 };
186 static const enum m68k_register mcf5206_ctrl[] = {
187 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
188 0
189 };
190 static const enum m68k_register mcf5208_ctrl[] = {
191 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
192 0
193 };
194 static const enum m68k_register mcf5210a_ctrl[] = {
195 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
196 0
197 };
198 static const enum m68k_register mcf5213_ctrl[] = {
199 VBR, RAMBAR, RAMBAR1, FLASHBAR,
200 0
201 };
202 static const enum m68k_register mcf5216_ctrl[] = {
203 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
204 0
205 };
206 static const enum m68k_register mcf5221x_ctrl[] = {
207 VBR, FLASHBAR, RAMBAR, RAMBAR1,
208 0
209 };
210 static const enum m68k_register mcf52223_ctrl[] = {
211 VBR, FLASHBAR, RAMBAR, RAMBAR1,
212 0
213 };
214 static const enum m68k_register mcf52235_ctrl[] = {
215 VBR, FLASHBAR, RAMBAR, RAMBAR1,
216 0
217 };
218 static const enum m68k_register mcf5225_ctrl[] = {
219 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
220 0
221 };
222 static const enum m68k_register mcf52259_ctrl[] = {
223 VBR, FLASHBAR, RAMBAR, RAMBAR1,
224 0
225 };
226 static const enum m68k_register mcf52277_ctrl[] = {
227 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
228 0
229 };
230 static const enum m68k_register mcf5235_ctrl[] = {
231 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
232 0
233 };
234 static const enum m68k_register mcf5249_ctrl[] = {
235 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
236 0
237 };
238 static const enum m68k_register mcf5250_ctrl[] = {
239 VBR,
240 0
241 };
242 static const enum m68k_register mcf5253_ctrl[] = {
243 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
244 0
245 };
246 static const enum m68k_register mcf5271_ctrl[] = {
247 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
248 0
249 };
250 static const enum m68k_register mcf5272_ctrl[] = {
251 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
252 0
253 };
254 static const enum m68k_register mcf5275_ctrl[] = {
255 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
256 0
257 };
258 static const enum m68k_register mcf5282_ctrl[] = {
259 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
260 0
261 };
262 static const enum m68k_register mcf53017_ctrl[] = {
263 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
264 0
265 };
266 static const enum m68k_register mcf5307_ctrl[] = {
267 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR,
268 0
269 };
270 static const enum m68k_register mcf5329_ctrl[] = {
271 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
272 0
273 };
274 static const enum m68k_register mcf5373_ctrl[] = {
275 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
276 0
277 };
278 static const enum m68k_register mcfv4e_ctrl[] = {
279 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
280 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
281 MBAR, SECMBAR,
282 MPCR /* Multiprocessor Control register */,
283 EDRAMBAR /* Embedded DRAM Base Address Register */,
284 /* Permutation control registers. */
285 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
286 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
287 /* Legacy names */
288 TC /* ASID */, BUSCR /* MMUBAR */,
289 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
290 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
291 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
292 0
293 };
294 static const enum m68k_register mcf5407_ctrl[] = {
295 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
296 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
297 /* Legacy names */
298 TC /* ASID */,
299 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
300 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
301 0
302 };
303 static const enum m68k_register mcf54418_ctrl[] = {
304 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR,
305 VBR, PC, RAMBAR1,
306 /* Legacy names */
307 TC /* ASID */, BUSCR /* MMUBAR */,
308 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
309 RAMBAR /* RAMBAR1 */,
310 0
311 };
312 static const enum m68k_register mcf54455_ctrl[] = {
313 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
314 VBR, PC, RAMBAR1,
315 /* Legacy names */
316 TC /* ASID */, BUSCR /* MMUBAR */,
317 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
318 RAMBAR /* RAMBAR1 */,
319 0
320 };
321 static const enum m68k_register mcf5475_ctrl[] = {
322 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
323 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
324 /* Legacy names */
325 TC /* ASID */, BUSCR /* MMUBAR */,
326 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
327 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
328 0
329 };
330 static const enum m68k_register mcf5485_ctrl[] = {
331 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
332 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
333 /* Legacy names */
334 TC /* ASID */, BUSCR /* MMUBAR */,
335 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
336 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
337 0
338 };
339 static const enum m68k_register fido_ctrl[] = {
340 SFC, DFC, USP, VBR, CAC, MBO,
341 0
342 };
343 #define cpu32_ctrl m68010_ctrl
344
345 static const enum m68k_register *control_regs;
346
347 /* Internal form of a 68020 instruction. */
348 struct m68k_it
349 {
350 const char *error;
351 const char *args; /* List of opcode info. */
352 int numargs;
353
354 int numo; /* Number of shorts in opcode. */
355 short opcode[11];
356
357 struct m68k_op operands[6];
358
359 int nexp; /* Number of exprs in use. */
360 struct m68k_exp exprs[4];
361
362 int nfrag; /* Number of frags we have to produce. */
363 struct
364 {
365 int fragoff; /* Where in the current opcode the frag ends. */
366 symbolS *fadd;
367 offsetT foff;
368 int fragty;
369 }
370 fragb[4];
371
372 int nrel; /* Num of reloc structs in use. */
373 struct
374 {
375 int n;
376 expressionS exp;
377 char wid;
378 char pcrel;
379 /* In a pc relative address the difference between the address
380 of the offset and the address that the offset is relative
381 to. This depends on the addressing mode. Basically this
382 is the value to put in the offset field to address the
383 first byte of the offset, without regarding the special
384 significance of some values (in the branch instruction, for
385 example). */
386 int pcrel_fix;
387 #ifdef OBJ_ELF
388 /* Whether this expression needs special pic relocation, and if
389 so, which. */
390 enum pic_relocation pic_reloc;
391 #endif
392 }
393 reloc[5]; /* Five is enough??? */
394 };
395
396 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
397 #define float_of_arch(x) ((x) & mfloat)
398 #define mmu_of_arch(x) ((x) & mmmu)
399 #define arch_coldfire_p(x) ((x) & mcfisa_a)
400 #define arch_coldfire_fpu(x) ((x) & cfloat)
401
402 /* Macros for determining if cpu supports a specific addressing mode. */
403 #define HAVE_LONG_DISP(x) \
404 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
405 #define HAVE_LONG_CALL(x) \
406 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
407 #define HAVE_LONG_COND(x) \
408 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
409 #define HAVE_LONG_BRANCH(x) \
410 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
411 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
412
413 static struct m68k_it the_ins; /* The instruction being assembled. */
414
415 #define op(ex) ((ex)->exp.X_op)
416 #define adds(ex) ((ex)->exp.X_add_symbol)
417 #define subs(ex) ((ex)->exp.X_op_symbol)
418 #define offs(ex) ((ex)->exp.X_add_number)
419
420 /* Macros for adding things to the m68k_it struct. */
421 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
422
423 /* Like addword, but goes BEFORE general operands. */
424
425 static void
426 insop (int w, const struct m68k_incant *opcode)
427 {
428 int z;
429 for (z = the_ins.numo; z > opcode->m_codenum; --z)
430 the_ins.opcode[z] = the_ins.opcode[z - 1];
431 for (z = 0; z < the_ins.nrel; z++)
432 the_ins.reloc[z].n += 2;
433 for (z = 0; z < the_ins.nfrag; z++)
434 the_ins.fragb[z].fragoff++;
435 the_ins.opcode[opcode->m_codenum] = w;
436 the_ins.numo++;
437 }
438
439 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
440 Blecch. */
441 static void
442 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
443 {
444 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
445 ? the_ins.numo * 2 - 1
446 : (width == 'b'
447 ? the_ins.numo * 2 + 1
448 : the_ins.numo * 2));
449 the_ins.reloc[the_ins.nrel].exp = exp->exp;
450 the_ins.reloc[the_ins.nrel].wid = width;
451 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
452 #ifdef OBJ_ELF
453 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
454 #endif
455 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
456 }
457
458 /* Cause an extra frag to be generated here, inserting up to 10 bytes
459 (that value is chosen in the frag_var call in md_assemble). TYPE
460 is the subtype of the frag to be generated; its primary type is
461 rs_machine_dependent.
462
463 The TYPE parameter is also used by md_convert_frag_1 and
464 md_estimate_size_before_relax. The appropriate type of fixup will
465 be emitted by md_convert_frag_1.
466
467 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
468 static void
469 add_frag (symbolS *add, offsetT off, int type)
470 {
471 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
472 the_ins.fragb[the_ins.nfrag].fadd = add;
473 the_ins.fragb[the_ins.nfrag].foff = off;
474 the_ins.fragb[the_ins.nfrag++].fragty = type;
475 }
476
477 #define isvar(ex) \
478 (op (ex) != O_constant && op (ex) != O_big)
479
480 static char *crack_operand (char *str, struct m68k_op *opP);
481 static int get_num (struct m68k_exp *exp, int ok);
482 static int reverse_16_bits (int in);
483 static int reverse_8_bits (int in);
484 static void install_gen_operand (int mode, int val);
485 static void install_operand (int mode, int val);
486 static void s_bss (int);
487 static void s_data1 (int);
488 static void s_data2 (int);
489 static void s_even (int);
490 static void s_proc (int);
491 static void s_chip (int);
492 static void s_fopt (int);
493 static void s_opt (int);
494 static void s_reg (int);
495 static void s_restore (int);
496 static void s_save (int);
497 static void s_mri_if (int);
498 static void s_mri_else (int);
499 static void s_mri_endi (int);
500 static void s_mri_break (int);
501 static void s_mri_next (int);
502 static void s_mri_for (int);
503 static void s_mri_endf (int);
504 static void s_mri_repeat (int);
505 static void s_mri_until (int);
506 static void s_mri_while (int);
507 static void s_mri_endw (int);
508 static void s_m68k_cpu (int);
509 static void s_m68k_arch (int);
510
511 struct m68k_cpu
512 {
513 unsigned long arch; /* Architecture features. */
514 const enum m68k_register *control_regs; /* Control regs on chip */
515 const char *name; /* Name */
516 int alias; /* Alias for a canonical name. If 1, then
517 succeeds canonical name, if -1 then
518 succeeds canonical name, if <-1 ||>1 this is a
519 deprecated name, and the next/previous name
520 should be used. */
521 };
522
523 /* We hold flags for features explicitly enabled and explicitly
524 disabled. */
525 static int current_architecture;
526 static int not_current_architecture;
527 static const struct m68k_cpu *selected_arch;
528 static const struct m68k_cpu *selected_cpu;
529 static int initialized;
530
531 /* Architecture models. */
532 static const struct m68k_cpu m68k_archs[] =
533 {
534 {m68000, m68000_ctrl, "68000", 0},
535 {m68010, m68010_ctrl, "68010", 0},
536 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
537 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
538 {m68040, m68040_ctrl, "68040", 0},
539 {m68060, m68060_ctrl, "68060", 0},
540 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
541 {fido_a, fido_ctrl, "fidoa", 0},
542 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
543 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
544 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
545 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
546 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
547 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
548 {0,0,NULL, 0}
549 };
550
551 /* For -mno-mac we want to turn off all types of mac. */
552 static const unsigned no_mac = mcfmac | mcfemac;
553
554 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
555 for either. */
556 static const struct m68k_cpu m68k_extensions[] =
557 {
558 {m68851, NULL, "68851", -1},
559 {m68881, NULL, "68881", -1},
560 {m68881, NULL, "68882", -1},
561
562 {cfloat|m68881, NULL, "float", 0},
563
564 {mcfhwdiv, NULL, "div", 1},
565 {mcfusp, NULL, "usp", 1},
566 {mcfmac, (void *)&no_mac, "mac", 1},
567 {mcfemac, NULL, "emac", 1},
568
569 {0,NULL,NULL, 0}
570 };
571
572 /* Processor list */
573 static const struct m68k_cpu m68k_cpus[] =
574 {
575 {m68000, m68000_ctrl, "68000", 0},
576 {m68000, m68000_ctrl, "68ec000", 1},
577 {m68000, m68000_ctrl, "68hc000", 1},
578 {m68000, m68000_ctrl, "68hc001", 1},
579 {m68000, m68000_ctrl, "68008", 1},
580 {m68000, m68000_ctrl, "68302", 1},
581 {m68000, m68000_ctrl, "68306", 1},
582 {m68000, m68000_ctrl, "68307", 1},
583 {m68000, m68000_ctrl, "68322", 1},
584 {m68000, m68000_ctrl, "68356", 1},
585 {m68010, m68010_ctrl, "68010", 0},
586 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
587 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
588 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
589 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
590 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
591 {m68040, m68040_ctrl, "68040", 0},
592 {m68040, m68040_ctrl, "68ec040", 1},
593 {m68060, m68060_ctrl, "68060", 0},
594 {m68060, m68060_ctrl, "68ec060", 1},
595
596 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
597 {cpu32|m68881, cpu32_ctrl, "68330", 1},
598 {cpu32|m68881, cpu32_ctrl, "68331", 1},
599 {cpu32|m68881, cpu32_ctrl, "68332", 1},
600 {cpu32|m68881, cpu32_ctrl, "68333", 1},
601 {cpu32|m68881, cpu32_ctrl, "68334", 1},
602 {cpu32|m68881, cpu32_ctrl, "68336", 1},
603 {cpu32|m68881, cpu32_ctrl, "68340", 1},
604 {cpu32|m68881, cpu32_ctrl, "68341", 1},
605 {cpu32|m68881, cpu32_ctrl, "68349", 1},
606 {cpu32|m68881, cpu32_ctrl, "68360", 1},
607
608 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0},
609 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1},
610 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ag", 1},
611 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1},
612 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1},
613 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51je", 1},
614 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jf", 1},
615 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jg", 1},
616 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1},
617 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51mm", 1},
618 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1},
619 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51qm", 1},
620
621 {mcfisa_a, mcf_ctrl, "5200", 0},
622 {mcfisa_a, mcf_ctrl, "5202", 1},
623 {mcfisa_a, mcf_ctrl, "5204", 1},
624 {mcfisa_a, mcf5206_ctrl, "5206", 1},
625
626 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
627
628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
630
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
633
634 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
637
638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
639 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
641
642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0},
643
644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
645 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
646
647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
649 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
650 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
651
652 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
653 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
654
655 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1},
656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0},
657
658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
659 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
661 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
662 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
663
664 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
665 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
666 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
667
668 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1},
669 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1},
670 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1},
671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1},
672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1},
673 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0},
674
675 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
677
678 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
679
680 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
681 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
682
683 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
684 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
685 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
686 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
687
688 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1},
689 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1},
690 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1},
691 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1},
692 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1},
693 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1},
694 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0},
695
696 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
697
698 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
699 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
700 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
701 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
702
703 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
704 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
705 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
706
707 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
708
709 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1},
710 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1},
711 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1},
712 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1},
713 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0},
714
715 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
716 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
717 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
718 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
719 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
720 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
721
722 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
723 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
724 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
725 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
726 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
727 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
728 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
729
730 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
731 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
732 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
733 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
734 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
735 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
736 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
737
738 {fido_a, fido_ctrl, "fidoa", 0},
739 {fido_a, fido_ctrl, "fido", 1},
740
741 {0,NULL,NULL, 0}
742 };
743
744 static const struct m68k_cpu *m68k_lookup_cpu
745 (const char *, const struct m68k_cpu *, int, int *);
746 static int m68k_set_arch (const char *, int, int);
747 static int m68k_set_cpu (const char *, int, int);
748 static int m68k_set_extension (const char *, int, int);
749 static void m68k_init_arch (void);
750
751 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
752 architecture and we have a lot of relaxation modes. */
753
754 /* Macros used in the relaxation code. */
755 #define TAB(x,y) (((x) << 2) + (y))
756 #define TABTYPE(x) ((x) >> 2)
757
758 /* Relaxation states. */
759 #define BYTE 0
760 #define SHORT 1
761 #define LONG 2
762 #define SZ_UNDEF 3
763
764 /* Here are all the relaxation modes we support. First we can relax ordinary
765 branches. On 68020 and higher and on CPU32 all branch instructions take
766 three forms, so on these CPUs all branches always remain as such. When we
767 have to expand to the LONG form on a 68000, though, we substitute an
768 absolute jump instead. This is a direct replacement for unconditional
769 branches and a branch over a jump for conditional branches. However, if the
770 user requires PIC and disables this with --pcrel, we can only relax between
771 BYTE and SHORT forms, punting if that isn't enough. This gives us four
772 different relaxation modes for branches: */
773
774 #define BRANCHBWL 0 /* Branch byte, word, or long. */
775 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
776 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
777 #define BRANCHBW 3 /* Branch byte or word. */
778
779 /* We also relax coprocessor branches and DBcc's. All CPUs that support
780 coprocessor branches support them in word and long forms, so we have only
781 one relaxation mode for them. DBcc's are word only on all CPUs. We can
782 relax them to the LONG form with a branch-around sequence. This sequence
783 can use a long branch (if available) or an absolute jump (if acceptable).
784 This gives us two relaxation modes. If long branches are not available and
785 absolute jumps are not acceptable, we don't relax DBcc's. */
786
787 #define FBRANCH 4 /* Coprocessor branch. */
788 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
789 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
790
791 /* That's all for instruction relaxation. However, we also relax PC-relative
792 operands. Specifically, we have three operand relaxation modes. On the
793 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
794 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
795 two. Also PC+displacement+index operands in their simple form (with a non-
796 suppressed index without memory indirection) are supported on all CPUs, but
797 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
798 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
799 form of the PC+displacement+index operand. Finally, some absolute operands
800 can be relaxed down to 16-bit PC-relative. */
801
802 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
803 #define PCINDEX 8 /* PC + displacement + index. */
804 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
805
806 /* This relaxation is required for branches where there is no long
807 branch and we are in pcrel mode. We generate a bne/beq pair. */
808 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs
809 */
810
811 /* Note that calls to frag_var need to specify the maximum expansion
812 needed; this is currently 12 bytes for bne/beq pair. */
813 #define FRAG_VAR_SIZE 12
814
815 /* The fields are:
816 How far Forward this mode will reach:
817 How far Backward this mode will reach:
818 How many bytes this mode will add to the size of the frag
819 Which mode to go to if the offset won't fit in this one
820
821 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
822 relax_typeS md_relax_table[] =
823 {
824 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
825 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
826 { 0, 0, 4, 0 },
827 { 1, 1, 0, 0 },
828
829 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
830 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
831 { 0, 0, 4, 0 },
832 { 1, 1, 0, 0 },
833
834 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
835 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
836 { 0, 0, 6, 0 },
837 { 1, 1, 0, 0 },
838
839 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
840 { 0, 0, 2, 0 },
841 { 1, 1, 0, 0 },
842 { 1, 1, 0, 0 },
843
844 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
845 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
846 { 0, 0, 4, 0 },
847 { 1, 1, 0, 0 },
848
849 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
850 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
851 { 0, 0, 10, 0 },
852 { 1, 1, 0, 0 },
853
854 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
855 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
856 { 0, 0, 10, 0 },
857 { 1, 1, 0, 0 },
858
859 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
860 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
861 { 0, 0, 6, 0 },
862 { 1, 1, 0, 0 },
863
864 { 125, -130, 0, TAB (PCINDEX, SHORT) },
865 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
866 { 0, 0, 4, 0 },
867 { 1, 1, 0, 0 },
868
869 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
870 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
871 { 0, 0, 4, 0 },
872 { 1, 1, 0, 0 },
873
874 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
875 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
876 { 0, 0, 10, 0 },
877 { 1, 1, 0, 0 },
878 };
879
880 /* These are the machine dependent pseudo-ops. These are included so
881 the assembler can work on the output from the SUN C compiler, which
882 generates these. */
883
884 /* This table describes all the machine specific pseudo-ops the assembler
885 has to support. The fields are:
886 pseudo-op name without dot
887 function to call to execute this pseudo-op
888 Integer arg to pass to the function. */
889 const pseudo_typeS md_pseudo_table[] =
890 {
891 {"data1", s_data1, 0},
892 {"data2", s_data2, 0},
893 {"bss", s_bss, 0},
894 {"even", s_even, 0},
895 {"skip", s_space, 0},
896 {"proc", s_proc, 0},
897 #if defined (TE_SUN3) || defined (OBJ_ELF)
898 {"align", s_align_bytes, 0},
899 #endif
900 #ifdef OBJ_ELF
901 {"swbeg", s_ignore, 0},
902 {"long", m68k_elf_cons, 4},
903 #endif
904 {"extend", float_cons, 'x'},
905 {"ldouble", float_cons, 'x'},
906
907 {"arch", s_m68k_arch, 0},
908 {"cpu", s_m68k_cpu, 0},
909
910 /* The following pseudo-ops are supported for MRI compatibility. */
911 {"chip", s_chip, 0},
912 {"comline", s_space, 1},
913 {"fopt", s_fopt, 0},
914 {"mask2", s_ignore, 0},
915 {"opt", s_opt, 0},
916 {"reg", s_reg, 0},
917 {"restore", s_restore, 0},
918 {"save", s_save, 0},
919
920 {"if", s_mri_if, 0},
921 {"if.b", s_mri_if, 'b'},
922 {"if.w", s_mri_if, 'w'},
923 {"if.l", s_mri_if, 'l'},
924 {"else", s_mri_else, 0},
925 {"else.s", s_mri_else, 's'},
926 {"else.l", s_mri_else, 'l'},
927 {"endi", s_mri_endi, 0},
928 {"break", s_mri_break, 0},
929 {"break.s", s_mri_break, 's'},
930 {"break.l", s_mri_break, 'l'},
931 {"next", s_mri_next, 0},
932 {"next.s", s_mri_next, 's'},
933 {"next.l", s_mri_next, 'l'},
934 {"for", s_mri_for, 0},
935 {"for.b", s_mri_for, 'b'},
936 {"for.w", s_mri_for, 'w'},
937 {"for.l", s_mri_for, 'l'},
938 {"endf", s_mri_endf, 0},
939 {"repeat", s_mri_repeat, 0},
940 {"until", s_mri_until, 0},
941 {"until.b", s_mri_until, 'b'},
942 {"until.w", s_mri_until, 'w'},
943 {"until.l", s_mri_until, 'l'},
944 {"while", s_mri_while, 0},
945 {"while.b", s_mri_while, 'b'},
946 {"while.w", s_mri_while, 'w'},
947 {"while.l", s_mri_while, 'l'},
948 {"endw", s_mri_endw, 0},
949
950 {0, 0, 0}
951 };
952
953 /* The mote pseudo ops are put into the opcode table, since they
954 don't start with a . they look like opcodes to gas. */
955
956 const pseudo_typeS mote_pseudo_table[] =
957 {
958
959 {"dcl", cons, 4},
960 {"dc", cons, 2},
961 {"dcw", cons, 2},
962 {"dcb", cons, 1},
963
964 {"dsl", s_space, 4},
965 {"ds", s_space, 2},
966 {"dsw", s_space, 2},
967 {"dsb", s_space, 1},
968
969 {"xdef", s_globl, 0},
970 #ifdef OBJ_ELF
971 {"align", s_align_bytes, 0},
972 #else
973 {"align", s_align_ptwo, 0},
974 #endif
975 #ifdef M68KCOFF
976 {"sect", obj_coff_section, 0},
977 {"section", obj_coff_section, 0},
978 #endif
979 {0, 0, 0}
980 };
981
982 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
983 gives identical results to a 32-bit host. */
984 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
985 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
986
987 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
988 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
989 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
990 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
991
992 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
993 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
994 #define islong(x) (1)
995
996 static char notend_table[256];
997 static char alt_notend_table[256];
998 #define notend(s) \
999 (! (notend_table[(unsigned char) *s] \
1000 || (*s == ':' \
1001 && alt_notend_table[(unsigned char) s[1]])))
1002
1003 #ifdef OBJ_ELF
1004
1005 /* Return zero if the reference to SYMBOL from within the same segment may
1006 be relaxed. */
1007
1008 /* On an ELF system, we can't relax an externally visible symbol,
1009 because it may be overridden by a shared library. However, if
1010 TARGET_OS is "elf", then we presume that we are assembling for an
1011 embedded system, in which case we don't have to worry about shared
1012 libraries, and we can relax any external sym. */
1013
1014 #define relaxable_symbol(symbol) \
1015 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
1016 || S_IS_WEAK (symbol)))
1017
1018 /* Compute the relocation code for a fixup of SIZE bytes, using pc
1019 relative relocation if PCREL is non-zero. PIC says whether a special
1020 pic relocation was requested. */
1021
1022 static bfd_reloc_code_real_type
1023 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
1024 {
1025 switch (pic)
1026 {
1027 case pic_got_pcrel:
1028 switch (size)
1029 {
1030 case 1:
1031 return BFD_RELOC_8_GOT_PCREL;
1032 case 2:
1033 return BFD_RELOC_16_GOT_PCREL;
1034 case 4:
1035 return BFD_RELOC_32_GOT_PCREL;
1036 }
1037 break;
1038
1039 case pic_got_off:
1040 switch (size)
1041 {
1042 case 1:
1043 return BFD_RELOC_8_GOTOFF;
1044 case 2:
1045 return BFD_RELOC_16_GOTOFF;
1046 case 4:
1047 return BFD_RELOC_32_GOTOFF;
1048 }
1049 break;
1050
1051 case pic_plt_pcrel:
1052 switch (size)
1053 {
1054 case 1:
1055 return BFD_RELOC_8_PLT_PCREL;
1056 case 2:
1057 return BFD_RELOC_16_PLT_PCREL;
1058 case 4:
1059 return BFD_RELOC_32_PLT_PCREL;
1060 }
1061 break;
1062
1063 case pic_plt_off:
1064 switch (size)
1065 {
1066 case 1:
1067 return BFD_RELOC_8_PLTOFF;
1068 case 2:
1069 return BFD_RELOC_16_PLTOFF;
1070 case 4:
1071 return BFD_RELOC_32_PLTOFF;
1072 }
1073 break;
1074
1075 case pic_tls_gd:
1076 switch (size)
1077 {
1078 case 1:
1079 return BFD_RELOC_68K_TLS_GD8;
1080 case 2:
1081 return BFD_RELOC_68K_TLS_GD16;
1082 case 4:
1083 return BFD_RELOC_68K_TLS_GD32;
1084 }
1085 break;
1086
1087 case pic_tls_ldm:
1088 switch (size)
1089 {
1090 case 1:
1091 return BFD_RELOC_68K_TLS_LDM8;
1092 case 2:
1093 return BFD_RELOC_68K_TLS_LDM16;
1094 case 4:
1095 return BFD_RELOC_68K_TLS_LDM32;
1096 }
1097 break;
1098
1099 case pic_tls_ldo:
1100 switch (size)
1101 {
1102 case 1:
1103 return BFD_RELOC_68K_TLS_LDO8;
1104 case 2:
1105 return BFD_RELOC_68K_TLS_LDO16;
1106 case 4:
1107 return BFD_RELOC_68K_TLS_LDO32;
1108 }
1109 break;
1110
1111 case pic_tls_ie:
1112 switch (size)
1113 {
1114 case 1:
1115 return BFD_RELOC_68K_TLS_IE8;
1116 case 2:
1117 return BFD_RELOC_68K_TLS_IE16;
1118 case 4:
1119 return BFD_RELOC_68K_TLS_IE32;
1120 }
1121 break;
1122
1123 case pic_tls_le:
1124 switch (size)
1125 {
1126 case 1:
1127 return BFD_RELOC_68K_TLS_LE8;
1128 case 2:
1129 return BFD_RELOC_68K_TLS_LE16;
1130 case 4:
1131 return BFD_RELOC_68K_TLS_LE32;
1132 }
1133 break;
1134
1135 case pic_none:
1136 if (pcrel)
1137 {
1138 switch (size)
1139 {
1140 case 1:
1141 return BFD_RELOC_8_PCREL;
1142 case 2:
1143 return BFD_RELOC_16_PCREL;
1144 case 4:
1145 return BFD_RELOC_32_PCREL;
1146 }
1147 }
1148 else
1149 {
1150 switch (size)
1151 {
1152 case 1:
1153 return BFD_RELOC_8;
1154 case 2:
1155 return BFD_RELOC_16;
1156 case 4:
1157 return BFD_RELOC_32;
1158 }
1159 }
1160 }
1161
1162 if (pcrel)
1163 {
1164 if (pic == pic_none)
1165 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1166 else
1167 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1168 }
1169 else
1170 {
1171 if (pic == pic_none)
1172 as_bad (_("Can not do %d byte relocation"), size);
1173 else
1174 as_bad (_("Can not do %d byte pic relocation"), size);
1175 }
1176
1177 return BFD_RELOC_NONE;
1178 }
1179
1180 /* Here we decide which fixups can be adjusted to make them relative
1181 to the beginning of the section instead of the symbol. Basically
1182 we need to make sure that the dynamic relocations are done
1183 correctly, so in some cases we force the original symbol to be
1184 used. */
1185 int
1186 tc_m68k_fix_adjustable (fixS *fixP)
1187 {
1188 /* Adjust_reloc_syms doesn't know about the GOT. */
1189 switch (fixP->fx_r_type)
1190 {
1191 case BFD_RELOC_8_GOT_PCREL:
1192 case BFD_RELOC_16_GOT_PCREL:
1193 case BFD_RELOC_32_GOT_PCREL:
1194 case BFD_RELOC_8_GOTOFF:
1195 case BFD_RELOC_16_GOTOFF:
1196 case BFD_RELOC_32_GOTOFF:
1197 case BFD_RELOC_8_PLT_PCREL:
1198 case BFD_RELOC_16_PLT_PCREL:
1199 case BFD_RELOC_32_PLT_PCREL:
1200 case BFD_RELOC_8_PLTOFF:
1201 case BFD_RELOC_16_PLTOFF:
1202 case BFD_RELOC_32_PLTOFF:
1203 case BFD_RELOC_68K_TLS_GD32:
1204 case BFD_RELOC_68K_TLS_GD16:
1205 case BFD_RELOC_68K_TLS_GD8:
1206 case BFD_RELOC_68K_TLS_LDM32:
1207 case BFD_RELOC_68K_TLS_LDM16:
1208 case BFD_RELOC_68K_TLS_LDM8:
1209 case BFD_RELOC_68K_TLS_LDO32:
1210 case BFD_RELOC_68K_TLS_LDO16:
1211 case BFD_RELOC_68K_TLS_LDO8:
1212 case BFD_RELOC_68K_TLS_IE32:
1213 case BFD_RELOC_68K_TLS_IE16:
1214 case BFD_RELOC_68K_TLS_IE8:
1215 case BFD_RELOC_68K_TLS_LE32:
1216 case BFD_RELOC_68K_TLS_LE16:
1217 case BFD_RELOC_68K_TLS_LE8:
1218 return 0;
1219
1220 case BFD_RELOC_VTABLE_INHERIT:
1221 case BFD_RELOC_VTABLE_ENTRY:
1222 return 0;
1223
1224 default:
1225 return 1;
1226 }
1227 }
1228
1229 #else /* !OBJ_ELF */
1230
1231 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1232
1233 /* PR gas/3041 Weak symbols are not relaxable
1234 because they must be treated as extern. */
1235 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1236
1237 #endif /* OBJ_ELF */
1238
1239 arelent *
1240 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1241 {
1242 arelent *reloc;
1243 bfd_reloc_code_real_type code;
1244
1245 /* If the tcbit is set, then this was a fixup of a negative value
1246 that was never resolved. We do not have a reloc to handle this,
1247 so just return. We assume that other code will have detected this
1248 situation and produced a helpful error message, so we just tell the
1249 user that the reloc cannot be produced. */
1250 if (fixp->fx_tcbit)
1251 {
1252 if (fixp->fx_addsy)
1253 as_bad_where (fixp->fx_file, fixp->fx_line,
1254 _("Unable to produce reloc against symbol '%s'"),
1255 S_GET_NAME (fixp->fx_addsy));
1256 return NULL;
1257 }
1258
1259 if (fixp->fx_r_type != BFD_RELOC_NONE)
1260 {
1261 code = fixp->fx_r_type;
1262
1263 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1264 that fixup_segment converted a non-PC relative reloc into a
1265 PC relative reloc. In such a case, we need to convert the
1266 reloc code. */
1267 if (fixp->fx_pcrel)
1268 {
1269 switch (code)
1270 {
1271 case BFD_RELOC_8:
1272 code = BFD_RELOC_8_PCREL;
1273 break;
1274 case BFD_RELOC_16:
1275 code = BFD_RELOC_16_PCREL;
1276 break;
1277 case BFD_RELOC_32:
1278 code = BFD_RELOC_32_PCREL;
1279 break;
1280 case BFD_RELOC_8_PCREL:
1281 case BFD_RELOC_16_PCREL:
1282 case BFD_RELOC_32_PCREL:
1283 case BFD_RELOC_8_GOT_PCREL:
1284 case BFD_RELOC_16_GOT_PCREL:
1285 case BFD_RELOC_32_GOT_PCREL:
1286 case BFD_RELOC_8_GOTOFF:
1287 case BFD_RELOC_16_GOTOFF:
1288 case BFD_RELOC_32_GOTOFF:
1289 case BFD_RELOC_8_PLT_PCREL:
1290 case BFD_RELOC_16_PLT_PCREL:
1291 case BFD_RELOC_32_PLT_PCREL:
1292 case BFD_RELOC_8_PLTOFF:
1293 case BFD_RELOC_16_PLTOFF:
1294 case BFD_RELOC_32_PLTOFF:
1295 case BFD_RELOC_68K_TLS_GD32:
1296 case BFD_RELOC_68K_TLS_GD16:
1297 case BFD_RELOC_68K_TLS_GD8:
1298 case BFD_RELOC_68K_TLS_LDM32:
1299 case BFD_RELOC_68K_TLS_LDM16:
1300 case BFD_RELOC_68K_TLS_LDM8:
1301 case BFD_RELOC_68K_TLS_LDO32:
1302 case BFD_RELOC_68K_TLS_LDO16:
1303 case BFD_RELOC_68K_TLS_LDO8:
1304 case BFD_RELOC_68K_TLS_IE32:
1305 case BFD_RELOC_68K_TLS_IE16:
1306 case BFD_RELOC_68K_TLS_IE8:
1307 case BFD_RELOC_68K_TLS_LE32:
1308 case BFD_RELOC_68K_TLS_LE16:
1309 case BFD_RELOC_68K_TLS_LE8:
1310 break;
1311 default:
1312 as_bad_where (fixp->fx_file, fixp->fx_line,
1313 _("Cannot make %s relocation PC relative"),
1314 bfd_get_reloc_code_name (code));
1315 }
1316 }
1317 }
1318 else
1319 {
1320 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1321 switch (F (fixp->fx_size, fixp->fx_pcrel))
1322 {
1323 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1324 MAP (1, 0, BFD_RELOC_8);
1325 MAP (2, 0, BFD_RELOC_16);
1326 MAP (4, 0, BFD_RELOC_32);
1327 MAP (1, 1, BFD_RELOC_8_PCREL);
1328 MAP (2, 1, BFD_RELOC_16_PCREL);
1329 MAP (4, 1, BFD_RELOC_32_PCREL);
1330 default:
1331 abort ();
1332 }
1333 }
1334 #undef F
1335 #undef MAP
1336
1337 reloc = XNEW (arelent);
1338 reloc->sym_ptr_ptr = XNEW (asymbol *);
1339 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1340 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1341 #ifndef OBJ_ELF
1342 if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1343 && fixp->fx_addsy
1344 && S_IS_WEAK (fixp->fx_addsy)
1345 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1346 {
1347 /* PR gas/3041 References to weak symbols must be treated as extern
1348 in order to be overridable by the linker, even if they are defined
1349 in the same object file. So the original addend must be written
1350 "as is" into the output section without further processing.
1351 The addend value must be hacked here in order to force
1352 bfd_install_relocation() to write the original value into the
1353 output section.
1354 1) MD_APPLY_SYM_VALUE() is set to 1 for m68k/a.out, so the symbol
1355 value has already been added to the addend in fixup_segment(). We
1356 have to remove it.
1357 2) bfd_install_relocation() will incorrectly treat this symbol as
1358 resolved, so it will write the symbol value plus its addend and
1359 section VMA. As a workaround we can tweak the addend value here in
1360 order to get the original value in the section after the call to
1361 bfd_install_relocation(). */
1362 reloc->addend = fixp->fx_addnumber
1363 /* Fix because of MD_APPLY_SYM_VALUE() */
1364 - S_GET_VALUE (fixp->fx_addsy)
1365 /* Fix for bfd_install_relocation() */
1366 - (S_GET_VALUE (fixp->fx_addsy)
1367 + S_GET_SEGMENT (fixp->fx_addsy)->vma);
1368 }
1369 else if (fixp->fx_pcrel)
1370 reloc->addend = fixp->fx_addnumber;
1371 else
1372 reloc->addend = 0;
1373 #else
1374 if (!fixp->fx_pcrel)
1375 reloc->addend = fixp->fx_addnumber;
1376 else
1377 reloc->addend = (section->vma
1378 + fixp->fx_pcrel_adjust
1379 + fixp->fx_addnumber
1380 + md_pcrel_from (fixp));
1381 #endif
1382
1383 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1384 gas_assert (reloc->howto != 0);
1385
1386 return reloc;
1387 }
1388
1389 /* Handle of the OPCODE hash table. NULL means any use before
1390 m68k_ip_begin() will crash. */
1391 static struct hash_control *op_hash;
1392 \f
1393 /* Assemble an m68k instruction. */
1394
1395 static void
1396 m68k_ip (char *instring)
1397 {
1398 char *p;
1399 struct m68k_op *opP;
1400 const struct m68k_incant *opcode;
1401 const char *s;
1402 int tmpreg = 0, baseo = 0, outro = 0, nextword;
1403 char *pdot, *pdotmove;
1404 enum m68k_size siz1, siz2;
1405 char c;
1406 int losing;
1407 int opsfound;
1408 struct m68k_op operands_backup[6];
1409 LITTLENUM_TYPE words[6];
1410 LITTLENUM_TYPE *wordp;
1411 unsigned long ok_arch = 0;
1412
1413 if (*instring == ' ')
1414 instring++; /* Skip leading whitespace. */
1415
1416 /* Scan up to end of operation-code, which MUST end in end-of-string
1417 or exactly 1 space. */
1418 pdot = 0;
1419 for (p = instring; *p != '\0'; p++)
1420 {
1421 if (*p == ' ')
1422 break;
1423 if (*p == '.')
1424 pdot = p;
1425 }
1426
1427 if (p == instring)
1428 {
1429 the_ins.error = _("No operator");
1430 return;
1431 }
1432
1433 /* p now points to the end of the opcode name, probably whitespace.
1434 Make sure the name is null terminated by clobbering the
1435 whitespace, look it up in the hash table, then fix it back.
1436 Remove a dot, first, since the opcode tables have none. */
1437 if (pdot != NULL)
1438 {
1439 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1440 *pdotmove = pdotmove[1];
1441 p--;
1442 }
1443
1444 c = *p;
1445 *p = '\0';
1446 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1447 *p = c;
1448
1449 if (pdot != NULL)
1450 {
1451 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1452 *pdotmove = pdotmove[-1];
1453 *pdot = '.';
1454 ++p;
1455 }
1456
1457 if (opcode == NULL)
1458 {
1459 the_ins.error = _("Unknown operator");
1460 return;
1461 }
1462
1463 /* Found a legitimate opcode, start matching operands. */
1464 while (*p == ' ')
1465 ++p;
1466
1467 if (opcode->m_operands == 0)
1468 {
1469 char *old = input_line_pointer;
1470 *old = '\n';
1471 input_line_pointer = p;
1472 /* Ahh - it's a motorola style pseudo op. */
1473 mote_pseudo_table[opcode->m_opnum].poc_handler
1474 (mote_pseudo_table[opcode->m_opnum].poc_val);
1475 input_line_pointer = old;
1476 *old = 0;
1477
1478 return;
1479 }
1480
1481 if (flag_mri && opcode->m_opnum == 0)
1482 {
1483 /* In MRI mode, random garbage is allowed after an instruction
1484 which accepts no operands. */
1485 the_ins.args = opcode->m_operands;
1486 the_ins.numargs = opcode->m_opnum;
1487 the_ins.numo = opcode->m_codenum;
1488 the_ins.opcode[0] = getone (opcode);
1489 the_ins.opcode[1] = gettwo (opcode);
1490 return;
1491 }
1492
1493 for (opP = &the_ins.operands[0]; *p; opP++)
1494 {
1495 p = crack_operand (p, opP);
1496
1497 if (opP->error)
1498 {
1499 the_ins.error = opP->error;
1500 return;
1501 }
1502 }
1503
1504 opsfound = opP - &the_ins.operands[0];
1505
1506 /* This ugly hack is to support the floating pt opcodes in their
1507 standard form. Essentially, we fake a first entry of type COP#1 */
1508 if (opcode->m_operands[0] == 'I')
1509 {
1510 int n;
1511
1512 for (n = opsfound; n > 0; --n)
1513 the_ins.operands[n] = the_ins.operands[n - 1];
1514
1515 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1516 the_ins.operands[0].mode = CONTROL;
1517 the_ins.operands[0].reg = m68k_float_copnum;
1518 opsfound++;
1519 }
1520
1521 /* We've got the operands. Find an opcode that'll accept them. */
1522 for (losing = 0;;)
1523 {
1524 /* If we didn't get the right number of ops, or we have no
1525 common model with this pattern then reject this pattern. */
1526
1527 ok_arch |= opcode->m_arch;
1528 if (opsfound != opcode->m_opnum
1529 || ((opcode->m_arch & current_architecture) == 0))
1530 ++losing;
1531 else
1532 {
1533 int i;
1534
1535 /* Make a copy of the operands of this insn so that
1536 we can modify them safely, should we want to. */
1537 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1538 for (i = 0; i < opsfound; i++)
1539 operands_backup[i] = the_ins.operands[i];
1540
1541 for (s = opcode->m_operands, opP = &operands_backup[0];
1542 *s && !losing;
1543 s += 2, opP++)
1544 {
1545 /* Warning: this switch is huge! */
1546 /* I've tried to organize the cases into this order:
1547 non-alpha first, then alpha by letter. Lower-case
1548 goes directly before uppercase counterpart. */
1549 /* Code with multiple case ...: gets sorted by the lowest
1550 case ... it belongs to. I hope this makes sense. */
1551 switch (*s)
1552 {
1553 case '!':
1554 switch (opP->mode)
1555 {
1556 case IMMED:
1557 case DREG:
1558 case AREG:
1559 case FPREG:
1560 case CONTROL:
1561 case AINC:
1562 case ADEC:
1563 case REGLST:
1564 losing++;
1565 break;
1566 default:
1567 break;
1568 }
1569 break;
1570
1571 case '<':
1572 switch (opP->mode)
1573 {
1574 case DREG:
1575 case AREG:
1576 case FPREG:
1577 case CONTROL:
1578 case IMMED:
1579 case ADEC:
1580 case REGLST:
1581 losing++;
1582 break;
1583 default:
1584 break;
1585 }
1586 break;
1587
1588 case '>':
1589 switch (opP->mode)
1590 {
1591 case DREG:
1592 case AREG:
1593 case FPREG:
1594 case CONTROL:
1595 case IMMED:
1596 case AINC:
1597 case REGLST:
1598 losing++;
1599 break;
1600 case ABSL:
1601 break;
1602 default:
1603 if (opP->reg == PC
1604 || opP->reg == ZPC)
1605 losing++;
1606 break;
1607 }
1608 break;
1609
1610 case 'm':
1611 switch (opP->mode)
1612 {
1613 case DREG:
1614 case AREG:
1615 case AINDR:
1616 case AINC:
1617 case ADEC:
1618 break;
1619 default:
1620 losing++;
1621 }
1622 break;
1623
1624 case 'n':
1625 switch (opP->mode)
1626 {
1627 case DISP:
1628 break;
1629 default:
1630 losing++;
1631 }
1632 break;
1633
1634 case 'o':
1635 switch (opP->mode)
1636 {
1637 case BASE:
1638 case ABSL:
1639 case IMMED:
1640 break;
1641 default:
1642 losing++;
1643 }
1644 break;
1645
1646 case 'p':
1647 switch (opP->mode)
1648 {
1649 case DREG:
1650 case AREG:
1651 case AINDR:
1652 case AINC:
1653 case ADEC:
1654 break;
1655 case DISP:
1656 if (opP->reg == PC || opP->reg == ZPC)
1657 losing++;
1658 break;
1659 default:
1660 losing++;
1661 }
1662 break;
1663
1664 case 'q':
1665 switch (opP->mode)
1666 {
1667 case DREG:
1668 case AINDR:
1669 case AINC:
1670 case ADEC:
1671 break;
1672 case DISP:
1673 if (opP->reg == PC || opP->reg == ZPC)
1674 losing++;
1675 break;
1676 default:
1677 losing++;
1678 break;
1679 }
1680 break;
1681
1682 case 'v':
1683 switch (opP->mode)
1684 {
1685 case DREG:
1686 case AINDR:
1687 case AINC:
1688 case ADEC:
1689 case ABSL:
1690 break;
1691 case DISP:
1692 if (opP->reg == PC || opP->reg == ZPC)
1693 losing++;
1694 break;
1695 default:
1696 losing++;
1697 break;
1698 }
1699 break;
1700
1701 case '#':
1702 if (opP->mode != IMMED)
1703 losing++;
1704 else if (s[1] == 'b'
1705 && ! isvar (&opP->disp)
1706 && (opP->disp.exp.X_op != O_constant
1707 || ! isbyte (opP->disp.exp.X_add_number)))
1708 losing++;
1709 else if (s[1] == 'B'
1710 && ! isvar (&opP->disp)
1711 && (opP->disp.exp.X_op != O_constant
1712 || ! issbyte (opP->disp.exp.X_add_number)))
1713 losing++;
1714 else if (s[1] == 'w'
1715 && ! isvar (&opP->disp)
1716 && (opP->disp.exp.X_op != O_constant
1717 || ! isword (opP->disp.exp.X_add_number)))
1718 losing++;
1719 else if (s[1] == 'W'
1720 && ! isvar (&opP->disp)
1721 && (opP->disp.exp.X_op != O_constant
1722 || ! issword (opP->disp.exp.X_add_number)))
1723 losing++;
1724 break;
1725
1726 case '^':
1727 case 'T':
1728 if (opP->mode != IMMED)
1729 losing++;
1730 break;
1731
1732 case '$':
1733 if (opP->mode == AREG
1734 || opP->mode == CONTROL
1735 || opP->mode == FPREG
1736 || opP->mode == IMMED
1737 || opP->mode == REGLST
1738 || (opP->mode != ABSL
1739 && (opP->reg == PC
1740 || opP->reg == ZPC)))
1741 losing++;
1742 break;
1743
1744 case '%':
1745 if (opP->mode == CONTROL
1746 || opP->mode == FPREG
1747 || opP->mode == REGLST
1748 || opP->mode == IMMED
1749 || (opP->mode != ABSL
1750 && (opP->reg == PC
1751 || opP->reg == ZPC)))
1752 losing++;
1753 break;
1754
1755 case '&':
1756 switch (opP->mode)
1757 {
1758 case DREG:
1759 case AREG:
1760 case FPREG:
1761 case CONTROL:
1762 case IMMED:
1763 case AINC:
1764 case ADEC:
1765 case REGLST:
1766 losing++;
1767 break;
1768 case ABSL:
1769 break;
1770 default:
1771 if (opP->reg == PC
1772 || opP->reg == ZPC)
1773 losing++;
1774 break;
1775 }
1776 break;
1777
1778 case '*':
1779 if (opP->mode == CONTROL
1780 || opP->mode == FPREG
1781 || opP->mode == REGLST)
1782 losing++;
1783 break;
1784
1785 case '+':
1786 if (opP->mode != AINC)
1787 losing++;
1788 break;
1789
1790 case '-':
1791 if (opP->mode != ADEC)
1792 losing++;
1793 break;
1794
1795 case '/':
1796 switch (opP->mode)
1797 {
1798 case AREG:
1799 case CONTROL:
1800 case FPREG:
1801 case AINC:
1802 case ADEC:
1803 case IMMED:
1804 case REGLST:
1805 losing++;
1806 break;
1807 default:
1808 break;
1809 }
1810 break;
1811
1812 case ';':
1813 switch (opP->mode)
1814 {
1815 case AREG:
1816 case CONTROL:
1817 case FPREG:
1818 case REGLST:
1819 losing++;
1820 break;
1821 default:
1822 break;
1823 }
1824 break;
1825
1826 case '?':
1827 switch (opP->mode)
1828 {
1829 case AREG:
1830 case CONTROL:
1831 case FPREG:
1832 case AINC:
1833 case ADEC:
1834 case IMMED:
1835 case REGLST:
1836 losing++;
1837 break;
1838 case ABSL:
1839 break;
1840 default:
1841 if (opP->reg == PC || opP->reg == ZPC)
1842 losing++;
1843 break;
1844 }
1845 break;
1846
1847 case '@':
1848 switch (opP->mode)
1849 {
1850 case AREG:
1851 case CONTROL:
1852 case FPREG:
1853 case IMMED:
1854 case REGLST:
1855 losing++;
1856 break;
1857 default:
1858 break;
1859 }
1860 break;
1861
1862 case '~': /* For now! (JF FOO is this right?) */
1863 switch (opP->mode)
1864 {
1865 case DREG:
1866 case AREG:
1867 case CONTROL:
1868 case FPREG:
1869 case IMMED:
1870 case REGLST:
1871 losing++;
1872 break;
1873 case ABSL:
1874 break;
1875 default:
1876 if (opP->reg == PC
1877 || opP->reg == ZPC)
1878 losing++;
1879 break;
1880 }
1881 break;
1882
1883 case '3':
1884 if (opP->mode != CONTROL
1885 || (opP->reg != TT0 && opP->reg != TT1))
1886 losing++;
1887 break;
1888
1889 case 'A':
1890 if (opP->mode != AREG)
1891 losing++;
1892 break;
1893
1894 case 'a':
1895 if (opP->mode != AINDR)
1896 ++losing;
1897 break;
1898
1899 case '4':
1900 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1901 && (opP->mode != DISP
1902 || opP->reg < ADDR0
1903 || opP->reg > ADDR7))
1904 ++losing;
1905 break;
1906
1907 case 'B': /* FOO */
1908 if (opP->mode != ABSL
1909 || (flag_long_jumps
1910 && strncmp (instring, "jbsr", 4) == 0))
1911 losing++;
1912 break;
1913
1914 case 'b':
1915 switch (opP->mode)
1916 {
1917 case IMMED:
1918 case ABSL:
1919 case AREG:
1920 case FPREG:
1921 case CONTROL:
1922 case POST:
1923 case PRE:
1924 case REGLST:
1925 losing++;
1926 break;
1927 default:
1928 break;
1929 }
1930 break;
1931
1932 case 'C':
1933 if (opP->mode != CONTROL || opP->reg != CCR)
1934 losing++;
1935 break;
1936
1937 case 'd':
1938 if (opP->mode != DISP
1939 || opP->reg < ADDR0
1940 || opP->reg > ADDR7)
1941 losing++;
1942 break;
1943
1944 case 'D':
1945 if (opP->mode != DREG)
1946 losing++;
1947 break;
1948
1949 case 'E':
1950 if (opP->reg != ACC)
1951 losing++;
1952 break;
1953
1954 case 'e':
1955 if (opP->reg != ACC && opP->reg != ACC1
1956 && opP->reg != ACC2 && opP->reg != ACC3)
1957 losing++;
1958 break;
1959
1960 case 'F':
1961 if (opP->mode != FPREG)
1962 losing++;
1963 break;
1964
1965 case 'G':
1966 if (opP->reg != MACSR)
1967 losing++;
1968 break;
1969
1970 case 'g':
1971 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1972 losing++;
1973 break;
1974
1975 case 'H':
1976 if (opP->reg != MASK)
1977 losing++;
1978 break;
1979
1980 case 'I':
1981 if (opP->mode != CONTROL
1982 || opP->reg < COP0
1983 || opP->reg > COP7)
1984 losing++;
1985 break;
1986
1987 case 'i':
1988 if (opP->mode != LSH && opP->mode != RSH)
1989 losing++;
1990 break;
1991
1992 case 'J':
1993 if (opP->mode != CONTROL
1994 || opP->reg < USP
1995 || opP->reg > last_movec_reg
1996 || !control_regs)
1997 losing++;
1998 else
1999 {
2000 const enum m68k_register *rp;
2001
2002 for (rp = control_regs; *rp; rp++)
2003 {
2004 if (*rp == opP->reg)
2005 break;
2006 /* In most CPUs RAMBAR refers to control reg
2007 c05 (RAMBAR1), but a few CPUs have it
2008 refer to c04 (RAMBAR0). */
2009 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
2010 {
2011 opP->reg = RAMBAR_ALT;
2012 break;
2013 }
2014 }
2015 if (*rp == 0)
2016 losing++;
2017 }
2018 break;
2019
2020 case 'k':
2021 if (opP->mode != IMMED)
2022 losing++;
2023 break;
2024
2025 case 'l':
2026 case 'L':
2027 if (opP->mode == DREG
2028 || opP->mode == AREG
2029 || opP->mode == FPREG)
2030 {
2031 if (s[1] == '8')
2032 losing++;
2033 else
2034 {
2035 switch (opP->mode)
2036 {
2037 case DREG:
2038 opP->mask = 1 << (opP->reg - DATA0);
2039 break;
2040 case AREG:
2041 opP->mask = 1 << (opP->reg - ADDR0 + 8);
2042 break;
2043 case FPREG:
2044 opP->mask = 1 << (opP->reg - FP0 + 16);
2045 break;
2046 default:
2047 abort ();
2048 }
2049 opP->mode = REGLST;
2050 }
2051 }
2052 else if (opP->mode == CONTROL)
2053 {
2054 if (s[1] != '8')
2055 losing++;
2056 else
2057 {
2058 switch (opP->reg)
2059 {
2060 case FPI:
2061 opP->mask = 1 << 24;
2062 break;
2063 case FPS:
2064 opP->mask = 1 << 25;
2065 break;
2066 case FPC:
2067 opP->mask = 1 << 26;
2068 break;
2069 default:
2070 losing++;
2071 break;
2072 }
2073 opP->mode = REGLST;
2074 }
2075 }
2076 else if (opP->mode != REGLST)
2077 losing++;
2078 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
2079 losing++;
2080 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
2081 losing++;
2082 break;
2083
2084 case 'M':
2085 if (opP->mode != IMMED)
2086 losing++;
2087 else if (opP->disp.exp.X_op != O_constant
2088 || ! issbyte (opP->disp.exp.X_add_number))
2089 losing++;
2090 else if (! m68k_quick
2091 && instring[3] != 'q'
2092 && instring[4] != 'q')
2093 losing++;
2094 break;
2095
2096 case 'O':
2097 if (opP->mode != DREG
2098 && opP->mode != IMMED
2099 && opP->mode != ABSL)
2100 losing++;
2101 break;
2102
2103 case 'Q':
2104 if (opP->mode != IMMED)
2105 losing++;
2106 else if (opP->disp.exp.X_op != O_constant
2107 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2108 losing++;
2109 else if (! m68k_quick
2110 && (strncmp (instring, "add", 3) == 0
2111 || strncmp (instring, "sub", 3) == 0)
2112 && instring[3] != 'q')
2113 losing++;
2114 break;
2115
2116 case 'R':
2117 if (opP->mode != DREG && opP->mode != AREG)
2118 losing++;
2119 break;
2120
2121 case 'r':
2122 if (opP->mode != AINDR
2123 && (opP->mode != BASE
2124 || (opP->reg != 0
2125 && opP->reg != ZADDR0)
2126 || opP->disp.exp.X_op != O_absent
2127 || ((opP->index.reg < DATA0
2128 || opP->index.reg > DATA7)
2129 && (opP->index.reg < ADDR0
2130 || opP->index.reg > ADDR7))
2131 || opP->index.size != SIZE_UNSPEC
2132 || opP->index.scale != 1))
2133 losing++;
2134 break;
2135
2136 case 's':
2137 if (opP->mode != CONTROL
2138 || ! (opP->reg == FPI
2139 || opP->reg == FPS
2140 || opP->reg == FPC))
2141 losing++;
2142 break;
2143
2144 case 'S':
2145 if (opP->mode != CONTROL || opP->reg != SR)
2146 losing++;
2147 break;
2148
2149 case 't':
2150 if (opP->mode != IMMED)
2151 losing++;
2152 else if (opP->disp.exp.X_op != O_constant
2153 || TRUNC (opP->disp.exp.X_add_number) > 7)
2154 losing++;
2155 break;
2156
2157 case 'U':
2158 if (opP->mode != CONTROL || opP->reg != USP)
2159 losing++;
2160 break;
2161
2162 case 'x':
2163 if (opP->mode != IMMED)
2164 losing++;
2165 else if (opP->disp.exp.X_op != O_constant
2166 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
2167 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
2168 losing++;
2169 break;
2170
2171 case 'j':
2172 if (opP->mode != IMMED)
2173 losing++;
2174 else if (opP->disp.exp.X_op != O_constant
2175 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2176 losing++;
2177 break;
2178
2179 case 'K':
2180 if (opP->mode != IMMED)
2181 losing++;
2182 else if (opP->disp.exp.X_op != O_constant
2183 || TRUNC (opP->disp.exp.X_add_number) > 511)
2184 losing++;
2185 break;
2186
2187 /* JF these are out of order. We could put them
2188 in order if we were willing to put up with
2189 bunches of #ifdef m68851s in the code.
2190
2191 Don't forget that you need these operands
2192 to use 68030 MMU instructions. */
2193 #ifndef NO_68851
2194 /* Memory addressing mode used by pflushr. */
2195 case '|':
2196 if (opP->mode == CONTROL
2197 || opP->mode == FPREG
2198 || opP->mode == DREG
2199 || opP->mode == AREG
2200 || opP->mode == REGLST)
2201 losing++;
2202 /* We should accept immediate operands, but they
2203 supposedly have to be quad word, and we don't
2204 handle that. I would like to see what a Motorola
2205 assembler does before doing something here. */
2206 if (opP->mode == IMMED)
2207 losing++;
2208 break;
2209
2210 case 'f':
2211 if (opP->mode != CONTROL
2212 || (opP->reg != SFC && opP->reg != DFC))
2213 losing++;
2214 break;
2215
2216 case '0':
2217 if (opP->mode != CONTROL || opP->reg != TC)
2218 losing++;
2219 break;
2220
2221 case '1':
2222 if (opP->mode != CONTROL || opP->reg != AC)
2223 losing++;
2224 break;
2225
2226 case '2':
2227 if (opP->mode != CONTROL
2228 || (opP->reg != CAL
2229 && opP->reg != VAL
2230 && opP->reg != SCC))
2231 losing++;
2232 break;
2233
2234 case 'V':
2235 if (opP->mode != CONTROL
2236 || opP->reg != VAL)
2237 losing++;
2238 break;
2239
2240 case 'W':
2241 if (opP->mode != CONTROL
2242 || (opP->reg != DRP
2243 && opP->reg != SRP
2244 && opP->reg != CRP))
2245 losing++;
2246 break;
2247
2248 case 'w':
2249 switch (opP->mode)
2250 {
2251 case IMMED:
2252 case ABSL:
2253 case AREG:
2254 case DREG:
2255 case FPREG:
2256 case CONTROL:
2257 case POST:
2258 case PRE:
2259 case REGLST:
2260 losing++;
2261 break;
2262 default:
2263 break;
2264 }
2265 break;
2266
2267 case 'X':
2268 if (opP->mode != CONTROL
2269 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2270 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2271 losing++;
2272 break;
2273
2274 case 'Y':
2275 if (opP->mode != CONTROL || opP->reg != PSR)
2276 losing++;
2277 break;
2278
2279 case 'Z':
2280 if (opP->mode != CONTROL || opP->reg != PCSR)
2281 losing++;
2282 break;
2283 #endif
2284 case 'c':
2285 if (opP->mode != CONTROL
2286 || (opP->reg != NC
2287 && opP->reg != IC
2288 && opP->reg != DC
2289 && opP->reg != BC))
2290 losing++;
2291 break;
2292
2293 case '_':
2294 if (opP->mode != ABSL)
2295 ++losing;
2296 break;
2297
2298 case 'u':
2299 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2300 losing++;
2301 /* FIXME: kludge instead of fixing parser:
2302 upper/lower registers are *not* CONTROL
2303 registers, but ordinary ones. */
2304 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2305 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2306 opP->mode = DREG;
2307 else
2308 opP->mode = AREG;
2309 break;
2310
2311 case 'y':
2312 if (!(opP->mode == AINDR
2313 || (opP->mode == DISP
2314 && !(opP->reg == PC || opP->reg == ZPC))))
2315 losing++;
2316 break;
2317
2318 case 'z':
2319 if (!(opP->mode == AINDR || opP->mode == DISP))
2320 losing++;
2321 break;
2322
2323 default:
2324 abort ();
2325 }
2326
2327 if (losing)
2328 break;
2329 }
2330
2331 /* Since we have found the correct instruction, copy
2332 in the modifications that we may have made. */
2333 if (!losing)
2334 for (i = 0; i < opsfound; i++)
2335 the_ins.operands[i] = operands_backup[i];
2336 }
2337
2338 if (!losing)
2339 break;
2340
2341 opcode = opcode->m_next;
2342
2343 if (!opcode)
2344 {
2345 if (ok_arch
2346 && !(ok_arch & current_architecture))
2347 {
2348 const struct m68k_cpu *cpu;
2349 int any = 0;
2350 size_t space = 400;
2351 char *buf = XNEWVEC (char, space + 1);
2352 size_t len;
2353 int paren = 1;
2354
2355 the_ins.error = buf;
2356 /* Make sure there's a NUL at the end of the buffer -- strncpy
2357 won't write one when it runs out of buffer. */
2358 buf[space] = 0;
2359 #define APPEND(STRING) \
2360 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2361
2362 APPEND (_("invalid instruction for this architecture; needs "));
2363 switch (ok_arch)
2364 {
2365 case mcfisa_a:
2366 APPEND ("ColdFire ISA_A");
2367 break;
2368 case mcfhwdiv:
2369 APPEND ("ColdFire ");
2370 APPEND (_("hardware divide"));
2371 break;
2372 case mcfisa_aa:
2373 APPEND ("ColdFire ISA_A+");
2374 break;
2375 case mcfisa_b:
2376 APPEND ("ColdFire ISA_B");
2377 break;
2378 case mcfisa_c:
2379 APPEND ("ColdFire ISA_C");
2380 break;
2381 case cfloat:
2382 APPEND ("ColdFire fpu");
2383 break;
2384 case mfloat:
2385 APPEND ("M68K fpu");
2386 break;
2387 case mmmu:
2388 APPEND ("M68K mmu");
2389 break;
2390 case m68020up:
2391 APPEND ("68020 ");
2392 APPEND (_("or higher"));
2393 break;
2394 case m68000up:
2395 APPEND ("68000 ");
2396 APPEND (_("or higher"));
2397 break;
2398 case m68010up:
2399 APPEND ("68010 ");
2400 APPEND (_("or higher"));
2401 break;
2402 default:
2403 paren = 0;
2404 }
2405 if (paren)
2406 APPEND (" (");
2407
2408 for (cpu = m68k_cpus; cpu->name; cpu++)
2409 if (!cpu->alias && (cpu->arch & ok_arch))
2410 {
2411 const struct m68k_cpu *alias;
2412 int seen_master = 0;
2413
2414 if (any)
2415 APPEND (", ");
2416 any = 0;
2417 APPEND (cpu->name);
2418 for (alias = cpu; alias != m68k_cpus; alias--)
2419 if (alias[-1].alias >= 0)
2420 break;
2421 for (; !seen_master || alias->alias > 0; alias++)
2422 {
2423 if (!alias->alias)
2424 seen_master = 1;
2425 else
2426 {
2427 if (any)
2428 APPEND (", ");
2429 else
2430 APPEND (" [");
2431 APPEND (alias->name);
2432 any = 1;
2433 }
2434 }
2435 if (any)
2436 APPEND ("]");
2437 any = 1;
2438 }
2439 if (paren)
2440 APPEND (")");
2441 #undef APPEND
2442 if (!space)
2443 {
2444 /* We ran out of space, so replace the end of the list
2445 with ellipsis. */
2446 buf -= 4;
2447 while (*buf != ' ')
2448 buf--;
2449 strcpy (buf, " ...");
2450 }
2451 }
2452 else
2453 the_ins.error = _("operands mismatch");
2454 return;
2455 }
2456
2457 losing = 0;
2458 }
2459
2460 /* Now assemble it. */
2461 the_ins.args = opcode->m_operands;
2462 the_ins.numargs = opcode->m_opnum;
2463 the_ins.numo = opcode->m_codenum;
2464 the_ins.opcode[0] = getone (opcode);
2465 the_ins.opcode[1] = gettwo (opcode);
2466
2467 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2468 {
2469 int have_disp = 0;
2470 int use_pl = 0;
2471
2472 /* This switch is a doozy.
2473 Watch the first step; it's a big one! */
2474 switch (s[0])
2475 {
2476
2477 case '*':
2478 case '~':
2479 case '%':
2480 case ';':
2481 case '@':
2482 case '!':
2483 case '&':
2484 case '$':
2485 case '?':
2486 case '/':
2487 case '<':
2488 case '>':
2489 case 'b':
2490 case 'm':
2491 case 'n':
2492 case 'o':
2493 case 'p':
2494 case 'q':
2495 case 'v':
2496 case 'w':
2497 case 'y':
2498 case 'z':
2499 case '4':
2500 #ifndef NO_68851
2501 case '|':
2502 #endif
2503 switch (opP->mode)
2504 {
2505 case IMMED:
2506 tmpreg = 0x3c; /* 7.4 */
2507 if (strchr ("bwl", s[1]))
2508 nextword = get_num (&opP->disp, 90);
2509 else
2510 nextword = get_num (&opP->disp, 0);
2511 if (isvar (&opP->disp))
2512 add_fix (s[1], &opP->disp, 0, 0);
2513 switch (s[1])
2514 {
2515 case 'b':
2516 if (!isbyte (nextword))
2517 opP->error = _("operand out of range");
2518 addword (nextword);
2519 baseo = 0;
2520 break;
2521 case 'w':
2522 if (!isword (nextword))
2523 opP->error = _("operand out of range");
2524 addword (nextword);
2525 baseo = 0;
2526 break;
2527 case 'W':
2528 if (!issword (nextword))
2529 opP->error = _("operand out of range");
2530 addword (nextword);
2531 baseo = 0;
2532 break;
2533 case 'l':
2534 addword (nextword >> 16);
2535 addword (nextword);
2536 baseo = 0;
2537 break;
2538
2539 case 'f':
2540 baseo = 2;
2541 outro = 8;
2542 break;
2543 case 'F':
2544 baseo = 4;
2545 outro = 11;
2546 break;
2547 case 'x':
2548 baseo = 6;
2549 outro = 15;
2550 break;
2551 case 'p':
2552 baseo = 6;
2553 outro = -1;
2554 break;
2555 default:
2556 abort ();
2557 }
2558 if (!baseo)
2559 break;
2560
2561 /* We gotta put out some float. */
2562 if (op (&opP->disp) != O_big)
2563 {
2564 valueT val;
2565 int gencnt;
2566
2567 /* Can other cases happen here? */
2568 if (op (&opP->disp) != O_constant)
2569 abort ();
2570
2571 val = (valueT) offs (&opP->disp);
2572 gencnt = 0;
2573 do
2574 {
2575 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2576 val >>= LITTLENUM_NUMBER_OF_BITS;
2577 ++gencnt;
2578 }
2579 while (val != 0);
2580 offs (&opP->disp) = gencnt;
2581 }
2582 if (offs (&opP->disp) > 0)
2583 {
2584 if (offs (&opP->disp) > baseo)
2585 {
2586 as_warn (_("Bignum too big for %c format; truncated"),
2587 s[1]);
2588 offs (&opP->disp) = baseo;
2589 }
2590 baseo -= offs (&opP->disp);
2591 while (baseo--)
2592 addword (0);
2593 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2594 offs (&opP->disp)--;
2595 --wordp)
2596 addword (*wordp);
2597 break;
2598 }
2599 gen_to_words (words, baseo, (long) outro);
2600 for (wordp = words; baseo--; wordp++)
2601 addword (*wordp);
2602 break;
2603 case DREG:
2604 tmpreg = opP->reg - DATA; /* 0.dreg */
2605 break;
2606 case AREG:
2607 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2608 break;
2609 case AINDR:
2610 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2611 break;
2612 case ADEC:
2613 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2614 break;
2615 case AINC:
2616 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2617 break;
2618 case DISP:
2619
2620 nextword = get_num (&opP->disp, 90);
2621
2622 /* Convert mode 5 addressing with a zero offset into
2623 mode 2 addressing to reduce the instruction size by a
2624 word. */
2625 if (! isvar (&opP->disp)
2626 && (nextword == 0)
2627 && (opP->disp.size == SIZE_UNSPEC)
2628 && (opP->reg >= ADDR0)
2629 && (opP->reg <= ADDR7))
2630 {
2631 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2632 break;
2633 }
2634
2635 if (opP->reg == PC
2636 && ! isvar (&opP->disp)
2637 && m68k_abspcadd)
2638 {
2639 opP->disp.exp.X_op = O_symbol;
2640 opP->disp.exp.X_add_symbol =
2641 section_symbol (absolute_section);
2642 }
2643
2644 /* Force into index mode. Hope this works. */
2645
2646 /* We do the first bit for 32-bit displacements, and the
2647 second bit for 16 bit ones. It is possible that we
2648 should make the default be WORD instead of LONG, but
2649 I think that'd break GCC, so we put up with a little
2650 inefficiency for the sake of working output. */
2651
2652 if (!issword (nextword)
2653 || (isvar (&opP->disp)
2654 && ((opP->disp.size == SIZE_UNSPEC
2655 && flag_short_refs == 0
2656 && cpu_of_arch (current_architecture) >= m68020
2657 && ! arch_coldfire_p (current_architecture))
2658 || opP->disp.size == SIZE_LONG)))
2659 {
2660 if (cpu_of_arch (current_architecture) < m68020
2661 || arch_coldfire_p (current_architecture))
2662 opP->error =
2663 _("displacement too large for this architecture; needs 68020 or higher");
2664 if (opP->reg == PC)
2665 tmpreg = 0x3B; /* 7.3 */
2666 else
2667 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2668 if (isvar (&opP->disp))
2669 {
2670 if (opP->reg == PC)
2671 {
2672 if (opP->disp.size == SIZE_LONG
2673 #ifdef OBJ_ELF
2674 /* If the displacement needs pic
2675 relocation it cannot be relaxed. */
2676 || opP->disp.pic_reloc != pic_none
2677 #endif
2678 )
2679 {
2680 addword (0x0170);
2681 add_fix ('l', &opP->disp, 1, 2);
2682 }
2683 else
2684 {
2685 add_frag (adds (&opP->disp),
2686 SEXT (offs (&opP->disp)),
2687 TAB (PCREL1632, SZ_UNDEF));
2688 break;
2689 }
2690 }
2691 else
2692 {
2693 addword (0x0170);
2694 add_fix ('l', &opP->disp, 0, 0);
2695 }
2696 }
2697 else
2698 addword (0x0170);
2699 addword (nextword >> 16);
2700 }
2701 else
2702 {
2703 if (opP->reg == PC)
2704 tmpreg = 0x3A; /* 7.2 */
2705 else
2706 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2707
2708 if (isvar (&opP->disp))
2709 {
2710 if (opP->reg == PC)
2711 {
2712 add_fix ('w', &opP->disp, 1, 0);
2713 }
2714 else
2715 add_fix ('w', &opP->disp, 0, 0);
2716 }
2717 }
2718 addword (nextword);
2719 break;
2720
2721 case POST:
2722 case PRE:
2723 case BASE:
2724 nextword = 0;
2725 baseo = get_num (&opP->disp, 90);
2726 if (opP->mode == POST || opP->mode == PRE)
2727 outro = get_num (&opP->odisp, 90);
2728 /* Figure out the `addressing mode'.
2729 Also turn on the BASE_DISABLE bit, if needed. */
2730 if (opP->reg == PC || opP->reg == ZPC)
2731 {
2732 tmpreg = 0x3b; /* 7.3 */
2733 if (opP->reg == ZPC)
2734 nextword |= 0x80;
2735 }
2736 else if (opP->reg == 0)
2737 {
2738 nextword |= 0x80;
2739 tmpreg = 0x30; /* 6.garbage */
2740 }
2741 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2742 {
2743 nextword |= 0x80;
2744 tmpreg = 0x30 + opP->reg - ZADDR0;
2745 }
2746 else
2747 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2748
2749 siz1 = opP->disp.size;
2750 if (opP->mode == POST || opP->mode == PRE)
2751 siz2 = opP->odisp.size;
2752 else
2753 siz2 = SIZE_UNSPEC;
2754
2755 /* Index register stuff. */
2756 if (opP->index.reg != 0
2757 && opP->index.reg >= DATA
2758 && opP->index.reg <= ADDR7)
2759 {
2760 nextword |= (opP->index.reg - DATA) << 12;
2761
2762 if (opP->index.size == SIZE_LONG
2763 || (opP->index.size == SIZE_UNSPEC
2764 && m68k_index_width_default == SIZE_LONG))
2765 nextword |= 0x800;
2766
2767 if ((opP->index.scale != 1
2768 && cpu_of_arch (current_architecture) < m68020)
2769 || (opP->index.scale == 8
2770 && (arch_coldfire_p (current_architecture)
2771 && !arch_coldfire_fpu (current_architecture))))
2772 {
2773 opP->error =
2774 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2775 }
2776
2777 if (arch_coldfire_p (current_architecture)
2778 && opP->index.size == SIZE_WORD)
2779 opP->error = _("invalid index size for coldfire");
2780
2781 switch (opP->index.scale)
2782 {
2783 case 1:
2784 break;
2785 case 2:
2786 nextword |= 0x200;
2787 break;
2788 case 4:
2789 nextword |= 0x400;
2790 break;
2791 case 8:
2792 nextword |= 0x600;
2793 break;
2794 default:
2795 abort ();
2796 }
2797 /* IF it's simple,
2798 GET US OUT OF HERE! */
2799
2800 /* Must be INDEX, with an index register. Address
2801 register cannot be ZERO-PC, and either :b was
2802 forced, or we know it will fit. For a 68000 or
2803 68010, force this mode anyways, because the
2804 larger modes aren't supported. */
2805 if (opP->mode == BASE
2806 && ((opP->reg >= ADDR0
2807 && opP->reg <= ADDR7)
2808 || opP->reg == PC))
2809 {
2810 if (siz1 == SIZE_BYTE
2811 || cpu_of_arch (current_architecture) < m68020
2812 || arch_coldfire_p (current_architecture)
2813 || (siz1 == SIZE_UNSPEC
2814 && ! isvar (&opP->disp)
2815 && issbyte (baseo)))
2816 {
2817 nextword += baseo & 0xff;
2818 addword (nextword);
2819 if (isvar (&opP->disp))
2820 {
2821 /* Do a byte relocation. If it doesn't
2822 fit (possible on m68000) let the
2823 fixup processing complain later. */
2824 if (opP->reg == PC)
2825 add_fix ('B', &opP->disp, 1, 1);
2826 else
2827 add_fix ('B', &opP->disp, 0, 0);
2828 }
2829 else if (siz1 != SIZE_BYTE)
2830 {
2831 if (siz1 != SIZE_UNSPEC)
2832 as_warn (_("Forcing byte displacement"));
2833 if (! issbyte (baseo))
2834 opP->error = _("byte displacement out of range");
2835 }
2836
2837 break;
2838 }
2839 else if (siz1 == SIZE_UNSPEC
2840 && opP->reg == PC
2841 && isvar (&opP->disp)
2842 && subs (&opP->disp) == NULL
2843 #ifdef OBJ_ELF
2844 /* If the displacement needs pic
2845 relocation it cannot be relaxed. */
2846 && opP->disp.pic_reloc == pic_none
2847 #endif
2848 )
2849 {
2850 /* The code in md_convert_frag_1 needs to be
2851 able to adjust nextword. Call frag_grow
2852 to ensure that we have enough space in
2853 the frag obstack to make all the bytes
2854 contiguous. */
2855 frag_grow (14);
2856 nextword += baseo & 0xff;
2857 addword (nextword);
2858 add_frag (adds (&opP->disp),
2859 SEXT (offs (&opP->disp)),
2860 TAB (PCINDEX, SZ_UNDEF));
2861
2862 break;
2863 }
2864 }
2865 }
2866 else
2867 {
2868 nextword |= 0x40; /* No index reg. */
2869 if (opP->index.reg >= ZDATA0
2870 && opP->index.reg <= ZDATA7)
2871 nextword |= (opP->index.reg - ZDATA0) << 12;
2872 else if (opP->index.reg >= ZADDR0
2873 || opP->index.reg <= ZADDR7)
2874 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2875 }
2876
2877 /* It isn't simple. */
2878
2879 if (cpu_of_arch (current_architecture) < m68020
2880 || arch_coldfire_p (current_architecture))
2881 opP->error =
2882 _("invalid operand mode for this architecture; needs 68020 or higher");
2883
2884 nextword |= 0x100;
2885 /* If the guy specified a width, we assume that it is
2886 wide enough. Maybe it isn't. If so, we lose. */
2887 switch (siz1)
2888 {
2889 case SIZE_UNSPEC:
2890 if (isvar (&opP->disp)
2891 ? m68k_rel32
2892 : ! issword (baseo))
2893 {
2894 siz1 = SIZE_LONG;
2895 nextword |= 0x30;
2896 }
2897 else if (! isvar (&opP->disp) && baseo == 0)
2898 nextword |= 0x10;
2899 else
2900 {
2901 nextword |= 0x20;
2902 siz1 = SIZE_WORD;
2903 }
2904 break;
2905 case SIZE_BYTE:
2906 as_warn (_(":b not permitted; defaulting to :w"));
2907 /* Fall through. */
2908 case SIZE_WORD:
2909 nextword |= 0x20;
2910 break;
2911 case SIZE_LONG:
2912 nextword |= 0x30;
2913 break;
2914 }
2915
2916 /* Figure out inner displacement stuff. */
2917 if (opP->mode == POST || opP->mode == PRE)
2918 {
2919 if (cpu_of_arch (current_architecture) & cpu32)
2920 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2921 switch (siz2)
2922 {
2923 case SIZE_UNSPEC:
2924 if (isvar (&opP->odisp)
2925 ? m68k_rel32
2926 : ! issword (outro))
2927 {
2928 siz2 = SIZE_LONG;
2929 nextword |= 0x3;
2930 }
2931 else if (! isvar (&opP->odisp) && outro == 0)
2932 nextword |= 0x1;
2933 else
2934 {
2935 nextword |= 0x2;
2936 siz2 = SIZE_WORD;
2937 }
2938 break;
2939 case 1:
2940 as_warn (_(":b not permitted; defaulting to :w"));
2941 /* Fall through. */
2942 case 2:
2943 nextword |= 0x2;
2944 break;
2945 case 3:
2946 nextword |= 0x3;
2947 break;
2948 }
2949 if (opP->mode == POST
2950 && (nextword & 0x40) == 0)
2951 nextword |= 0x04;
2952 }
2953 addword (nextword);
2954
2955 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2956 {
2957 if (opP->reg == PC || opP->reg == ZPC)
2958 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2959 else
2960 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2961 }
2962 if (siz1 == SIZE_LONG)
2963 addword (baseo >> 16);
2964 if (siz1 != SIZE_UNSPEC)
2965 addword (baseo);
2966
2967 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2968 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2969 if (siz2 == SIZE_LONG)
2970 addword (outro >> 16);
2971 if (siz2 != SIZE_UNSPEC)
2972 addword (outro);
2973
2974 break;
2975
2976 case ABSL:
2977 nextword = get_num (&opP->disp, 90);
2978 switch (opP->disp.size)
2979 {
2980 default:
2981 abort ();
2982 case SIZE_UNSPEC:
2983 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2984 {
2985 tmpreg = 0x38; /* 7.0 */
2986 addword (nextword);
2987 break;
2988 }
2989 if (isvar (&opP->disp)
2990 && !subs (&opP->disp)
2991 && adds (&opP->disp)
2992 #ifdef OBJ_ELF
2993 /* If the displacement needs pic relocation it
2994 cannot be relaxed. */
2995 && opP->disp.pic_reloc == pic_none
2996 #endif
2997 && !flag_long_jumps
2998 && !strchr ("~%&$?", s[0]))
2999 {
3000 tmpreg = 0x3A; /* 7.2 */
3001 add_frag (adds (&opP->disp),
3002 SEXT (offs (&opP->disp)),
3003 TAB (ABSTOPCREL, SZ_UNDEF));
3004 break;
3005 }
3006 /* Fall through. */
3007 case SIZE_LONG:
3008 if (isvar (&opP->disp))
3009 add_fix ('l', &opP->disp, 0, 0);
3010
3011 tmpreg = 0x39;/* 7.1 mode */
3012 addword (nextword >> 16);
3013 addword (nextword);
3014 break;
3015
3016 case SIZE_BYTE:
3017 as_bad (_("unsupported byte value; use a different suffix"));
3018 /* Fall through. */
3019
3020 case SIZE_WORD:
3021 if (isvar (&opP->disp))
3022 add_fix ('w', &opP->disp, 0, 0);
3023
3024 tmpreg = 0x38;/* 7.0 mode */
3025 addword (nextword);
3026 break;
3027 }
3028 break;
3029 case CONTROL:
3030 case FPREG:
3031 default:
3032 as_bad (_("unknown/incorrect operand"));
3033 /* abort (); */
3034 }
3035
3036 /* If s[0] is '4', then this is for the mac instructions
3037 that can have a trailing_ampersand set. If so, set 0x100
3038 bit on tmpreg so install_gen_operand can check for it and
3039 set the appropriate bit (word2, bit 5). */
3040 if (s[0] == '4')
3041 {
3042 if (opP->trailing_ampersand)
3043 tmpreg |= 0x100;
3044 }
3045 install_gen_operand (s[1], tmpreg);
3046 break;
3047
3048 case '#':
3049 case '^':
3050 switch (s[1])
3051 { /* JF: I hate floating point! */
3052 case 'j':
3053 tmpreg = 70;
3054 break;
3055 case '8':
3056 tmpreg = 20;
3057 break;
3058 case 'C':
3059 tmpreg = 50;
3060 break;
3061 case '3':
3062 default:
3063 tmpreg = 90;
3064 break;
3065 }
3066 tmpreg = get_num (&opP->disp, tmpreg);
3067 if (isvar (&opP->disp))
3068 add_fix (s[1], &opP->disp, 0, 0);
3069 switch (s[1])
3070 {
3071 case 'b': /* Danger: These do no check for
3072 certain types of overflow.
3073 user beware! */
3074 if (!isbyte (tmpreg))
3075 opP->error = _("out of range");
3076 insop (tmpreg, opcode);
3077 if (isvar (&opP->disp))
3078 the_ins.reloc[the_ins.nrel - 1].n =
3079 (opcode->m_codenum) * 2 + 1;
3080 break;
3081 case 'B':
3082 if (!issbyte (tmpreg))
3083 opP->error = _("out of range");
3084 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
3085 if (isvar (&opP->disp))
3086 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
3087 break;
3088 case 'w':
3089 if (!isword (tmpreg))
3090 opP->error = _("out of range");
3091 insop (tmpreg, opcode);
3092 if (isvar (&opP->disp))
3093 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3094 break;
3095 case 'W':
3096 if (!issword (tmpreg))
3097 opP->error = _("out of range");
3098 insop (tmpreg, opcode);
3099 if (isvar (&opP->disp))
3100 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3101 break;
3102 case 'l':
3103 /* Because of the way insop works, we put these two out
3104 backwards. */
3105 insop (tmpreg, opcode);
3106 insop (tmpreg >> 16, opcode);
3107 if (isvar (&opP->disp))
3108 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3109 break;
3110 case '3':
3111 tmpreg &= 0xFF;
3112 /* Fall through. */
3113 case '8':
3114 case 'C':
3115 case 'j':
3116 install_operand (s[1], tmpreg);
3117 break;
3118 default:
3119 abort ();
3120 }
3121 break;
3122
3123 case '+':
3124 case '-':
3125 case 'A':
3126 case 'a':
3127 install_operand (s[1], opP->reg - ADDR);
3128 break;
3129
3130 case 'B':
3131 tmpreg = get_num (&opP->disp, 90);
3132
3133 switch (s[1])
3134 {
3135 case 'B':
3136 add_fix ('B', &opP->disp, 1, -1);
3137 break;
3138 case 'W':
3139 add_fix ('w', &opP->disp, 1, 0);
3140 addword (0);
3141 break;
3142 case 'L':
3143 long_branch:
3144 the_ins.opcode[0] |= 0xff;
3145 add_fix ('l', &opP->disp, 1, 0);
3146 addword (0);
3147 addword (0);
3148 break;
3149 case 'g': /* Conditional branch */
3150 have_disp = HAVE_LONG_CALL (current_architecture);
3151 goto var_branch;
3152
3153 case 'b': /* Unconditional branch */
3154 have_disp = HAVE_LONG_BRANCH (current_architecture);
3155 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
3156 goto var_branch;
3157
3158 case 's': /* Unconditional subroutine */
3159 have_disp = HAVE_LONG_CALL (current_architecture);
3160
3161 var_branch:
3162 if (subs (&opP->disp) /* We can't relax it. */
3163 #ifdef OBJ_ELF
3164 /* If the displacement needs pic relocation it cannot be
3165 relaxed. */
3166 || opP->disp.pic_reloc != pic_none
3167 #endif
3168 || 0)
3169 {
3170 if (!have_disp)
3171 as_warn (_("Can't use long branches on this architecture"));
3172 goto long_branch;
3173 }
3174
3175 /* This could either be a symbol, or an absolute
3176 address. If it's an absolute address, turn it into
3177 an absolute jump right here and keep it out of the
3178 relaxer. */
3179 if (adds (&opP->disp) == 0)
3180 {
3181 if (the_ins.opcode[0] == 0x6000) /* jbra */
3182 the_ins.opcode[0] = 0x4EF9;
3183 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
3184 the_ins.opcode[0] = 0x4EB9;
3185 else /* jCC */
3186 {
3187 the_ins.opcode[0] ^= 0x0100;
3188 the_ins.opcode[0] |= 0x0006;
3189 addword (0x4EF9);
3190 }
3191 add_fix ('l', &opP->disp, 0, 0);
3192 addword (0);
3193 addword (0);
3194 break;
3195 }
3196
3197 /* Now we know it's going into the relaxer. Now figure
3198 out which mode. We try in this order of preference:
3199 long branch, absolute jump, byte/word branches only. */
3200 if (have_disp)
3201 add_frag (adds (&opP->disp),
3202 SEXT (offs (&opP->disp)),
3203 TAB (BRANCHBWL, SZ_UNDEF));
3204 else if (! flag_keep_pcrel)
3205 {
3206 if ((the_ins.opcode[0] == 0x6000)
3207 || (the_ins.opcode[0] == 0x6100))
3208 add_frag (adds (&opP->disp),
3209 SEXT (offs (&opP->disp)),
3210 TAB (BRABSJUNC, SZ_UNDEF));
3211 else
3212 add_frag (adds (&opP->disp),
3213 SEXT (offs (&opP->disp)),
3214 TAB (BRABSJCOND, SZ_UNDEF));
3215 }
3216 else
3217 add_frag (adds (&opP->disp),
3218 SEXT (offs (&opP->disp)),
3219 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3220 : TAB (BRANCHBW, SZ_UNDEF)));
3221 break;
3222 case 'w':
3223 if (isvar (&opP->disp))
3224 {
3225 /* Check for DBcc instructions. We can relax them,
3226 but only if we have long branches and/or absolute
3227 jumps. */
3228 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3229 && (HAVE_LONG_BRANCH (current_architecture)
3230 || ! flag_keep_pcrel))
3231 {
3232 if (HAVE_LONG_BRANCH (current_architecture))
3233 add_frag (adds (&opP->disp),
3234 SEXT (offs (&opP->disp)),
3235 TAB (DBCCLBR, SZ_UNDEF));
3236 else
3237 add_frag (adds (&opP->disp),
3238 SEXT (offs (&opP->disp)),
3239 TAB (DBCCABSJ, SZ_UNDEF));
3240 break;
3241 }
3242 add_fix ('w', &opP->disp, 1, 0);
3243 }
3244 addword (0);
3245 break;
3246 case 'C': /* Fixed size LONG coproc branches. */
3247 add_fix ('l', &opP->disp, 1, 0);
3248 addword (0);
3249 addword (0);
3250 break;
3251 case 'c': /* Var size Coprocesssor branches. */
3252 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3253 {
3254 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3255 add_fix ('l', &opP->disp, 1, 0);
3256 addword (0);
3257 addword (0);
3258 }
3259 else
3260 add_frag (adds (&opP->disp),
3261 SEXT (offs (&opP->disp)),
3262 TAB (FBRANCH, SZ_UNDEF));
3263 break;
3264 default:
3265 abort ();
3266 }
3267 break;
3268
3269 case 'C': /* Ignore it. */
3270 break;
3271
3272 case 'd': /* JF this is a kludge. */
3273 install_operand ('s', opP->reg - ADDR);
3274 tmpreg = get_num (&opP->disp, 90);
3275 if (!issword (tmpreg))
3276 {
3277 as_warn (_("Expression out of range, using 0"));
3278 tmpreg = 0;
3279 }
3280 addword (tmpreg);
3281 break;
3282
3283 case 'D':
3284 install_operand (s[1], opP->reg - DATA);
3285 break;
3286
3287 case 'e': /* EMAC ACCx, reg/reg. */
3288 install_operand (s[1], opP->reg - ACC);
3289 break;
3290
3291 case 'E': /* Ignore it. */
3292 break;
3293
3294 case 'F':
3295 install_operand (s[1], opP->reg - FP0);
3296 break;
3297
3298 case 'g': /* EMAC ACCEXTx. */
3299 install_operand (s[1], opP->reg - ACCEXT01);
3300 break;
3301
3302 case 'G': /* Ignore it. */
3303 case 'H':
3304 break;
3305
3306 case 'I':
3307 tmpreg = opP->reg - COP0;
3308 install_operand (s[1], tmpreg);
3309 break;
3310
3311 case 'i': /* MAC/EMAC scale factor. */
3312 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3313 break;
3314
3315 case 'J': /* JF foo. */
3316 switch (opP->reg)
3317 {
3318 case SFC:
3319 tmpreg = 0x000;
3320 break;
3321 case DFC:
3322 tmpreg = 0x001;
3323 break;
3324 case CACR:
3325 tmpreg = 0x002;
3326 break;
3327 case TC:
3328 case ASID:
3329 tmpreg = 0x003;
3330 break;
3331 case ACR0:
3332 case ITT0:
3333 tmpreg = 0x004;
3334 break;
3335 case ACR1:
3336 case ITT1:
3337 tmpreg = 0x005;
3338 break;
3339 case ACR2:
3340 case DTT0:
3341 tmpreg = 0x006;
3342 break;
3343 case ACR3:
3344 case DTT1:
3345 tmpreg = 0x007;
3346 break;
3347 case BUSCR:
3348 case MMUBAR:
3349 tmpreg = 0x008;
3350 break;
3351 case RGPIOBAR:
3352 tmpreg = 0x009;
3353 break;
3354 case ACR4:
3355 case ACR5:
3356 case ACR6:
3357 case ACR7:
3358 tmpreg = 0x00c + (opP->reg - ACR4);
3359 break;
3360
3361 case USP:
3362 tmpreg = 0x800;
3363 break;
3364 case VBR:
3365 tmpreg = 0x801;
3366 break;
3367 case CAAR:
3368 case CPUCR:
3369 tmpreg = 0x802;
3370 break;
3371 case MSP:
3372 tmpreg = 0x803;
3373 break;
3374 case ISP:
3375 tmpreg = 0x804;
3376 break;
3377 case MMUSR:
3378 tmpreg = 0x805;
3379 break;
3380 case URP:
3381 tmpreg = 0x806;
3382 break;
3383 case SRP:
3384 tmpreg = 0x807;
3385 break;
3386 case PCR:
3387 tmpreg = 0x808;
3388 break;
3389 case ROMBAR:
3390 case ROMBAR0:
3391 tmpreg = 0xC00;
3392 break;
3393 case ROMBAR1:
3394 tmpreg = 0xC01;
3395 break;
3396 case FLASHBAR:
3397 case RAMBAR0:
3398 case RAMBAR_ALT:
3399 tmpreg = 0xC04;
3400 break;
3401 case RAMBAR:
3402 case RAMBAR1:
3403 tmpreg = 0xC05;
3404 break;
3405 case MPCR:
3406 tmpreg = 0xC0C;
3407 break;
3408 case EDRAMBAR:
3409 tmpreg = 0xC0D;
3410 break;
3411 case MBAR0:
3412 case MBAR2:
3413 case SECMBAR:
3414 tmpreg = 0xC0E;
3415 break;
3416 case MBAR1:
3417 case MBAR:
3418 tmpreg = 0xC0F;
3419 break;
3420 case PCR1U0:
3421 tmpreg = 0xD02;
3422 break;
3423 case PCR1L0:
3424 tmpreg = 0xD03;
3425 break;
3426 case PCR2U0:
3427 tmpreg = 0xD04;
3428 break;
3429 case PCR2L0:
3430 tmpreg = 0xD05;
3431 break;
3432 case PCR3U0:
3433 tmpreg = 0xD06;
3434 break;
3435 case PCR3L0:
3436 tmpreg = 0xD07;
3437 break;
3438 case PCR1L1:
3439 tmpreg = 0xD0A;
3440 break;
3441 case PCR1U1:
3442 tmpreg = 0xD0B;
3443 break;
3444 case PCR2L1:
3445 tmpreg = 0xD0C;
3446 break;
3447 case PCR2U1:
3448 tmpreg = 0xD0D;
3449 break;
3450 case PCR3L1:
3451 tmpreg = 0xD0E;
3452 break;
3453 case PCR3U1:
3454 tmpreg = 0xD0F;
3455 break;
3456 case CAC:
3457 tmpreg = 0xFFE;
3458 break;
3459 case MBO:
3460 tmpreg = 0xFFF;
3461 break;
3462 default:
3463 abort ();
3464 }
3465 install_operand (s[1], tmpreg);
3466 break;
3467
3468 case 'k':
3469 tmpreg = get_num (&opP->disp, 55);
3470 install_operand (s[1], tmpreg & 0x7f);
3471 break;
3472
3473 case 'l':
3474 tmpreg = opP->mask;
3475 if (s[1] == 'w')
3476 {
3477 if (tmpreg & 0x7FF0000)
3478 as_bad (_("Floating point register in register list"));
3479 insop (reverse_16_bits (tmpreg), opcode);
3480 }
3481 else
3482 {
3483 if (tmpreg & 0x700FFFF)
3484 as_bad (_("Wrong register in floating-point reglist"));
3485 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3486 }
3487 break;
3488
3489 case 'L':
3490 tmpreg = opP->mask;
3491 if (s[1] == 'w')
3492 {
3493 if (tmpreg & 0x7FF0000)
3494 as_bad (_("Floating point register in register list"));
3495 insop (tmpreg, opcode);
3496 }
3497 else if (s[1] == '8')
3498 {
3499 if (tmpreg & 0x0FFFFFF)
3500 as_bad (_("incorrect register in reglist"));
3501 install_operand (s[1], tmpreg >> 24);
3502 }
3503 else
3504 {
3505 if (tmpreg & 0x700FFFF)
3506 as_bad (_("wrong register in floating-point reglist"));
3507 else
3508 install_operand (s[1], tmpreg >> 16);
3509 }
3510 break;
3511
3512 case 'M':
3513 install_operand (s[1], get_num (&opP->disp, 60));
3514 break;
3515
3516 case 'O':
3517 tmpreg = ((opP->mode == DREG)
3518 ? 0x20 + (int) (opP->reg - DATA)
3519 : (get_num (&opP->disp, 40) & 0x1F));
3520 install_operand (s[1], tmpreg);
3521 break;
3522
3523 case 'Q':
3524 tmpreg = get_num (&opP->disp, 10);
3525 if (tmpreg == 8)
3526 tmpreg = 0;
3527 install_operand (s[1], tmpreg);
3528 break;
3529
3530 case 'R':
3531 /* This depends on the fact that ADDR registers are eight
3532 more than their corresponding DATA regs, so the result
3533 will have the ADDR_REG bit set. */
3534 install_operand (s[1], opP->reg - DATA);
3535 break;
3536
3537 case 'r':
3538 if (opP->mode == AINDR)
3539 install_operand (s[1], opP->reg - DATA);
3540 else
3541 install_operand (s[1], opP->index.reg - DATA);
3542 break;
3543
3544 case 's':
3545 if (opP->reg == FPI)
3546 tmpreg = 0x1;
3547 else if (opP->reg == FPS)
3548 tmpreg = 0x2;
3549 else if (opP->reg == FPC)
3550 tmpreg = 0x4;
3551 else
3552 abort ();
3553 install_operand (s[1], tmpreg);
3554 break;
3555
3556 case 'S': /* Ignore it. */
3557 break;
3558
3559 case 'T':
3560 install_operand (s[1], get_num (&opP->disp, 30));
3561 break;
3562
3563 case 'U': /* Ignore it. */
3564 break;
3565
3566 case 'c':
3567 switch (opP->reg)
3568 {
3569 case NC:
3570 tmpreg = 0;
3571 break;
3572 case DC:
3573 tmpreg = 1;
3574 break;
3575 case IC:
3576 tmpreg = 2;
3577 break;
3578 case BC:
3579 tmpreg = 3;
3580 break;
3581 default:
3582 as_fatal (_("failed sanity check"));
3583 } /* switch on cache token. */
3584 install_operand (s[1], tmpreg);
3585 break;
3586 #ifndef NO_68851
3587 /* JF: These are out of order, I fear. */
3588 case 'f':
3589 switch (opP->reg)
3590 {
3591 case SFC:
3592 tmpreg = 0;
3593 break;
3594 case DFC:
3595 tmpreg = 1;
3596 break;
3597 default:
3598 abort ();
3599 }
3600 install_operand (s[1], tmpreg);
3601 break;
3602
3603 case '0':
3604 case '1':
3605 case '2':
3606 switch (opP->reg)
3607 {
3608 case TC:
3609 tmpreg = 0;
3610 break;
3611 case CAL:
3612 tmpreg = 4;
3613 break;
3614 case VAL:
3615 tmpreg = 5;
3616 break;
3617 case SCC:
3618 tmpreg = 6;
3619 break;
3620 case AC:
3621 tmpreg = 7;
3622 break;
3623 default:
3624 abort ();
3625 }
3626 install_operand (s[1], tmpreg);
3627 break;
3628
3629 case 'V':
3630 if (opP->reg == VAL)
3631 break;
3632 abort ();
3633
3634 case 'W':
3635 switch (opP->reg)
3636 {
3637 case DRP:
3638 tmpreg = 1;
3639 break;
3640 case SRP:
3641 tmpreg = 2;
3642 break;
3643 case CRP:
3644 tmpreg = 3;
3645 break;
3646 default:
3647 abort ();
3648 }
3649 install_operand (s[1], tmpreg);
3650 break;
3651
3652 case 'X':
3653 switch (opP->reg)
3654 {
3655 case BAD:
3656 case BAD + 1:
3657 case BAD + 2:
3658 case BAD + 3:
3659 case BAD + 4:
3660 case BAD + 5:
3661 case BAD + 6:
3662 case BAD + 7:
3663 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3664 break;
3665
3666 case BAC:
3667 case BAC + 1:
3668 case BAC + 2:
3669 case BAC + 3:
3670 case BAC + 4:
3671 case BAC + 5:
3672 case BAC + 6:
3673 case BAC + 7:
3674 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3675 break;
3676
3677 default:
3678 abort ();
3679 }
3680 install_operand (s[1], tmpreg);
3681 break;
3682 case 'Y':
3683 know (opP->reg == PSR);
3684 break;
3685 case 'Z':
3686 know (opP->reg == PCSR);
3687 break;
3688 #endif /* m68851 */
3689 case '3':
3690 switch (opP->reg)
3691 {
3692 case TT0:
3693 tmpreg = 2;
3694 break;
3695 case TT1:
3696 tmpreg = 3;
3697 break;
3698 default:
3699 abort ();
3700 }
3701 install_operand (s[1], tmpreg);
3702 break;
3703 case 't':
3704 tmpreg = get_num (&opP->disp, 20);
3705 install_operand (s[1], tmpreg);
3706 break;
3707 case '_': /* used only for move16 absolute 32-bit address. */
3708 if (isvar (&opP->disp))
3709 add_fix ('l', &opP->disp, 0, 0);
3710 tmpreg = get_num (&opP->disp, 90);
3711 addword (tmpreg >> 16);
3712 addword (tmpreg & 0xFFFF);
3713 break;
3714 case 'u':
3715 install_operand (s[1], opP->reg - DATA0L);
3716 opP->reg -= (DATA0L);
3717 opP->reg &= 0x0F; /* remove upper/lower bit. */
3718 break;
3719 case 'x':
3720 tmpreg = get_num (&opP->disp, 80);
3721 if (tmpreg == -1)
3722 tmpreg = 0;
3723 install_operand (s[1], tmpreg);
3724 break;
3725 case 'j':
3726 tmpreg = get_num (&opP->disp, 10);
3727 install_operand (s[1], tmpreg - 1);
3728 break;
3729 case 'K':
3730 tmpreg = get_num (&opP->disp, 65);
3731 install_operand (s[1], tmpreg);
3732 break;
3733 default:
3734 abort ();
3735 }
3736 }
3737
3738 /* By the time when get here (FINALLY) the_ins contains the complete
3739 instruction, ready to be emitted. . . */
3740 }
3741
3742 static int
3743 reverse_16_bits (int in)
3744 {
3745 int out = 0;
3746 int n;
3747
3748 static int mask[16] =
3749 {
3750 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3751 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3752 };
3753 for (n = 0; n < 16; n++)
3754 {
3755 if (in & mask[n])
3756 out |= mask[15 - n];
3757 }
3758 return out;
3759 } /* reverse_16_bits() */
3760
3761 static int
3762 reverse_8_bits (int in)
3763 {
3764 int out = 0;
3765 int n;
3766
3767 static int mask[8] =
3768 {
3769 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3770 };
3771
3772 for (n = 0; n < 8; n++)
3773 {
3774 if (in & mask[n])
3775 out |= mask[7 - n];
3776 }
3777 return out;
3778 } /* reverse_8_bits() */
3779
3780 /* Cause an extra frag to be generated here, inserting up to
3781 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3782 generated; its primary type is rs_machine_dependent.
3783
3784 The TYPE parameter is also used by md_convert_frag_1 and
3785 md_estimate_size_before_relax. The appropriate type of fixup will
3786 be emitted by md_convert_frag_1.
3787
3788 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3789 static void
3790 install_operand (int mode, int val)
3791 {
3792 switch (mode)
3793 {
3794 case 's':
3795 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3796 break;
3797 case 'd':
3798 the_ins.opcode[0] |= val << 9;
3799 break;
3800 case 'E':
3801 the_ins.opcode[1] |= val << 9;
3802 break;
3803 case '1':
3804 the_ins.opcode[1] |= val << 12;
3805 break;
3806 case '2':
3807 the_ins.opcode[1] |= val << 6;
3808 break;
3809 case '3':
3810 the_ins.opcode[1] |= val;
3811 break;
3812 case '4':
3813 the_ins.opcode[2] |= val << 12;
3814 break;
3815 case '5':
3816 the_ins.opcode[2] |= val << 6;
3817 break;
3818 case '6':
3819 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3820 three words long! */
3821 the_ins.numo++;
3822 the_ins.opcode[2] |= val;
3823 break;
3824 case '7':
3825 the_ins.opcode[1] |= val << 7;
3826 break;
3827 case '8':
3828 the_ins.opcode[1] |= val << 10;
3829 break;
3830 #ifndef NO_68851
3831 case '9':
3832 the_ins.opcode[1] |= val << 5;
3833 break;
3834 #endif
3835
3836 case 't':
3837 the_ins.opcode[1] |= (val << 10) | (val << 7);
3838 break;
3839 case 'D':
3840 the_ins.opcode[1] |= (val << 12) | val;
3841 break;
3842 case 'g':
3843 the_ins.opcode[0] |= val = 0xff;
3844 break;
3845 case 'i':
3846 the_ins.opcode[0] |= val << 9;
3847 break;
3848 case 'C':
3849 the_ins.opcode[1] |= val;
3850 break;
3851 case 'j':
3852 the_ins.opcode[1] |= val;
3853 the_ins.numo++; /* What a hack. */
3854 break;
3855 case 'k':
3856 the_ins.opcode[1] |= val << 4;
3857 break;
3858 case 'b':
3859 case 'w':
3860 case 'W':
3861 case 'l':
3862 break;
3863 case 'e':
3864 the_ins.opcode[0] |= (val << 6);
3865 break;
3866 case 'L':
3867 the_ins.opcode[1] = (val >> 16);
3868 the_ins.opcode[2] = val & 0xffff;
3869 break;
3870 case 'm':
3871 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3872 the_ins.opcode[0] |= ((val & 0x7) << 9);
3873 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3874 break;
3875 case 'n': /* MAC/EMAC Rx on !load. */
3876 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3877 the_ins.opcode[0] |= ((val & 0x7) << 9);
3878 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3879 break;
3880 case 'o': /* MAC/EMAC Rx on load. */
3881 the_ins.opcode[1] |= val << 12;
3882 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3883 break;
3884 case 'M': /* MAC/EMAC Ry on !load. */
3885 the_ins.opcode[0] |= (val & 0xF);
3886 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3887 break;
3888 case 'N': /* MAC/EMAC Ry on load. */
3889 the_ins.opcode[1] |= (val & 0xF);
3890 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3891 break;
3892 case 'h':
3893 the_ins.opcode[1] |= ((val != 1) << 10);
3894 break;
3895 case 'F':
3896 the_ins.opcode[0] |= ((val & 0x3) << 9);
3897 break;
3898 case 'f':
3899 the_ins.opcode[0] |= ((val & 0x3) << 0);
3900 break;
3901 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3902 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3903 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3904 break;
3905 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3906 the_ins.opcode[0] |= ((val & 0x1) << 7);
3907 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3908 break;
3909 case 'I':
3910 the_ins.opcode[1] |= ((val & 0x3) << 9);
3911 break;
3912 case ']':
3913 the_ins.opcode[0] |= (val & 0x1) <<10;
3914 break;
3915 case 'c':
3916 default:
3917 as_fatal (_("failed sanity check."));
3918 }
3919 }
3920
3921 static void
3922 install_gen_operand (int mode, int val)
3923 {
3924 switch (mode)
3925 {
3926 case '/': /* Special for mask loads for mac/msac insns with
3927 possible mask; trailing_ampersand set in bit 8. */
3928 the_ins.opcode[0] |= (val & 0x3f);
3929 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3930 break;
3931 case 's':
3932 the_ins.opcode[0] |= val;
3933 break;
3934 case 'd':
3935 /* This is a kludge!!! */
3936 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3937 break;
3938 case 'b':
3939 case 'w':
3940 case 'l':
3941 case 'f':
3942 case 'F':
3943 case 'x':
3944 case 'p':
3945 the_ins.opcode[0] |= val;
3946 break;
3947 /* more stuff goes here. */
3948 default:
3949 as_fatal (_("failed sanity check."));
3950 }
3951 }
3952
3953 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3954 then deal with the bitfield hack. */
3955
3956 static char *
3957 crack_operand (char *str, struct m68k_op *opP)
3958 {
3959 int parens;
3960 int c;
3961 char *beg_str;
3962 int inquote = 0;
3963
3964 if (!str)
3965 {
3966 return str;
3967 }
3968 beg_str = str;
3969 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3970 {
3971 if (! inquote)
3972 {
3973 if (*str == '(')
3974 parens++;
3975 else if (*str == ')')
3976 {
3977 if (!parens)
3978 { /* ERROR. */
3979 opP->error = _("Extra )");
3980 return str;
3981 }
3982 --parens;
3983 }
3984 }
3985 if (flag_mri && *str == '\'')
3986 inquote = ! inquote;
3987 }
3988 if (!*str && parens)
3989 { /* ERROR. */
3990 opP->error = _("Missing )");
3991 return str;
3992 }
3993 c = *str;
3994 *str = '\0';
3995 if (m68k_ip_op (beg_str, opP) != 0)
3996 {
3997 *str = c;
3998 return str;
3999 }
4000 *str = c;
4001 if (c == '}')
4002 c = *++str; /* JF bitfield hack. */
4003 if (c)
4004 {
4005 c = *++str;
4006 if (!c)
4007 as_bad (_("Missing operand"));
4008 }
4009
4010 /* Detect MRI REG symbols and convert them to REGLSTs. */
4011 if (opP->mode == CONTROL && (int)opP->reg < 0)
4012 {
4013 opP->mode = REGLST;
4014 opP->mask = ~(int)opP->reg;
4015 opP->reg = 0;
4016 }
4017
4018 return str;
4019 }
4020
4021 /* This is the guts of the machine-dependent assembler. STR points to a
4022 machine dependent instruction. This function is supposed to emit
4023 the frags/bytes it assembles to.
4024 */
4025
4026 static void
4027 insert_reg (const char *regname, int regnum)
4028 {
4029 char buf[100];
4030 int i;
4031
4032 #ifdef REGISTER_PREFIX
4033 if (!flag_reg_prefix_optional)
4034 {
4035 buf[0] = REGISTER_PREFIX;
4036 strcpy (buf + 1, regname);
4037 regname = buf;
4038 }
4039 #endif
4040
4041 symbol_table_insert (symbol_new (regname, reg_section, regnum,
4042 &zero_address_frag));
4043
4044 for (i = 0; regname[i]; i++)
4045 buf[i] = TOUPPER (regname[i]);
4046 buf[i] = '\0';
4047
4048 symbol_table_insert (symbol_new (buf, reg_section, regnum,
4049 &zero_address_frag));
4050 }
4051
4052 struct init_entry
4053 {
4054 const char *name;
4055 int number;
4056 };
4057
4058 static const struct init_entry init_table[] =
4059 {
4060 { "d0", DATA0 },
4061 { "d1", DATA1 },
4062 { "d2", DATA2 },
4063 { "d3", DATA3 },
4064 { "d4", DATA4 },
4065 { "d5", DATA5 },
4066 { "d6", DATA6 },
4067 { "d7", DATA7 },
4068 { "a0", ADDR0 },
4069 { "a1", ADDR1 },
4070 { "a2", ADDR2 },
4071 { "a3", ADDR3 },
4072 { "a4", ADDR4 },
4073 { "a5", ADDR5 },
4074 { "a6", ADDR6 },
4075 { "fp", ADDR6 },
4076 { "a7", ADDR7 },
4077 { "sp", ADDR7 },
4078 { "ssp", ADDR7 },
4079 { "fp0", FP0 },
4080 { "fp1", FP1 },
4081 { "fp2", FP2 },
4082 { "fp3", FP3 },
4083 { "fp4", FP4 },
4084 { "fp5", FP5 },
4085 { "fp6", FP6 },
4086 { "fp7", FP7 },
4087 { "fpi", FPI },
4088 { "fpiar", FPI },
4089 { "fpc", FPI },
4090 { "fps", FPS },
4091 { "fpsr", FPS },
4092 { "fpc", FPC },
4093 { "fpcr", FPC },
4094 { "control", FPC },
4095 { "status", FPS },
4096 { "iaddr", FPI },
4097
4098 { "cop0", COP0 },
4099 { "cop1", COP1 },
4100 { "cop2", COP2 },
4101 { "cop3", COP3 },
4102 { "cop4", COP4 },
4103 { "cop5", COP5 },
4104 { "cop6", COP6 },
4105 { "cop7", COP7 },
4106 { "pc", PC },
4107 { "zpc", ZPC },
4108 { "sr", SR },
4109
4110 { "ccr", CCR },
4111 { "cc", CCR },
4112
4113 { "acc", ACC },
4114 { "acc0", ACC },
4115 { "acc1", ACC1 },
4116 { "acc2", ACC2 },
4117 { "acc3", ACC3 },
4118 { "accext01", ACCEXT01 },
4119 { "accext23", ACCEXT23 },
4120 { "macsr", MACSR },
4121 { "mask", MASK },
4122
4123 /* Control registers. */
4124 { "sfc", SFC }, /* Source Function Code. */
4125 { "sfcr", SFC },
4126 { "dfc", DFC }, /* Destination Function Code. */
4127 { "dfcr", DFC },
4128 { "cacr", CACR }, /* Cache Control Register. */
4129 { "caar", CAAR }, /* Cache Address Register. */
4130 { "cpucr", CPUCR }, /* CPU Control Register. */
4131
4132 { "usp", USP }, /* User Stack Pointer. */
4133 { "vbr", VBR }, /* Vector Base Register. */
4134 { "msp", MSP }, /* Master Stack Pointer. */
4135 { "isp", ISP }, /* Interrupt Stack Pointer. */
4136
4137 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
4138 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
4139 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
4140 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
4141
4142 /* 68ec040 versions of same */
4143 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
4144 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
4145 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
4146 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
4147
4148 /* Coldfire versions of same. The ColdFire programmer's reference
4149 manual indicated that the order is 2,3,0,1, but Ken Rose
4150 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
4151 { "acr0", ACR0 }, /* Access Control Unit 0. */
4152 { "acr1", ACR1 }, /* Access Control Unit 1. */
4153 { "acr2", ACR2 }, /* Access Control Unit 2. */
4154 { "acr3", ACR3 }, /* Access Control Unit 3. */
4155 { "acr4", ACR4 }, /* Access Control Unit 4. */
4156 { "acr5", ACR5 }, /* Access Control Unit 5. */
4157 { "acr6", ACR6 }, /* Access Control Unit 6. */
4158 { "acr7", ACR7 }, /* Access Control Unit 7. */
4159
4160 { "tc", TC }, /* MMU Translation Control Register. */
4161 { "tcr", TC },
4162 { "asid", ASID },
4163
4164 { "mmusr", MMUSR }, /* MMU Status Register. */
4165 { "srp", SRP }, /* User Root Pointer. */
4166 { "urp", URP }, /* Supervisor Root Pointer. */
4167
4168 { "buscr", BUSCR },
4169 { "mmubar", MMUBAR },
4170 { "pcr", PCR },
4171
4172 { "rombar", ROMBAR }, /* ROM Base Address Register. */
4173 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
4174 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
4175 { "mbar", MBAR }, /* Module Base Address Register. */
4176
4177 { "mbar0", MBAR0 }, /* mcfv4e registers. */
4178 { "mbar1", MBAR1 }, /* mcfv4e registers. */
4179 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
4180 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
4181 { "mpcr", MPCR }, /* mcfv4e registers. */
4182 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
4183 { "secmbar", SECMBAR }, /* mcfv4e registers. */
4184 { "asid", TC }, /* mcfv4e registers. */
4185 { "mmubar", BUSCR }, /* mcfv4e registers. */
4186 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
4187 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
4188 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
4189 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
4190 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
4191 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
4192 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
4193 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
4194 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
4195 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4196 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4197 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4198
4199 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4200 { "rambar", RAMBAR }, /* mcf528x registers. */
4201
4202 { "mbar2", MBAR2 }, /* mcf5249 registers. */
4203
4204 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */
4205
4206 { "cac", CAC }, /* fido registers. */
4207 { "mbb", MBO }, /* fido registers (obsolete). */
4208 { "mbo", MBO }, /* fido registers. */
4209 /* End of control registers. */
4210
4211 { "ac", AC },
4212 { "bc", BC },
4213 { "cal", CAL },
4214 { "crp", CRP },
4215 { "drp", DRP },
4216 { "pcsr", PCSR },
4217 { "psr", PSR },
4218 { "scc", SCC },
4219 { "val", VAL },
4220 { "bad0", BAD0 },
4221 { "bad1", BAD1 },
4222 { "bad2", BAD2 },
4223 { "bad3", BAD3 },
4224 { "bad4", BAD4 },
4225 { "bad5", BAD5 },
4226 { "bad6", BAD6 },
4227 { "bad7", BAD7 },
4228 { "bac0", BAC0 },
4229 { "bac1", BAC1 },
4230 { "bac2", BAC2 },
4231 { "bac3", BAC3 },
4232 { "bac4", BAC4 },
4233 { "bac5", BAC5 },
4234 { "bac6", BAC6 },
4235 { "bac7", BAC7 },
4236
4237 { "ic", IC },
4238 { "dc", DC },
4239 { "nc", NC },
4240
4241 { "tt0", TT0 },
4242 { "tt1", TT1 },
4243 /* 68ec030 versions of same. */
4244 { "ac0", TT0 },
4245 { "ac1", TT1 },
4246 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4247 { "acusr", PSR },
4248
4249 /* Suppressed data and address registers. */
4250 { "zd0", ZDATA0 },
4251 { "zd1", ZDATA1 },
4252 { "zd2", ZDATA2 },
4253 { "zd3", ZDATA3 },
4254 { "zd4", ZDATA4 },
4255 { "zd5", ZDATA5 },
4256 { "zd6", ZDATA6 },
4257 { "zd7", ZDATA7 },
4258 { "za0", ZADDR0 },
4259 { "za1", ZADDR1 },
4260 { "za2", ZADDR2 },
4261 { "za3", ZADDR3 },
4262 { "za4", ZADDR4 },
4263 { "za5", ZADDR5 },
4264 { "za6", ZADDR6 },
4265 { "za7", ZADDR7 },
4266
4267 /* Upper and lower data and address registers, used by macw and msacw. */
4268 { "d0l", DATA0L },
4269 { "d1l", DATA1L },
4270 { "d2l", DATA2L },
4271 { "d3l", DATA3L },
4272 { "d4l", DATA4L },
4273 { "d5l", DATA5L },
4274 { "d6l", DATA6L },
4275 { "d7l", DATA7L },
4276
4277 { "a0l", ADDR0L },
4278 { "a1l", ADDR1L },
4279 { "a2l", ADDR2L },
4280 { "a3l", ADDR3L },
4281 { "a4l", ADDR4L },
4282 { "a5l", ADDR5L },
4283 { "a6l", ADDR6L },
4284 { "a7l", ADDR7L },
4285
4286 { "d0u", DATA0U },
4287 { "d1u", DATA1U },
4288 { "d2u", DATA2U },
4289 { "d3u", DATA3U },
4290 { "d4u", DATA4U },
4291 { "d5u", DATA5U },
4292 { "d6u", DATA6U },
4293 { "d7u", DATA7U },
4294
4295 { "a0u", ADDR0U },
4296 { "a1u", ADDR1U },
4297 { "a2u", ADDR2U },
4298 { "a3u", ADDR3U },
4299 { "a4u", ADDR4U },
4300 { "a5u", ADDR5U },
4301 { "a6u", ADDR6U },
4302 { "a7u", ADDR7U },
4303
4304 { 0, 0 }
4305 };
4306
4307 static void
4308 init_regtable (void)
4309 {
4310 int i;
4311 for (i = 0; init_table[i].name; i++)
4312 insert_reg (init_table[i].name, init_table[i].number);
4313 }
4314
4315 void
4316 md_assemble (char *str)
4317 {
4318 const char *er;
4319 short *fromP;
4320 char *toP = NULL;
4321 int m, n = 0;
4322 char *to_beg_P;
4323 int shorts_this_frag;
4324 fixS *fixP;
4325
4326 if (!selected_cpu && !selected_arch)
4327 {
4328 /* We've not selected an architecture yet. Set the default
4329 now. We do this lazily so that an initial .cpu or .arch directive
4330 can specify. */
4331 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4332 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4333 }
4334 if (!initialized)
4335 m68k_init_arch ();
4336
4337 /* In MRI mode, the instruction and operands are separated by a
4338 space. Anything following the operands is a comment. The label
4339 has already been removed. */
4340 if (flag_mri)
4341 {
4342 char *s;
4343 int fields = 0;
4344 int infield = 0;
4345 int inquote = 0;
4346
4347 for (s = str; *s != '\0'; s++)
4348 {
4349 if ((*s == ' ' || *s == '\t') && ! inquote)
4350 {
4351 if (infield)
4352 {
4353 ++fields;
4354 if (fields >= 2)
4355 {
4356 *s = '\0';
4357 break;
4358 }
4359 infield = 0;
4360 }
4361 }
4362 else
4363 {
4364 if (! infield)
4365 infield = 1;
4366 if (*s == '\'')
4367 inquote = ! inquote;
4368 }
4369 }
4370 }
4371
4372 memset (&the_ins, '\0', sizeof (the_ins));
4373 m68k_ip (str);
4374 er = the_ins.error;
4375 if (!er)
4376 {
4377 for (n = 0; n < the_ins.numargs; n++)
4378 if (the_ins.operands[n].error)
4379 {
4380 er = the_ins.operands[n].error;
4381 break;
4382 }
4383 }
4384 if (er)
4385 {
4386 as_bad (_("%s -- statement `%s' ignored"), er, str);
4387 return;
4388 }
4389
4390 /* If there is a current label, record that it marks an instruction. */
4391 if (current_label != NULL)
4392 {
4393 current_label->text = 1;
4394 current_label = NULL;
4395 }
4396
4397 #ifdef OBJ_ELF
4398 /* Tie dwarf2 debug info to the address at the start of the insn. */
4399 dwarf2_emit_insn (0);
4400 #endif
4401
4402 if (the_ins.nfrag == 0)
4403 {
4404 /* No frag hacking involved; just put it out. */
4405 toP = frag_more (2 * the_ins.numo);
4406 fromP = &the_ins.opcode[0];
4407 for (m = the_ins.numo; m; --m)
4408 {
4409 md_number_to_chars (toP, (long) (*fromP), 2);
4410 toP += 2;
4411 fromP++;
4412 }
4413 /* Put out symbol-dependent info. */
4414 for (m = 0; m < the_ins.nrel; m++)
4415 {
4416 switch (the_ins.reloc[m].wid)
4417 {
4418 case 'B':
4419 n = 1;
4420 break;
4421 case 'b':
4422 n = 1;
4423 break;
4424 case '3':
4425 n = 1;
4426 break;
4427 case 'w':
4428 case 'W':
4429 n = 2;
4430 break;
4431 case 'l':
4432 n = 4;
4433 break;
4434 default:
4435 as_fatal (_("Don't know how to figure out width of %c in md_assemble()"),
4436 the_ins.reloc[m].wid);
4437 }
4438
4439 fixP = fix_new_exp (frag_now,
4440 ((toP - frag_now->fr_literal)
4441 - the_ins.numo * 2 + the_ins.reloc[m].n),
4442 n,
4443 &the_ins.reloc[m].exp,
4444 the_ins.reloc[m].pcrel,
4445 get_reloc_code (n, the_ins.reloc[m].pcrel,
4446 the_ins.reloc[m].pic_reloc));
4447 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4448 if (the_ins.reloc[m].wid == 'B')
4449 fixP->fx_signed = 1;
4450 }
4451 return;
4452 }
4453
4454 /* There's some frag hacking. */
4455 {
4456 /* Calculate the max frag size. */
4457 int wid;
4458
4459 wid = 2 * the_ins.fragb[0].fragoff;
4460 for (n = 1; n < the_ins.nfrag; n++)
4461 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4462 /* frag_var part. */
4463 wid += FRAG_VAR_SIZE;
4464 /* Make sure the whole insn fits in one chunk, in particular that
4465 the var part is attached, as we access one byte before the
4466 variable frag for byte branches. */
4467 frag_grow (wid);
4468 }
4469
4470 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4471 {
4472 int wid;
4473
4474 if (n == 0)
4475 wid = 2 * the_ins.fragb[n].fragoff;
4476 else
4477 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4478 toP = frag_more (wid);
4479 to_beg_P = toP;
4480 shorts_this_frag = 0;
4481 for (m = wid / 2; m; --m)
4482 {
4483 md_number_to_chars (toP, (long) (*fromP), 2);
4484 toP += 2;
4485 fromP++;
4486 shorts_this_frag++;
4487 }
4488 for (m = 0; m < the_ins.nrel; m++)
4489 {
4490 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4491 {
4492 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4493 break;
4494 }
4495 wid = the_ins.reloc[m].wid;
4496 if (wid == 0)
4497 continue;
4498 the_ins.reloc[m].wid = 0;
4499 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4500
4501 fixP = fix_new_exp (frag_now,
4502 ((toP - frag_now->fr_literal)
4503 - the_ins.numo * 2 + the_ins.reloc[m].n),
4504 wid,
4505 &the_ins.reloc[m].exp,
4506 the_ins.reloc[m].pcrel,
4507 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4508 the_ins.reloc[m].pic_reloc));
4509 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4510 }
4511 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
4512 (relax_substateT) (the_ins.fragb[n].fragty),
4513 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4514 }
4515 gas_assert (the_ins.nfrag >= 1);
4516 n = the_ins.numo - the_ins.fragb[the_ins.nfrag - 1].fragoff;
4517 shorts_this_frag = 0;
4518 if (n)
4519 {
4520 toP = frag_more (n * 2);
4521 while (n--)
4522 {
4523 md_number_to_chars (toP, (long) (*fromP), 2);
4524 toP += 2;
4525 fromP++;
4526 shorts_this_frag++;
4527 }
4528 }
4529 for (m = 0; m < the_ins.nrel; m++)
4530 {
4531 int wid;
4532
4533 wid = the_ins.reloc[m].wid;
4534 if (wid == 0)
4535 continue;
4536 the_ins.reloc[m].wid = 0;
4537 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4538
4539 fixP = fix_new_exp (frag_now,
4540 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4541 - shorts_this_frag * 2),
4542 wid,
4543 &the_ins.reloc[m].exp,
4544 the_ins.reloc[m].pcrel,
4545 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4546 the_ins.reloc[m].pic_reloc));
4547 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4548 }
4549 }
4550
4551 /* Comparison function used by qsort to rank the opcode entries by name. */
4552
4553 static int
4554 m68k_compare_opcode (const void * v1, const void * v2)
4555 {
4556 struct m68k_opcode * op1, * op2;
4557 int ret;
4558
4559 if (v1 == v2)
4560 return 0;
4561
4562 op1 = *(struct m68k_opcode **) v1;
4563 op2 = *(struct m68k_opcode **) v2;
4564
4565 /* Compare the two names. If different, return the comparison.
4566 If the same, return the order they are in the opcode table. */
4567 ret = strcmp (op1->name, op2->name);
4568 if (ret)
4569 return ret;
4570 if (op1 < op2)
4571 return -1;
4572 return 1;
4573 }
4574
4575 void
4576 md_begin (void)
4577 {
4578 const struct m68k_opcode *ins;
4579 struct m68k_incant *hack, *slak;
4580 const char *retval = 0; /* Empty string, or error msg text. */
4581 int i;
4582
4583 /* Set up hash tables with 68000 instructions.
4584 similar to what the vax assembler does. */
4585 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4586 a copy of it at runtime, adding in the information we want but isn't
4587 there. I think it'd be better to have an awk script hack the table
4588 at compile time. Or even just xstr the table and use it as-is. But
4589 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4590 names. */
4591
4592 if (flag_mri)
4593 {
4594 flag_reg_prefix_optional = 1;
4595 m68k_abspcadd = 1;
4596 if (! m68k_rel32_from_cmdline)
4597 m68k_rel32 = 0;
4598 }
4599
4600 /* First sort the opcode table into alphabetical order to separate
4601 the order that the assembler wants to see the opcodes from the
4602 order that the disassembler wants to see them. */
4603 m68k_sorted_opcodes = XNEWVEC (const struct m68k_opcode *, m68k_numopcodes);
4604
4605 for (i = m68k_numopcodes; i--;)
4606 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4607
4608 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4609 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4610
4611 op_hash = hash_new ();
4612
4613 obstack_begin (&robyn, 4000);
4614 for (i = 0; i < m68k_numopcodes; i++)
4615 {
4616 hack = slak = XOBNEW (&robyn, struct m68k_incant);
4617 do
4618 {
4619 ins = m68k_sorted_opcodes[i];
4620
4621 /* We must enter all insns into the table, because .arch and
4622 .cpu directives can change things. */
4623 slak->m_operands = ins->args;
4624 slak->m_arch = ins->arch;
4625 slak->m_opcode = ins->opcode;
4626
4627 /* In most cases we can determine the number of opcode words
4628 by checking the second word of the mask. Unfortunately
4629 some instructions have 2 opcode words, but no fixed bits
4630 in the second word. A leading dot in the operands
4631 string also indicates 2 opcodes. */
4632 if (*slak->m_operands == '.')
4633 {
4634 slak->m_operands++;
4635 slak->m_codenum = 2;
4636 }
4637 else if (ins->match & 0xffffL)
4638 slak->m_codenum = 2;
4639 else
4640 slak->m_codenum = 1;
4641 slak->m_opnum = strlen (slak->m_operands) / 2;
4642
4643 if (i + 1 != m68k_numopcodes
4644 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4645 {
4646 slak->m_next = XOBNEW (&robyn, struct m68k_incant);
4647 i++;
4648 }
4649 else
4650 slak->m_next = 0;
4651 slak = slak->m_next;
4652 }
4653 while (slak);
4654
4655 retval = hash_insert (op_hash, ins->name, (char *) hack);
4656 if (retval)
4657 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4658 }
4659
4660 for (i = 0; i < m68k_numaliases; i++)
4661 {
4662 const char *name = m68k_opcode_aliases[i].primary;
4663 const char *alias = m68k_opcode_aliases[i].alias;
4664 void *val = hash_find (op_hash, name);
4665
4666 if (!val)
4667 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4668 retval = hash_insert (op_hash, alias, val);
4669 if (retval)
4670 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4671 }
4672
4673 /* In MRI mode, all unsized branches are variable sized. Normally,
4674 they are word sized. */
4675 if (flag_mri)
4676 {
4677 static struct m68k_opcode_alias mri_aliases[] =
4678 {
4679 { "bhi", "jhi", },
4680 { "bls", "jls", },
4681 { "bcc", "jcc", },
4682 { "bcs", "jcs", },
4683 { "bne", "jne", },
4684 { "beq", "jeq", },
4685 { "bvc", "jvc", },
4686 { "bvs", "jvs", },
4687 { "bpl", "jpl", },
4688 { "bmi", "jmi", },
4689 { "bge", "jge", },
4690 { "blt", "jlt", },
4691 { "bgt", "jgt", },
4692 { "ble", "jle", },
4693 { "bra", "jra", },
4694 { "bsr", "jbsr", },
4695 };
4696
4697 for (i = 0;
4698 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4699 i++)
4700 {
4701 const char *name = mri_aliases[i].primary;
4702 const char *alias = mri_aliases[i].alias;
4703 void *val = hash_find (op_hash, name);
4704
4705 if (!val)
4706 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4707 retval = hash_jam (op_hash, alias, val);
4708 if (retval)
4709 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4710 }
4711 }
4712
4713 for (i = 0; i < (int) sizeof (notend_table); i++)
4714 {
4715 notend_table[i] = 0;
4716 alt_notend_table[i] = 0;
4717 }
4718
4719 notend_table[','] = 1;
4720 notend_table['{'] = 1;
4721 notend_table['}'] = 1;
4722 alt_notend_table['a'] = 1;
4723 alt_notend_table['A'] = 1;
4724 alt_notend_table['d'] = 1;
4725 alt_notend_table['D'] = 1;
4726 alt_notend_table['#'] = 1;
4727 alt_notend_table['&'] = 1;
4728 alt_notend_table['f'] = 1;
4729 alt_notend_table['F'] = 1;
4730 #ifdef REGISTER_PREFIX
4731 alt_notend_table[REGISTER_PREFIX] = 1;
4732 #endif
4733
4734 /* We need to put '(' in alt_notend_table to handle
4735 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4736 alt_notend_table['('] = 1;
4737
4738 /* We need to put '@' in alt_notend_table to handle
4739 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4740 alt_notend_table['@'] = 1;
4741
4742 /* We need to put digits in alt_notend_table to handle
4743 bfextu %d0{24:1},%d0 */
4744 alt_notend_table['0'] = 1;
4745 alt_notend_table['1'] = 1;
4746 alt_notend_table['2'] = 1;
4747 alt_notend_table['3'] = 1;
4748 alt_notend_table['4'] = 1;
4749 alt_notend_table['5'] = 1;
4750 alt_notend_table['6'] = 1;
4751 alt_notend_table['7'] = 1;
4752 alt_notend_table['8'] = 1;
4753 alt_notend_table['9'] = 1;
4754
4755 #ifndef MIT_SYNTAX_ONLY
4756 /* Insert pseudo ops, these have to go into the opcode table since
4757 gas expects pseudo ops to start with a dot. */
4758 {
4759 int n = 0;
4760
4761 while (mote_pseudo_table[n].poc_name)
4762 {
4763 hack = XOBNEW (&robyn, struct m68k_incant);
4764 hash_insert (op_hash,
4765 mote_pseudo_table[n].poc_name, (char *) hack);
4766 hack->m_operands = 0;
4767 hack->m_opnum = n;
4768 n++;
4769 }
4770 }
4771 #endif
4772
4773 init_regtable ();
4774
4775 #ifdef OBJ_ELF
4776 record_alignment (text_section, 2);
4777 record_alignment (data_section, 2);
4778 record_alignment (bss_section, 2);
4779 #endif
4780 }
4781
4782 \f
4783 /* This is called when a label is defined. */
4784
4785 void
4786 m68k_frob_label (symbolS *sym)
4787 {
4788 struct label_line *n;
4789
4790 n = XNEW (struct label_line);
4791 n->next = labels;
4792 n->label = sym;
4793 n->file = as_where (&n->line);
4794 n->text = 0;
4795 labels = n;
4796 current_label = n;
4797
4798 #ifdef OBJ_ELF
4799 dwarf2_emit_label (sym);
4800 #endif
4801 }
4802
4803 /* This is called when a value that is not an instruction is emitted. */
4804
4805 void
4806 m68k_flush_pending_output (void)
4807 {
4808 current_label = NULL;
4809 }
4810
4811 /* This is called at the end of the assembly, when the final value of
4812 the label is known. We warn if this is a text symbol aligned at an
4813 odd location. */
4814
4815 void
4816 m68k_frob_symbol (symbolS *sym)
4817 {
4818 if (S_GET_SEGMENT (sym) == reg_section
4819 && (int) S_GET_VALUE (sym) < 0)
4820 {
4821 S_SET_SEGMENT (sym, absolute_section);
4822 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4823 }
4824 else if ((S_GET_VALUE (sym) & 1) != 0)
4825 {
4826 struct label_line *l;
4827
4828 for (l = labels; l != NULL; l = l->next)
4829 {
4830 if (l->label == sym)
4831 {
4832 if (l->text)
4833 as_warn_where (l->file, l->line,
4834 _("text label `%s' aligned to odd boundary"),
4835 S_GET_NAME (sym));
4836 break;
4837 }
4838 }
4839 }
4840 }
4841 \f
4842 /* This is called if we go in or out of MRI mode because of the .mri
4843 pseudo-op. */
4844
4845 void
4846 m68k_mri_mode_change (int on)
4847 {
4848 if (on)
4849 {
4850 if (! flag_reg_prefix_optional)
4851 {
4852 flag_reg_prefix_optional = 1;
4853 #ifdef REGISTER_PREFIX
4854 init_regtable ();
4855 #endif
4856 }
4857 m68k_abspcadd = 1;
4858 if (! m68k_rel32_from_cmdline)
4859 m68k_rel32 = 0;
4860 }
4861 else
4862 {
4863 if (! reg_prefix_optional_seen)
4864 {
4865 #ifdef REGISTER_PREFIX_OPTIONAL
4866 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4867 #else
4868 flag_reg_prefix_optional = 0;
4869 #endif
4870 #ifdef REGISTER_PREFIX
4871 init_regtable ();
4872 #endif
4873 }
4874 m68k_abspcadd = 0;
4875 if (! m68k_rel32_from_cmdline)
4876 m68k_rel32 = 1;
4877 }
4878 }
4879
4880 const char *
4881 md_atof (int type, char *litP, int *sizeP)
4882 {
4883 return ieee_md_atof (type, litP, sizeP, TRUE);
4884 }
4885
4886 void
4887 md_number_to_chars (char *buf, valueT val, int n)
4888 {
4889 number_to_chars_bigendian (buf, val, n);
4890 }
4891
4892 void
4893 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4894 {
4895 offsetT val = *valP;
4896 addressT upper_limit;
4897 offsetT lower_limit;
4898
4899 /* This is unnecessary but it convinces the native rs6000 compiler
4900 to generate the code we want. */
4901 char *buf = fixP->fx_frag->fr_literal;
4902 buf += fixP->fx_where;
4903 /* End ibm compiler workaround. */
4904
4905 val = SEXT (val);
4906
4907 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4908 fixP->fx_done = 1;
4909
4910 #ifdef OBJ_ELF
4911 if (fixP->fx_addsy)
4912 {
4913 memset (buf, 0, fixP->fx_size);
4914 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4915
4916 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4917 && !S_IS_DEFINED (fixP->fx_addsy)
4918 && !S_IS_WEAK (fixP->fx_addsy))
4919 S_SET_WEAK (fixP->fx_addsy);
4920
4921 switch (fixP->fx_r_type)
4922 {
4923 case BFD_RELOC_68K_TLS_GD32:
4924 case BFD_RELOC_68K_TLS_GD16:
4925 case BFD_RELOC_68K_TLS_GD8:
4926 case BFD_RELOC_68K_TLS_LDM32:
4927 case BFD_RELOC_68K_TLS_LDM16:
4928 case BFD_RELOC_68K_TLS_LDM8:
4929 case BFD_RELOC_68K_TLS_LDO32:
4930 case BFD_RELOC_68K_TLS_LDO16:
4931 case BFD_RELOC_68K_TLS_LDO8:
4932 case BFD_RELOC_68K_TLS_IE32:
4933 case BFD_RELOC_68K_TLS_IE16:
4934 case BFD_RELOC_68K_TLS_IE8:
4935 case BFD_RELOC_68K_TLS_LE32:
4936 case BFD_RELOC_68K_TLS_LE16:
4937 case BFD_RELOC_68K_TLS_LE8:
4938 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4939 break;
4940
4941 default:
4942 break;
4943 }
4944
4945 return;
4946 }
4947 #elif defined(OBJ_AOUT)
4948 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4949 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4950 {
4951 memset (buf, 0, fixP->fx_size);
4952 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4953 return;
4954 }
4955 #endif
4956
4957 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4958 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4959 return;
4960
4961 switch (fixP->fx_size)
4962 {
4963 /* The cast to offsetT below are necessary to make code
4964 correct for machines where ints are smaller than offsetT. */
4965 case 1:
4966 *buf++ = val;
4967 upper_limit = 0x7f;
4968 lower_limit = - (offsetT) 0x80;
4969 break;
4970 case 2:
4971 *buf++ = (val >> 8);
4972 *buf++ = val;
4973 upper_limit = 0x7fff;
4974 lower_limit = - (offsetT) 0x8000;
4975 break;
4976 case 4:
4977 *buf++ = (val >> 24);
4978 *buf++ = (val >> 16);
4979 *buf++ = (val >> 8);
4980 *buf++ = val;
4981 upper_limit = 0x7fffffff;
4982 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4983 break;
4984 default:
4985 BAD_CASE (fixP->fx_size);
4986 }
4987
4988 /* Fix up a negative reloc. */
4989 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4990 {
4991 fixP->fx_addsy = fixP->fx_subsy;
4992 fixP->fx_subsy = NULL;
4993 fixP->fx_tcbit = 1;
4994 }
4995
4996 /* For non-pc-relative values, it's conceivable we might get something
4997 like "0xff" for a byte field. So extend the upper part of the range
4998 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4999 so that we can do any range checking at all. */
5000 if (! fixP->fx_pcrel && ! fixP->fx_signed)
5001 upper_limit = upper_limit * 2 + 1;
5002
5003 if ((addressT) val > upper_limit
5004 && (val > 0 || val < lower_limit))
5005 as_bad_where (fixP->fx_file, fixP->fx_line,
5006 _("value %ld out of range"), (long)val);
5007
5008 /* A one byte PC-relative reloc means a short branch. We can't use
5009 a short branch with a value of 0 or -1, because those indicate
5010 different opcodes (branches with longer offsets). fixup_segment
5011 in write.c may have clobbered fx_pcrel, so we need to examine the
5012 reloc type. */
5013 if ((fixP->fx_pcrel
5014 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5015 && fixP->fx_size == 1
5016 && (fixP->fx_addsy == NULL
5017 || S_IS_DEFINED (fixP->fx_addsy))
5018 && (val == 0 || val == -1))
5019 as_bad_where (fixP->fx_file, fixP->fx_line,
5020 _("invalid byte branch offset"));
5021 }
5022
5023 /* *fragP has been relaxed to its final size, and now needs to have
5024 the bytes inside it modified to conform to the new size There is UGLY
5025 MAGIC here. ..
5026 */
5027 static void
5028 md_convert_frag_1 (fragS *fragP)
5029 {
5030 long disp;
5031 fixS *fixP = NULL;
5032
5033 /* Address in object code of the displacement. */
5034 int object_address = fragP->fr_fix + fragP->fr_address;
5035
5036 /* Address in gas core of the place to store the displacement. */
5037 /* This convinces the native rs6000 compiler to generate the code we
5038 want. */
5039 char *buffer_address = fragP->fr_literal;
5040 buffer_address += fragP->fr_fix;
5041 /* End ibm compiler workaround. */
5042
5043 /* The displacement of the address, from current location. */
5044 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
5045 disp = (disp + fragP->fr_offset) - object_address;
5046
5047 switch (fragP->fr_subtype)
5048 {
5049 case TAB (BRANCHBWL, BYTE):
5050 case TAB (BRABSJUNC, BYTE):
5051 case TAB (BRABSJCOND, BYTE):
5052 case TAB (BRANCHBW, BYTE):
5053 case TAB (BRANCHBWPL, BYTE):
5054 know (issbyte (disp));
5055 if (disp == 0)
5056 as_bad_where (fragP->fr_file, fragP->fr_line,
5057 _("short branch with zero offset: use :w"));
5058 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5059 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5060 fixP->fx_pcrel_adjust = -1;
5061 break;
5062 case TAB (BRANCHBWL, SHORT):
5063 case TAB (BRABSJUNC, SHORT):
5064 case TAB (BRABSJCOND, SHORT):
5065 case TAB (BRANCHBW, SHORT):
5066 case TAB (BRANCHBWPL, SHORT):
5067 fragP->fr_opcode[1] = 0x00;
5068 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5069 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5070 fragP->fr_fix += 2;
5071 break;
5072 case TAB (BRANCHBWL, LONG):
5073 fragP->fr_opcode[1] = (char) 0xFF;
5074 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5075 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5076 fragP->fr_fix += 4;
5077 break;
5078 case TAB (BRANCHBWPL, LONG):
5079 /* Here we are converting an unconditional branch into a pair of
5080 conditional branches, in order to get the range. */
5081 fragP->fr_opcode[0] = 0x66; /* bne */
5082 fragP->fr_opcode[1] = 0xFF;
5083 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5084 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5085 fixP->fx_file = fragP->fr_file;
5086 fixP->fx_line = fragP->fr_line;
5087 fragP->fr_fix += 4; /* Skip first offset */
5088 buffer_address += 4;
5089 *buffer_address++ = 0x67; /* beq */
5090 *buffer_address++ = 0xff;
5091 fragP->fr_fix += 2; /* Skip second branch opcode */
5092 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5093 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5094 fragP->fr_fix += 4;
5095 break;
5096 case TAB (BRABSJUNC, LONG):
5097 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
5098 {
5099 if (flag_keep_pcrel)
5100 as_bad_where (fragP->fr_file, fragP->fr_line,
5101 _("Conversion of PC relative BSR to absolute JSR"));
5102 fragP->fr_opcode[0] = 0x4E;
5103 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
5104 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5105 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5106 fragP->fr_fix += 4;
5107 }
5108 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
5109 {
5110 if (flag_keep_pcrel)
5111 as_bad_where (fragP->fr_file, fragP->fr_line,
5112 _("Conversion of PC relative branch to absolute jump"));
5113 fragP->fr_opcode[0] = 0x4E;
5114 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
5115 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5116 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5117 fragP->fr_fix += 4;
5118 }
5119 else
5120 {
5121 /* This cannot happen, because jbsr and jbra are the only two
5122 unconditional branches. */
5123 abort ();
5124 }
5125 break;
5126 case TAB (BRABSJCOND, LONG):
5127 if (flag_keep_pcrel)
5128 as_bad_where (fragP->fr_file, fragP->fr_line,
5129 _("Conversion of PC relative conditional branch to absolute jump"));
5130
5131 /* Only Bcc 68000 instructions can come here
5132 Change bcc into b!cc/jmp absl long. */
5133 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
5134 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
5135
5136 /* JF: these used to be fr_opcode[2,3], but they may be in a
5137 different frag, in which case referring to them is a no-no.
5138 Only fr_opcode[0,1] are guaranteed to work. */
5139 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
5140 *buffer_address++ = (char) 0xf9;
5141 fragP->fr_fix += 2; /* Account for jmp instruction. */
5142 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5143 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5144 fragP->fr_fix += 4;
5145 break;
5146 case TAB (FBRANCH, SHORT):
5147 know ((fragP->fr_opcode[1] & 0x40) == 0);
5148 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5149 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5150 fragP->fr_fix += 2;
5151 break;
5152 case TAB (FBRANCH, LONG):
5153 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
5154 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5155 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5156 fragP->fr_fix += 4;
5157 break;
5158 case TAB (DBCCLBR, SHORT):
5159 case TAB (DBCCABSJ, SHORT):
5160 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5161 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5162 fragP->fr_fix += 2;
5163 break;
5164 case TAB (DBCCLBR, LONG):
5165 /* Only DBcc instructions can come here.
5166 Change dbcc into dbcc/bral.
5167 JF: these used to be fr_opcode[2-7], but that's wrong. */
5168 *buffer_address++ = 0x00; /* Branch offset = 4. */
5169 *buffer_address++ = 0x04;
5170 *buffer_address++ = 0x60; /* Put in bra pc+6. */
5171 *buffer_address++ = 0x06;
5172 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5173 *buffer_address++ = (char) 0xff;
5174
5175 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5176 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5177 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5178 fragP->fr_fix += 4;
5179 break;
5180 case TAB (DBCCABSJ, LONG):
5181 /* Only DBcc instructions can come here.
5182 Change dbcc into dbcc/jmp.
5183 JF: these used to be fr_opcode[2-7], but that's wrong. */
5184 if (flag_keep_pcrel)
5185 as_bad_where (fragP->fr_file, fragP->fr_line,
5186 _("Conversion of PC relative conditional branch to absolute jump"));
5187
5188 *buffer_address++ = 0x00; /* Branch offset = 4. */
5189 *buffer_address++ = 0x04;
5190 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
5191 *buffer_address++ = 0x06;
5192 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
5193 *buffer_address++ = (char) 0xf9;
5194
5195 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5196 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5197 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5198 fragP->fr_fix += 4;
5199 break;
5200 case TAB (PCREL1632, SHORT):
5201 fragP->fr_opcode[1] &= ~0x3F;
5202 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
5203 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5204 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5205 fragP->fr_fix += 2;
5206 break;
5207 case TAB (PCREL1632, LONG):
5208 /* Already set to mode 7.3; this indicates: PC indirect with
5209 suppressed index, 32-bit displacement. */
5210 *buffer_address++ = 0x01;
5211 *buffer_address++ = 0x70;
5212 fragP->fr_fix += 2;
5213 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5214 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5215 fixP->fx_pcrel_adjust = 2;
5216 fragP->fr_fix += 4;
5217 break;
5218 case TAB (PCINDEX, BYTE):
5219 gas_assert (fragP->fr_fix >= 2);
5220 buffer_address[-2] &= ~1;
5221 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5222 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5223 fixP->fx_pcrel_adjust = 1;
5224 break;
5225 case TAB (PCINDEX, SHORT):
5226 gas_assert (fragP->fr_fix >= 2);
5227 buffer_address[-2] |= 0x1;
5228 buffer_address[-1] = 0x20;
5229 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5230 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5231 fixP->fx_pcrel_adjust = 2;
5232 fragP->fr_fix += 2;
5233 break;
5234 case TAB (PCINDEX, LONG):
5235 gas_assert (fragP->fr_fix >= 2);
5236 buffer_address[-2] |= 0x1;
5237 buffer_address[-1] = 0x30;
5238 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5239 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5240 fixP->fx_pcrel_adjust = 2;
5241 fragP->fr_fix += 4;
5242 break;
5243 case TAB (ABSTOPCREL, SHORT):
5244 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5245 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5246 fragP->fr_fix += 2;
5247 break;
5248 case TAB (ABSTOPCREL, LONG):
5249 if (flag_keep_pcrel)
5250 as_bad_where (fragP->fr_file, fragP->fr_line,
5251 _("Conversion of PC relative displacement to absolute"));
5252 /* The thing to do here is force it to ABSOLUTE LONG, since
5253 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5254 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5255 abort ();
5256 fragP->fr_opcode[1] &= ~0x3F;
5257 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
5258 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5259 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5260 fragP->fr_fix += 4;
5261 break;
5262 }
5263 if (fixP)
5264 {
5265 fixP->fx_file = fragP->fr_file;
5266 fixP->fx_line = fragP->fr_line;
5267 }
5268 }
5269
5270 void
5271 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5272 segT sec ATTRIBUTE_UNUSED,
5273 fragS *fragP)
5274 {
5275 md_convert_frag_1 (fragP);
5276 }
5277
5278 /* Force truly undefined symbols to their maximum size, and generally set up
5279 the frag list to be relaxed
5280 */
5281 int
5282 md_estimate_size_before_relax (fragS *fragP, segT segment)
5283 {
5284 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5285 switch (fragP->fr_subtype)
5286 {
5287 case TAB (BRANCHBWL, SZ_UNDEF):
5288 case TAB (BRANCHBWPL, SZ_UNDEF):
5289 case TAB (BRABSJUNC, SZ_UNDEF):
5290 case TAB (BRABSJCOND, SZ_UNDEF):
5291 {
5292 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5293 && relaxable_symbol (fragP->fr_symbol))
5294 {
5295 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5296 }
5297 else if (flag_short_refs)
5298 {
5299 /* Symbol is undefined and we want short ref. */
5300 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5301 }
5302 else
5303 {
5304 /* Symbol is still undefined. Make it LONG. */
5305 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5306 }
5307 break;
5308 }
5309
5310 case TAB (BRANCHBW, SZ_UNDEF):
5311 {
5312 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5313 && relaxable_symbol (fragP->fr_symbol))
5314 {
5315 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5316 }
5317 else
5318 {
5319 /* Symbol is undefined and we don't have long branches. */
5320 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5321 }
5322 break;
5323 }
5324
5325 case TAB (FBRANCH, SZ_UNDEF):
5326 case TAB (DBCCLBR, SZ_UNDEF):
5327 case TAB (DBCCABSJ, SZ_UNDEF):
5328 case TAB (PCREL1632, SZ_UNDEF):
5329 {
5330 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5331 && relaxable_symbol (fragP->fr_symbol))
5332 || flag_short_refs)
5333 {
5334 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5335 }
5336 else
5337 {
5338 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5339 }
5340 break;
5341 }
5342
5343 case TAB (PCINDEX, SZ_UNDEF):
5344 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5345 && relaxable_symbol (fragP->fr_symbol)))
5346 {
5347 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5348 }
5349 else
5350 {
5351 fragP->fr_subtype = TAB (PCINDEX, LONG);
5352 }
5353 break;
5354
5355 case TAB (ABSTOPCREL, SZ_UNDEF):
5356 {
5357 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5358 && relaxable_symbol (fragP->fr_symbol)))
5359 {
5360 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5361 }
5362 else
5363 {
5364 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5365 }
5366 break;
5367 }
5368
5369 default:
5370 break;
5371 }
5372
5373 /* Now that SZ_UNDEF are taken care of, check others. */
5374 switch (fragP->fr_subtype)
5375 {
5376 case TAB (BRANCHBWL, BYTE):
5377 case TAB (BRABSJUNC, BYTE):
5378 case TAB (BRABSJCOND, BYTE):
5379 case TAB (BRANCHBW, BYTE):
5380 /* We can't do a short jump to the next instruction, so in that
5381 case we force word mode. If the symbol is at the start of a
5382 frag, and it is the next frag with any data in it (usually
5383 this is just the next frag, but assembler listings may
5384 introduce empty frags), we must use word mode. */
5385 if (fragP->fr_symbol)
5386 {
5387 fragS *sym_frag;
5388
5389 sym_frag = symbol_get_frag (fragP->fr_symbol);
5390 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5391 {
5392 fragS *l;
5393
5394 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5395 if (l->fr_fix != 0)
5396 break;
5397 if (l == sym_frag)
5398 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5399 }
5400 }
5401 break;
5402 default:
5403 break;
5404 }
5405 return md_relax_table[fragP->fr_subtype].rlx_length;
5406 }
5407
5408 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5409 /* the bit-field entries in the relocation_info struct plays hell
5410 with the byte-order problems of cross-assembly. So as a hack,
5411 I added this mach. dependent ri twiddler. Ugly, but it gets
5412 you there. -KWK */
5413 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5414 are symbolnum, most sig. byte first. Last byte is broken up with
5415 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5416 nibble as nuthin. (on Sun 3 at least) */
5417 /* Translate the internal relocation information into target-specific
5418 format. */
5419 #ifdef comment
5420 void
5421 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5422 {
5423 /* This is easy. */
5424 md_number_to_chars (the_bytes, ri->r_address, 4);
5425 /* Now the fun stuff. */
5426 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5427 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5428 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5429 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5430 | ((ri->r_length << 5) & 0x60)
5431 | ((ri->r_extern << 4) & 0x10));
5432 }
5433
5434 #endif
5435
5436 #endif /* OBJ_AOUT or OBJ_BOUT */
5437
5438 #ifndef WORKING_DOT_WORD
5439 int md_short_jump_size = 4;
5440 int md_long_jump_size = 6;
5441
5442 void
5443 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5444 fragS *frag ATTRIBUTE_UNUSED,
5445 symbolS *to_symbol ATTRIBUTE_UNUSED)
5446 {
5447 valueT offset;
5448
5449 offset = to_addr - (from_addr + 2);
5450
5451 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5452 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5453 }
5454
5455 void
5456 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5457 fragS *frag, symbolS *to_symbol)
5458 {
5459 valueT offset;
5460
5461 if (!HAVE_LONG_BRANCH (current_architecture))
5462 {
5463 if (flag_keep_pcrel)
5464 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5465 offset = to_addr - S_GET_VALUE (to_symbol);
5466 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5467 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5468 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5469 0, NO_RELOC);
5470 }
5471 else
5472 {
5473 offset = to_addr - (from_addr + 2);
5474 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5475 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5476 }
5477 }
5478
5479 #endif
5480
5481 /* Different values of OK tell what it's OK to return. Things that
5482 aren't OK are an error (what a shock, no?)
5483
5484 0: Everything is OK
5485 10: Absolute 1:8 only
5486 20: Absolute 0:7 only
5487 30: absolute 0:15 only
5488 40: Absolute 0:31 only
5489 50: absolute 0:127 only
5490 55: absolute -64:63 only
5491 60: absolute -128:127 only
5492 65: absolute 0:511 only
5493 70: absolute 0:4095 only
5494 80: absolute -1, 1:7 only
5495 90: No bignums. */
5496
5497 static int
5498 get_num (struct m68k_exp *exp, int ok)
5499 {
5500 if (exp->exp.X_op == O_absent)
5501 {
5502 /* Do the same thing the VAX asm does. */
5503 op (exp) = O_constant;
5504 adds (exp) = 0;
5505 subs (exp) = 0;
5506 offs (exp) = 0;
5507 if (ok == 10)
5508 {
5509 as_warn (_("expression out of range: defaulting to 1"));
5510 offs (exp) = 1;
5511 }
5512 }
5513 else if (exp->exp.X_op == O_constant)
5514 {
5515 switch (ok)
5516 {
5517 case 10:
5518 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5519 {
5520 as_warn (_("expression out of range: defaulting to 1"));
5521 offs (exp) = 1;
5522 }
5523 break;
5524 case 20:
5525 if ((valueT) TRUNC (offs (exp)) > 7)
5526 goto outrange;
5527 break;
5528 case 30:
5529 if ((valueT) TRUNC (offs (exp)) > 15)
5530 goto outrange;
5531 break;
5532 case 40:
5533 if ((valueT) TRUNC (offs (exp)) > 32)
5534 goto outrange;
5535 break;
5536 case 50:
5537 if ((valueT) TRUNC (offs (exp)) > 127)
5538 goto outrange;
5539 break;
5540 case 55:
5541 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5542 goto outrange;
5543 break;
5544 case 60:
5545 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5546 goto outrange;
5547 break;
5548 case 65:
5549 if ((valueT) TRUNC (offs (exp)) > 511)
5550 goto outrange;
5551 break;
5552 case 70:
5553 if ((valueT) TRUNC (offs (exp)) > 4095)
5554 {
5555 outrange:
5556 as_warn (_("expression out of range: defaulting to 0"));
5557 offs (exp) = 0;
5558 }
5559 break;
5560 case 80:
5561 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5562 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5563 {
5564 as_warn (_("expression out of range: defaulting to 1"));
5565 offs (exp) = 1;
5566 }
5567 break;
5568 default:
5569 break;
5570 }
5571 }
5572 else if (exp->exp.X_op == O_big)
5573 {
5574 if (offs (exp) <= 0 /* flonum. */
5575 && (ok == 90 /* no bignums */
5576 || (ok > 10 /* Small-int ranges including 0 ok. */
5577 /* If we have a flonum zero, a zero integer should
5578 do as well (e.g., in moveq). */
5579 && generic_floating_point_number.exponent == 0
5580 && generic_floating_point_number.low[0] == 0)))
5581 {
5582 /* HACK! Turn it into a long. */
5583 LITTLENUM_TYPE words[6];
5584
5585 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5586 op (exp) = O_constant;
5587 adds (exp) = 0;
5588 subs (exp) = 0;
5589 offs (exp) = words[1] | (words[0] << 16);
5590 }
5591 else if (ok != 0)
5592 {
5593 op (exp) = O_constant;
5594 adds (exp) = 0;
5595 subs (exp) = 0;
5596 offs (exp) = (ok == 10) ? 1 : 0;
5597 as_warn (_("Can't deal with expression; defaulting to %ld"),
5598 (long) offs (exp));
5599 }
5600 }
5601 else
5602 {
5603 if (ok >= 10 && ok <= 80)
5604 {
5605 op (exp) = O_constant;
5606 adds (exp) = 0;
5607 subs (exp) = 0;
5608 offs (exp) = (ok == 10) ? 1 : 0;
5609 as_warn (_("Can't deal with expression; defaulting to %ld"),
5610 (long) offs (exp));
5611 }
5612 }
5613
5614 if (exp->size != SIZE_UNSPEC)
5615 {
5616 switch (exp->size)
5617 {
5618 case SIZE_UNSPEC:
5619 case SIZE_LONG:
5620 break;
5621 case SIZE_BYTE:
5622 if (!isbyte (offs (exp)))
5623 as_warn (_("expression doesn't fit in BYTE"));
5624 break;
5625 case SIZE_WORD:
5626 if (!isword (offs (exp)))
5627 as_warn (_("expression doesn't fit in WORD"));
5628 break;
5629 }
5630 }
5631
5632 return offs (exp);
5633 }
5634
5635 /* These are the back-ends for the various machine dependent pseudo-ops. */
5636
5637 static void
5638 s_data1 (int ignore ATTRIBUTE_UNUSED)
5639 {
5640 subseg_set (data_section, 1);
5641 demand_empty_rest_of_line ();
5642 }
5643
5644 static void
5645 s_data2 (int ignore ATTRIBUTE_UNUSED)
5646 {
5647 subseg_set (data_section, 2);
5648 demand_empty_rest_of_line ();
5649 }
5650
5651 static void
5652 s_bss (int ignore ATTRIBUTE_UNUSED)
5653 {
5654 /* We don't support putting frags in the BSS segment, we fake it
5655 by marking in_bss, then looking at s_skip for clues. */
5656
5657 subseg_set (bss_section, 0);
5658 demand_empty_rest_of_line ();
5659 }
5660
5661 static void
5662 s_even (int ignore ATTRIBUTE_UNUSED)
5663 {
5664 int temp;
5665 long temp_fill;
5666
5667 temp = 1; /* JF should be 2? */
5668 temp_fill = get_absolute_expression ();
5669 if (!need_pass_2) /* Never make frag if expect extra pass. */
5670 frag_align (temp, (int) temp_fill, 0);
5671 demand_empty_rest_of_line ();
5672 record_alignment (now_seg, temp);
5673 }
5674
5675 static void
5676 s_proc (int ignore ATTRIBUTE_UNUSED)
5677 {
5678 demand_empty_rest_of_line ();
5679 }
5680 \f
5681 /* Pseudo-ops handled for MRI compatibility. */
5682
5683 /* This function returns non-zero if the argument is a conditional
5684 pseudo-op. This is called when checking whether a pending
5685 alignment is needed. */
5686
5687 int
5688 m68k_conditional_pseudoop (pseudo_typeS *pop)
5689 {
5690 return (pop->poc_handler == s_mri_if
5691 || pop->poc_handler == s_mri_else);
5692 }
5693
5694 /* Handle an MRI style chip specification. */
5695
5696 static void
5697 mri_chip (void)
5698 {
5699 char *s;
5700 char c;
5701 int i;
5702
5703 s = input_line_pointer;
5704 /* We can't use get_symbol_name since the processor names are not proper
5705 symbols. */
5706 while (is_part_of_name (c = *input_line_pointer++))
5707 ;
5708 *--input_line_pointer = 0;
5709 for (i = 0; m68k_cpus[i].name; i++)
5710 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5711 break;
5712 if (!m68k_cpus[i].name)
5713 {
5714 as_bad (_("%s: unrecognized processor name"), s);
5715 *input_line_pointer = c;
5716 ignore_rest_of_line ();
5717 return;
5718 }
5719 *input_line_pointer = c;
5720
5721 if (*input_line_pointer == '/')
5722 current_architecture = 0;
5723 else
5724 current_architecture &= m68881 | m68851;
5725 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5726 control_regs = m68k_cpus[i].control_regs;
5727
5728 while (*input_line_pointer == '/')
5729 {
5730 ++input_line_pointer;
5731 s = input_line_pointer;
5732 /* We can't use get_symbol_name since the processor names are not
5733 proper symbols. */
5734 while (is_part_of_name (c = *input_line_pointer++))
5735 ;
5736 *--input_line_pointer = 0;
5737 if (strcmp (s, "68881") == 0)
5738 current_architecture |= m68881;
5739 else if (strcmp (s, "68851") == 0)
5740 current_architecture |= m68851;
5741 *input_line_pointer = c;
5742 }
5743 }
5744
5745 /* The MRI CHIP pseudo-op. */
5746
5747 static void
5748 s_chip (int ignore ATTRIBUTE_UNUSED)
5749 {
5750 char *stop = NULL;
5751 char stopc;
5752
5753 if (flag_mri)
5754 stop = mri_comment_field (&stopc);
5755 mri_chip ();
5756 if (flag_mri)
5757 mri_comment_end (stop, stopc);
5758 demand_empty_rest_of_line ();
5759 }
5760
5761 /* The MRI FOPT pseudo-op. */
5762
5763 static void
5764 s_fopt (int ignore ATTRIBUTE_UNUSED)
5765 {
5766 SKIP_WHITESPACE ();
5767
5768 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5769 {
5770 int temp;
5771
5772 input_line_pointer += 3;
5773 temp = get_absolute_expression ();
5774 if (temp < 0 || temp > 7)
5775 as_bad (_("bad coprocessor id"));
5776 else
5777 m68k_float_copnum = COP0 + temp;
5778 }
5779 else
5780 {
5781 as_bad (_("unrecognized fopt option"));
5782 ignore_rest_of_line ();
5783 return;
5784 }
5785
5786 demand_empty_rest_of_line ();
5787 }
5788
5789 /* The structure used to handle the MRI OPT pseudo-op. */
5790
5791 struct opt_action
5792 {
5793 /* The name of the option. */
5794 const char *name;
5795
5796 /* If this is not NULL, just call this function. The first argument
5797 is the ARG field of this structure, the second argument is
5798 whether the option was negated. */
5799 void (*pfn) (int arg, int on);
5800
5801 /* If this is not NULL, and the PFN field is NULL, set the variable
5802 this points to. Set it to the ARG field if the option was not
5803 negated, and the NOTARG field otherwise. */
5804 int *pvar;
5805
5806 /* The value to pass to PFN or to assign to *PVAR. */
5807 int arg;
5808
5809 /* The value to assign to *PVAR if the option is negated. If PFN is
5810 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5811 the option may not be negated. */
5812 int notarg;
5813 };
5814
5815 /* The table used to handle the MRI OPT pseudo-op. */
5816
5817 static void skip_to_comma (int, int);
5818 static void opt_nest (int, int);
5819 static void opt_chip (int, int);
5820 static void opt_list (int, int);
5821 static void opt_list_symbols (int, int);
5822
5823 static const struct opt_action opt_table[] =
5824 {
5825 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5826
5827 /* We do relaxing, so there is little use for these options. */
5828 { "b", 0, 0, 0, 0 },
5829 { "brs", 0, 0, 0, 0 },
5830 { "brb", 0, 0, 0, 0 },
5831 { "brl", 0, 0, 0, 0 },
5832 { "brw", 0, 0, 0, 0 },
5833
5834 { "c", 0, 0, 0, 0 },
5835 { "cex", 0, 0, 0, 0 },
5836 { "case", 0, &symbols_case_sensitive, 1, 0 },
5837 { "cl", 0, 0, 0, 0 },
5838 { "cre", 0, 0, 0, 0 },
5839 { "d", 0, &flag_keep_locals, 1, 0 },
5840 { "e", 0, 0, 0, 0 },
5841 { "f", 0, &flag_short_refs, 1, 0 },
5842 { "frs", 0, &flag_short_refs, 1, 0 },
5843 { "frl", 0, &flag_short_refs, 0, 1 },
5844 { "g", 0, 0, 0, 0 },
5845 { "i", 0, 0, 0, 0 },
5846 { "m", 0, 0, 0, 0 },
5847 { "mex", 0, 0, 0, 0 },
5848 { "mc", 0, 0, 0, 0 },
5849 { "md", 0, 0, 0, 0 },
5850 { "nest", opt_nest, 0, 0, 0 },
5851 { "next", skip_to_comma, 0, 0, 0 },
5852 { "o", 0, 0, 0, 0 },
5853 { "old", 0, 0, 0, 0 },
5854 { "op", skip_to_comma, 0, 0, 0 },
5855 { "pco", 0, 0, 0, 0 },
5856 { "p", opt_chip, 0, 0, 0 },
5857 { "pcr", 0, 0, 0, 0 },
5858 { "pcs", 0, 0, 0, 0 },
5859 { "r", 0, 0, 0, 0 },
5860 { "quick", 0, &m68k_quick, 1, 0 },
5861 { "rel32", 0, &m68k_rel32, 1, 0 },
5862 { "s", opt_list, 0, 0, 0 },
5863 { "t", opt_list_symbols, 0, 0, 0 },
5864 { "w", 0, &flag_no_warnings, 0, 1 },
5865 { "x", 0, 0, 0, 0 }
5866 };
5867
5868 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5869
5870 /* The MRI OPT pseudo-op. */
5871
5872 static void
5873 s_opt (int ignore ATTRIBUTE_UNUSED)
5874 {
5875 do
5876 {
5877 int t;
5878 char *s;
5879 char c;
5880 int i;
5881 const struct opt_action *o;
5882
5883 SKIP_WHITESPACE ();
5884
5885 t = 1;
5886 if (*input_line_pointer == '-')
5887 {
5888 ++input_line_pointer;
5889 t = 0;
5890 }
5891 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5892 {
5893 input_line_pointer += 2;
5894 t = 0;
5895 }
5896
5897 c = get_symbol_name (&s);
5898
5899 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5900 {
5901 if (strcasecmp (s, o->name) == 0)
5902 {
5903 if (o->pfn)
5904 {
5905 /* Restore input_line_pointer now in case the option
5906 takes arguments. */
5907 (void) restore_line_pointer (c);
5908 (*o->pfn) (o->arg, t);
5909 }
5910 else if (o->pvar != NULL)
5911 {
5912 if (! t && o->arg == o->notarg)
5913 as_bad (_("option `%s' may not be negated"), s);
5914 restore_line_pointer (c);
5915 *o->pvar = t ? o->arg : o->notarg;
5916 }
5917 else
5918 *input_line_pointer = c;
5919 break;
5920 }
5921 }
5922 if (i >= OPTCOUNT)
5923 {
5924 as_bad (_("option `%s' not recognized"), s);
5925 restore_line_pointer (c);
5926 }
5927 }
5928 while (*input_line_pointer++ == ',');
5929
5930 /* Move back to terminating character. */
5931 --input_line_pointer;
5932 demand_empty_rest_of_line ();
5933 }
5934
5935 /* Skip ahead to a comma. This is used for OPT options which we do
5936 not support and which take arguments. */
5937
5938 static void
5939 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5940 {
5941 while (*input_line_pointer != ','
5942 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5943 ++input_line_pointer;
5944 }
5945
5946 /* Handle the OPT NEST=depth option. */
5947
5948 static void
5949 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5950 {
5951 if (*input_line_pointer != '=')
5952 {
5953 as_bad (_("bad format of OPT NEST=depth"));
5954 return;
5955 }
5956
5957 ++input_line_pointer;
5958 max_macro_nest = get_absolute_expression ();
5959 }
5960
5961 /* Handle the OPT P=chip option. */
5962
5963 static void
5964 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5965 {
5966 if (*input_line_pointer != '=')
5967 {
5968 /* This is just OPT P, which we do not support. */
5969 return;
5970 }
5971
5972 ++input_line_pointer;
5973 mri_chip ();
5974 }
5975
5976 /* Handle the OPT S option. */
5977
5978 static void
5979 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5980 {
5981 listing_list (on);
5982 }
5983
5984 /* Handle the OPT T option. */
5985
5986 static void
5987 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5988 {
5989 if (on)
5990 listing |= LISTING_SYMBOLS;
5991 else
5992 listing &= ~LISTING_SYMBOLS;
5993 }
5994
5995 /* Handle the MRI REG pseudo-op. */
5996
5997 static void
5998 s_reg (int ignore ATTRIBUTE_UNUSED)
5999 {
6000 char *s;
6001 int c;
6002 struct m68k_op rop;
6003 int mask;
6004 char *stop = NULL;
6005 char stopc;
6006
6007 if (line_label == NULL)
6008 {
6009 as_bad (_("missing label"));
6010 ignore_rest_of_line ();
6011 return;
6012 }
6013
6014 if (flag_mri)
6015 stop = mri_comment_field (&stopc);
6016
6017 SKIP_WHITESPACE ();
6018
6019 s = input_line_pointer;
6020 while (ISALNUM (*input_line_pointer)
6021 #ifdef REGISTER_PREFIX
6022 || *input_line_pointer == REGISTER_PREFIX
6023 #endif
6024 || *input_line_pointer == '/'
6025 || *input_line_pointer == '-')
6026 ++input_line_pointer;
6027 c = *input_line_pointer;
6028 *input_line_pointer = '\0';
6029
6030 if (m68k_ip_op (s, &rop) != 0)
6031 {
6032 if (rop.error == NULL)
6033 as_bad (_("bad register list"));
6034 else
6035 as_bad (_("bad register list: %s"), rop.error);
6036 *input_line_pointer = c;
6037 ignore_rest_of_line ();
6038 return;
6039 }
6040
6041 *input_line_pointer = c;
6042
6043 if (rop.mode == REGLST)
6044 mask = rop.mask;
6045 else if (rop.mode == DREG)
6046 mask = 1 << (rop.reg - DATA0);
6047 else if (rop.mode == AREG)
6048 mask = 1 << (rop.reg - ADDR0 + 8);
6049 else if (rop.mode == FPREG)
6050 mask = 1 << (rop.reg - FP0 + 16);
6051 else if (rop.mode == CONTROL
6052 && rop.reg == FPI)
6053 mask = 1 << 24;
6054 else if (rop.mode == CONTROL
6055 && rop.reg == FPS)
6056 mask = 1 << 25;
6057 else if (rop.mode == CONTROL
6058 && rop.reg == FPC)
6059 mask = 1 << 26;
6060 else
6061 {
6062 as_bad (_("bad register list"));
6063 ignore_rest_of_line ();
6064 return;
6065 }
6066
6067 S_SET_SEGMENT (line_label, reg_section);
6068 S_SET_VALUE (line_label, ~mask);
6069 symbol_set_frag (line_label, &zero_address_frag);
6070
6071 if (flag_mri)
6072 mri_comment_end (stop, stopc);
6073
6074 demand_empty_rest_of_line ();
6075 }
6076
6077 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
6078
6079 struct save_opts
6080 {
6081 struct save_opts *next;
6082 int abspcadd;
6083 int symbols_case_sensitive;
6084 int keep_locals;
6085 int short_refs;
6086 int architecture;
6087 const enum m68k_register *control_regs;
6088 int quick;
6089 int rel32;
6090 int listing;
6091 int no_warnings;
6092 /* FIXME: We don't save OPT S. */
6093 };
6094
6095 /* This variable holds the stack of saved options. */
6096
6097 static struct save_opts *save_stack;
6098
6099 /* The MRI SAVE pseudo-op. */
6100
6101 static void
6102 s_save (int ignore ATTRIBUTE_UNUSED)
6103 {
6104 struct save_opts *s;
6105
6106 s = XNEW (struct save_opts);
6107 s->abspcadd = m68k_abspcadd;
6108 s->symbols_case_sensitive = symbols_case_sensitive;
6109 s->keep_locals = flag_keep_locals;
6110 s->short_refs = flag_short_refs;
6111 s->architecture = current_architecture;
6112 s->control_regs = control_regs;
6113 s->quick = m68k_quick;
6114 s->rel32 = m68k_rel32;
6115 s->listing = listing;
6116 s->no_warnings = flag_no_warnings;
6117
6118 s->next = save_stack;
6119 save_stack = s;
6120
6121 demand_empty_rest_of_line ();
6122 }
6123
6124 /* The MRI RESTORE pseudo-op. */
6125
6126 static void
6127 s_restore (int ignore ATTRIBUTE_UNUSED)
6128 {
6129 struct save_opts *s;
6130
6131 if (save_stack == NULL)
6132 {
6133 as_bad (_("restore without save"));
6134 ignore_rest_of_line ();
6135 return;
6136 }
6137
6138 s = save_stack;
6139 save_stack = s->next;
6140
6141 m68k_abspcadd = s->abspcadd;
6142 symbols_case_sensitive = s->symbols_case_sensitive;
6143 flag_keep_locals = s->keep_locals;
6144 flag_short_refs = s->short_refs;
6145 current_architecture = s->architecture;
6146 control_regs = s->control_regs;
6147 m68k_quick = s->quick;
6148 m68k_rel32 = s->rel32;
6149 listing = s->listing;
6150 flag_no_warnings = s->no_warnings;
6151
6152 free (s);
6153
6154 demand_empty_rest_of_line ();
6155 }
6156
6157 /* Types of MRI structured control directives. */
6158
6159 enum mri_control_type
6160 {
6161 mri_for,
6162 mri_if,
6163 mri_repeat,
6164 mri_while
6165 };
6166
6167 /* This structure is used to stack the MRI structured control
6168 directives. */
6169
6170 struct mri_control_info
6171 {
6172 /* The directive within which this one is enclosed. */
6173 struct mri_control_info *outer;
6174
6175 /* The type of directive. */
6176 enum mri_control_type type;
6177
6178 /* Whether an ELSE has been in an IF. */
6179 int else_seen;
6180
6181 /* The add or sub statement at the end of a FOR. */
6182 char *incr;
6183
6184 /* The label of the top of a FOR or REPEAT loop. */
6185 char *top;
6186
6187 /* The label to jump to for the next iteration, or the else
6188 expression of a conditional. */
6189 char *next;
6190
6191 /* The label to jump to to break out of the loop, or the label past
6192 the end of a conditional. */
6193 char *bottom;
6194 };
6195
6196 /* The stack of MRI structured control directives. */
6197
6198 static struct mri_control_info *mri_control_stack;
6199
6200 /* The current MRI structured control directive index number, used to
6201 generate label names. */
6202
6203 static int mri_control_index;
6204
6205 /* Assemble an instruction for an MRI structured control directive. */
6206
6207 static void
6208 mri_assemble (char *str)
6209 {
6210 char *s;
6211
6212 /* md_assemble expects the opcode to be in lower case. */
6213 for (s = str; *s != ' ' && *s != '\0'; s++)
6214 *s = TOLOWER (*s);
6215
6216 md_assemble (str);
6217 }
6218
6219 /* Generate a new MRI label structured control directive label name. */
6220
6221 static char *
6222 mri_control_label (void)
6223 {
6224 char *n;
6225
6226 n = XNEWVEC (char, 20);
6227 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6228 ++mri_control_index;
6229 return n;
6230 }
6231
6232 /* Create a new MRI structured control directive. */
6233
6234 static struct mri_control_info *
6235 push_mri_control (enum mri_control_type type)
6236 {
6237 struct mri_control_info *n;
6238
6239 n = XNEW (struct mri_control_info);
6240
6241 n->type = type;
6242 n->else_seen = 0;
6243 if (type == mri_if || type == mri_while)
6244 n->top = NULL;
6245 else
6246 n->top = mri_control_label ();
6247 n->next = mri_control_label ();
6248 n->bottom = mri_control_label ();
6249
6250 n->outer = mri_control_stack;
6251 mri_control_stack = n;
6252
6253 return n;
6254 }
6255
6256 /* Pop off the stack of MRI structured control directives. */
6257
6258 static void
6259 pop_mri_control (void)
6260 {
6261 struct mri_control_info *n;
6262
6263 n = mri_control_stack;
6264 mri_control_stack = n->outer;
6265 if (n->top != NULL)
6266 free (n->top);
6267 free (n->next);
6268 free (n->bottom);
6269 free (n);
6270 }
6271
6272 /* Recognize a condition code in an MRI structured control expression. */
6273
6274 static int
6275 parse_mri_condition (int *pcc)
6276 {
6277 char c1, c2;
6278
6279 know (*input_line_pointer == '<');
6280
6281 ++input_line_pointer;
6282 c1 = *input_line_pointer++;
6283 c2 = *input_line_pointer++;
6284
6285 if (*input_line_pointer != '>')
6286 {
6287 as_bad (_("syntax error in structured control directive"));
6288 return 0;
6289 }
6290
6291 ++input_line_pointer;
6292 SKIP_WHITESPACE ();
6293
6294 c1 = TOLOWER (c1);
6295 c2 = TOLOWER (c2);
6296
6297 *pcc = (c1 << 8) | c2;
6298
6299 return 1;
6300 }
6301
6302 /* Parse a single operand in an MRI structured control expression. */
6303
6304 static int
6305 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6306 char **rightstart, char **rightstop)
6307 {
6308 char *s;
6309
6310 SKIP_WHITESPACE ();
6311
6312 *pcc = -1;
6313 *leftstart = NULL;
6314 *leftstop = NULL;
6315 *rightstart = NULL;
6316 *rightstop = NULL;
6317
6318 if (*input_line_pointer == '<')
6319 {
6320 /* It's just a condition code. */
6321 return parse_mri_condition (pcc);
6322 }
6323
6324 /* Look ahead for the condition code. */
6325 for (s = input_line_pointer; *s != '\0'; ++s)
6326 {
6327 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6328 break;
6329 }
6330 if (*s == '\0')
6331 {
6332 as_bad (_("missing condition code in structured control directive"));
6333 return 0;
6334 }
6335
6336 *leftstart = input_line_pointer;
6337 *leftstop = s;
6338 if (*leftstop > *leftstart
6339 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6340 --*leftstop;
6341
6342 input_line_pointer = s;
6343 if (! parse_mri_condition (pcc))
6344 return 0;
6345
6346 /* Look ahead for AND or OR or end of line. */
6347 for (s = input_line_pointer; *s != '\0'; ++s)
6348 {
6349 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6350 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6351 ^^^ ^^ */
6352 if ((s == input_line_pointer
6353 || *(s-1) == ' '
6354 || *(s-1) == '\t')
6355 && ((strncasecmp (s, "AND", 3) == 0
6356 && (s[3] == '.' || ! is_part_of_name (s[3])))
6357 || (strncasecmp (s, "OR", 2) == 0
6358 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6359 break;
6360 }
6361
6362 *rightstart = input_line_pointer;
6363 *rightstop = s;
6364 if (*rightstop > *rightstart
6365 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6366 --*rightstop;
6367
6368 input_line_pointer = s;
6369
6370 return 1;
6371 }
6372
6373 #define MCC(b1, b2) (((b1) << 8) | (b2))
6374
6375 /* Swap the sense of a condition. This changes the condition so that
6376 it generates the same result when the operands are swapped. */
6377
6378 static int
6379 swap_mri_condition (int cc)
6380 {
6381 switch (cc)
6382 {
6383 case MCC ('h', 'i'): return MCC ('c', 's');
6384 case MCC ('l', 's'): return MCC ('c', 'c');
6385 /* <HS> is an alias for <CC>. */
6386 case MCC ('h', 's'):
6387 case MCC ('c', 'c'): return MCC ('l', 's');
6388 /* <LO> is an alias for <CS>. */
6389 case MCC ('l', 'o'):
6390 case MCC ('c', 's'): return MCC ('h', 'i');
6391 case MCC ('p', 'l'): return MCC ('m', 'i');
6392 case MCC ('m', 'i'): return MCC ('p', 'l');
6393 case MCC ('g', 'e'): return MCC ('l', 'e');
6394 case MCC ('l', 't'): return MCC ('g', 't');
6395 case MCC ('g', 't'): return MCC ('l', 't');
6396 case MCC ('l', 'e'): return MCC ('g', 'e');
6397 /* Issue a warning for conditions we can not swap. */
6398 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6399 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
6400 case MCC ('v', 'c'):
6401 case MCC ('v', 's'):
6402 default :
6403 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6404 (char) (cc >> 8), (char) (cc));
6405 break;
6406 }
6407 return cc;
6408 }
6409
6410 /* Reverse the sense of a condition. */
6411
6412 static int
6413 reverse_mri_condition (int cc)
6414 {
6415 switch (cc)
6416 {
6417 case MCC ('h', 'i'): return MCC ('l', 's');
6418 case MCC ('l', 's'): return MCC ('h', 'i');
6419 /* <HS> is an alias for <CC> */
6420 case MCC ('h', 's'): return MCC ('l', 'o');
6421 case MCC ('c', 'c'): return MCC ('c', 's');
6422 /* <LO> is an alias for <CS> */
6423 case MCC ('l', 'o'): return MCC ('h', 's');
6424 case MCC ('c', 's'): return MCC ('c', 'c');
6425 case MCC ('n', 'e'): return MCC ('e', 'q');
6426 case MCC ('e', 'q'): return MCC ('n', 'e');
6427 case MCC ('v', 'c'): return MCC ('v', 's');
6428 case MCC ('v', 's'): return MCC ('v', 'c');
6429 case MCC ('p', 'l'): return MCC ('m', 'i');
6430 case MCC ('m', 'i'): return MCC ('p', 'l');
6431 case MCC ('g', 'e'): return MCC ('l', 't');
6432 case MCC ('l', 't'): return MCC ('g', 'e');
6433 case MCC ('g', 't'): return MCC ('l', 'e');
6434 case MCC ('l', 'e'): return MCC ('g', 't');
6435 }
6436 return cc;
6437 }
6438
6439 /* Build an MRI structured control expression. This generates test
6440 and branch instructions. It goes to TRUELAB if the condition is
6441 true, and to FALSELAB if the condition is false. Exactly one of
6442 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6443 is the size qualifier for the expression. EXTENT is the size to
6444 use for the branch. */
6445
6446 static void
6447 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6448 char *rightstart, char *rightstop,
6449 const char *truelab, const char *falselab,
6450 int extent)
6451 {
6452 char *buf;
6453 char *s;
6454
6455 if (leftstart != NULL)
6456 {
6457 struct m68k_op leftop, rightop;
6458 char c;
6459
6460 /* Swap the compare operands, if necessary, to produce a legal
6461 m68k compare instruction. Comparing a register operand with
6462 a non-register operand requires the register to be on the
6463 right (cmp, cmpa). Comparing an immediate value with
6464 anything requires the immediate value to be on the left
6465 (cmpi). */
6466
6467 c = *leftstop;
6468 *leftstop = '\0';
6469 (void) m68k_ip_op (leftstart, &leftop);
6470 *leftstop = c;
6471
6472 c = *rightstop;
6473 *rightstop = '\0';
6474 (void) m68k_ip_op (rightstart, &rightop);
6475 *rightstop = c;
6476
6477 if (rightop.mode == IMMED
6478 || ((leftop.mode == DREG || leftop.mode == AREG)
6479 && (rightop.mode != DREG && rightop.mode != AREG)))
6480 {
6481 char *temp;
6482
6483 /* Correct conditional handling:
6484 if #1 <lt> d0 then ;means if (1 < d0)
6485 ...
6486 endi
6487
6488 should assemble to:
6489
6490 cmp #1,d0 if we do *not* swap the operands
6491 bgt true we need the swapped condition!
6492 ble false
6493 true:
6494 ...
6495 false:
6496 */
6497 temp = leftstart;
6498 leftstart = rightstart;
6499 rightstart = temp;
6500 temp = leftstop;
6501 leftstop = rightstop;
6502 rightstop = temp;
6503 }
6504 else
6505 {
6506 cc = swap_mri_condition (cc);
6507 }
6508 }
6509
6510 if (truelab == NULL)
6511 {
6512 cc = reverse_mri_condition (cc);
6513 truelab = falselab;
6514 }
6515
6516 if (leftstart != NULL)
6517 {
6518 buf = XNEWVEC (char, (20
6519 + (leftstop - leftstart)
6520 + (rightstop - rightstart)));
6521 s = buf;
6522 *s++ = 'c';
6523 *s++ = 'm';
6524 *s++ = 'p';
6525 if (qual != '\0')
6526 *s++ = TOLOWER (qual);
6527 *s++ = ' ';
6528 memcpy (s, leftstart, leftstop - leftstart);
6529 s += leftstop - leftstart;
6530 *s++ = ',';
6531 memcpy (s, rightstart, rightstop - rightstart);
6532 s += rightstop - rightstart;
6533 *s = '\0';
6534 mri_assemble (buf);
6535 free (buf);
6536 }
6537
6538 buf = XNEWVEC (char, 20 + strlen (truelab));
6539 s = buf;
6540 *s++ = 'b';
6541 *s++ = cc >> 8;
6542 *s++ = cc & 0xff;
6543 if (extent != '\0')
6544 *s++ = TOLOWER (extent);
6545 *s++ = ' ';
6546 strcpy (s, truelab);
6547 mri_assemble (buf);
6548 free (buf);
6549 }
6550
6551 /* Parse an MRI structured control expression. This generates test
6552 and branch instructions. STOP is where the expression ends. It
6553 goes to TRUELAB if the condition is true, and to FALSELAB if the
6554 condition is false. Exactly one of TRUELAB and FALSELAB will be
6555 NULL, meaning to fall through. QUAL is the size qualifier for the
6556 expression. EXTENT is the size to use for the branch. */
6557
6558 static void
6559 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6560 const char *falselab, int extent)
6561 {
6562 int c;
6563 int cc;
6564 char *leftstart;
6565 char *leftstop;
6566 char *rightstart;
6567 char *rightstop;
6568
6569 c = *stop;
6570 *stop = '\0';
6571
6572 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6573 &rightstart, &rightstop))
6574 {
6575 *stop = c;
6576 return;
6577 }
6578
6579 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6580 {
6581 const char *flab;
6582
6583 if (falselab != NULL)
6584 flab = falselab;
6585 else
6586 flab = mri_control_label ();
6587
6588 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6589 rightstop, (const char *) NULL, flab, extent);
6590
6591 input_line_pointer += 3;
6592 if (*input_line_pointer != '.'
6593 || input_line_pointer[1] == '\0')
6594 qual = '\0';
6595 else
6596 {
6597 qual = input_line_pointer[1];
6598 input_line_pointer += 2;
6599 }
6600
6601 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6602 &rightstart, &rightstop))
6603 {
6604 *stop = c;
6605 return;
6606 }
6607
6608 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6609 rightstop, truelab, falselab, extent);
6610
6611 if (falselab == NULL)
6612 colon (flab);
6613 }
6614 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6615 {
6616 const char *tlab;
6617
6618 if (truelab != NULL)
6619 tlab = truelab;
6620 else
6621 tlab = mri_control_label ();
6622
6623 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6624 rightstop, tlab, (const char *) NULL, extent);
6625
6626 input_line_pointer += 2;
6627 if (*input_line_pointer != '.'
6628 || input_line_pointer[1] == '\0')
6629 qual = '\0';
6630 else
6631 {
6632 qual = input_line_pointer[1];
6633 input_line_pointer += 2;
6634 }
6635
6636 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6637 &rightstart, &rightstop))
6638 {
6639 *stop = c;
6640 return;
6641 }
6642
6643 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6644 rightstop, truelab, falselab, extent);
6645
6646 if (truelab == NULL)
6647 colon (tlab);
6648 }
6649 else
6650 {
6651 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6652 rightstop, truelab, falselab, extent);
6653 }
6654
6655 *stop = c;
6656 if (input_line_pointer != stop)
6657 as_bad (_("syntax error in structured control directive"));
6658 }
6659
6660 /* Handle the MRI IF pseudo-op. This may be a structured control
6661 directive, or it may be a regular assembler conditional, depending
6662 on its operands. */
6663
6664 static void
6665 s_mri_if (int qual)
6666 {
6667 char *s;
6668 int c;
6669 struct mri_control_info *n;
6670
6671 /* A structured control directive must end with THEN with an
6672 optional qualifier. */
6673 s = input_line_pointer;
6674 /* We only accept '*' as introduction of comments if preceded by white space
6675 or at first column of a line (I think this can't actually happen here?)
6676 This is important when assembling:
6677 if d0 <ne> 12(a0,d0*2) then
6678 if d0 <ne> #CONST*20 then. */
6679 while (! (is_end_of_line[(unsigned char) *s]
6680 || (flag_mri
6681 && *s == '*'
6682 && (s == input_line_pointer
6683 || *(s-1) == ' '
6684 || *(s-1) == '\t'))))
6685 ++s;
6686 --s;
6687 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6688 --s;
6689
6690 if (s - input_line_pointer > 1
6691 && s[-1] == '.')
6692 s -= 2;
6693
6694 if (s - input_line_pointer < 3
6695 || strncasecmp (s - 3, "THEN", 4) != 0)
6696 {
6697 if (qual != '\0')
6698 {
6699 as_bad (_("missing then"));
6700 ignore_rest_of_line ();
6701 return;
6702 }
6703
6704 /* It's a conditional. */
6705 s_if (O_ne);
6706 return;
6707 }
6708
6709 /* Since this might be a conditional if, this pseudo-op will be
6710 called even if we are supported to be ignoring input. Double
6711 check now. Clobber *input_line_pointer so that ignore_input
6712 thinks that this is not a special pseudo-op. */
6713 c = *input_line_pointer;
6714 *input_line_pointer = 0;
6715 if (ignore_input ())
6716 {
6717 *input_line_pointer = c;
6718 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6719 ++input_line_pointer;
6720 demand_empty_rest_of_line ();
6721 return;
6722 }
6723 *input_line_pointer = c;
6724
6725 n = push_mri_control (mri_if);
6726
6727 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6728 n->next, s[1] == '.' ? s[2] : '\0');
6729
6730 if (s[1] == '.')
6731 input_line_pointer = s + 3;
6732 else
6733 input_line_pointer = s + 1;
6734
6735 if (flag_mri)
6736 {
6737 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6738 ++input_line_pointer;
6739 }
6740
6741 demand_empty_rest_of_line ();
6742 }
6743
6744 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6745 structured IF, associate the ELSE with the IF. Otherwise, assume
6746 it is a conditional else. */
6747
6748 static void
6749 s_mri_else (int qual)
6750 {
6751 int c;
6752 char *buf;
6753 char q[2];
6754
6755 if (qual == '\0'
6756 && (mri_control_stack == NULL
6757 || mri_control_stack->type != mri_if
6758 || mri_control_stack->else_seen))
6759 {
6760 s_else (0);
6761 return;
6762 }
6763
6764 c = *input_line_pointer;
6765 *input_line_pointer = 0;
6766 if (ignore_input ())
6767 {
6768 *input_line_pointer = c;
6769 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6770 ++input_line_pointer;
6771 demand_empty_rest_of_line ();
6772 return;
6773 }
6774 *input_line_pointer = c;
6775
6776 if (mri_control_stack == NULL
6777 || mri_control_stack->type != mri_if
6778 || mri_control_stack->else_seen)
6779 {
6780 as_bad (_("else without matching if"));
6781 ignore_rest_of_line ();
6782 return;
6783 }
6784
6785 mri_control_stack->else_seen = 1;
6786
6787 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->bottom));
6788 q[0] = TOLOWER (qual);
6789 q[1] = '\0';
6790 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6791 mri_assemble (buf);
6792 free (buf);
6793
6794 colon (mri_control_stack->next);
6795
6796 if (flag_mri)
6797 {
6798 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6799 ++input_line_pointer;
6800 }
6801
6802 demand_empty_rest_of_line ();
6803 }
6804
6805 /* Handle the MRI ENDI pseudo-op. */
6806
6807 static void
6808 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6809 {
6810 if (mri_control_stack == NULL
6811 || mri_control_stack->type != mri_if)
6812 {
6813 as_bad (_("endi without matching if"));
6814 ignore_rest_of_line ();
6815 return;
6816 }
6817
6818 /* ignore_input will not return true for ENDI, so we don't need to
6819 worry about checking it again here. */
6820
6821 if (! mri_control_stack->else_seen)
6822 colon (mri_control_stack->next);
6823 colon (mri_control_stack->bottom);
6824
6825 pop_mri_control ();
6826
6827 if (flag_mri)
6828 {
6829 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6830 ++input_line_pointer;
6831 }
6832
6833 demand_empty_rest_of_line ();
6834 }
6835
6836 /* Handle the MRI BREAK pseudo-op. */
6837
6838 static void
6839 s_mri_break (int extent)
6840 {
6841 struct mri_control_info *n;
6842 char *buf;
6843 char ex[2];
6844
6845 n = mri_control_stack;
6846 while (n != NULL
6847 && n->type != mri_for
6848 && n->type != mri_repeat
6849 && n->type != mri_while)
6850 n = n->outer;
6851 if (n == NULL)
6852 {
6853 as_bad (_("break outside of structured loop"));
6854 ignore_rest_of_line ();
6855 return;
6856 }
6857
6858 buf = XNEWVEC (char, 20 + strlen (n->bottom));
6859 ex[0] = TOLOWER (extent);
6860 ex[1] = '\0';
6861 sprintf (buf, "bra%s %s", ex, n->bottom);
6862 mri_assemble (buf);
6863 free (buf);
6864
6865 if (flag_mri)
6866 {
6867 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6868 ++input_line_pointer;
6869 }
6870
6871 demand_empty_rest_of_line ();
6872 }
6873
6874 /* Handle the MRI NEXT pseudo-op. */
6875
6876 static void
6877 s_mri_next (int extent)
6878 {
6879 struct mri_control_info *n;
6880 char *buf;
6881 char ex[2];
6882
6883 n = mri_control_stack;
6884 while (n != NULL
6885 && n->type != mri_for
6886 && n->type != mri_repeat
6887 && n->type != mri_while)
6888 n = n->outer;
6889 if (n == NULL)
6890 {
6891 as_bad (_("next outside of structured loop"));
6892 ignore_rest_of_line ();
6893 return;
6894 }
6895
6896 buf = XNEWVEC (char, 20 + strlen (n->next));
6897 ex[0] = TOLOWER (extent);
6898 ex[1] = '\0';
6899 sprintf (buf, "bra%s %s", ex, n->next);
6900 mri_assemble (buf);
6901 free (buf);
6902
6903 if (flag_mri)
6904 {
6905 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6906 ++input_line_pointer;
6907 }
6908
6909 demand_empty_rest_of_line ();
6910 }
6911
6912 /* Handle the MRI FOR pseudo-op. */
6913
6914 static void
6915 s_mri_for (int qual)
6916 {
6917 const char *varstart, *varstop;
6918 const char *initstart, *initstop;
6919 const char *endstart, *endstop;
6920 const char *bystart, *bystop;
6921 int up;
6922 int by;
6923 int extent;
6924 struct mri_control_info *n;
6925 char *buf;
6926 char *s;
6927 char ex[2];
6928
6929 /* The syntax is
6930 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6931 */
6932
6933 SKIP_WHITESPACE ();
6934 varstart = input_line_pointer;
6935
6936 /* Look for the '='. */
6937 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6938 && *input_line_pointer != '=')
6939 ++input_line_pointer;
6940 if (*input_line_pointer != '=')
6941 {
6942 as_bad (_("missing ="));
6943 ignore_rest_of_line ();
6944 return;
6945 }
6946
6947 varstop = input_line_pointer;
6948 if (varstop > varstart
6949 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6950 --varstop;
6951
6952 ++input_line_pointer;
6953
6954 initstart = input_line_pointer;
6955
6956 /* Look for TO or DOWNTO. */
6957 up = 1;
6958 initstop = NULL;
6959 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6960 {
6961 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6962 && ! is_part_of_name (input_line_pointer[2]))
6963 {
6964 initstop = input_line_pointer;
6965 input_line_pointer += 2;
6966 break;
6967 }
6968 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6969 && ! is_part_of_name (input_line_pointer[6]))
6970 {
6971 initstop = input_line_pointer;
6972 up = 0;
6973 input_line_pointer += 6;
6974 break;
6975 }
6976 ++input_line_pointer;
6977 }
6978 if (initstop == NULL)
6979 {
6980 as_bad (_("missing to or downto"));
6981 ignore_rest_of_line ();
6982 return;
6983 }
6984 if (initstop > initstart
6985 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6986 --initstop;
6987
6988 SKIP_WHITESPACE ();
6989 endstart = input_line_pointer;
6990
6991 /* Look for BY or DO. */
6992 by = 0;
6993 endstop = NULL;
6994 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6995 {
6996 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6997 && ! is_part_of_name (input_line_pointer[2]))
6998 {
6999 endstop = input_line_pointer;
7000 by = 1;
7001 input_line_pointer += 2;
7002 break;
7003 }
7004 if (strncasecmp (input_line_pointer, "DO", 2) == 0
7005 && (input_line_pointer[2] == '.'
7006 || ! is_part_of_name (input_line_pointer[2])))
7007 {
7008 endstop = input_line_pointer;
7009 input_line_pointer += 2;
7010 break;
7011 }
7012 ++input_line_pointer;
7013 }
7014 if (endstop == NULL)
7015 {
7016 as_bad (_("missing do"));
7017 ignore_rest_of_line ();
7018 return;
7019 }
7020 if (endstop > endstart
7021 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
7022 --endstop;
7023
7024 if (! by)
7025 {
7026 bystart = "#1";
7027 bystop = bystart + 2;
7028 }
7029 else
7030 {
7031 SKIP_WHITESPACE ();
7032 bystart = input_line_pointer;
7033
7034 /* Look for DO. */
7035 bystop = NULL;
7036 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7037 {
7038 if (strncasecmp (input_line_pointer, "DO", 2) == 0
7039 && (input_line_pointer[2] == '.'
7040 || ! is_part_of_name (input_line_pointer[2])))
7041 {
7042 bystop = input_line_pointer;
7043 input_line_pointer += 2;
7044 break;
7045 }
7046 ++input_line_pointer;
7047 }
7048 if (bystop == NULL)
7049 {
7050 as_bad (_("missing do"));
7051 ignore_rest_of_line ();
7052 return;
7053 }
7054 if (bystop > bystart
7055 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
7056 --bystop;
7057 }
7058
7059 if (*input_line_pointer != '.')
7060 extent = '\0';
7061 else
7062 {
7063 extent = input_line_pointer[1];
7064 input_line_pointer += 2;
7065 }
7066
7067 /* We have fully parsed the FOR operands. Now build the loop. */
7068 n = push_mri_control (mri_for);
7069
7070 buf = XNEWVEC (char, 50 + (input_line_pointer - varstart));
7071
7072 /* Move init,var. */
7073 s = buf;
7074 *s++ = 'm';
7075 *s++ = 'o';
7076 *s++ = 'v';
7077 *s++ = 'e';
7078 if (qual != '\0')
7079 *s++ = TOLOWER (qual);
7080 *s++ = ' ';
7081 memcpy (s, initstart, initstop - initstart);
7082 s += initstop - initstart;
7083 *s++ = ',';
7084 memcpy (s, varstart, varstop - varstart);
7085 s += varstop - varstart;
7086 *s = '\0';
7087 mri_assemble (buf);
7088
7089 colon (n->top);
7090
7091 /* cmp end,var. */
7092 s = buf;
7093 *s++ = 'c';
7094 *s++ = 'm';
7095 *s++ = 'p';
7096 if (qual != '\0')
7097 *s++ = TOLOWER (qual);
7098 *s++ = ' ';
7099 memcpy (s, endstart, endstop - endstart);
7100 s += endstop - endstart;
7101 *s++ = ',';
7102 memcpy (s, varstart, varstop - varstart);
7103 s += varstop - varstart;
7104 *s = '\0';
7105 mri_assemble (buf);
7106
7107 /* bcc bottom. */
7108 ex[0] = TOLOWER (extent);
7109 ex[1] = '\0';
7110 if (up)
7111 sprintf (buf, "blt%s %s", ex, n->bottom);
7112 else
7113 sprintf (buf, "bgt%s %s", ex, n->bottom);
7114 mri_assemble (buf);
7115
7116 /* Put together the add or sub instruction used by ENDF. */
7117 s = buf;
7118 if (up)
7119 strcpy (s, "add");
7120 else
7121 strcpy (s, "sub");
7122 s += 3;
7123 if (qual != '\0')
7124 *s++ = TOLOWER (qual);
7125 *s++ = ' ';
7126 memcpy (s, bystart, bystop - bystart);
7127 s += bystop - bystart;
7128 *s++ = ',';
7129 memcpy (s, varstart, varstop - varstart);
7130 s += varstop - varstart;
7131 *s = '\0';
7132 n->incr = buf;
7133
7134 if (flag_mri)
7135 {
7136 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7137 ++input_line_pointer;
7138 }
7139
7140 demand_empty_rest_of_line ();
7141 }
7142
7143 /* Handle the MRI ENDF pseudo-op. */
7144
7145 static void
7146 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
7147 {
7148 if (mri_control_stack == NULL
7149 || mri_control_stack->type != mri_for)
7150 {
7151 as_bad (_("endf without for"));
7152 ignore_rest_of_line ();
7153 return;
7154 }
7155
7156 colon (mri_control_stack->next);
7157
7158 mri_assemble (mri_control_stack->incr);
7159
7160 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
7161 mri_assemble (mri_control_stack->incr);
7162
7163 free (mri_control_stack->incr);
7164
7165 colon (mri_control_stack->bottom);
7166
7167 pop_mri_control ();
7168
7169 if (flag_mri)
7170 {
7171 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7172 ++input_line_pointer;
7173 }
7174
7175 demand_empty_rest_of_line ();
7176 }
7177
7178 /* Handle the MRI REPEAT pseudo-op. */
7179
7180 static void
7181 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
7182 {
7183 struct mri_control_info *n;
7184
7185 n = push_mri_control (mri_repeat);
7186 colon (n->top);
7187 if (flag_mri)
7188 {
7189 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7190 ++input_line_pointer;
7191 }
7192 demand_empty_rest_of_line ();
7193 }
7194
7195 /* Handle the MRI UNTIL pseudo-op. */
7196
7197 static void
7198 s_mri_until (int qual)
7199 {
7200 char *s;
7201
7202 if (mri_control_stack == NULL
7203 || mri_control_stack->type != mri_repeat)
7204 {
7205 as_bad (_("until without repeat"));
7206 ignore_rest_of_line ();
7207 return;
7208 }
7209
7210 colon (mri_control_stack->next);
7211
7212 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7213 ;
7214
7215 parse_mri_control_expression (s, qual, (const char *) NULL,
7216 mri_control_stack->top, '\0');
7217
7218 colon (mri_control_stack->bottom);
7219
7220 input_line_pointer = s;
7221
7222 pop_mri_control ();
7223
7224 if (flag_mri)
7225 {
7226 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7227 ++input_line_pointer;
7228 }
7229
7230 demand_empty_rest_of_line ();
7231 }
7232
7233 /* Handle the MRI WHILE pseudo-op. */
7234
7235 static void
7236 s_mri_while (int qual)
7237 {
7238 char *s;
7239
7240 struct mri_control_info *n;
7241
7242 s = input_line_pointer;
7243 /* We only accept '*' as introduction of comments if preceded by white space
7244 or at first column of a line (I think this can't actually happen here?)
7245 This is important when assembling:
7246 while d0 <ne> 12(a0,d0*2) do
7247 while d0 <ne> #CONST*20 do. */
7248 while (! (is_end_of_line[(unsigned char) *s]
7249 || (flag_mri
7250 && *s == '*'
7251 && (s == input_line_pointer
7252 || *(s-1) == ' '
7253 || *(s-1) == '\t'))))
7254 s++;
7255 --s;
7256 while (*s == ' ' || *s == '\t')
7257 --s;
7258 if (s - input_line_pointer > 1
7259 && s[-1] == '.')
7260 s -= 2;
7261 if (s - input_line_pointer < 2
7262 || strncasecmp (s - 1, "DO", 2) != 0)
7263 {
7264 as_bad (_("missing do"));
7265 ignore_rest_of_line ();
7266 return;
7267 }
7268
7269 n = push_mri_control (mri_while);
7270
7271 colon (n->next);
7272
7273 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7274 s[1] == '.' ? s[2] : '\0');
7275
7276 input_line_pointer = s + 1;
7277 if (*input_line_pointer == '.')
7278 input_line_pointer += 2;
7279
7280 if (flag_mri)
7281 {
7282 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7283 ++input_line_pointer;
7284 }
7285
7286 demand_empty_rest_of_line ();
7287 }
7288
7289 /* Handle the MRI ENDW pseudo-op. */
7290
7291 static void
7292 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7293 {
7294 char *buf;
7295
7296 if (mri_control_stack == NULL
7297 || mri_control_stack->type != mri_while)
7298 {
7299 as_bad (_("endw without while"));
7300 ignore_rest_of_line ();
7301 return;
7302 }
7303
7304 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->next));
7305 sprintf (buf, "bra %s", mri_control_stack->next);
7306 mri_assemble (buf);
7307 free (buf);
7308
7309 colon (mri_control_stack->bottom);
7310
7311 pop_mri_control ();
7312
7313 if (flag_mri)
7314 {
7315 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7316 ++input_line_pointer;
7317 }
7318
7319 demand_empty_rest_of_line ();
7320 }
7321 \f
7322 /* Parse a .cpu directive. */
7323
7324 static void
7325 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7326 {
7327 char saved_char;
7328 char *name;
7329
7330 if (initialized)
7331 {
7332 as_bad (_("already assembled instructions"));
7333 ignore_rest_of_line ();
7334 return;
7335 }
7336
7337 name = input_line_pointer;
7338 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7339 input_line_pointer++;
7340 saved_char = *input_line_pointer;
7341 *input_line_pointer = 0;
7342
7343 m68k_set_cpu (name, 1, 0);
7344
7345 *input_line_pointer = saved_char;
7346 demand_empty_rest_of_line ();
7347 return;
7348 }
7349
7350 /* Parse a .arch directive. */
7351
7352 static void
7353 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7354 {
7355 char saved_char;
7356 char *name;
7357
7358 if (initialized)
7359 {
7360 as_bad (_("already assembled instructions"));
7361 ignore_rest_of_line ();
7362 return;
7363 }
7364
7365 name = input_line_pointer;
7366 while (*input_line_pointer && *input_line_pointer != ','
7367 && !ISSPACE (*input_line_pointer))
7368 input_line_pointer++;
7369 saved_char = *input_line_pointer;
7370 *input_line_pointer = 0;
7371
7372 if (m68k_set_arch (name, 1, 0))
7373 {
7374 /* Scan extensions. */
7375 do
7376 {
7377 *input_line_pointer++ = saved_char;
7378 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7379 break;
7380 name = input_line_pointer;
7381 while (*input_line_pointer && *input_line_pointer != ','
7382 && !ISSPACE (*input_line_pointer))
7383 input_line_pointer++;
7384 saved_char = *input_line_pointer;
7385 *input_line_pointer = 0;
7386 }
7387 while (m68k_set_extension (name, 1, 0));
7388 }
7389
7390 *input_line_pointer = saved_char;
7391 demand_empty_rest_of_line ();
7392 return;
7393 }
7394 \f
7395 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7396 if none is found, the caller is responsible for emitting an error
7397 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7398 cpu name, if it begins with a '6' (possibly skipping an intervening
7399 'c'. We also allow a 'c' in the same place. if NEGATED is
7400 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7401 the option is indeed negated. */
7402
7403 static const struct m68k_cpu *
7404 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7405 int allow_m, int *negated)
7406 {
7407 /* allow negated value? */
7408 if (negated)
7409 {
7410 *negated = 0;
7411
7412 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7413 {
7414 arg += 3;
7415 *negated = 1;
7416 }
7417 }
7418
7419 /* Remove 'm' or 'mc' prefix from 68k variants. */
7420 if (allow_m)
7421 {
7422 if (arg[0] == 'm')
7423 {
7424 if (arg[1] == '6')
7425 arg += 1;
7426 else if (arg[1] == 'c' && arg[2] == '6')
7427 arg += 2;
7428 }
7429 }
7430 else if (arg[0] == 'c' && arg[1] == '6')
7431 arg += 1;
7432
7433 for (; table->name; table++)
7434 if (!strcmp (arg, table->name))
7435 {
7436 if (table->alias < -1 || table->alias > 1)
7437 as_bad (_("`%s' is deprecated, use `%s'"),
7438 table->name, table[table->alias < 0 ? 1 : -1].name);
7439 return table;
7440 }
7441 return 0;
7442 }
7443
7444 /* Set the cpu, issuing errors if it is unrecognized. */
7445
7446 static int
7447 m68k_set_cpu (char const *name, int allow_m, int silent)
7448 {
7449 const struct m68k_cpu *cpu;
7450
7451 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7452
7453 if (!cpu)
7454 {
7455 if (!silent)
7456 as_bad (_("cpu `%s' unrecognized"), name);
7457 return 0;
7458 }
7459 selected_cpu = cpu;
7460 return 1;
7461 }
7462
7463 /* Set the architecture, issuing errors if it is unrecognized. */
7464
7465 static int
7466 m68k_set_arch (char const *name, int allow_m, int silent)
7467 {
7468 const struct m68k_cpu *arch;
7469
7470 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7471
7472 if (!arch)
7473 {
7474 if (!silent)
7475 as_bad (_("architecture `%s' unrecognized"), name);
7476 return 0;
7477 }
7478 selected_arch = arch;
7479 return 1;
7480 }
7481
7482 /* Set the architecture extension, issuing errors if it is
7483 unrecognized, or invalid */
7484
7485 static int
7486 m68k_set_extension (char const *name, int allow_m, int silent)
7487 {
7488 int negated;
7489 const struct m68k_cpu *ext;
7490
7491 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7492
7493 if (!ext)
7494 {
7495 if (!silent)
7496 as_bad (_("extension `%s' unrecognized"), name);
7497 return 0;
7498 }
7499
7500 if (negated)
7501 not_current_architecture |= (ext->control_regs
7502 ? *(unsigned *)ext->control_regs: ext->arch);
7503 else
7504 current_architecture |= ext->arch;
7505 return 1;
7506 }
7507
7508 /* md_parse_option
7509 Invocation line includes a switch not recognized by the base assembler.
7510 */
7511
7512 #ifdef OBJ_ELF
7513 const char *md_shortopts = "lSA:m:kQ:V";
7514 #else
7515 const char *md_shortopts = "lSA:m:k";
7516 #endif
7517
7518 struct option md_longopts[] = {
7519 #define OPTION_PIC (OPTION_MD_BASE)
7520 {"pic", no_argument, NULL, OPTION_PIC},
7521 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7522 {"register-prefix-optional", no_argument, NULL,
7523 OPTION_REGISTER_PREFIX_OPTIONAL},
7524 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7525 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7526 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7527 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7528 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7529 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7530 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7531 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7532 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7533 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7534 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7535 {"pcrel", no_argument, NULL, OPTION_PCREL},
7536 {NULL, no_argument, NULL, 0}
7537 };
7538 size_t md_longopts_size = sizeof (md_longopts);
7539
7540 int
7541 md_parse_option (int c, const char *arg)
7542 {
7543 switch (c)
7544 {
7545 case 'l': /* -l means keep external to 2 bit offset
7546 rather than 16 bit one. */
7547 flag_short_refs = 1;
7548 break;
7549
7550 case 'S': /* -S means that jbsr's always turn into
7551 jsr's. */
7552 flag_long_jumps = 1;
7553 break;
7554
7555 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7556 branches into absolute jumps. */
7557 flag_keep_pcrel = 1;
7558 break;
7559
7560 case OPTION_PIC:
7561 case 'k':
7562 flag_want_pic = 1;
7563 break; /* -pic, Position Independent Code. */
7564
7565 case OPTION_REGISTER_PREFIX_OPTIONAL:
7566 flag_reg_prefix_optional = 1;
7567 reg_prefix_optional_seen = 1;
7568 break;
7569
7570 /* -V: SVR4 argument to print version ID. */
7571 case 'V':
7572 print_version_id ();
7573 break;
7574
7575 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7576 should be emitted or not. FIXME: Not implemented. */
7577 case 'Q':
7578 break;
7579
7580 case OPTION_BITWISE_OR:
7581 {
7582 char *n, *t;
7583 const char *s;
7584
7585 n = XNEWVEC (char, strlen (m68k_comment_chars) + 1);
7586 t = n;
7587 for (s = m68k_comment_chars; *s != '\0'; s++)
7588 if (*s != '|')
7589 *t++ = *s;
7590 *t = '\0';
7591 m68k_comment_chars = n;
7592 }
7593 break;
7594
7595 case OPTION_BASE_SIZE_DEFAULT_16:
7596 m68k_index_width_default = SIZE_WORD;
7597 break;
7598
7599 case OPTION_BASE_SIZE_DEFAULT_32:
7600 m68k_index_width_default = SIZE_LONG;
7601 break;
7602
7603 case OPTION_DISP_SIZE_DEFAULT_16:
7604 m68k_rel32 = 0;
7605 m68k_rel32_from_cmdline = 1;
7606 break;
7607
7608 case OPTION_DISP_SIZE_DEFAULT_32:
7609 m68k_rel32 = 1;
7610 m68k_rel32_from_cmdline = 1;
7611 break;
7612
7613 case 'A':
7614 #if WARN_DEPRECATED
7615 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7616 arg, arg));
7617 #endif
7618 /* Intentional fall-through. */
7619 case 'm':
7620 if (!strncmp (arg, "arch=", 5))
7621 m68k_set_arch (arg + 5, 1, 0);
7622 else if (!strncmp (arg, "cpu=", 4))
7623 m68k_set_cpu (arg + 4, 1, 0);
7624 else if (m68k_set_extension (arg, 0, 1))
7625 ;
7626 else if (m68k_set_arch (arg, 0, 1))
7627 ;
7628 else if (m68k_set_cpu (arg, 0, 1))
7629 ;
7630 else
7631 return 0;
7632 break;
7633
7634 default:
7635 return 0;
7636 }
7637
7638 return 1;
7639 }
7640
7641 /* Setup tables from the selected arch and/or cpu */
7642
7643 static void
7644 m68k_init_arch (void)
7645 {
7646 if (not_current_architecture & current_architecture)
7647 {
7648 as_bad (_("architecture features both enabled and disabled"));
7649 not_current_architecture &= ~current_architecture;
7650 }
7651 if (selected_arch)
7652 {
7653 current_architecture |= selected_arch->arch;
7654 control_regs = selected_arch->control_regs;
7655 }
7656 else
7657 current_architecture |= selected_cpu->arch;
7658
7659 current_architecture &= ~not_current_architecture;
7660
7661 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7662 {
7663 /* Determine which float is really meant. */
7664 if (current_architecture & (m68k_mask & ~m68881))
7665 current_architecture ^= cfloat;
7666 else
7667 current_architecture ^= m68881;
7668 }
7669
7670 if (selected_cpu)
7671 {
7672 control_regs = selected_cpu->control_regs;
7673 if (current_architecture & ~selected_cpu->arch)
7674 {
7675 as_bad (_("selected processor does not have all features of selected architecture"));
7676 current_architecture
7677 = selected_cpu->arch & ~not_current_architecture;
7678 }
7679 }
7680
7681 if ((current_architecture & m68k_mask)
7682 && (current_architecture & ~m68k_mask))
7683 {
7684 as_bad (_ ("m68k and cf features both selected"));
7685 if (current_architecture & m68k_mask)
7686 current_architecture &= m68k_mask;
7687 else
7688 current_architecture &= ~m68k_mask;
7689 }
7690
7691 /* Permit m68881 specification with all cpus; those that can't work
7692 with a coprocessor could be doing emulation. */
7693 if (current_architecture & m68851)
7694 {
7695 if (current_architecture & m68040)
7696 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7697 }
7698 /* What other incompatibilities could we check for? */
7699
7700 if (cpu_of_arch (current_architecture) < m68020
7701 || arch_coldfire_p (current_architecture))
7702 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7703
7704 initialized = 1;
7705 }
7706
7707 void
7708 md_show_usage (FILE *stream)
7709 {
7710 const char *default_cpu = TARGET_CPU;
7711 int i;
7712
7713 /* Get the canonical name for the default target CPU. */
7714 if (*default_cpu == 'm')
7715 default_cpu++;
7716 for (i = 0; m68k_cpus[i].name; i++)
7717 {
7718 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7719 {
7720 while (m68k_cpus[i].alias > 0)
7721 i--;
7722 while (m68k_cpus[i].alias < 0)
7723 i++;
7724 default_cpu = m68k_cpus[i].name;
7725 }
7726 }
7727
7728 fprintf (stream, _("\
7729 -march=<arch> set architecture\n\
7730 -mcpu=<cpu> set cpu [default %s]\n\
7731 "), default_cpu);
7732 for (i = 0; m68k_extensions[i].name; i++)
7733 fprintf (stream, _("\
7734 -m[no-]%-16s enable/disable %s architecture extension\n\
7735 "), m68k_extensions[i].name,
7736 m68k_extensions[i].alias > 0 ? " ColdFire"
7737 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7738
7739 fprintf (stream, _("\
7740 -l use 1 word for refs to undefined symbols [default 2]\n\
7741 -pic, -k generate position independent code\n\
7742 -S turn jbsr into jsr\n\
7743 --pcrel never turn PC-relative branches into absolute jumps\n\
7744 --register-prefix-optional\n\
7745 recognize register names without prefix character\n\
7746 --bitwise-or do not treat `|' as a comment character\n\
7747 --base-size-default-16 base reg without size is 16 bits\n\
7748 --base-size-default-32 base reg without size is 32 bits (default)\n\
7749 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7750 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7751 "));
7752
7753 fprintf (stream, _("Architecture variants are: "));
7754 for (i = 0; m68k_archs[i].name; i++)
7755 {
7756 if (i)
7757 fprintf (stream, " | ");
7758 fprintf (stream, "%s", m68k_archs[i].name);
7759 }
7760 fprintf (stream, "\n");
7761
7762 fprintf (stream, _("Processor variants are: "));
7763 for (i = 0; m68k_cpus[i].name; i++)
7764 {
7765 if (i)
7766 fprintf (stream, " | ");
7767 fprintf (stream, "%s", m68k_cpus[i].name);
7768 }
7769 fprintf (stream, _("\n"));
7770 }
7771 \f
7772 #ifdef TEST2
7773
7774 /* TEST2: Test md_assemble() */
7775 /* Warning, this routine probably doesn't work anymore. */
7776 int
7777 main (void)
7778 {
7779 struct m68k_it the_ins;
7780 char buf[120];
7781 char *cp;
7782 int n;
7783
7784 m68k_ip_begin ();
7785 for (;;)
7786 {
7787 if (!gets (buf) || !*buf)
7788 break;
7789 if (buf[0] == '|' || buf[1] == '.')
7790 continue;
7791 for (cp = buf; *cp; cp++)
7792 if (*cp == '\t')
7793 *cp = ' ';
7794 if (is_label (buf))
7795 continue;
7796 memset (&the_ins, '\0', sizeof (the_ins));
7797 m68k_ip (&the_ins, buf);
7798 if (the_ins.error)
7799 {
7800 printf (_("Error %s in %s\n"), the_ins.error, buf);
7801 }
7802 else
7803 {
7804 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7805 for (n = 0; n < the_ins.numo; n++)
7806 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7807 printf (" ");
7808 print_the_insn (&the_ins.opcode[0], stdout);
7809 (void) putchar ('\n');
7810 }
7811 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7812 {
7813 if (the_ins.operands[n].error)
7814 {
7815 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7816 continue;
7817 }
7818 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7819 the_ins.operands[n].reg);
7820 if (the_ins.operands[n].b_const)
7821 printf ("Constant: '%.*s', ",
7822 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7823 the_ins.operands[n].b_const);
7824 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7825 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7826 if (the_ins.operands[n].b_iadd)
7827 printf ("Iadd: '%.*s',",
7828 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7829 the_ins.operands[n].b_iadd);
7830 putchar ('\n');
7831 }
7832 }
7833 m68k_ip_end ();
7834 return 0;
7835 }
7836
7837 int
7838 is_label (char *str)
7839 {
7840 while (*str == ' ')
7841 str++;
7842 while (*str && *str != ' ')
7843 str++;
7844 if (str[-1] == ':' || str[1] == '=')
7845 return 1;
7846 return 0;
7847 }
7848
7849 #endif
7850
7851 /* Possible states for relaxation:
7852
7853 0 0 branch offset byte (bra, etc)
7854 0 1 word
7855 0 2 long
7856
7857 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7858 1 1 word
7859 1 2 long
7860
7861 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7862 2 1 word-long
7863 2 2 long-word
7864 2 3 long-long
7865
7866 */
7867
7868 /* We have no need to default values of symbols. */
7869
7870 symbolS *
7871 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7872 {
7873 return 0;
7874 }
7875
7876 /* Round up a section size to the appropriate boundary. */
7877 valueT
7878 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7879 {
7880 #ifdef OBJ_AOUT
7881 /* For a.out, force the section size to be aligned. If we don't do
7882 this, BFD will align it for us, but it will not write out the
7883 final bytes of the section. This may be a bug in BFD, but it is
7884 easier to fix it here since that is how the other a.out targets
7885 work. */
7886 int align;
7887
7888 align = bfd_get_section_alignment (stdoutput, segment);
7889 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
7890 #endif
7891
7892 return size;
7893 }
7894
7895 /* Exactly what point is a PC-relative offset relative TO?
7896 On the 68k, it is relative to the address of the first extension
7897 word. The difference between the addresses of the offset and the
7898 first extension word is stored in fx_pcrel_adjust. */
7899 long
7900 md_pcrel_from (fixS *fixP)
7901 {
7902 int adjust;
7903
7904 adjust = fixP->fx_pcrel_adjust;
7905 if (adjust == 64)
7906 adjust = -1;
7907 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7908 }
7909
7910 #ifdef OBJ_ELF
7911 void
7912 m68k_elf_final_processing (void)
7913 {
7914 unsigned flags = 0;
7915
7916 if (arch_coldfire_fpu (current_architecture))
7917 flags |= EF_M68K_CFV4E;
7918 /* Set file-specific flags if this is a cpu32 processor. */
7919 if (cpu_of_arch (current_architecture) & cpu32)
7920 flags |= EF_M68K_CPU32;
7921 else if (cpu_of_arch (current_architecture) & fido_a)
7922 flags |= EF_M68K_FIDO;
7923 else if ((cpu_of_arch (current_architecture) & m68000up)
7924 && !(cpu_of_arch (current_architecture) & m68020up))
7925 flags |= EF_M68K_M68000;
7926
7927 if (current_architecture & mcfisa_a)
7928 {
7929 static const unsigned isa_features[][2] =
7930 {
7931 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7932 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7933 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7934 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7935 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7936 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7937 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
7938 {0,0},
7939 };
7940 static const unsigned mac_features[][2] =
7941 {
7942 {EF_M68K_CF_MAC, mcfmac},
7943 {EF_M68K_CF_EMAC, mcfemac},
7944 {0,0},
7945 };
7946 unsigned ix;
7947 unsigned pattern;
7948
7949 pattern = (current_architecture
7950 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7951 for (ix = 0; isa_features[ix][1]; ix++)
7952 {
7953 if (pattern == isa_features[ix][1])
7954 {
7955 flags |= isa_features[ix][0];
7956 break;
7957 }
7958 }
7959 if (!isa_features[ix][1])
7960 {
7961 cf_bad:
7962 as_warn (_("Not a defined coldfire architecture"));
7963 }
7964 else
7965 {
7966 if (current_architecture & cfloat)
7967 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7968
7969 pattern = current_architecture & (mcfmac|mcfemac);
7970 if (pattern)
7971 {
7972 for (ix = 0; mac_features[ix][1]; ix++)
7973 {
7974 if (pattern == mac_features[ix][1])
7975 {
7976 flags |= mac_features[ix][0];
7977 break;
7978 }
7979 }
7980 if (!mac_features[ix][1])
7981 goto cf_bad;
7982 }
7983 }
7984 }
7985 elf_elfheader (stdoutput)->e_flags |= flags;
7986 }
7987
7988 /* Parse @TLSLDO and return the desired relocation. */
7989 static bfd_reloc_code_real_type
7990 m68k_elf_suffix (char **str_p, expressionS *exp_p)
7991 {
7992 char ident[20];
7993 char *str = *str_p;
7994 char *str2;
7995 int ch;
7996 int len;
7997
7998 if (*str++ != '@')
7999 return BFD_RELOC_UNUSED;
8000
8001 for (ch = *str, str2 = ident;
8002 (str2 < ident + sizeof (ident) - 1
8003 && (ISALNUM (ch) || ch == '@'));
8004 ch = *++str)
8005 {
8006 *str2++ = ch;
8007 }
8008
8009 *str2 = '\0';
8010 len = str2 - ident;
8011
8012 if (strncmp (ident, "TLSLDO", 6) == 0
8013 && len == 6)
8014 {
8015 /* Now check for identifier@suffix+constant. */
8016 if (*str == '-' || *str == '+')
8017 {
8018 char *orig_line = input_line_pointer;
8019 expressionS new_exp;
8020
8021 input_line_pointer = str;
8022 expression (&new_exp);
8023 if (new_exp.X_op == O_constant)
8024 {
8025 exp_p->X_add_number += new_exp.X_add_number;
8026 str = input_line_pointer;
8027 }
8028
8029 if (&input_line_pointer != str_p)
8030 input_line_pointer = orig_line;
8031 }
8032 *str_p = str;
8033
8034 return BFD_RELOC_68K_TLS_LDO32;
8035 }
8036
8037 return BFD_RELOC_UNUSED;
8038 }
8039
8040 /* Handles .long <tls_symbol>+0x8000 debug info.
8041 Clobbers input_line_pointer, checks end-of-line.
8042 Adapted from tc-ppc.c:ppc_elf_cons. */
8043 static void
8044 m68k_elf_cons (int nbytes /* 4=.long */)
8045 {
8046 if (is_it_end_of_statement ())
8047 {
8048 demand_empty_rest_of_line ();
8049 return;
8050 }
8051
8052 do
8053 {
8054 expressionS exp;
8055 bfd_reloc_code_real_type reloc;
8056
8057 expression (&exp);
8058 if (exp.X_op == O_symbol
8059 && *input_line_pointer == '@'
8060 && (reloc = m68k_elf_suffix (&input_line_pointer,
8061 &exp)) != BFD_RELOC_UNUSED)
8062 {
8063 reloc_howto_type *reloc_howto;
8064 int size;
8065
8066 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
8067 size = bfd_get_reloc_size (reloc_howto);
8068
8069 if (size > nbytes)
8070 {
8071 as_bad (_("%s relocations do not fit in %d bytes\n"),
8072 reloc_howto->name, nbytes);
8073 }
8074 else
8075 {
8076 char *p;
8077 int offset;
8078
8079 p = frag_more (nbytes);
8080 offset = 0;
8081 if (target_big_endian)
8082 offset = nbytes - size;
8083 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
8084 &exp, 0, reloc);
8085 }
8086 }
8087 else
8088 emit_expr (&exp, (unsigned int) nbytes);
8089 }
8090 while (*input_line_pointer++ == ',');
8091
8092 /* Put terminator back into stream. */
8093 input_line_pointer--;
8094 demand_empty_rest_of_line ();
8095 }
8096 #endif
8097
8098 int
8099 tc_m68k_regname_to_dw2regnum (const char *regname)
8100 {
8101 unsigned int regnum;
8102 static const char *const regnames[] =
8103 {
8104 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
8105 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
8106 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
8107 "pc"
8108 };
8109
8110 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
8111 if (strcmp (regname, regnames[regnum]) == 0)
8112 return regnum;
8113
8114 return -1;
8115 }
8116
8117 void
8118 tc_m68k_frame_initial_instructions (void)
8119 {
8120 static int sp_regno = -1;
8121
8122 if (sp_regno < 0)
8123 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
8124
8125 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
8126 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
8127 }
8128
8129 /* Check and emit error if broken-word handling has failed to fix up a
8130 case-table. This is called from write.c, after doing everything it
8131 knows about how to handle broken words. */
8132
8133 void
8134 tc_m68k_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP)
8135 {
8136 if (new_offset > 32767 || new_offset < -32768)
8137 as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line,
8138 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."),
8139 (long) new_offset);
8140 }
8141
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