1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars
= "|#";
47 const char *m68k_comment_chars
= "|";
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars
[] = "#*";
59 const char line_separator_chars
[] = ";";
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS
[] = "eE";
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
67 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
79 static int flag_short_refs
; /* -l option. */
80 static int flag_long_jumps
; /* -S option. */
81 static int flag_keep_pcrel
; /* --pcrel option. */
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
86 int flag_reg_prefix_optional
;
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen
;
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum
= COP1
;
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd
;
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick
= 1;
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
106 static int m68k_rel32
= 1;
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline
;
111 /* The default width to use for an index register when using a base
113 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
120 struct label_line
*next
;
127 /* The list of labels. */
129 static struct label_line
*labels
;
131 /* The current label. */
133 static struct label_line
*current_label
;
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode
const ** m68k_sorted_opcodes
;
138 /* Its an arbitrary name: This means I don't approve of it.
140 static struct obstack robyn
;
144 const char *m_operands
;
145 unsigned long m_opcode
;
149 struct m68k_incant
*m_next
;
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
155 static const enum m68k_register m68000_ctrl
[] = { 0 };
156 static const enum m68k_register m68010_ctrl
[] = {
160 static const enum m68k_register m68020_ctrl
[] = {
161 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
164 static const enum m68k_register m68040_ctrl
[] = {
165 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
166 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
169 static const enum m68k_register m68060_ctrl
[] = {
170 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
171 USP
, VBR
, URP
, SRP
, PCR
,
174 static const enum m68k_register mcf_ctrl
[] = {
175 CACR
, TC
, ACR0
, ACR1
, ACR2
, ACR3
, VBR
, ROMBAR
,
176 RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
,
179 static const enum m68k_register mcf5206_ctrl
[] = {
180 CACR
, ACR0
, ACR1
, VBR
, RAMBAR0
, RAMBAR_ALT
, MBAR
,
183 static const enum m68k_register mcf5208_ctrl
[] = {
184 CACR
, ACR0
, ACR1
, VBR
, RAMBAR
, RAMBAR1
,
187 static const enum m68k_register mcf5210a_ctrl
[] = {
188 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR
, RAMBAR1
, MBAR
,
191 static const enum m68k_register mcf5213_ctrl
[] = {
192 VBR
, RAMBAR
, RAMBAR1
, FLASHBAR
,
195 static const enum m68k_register mcf5216_ctrl
[] = {
196 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
199 static const enum m68k_register mcf52223_ctrl
[] = {
200 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
203 static const enum m68k_register mcf52235_ctrl
[] = {
204 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
207 static const enum m68k_register mcf5225_ctrl
[] = {
208 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, MBAR
, RAMBAR1
,
211 static const enum m68k_register mcf5235_ctrl
[] = {
212 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
215 static const enum m68k_register mcf5249_ctrl
[] = {
216 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
, MBAR2
,
219 static const enum m68k_register mcf5250_ctrl
[] = {
223 static const enum m68k_register mcf5253_ctrl
[] = {
224 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, MBAR
,
227 static const enum m68k_register mcf5271_ctrl
[] = {
228 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
231 static const enum m68k_register mcf5272_ctrl
[] = {
232 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR_ALT
, RAMBAR0
, MBAR
,
235 static const enum m68k_register mcf5275_ctrl
[] = {
236 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
239 static const enum m68k_register mcf5282_ctrl
[] = {
240 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
243 static const enum m68k_register mcf5307_ctrl
[] = {
244 CACR
, ACR0
, ACR1
, VBR
, RAMBAR0
, RAMBAR_ALT
, MBAR
,
247 static const enum m68k_register mcf5329_ctrl
[] = {
248 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
251 static const enum m68k_register mcf5373_ctrl
[] = {
252 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
255 static const enum m68k_register mcfv4e_ctrl
[] = {
256 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
257 VBR
, PC
, ROMBAR0
, ROMBAR1
, RAMBAR0
, RAMBAR1
,
259 MPCR
/* Multiprocessor Control register */,
260 EDRAMBAR
/* Embedded DRAM Base Address Register */,
261 /* Permutation control registers. */
262 PCR1U0
, PCR1L0
, PCR1U1
, PCR1L1
, PCR2U0
, PCR2L0
, PCR2U1
, PCR2L1
,
263 PCR3U0
, PCR3L0
, PCR3U1
, PCR3L1
,
265 TC
/* ASID */, BUSCR
/* MMUBAR */,
266 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
267 MBAR1
/* MBAR */, MBAR2
/* SECMBAR */, MBAR0
/* SECMBAR */,
268 ROMBAR
/* ROMBAR0 */, RAMBAR
/* RAMBAR1 */,
271 static const enum m68k_register mcf54455_ctrl
[] = {
272 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
273 VBR
, PC
, RAMBAR1
, MBAR
,
275 TC
/* ASID */, BUSCR
/* MMUBAR */,
276 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
277 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
280 static const enum m68k_register mcf5475_ctrl
[] = {
281 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
282 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
284 TC
/* ASID */, BUSCR
/* MMUBAR */,
285 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
286 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
289 static const enum m68k_register mcf5485_ctrl
[] = {
290 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
291 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
293 TC
/* ASID */, BUSCR
/* MMUBAR */,
294 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
295 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
298 static const enum m68k_register fido_ctrl
[] = {
299 SFC
, DFC
, USP
, VBR
, CAC
, MBB
,
302 #define cpu32_ctrl m68010_ctrl
304 static const enum m68k_register
*control_regs
;
306 /* Internal form of a 68020 instruction. */
310 const char *args
; /* List of opcode info. */
313 int numo
; /* Number of shorts in opcode. */
316 struct m68k_op operands
[6];
318 int nexp
; /* Number of exprs in use. */
319 struct m68k_exp exprs
[4];
321 int nfrag
; /* Number of frags we have to produce. */
324 int fragoff
; /* Where in the current opcode the frag ends. */
331 int nrel
; /* Num of reloc strucs in use. */
338 /* In a pc relative address the difference between the address
339 of the offset and the address that the offset is relative
340 to. This depends on the addressing mode. Basically this
341 is the value to put in the offset field to address the
342 first byte of the offset, without regarding the special
343 significance of some values (in the branch instruction, for
347 /* Whether this expression needs special pic relocation, and if
349 enum pic_relocation pic_reloc
;
352 reloc
[5]; /* Five is enough??? */
355 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
356 #define float_of_arch(x) ((x) & mfloat)
357 #define mmu_of_arch(x) ((x) & mmmu)
358 #define arch_coldfire_p(x) ((x) & mcfisa_a)
359 #define arch_coldfire_fpu(x) ((x) & cfloat)
361 /* Macros for determining if cpu supports a specific addressing mode. */
362 #define HAVE_LONG_DISP(x) \
363 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
364 #define HAVE_LONG_CALL(x) \
365 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
366 #define HAVE_LONG_COND(x) \
367 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
368 #define HAVE_LONG_BRANCH(x) \
369 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
371 static struct m68k_it the_ins
; /* The instruction being assembled. */
373 #define op(ex) ((ex)->exp.X_op)
374 #define adds(ex) ((ex)->exp.X_add_symbol)
375 #define subs(ex) ((ex)->exp.X_op_symbol)
376 #define offs(ex) ((ex)->exp.X_add_number)
378 /* Macros for adding things to the m68k_it struct. */
379 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
381 /* Like addword, but goes BEFORE general operands. */
384 insop (int w
, const struct m68k_incant
*opcode
)
387 for (z
= the_ins
.numo
; z
> opcode
->m_codenum
; --z
)
388 the_ins
.opcode
[z
] = the_ins
.opcode
[z
- 1];
389 for (z
= 0; z
< the_ins
.nrel
; z
++)
390 the_ins
.reloc
[z
].n
+= 2;
391 for (z
= 0; z
< the_ins
.nfrag
; z
++)
392 the_ins
.fragb
[z
].fragoff
++;
393 the_ins
.opcode
[opcode
->m_codenum
] = w
;
397 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
400 add_fix (int width
, struct m68k_exp
*exp
, int pc_rel
, int pc_fix
)
402 the_ins
.reloc
[the_ins
.nrel
].n
= (width
== 'B' || width
== '3'
403 ? the_ins
.numo
* 2 - 1
405 ? the_ins
.numo
* 2 + 1
406 : the_ins
.numo
* 2));
407 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
408 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
409 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
411 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
413 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
416 /* Cause an extra frag to be generated here, inserting up to 10 bytes
417 (that value is chosen in the frag_var call in md_assemble). TYPE
418 is the subtype of the frag to be generated; its primary type is
419 rs_machine_dependent.
421 The TYPE parameter is also used by md_convert_frag_1 and
422 md_estimate_size_before_relax. The appropriate type of fixup will
423 be emitted by md_convert_frag_1.
425 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
427 add_frag (symbolS
*add
, offsetT off
, int type
)
429 the_ins
.fragb
[the_ins
.nfrag
].fragoff
= the_ins
.numo
;
430 the_ins
.fragb
[the_ins
.nfrag
].fadd
= add
;
431 the_ins
.fragb
[the_ins
.nfrag
].foff
= off
;
432 the_ins
.fragb
[the_ins
.nfrag
++].fragty
= type
;
436 (op (ex) != O_constant && op (ex) != O_big)
438 static char *crack_operand (char *str
, struct m68k_op
*opP
);
439 static int get_num (struct m68k_exp
*exp
, int ok
);
440 static int reverse_16_bits (int in
);
441 static int reverse_8_bits (int in
);
442 static void install_gen_operand (int mode
, int val
);
443 static void install_operand (int mode
, int val
);
444 static void s_bss (int);
445 static void s_data1 (int);
446 static void s_data2 (int);
447 static void s_even (int);
448 static void s_proc (int);
449 static void s_chip (int);
450 static void s_fopt (int);
451 static void s_opt (int);
452 static void s_reg (int);
453 static void s_restore (int);
454 static void s_save (int);
455 static void s_mri_if (int);
456 static void s_mri_else (int);
457 static void s_mri_endi (int);
458 static void s_mri_break (int);
459 static void s_mri_next (int);
460 static void s_mri_for (int);
461 static void s_mri_endf (int);
462 static void s_mri_repeat (int);
463 static void s_mri_until (int);
464 static void s_mri_while (int);
465 static void s_mri_endw (int);
466 static void s_m68k_cpu (int);
467 static void s_m68k_arch (int);
471 unsigned long arch
; /* Architecture features. */
472 const enum m68k_register
*control_regs
; /* Control regs on chip */
473 const char *name
; /* Name */
474 int alias
; /* Alias for a cannonical name. If 1, then
475 succeeds canonical name, if -1 then
476 succeeds canonical name, if <-1 ||>1 this is a
477 deprecated name, and the next/previous name
481 /* We hold flags for features explicitly enabled and explicitly
483 static int current_architecture
;
484 static int not_current_architecture
;
485 static const struct m68k_cpu
*selected_arch
;
486 static const struct m68k_cpu
*selected_cpu
;
487 static int initialized
;
489 /* Architecture models. */
490 static const struct m68k_cpu m68k_archs
[] =
492 {m68000
, m68000_ctrl
, "68000", 0},
493 {m68010
, m68010_ctrl
, "68010", 0},
494 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
495 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
496 {m68040
, m68040_ctrl
, "68040", 0},
497 {m68060
, m68060_ctrl
, "68060", 0},
498 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
499 {fido_a
, fido_ctrl
, "fidoa", 0},
500 {mcfisa_a
|mcfhwdiv
, NULL
, "isaa", 0},
501 {mcfisa_a
|mcfhwdiv
|mcfisa_aa
|mcfusp
, NULL
, "isaaplus", 0},
502 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfusp
, NULL
, "isab", 0},
503 {mcfisa_a
|mcfhwdiv
|mcfisa_c
|mcfusp
, NULL
, "isac", 0},
504 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfmac
|mcfusp
, mcf_ctrl
, "cfv4", 0},
505 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "cfv4e", 0},
509 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
511 static const struct m68k_cpu m68k_extensions
[] =
513 {m68851
, NULL
, "68851", -1},
514 {m68881
, NULL
, "68881", -1},
515 {m68881
, NULL
, "68882", -1},
517 {cfloat
|m68881
, NULL
, "float", 0},
519 {mcfhwdiv
, NULL
, "div", 1},
520 {mcfusp
, NULL
, "usp", 1},
521 {mcfmac
, NULL
, "mac", 1},
522 {mcfemac
, NULL
, "emac", 1},
528 static const struct m68k_cpu m68k_cpus
[] =
530 {m68000
, m68000_ctrl
, "68000", 0},
531 {m68000
, m68000_ctrl
, "68ec000", 1},
532 {m68000
, m68000_ctrl
, "68hc000", 1},
533 {m68000
, m68000_ctrl
, "68hc001", 1},
534 {m68000
, m68000_ctrl
, "68008", 1},
535 {m68000
, m68000_ctrl
, "68302", 1},
536 {m68000
, m68000_ctrl
, "68306", 1},
537 {m68000
, m68000_ctrl
, "68307", 1},
538 {m68000
, m68000_ctrl
, "68322", 1},
539 {m68000
, m68000_ctrl
, "68356", 1},
540 {m68010
, m68010_ctrl
, "68010", 0},
541 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
542 {m68020
|m68881
|m68851
, m68020_ctrl
, "68k", 1},
543 {m68020
|m68881
|m68851
, m68020_ctrl
, "68ec020", 1},
544 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
545 {m68030
|m68881
|m68851
, m68020_ctrl
, "68ec030", 1},
546 {m68040
, m68040_ctrl
, "68040", 0},
547 {m68040
, m68040_ctrl
, "68ec040", 1},
548 {m68060
, m68060_ctrl
, "68060", 0},
549 {m68060
, m68060_ctrl
, "68ec060", 1},
551 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
552 {cpu32
|m68881
, cpu32_ctrl
, "68330", 1},
553 {cpu32
|m68881
, cpu32_ctrl
, "68331", 1},
554 {cpu32
|m68881
, cpu32_ctrl
, "68332", 1},
555 {cpu32
|m68881
, cpu32_ctrl
, "68333", 1},
556 {cpu32
|m68881
, cpu32_ctrl
, "68334", 1},
557 {cpu32
|m68881
, cpu32_ctrl
, "68336", 1},
558 {cpu32
|m68881
, cpu32_ctrl
, "68340", 1},
559 {cpu32
|m68881
, cpu32_ctrl
, "68341", 1},
560 {cpu32
|m68881
, cpu32_ctrl
, "68349", 1},
561 {cpu32
|m68881
, cpu32_ctrl
, "68360", 1},
563 {mcfisa_a
, mcf_ctrl
, "5200", 0},
564 {mcfisa_a
, mcf_ctrl
, "5202", 1},
565 {mcfisa_a
, mcf_ctrl
, "5204", 1},
566 {mcfisa_a
, mcf5206_ctrl
, "5206", 1},
568 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5206_ctrl
, "5206e", 0},
570 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5207", -1},
571 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5208", 0},
573 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5210a", 0},
574 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5211a", 1},
576 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5211", -1},
577 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5212", -1},
578 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5213", 0},
580 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5214", -1},
581 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5216", 0},
582 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "521x", 2},
584 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf52223_ctrl
, "52221", -1},
585 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf52223_ctrl
, "52223", 0},
587 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52230", -1},
588 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52233", -1},
589 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52234", -1},
590 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52235", 0},
592 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5224", -1},
593 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5225", 0},
595 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5232", -1},
596 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5233", -1},
597 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5234", -1},
598 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5235", -1},
599 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "523x", 0},
601 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5249_ctrl
, "5249", 0},
602 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5250_ctrl
, "5250", 0},
603 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5253_ctrl
, "5253", 0},
605 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5270", -1},
606 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5271", 0},
608 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5272_ctrl
, "5272", 0},
610 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5274", -1},
611 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5275", 0},
613 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5280", -1},
614 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5281", -1},
615 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5282", -1},
616 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "528x", 0},
618 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5307_ctrl
, "5307", 0},
620 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5327", -1},
621 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5328", -1},
622 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5329", -1},
623 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "532x", 0},
625 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5372", -1},
626 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5373", -1},
627 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "537x", 0},
629 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfmac
, mcf_ctrl
, "5407",0},
631 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54450", -1},
632 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54451", -1},
633 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54452", -1},
634 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54453", -1},
635 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54454", -1},
636 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54455", 0},
638 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5470", -1},
639 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5471", -1},
640 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5472", -1},
641 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5473", -1},
642 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5474", -1},
643 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5475", -1},
644 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "547x", 0},
646 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5480", -1},
647 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5481", -1},
648 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5482", -1},
649 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5483", -1},
650 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5484", -1},
651 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5485", -1},
652 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "548x", 0},
654 {fido_a
, fido_ctrl
, "fidoa", 0},
655 {fido_a
, fido_ctrl
, "fido", 1},
660 static const struct m68k_cpu
*m68k_lookup_cpu
661 (const char *, const struct m68k_cpu
*, int, int *);
662 static int m68k_set_arch (const char *, int, int);
663 static int m68k_set_cpu (const char *, int, int);
664 static int m68k_set_extension (const char *, int, int);
665 static void m68k_init_arch (void);
667 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
668 architecture and we have a lot of relaxation modes. */
670 /* Macros used in the relaxation code. */
671 #define TAB(x,y) (((x) << 2) + (y))
672 #define TABTYPE(x) ((x) >> 2)
674 /* Relaxation states. */
680 /* Here are all the relaxation modes we support. First we can relax ordinary
681 branches. On 68020 and higher and on CPU32 all branch instructions take
682 three forms, so on these CPUs all branches always remain as such. When we
683 have to expand to the LONG form on a 68000, though, we substitute an
684 absolute jump instead. This is a direct replacement for unconditional
685 branches and a branch over a jump for conditional branches. However, if the
686 user requires PIC and disables this with --pcrel, we can only relax between
687 BYTE and SHORT forms, punting if that isn't enough. This gives us four
688 different relaxation modes for branches: */
690 #define BRANCHBWL 0 /* Branch byte, word, or long. */
691 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
692 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
693 #define BRANCHBW 3 /* Branch byte or word. */
695 /* We also relax coprocessor branches and DBcc's. All CPUs that support
696 coprocessor branches support them in word and long forms, so we have only
697 one relaxation mode for them. DBcc's are word only on all CPUs. We can
698 relax them to the LONG form with a branch-around sequence. This sequence
699 can use a long branch (if available) or an absolute jump (if acceptable).
700 This gives us two relaxation modes. If long branches are not available and
701 absolute jumps are not acceptable, we don't relax DBcc's. */
703 #define FBRANCH 4 /* Coprocessor branch. */
704 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
705 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
707 /* That's all for instruction relaxation. However, we also relax PC-relative
708 operands. Specifically, we have three operand relaxation modes. On the
709 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
710 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
711 two. Also PC+displacement+index operands in their simple form (with a non-
712 suppressed index without memory indirection) are supported on all CPUs, but
713 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
714 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
715 form of the PC+displacement+index operand. Finally, some absolute operands
716 can be relaxed down to 16-bit PC-relative. */
718 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
719 #define PCINDEX 8 /* PC + displacement + index. */
720 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
722 /* Note that calls to frag_var need to specify the maximum expansion
723 needed; this is currently 10 bytes for DBCC. */
726 How far Forward this mode will reach:
727 How far Backward this mode will reach:
728 How many bytes this mode will add to the size of the frag
729 Which mode to go to if the offset won't fit in this one
731 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
732 relax_typeS md_relax_table
[] =
734 { 127, -128, 0, TAB (BRANCHBWL
, SHORT
) },
735 { 32767, -32768, 2, TAB (BRANCHBWL
, LONG
) },
739 { 127, -128, 0, TAB (BRABSJUNC
, SHORT
) },
740 { 32767, -32768, 2, TAB (BRABSJUNC
, LONG
) },
744 { 127, -128, 0, TAB (BRABSJCOND
, SHORT
) },
745 { 32767, -32768, 2, TAB (BRABSJCOND
, LONG
) },
749 { 127, -128, 0, TAB (BRANCHBW
, SHORT
) },
754 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
755 { 32767, -32768, 2, TAB (FBRANCH
, LONG
) },
759 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
760 { 32767, -32768, 2, TAB (DBCCLBR
, LONG
) },
764 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
765 { 32767, -32768, 2, TAB (DBCCABSJ
, LONG
) },
769 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
770 { 32767, -32768, 2, TAB (PCREL1632
, LONG
) },
774 { 125, -130, 0, TAB (PCINDEX
, SHORT
) },
775 { 32765, -32770, 2, TAB (PCINDEX
, LONG
) },
779 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
780 { 32767, -32768, 2, TAB (ABSTOPCREL
, LONG
) },
785 /* These are the machine dependent pseudo-ops. These are included so
786 the assembler can work on the output from the SUN C compiler, which
789 /* This table describes all the machine specific pseudo-ops the assembler
790 has to support. The fields are:
791 pseudo-op name without dot
792 function to call to execute this pseudo-op
793 Integer arg to pass to the function. */
794 const pseudo_typeS md_pseudo_table
[] =
796 {"data1", s_data1
, 0},
797 {"data2", s_data2
, 0},
800 {"skip", s_space
, 0},
802 #if defined (TE_SUN3) || defined (OBJ_ELF)
803 {"align", s_align_bytes
, 0},
806 {"swbeg", s_ignore
, 0},
808 {"extend", float_cons
, 'x'},
809 {"ldouble", float_cons
, 'x'},
811 {"arch", s_m68k_arch
, 0},
812 {"cpu", s_m68k_cpu
, 0},
814 /* The following pseudo-ops are supported for MRI compatibility. */
816 {"comline", s_space
, 1},
818 {"mask2", s_ignore
, 0},
821 {"restore", s_restore
, 0},
825 {"if.b", s_mri_if
, 'b'},
826 {"if.w", s_mri_if
, 'w'},
827 {"if.l", s_mri_if
, 'l'},
828 {"else", s_mri_else
, 0},
829 {"else.s", s_mri_else
, 's'},
830 {"else.l", s_mri_else
, 'l'},
831 {"endi", s_mri_endi
, 0},
832 {"break", s_mri_break
, 0},
833 {"break.s", s_mri_break
, 's'},
834 {"break.l", s_mri_break
, 'l'},
835 {"next", s_mri_next
, 0},
836 {"next.s", s_mri_next
, 's'},
837 {"next.l", s_mri_next
, 'l'},
838 {"for", s_mri_for
, 0},
839 {"for.b", s_mri_for
, 'b'},
840 {"for.w", s_mri_for
, 'w'},
841 {"for.l", s_mri_for
, 'l'},
842 {"endf", s_mri_endf
, 0},
843 {"repeat", s_mri_repeat
, 0},
844 {"until", s_mri_until
, 0},
845 {"until.b", s_mri_until
, 'b'},
846 {"until.w", s_mri_until
, 'w'},
847 {"until.l", s_mri_until
, 'l'},
848 {"while", s_mri_while
, 0},
849 {"while.b", s_mri_while
, 'b'},
850 {"while.w", s_mri_while
, 'w'},
851 {"while.l", s_mri_while
, 'l'},
852 {"endw", s_mri_endw
, 0},
857 /* The mote pseudo ops are put into the opcode table, since they
858 don't start with a . they look like opcodes to gas. */
860 const pseudo_typeS mote_pseudo_table
[] =
873 {"xdef", s_globl
, 0},
875 {"align", s_align_bytes
, 0},
877 {"align", s_align_ptwo
, 0},
880 {"sect", obj_coff_section
, 0},
881 {"section", obj_coff_section
, 0},
886 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
887 gives identical results to a 32-bit host. */
888 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
889 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
891 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
892 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
893 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
894 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
896 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
897 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
898 #define islong(x) (1)
900 static char notend_table
[256];
901 static char alt_notend_table
[256];
903 (! (notend_table[(unsigned char) *s] \
905 && alt_notend_table[(unsigned char) s[1]])))
909 /* Return zero if the reference to SYMBOL from within the same segment may
912 /* On an ELF system, we can't relax an externally visible symbol,
913 because it may be overridden by a shared library. However, if
914 TARGET_OS is "elf", then we presume that we are assembling for an
915 embedded system, in which case we don't have to worry about shared
916 libraries, and we can relax any external sym. */
918 #define relaxable_symbol(symbol) \
919 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
920 || S_IS_WEAK (symbol)))
922 /* Compute the relocation code for a fixup of SIZE bytes, using pc
923 relative relocation if PCREL is non-zero. PIC says whether a special
924 pic relocation was requested. */
926 static bfd_reloc_code_real_type
927 get_reloc_code (int size
, int pcrel
, enum pic_relocation pic
)
935 return BFD_RELOC_8_GOT_PCREL
;
937 return BFD_RELOC_16_GOT_PCREL
;
939 return BFD_RELOC_32_GOT_PCREL
;
947 return BFD_RELOC_8_GOTOFF
;
949 return BFD_RELOC_16_GOTOFF
;
951 return BFD_RELOC_32_GOTOFF
;
959 return BFD_RELOC_8_PLT_PCREL
;
961 return BFD_RELOC_16_PLT_PCREL
;
963 return BFD_RELOC_32_PLT_PCREL
;
971 return BFD_RELOC_8_PLTOFF
;
973 return BFD_RELOC_16_PLTOFF
;
975 return BFD_RELOC_32_PLTOFF
;
985 return BFD_RELOC_8_PCREL
;
987 return BFD_RELOC_16_PCREL
;
989 return BFD_RELOC_32_PCREL
;
1001 return BFD_RELOC_32
;
1008 if (pic
== pic_none
)
1009 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
1011 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
1015 if (pic
== pic_none
)
1016 as_bad (_("Can not do %d byte relocation"), size
);
1018 as_bad (_("Can not do %d byte pic relocation"), size
);
1021 return BFD_RELOC_NONE
;
1024 /* Here we decide which fixups can be adjusted to make them relative
1025 to the beginning of the section instead of the symbol. Basically
1026 we need to make sure that the dynamic relocations are done
1027 correctly, so in some cases we force the original symbol to be
1030 tc_m68k_fix_adjustable (fixS
*fixP
)
1032 /* Adjust_reloc_syms doesn't know about the GOT. */
1033 switch (fixP
->fx_r_type
)
1035 case BFD_RELOC_8_GOT_PCREL
:
1036 case BFD_RELOC_16_GOT_PCREL
:
1037 case BFD_RELOC_32_GOT_PCREL
:
1038 case BFD_RELOC_8_GOTOFF
:
1039 case BFD_RELOC_16_GOTOFF
:
1040 case BFD_RELOC_32_GOTOFF
:
1041 case BFD_RELOC_8_PLT_PCREL
:
1042 case BFD_RELOC_16_PLT_PCREL
:
1043 case BFD_RELOC_32_PLT_PCREL
:
1044 case BFD_RELOC_8_PLTOFF
:
1045 case BFD_RELOC_16_PLTOFF
:
1046 case BFD_RELOC_32_PLTOFF
:
1049 case BFD_RELOC_VTABLE_INHERIT
:
1050 case BFD_RELOC_VTABLE_ENTRY
:
1058 #else /* !OBJ_ELF */
1060 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1062 /* PR gas/3041 Weak symbols are not relaxable
1063 because they must be treated as extern. */
1064 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1066 #endif /* OBJ_ELF */
1069 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
1072 bfd_reloc_code_real_type code
;
1074 /* If the tcbit is set, then this was a fixup of a negative value
1075 that was never resolved. We do not have a reloc to handle this,
1076 so just return. We assume that other code will have detected this
1077 situation and produced a helpful error message, so we just tell the
1078 user that the reloc cannot be produced. */
1082 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1083 _("Unable to produce reloc against symbol '%s'"),
1084 S_GET_NAME (fixp
->fx_addsy
));
1088 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
1090 code
= fixp
->fx_r_type
;
1092 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1093 that fixup_segment converted a non-PC relative reloc into a
1094 PC relative reloc. In such a case, we need to convert the
1101 code
= BFD_RELOC_8_PCREL
;
1104 code
= BFD_RELOC_16_PCREL
;
1107 code
= BFD_RELOC_32_PCREL
;
1109 case BFD_RELOC_8_PCREL
:
1110 case BFD_RELOC_16_PCREL
:
1111 case BFD_RELOC_32_PCREL
:
1112 case BFD_RELOC_8_GOT_PCREL
:
1113 case BFD_RELOC_16_GOT_PCREL
:
1114 case BFD_RELOC_32_GOT_PCREL
:
1115 case BFD_RELOC_8_GOTOFF
:
1116 case BFD_RELOC_16_GOTOFF
:
1117 case BFD_RELOC_32_GOTOFF
:
1118 case BFD_RELOC_8_PLT_PCREL
:
1119 case BFD_RELOC_16_PLT_PCREL
:
1120 case BFD_RELOC_32_PLT_PCREL
:
1121 case BFD_RELOC_8_PLTOFF
:
1122 case BFD_RELOC_16_PLTOFF
:
1123 case BFD_RELOC_32_PLTOFF
:
1126 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1127 _("Cannot make %s relocation PC relative"),
1128 bfd_get_reloc_code_name (code
));
1134 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1135 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
1137 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1138 MAP (1, 0, BFD_RELOC_8
);
1139 MAP (2, 0, BFD_RELOC_16
);
1140 MAP (4, 0, BFD_RELOC_32
);
1141 MAP (1, 1, BFD_RELOC_8_PCREL
);
1142 MAP (2, 1, BFD_RELOC_16_PCREL
);
1143 MAP (4, 1, BFD_RELOC_32_PCREL
);
1151 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1152 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1153 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1154 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1157 reloc
->addend
= fixp
->fx_addnumber
;
1158 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
1160 && S_IS_WEAK (fixp
->fx_addsy
)
1161 && ! bfd_is_und_section (S_GET_SEGMENT (fixp
->fx_addsy
)))
1162 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1163 to put the symbol offset into frags referencing a weak symbol. */
1164 reloc
->addend
= fixp
->fx_addnumber
1165 - (S_GET_VALUE (fixp
->fx_addsy
) * 2);
1169 if (!fixp
->fx_pcrel
)
1170 reloc
->addend
= fixp
->fx_addnumber
;
1172 reloc
->addend
= (section
->vma
1173 /* Explicit sign extension in case char is
1175 + ((fixp
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80
1176 + fixp
->fx_addnumber
1177 + md_pcrel_from (fixp
));
1180 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1181 assert (reloc
->howto
!= 0);
1186 /* Handle of the OPCODE hash table. NULL means any use before
1187 m68k_ip_begin() will crash. */
1188 static struct hash_control
*op_hash
;
1190 /* Assemble an m68k instruction. */
1193 m68k_ip (char *instring
)
1196 register struct m68k_op
*opP
;
1197 register const struct m68k_incant
*opcode
;
1198 register const char *s
;
1199 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1200 char *pdot
, *pdotmove
;
1201 enum m68k_size siz1
, siz2
;
1205 struct m68k_op operands_backup
[6];
1206 LITTLENUM_TYPE words
[6];
1207 LITTLENUM_TYPE
*wordp
;
1208 unsigned long ok_arch
= 0;
1210 if (*instring
== ' ')
1211 instring
++; /* Skip leading whitespace. */
1213 /* Scan up to end of operation-code, which MUST end in end-of-string
1214 or exactly 1 space. */
1216 for (p
= instring
; *p
!= '\0'; p
++)
1226 the_ins
.error
= _("No operator");
1230 /* p now points to the end of the opcode name, probably whitespace.
1231 Make sure the name is null terminated by clobbering the
1232 whitespace, look it up in the hash table, then fix it back.
1233 Remove a dot, first, since the opcode tables have none. */
1236 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1237 *pdotmove
= pdotmove
[1];
1243 opcode
= (const struct m68k_incant
*) hash_find (op_hash
, instring
);
1248 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1249 *pdotmove
= pdotmove
[-1];
1256 the_ins
.error
= _("Unknown operator");
1260 /* Found a legitimate opcode, start matching operands. */
1264 if (opcode
->m_operands
== 0)
1266 char *old
= input_line_pointer
;
1268 input_line_pointer
= p
;
1269 /* Ahh - it's a motorola style psuedo op. */
1270 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1271 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1272 input_line_pointer
= old
;
1278 if (flag_mri
&& opcode
->m_opnum
== 0)
1280 /* In MRI mode, random garbage is allowed after an instruction
1281 which accepts no operands. */
1282 the_ins
.args
= opcode
->m_operands
;
1283 the_ins
.numargs
= opcode
->m_opnum
;
1284 the_ins
.numo
= opcode
->m_codenum
;
1285 the_ins
.opcode
[0] = getone (opcode
);
1286 the_ins
.opcode
[1] = gettwo (opcode
);
1290 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1292 p
= crack_operand (p
, opP
);
1296 the_ins
.error
= opP
->error
;
1301 opsfound
= opP
- &the_ins
.operands
[0];
1303 /* This ugly hack is to support the floating pt opcodes in their
1304 standard form. Essentially, we fake a first enty of type COP#1 */
1305 if (opcode
->m_operands
[0] == 'I')
1309 for (n
= opsfound
; n
> 0; --n
)
1310 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1312 memset (&the_ins
.operands
[0], '\0', sizeof (the_ins
.operands
[0]));
1313 the_ins
.operands
[0].mode
= CONTROL
;
1314 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1318 /* We've got the operands. Find an opcode that'll accept them. */
1321 /* If we didn't get the right number of ops, or we have no
1322 common model with this pattern then reject this pattern. */
1324 ok_arch
|= opcode
->m_arch
;
1325 if (opsfound
!= opcode
->m_opnum
1326 || ((opcode
->m_arch
& current_architecture
) == 0))
1332 /* Make a copy of the operands of this insn so that
1333 we can modify them safely, should we want to. */
1334 assert (opsfound
<= (int) ARRAY_SIZE (operands_backup
));
1335 for (i
= 0; i
< opsfound
; i
++)
1336 operands_backup
[i
] = the_ins
.operands
[i
];
1338 for (s
= opcode
->m_operands
, opP
= &operands_backup
[0];
1342 /* Warning: this switch is huge! */
1343 /* I've tried to organize the cases into this order:
1344 non-alpha first, then alpha by letter. Lower-case
1345 goes directly before uppercase counterpart. */
1346 /* Code with multiple case ...: gets sorted by the lowest
1347 case ... it belongs to. I hope this makes sense. */
1453 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1470 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1489 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1499 if (opP
->mode
!= IMMED
)
1501 else if (s
[1] == 'b'
1502 && ! isvar (&opP
->disp
)
1503 && (opP
->disp
.exp
.X_op
!= O_constant
1504 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1506 else if (s
[1] == 'B'
1507 && ! isvar (&opP
->disp
)
1508 && (opP
->disp
.exp
.X_op
!= O_constant
1509 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1511 else if (s
[1] == 'w'
1512 && ! isvar (&opP
->disp
)
1513 && (opP
->disp
.exp
.X_op
!= O_constant
1514 || ! isword (opP
->disp
.exp
.X_add_number
)))
1516 else if (s
[1] == 'W'
1517 && ! isvar (&opP
->disp
)
1518 && (opP
->disp
.exp
.X_op
!= O_constant
1519 || ! issword (opP
->disp
.exp
.X_add_number
)))
1525 if (opP
->mode
!= IMMED
)
1530 if (opP
->mode
== AREG
1531 || opP
->mode
== CONTROL
1532 || opP
->mode
== FPREG
1533 || opP
->mode
== IMMED
1534 || opP
->mode
== REGLST
1535 || (opP
->mode
!= ABSL
1537 || opP
->reg
== ZPC
)))
1542 if (opP
->mode
== CONTROL
1543 || opP
->mode
== FPREG
1544 || opP
->mode
== REGLST
1545 || opP
->mode
== IMMED
1546 || (opP
->mode
!= ABSL
1548 || opP
->reg
== ZPC
)))
1576 if (opP
->mode
== CONTROL
1577 || opP
->mode
== FPREG
1578 || opP
->mode
== REGLST
)
1583 if (opP
->mode
!= AINC
)
1588 if (opP
->mode
!= ADEC
)
1638 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1659 case '~': /* For now! (JF FOO is this right?) */
1681 if (opP
->mode
!= CONTROL
1682 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1687 if (opP
->mode
!= AREG
)
1692 if (opP
->mode
!= AINDR
)
1697 if (opP
->mode
!= AINDR
&& opP
->mode
!= AINC
&& opP
->mode
!= ADEC
1698 && (opP
->mode
!= DISP
1700 || opP
->reg
> ADDR7
))
1705 if (opP
->mode
!= ABSL
1707 && strncmp (instring
, "jbsr", 4) == 0))
1730 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1735 if (opP
->mode
!= DISP
1737 || opP
->reg
> ADDR7
)
1742 if (opP
->mode
!= DREG
)
1747 if (opP
->reg
!= ACC
)
1752 if (opP
->reg
!= ACC
&& opP
->reg
!= ACC1
1753 && opP
->reg
!= ACC2
&& opP
->reg
!= ACC3
)
1758 if (opP
->mode
!= FPREG
)
1763 if (opP
->reg
!= MACSR
)
1768 if (opP
->reg
!= ACCEXT01
&& opP
->reg
!= ACCEXT23
)
1773 if (opP
->reg
!= MASK
)
1778 if (opP
->mode
!= CONTROL
1785 if (opP
->mode
!= LSH
&& opP
->mode
!= RSH
)
1790 if (opP
->mode
!= CONTROL
1792 || opP
->reg
> last_movec_reg
1797 const enum m68k_register
*rp
;
1799 for (rp
= control_regs
; *rp
; rp
++)
1801 if (*rp
== opP
->reg
)
1803 /* In most CPUs RAMBAR refers to control reg
1804 c05 (RAMBAR1), but a few CPUs have it
1805 refer to c04 (RAMBAR0). */
1806 else if (*rp
== RAMBAR_ALT
&& opP
->reg
== RAMBAR
)
1808 opP
->reg
= RAMBAR_ALT
;
1818 if (opP
->mode
!= IMMED
)
1824 if (opP
->mode
== DREG
1825 || opP
->mode
== AREG
1826 || opP
->mode
== FPREG
)
1835 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1838 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1841 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1849 else if (opP
->mode
== CONTROL
)
1858 opP
->mask
= 1 << 24;
1861 opP
->mask
= 1 << 25;
1864 opP
->mask
= 1 << 26;
1873 else if (opP
->mode
!= REGLST
)
1875 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
1877 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
1882 if (opP
->mode
!= IMMED
)
1884 else if (opP
->disp
.exp
.X_op
!= O_constant
1885 || ! issbyte (opP
->disp
.exp
.X_add_number
))
1887 else if (! m68k_quick
1888 && instring
[3] != 'q'
1889 && instring
[4] != 'q')
1894 if (opP
->mode
!= DREG
1895 && opP
->mode
!= IMMED
1896 && opP
->mode
!= ABSL
)
1901 if (opP
->mode
!= IMMED
)
1903 else if (opP
->disp
.exp
.X_op
!= O_constant
1904 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
1906 else if (! m68k_quick
1907 && (strncmp (instring
, "add", 3) == 0
1908 || strncmp (instring
, "sub", 3) == 0)
1909 && instring
[3] != 'q')
1914 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1919 if (opP
->mode
!= AINDR
1920 && (opP
->mode
!= BASE
1922 && opP
->reg
!= ZADDR0
)
1923 || opP
->disp
.exp
.X_op
!= O_absent
1924 || ((opP
->index
.reg
< DATA0
1925 || opP
->index
.reg
> DATA7
)
1926 && (opP
->index
.reg
< ADDR0
1927 || opP
->index
.reg
> ADDR7
))
1928 || opP
->index
.size
!= SIZE_UNSPEC
1929 || opP
->index
.scale
!= 1))
1934 if (opP
->mode
!= CONTROL
1935 || ! (opP
->reg
== FPI
1937 || opP
->reg
== FPC
))
1942 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
1947 if (opP
->mode
!= IMMED
)
1949 else if (opP
->disp
.exp
.X_op
!= O_constant
1950 || TRUNC (opP
->disp
.exp
.X_add_number
) > 7)
1955 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
1960 if (opP
->mode
!= IMMED
)
1962 else if (opP
->disp
.exp
.X_op
!= O_constant
1963 || (TRUNC (opP
->disp
.exp
.X_add_number
) != 0xffffffff
1964 && TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 6))
1968 /* JF these are out of order. We could put them
1969 in order if we were willing to put up with
1970 bunches of #ifdef m68851s in the code.
1972 Don't forget that you need these operands
1973 to use 68030 MMU instructions. */
1975 /* Memory addressing mode used by pflushr. */
1977 if (opP
->mode
== CONTROL
1978 || opP
->mode
== FPREG
1979 || opP
->mode
== DREG
1980 || opP
->mode
== AREG
1981 || opP
->mode
== REGLST
)
1983 /* We should accept immediate operands, but they
1984 supposedly have to be quad word, and we don't
1985 handle that. I would like to see what a Motorola
1986 assembler does before doing something here. */
1987 if (opP
->mode
== IMMED
)
1992 if (opP
->mode
!= CONTROL
1993 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1998 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
2003 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
2008 if (opP
->mode
!= CONTROL
2011 && opP
->reg
!= SCC
))
2016 if (opP
->mode
!= CONTROL
2022 if (opP
->mode
!= CONTROL
2025 && opP
->reg
!= CRP
))
2049 if (opP
->mode
!= CONTROL
2050 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
2051 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
2056 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
2061 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
2066 if (opP
->mode
!= CONTROL
2075 if (opP
->mode
!= ABSL
)
2080 if (opP
->reg
< DATA0L
|| opP
->reg
> ADDR7U
)
2082 /* FIXME: kludge instead of fixing parser:
2083 upper/lower registers are *not* CONTROL
2084 registers, but ordinary ones. */
2085 if ((opP
->reg
>= DATA0L
&& opP
->reg
<= DATA7L
)
2086 || (opP
->reg
>= DATA0U
&& opP
->reg
<= DATA7U
))
2093 if (!(opP
->mode
== AINDR
2094 || (opP
->mode
== DISP
2095 && !(opP
->reg
== PC
|| opP
->reg
== ZPC
))))
2100 if (!(opP
->mode
== AINDR
|| opP
->mode
== DISP
))
2112 /* Since we have found the correct instruction, copy
2113 in the modifications that we may have made. */
2115 for (i
= 0; i
< opsfound
; i
++)
2116 the_ins
.operands
[i
] = operands_backup
[i
];
2122 opcode
= opcode
->m_next
;
2127 && !(ok_arch
& current_architecture
))
2129 const struct m68k_cpu
*cpu
;
2132 char *buf
= xmalloc (space
+ 1);
2136 the_ins
.error
= buf
;
2137 /* Make sure there's a NUL at the end of the buffer -- strncpy
2138 won't write one when it runs out of buffer */
2140 #define APPEND(STRING) \
2141 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2143 APPEND (_("invalid instruction for this architecture; needs "));
2147 APPEND (_("ColdFire ISA_A"));
2150 APPEND (_("ColdFire hardware divide"));
2153 APPEND (_("ColdFire ISA_A+"));
2156 APPEND (_("ColdFire ISA_B"));
2159 APPEND (_("ColdFire fpu"));
2162 APPEND (_("M68K fpu"));
2165 APPEND (_("M68K mmu"));
2168 APPEND (_("68020 or higher"));
2171 APPEND (_("68000 or higher"));
2174 APPEND (_("68010 or higher"));
2182 for (cpu
= m68k_cpus
; cpu
->name
; cpu
++)
2183 if (!cpu
->alias
&& (cpu
->arch
& ok_arch
))
2185 const struct m68k_cpu
*alias
;
2186 int seen_master
= 0;
2192 for (alias
= cpu
; alias
!= m68k_cpus
; alias
--)
2193 if (alias
[-1].alias
>= 0)
2195 for (; !seen_master
|| alias
->alias
> 0; alias
++)
2205 APPEND (alias
->name
);
2218 /* we ran out of space, so replace the end of the list
2223 strcpy (buf
, " ...");
2227 the_ins
.error
= _("operands mismatch");
2234 /* Now assemble it. */
2235 the_ins
.args
= opcode
->m_operands
;
2236 the_ins
.numargs
= opcode
->m_opnum
;
2237 the_ins
.numo
= opcode
->m_codenum
;
2238 the_ins
.opcode
[0] = getone (opcode
);
2239 the_ins
.opcode
[1] = gettwo (opcode
);
2241 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2245 /* This switch is a doozy.
2246 Watch the first step; its a big one! */
2279 tmpreg
= 0x3c; /* 7.4 */
2280 if (strchr ("bwl", s
[1]))
2281 nextword
= get_num (&opP
->disp
, 90);
2283 nextword
= get_num (&opP
->disp
, 0);
2284 if (isvar (&opP
->disp
))
2285 add_fix (s
[1], &opP
->disp
, 0, 0);
2289 if (!isbyte (nextword
))
2290 opP
->error
= _("operand out of range");
2295 if (!isword (nextword
))
2296 opP
->error
= _("operand out of range");
2301 if (!issword (nextword
))
2302 opP
->error
= _("operand out of range");
2307 addword (nextword
>> 16);
2334 /* We gotta put out some float. */
2335 if (op (&opP
->disp
) != O_big
)
2340 /* Can other cases happen here? */
2341 if (op (&opP
->disp
) != O_constant
)
2344 val
= (valueT
) offs (&opP
->disp
);
2348 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2349 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2353 offs (&opP
->disp
) = gencnt
;
2355 if (offs (&opP
->disp
) > 0)
2357 if (offs (&opP
->disp
) > baseo
)
2359 as_warn (_("Bignum too big for %c format; truncated"),
2361 offs (&opP
->disp
) = baseo
;
2363 baseo
-= offs (&opP
->disp
);
2366 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
2367 offs (&opP
->disp
)--;
2372 gen_to_words (words
, baseo
, (long) outro
);
2373 for (wordp
= words
; baseo
--; wordp
++)
2377 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2380 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2383 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2386 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2389 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2393 nextword
= get_num (&opP
->disp
, 90);
2395 /* Convert mode 5 addressing with a zero offset into
2396 mode 2 addressing to reduce the instruction size by a
2398 if (! isvar (&opP
->disp
)
2400 && (opP
->disp
.size
== SIZE_UNSPEC
)
2401 && (opP
->reg
>= ADDR0
)
2402 && (opP
->reg
<= ADDR7
))
2404 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2409 && ! isvar (&opP
->disp
)
2412 opP
->disp
.exp
.X_op
= O_symbol
;
2413 opP
->disp
.exp
.X_add_symbol
=
2414 section_symbol (absolute_section
);
2417 /* Force into index mode. Hope this works. */
2419 /* We do the first bit for 32-bit displacements, and the
2420 second bit for 16 bit ones. It is possible that we
2421 should make the default be WORD instead of LONG, but
2422 I think that'd break GCC, so we put up with a little
2423 inefficiency for the sake of working output. */
2425 if (!issword (nextword
)
2426 || (isvar (&opP
->disp
)
2427 && ((opP
->disp
.size
== SIZE_UNSPEC
2428 && flag_short_refs
== 0
2429 && cpu_of_arch (current_architecture
) >= m68020
2430 && ! arch_coldfire_p (current_architecture
))
2431 || opP
->disp
.size
== SIZE_LONG
)))
2433 if (cpu_of_arch (current_architecture
) < m68020
2434 || arch_coldfire_p (current_architecture
))
2436 _("displacement too large for this architecture; needs 68020 or higher");
2438 tmpreg
= 0x3B; /* 7.3 */
2440 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2441 if (isvar (&opP
->disp
))
2445 if (opP
->disp
.size
== SIZE_LONG
2447 /* If the displacement needs pic
2448 relocation it cannot be relaxed. */
2449 || opP
->disp
.pic_reloc
!= pic_none
2454 add_fix ('l', &opP
->disp
, 1, 2);
2458 add_frag (adds (&opP
->disp
),
2459 SEXT (offs (&opP
->disp
)),
2460 TAB (PCREL1632
, SZ_UNDEF
));
2467 add_fix ('l', &opP
->disp
, 0, 0);
2472 addword (nextword
>> 16);
2477 tmpreg
= 0x3A; /* 7.2 */
2479 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2481 if (isvar (&opP
->disp
))
2485 add_fix ('w', &opP
->disp
, 1, 0);
2488 add_fix ('w', &opP
->disp
, 0, 0);
2498 baseo
= get_num (&opP
->disp
, 90);
2499 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2500 outro
= get_num (&opP
->odisp
, 90);
2501 /* Figure out the `addressing mode'.
2502 Also turn on the BASE_DISABLE bit, if needed. */
2503 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2505 tmpreg
= 0x3b; /* 7.3 */
2506 if (opP
->reg
== ZPC
)
2509 else if (opP
->reg
== 0)
2512 tmpreg
= 0x30; /* 6.garbage */
2514 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2517 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2520 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2522 siz1
= opP
->disp
.size
;
2523 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2524 siz2
= opP
->odisp
.size
;
2528 /* Index register stuff. */
2529 if (opP
->index
.reg
!= 0
2530 && opP
->index
.reg
>= DATA
2531 && opP
->index
.reg
<= ADDR7
)
2533 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2535 if (opP
->index
.size
== SIZE_LONG
2536 || (opP
->index
.size
== SIZE_UNSPEC
2537 && m68k_index_width_default
== SIZE_LONG
))
2540 if ((opP
->index
.scale
!= 1
2541 && cpu_of_arch (current_architecture
) < m68020
)
2542 || (opP
->index
.scale
== 8
2543 && (arch_coldfire_p (current_architecture
)
2544 && !arch_coldfire_fpu (current_architecture
))))
2547 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2550 if (arch_coldfire_p (current_architecture
)
2551 && opP
->index
.size
== SIZE_WORD
)
2552 opP
->error
= _("invalid index size for coldfire");
2554 switch (opP
->index
.scale
)
2571 GET US OUT OF HERE! */
2573 /* Must be INDEX, with an index register. Address
2574 register cannot be ZERO-PC, and either :b was
2575 forced, or we know it will fit. For a 68000 or
2576 68010, force this mode anyways, because the
2577 larger modes aren't supported. */
2578 if (opP
->mode
== BASE
2579 && ((opP
->reg
>= ADDR0
2580 && opP
->reg
<= ADDR7
)
2583 if (siz1
== SIZE_BYTE
2584 || cpu_of_arch (current_architecture
) < m68020
2585 || arch_coldfire_p (current_architecture
)
2586 || (siz1
== SIZE_UNSPEC
2587 && ! isvar (&opP
->disp
)
2588 && issbyte (baseo
)))
2590 nextword
+= baseo
& 0xff;
2592 if (isvar (&opP
->disp
))
2594 /* Do a byte relocation. If it doesn't
2595 fit (possible on m68000) let the
2596 fixup processing complain later. */
2598 add_fix ('B', &opP
->disp
, 1, 1);
2600 add_fix ('B', &opP
->disp
, 0, 0);
2602 else if (siz1
!= SIZE_BYTE
)
2604 if (siz1
!= SIZE_UNSPEC
)
2605 as_warn (_("Forcing byte displacement"));
2606 if (! issbyte (baseo
))
2607 opP
->error
= _("byte displacement out of range");
2612 else if (siz1
== SIZE_UNSPEC
2614 && isvar (&opP
->disp
)
2615 && subs (&opP
->disp
) == NULL
2617 /* If the displacement needs pic
2618 relocation it cannot be relaxed. */
2619 && opP
->disp
.pic_reloc
== pic_none
2623 /* The code in md_convert_frag_1 needs to be
2624 able to adjust nextword. Call frag_grow
2625 to ensure that we have enough space in
2626 the frag obstack to make all the bytes
2629 nextword
+= baseo
& 0xff;
2631 add_frag (adds (&opP
->disp
),
2632 SEXT (offs (&opP
->disp
)),
2633 TAB (PCINDEX
, SZ_UNDEF
));
2641 nextword
|= 0x40; /* No index reg. */
2642 if (opP
->index
.reg
>= ZDATA0
2643 && opP
->index
.reg
<= ZDATA7
)
2644 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2645 else if (opP
->index
.reg
>= ZADDR0
2646 || opP
->index
.reg
<= ZADDR7
)
2647 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2650 /* It isn't simple. */
2652 if (cpu_of_arch (current_architecture
) < m68020
2653 || arch_coldfire_p (current_architecture
))
2655 _("invalid operand mode for this architecture; needs 68020 or higher");
2658 /* If the guy specified a width, we assume that it is
2659 wide enough. Maybe it isn't. If so, we lose. */
2663 if (isvar (&opP
->disp
)
2665 : ! issword (baseo
))
2670 else if (! isvar (&opP
->disp
) && baseo
== 0)
2679 as_warn (_(":b not permitted; defaulting to :w"));
2689 /* Figure out inner displacement stuff. */
2690 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2692 if (cpu_of_arch (current_architecture
) & cpu32
)
2693 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2697 if (isvar (&opP
->odisp
)
2699 : ! issword (outro
))
2704 else if (! isvar (&opP
->odisp
) && outro
== 0)
2713 as_warn (_(":b not permitted; defaulting to :w"));
2722 if (opP
->mode
== POST
2723 && (nextword
& 0x40) == 0)
2728 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2730 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2731 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2733 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2735 if (siz1
== SIZE_LONG
)
2736 addword (baseo
>> 16);
2737 if (siz1
!= SIZE_UNSPEC
)
2740 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2741 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2742 if (siz2
== SIZE_LONG
)
2743 addword (outro
>> 16);
2744 if (siz2
!= SIZE_UNSPEC
)
2750 nextword
= get_num (&opP
->disp
, 90);
2751 switch (opP
->disp
.size
)
2756 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2758 tmpreg
= 0x38; /* 7.0 */
2762 if (isvar (&opP
->disp
)
2763 && !subs (&opP
->disp
)
2764 && adds (&opP
->disp
)
2766 /* If the displacement needs pic relocation it
2767 cannot be relaxed. */
2768 && opP
->disp
.pic_reloc
== pic_none
2771 && !strchr ("~%&$?", s
[0]))
2773 tmpreg
= 0x3A; /* 7.2 */
2774 add_frag (adds (&opP
->disp
),
2775 SEXT (offs (&opP
->disp
)),
2776 TAB (ABSTOPCREL
, SZ_UNDEF
));
2779 /* Fall through into long. */
2781 if (isvar (&opP
->disp
))
2782 add_fix ('l', &opP
->disp
, 0, 0);
2784 tmpreg
= 0x39;/* 7.1 mode */
2785 addword (nextword
>> 16);
2790 as_bad (_("unsupported byte value; use a different suffix"));
2794 if (isvar (&opP
->disp
))
2795 add_fix ('w', &opP
->disp
, 0, 0);
2797 tmpreg
= 0x38;/* 7.0 mode */
2805 as_bad (_("unknown/incorrect operand"));
2809 /* If s[0] is '4', then this is for the mac instructions
2810 that can have a trailing_ampersand set. If so, set 0x100
2811 bit on tmpreg so install_gen_operand can check for it and
2812 set the appropriate bit (word2, bit 5). */
2815 if (opP
->trailing_ampersand
)
2818 install_gen_operand (s
[1], tmpreg
);
2824 { /* JF: I hate floating point! */
2839 tmpreg
= get_num (&opP
->disp
, tmpreg
);
2840 if (isvar (&opP
->disp
))
2841 add_fix (s
[1], &opP
->disp
, 0, 0);
2844 case 'b': /* Danger: These do no check for
2845 certain types of overflow.
2847 if (!isbyte (tmpreg
))
2848 opP
->error
= _("out of range");
2849 insop (tmpreg
, opcode
);
2850 if (isvar (&opP
->disp
))
2851 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
2852 (opcode
->m_codenum
) * 2 + 1;
2855 if (!issbyte (tmpreg
))
2856 opP
->error
= _("out of range");
2857 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
2858 if (isvar (&opP
->disp
))
2859 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
2862 if (!isword (tmpreg
))
2863 opP
->error
= _("out of range");
2864 insop (tmpreg
, opcode
);
2865 if (isvar (&opP
->disp
))
2866 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2869 if (!issword (tmpreg
))
2870 opP
->error
= _("out of range");
2871 insop (tmpreg
, opcode
);
2872 if (isvar (&opP
->disp
))
2873 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2876 /* Because of the way insop works, we put these two out
2878 insop (tmpreg
, opcode
);
2879 insop (tmpreg
>> 16, opcode
);
2880 if (isvar (&opP
->disp
))
2881 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2888 install_operand (s
[1], tmpreg
);
2899 install_operand (s
[1], opP
->reg
- ADDR
);
2903 tmpreg
= get_num (&opP
->disp
, 90);
2908 add_fix ('B', &opP
->disp
, 1, -1);
2911 add_fix ('w', &opP
->disp
, 1, 0);
2916 the_ins
.opcode
[0] |= 0xff;
2917 add_fix ('l', &opP
->disp
, 1, 0);
2921 case 'g': /* Conditional branch */
2922 have_disp
= HAVE_LONG_CALL (current_architecture
);
2925 case 'b': /* Unconditional branch */
2926 have_disp
= HAVE_LONG_BRANCH (current_architecture
);
2929 case 's': /* Unconditional subroutine */
2930 have_disp
= HAVE_LONG_CALL (current_architecture
);
2933 if (subs (&opP
->disp
) /* We can't relax it. */
2935 /* If the displacement needs pic relocation it cannot be
2937 || opP
->disp
.pic_reloc
!= pic_none
2942 as_warn (_("Can't use long branches on this architecture"));
2946 /* This could either be a symbol, or an absolute
2947 address. If it's an absolute address, turn it into
2948 an absolute jump right here and keep it out of the
2950 if (adds (&opP
->disp
) == 0)
2952 if (the_ins
.opcode
[0] == 0x6000) /* jbra */
2953 the_ins
.opcode
[0] = 0x4EF9;
2954 else if (the_ins
.opcode
[0] == 0x6100) /* jbsr */
2955 the_ins
.opcode
[0] = 0x4EB9;
2958 the_ins
.opcode
[0] ^= 0x0100;
2959 the_ins
.opcode
[0] |= 0x0006;
2962 add_fix ('l', &opP
->disp
, 0, 0);
2968 /* Now we know it's going into the relaxer. Now figure
2969 out which mode. We try in this order of preference:
2970 long branch, absolute jump, byte/word branches only. */
2972 add_frag (adds (&opP
->disp
),
2973 SEXT (offs (&opP
->disp
)),
2974 TAB (BRANCHBWL
, SZ_UNDEF
));
2975 else if (! flag_keep_pcrel
)
2977 if ((the_ins
.opcode
[0] == 0x6000)
2978 || (the_ins
.opcode
[0] == 0x6100))
2979 add_frag (adds (&opP
->disp
),
2980 SEXT (offs (&opP
->disp
)),
2981 TAB (BRABSJUNC
, SZ_UNDEF
));
2983 add_frag (adds (&opP
->disp
),
2984 SEXT (offs (&opP
->disp
)),
2985 TAB (BRABSJCOND
, SZ_UNDEF
));
2988 add_frag (adds (&opP
->disp
),
2989 SEXT (offs (&opP
->disp
)),
2990 TAB (BRANCHBW
, SZ_UNDEF
));
2993 if (isvar (&opP
->disp
))
2995 /* Check for DBcc instructions. We can relax them,
2996 but only if we have long branches and/or absolute
2998 if (((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2999 && (HAVE_LONG_BRANCH (current_architecture
)
3000 || ! flag_keep_pcrel
))
3002 if (HAVE_LONG_BRANCH (current_architecture
))
3003 add_frag (adds (&opP
->disp
),
3004 SEXT (offs (&opP
->disp
)),
3005 TAB (DBCCLBR
, SZ_UNDEF
));
3007 add_frag (adds (&opP
->disp
),
3008 SEXT (offs (&opP
->disp
)),
3009 TAB (DBCCABSJ
, SZ_UNDEF
));
3012 add_fix ('w', &opP
->disp
, 1, 0);
3016 case 'C': /* Fixed size LONG coproc branches. */
3017 add_fix ('l', &opP
->disp
, 1, 0);
3021 case 'c': /* Var size Coprocesssor branches. */
3022 if (subs (&opP
->disp
) || (adds (&opP
->disp
) == 0))
3024 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
3025 add_fix ('l', &opP
->disp
, 1, 0);
3030 add_frag (adds (&opP
->disp
),
3031 SEXT (offs (&opP
->disp
)),
3032 TAB (FBRANCH
, SZ_UNDEF
));
3039 case 'C': /* Ignore it. */
3042 case 'd': /* JF this is a kludge. */
3043 install_operand ('s', opP
->reg
- ADDR
);
3044 tmpreg
= get_num (&opP
->disp
, 90);
3045 if (!issword (tmpreg
))
3047 as_warn (_("Expression out of range, using 0"));
3054 install_operand (s
[1], opP
->reg
- DATA
);
3057 case 'e': /* EMAC ACCx, reg/reg. */
3058 install_operand (s
[1], opP
->reg
- ACC
);
3061 case 'E': /* Ignore it. */
3065 install_operand (s
[1], opP
->reg
- FP0
);
3068 case 'g': /* EMAC ACCEXTx. */
3069 install_operand (s
[1], opP
->reg
- ACCEXT01
);
3072 case 'G': /* Ignore it. */
3077 tmpreg
= opP
->reg
- COP0
;
3078 install_operand (s
[1], tmpreg
);
3081 case 'i': /* MAC/EMAC scale factor. */
3082 install_operand (s
[1], opP
->mode
== LSH
? 0x1 : 0x3);
3085 case 'J': /* JF foo. */
3225 install_operand (s
[1], tmpreg
);
3229 tmpreg
= get_num (&opP
->disp
, 55);
3230 install_operand (s
[1], tmpreg
& 0x7f);
3237 if (tmpreg
& 0x7FF0000)
3238 as_bad (_("Floating point register in register list"));
3239 insop (reverse_16_bits (tmpreg
), opcode
);
3243 if (tmpreg
& 0x700FFFF)
3244 as_bad (_("Wrong register in floating-point reglist"));
3245 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
3253 if (tmpreg
& 0x7FF0000)
3254 as_bad (_("Floating point register in register list"));
3255 insop (tmpreg
, opcode
);
3257 else if (s
[1] == '8')
3259 if (tmpreg
& 0x0FFFFFF)
3260 as_bad (_("incorrect register in reglist"));
3261 install_operand (s
[1], tmpreg
>> 24);
3265 if (tmpreg
& 0x700FFFF)
3266 as_bad (_("wrong register in floating-point reglist"));
3268 install_operand (s
[1], tmpreg
>> 16);
3273 install_operand (s
[1], get_num (&opP
->disp
, 60));
3277 tmpreg
= ((opP
->mode
== DREG
)
3278 ? 0x20 + (int) (opP
->reg
- DATA
)
3279 : (get_num (&opP
->disp
, 40) & 0x1F));
3280 install_operand (s
[1], tmpreg
);
3284 tmpreg
= get_num (&opP
->disp
, 10);
3287 install_operand (s
[1], tmpreg
);
3291 /* This depends on the fact that ADDR registers are eight
3292 more than their corresponding DATA regs, so the result
3293 will have the ADDR_REG bit set. */
3294 install_operand (s
[1], opP
->reg
- DATA
);
3298 if (opP
->mode
== AINDR
)
3299 install_operand (s
[1], opP
->reg
- DATA
);
3301 install_operand (s
[1], opP
->index
.reg
- DATA
);
3305 if (opP
->reg
== FPI
)
3307 else if (opP
->reg
== FPS
)
3309 else if (opP
->reg
== FPC
)
3313 install_operand (s
[1], tmpreg
);
3316 case 'S': /* Ignore it. */
3320 install_operand (s
[1], get_num (&opP
->disp
, 30));
3323 case 'U': /* Ignore it. */
3342 as_fatal (_("failed sanity check"));
3343 } /* switch on cache token. */
3344 install_operand (s
[1], tmpreg
);
3347 /* JF: These are out of order, I fear. */
3360 install_operand (s
[1], tmpreg
);
3386 install_operand (s
[1], tmpreg
);
3390 if (opP
->reg
== VAL
)
3409 install_operand (s
[1], tmpreg
);
3423 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3434 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3440 install_operand (s
[1], tmpreg
);
3443 know (opP
->reg
== PSR
);
3446 know (opP
->reg
== PCSR
);
3461 install_operand (s
[1], tmpreg
);
3464 tmpreg
= get_num (&opP
->disp
, 20);
3465 install_operand (s
[1], tmpreg
);
3467 case '_': /* used only for move16 absolute 32-bit address. */
3468 if (isvar (&opP
->disp
))
3469 add_fix ('l', &opP
->disp
, 0, 0);
3470 tmpreg
= get_num (&opP
->disp
, 90);
3471 addword (tmpreg
>> 16);
3472 addword (tmpreg
& 0xFFFF);
3475 install_operand (s
[1], opP
->reg
- DATA0L
);
3476 opP
->reg
-= (DATA0L
);
3477 opP
->reg
&= 0x0F; /* remove upper/lower bit. */
3480 tmpreg
= get_num (&opP
->disp
, 80);
3483 install_operand (s
[1], tmpreg
);
3490 /* By the time whe get here (FINALLY) the_ins contains the complete
3491 instruction, ready to be emitted. . . */
3495 reverse_16_bits (int in
)
3500 static int mask
[16] =
3502 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3503 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3505 for (n
= 0; n
< 16; n
++)
3508 out
|= mask
[15 - n
];
3511 } /* reverse_16_bits() */
3514 reverse_8_bits (int in
)
3519 static int mask
[8] =
3521 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3524 for (n
= 0; n
< 8; n
++)
3530 } /* reverse_8_bits() */
3532 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3533 (that value is chosen in the frag_var call in md_assemble). TYPE
3534 is the subtype of the frag to be generated; its primary type is
3535 rs_machine_dependent.
3537 The TYPE parameter is also used by md_convert_frag_1 and
3538 md_estimate_size_before_relax. The appropriate type of fixup will
3539 be emitted by md_convert_frag_1.
3541 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3543 install_operand (int mode
, int val
)
3548 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge. */
3551 the_ins
.opcode
[0] |= val
<< 9;
3554 the_ins
.opcode
[1] |= val
<< 12;
3557 the_ins
.opcode
[1] |= val
<< 6;
3560 the_ins
.opcode
[1] |= val
;
3563 the_ins
.opcode
[2] |= val
<< 12;
3566 the_ins
.opcode
[2] |= val
<< 6;
3569 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3570 three words long! */
3572 the_ins
.opcode
[2] |= val
;
3575 the_ins
.opcode
[1] |= val
<< 7;
3578 the_ins
.opcode
[1] |= val
<< 10;
3582 the_ins
.opcode
[1] |= val
<< 5;
3587 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3590 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3593 the_ins
.opcode
[0] |= val
= 0xff;
3596 the_ins
.opcode
[0] |= val
<< 9;
3599 the_ins
.opcode
[1] |= val
;
3602 the_ins
.opcode
[1] |= val
;
3603 the_ins
.numo
++; /* What a hack. */
3606 the_ins
.opcode
[1] |= val
<< 4;
3614 the_ins
.opcode
[0] |= (val
<< 6);
3617 the_ins
.opcode
[1] = (val
>> 16);
3618 the_ins
.opcode
[2] = val
& 0xffff;
3621 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3622 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3623 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3625 case 'n': /* MAC/EMAC Rx on !load. */
3626 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3627 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3628 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3630 case 'o': /* MAC/EMAC Rx on load. */
3631 the_ins
.opcode
[1] |= val
<< 12;
3632 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3634 case 'M': /* MAC/EMAC Ry on !load. */
3635 the_ins
.opcode
[0] |= (val
& 0xF);
3636 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3638 case 'N': /* MAC/EMAC Ry on load. */
3639 the_ins
.opcode
[1] |= (val
& 0xF);
3640 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3643 the_ins
.opcode
[1] |= ((val
!= 1) << 10);
3646 the_ins
.opcode
[0] |= ((val
& 0x3) << 9);
3649 the_ins
.opcode
[0] |= ((val
& 0x3) << 0);
3651 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3652 the_ins
.opcode
[0] |= ((~val
& 0x1) << 7);
3653 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3655 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3656 the_ins
.opcode
[0] |= ((val
& 0x1) << 7);
3657 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3660 the_ins
.opcode
[1] |= ((val
& 0x3) << 9);
3663 the_ins
.opcode
[0] |= (val
& 0x1) <<10;
3667 as_fatal (_("failed sanity check."));
3672 install_gen_operand (int mode
, int val
)
3676 case '/': /* Special for mask loads for mac/msac insns with
3677 possible mask; trailing_ampersend set in bit 8. */
3678 the_ins
.opcode
[0] |= (val
& 0x3f);
3679 the_ins
.opcode
[1] |= (((val
& 0x100) >> 8) << 5);
3682 the_ins
.opcode
[0] |= val
;
3685 /* This is a kludge!!! */
3686 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3695 the_ins
.opcode
[0] |= val
;
3697 /* more stuff goes here. */
3699 as_fatal (_("failed sanity check."));
3703 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3704 then deal with the bitfield hack. */
3707 crack_operand (char *str
, struct m68k_op
*opP
)
3709 register int parens
;
3711 register char *beg_str
;
3719 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3725 else if (*str
== ')')
3729 opP
->error
= _("Extra )");
3735 if (flag_mri
&& *str
== '\'')
3736 inquote
= ! inquote
;
3738 if (!*str
&& parens
)
3740 opP
->error
= _("Missing )");
3745 if (m68k_ip_op (beg_str
, opP
) != 0)
3752 c
= *++str
; /* JF bitfield hack. */
3757 as_bad (_("Missing operand"));
3760 /* Detect MRI REG symbols and convert them to REGLSTs. */
3761 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
3764 opP
->mask
= ~(int)opP
->reg
;
3771 /* This is the guts of the machine-dependent assembler. STR points to a
3772 machine dependent instruction. This function is supposed to emit
3773 the frags/bytes it assembles to.
3777 insert_reg (const char *regname
, int regnum
)
3782 #ifdef REGISTER_PREFIX
3783 if (!flag_reg_prefix_optional
)
3785 buf
[0] = REGISTER_PREFIX
;
3786 strcpy (buf
+ 1, regname
);
3791 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
3792 &zero_address_frag
));
3794 for (i
= 0; regname
[i
]; i
++)
3795 buf
[i
] = TOUPPER (regname
[i
]);
3798 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
3799 &zero_address_frag
));
3808 static const struct init_entry init_table
[] =
3868 { "accext01", ACCEXT01
},
3869 { "accext23", ACCEXT23
},
3873 /* Control registers. */
3874 { "sfc", SFC
}, /* Source Function Code. */
3876 { "dfc", DFC
}, /* Destination Function Code. */
3878 { "cacr", CACR
}, /* Cache Control Register. */
3879 { "caar", CAAR
}, /* Cache Address Register. */
3881 { "usp", USP
}, /* User Stack Pointer. */
3882 { "vbr", VBR
}, /* Vector Base Register. */
3883 { "msp", MSP
}, /* Master Stack Pointer. */
3884 { "isp", ISP
}, /* Interrupt Stack Pointer. */
3886 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0. */
3887 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1. */
3888 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0. */
3889 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1. */
3891 /* 68ec040 versions of same */
3892 { "iacr0", ITT0
}, /* Instruction Access Control Register 0. */
3893 { "iacr1", ITT1
}, /* Instruction Access Control Register 0. */
3894 { "dacr0", DTT0
}, /* Data Access Control Register 0. */
3895 { "dacr1", DTT1
}, /* Data Access Control Register 0. */
3897 /* Coldfire versions of same. The ColdFire programmer's reference
3898 manual indicated that the order is 2,3,0,1, but Ken Rose
3899 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3900 { "acr0", ACR0
}, /* Access Control Unit 0. */
3901 { "acr1", ACR1
}, /* Access Control Unit 1. */
3902 { "acr2", ACR2
}, /* Access Control Unit 2. */
3903 { "acr3", ACR3
}, /* Access Control Unit 3. */
3905 { "tc", TC
}, /* MMU Translation Control Register. */
3909 { "mmusr", MMUSR
}, /* MMU Status Register. */
3910 { "srp", SRP
}, /* User Root Pointer. */
3911 { "urp", URP
}, /* Supervisor Root Pointer. */
3914 { "mmubar", MMUBAR
},
3917 { "rombar", ROMBAR
}, /* ROM Base Address Register. */
3918 { "rambar0", RAMBAR0
}, /* ROM Base Address Register. */
3919 { "rambar1", RAMBAR1
}, /* ROM Base Address Register. */
3920 { "mbar", MBAR
}, /* Module Base Address Register. */
3922 { "mbar0", MBAR0
}, /* mcfv4e registers. */
3923 { "mbar1", MBAR1
}, /* mcfv4e registers. */
3924 { "rombar0", ROMBAR0
}, /* mcfv4e registers. */
3925 { "rombar1", ROMBAR1
}, /* mcfv4e registers. */
3926 { "mpcr", MPCR
}, /* mcfv4e registers. */
3927 { "edrambar", EDRAMBAR
}, /* mcfv4e registers. */
3928 { "secmbar", SECMBAR
}, /* mcfv4e registers. */
3929 { "asid", TC
}, /* mcfv4e registers. */
3930 { "mmubar", BUSCR
}, /* mcfv4e registers. */
3931 { "pcr1u0", PCR1U0
}, /* mcfv4e registers. */
3932 { "pcr1l0", PCR1L0
}, /* mcfv4e registers. */
3933 { "pcr2u0", PCR2U0
}, /* mcfv4e registers. */
3934 { "pcr2l0", PCR2L0
}, /* mcfv4e registers. */
3935 { "pcr3u0", PCR3U0
}, /* mcfv4e registers. */
3936 { "pcr3l0", PCR3L0
}, /* mcfv4e registers. */
3937 { "pcr1u1", PCR1U1
}, /* mcfv4e registers. */
3938 { "pcr1l1", PCR1L1
}, /* mcfv4e registers. */
3939 { "pcr2u1", PCR2U1
}, /* mcfv4e registers. */
3940 { "pcr2l1", PCR2L1
}, /* mcfv4e registers. */
3941 { "pcr3u1", PCR3U1
}, /* mcfv4e registers. */
3942 { "pcr3l1", PCR3L1
}, /* mcfv4e registers. */
3944 { "flashbar", FLASHBAR
}, /* mcf528x registers. */
3945 { "rambar", RAMBAR
}, /* mcf528x registers. */
3947 { "mbar2", MBAR2
}, /* mcf5249 registers. */
3949 { "cac", CAC
}, /* fido registers. */
3950 { "mbb", MBB
}, /* fido registers. */
3951 /* End of control registers. */
3985 /* 68ec030 versions of same. */
3988 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3991 /* Suppressed data and address registers. */
4009 /* Upper and lower data and address registers, used by macw and msacw. */
4050 init_regtable (void)
4053 for (i
= 0; init_table
[i
].name
; i
++)
4054 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
4058 md_assemble (char *str
)
4065 int shorts_this_frag
;
4068 if (!selected_cpu
&& !selected_arch
)
4070 /* We've not selected an architecture yet. Set the default
4071 now. We do this lazily so that an initial .cpu or .arch directive
4073 if (!m68k_set_cpu (TARGET_CPU
, 1, 1))
4074 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU
);
4079 /* In MRI mode, the instruction and operands are separated by a
4080 space. Anything following the operands is a comment. The label
4081 has already been removed. */
4089 for (s
= str
; *s
!= '\0'; s
++)
4091 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
4109 inquote
= ! inquote
;
4114 memset (&the_ins
, '\0', sizeof (the_ins
));
4119 for (n
= 0; n
< the_ins
.numargs
; n
++)
4120 if (the_ins
.operands
[n
].error
)
4122 er
= the_ins
.operands
[n
].error
;
4128 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
4132 /* If there is a current label, record that it marks an instruction. */
4133 if (current_label
!= NULL
)
4135 current_label
->text
= 1;
4136 current_label
= NULL
;
4140 /* Tie dwarf2 debug info to the address at the start of the insn. */
4141 dwarf2_emit_insn (0);
4144 if (the_ins
.nfrag
== 0)
4146 /* No frag hacking involved; just put it out. */
4147 toP
= frag_more (2 * the_ins
.numo
);
4148 fromP
= &the_ins
.opcode
[0];
4149 for (m
= the_ins
.numo
; m
; --m
)
4151 md_number_to_chars (toP
, (long) (*fromP
), 2);
4155 /* Put out symbol-dependent info. */
4156 for (m
= 0; m
< the_ins
.nrel
; m
++)
4158 switch (the_ins
.reloc
[m
].wid
)
4177 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4178 the_ins
.reloc
[m
].wid
);
4181 fixP
= fix_new_exp (frag_now
,
4182 ((toP
- frag_now
->fr_literal
)
4183 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4185 &the_ins
.reloc
[m
].exp
,
4186 the_ins
.reloc
[m
].pcrel
,
4187 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
4188 the_ins
.reloc
[m
].pic_reloc
));
4189 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4190 if (the_ins
.reloc
[m
].wid
== 'B')
4191 fixP
->fx_signed
= 1;
4196 /* There's some frag hacking. */
4198 /* Calculate the max frag size. */
4201 wid
= 2 * the_ins
.fragb
[0].fragoff
;
4202 for (n
= 1; n
< the_ins
.nfrag
; n
++)
4203 wid
+= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4204 /* frag_var part. */
4206 /* Make sure the whole insn fits in one chunk, in particular that
4207 the var part is attached, as we access one byte before the
4208 variable frag for byte branches. */
4212 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
4217 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
4219 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4220 toP
= frag_more (wid
);
4222 shorts_this_frag
= 0;
4223 for (m
= wid
/ 2; m
; --m
)
4225 md_number_to_chars (toP
, (long) (*fromP
), 2);
4230 for (m
= 0; m
< the_ins
.nrel
; m
++)
4232 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
4234 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
4237 wid
= the_ins
.reloc
[m
].wid
;
4240 the_ins
.reloc
[m
].wid
= 0;
4241 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4243 fixP
= fix_new_exp (frag_now
,
4244 ((toP
- frag_now
->fr_literal
)
4245 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4247 &the_ins
.reloc
[m
].exp
,
4248 the_ins
.reloc
[m
].pcrel
,
4249 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4250 the_ins
.reloc
[m
].pic_reloc
));
4251 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4253 (void) frag_var (rs_machine_dependent
, 10, 0,
4254 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
4255 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
4257 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4258 shorts_this_frag
= 0;
4261 toP
= frag_more (n
* 2);
4264 md_number_to_chars (toP
, (long) (*fromP
), 2);
4270 for (m
= 0; m
< the_ins
.nrel
; m
++)
4274 wid
= the_ins
.reloc
[m
].wid
;
4277 the_ins
.reloc
[m
].wid
= 0;
4278 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4280 fixP
= fix_new_exp (frag_now
,
4281 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
4282 - shorts_this_frag
* 2),
4284 &the_ins
.reloc
[m
].exp
,
4285 the_ins
.reloc
[m
].pcrel
,
4286 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4287 the_ins
.reloc
[m
].pic_reloc
));
4288 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4292 /* Comparison function used by qsort to rank the opcode entries by name. */
4295 m68k_compare_opcode (const void * v1
, const void * v2
)
4297 struct m68k_opcode
* op1
, * op2
;
4303 op1
= *(struct m68k_opcode
**) v1
;
4304 op2
= *(struct m68k_opcode
**) v2
;
4306 /* Compare the two names. If different, return the comparison.
4307 If the same, return the order they are in the opcode table. */
4308 ret
= strcmp (op1
->name
, op2
->name
);
4319 const struct m68k_opcode
*ins
;
4320 struct m68k_incant
*hack
, *slak
;
4321 const char *retval
= 0; /* Empty string, or error msg text. */
4324 /* Set up hash tables with 68000 instructions.
4325 similar to what the vax assembler does. */
4326 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4327 a copy of it at runtime, adding in the information we want but isn't
4328 there. I think it'd be better to have an awk script hack the table
4329 at compile time. Or even just xstr the table and use it as-is. But
4330 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4335 flag_reg_prefix_optional
= 1;
4337 if (! m68k_rel32_from_cmdline
)
4341 /* First sort the opcode table into alphabetical order to seperate
4342 the order that the assembler wants to see the opcodes from the
4343 order that the disassembler wants to see them. */
4344 m68k_sorted_opcodes
= xmalloc (m68k_numopcodes
* sizeof (* m68k_sorted_opcodes
));
4345 if (!m68k_sorted_opcodes
)
4346 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4347 m68k_numopcodes
* ((int) sizeof (* m68k_sorted_opcodes
)));
4349 for (i
= m68k_numopcodes
; i
--;)
4350 m68k_sorted_opcodes
[i
] = m68k_opcodes
+ i
;
4352 qsort (m68k_sorted_opcodes
, m68k_numopcodes
,
4353 sizeof (m68k_sorted_opcodes
[0]), m68k_compare_opcode
);
4355 op_hash
= hash_new ();
4357 obstack_begin (&robyn
, 4000);
4358 for (i
= 0; i
< m68k_numopcodes
; i
++)
4360 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4363 ins
= m68k_sorted_opcodes
[i
];
4365 /* We *could* ignore insns that don't match our
4366 arch here by just leaving them out of the hash. */
4367 slak
->m_operands
= ins
->args
;
4368 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
4369 slak
->m_arch
= ins
->arch
;
4370 slak
->m_opcode
= ins
->opcode
;
4371 /* This is kludgey. */
4372 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
4373 if (i
+ 1 != m68k_numopcodes
4374 && !strcmp (ins
->name
, m68k_sorted_opcodes
[i
+ 1]->name
))
4376 slak
->m_next
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4381 slak
= slak
->m_next
;
4385 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
4387 as_fatal (_("Internal Error: Can't hash %s: %s"), ins
->name
, retval
);
4390 for (i
= 0; i
< m68k_numaliases
; i
++)
4392 const char *name
= m68k_opcode_aliases
[i
].primary
;
4393 const char *alias
= m68k_opcode_aliases
[i
].alias
;
4394 PTR val
= hash_find (op_hash
, name
);
4397 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4398 retval
= hash_insert (op_hash
, alias
, val
);
4400 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4403 /* In MRI mode, all unsized branches are variable sized. Normally,
4404 they are word sized. */
4407 static struct m68k_opcode_alias mri_aliases
[] =
4428 i
< (int) (sizeof mri_aliases
/ sizeof mri_aliases
[0]);
4431 const char *name
= mri_aliases
[i
].primary
;
4432 const char *alias
= mri_aliases
[i
].alias
;
4433 PTR val
= hash_find (op_hash
, name
);
4436 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4437 retval
= hash_jam (op_hash
, alias
, val
);
4439 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4443 for (i
= 0; i
< (int) sizeof (notend_table
); i
++)
4445 notend_table
[i
] = 0;
4446 alt_notend_table
[i
] = 0;
4449 notend_table
[','] = 1;
4450 notend_table
['{'] = 1;
4451 notend_table
['}'] = 1;
4452 alt_notend_table
['a'] = 1;
4453 alt_notend_table
['A'] = 1;
4454 alt_notend_table
['d'] = 1;
4455 alt_notend_table
['D'] = 1;
4456 alt_notend_table
['#'] = 1;
4457 alt_notend_table
['&'] = 1;
4458 alt_notend_table
['f'] = 1;
4459 alt_notend_table
['F'] = 1;
4460 #ifdef REGISTER_PREFIX
4461 alt_notend_table
[REGISTER_PREFIX
] = 1;
4464 /* We need to put '(' in alt_notend_table to handle
4465 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4466 alt_notend_table
['('] = 1;
4468 /* We need to put '@' in alt_notend_table to handle
4469 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4470 alt_notend_table
['@'] = 1;
4472 /* We need to put digits in alt_notend_table to handle
4473 bfextu %d0{24:1},%d0 */
4474 alt_notend_table
['0'] = 1;
4475 alt_notend_table
['1'] = 1;
4476 alt_notend_table
['2'] = 1;
4477 alt_notend_table
['3'] = 1;
4478 alt_notend_table
['4'] = 1;
4479 alt_notend_table
['5'] = 1;
4480 alt_notend_table
['6'] = 1;
4481 alt_notend_table
['7'] = 1;
4482 alt_notend_table
['8'] = 1;
4483 alt_notend_table
['9'] = 1;
4485 #ifndef MIT_SYNTAX_ONLY
4486 /* Insert pseudo ops, these have to go into the opcode table since
4487 gas expects pseudo ops to start with a dot. */
4491 while (mote_pseudo_table
[n
].poc_name
)
4493 hack
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4494 hash_insert (op_hash
,
4495 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
4496 hack
->m_operands
= 0;
4506 record_alignment (text_section
, 2);
4507 record_alignment (data_section
, 2);
4508 record_alignment (bss_section
, 2);
4513 /* This is called when a label is defined. */
4516 m68k_frob_label (symbolS
*sym
)
4518 struct label_line
*n
;
4520 n
= (struct label_line
*) xmalloc (sizeof *n
);
4523 as_where (&n
->file
, &n
->line
);
4529 dwarf2_emit_label (sym
);
4533 /* This is called when a value that is not an instruction is emitted. */
4536 m68k_flush_pending_output (void)
4538 current_label
= NULL
;
4541 /* This is called at the end of the assembly, when the final value of
4542 the label is known. We warn if this is a text symbol aligned at an
4546 m68k_frob_symbol (symbolS
*sym
)
4548 if (S_GET_SEGMENT (sym
) == reg_section
4549 && (int) S_GET_VALUE (sym
) < 0)
4551 S_SET_SEGMENT (sym
, absolute_section
);
4552 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
4554 else if ((S_GET_VALUE (sym
) & 1) != 0)
4556 struct label_line
*l
;
4558 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4560 if (l
->label
== sym
)
4563 as_warn_where (l
->file
, l
->line
,
4564 _("text label `%s' aligned to odd boundary"),
4572 /* This is called if we go in or out of MRI mode because of the .mri
4576 m68k_mri_mode_change (int on
)
4580 if (! flag_reg_prefix_optional
)
4582 flag_reg_prefix_optional
= 1;
4583 #ifdef REGISTER_PREFIX
4588 if (! m68k_rel32_from_cmdline
)
4593 if (! reg_prefix_optional_seen
)
4595 #ifdef REGISTER_PREFIX_OPTIONAL
4596 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
4598 flag_reg_prefix_optional
= 0;
4600 #ifdef REGISTER_PREFIX
4605 if (! m68k_rel32_from_cmdline
)
4610 /* Equal to MAX_PRECISION in atof-ieee.c. */
4611 #define MAX_LITTLENUMS 6
4613 /* Turn a string in input_line_pointer into a floating point constant
4614 of type TYPE, and store the appropriate bytes in *LITP. The number
4615 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4616 returned, or NULL on OK. */
4619 md_atof (int type
, char *litP
, int *sizeP
)
4622 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4623 LITTLENUM_TYPE
*wordP
;
4654 return _("Bad call to MD_ATOF()");
4656 t
= atof_ieee (input_line_pointer
, type
, words
);
4658 input_line_pointer
= t
;
4660 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4661 for (wordP
= words
; prec
--;)
4663 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
4664 litP
+= sizeof (LITTLENUM_TYPE
);
4670 md_number_to_chars (char *buf
, valueT val
, int n
)
4672 number_to_chars_bigendian (buf
, val
, n
);
4676 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4678 offsetT val
= *valP
;
4679 addressT upper_limit
;
4680 offsetT lower_limit
;
4682 /* This is unnecessary but it convinces the native rs6000 compiler
4683 to generate the code we want. */
4684 char *buf
= fixP
->fx_frag
->fr_literal
;
4685 buf
+= fixP
->fx_where
;
4686 /* End ibm compiler workaround. */
4690 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4696 memset (buf
, 0, fixP
->fx_size
);
4697 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4699 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4700 && !S_IS_DEFINED (fixP
->fx_addsy
)
4701 && !S_IS_WEAK (fixP
->fx_addsy
))
4702 S_SET_WEAK (fixP
->fx_addsy
);
4705 #elif defined(OBJ_AOUT)
4706 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4707 if (fixP
->fx_addsy
&& S_IS_WEAK (fixP
->fx_addsy
))
4709 memset (buf
, 0, fixP
->fx_size
);
4710 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4715 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4716 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4719 switch (fixP
->fx_size
)
4721 /* The cast to offsetT below are necessary to make code
4722 correct for machines where ints are smaller than offsetT. */
4726 lower_limit
= - (offsetT
) 0x80;
4729 *buf
++ = (val
>> 8);
4731 upper_limit
= 0x7fff;
4732 lower_limit
= - (offsetT
) 0x8000;
4735 *buf
++ = (val
>> 24);
4736 *buf
++ = (val
>> 16);
4737 *buf
++ = (val
>> 8);
4739 upper_limit
= 0x7fffffff;
4740 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* Avoid constant overflow. */
4743 BAD_CASE (fixP
->fx_size
);
4746 /* Fix up a negative reloc. */
4747 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4749 fixP
->fx_addsy
= fixP
->fx_subsy
;
4750 fixP
->fx_subsy
= NULL
;
4754 /* For non-pc-relative values, it's conceivable we might get something
4755 like "0xff" for a byte field. So extend the upper part of the range
4756 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4757 so that we can do any range checking at all. */
4758 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
4759 upper_limit
= upper_limit
* 2 + 1;
4761 if ((addressT
) val
> upper_limit
4762 && (val
> 0 || val
< lower_limit
))
4763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("value out of range"));
4765 /* A one byte PC-relative reloc means a short branch. We can't use
4766 a short branch with a value of 0 or -1, because those indicate
4767 different opcodes (branches with longer offsets). fixup_segment
4768 in write.c may have clobbered fx_pcrel, so we need to examine the
4771 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4772 && fixP
->fx_size
== 1
4773 && (fixP
->fx_addsy
== NULL
4774 || S_IS_DEFINED (fixP
->fx_addsy
))
4775 && (val
== 0 || val
== -1))
4776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("invalid byte branch offset"));
4779 /* *fragP has been relaxed to its final size, and now needs to have
4780 the bytes inside it modified to conform to the new size There is UGLY
4784 md_convert_frag_1 (fragS
*fragP
)
4789 /* Address in object code of the displacement. */
4790 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4792 /* Address in gas core of the place to store the displacement. */
4793 /* This convinces the native rs6000 compiler to generate the code we
4795 register char *buffer_address
= fragP
->fr_literal
;
4796 buffer_address
+= fragP
->fr_fix
;
4797 /* End ibm compiler workaround. */
4799 /* The displacement of the address, from current location. */
4800 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4801 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4803 switch (fragP
->fr_subtype
)
4805 case TAB (BRANCHBWL
, BYTE
):
4806 case TAB (BRABSJUNC
, BYTE
):
4807 case TAB (BRABSJCOND
, BYTE
):
4808 case TAB (BRANCHBW
, BYTE
):
4809 know (issbyte (disp
));
4811 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4812 _("short branch with zero offset: use :w"));
4813 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4814 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4815 fixP
->fx_pcrel_adjust
= -1;
4817 case TAB (BRANCHBWL
, SHORT
):
4818 case TAB (BRABSJUNC
, SHORT
):
4819 case TAB (BRABSJCOND
, SHORT
):
4820 case TAB (BRANCHBW
, SHORT
):
4821 fragP
->fr_opcode
[1] = 0x00;
4822 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4823 1, RELAX_RELOC_PC16
);
4826 case TAB (BRANCHBWL
, LONG
):
4827 fragP
->fr_opcode
[1] = (char) 0xFF;
4828 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4829 1, RELAX_RELOC_PC32
);
4832 case TAB (BRABSJUNC
, LONG
):
4833 if (fragP
->fr_opcode
[0] == 0x61) /* jbsr */
4835 if (flag_keep_pcrel
)
4836 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4837 fragP
->fr_opcode
[0] = 0x4E;
4838 fragP
->fr_opcode
[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4839 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4840 0, RELAX_RELOC_ABS32
);
4843 else if (fragP
->fr_opcode
[0] == 0x60) /* jbra */
4845 if (flag_keep_pcrel
)
4846 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4847 fragP
->fr_opcode
[0] = 0x4E;
4848 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4849 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4850 0, RELAX_RELOC_ABS32
);
4855 /* This cannot happen, because jbsr and jbra are the only two
4856 unconditional branches. */
4860 case TAB (BRABSJCOND
, LONG
):
4861 if (flag_keep_pcrel
)
4862 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4864 /* Only Bcc 68000 instructions can come here
4865 Change bcc into b!cc/jmp absl long. */
4866 fragP
->fr_opcode
[0] ^= 0x01; /* Invert bcc. */
4867 fragP
->fr_opcode
[1] = 0x06; /* Branch offset = 6. */
4869 /* JF: these used to be fr_opcode[2,3], but they may be in a
4870 different frag, in which case referring to them is a no-no.
4871 Only fr_opcode[0,1] are guaranteed to work. */
4872 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4873 *buffer_address
++ = (char) 0xf9;
4874 fragP
->fr_fix
+= 2; /* Account for jmp instruction. */
4875 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4876 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
4879 case TAB (FBRANCH
, SHORT
):
4880 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4881 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4882 1, RELAX_RELOC_PC16
);
4885 case TAB (FBRANCH
, LONG
):
4886 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit. */
4887 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4888 1, RELAX_RELOC_PC32
);
4891 case TAB (DBCCLBR
, SHORT
):
4892 case TAB (DBCCABSJ
, SHORT
):
4893 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4894 1, RELAX_RELOC_PC16
);
4897 case TAB (DBCCLBR
, LONG
):
4898 /* Only DBcc instructions can come here.
4899 Change dbcc into dbcc/bral.
4900 JF: these used to be fr_opcode[2-7], but that's wrong. */
4901 if (flag_keep_pcrel
)
4902 as_fatal (_("Tried to convert DBcc to absolute jump"));
4904 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4905 *buffer_address
++ = 0x04;
4906 *buffer_address
++ = 0x60; /* Put in bra pc+6. */
4907 *buffer_address
++ = 0x06;
4908 *buffer_address
++ = 0x60; /* Put in bral (0x60ff). */
4909 *buffer_address
++ = (char) 0xff;
4911 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4912 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 1,
4916 case TAB (DBCCABSJ
, LONG
):
4917 /* Only DBcc instructions can come here.
4918 Change dbcc into dbcc/jmp.
4919 JF: these used to be fr_opcode[2-7], but that's wrong. */
4920 if (flag_keep_pcrel
)
4921 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4923 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4924 *buffer_address
++ = 0x04;
4925 *buffer_address
++ = 0x60; /* Put in bra pc + 6. */
4926 *buffer_address
++ = 0x06;
4927 *buffer_address
++ = 0x4e; /* Put in jmp long (0x4ef9). */
4928 *buffer_address
++ = (char) 0xf9;
4930 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4931 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 0,
4935 case TAB (PCREL1632
, SHORT
):
4936 fragP
->fr_opcode
[1] &= ~0x3F;
4937 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
4938 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4939 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4942 case TAB (PCREL1632
, LONG
):
4943 /* Already set to mode 7.3; this indicates: PC indirect with
4944 suppressed index, 32-bit displacement. */
4945 *buffer_address
++ = 0x01;
4946 *buffer_address
++ = 0x70;
4948 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4949 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4950 fixP
->fx_pcrel_adjust
= 2;
4953 case TAB (PCINDEX
, BYTE
):
4954 assert (fragP
->fr_fix
>= 2);
4955 buffer_address
[-2] &= ~1;
4956 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4957 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4958 fixP
->fx_pcrel_adjust
= 1;
4960 case TAB (PCINDEX
, SHORT
):
4961 assert (fragP
->fr_fix
>= 2);
4962 buffer_address
[-2] |= 0x1;
4963 buffer_address
[-1] = 0x20;
4964 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4965 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4966 fixP
->fx_pcrel_adjust
= 2;
4969 case TAB (PCINDEX
, LONG
):
4970 assert (fragP
->fr_fix
>= 2);
4971 buffer_address
[-2] |= 0x1;
4972 buffer_address
[-1] = 0x30;
4973 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4974 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4975 fixP
->fx_pcrel_adjust
= 2;
4978 case TAB (ABSTOPCREL
, SHORT
):
4979 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4980 1, RELAX_RELOC_PC16
);
4983 case TAB (ABSTOPCREL
, LONG
):
4984 if (flag_keep_pcrel
)
4985 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4986 /* The thing to do here is force it to ABSOLUTE LONG, since
4987 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4988 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
4990 fragP
->fr_opcode
[1] &= ~0x3F;
4991 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
4992 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4993 0, RELAX_RELOC_ABS32
);
5000 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
5001 segT sec ATTRIBUTE_UNUSED
,
5004 md_convert_frag_1 (fragP
);
5007 /* Force truly undefined symbols to their maximum size, and generally set up
5008 the frag list to be relaxed
5011 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
5013 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5014 switch (fragP
->fr_subtype
)
5016 case TAB (BRANCHBWL
, SZ_UNDEF
):
5017 case TAB (BRABSJUNC
, SZ_UNDEF
):
5018 case TAB (BRABSJCOND
, SZ_UNDEF
):
5020 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5021 && relaxable_symbol (fragP
->fr_symbol
))
5023 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
5025 else if (flag_short_refs
)
5027 /* Symbol is undefined and we want short ref. */
5028 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5032 /* Symbol is still undefined. Make it LONG. */
5033 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
5038 case TAB (BRANCHBW
, SZ_UNDEF
):
5040 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5041 && relaxable_symbol (fragP
->fr_symbol
))
5043 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
5047 /* Symbol is undefined and we don't have long branches. */
5048 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5053 case TAB (FBRANCH
, SZ_UNDEF
):
5054 case TAB (DBCCLBR
, SZ_UNDEF
):
5055 case TAB (DBCCABSJ
, SZ_UNDEF
):
5056 case TAB (PCREL1632
, SZ_UNDEF
):
5058 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5059 && relaxable_symbol (fragP
->fr_symbol
))
5062 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5066 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
5071 case TAB (PCINDEX
, SZ_UNDEF
):
5072 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5073 && relaxable_symbol (fragP
->fr_symbol
)))
5075 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
5079 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
5083 case TAB (ABSTOPCREL
, SZ_UNDEF
):
5085 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5086 && relaxable_symbol (fragP
->fr_symbol
)))
5088 fragP
->fr_subtype
= TAB (ABSTOPCREL
, SHORT
);
5092 fragP
->fr_subtype
= TAB (ABSTOPCREL
, LONG
);
5101 /* Now that SZ_UNDEF are taken care of, check others. */
5102 switch (fragP
->fr_subtype
)
5104 case TAB (BRANCHBWL
, BYTE
):
5105 case TAB (BRABSJUNC
, BYTE
):
5106 case TAB (BRABSJCOND
, BYTE
):
5107 case TAB (BRANCHBW
, BYTE
):
5108 /* We can't do a short jump to the next instruction, so in that
5109 case we force word mode. If the symbol is at the start of a
5110 frag, and it is the next frag with any data in it (usually
5111 this is just the next frag, but assembler listings may
5112 introduce empty frags), we must use word mode. */
5113 if (fragP
->fr_symbol
)
5117 sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
5118 if (S_GET_VALUE (fragP
->fr_symbol
) == sym_frag
->fr_address
)
5122 for (l
= fragP
->fr_next
; l
&& l
!= sym_frag
; l
= l
->fr_next
)
5126 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5133 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5136 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5137 /* the bit-field entries in the relocation_info struct plays hell
5138 with the byte-order problems of cross-assembly. So as a hack,
5139 I added this mach. dependent ri twiddler. Ugly, but it gets
5141 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5142 are symbolnum, most sig. byte first. Last byte is broken up with
5143 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5144 nibble as nuthin. (on Sun 3 at least) */
5145 /* Translate the internal relocation information into target-specific
5149 md_ri_to_chars (char *the_bytes
, struct reloc_info_generic
*ri
)
5152 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
5153 /* Now the fun stuff. */
5154 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
5155 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
5156 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
5157 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80)
5158 | ((ri
->r_length
<< 5) & 0x60)
5159 | ((ri
->r_extern
<< 4) & 0x10));
5164 #endif /* OBJ_AOUT or OBJ_BOUT */
5166 #ifndef WORKING_DOT_WORD
5167 int md_short_jump_size
= 4;
5168 int md_long_jump_size
= 6;
5171 md_create_short_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5172 fragS
*frag ATTRIBUTE_UNUSED
,
5173 symbolS
*to_symbol ATTRIBUTE_UNUSED
)
5177 offset
= to_addr
- (from_addr
+ 2);
5179 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
5180 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
5184 md_create_long_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5185 fragS
*frag
, symbolS
*to_symbol
)
5189 if (!HAVE_LONG_BRANCH (current_architecture
))
5191 if (flag_keep_pcrel
)
5192 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5193 offset
= to_addr
- S_GET_VALUE (to_symbol
);
5194 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
5195 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5196 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
5201 offset
= to_addr
- (from_addr
+ 2);
5202 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
5203 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5209 /* Different values of OK tell what its OK to return. Things that
5210 aren't OK are an error (what a shock, no?)
5213 10: Absolute 1:8 only
5214 20: Absolute 0:7 only
5215 30: absolute 0:15 only
5216 40: Absolute 0:31 only
5217 50: absolute 0:127 only
5218 55: absolute -64:63 only
5219 60: absolute -128:127 only
5220 70: absolute 0:4095 only
5221 80: absolute -1, 1:7 only
5225 get_num (struct m68k_exp
*exp
, int ok
)
5227 if (exp
->exp
.X_op
== O_absent
)
5229 /* Do the same thing the VAX asm does. */
5230 op (exp
) = O_constant
;
5236 as_warn (_("expression out of range: defaulting to 1"));
5240 else if (exp
->exp
.X_op
== O_constant
)
5245 if ((valueT
) TRUNC (offs (exp
)) - 1 > 7)
5247 as_warn (_("expression out of range: defaulting to 1"));
5252 if ((valueT
) TRUNC (offs (exp
)) > 7)
5256 if ((valueT
) TRUNC (offs (exp
)) > 15)
5260 if ((valueT
) TRUNC (offs (exp
)) > 32)
5264 if ((valueT
) TRUNC (offs (exp
)) > 127)
5268 if ((valueT
) SEXT (offs (exp
)) + 64 > 127)
5272 if ((valueT
) SEXT (offs (exp
)) + 128 > 255)
5276 if ((valueT
) TRUNC (offs (exp
)) > 4095)
5279 as_warn (_("expression out of range: defaulting to 0"));
5284 if ((valueT
) TRUNC (offs (exp
)) != 0xffffffff
5285 && (valueT
) TRUNC (offs (exp
)) - 1 > 6)
5287 as_warn (_("expression out of range: defaulting to 1"));
5295 else if (exp
->exp
.X_op
== O_big
)
5297 if (offs (exp
) <= 0 /* flonum. */
5298 && (ok
== 90 /* no bignums */
5299 || (ok
> 10 /* Small-int ranges including 0 ok. */
5300 /* If we have a flonum zero, a zero integer should
5301 do as well (e.g., in moveq). */
5302 && generic_floating_point_number
.exponent
== 0
5303 && generic_floating_point_number
.low
[0] == 0)))
5305 /* HACK! Turn it into a long. */
5306 LITTLENUM_TYPE words
[6];
5308 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
5309 op (exp
) = O_constant
;
5312 offs (exp
) = words
[1] | (words
[0] << 16);
5316 op (exp
) = O_constant
;
5319 offs (exp
) = (ok
== 10) ? 1 : 0;
5320 as_warn (_("Can't deal with expression; defaulting to %ld"),
5326 if (ok
>= 10 && ok
<= 80)
5328 op (exp
) = O_constant
;
5331 offs (exp
) = (ok
== 10) ? 1 : 0;
5332 as_warn (_("Can't deal with expression; defaulting to %ld"),
5337 if (exp
->size
!= SIZE_UNSPEC
)
5345 if (!isbyte (offs (exp
)))
5346 as_warn (_("expression doesn't fit in BYTE"));
5349 if (!isword (offs (exp
)))
5350 as_warn (_("expression doesn't fit in WORD"));
5358 /* These are the back-ends for the various machine dependent pseudo-ops. */
5361 s_data1 (int ignore ATTRIBUTE_UNUSED
)
5363 subseg_set (data_section
, 1);
5364 demand_empty_rest_of_line ();
5368 s_data2 (int ignore ATTRIBUTE_UNUSED
)
5370 subseg_set (data_section
, 2);
5371 demand_empty_rest_of_line ();
5375 s_bss (int ignore ATTRIBUTE_UNUSED
)
5377 /* We don't support putting frags in the BSS segment, we fake it
5378 by marking in_bss, then looking at s_skip for clues. */
5380 subseg_set (bss_section
, 0);
5381 demand_empty_rest_of_line ();
5385 s_even (int ignore ATTRIBUTE_UNUSED
)
5388 register long temp_fill
;
5390 temp
= 1; /* JF should be 2? */
5391 temp_fill
= get_absolute_expression ();
5392 if (!need_pass_2
) /* Never make frag if expect extra pass. */
5393 frag_align (temp
, (int) temp_fill
, 0);
5394 demand_empty_rest_of_line ();
5395 record_alignment (now_seg
, temp
);
5399 s_proc (int ignore ATTRIBUTE_UNUSED
)
5401 demand_empty_rest_of_line ();
5404 /* Pseudo-ops handled for MRI compatibility. */
5406 /* This function returns non-zero if the argument is a conditional
5407 pseudo-op. This is called when checking whether a pending
5408 alignment is needed. */
5411 m68k_conditional_pseudoop (pseudo_typeS
*pop
)
5413 return (pop
->poc_handler
== s_mri_if
5414 || pop
->poc_handler
== s_mri_else
);
5417 /* Handle an MRI style chip specification. */
5426 s
= input_line_pointer
;
5427 /* We can't use get_symbol_end since the processor names are not proper
5429 while (is_part_of_name (c
= *input_line_pointer
++))
5431 *--input_line_pointer
= 0;
5432 for (i
= 0; m68k_cpus
[i
].name
; i
++)
5433 if (strcasecmp (s
, m68k_cpus
[i
].name
) == 0)
5435 if (!m68k_cpus
[i
].name
)
5437 as_bad (_("%s: unrecognized processor name"), s
);
5438 *input_line_pointer
= c
;
5439 ignore_rest_of_line ();
5442 *input_line_pointer
= c
;
5444 if (*input_line_pointer
== '/')
5445 current_architecture
= 0;
5447 current_architecture
&= m68881
| m68851
;
5448 current_architecture
|= m68k_cpus
[i
].arch
& ~(m68881
| m68851
);
5449 control_regs
= m68k_cpus
[i
].control_regs
;
5451 while (*input_line_pointer
== '/')
5453 ++input_line_pointer
;
5454 s
= input_line_pointer
;
5455 /* We can't use get_symbol_end since the processor names are not
5457 while (is_part_of_name (c
= *input_line_pointer
++))
5459 *--input_line_pointer
= 0;
5460 if (strcmp (s
, "68881") == 0)
5461 current_architecture
|= m68881
;
5462 else if (strcmp (s
, "68851") == 0)
5463 current_architecture
|= m68851
;
5464 *input_line_pointer
= c
;
5468 /* The MRI CHIP pseudo-op. */
5471 s_chip (int ignore ATTRIBUTE_UNUSED
)
5477 stop
= mri_comment_field (&stopc
);
5480 mri_comment_end (stop
, stopc
);
5481 demand_empty_rest_of_line ();
5484 /* The MRI FOPT pseudo-op. */
5487 s_fopt (int ignore ATTRIBUTE_UNUSED
)
5491 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
5495 input_line_pointer
+= 3;
5496 temp
= get_absolute_expression ();
5497 if (temp
< 0 || temp
> 7)
5498 as_bad (_("bad coprocessor id"));
5500 m68k_float_copnum
= COP0
+ temp
;
5504 as_bad (_("unrecognized fopt option"));
5505 ignore_rest_of_line ();
5509 demand_empty_rest_of_line ();
5512 /* The structure used to handle the MRI OPT pseudo-op. */
5516 /* The name of the option. */
5519 /* If this is not NULL, just call this function. The first argument
5520 is the ARG field of this structure, the second argument is
5521 whether the option was negated. */
5522 void (*pfn
) (int arg
, int on
);
5524 /* If this is not NULL, and the PFN field is NULL, set the variable
5525 this points to. Set it to the ARG field if the option was not
5526 negated, and the NOTARG field otherwise. */
5529 /* The value to pass to PFN or to assign to *PVAR. */
5532 /* The value to assign to *PVAR if the option is negated. If PFN is
5533 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5534 the option may not be negated. */
5538 /* The table used to handle the MRI OPT pseudo-op. */
5540 static void skip_to_comma (int, int);
5541 static void opt_nest (int, int);
5542 static void opt_chip (int, int);
5543 static void opt_list (int, int);
5544 static void opt_list_symbols (int, int);
5546 static const struct opt_action opt_table
[] =
5548 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5550 /* We do relaxing, so there is little use for these options. */
5551 { "b", 0, 0, 0, 0 },
5552 { "brs", 0, 0, 0, 0 },
5553 { "brb", 0, 0, 0, 0 },
5554 { "brl", 0, 0, 0, 0 },
5555 { "brw", 0, 0, 0, 0 },
5557 { "c", 0, 0, 0, 0 },
5558 { "cex", 0, 0, 0, 0 },
5559 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5560 { "cl", 0, 0, 0, 0 },
5561 { "cre", 0, 0, 0, 0 },
5562 { "d", 0, &flag_keep_locals
, 1, 0 },
5563 { "e", 0, 0, 0, 0 },
5564 { "f", 0, &flag_short_refs
, 1, 0 },
5565 { "frs", 0, &flag_short_refs
, 1, 0 },
5566 { "frl", 0, &flag_short_refs
, 0, 1 },
5567 { "g", 0, 0, 0, 0 },
5568 { "i", 0, 0, 0, 0 },
5569 { "m", 0, 0, 0, 0 },
5570 { "mex", 0, 0, 0, 0 },
5571 { "mc", 0, 0, 0, 0 },
5572 { "md", 0, 0, 0, 0 },
5573 { "nest", opt_nest
, 0, 0, 0 },
5574 { "next", skip_to_comma
, 0, 0, 0 },
5575 { "o", 0, 0, 0, 0 },
5576 { "old", 0, 0, 0, 0 },
5577 { "op", skip_to_comma
, 0, 0, 0 },
5578 { "pco", 0, 0, 0, 0 },
5579 { "p", opt_chip
, 0, 0, 0 },
5580 { "pcr", 0, 0, 0, 0 },
5581 { "pcs", 0, 0, 0, 0 },
5582 { "r", 0, 0, 0, 0 },
5583 { "quick", 0, &m68k_quick
, 1, 0 },
5584 { "rel32", 0, &m68k_rel32
, 1, 0 },
5585 { "s", opt_list
, 0, 0, 0 },
5586 { "t", opt_list_symbols
, 0, 0, 0 },
5587 { "w", 0, &flag_no_warnings
, 0, 1 },
5591 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5593 /* The MRI OPT pseudo-op. */
5596 s_opt (int ignore ATTRIBUTE_UNUSED
)
5604 const struct opt_action
*o
;
5609 if (*input_line_pointer
== '-')
5611 ++input_line_pointer
;
5614 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5616 input_line_pointer
+= 2;
5620 s
= input_line_pointer
;
5621 c
= get_symbol_end ();
5623 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5625 if (strcasecmp (s
, o
->name
) == 0)
5629 /* Restore input_line_pointer now in case the option
5631 *input_line_pointer
= c
;
5632 (*o
->pfn
) (o
->arg
, t
);
5634 else if (o
->pvar
!= NULL
)
5636 if (! t
&& o
->arg
== o
->notarg
)
5637 as_bad (_("option `%s' may not be negated"), s
);
5638 *input_line_pointer
= c
;
5639 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5642 *input_line_pointer
= c
;
5648 as_bad (_("option `%s' not recognized"), s
);
5649 *input_line_pointer
= c
;
5652 while (*input_line_pointer
++ == ',');
5654 /* Move back to terminating character. */
5655 --input_line_pointer
;
5656 demand_empty_rest_of_line ();
5659 /* Skip ahead to a comma. This is used for OPT options which we do
5660 not support and which take arguments. */
5663 skip_to_comma (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5665 while (*input_line_pointer
!= ','
5666 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5667 ++input_line_pointer
;
5670 /* Handle the OPT NEST=depth option. */
5673 opt_nest (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5675 if (*input_line_pointer
!= '=')
5677 as_bad (_("bad format of OPT NEST=depth"));
5681 ++input_line_pointer
;
5682 max_macro_nest
= get_absolute_expression ();
5685 /* Handle the OPT P=chip option. */
5688 opt_chip (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5690 if (*input_line_pointer
!= '=')
5692 /* This is just OPT P, which we do not support. */
5696 ++input_line_pointer
;
5700 /* Handle the OPT S option. */
5703 opt_list (int arg ATTRIBUTE_UNUSED
, int on
)
5708 /* Handle the OPT T option. */
5711 opt_list_symbols (int arg ATTRIBUTE_UNUSED
, int on
)
5714 listing
|= LISTING_SYMBOLS
;
5716 listing
&= ~LISTING_SYMBOLS
;
5719 /* Handle the MRI REG pseudo-op. */
5722 s_reg (int ignore ATTRIBUTE_UNUSED
)
5731 if (line_label
== NULL
)
5733 as_bad (_("missing label"));
5734 ignore_rest_of_line ();
5739 stop
= mri_comment_field (&stopc
);
5743 s
= input_line_pointer
;
5744 while (ISALNUM (*input_line_pointer
)
5745 #ifdef REGISTER_PREFIX
5746 || *input_line_pointer
== REGISTER_PREFIX
5748 || *input_line_pointer
== '/'
5749 || *input_line_pointer
== '-')
5750 ++input_line_pointer
;
5751 c
= *input_line_pointer
;
5752 *input_line_pointer
= '\0';
5754 if (m68k_ip_op (s
, &rop
) != 0)
5756 if (rop
.error
== NULL
)
5757 as_bad (_("bad register list"));
5759 as_bad (_("bad register list: %s"), rop
.error
);
5760 *input_line_pointer
= c
;
5761 ignore_rest_of_line ();
5765 *input_line_pointer
= c
;
5767 if (rop
.mode
== REGLST
)
5769 else if (rop
.mode
== DREG
)
5770 mask
= 1 << (rop
.reg
- DATA0
);
5771 else if (rop
.mode
== AREG
)
5772 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
5773 else if (rop
.mode
== FPREG
)
5774 mask
= 1 << (rop
.reg
- FP0
+ 16);
5775 else if (rop
.mode
== CONTROL
5778 else if (rop
.mode
== CONTROL
5781 else if (rop
.mode
== CONTROL
5786 as_bad (_("bad register list"));
5787 ignore_rest_of_line ();
5791 S_SET_SEGMENT (line_label
, reg_section
);
5792 S_SET_VALUE (line_label
, ~mask
);
5793 symbol_set_frag (line_label
, &zero_address_frag
);
5796 mri_comment_end (stop
, stopc
);
5798 demand_empty_rest_of_line ();
5801 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5805 struct save_opts
*next
;
5807 int symbols_case_sensitive
;
5811 const enum m68k_register
*control_regs
;
5816 /* FIXME: We don't save OPT S. */
5819 /* This variable holds the stack of saved options. */
5821 static struct save_opts
*save_stack
;
5823 /* The MRI SAVE pseudo-op. */
5826 s_save (int ignore ATTRIBUTE_UNUSED
)
5828 struct save_opts
*s
;
5830 s
= (struct save_opts
*) xmalloc (sizeof (struct save_opts
));
5831 s
->abspcadd
= m68k_abspcadd
;
5832 s
->symbols_case_sensitive
= symbols_case_sensitive
;
5833 s
->keep_locals
= flag_keep_locals
;
5834 s
->short_refs
= flag_short_refs
;
5835 s
->architecture
= current_architecture
;
5836 s
->control_regs
= control_regs
;
5837 s
->quick
= m68k_quick
;
5838 s
->rel32
= m68k_rel32
;
5839 s
->listing
= listing
;
5840 s
->no_warnings
= flag_no_warnings
;
5842 s
->next
= save_stack
;
5845 demand_empty_rest_of_line ();
5848 /* The MRI RESTORE pseudo-op. */
5851 s_restore (int ignore ATTRIBUTE_UNUSED
)
5853 struct save_opts
*s
;
5855 if (save_stack
== NULL
)
5857 as_bad (_("restore without save"));
5858 ignore_rest_of_line ();
5863 save_stack
= s
->next
;
5865 m68k_abspcadd
= s
->abspcadd
;
5866 symbols_case_sensitive
= s
->symbols_case_sensitive
;
5867 flag_keep_locals
= s
->keep_locals
;
5868 flag_short_refs
= s
->short_refs
;
5869 current_architecture
= s
->architecture
;
5870 control_regs
= s
->control_regs
;
5871 m68k_quick
= s
->quick
;
5872 m68k_rel32
= s
->rel32
;
5873 listing
= s
->listing
;
5874 flag_no_warnings
= s
->no_warnings
;
5878 demand_empty_rest_of_line ();
5881 /* Types of MRI structured control directives. */
5883 enum mri_control_type
5891 /* This structure is used to stack the MRI structured control
5894 struct mri_control_info
5896 /* The directive within which this one is enclosed. */
5897 struct mri_control_info
*outer
;
5899 /* The type of directive. */
5900 enum mri_control_type type
;
5902 /* Whether an ELSE has been in an IF. */
5905 /* The add or sub statement at the end of a FOR. */
5908 /* The label of the top of a FOR or REPEAT loop. */
5911 /* The label to jump to for the next iteration, or the else
5912 expression of a conditional. */
5915 /* The label to jump to to break out of the loop, or the label past
5916 the end of a conditional. */
5920 /* The stack of MRI structured control directives. */
5922 static struct mri_control_info
*mri_control_stack
;
5924 /* The current MRI structured control directive index number, used to
5925 generate label names. */
5927 static int mri_control_index
;
5929 /* Assemble an instruction for an MRI structured control directive. */
5932 mri_assemble (char *str
)
5936 /* md_assemble expects the opcode to be in lower case. */
5937 for (s
= str
; *s
!= ' ' && *s
!= '\0'; s
++)
5943 /* Generate a new MRI label structured control directive label name. */
5946 mri_control_label (void)
5950 n
= (char *) xmalloc (20);
5951 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
5952 ++mri_control_index
;
5956 /* Create a new MRI structured control directive. */
5958 static struct mri_control_info
*
5959 push_mri_control (enum mri_control_type type
)
5961 struct mri_control_info
*n
;
5963 n
= (struct mri_control_info
*) xmalloc (sizeof (struct mri_control_info
));
5967 if (type
== mri_if
|| type
== mri_while
)
5970 n
->top
= mri_control_label ();
5971 n
->next
= mri_control_label ();
5972 n
->bottom
= mri_control_label ();
5974 n
->outer
= mri_control_stack
;
5975 mri_control_stack
= n
;
5980 /* Pop off the stack of MRI structured control directives. */
5983 pop_mri_control (void)
5985 struct mri_control_info
*n
;
5987 n
= mri_control_stack
;
5988 mri_control_stack
= n
->outer
;
5996 /* Recognize a condition code in an MRI structured control expression. */
5999 parse_mri_condition (int *pcc
)
6003 know (*input_line_pointer
== '<');
6005 ++input_line_pointer
;
6006 c1
= *input_line_pointer
++;
6007 c2
= *input_line_pointer
++;
6009 if (*input_line_pointer
!= '>')
6011 as_bad (_("syntax error in structured control directive"));
6015 ++input_line_pointer
;
6021 *pcc
= (c1
<< 8) | c2
;
6026 /* Parse a single operand in an MRI structured control expression. */
6029 parse_mri_control_operand (int *pcc
, char **leftstart
, char **leftstop
,
6030 char **rightstart
, char **rightstop
)
6042 if (*input_line_pointer
== '<')
6044 /* It's just a condition code. */
6045 return parse_mri_condition (pcc
);
6048 /* Look ahead for the condition code. */
6049 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
6051 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
6056 as_bad (_("missing condition code in structured control directive"));
6060 *leftstart
= input_line_pointer
;
6062 if (*leftstop
> *leftstart
6063 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
6066 input_line_pointer
= s
;
6067 if (! parse_mri_condition (pcc
))
6070 /* Look ahead for AND or OR or end of line. */
6071 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
6073 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6074 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6076 if ((s
== input_line_pointer
6079 && ((strncasecmp (s
, "AND", 3) == 0
6080 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
6081 || (strncasecmp (s
, "OR", 2) == 0
6082 && (s
[2] == '.' || ! is_part_of_name (s
[2])))))
6086 *rightstart
= input_line_pointer
;
6088 if (*rightstop
> *rightstart
6089 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
6092 input_line_pointer
= s
;
6097 #define MCC(b1, b2) (((b1) << 8) | (b2))
6099 /* Swap the sense of a condition. This changes the condition so that
6100 it generates the same result when the operands are swapped. */
6103 swap_mri_condition (int cc
)
6107 case MCC ('h', 'i'): return MCC ('c', 's');
6108 case MCC ('l', 's'): return MCC ('c', 'c');
6109 /* <HS> is an alias for <CC>. */
6110 case MCC ('h', 's'):
6111 case MCC ('c', 'c'): return MCC ('l', 's');
6112 /* <LO> is an alias for <CS>. */
6113 case MCC ('l', 'o'):
6114 case MCC ('c', 's'): return MCC ('h', 'i');
6115 case MCC ('p', 'l'): return MCC ('m', 'i');
6116 case MCC ('m', 'i'): return MCC ('p', 'l');
6117 case MCC ('g', 'e'): return MCC ('l', 'e');
6118 case MCC ('l', 't'): return MCC ('g', 't');
6119 case MCC ('g', 't'): return MCC ('l', 't');
6120 case MCC ('l', 'e'): return MCC ('g', 'e');
6121 /* Issue a warning for conditions we can not swap. */
6122 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6123 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6124 case MCC ('v', 'c'):
6125 case MCC ('v', 's'):
6127 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6128 (char) (cc
>> 8), (char) (cc
));
6134 /* Reverse the sense of a condition. */
6137 reverse_mri_condition (int cc
)
6141 case MCC ('h', 'i'): return MCC ('l', 's');
6142 case MCC ('l', 's'): return MCC ('h', 'i');
6143 /* <HS> is an alias for <CC> */
6144 case MCC ('h', 's'): return MCC ('l', 'o');
6145 case MCC ('c', 'c'): return MCC ('c', 's');
6146 /* <LO> is an alias for <CS> */
6147 case MCC ('l', 'o'): return MCC ('h', 's');
6148 case MCC ('c', 's'): return MCC ('c', 'c');
6149 case MCC ('n', 'e'): return MCC ('e', 'q');
6150 case MCC ('e', 'q'): return MCC ('n', 'e');
6151 case MCC ('v', 'c'): return MCC ('v', 's');
6152 case MCC ('v', 's'): return MCC ('v', 'c');
6153 case MCC ('p', 'l'): return MCC ('m', 'i');
6154 case MCC ('m', 'i'): return MCC ('p', 'l');
6155 case MCC ('g', 'e'): return MCC ('l', 't');
6156 case MCC ('l', 't'): return MCC ('g', 'e');
6157 case MCC ('g', 't'): return MCC ('l', 'e');
6158 case MCC ('l', 'e'): return MCC ('g', 't');
6163 /* Build an MRI structured control expression. This generates test
6164 and branch instructions. It goes to TRUELAB if the condition is
6165 true, and to FALSELAB if the condition is false. Exactly one of
6166 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6167 is the size qualifier for the expression. EXTENT is the size to
6168 use for the branch. */
6171 build_mri_control_operand (int qual
, int cc
, char *leftstart
, char *leftstop
,
6172 char *rightstart
, char *rightstop
,
6173 const char *truelab
, const char *falselab
,
6179 if (leftstart
!= NULL
)
6181 struct m68k_op leftop
, rightop
;
6184 /* Swap the compare operands, if necessary, to produce a legal
6185 m68k compare instruction. Comparing a register operand with
6186 a non-register operand requires the register to be on the
6187 right (cmp, cmpa). Comparing an immediate value with
6188 anything requires the immediate value to be on the left
6193 (void) m68k_ip_op (leftstart
, &leftop
);
6198 (void) m68k_ip_op (rightstart
, &rightop
);
6201 if (rightop
.mode
== IMMED
6202 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
6203 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
6207 /* Correct conditional handling:
6208 if #1 <lt> d0 then ;means if (1 < d0)
6214 cmp #1,d0 if we do *not* swap the operands
6215 bgt true we need the swapped condition!
6222 leftstart
= rightstart
;
6225 leftstop
= rightstop
;
6230 cc
= swap_mri_condition (cc
);
6234 if (truelab
== NULL
)
6236 cc
= reverse_mri_condition (cc
);
6240 if (leftstart
!= NULL
)
6242 buf
= (char *) xmalloc (20
6243 + (leftstop
- leftstart
)
6244 + (rightstop
- rightstart
));
6250 *s
++ = TOLOWER (qual
);
6252 memcpy (s
, leftstart
, leftstop
- leftstart
);
6253 s
+= leftstop
- leftstart
;
6255 memcpy (s
, rightstart
, rightstop
- rightstart
);
6256 s
+= rightstop
- rightstart
;
6262 buf
= (char *) xmalloc (20 + strlen (truelab
));
6268 *s
++ = TOLOWER (extent
);
6270 strcpy (s
, truelab
);
6275 /* Parse an MRI structured control expression. This generates test
6276 and branch instructions. STOP is where the expression ends. It
6277 goes to TRUELAB if the condition is true, and to FALSELAB if the
6278 condition is false. Exactly one of TRUELAB and FALSELAB will be
6279 NULL, meaning to fall through. QUAL is the size qualifier for the
6280 expression. EXTENT is the size to use for the branch. */
6283 parse_mri_control_expression (char *stop
, int qual
, const char *truelab
,
6284 const char *falselab
, int extent
)
6296 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6297 &rightstart
, &rightstop
))
6303 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
6307 if (falselab
!= NULL
)
6310 flab
= mri_control_label ();
6312 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6313 rightstop
, (const char *) NULL
, flab
, extent
);
6315 input_line_pointer
+= 3;
6316 if (*input_line_pointer
!= '.'
6317 || input_line_pointer
[1] == '\0')
6321 qual
= input_line_pointer
[1];
6322 input_line_pointer
+= 2;
6325 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6326 &rightstart
, &rightstop
))
6332 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6333 rightstop
, truelab
, falselab
, extent
);
6335 if (falselab
== NULL
)
6338 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
6342 if (truelab
!= NULL
)
6345 tlab
= mri_control_label ();
6347 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6348 rightstop
, tlab
, (const char *) NULL
, extent
);
6350 input_line_pointer
+= 2;
6351 if (*input_line_pointer
!= '.'
6352 || input_line_pointer
[1] == '\0')
6356 qual
= input_line_pointer
[1];
6357 input_line_pointer
+= 2;
6360 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6361 &rightstart
, &rightstop
))
6367 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6368 rightstop
, truelab
, falselab
, extent
);
6370 if (truelab
== NULL
)
6375 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6376 rightstop
, truelab
, falselab
, extent
);
6380 if (input_line_pointer
!= stop
)
6381 as_bad (_("syntax error in structured control directive"));
6384 /* Handle the MRI IF pseudo-op. This may be a structured control
6385 directive, or it may be a regular assembler conditional, depending
6393 struct mri_control_info
*n
;
6395 /* A structured control directive must end with THEN with an
6396 optional qualifier. */
6397 s
= input_line_pointer
;
6398 /* We only accept '*' as introduction of comments if preceded by white space
6399 or at first column of a line (I think this can't actually happen here?)
6400 This is important when assembling:
6401 if d0 <ne> 12(a0,d0*2) then
6402 if d0 <ne> #CONST*20 then. */
6403 while (! (is_end_of_line
[(unsigned char) *s
]
6406 && (s
== input_line_pointer
6408 || *(s
-1) == '\t'))))
6411 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
6414 if (s
- input_line_pointer
> 1
6418 if (s
- input_line_pointer
< 3
6419 || strncasecmp (s
- 3, "THEN", 4) != 0)
6423 as_bad (_("missing then"));
6424 ignore_rest_of_line ();
6428 /* It's a conditional. */
6433 /* Since this might be a conditional if, this pseudo-op will be
6434 called even if we are supported to be ignoring input. Double
6435 check now. Clobber *input_line_pointer so that ignore_input
6436 thinks that this is not a special pseudo-op. */
6437 c
= *input_line_pointer
;
6438 *input_line_pointer
= 0;
6439 if (ignore_input ())
6441 *input_line_pointer
= c
;
6442 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6443 ++input_line_pointer
;
6444 demand_empty_rest_of_line ();
6447 *input_line_pointer
= c
;
6449 n
= push_mri_control (mri_if
);
6451 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
6452 n
->next
, s
[1] == '.' ? s
[2] : '\0');
6455 input_line_pointer
= s
+ 3;
6457 input_line_pointer
= s
+ 1;
6461 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6462 ++input_line_pointer
;
6465 demand_empty_rest_of_line ();
6468 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6469 structured IF, associate the ELSE with the IF. Otherwise, assume
6470 it is a conditional else. */
6473 s_mri_else (int qual
)
6480 && (mri_control_stack
== NULL
6481 || mri_control_stack
->type
!= mri_if
6482 || mri_control_stack
->else_seen
))
6488 c
= *input_line_pointer
;
6489 *input_line_pointer
= 0;
6490 if (ignore_input ())
6492 *input_line_pointer
= c
;
6493 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6494 ++input_line_pointer
;
6495 demand_empty_rest_of_line ();
6498 *input_line_pointer
= c
;
6500 if (mri_control_stack
== NULL
6501 || mri_control_stack
->type
!= mri_if
6502 || mri_control_stack
->else_seen
)
6504 as_bad (_("else without matching if"));
6505 ignore_rest_of_line ();
6509 mri_control_stack
->else_seen
= 1;
6511 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->bottom
));
6512 q
[0] = TOLOWER (qual
);
6514 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6518 colon (mri_control_stack
->next
);
6522 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6523 ++input_line_pointer
;
6526 demand_empty_rest_of_line ();
6529 /* Handle the MRI ENDI pseudo-op. */
6532 s_mri_endi (int ignore ATTRIBUTE_UNUSED
)
6534 if (mri_control_stack
== NULL
6535 || mri_control_stack
->type
!= mri_if
)
6537 as_bad (_("endi without matching if"));
6538 ignore_rest_of_line ();
6542 /* ignore_input will not return true for ENDI, so we don't need to
6543 worry about checking it again here. */
6545 if (! mri_control_stack
->else_seen
)
6546 colon (mri_control_stack
->next
);
6547 colon (mri_control_stack
->bottom
);
6553 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6554 ++input_line_pointer
;
6557 demand_empty_rest_of_line ();
6560 /* Handle the MRI BREAK pseudo-op. */
6563 s_mri_break (int extent
)
6565 struct mri_control_info
*n
;
6569 n
= mri_control_stack
;
6571 && n
->type
!= mri_for
6572 && n
->type
!= mri_repeat
6573 && n
->type
!= mri_while
)
6577 as_bad (_("break outside of structured loop"));
6578 ignore_rest_of_line ();
6582 buf
= (char *) xmalloc (20 + strlen (n
->bottom
));
6583 ex
[0] = TOLOWER (extent
);
6585 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6591 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6592 ++input_line_pointer
;
6595 demand_empty_rest_of_line ();
6598 /* Handle the MRI NEXT pseudo-op. */
6601 s_mri_next (int extent
)
6603 struct mri_control_info
*n
;
6607 n
= mri_control_stack
;
6609 && n
->type
!= mri_for
6610 && n
->type
!= mri_repeat
6611 && n
->type
!= mri_while
)
6615 as_bad (_("next outside of structured loop"));
6616 ignore_rest_of_line ();
6620 buf
= (char *) xmalloc (20 + strlen (n
->next
));
6621 ex
[0] = TOLOWER (extent
);
6623 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6629 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6630 ++input_line_pointer
;
6633 demand_empty_rest_of_line ();
6636 /* Handle the MRI FOR pseudo-op. */
6639 s_mri_for (int qual
)
6641 const char *varstart
, *varstop
;
6642 const char *initstart
, *initstop
;
6643 const char *endstart
, *endstop
;
6644 const char *bystart
, *bystop
;
6648 struct mri_control_info
*n
;
6654 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6658 varstart
= input_line_pointer
;
6660 /* Look for the '='. */
6661 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6662 && *input_line_pointer
!= '=')
6663 ++input_line_pointer
;
6664 if (*input_line_pointer
!= '=')
6666 as_bad (_("missing ="));
6667 ignore_rest_of_line ();
6671 varstop
= input_line_pointer
;
6672 if (varstop
> varstart
6673 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6676 ++input_line_pointer
;
6678 initstart
= input_line_pointer
;
6680 /* Look for TO or DOWNTO. */
6683 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6685 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6686 && ! is_part_of_name (input_line_pointer
[2]))
6688 initstop
= input_line_pointer
;
6689 input_line_pointer
+= 2;
6692 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6693 && ! is_part_of_name (input_line_pointer
[6]))
6695 initstop
= input_line_pointer
;
6697 input_line_pointer
+= 6;
6700 ++input_line_pointer
;
6702 if (initstop
== NULL
)
6704 as_bad (_("missing to or downto"));
6705 ignore_rest_of_line ();
6708 if (initstop
> initstart
6709 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6713 endstart
= input_line_pointer
;
6715 /* Look for BY or DO. */
6718 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6720 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
6721 && ! is_part_of_name (input_line_pointer
[2]))
6723 endstop
= input_line_pointer
;
6725 input_line_pointer
+= 2;
6728 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6729 && (input_line_pointer
[2] == '.'
6730 || ! is_part_of_name (input_line_pointer
[2])))
6732 endstop
= input_line_pointer
;
6733 input_line_pointer
+= 2;
6736 ++input_line_pointer
;
6738 if (endstop
== NULL
)
6740 as_bad (_("missing do"));
6741 ignore_rest_of_line ();
6744 if (endstop
> endstart
6745 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
6751 bystop
= bystart
+ 2;
6756 bystart
= input_line_pointer
;
6760 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6762 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6763 && (input_line_pointer
[2] == '.'
6764 || ! is_part_of_name (input_line_pointer
[2])))
6766 bystop
= input_line_pointer
;
6767 input_line_pointer
+= 2;
6770 ++input_line_pointer
;
6774 as_bad (_("missing do"));
6775 ignore_rest_of_line ();
6778 if (bystop
> bystart
6779 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
6783 if (*input_line_pointer
!= '.')
6787 extent
= input_line_pointer
[1];
6788 input_line_pointer
+= 2;
6791 /* We have fully parsed the FOR operands. Now build the loop. */
6792 n
= push_mri_control (mri_for
);
6794 buf
= (char *) xmalloc (50 + (input_line_pointer
- varstart
));
6796 /* Move init,var. */
6803 *s
++ = TOLOWER (qual
);
6805 memcpy (s
, initstart
, initstop
- initstart
);
6806 s
+= initstop
- initstart
;
6808 memcpy (s
, varstart
, varstop
- varstart
);
6809 s
+= varstop
- varstart
;
6821 *s
++ = TOLOWER (qual
);
6823 memcpy (s
, endstart
, endstop
- endstart
);
6824 s
+= endstop
- endstart
;
6826 memcpy (s
, varstart
, varstop
- varstart
);
6827 s
+= varstop
- varstart
;
6832 ex
[0] = TOLOWER (extent
);
6835 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
6837 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
6840 /* Put together the add or sub instruction used by ENDF. */
6848 *s
++ = TOLOWER (qual
);
6850 memcpy (s
, bystart
, bystop
- bystart
);
6851 s
+= bystop
- bystart
;
6853 memcpy (s
, varstart
, varstop
- varstart
);
6854 s
+= varstop
- varstart
;
6860 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6861 ++input_line_pointer
;
6864 demand_empty_rest_of_line ();
6867 /* Handle the MRI ENDF pseudo-op. */
6870 s_mri_endf (int ignore ATTRIBUTE_UNUSED
)
6872 if (mri_control_stack
== NULL
6873 || mri_control_stack
->type
!= mri_for
)
6875 as_bad (_("endf without for"));
6876 ignore_rest_of_line ();
6880 colon (mri_control_stack
->next
);
6882 mri_assemble (mri_control_stack
->incr
);
6884 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
6885 mri_assemble (mri_control_stack
->incr
);
6887 free (mri_control_stack
->incr
);
6889 colon (mri_control_stack
->bottom
);
6895 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6896 ++input_line_pointer
;
6899 demand_empty_rest_of_line ();
6902 /* Handle the MRI REPEAT pseudo-op. */
6905 s_mri_repeat (int ignore ATTRIBUTE_UNUSED
)
6907 struct mri_control_info
*n
;
6909 n
= push_mri_control (mri_repeat
);
6913 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6914 ++input_line_pointer
;
6916 demand_empty_rest_of_line ();
6919 /* Handle the MRI UNTIL pseudo-op. */
6922 s_mri_until (int qual
)
6926 if (mri_control_stack
== NULL
6927 || mri_control_stack
->type
!= mri_repeat
)
6929 as_bad (_("until without repeat"));
6930 ignore_rest_of_line ();
6934 colon (mri_control_stack
->next
);
6936 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
6939 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
6940 mri_control_stack
->top
, '\0');
6942 colon (mri_control_stack
->bottom
);
6944 input_line_pointer
= s
;
6950 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6951 ++input_line_pointer
;
6954 demand_empty_rest_of_line ();
6957 /* Handle the MRI WHILE pseudo-op. */
6960 s_mri_while (int qual
)
6964 struct mri_control_info
*n
;
6966 s
= input_line_pointer
;
6967 /* We only accept '*' as introduction of comments if preceded by white space
6968 or at first column of a line (I think this can't actually happen here?)
6969 This is important when assembling:
6970 while d0 <ne> 12(a0,d0*2) do
6971 while d0 <ne> #CONST*20 do. */
6972 while (! (is_end_of_line
[(unsigned char) *s
]
6975 && (s
== input_line_pointer
6977 || *(s
-1) == '\t'))))
6980 while (*s
== ' ' || *s
== '\t')
6982 if (s
- input_line_pointer
> 1
6985 if (s
- input_line_pointer
< 2
6986 || strncasecmp (s
- 1, "DO", 2) != 0)
6988 as_bad (_("missing do"));
6989 ignore_rest_of_line ();
6993 n
= push_mri_control (mri_while
);
6997 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
6998 s
[1] == '.' ? s
[2] : '\0');
7000 input_line_pointer
= s
+ 1;
7001 if (*input_line_pointer
== '.')
7002 input_line_pointer
+= 2;
7006 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7007 ++input_line_pointer
;
7010 demand_empty_rest_of_line ();
7013 /* Handle the MRI ENDW pseudo-op. */
7016 s_mri_endw (int ignore ATTRIBUTE_UNUSED
)
7020 if (mri_control_stack
== NULL
7021 || mri_control_stack
->type
!= mri_while
)
7023 as_bad (_("endw without while"));
7024 ignore_rest_of_line ();
7028 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->next
));
7029 sprintf (buf
, "bra %s", mri_control_stack
->next
);
7033 colon (mri_control_stack
->bottom
);
7039 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7040 ++input_line_pointer
;
7043 demand_empty_rest_of_line ();
7046 /* Parse a .cpu directive. */
7049 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED
)
7056 as_bad (_("already assembled instructions"));
7057 ignore_rest_of_line ();
7061 name
= input_line_pointer
;
7062 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
7063 input_line_pointer
++;
7064 saved_char
= *input_line_pointer
;
7065 *input_line_pointer
= 0;
7067 m68k_set_cpu (name
, 1, 0);
7069 *input_line_pointer
= saved_char
;
7070 demand_empty_rest_of_line ();
7074 /* Parse a .arch directive. */
7077 s_m68k_arch (int ignored ATTRIBUTE_UNUSED
)
7084 as_bad (_("already assembled instructions"));
7085 ignore_rest_of_line ();
7089 name
= input_line_pointer
;
7090 while (*input_line_pointer
&& *input_line_pointer
!= ','
7091 && !ISSPACE (*input_line_pointer
))
7092 input_line_pointer
++;
7093 saved_char
= *input_line_pointer
;
7094 *input_line_pointer
= 0;
7096 if (m68k_set_arch (name
, 1, 0))
7098 /* Scan extensions. */
7101 *input_line_pointer
++ = saved_char
;
7102 if (!*input_line_pointer
|| ISSPACE (*input_line_pointer
))
7104 name
= input_line_pointer
;
7105 while (*input_line_pointer
&& *input_line_pointer
!= ','
7106 && !ISSPACE (*input_line_pointer
))
7107 input_line_pointer
++;
7108 saved_char
= *input_line_pointer
;
7109 *input_line_pointer
= 0;
7111 while (m68k_set_extension (name
, 1, 0));
7114 *input_line_pointer
= saved_char
;
7115 demand_empty_rest_of_line ();
7119 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7120 if none is found, the caller is responsible for emitting an error
7121 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7122 cpu name, if it begins with a '6' (possibly skipping an intervening
7123 'c'. We also allow a 'c' in the same place. if NEGATED is
7124 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7125 the option is indeed negated. */
7127 static const struct m68k_cpu
*
7128 m68k_lookup_cpu (const char *arg
, const struct m68k_cpu
*table
,
7129 int allow_m
, int *negated
)
7131 /* allow negated value? */
7136 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
7143 /* Remove 'm' or 'mc' prefix from 68k variants. */
7150 else if (arg
[1] == 'c' && arg
[2] == '6')
7154 else if (arg
[0] == 'c' && arg
[1] == '6')
7157 for (; table
->name
; table
++)
7158 if (!strcmp (arg
, table
->name
))
7160 if (table
->alias
< -1 || table
->alias
> 1)
7161 as_bad (_("`%s' is deprecated, use `%s'"),
7162 table
->name
, table
[table
->alias
< 0 ? 1 : -1].name
);
7168 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7171 m68k_set_cpu (char const *name
, int allow_m
, int silent
)
7173 const struct m68k_cpu
*cpu
;
7175 cpu
= m68k_lookup_cpu (name
, m68k_cpus
, allow_m
, NULL
);
7180 as_bad (_("cpu `%s' unrecognized"), name
);
7184 if (selected_cpu
&& selected_cpu
!= cpu
)
7186 as_bad (_("already selected `%s' processor"),
7187 selected_cpu
->name
);
7194 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7197 m68k_set_arch (char const *name
, int allow_m
, int silent
)
7199 const struct m68k_cpu
*arch
;
7201 arch
= m68k_lookup_cpu (name
, m68k_archs
, allow_m
, NULL
);
7206 as_bad (_("architecture `%s' unrecognized"), name
);
7210 if (selected_arch
&& selected_arch
!= arch
)
7212 as_bad (_("already selected `%s' architecture"),
7213 selected_arch
->name
);
7217 selected_arch
= arch
;
7221 /* Set the architecture extension, issuing errors if it is
7222 unrecognized, or invalid */
7225 m68k_set_extension (char const *name
, int allow_m
, int silent
)
7228 const struct m68k_cpu
*ext
;
7230 ext
= m68k_lookup_cpu (name
, m68k_extensions
, allow_m
, &negated
);
7235 as_bad (_("extension `%s' unrecognized"), name
);
7240 not_current_architecture
|= ext
->arch
;
7242 current_architecture
|= ext
->arch
;
7247 Invocation line includes a switch not recognized by the base assembler.
7251 const char *md_shortopts
= "lSA:m:kQ:V";
7253 const char *md_shortopts
= "lSA:m:k";
7256 struct option md_longopts
[] = {
7257 #define OPTION_PIC (OPTION_MD_BASE)
7258 {"pic", no_argument
, NULL
, OPTION_PIC
},
7259 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7260 {"register-prefix-optional", no_argument
, NULL
,
7261 OPTION_REGISTER_PREFIX_OPTIONAL
},
7262 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7263 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
7264 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7265 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
7266 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7267 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
7268 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7269 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
7270 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7271 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
7272 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7273 {"pcrel", no_argument
, NULL
, OPTION_PCREL
},
7274 {NULL
, no_argument
, NULL
, 0}
7276 size_t md_longopts_size
= sizeof (md_longopts
);
7279 md_parse_option (int c
, char *arg
)
7283 case 'l': /* -l means keep external to 2 bit offset
7284 rather than 16 bit one. */
7285 flag_short_refs
= 1;
7288 case 'S': /* -S means that jbsr's always turn into
7290 flag_long_jumps
= 1;
7293 case OPTION_PCREL
: /* --pcrel means never turn PC-relative
7294 branches into absolute jumps. */
7295 flag_keep_pcrel
= 1;
7301 break; /* -pic, Position Independent Code. */
7303 case OPTION_REGISTER_PREFIX_OPTIONAL
:
7304 flag_reg_prefix_optional
= 1;
7305 reg_prefix_optional_seen
= 1;
7308 /* -V: SVR4 argument to print version ID. */
7310 print_version_id ();
7313 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7314 should be emitted or not. FIXME: Not implemented. */
7318 case OPTION_BITWISE_OR
:
7323 n
= (char *) xmalloc (strlen (m68k_comment_chars
) + 1);
7325 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
7329 m68k_comment_chars
= n
;
7333 case OPTION_BASE_SIZE_DEFAULT_16
:
7334 m68k_index_width_default
= SIZE_WORD
;
7337 case OPTION_BASE_SIZE_DEFAULT_32
:
7338 m68k_index_width_default
= SIZE_LONG
;
7341 case OPTION_DISP_SIZE_DEFAULT_16
:
7343 m68k_rel32_from_cmdline
= 1;
7346 case OPTION_DISP_SIZE_DEFAULT_32
:
7348 m68k_rel32_from_cmdline
= 1;
7353 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7356 /* Intentional fall-through. */
7358 if (!strncmp (arg
, "arch=", 5))
7359 m68k_set_arch (arg
+ 5, 1, 0);
7360 else if (!strncmp (arg
, "cpu=", 4))
7361 m68k_set_cpu (arg
+ 4, 1, 0);
7362 else if (m68k_set_extension (arg
, 0, 1))
7364 else if (m68k_set_arch (arg
, 0, 1))
7366 else if (m68k_set_cpu (arg
, 0, 1))
7379 /* Setup tables from the selected arch and/or cpu */
7382 m68k_init_arch (void)
7384 if (not_current_architecture
& current_architecture
)
7386 as_bad (_("architecture features both enabled and disabled"));
7387 not_current_architecture
&= ~current_architecture
;
7391 current_architecture
|= selected_arch
->arch
;
7392 control_regs
= selected_arch
->control_regs
;
7395 current_architecture
|= selected_cpu
->arch
;
7397 current_architecture
&= ~not_current_architecture
;
7399 if ((current_architecture
& (cfloat
| m68881
)) == (cfloat
| m68881
))
7401 /* Determine which float is really meant. */
7402 if (current_architecture
& (m68k_mask
& ~m68881
))
7403 current_architecture
^= cfloat
;
7405 current_architecture
^= m68881
;
7410 control_regs
= selected_cpu
->control_regs
;
7411 if (current_architecture
& ~selected_cpu
->arch
)
7413 as_bad (_("selected processor does not have all features of selected architecture"));
7414 current_architecture
7415 = selected_cpu
->arch
& ~not_current_architecture
;
7419 if ((current_architecture
& m68k_mask
)
7420 && (current_architecture
& ~m68k_mask
))
7422 as_bad (_ ("m68k and cf features both selected"));
7423 if (current_architecture
& m68k_mask
)
7424 current_architecture
&= m68k_mask
;
7426 current_architecture
&= ~m68k_mask
;
7429 /* Permit m68881 specification with all cpus; those that can't work
7430 with a coprocessor could be doing emulation. */
7431 if (current_architecture
& m68851
)
7433 if (current_architecture
& m68040
)
7434 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7436 /* What other incompatibilities could we check for? */
7438 if (cpu_of_arch (current_architecture
) < m68020
7439 || arch_coldfire_p (current_architecture
))
7440 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
7446 md_show_usage (FILE *stream
)
7448 const char *default_cpu
= TARGET_CPU
;
7450 unsigned int default_arch
;
7452 /* Get the canonical name for the default target CPU. */
7453 if (*default_cpu
== 'm')
7455 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7457 if (strcasecmp (default_cpu
, m68k_cpus
[i
].name
) == 0)
7459 default_arch
= m68k_cpus
[i
].arch
;
7460 while (m68k_cpus
[i
].alias
> 0)
7462 while (m68k_cpus
[i
].alias
< 0)
7464 default_cpu
= m68k_cpus
[i
].name
;
7468 fprintf (stream
, _("\
7469 -march=<arch> set architecture\n\
7470 -mcpu=<cpu> set cpu [default %s]\n\
7472 for (i
= 0; m68k_extensions
[i
].name
; i
++)
7473 fprintf (stream
, _("\
7474 -m[no-]%-16s enable/disable%s architecture extension\n\
7475 "), m68k_extensions
[i
].name
,
7476 m68k_extensions
[i
].alias
> 0 ? " ColdFire"
7477 : m68k_extensions
[i
].alias
< 0 ? " m68k" : "");
7479 fprintf (stream
, _("\
7480 -l use 1 word for refs to undefined symbols [default 2]\n\
7481 -pic, -k generate position independent code\n\
7482 -S turn jbsr into jsr\n\
7483 --pcrel never turn PC-relative branches into absolute jumps\n\
7484 --register-prefix-optional\n\
7485 recognize register names without prefix character\n\
7486 --bitwise-or do not treat `|' as a comment character\n\
7487 --base-size-default-16 base reg without size is 16 bits\n\
7488 --base-size-default-32 base reg without size is 32 bits (default)\n\
7489 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7490 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7493 fprintf (stream
, _("Architecture variants are: "));
7494 for (i
= 0; m68k_archs
[i
].name
; i
++)
7497 fprintf (stream
, " | ");
7498 fprintf (stream
, m68k_archs
[i
].name
);
7500 fprintf (stream
, "\n");
7502 fprintf (stream
, _("Processor variants are: "));
7503 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7506 fprintf (stream
, " | ");
7507 fprintf (stream
, m68k_cpus
[i
].name
);
7509 fprintf (stream
, _("\n"));
7514 /* TEST2: Test md_assemble() */
7515 /* Warning, this routine probably doesn't work anymore. */
7519 struct m68k_it the_ins
;
7527 if (!gets (buf
) || !*buf
)
7529 if (buf
[0] == '|' || buf
[1] == '.')
7531 for (cp
= buf
; *cp
; cp
++)
7536 memset (&the_ins
, '\0', sizeof (the_ins
));
7537 m68k_ip (&the_ins
, buf
);
7540 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
7544 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
7545 for (n
= 0; n
< the_ins
.numo
; n
++)
7546 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
7548 print_the_insn (&the_ins
.opcode
[0], stdout
);
7549 (void) putchar ('\n');
7551 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
7553 if (the_ins
.operands
[n
].error
)
7555 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
7558 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
,
7559 the_ins
.operands
[n
].reg
);
7560 if (the_ins
.operands
[n
].b_const
)
7561 printf ("Constant: '%.*s', ",
7562 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
,
7563 the_ins
.operands
[n
].b_const
);
7564 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
,
7565 the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
7566 if (the_ins
.operands
[n
].b_iadd
)
7567 printf ("Iadd: '%.*s',",
7568 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
,
7569 the_ins
.operands
[n
].b_iadd
);
7578 is_label (char *str
)
7582 while (*str
&& *str
!= ' ')
7584 if (str
[-1] == ':' || str
[1] == '=')
7591 /* Possible states for relaxation:
7593 0 0 branch offset byte (bra, etc)
7597 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7601 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7608 /* We have no need to default values of symbols. */
7611 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7616 /* Round up a section size to the appropriate boundary. */
7618 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7621 /* For a.out, force the section size to be aligned. If we don't do
7622 this, BFD will align it for us, but it will not write out the
7623 final bytes of the section. This may be a bug in BFD, but it is
7624 easier to fix it here since that is how the other a.out targets
7628 align
= bfd_get_section_alignment (stdoutput
, segment
);
7629 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7635 /* Exactly what point is a PC-relative offset relative TO?
7636 On the 68k, it is relative to the address of the first extension
7637 word. The difference between the addresses of the offset and the
7638 first extension word is stored in fx_pcrel_adjust. */
7640 md_pcrel_from (fixS
*fixP
)
7644 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7645 sign extend the value here. */
7646 adjust
= ((fixP
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80;
7649 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
7654 m68k_elf_final_processing (void)
7658 if (arch_coldfire_fpu (current_architecture
))
7659 flags
|= EF_M68K_CFV4E
;
7660 /* Set file-specific flags if this is a cpu32 processor. */
7661 if (cpu_of_arch (current_architecture
) & cpu32
)
7662 flags
|= EF_M68K_CPU32
;
7663 else if (cpu_of_arch (current_architecture
) & fido_a
)
7664 flags
|= EF_M68K_FIDO
;
7665 else if ((cpu_of_arch (current_architecture
) & m68000up
)
7666 && !(cpu_of_arch (current_architecture
) & m68020up
))
7667 flags
|= EF_M68K_M68000
;
7669 if (current_architecture
& mcfisa_a
)
7671 static const unsigned isa_features
[][2] =
7673 {EF_M68K_CF_ISA_A_NODIV
,mcfisa_a
},
7674 {EF_M68K_CF_ISA_A
, mcfisa_a
|mcfhwdiv
},
7675 {EF_M68K_CF_ISA_A_PLUS
, mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfusp
},
7676 {EF_M68K_CF_ISA_B_NOUSP
,mcfisa_a
|mcfisa_b
|mcfhwdiv
},
7677 {EF_M68K_CF_ISA_B
, mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfusp
},
7678 {EF_M68K_CF_ISA_C
, mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfusp
},
7681 static const unsigned mac_features
[][2] =
7683 {EF_M68K_CF_MAC
, mcfmac
},
7684 {EF_M68K_CF_EMAC
, mcfemac
},
7690 pattern
= (current_architecture
7691 & (mcfisa_a
|mcfisa_aa
|mcfisa_b
|mcfisa_c
|mcfhwdiv
|mcfusp
));
7692 for (ix
= 0; isa_features
[ix
][1]; ix
++)
7694 if (pattern
== isa_features
[ix
][1])
7696 flags
|= isa_features
[ix
][0];
7700 if (!isa_features
[ix
][1])
7703 as_warn (_("Not a defined coldfire architecture"));
7707 if (current_architecture
& cfloat
)
7708 flags
|= EF_M68K_CF_FLOAT
| EF_M68K_CFV4E
;
7710 pattern
= current_architecture
& (mcfmac
|mcfemac
);
7713 for (ix
= 0; mac_features
[ix
][1]; ix
++)
7715 if (pattern
== mac_features
[ix
][1])
7717 flags
|= mac_features
[ix
][0];
7721 if (!mac_features
[ix
][1])
7726 elf_elfheader (stdoutput
)->e_flags
|= flags
;
7731 tc_m68k_regname_to_dw2regnum (char *regname
)
7733 unsigned int regnum
;
7734 static const char *const regnames
[] =
7736 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7737 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7738 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7742 for (regnum
= 0; regnum
< ARRAY_SIZE (regnames
); regnum
++)
7743 if (strcmp (regname
, regnames
[regnum
]) == 0)
7750 tc_m68k_frame_initial_instructions (void)
7752 static int sp_regno
= -1;
7755 sp_regno
= tc_m68k_regname_to_dw2regnum ("sp");
7757 cfi_add_CFA_def_cfa (sp_regno
, -DWARF2_CIE_DATA_ALIGNMENT
);
7758 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, DWARF2_CIE_DATA_ALIGNMENT
);