1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987-2024 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 #include "safe-ctype.h"
25 #include "dwarf2dbg.h"
26 #include "dw2gencfi.h"
28 #include "opcode/m68k.h"
29 #include "m68k-parse.h"
32 static void m68k_elf_cons (int);
33 static void m68k_elf_gnu_attribute (int);
35 /* This string holds the chars that always start a comment. If the
36 pre-processor is disabled, these aren't very useful. The macro
37 tc_comment_chars points to this. We use this, rather than the
38 usual comment_chars, so that the --bitwise-or option will work. */
39 #if defined (TE_SVR4) || defined (TE_DELTA)
40 const char *m68k_comment_chars
= "|#";
42 const char *m68k_comment_chars
= "|";
45 /* This array holds the chars that only start a comment at the beginning of
46 a line. If the line seems to have the form '# 123 filename'
47 .line and .file directives will appear in the pre-processed output */
48 /* Note that input_file.c hand checks for '#' at the beginning of the
49 first line of the input file. This is because the compiler outputs
50 #NO_APP at the beginning of its output. */
51 /* Also note that comments like this one will always work. */
52 const char line_comment_chars
[] = "#*";
54 const char line_separator_chars
[] = ";";
56 /* Chars that can be used to separate mant from exp in floating point nums. */
57 const char EXP_CHARS
[] = "eE";
59 /* Chars that mean this number is a floating point constant, as
60 in "0f12.456" or "0d1.2345e12". */
62 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
64 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
65 changed in read.c . Ideally it shouldn't have to know about it at all,
66 but nothing is ideal around here. */
68 /* Are we trying to generate PIC code? If so, absolute references
69 ought to be made into linkage table references or pc-relative
70 references. Not implemented. For ELF there are other means
71 to denote pic relocations. */
74 static int flag_short_refs
; /* -l option. */
75 static int flag_long_jumps
; /* -S option. */
76 static int flag_keep_pcrel
; /* --pcrel option. */
78 #ifdef REGISTER_PREFIX_OPTIONAL
79 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
81 int flag_reg_prefix_optional
;
84 /* Whether --register-prefix-optional was used on the command line. */
85 static int reg_prefix_optional_seen
;
87 /* The floating point coprocessor to use by default. */
88 static enum m68k_register m68k_float_copnum
= COP1
;
90 /* If this is non-zero, then references to number(%pc) will be taken
91 to refer to number, rather than to %pc + number. */
92 static int m68k_abspcadd
;
94 /* If this is non-zero, then the quick forms of the move, add, and sub
95 instructions are used when possible. */
96 static int m68k_quick
= 1;
98 /* If this is non-zero, then if the size is not specified for a base
99 or outer displacement, the assembler assumes that the size should
101 static int m68k_rel32
= 1;
103 /* This is non-zero if m68k_rel32 was set from the command line. */
104 static int m68k_rel32_from_cmdline
;
106 /* The default width to use for an index register when using a base
108 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
110 /* The current label. */
112 static struct m68k_tc_sy
*current_label
;
114 /* Pointer to list holding the opcodes sorted by name. */
115 static struct m68k_opcode
const ** m68k_sorted_opcodes
;
117 /* It's an arbitrary name: This means I don't approve of it.
119 static struct obstack robyn
;
123 const char *m_operands
;
124 unsigned long m_opcode
;
128 struct m68k_incant
*m_next
;
131 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
132 #define gettwo(x) (((x)->m_opcode)&0xffff)
134 static const enum m68k_register m68000_ctrl
[] = { 0 };
135 static const enum m68k_register m68010_ctrl
[] = {
139 static const enum m68k_register m68020_ctrl
[] = {
140 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
143 static const enum m68k_register m68040_ctrl
[] = {
144 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
145 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
148 static const enum m68k_register m68060_ctrl
[] = {
149 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
150 USP
, VBR
, URP
, SRP
, PCR
,
153 static const enum m68k_register mcf_ctrl
[] = {
154 CACR
, TC
, ACR0
, ACR1
, ACR2
, ACR3
, VBR
, ROMBAR
,
155 RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
,
158 static const enum m68k_register mcf51_ctrl
[] = {
162 static const enum m68k_register mcf5206_ctrl
[] = {
163 CACR
, ACR0
, ACR1
, VBR
, RAMBAR0
, RAMBAR_ALT
, MBAR
,
166 static const enum m68k_register mcf5208_ctrl
[] = {
167 CACR
, ACR0
, ACR1
, VBR
, RAMBAR
, RAMBAR1
,
170 static const enum m68k_register mcf5210a_ctrl
[] = {
171 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR
, RAMBAR1
, MBAR
,
174 static const enum m68k_register mcf5213_ctrl
[] = {
175 VBR
, RAMBAR
, RAMBAR1
, FLASHBAR
,
178 static const enum m68k_register mcf5216_ctrl
[] = {
179 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
182 static const enum m68k_register mcf5221x_ctrl
[] = {
183 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
186 static const enum m68k_register mcf52223_ctrl
[] = {
187 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
190 static const enum m68k_register mcf52235_ctrl
[] = {
191 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
194 static const enum m68k_register mcf5225_ctrl
[] = {
195 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, MBAR
, RAMBAR1
,
198 static const enum m68k_register mcf52259_ctrl
[] = {
199 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
202 static const enum m68k_register mcf52277_ctrl
[] = {
203 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
206 static const enum m68k_register mcf5235_ctrl
[] = {
207 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
210 static const enum m68k_register mcf5249_ctrl
[] = {
211 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
, MBAR2
,
214 static const enum m68k_register mcf5250_ctrl
[] = {
218 static const enum m68k_register mcf5253_ctrl
[] = {
219 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
, MBAR2
,
222 static const enum m68k_register mcf5271_ctrl
[] = {
223 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
226 static const enum m68k_register mcf5272_ctrl
[] = {
227 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR_ALT
, RAMBAR0
, MBAR
,
230 static const enum m68k_register mcf5275_ctrl
[] = {
231 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
234 static const enum m68k_register mcf5282_ctrl
[] = {
235 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
238 static const enum m68k_register mcf53017_ctrl
[] = {
239 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
242 static const enum m68k_register mcf5307_ctrl
[] = {
243 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR_ALT
, MBAR
,
246 static const enum m68k_register mcf5329_ctrl
[] = {
247 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
250 static const enum m68k_register mcf5373_ctrl
[] = {
251 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
254 static const enum m68k_register mcfv4e_ctrl
[] = {
255 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
256 VBR
, PC
, ROMBAR0
, ROMBAR1
, RAMBAR0
, RAMBAR1
,
258 MPCR
/* Multiprocessor Control register */,
259 EDRAMBAR
/* Embedded DRAM Base Address Register */,
260 /* Permutation control registers. */
261 PCR1U0
, PCR1L0
, PCR1U1
, PCR1L1
, PCR2U0
, PCR2L0
, PCR2U1
, PCR2L1
,
262 PCR3U0
, PCR3L0
, PCR3U1
, PCR3L1
,
264 TC
/* ASID */, BUSCR
/* MMUBAR */,
265 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
266 MBAR1
/* MBAR */, MBAR2
/* SECMBAR */, MBAR0
/* SECMBAR */,
267 ROMBAR
/* ROMBAR0 */, RAMBAR
/* RAMBAR1 */,
270 static const enum m68k_register mcf5407_ctrl
[] = {
271 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
,
272 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
275 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
276 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
279 static const enum m68k_register mcf54418_ctrl
[] = {
280 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, ACR4
, ACR5
, ACR6
, ACR7
, MMUBAR
, RGPIOBAR
,
283 TC
/* ASID */, BUSCR
/* MMUBAR */,
284 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
285 RAMBAR
/* RAMBAR1 */,
288 static const enum m68k_register mcf54455_ctrl
[] = {
289 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
292 TC
/* ASID */, BUSCR
/* MMUBAR */,
293 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
294 RAMBAR
/* RAMBAR1 */,
297 static const enum m68k_register mcf5475_ctrl
[] = {
298 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
299 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
301 TC
/* ASID */, BUSCR
/* MMUBAR */,
302 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
303 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
306 static const enum m68k_register mcf5485_ctrl
[] = {
307 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
308 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
310 TC
/* ASID */, BUSCR
/* MMUBAR */,
311 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
312 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
315 static const enum m68k_register fido_ctrl
[] = {
316 SFC
, DFC
, USP
, VBR
, CAC
, MBO
,
319 #define cpu32_ctrl m68010_ctrl
321 static const enum m68k_register
*control_regs
;
323 /* Internal form of a 68020 instruction. */
327 const char *args
; /* List of opcode info. */
330 int numo
; /* Number of shorts in opcode. */
333 struct m68k_op operands
[6];
335 int nexp
; /* Number of exprs in use. */
336 struct m68k_exp exprs
[4];
338 int nfrag
; /* Number of frags we have to produce. */
341 int fragoff
; /* Where in the current opcode the frag ends. */
348 int nrel
; /* Num of reloc structs in use. */
355 /* In a pc relative address the difference between the address
356 of the offset and the address that the offset is relative
357 to. This depends on the addressing mode. Basically this
358 is the value to put in the offset field to address the
359 first byte of the offset, without regarding the special
360 significance of some values (in the branch instruction, for
363 /* Whether this expression needs special pic relocation, and if
365 enum pic_relocation pic_reloc
;
367 reloc
[5]; /* Five is enough??? */
370 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
371 #define float_of_arch(x) ((x) & mfloat)
372 #define mmu_of_arch(x) ((x) & mmmu)
373 #define arch_coldfire_p(x) ((x) & mcfisa_a)
374 #define arch_coldfire_fpu(x) ((x) & cfloat)
376 /* Macros for determining if cpu supports a specific addressing mode. */
377 #define HAVE_LONG_DISP(x) \
378 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
379 #define HAVE_LONG_CALL(x) \
380 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
381 #define HAVE_LONG_COND(x) \
382 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
383 #define HAVE_LONG_BRANCH(x) \
384 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
385 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
387 static struct m68k_it the_ins
; /* The instruction being assembled. */
389 #define op(ex) ((ex)->exp.X_op)
390 #define adds(ex) ((ex)->exp.X_add_symbol)
391 #define subs(ex) ((ex)->exp.X_op_symbol)
392 #define offs(ex) ((ex)->exp.X_add_number)
394 /* Macros for adding things to the m68k_it struct. */
395 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
397 /* Like addword, but goes BEFORE general operands. */
400 insop (int w
, const struct m68k_incant
*opcode
)
403 for (z
= the_ins
.numo
; z
> opcode
->m_codenum
; --z
)
404 the_ins
.opcode
[z
] = the_ins
.opcode
[z
- 1];
405 for (z
= 0; z
< the_ins
.nrel
; z
++)
406 the_ins
.reloc
[z
].n
+= 2;
407 for (z
= 0; z
< the_ins
.nfrag
; z
++)
408 the_ins
.fragb
[z
].fragoff
++;
409 the_ins
.opcode
[opcode
->m_codenum
] = w
;
413 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
416 add_fix (int width
, struct m68k_exp
*exp
, int pc_rel
, int pc_fix
)
418 the_ins
.reloc
[the_ins
.nrel
].n
= (width
== 'B' || width
== '3'
419 ? the_ins
.numo
* 2 - 1
421 ? the_ins
.numo
* 2 + 1
422 : the_ins
.numo
* 2));
423 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
424 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
425 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
426 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
427 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
430 /* Cause an extra frag to be generated here, inserting up to 10 bytes
431 (that value is chosen in the frag_var call in md_assemble). TYPE
432 is the subtype of the frag to be generated; its primary type is
433 rs_machine_dependent.
435 The TYPE parameter is also used by md_convert_frag_1 and
436 md_estimate_size_before_relax. The appropriate type of fixup will
437 be emitted by md_convert_frag_1.
439 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
441 add_frag (symbolS
*add
, offsetT off
, int type
)
443 the_ins
.fragb
[the_ins
.nfrag
].fragoff
= the_ins
.numo
;
444 the_ins
.fragb
[the_ins
.nfrag
].fadd
= add
;
445 the_ins
.fragb
[the_ins
.nfrag
].foff
= off
;
446 the_ins
.fragb
[the_ins
.nfrag
++].fragty
= type
;
450 (op (ex) != O_constant && op (ex) != O_big)
452 static char *crack_operand (char *str
, struct m68k_op
*opP
);
453 static int get_num (struct m68k_exp
*exp
, int ok
);
454 static int reverse_16_bits (int in
);
455 static int reverse_8_bits (int in
);
456 static void install_gen_operand (int mode
, int val
);
457 static void install_operand (int mode
, int val
);
458 static void s_bss (int);
459 static void s_data1 (int);
460 static void s_data2 (int);
461 static void s_even (int);
462 static void s_proc (int);
463 static void s_chip (int);
464 static void s_fopt (int);
465 static void s_opt (int);
466 static void s_reg (int);
467 static void s_restore (int);
468 static void s_save (int);
469 static void s_mri_if (int);
470 static void s_mri_else (int);
471 static void s_mri_endi (int);
472 static void s_mri_break (int);
473 static void s_mri_next (int);
474 static void s_mri_for (int);
475 static void s_mri_endf (int);
476 static void s_mri_repeat (int);
477 static void s_mri_until (int);
478 static void s_mri_while (int);
479 static void s_mri_endw (int);
480 static void s_m68k_cpu (int);
481 static void s_m68k_arch (int);
485 unsigned long arch
; /* Architecture features. */
486 const enum m68k_register
*control_regs
; /* Control regs on chip */
487 const char *name
; /* Name */
488 int alias
; /* Alias for a canonical name. If 1, then
489 succeeds canonical name, if -1 then
490 succeeds canonical name, if <-1 ||>1 this is a
491 deprecated name, and the next/previous name
495 /* We hold flags for features explicitly enabled and explicitly
497 static int current_architecture
;
498 static int not_current_architecture
;
499 static const struct m68k_cpu
*selected_arch
;
500 static const struct m68k_cpu
*selected_cpu
;
501 static int initialized
;
503 /* Architecture models. */
504 static const struct m68k_cpu m68k_archs
[] =
506 {m68000
, m68000_ctrl
, "68000", 0},
507 {m68010
, m68010_ctrl
, "68010", 0},
508 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
509 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
510 {m68040
, m68040_ctrl
, "68040", 0},
511 {m68060
, m68060_ctrl
, "68060", 0},
512 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
513 {fido_a
, fido_ctrl
, "fidoa", 0},
514 {mcfisa_a
|mcfhwdiv
, NULL
, "isaa", 0},
515 {mcfisa_a
|mcfhwdiv
|mcfisa_aa
|mcfusp
, NULL
, "isaaplus", 0},
516 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfusp
, NULL
, "isab", 0},
517 {mcfisa_a
|mcfhwdiv
|mcfisa_c
|mcfusp
, NULL
, "isac", 0},
518 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfmac
|mcfusp
, mcf_ctrl
, "cfv4", 0},
519 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "cfv4e", 0},
523 /* For -mno-mac we want to turn off all types of mac. */
524 static const unsigned no_mac
= mcfmac
| mcfemac
;
526 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
528 static const struct m68k_cpu m68k_extensions
[] =
530 {m68851
, NULL
, "68851", -1},
531 {m68881
, NULL
, "68881", -1},
532 {m68881
, NULL
, "68882", -1},
534 {cfloat
|m68881
, NULL
, "float", 0},
536 {mcfhwdiv
, NULL
, "div", 1},
537 {mcfusp
, NULL
, "usp", 1},
538 {mcfmac
, (void *)&no_mac
, "mac", 1},
539 {mcfemac
, NULL
, "emac", 1},
545 static const struct m68k_cpu m68k_cpus
[] =
547 {m68000
, m68000_ctrl
, "68000", 0},
548 {m68000
, m68000_ctrl
, "68ec000", 1},
549 {m68000
, m68000_ctrl
, "68hc000", 1},
550 {m68000
, m68000_ctrl
, "68hc001", 1},
551 {m68000
, m68000_ctrl
, "68008", 1},
552 {m68000
, m68000_ctrl
, "68302", 1},
553 {m68000
, m68000_ctrl
, "68306", 1},
554 {m68000
, m68000_ctrl
, "68307", 1},
555 {m68000
, m68000_ctrl
, "68322", 1},
556 {m68000
, m68000_ctrl
, "68356", 1},
557 {m68010
, m68010_ctrl
, "68010", 0},
558 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
559 {m68020
|m68881
|m68851
, m68020_ctrl
, "68k", 1},
560 {m68020
|m68881
|m68851
, m68020_ctrl
, "68ec020", 1},
561 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
562 {m68030
|m68881
|m68851
, m68020_ctrl
, "68ec030", 1},
563 {m68040
, m68040_ctrl
, "68040", 0},
564 {m68040
, m68040_ctrl
, "68ec040", 1},
565 {m68060
, m68060_ctrl
, "68060", 0},
566 {m68060
, m68060_ctrl
, "68ec060", 1},
568 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
569 {cpu32
|m68881
, cpu32_ctrl
, "68330", 1},
570 {cpu32
|m68881
, cpu32_ctrl
, "68331", 1},
571 {cpu32
|m68881
, cpu32_ctrl
, "68332", 1},
572 {cpu32
|m68881
, cpu32_ctrl
, "68333", 1},
573 {cpu32
|m68881
, cpu32_ctrl
, "68334", 1},
574 {cpu32
|m68881
, cpu32_ctrl
, "68336", 1},
575 {cpu32
|m68881
, cpu32_ctrl
, "68340", 1},
576 {cpu32
|m68881
, cpu32_ctrl
, "68341", 1},
577 {cpu32
|m68881
, cpu32_ctrl
, "68349", 1},
578 {cpu32
|m68881
, cpu32_ctrl
, "68360", 1},
580 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51", 0},
581 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51ac", 1},
582 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51ag", 1},
583 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51cn", 1},
584 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfmac
, mcf51_ctrl
, "51em", 1},
585 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfmac
, mcf51_ctrl
, "51je", 1},
586 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfemac
, mcf51_ctrl
, "51jf", 1},
587 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfemac
, mcf51_ctrl
, "51jg", 1},
588 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51jm", 1},
589 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfmac
, mcf51_ctrl
, "51mm", 1},
590 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51qe", 1},
591 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfemac
, mcf51_ctrl
, "51qm", 1},
593 {mcfisa_a
, mcf_ctrl
, "5200", 0},
594 {mcfisa_a
, mcf_ctrl
, "5202", 1},
595 {mcfisa_a
, mcf_ctrl
, "5204", 1},
596 {mcfisa_a
, mcf5206_ctrl
, "5206", 1},
598 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5206_ctrl
, "5206e", 0},
600 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5207", -1},
601 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5208", 0},
603 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5210a", 0},
604 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5211a", 1},
606 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5211", -1},
607 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5212", -1},
608 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5213", 0},
610 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5214", -1},
611 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5216", 0},
612 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "521x", 2},
614 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5221x_ctrl
, "5221x", 0},
616 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf52223_ctrl
, "52221", -1},
617 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf52223_ctrl
, "52223", 0},
619 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52230", -1},
620 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52233", -1},
621 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52234", -1},
622 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52235", 0},
624 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5224", -1},
625 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5225", 0},
627 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52277_ctrl
, "52274", -1},
628 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52277_ctrl
, "52277", 0},
630 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5232", -1},
631 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5233", -1},
632 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5234", -1},
633 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5235", -1},
634 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "523x", 0},
636 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5249_ctrl
, "5249", 0},
637 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5250_ctrl
, "5250", 0},
638 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5253_ctrl
, "5253", 0},
640 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52252", -1},
641 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52254", -1},
642 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52255", -1},
643 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52256", -1},
644 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52258", -1},
645 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52259", 0},
647 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5270", -1},
648 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5271", 0},
650 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5272_ctrl
, "5272", 0},
652 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5274", -1},
653 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5275", 0},
655 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5280", -1},
656 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5281", -1},
657 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5282", -1},
658 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "528x", 0},
660 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53011", -1},
661 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53012", -1},
662 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53013", -1},
663 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53014", -1},
664 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53015", -1},
665 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53016", -1},
666 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53017", 0},
668 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5307_ctrl
, "5307", 0},
670 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5327", -1},
671 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5328", -1},
672 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5329", -1},
673 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "532x", 0},
675 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5372", -1},
676 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5373", -1},
677 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "537x", 0},
679 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfmac
, mcf5407_ctrl
, "5407",0},
681 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54410", -1},
682 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54415", -1},
683 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54416", -1},
684 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54417", -1},
685 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54418", 0},
687 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54450", -1},
688 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54451", -1},
689 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54452", -1},
690 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54453", -1},
691 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54454", -1},
692 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54455", 0},
694 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5470", -1},
695 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5471", -1},
696 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5472", -1},
697 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5473", -1},
698 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5474", -1},
699 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5475", -1},
700 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "547x", 0},
702 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5480", -1},
703 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5481", -1},
704 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5482", -1},
705 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5483", -1},
706 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5484", -1},
707 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5485", -1},
708 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "548x", 0},
710 {fido_a
, fido_ctrl
, "fidoa", 0},
711 {fido_a
, fido_ctrl
, "fido", 1},
716 static const struct m68k_cpu
*m68k_lookup_cpu
717 (const char *, const struct m68k_cpu
*, int, int *);
718 static int m68k_set_arch (const char *, int, int);
719 static int m68k_set_cpu (const char *, int, int);
720 static int m68k_set_extension (const char *, int, int);
721 static void m68k_init_arch (void);
723 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
724 architecture and we have a lot of relaxation modes. */
726 /* Macros used in the relaxation code. */
727 #define TAB(x,y) (((x) << 2) + (y))
728 #define TABTYPE(x) ((x) >> 2)
730 /* Relaxation states. */
736 /* Here are all the relaxation modes we support. First we can relax ordinary
737 branches. On 68020 and higher and on CPU32 all branch instructions take
738 three forms, so on these CPUs all branches always remain as such. When we
739 have to expand to the LONG form on a 68000, though, we substitute an
740 absolute jump instead. This is a direct replacement for unconditional
741 branches and a branch over a jump for conditional branches. However, if the
742 user requires PIC and disables this with --pcrel, we can only relax between
743 BYTE and SHORT forms, punting if that isn't enough. This gives us four
744 different relaxation modes for branches: */
746 #define BRANCHBWL 0 /* Branch byte, word, or long. */
747 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
748 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
749 #define BRANCHBW 3 /* Branch byte or word. */
751 /* We also relax coprocessor branches and DBcc's. All CPUs that support
752 coprocessor branches support them in word and long forms, so we have only
753 one relaxation mode for them. DBcc's are word only on all CPUs. We can
754 relax them to the LONG form with a branch-around sequence. This sequence
755 can use a long branch (if available) or an absolute jump (if acceptable).
756 This gives us two relaxation modes. If long branches are not available and
757 absolute jumps are not acceptable, we don't relax DBcc's. */
759 #define FBRANCH 4 /* Coprocessor branch. */
760 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
761 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
763 /* That's all for instruction relaxation. However, we also relax PC-relative
764 operands. Specifically, we have three operand relaxation modes. On the
765 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
766 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
767 two. Also PC+displacement+index operands in their simple form (with a non-
768 suppressed index without memory indirection) are supported on all CPUs, but
769 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
770 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
771 form of the PC+displacement+index operand. Finally, some absolute operands
772 can be relaxed down to 16-bit PC-relative. */
774 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
775 #define PCINDEX 8 /* PC + displacement + index. */
776 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
778 /* This relaxation is required for branches where there is no long
779 branch and we are in pcrel mode. We generate a bne/beq pair. */
780 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs
783 /* Note that calls to frag_var need to specify the maximum expansion
784 needed; this is currently 12 bytes for bne/beq pair. */
785 #define FRAG_VAR_SIZE 12
788 How far Forward this mode will reach:
789 How far Backward this mode will reach:
790 How many bytes this mode will add to the size of the frag
791 Which mode to go to if the offset won't fit in this one
793 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
794 relax_typeS md_relax_table
[] =
796 { 127, -128, 0, TAB (BRANCHBWL
, SHORT
) },
797 { 32767, -32768, 2, TAB (BRANCHBWL
, LONG
) },
801 { 127, -128, 0, TAB (BRABSJUNC
, SHORT
) },
802 { 32767, -32768, 2, TAB (BRABSJUNC
, LONG
) },
806 { 127, -128, 0, TAB (BRABSJCOND
, SHORT
) },
807 { 32767, -32768, 2, TAB (BRABSJCOND
, LONG
) },
811 { 127, -128, 0, TAB (BRANCHBW
, SHORT
) },
816 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
817 { 32767, -32768, 2, TAB (FBRANCH
, LONG
) },
821 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
822 { 32767, -32768, 2, TAB (DBCCLBR
, LONG
) },
826 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
827 { 32767, -32768, 2, TAB (DBCCABSJ
, LONG
) },
831 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
832 { 32767, -32768, 2, TAB (PCREL1632
, LONG
) },
836 { 125, -130, 0, TAB (PCINDEX
, SHORT
) },
837 { 32765, -32770, 2, TAB (PCINDEX
, LONG
) },
841 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
842 { 32767, -32768, 2, TAB (ABSTOPCREL
, LONG
) },
846 { 127, -128, 0, TAB (BRANCHBWPL
, SHORT
) },
847 { 32767, -32768, 2, TAB (BRANCHBWPL
, LONG
) },
852 /* These are the machine dependent pseudo-ops. These are included so
853 the assembler can work on the output from the SUN C compiler, which
856 /* This table describes all the machine specific pseudo-ops the assembler
857 has to support. The fields are:
858 pseudo-op name without dot
859 function to call to execute this pseudo-op
860 Integer arg to pass to the function. */
861 const pseudo_typeS md_pseudo_table
[] =
863 {"data1", s_data1
, 0},
864 {"data2", s_data2
, 0},
867 {"skip", s_space
, 0},
869 {"align", s_align_bytes
, 0},
870 {"swbeg", s_ignore
, 0},
871 {"long", m68k_elf_cons
, 4},
872 {"extend", float_cons
, 'x'},
873 {"ldouble", float_cons
, 'x'},
875 {"arch", s_m68k_arch
, 0},
876 {"cpu", s_m68k_cpu
, 0},
877 {"gnu_attribute", m68k_elf_gnu_attribute
, 0},
879 /* The following pseudo-ops are supported for MRI compatibility. */
881 {"comline", s_space
, 1},
883 {"mask2", s_ignore
, 0},
886 {"restore", s_restore
, 0},
890 {"if.b", s_mri_if
, 'b'},
891 {"if.w", s_mri_if
, 'w'},
892 {"if.l", s_mri_if
, 'l'},
893 {"else", s_mri_else
, 0},
894 {"else.s", s_mri_else
, 's'},
895 {"else.l", s_mri_else
, 'l'},
896 {"endi", s_mri_endi
, 0},
897 {"break", s_mri_break
, 0},
898 {"break.s", s_mri_break
, 's'},
899 {"break.l", s_mri_break
, 'l'},
900 {"next", s_mri_next
, 0},
901 {"next.s", s_mri_next
, 's'},
902 {"next.l", s_mri_next
, 'l'},
903 {"for", s_mri_for
, 0},
904 {"for.b", s_mri_for
, 'b'},
905 {"for.w", s_mri_for
, 'w'},
906 {"for.l", s_mri_for
, 'l'},
907 {"endf", s_mri_endf
, 0},
908 {"repeat", s_mri_repeat
, 0},
909 {"until", s_mri_until
, 0},
910 {"until.b", s_mri_until
, 'b'},
911 {"until.w", s_mri_until
, 'w'},
912 {"until.l", s_mri_until
, 'l'},
913 {"while", s_mri_while
, 0},
914 {"while.b", s_mri_while
, 'b'},
915 {"while.w", s_mri_while
, 'w'},
916 {"while.l", s_mri_while
, 'l'},
917 {"endw", s_mri_endw
, 0},
922 /* The mote pseudo ops are put into the opcode table, since they
923 don't start with a . they look like opcodes to gas. */
925 const pseudo_typeS mote_pseudo_table
[] =
938 {"xdef", s_globl
, 0},
939 {"align", s_align_bytes
, 0},
943 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
944 gives identical results to a 32-bit host. */
945 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
946 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
948 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
949 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
950 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
951 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
953 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
954 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
955 #define islong(x) (1)
957 static char notend_table
[256];
958 static char alt_notend_table
[256];
960 (! (notend_table[(unsigned char) *s] \
962 && alt_notend_table[(unsigned char) s[1]])))
965 /* Return zero if the reference to SYMBOL from within the same segment may
968 /* On an ELF system, we can't relax an externally visible symbol,
969 because it may be overridden by a shared library. However, if
970 TARGET_OS is "elf", then we presume that we are assembling for an
971 embedded system, in which case we don't have to worry about shared
972 libraries, and we can relax any external sym. */
974 #define relaxable_symbol(symbol) \
975 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
976 || S_IS_WEAK (symbol)))
978 /* Compute the relocation code for a fixup of SIZE bytes, using pc
979 relative relocation if PCREL is non-zero. PIC says whether a special
980 pic relocation was requested. */
982 static bfd_reloc_code_real_type
983 get_reloc_code (int size
, int pcrel
, enum pic_relocation pic
)
991 return BFD_RELOC_8_GOT_PCREL
;
993 return BFD_RELOC_16_GOT_PCREL
;
995 return BFD_RELOC_32_GOT_PCREL
;
1003 return BFD_RELOC_8_GOTOFF
;
1005 return BFD_RELOC_16_GOTOFF
;
1007 return BFD_RELOC_32_GOTOFF
;
1015 return BFD_RELOC_8_PLT_PCREL
;
1017 return BFD_RELOC_16_PLT_PCREL
;
1019 return BFD_RELOC_32_PLT_PCREL
;
1027 return BFD_RELOC_8_PLTOFF
;
1029 return BFD_RELOC_16_PLTOFF
;
1031 return BFD_RELOC_32_PLTOFF
;
1039 return BFD_RELOC_68K_TLS_GD8
;
1041 return BFD_RELOC_68K_TLS_GD16
;
1043 return BFD_RELOC_68K_TLS_GD32
;
1051 return BFD_RELOC_68K_TLS_LDM8
;
1053 return BFD_RELOC_68K_TLS_LDM16
;
1055 return BFD_RELOC_68K_TLS_LDM32
;
1063 return BFD_RELOC_68K_TLS_LDO8
;
1065 return BFD_RELOC_68K_TLS_LDO16
;
1067 return BFD_RELOC_68K_TLS_LDO32
;
1075 return BFD_RELOC_68K_TLS_IE8
;
1077 return BFD_RELOC_68K_TLS_IE16
;
1079 return BFD_RELOC_68K_TLS_IE32
;
1087 return BFD_RELOC_68K_TLS_LE8
;
1089 return BFD_RELOC_68K_TLS_LE16
;
1091 return BFD_RELOC_68K_TLS_LE32
;
1101 return BFD_RELOC_8_PCREL
;
1103 return BFD_RELOC_16_PCREL
;
1105 return BFD_RELOC_32_PCREL
;
1115 return BFD_RELOC_16
;
1117 return BFD_RELOC_32
;
1124 if (pic
== pic_none
)
1125 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
1127 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
1131 if (pic
== pic_none
)
1132 as_bad (_("Can not do %d byte relocation"), size
);
1134 as_bad (_("Can not do %d byte pic relocation"), size
);
1137 return BFD_RELOC_NONE
;
1140 /* Here we decide which fixups can be adjusted to make them relative
1141 to the beginning of the section instead of the symbol. Basically
1142 we need to make sure that the dynamic relocations are done
1143 correctly, so in some cases we force the original symbol to be
1146 tc_m68k_fix_adjustable (fixS
*fixP
)
1148 /* Adjust_reloc_syms doesn't know about the GOT. */
1149 switch (fixP
->fx_r_type
)
1151 case BFD_RELOC_8_GOT_PCREL
:
1152 case BFD_RELOC_16_GOT_PCREL
:
1153 case BFD_RELOC_32_GOT_PCREL
:
1154 case BFD_RELOC_8_GOTOFF
:
1155 case BFD_RELOC_16_GOTOFF
:
1156 case BFD_RELOC_32_GOTOFF
:
1157 case BFD_RELOC_8_PLT_PCREL
:
1158 case BFD_RELOC_16_PLT_PCREL
:
1159 case BFD_RELOC_32_PLT_PCREL
:
1160 case BFD_RELOC_8_PLTOFF
:
1161 case BFD_RELOC_16_PLTOFF
:
1162 case BFD_RELOC_32_PLTOFF
:
1163 case BFD_RELOC_68K_TLS_GD32
:
1164 case BFD_RELOC_68K_TLS_GD16
:
1165 case BFD_RELOC_68K_TLS_GD8
:
1166 case BFD_RELOC_68K_TLS_LDM32
:
1167 case BFD_RELOC_68K_TLS_LDM16
:
1168 case BFD_RELOC_68K_TLS_LDM8
:
1169 case BFD_RELOC_68K_TLS_LDO32
:
1170 case BFD_RELOC_68K_TLS_LDO16
:
1171 case BFD_RELOC_68K_TLS_LDO8
:
1172 case BFD_RELOC_68K_TLS_IE32
:
1173 case BFD_RELOC_68K_TLS_IE16
:
1174 case BFD_RELOC_68K_TLS_IE8
:
1175 case BFD_RELOC_68K_TLS_LE32
:
1176 case BFD_RELOC_68K_TLS_LE16
:
1177 case BFD_RELOC_68K_TLS_LE8
:
1180 case BFD_RELOC_VTABLE_INHERIT
:
1181 case BFD_RELOC_VTABLE_ENTRY
:
1190 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
1193 bfd_reloc_code_real_type code
;
1195 /* If the tcbit is set, then this was a fixup of a negative value
1196 that was never resolved. We do not have a reloc to handle this,
1197 so just return. We assume that other code will have detected this
1198 situation and produced a helpful error message, so we just tell the
1199 user that the reloc cannot be produced. */
1203 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1204 _("Unable to produce reloc against symbol '%s'"),
1205 S_GET_NAME (fixp
->fx_addsy
));
1209 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
1211 code
= fixp
->fx_r_type
;
1213 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1214 that fixup_segment converted a non-PC relative reloc into a
1215 PC relative reloc. In such a case, we need to convert the
1222 code
= BFD_RELOC_8_PCREL
;
1225 code
= BFD_RELOC_16_PCREL
;
1228 code
= BFD_RELOC_32_PCREL
;
1230 case BFD_RELOC_8_PCREL
:
1231 case BFD_RELOC_16_PCREL
:
1232 case BFD_RELOC_32_PCREL
:
1233 case BFD_RELOC_8_GOT_PCREL
:
1234 case BFD_RELOC_16_GOT_PCREL
:
1235 case BFD_RELOC_32_GOT_PCREL
:
1236 case BFD_RELOC_8_GOTOFF
:
1237 case BFD_RELOC_16_GOTOFF
:
1238 case BFD_RELOC_32_GOTOFF
:
1239 case BFD_RELOC_8_PLT_PCREL
:
1240 case BFD_RELOC_16_PLT_PCREL
:
1241 case BFD_RELOC_32_PLT_PCREL
:
1242 case BFD_RELOC_8_PLTOFF
:
1243 case BFD_RELOC_16_PLTOFF
:
1244 case BFD_RELOC_32_PLTOFF
:
1245 case BFD_RELOC_68K_TLS_GD32
:
1246 case BFD_RELOC_68K_TLS_GD16
:
1247 case BFD_RELOC_68K_TLS_GD8
:
1248 case BFD_RELOC_68K_TLS_LDM32
:
1249 case BFD_RELOC_68K_TLS_LDM16
:
1250 case BFD_RELOC_68K_TLS_LDM8
:
1251 case BFD_RELOC_68K_TLS_LDO32
:
1252 case BFD_RELOC_68K_TLS_LDO16
:
1253 case BFD_RELOC_68K_TLS_LDO8
:
1254 case BFD_RELOC_68K_TLS_IE32
:
1255 case BFD_RELOC_68K_TLS_IE16
:
1256 case BFD_RELOC_68K_TLS_IE8
:
1257 case BFD_RELOC_68K_TLS_LE32
:
1258 case BFD_RELOC_68K_TLS_LE16
:
1259 case BFD_RELOC_68K_TLS_LE8
:
1262 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1263 _("Cannot make %s relocation PC relative"),
1264 bfd_get_reloc_code_name (code
));
1270 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1271 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
1273 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1274 MAP (1, 0, BFD_RELOC_8
);
1275 MAP (2, 0, BFD_RELOC_16
);
1276 MAP (4, 0, BFD_RELOC_32
);
1277 MAP (1, 1, BFD_RELOC_8_PCREL
);
1278 MAP (2, 1, BFD_RELOC_16_PCREL
);
1279 MAP (4, 1, BFD_RELOC_32_PCREL
);
1287 reloc
= XNEW (arelent
);
1288 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
1289 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1290 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1291 if (!fixp
->fx_pcrel
)
1292 reloc
->addend
= fixp
->fx_addnumber
;
1294 reloc
->addend
= (section
->vma
1295 + fixp
->fx_pcrel_adjust
1296 + fixp
->fx_addnumber
1297 + md_pcrel_from (fixp
));
1299 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1300 gas_assert (reloc
->howto
!= 0);
1305 /* Handle of the OPCODE hash table. NULL means any use before
1306 m68k_ip_begin() will crash. */
1307 static htab_t op_hash
;
1309 /* Assemble an m68k instruction. */
1312 m68k_ip (char *instring
)
1315 struct m68k_op
*opP
;
1316 const struct m68k_incant
*opcode
;
1318 int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1319 char *pdot
, *pdotmove
;
1320 enum m68k_size siz1
, siz2
;
1324 struct m68k_op operands_backup
[6];
1325 LITTLENUM_TYPE words
[6];
1326 LITTLENUM_TYPE
*wordp
;
1327 unsigned long ok_arch
= 0;
1329 if (*instring
== ' ')
1330 instring
++; /* Skip leading whitespace. */
1332 /* Scan up to end of operation-code, which MUST end in end-of-string
1333 or exactly 1 space. */
1335 for (p
= instring
; *p
!= '\0'; p
++)
1345 the_ins
.error
= _("No operator");
1349 /* p now points to the end of the opcode name, probably whitespace.
1350 Make sure the name is null terminated by clobbering the
1351 whitespace, look it up in the hash table, then fix it back.
1352 Remove a dot, first, since the opcode tables have none. */
1355 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1356 *pdotmove
= pdotmove
[1];
1362 opcode
= (const struct m68k_incant
*) str_hash_find (op_hash
, instring
);
1367 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1368 *pdotmove
= pdotmove
[-1];
1375 the_ins
.error
= _("Unknown operator");
1379 /* Found a legitimate opcode, start matching operands. */
1383 if (opcode
->m_operands
== 0)
1385 char *old
= input_line_pointer
;
1387 input_line_pointer
= p
;
1388 /* Ahh - it's a motorola style pseudo op. */
1389 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1390 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1391 input_line_pointer
= old
;
1397 if (flag_mri
&& opcode
->m_opnum
== 0)
1399 /* In MRI mode, random garbage is allowed after an instruction
1400 which accepts no operands. */
1401 the_ins
.args
= opcode
->m_operands
;
1402 the_ins
.numargs
= opcode
->m_opnum
;
1403 the_ins
.numo
= opcode
->m_codenum
;
1404 the_ins
.opcode
[0] = getone (opcode
);
1405 the_ins
.opcode
[1] = gettwo (opcode
);
1409 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1411 p
= crack_operand (p
, opP
);
1415 the_ins
.error
= opP
->error
;
1420 opsfound
= opP
- &the_ins
.operands
[0];
1422 /* This ugly hack is to support the floating pt opcodes in their
1423 standard form. Essentially, we fake a first entry of type COP#1 */
1424 if (opcode
->m_operands
[0] == 'I')
1428 for (n
= opsfound
; n
> 0; --n
)
1429 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1431 memset (&the_ins
.operands
[0], '\0', sizeof (the_ins
.operands
[0]));
1432 the_ins
.operands
[0].mode
= CONTROL
;
1433 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1437 /* We've got the operands. Find an opcode that'll accept them. */
1440 /* If we didn't get the right number of ops, or we have no
1441 common model with this pattern then reject this pattern. */
1443 ok_arch
|= opcode
->m_arch
;
1444 if (opsfound
!= opcode
->m_opnum
1445 || ((opcode
->m_arch
& current_architecture
) == 0))
1451 /* Make a copy of the operands of this insn so that
1452 we can modify them safely, should we want to. */
1453 gas_assert (opsfound
<= (int) ARRAY_SIZE (operands_backup
));
1454 for (i
= 0; i
< opsfound
; i
++)
1455 operands_backup
[i
] = the_ins
.operands
[i
];
1457 for (s
= opcode
->m_operands
, opP
= &operands_backup
[0];
1461 /* Warning: this switch is huge! */
1462 /* I've tried to organize the cases into this order:
1463 non-alpha first, then alpha by letter. Lower-case
1464 goes directly before uppercase counterpart. */
1465 /* Code with multiple case ...: gets sorted by the lowest
1466 case ... it belongs to. I hope this makes sense. */
1572 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1589 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1608 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1618 if (opP
->mode
!= IMMED
)
1620 else if (s
[1] == 'b'
1621 && ! isvar (&opP
->disp
)
1622 && (opP
->disp
.exp
.X_op
!= O_constant
1623 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1625 else if (s
[1] == 'B'
1626 && ! isvar (&opP
->disp
)
1627 && (opP
->disp
.exp
.X_op
!= O_constant
1628 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1630 else if (s
[1] == 'w'
1631 && ! isvar (&opP
->disp
)
1632 && (opP
->disp
.exp
.X_op
!= O_constant
1633 || ! isword (opP
->disp
.exp
.X_add_number
)))
1635 else if (s
[1] == 'W'
1636 && ! isvar (&opP
->disp
)
1637 && (opP
->disp
.exp
.X_op
!= O_constant
1638 || ! issword (opP
->disp
.exp
.X_add_number
)))
1644 if (opP
->mode
!= IMMED
)
1649 if (opP
->mode
== AREG
1650 || opP
->mode
== CONTROL
1651 || opP
->mode
== FPREG
1652 || opP
->mode
== IMMED
1653 || opP
->mode
== REGLST
1654 || (opP
->mode
!= ABSL
1656 || opP
->reg
== ZPC
)))
1661 if (opP
->mode
== CONTROL
1662 || opP
->mode
== FPREG
1663 || opP
->mode
== REGLST
1664 || opP
->mode
== IMMED
1665 || (opP
->mode
!= ABSL
1667 || opP
->reg
== ZPC
)))
1695 if (opP
->mode
== CONTROL
1696 || opP
->mode
== FPREG
1697 || opP
->mode
== REGLST
)
1702 if (opP
->mode
!= AINC
)
1707 if (opP
->mode
!= ADEC
)
1757 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1778 case '~': /* For now! (JF FOO is this right?) */
1800 if (opP
->mode
!= CONTROL
1801 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1806 if (opP
->mode
!= AREG
)
1811 if (opP
->mode
!= AINDR
)
1816 if (opP
->mode
!= AINDR
&& opP
->mode
!= AINC
&& opP
->mode
!= ADEC
1817 && (opP
->mode
!= DISP
1819 || opP
->reg
> ADDR7
))
1824 if (opP
->mode
!= ABSL
1826 && startswith (instring
, "jbsr")))
1849 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1854 if (opP
->mode
!= DISP
1856 || opP
->reg
> ADDR7
)
1861 if (opP
->mode
!= DREG
)
1866 if (opP
->reg
!= ACC
)
1871 if (opP
->reg
!= ACC
&& opP
->reg
!= ACC1
1872 && opP
->reg
!= ACC2
&& opP
->reg
!= ACC3
)
1877 if (opP
->mode
!= FPREG
)
1882 if (opP
->reg
!= MACSR
)
1887 if (opP
->reg
!= ACCEXT01
&& opP
->reg
!= ACCEXT23
)
1892 if (opP
->reg
!= MASK
)
1897 if (opP
->mode
!= CONTROL
1904 if (opP
->mode
!= LSH
&& opP
->mode
!= RSH
)
1909 if (opP
->mode
!= CONTROL
1911 || opP
->reg
> last_movec_reg
1916 const enum m68k_register
*rp
;
1918 for (rp
= control_regs
; *rp
; rp
++)
1920 if (*rp
== opP
->reg
)
1922 /* In most CPUs RAMBAR refers to control reg
1923 c05 (RAMBAR1), but a few CPUs have it
1924 refer to c04 (RAMBAR0). */
1925 else if (*rp
== RAMBAR_ALT
&& opP
->reg
== RAMBAR
)
1927 opP
->reg
= RAMBAR_ALT
;
1937 if (opP
->mode
!= IMMED
)
1943 if (opP
->mode
== DREG
1944 || opP
->mode
== AREG
1945 || opP
->mode
== FPREG
)
1954 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1957 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1960 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1968 else if (opP
->mode
== CONTROL
)
1977 opP
->mask
= 1 << 24;
1980 opP
->mask
= 1 << 25;
1983 opP
->mask
= 1 << 26;
1992 else if (opP
->mode
!= REGLST
)
1994 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
1996 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
2001 if (opP
->mode
!= IMMED
)
2003 else if (opP
->disp
.exp
.X_op
!= O_constant
2004 || ! issbyte (opP
->disp
.exp
.X_add_number
))
2006 else if (! m68k_quick
2007 && instring
[3] != 'q'
2008 && instring
[4] != 'q')
2013 if (opP
->mode
!= DREG
2014 && opP
->mode
!= IMMED
2015 && opP
->mode
!= ABSL
)
2020 if (opP
->mode
!= IMMED
)
2022 else if (opP
->disp
.exp
.X_op
!= O_constant
2023 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
2025 else if (! m68k_quick
2026 && (startswith (instring
, "add")
2027 || startswith (instring
, "sub"))
2028 && instring
[3] != 'q')
2033 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
2038 if (opP
->mode
!= AINDR
2039 && (opP
->mode
!= BASE
2041 && opP
->reg
!= ZADDR0
)
2042 || opP
->disp
.exp
.X_op
!= O_absent
2043 || ((opP
->index
.reg
< DATA0
2044 || opP
->index
.reg
> DATA7
)
2045 && (opP
->index
.reg
< ADDR0
2046 || opP
->index
.reg
> ADDR7
))
2047 || opP
->index
.size
!= SIZE_UNSPEC
2048 || opP
->index
.scale
!= 1))
2053 if (opP
->mode
!= CONTROL
2054 || ! (opP
->reg
== FPI
2056 || opP
->reg
== FPC
))
2061 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
2066 if (opP
->mode
!= IMMED
)
2068 else if (opP
->disp
.exp
.X_op
!= O_constant
2069 || TRUNC (opP
->disp
.exp
.X_add_number
) > 7)
2074 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
2079 if (opP
->mode
!= IMMED
)
2081 else if (opP
->disp
.exp
.X_op
!= O_constant
2082 || (TRUNC (opP
->disp
.exp
.X_add_number
) != 0xffffffff
2083 && TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 6))
2088 if (opP
->mode
!= IMMED
)
2090 else if (opP
->disp
.exp
.X_op
!= O_constant
2091 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
2096 if (opP
->mode
!= IMMED
)
2098 else if (opP
->disp
.exp
.X_op
!= O_constant
2099 || TRUNC (opP
->disp
.exp
.X_add_number
) > 511)
2103 /* JF these are out of order. We could put them
2104 in order if we were willing to put up with
2105 bunches of #ifdef m68851s in the code.
2107 Don't forget that you need these operands
2108 to use 68030 MMU instructions. */
2110 /* Memory addressing mode used by pflushr. */
2112 if (opP
->mode
== CONTROL
2113 || opP
->mode
== FPREG
2114 || opP
->mode
== DREG
2115 || opP
->mode
== AREG
2116 || opP
->mode
== REGLST
)
2118 /* We should accept immediate operands, but they
2119 supposedly have to be quad word, and we don't
2120 handle that. I would like to see what a Motorola
2121 assembler does before doing something here. */
2122 if (opP
->mode
== IMMED
)
2127 if (opP
->mode
!= CONTROL
2128 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
2133 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
2138 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
2143 if (opP
->mode
!= CONTROL
2146 && opP
->reg
!= SCC
))
2151 if (opP
->mode
!= CONTROL
2157 if (opP
->mode
!= CONTROL
2160 && opP
->reg
!= CRP
))
2184 if (opP
->mode
!= CONTROL
2185 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
2186 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
2191 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
2196 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
2201 if (opP
->mode
!= CONTROL
2210 if (opP
->mode
!= ABSL
)
2215 if (opP
->reg
< DATA0L
|| opP
->reg
> ADDR7U
)
2217 /* FIXME: kludge instead of fixing parser:
2218 upper/lower registers are *not* CONTROL
2219 registers, but ordinary ones. */
2220 if ((opP
->reg
>= DATA0L
&& opP
->reg
<= DATA7L
)
2221 || (opP
->reg
>= DATA0U
&& opP
->reg
<= DATA7U
))
2228 if (!(opP
->mode
== AINDR
2229 || (opP
->mode
== DISP
2230 && !(opP
->reg
== PC
|| opP
->reg
== ZPC
))))
2235 if (!(opP
->mode
== AINDR
|| opP
->mode
== DISP
))
2247 /* Since we have found the correct instruction, copy
2248 in the modifications that we may have made. */
2250 for (i
= 0; i
< opsfound
; i
++)
2251 the_ins
.operands
[i
] = operands_backup
[i
];
2257 opcode
= opcode
->m_next
;
2262 && !(ok_arch
& current_architecture
))
2264 const struct m68k_cpu
*cpu
;
2267 char *buf
= XNEWVEC (char, space
+ 1);
2271 the_ins
.error
= buf
;
2272 /* Make sure there's a NUL at the end of the buffer -- strncpy
2273 won't write one when it runs out of buffer. */
2275 #define APPEND(STRING) \
2276 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2278 APPEND (_("invalid instruction for this architecture; needs "));
2282 APPEND ("ColdFire ISA_A");
2285 APPEND ("ColdFire ");
2286 APPEND (_("hardware divide"));
2289 APPEND ("ColdFire ISA_A+");
2292 APPEND ("ColdFire ISA_B");
2295 APPEND ("ColdFire ISA_C");
2298 APPEND ("ColdFire fpu");
2301 APPEND ("M68K fpu");
2304 APPEND ("M68K mmu");
2308 APPEND (_("or higher"));
2312 APPEND (_("or higher"));
2316 APPEND (_("or higher"));
2324 for (cpu
= m68k_cpus
; cpu
->name
; cpu
++)
2325 if (!cpu
->alias
&& (cpu
->arch
& ok_arch
))
2327 const struct m68k_cpu
*alias
;
2328 int seen_master
= 0;
2334 for (alias
= cpu
; alias
!= m68k_cpus
; alias
--)
2335 if (alias
[-1].alias
>= 0)
2337 for (; !seen_master
|| alias
->alias
> 0; alias
++)
2347 APPEND (alias
->name
);
2360 /* We ran out of space, so replace the end of the list
2365 strcpy (buf
, " ...");
2369 the_ins
.error
= _("operands mismatch");
2376 /* Now assemble it. */
2377 the_ins
.args
= opcode
->m_operands
;
2378 the_ins
.numargs
= opcode
->m_opnum
;
2379 the_ins
.numo
= opcode
->m_codenum
;
2380 the_ins
.opcode
[0] = getone (opcode
);
2381 the_ins
.opcode
[1] = gettwo (opcode
);
2383 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2388 /* This switch is a doozy.
2389 Watch the first step; it's a big one! */
2422 tmpreg
= 0x3c; /* 7.4 */
2423 if (strchr ("bwl", s
[1]))
2424 nextword
= get_num (&opP
->disp
, 90);
2426 nextword
= get_num (&opP
->disp
, 0);
2427 if (isvar (&opP
->disp
))
2428 add_fix (s
[1], &opP
->disp
, 0, 0);
2432 if (!isbyte (nextword
))
2433 opP
->error
= _("operand out of range");
2438 if (!isword (nextword
))
2439 opP
->error
= _("operand out of range");
2444 if (!issword (nextword
))
2445 opP
->error
= _("operand out of range");
2450 addword (nextword
>> 16);
2477 /* We gotta put out some float. */
2478 if (op (&opP
->disp
) != O_big
)
2483 /* Can other cases happen here? */
2484 if (op (&opP
->disp
) != O_constant
)
2487 val
= (valueT
) offs (&opP
->disp
);
2491 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2492 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2496 offs (&opP
->disp
) = gencnt
;
2498 if (offs (&opP
->disp
) > 0)
2500 if (offs (&opP
->disp
) > baseo
)
2502 as_warn (_("Bignum too big for %c format; truncated"),
2504 offs (&opP
->disp
) = baseo
;
2506 baseo
-= offs (&opP
->disp
);
2509 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
2510 offs (&opP
->disp
)--;
2515 gen_to_words (words
, baseo
, (long) outro
);
2516 for (wordp
= words
; baseo
--; wordp
++)
2520 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2523 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2526 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2529 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2532 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2536 nextword
= get_num (&opP
->disp
, 90);
2538 /* Convert mode 5 addressing with a zero offset into
2539 mode 2 addressing to reduce the instruction size by a
2541 if (! isvar (&opP
->disp
)
2543 && (opP
->disp
.size
== SIZE_UNSPEC
)
2544 && (opP
->reg
>= ADDR0
)
2545 && (opP
->reg
<= ADDR7
))
2547 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2552 && ! isvar (&opP
->disp
)
2555 opP
->disp
.exp
.X_op
= O_symbol
;
2556 opP
->disp
.exp
.X_add_symbol
=
2557 section_symbol (absolute_section
);
2560 /* Force into index mode. Hope this works. */
2562 /* We do the first bit for 32-bit displacements, and the
2563 second bit for 16 bit ones. It is possible that we
2564 should make the default be WORD instead of LONG, but
2565 I think that'd break GCC, so we put up with a little
2566 inefficiency for the sake of working output. */
2568 if (!issword (nextword
)
2569 || (isvar (&opP
->disp
)
2570 && ((opP
->disp
.size
== SIZE_UNSPEC
2571 && flag_short_refs
== 0
2572 && cpu_of_arch (current_architecture
) >= m68020
2573 && ! arch_coldfire_p (current_architecture
))
2574 || opP
->disp
.size
== SIZE_LONG
)))
2576 if (cpu_of_arch (current_architecture
) < m68020
2577 || arch_coldfire_p (current_architecture
))
2579 _("displacement too large for this architecture; needs 68020 or higher");
2581 tmpreg
= 0x3B; /* 7.3 */
2583 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2584 if (isvar (&opP
->disp
))
2588 if (opP
->disp
.size
== SIZE_LONG
2589 /* If the displacement needs pic
2590 relocation it cannot be relaxed. */
2591 || opP
->disp
.pic_reloc
!= pic_none
)
2594 add_fix ('l', &opP
->disp
, 1, 2);
2598 add_frag (adds (&opP
->disp
),
2599 SEXT (offs (&opP
->disp
)),
2600 TAB (PCREL1632
, SZ_UNDEF
));
2607 add_fix ('l', &opP
->disp
, 0, 0);
2612 addword (nextword
>> 16);
2617 tmpreg
= 0x3A; /* 7.2 */
2619 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2621 if (isvar (&opP
->disp
))
2625 add_fix ('w', &opP
->disp
, 1, 0);
2628 add_fix ('w', &opP
->disp
, 0, 0);
2638 baseo
= get_num (&opP
->disp
, 90);
2639 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2640 outro
= get_num (&opP
->odisp
, 90);
2641 /* Figure out the `addressing mode'.
2642 Also turn on the BASE_DISABLE bit, if needed. */
2643 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2645 tmpreg
= 0x3b; /* 7.3 */
2646 if (opP
->reg
== ZPC
)
2649 else if (opP
->reg
== 0)
2652 tmpreg
= 0x30; /* 6.garbage */
2654 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2657 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2660 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2662 siz1
= opP
->disp
.size
;
2663 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2664 siz2
= opP
->odisp
.size
;
2668 /* Index register stuff. */
2669 if (opP
->index
.reg
!= 0
2670 && opP
->index
.reg
>= DATA
2671 && opP
->index
.reg
<= ADDR7
)
2673 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2675 if (opP
->index
.size
== SIZE_LONG
2676 || (opP
->index
.size
== SIZE_UNSPEC
2677 && m68k_index_width_default
== SIZE_LONG
))
2680 if ((opP
->index
.scale
!= 1
2681 && cpu_of_arch (current_architecture
) < m68020
)
2682 || (opP
->index
.scale
== 8
2683 && (arch_coldfire_p (current_architecture
)
2684 && !arch_coldfire_fpu (current_architecture
))))
2687 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2690 if (arch_coldfire_p (current_architecture
)
2691 && opP
->index
.size
== SIZE_WORD
)
2692 opP
->error
= _("invalid index size for coldfire");
2694 switch (opP
->index
.scale
)
2711 GET US OUT OF HERE! */
2713 /* Must be INDEX, with an index register. Address
2714 register cannot be ZERO-PC, and either :b was
2715 forced, or we know it will fit. For a 68000 or
2716 68010, force this mode anyways, because the
2717 larger modes aren't supported. */
2718 if (opP
->mode
== BASE
2719 && ((opP
->reg
>= ADDR0
2720 && opP
->reg
<= ADDR7
)
2723 if (siz1
== SIZE_BYTE
2724 || cpu_of_arch (current_architecture
) < m68020
2725 || arch_coldfire_p (current_architecture
)
2726 || (siz1
== SIZE_UNSPEC
2727 && ! isvar (&opP
->disp
)
2728 && issbyte (baseo
)))
2730 nextword
+= baseo
& 0xff;
2732 if (isvar (&opP
->disp
))
2734 /* Do a byte relocation. If it doesn't
2735 fit (possible on m68000) let the
2736 fixup processing complain later. */
2738 add_fix ('B', &opP
->disp
, 1, 1);
2740 add_fix ('B', &opP
->disp
, 0, 0);
2742 else if (siz1
!= SIZE_BYTE
)
2744 if (siz1
!= SIZE_UNSPEC
)
2745 as_warn (_("Forcing byte displacement"));
2746 if (! issbyte (baseo
))
2747 opP
->error
= _("byte displacement out of range");
2752 else if (siz1
== SIZE_UNSPEC
2754 && isvar (&opP
->disp
)
2755 && subs (&opP
->disp
) == NULL
2756 /* If the displacement needs pic
2757 relocation it cannot be relaxed. */
2758 && opP
->disp
.pic_reloc
== pic_none
)
2760 /* The code in md_convert_frag_1 needs to be
2761 able to adjust nextword. Call frag_grow
2762 to ensure that we have enough space in
2763 the frag obstack to make all the bytes
2766 nextword
+= baseo
& 0xff;
2768 add_frag (adds (&opP
->disp
),
2769 SEXT (offs (&opP
->disp
)),
2770 TAB (PCINDEX
, SZ_UNDEF
));
2778 nextword
|= 0x40; /* No index reg. */
2779 if (opP
->index
.reg
>= ZDATA0
2780 && opP
->index
.reg
<= ZDATA7
)
2781 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2782 else if (opP
->index
.reg
>= ZADDR0
2783 && opP
->index
.reg
<= ZADDR7
)
2784 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2787 /* It isn't simple. */
2789 if (cpu_of_arch (current_architecture
) < m68020
2790 || arch_coldfire_p (current_architecture
))
2792 _("invalid operand mode for this architecture; needs 68020 or higher");
2795 /* If the guy specified a width, we assume that it is
2796 wide enough. Maybe it isn't. If so, we lose. */
2800 if (isvar (&opP
->disp
)
2802 : ! issword (baseo
))
2807 else if (! isvar (&opP
->disp
) && baseo
== 0)
2816 as_warn (_(":b not permitted; defaulting to :w"));
2826 /* Figure out inner displacement stuff. */
2827 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2829 if (cpu_of_arch (current_architecture
) & cpu32
)
2830 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2834 if (isvar (&opP
->odisp
)
2836 : ! issword (outro
))
2841 else if (! isvar (&opP
->odisp
) && outro
== 0)
2850 as_warn (_(":b not permitted; defaulting to :w"));
2859 if (opP
->mode
== POST
2860 && (nextword
& 0x40) == 0)
2865 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2867 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2868 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2870 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2872 if (siz1
== SIZE_LONG
)
2873 addword (baseo
>> 16);
2874 if (siz1
!= SIZE_UNSPEC
)
2877 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2878 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2879 if (siz2
== SIZE_LONG
)
2880 addword (outro
>> 16);
2881 if (siz2
!= SIZE_UNSPEC
)
2887 nextword
= get_num (&opP
->disp
, 90);
2888 switch (opP
->disp
.size
)
2893 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2895 tmpreg
= 0x38; /* 7.0 */
2899 if (isvar (&opP
->disp
)
2900 && !subs (&opP
->disp
)
2901 && adds (&opP
->disp
)
2902 /* If the displacement needs pic relocation it
2903 cannot be relaxed. */
2904 && opP
->disp
.pic_reloc
== pic_none
2906 && !strchr ("~%&$?", s
[0]))
2908 tmpreg
= 0x3A; /* 7.2 */
2909 add_frag (adds (&opP
->disp
),
2910 SEXT (offs (&opP
->disp
)),
2911 TAB (ABSTOPCREL
, SZ_UNDEF
));
2916 if (isvar (&opP
->disp
))
2917 add_fix ('l', &opP
->disp
, 0, 0);
2919 tmpreg
= 0x39;/* 7.1 mode */
2920 addword (nextword
>> 16);
2925 as_bad (_("unsupported byte value; use a different suffix"));
2929 if (isvar (&opP
->disp
))
2930 add_fix ('w', &opP
->disp
, 0, 0);
2932 tmpreg
= 0x38;/* 7.0 mode */
2940 as_bad (_("unknown/incorrect operand"));
2944 /* If s[0] is '4', then this is for the mac instructions
2945 that can have a trailing_ampersand set. If so, set 0x100
2946 bit on tmpreg so install_gen_operand can check for it and
2947 set the appropriate bit (word2, bit 5). */
2950 if (opP
->trailing_ampersand
)
2953 install_gen_operand (s
[1], tmpreg
);
2959 { /* JF: I hate floating point! */
2974 tmpreg
= get_num (&opP
->disp
, tmpreg
);
2975 if (isvar (&opP
->disp
))
2976 add_fix (s
[1], &opP
->disp
, 0, 0);
2979 case 'b': /* Danger: These do no check for
2980 certain types of overflow.
2982 if (!isbyte (tmpreg
))
2983 opP
->error
= _("out of range");
2984 insop (tmpreg
, opcode
);
2985 if (isvar (&opP
->disp
))
2986 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
2987 (opcode
->m_codenum
) * 2 + 1;
2990 if (!issbyte (tmpreg
))
2991 opP
->error
= _("out of range");
2992 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
2993 if (isvar (&opP
->disp
))
2994 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
2997 if (!isword (tmpreg
))
2998 opP
->error
= _("out of range");
2999 insop (tmpreg
, opcode
);
3000 if (isvar (&opP
->disp
))
3001 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
3004 if (!issword (tmpreg
))
3005 opP
->error
= _("out of range");
3006 insop (tmpreg
, opcode
);
3007 if (isvar (&opP
->disp
))
3008 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
3011 /* Because of the way insop works, we put these two out
3013 insop (tmpreg
, opcode
);
3014 insop (tmpreg
>> 16, opcode
);
3015 if (isvar (&opP
->disp
))
3016 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
3024 install_operand (s
[1], tmpreg
);
3035 install_operand (s
[1], opP
->reg
- ADDR
);
3039 tmpreg
= get_num (&opP
->disp
, 90);
3044 add_fix ('B', &opP
->disp
, 1, -1);
3047 add_fix ('w', &opP
->disp
, 1, 0);
3052 the_ins
.opcode
[0] |= 0xff;
3053 add_fix ('l', &opP
->disp
, 1, 0);
3057 case 'g': /* Conditional branch */
3058 have_disp
= HAVE_LONG_CALL (current_architecture
);
3061 case 'b': /* Unconditional branch */
3062 have_disp
= HAVE_LONG_BRANCH (current_architecture
);
3063 use_pl
= LONG_BRANCH_VIA_COND (current_architecture
);
3066 case 's': /* Unconditional subroutine */
3067 have_disp
= HAVE_LONG_CALL (current_architecture
);
3070 if (subs (&opP
->disp
) /* We can't relax it. */
3071 /* If the displacement needs pic relocation it cannot be
3073 || opP
->disp
.pic_reloc
!= pic_none
)
3076 as_warn (_("Can't use long branches on this architecture"));
3080 /* This could either be a symbol, or an absolute
3081 address. If it's an absolute address, turn it into
3082 an absolute jump right here and keep it out of the
3084 if (adds (&opP
->disp
) == 0)
3086 if (the_ins
.opcode
[0] == 0x6000) /* jbra */
3087 the_ins
.opcode
[0] = 0x4EF9;
3088 else if (the_ins
.opcode
[0] == 0x6100) /* jbsr */
3089 the_ins
.opcode
[0] = 0x4EB9;
3092 the_ins
.opcode
[0] ^= 0x0100;
3093 the_ins
.opcode
[0] |= 0x0006;
3096 add_fix ('l', &opP
->disp
, 0, 0);
3102 /* Now we know it's going into the relaxer. Now figure
3103 out which mode. We try in this order of preference:
3104 long branch, absolute jump, byte/word branches only. */
3106 add_frag (adds (&opP
->disp
),
3107 SEXT (offs (&opP
->disp
)),
3108 TAB (BRANCHBWL
, SZ_UNDEF
));
3109 else if (! flag_keep_pcrel
)
3111 if ((the_ins
.opcode
[0] == 0x6000)
3112 || (the_ins
.opcode
[0] == 0x6100))
3113 add_frag (adds (&opP
->disp
),
3114 SEXT (offs (&opP
->disp
)),
3115 TAB (BRABSJUNC
, SZ_UNDEF
));
3117 add_frag (adds (&opP
->disp
),
3118 SEXT (offs (&opP
->disp
)),
3119 TAB (BRABSJCOND
, SZ_UNDEF
));
3122 add_frag (adds (&opP
->disp
),
3123 SEXT (offs (&opP
->disp
)),
3124 (use_pl
? TAB (BRANCHBWPL
, SZ_UNDEF
)
3125 : TAB (BRANCHBW
, SZ_UNDEF
)));
3128 if (isvar (&opP
->disp
))
3130 /* Check for DBcc instructions. We can relax them,
3131 but only if we have long branches and/or absolute
3133 if (((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
3134 && (HAVE_LONG_BRANCH (current_architecture
)
3135 || ! flag_keep_pcrel
))
3137 if (HAVE_LONG_BRANCH (current_architecture
))
3138 add_frag (adds (&opP
->disp
),
3139 SEXT (offs (&opP
->disp
)),
3140 TAB (DBCCLBR
, SZ_UNDEF
));
3142 add_frag (adds (&opP
->disp
),
3143 SEXT (offs (&opP
->disp
)),
3144 TAB (DBCCABSJ
, SZ_UNDEF
));
3147 add_fix ('w', &opP
->disp
, 1, 0);
3151 case 'C': /* Fixed size LONG coproc branches. */
3152 add_fix ('l', &opP
->disp
, 1, 0);
3156 case 'c': /* Var size Coprocesssor branches. */
3157 if (subs (&opP
->disp
) || (adds (&opP
->disp
) == 0))
3159 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
3160 add_fix ('l', &opP
->disp
, 1, 0);
3165 add_frag (adds (&opP
->disp
),
3166 SEXT (offs (&opP
->disp
)),
3167 TAB (FBRANCH
, SZ_UNDEF
));
3174 case 'C': /* Ignore it. */
3177 case 'd': /* JF this is a kludge. */
3178 install_operand ('s', opP
->reg
- ADDR
);
3179 tmpreg
= get_num (&opP
->disp
, 90);
3180 if (!issword (tmpreg
))
3182 as_warn (_("Expression out of range, using 0"));
3189 install_operand (s
[1], opP
->reg
- DATA
);
3192 case 'e': /* EMAC ACCx, reg/reg. */
3193 install_operand (s
[1], opP
->reg
- ACC
);
3196 case 'E': /* Ignore it. */
3200 install_operand (s
[1], opP
->reg
- FP0
);
3203 case 'g': /* EMAC ACCEXTx. */
3204 install_operand (s
[1], opP
->reg
- ACCEXT01
);
3207 case 'G': /* Ignore it. */
3212 tmpreg
= opP
->reg
- COP0
;
3213 install_operand (s
[1], tmpreg
);
3216 case 'i': /* MAC/EMAC scale factor. */
3217 install_operand (s
[1], opP
->mode
== LSH
? 0x1 : 0x3);
3220 case 'J': /* JF foo. */
3263 tmpreg
= 0x00c + (opP
->reg
- ACR4
);
3370 install_operand (s
[1], tmpreg
);
3374 tmpreg
= get_num (&opP
->disp
, 55);
3375 install_operand (s
[1], tmpreg
& 0x7f);
3382 if (tmpreg
& 0x7FF0000)
3383 as_bad (_("Floating point register in register list"));
3384 insop (reverse_16_bits (tmpreg
), opcode
);
3388 if (tmpreg
& 0x700FFFF)
3389 as_bad (_("Wrong register in floating-point reglist"));
3390 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
3398 if (tmpreg
& 0x7FF0000)
3399 as_bad (_("Floating point register in register list"));
3400 insop (tmpreg
, opcode
);
3402 else if (s
[1] == '8')
3404 if (tmpreg
& 0x0FFFFFF)
3405 as_bad (_("incorrect register in reglist"));
3406 install_operand (s
[1], tmpreg
>> 24);
3410 if (tmpreg
& 0x700FFFF)
3411 as_bad (_("wrong register in floating-point reglist"));
3413 install_operand (s
[1], tmpreg
>> 16);
3418 install_operand (s
[1], get_num (&opP
->disp
, 60));
3422 tmpreg
= ((opP
->mode
== DREG
)
3423 ? 0x20 + (int) (opP
->reg
- DATA
)
3424 : (get_num (&opP
->disp
, 40) & 0x1F));
3425 install_operand (s
[1], tmpreg
);
3429 tmpreg
= get_num (&opP
->disp
, 10);
3432 install_operand (s
[1], tmpreg
);
3436 /* This depends on the fact that ADDR registers are eight
3437 more than their corresponding DATA regs, so the result
3438 will have the ADDR_REG bit set. */
3439 install_operand (s
[1], opP
->reg
- DATA
);
3443 if (opP
->mode
== AINDR
)
3444 install_operand (s
[1], opP
->reg
- DATA
);
3446 install_operand (s
[1], opP
->index
.reg
- DATA
);
3450 if (opP
->reg
== FPI
)
3452 else if (opP
->reg
== FPS
)
3454 else if (opP
->reg
== FPC
)
3458 install_operand (s
[1], tmpreg
);
3461 case 'S': /* Ignore it. */
3465 install_operand (s
[1], get_num (&opP
->disp
, 30));
3468 case 'U': /* Ignore it. */
3487 as_fatal (_("failed sanity check"));
3488 } /* switch on cache token. */
3489 install_operand (s
[1], tmpreg
);
3492 /* JF: These are out of order, I fear. */
3505 install_operand (s
[1], tmpreg
);
3531 install_operand (s
[1], tmpreg
);
3535 if (opP
->reg
== VAL
)
3554 install_operand (s
[1], tmpreg
);
3568 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3579 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3585 install_operand (s
[1], tmpreg
);
3588 know (opP
->reg
== PSR
);
3591 know (opP
->reg
== PCSR
);
3606 install_operand (s
[1], tmpreg
);
3609 tmpreg
= get_num (&opP
->disp
, 20);
3610 install_operand (s
[1], tmpreg
);
3612 case '_': /* used only for move16 absolute 32-bit address. */
3613 if (isvar (&opP
->disp
))
3614 add_fix ('l', &opP
->disp
, 0, 0);
3615 tmpreg
= get_num (&opP
->disp
, 90);
3616 addword (tmpreg
>> 16);
3617 addword (tmpreg
& 0xFFFF);
3620 install_operand (s
[1], opP
->reg
- DATA0L
);
3621 opP
->reg
-= (DATA0L
);
3622 opP
->reg
&= 0x0F; /* remove upper/lower bit. */
3625 tmpreg
= get_num (&opP
->disp
, 80);
3628 install_operand (s
[1], tmpreg
);
3631 tmpreg
= get_num (&opP
->disp
, 10);
3632 install_operand (s
[1], tmpreg
- 1);
3635 tmpreg
= get_num (&opP
->disp
, 65);
3636 install_operand (s
[1], tmpreg
);
3643 /* By the time when get here (FINALLY) the_ins contains the complete
3644 instruction, ready to be emitted. . . */
3648 reverse_16_bits (int in
)
3653 static int mask
[16] =
3655 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3656 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3658 for (n
= 0; n
< 16; n
++)
3661 out
|= mask
[15 - n
];
3664 } /* reverse_16_bits() */
3667 reverse_8_bits (int in
)
3672 static int mask
[8] =
3674 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3677 for (n
= 0; n
< 8; n
++)
3683 } /* reverse_8_bits() */
3685 /* Cause an extra frag to be generated here, inserting up to
3686 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3687 generated; its primary type is rs_machine_dependent.
3689 The TYPE parameter is also used by md_convert_frag_1 and
3690 md_estimate_size_before_relax. The appropriate type of fixup will
3691 be emitted by md_convert_frag_1.
3693 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3695 install_operand (int mode
, int val
)
3700 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge. */
3703 the_ins
.opcode
[0] |= val
<< 9;
3706 the_ins
.opcode
[1] |= val
<< 9;
3709 the_ins
.opcode
[1] |= val
<< 12;
3712 the_ins
.opcode
[1] |= val
<< 6;
3715 the_ins
.opcode
[1] |= val
;
3718 the_ins
.opcode
[2] |= val
<< 12;
3721 the_ins
.opcode
[2] |= val
<< 6;
3724 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3725 three words long! */
3727 the_ins
.opcode
[2] |= val
;
3730 the_ins
.opcode
[1] |= val
<< 7;
3733 the_ins
.opcode
[1] |= val
<< 10;
3737 the_ins
.opcode
[1] |= val
<< 5;
3742 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3745 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3748 the_ins
.opcode
[0] |= val
= 0xff;
3751 the_ins
.opcode
[0] |= val
<< 9;
3754 the_ins
.opcode
[1] |= val
;
3757 the_ins
.opcode
[1] |= val
;
3758 the_ins
.numo
++; /* What a hack. */
3761 the_ins
.opcode
[1] |= val
<< 4;
3769 the_ins
.opcode
[0] |= (val
<< 6);
3772 the_ins
.opcode
[1] = (val
>> 16);
3773 the_ins
.opcode
[2] = val
& 0xffff;
3776 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3777 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3778 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3780 case 'n': /* MAC/EMAC Rx on !load. */
3781 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3782 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3783 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3785 case 'o': /* MAC/EMAC Rx on load. */
3786 the_ins
.opcode
[1] |= val
<< 12;
3787 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3789 case 'M': /* MAC/EMAC Ry on !load. */
3790 the_ins
.opcode
[0] |= (val
& 0xF);
3791 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3793 case 'N': /* MAC/EMAC Ry on load. */
3794 the_ins
.opcode
[1] |= (val
& 0xF);
3795 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3798 the_ins
.opcode
[1] |= ((val
!= 1) << 10);
3801 the_ins
.opcode
[0] |= ((val
& 0x3) << 9);
3804 the_ins
.opcode
[0] |= ((val
& 0x3) << 0);
3806 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3807 the_ins
.opcode
[0] |= ((~val
& 0x1) << 7);
3808 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3810 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3811 the_ins
.opcode
[0] |= ((val
& 0x1) << 7);
3812 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3815 the_ins
.opcode
[1] |= ((val
& 0x3) << 9);
3818 the_ins
.opcode
[0] |= (val
& 0x1) <<10;
3822 as_fatal (_("failed sanity check."));
3827 install_gen_operand (int mode
, int val
)
3831 case '/': /* Special for mask loads for mac/msac insns with
3832 possible mask; trailing_ampersand set in bit 8. */
3833 the_ins
.opcode
[0] |= (val
& 0x3f);
3834 the_ins
.opcode
[1] |= (((val
& 0x100) >> 8) << 5);
3837 the_ins
.opcode
[0] |= val
;
3840 /* This is a kludge!!! */
3841 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3850 the_ins
.opcode
[0] |= val
;
3852 /* more stuff goes here. */
3854 as_fatal (_("failed sanity check."));
3858 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3859 then deal with the bitfield hack. */
3862 crack_operand (char *str
, struct m68k_op
*opP
)
3874 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3880 else if (*str
== ')')
3884 opP
->error
= _("Extra )");
3890 if (flag_mri
&& *str
== '\'')
3891 inquote
= ! inquote
;
3893 if (!*str
&& parens
)
3895 opP
->error
= _("Missing )");
3900 if (m68k_ip_op (beg_str
, opP
) != 0)
3907 c
= *++str
; /* JF bitfield hack. */
3912 as_bad (_("Missing operand"));
3915 /* Detect MRI REG symbols and convert them to REGLSTs. */
3916 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
3919 opP
->mask
= ~(int)opP
->reg
;
3926 /* This is the guts of the machine-dependent assembler. STR points to a
3927 machine dependent instruction. This function is supposed to emit
3928 the frags/bytes it assembles to.
3932 insert_reg (const char *regname
, int regnum
)
3937 #ifdef REGISTER_PREFIX
3938 if (!flag_reg_prefix_optional
)
3940 buf
[0] = REGISTER_PREFIX
;
3941 strcpy (buf
+ 1, regname
);
3946 symbol_table_insert (symbol_new (regname
, reg_section
,
3947 &zero_address_frag
, regnum
));
3949 for (i
= 0; regname
[i
]; i
++)
3950 buf
[i
] = TOUPPER (regname
[i
]);
3953 symbol_table_insert (symbol_new (buf
, reg_section
,
3954 &zero_address_frag
, regnum
));
3963 static const struct init_entry init_table
[] =
4023 { "accext01", ACCEXT01
},
4024 { "accext23", ACCEXT23
},
4028 /* Control registers. */
4029 { "sfc", SFC
}, /* Source Function Code. */
4031 { "dfc", DFC
}, /* Destination Function Code. */
4033 { "cacr", CACR
}, /* Cache Control Register. */
4034 { "caar", CAAR
}, /* Cache Address Register. */
4035 { "cpucr", CPUCR
}, /* CPU Control Register. */
4037 { "usp", USP
}, /* User Stack Pointer. */
4038 { "vbr", VBR
}, /* Vector Base Register. */
4039 { "msp", MSP
}, /* Master Stack Pointer. */
4040 { "isp", ISP
}, /* Interrupt Stack Pointer. */
4042 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0. */
4043 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1. */
4044 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0. */
4045 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1. */
4047 /* 68ec040 versions of same */
4048 { "iacr0", ITT0
}, /* Instruction Access Control Register 0. */
4049 { "iacr1", ITT1
}, /* Instruction Access Control Register 0. */
4050 { "dacr0", DTT0
}, /* Data Access Control Register 0. */
4051 { "dacr1", DTT1
}, /* Data Access Control Register 0. */
4053 /* Coldfire versions of same. The ColdFire programmer's reference
4054 manual indicated that the order is 2,3,0,1, but Ken Rose
4055 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
4056 { "acr0", ACR0
}, /* Access Control Unit 0. */
4057 { "acr1", ACR1
}, /* Access Control Unit 1. */
4058 { "acr2", ACR2
}, /* Access Control Unit 2. */
4059 { "acr3", ACR3
}, /* Access Control Unit 3. */
4060 { "acr4", ACR4
}, /* Access Control Unit 4. */
4061 { "acr5", ACR5
}, /* Access Control Unit 5. */
4062 { "acr6", ACR6
}, /* Access Control Unit 6. */
4063 { "acr7", ACR7
}, /* Access Control Unit 7. */
4065 { "tc", TC
}, /* MMU Translation Control Register. */
4069 { "mmusr", MMUSR
}, /* MMU Status Register. */
4070 { "srp", SRP
}, /* User Root Pointer. */
4071 { "urp", URP
}, /* Supervisor Root Pointer. */
4074 { "mmubar", MMUBAR
},
4077 { "rombar", ROMBAR
}, /* ROM Base Address Register. */
4078 { "rambar0", RAMBAR0
}, /* ROM Base Address Register. */
4079 { "rambar1", RAMBAR1
}, /* ROM Base Address Register. */
4080 { "mbar", MBAR
}, /* Module Base Address Register. */
4082 { "mbar0", MBAR0
}, /* mcfv4e registers. */
4083 { "mbar1", MBAR1
}, /* mcfv4e registers. */
4084 { "rombar0", ROMBAR0
}, /* mcfv4e registers. */
4085 { "rombar1", ROMBAR1
}, /* mcfv4e registers. */
4086 { "mpcr", MPCR
}, /* mcfv4e registers. */
4087 { "edrambar", EDRAMBAR
}, /* mcfv4e registers. */
4088 { "secmbar", SECMBAR
}, /* mcfv4e registers. */
4089 { "asid", TC
}, /* mcfv4e registers. */
4090 { "mmubar", BUSCR
}, /* mcfv4e registers. */
4091 { "pcr1u0", PCR1U0
}, /* mcfv4e registers. */
4092 { "pcr1l0", PCR1L0
}, /* mcfv4e registers. */
4093 { "pcr2u0", PCR2U0
}, /* mcfv4e registers. */
4094 { "pcr2l0", PCR2L0
}, /* mcfv4e registers. */
4095 { "pcr3u0", PCR3U0
}, /* mcfv4e registers. */
4096 { "pcr3l0", PCR3L0
}, /* mcfv4e registers. */
4097 { "pcr1u1", PCR1U1
}, /* mcfv4e registers. */
4098 { "pcr1l1", PCR1L1
}, /* mcfv4e registers. */
4099 { "pcr2u1", PCR2U1
}, /* mcfv4e registers. */
4100 { "pcr2l1", PCR2L1
}, /* mcfv4e registers. */
4101 { "pcr3u1", PCR3U1
}, /* mcfv4e registers. */
4102 { "pcr3l1", PCR3L1
}, /* mcfv4e registers. */
4104 { "flashbar", FLASHBAR
}, /* mcf528x registers. */
4105 { "rambar", RAMBAR
}, /* mcf528x registers. */
4107 { "mbar2", MBAR2
}, /* mcf5249 registers. */
4109 { "rgpiobar", RGPIOBAR
}, /* mcf54418 registers. */
4111 { "cac", CAC
}, /* fido registers. */
4112 { "mbb", MBO
}, /* fido registers (obsolete). */
4113 { "mbo", MBO
}, /* fido registers. */
4114 /* End of control registers. */
4148 /* 68ec030 versions of same. */
4151 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4154 /* Suppressed data and address registers. */
4172 /* Upper and lower data and address registers, used by macw and msacw. */
4213 init_regtable (void)
4216 for (i
= 0; init_table
[i
].name
; i
++)
4217 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
4221 md_assemble (char *str
)
4228 int shorts_this_frag
;
4231 if (!selected_cpu
&& !selected_arch
)
4233 /* We've not selected an architecture yet. Set the default
4234 now. We do this lazily so that an initial .cpu or .arch directive
4236 if (!m68k_set_cpu (TARGET_CPU
, 1, 1))
4237 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU
);
4242 /* In MRI mode, the instruction and operands are separated by a
4243 space. Anything following the operands is a comment. The label
4244 has already been removed. */
4252 for (s
= str
; *s
!= '\0'; s
++)
4254 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
4272 inquote
= ! inquote
;
4277 memset (&the_ins
, '\0', sizeof (the_ins
));
4282 for (n
= 0; n
< the_ins
.numargs
; n
++)
4283 if (the_ins
.operands
[n
].error
)
4285 er
= the_ins
.operands
[n
].error
;
4291 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
4295 /* If there is a current label, record that it marks an instruction. */
4296 if (current_label
!= NULL
)
4298 current_label
->text
= 1;
4299 current_label
= NULL
;
4302 /* Tie dwarf2 debug info to the address at the start of the insn. */
4303 dwarf2_emit_insn (0);
4305 if (the_ins
.nfrag
== 0)
4307 /* No frag hacking involved; just put it out. */
4308 toP
= frag_more (2 * the_ins
.numo
);
4309 fromP
= &the_ins
.opcode
[0];
4310 for (m
= the_ins
.numo
; m
; --m
)
4312 md_number_to_chars (toP
, (long) (*fromP
), 2);
4316 /* Put out symbol-dependent info. */
4317 for (m
= 0; m
< the_ins
.nrel
; m
++)
4319 switch (the_ins
.reloc
[m
].wid
)
4338 as_fatal (_("Don't know how to figure out width of %c in md_assemble()"),
4339 the_ins
.reloc
[m
].wid
);
4342 fixP
= fix_new_exp (frag_now
,
4343 ((toP
- frag_now
->fr_literal
)
4344 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4346 &the_ins
.reloc
[m
].exp
,
4347 the_ins
.reloc
[m
].pcrel
,
4348 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
4349 the_ins
.reloc
[m
].pic_reloc
));
4350 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4351 if (the_ins
.reloc
[m
].wid
== 'B')
4352 fixP
->fx_signed
= 1;
4357 /* There's some frag hacking. */
4359 /* Calculate the max frag size. */
4362 wid
= 2 * the_ins
.fragb
[0].fragoff
;
4363 for (n
= 1; n
< the_ins
.nfrag
; n
++)
4364 wid
+= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4365 /* frag_var part. */
4366 wid
+= FRAG_VAR_SIZE
;
4367 /* Make sure the whole insn fits in one chunk, in particular that
4368 the var part is attached, as we access one byte before the
4369 variable frag for byte branches. */
4373 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
4378 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
4380 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4381 toP
= frag_more (wid
);
4383 shorts_this_frag
= 0;
4384 for (m
= wid
/ 2; m
; --m
)
4386 md_number_to_chars (toP
, (long) (*fromP
), 2);
4391 for (m
= 0; m
< the_ins
.nrel
; m
++)
4393 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
4395 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
4398 wid
= the_ins
.reloc
[m
].wid
;
4401 the_ins
.reloc
[m
].wid
= 0;
4402 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4404 fixP
= fix_new_exp (frag_now
,
4405 ((toP
- frag_now
->fr_literal
)
4406 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4408 &the_ins
.reloc
[m
].exp
,
4409 the_ins
.reloc
[m
].pcrel
,
4410 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4411 the_ins
.reloc
[m
].pic_reloc
));
4412 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4414 (void) frag_var (rs_machine_dependent
, FRAG_VAR_SIZE
, 0,
4415 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
4416 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
4418 gas_assert (the_ins
.nfrag
>= 1);
4419 n
= the_ins
.numo
- the_ins
.fragb
[the_ins
.nfrag
- 1].fragoff
;
4420 shorts_this_frag
= 0;
4423 toP
= frag_more (n
* 2);
4426 md_number_to_chars (toP
, (long) (*fromP
), 2);
4432 for (m
= 0; m
< the_ins
.nrel
; m
++)
4436 wid
= the_ins
.reloc
[m
].wid
;
4439 the_ins
.reloc
[m
].wid
= 0;
4440 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4442 fixP
= fix_new_exp (frag_now
,
4443 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
4444 - shorts_this_frag
* 2),
4446 &the_ins
.reloc
[m
].exp
,
4447 the_ins
.reloc
[m
].pcrel
,
4448 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4449 the_ins
.reloc
[m
].pic_reloc
));
4450 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4454 /* Comparison function used by qsort to rank the opcode entries by name. */
4457 m68k_compare_opcode (const void * v1
, const void * v2
)
4459 struct m68k_opcode
* op1
, * op2
;
4465 op1
= *(struct m68k_opcode
**) v1
;
4466 op2
= *(struct m68k_opcode
**) v2
;
4468 /* Compare the two names. If different, return the comparison.
4469 If the same, return the order they are in the opcode table. */
4470 ret
= strcmp (op1
->name
, op2
->name
);
4481 const struct m68k_opcode
*ins
;
4482 struct m68k_incant
*hack
, *slak
;
4485 /* Set up hash tables with 68000 instructions.
4486 similar to what the vax assembler does. */
4487 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4488 a copy of it at runtime, adding in the information we want but isn't
4489 there. I think it'd be better to have an awk script hack the table
4490 at compile time. Or even just xstr the table and use it as-is. But
4491 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4496 flag_reg_prefix_optional
= 1;
4498 if (! m68k_rel32_from_cmdline
)
4502 /* First sort the opcode table into alphabetical order to separate
4503 the order that the assembler wants to see the opcodes from the
4504 order that the disassembler wants to see them. */
4505 m68k_sorted_opcodes
= XNEWVEC (const struct m68k_opcode
*, m68k_numopcodes
);
4507 for (i
= m68k_numopcodes
; i
--;)
4508 m68k_sorted_opcodes
[i
] = m68k_opcodes
+ i
;
4510 qsort (m68k_sorted_opcodes
, m68k_numopcodes
,
4511 sizeof (m68k_sorted_opcodes
[0]), m68k_compare_opcode
);
4513 op_hash
= str_htab_create ();
4515 obstack_begin (&robyn
, 4000);
4516 for (i
= 0; i
< m68k_numopcodes
; i
++)
4518 hack
= slak
= XOBNEW (&robyn
, struct m68k_incant
);
4521 ins
= m68k_sorted_opcodes
[i
];
4523 /* We must enter all insns into the table, because .arch and
4524 .cpu directives can change things. */
4525 slak
->m_operands
= ins
->args
;
4526 slak
->m_arch
= ins
->arch
;
4527 slak
->m_opcode
= ins
->opcode
;
4529 /* In most cases we can determine the number of opcode words
4530 by checking the second word of the mask. Unfortunately
4531 some instructions have 2 opcode words, but no fixed bits
4532 in the second word. A leading dot in the operands
4533 string also indicates 2 opcodes. */
4534 if (*slak
->m_operands
== '.')
4537 slak
->m_codenum
= 2;
4539 else if (ins
->match
& 0xffffL
)
4540 slak
->m_codenum
= 2;
4542 slak
->m_codenum
= 1;
4543 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
4545 if (i
+ 1 != m68k_numopcodes
4546 && !strcmp (ins
->name
, m68k_sorted_opcodes
[i
+ 1]->name
))
4548 slak
->m_next
= XOBNEW (&robyn
, struct m68k_incant
);
4553 slak
= slak
->m_next
;
4557 if (str_hash_insert (op_hash
, ins
->name
, hack
, 0) != NULL
)
4558 as_fatal (_("duplicate %s"), ins
->name
);
4561 for (i
= 0; i
< m68k_numaliases
; i
++)
4563 const char *name
= m68k_opcode_aliases
[i
].primary
;
4564 const char *alias
= m68k_opcode_aliases
[i
].alias
;
4565 void *val
= (void *) str_hash_find (op_hash
, name
);
4568 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4569 if (str_hash_insert (op_hash
, alias
, val
, 0) != NULL
)
4570 as_fatal (_("duplicate %s"), alias
);
4573 /* In MRI mode, all unsized branches are variable sized. Normally,
4574 they are word sized. */
4577 static struct m68k_opcode_alias mri_aliases
[] =
4598 i
< (int) (sizeof mri_aliases
/ sizeof mri_aliases
[0]);
4601 const char *name
= mri_aliases
[i
].primary
;
4602 const char *alias
= mri_aliases
[i
].alias
;
4603 void *val
= (void *) str_hash_find (op_hash
, name
);
4606 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4607 str_hash_insert (op_hash
, alias
, val
, 1);
4611 for (i
= 0; i
< (int) sizeof (notend_table
); i
++)
4613 notend_table
[i
] = 0;
4614 alt_notend_table
[i
] = 0;
4617 notend_table
[','] = 1;
4618 notend_table
['{'] = 1;
4619 notend_table
['}'] = 1;
4620 alt_notend_table
['a'] = 1;
4621 alt_notend_table
['A'] = 1;
4622 alt_notend_table
['d'] = 1;
4623 alt_notend_table
['D'] = 1;
4624 alt_notend_table
['#'] = 1;
4625 alt_notend_table
['&'] = 1;
4626 alt_notend_table
['f'] = 1;
4627 alt_notend_table
['F'] = 1;
4628 #ifdef REGISTER_PREFIX
4629 alt_notend_table
[REGISTER_PREFIX
] = 1;
4632 /* We need to put '(' in alt_notend_table to handle
4633 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4634 alt_notend_table
['('] = 1;
4636 /* We need to put '@' in alt_notend_table to handle
4637 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4638 alt_notend_table
['@'] = 1;
4640 /* We need to put digits in alt_notend_table to handle
4641 bfextu %d0{24:1},%d0 */
4642 alt_notend_table
['0'] = 1;
4643 alt_notend_table
['1'] = 1;
4644 alt_notend_table
['2'] = 1;
4645 alt_notend_table
['3'] = 1;
4646 alt_notend_table
['4'] = 1;
4647 alt_notend_table
['5'] = 1;
4648 alt_notend_table
['6'] = 1;
4649 alt_notend_table
['7'] = 1;
4650 alt_notend_table
['8'] = 1;
4651 alt_notend_table
['9'] = 1;
4653 #ifndef MIT_SYNTAX_ONLY
4654 /* Insert pseudo ops, these have to go into the opcode table since
4655 gas expects pseudo ops to start with a dot. */
4659 while (mote_pseudo_table
[n
].poc_name
)
4661 hack
= XOBNEW (&robyn
, struct m68k_incant
);
4662 str_hash_insert (op_hash
,
4663 mote_pseudo_table
[n
].poc_name
, hack
, 0);
4664 hack
->m_operands
= 0;
4673 record_alignment (text_section
, 2);
4674 record_alignment (data_section
, 2);
4675 record_alignment (bss_section
, 2);
4679 /* This is called when a label is defined. */
4682 m68k_frob_label (symbolS
*sym
)
4684 struct m68k_tc_sy
*n
;
4686 n
= symbol_get_tc (sym
);
4687 n
->file
= as_where (&n
->line
);
4691 dwarf2_emit_label (sym
);
4694 /* This is called when a value that is not an instruction is emitted. */
4697 m68k_flush_pending_output (void)
4699 current_label
= NULL
;
4702 /* This is called at the end of the assembly, when the final value of
4703 the label is known. We warn if this is a text symbol aligned at an
4707 m68k_frob_symbol (symbolS
*sym
)
4709 if (S_GET_SEGMENT (sym
) == reg_section
4710 && (int) S_GET_VALUE (sym
) < 0)
4712 S_SET_SEGMENT (sym
, absolute_section
);
4713 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
4715 else if ((S_GET_VALUE (sym
) & 1) != 0)
4717 struct m68k_tc_sy
*l
;
4718 l
= symbol_get_tc (sym
);
4721 as_warn_where (l
->file
, l
->line
,
4722 _("text label `%s' aligned to odd boundary"),
4727 /* This is called if we go in or out of MRI mode because of the .mri
4731 m68k_mri_mode_change (int on
)
4735 if (! flag_reg_prefix_optional
)
4737 flag_reg_prefix_optional
= 1;
4738 #ifdef REGISTER_PREFIX
4743 if (! m68k_rel32_from_cmdline
)
4748 if (! reg_prefix_optional_seen
)
4750 #ifdef REGISTER_PREFIX_OPTIONAL
4751 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
4753 flag_reg_prefix_optional
= 0;
4755 #ifdef REGISTER_PREFIX
4760 if (! m68k_rel32_from_cmdline
)
4766 md_atof (int type
, char *litP
, int *sizeP
)
4768 return ieee_md_atof (type
, litP
, sizeP
, true);
4772 md_number_to_chars (char *buf
, valueT val
, int n
)
4774 number_to_chars_bigendian (buf
, val
, n
);
4778 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4780 offsetT val
= *valP
;
4781 addressT upper_limit
;
4782 offsetT lower_limit
;
4784 /* This is unnecessary but it convinces the native rs6000 compiler
4785 to generate the code we want. */
4786 char *buf
= fixP
->fx_frag
->fr_literal
;
4787 buf
+= fixP
->fx_where
;
4788 /* End ibm compiler workaround. */
4792 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4797 memset (buf
, 0, fixP
->fx_size
);
4798 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4800 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4801 && !S_IS_DEFINED (fixP
->fx_addsy
)
4802 && !S_IS_WEAK (fixP
->fx_addsy
))
4803 S_SET_WEAK (fixP
->fx_addsy
);
4805 switch (fixP
->fx_r_type
)
4807 case BFD_RELOC_68K_TLS_GD32
:
4808 case BFD_RELOC_68K_TLS_GD16
:
4809 case BFD_RELOC_68K_TLS_GD8
:
4810 case BFD_RELOC_68K_TLS_LDM32
:
4811 case BFD_RELOC_68K_TLS_LDM16
:
4812 case BFD_RELOC_68K_TLS_LDM8
:
4813 case BFD_RELOC_68K_TLS_LDO32
:
4814 case BFD_RELOC_68K_TLS_LDO16
:
4815 case BFD_RELOC_68K_TLS_LDO8
:
4816 case BFD_RELOC_68K_TLS_IE32
:
4817 case BFD_RELOC_68K_TLS_IE16
:
4818 case BFD_RELOC_68K_TLS_IE8
:
4819 case BFD_RELOC_68K_TLS_LE32
:
4820 case BFD_RELOC_68K_TLS_LE16
:
4821 case BFD_RELOC_68K_TLS_LE8
:
4822 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4832 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4833 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4836 switch (fixP
->fx_size
)
4838 /* The cast to offsetT below are necessary to make code
4839 correct for machines where ints are smaller than offsetT. */
4843 lower_limit
= - (offsetT
) 0x80;
4846 *buf
++ = (val
>> 8);
4848 upper_limit
= 0x7fff;
4849 lower_limit
= - (offsetT
) 0x8000;
4852 *buf
++ = (val
>> 24);
4853 *buf
++ = (val
>> 16);
4854 *buf
++ = (val
>> 8);
4856 upper_limit
= 0x7fffffff;
4857 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* Avoid constant overflow. */
4860 BAD_CASE (fixP
->fx_size
);
4863 /* Fix up a negative reloc. */
4864 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4866 fixP
->fx_addsy
= fixP
->fx_subsy
;
4867 fixP
->fx_subsy
= NULL
;
4871 /* For non-pc-relative values, it's conceivable we might get something
4872 like "0xff" for a byte field. So extend the upper part of the range
4873 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4874 so that we can do any range checking at all. */
4875 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
4876 upper_limit
= upper_limit
* 2 + 1;
4878 if ((addressT
) val
> upper_limit
4879 && (val
> 0 || val
< lower_limit
))
4880 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4881 _("value %ld out of range"), (long)val
);
4883 /* A one byte PC-relative reloc means a short branch. We can't use
4884 a short branch with a value of 0 or -1, because those indicate
4885 different opcodes (branches with longer offsets). fixup_segment
4886 in write.c may have clobbered fx_pcrel, so we need to examine the
4889 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4890 && fixP
->fx_size
== 1
4891 && (fixP
->fx_addsy
== NULL
4892 || S_IS_DEFINED (fixP
->fx_addsy
))
4893 && (val
== 0 || val
== -1))
4894 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4895 _("invalid byte branch offset"));
4898 /* *fragP has been relaxed to its final size, and now needs to have
4899 the bytes inside it modified to conform to the new size There is UGLY
4903 md_convert_frag_1 (fragS
*fragP
)
4908 /* Address in object code of the displacement. */
4909 int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4911 /* Address in gas core of the place to store the displacement. */
4912 /* This convinces the native rs6000 compiler to generate the code we
4914 char *buffer_address
= fragP
->fr_literal
;
4915 buffer_address
+= fragP
->fr_fix
;
4916 /* End ibm compiler workaround. */
4918 /* The displacement of the address, from current location. */
4919 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4920 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4922 switch (fragP
->fr_subtype
)
4924 case TAB (BRANCHBWL
, BYTE
):
4925 case TAB (BRABSJUNC
, BYTE
):
4926 case TAB (BRABSJCOND
, BYTE
):
4927 case TAB (BRANCHBW
, BYTE
):
4928 case TAB (BRANCHBWPL
, BYTE
):
4929 know (issbyte (disp
));
4931 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4932 _("short branch with zero offset: use :w"));
4933 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4934 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4935 fixP
->fx_pcrel_adjust
= -1;
4937 case TAB (BRANCHBWL
, SHORT
):
4938 case TAB (BRABSJUNC
, SHORT
):
4939 case TAB (BRABSJCOND
, SHORT
):
4940 case TAB (BRANCHBW
, SHORT
):
4941 case TAB (BRANCHBWPL
, SHORT
):
4942 fragP
->fr_opcode
[1] = 0x00;
4943 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4944 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4947 case TAB (BRANCHBWL
, LONG
):
4948 fragP
->fr_opcode
[1] = (char) 0xFF;
4949 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4950 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4953 case TAB (BRANCHBWPL
, LONG
):
4954 /* Here we are converting an unconditional branch into a pair of
4955 conditional branches, in order to get the range. */
4956 fragP
->fr_opcode
[0] = 0x66; /* bne */
4957 fragP
->fr_opcode
[1] = 0xFF;
4958 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4959 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4960 fixP
->fx_file
= fragP
->fr_file
;
4961 fixP
->fx_line
= fragP
->fr_line
;
4962 fragP
->fr_fix
+= 4; /* Skip first offset */
4963 buffer_address
+= 4;
4964 *buffer_address
++ = 0x67; /* beq */
4965 *buffer_address
++ = 0xff;
4966 fragP
->fr_fix
+= 2; /* Skip second branch opcode */
4967 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4968 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4971 case TAB (BRABSJUNC
, LONG
):
4972 if (fragP
->fr_opcode
[0] == 0x61) /* jbsr */
4974 if (flag_keep_pcrel
)
4975 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4976 _("Conversion of PC relative BSR to absolute JSR"));
4977 fragP
->fr_opcode
[0] = 0x4E;
4978 fragP
->fr_opcode
[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4979 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4980 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
4983 else if (fragP
->fr_opcode
[0] == 0x60) /* jbra */
4985 if (flag_keep_pcrel
)
4986 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4987 _("Conversion of PC relative branch to absolute jump"));
4988 fragP
->fr_opcode
[0] = 0x4E;
4989 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4990 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4991 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
4996 /* This cannot happen, because jbsr and jbra are the only two
4997 unconditional branches. */
5001 case TAB (BRABSJCOND
, LONG
):
5002 if (flag_keep_pcrel
)
5003 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5004 _("Conversion of PC relative conditional branch to absolute jump"));
5006 /* Only Bcc 68000 instructions can come here
5007 Change bcc into b!cc/jmp absl long. */
5008 fragP
->fr_opcode
[0] ^= 0x01; /* Invert bcc. */
5009 fragP
->fr_opcode
[1] = 0x06; /* Branch offset = 6. */
5011 /* JF: these used to be fr_opcode[2,3], but they may be in a
5012 different frag, in which case referring to them is a no-no.
5013 Only fr_opcode[0,1] are guaranteed to work. */
5014 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
5015 *buffer_address
++ = (char) 0xf9;
5016 fragP
->fr_fix
+= 2; /* Account for jmp instruction. */
5017 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5018 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5021 case TAB (FBRANCH
, SHORT
):
5022 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
5023 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5024 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5027 case TAB (FBRANCH
, LONG
):
5028 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit. */
5029 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5030 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5033 case TAB (DBCCLBR
, SHORT
):
5034 case TAB (DBCCABSJ
, SHORT
):
5035 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5036 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5039 case TAB (DBCCLBR
, LONG
):
5040 /* Only DBcc instructions can come here.
5041 Change dbcc into dbcc/bral.
5042 JF: these used to be fr_opcode[2-7], but that's wrong. */
5043 *buffer_address
++ = 0x00; /* Branch offset = 4. */
5044 *buffer_address
++ = 0x04;
5045 *buffer_address
++ = 0x60; /* Put in bra pc+6. */
5046 *buffer_address
++ = 0x06;
5047 *buffer_address
++ = 0x60; /* Put in bral (0x60ff). */
5048 *buffer_address
++ = (char) 0xff;
5050 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
5051 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5052 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5055 case TAB (DBCCABSJ
, LONG
):
5056 /* Only DBcc instructions can come here.
5057 Change dbcc into dbcc/jmp.
5058 JF: these used to be fr_opcode[2-7], but that's wrong. */
5059 if (flag_keep_pcrel
)
5060 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5061 _("Conversion of PC relative conditional branch to absolute jump"));
5063 *buffer_address
++ = 0x00; /* Branch offset = 4. */
5064 *buffer_address
++ = 0x04;
5065 *buffer_address
++ = 0x60; /* Put in bra pc + 6. */
5066 *buffer_address
++ = 0x06;
5067 *buffer_address
++ = 0x4e; /* Put in jmp long (0x4ef9). */
5068 *buffer_address
++ = (char) 0xf9;
5070 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
5071 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5072 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5075 case TAB (PCREL1632
, SHORT
):
5076 fragP
->fr_opcode
[1] &= ~0x3F;
5077 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
5078 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
5079 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5082 case TAB (PCREL1632
, LONG
):
5083 /* Already set to mode 7.3; this indicates: PC indirect with
5084 suppressed index, 32-bit displacement. */
5085 *buffer_address
++ = 0x01;
5086 *buffer_address
++ = 0x70;
5088 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
5089 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5090 fixP
->fx_pcrel_adjust
= 2;
5093 case TAB (PCINDEX
, BYTE
):
5094 gas_assert (fragP
->fr_fix
>= 2);
5095 buffer_address
[-2] &= ~1;
5096 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
5097 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
5098 fixP
->fx_pcrel_adjust
= 1;
5100 case TAB (PCINDEX
, SHORT
):
5101 gas_assert (fragP
->fr_fix
>= 2);
5102 buffer_address
[-2] |= 0x1;
5103 buffer_address
[-1] = 0x20;
5104 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
5105 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5106 fixP
->fx_pcrel_adjust
= 2;
5109 case TAB (PCINDEX
, LONG
):
5110 gas_assert (fragP
->fr_fix
>= 2);
5111 buffer_address
[-2] |= 0x1;
5112 buffer_address
[-1] = 0x30;
5113 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
5114 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5115 fixP
->fx_pcrel_adjust
= 2;
5118 case TAB (ABSTOPCREL
, SHORT
):
5119 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5120 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5123 case TAB (ABSTOPCREL
, LONG
):
5124 if (flag_keep_pcrel
)
5125 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5126 _("Conversion of PC relative displacement to absolute"));
5127 /* The thing to do here is force it to ABSOLUTE LONG, since
5128 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5129 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
5131 fragP
->fr_opcode
[1] &= ~0x3F;
5132 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
5133 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5134 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5140 fixP
->fx_file
= fragP
->fr_file
;
5141 fixP
->fx_line
= fragP
->fr_line
;
5146 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
5147 segT sec ATTRIBUTE_UNUSED
,
5150 md_convert_frag_1 (fragP
);
5153 /* Force truly undefined symbols to their maximum size, and generally set up
5154 the frag list to be relaxed
5157 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
5159 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5160 switch (fragP
->fr_subtype
)
5162 case TAB (BRANCHBWL
, SZ_UNDEF
):
5163 case TAB (BRANCHBWPL
, SZ_UNDEF
):
5164 case TAB (BRABSJUNC
, SZ_UNDEF
):
5165 case TAB (BRABSJCOND
, SZ_UNDEF
):
5167 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5168 && relaxable_symbol (fragP
->fr_symbol
))
5170 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
5172 else if (flag_short_refs
)
5174 /* Symbol is undefined and we want short ref. */
5175 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5179 /* Symbol is still undefined. Make it LONG. */
5180 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
5185 case TAB (BRANCHBW
, SZ_UNDEF
):
5187 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5188 && relaxable_symbol (fragP
->fr_symbol
))
5190 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
5194 /* Symbol is undefined and we don't have long branches. */
5195 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5200 case TAB (FBRANCH
, SZ_UNDEF
):
5201 case TAB (DBCCLBR
, SZ_UNDEF
):
5202 case TAB (DBCCABSJ
, SZ_UNDEF
):
5203 case TAB (PCREL1632
, SZ_UNDEF
):
5205 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5206 && relaxable_symbol (fragP
->fr_symbol
))
5209 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5213 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
5218 case TAB (PCINDEX
, SZ_UNDEF
):
5219 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5220 && relaxable_symbol (fragP
->fr_symbol
)))
5222 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
5226 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
5230 case TAB (ABSTOPCREL
, SZ_UNDEF
):
5232 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5233 && relaxable_symbol (fragP
->fr_symbol
)))
5235 fragP
->fr_subtype
= TAB (ABSTOPCREL
, SHORT
);
5239 fragP
->fr_subtype
= TAB (ABSTOPCREL
, LONG
);
5248 /* Now that SZ_UNDEF are taken care of, check others. */
5249 switch (fragP
->fr_subtype
)
5251 case TAB (BRANCHBWL
, BYTE
):
5252 case TAB (BRABSJUNC
, BYTE
):
5253 case TAB (BRABSJCOND
, BYTE
):
5254 case TAB (BRANCHBW
, BYTE
):
5255 /* We can't do a short jump to the next instruction, so in that
5256 case we force word mode. If the symbol is at the start of a
5257 frag, and it is the next frag with any data in it (usually
5258 this is just the next frag, but assembler listings may
5259 introduce empty frags), we must use word mode. */
5260 if (fragP
->fr_symbol
)
5264 sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
5265 if (S_GET_VALUE (fragP
->fr_symbol
) == sym_frag
->fr_address
)
5269 for (l
= fragP
->fr_next
; l
&& l
!= sym_frag
; l
= l
->fr_next
)
5273 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5280 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5283 #ifndef WORKING_DOT_WORD
5284 int md_short_jump_size
= 4;
5285 int md_long_jump_size
= 6;
5288 md_create_short_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5289 fragS
*frag ATTRIBUTE_UNUSED
,
5290 symbolS
*to_symbol ATTRIBUTE_UNUSED
)
5294 offset
= to_addr
- (from_addr
+ 2);
5296 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
5297 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
5301 md_create_long_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5302 fragS
*frag
, symbolS
*to_symbol
)
5306 if (!HAVE_LONG_BRANCH (current_architecture
))
5308 if (flag_keep_pcrel
)
5309 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5310 offset
= to_addr
- S_GET_VALUE (to_symbol
);
5311 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
5312 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5313 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
5318 offset
= to_addr
- (from_addr
+ 2);
5319 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
5320 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5326 /* Different values of OK tell what it's OK to return. Things that
5327 aren't OK are an error (what a shock, no?)
5330 10: Absolute 1:8 only
5331 20: Absolute 0:7 only
5332 30: absolute 0:15 only
5333 40: Absolute 0:31 only
5334 50: absolute 0:127 only
5335 55: absolute -64:63 only
5336 60: absolute -128:127 only
5337 65: absolute 0:511 only
5338 70: absolute 0:4095 only
5339 80: absolute -1, 1:7 only
5343 get_num (struct m68k_exp
*exp
, int ok
)
5345 if (exp
->exp
.X_op
== O_absent
)
5347 /* Do the same thing the VAX asm does. */
5348 op (exp
) = O_constant
;
5354 as_warn (_("expression out of range: defaulting to 1"));
5358 else if (exp
->exp
.X_op
== O_constant
)
5363 if ((valueT
) TRUNC (offs (exp
)) - 1 > 7)
5365 as_warn (_("expression out of range: defaulting to 1"));
5370 if ((valueT
) TRUNC (offs (exp
)) > 7)
5374 if ((valueT
) TRUNC (offs (exp
)) > 15)
5378 if ((valueT
) TRUNC (offs (exp
)) > 32)
5382 if ((valueT
) TRUNC (offs (exp
)) > 127)
5386 if ((valueT
) SEXT (offs (exp
)) + 64 > 127)
5390 if ((valueT
) SEXT (offs (exp
)) + 128 > 255)
5394 if ((valueT
) TRUNC (offs (exp
)) > 511)
5398 if ((valueT
) TRUNC (offs (exp
)) > 4095)
5401 as_warn (_("expression out of range: defaulting to 0"));
5406 if ((valueT
) TRUNC (offs (exp
)) != 0xffffffff
5407 && (valueT
) TRUNC (offs (exp
)) - 1 > 6)
5409 as_warn (_("expression out of range: defaulting to 1"));
5417 else if (exp
->exp
.X_op
== O_big
)
5419 if (offs (exp
) <= 0 /* flonum. */
5420 && (ok
== 90 /* no bignums */
5421 || (ok
> 10 /* Small-int ranges including 0 ok. */
5422 /* If we have a flonum zero, a zero integer should
5423 do as well (e.g., in moveq). */
5424 && generic_floating_point_number
.exponent
== 0
5425 && generic_floating_point_number
.low
[0] == 0)))
5427 /* HACK! Turn it into a long. */
5428 LITTLENUM_TYPE words
[6];
5430 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
5431 op (exp
) = O_constant
;
5434 offs (exp
) = words
[1] | (words
[0] << 16);
5438 op (exp
) = O_constant
;
5441 offs (exp
) = (ok
== 10) ? 1 : 0;
5442 as_warn (_("Can't deal with expression; defaulting to %ld"),
5448 if (ok
>= 10 && ok
<= 80)
5450 op (exp
) = O_constant
;
5453 offs (exp
) = (ok
== 10) ? 1 : 0;
5454 as_warn (_("Can't deal with expression; defaulting to %ld"),
5459 if (exp
->size
!= SIZE_UNSPEC
)
5467 if (!isbyte (offs (exp
)))
5468 as_warn (_("expression doesn't fit in BYTE"));
5471 if (!isword (offs (exp
)))
5472 as_warn (_("expression doesn't fit in WORD"));
5480 /* These are the back-ends for the various machine dependent pseudo-ops. */
5483 s_data1 (int ignore ATTRIBUTE_UNUSED
)
5485 subseg_set (data_section
, 1);
5486 demand_empty_rest_of_line ();
5490 s_data2 (int ignore ATTRIBUTE_UNUSED
)
5492 subseg_set (data_section
, 2);
5493 demand_empty_rest_of_line ();
5497 s_bss (int ignore ATTRIBUTE_UNUSED
)
5499 /* We don't support putting frags in the BSS segment, we fake it
5500 by marking in_bss, then looking at s_skip for clues. */
5502 subseg_set (bss_section
, 0);
5503 demand_empty_rest_of_line ();
5507 s_even (int ignore ATTRIBUTE_UNUSED
)
5512 temp
= 1; /* JF should be 2? */
5513 temp_fill
= get_absolute_expression ();
5514 if (!need_pass_2
) /* Never make frag if expect extra pass. */
5515 frag_align (temp
, (int) temp_fill
, 0);
5516 demand_empty_rest_of_line ();
5517 record_alignment (now_seg
, temp
);
5521 s_proc (int ignore ATTRIBUTE_UNUSED
)
5523 demand_empty_rest_of_line ();
5526 /* Pseudo-ops handled for MRI compatibility. */
5528 /* This function returns non-zero if the argument is a conditional
5529 pseudo-op. This is called when checking whether a pending
5530 alignment is needed. */
5533 m68k_conditional_pseudoop (const pseudo_typeS
*pop
)
5535 return (pop
->poc_handler
== s_mri_if
5536 || pop
->poc_handler
== s_mri_else
);
5539 /* Handle an MRI style chip specification. */
5548 s
= input_line_pointer
;
5549 /* We can't use get_symbol_name since the processor names are not proper
5551 while (is_part_of_name (c
= *input_line_pointer
++))
5553 *--input_line_pointer
= 0;
5554 for (i
= 0; m68k_cpus
[i
].name
; i
++)
5555 if (strcasecmp (s
, m68k_cpus
[i
].name
) == 0)
5557 if (!m68k_cpus
[i
].name
)
5559 as_bad (_("%s: unrecognized processor name"), s
);
5560 *input_line_pointer
= c
;
5561 ignore_rest_of_line ();
5564 *input_line_pointer
= c
;
5566 if (*input_line_pointer
== '/')
5567 current_architecture
= 0;
5569 current_architecture
&= m68881
| m68851
;
5570 current_architecture
|= m68k_cpus
[i
].arch
& ~(m68881
| m68851
);
5571 control_regs
= m68k_cpus
[i
].control_regs
;
5573 while (*input_line_pointer
== '/')
5575 ++input_line_pointer
;
5576 s
= input_line_pointer
;
5577 /* We can't use get_symbol_name since the processor names are not
5579 while (is_part_of_name (c
= *input_line_pointer
++))
5581 *--input_line_pointer
= 0;
5582 if (strcmp (s
, "68881") == 0)
5583 current_architecture
|= m68881
;
5584 else if (strcmp (s
, "68851") == 0)
5585 current_architecture
|= m68851
;
5586 *input_line_pointer
= c
;
5590 /* The MRI CHIP pseudo-op. */
5593 s_chip (int ignore ATTRIBUTE_UNUSED
)
5599 stop
= mri_comment_field (&stopc
);
5602 mri_comment_end (stop
, stopc
);
5603 demand_empty_rest_of_line ();
5606 /* The MRI FOPT pseudo-op. */
5609 s_fopt (int ignore ATTRIBUTE_UNUSED
)
5613 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
5617 input_line_pointer
+= 3;
5618 temp
= get_absolute_expression ();
5619 if (temp
< 0 || temp
> 7)
5620 as_bad (_("bad coprocessor id"));
5622 m68k_float_copnum
= COP0
+ temp
;
5626 as_bad (_("unrecognized fopt option"));
5627 ignore_rest_of_line ();
5631 demand_empty_rest_of_line ();
5634 /* The structure used to handle the MRI OPT pseudo-op. */
5638 /* The name of the option. */
5641 /* If this is not NULL, just call this function. The first argument
5642 is the ARG field of this structure, the second argument is
5643 whether the option was negated. */
5644 void (*pfn
) (int arg
, int on
);
5646 /* If this is not NULL, and the PFN field is NULL, set the variable
5647 this points to. Set it to the ARG field if the option was not
5648 negated, and the NOTARG field otherwise. */
5651 /* The value to pass to PFN or to assign to *PVAR. */
5654 /* The value to assign to *PVAR if the option is negated. If PFN is
5655 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5656 the option may not be negated. */
5660 /* The table used to handle the MRI OPT pseudo-op. */
5662 static void skip_to_comma (int, int);
5663 static void opt_nest (int, int);
5664 static void opt_chip (int, int);
5665 static void opt_list (int, int);
5666 static void opt_list_symbols (int, int);
5668 static const struct opt_action opt_table
[] =
5670 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5672 /* We do relaxing, so there is little use for these options. */
5673 { "b", 0, 0, 0, 0 },
5674 { "brs", 0, 0, 0, 0 },
5675 { "brb", 0, 0, 0, 0 },
5676 { "brl", 0, 0, 0, 0 },
5677 { "brw", 0, 0, 0, 0 },
5679 { "c", 0, 0, 0, 0 },
5680 { "cex", 0, 0, 0, 0 },
5681 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5682 { "cl", 0, 0, 0, 0 },
5683 { "cre", 0, 0, 0, 0 },
5684 { "d", 0, &flag_keep_locals
, 1, 0 },
5685 { "e", 0, 0, 0, 0 },
5686 { "f", 0, &flag_short_refs
, 1, 0 },
5687 { "frs", 0, &flag_short_refs
, 1, 0 },
5688 { "frl", 0, &flag_short_refs
, 0, 1 },
5689 { "g", 0, 0, 0, 0 },
5690 { "i", 0, 0, 0, 0 },
5691 { "m", 0, 0, 0, 0 },
5692 { "mex", 0, 0, 0, 0 },
5693 { "mc", 0, 0, 0, 0 },
5694 { "md", 0, 0, 0, 0 },
5695 { "nest", opt_nest
, 0, 0, 0 },
5696 { "next", skip_to_comma
, 0, 0, 0 },
5697 { "o", 0, 0, 0, 0 },
5698 { "old", 0, 0, 0, 0 },
5699 { "op", skip_to_comma
, 0, 0, 0 },
5700 { "pco", 0, 0, 0, 0 },
5701 { "p", opt_chip
, 0, 0, 0 },
5702 { "pcr", 0, 0, 0, 0 },
5703 { "pcs", 0, 0, 0, 0 },
5704 { "r", 0, 0, 0, 0 },
5705 { "quick", 0, &m68k_quick
, 1, 0 },
5706 { "rel32", 0, &m68k_rel32
, 1, 0 },
5707 { "s", opt_list
, 0, 0, 0 },
5708 { "t", opt_list_symbols
, 0, 0, 0 },
5709 { "w", 0, &flag_no_warnings
, 0, 1 },
5713 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5715 /* The MRI OPT pseudo-op. */
5718 s_opt (int ignore ATTRIBUTE_UNUSED
)
5726 const struct opt_action
*o
;
5731 if (*input_line_pointer
== '-')
5733 ++input_line_pointer
;
5736 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5738 input_line_pointer
+= 2;
5742 c
= get_symbol_name (&s
);
5744 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5746 if (strcasecmp (s
, o
->name
) == 0)
5750 /* Restore input_line_pointer now in case the option
5752 (void) restore_line_pointer (c
);
5753 (*o
->pfn
) (o
->arg
, t
);
5755 else if (o
->pvar
!= NULL
)
5757 if (! t
&& o
->arg
== o
->notarg
)
5758 as_bad (_("option `%s' may not be negated"), s
);
5759 restore_line_pointer (c
);
5760 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5763 *input_line_pointer
= c
;
5769 as_bad (_("option `%s' not recognized"), s
);
5770 restore_line_pointer (c
);
5773 while (*input_line_pointer
++ == ',');
5775 /* Move back to terminating character. */
5776 --input_line_pointer
;
5777 demand_empty_rest_of_line ();
5780 /* Skip ahead to a comma. This is used for OPT options which we do
5781 not support and which take arguments. */
5784 skip_to_comma (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5786 while (*input_line_pointer
!= ','
5787 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5788 ++input_line_pointer
;
5791 /* Handle the OPT NEST=depth option. */
5794 opt_nest (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5796 if (*input_line_pointer
!= '=')
5798 as_bad (_("bad format of OPT NEST=depth"));
5802 ++input_line_pointer
;
5803 max_macro_nest
= get_absolute_expression ();
5806 /* Handle the OPT P=chip option. */
5809 opt_chip (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5811 if (*input_line_pointer
!= '=')
5813 /* This is just OPT P, which we do not support. */
5817 ++input_line_pointer
;
5821 /* Handle the OPT S option. */
5824 opt_list (int arg ATTRIBUTE_UNUSED
, int on
)
5829 /* Handle the OPT T option. */
5832 opt_list_symbols (int arg ATTRIBUTE_UNUSED
, int on
)
5835 listing
|= LISTING_SYMBOLS
;
5837 listing
&= ~LISTING_SYMBOLS
;
5840 /* Handle the MRI REG pseudo-op. */
5843 s_reg (int ignore ATTRIBUTE_UNUSED
)
5852 if (line_label
== NULL
)
5854 as_bad (_("missing label"));
5855 ignore_rest_of_line ();
5860 stop
= mri_comment_field (&stopc
);
5864 s
= input_line_pointer
;
5865 while (ISALNUM (*input_line_pointer
)
5866 #ifdef REGISTER_PREFIX
5867 || *input_line_pointer
== REGISTER_PREFIX
5869 || *input_line_pointer
== '/'
5870 || *input_line_pointer
== '-')
5871 ++input_line_pointer
;
5872 c
= *input_line_pointer
;
5873 *input_line_pointer
= '\0';
5875 if (m68k_ip_op (s
, &rop
) != 0)
5877 if (rop
.error
== NULL
)
5878 as_bad (_("bad register list"));
5880 as_bad (_("bad register list: %s"), rop
.error
);
5881 *input_line_pointer
= c
;
5882 ignore_rest_of_line ();
5886 *input_line_pointer
= c
;
5888 if (rop
.mode
== REGLST
)
5890 else if (rop
.mode
== DREG
)
5891 mask
= 1 << (rop
.reg
- DATA0
);
5892 else if (rop
.mode
== AREG
)
5893 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
5894 else if (rop
.mode
== FPREG
)
5895 mask
= 1 << (rop
.reg
- FP0
+ 16);
5896 else if (rop
.mode
== CONTROL
5899 else if (rop
.mode
== CONTROL
5902 else if (rop
.mode
== CONTROL
5907 as_bad (_("bad register list"));
5908 ignore_rest_of_line ();
5912 S_SET_SEGMENT (line_label
, reg_section
);
5913 S_SET_VALUE (line_label
, ~mask
);
5914 symbol_set_frag (line_label
, &zero_address_frag
);
5917 mri_comment_end (stop
, stopc
);
5919 demand_empty_rest_of_line ();
5922 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5926 struct save_opts
*next
;
5928 int symbols_case_sensitive
;
5932 const enum m68k_register
*control_regs
;
5937 /* FIXME: We don't save OPT S. */
5940 /* This variable holds the stack of saved options. */
5942 static struct save_opts
*save_stack
;
5944 /* The MRI SAVE pseudo-op. */
5947 s_save (int ignore ATTRIBUTE_UNUSED
)
5949 struct save_opts
*s
;
5951 s
= XNEW (struct save_opts
);
5952 s
->abspcadd
= m68k_abspcadd
;
5953 s
->symbols_case_sensitive
= symbols_case_sensitive
;
5954 s
->keep_locals
= flag_keep_locals
;
5955 s
->short_refs
= flag_short_refs
;
5956 s
->architecture
= current_architecture
;
5957 s
->control_regs
= control_regs
;
5958 s
->quick
= m68k_quick
;
5959 s
->rel32
= m68k_rel32
;
5960 s
->listing
= listing
;
5961 s
->no_warnings
= flag_no_warnings
;
5963 s
->next
= save_stack
;
5966 demand_empty_rest_of_line ();
5969 /* The MRI RESTORE pseudo-op. */
5972 s_restore (int ignore ATTRIBUTE_UNUSED
)
5974 struct save_opts
*s
;
5976 if (save_stack
== NULL
)
5978 as_bad (_("restore without save"));
5979 ignore_rest_of_line ();
5984 save_stack
= s
->next
;
5986 m68k_abspcadd
= s
->abspcadd
;
5987 symbols_case_sensitive
= s
->symbols_case_sensitive
;
5988 flag_keep_locals
= s
->keep_locals
;
5989 flag_short_refs
= s
->short_refs
;
5990 current_architecture
= s
->architecture
;
5991 control_regs
= s
->control_regs
;
5992 m68k_quick
= s
->quick
;
5993 m68k_rel32
= s
->rel32
;
5994 listing
= s
->listing
;
5995 flag_no_warnings
= s
->no_warnings
;
5999 demand_empty_rest_of_line ();
6002 /* Types of MRI structured control directives. */
6004 enum mri_control_type
6012 /* This structure is used to stack the MRI structured control
6015 struct mri_control_info
6017 /* The directive within which this one is enclosed. */
6018 struct mri_control_info
*outer
;
6020 /* The type of directive. */
6021 enum mri_control_type type
;
6023 /* Whether an ELSE has been in an IF. */
6026 /* The add or sub statement at the end of a FOR. */
6029 /* The label of the top of a FOR or REPEAT loop. */
6032 /* The label to jump to for the next iteration, or the else
6033 expression of a conditional. */
6036 /* The label to jump to to break out of the loop, or the label past
6037 the end of a conditional. */
6041 /* The stack of MRI structured control directives. */
6043 static struct mri_control_info
*mri_control_stack
;
6045 /* The current MRI structured control directive index number, used to
6046 generate label names. */
6048 static int mri_control_index
;
6050 /* Assemble an instruction for an MRI structured control directive. */
6053 mri_assemble (char *str
)
6057 /* md_assemble expects the opcode to be in lower case. */
6058 for (s
= str
; *s
!= ' ' && *s
!= '\0'; s
++)
6064 /* Generate a new MRI label structured control directive label name. */
6067 mri_control_label (void)
6071 n
= XNEWVEC (char, 20);
6072 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
6073 ++mri_control_index
;
6077 /* Create a new MRI structured control directive. */
6079 static struct mri_control_info
*
6080 push_mri_control (enum mri_control_type type
)
6082 struct mri_control_info
*n
;
6084 n
= XNEW (struct mri_control_info
);
6088 if (type
== mri_if
|| type
== mri_while
)
6091 n
->top
= mri_control_label ();
6092 n
->next
= mri_control_label ();
6093 n
->bottom
= mri_control_label ();
6095 n
->outer
= mri_control_stack
;
6096 mri_control_stack
= n
;
6101 /* Pop off the stack of MRI structured control directives. */
6104 pop_mri_control (void)
6106 struct mri_control_info
*n
;
6108 n
= mri_control_stack
;
6109 mri_control_stack
= n
->outer
;
6116 /* Recognize a condition code in an MRI structured control expression. */
6119 parse_mri_condition (int *pcc
)
6123 know (*input_line_pointer
== '<');
6125 ++input_line_pointer
;
6126 c1
= *input_line_pointer
++;
6127 c2
= *input_line_pointer
++;
6129 if (*input_line_pointer
!= '>')
6131 as_bad (_("syntax error in structured control directive"));
6135 ++input_line_pointer
;
6141 *pcc
= (c1
<< 8) | c2
;
6146 /* Parse a single operand in an MRI structured control expression. */
6149 parse_mri_control_operand (int *pcc
, char **leftstart
, char **leftstop
,
6150 char **rightstart
, char **rightstop
)
6162 if (*input_line_pointer
== '<')
6164 /* It's just a condition code. */
6165 return parse_mri_condition (pcc
);
6168 /* Look ahead for the condition code. */
6169 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
6171 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
6176 as_bad (_("missing condition code in structured control directive"));
6180 *leftstart
= input_line_pointer
;
6182 if (*leftstop
> *leftstart
6183 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
6186 input_line_pointer
= s
;
6187 if (! parse_mri_condition (pcc
))
6190 /* Look ahead for AND or OR or end of line. */
6191 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
6193 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6194 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6196 if ((s
== input_line_pointer
6199 && ((strncasecmp (s
, "AND", 3) == 0
6200 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
6201 || (strncasecmp (s
, "OR", 2) == 0
6202 && (s
[2] == '.' || ! is_part_of_name (s
[2])))))
6206 *rightstart
= input_line_pointer
;
6208 if (*rightstop
> *rightstart
6209 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
6212 input_line_pointer
= s
;
6217 #define MCC(b1, b2) (((b1) << 8) | (b2))
6219 /* Swap the sense of a condition. This changes the condition so that
6220 it generates the same result when the operands are swapped. */
6223 swap_mri_condition (int cc
)
6227 case MCC ('h', 'i'): return MCC ('c', 's');
6228 case MCC ('l', 's'): return MCC ('c', 'c');
6229 /* <HS> is an alias for <CC>. */
6230 case MCC ('h', 's'):
6231 case MCC ('c', 'c'): return MCC ('l', 's');
6232 /* <LO> is an alias for <CS>. */
6233 case MCC ('l', 'o'):
6234 case MCC ('c', 's'): return MCC ('h', 'i');
6235 case MCC ('p', 'l'): return MCC ('m', 'i');
6236 case MCC ('m', 'i'): return MCC ('p', 'l');
6237 case MCC ('g', 'e'): return MCC ('l', 'e');
6238 case MCC ('l', 't'): return MCC ('g', 't');
6239 case MCC ('g', 't'): return MCC ('l', 't');
6240 case MCC ('l', 'e'): return MCC ('g', 'e');
6241 /* Issue a warning for conditions we can not swap. */
6242 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6243 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
6244 case MCC ('v', 'c'):
6245 case MCC ('v', 's'):
6247 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6248 (char) (cc
>> 8), (char) (cc
));
6254 /* Reverse the sense of a condition. */
6257 reverse_mri_condition (int cc
)
6261 case MCC ('h', 'i'): return MCC ('l', 's');
6262 case MCC ('l', 's'): return MCC ('h', 'i');
6263 /* <HS> is an alias for <CC> */
6264 case MCC ('h', 's'): return MCC ('l', 'o');
6265 case MCC ('c', 'c'): return MCC ('c', 's');
6266 /* <LO> is an alias for <CS> */
6267 case MCC ('l', 'o'): return MCC ('h', 's');
6268 case MCC ('c', 's'): return MCC ('c', 'c');
6269 case MCC ('n', 'e'): return MCC ('e', 'q');
6270 case MCC ('e', 'q'): return MCC ('n', 'e');
6271 case MCC ('v', 'c'): return MCC ('v', 's');
6272 case MCC ('v', 's'): return MCC ('v', 'c');
6273 case MCC ('p', 'l'): return MCC ('m', 'i');
6274 case MCC ('m', 'i'): return MCC ('p', 'l');
6275 case MCC ('g', 'e'): return MCC ('l', 't');
6276 case MCC ('l', 't'): return MCC ('g', 'e');
6277 case MCC ('g', 't'): return MCC ('l', 'e');
6278 case MCC ('l', 'e'): return MCC ('g', 't');
6283 /* Build an MRI structured control expression. This generates test
6284 and branch instructions. It goes to TRUELAB if the condition is
6285 true, and to FALSELAB if the condition is false. Exactly one of
6286 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6287 is the size qualifier for the expression. EXTENT is the size to
6288 use for the branch. */
6291 build_mri_control_operand (int qual
, int cc
, char *leftstart
, char *leftstop
,
6292 char *rightstart
, char *rightstop
,
6293 const char *truelab
, const char *falselab
,
6299 if (leftstart
!= NULL
)
6301 struct m68k_op leftop
, rightop
;
6304 /* Swap the compare operands, if necessary, to produce a legal
6305 m68k compare instruction. Comparing a register operand with
6306 a non-register operand requires the register to be on the
6307 right (cmp, cmpa). Comparing an immediate value with
6308 anything requires the immediate value to be on the left
6313 (void) m68k_ip_op (leftstart
, &leftop
);
6318 (void) m68k_ip_op (rightstart
, &rightop
);
6321 if (rightop
.mode
== IMMED
6322 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
6323 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
6327 /* Correct conditional handling:
6328 if #1 <lt> d0 then ;means if (1 < d0)
6334 cmp #1,d0 if we do *not* swap the operands
6335 bgt true we need the swapped condition!
6342 leftstart
= rightstart
;
6345 leftstop
= rightstop
;
6350 cc
= swap_mri_condition (cc
);
6354 if (truelab
== NULL
)
6356 cc
= reverse_mri_condition (cc
);
6360 if (leftstart
!= NULL
)
6362 buf
= XNEWVEC (char, (20
6363 + (leftstop
- leftstart
)
6364 + (rightstop
- rightstart
)));
6370 *s
++ = TOLOWER (qual
);
6372 memcpy (s
, leftstart
, leftstop
- leftstart
);
6373 s
+= leftstop
- leftstart
;
6375 memcpy (s
, rightstart
, rightstop
- rightstart
);
6376 s
+= rightstop
- rightstart
;
6382 buf
= XNEWVEC (char, 20 + strlen (truelab
));
6388 *s
++ = TOLOWER (extent
);
6390 strcpy (s
, truelab
);
6395 /* Parse an MRI structured control expression. This generates test
6396 and branch instructions. STOP is where the expression ends. It
6397 goes to TRUELAB if the condition is true, and to FALSELAB if the
6398 condition is false. Exactly one of TRUELAB and FALSELAB will be
6399 NULL, meaning to fall through. QUAL is the size qualifier for the
6400 expression. EXTENT is the size to use for the branch. */
6403 parse_mri_control_expression (char *stop
, int qual
, const char *truelab
,
6404 const char *falselab
, int extent
)
6416 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6417 &rightstart
, &rightstop
))
6423 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
6427 if (falselab
!= NULL
)
6430 flab
= mri_control_label ();
6432 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6433 rightstop
, (const char *) NULL
, flab
, extent
);
6435 input_line_pointer
+= 3;
6436 if (*input_line_pointer
!= '.'
6437 || input_line_pointer
[1] == '\0')
6441 qual
= input_line_pointer
[1];
6442 input_line_pointer
+= 2;
6445 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6446 &rightstart
, &rightstop
))
6452 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6453 rightstop
, truelab
, falselab
, extent
);
6455 if (falselab
== NULL
)
6458 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
6462 if (truelab
!= NULL
)
6465 tlab
= mri_control_label ();
6467 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6468 rightstop
, tlab
, (const char *) NULL
, extent
);
6470 input_line_pointer
+= 2;
6471 if (*input_line_pointer
!= '.'
6472 || input_line_pointer
[1] == '\0')
6476 qual
= input_line_pointer
[1];
6477 input_line_pointer
+= 2;
6480 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6481 &rightstart
, &rightstop
))
6487 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6488 rightstop
, truelab
, falselab
, extent
);
6490 if (truelab
== NULL
)
6495 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6496 rightstop
, truelab
, falselab
, extent
);
6500 if (input_line_pointer
!= stop
)
6501 as_bad (_("syntax error in structured control directive"));
6504 /* Handle the MRI IF pseudo-op. This may be a structured control
6505 directive, or it may be a regular assembler conditional, depending
6513 struct mri_control_info
*n
;
6515 /* A structured control directive must end with THEN with an
6516 optional qualifier. */
6517 s
= input_line_pointer
;
6518 /* We only accept '*' as introduction of comments if preceded by white space
6519 or at first column of a line (I think this can't actually happen here?)
6520 This is important when assembling:
6521 if d0 <ne> 12(a0,d0*2) then
6522 if d0 <ne> #CONST*20 then. */
6523 while (! (is_end_of_line
[(unsigned char) *s
]
6526 && (s
== input_line_pointer
6528 || *(s
-1) == '\t'))))
6531 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
6534 if (s
- input_line_pointer
> 1
6538 if (s
- input_line_pointer
< 3
6539 || strncasecmp (s
- 3, "THEN", 4) != 0)
6543 as_bad (_("missing then"));
6544 ignore_rest_of_line ();
6548 /* It's a conditional. */
6553 /* Since this might be a conditional if, this pseudo-op will be
6554 called even if we are supported to be ignoring input. Double
6555 check now. Clobber *input_line_pointer so that ignore_input
6556 thinks that this is not a special pseudo-op. */
6557 c
= *input_line_pointer
;
6558 *input_line_pointer
= 0;
6559 if (ignore_input ())
6561 *input_line_pointer
= c
;
6562 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6563 ++input_line_pointer
;
6564 demand_empty_rest_of_line ();
6567 *input_line_pointer
= c
;
6569 n
= push_mri_control (mri_if
);
6571 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
6572 n
->next
, s
[1] == '.' ? s
[2] : '\0');
6575 input_line_pointer
= s
+ 3;
6577 input_line_pointer
= s
+ 1;
6581 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6582 ++input_line_pointer
;
6585 demand_empty_rest_of_line ();
6588 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6589 structured IF, associate the ELSE with the IF. Otherwise, assume
6590 it is a conditional else. */
6593 s_mri_else (int qual
)
6600 && (mri_control_stack
== NULL
6601 || mri_control_stack
->type
!= mri_if
6602 || mri_control_stack
->else_seen
))
6608 c
= *input_line_pointer
;
6609 *input_line_pointer
= 0;
6610 if (ignore_input ())
6612 *input_line_pointer
= c
;
6613 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6614 ++input_line_pointer
;
6615 demand_empty_rest_of_line ();
6618 *input_line_pointer
= c
;
6620 if (mri_control_stack
== NULL
6621 || mri_control_stack
->type
!= mri_if
6622 || mri_control_stack
->else_seen
)
6624 as_bad (_("else without matching if"));
6625 ignore_rest_of_line ();
6629 mri_control_stack
->else_seen
= 1;
6631 buf
= XNEWVEC (char, 20 + strlen (mri_control_stack
->bottom
));
6632 q
[0] = TOLOWER (qual
);
6634 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6638 colon (mri_control_stack
->next
);
6642 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6643 ++input_line_pointer
;
6646 demand_empty_rest_of_line ();
6649 /* Handle the MRI ENDI pseudo-op. */
6652 s_mri_endi (int ignore ATTRIBUTE_UNUSED
)
6654 if (mri_control_stack
== NULL
6655 || mri_control_stack
->type
!= mri_if
)
6657 as_bad (_("endi without matching if"));
6658 ignore_rest_of_line ();
6662 /* ignore_input will not return true for ENDI, so we don't need to
6663 worry about checking it again here. */
6665 if (! mri_control_stack
->else_seen
)
6666 colon (mri_control_stack
->next
);
6667 colon (mri_control_stack
->bottom
);
6673 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6674 ++input_line_pointer
;
6677 demand_empty_rest_of_line ();
6680 /* Handle the MRI BREAK pseudo-op. */
6683 s_mri_break (int extent
)
6685 struct mri_control_info
*n
;
6689 n
= mri_control_stack
;
6691 && n
->type
!= mri_for
6692 && n
->type
!= mri_repeat
6693 && n
->type
!= mri_while
)
6697 as_bad (_("break outside of structured loop"));
6698 ignore_rest_of_line ();
6702 buf
= XNEWVEC (char, 20 + strlen (n
->bottom
));
6703 ex
[0] = TOLOWER (extent
);
6705 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6711 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6712 ++input_line_pointer
;
6715 demand_empty_rest_of_line ();
6718 /* Handle the MRI NEXT pseudo-op. */
6721 s_mri_next (int extent
)
6723 struct mri_control_info
*n
;
6727 n
= mri_control_stack
;
6729 && n
->type
!= mri_for
6730 && n
->type
!= mri_repeat
6731 && n
->type
!= mri_while
)
6735 as_bad (_("next outside of structured loop"));
6736 ignore_rest_of_line ();
6740 buf
= XNEWVEC (char, 20 + strlen (n
->next
));
6741 ex
[0] = TOLOWER (extent
);
6743 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6749 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6750 ++input_line_pointer
;
6753 demand_empty_rest_of_line ();
6756 /* Handle the MRI FOR pseudo-op. */
6759 s_mri_for (int qual
)
6761 const char *varstart
, *varstop
;
6762 const char *initstart
, *initstop
;
6763 const char *endstart
, *endstop
;
6764 const char *bystart
, *bystop
;
6768 struct mri_control_info
*n
;
6774 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6778 varstart
= input_line_pointer
;
6780 /* Look for the '='. */
6781 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6782 && *input_line_pointer
!= '=')
6783 ++input_line_pointer
;
6784 if (*input_line_pointer
!= '=')
6786 as_bad (_("missing ="));
6787 ignore_rest_of_line ();
6791 varstop
= input_line_pointer
;
6792 if (varstop
> varstart
6793 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6796 ++input_line_pointer
;
6798 initstart
= input_line_pointer
;
6800 /* Look for TO or DOWNTO. */
6803 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6805 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6806 && ! is_part_of_name (input_line_pointer
[2]))
6808 initstop
= input_line_pointer
;
6809 input_line_pointer
+= 2;
6812 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6813 && ! is_part_of_name (input_line_pointer
[6]))
6815 initstop
= input_line_pointer
;
6817 input_line_pointer
+= 6;
6820 ++input_line_pointer
;
6822 if (initstop
== NULL
)
6824 as_bad (_("missing to or downto"));
6825 ignore_rest_of_line ();
6828 if (initstop
> initstart
6829 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6833 endstart
= input_line_pointer
;
6835 /* Look for BY or DO. */
6838 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6840 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
6841 && ! is_part_of_name (input_line_pointer
[2]))
6843 endstop
= input_line_pointer
;
6845 input_line_pointer
+= 2;
6848 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6849 && (input_line_pointer
[2] == '.'
6850 || ! is_part_of_name (input_line_pointer
[2])))
6852 endstop
= input_line_pointer
;
6853 input_line_pointer
+= 2;
6856 ++input_line_pointer
;
6858 if (endstop
== NULL
)
6860 as_bad (_("missing do"));
6861 ignore_rest_of_line ();
6864 if (endstop
> endstart
6865 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
6871 bystop
= bystart
+ 2;
6876 bystart
= input_line_pointer
;
6880 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6882 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6883 && (input_line_pointer
[2] == '.'
6884 || ! is_part_of_name (input_line_pointer
[2])))
6886 bystop
= input_line_pointer
;
6887 input_line_pointer
+= 2;
6890 ++input_line_pointer
;
6894 as_bad (_("missing do"));
6895 ignore_rest_of_line ();
6898 if (bystop
> bystart
6899 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
6903 if (*input_line_pointer
!= '.')
6907 extent
= input_line_pointer
[1];
6908 input_line_pointer
+= 2;
6911 /* We have fully parsed the FOR operands. Now build the loop. */
6912 n
= push_mri_control (mri_for
);
6914 buf
= XNEWVEC (char, 50 + (input_line_pointer
- varstart
));
6916 /* Move init,var. */
6923 *s
++ = TOLOWER (qual
);
6925 memcpy (s
, initstart
, initstop
- initstart
);
6926 s
+= initstop
- initstart
;
6928 memcpy (s
, varstart
, varstop
- varstart
);
6929 s
+= varstop
- varstart
;
6941 *s
++ = TOLOWER (qual
);
6943 memcpy (s
, endstart
, endstop
- endstart
);
6944 s
+= endstop
- endstart
;
6946 memcpy (s
, varstart
, varstop
- varstart
);
6947 s
+= varstop
- varstart
;
6952 ex
[0] = TOLOWER (extent
);
6955 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
6957 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
6960 /* Put together the add or sub instruction used by ENDF. */
6968 *s
++ = TOLOWER (qual
);
6970 memcpy (s
, bystart
, bystop
- bystart
);
6971 s
+= bystop
- bystart
;
6973 memcpy (s
, varstart
, varstop
- varstart
);
6974 s
+= varstop
- varstart
;
6980 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6981 ++input_line_pointer
;
6984 demand_empty_rest_of_line ();
6987 /* Handle the MRI ENDF pseudo-op. */
6990 s_mri_endf (int ignore ATTRIBUTE_UNUSED
)
6992 if (mri_control_stack
== NULL
6993 || mri_control_stack
->type
!= mri_for
)
6995 as_bad (_("endf without for"));
6996 ignore_rest_of_line ();
7000 colon (mri_control_stack
->next
);
7002 mri_assemble (mri_control_stack
->incr
);
7004 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
7005 mri_assemble (mri_control_stack
->incr
);
7007 free (mri_control_stack
->incr
);
7009 colon (mri_control_stack
->bottom
);
7015 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7016 ++input_line_pointer
;
7019 demand_empty_rest_of_line ();
7022 /* Handle the MRI REPEAT pseudo-op. */
7025 s_mri_repeat (int ignore ATTRIBUTE_UNUSED
)
7027 struct mri_control_info
*n
;
7029 n
= push_mri_control (mri_repeat
);
7033 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7034 ++input_line_pointer
;
7036 demand_empty_rest_of_line ();
7039 /* Handle the MRI UNTIL pseudo-op. */
7042 s_mri_until (int qual
)
7046 if (mri_control_stack
== NULL
7047 || mri_control_stack
->type
!= mri_repeat
)
7049 as_bad (_("until without repeat"));
7050 ignore_rest_of_line ();
7054 colon (mri_control_stack
->next
);
7056 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
7059 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
7060 mri_control_stack
->top
, '\0');
7062 colon (mri_control_stack
->bottom
);
7064 input_line_pointer
= s
;
7070 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7071 ++input_line_pointer
;
7074 demand_empty_rest_of_line ();
7077 /* Handle the MRI WHILE pseudo-op. */
7080 s_mri_while (int qual
)
7084 struct mri_control_info
*n
;
7086 s
= input_line_pointer
;
7087 /* We only accept '*' as introduction of comments if preceded by white space
7088 or at first column of a line (I think this can't actually happen here?)
7089 This is important when assembling:
7090 while d0 <ne> 12(a0,d0*2) do
7091 while d0 <ne> #CONST*20 do. */
7092 while (! (is_end_of_line
[(unsigned char) *s
]
7095 && (s
== input_line_pointer
7097 || *(s
-1) == '\t'))))
7100 while (*s
== ' ' || *s
== '\t')
7102 if (s
- input_line_pointer
> 1
7105 if (s
- input_line_pointer
< 2
7106 || strncasecmp (s
- 1, "DO", 2) != 0)
7108 as_bad (_("missing do"));
7109 ignore_rest_of_line ();
7113 n
= push_mri_control (mri_while
);
7117 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
7118 s
[1] == '.' ? s
[2] : '\0');
7120 input_line_pointer
= s
+ 1;
7121 if (*input_line_pointer
== '.')
7122 input_line_pointer
+= 2;
7126 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7127 ++input_line_pointer
;
7130 demand_empty_rest_of_line ();
7133 /* Handle the MRI ENDW pseudo-op. */
7136 s_mri_endw (int ignore ATTRIBUTE_UNUSED
)
7140 if (mri_control_stack
== NULL
7141 || mri_control_stack
->type
!= mri_while
)
7143 as_bad (_("endw without while"));
7144 ignore_rest_of_line ();
7148 buf
= XNEWVEC (char, 20 + strlen (mri_control_stack
->next
));
7149 sprintf (buf
, "bra %s", mri_control_stack
->next
);
7153 colon (mri_control_stack
->bottom
);
7159 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7160 ++input_line_pointer
;
7163 demand_empty_rest_of_line ();
7166 /* Parse a .cpu directive. */
7169 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED
)
7176 as_bad (_("already assembled instructions"));
7177 ignore_rest_of_line ();
7181 name
= input_line_pointer
;
7182 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
7183 input_line_pointer
++;
7184 saved_char
= *input_line_pointer
;
7185 *input_line_pointer
= 0;
7187 m68k_set_cpu (name
, 1, 0);
7189 *input_line_pointer
= saved_char
;
7190 demand_empty_rest_of_line ();
7194 /* Parse a .arch directive. */
7197 s_m68k_arch (int ignored ATTRIBUTE_UNUSED
)
7204 as_bad (_("already assembled instructions"));
7205 ignore_rest_of_line ();
7209 name
= input_line_pointer
;
7210 while (*input_line_pointer
&& *input_line_pointer
!= ','
7211 && !ISSPACE (*input_line_pointer
))
7212 input_line_pointer
++;
7213 saved_char
= *input_line_pointer
;
7214 *input_line_pointer
= 0;
7216 if (m68k_set_arch (name
, 1, 0))
7218 /* Scan extensions. */
7221 *input_line_pointer
++ = saved_char
;
7222 if (!*input_line_pointer
|| ISSPACE (*input_line_pointer
))
7224 name
= input_line_pointer
;
7225 while (*input_line_pointer
&& *input_line_pointer
!= ','
7226 && !ISSPACE (*input_line_pointer
))
7227 input_line_pointer
++;
7228 saved_char
= *input_line_pointer
;
7229 *input_line_pointer
= 0;
7231 while (m68k_set_extension (name
, 1, 0));
7234 *input_line_pointer
= saved_char
;
7235 demand_empty_rest_of_line ();
7239 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7240 if none is found, the caller is responsible for emitting an error
7241 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7242 cpu name, if it begins with a '6' (possibly skipping an intervening
7243 'c'. We also allow a 'c' in the same place. if NEGATED is
7244 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7245 the option is indeed negated. */
7247 static const struct m68k_cpu
*
7248 m68k_lookup_cpu (const char *arg
, const struct m68k_cpu
*table
,
7249 int allow_m
, int *negated
)
7251 /* allow negated value? */
7256 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
7263 /* Remove 'm' or 'mc' prefix from 68k variants. */
7270 else if (arg
[1] == 'c' && arg
[2] == '6')
7274 else if (arg
[0] == 'c' && arg
[1] == '6')
7277 for (; table
->name
; table
++)
7278 if (!strcmp (arg
, table
->name
))
7280 if (table
->alias
< -1 || table
->alias
> 1)
7281 as_bad (_("`%s' is deprecated, use `%s'"),
7282 table
->name
, table
[table
->alias
< 0 ? 1 : -1].name
);
7288 /* Set the cpu, issuing errors if it is unrecognized. */
7291 m68k_set_cpu (char const *name
, int allow_m
, int silent
)
7293 const struct m68k_cpu
*cpu
;
7295 cpu
= m68k_lookup_cpu (name
, m68k_cpus
, allow_m
, NULL
);
7300 as_bad (_("cpu `%s' unrecognized"), name
);
7307 /* Set the architecture, issuing errors if it is unrecognized. */
7310 m68k_set_arch (char const *name
, int allow_m
, int silent
)
7312 const struct m68k_cpu
*arch
;
7314 arch
= m68k_lookup_cpu (name
, m68k_archs
, allow_m
, NULL
);
7319 as_bad (_("architecture `%s' unrecognized"), name
);
7322 selected_arch
= arch
;
7326 /* Set the architecture extension, issuing errors if it is
7327 unrecognized, or invalid */
7330 m68k_set_extension (char const *name
, int allow_m
, int silent
)
7333 const struct m68k_cpu
*ext
;
7335 ext
= m68k_lookup_cpu (name
, m68k_extensions
, allow_m
, &negated
);
7340 as_bad (_("extension `%s' unrecognized"), name
);
7345 not_current_architecture
|= (ext
->control_regs
7346 ? *(unsigned *)ext
->control_regs
: ext
->arch
);
7348 current_architecture
|= ext
->arch
;
7353 Invocation line includes a switch not recognized by the base assembler.
7356 const char *md_shortopts
= "lSA:m:kQ:V";
7358 struct option md_longopts
[] = {
7359 #define OPTION_PIC (OPTION_MD_BASE)
7360 {"pic", no_argument
, NULL
, OPTION_PIC
},
7361 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7362 {"register-prefix-optional", no_argument
, NULL
,
7363 OPTION_REGISTER_PREFIX_OPTIONAL
},
7364 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7365 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
7366 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7367 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
7368 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7369 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
7370 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7371 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
7372 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7373 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
7374 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7375 {"pcrel", no_argument
, NULL
, OPTION_PCREL
},
7376 {NULL
, no_argument
, NULL
, 0}
7378 size_t md_longopts_size
= sizeof (md_longopts
);
7381 md_parse_option (int c
, const char *arg
)
7385 case 'l': /* -l means keep external to 2 bit offset
7386 rather than 16 bit one. */
7387 flag_short_refs
= 1;
7390 case 'S': /* -S means that jbsr's always turn into
7392 flag_long_jumps
= 1;
7395 case OPTION_PCREL
: /* --pcrel means never turn PC-relative
7396 branches into absolute jumps. */
7397 flag_keep_pcrel
= 1;
7403 break; /* -pic, Position Independent Code. */
7405 case OPTION_REGISTER_PREFIX_OPTIONAL
:
7406 flag_reg_prefix_optional
= 1;
7407 reg_prefix_optional_seen
= 1;
7410 /* -V: SVR4 argument to print version ID. */
7412 print_version_id ();
7415 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7416 should be emitted or not. FIXME: Not implemented. */
7420 case OPTION_BITWISE_OR
:
7425 n
= XNEWVEC (char, strlen (m68k_comment_chars
) + 1);
7427 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
7431 m68k_comment_chars
= n
;
7435 case OPTION_BASE_SIZE_DEFAULT_16
:
7436 m68k_index_width_default
= SIZE_WORD
;
7439 case OPTION_BASE_SIZE_DEFAULT_32
:
7440 m68k_index_width_default
= SIZE_LONG
;
7443 case OPTION_DISP_SIZE_DEFAULT_16
:
7445 m68k_rel32_from_cmdline
= 1;
7448 case OPTION_DISP_SIZE_DEFAULT_32
:
7450 m68k_rel32_from_cmdline
= 1;
7455 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7458 /* Intentional fall-through. */
7460 if (startswith (arg
, "arch="))
7461 m68k_set_arch (arg
+ 5, 1, 0);
7462 else if (startswith (arg
, "cpu="))
7463 m68k_set_cpu (arg
+ 4, 1, 0);
7464 else if (m68k_set_extension (arg
, 0, 1))
7466 else if (m68k_set_arch (arg
, 0, 1))
7468 else if (m68k_set_cpu (arg
, 0, 1))
7481 /* Setup tables from the selected arch and/or cpu */
7484 m68k_init_arch (void)
7486 if (not_current_architecture
& current_architecture
)
7488 as_bad (_("architecture features both enabled and disabled"));
7489 not_current_architecture
&= ~current_architecture
;
7493 current_architecture
|= selected_arch
->arch
;
7494 control_regs
= selected_arch
->control_regs
;
7497 current_architecture
|= selected_cpu
->arch
;
7499 current_architecture
&= ~not_current_architecture
;
7501 if ((current_architecture
& (cfloat
| m68881
)) == (cfloat
| m68881
))
7503 /* Determine which float is really meant. */
7504 if (current_architecture
& (m68k_mask
& ~m68881
))
7505 current_architecture
^= cfloat
;
7507 current_architecture
^= m68881
;
7512 control_regs
= selected_cpu
->control_regs
;
7513 if (current_architecture
& ~selected_cpu
->arch
)
7515 as_bad (_("selected processor does not have all features of selected architecture"));
7516 current_architecture
7517 = selected_cpu
->arch
& ~not_current_architecture
;
7521 if ((current_architecture
& m68k_mask
)
7522 && (current_architecture
& ~m68k_mask
))
7524 as_bad (_ ("m68k and cf features both selected"));
7525 if (current_architecture
& m68k_mask
)
7526 current_architecture
&= m68k_mask
;
7528 current_architecture
&= ~m68k_mask
;
7531 /* Permit m68881 specification with all cpus; those that can't work
7532 with a coprocessor could be doing emulation. */
7533 if (current_architecture
& m68851
)
7535 if (current_architecture
& m68040
)
7536 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7538 /* What other incompatibilities could we check for? */
7540 if (cpu_of_arch (current_architecture
) < m68020
7541 || arch_coldfire_p (current_architecture
))
7542 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
7548 md_show_usage (FILE *stream
)
7550 const char *default_cpu
= TARGET_CPU
;
7553 /* Get the canonical name for the default target CPU. */
7554 if (*default_cpu
== 'm')
7556 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7558 if (strcasecmp (default_cpu
, m68k_cpus
[i
].name
) == 0)
7560 while (m68k_cpus
[i
].alias
> 0)
7562 while (m68k_cpus
[i
].alias
< 0)
7564 default_cpu
= m68k_cpus
[i
].name
;
7568 fprintf (stream
, _("\
7569 -march=<arch> set architecture\n\
7570 -mcpu=<cpu> set cpu [default %s]\n\
7572 for (i
= 0; m68k_extensions
[i
].name
; i
++)
7573 fprintf (stream
, _("\
7574 -m[no-]%-16s enable/disable %s architecture extension\n\
7575 "), m68k_extensions
[i
].name
,
7576 m68k_extensions
[i
].alias
> 0 ? " ColdFire"
7577 : m68k_extensions
[i
].alias
< 0 ? " m68k" : "");
7579 fprintf (stream
, _("\
7580 -l use 1 word for refs to undefined symbols [default 2]\n\
7581 -pic, -k generate position independent code\n\
7582 -S turn jbsr into jsr\n\
7583 --pcrel never turn PC-relative branches into absolute jumps\n\
7584 --register-prefix-optional\n\
7585 recognize register names without prefix character\n\
7586 --bitwise-or do not treat `|' as a comment character\n\
7587 --base-size-default-16 base reg without size is 16 bits\n\
7588 --base-size-default-32 base reg without size is 32 bits (default)\n\
7589 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7590 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7593 fprintf (stream
, _("Architecture variants are: "));
7594 for (i
= 0; m68k_archs
[i
].name
; i
++)
7597 fprintf (stream
, " | ");
7598 fprintf (stream
, "%s", m68k_archs
[i
].name
);
7600 fprintf (stream
, "\n");
7602 fprintf (stream
, _("Processor variants are: "));
7603 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7606 fprintf (stream
, " | ");
7607 fprintf (stream
, "%s", m68k_cpus
[i
].name
);
7609 fprintf (stream
, _("\n"));
7614 /* TEST2: Test md_assemble() */
7615 /* Warning, this routine probably doesn't work anymore. */
7619 struct m68k_it the_ins
;
7627 if (!gets (buf
) || !*buf
)
7629 if (buf
[0] == '|' || buf
[1] == '.')
7631 for (cp
= buf
; *cp
; cp
++)
7636 memset (&the_ins
, '\0', sizeof (the_ins
));
7637 m68k_ip (&the_ins
, buf
);
7640 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
7644 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
7645 for (n
= 0; n
< the_ins
.numo
; n
++)
7646 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
7648 print_the_insn (&the_ins
.opcode
[0], stdout
);
7649 (void) putchar ('\n');
7651 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
7653 if (the_ins
.operands
[n
].error
)
7655 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
7658 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
,
7659 the_ins
.operands
[n
].reg
);
7660 if (the_ins
.operands
[n
].b_const
)
7661 printf ("Constant: '%.*s', ",
7662 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
,
7663 the_ins
.operands
[n
].b_const
);
7664 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
,
7665 the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
7666 if (the_ins
.operands
[n
].b_iadd
)
7667 printf ("Iadd: '%.*s',",
7668 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
,
7669 the_ins
.operands
[n
].b_iadd
);
7678 is_label (char *str
)
7682 while (*str
&& *str
!= ' ')
7684 if (str
[-1] == ':' || str
[1] == '=')
7691 /* Possible states for relaxation:
7693 0 0 branch offset byte (bra, etc)
7697 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7701 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7708 /* We have no need to default values of symbols. */
7711 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7716 /* Round up a section size to the appropriate boundary. */
7718 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7723 /* Exactly what point is a PC-relative offset relative TO?
7724 On the 68k, it is relative to the address of the first extension
7725 word. The difference between the addresses of the offset and the
7726 first extension word is stored in fx_pcrel_adjust. */
7728 md_pcrel_from (fixS
*fixP
)
7732 adjust
= fixP
->fx_pcrel_adjust
;
7735 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
7739 m68k_elf_final_processing (void)
7743 if (arch_coldfire_fpu (current_architecture
))
7744 flags
|= EF_M68K_CFV4E
;
7745 /* Set file-specific flags if this is a cpu32 processor. */
7746 if (cpu_of_arch (current_architecture
) & cpu32
)
7747 flags
|= EF_M68K_CPU32
;
7748 else if (cpu_of_arch (current_architecture
) & fido_a
)
7749 flags
|= EF_M68K_FIDO
;
7750 else if ((cpu_of_arch (current_architecture
) & m68000up
)
7751 && !(cpu_of_arch (current_architecture
) & m68020up
))
7752 flags
|= EF_M68K_M68000
;
7754 if (current_architecture
& mcfisa_a
)
7756 static const unsigned isa_features
[][2] =
7758 {EF_M68K_CF_ISA_A_NODIV
,mcfisa_a
},
7759 {EF_M68K_CF_ISA_A
, mcfisa_a
|mcfhwdiv
},
7760 {EF_M68K_CF_ISA_A_PLUS
, mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfusp
},
7761 {EF_M68K_CF_ISA_B_NOUSP
,mcfisa_a
|mcfisa_b
|mcfhwdiv
},
7762 {EF_M68K_CF_ISA_B
, mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfusp
},
7763 {EF_M68K_CF_ISA_C
, mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfusp
},
7764 {EF_M68K_CF_ISA_C_NODIV
,mcfisa_a
|mcfisa_c
|mcfusp
},
7767 static const unsigned mac_features
[][2] =
7769 {EF_M68K_CF_MAC
, mcfmac
},
7770 {EF_M68K_CF_EMAC
, mcfemac
},
7776 pattern
= (current_architecture
7777 & (mcfisa_a
|mcfisa_aa
|mcfisa_b
|mcfisa_c
|mcfhwdiv
|mcfusp
));
7778 for (ix
= 0; isa_features
[ix
][1]; ix
++)
7780 if (pattern
== isa_features
[ix
][1])
7782 flags
|= isa_features
[ix
][0];
7786 if (!isa_features
[ix
][1])
7789 as_warn (_("Not a defined coldfire architecture"));
7793 if (current_architecture
& cfloat
)
7794 flags
|= EF_M68K_CF_FLOAT
| EF_M68K_CFV4E
;
7796 pattern
= current_architecture
& (mcfmac
|mcfemac
);
7799 for (ix
= 0; mac_features
[ix
][1]; ix
++)
7801 if (pattern
== mac_features
[ix
][1])
7803 flags
|= mac_features
[ix
][0];
7807 if (!mac_features
[ix
][1])
7812 elf_elfheader (stdoutput
)->e_flags
|= flags
;
7815 /* Parse @TLSLDO and return the desired relocation. */
7816 static bfd_reloc_code_real_type
7817 m68k_elf_suffix (char **str_p
, expressionS
*exp_p
)
7826 return BFD_RELOC_UNUSED
;
7828 for (ch
= *str
, str2
= ident
;
7829 (str2
< ident
+ sizeof (ident
) - 1
7830 && (ISALNUM (ch
) || ch
== '@'));
7839 if (startswith (ident
, "TLSLDO")
7842 /* Now check for identifier@suffix+constant. */
7843 if (*str
== '-' || *str
== '+')
7845 char *orig_line
= input_line_pointer
;
7846 expressionS new_exp
;
7848 input_line_pointer
= str
;
7849 expression (&new_exp
);
7850 if (new_exp
.X_op
== O_constant
)
7852 exp_p
->X_add_number
+= new_exp
.X_add_number
;
7853 str
= input_line_pointer
;
7856 if (&input_line_pointer
!= str_p
)
7857 input_line_pointer
= orig_line
;
7861 return BFD_RELOC_68K_TLS_LDO32
;
7864 return BFD_RELOC_UNUSED
;
7867 /* Handles .long <tls_symbol>+0x8000 debug info.
7868 Clobbers input_line_pointer, checks end-of-line.
7869 Adapted from tc-ppc.c:ppc_elf_cons. */
7871 m68k_elf_cons (int nbytes
/* 4=.long */)
7873 if (is_it_end_of_statement ())
7875 demand_empty_rest_of_line ();
7882 bfd_reloc_code_real_type reloc
;
7885 if (exp
.X_op
== O_symbol
7886 && *input_line_pointer
== '@'
7887 && (reloc
= m68k_elf_suffix (&input_line_pointer
,
7888 &exp
)) != BFD_RELOC_UNUSED
)
7890 reloc_howto_type
*reloc_howto
;
7893 reloc_howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
7894 size
= bfd_get_reloc_size (reloc_howto
);
7898 as_bad (ngettext ("%s relocations do not fit in %u byte",
7899 "%s relocations do not fit in %u bytes",
7901 reloc_howto
->name
, nbytes
);
7908 p
= frag_more (nbytes
);
7910 if (target_big_endian
)
7911 offset
= nbytes
- size
;
7912 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
, size
,
7917 emit_expr (&exp
, (unsigned int) nbytes
);
7919 while (*input_line_pointer
++ == ',');
7921 /* Put terminator back into stream. */
7922 input_line_pointer
--;
7923 demand_empty_rest_of_line ();
7926 /* Parse a .gnu_attribute directive. */
7928 m68k_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED
)
7930 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_GNU
);
7932 /* Check validity of defined m68k tags. */
7933 if (tag
== Tag_GNU_M68K_ABI_FP
)
7937 val
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, tag
);
7939 if (tag
== Tag_GNU_M68K_ABI_FP
&& val
> 2)
7940 as_warn (_("unknown .gnu_attribute value"));
7945 tc_m68k_regname_to_dw2regnum (const char *regname
)
7947 unsigned int regnum
;
7948 static const char *const regnames
[] =
7950 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7951 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7952 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7956 for (regnum
= 0; regnum
< ARRAY_SIZE (regnames
); regnum
++)
7957 if (strcmp (regname
, regnames
[regnum
]) == 0)
7964 tc_m68k_frame_initial_instructions (void)
7966 static int sp_regno
= -1;
7969 sp_regno
= tc_m68k_regname_to_dw2regnum ("sp");
7971 cfi_add_CFA_def_cfa (sp_regno
, -DWARF2_CIE_DATA_ALIGNMENT
);
7972 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, DWARF2_CIE_DATA_ALIGNMENT
);
7975 /* Check and emit error if broken-word handling has failed to fix up a
7976 case-table. This is called from write.c, after doing everything it
7977 knows about how to handle broken words. */
7980 tc_m68k_check_adjusted_broken_word (offsetT new_offset
, struct broken_word
*brokwP
)
7982 if (new_offset
> 32767 || new_offset
< -32768)
7983 as_bad_where (brokwP
->frag
->fr_file
, brokwP
->frag
->fr_line
,
7984 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."),