1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2021 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= false;
86 int mips_flag_pdr
= true;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The name if this is an label. */
147 /* The target label name if this is an branch. */
150 /* The frag that contains the instruction. */
153 /* The offset into FRAG of the first instruction byte. */
156 /* The relocs associated with the instruction, if any. */
159 /* True if this entry cannot be moved from its current position. */
160 unsigned int fixed_p
: 1;
162 /* True if this instruction occurred in a .set noreorder block. */
163 unsigned int noreorder_p
: 1;
165 /* True for mips16 instructions that jump to an absolute address. */
166 unsigned int mips16_absolute_jump_p
: 1;
168 /* True if this instruction is complete. */
169 unsigned int complete_p
: 1;
171 /* True if this instruction is cleared from history by unconditional
173 unsigned int cleared_p
: 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi
= NO_ABI
;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls
= false;
193 /* Whether or not we have code which can be put into a shared
195 static bool mips_in_shared
= true;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
208 <asename>', by command line options, and based on the default
211 /* Whether we are assembling for the mips16 processor. 0 if we are
212 not, 1 if we are, and -1 if the value has not been initialized.
213 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
214 -nomips16 command line options, and the default CPU. */
216 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
217 1 if we are, and -1 if the value has not been initialized. Changed
218 by `.set micromips' and `.set nomicromips', and the -mmicromips
219 and -mno-micromips command line options, and the default CPU. */
221 /* Non-zero if we should not reorder instructions. Changed by `.set
222 reorder' and `.set noreorder'. */
224 /* Non-zero if we should not permit the register designated "assembler
225 temporary" to be used in instructions. The value is the register
226 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
227 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
229 /* Non-zero if we should warn when a macro instruction expands into
230 more than one machine instruction. Changed by `.set nomacro' and
232 int warn_about_macros
;
233 /* Non-zero if we should not move instructions. Changed by `.set
234 move', `.set volatile', `.set nomove', and `.set novolatile'. */
236 /* Non-zero if we should not optimize branches by moving the target
237 of the branch into the delay slot. Actually, we don't perform
238 this optimization anyhow. Changed by `.set bopt' and `.set
241 /* Non-zero if we should not autoextend mips16 instructions.
242 Changed by `.set autoextend' and `.set noautoextend'. */
244 /* True if we should only emit 32-bit microMIPS instructions.
245 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
246 and -mno-insn32 command line options. */
248 /* Restrict general purpose registers and floating point registers
249 to 32 bit. This is initially determined when -mgp32 or -mfp32
250 is passed but can changed if the assembler code uses .set mipsN. */
253 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
254 command line option, and the default CPU. */
256 /* True if ".set sym32" is in effect. */
258 /* True if floating-point operations are not allowed. Changed by .set
259 softfloat or .set hardfloat, by command line options -msoft-float or
260 -mhard-float. The default is false. */
263 /* True if only single-precision floating-point operations are allowed.
264 Changed by .set singlefloat or .set doublefloat, command-line options
265 -msingle-float or -mdouble-float. The default is false. */
268 /* 1 if single-precision operations on odd-numbered registers are
272 /* The set of ASEs that should be enabled for the user specified
273 architecture. This cannot be inferred from 'arch' for all cores
274 as processors only have a unique 'arch' if they add architecture
275 specific instructions (UDI). */
279 /* Specifies whether module level options have been checked yet. */
280 static bool file_mips_opts_checked
= false;
282 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
283 value has not been initialized. Changed by `.nan legacy' and
284 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
285 options, and the default CPU. */
286 static int mips_nan2008
= -1;
288 /* This is the struct we use to hold the module level set of options.
289 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
290 fp fields to -1 to indicate that they have not been initialized. */
292 static struct mips_set_options file_mips_opts
=
294 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
295 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
296 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ false,
297 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ false,
298 /* soft_float */ false, /* single_float */ false, /* oddspreg */ -1,
302 /* This is similar to file_mips_opts, but for the current set of options. */
304 static struct mips_set_options mips_opts
=
306 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
307 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
308 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ false,
309 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ false,
310 /* soft_float */ false, /* single_float */ false, /* oddspreg */ -1,
314 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
315 static unsigned int file_ase_explicit
;
317 /* These variables are filled in with the masks of registers used.
318 The object format code reads them and puts them in the appropriate
320 unsigned long mips_gprmask
;
321 unsigned long mips_cprmask
[4];
323 /* True if any MIPS16 code was produced. */
324 static int file_ase_mips16
;
326 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
327 || mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS32R3 \
329 || mips_opts.isa == ISA_MIPS32R5 \
330 || mips_opts.isa == ISA_MIPS64 \
331 || mips_opts.isa == ISA_MIPS64R2 \
332 || mips_opts.isa == ISA_MIPS64R3 \
333 || mips_opts.isa == ISA_MIPS64R5)
335 /* True if any microMIPS code was produced. */
336 static int file_ase_micromips
;
338 /* True if we want to create R_MIPS_JALR for jalr $25. */
340 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
342 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
343 because there's no place for any addend, the only acceptable
344 expression is a bare symbol. */
345 #define MIPS_JALR_HINT_P(EXPR) \
346 (!HAVE_IN_PLACE_ADDENDS \
347 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
350 /* The argument of the -march= flag. The architecture we are assembling. */
351 static const char *mips_arch_string
;
353 /* The argument of the -mtune= flag. The architecture for which we
355 static int mips_tune
= CPU_UNKNOWN
;
356 static const char *mips_tune_string
;
358 /* True when generating 32-bit code for a 64-bit processor. */
359 static int mips_32bitmode
= 0;
361 /* True if the given ABI requires 32-bit registers. */
362 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
364 /* Likewise 64-bit registers. */
365 #define ABI_NEEDS_64BIT_REGS(ABI) \
367 || (ABI) == N64_ABI \
370 #define ISA_IS_R6(ISA) \
371 ((ISA) == ISA_MIPS32R6 \
372 || (ISA) == ISA_MIPS64R6)
374 /* Return true if ISA supports 64 bit wide gp registers. */
375 #define ISA_HAS_64BIT_REGS(ISA) \
376 ((ISA) == ISA_MIPS3 \
377 || (ISA) == ISA_MIPS4 \
378 || (ISA) == ISA_MIPS5 \
379 || (ISA) == ISA_MIPS64 \
380 || (ISA) == ISA_MIPS64R2 \
381 || (ISA) == ISA_MIPS64R3 \
382 || (ISA) == ISA_MIPS64R5 \
383 || (ISA) == ISA_MIPS64R6)
385 /* Return true if ISA supports 64 bit wide float registers. */
386 #define ISA_HAS_64BIT_FPRS(ISA) \
387 ((ISA) == ISA_MIPS3 \
388 || (ISA) == ISA_MIPS4 \
389 || (ISA) == ISA_MIPS5 \
390 || (ISA) == ISA_MIPS32R2 \
391 || (ISA) == ISA_MIPS32R3 \
392 || (ISA) == ISA_MIPS32R5 \
393 || (ISA) == ISA_MIPS32R6 \
394 || (ISA) == ISA_MIPS64 \
395 || (ISA) == ISA_MIPS64R2 \
396 || (ISA) == ISA_MIPS64R3 \
397 || (ISA) == ISA_MIPS64R5 \
398 || (ISA) == ISA_MIPS64R6)
400 /* Return true if ISA supports 64-bit right rotate (dror et al.)
402 #define ISA_HAS_DROR(ISA) \
403 ((ISA) == ISA_MIPS64R2 \
404 || (ISA) == ISA_MIPS64R3 \
405 || (ISA) == ISA_MIPS64R5 \
406 || (ISA) == ISA_MIPS64R6 \
407 || (mips_opts.micromips \
408 && ISA_HAS_64BIT_REGS (ISA)) \
411 /* Return true if ISA supports 32-bit right rotate (ror et al.)
413 #define ISA_HAS_ROR(ISA) \
414 ((ISA) == ISA_MIPS32R2 \
415 || (ISA) == ISA_MIPS32R3 \
416 || (ISA) == ISA_MIPS32R5 \
417 || (ISA) == ISA_MIPS32R6 \
418 || (ISA) == ISA_MIPS64R2 \
419 || (ISA) == ISA_MIPS64R3 \
420 || (ISA) == ISA_MIPS64R5 \
421 || (ISA) == ISA_MIPS64R6 \
422 || (mips_opts.ase & ASE_SMARTMIPS) \
423 || mips_opts.micromips \
426 /* Return true if ISA supports single-precision floats in odd registers. */
427 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
428 (((ISA) == ISA_MIPS32 \
429 || (ISA) == ISA_MIPS32R2 \
430 || (ISA) == ISA_MIPS32R3 \
431 || (ISA) == ISA_MIPS32R5 \
432 || (ISA) == ISA_MIPS32R6 \
433 || (ISA) == ISA_MIPS64 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6 \
438 || (CPU) == CPU_R5900) \
439 && ((CPU) != CPU_GS464 \
440 || (CPU) != CPU_GS464E \
441 || (CPU) != CPU_GS264E))
443 /* Return true if ISA supports move to/from high part of a 64-bit
444 floating-point register. */
445 #define ISA_HAS_MXHC1(ISA) \
446 ((ISA) == ISA_MIPS32R2 \
447 || (ISA) == ISA_MIPS32R3 \
448 || (ISA) == ISA_MIPS32R5 \
449 || (ISA) == ISA_MIPS32R6 \
450 || (ISA) == ISA_MIPS64R2 \
451 || (ISA) == ISA_MIPS64R3 \
452 || (ISA) == ISA_MIPS64R5 \
453 || (ISA) == ISA_MIPS64R6)
455 /* Return true if ISA supports legacy NAN. */
456 #define ISA_HAS_LEGACY_NAN(ISA) \
457 ((ISA) == ISA_MIPS1 \
458 || (ISA) == ISA_MIPS2 \
459 || (ISA) == ISA_MIPS3 \
460 || (ISA) == ISA_MIPS4 \
461 || (ISA) == ISA_MIPS5 \
462 || (ISA) == ISA_MIPS32 \
463 || (ISA) == ISA_MIPS32R2 \
464 || (ISA) == ISA_MIPS32R3 \
465 || (ISA) == ISA_MIPS32R5 \
466 || (ISA) == ISA_MIPS64 \
467 || (ISA) == ISA_MIPS64R2 \
468 || (ISA) == ISA_MIPS64R3 \
469 || (ISA) == ISA_MIPS64R5)
472 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
477 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
481 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
483 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
485 /* True if relocations are stored in-place. */
486 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
488 /* The ABI-derived address size. */
489 #define HAVE_64BIT_ADDRESSES \
490 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
491 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
493 /* The size of symbolic constants (i.e., expressions of the form
494 "SYMBOL" or "SYMBOL + OFFSET"). */
495 #define HAVE_32BIT_SYMBOLS \
496 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
497 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
499 /* Addresses are loaded in different ways, depending on the address size
500 in use. The n32 ABI Documentation also mandates the use of additions
501 with overflow checking, but existing implementations don't follow it. */
502 #define ADDRESS_ADD_INSN \
503 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
505 #define ADDRESS_ADDI_INSN \
506 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
508 #define ADDRESS_LOAD_INSN \
509 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
511 #define ADDRESS_STORE_INSN \
512 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
514 /* Return true if the given CPU supports the MIPS16 ASE. */
515 #define CPU_HAS_MIPS16(cpu) \
516 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
517 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
519 /* Return true if the given CPU supports the microMIPS ASE. */
520 #define CPU_HAS_MICROMIPS(cpu) 0
522 /* True if CPU has a dror instruction. */
523 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
525 /* True if CPU has a ror instruction. */
526 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
528 /* True if CPU is in the Octeon family. */
529 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
530 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
532 /* True if CPU has seq/sne and seqi/snei instructions. */
533 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
535 /* True, if CPU has support for ldc1 and sdc1. */
536 #define CPU_HAS_LDC1_SDC1(CPU) \
537 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
539 /* True if mflo and mfhi can be immediately followed by instructions
540 which write to the HI and LO registers.
542 According to MIPS specifications, MIPS ISAs I, II, and III need
543 (at least) two instructions between the reads of HI/LO and
544 instructions which write them, and later ISAs do not. Contradicting
545 the MIPS specifications, some MIPS IV processor user manuals (e.g.
546 the UM for the NEC Vr5000) document needing the instructions between
547 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
548 MIPS64 and later ISAs to have the interlocks, plus any specific
549 earlier-ISA CPUs for which CPU documentation declares that the
550 instructions are really interlocked. */
551 #define hilo_interlocks \
552 (mips_opts.isa == ISA_MIPS32 \
553 || mips_opts.isa == ISA_MIPS32R2 \
554 || mips_opts.isa == ISA_MIPS32R3 \
555 || mips_opts.isa == ISA_MIPS32R5 \
556 || mips_opts.isa == ISA_MIPS32R6 \
557 || mips_opts.isa == ISA_MIPS64 \
558 || mips_opts.isa == ISA_MIPS64R2 \
559 || mips_opts.isa == ISA_MIPS64R3 \
560 || mips_opts.isa == ISA_MIPS64R5 \
561 || mips_opts.isa == ISA_MIPS64R6 \
562 || mips_opts.arch == CPU_R4010 \
563 || mips_opts.arch == CPU_R5900 \
564 || mips_opts.arch == CPU_R10000 \
565 || mips_opts.arch == CPU_R12000 \
566 || mips_opts.arch == CPU_R14000 \
567 || mips_opts.arch == CPU_R16000 \
568 || mips_opts.arch == CPU_RM7000 \
569 || mips_opts.arch == CPU_VR5500 \
570 || mips_opts.micromips \
573 /* Whether the processor uses hardware interlocks to protect reads
574 from the GPRs after they are loaded from memory, and thus does not
575 require nops to be inserted. This applies to instructions marked
576 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
577 level I and microMIPS mode instructions are always interlocked. */
578 #define gpr_interlocks \
579 (mips_opts.isa != ISA_MIPS1 \
580 || mips_opts.arch == CPU_R3900 \
581 || mips_opts.arch == CPU_R5900 \
582 || mips_opts.micromips \
585 /* Whether the processor uses hardware interlocks to avoid delays
586 required by coprocessor instructions, and thus does not require
587 nops to be inserted. This applies to instructions marked
588 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
589 instructions marked INSN_WRITE_COND_CODE and ones marked
590 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
591 levels I, II, and III and microMIPS mode instructions are always
593 /* Itbl support may require additional care here. */
594 #define cop_interlocks \
595 ((mips_opts.isa != ISA_MIPS1 \
596 && mips_opts.isa != ISA_MIPS2 \
597 && mips_opts.isa != ISA_MIPS3) \
598 || mips_opts.arch == CPU_R4300 \
599 || mips_opts.micromips \
602 /* Whether the processor uses hardware interlocks to protect reads
603 from coprocessor registers after they are loaded from memory, and
604 thus does not require nops to be inserted. This applies to
605 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
606 requires at MIPS ISA level I and microMIPS mode instructions are
607 always interlocked. */
608 #define cop_mem_interlocks \
609 (mips_opts.isa != ISA_MIPS1 \
610 || mips_opts.micromips \
613 /* Is this a mfhi or mflo instruction? */
614 #define MF_HILO_INSN(PINFO) \
615 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
617 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
618 has been selected. This implies, in particular, that addresses of text
619 labels have their LSB set. */
620 #define HAVE_CODE_COMPRESSION \
621 ((mips_opts.mips16 | mips_opts.micromips) != 0)
623 /* The minimum and maximum signed values that can be stored in a GPR. */
624 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
625 #define GPR_SMIN (-GPR_SMAX - 1)
627 /* MIPS PIC level. */
629 enum mips_pic_level mips_pic
;
631 /* 1 if we should generate 32 bit offsets from the $gp register in
632 SVR4_PIC mode. Currently has no meaning in other modes. */
633 static int mips_big_got
= 0;
635 /* 1 if trap instructions should used for overflow rather than break
637 static int mips_trap
= 0;
639 /* 1 if double width floating point constants should not be constructed
640 by assembling two single width halves into two single width floating
641 point registers which just happen to alias the double width destination
642 register. On some architectures this aliasing can be disabled by a bit
643 in the status register, and the setting of this bit cannot be determined
644 automatically at assemble time. */
645 static int mips_disable_float_construction
;
647 /* Non-zero if any .set noreorder directives were used. */
649 static int mips_any_noreorder
;
651 /* Non-zero if nops should be inserted when the register referenced in
652 an mfhi/mflo instruction is read in the next two instructions. */
653 static int mips_7000_hilo_fix
;
655 /* The size of objects in the small data section. */
656 static unsigned int g_switch_value
= 8;
657 /* Whether the -G option was used. */
658 static int g_switch_seen
= 0;
663 /* If we can determine in advance that GP optimization won't be
664 possible, we can skip the relaxation stuff that tries to produce
665 GP-relative references. This makes delay slot optimization work
668 This function can only provide a guess, but it seems to work for
669 gcc output. It needs to guess right for gcc, otherwise gcc
670 will put what it thinks is a GP-relative instruction in a branch
673 I don't know if a fix is needed for the SVR4_PIC mode. I've only
674 fixed it for the non-PIC mode. KR 95/04/07 */
675 static int nopic_need_relax (symbolS
*, int);
677 /* Handle of the OPCODE hash table. */
678 static htab_t op_hash
= NULL
;
680 /* The opcode hash table we use for the mips16. */
681 static htab_t mips16_op_hash
= NULL
;
683 /* The opcode hash table we use for the microMIPS ASE. */
684 static htab_t micromips_op_hash
= NULL
;
686 /* This array holds the chars that always start a comment. If the
687 pre-processor is disabled, these aren't very useful. */
688 const char comment_chars
[] = "#";
690 /* This array holds the chars that only start a comment at the beginning of
691 a line. If the line seems to have the form '# 123 filename'
692 .line and .file directives will appear in the pre-processed output. */
693 /* Note that input_file.c hand checks for '#' at the beginning of the
694 first line of the input file. This is because the compiler outputs
695 #NO_APP at the beginning of its output. */
696 /* Also note that C style comments are always supported. */
697 const char line_comment_chars
[] = "#";
699 /* This array holds machine specific line separator characters. */
700 const char line_separator_chars
[] = ";";
702 /* Chars that can be used to separate mant from exp in floating point nums. */
703 const char EXP_CHARS
[] = "eE";
705 /* Chars that mean this number is a floating point constant.
708 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
710 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
711 changed in read.c . Ideally it shouldn't have to know about it at all,
712 but nothing is ideal around here. */
714 /* Types of printf format used for instruction-related error messages.
715 "I" means int ("%d") and "S" means string ("%s"). */
716 enum mips_insn_error_format
723 /* Information about an error that was found while assembling the current
725 struct mips_insn_error
727 /* We sometimes need to match an instruction against more than one
728 opcode table entry. Errors found during this matching are reported
729 against a particular syntactic argument rather than against the
730 instruction as a whole. We grade these messages so that errors
731 against argument N have a greater priority than an error against
732 any argument < N, since the former implies that arguments up to N
733 were acceptable and that the opcode entry was therefore a closer match.
734 If several matches report an error against the same argument,
735 we only use that error if it is the same in all cases.
737 min_argnum is the minimum argument number for which an error message
738 should be accepted. It is 0 if MSG is against the instruction as
742 /* The printf()-style message, including its format and arguments. */
743 enum mips_insn_error_format format
;
752 /* The error that should be reported for the current instruction. */
753 static struct mips_insn_error insn_error
;
755 static int auto_align
= 1;
757 /* When outputting SVR4 PIC code, the assembler needs to know the
758 offset in the stack frame from which to restore the $gp register.
759 This is set by the .cprestore pseudo-op, and saved in this
761 static offsetT mips_cprestore_offset
= -1;
763 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
764 more optimizations, it can use a register value instead of a memory-saved
765 offset and even an other register than $gp as global pointer. */
766 static offsetT mips_cpreturn_offset
= -1;
767 static int mips_cpreturn_register
= -1;
768 static int mips_gp_register
= GP
;
769 static int mips_gprel_offset
= 0;
771 /* Whether mips_cprestore_offset has been set in the current function
772 (or whether it has already been warned about, if not). */
773 static int mips_cprestore_valid
= 0;
775 /* This is the register which holds the stack frame, as set by the
776 .frame pseudo-op. This is needed to implement .cprestore. */
777 static int mips_frame_reg
= SP
;
779 /* Whether mips_frame_reg has been set in the current function
780 (or whether it has already been warned about, if not). */
781 static int mips_frame_reg_valid
= 0;
783 /* To output NOP instructions correctly, we need to keep information
784 about the previous two instructions. */
786 /* Whether we are optimizing. The default value of 2 means to remove
787 unneeded NOPs and swap branch instructions when possible. A value
788 of 1 means to not swap branches. A value of 0 means to always
790 static int mips_optimize
= 2;
792 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
793 equivalent to seeing no -g option at all. */
794 static int mips_debug
= 0;
796 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
797 #define MAX_VR4130_NOPS 4
799 /* The maximum number of NOPs needed to fill delay slots. */
800 #define MAX_DELAY_NOPS 2
802 /* The maximum number of NOPs needed for any purpose. */
805 /* The maximum range of context length of ll/sc. */
806 #define MAX_LLSC_RANGE 20
808 /* A list of previous instructions, with index 0 being the most recent.
809 We need to look back MAX_NOPS instructions when filling delay slots
810 or working around processor errata. We need to look back one
811 instruction further if we're thinking about using history[0] to
812 fill a branch delay slot. */
813 static struct mips_cl_insn history
[1 + MAX_NOPS
+ MAX_LLSC_RANGE
];
815 /* The maximum number of LABELS detect for the same address. */
816 #define MAX_LABELS_SAME 10
818 /* Arrays of operands for each instruction. */
819 #define MAX_OPERANDS 6
820 struct mips_operand_array
822 const struct mips_operand
*operand
[MAX_OPERANDS
];
824 static struct mips_operand_array
*mips_operands
;
825 static struct mips_operand_array
*mips16_operands
;
826 static struct mips_operand_array
*micromips_operands
;
828 /* Nop instructions used by emit_nop. */
829 static struct mips_cl_insn nop_insn
;
830 static struct mips_cl_insn mips16_nop_insn
;
831 static struct mips_cl_insn micromips_nop16_insn
;
832 static struct mips_cl_insn micromips_nop32_insn
;
834 /* Sync instructions used by insert sync. */
835 static struct mips_cl_insn sync_insn
;
837 /* The appropriate nop for the current mode. */
838 #define NOP_INSN (mips_opts.mips16 \
840 : (mips_opts.micromips \
841 ? (mips_opts.insn32 \
842 ? µmips_nop32_insn \
843 : µmips_nop16_insn) \
846 /* The size of NOP_INSN in bytes. */
847 #define NOP_INSN_SIZE ((mips_opts.mips16 \
848 || (mips_opts.micromips && !mips_opts.insn32)) \
851 /* If this is set, it points to a frag holding nop instructions which
852 were inserted before the start of a noreorder section. If those
853 nops turn out to be unnecessary, the size of the frag can be
855 static fragS
*prev_nop_frag
;
857 /* The number of nop instructions we created in prev_nop_frag. */
858 static int prev_nop_frag_holds
;
860 /* The number of nop instructions that we know we need in
862 static int prev_nop_frag_required
;
864 /* The number of instructions we've seen since prev_nop_frag. */
865 static int prev_nop_frag_since
;
867 /* Relocations against symbols are sometimes done in two parts, with a HI
868 relocation and a LO relocation. Each relocation has only 16 bits of
869 space to store an addend. This means that in order for the linker to
870 handle carries correctly, it must be able to locate both the HI and
871 the LO relocation. This means that the relocations must appear in
872 order in the relocation table.
874 In order to implement this, we keep track of each unmatched HI
875 relocation. We then sort them so that they immediately precede the
876 corresponding LO relocation. */
881 struct mips_hi_fixup
*next
;
884 /* The section this fixup is in. */
888 /* The list of unmatched HI relocs. */
890 static struct mips_hi_fixup
*mips_hi_fixup_list
;
892 /* Map mips16 register numbers to normal MIPS register numbers. */
894 static const unsigned int mips16_to_32_reg_map
[] =
896 16, 17, 2, 3, 4, 5, 6, 7
899 /* Map microMIPS register numbers to normal MIPS register numbers. */
901 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
903 /* The microMIPS registers with type h. */
904 static const unsigned int micromips_to_32_reg_h_map1
[] =
906 5, 5, 6, 4, 4, 4, 4, 4
908 static const unsigned int micromips_to_32_reg_h_map2
[] =
910 6, 7, 7, 21, 22, 5, 6, 7
913 /* The microMIPS registers with type m. */
914 static const unsigned int micromips_to_32_reg_m_map
[] =
916 0, 17, 2, 3, 16, 18, 19, 20
919 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
921 /* Classifies the kind of instructions we're interested in when
922 implementing -mfix-vr4120. */
923 enum fix_vr4120_class
931 NUM_FIX_VR4120_CLASSES
934 /* ...likewise -mfix-loongson2f-jump. */
935 static bool mips_fix_loongson2f_jump
;
937 /* ...likewise -mfix-loongson2f-nop. */
938 static bool mips_fix_loongson2f_nop
;
940 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
941 static bool mips_fix_loongson2f
;
943 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
944 there must be at least one other instruction between an instruction
945 of type X and an instruction of type Y. */
946 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
948 /* True if -mfix-vr4120 is in force. */
949 static int mips_fix_vr4120
;
951 /* ...likewise -mfix-vr4130. */
952 static int mips_fix_vr4130
;
954 /* ...likewise -mfix-24k. */
955 static int mips_fix_24k
;
957 /* ...likewise -mfix-rm7000 */
958 static int mips_fix_rm7000
;
960 /* ...likewise -mfix-cn63xxp1 */
961 static bool mips_fix_cn63xxp1
;
963 /* ...likewise -mfix-r5900 */
964 static bool mips_fix_r5900
;
965 static bool mips_fix_r5900_explicit
;
967 /* ...likewise -mfix-loongson3-llsc. */
968 static bool mips_fix_loongson3_llsc
= DEFAULT_MIPS_FIX_LOONGSON3_LLSC
;
970 /* We don't relax branches by default, since this causes us to expand
971 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
972 fail to compute the offset before expanding the macro to the most
973 efficient expansion. */
975 static int mips_relax_branch
;
977 /* TRUE if checks are suppressed for invalid branches between ISA modes.
978 Needed for broken assembly produced by some GCC versions and some
979 sloppy code out there, where branches to data labels are present. */
980 static bool mips_ignore_branch_isa
;
982 /* The expansion of many macros depends on the type of symbol that
983 they refer to. For example, when generating position-dependent code,
984 a macro that refers to a symbol may have two different expansions,
985 one which uses GP-relative addresses and one which uses absolute
986 addresses. When generating SVR4-style PIC, a macro may have
987 different expansions for local and global symbols.
989 We handle these situations by generating both sequences and putting
990 them in variant frags. In position-dependent code, the first sequence
991 will be the GP-relative one and the second sequence will be the
992 absolute one. In SVR4 PIC, the first sequence will be for global
993 symbols and the second will be for local symbols.
995 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
996 SECOND are the lengths of the two sequences in bytes. These fields
997 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
998 the subtype has the following flags:
1001 Set if generating PIC code.
1004 Set if it has been decided that we should use the second
1005 sequence instead of the first.
1008 Set in the first variant frag if the macro's second implementation
1009 is longer than its first. This refers to the macro as a whole,
1010 not an individual relaxation.
1013 Set in the first variant frag if the macro appeared in a .set nomacro
1014 block and if one alternative requires a warning but the other does not.
1017 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
1020 RELAX_DELAY_SLOT_16BIT
1021 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1024 RELAX_DELAY_SLOT_SIZE_FIRST
1025 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1026 the macro is of the wrong size for the branch delay slot.
1028 RELAX_DELAY_SLOT_SIZE_SECOND
1029 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1030 the macro is of the wrong size for the branch delay slot.
1032 The frag's "opcode" points to the first fixup for relaxable code.
1034 Relaxable macros are generated using a sequence such as:
1036 relax_start (SYMBOL);
1037 ... generate first expansion ...
1039 ... generate second expansion ...
1042 The code and fixups for the unwanted alternative are discarded
1043 by md_convert_frag. */
1044 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1045 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1047 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1048 #define RELAX_SECOND(X) ((X) & 0xff)
1049 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1050 #define RELAX_USE_SECOND 0x20000
1051 #define RELAX_SECOND_LONGER 0x40000
1052 #define RELAX_NOMACRO 0x80000
1053 #define RELAX_DELAY_SLOT 0x100000
1054 #define RELAX_DELAY_SLOT_16BIT 0x200000
1055 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1056 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1058 /* Branch without likely bit. If label is out of range, we turn:
1060 beq reg1, reg2, label
1070 with the following opcode replacements:
1077 bltzal <-> bgezal (with jal label instead of j label)
1079 Even though keeping the delay slot instruction in the delay slot of
1080 the branch would be more efficient, it would be very tricky to do
1081 correctly, because we'd have to introduce a variable frag *after*
1082 the delay slot instruction, and expand that instead. Let's do it
1083 the easy way for now, even if the branch-not-taken case now costs
1084 one additional instruction. Out-of-range branches are not supposed
1085 to be common, anyway.
1087 Branch likely. If label is out of range, we turn:
1089 beql reg1, reg2, label
1090 delay slot (annulled if branch not taken)
1099 delay slot (executed only if branch taken)
1102 It would be possible to generate a shorter sequence by losing the
1103 likely bit, generating something like:
1108 delay slot (executed only if branch taken)
1120 bltzall -> bgezal (with jal label instead of j label)
1121 bgezall -> bltzal (ditto)
1124 but it's not clear that it would actually improve performance. */
1125 #define RELAX_BRANCH_ENCODE(at, pic, \
1126 uncond, likely, link, toofar) \
1127 ((relax_substateT) \
1130 | ((pic) ? 0x20 : 0) \
1131 | ((toofar) ? 0x40 : 0) \
1132 | ((link) ? 0x80 : 0) \
1133 | ((likely) ? 0x100 : 0) \
1134 | ((uncond) ? 0x200 : 0)))
1135 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1136 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1137 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1138 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1139 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1140 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1141 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1143 /* For mips16 code, we use an entirely different form of relaxation.
1144 mips16 supports two versions of most instructions which take
1145 immediate values: a small one which takes some small value, and a
1146 larger one which takes a 16 bit value. Since branches also follow
1147 this pattern, relaxing these values is required.
1149 We can assemble both mips16 and normal MIPS code in a single
1150 object. Therefore, we need to support this type of relaxation at
1151 the same time that we support the relaxation described above. We
1152 use the high bit of the subtype field to distinguish these cases.
1154 The information we store for this type of relaxation is the
1155 argument code found in the opcode file for this relocation, whether
1156 the user explicitly requested a small or extended form, and whether
1157 the relocation is in a jump or jal delay slot. That tells us the
1158 size of the value, and how it should be stored. We also store
1159 whether the fragment is considered to be extended or not. We also
1160 store whether this is known to be a branch to a different section,
1161 whether we have tried to relax this frag yet, and whether we have
1162 ever extended a PC relative fragment because of a shift count. */
1163 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1168 | ((e2) ? 0x100 : 0) \
1169 | ((pic) ? 0x200 : 0) \
1170 | ((sym32) ? 0x400 : 0) \
1171 | ((nomacro) ? 0x800 : 0) \
1172 | ((small) ? 0x1000 : 0) \
1173 | ((ext) ? 0x2000 : 0) \
1174 | ((dslot) ? 0x4000 : 0) \
1175 | ((jal_dslot) ? 0x8000 : 0))
1177 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1178 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1179 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1180 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1181 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1182 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1183 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1184 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1185 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1186 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1188 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1189 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1190 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1191 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1192 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1193 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1194 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1195 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1196 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1198 /* For microMIPS code, we use relaxation similar to one we use for
1199 MIPS16 code. Some instructions that take immediate values support
1200 two encodings: a small one which takes some small value, and a
1201 larger one which takes a 16 bit value. As some branches also follow
1202 this pattern, relaxing these values is required.
1204 We can assemble both microMIPS and normal MIPS code in a single
1205 object. Therefore, we need to support this type of relaxation at
1206 the same time that we support the relaxation described above. We
1207 use one of the high bits of the subtype field to distinguish these
1210 The information we store for this type of relaxation is the argument
1211 code found in the opcode file for this relocation, the register
1212 selected as the assembler temporary, whether in the 32-bit
1213 instruction mode, whether the branch is unconditional, whether it is
1214 compact, whether there is no delay-slot instruction available to fill
1215 in, whether it stores the link address implicitly in $ra, whether
1216 relaxation of out-of-range 32-bit branches to a sequence of
1217 instructions is enabled, and whether the displacement of a branch is
1218 too large to fit as an immediate argument of a 16-bit and a 32-bit
1219 branch, respectively. */
1220 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1221 uncond, compact, link, nods, \
1222 relax32, toofar16, toofar32) \
1225 | (((at) & 0x1f) << 8) \
1226 | ((insn32) ? 0x2000 : 0) \
1227 | ((pic) ? 0x4000 : 0) \
1228 | ((uncond) ? 0x8000 : 0) \
1229 | ((compact) ? 0x10000 : 0) \
1230 | ((link) ? 0x20000 : 0) \
1231 | ((nods) ? 0x40000 : 0) \
1232 | ((relax32) ? 0x80000 : 0) \
1233 | ((toofar16) ? 0x100000 : 0) \
1234 | ((toofar32) ? 0x200000 : 0))
1235 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1236 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1237 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1238 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1239 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1240 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1241 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1242 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1243 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1244 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1246 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1247 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1248 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1249 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1250 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1251 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1253 /* Sign-extend 16-bit value X. */
1254 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1256 /* Is the given value a sign-extended 32-bit value? */
1257 #define IS_SEXT_32BIT_NUM(x) \
1258 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1259 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1261 /* Is the given value a sign-extended 16-bit value? */
1262 #define IS_SEXT_16BIT_NUM(x) \
1263 (((x) &~ (offsetT) 0x7fff) == 0 \
1264 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1266 /* Is the given value a sign-extended 12-bit value? */
1267 #define IS_SEXT_12BIT_NUM(x) \
1268 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1270 /* Is the given value a sign-extended 9-bit value? */
1271 #define IS_SEXT_9BIT_NUM(x) \
1272 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1274 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1275 #define IS_ZEXT_32BIT_NUM(x) \
1276 (((x) &~ (offsetT) 0xffffffff) == 0 \
1277 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1279 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1281 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1282 (((STRUCT) >> (SHIFT)) & (MASK))
1284 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1285 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1287 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1288 : EXTRACT_BITS ((INSN).insn_opcode, \
1289 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1290 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1291 EXTRACT_BITS ((INSN).insn_opcode, \
1292 MIPS16OP_MASK_##FIELD, \
1293 MIPS16OP_SH_##FIELD)
1295 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1296 #define MIPS16_EXTEND (0xf000U << 16)
1298 /* Whether or not we are emitting a branch-likely macro. */
1299 static bool emit_branch_likely_macro
= false;
1301 /* Global variables used when generating relaxable macros. See the
1302 comment above RELAX_ENCODE for more details about how relaxation
1305 /* 0 if we're not emitting a relaxable macro.
1306 1 if we're emitting the first of the two relaxation alternatives.
1307 2 if we're emitting the second alternative. */
1310 /* The first relaxable fixup in the current frag. (In other words,
1311 the first fixup that refers to relaxable code.) */
1314 /* sizes[0] says how many bytes of the first alternative are stored in
1315 the current frag. Likewise sizes[1] for the second alternative. */
1316 unsigned int sizes
[2];
1318 /* The symbol on which the choice of sequence depends. */
1322 /* Global variables used to decide whether a macro needs a warning. */
1324 /* True if the macro is in a branch delay slot. */
1327 /* Set to the length in bytes required if the macro is in a delay slot
1328 that requires a specific length of instruction, otherwise zero. */
1329 unsigned int delay_slot_length
;
1331 /* For relaxable macros, sizes[0] is the length of the first alternative
1332 in bytes and sizes[1] is the length of the second alternative.
1333 For non-relaxable macros, both elements give the length of the
1335 unsigned int sizes
[2];
1337 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1338 instruction of the first alternative in bytes and first_insn_sizes[1]
1339 is the length of the first instruction of the second alternative.
1340 For non-relaxable macros, both elements give the length of the first
1341 instruction in bytes.
1343 Set to zero if we haven't yet seen the first instruction. */
1344 unsigned int first_insn_sizes
[2];
1346 /* For relaxable macros, insns[0] is the number of instructions for the
1347 first alternative and insns[1] is the number of instructions for the
1350 For non-relaxable macros, both elements give the number of
1351 instructions for the macro. */
1352 unsigned int insns
[2];
1354 /* The first variant frag for this macro. */
1356 } mips_macro_warning
;
1358 /* Prototypes for static functions. */
1360 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1362 static void append_insn
1363 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1365 static void mips_no_prev_insn (void);
1366 static void macro_build (expressionS
*, const char *, const char *, ...);
1367 static void mips16_macro_build
1368 (expressionS
*, const char *, const char *, va_list *);
1369 static void load_register (int, expressionS
*, int);
1370 static void macro_start (void);
1371 static void macro_end (void);
1372 static void macro (struct mips_cl_insn
*ip
, char *str
);
1373 static void mips16_macro (struct mips_cl_insn
* ip
);
1374 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1375 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1376 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1377 static void mips16_immed
1378 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1379 unsigned int, unsigned long *);
1380 static size_t my_getSmallExpression
1381 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1382 static void my_getExpression (expressionS
*, char *);
1383 static void s_align (int);
1384 static void s_change_sec (int);
1385 static void s_change_section (int);
1386 static void s_cons (int);
1387 static void s_float_cons (int);
1388 static void s_mips_globl (int);
1389 static void s_option (int);
1390 static void s_mipsset (int);
1391 static void s_abicalls (int);
1392 static void s_cpload (int);
1393 static void s_cpsetup (int);
1394 static void s_cplocal (int);
1395 static void s_cprestore (int);
1396 static void s_cpreturn (int);
1397 static void s_dtprelword (int);
1398 static void s_dtpreldword (int);
1399 static void s_tprelword (int);
1400 static void s_tpreldword (int);
1401 static void s_gpvalue (int);
1402 static void s_gpword (int);
1403 static void s_gpdword (int);
1404 static void s_ehword (int);
1405 static void s_cpadd (int);
1406 static void s_insn (int);
1407 static void s_nan (int);
1408 static void s_module (int);
1409 static void s_mips_ent (int);
1410 static void s_mips_end (int);
1411 static void s_mips_frame (int);
1412 static void s_mips_mask (int reg_type
);
1413 static void s_mips_stab (int);
1414 static void s_mips_weakext (int);
1415 static void s_mips_file (int);
1416 static void s_mips_loc (int);
1417 static bool pic_need_relax (symbolS
*);
1418 static int relaxed_branch_length (fragS
*, asection
*, int);
1419 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1420 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1421 static void file_mips_check_options (void);
1423 /* Table and functions used to map between CPU/ISA names, and
1424 ISA levels, and CPU numbers. */
1426 struct mips_cpu_info
1428 const char *name
; /* CPU or ISA name. */
1429 int flags
; /* MIPS_CPU_* flags. */
1430 int ase
; /* Set of ASEs implemented by the CPU. */
1431 int isa
; /* ISA level. */
1432 int cpu
; /* CPU number (default CPU if ISA). */
1435 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1437 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1438 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1439 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1441 /* Command-line options. */
1442 const char *md_shortopts
= "O::g::G:";
1446 OPTION_MARCH
= OPTION_MD_BASE
,
1478 OPTION_NO_SMARTMIPS
,
1488 OPTION_NO_MICROMIPS
,
1503 OPTION_M7000_HILO_FIX
,
1504 OPTION_MNO_7000_HILO_FIX
,
1508 OPTION_NO_FIX_RM7000
,
1509 OPTION_FIX_LOONGSON3_LLSC
,
1510 OPTION_NO_FIX_LOONGSON3_LLSC
,
1511 OPTION_FIX_LOONGSON2F_JUMP
,
1512 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1513 OPTION_FIX_LOONGSON2F_NOP
,
1514 OPTION_NO_FIX_LOONGSON2F_NOP
,
1516 OPTION_NO_FIX_VR4120
,
1518 OPTION_NO_FIX_VR4130
,
1519 OPTION_FIX_CN63XXP1
,
1520 OPTION_NO_FIX_CN63XXP1
,
1522 OPTION_NO_FIX_R5900
,
1529 OPTION_CONSTRUCT_FLOATS
,
1530 OPTION_NO_CONSTRUCT_FLOATS
,
1534 OPTION_RELAX_BRANCH
,
1535 OPTION_NO_RELAX_BRANCH
,
1536 OPTION_IGNORE_BRANCH_ISA
,
1537 OPTION_NO_IGNORE_BRANCH_ISA
,
1546 OPTION_SINGLE_FLOAT
,
1547 OPTION_DOUBLE_FLOAT
,
1560 OPTION_MVXWORKS_PIC
,
1563 OPTION_NO_ODD_SPREG
,
1566 OPTION_LOONGSON_MMI
,
1567 OPTION_NO_LOONGSON_MMI
,
1568 OPTION_LOONGSON_CAM
,
1569 OPTION_NO_LOONGSON_CAM
,
1570 OPTION_LOONGSON_EXT
,
1571 OPTION_NO_LOONGSON_EXT
,
1572 OPTION_LOONGSON_EXT2
,
1573 OPTION_NO_LOONGSON_EXT2
,
1577 struct option md_longopts
[] =
1579 /* Options which specify architecture. */
1580 {"march", required_argument
, NULL
, OPTION_MARCH
},
1581 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1582 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1583 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1584 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1585 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1586 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1587 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1588 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1589 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1590 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1591 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1592 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1593 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1594 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1595 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1596 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1597 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1599 /* Options which specify Application Specific Extensions (ASEs). */
1600 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1601 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1602 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1603 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1604 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1605 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1606 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1607 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1608 {"mmt", no_argument
, NULL
, OPTION_MT
},
1609 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1610 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1611 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1612 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1613 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1614 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1615 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1616 {"meva", no_argument
, NULL
, OPTION_EVA
},
1617 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1618 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1619 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1620 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1621 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1622 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1623 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1624 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1625 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1626 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1627 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1628 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1629 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1630 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1631 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1632 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1633 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1634 {"mloongson-mmi", no_argument
, NULL
, OPTION_LOONGSON_MMI
},
1635 {"mno-loongson-mmi", no_argument
, NULL
, OPTION_NO_LOONGSON_MMI
},
1636 {"mloongson-cam", no_argument
, NULL
, OPTION_LOONGSON_CAM
},
1637 {"mno-loongson-cam", no_argument
, NULL
, OPTION_NO_LOONGSON_CAM
},
1638 {"mloongson-ext", no_argument
, NULL
, OPTION_LOONGSON_EXT
},
1639 {"mno-loongson-ext", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT
},
1640 {"mloongson-ext2", no_argument
, NULL
, OPTION_LOONGSON_EXT2
},
1641 {"mno-loongson-ext2", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT2
},
1643 /* Old-style architecture options. Don't add more of these. */
1644 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1645 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1646 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1647 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1648 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1649 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1650 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1651 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1653 /* Options which enable bug fixes. */
1654 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1655 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1656 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1657 {"mfix-loongson3-llsc", no_argument
, NULL
, OPTION_FIX_LOONGSON3_LLSC
},
1658 {"mno-fix-loongson3-llsc", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON3_LLSC
},
1659 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1660 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1661 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1662 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1663 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1664 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1665 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1666 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1667 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1668 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1669 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1670 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1671 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1672 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1673 {"mfix-r5900", no_argument
, NULL
, OPTION_FIX_R5900
},
1674 {"mno-fix-r5900", no_argument
, NULL
, OPTION_NO_FIX_R5900
},
1676 /* Miscellaneous options. */
1677 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1678 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1679 {"break", no_argument
, NULL
, OPTION_BREAK
},
1680 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1681 {"EB", no_argument
, NULL
, OPTION_EB
},
1682 {"EL", no_argument
, NULL
, OPTION_EL
},
1683 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1684 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1685 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1686 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1687 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1688 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1689 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1690 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1691 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1692 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1693 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1694 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1695 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1696 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1697 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1698 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1699 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1700 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1701 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1702 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1703 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1704 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1705 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1707 /* Strictly speaking this next option is ELF specific,
1708 but we allow it for other ports as well in order to
1709 make testing easier. */
1710 {"32", no_argument
, NULL
, OPTION_32
},
1712 /* ELF-specific options. */
1713 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1714 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1715 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1716 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1717 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1718 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1719 {"n32", no_argument
, NULL
, OPTION_N32
},
1720 {"64", no_argument
, NULL
, OPTION_64
},
1721 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1722 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1723 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1724 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1725 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1726 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1728 {NULL
, no_argument
, NULL
, 0}
1730 size_t md_longopts_size
= sizeof (md_longopts
);
1732 /* Information about either an Application Specific Extension or an
1733 optional architecture feature that, for simplicity, we treat in the
1734 same way as an ASE. */
1737 /* The name of the ASE, used in both the command-line and .set options. */
1740 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1741 and 64-bit architectures, the flags here refer to the subset that
1742 is available on both. */
1745 /* The ASE_* flag used for instructions that are available on 64-bit
1746 architectures but that are not included in FLAGS. */
1747 unsigned int flags64
;
1749 /* The command-line options that turn the ASE on and off. */
1753 /* The minimum required architecture revisions for MIPS32, MIPS64,
1754 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1757 int micromips32_rev
;
1758 int micromips64_rev
;
1760 /* The architecture where the ASE was removed or -1 if the extension has not
1765 /* A table of all supported ASEs. */
1766 static const struct mips_ase mips_ases
[] = {
1767 { "dsp", ASE_DSP
, ASE_DSP64
,
1768 OPTION_DSP
, OPTION_NO_DSP
,
1772 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1773 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1777 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1778 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1782 { "eva", ASE_EVA
, 0,
1783 OPTION_EVA
, OPTION_NO_EVA
,
1787 { "mcu", ASE_MCU
, 0,
1788 OPTION_MCU
, OPTION_NO_MCU
,
1792 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1793 { "mdmx", ASE_MDMX
, 0,
1794 OPTION_MDMX
, OPTION_NO_MDMX
,
1798 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1799 { "mips3d", ASE_MIPS3D
, 0,
1800 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1805 OPTION_MT
, OPTION_NO_MT
,
1809 { "smartmips", ASE_SMARTMIPS
, 0,
1810 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1814 { "virt", ASE_VIRT
, ASE_VIRT64
,
1815 OPTION_VIRT
, OPTION_NO_VIRT
,
1819 { "msa", ASE_MSA
, ASE_MSA64
,
1820 OPTION_MSA
, OPTION_NO_MSA
,
1824 { "xpa", ASE_XPA
, 0,
1825 OPTION_XPA
, OPTION_NO_XPA
,
1829 { "mips16e2", ASE_MIPS16E2
, 0,
1830 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1834 { "crc", ASE_CRC
, ASE_CRC64
,
1835 OPTION_CRC
, OPTION_NO_CRC
,
1839 { "ginv", ASE_GINV
, 0,
1840 OPTION_GINV
, OPTION_NO_GINV
,
1844 { "loongson-mmi", ASE_LOONGSON_MMI
, 0,
1845 OPTION_LOONGSON_MMI
, OPTION_NO_LOONGSON_MMI
,
1849 { "loongson-cam", ASE_LOONGSON_CAM
, 0,
1850 OPTION_LOONGSON_CAM
, OPTION_NO_LOONGSON_CAM
,
1854 { "loongson-ext", ASE_LOONGSON_EXT
, 0,
1855 OPTION_LOONGSON_EXT
, OPTION_NO_LOONGSON_EXT
,
1859 { "loongson-ext2", ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
, 0,
1860 OPTION_LOONGSON_EXT2
, OPTION_NO_LOONGSON_EXT2
,
1865 /* The set of ASEs that require -mfp64. */
1866 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1868 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1869 static const unsigned int mips_ase_groups
[] = {
1870 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
,
1871 ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
1876 The following pseudo-ops from the Kane and Heinrich MIPS book
1877 should be defined here, but are currently unsupported: .alias,
1878 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1880 The following pseudo-ops from the Kane and Heinrich MIPS book are
1881 specific to the type of debugging information being generated, and
1882 should be defined by the object format: .aent, .begin, .bend,
1883 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1886 The following pseudo-ops from the Kane and Heinrich MIPS book are
1887 not MIPS CPU specific, but are also not specific to the object file
1888 format. This file is probably the best place to define them, but
1889 they are not currently supported: .asm0, .endr, .lab, .struct. */
1891 static const pseudo_typeS mips_pseudo_table
[] =
1893 /* MIPS specific pseudo-ops. */
1894 {"option", s_option
, 0},
1895 {"set", s_mipsset
, 0},
1896 {"rdata", s_change_sec
, 'r'},
1897 {"sdata", s_change_sec
, 's'},
1898 {"livereg", s_ignore
, 0},
1899 {"abicalls", s_abicalls
, 0},
1900 {"cpload", s_cpload
, 0},
1901 {"cpsetup", s_cpsetup
, 0},
1902 {"cplocal", s_cplocal
, 0},
1903 {"cprestore", s_cprestore
, 0},
1904 {"cpreturn", s_cpreturn
, 0},
1905 {"dtprelword", s_dtprelword
, 0},
1906 {"dtpreldword", s_dtpreldword
, 0},
1907 {"tprelword", s_tprelword
, 0},
1908 {"tpreldword", s_tpreldword
, 0},
1909 {"gpvalue", s_gpvalue
, 0},
1910 {"gpword", s_gpword
, 0},
1911 {"gpdword", s_gpdword
, 0},
1912 {"ehword", s_ehword
, 0},
1913 {"cpadd", s_cpadd
, 0},
1914 {"insn", s_insn
, 0},
1916 {"module", s_module
, 0},
1918 /* Relatively generic pseudo-ops that happen to be used on MIPS
1920 {"asciiz", stringer
, 8 + 1},
1921 {"bss", s_change_sec
, 'b'},
1923 {"half", s_cons
, 1},
1924 {"dword", s_cons
, 3},
1925 {"weakext", s_mips_weakext
, 0},
1926 {"origin", s_org
, 0},
1927 {"repeat", s_rept
, 0},
1929 /* For MIPS this is non-standard, but we define it for consistency. */
1930 {"sbss", s_change_sec
, 'B'},
1932 /* These pseudo-ops are defined in read.c, but must be overridden
1933 here for one reason or another. */
1934 {"align", s_align
, 0},
1935 {"byte", s_cons
, 0},
1936 {"data", s_change_sec
, 'd'},
1937 {"double", s_float_cons
, 'd'},
1938 {"float", s_float_cons
, 'f'},
1939 {"globl", s_mips_globl
, 0},
1940 {"global", s_mips_globl
, 0},
1941 {"hword", s_cons
, 1},
1943 {"long", s_cons
, 2},
1944 {"octa", s_cons
, 4},
1945 {"quad", s_cons
, 3},
1946 {"section", s_change_section
, 0},
1947 {"short", s_cons
, 1},
1948 {"single", s_float_cons
, 'f'},
1949 {"stabd", s_mips_stab
, 'd'},
1950 {"stabn", s_mips_stab
, 'n'},
1951 {"stabs", s_mips_stab
, 's'},
1952 {"text", s_change_sec
, 't'},
1953 {"word", s_cons
, 2},
1955 { "extern", ecoff_directive_extern
, 0},
1960 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1962 /* These pseudo-ops should be defined by the object file format.
1963 However, a.out doesn't support them, so we have versions here. */
1964 {"aent", s_mips_ent
, 1},
1965 {"bgnb", s_ignore
, 0},
1966 {"end", s_mips_end
, 0},
1967 {"endb", s_ignore
, 0},
1968 {"ent", s_mips_ent
, 0},
1969 {"file", s_mips_file
, 0},
1970 {"fmask", s_mips_mask
, 'F'},
1971 {"frame", s_mips_frame
, 0},
1972 {"loc", s_mips_loc
, 0},
1973 {"mask", s_mips_mask
, 'R'},
1974 {"verstamp", s_ignore
, 0},
1978 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1979 purpose of the `.dc.a' internal pseudo-op. */
1982 mips_address_bytes (void)
1984 file_mips_check_options ();
1985 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1988 extern void pop_insert (const pseudo_typeS
*);
1991 mips_pop_insert (void)
1993 pop_insert (mips_pseudo_table
);
1994 if (! ECOFF_DEBUGGING
)
1995 pop_insert (mips_nonecoff_pseudo_table
);
1998 /* Symbols labelling the current insn. */
2000 struct insn_label_list
2002 struct insn_label_list
*next
;
2006 static struct insn_label_list
*free_insn_labels
;
2007 #define label_list tc_segment_info_data.labels
2009 static void mips_clear_insn_labels (void);
2010 static void mips_mark_labels (void);
2011 static void mips_compressed_mark_labels (void);
2014 mips_clear_insn_labels (void)
2016 struct insn_label_list
**pl
;
2017 segment_info_type
*si
;
2021 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
2024 si
= seg_info (now_seg
);
2025 *pl
= si
->label_list
;
2026 si
->label_list
= NULL
;
2030 /* Mark instruction labels in MIPS16/microMIPS mode. */
2033 mips_mark_labels (void)
2035 if (HAVE_CODE_COMPRESSION
)
2036 mips_compressed_mark_labels ();
2039 static char *expr_end
;
2041 /* An expression in a macro instruction. This is set by mips_ip and
2042 mips16_ip and when populated is always an O_constant. */
2044 static expressionS imm_expr
;
2046 /* The relocatable field in an instruction and the relocs associated
2047 with it. These variables are used for instructions like LUI and
2048 JAL as well as true offsets. They are also used for address
2049 operands in macros. */
2051 static expressionS offset_expr
;
2052 static bfd_reloc_code_real_type offset_reloc
[3]
2053 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2055 /* This is set to the resulting size of the instruction to be produced
2056 by mips16_ip if an explicit extension is used or by mips_ip if an
2057 explicit size is supplied. */
2059 static unsigned int forced_insn_length
;
2061 /* True if we are assembling an instruction. All dot symbols defined during
2062 this time should be treated as code labels. */
2064 static bool mips_assembling_insn
;
2066 /* The pdr segment for per procedure frame/regmask info. Not used for
2069 static segT pdr_seg
;
2071 /* The default target format to use. */
2073 #if defined (TE_FreeBSD)
2074 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2075 #elif defined (TE_TMIPS)
2076 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2078 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2082 mips_target_format (void)
2084 switch (OUTPUT_FLAVOR
)
2086 case bfd_target_elf_flavour
:
2088 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2089 return (target_big_endian
2090 ? "elf32-bigmips-vxworks"
2091 : "elf32-littlemips-vxworks");
2093 return (target_big_endian
2094 ? (HAVE_64BIT_OBJECTS
2095 ? ELF_TARGET ("elf64-", "big")
2097 ? ELF_TARGET ("elf32-n", "big")
2098 : ELF_TARGET ("elf32-", "big")))
2099 : (HAVE_64BIT_OBJECTS
2100 ? ELF_TARGET ("elf64-", "little")
2102 ? ELF_TARGET ("elf32-n", "little")
2103 : ELF_TARGET ("elf32-", "little"))));
2110 /* Return the ISA revision that is currently in use, or 0 if we are
2111 generating code for MIPS V or below. */
2116 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2119 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2122 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2125 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2128 /* microMIPS implies revision 2 or above. */
2129 if (mips_opts
.micromips
)
2132 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2138 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2141 mips_ase_mask (unsigned int flags
)
2145 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2146 if (flags
& mips_ase_groups
[i
])
2147 flags
|= mips_ase_groups
[i
];
2151 /* Check whether the current ISA supports ASE. Issue a warning if
2155 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2159 static unsigned int warned_isa
;
2160 static unsigned int warned_fp32
;
2162 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2163 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2165 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2166 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2167 && (warned_isa
& ase
->flags
) != ase
->flags
)
2169 warned_isa
|= ase
->flags
;
2170 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2171 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2173 as_warn (_("the %d-bit %s architecture does not support the"
2174 " `%s' extension"), size
, base
, ase
->name
);
2176 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2177 ase
->name
, base
, size
, min_rev
);
2179 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2180 && (warned_isa
& ase
->flags
) != ase
->flags
)
2182 warned_isa
|= ase
->flags
;
2183 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2184 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2185 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2186 ase
->name
, base
, size
, ase
->rem_rev
);
2189 if ((ase
->flags
& FP64_ASES
)
2190 && mips_opts
.fp
!= 64
2191 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2193 warned_fp32
|= ase
->flags
;
2194 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2198 /* Check all enabled ASEs to see whether they are supported by the
2199 chosen architecture. */
2202 mips_check_isa_supports_ases (void)
2204 unsigned int i
, mask
;
2206 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2208 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2209 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2210 mips_check_isa_supports_ase (&mips_ases
[i
]);
2214 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2215 that were affected. */
2218 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2223 mask
= mips_ase_mask (ase
->flags
);
2226 /* Clear combination ASE flags, which need to be recalculated based on
2227 updated regular ASE settings. */
2228 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
| ASE_EVA_R6
);
2231 opts
->ase
|= ase
->flags
;
2233 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2234 instructions which are only valid when both ASEs are enabled.
2235 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2236 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2238 opts
->ase
|= ASE_XPA_VIRT
;
2239 mask
|= ASE_XPA_VIRT
;
2241 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2243 opts
->ase
|= ASE_MIPS16E2_MT
;
2244 mask
|= ASE_MIPS16E2_MT
;
2247 /* The EVA Extension has instructions which are only valid when the R6 ISA
2248 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
2250 if (((opts
->ase
& ASE_EVA
) != 0) && ISA_IS_R6 (opts
->isa
))
2252 opts
->ase
|= ASE_EVA_R6
;
2259 /* Return the ASE called NAME, or null if none. */
2261 static const struct mips_ase
*
2262 mips_lookup_ase (const char *name
)
2266 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2267 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2268 return &mips_ases
[i
];
2272 /* Return the length of a microMIPS instruction in bytes. If bits of
2273 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2274 otherwise it is a 32-bit instruction. */
2276 static inline unsigned int
2277 micromips_insn_length (const struct mips_opcode
*mo
)
2279 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2282 /* Return the length of MIPS16 instruction OPCODE. */
2284 static inline unsigned int
2285 mips16_opcode_length (unsigned long opcode
)
2287 return (opcode
>> 16) == 0 ? 2 : 4;
2290 /* Return the length of instruction INSN. */
2292 static inline unsigned int
2293 insn_length (const struct mips_cl_insn
*insn
)
2295 if (mips_opts
.micromips
)
2296 return micromips_insn_length (insn
->insn_mo
);
2297 else if (mips_opts
.mips16
)
2298 return mips16_opcode_length (insn
->insn_opcode
);
2303 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2306 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2311 insn
->insn_opcode
= mo
->match
;
2314 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2315 insn
->fixp
[i
] = NULL
;
2316 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2317 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2318 insn
->mips16_absolute_jump_p
= 0;
2319 insn
->complete_p
= 0;
2320 insn
->cleared_p
= 0;
2323 /* Get a list of all the operands in INSN. */
2325 static const struct mips_operand_array
*
2326 insn_operands (const struct mips_cl_insn
*insn
)
2328 if (insn
->insn_mo
>= &mips_opcodes
[0]
2329 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2330 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2332 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2333 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2334 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2336 if (insn
->insn_mo
>= µmips_opcodes
[0]
2337 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2338 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2343 /* Get a description of operand OPNO of INSN. */
2345 static const struct mips_operand
*
2346 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2348 const struct mips_operand_array
*operands
;
2350 operands
= insn_operands (insn
);
2351 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2353 return operands
->operand
[opno
];
2356 /* Install UVAL as the value of OPERAND in INSN. */
2359 insn_insert_operand (struct mips_cl_insn
*insn
,
2360 const struct mips_operand
*operand
, unsigned int uval
)
2362 if (mips_opts
.mips16
2363 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2364 && mips_opcode_32bit_p (insn
->insn_mo
))
2365 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2367 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2370 /* Extract the value of OPERAND from INSN. */
2372 static inline unsigned
2373 insn_extract_operand (const struct mips_cl_insn
*insn
,
2374 const struct mips_operand
*operand
)
2376 return mips_extract_operand (operand
, insn
->insn_opcode
);
2379 /* Record the current MIPS16/microMIPS mode in now_seg. */
2382 mips_record_compressed_mode (void)
2384 segment_info_type
*si
;
2386 si
= seg_info (now_seg
);
2387 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2388 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2389 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2390 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2393 /* Read a standard MIPS instruction from BUF. */
2395 static unsigned long
2396 read_insn (char *buf
)
2398 if (target_big_endian
)
2399 return bfd_getb32 ((bfd_byte
*) buf
);
2401 return bfd_getl32 ((bfd_byte
*) buf
);
2404 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2408 write_insn (char *buf
, unsigned int insn
)
2410 md_number_to_chars (buf
, insn
, 4);
2414 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2415 has length LENGTH. */
2417 static unsigned long
2418 read_compressed_insn (char *buf
, unsigned int length
)
2424 for (i
= 0; i
< length
; i
+= 2)
2427 if (target_big_endian
)
2428 insn
|= bfd_getb16 ((char *) buf
);
2430 insn
|= bfd_getl16 ((char *) buf
);
2436 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2437 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2440 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2444 for (i
= 0; i
< length
; i
+= 2)
2445 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2446 return buf
+ length
;
2449 /* Install INSN at the location specified by its "frag" and "where" fields. */
2452 install_insn (const struct mips_cl_insn
*insn
)
2454 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2455 if (HAVE_CODE_COMPRESSION
)
2456 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2458 write_insn (f
, insn
->insn_opcode
);
2459 mips_record_compressed_mode ();
2462 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2463 and install the opcode in the new location. */
2466 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2471 insn
->where
= where
;
2472 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2473 if (insn
->fixp
[i
] != NULL
)
2475 insn
->fixp
[i
]->fx_frag
= frag
;
2476 insn
->fixp
[i
]->fx_where
= where
;
2478 install_insn (insn
);
2481 /* Add INSN to the end of the output. */
2484 add_fixed_insn (struct mips_cl_insn
*insn
)
2486 char *f
= frag_more (insn_length (insn
));
2487 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2490 /* Start a variant frag and move INSN to the start of the variant part,
2491 marking it as fixed. The other arguments are as for frag_var. */
2494 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2495 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2497 frag_grow (max_chars
);
2498 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2500 frag_var (rs_machine_dependent
, max_chars
, var
,
2501 subtype
, symbol
, offset
, NULL
);
2504 /* Insert N copies of INSN into the history buffer, starting at
2505 position FIRST. Neither FIRST nor N need to be clipped. */
2508 insert_into_history (unsigned int first
, unsigned int n
,
2509 const struct mips_cl_insn
*insn
)
2511 if (mips_relax
.sequence
!= 2)
2515 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2517 history
[i
] = history
[i
- n
];
2523 /* Clear the error in insn_error. */
2526 clear_insn_error (void)
2528 memset (&insn_error
, 0, sizeof (insn_error
));
2531 /* Possibly record error message MSG for the current instruction.
2532 If the error is about a particular argument, ARGNUM is the 1-based
2533 number of that argument, otherwise it is 0. FORMAT is the format
2534 of MSG. Return true if MSG was used, false if the current message
2538 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2543 /* Give priority to errors against specific arguments, and to
2544 the first whole-instruction message. */
2550 /* Keep insn_error if it is against a later argument. */
2551 if (argnum
< insn_error
.min_argnum
)
2554 /* If both errors are against the same argument but are different,
2555 give up on reporting a specific error for this argument.
2556 See the comment about mips_insn_error for details. */
2557 if (argnum
== insn_error
.min_argnum
2559 && strcmp (insn_error
.msg
, msg
) != 0)
2562 insn_error
.min_argnum
+= 1;
2566 insn_error
.min_argnum
= argnum
;
2567 insn_error
.format
= format
;
2568 insn_error
.msg
= msg
;
2572 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2573 as for set_insn_error_format. */
2576 set_insn_error (int argnum
, const char *msg
)
2578 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2581 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2582 as for set_insn_error_format. */
2585 set_insn_error_i (int argnum
, const char *msg
, int i
)
2587 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2591 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2592 are as for set_insn_error_format. */
2595 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2597 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2599 insn_error
.u
.ss
[0] = s1
;
2600 insn_error
.u
.ss
[1] = s2
;
2604 /* Report the error in insn_error, which is against assembly code STR. */
2607 report_insn_error (const char *str
)
2609 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2611 switch (insn_error
.format
)
2618 as_bad (msg
, insn_error
.u
.i
, str
);
2622 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2626 free ((char *) msg
);
2629 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2630 the idea is to make it obvious at a glance that each errata is
2634 init_vr4120_conflicts (void)
2636 #define CONFLICT(FIRST, SECOND) \
2637 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2639 /* Errata 21 - [D]DIV[U] after [D]MACC */
2640 CONFLICT (MACC
, DIV
);
2641 CONFLICT (DMACC
, DIV
);
2643 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2644 CONFLICT (DMULT
, DMULT
);
2645 CONFLICT (DMULT
, DMACC
);
2646 CONFLICT (DMACC
, DMULT
);
2647 CONFLICT (DMACC
, DMACC
);
2649 /* Errata 24 - MT{LO,HI} after [D]MACC */
2650 CONFLICT (MACC
, MTHILO
);
2651 CONFLICT (DMACC
, MTHILO
);
2653 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2654 instruction is executed immediately after a MACC or DMACC
2655 instruction, the result of [either instruction] is incorrect." */
2656 CONFLICT (MACC
, MULT
);
2657 CONFLICT (MACC
, DMULT
);
2658 CONFLICT (DMACC
, MULT
);
2659 CONFLICT (DMACC
, DMULT
);
2661 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2662 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2663 DDIV or DDIVU instruction, the result of the MACC or
2664 DMACC instruction is incorrect.". */
2665 CONFLICT (DMULT
, MACC
);
2666 CONFLICT (DMULT
, DMACC
);
2667 CONFLICT (DIV
, MACC
);
2668 CONFLICT (DIV
, DMACC
);
2678 #define RNUM_MASK 0x00000ff
2679 #define RTYPE_MASK 0x0ffff00
2680 #define RTYPE_NUM 0x0000100
2681 #define RTYPE_FPU 0x0000200
2682 #define RTYPE_FCC 0x0000400
2683 #define RTYPE_VEC 0x0000800
2684 #define RTYPE_GP 0x0001000
2685 #define RTYPE_CP0 0x0002000
2686 #define RTYPE_PC 0x0004000
2687 #define RTYPE_ACC 0x0008000
2688 #define RTYPE_CCC 0x0010000
2689 #define RTYPE_VI 0x0020000
2690 #define RTYPE_VF 0x0040000
2691 #define RTYPE_R5900_I 0x0080000
2692 #define RTYPE_R5900_Q 0x0100000
2693 #define RTYPE_R5900_R 0x0200000
2694 #define RTYPE_R5900_ACC 0x0400000
2695 #define RTYPE_MSA 0x0800000
2696 #define RWARN 0x8000000
2698 #define GENERIC_REGISTER_NUMBERS \
2699 {"$0", RTYPE_NUM | 0}, \
2700 {"$1", RTYPE_NUM | 1}, \
2701 {"$2", RTYPE_NUM | 2}, \
2702 {"$3", RTYPE_NUM | 3}, \
2703 {"$4", RTYPE_NUM | 4}, \
2704 {"$5", RTYPE_NUM | 5}, \
2705 {"$6", RTYPE_NUM | 6}, \
2706 {"$7", RTYPE_NUM | 7}, \
2707 {"$8", RTYPE_NUM | 8}, \
2708 {"$9", RTYPE_NUM | 9}, \
2709 {"$10", RTYPE_NUM | 10}, \
2710 {"$11", RTYPE_NUM | 11}, \
2711 {"$12", RTYPE_NUM | 12}, \
2712 {"$13", RTYPE_NUM | 13}, \
2713 {"$14", RTYPE_NUM | 14}, \
2714 {"$15", RTYPE_NUM | 15}, \
2715 {"$16", RTYPE_NUM | 16}, \
2716 {"$17", RTYPE_NUM | 17}, \
2717 {"$18", RTYPE_NUM | 18}, \
2718 {"$19", RTYPE_NUM | 19}, \
2719 {"$20", RTYPE_NUM | 20}, \
2720 {"$21", RTYPE_NUM | 21}, \
2721 {"$22", RTYPE_NUM | 22}, \
2722 {"$23", RTYPE_NUM | 23}, \
2723 {"$24", RTYPE_NUM | 24}, \
2724 {"$25", RTYPE_NUM | 25}, \
2725 {"$26", RTYPE_NUM | 26}, \
2726 {"$27", RTYPE_NUM | 27}, \
2727 {"$28", RTYPE_NUM | 28}, \
2728 {"$29", RTYPE_NUM | 29}, \
2729 {"$30", RTYPE_NUM | 30}, \
2730 {"$31", RTYPE_NUM | 31}
2732 #define FPU_REGISTER_NAMES \
2733 {"$f0", RTYPE_FPU | 0}, \
2734 {"$f1", RTYPE_FPU | 1}, \
2735 {"$f2", RTYPE_FPU | 2}, \
2736 {"$f3", RTYPE_FPU | 3}, \
2737 {"$f4", RTYPE_FPU | 4}, \
2738 {"$f5", RTYPE_FPU | 5}, \
2739 {"$f6", RTYPE_FPU | 6}, \
2740 {"$f7", RTYPE_FPU | 7}, \
2741 {"$f8", RTYPE_FPU | 8}, \
2742 {"$f9", RTYPE_FPU | 9}, \
2743 {"$f10", RTYPE_FPU | 10}, \
2744 {"$f11", RTYPE_FPU | 11}, \
2745 {"$f12", RTYPE_FPU | 12}, \
2746 {"$f13", RTYPE_FPU | 13}, \
2747 {"$f14", RTYPE_FPU | 14}, \
2748 {"$f15", RTYPE_FPU | 15}, \
2749 {"$f16", RTYPE_FPU | 16}, \
2750 {"$f17", RTYPE_FPU | 17}, \
2751 {"$f18", RTYPE_FPU | 18}, \
2752 {"$f19", RTYPE_FPU | 19}, \
2753 {"$f20", RTYPE_FPU | 20}, \
2754 {"$f21", RTYPE_FPU | 21}, \
2755 {"$f22", RTYPE_FPU | 22}, \
2756 {"$f23", RTYPE_FPU | 23}, \
2757 {"$f24", RTYPE_FPU | 24}, \
2758 {"$f25", RTYPE_FPU | 25}, \
2759 {"$f26", RTYPE_FPU | 26}, \
2760 {"$f27", RTYPE_FPU | 27}, \
2761 {"$f28", RTYPE_FPU | 28}, \
2762 {"$f29", RTYPE_FPU | 29}, \
2763 {"$f30", RTYPE_FPU | 30}, \
2764 {"$f31", RTYPE_FPU | 31}
2766 #define FPU_CONDITION_CODE_NAMES \
2767 {"$fcc0", RTYPE_FCC | 0}, \
2768 {"$fcc1", RTYPE_FCC | 1}, \
2769 {"$fcc2", RTYPE_FCC | 2}, \
2770 {"$fcc3", RTYPE_FCC | 3}, \
2771 {"$fcc4", RTYPE_FCC | 4}, \
2772 {"$fcc5", RTYPE_FCC | 5}, \
2773 {"$fcc6", RTYPE_FCC | 6}, \
2774 {"$fcc7", RTYPE_FCC | 7}
2776 #define COPROC_CONDITION_CODE_NAMES \
2777 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2778 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2779 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2780 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2781 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2782 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2783 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2784 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2786 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2787 {"$a4", RTYPE_GP | 8}, \
2788 {"$a5", RTYPE_GP | 9}, \
2789 {"$a6", RTYPE_GP | 10}, \
2790 {"$a7", RTYPE_GP | 11}, \
2791 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2792 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2793 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2794 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2795 {"$t0", RTYPE_GP | 12}, \
2796 {"$t1", RTYPE_GP | 13}, \
2797 {"$t2", RTYPE_GP | 14}, \
2798 {"$t3", RTYPE_GP | 15}
2800 #define O32_SYMBOLIC_REGISTER_NAMES \
2801 {"$t0", RTYPE_GP | 8}, \
2802 {"$t1", RTYPE_GP | 9}, \
2803 {"$t2", RTYPE_GP | 10}, \
2804 {"$t3", RTYPE_GP | 11}, \
2805 {"$t4", RTYPE_GP | 12}, \
2806 {"$t5", RTYPE_GP | 13}, \
2807 {"$t6", RTYPE_GP | 14}, \
2808 {"$t7", RTYPE_GP | 15}, \
2809 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2810 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2811 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2812 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2814 /* Remaining symbolic register names. */
2815 #define SYMBOLIC_REGISTER_NAMES \
2816 {"$zero", RTYPE_GP | 0}, \
2817 {"$at", RTYPE_GP | 1}, \
2818 {"$AT", RTYPE_GP | 1}, \
2819 {"$v0", RTYPE_GP | 2}, \
2820 {"$v1", RTYPE_GP | 3}, \
2821 {"$a0", RTYPE_GP | 4}, \
2822 {"$a1", RTYPE_GP | 5}, \
2823 {"$a2", RTYPE_GP | 6}, \
2824 {"$a3", RTYPE_GP | 7}, \
2825 {"$s0", RTYPE_GP | 16}, \
2826 {"$s1", RTYPE_GP | 17}, \
2827 {"$s2", RTYPE_GP | 18}, \
2828 {"$s3", RTYPE_GP | 19}, \
2829 {"$s4", RTYPE_GP | 20}, \
2830 {"$s5", RTYPE_GP | 21}, \
2831 {"$s6", RTYPE_GP | 22}, \
2832 {"$s7", RTYPE_GP | 23}, \
2833 {"$t8", RTYPE_GP | 24}, \
2834 {"$t9", RTYPE_GP | 25}, \
2835 {"$k0", RTYPE_GP | 26}, \
2836 {"$kt0", RTYPE_GP | 26}, \
2837 {"$k1", RTYPE_GP | 27}, \
2838 {"$kt1", RTYPE_GP | 27}, \
2839 {"$gp", RTYPE_GP | 28}, \
2840 {"$sp", RTYPE_GP | 29}, \
2841 {"$s8", RTYPE_GP | 30}, \
2842 {"$fp", RTYPE_GP | 30}, \
2843 {"$ra", RTYPE_GP | 31}
2845 #define MIPS16_SPECIAL_REGISTER_NAMES \
2846 {"$pc", RTYPE_PC | 0}
2848 #define MDMX_VECTOR_REGISTER_NAMES \
2849 /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \
2850 /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \
2851 {"$v2", RTYPE_VEC | 2}, \
2852 {"$v3", RTYPE_VEC | 3}, \
2853 {"$v4", RTYPE_VEC | 4}, \
2854 {"$v5", RTYPE_VEC | 5}, \
2855 {"$v6", RTYPE_VEC | 6}, \
2856 {"$v7", RTYPE_VEC | 7}, \
2857 {"$v8", RTYPE_VEC | 8}, \
2858 {"$v9", RTYPE_VEC | 9}, \
2859 {"$v10", RTYPE_VEC | 10}, \
2860 {"$v11", RTYPE_VEC | 11}, \
2861 {"$v12", RTYPE_VEC | 12}, \
2862 {"$v13", RTYPE_VEC | 13}, \
2863 {"$v14", RTYPE_VEC | 14}, \
2864 {"$v15", RTYPE_VEC | 15}, \
2865 {"$v16", RTYPE_VEC | 16}, \
2866 {"$v17", RTYPE_VEC | 17}, \
2867 {"$v18", RTYPE_VEC | 18}, \
2868 {"$v19", RTYPE_VEC | 19}, \
2869 {"$v20", RTYPE_VEC | 20}, \
2870 {"$v21", RTYPE_VEC | 21}, \
2871 {"$v22", RTYPE_VEC | 22}, \
2872 {"$v23", RTYPE_VEC | 23}, \
2873 {"$v24", RTYPE_VEC | 24}, \
2874 {"$v25", RTYPE_VEC | 25}, \
2875 {"$v26", RTYPE_VEC | 26}, \
2876 {"$v27", RTYPE_VEC | 27}, \
2877 {"$v28", RTYPE_VEC | 28}, \
2878 {"$v29", RTYPE_VEC | 29}, \
2879 {"$v30", RTYPE_VEC | 30}, \
2880 {"$v31", RTYPE_VEC | 31}
2882 #define R5900_I_NAMES \
2883 {"$I", RTYPE_R5900_I | 0}
2885 #define R5900_Q_NAMES \
2886 {"$Q", RTYPE_R5900_Q | 0}
2888 #define R5900_R_NAMES \
2889 {"$R", RTYPE_R5900_R | 0}
2891 #define R5900_ACC_NAMES \
2892 {"$ACC", RTYPE_R5900_ACC | 0 }
2894 #define MIPS_DSP_ACCUMULATOR_NAMES \
2895 {"$ac0", RTYPE_ACC | 0}, \
2896 {"$ac1", RTYPE_ACC | 1}, \
2897 {"$ac2", RTYPE_ACC | 2}, \
2898 {"$ac3", RTYPE_ACC | 3}
2900 static const struct regname reg_names
[] = {
2901 GENERIC_REGISTER_NUMBERS
,
2903 FPU_CONDITION_CODE_NAMES
,
2904 COPROC_CONDITION_CODE_NAMES
,
2906 /* The $txx registers depends on the abi,
2907 these will be added later into the symbol table from
2908 one of the tables below once mips_abi is set after
2909 parsing of arguments from the command line. */
2910 SYMBOLIC_REGISTER_NAMES
,
2912 MIPS16_SPECIAL_REGISTER_NAMES
,
2913 MDMX_VECTOR_REGISTER_NAMES
,
2918 MIPS_DSP_ACCUMULATOR_NAMES
,
2922 static const struct regname reg_names_o32
[] = {
2923 O32_SYMBOLIC_REGISTER_NAMES
,
2927 static const struct regname reg_names_n32n64
[] = {
2928 N32N64_SYMBOLIC_REGISTER_NAMES
,
2932 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2933 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2934 of these register symbols, return the associated vector register,
2935 otherwise return SYMVAL itself. */
2938 mips_prefer_vec_regno (unsigned int symval
)
2940 if ((symval
& -2) == (RTYPE_GP
| 2))
2941 return RTYPE_VEC
| (symval
& 1);
2945 /* Return true if string [S, E) is a valid register name, storing its
2946 symbol value in *SYMVAL_PTR if so. */
2949 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2954 /* Terminate name. */
2958 /* Look up the name. */
2959 symbol
= symbol_find (s
);
2962 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2965 *symval_ptr
= S_GET_VALUE (symbol
);
2969 /* Return true if the string at *SPTR is a valid register name. Allow it
2970 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2973 When returning true, move *SPTR past the register, store the
2974 register's symbol value in *SYMVAL_PTR and the channel mask in
2975 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2976 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2977 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2980 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2981 unsigned int *channels_ptr
)
2985 unsigned int channels
, symval
, bit
;
2987 /* Find end of name. */
2989 if (is_name_beginner (*e
))
2991 while (is_part_of_name (*e
))
2995 if (!mips_parse_register_1 (s
, e
, &symval
))
3000 /* Eat characters from the end of the string that are valid
3001 channel suffixes. The preceding register must be $ACC or
3002 end with a digit, so there is no ambiguity. */
3005 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
3006 if (m
> s
&& m
[-1] == *q
)
3013 || !mips_parse_register_1 (s
, m
, &symval
)
3014 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
3019 *symval_ptr
= symval
;
3021 *channels_ptr
= channels
;
3025 /* Check if SPTR points at a valid register specifier according to TYPES.
3026 If so, then return 1, advance S to consume the specifier and store
3027 the register's number in REGNOP, otherwise return 0. */
3030 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
3034 if (mips_parse_register (s
, ®no
, NULL
))
3036 if (types
& RTYPE_VEC
)
3037 regno
= mips_prefer_vec_regno (regno
);
3046 as_warn (_("unrecognized register name `%s'"), *s
);
3051 return regno
<= RNUM_MASK
;
3054 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3055 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3058 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
3063 for (i
= 0; i
< 4; i
++)
3064 if (*s
== "xyzw"[i
])
3066 *channels
|= 1 << (3 - i
);
3072 /* Token types for parsed operand lists. */
3073 enum mips_operand_token_type
{
3074 /* A plain register, e.g. $f2. */
3077 /* A 4-bit XYZW channel mask. */
3080 /* A constant vector index, e.g. [1]. */
3083 /* A register vector index, e.g. [$2]. */
3086 /* A continuous range of registers, e.g. $s0-$s4. */
3089 /* A (possibly relocated) expression. */
3092 /* A floating-point value. */
3095 /* A single character. This can be '(', ')' or ',', but '(' only appears
3099 /* A doubled character, either "--" or "++". */
3102 /* The end of the operand list. */
3106 /* A parsed operand token. */
3107 struct mips_operand_token
3109 /* The type of token. */
3110 enum mips_operand_token_type type
;
3113 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3116 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3117 unsigned int channels
;
3119 /* The integer value of an OT_INTEGER_INDEX. */
3122 /* The two register symbol values involved in an OT_REG_RANGE. */
3124 unsigned int regno1
;
3125 unsigned int regno2
;
3128 /* The value of an OT_INTEGER. The value is represented as an
3129 expression and the relocation operators that were applied to
3130 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3131 relocation operators were used. */
3134 bfd_reloc_code_real_type relocs
[3];
3137 /* The binary data for an OT_FLOAT constant, and the number of bytes
3140 unsigned char data
[8];
3144 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3149 /* An obstack used to construct lists of mips_operand_tokens. */
3150 static struct obstack mips_operand_tokens
;
3152 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3155 mips_add_token (struct mips_operand_token
*token
,
3156 enum mips_operand_token_type type
)
3159 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3162 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3163 and OT_REG tokens for them if so, and return a pointer to the first
3164 unconsumed character. Return null otherwise. */
3167 mips_parse_base_start (char *s
)
3169 struct mips_operand_token token
;
3170 unsigned int regno
, channels
;
3177 SKIP_SPACE_TABS (s
);
3179 /* Only match "--" as part of a base expression. In other contexts "--X"
3180 is a double negative. */
3181 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3185 SKIP_SPACE_TABS (s
);
3188 /* Allow a channel specifier because that leads to better error messages
3189 than treating something like "$vf0x++" as an expression. */
3190 if (!mips_parse_register (&s
, ®no
, &channels
))
3194 mips_add_token (&token
, OT_CHAR
);
3199 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3202 token
.u
.regno
= regno
;
3203 mips_add_token (&token
, OT_REG
);
3207 token
.u
.channels
= channels
;
3208 mips_add_token (&token
, OT_CHANNELS
);
3211 /* For consistency, only match "++" as part of base expressions too. */
3212 SKIP_SPACE_TABS (s
);
3213 if (s
[0] == '+' && s
[1] == '+')
3217 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3223 /* Parse one or more tokens from S. Return a pointer to the first
3224 unconsumed character on success. Return null if an error was found
3225 and store the error text in insn_error. FLOAT_FORMAT is as for
3226 mips_parse_arguments. */
3229 mips_parse_argument_token (char *s
, char float_format
)
3231 char *end
, *save_in
;
3233 unsigned int regno1
, regno2
, channels
;
3234 struct mips_operand_token token
;
3236 /* First look for "($reg", since we want to treat that as an
3237 OT_CHAR and OT_REG rather than an expression. */
3238 end
= mips_parse_base_start (s
);
3242 /* Handle other characters that end up as OT_CHARs. */
3243 if (*s
== ')' || *s
== ',')
3246 mips_add_token (&token
, OT_CHAR
);
3251 /* Handle tokens that start with a register. */
3252 if (mips_parse_register (&s
, ®no1
, &channels
))
3256 /* A register and a VU0 channel suffix. */
3257 token
.u
.regno
= regno1
;
3258 mips_add_token (&token
, OT_REG
);
3260 token
.u
.channels
= channels
;
3261 mips_add_token (&token
, OT_CHANNELS
);
3265 SKIP_SPACE_TABS (s
);
3268 /* A register range. */
3270 SKIP_SPACE_TABS (s
);
3271 if (!mips_parse_register (&s
, ®no2
, NULL
))
3273 set_insn_error (0, _("invalid register range"));
3277 token
.u
.reg_range
.regno1
= regno1
;
3278 token
.u
.reg_range
.regno2
= regno2
;
3279 mips_add_token (&token
, OT_REG_RANGE
);
3283 /* Add the register itself. */
3284 token
.u
.regno
= regno1
;
3285 mips_add_token (&token
, OT_REG
);
3287 /* Check for a vector index. */
3291 SKIP_SPACE_TABS (s
);
3292 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3293 mips_add_token (&token
, OT_REG_INDEX
);
3296 expressionS element
;
3298 my_getExpression (&element
, s
);
3299 if (element
.X_op
!= O_constant
)
3301 set_insn_error (0, _("vector element must be constant"));
3305 token
.u
.index
= element
.X_add_number
;
3306 mips_add_token (&token
, OT_INTEGER_INDEX
);
3308 SKIP_SPACE_TABS (s
);
3311 set_insn_error (0, _("missing `]'"));
3321 /* First try to treat expressions as floats. */
3322 save_in
= input_line_pointer
;
3323 input_line_pointer
= s
;
3324 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3325 &token
.u
.flt
.length
);
3326 end
= input_line_pointer
;
3327 input_line_pointer
= save_in
;
3330 set_insn_error (0, err
);
3335 mips_add_token (&token
, OT_FLOAT
);
3340 /* Treat everything else as an integer expression. */
3341 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3342 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3343 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3344 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3346 mips_add_token (&token
, OT_INTEGER
);
3350 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3351 if expressions should be treated as 32-bit floating-point constants,
3352 'd' if they should be treated as 64-bit floating-point constants,
3353 or 0 if they should be treated as integer expressions (the usual case).
3355 Return a list of tokens on success, otherwise return 0. The caller
3356 must obstack_free the list after use. */
3358 static struct mips_operand_token
*
3359 mips_parse_arguments (char *s
, char float_format
)
3361 struct mips_operand_token token
;
3363 SKIP_SPACE_TABS (s
);
3366 s
= mips_parse_argument_token (s
, float_format
);
3369 obstack_free (&mips_operand_tokens
,
3370 obstack_finish (&mips_operand_tokens
));
3373 SKIP_SPACE_TABS (s
);
3375 mips_add_token (&token
, OT_END
);
3376 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3379 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3380 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3383 is_opcode_valid (const struct mips_opcode
*mo
)
3385 int isa
= mips_opts
.isa
;
3386 int ase
= mips_opts
.ase
;
3390 if (ISA_HAS_64BIT_REGS (isa
))
3391 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3392 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3393 ase
|= mips_ases
[i
].flags64
;
3395 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3398 /* Check whether the instruction or macro requires single-precision or
3399 double-precision floating-point support. Note that this information is
3400 stored differently in the opcode table for insns and macros. */
3401 if (mo
->pinfo
== INSN_MACRO
)
3403 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3404 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3408 fp_s
= mo
->pinfo
& FP_S
;
3409 fp_d
= mo
->pinfo
& FP_D
;
3412 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3415 if (fp_s
&& mips_opts
.soft_float
)
3421 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3422 selected ISA and architecture. */
3425 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3427 int isa
= mips_opts
.isa
;
3428 int ase
= mips_opts
.ase
;
3431 if (ISA_HAS_64BIT_REGS (isa
))
3432 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3433 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3434 ase
|= mips_ases
[i
].flags64
;
3436 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3439 /* Return TRUE if the size of the microMIPS opcode MO matches one
3440 explicitly requested. Always TRUE in the standard MIPS mode.
3441 Use is_size_valid_16 for MIPS16 opcodes. */
3444 is_size_valid (const struct mips_opcode
*mo
)
3446 if (!mips_opts
.micromips
)
3449 if (mips_opts
.insn32
)
3451 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3453 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3456 if (!forced_insn_length
)
3458 if (mo
->pinfo
== INSN_MACRO
)
3460 return forced_insn_length
== micromips_insn_length (mo
);
3463 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3464 explicitly requested. */
3467 is_size_valid_16 (const struct mips_opcode
*mo
)
3469 if (!forced_insn_length
)
3471 if (mo
->pinfo
== INSN_MACRO
)
3473 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3475 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3480 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3481 of the preceding instruction. Always TRUE in the standard MIPS mode.
3483 We don't accept macros in 16-bit delay slots to avoid a case where
3484 a macro expansion fails because it relies on a preceding 32-bit real
3485 instruction to have matched and does not handle the operands correctly.
3486 The only macros that may expand to 16-bit instructions are JAL that
3487 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3488 and BGT (that likewise cannot be placed in a delay slot) that decay to
3489 a NOP. In all these cases the macros precede any corresponding real
3490 instruction definitions in the opcode table, so they will match in the
3491 second pass where the size of the delay slot is ignored and therefore
3492 produce correct code. */
3495 is_delay_slot_valid (const struct mips_opcode
*mo
)
3497 if (!mips_opts
.micromips
)
3500 if (mo
->pinfo
== INSN_MACRO
)
3501 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3502 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3503 && micromips_insn_length (mo
) != 4)
3505 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3506 && micromips_insn_length (mo
) != 2)
3512 /* For consistency checking, verify that all bits of OPCODE are specified
3513 either by the match/mask part of the instruction definition, or by the
3514 operand list. Also build up a list of operands in OPERANDS.
3516 INSN_BITS says which bits of the instruction are significant.
3517 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3518 provides the mips_operand description of each operand. DECODE_OPERAND
3519 is null for MIPS16 instructions. */
3522 validate_mips_insn (const struct mips_opcode
*opcode
,
3523 unsigned long insn_bits
,
3524 const struct mips_operand
*(*decode_operand
) (const char *),
3525 struct mips_operand_array
*operands
)
3528 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3529 const struct mips_operand
*operand
;
3531 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3532 if ((mask
& opcode
->match
) != opcode
->match
)
3534 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3535 opcode
->name
, opcode
->args
);
3540 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3541 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3542 for (s
= opcode
->args
; *s
; ++s
)
3555 if (!decode_operand
)
3556 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3558 operand
= decode_operand (s
);
3559 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3561 as_bad (_("internal: unknown operand type: %s %s"),
3562 opcode
->name
, opcode
->args
);
3565 gas_assert (opno
< MAX_OPERANDS
);
3566 operands
->operand
[opno
] = operand
;
3567 if (!decode_operand
&& operand
3568 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3569 && mips_opcode_32bit_p (opcode
))
3570 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3571 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3573 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3574 if (operand
->type
== OP_MDMX_IMM_REG
)
3575 /* Bit 5 is the format selector (OB vs QH). The opcode table
3576 has separate entries for each format. */
3577 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3578 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3579 used_bits
&= ~(mask
& 0x700);
3580 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3581 operand field that cannot be fully described with LSB/SIZE. */
3582 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3583 used_bits
&= ~0x6000;
3585 /* Skip prefix characters. */
3586 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3591 doubled
= used_bits
& mask
& insn_bits
;
3594 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3595 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3599 undefined
= ~used_bits
& insn_bits
;
3600 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3602 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3603 undefined
, opcode
->name
, opcode
->args
);
3606 used_bits
&= ~insn_bits
;
3609 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3610 used_bits
, opcode
->name
, opcode
->args
);
3616 /* The MIPS16 version of validate_mips_insn. */
3619 validate_mips16_insn (const struct mips_opcode
*opcode
,
3620 struct mips_operand_array
*operands
)
3622 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3624 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3627 /* The microMIPS version of validate_mips_insn. */
3630 validate_micromips_insn (const struct mips_opcode
*opc
,
3631 struct mips_operand_array
*operands
)
3633 unsigned long insn_bits
;
3634 unsigned long major
;
3635 unsigned int length
;
3637 if (opc
->pinfo
== INSN_MACRO
)
3638 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3641 length
= micromips_insn_length (opc
);
3642 if (length
!= 2 && length
!= 4)
3644 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3645 "%s %s"), length
, opc
->name
, opc
->args
);
3648 major
= opc
->match
>> (10 + 8 * (length
- 2));
3649 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3650 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3652 as_bad (_("internal error: bad microMIPS opcode "
3653 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3657 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3658 insn_bits
= 1 << 4 * length
;
3659 insn_bits
<<= 4 * length
;
3661 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3665 /* This function is called once, at assembler startup time. It should set up
3666 all the tables, etc. that the MD part of the assembler will need. */
3674 if (mips_pic
!= NO_PIC
)
3676 if (g_switch_seen
&& g_switch_value
!= 0)
3677 as_bad (_("-G may not be used in position-independent code"));
3680 else if (mips_abicalls
)
3682 if (g_switch_seen
&& g_switch_value
!= 0)
3683 as_bad (_("-G may not be used with abicalls"));
3687 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3688 as_warn (_("could not set architecture and machine"));
3690 op_hash
= str_htab_create ();
3692 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3693 for (i
= 0; i
< NUMOPCODES
;)
3695 const char *name
= mips_opcodes
[i
].name
;
3697 if (str_hash_insert (op_hash
, name
, &mips_opcodes
[i
], 0) != NULL
)
3698 as_fatal (_("duplicate %s"), name
);
3701 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3702 decode_mips_operand
, &mips_operands
[i
]))
3705 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3707 create_insn (&nop_insn
, mips_opcodes
+ i
);
3708 if (mips_fix_loongson2f_nop
)
3709 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3710 nop_insn
.fixed_p
= 1;
3713 if (sync_insn
.insn_mo
== NULL
&& strcmp (name
, "sync") == 0)
3714 create_insn (&sync_insn
, mips_opcodes
+ i
);
3718 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3721 mips16_op_hash
= str_htab_create ();
3722 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3723 bfd_mips16_num_opcodes
);
3726 while (i
< bfd_mips16_num_opcodes
)
3728 const char *name
= mips16_opcodes
[i
].name
;
3730 if (str_hash_insert (mips16_op_hash
, name
, &mips16_opcodes
[i
], 0))
3731 as_fatal (_("duplicate %s"), name
);
3734 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3736 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3738 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3739 mips16_nop_insn
.fixed_p
= 1;
3743 while (i
< bfd_mips16_num_opcodes
3744 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3747 micromips_op_hash
= str_htab_create ();
3748 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3749 bfd_micromips_num_opcodes
);
3752 while (i
< bfd_micromips_num_opcodes
)
3754 const char *name
= micromips_opcodes
[i
].name
;
3756 if (str_hash_insert (micromips_op_hash
, name
, µmips_opcodes
[i
], 0))
3757 as_fatal (_("duplicate %s"), name
);
3760 struct mips_cl_insn
*micromips_nop_insn
;
3762 if (!validate_micromips_insn (µmips_opcodes
[i
],
3763 µmips_operands
[i
]))
3766 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3768 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3769 micromips_nop_insn
= µmips_nop16_insn
;
3770 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3771 micromips_nop_insn
= µmips_nop32_insn
;
3775 if (micromips_nop_insn
->insn_mo
== NULL
3776 && strcmp (name
, "nop") == 0)
3778 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3779 micromips_nop_insn
->fixed_p
= 1;
3783 while (++i
< bfd_micromips_num_opcodes
3784 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3788 as_fatal (_("broken assembler, no assembly attempted"));
3790 /* We add all the general register names to the symbol table. This
3791 helps us detect invalid uses of them. */
3792 for (i
= 0; reg_names
[i
].name
; i
++)
3793 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3797 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3798 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3800 reg_names_n32n64
[i
].num
));
3802 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3803 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3805 reg_names_o32
[i
].num
));
3807 for (i
= 0; i
< 32; i
++)
3811 /* R5900 VU0 floating-point register. */
3812 sprintf (regname
, "$vf%d", i
);
3813 symbol_table_insert (symbol_new (regname
, reg_section
,
3814 &zero_address_frag
, RTYPE_VF
| i
));
3816 /* R5900 VU0 integer register. */
3817 sprintf (regname
, "$vi%d", i
);
3818 symbol_table_insert (symbol_new (regname
, reg_section
,
3819 &zero_address_frag
, RTYPE_VI
| i
));
3822 sprintf (regname
, "$w%d", i
);
3823 symbol_table_insert (symbol_new (regname
, reg_section
,
3824 &zero_address_frag
, RTYPE_MSA
| i
));
3827 obstack_init (&mips_operand_tokens
);
3829 mips_no_prev_insn ();
3832 mips_cprmask
[0] = 0;
3833 mips_cprmask
[1] = 0;
3834 mips_cprmask
[2] = 0;
3835 mips_cprmask
[3] = 0;
3837 /* set the default alignment for the text section (2**2) */
3838 record_alignment (text_section
, 2);
3840 bfd_set_gp_size (stdoutput
, g_switch_value
);
3842 /* On a native system other than VxWorks, sections must be aligned
3843 to 16 byte boundaries. When configured for an embedded ELF
3844 target, we don't bother. */
3845 if (strncmp (TARGET_OS
, "elf", 3) != 0
3846 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3848 bfd_set_section_alignment (text_section
, 4);
3849 bfd_set_section_alignment (data_section
, 4);
3850 bfd_set_section_alignment (bss_section
, 4);
3853 /* Create a .reginfo section for register masks and a .mdebug
3854 section for debugging information. */
3862 subseg
= now_subseg
;
3864 /* The ABI says this section should be loaded so that the
3865 running program can access it. However, we don't load it
3866 if we are configured for an embedded target. */
3867 flags
= SEC_READONLY
| SEC_DATA
;
3868 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3869 flags
|= SEC_ALLOC
| SEC_LOAD
;
3871 if (mips_abi
!= N64_ABI
)
3873 sec
= subseg_new (".reginfo", (subsegT
) 0);
3875 bfd_set_section_flags (sec
, flags
);
3876 bfd_set_section_alignment (sec
, HAVE_NEWABI
? 3 : 2);
3878 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3882 /* The 64-bit ABI uses a .MIPS.options section rather than
3883 .reginfo section. */
3884 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3885 bfd_set_section_flags (sec
, flags
);
3886 bfd_set_section_alignment (sec
, 3);
3888 /* Set up the option header. */
3890 Elf_Internal_Options opthdr
;
3893 opthdr
.kind
= ODK_REGINFO
;
3894 opthdr
.size
= (sizeof (Elf_External_Options
)
3895 + sizeof (Elf64_External_RegInfo
));
3898 f
= frag_more (sizeof (Elf_External_Options
));
3899 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3900 (Elf_External_Options
*) f
);
3902 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3906 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3907 bfd_set_section_flags (sec
,
3908 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3909 bfd_set_section_alignment (sec
, 3);
3910 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3912 if (ECOFF_DEBUGGING
)
3914 sec
= subseg_new (".mdebug", (subsegT
) 0);
3915 bfd_set_section_flags (sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
3916 bfd_set_section_alignment (sec
, 2);
3918 else if (mips_flag_pdr
)
3920 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3921 bfd_set_section_flags (pdr_seg
,
3922 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
3923 bfd_set_section_alignment (pdr_seg
, 2);
3926 subseg_set (seg
, subseg
);
3929 if (mips_fix_vr4120
)
3930 init_vr4120_conflicts ();
3934 fpabi_incompatible_with (int fpabi
, const char *what
)
3936 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3937 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3941 fpabi_requires (int fpabi
, const char *what
)
3943 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3944 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3947 /* Check -mabi and register sizes against the specified FP ABI. */
3949 check_fpabi (int fpabi
)
3953 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3954 if (file_mips_opts
.soft_float
)
3955 fpabi_incompatible_with (fpabi
, "softfloat");
3956 else if (file_mips_opts
.single_float
)
3957 fpabi_incompatible_with (fpabi
, "singlefloat");
3958 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3959 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3960 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3961 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3964 case Val_GNU_MIPS_ABI_FP_XX
:
3965 if (mips_abi
!= O32_ABI
)
3966 fpabi_requires (fpabi
, "-mabi=32");
3967 else if (file_mips_opts
.soft_float
)
3968 fpabi_incompatible_with (fpabi
, "softfloat");
3969 else if (file_mips_opts
.single_float
)
3970 fpabi_incompatible_with (fpabi
, "singlefloat");
3971 else if (file_mips_opts
.fp
!= 0)
3972 fpabi_requires (fpabi
, "fp=xx");
3975 case Val_GNU_MIPS_ABI_FP_64A
:
3976 case Val_GNU_MIPS_ABI_FP_64
:
3977 if (mips_abi
!= O32_ABI
)
3978 fpabi_requires (fpabi
, "-mabi=32");
3979 else if (file_mips_opts
.soft_float
)
3980 fpabi_incompatible_with (fpabi
, "softfloat");
3981 else if (file_mips_opts
.single_float
)
3982 fpabi_incompatible_with (fpabi
, "singlefloat");
3983 else if (file_mips_opts
.fp
!= 64)
3984 fpabi_requires (fpabi
, "fp=64");
3985 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3986 fpabi_incompatible_with (fpabi
, "nooddspreg");
3987 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3988 fpabi_requires (fpabi
, "nooddspreg");
3991 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3992 if (file_mips_opts
.soft_float
)
3993 fpabi_incompatible_with (fpabi
, "softfloat");
3994 else if (!file_mips_opts
.single_float
)
3995 fpabi_requires (fpabi
, "singlefloat");
3998 case Val_GNU_MIPS_ABI_FP_SOFT
:
3999 if (!file_mips_opts
.soft_float
)
4000 fpabi_requires (fpabi
, "softfloat");
4003 case Val_GNU_MIPS_ABI_FP_OLD_64
:
4004 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
4005 Tag_GNU_MIPS_ABI_FP
, fpabi
);
4008 case Val_GNU_MIPS_ABI_FP_NAN2008
:
4009 /* Silently ignore compatibility value. */
4013 as_warn (_(".gnu_attribute %d,%d is not a recognized"
4014 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
4019 /* Perform consistency checks on the current options. */
4022 mips_check_options (struct mips_set_options
*opts
, bool abi_checks
)
4024 /* Check the size of integer registers agrees with the ABI and ISA. */
4025 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
4026 as_bad (_("`gp=64' used with a 32-bit processor"));
4028 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4029 as_bad (_("`gp=32' used with a 64-bit ABI"));
4031 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
4032 as_bad (_("`gp=64' used with a 32-bit ABI"));
4034 /* Check the size of the float registers agrees with the ABI and ISA. */
4038 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
4039 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4040 else if (opts
->single_float
== 1)
4041 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4044 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
4045 as_bad (_("`fp=64' used with a 32-bit fpu"));
4047 && ABI_NEEDS_32BIT_REGS (mips_abi
)
4048 && !ISA_HAS_MXHC1 (opts
->isa
))
4049 as_warn (_("`fp=64' used with a 32-bit ABI"));
4053 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4054 as_warn (_("`fp=32' used with a 64-bit ABI"));
4055 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
4056 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4059 as_bad (_("Unknown size of floating point registers"));
4063 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
4064 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4066 if (opts
->micromips
== 1 && opts
->mips16
== 1)
4067 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4068 else if (ISA_IS_R6 (opts
->isa
)
4069 && (opts
->micromips
== 1
4070 || opts
->mips16
== 1))
4071 as_fatal (_("`%s' cannot be used with `%s'"),
4072 opts
->micromips
? "micromips" : "mips16",
4073 mips_cpu_info_from_isa (opts
->isa
)->name
);
4075 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4076 as_fatal (_("branch relaxation is not supported in `%s'"),
4077 mips_cpu_info_from_isa (opts
->isa
)->name
);
4080 /* Perform consistency checks on the module level options exactly once.
4081 This is a deferred check that happens:
4082 at the first .set directive
4083 or, at the first pseudo op that generates code (inc .dc.a)
4084 or, at the first instruction
4088 file_mips_check_options (void)
4090 if (file_mips_opts_checked
)
4093 /* The following code determines the register size.
4094 Similar code was added to GCC 3.3 (see override_options() in
4095 config/mips/mips.c). The GAS and GCC code should be kept in sync
4096 as much as possible. */
4098 if (file_mips_opts
.gp
< 0)
4100 /* Infer the integer register size from the ABI and processor.
4101 Restrict ourselves to 32-bit registers if that's all the
4102 processor has, or if the ABI cannot handle 64-bit registers. */
4103 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4104 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4108 if (file_mips_opts
.fp
< 0)
4110 /* No user specified float register size.
4111 ??? GAS treats single-float processors as though they had 64-bit
4112 float registers (although it complains when double-precision
4113 instructions are used). As things stand, saying they have 32-bit
4114 registers would lead to spurious "register must be even" messages.
4115 So here we assume float registers are never smaller than the
4117 if (file_mips_opts
.gp
== 64)
4118 /* 64-bit integer registers implies 64-bit float registers. */
4119 file_mips_opts
.fp
= 64;
4120 else if ((file_mips_opts
.ase
& FP64_ASES
)
4121 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4122 /* Handle ASEs that require 64-bit float registers, if possible. */
4123 file_mips_opts
.fp
= 64;
4124 else if (ISA_IS_R6 (mips_opts
.isa
))
4125 /* R6 implies 64-bit float registers. */
4126 file_mips_opts
.fp
= 64;
4128 /* 32-bit float registers. */
4129 file_mips_opts
.fp
= 32;
4132 /* Disable operations on odd-numbered floating-point registers by default
4133 when using the FPXX ABI. */
4134 if (file_mips_opts
.oddspreg
< 0)
4136 if (file_mips_opts
.fp
== 0)
4137 file_mips_opts
.oddspreg
= 0;
4139 file_mips_opts
.oddspreg
= 1;
4142 /* End of GCC-shared inference code. */
4144 /* This flag is set when we have a 64-bit capable CPU but use only
4145 32-bit wide registers. Note that EABI does not use it. */
4146 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4147 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4148 || mips_abi
== O32_ABI
))
4151 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4152 as_bad (_("trap exception not supported at ISA 1"));
4154 /* If the selected architecture includes support for ASEs, enable
4155 generation of code for them. */
4156 if (file_mips_opts
.mips16
== -1)
4157 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4158 if (file_mips_opts
.micromips
== -1)
4159 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4162 if (mips_nan2008
== -1)
4163 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4164 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4165 as_fatal (_("`%s' does not support legacy NaN"),
4166 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4168 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4169 being selected implicitly. */
4170 if (file_mips_opts
.fp
!= 64)
4171 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4173 /* If the user didn't explicitly select or deselect a particular ASE,
4174 use the default setting for the CPU. */
4175 file_mips_opts
.ase
|= (file_mips_opts
.init_ase
& ~file_ase_explicit
);
4177 /* Set up the current options. These may change throughout assembly. */
4178 mips_opts
= file_mips_opts
;
4180 mips_check_isa_supports_ases ();
4181 mips_check_options (&file_mips_opts
, true);
4182 file_mips_opts_checked
= true;
4184 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4185 as_warn (_("could not set architecture and machine"));
4189 md_assemble (char *str
)
4191 struct mips_cl_insn insn
;
4192 bfd_reloc_code_real_type unused_reloc
[3]
4193 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4195 file_mips_check_options ();
4197 imm_expr
.X_op
= O_absent
;
4198 offset_expr
.X_op
= O_absent
;
4199 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4200 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4201 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4203 mips_mark_labels ();
4204 mips_assembling_insn
= true;
4205 clear_insn_error ();
4207 if (mips_opts
.mips16
)
4208 mips16_ip (str
, &insn
);
4211 mips_ip (str
, &insn
);
4212 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4213 str
, insn
.insn_opcode
));
4217 report_insn_error (str
);
4218 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4221 if (mips_opts
.mips16
)
4222 mips16_macro (&insn
);
4229 if (offset_expr
.X_op
!= O_absent
)
4230 append_insn (&insn
, &offset_expr
, offset_reloc
, false);
4232 append_insn (&insn
, NULL
, unused_reloc
, false);
4235 mips_assembling_insn
= false;
4238 /* Convenience functions for abstracting away the differences between
4239 MIPS16 and non-MIPS16 relocations. */
4242 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4246 case BFD_RELOC_MIPS16_JMP
:
4247 case BFD_RELOC_MIPS16_GPREL
:
4248 case BFD_RELOC_MIPS16_GOT16
:
4249 case BFD_RELOC_MIPS16_CALL16
:
4250 case BFD_RELOC_MIPS16_HI16_S
:
4251 case BFD_RELOC_MIPS16_HI16
:
4252 case BFD_RELOC_MIPS16_LO16
:
4253 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4262 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4266 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4267 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4268 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4269 case BFD_RELOC_MICROMIPS_GPREL16
:
4270 case BFD_RELOC_MICROMIPS_JMP
:
4271 case BFD_RELOC_MICROMIPS_HI16
:
4272 case BFD_RELOC_MICROMIPS_HI16_S
:
4273 case BFD_RELOC_MICROMIPS_LO16
:
4274 case BFD_RELOC_MICROMIPS_LITERAL
:
4275 case BFD_RELOC_MICROMIPS_GOT16
:
4276 case BFD_RELOC_MICROMIPS_CALL16
:
4277 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4278 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4279 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4280 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4281 case BFD_RELOC_MICROMIPS_SUB
:
4282 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4283 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4284 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4285 case BFD_RELOC_MICROMIPS_HIGHEST
:
4286 case BFD_RELOC_MICROMIPS_HIGHER
:
4287 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4288 case BFD_RELOC_MICROMIPS_JALR
:
4297 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4299 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4303 b_reloc_p (bfd_reloc_code_real_type reloc
)
4305 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4306 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4307 || reloc
== BFD_RELOC_16_PCREL_S2
4308 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4309 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4310 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4311 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4315 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4317 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4318 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4322 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4324 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4325 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4329 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4331 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4332 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4336 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4338 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4342 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4344 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4345 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4348 /* Return true if RELOC is a PC-relative relocation that does not have
4349 full address range. */
4352 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4356 case BFD_RELOC_16_PCREL_S2
:
4357 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4358 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4359 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4360 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4361 case BFD_RELOC_MIPS_21_PCREL_S2
:
4362 case BFD_RELOC_MIPS_26_PCREL_S2
:
4363 case BFD_RELOC_MIPS_18_PCREL_S3
:
4364 case BFD_RELOC_MIPS_19_PCREL_S2
:
4367 case BFD_RELOC_32_PCREL
:
4368 case BFD_RELOC_HI16_S_PCREL
:
4369 case BFD_RELOC_LO16_PCREL
:
4370 return HAVE_64BIT_ADDRESSES
;
4377 /* Return true if the given relocation might need a matching %lo().
4378 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4379 need a matching %lo() when applied to local symbols. */
4382 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4384 return (HAVE_IN_PLACE_ADDENDS
4385 && (hi16_reloc_p (reloc
)
4386 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4387 all GOT16 relocations evaluate to "G". */
4388 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4391 /* Return the type of %lo() reloc needed by RELOC, given that
4392 reloc_needs_lo_p. */
4394 static inline bfd_reloc_code_real_type
4395 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4397 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4398 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4402 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4406 fixup_has_matching_lo_p (fixS
*fixp
)
4408 return (fixp
->fx_next
!= NULL
4409 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4410 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4411 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4414 /* Move all labels in LABELS to the current insertion point. TEXT_P
4415 says whether the labels refer to text or data. */
4418 mips_move_labels (struct insn_label_list
*labels
, bool text_p
)
4420 struct insn_label_list
*l
;
4423 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4425 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4426 symbol_set_frag (l
->label
, frag_now
);
4427 val
= (valueT
) frag_now_fix ();
4428 /* MIPS16/microMIPS text labels are stored as odd.
4429 We just carry the ISA mode bit forward. */
4430 if (text_p
&& HAVE_CODE_COMPRESSION
)
4431 val
|= (S_GET_VALUE (l
->label
) & 0x1);
4432 S_SET_VALUE (l
->label
, val
);
4436 /* Move all labels in insn_labels to the current insertion point
4437 and treat them as text labels. */
4440 mips_move_text_labels (void)
4442 mips_move_labels (seg_info (now_seg
)->label_list
, true);
4445 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4448 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4450 bool linkonce
= false;
4451 segT symseg
= S_GET_SEGMENT (sym
);
4453 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4455 if ((bfd_section_flags (symseg
) & SEC_LINK_ONCE
))
4457 /* The GNU toolchain uses an extension for ELF: a section
4458 beginning with the magic string .gnu.linkonce is a
4459 linkonce section. */
4460 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4461 sizeof ".gnu.linkonce" - 1) == 0)
4467 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4468 linker to handle them specially, such as generating jalx instructions
4469 when needed. We also make them odd for the duration of the assembly,
4470 in order to generate the right sort of code. We will make them even
4471 in the adjust_symtab routine, while leaving them marked. This is
4472 convenient for the debugger and the disassembler. The linker knows
4473 to make them odd again. */
4476 mips_compressed_mark_label (symbolS
*label
)
4478 gas_assert (HAVE_CODE_COMPRESSION
);
4480 if (mips_opts
.mips16
)
4481 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4483 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4484 if ((S_GET_VALUE (label
) & 1) == 0
4485 /* Don't adjust the address if the label is global or weak, or
4486 in a link-once section, since we'll be emitting symbol reloc
4487 references to it which will be patched up by the linker, and
4488 the final value of the symbol may or may not be MIPS16/microMIPS. */
4489 && !S_IS_WEAK (label
)
4490 && !S_IS_EXTERNAL (label
)
4491 && !s_is_linkonce (label
, now_seg
))
4492 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4495 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4498 mips_compressed_mark_labels (void)
4500 struct insn_label_list
*l
;
4502 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4503 mips_compressed_mark_label (l
->label
);
4506 /* End the current frag. Make it a variant frag and record the
4510 relax_close_frag (void)
4512 mips_macro_warning
.first_frag
= frag_now
;
4513 frag_var (rs_machine_dependent
, 0, 0,
4514 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4515 mips_pic
!= NO_PIC
),
4516 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4518 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4519 mips_relax
.first_fixup
= 0;
4522 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4523 See the comment above RELAX_ENCODE for more details. */
4526 relax_start (symbolS
*symbol
)
4528 gas_assert (mips_relax
.sequence
== 0);
4529 mips_relax
.sequence
= 1;
4530 mips_relax
.symbol
= symbol
;
4533 /* Start generating the second version of a relaxable sequence.
4534 See the comment above RELAX_ENCODE for more details. */
4539 gas_assert (mips_relax
.sequence
== 1);
4540 mips_relax
.sequence
= 2;
4543 /* End the current relaxable sequence. */
4548 gas_assert (mips_relax
.sequence
== 2);
4549 relax_close_frag ();
4550 mips_relax
.sequence
= 0;
4553 /* Return true if IP is a delayed branch or jump. */
4556 delayed_branch_p (const struct mips_cl_insn
*ip
)
4558 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4559 | INSN_COND_BRANCH_DELAY
4560 | INSN_COND_BRANCH_LIKELY
)) != 0;
4563 /* Return true if IP is a compact branch or jump. */
4566 compact_branch_p (const struct mips_cl_insn
*ip
)
4568 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4569 | INSN2_COND_BRANCH
)) != 0;
4572 /* Return true if IP is an unconditional branch or jump. */
4575 uncond_branch_p (const struct mips_cl_insn
*ip
)
4577 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4578 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4581 /* Return true if IP is a branch-likely instruction. */
4584 branch_likely_p (const struct mips_cl_insn
*ip
)
4586 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4589 /* Return the type of nop that should be used to fill the delay slot
4590 of delayed branch IP. */
4592 static struct mips_cl_insn
*
4593 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4595 if (mips_opts
.micromips
4596 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4597 return µmips_nop32_insn
;
4601 /* Return a mask that has bit N set if OPCODE reads the register(s)
4605 insn_read_mask (const struct mips_opcode
*opcode
)
4607 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4610 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4614 insn_write_mask (const struct mips_opcode
*opcode
)
4616 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4619 /* Return a mask of the registers specified by operand OPERAND of INSN.
4620 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4624 operand_reg_mask (const struct mips_cl_insn
*insn
,
4625 const struct mips_operand
*operand
,
4626 unsigned int type_mask
)
4628 unsigned int uval
, vsel
;
4630 switch (operand
->type
)
4637 case OP_ADDIUSP_INT
:
4638 case OP_ENTRY_EXIT_LIST
:
4639 case OP_REPEAT_DEST_REG
:
4640 case OP_REPEAT_PREV_REG
:
4643 case OP_VU0_MATCH_SUFFIX
:
4651 case OP_OPTIONAL_REG
:
4653 const struct mips_reg_operand
*reg_op
;
4655 reg_op
= (const struct mips_reg_operand
*) operand
;
4656 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4658 uval
= insn_extract_operand (insn
, operand
);
4659 return 1u << mips_decode_reg_operand (reg_op
, uval
);
4664 const struct mips_reg_pair_operand
*pair_op
;
4666 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4667 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4669 uval
= insn_extract_operand (insn
, operand
);
4670 return (1u << pair_op
->reg1_map
[uval
]) | (1u << pair_op
->reg2_map
[uval
]);
4673 case OP_CLO_CLZ_DEST
:
4674 if (!(type_mask
& (1 << OP_REG_GP
)))
4676 uval
= insn_extract_operand (insn
, operand
);
4677 return (1u << (uval
& 31)) | (1u << (uval
>> 5));
4680 if (!(type_mask
& (1 << OP_REG_GP
)))
4682 uval
= insn_extract_operand (insn
, operand
);
4683 gas_assert ((uval
& 31) == (uval
>> 5));
4684 return 1u << (uval
& 31);
4687 case OP_NON_ZERO_REG
:
4688 if (!(type_mask
& (1 << OP_REG_GP
)))
4690 uval
= insn_extract_operand (insn
, operand
);
4691 return 1u << (uval
& 31);
4693 case OP_LWM_SWM_LIST
:
4696 case OP_SAVE_RESTORE_LIST
:
4699 case OP_MDMX_IMM_REG
:
4700 if (!(type_mask
& (1 << OP_REG_VEC
)))
4702 uval
= insn_extract_operand (insn
, operand
);
4704 if ((vsel
& 0x18) == 0x18)
4706 return 1u << (uval
& 31);
4709 if (!(type_mask
& (1 << OP_REG_GP
)))
4711 return 1u << insn_extract_operand (insn
, operand
);
4716 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4717 where bit N of OPNO_MASK is set if operand N should be included.
4718 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4722 insn_reg_mask (const struct mips_cl_insn
*insn
,
4723 unsigned int type_mask
, unsigned int opno_mask
)
4725 unsigned int opno
, reg_mask
;
4729 while (opno_mask
!= 0)
4732 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4739 /* Return the mask of core registers that IP reads. */
4742 gpr_read_mask (const struct mips_cl_insn
*ip
)
4744 unsigned long pinfo
, pinfo2
;
4747 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4748 pinfo
= ip
->insn_mo
->pinfo
;
4749 pinfo2
= ip
->insn_mo
->pinfo2
;
4750 if (pinfo
& INSN_UDI
)
4752 /* UDI instructions have traditionally been assumed to read RS
4754 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4755 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4757 if (pinfo
& INSN_READ_GPR_24
)
4759 if (pinfo2
& INSN2_READ_GPR_16
)
4761 if (pinfo2
& INSN2_READ_SP
)
4763 if (pinfo2
& INSN2_READ_GPR_31
)
4765 /* Don't include register 0. */
4769 /* Return the mask of core registers that IP writes. */
4772 gpr_write_mask (const struct mips_cl_insn
*ip
)
4774 unsigned long pinfo
, pinfo2
;
4777 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4778 pinfo
= ip
->insn_mo
->pinfo
;
4779 pinfo2
= ip
->insn_mo
->pinfo2
;
4780 if (pinfo
& INSN_WRITE_GPR_24
)
4782 if (pinfo
& INSN_WRITE_GPR_31
)
4784 if (pinfo
& INSN_UDI
)
4785 /* UDI instructions have traditionally been assumed to write to RD. */
4786 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4787 if (pinfo2
& INSN2_WRITE_SP
)
4789 /* Don't include register 0. */
4793 /* Return the mask of floating-point registers that IP reads. */
4796 fpr_read_mask (const struct mips_cl_insn
*ip
)
4798 unsigned long pinfo
;
4801 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4802 | (1 << OP_REG_MSA
)),
4803 insn_read_mask (ip
->insn_mo
));
4804 pinfo
= ip
->insn_mo
->pinfo
;
4805 /* Conservatively treat all operands to an FP_D instruction are doubles.
4806 (This is overly pessimistic for things like cvt.d.s.) */
4807 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4812 /* Return the mask of floating-point registers that IP writes. */
4815 fpr_write_mask (const struct mips_cl_insn
*ip
)
4817 unsigned long pinfo
;
4820 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4821 | (1 << OP_REG_MSA
)),
4822 insn_write_mask (ip
->insn_mo
));
4823 pinfo
= ip
->insn_mo
->pinfo
;
4824 /* Conservatively treat all operands to an FP_D instruction are doubles.
4825 (This is overly pessimistic for things like cvt.s.d.) */
4826 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4831 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4832 Check whether that is allowed. */
4835 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4837 const char *s
= insn
->name
;
4838 bool oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4839 || FPR_SIZE
== 64) && mips_opts
.oddspreg
;
4841 if (insn
->pinfo
== INSN_MACRO
)
4842 /* Let a macro pass, we'll catch it later when it is expanded. */
4845 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4846 otherwise it depends on oddspreg. */
4847 if ((insn
->pinfo
& FP_S
)
4848 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4849 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4850 return FPR_SIZE
== 32 || oddspreg
;
4852 /* Allow odd registers for single-precision ops and double-precision if the
4853 floating-point registers are 64-bit wide. */
4854 switch (insn
->pinfo
& (FP_S
| FP_D
))
4860 return FPR_SIZE
== 64;
4865 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4866 s
= strchr (insn
->name
, '.');
4867 if (s
!= NULL
&& opnum
== 2)
4868 s
= strchr (s
+ 1, '.');
4869 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4872 return FPR_SIZE
== 64;
4875 /* Information about an instruction argument that we're trying to match. */
4876 struct mips_arg_info
4878 /* The instruction so far. */
4879 struct mips_cl_insn
*insn
;
4881 /* The first unconsumed operand token. */
4882 struct mips_operand_token
*token
;
4884 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4887 /* The 1-based argument number, for error reporting. This does not
4888 count elided optional registers, etc.. */
4891 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4892 unsigned int last_regno
;
4894 /* If the first operand was an OP_REG, this is the register that it
4895 specified, otherwise it is ILLEGAL_REG. */
4896 unsigned int dest_regno
;
4898 /* The value of the last OP_INT operand. Only used for OP_MSB,
4899 where it gives the lsb position. */
4900 unsigned int last_op_int
;
4902 /* If true, match routines should assume that no later instruction
4903 alternative matches and should therefore be as accommodating as
4904 possible. Match routines should not report errors if something
4905 is only invalid for !LAX_MATCH. */
4908 /* True if a reference to the current AT register was seen. */
4912 /* Record that the argument is out of range. */
4915 match_out_of_range (struct mips_arg_info
*arg
)
4917 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4920 /* Record that the argument isn't constant but needs to be. */
4923 match_not_constant (struct mips_arg_info
*arg
)
4925 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4929 /* Try to match an OT_CHAR token for character CH. Consume the token
4930 and return true on success, otherwise return false. */
4933 match_char (struct mips_arg_info
*arg
, char ch
)
4935 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4945 /* Try to get an expression from the next tokens in ARG. Consume the
4946 tokens and return true on success, storing the expression value in
4947 VALUE and relocation types in R. */
4950 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4951 bfd_reloc_code_real_type
*r
)
4953 /* If the next token is a '(' that was parsed as being part of a base
4954 expression, assume we have an elided offset. The later match will fail
4955 if this turns out to be wrong. */
4956 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4958 value
->X_op
= O_constant
;
4959 value
->X_add_number
= 0;
4960 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4964 /* Reject register-based expressions such as "0+$2" and "(($2))".
4965 For plain registers the default error seems more appropriate. */
4966 if (arg
->token
->type
== OT_INTEGER
4967 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4969 set_insn_error (arg
->argnum
, _("register value used as expression"));
4973 if (arg
->token
->type
== OT_INTEGER
)
4975 *value
= arg
->token
->u
.integer
.value
;
4976 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4982 (arg
->argnum
, _("operand %d must be an immediate expression"),
4987 /* Try to get a constant expression from the next tokens in ARG. Consume
4988 the tokens and return true on success, storing the constant value
4992 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4995 bfd_reloc_code_real_type r
[3];
4997 if (!match_expression (arg
, &ex
, r
))
5000 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
5001 *value
= ex
.X_add_number
;
5004 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
5005 match_out_of_range (arg
);
5007 match_not_constant (arg
);
5013 /* Return the RTYPE_* flags for a register operand of type TYPE that
5014 appears in instruction OPCODE. */
5017 convert_reg_type (const struct mips_opcode
*opcode
,
5018 enum mips_reg_operand_type type
)
5023 return RTYPE_NUM
| RTYPE_GP
;
5026 /* Allow vector register names for MDMX if the instruction is a 64-bit
5027 FPR load, store or move (including moves to and from GPRs). */
5028 if ((mips_opts
.ase
& ASE_MDMX
)
5029 && (opcode
->pinfo
& FP_D
)
5030 && (opcode
->pinfo
& (INSN_COPROC_MOVE
5031 | INSN_COPROC_MEMORY_DELAY
5034 | INSN_STORE_MEMORY
)))
5035 return RTYPE_FPU
| RTYPE_VEC
;
5039 if (opcode
->pinfo
& (FP_D
| FP_S
))
5040 return RTYPE_CCC
| RTYPE_FCC
;
5044 if (opcode
->membership
& INSN_5400
)
5046 return RTYPE_FPU
| RTYPE_VEC
;
5052 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
5053 return RTYPE_NUM
| RTYPE_CP0
;
5060 return RTYPE_NUM
| RTYPE_VI
;
5063 return RTYPE_NUM
| RTYPE_VF
;
5065 case OP_REG_R5900_I
:
5066 return RTYPE_R5900_I
;
5068 case OP_REG_R5900_Q
:
5069 return RTYPE_R5900_Q
;
5071 case OP_REG_R5900_R
:
5072 return RTYPE_R5900_R
;
5074 case OP_REG_R5900_ACC
:
5075 return RTYPE_R5900_ACC
;
5080 case OP_REG_MSA_CTRL
:
5086 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5089 check_regno (struct mips_arg_info
*arg
,
5090 enum mips_reg_operand_type type
, unsigned int regno
)
5092 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5093 arg
->seen_at
= true;
5095 if (type
== OP_REG_FP
5097 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5099 /* This was a warning prior to introducing O32 FPXX and FP64 support
5100 so maintain a warning for FP32 but raise an error for the new
5103 as_warn (_("float register should be even, was %d"), regno
);
5105 as_bad (_("float register should be even, was %d"), regno
);
5108 if (type
== OP_REG_CCC
)
5113 name
= arg
->insn
->insn_mo
->name
;
5114 length
= strlen (name
);
5115 if ((regno
& 1) != 0
5116 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5117 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5118 as_warn (_("condition code register should be even for %s, was %d"),
5121 if ((regno
& 3) != 0
5122 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5123 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5128 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5129 a register of type TYPE. Return true on success, storing the register
5130 number in *REGNO and warning about any dubious uses. */
5133 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5134 unsigned int symval
, unsigned int *regno
)
5136 if (type
== OP_REG_VEC
)
5137 symval
= mips_prefer_vec_regno (symval
);
5138 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5141 *regno
= symval
& RNUM_MASK
;
5142 check_regno (arg
, type
, *regno
);
5146 /* Try to interpret the next token in ARG as a register of type TYPE.
5147 Consume the token and return true on success, storing the register
5148 number in *REGNO. Return false on failure. */
5151 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5152 unsigned int *regno
)
5154 if (arg
->token
->type
== OT_REG
5155 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5163 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5164 Consume the token and return true on success, storing the register numbers
5165 in *REGNO1 and *REGNO2. Return false on failure. */
5168 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5169 unsigned int *regno1
, unsigned int *regno2
)
5171 if (match_reg (arg
, type
, regno1
))
5176 if (arg
->token
->type
== OT_REG_RANGE
5177 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5178 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5179 && *regno1
<= *regno2
)
5187 /* OP_INT matcher. */
5190 match_int_operand (struct mips_arg_info
*arg
,
5191 const struct mips_operand
*operand_base
)
5193 const struct mips_int_operand
*operand
;
5195 int min_val
, max_val
, factor
;
5198 operand
= (const struct mips_int_operand
*) operand_base
;
5199 factor
= 1 << operand
->shift
;
5200 min_val
= mips_int_operand_min (operand
);
5201 max_val
= mips_int_operand_max (operand
);
5203 if (operand_base
->lsb
== 0
5204 && operand_base
->size
== 16
5205 && operand
->shift
== 0
5206 && operand
->bias
== 0
5207 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5209 /* The operand can be relocated. */
5210 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5213 if (offset_expr
.X_op
== O_big
)
5215 match_out_of_range (arg
);
5219 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5220 /* Relocation operators were used. Accept the argument and
5221 leave the relocation value in offset_expr and offset_relocs
5222 for the caller to process. */
5225 if (offset_expr
.X_op
!= O_constant
)
5227 /* Accept non-constant operands if no later alternative matches,
5228 leaving it for the caller to process. */
5229 if (!arg
->lax_match
)
5231 match_not_constant (arg
);
5234 offset_reloc
[0] = BFD_RELOC_LO16
;
5238 /* Clear the global state; we're going to install the operand
5240 sval
= offset_expr
.X_add_number
;
5241 offset_expr
.X_op
= O_absent
;
5243 /* For compatibility with older assemblers, we accept
5244 0x8000-0xffff as signed 16-bit numbers when only
5245 signed numbers are allowed. */
5248 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5249 if (!arg
->lax_match
&& sval
<= max_val
)
5251 match_out_of_range (arg
);
5258 if (!match_const_int (arg
, &sval
))
5262 arg
->last_op_int
= sval
;
5264 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5266 match_out_of_range (arg
);
5270 uval
= (unsigned int) sval
>> operand
->shift
;
5271 uval
-= operand
->bias
;
5273 /* Handle -mfix-cn63xxp1. */
5275 && mips_fix_cn63xxp1
5276 && !mips_opts
.micromips
5277 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5292 /* The rest must be changed to 28. */
5297 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5301 /* OP_MAPPED_INT matcher. */
5304 match_mapped_int_operand (struct mips_arg_info
*arg
,
5305 const struct mips_operand
*operand_base
)
5307 const struct mips_mapped_int_operand
*operand
;
5308 unsigned int uval
, num_vals
;
5311 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5312 if (!match_const_int (arg
, &sval
))
5315 num_vals
= 1 << operand_base
->size
;
5316 for (uval
= 0; uval
< num_vals
; uval
++)
5317 if (operand
->int_map
[uval
] == sval
)
5319 if (uval
== num_vals
)
5321 match_out_of_range (arg
);
5325 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5329 /* OP_MSB matcher. */
5332 match_msb_operand (struct mips_arg_info
*arg
,
5333 const struct mips_operand
*operand_base
)
5335 const struct mips_msb_operand
*operand
;
5336 int min_val
, max_val
, max_high
;
5337 offsetT size
, sval
, high
;
5339 operand
= (const struct mips_msb_operand
*) operand_base
;
5340 min_val
= operand
->bias
;
5341 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5342 max_high
= operand
->opsize
;
5344 if (!match_const_int (arg
, &size
))
5347 high
= size
+ arg
->last_op_int
;
5348 sval
= operand
->add_lsb
? high
: size
;
5350 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5352 match_out_of_range (arg
);
5355 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5359 /* OP_REG matcher. */
5362 match_reg_operand (struct mips_arg_info
*arg
,
5363 const struct mips_operand
*operand_base
)
5365 const struct mips_reg_operand
*operand
;
5366 unsigned int regno
, uval
, num_vals
;
5368 operand
= (const struct mips_reg_operand
*) operand_base
;
5369 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5372 if (operand
->reg_map
)
5374 num_vals
= 1 << operand
->root
.size
;
5375 for (uval
= 0; uval
< num_vals
; uval
++)
5376 if (operand
->reg_map
[uval
] == regno
)
5378 if (num_vals
== uval
)
5384 arg
->last_regno
= regno
;
5385 if (arg
->opnum
== 1)
5386 arg
->dest_regno
= regno
;
5387 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5391 /* OP_REG_PAIR matcher. */
5394 match_reg_pair_operand (struct mips_arg_info
*arg
,
5395 const struct mips_operand
*operand_base
)
5397 const struct mips_reg_pair_operand
*operand
;
5398 unsigned int regno1
, regno2
, uval
, num_vals
;
5400 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5401 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5402 || !match_char (arg
, ',')
5403 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5406 num_vals
= 1 << operand_base
->size
;
5407 for (uval
= 0; uval
< num_vals
; uval
++)
5408 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5410 if (uval
== num_vals
)
5413 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5417 /* OP_PCREL matcher. The caller chooses the relocation type. */
5420 match_pcrel_operand (struct mips_arg_info
*arg
)
5422 bfd_reloc_code_real_type r
[3];
5424 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5427 /* OP_PERF_REG matcher. */
5430 match_perf_reg_operand (struct mips_arg_info
*arg
,
5431 const struct mips_operand
*operand
)
5435 if (!match_const_int (arg
, &sval
))
5440 || (mips_opts
.arch
== CPU_R5900
5441 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5442 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5444 set_insn_error (arg
->argnum
, _("invalid performance register"));
5448 insn_insert_operand (arg
->insn
, operand
, sval
);
5452 /* OP_ADDIUSP matcher. */
5455 match_addiusp_operand (struct mips_arg_info
*arg
,
5456 const struct mips_operand
*operand
)
5461 if (!match_const_int (arg
, &sval
))
5466 match_out_of_range (arg
);
5471 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5473 match_out_of_range (arg
);
5477 uval
= (unsigned int) sval
;
5478 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5479 insn_insert_operand (arg
->insn
, operand
, uval
);
5483 /* OP_CLO_CLZ_DEST matcher. */
5486 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5487 const struct mips_operand
*operand
)
5491 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5494 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5498 /* OP_CHECK_PREV matcher. */
5501 match_check_prev_operand (struct mips_arg_info
*arg
,
5502 const struct mips_operand
*operand_base
)
5504 const struct mips_check_prev_operand
*operand
;
5507 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5509 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5512 if (!operand
->zero_ok
&& regno
== 0)
5515 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5516 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5517 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5519 arg
->last_regno
= regno
;
5520 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5527 /* OP_SAME_RS_RT matcher. */
5530 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5531 const struct mips_operand
*operand
)
5535 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5540 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5544 arg
->last_regno
= regno
;
5546 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5550 /* OP_LWM_SWM_LIST matcher. */
5553 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5554 const struct mips_operand
*operand
)
5556 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5557 struct mips_arg_info reset
;
5560 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5564 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5569 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5572 while (match_char (arg
, ',')
5573 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5576 if (operand
->size
== 2)
5578 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5584 and any permutations of these. */
5585 if ((reglist
& 0xfff1ffff) != 0x80010000)
5588 sregs
= (reglist
>> 17) & 7;
5593 /* The list must include at least one of ra and s0-sN,
5594 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5595 which are $23 and $30 respectively.) E.g.:
5603 and any permutations of these. */
5604 if ((reglist
& 0x3f00ffff) != 0)
5607 ra
= (reglist
>> 27) & 0x10;
5608 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5611 if ((sregs
& -sregs
) != sregs
)
5614 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5618 /* OP_ENTRY_EXIT_LIST matcher. */
5621 match_entry_exit_operand (struct mips_arg_info
*arg
,
5622 const struct mips_operand
*operand
)
5627 /* The format is the same for both ENTRY and EXIT, but the constraints
5629 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5630 mask
= (is_exit
? 7 << 3 : 0);
5633 unsigned int regno1
, regno2
;
5636 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5638 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5643 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5646 mask
|= (5 + regno2
) << 3;
5648 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5649 mask
|= (regno2
- 3) << 3;
5650 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5651 mask
|= (regno2
- 15) << 1;
5652 else if (regno1
== RA
&& regno2
== RA
)
5657 while (match_char (arg
, ','));
5659 insn_insert_operand (arg
->insn
, operand
, mask
);
5663 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5664 the argument register mask AMASK, the number of static registers
5665 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5666 respectively, and the frame size FRAME_SIZE. */
5669 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5670 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5671 unsigned int frame_size
)
5673 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5674 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5677 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5678 argument register mask AMASK, the number of static registers saved
5679 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5680 respectively, and the frame size FRAME_SIZE. */
5683 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5684 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5685 unsigned int frame_size
)
5689 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5690 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5691 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5692 | ((frame_size
& 0xf0) << 16));
5696 /* OP_SAVE_RESTORE_LIST matcher. */
5699 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5701 unsigned int opcode
, args
, statics
, sregs
;
5702 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5703 unsigned int arg_mask
, ra
, s0
, s1
;
5706 opcode
= arg
->insn
->insn_opcode
;
5708 num_frame_sizes
= 0;
5717 unsigned int regno1
, regno2
;
5719 if (arg
->token
->type
== OT_INTEGER
)
5721 /* Handle the frame size. */
5722 if (!match_const_int (arg
, &frame_size
))
5724 num_frame_sizes
+= 1;
5728 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5731 while (regno1
<= regno2
)
5733 if (regno1
>= 4 && regno1
<= 7)
5735 if (num_frame_sizes
== 0)
5737 args
|= 1 << (regno1
- 4);
5739 /* statics $a0-$a3 */
5740 statics
|= 1 << (regno1
- 4);
5742 else if (regno1
>= 16 && regno1
<= 23)
5744 sregs
|= 1 << (regno1
- 16);
5745 else if (regno1
== 30)
5748 else if (regno1
== 31)
5749 /* Add $ra to insn. */
5759 while (match_char (arg
, ','));
5761 /* Encode args/statics combination. */
5764 else if (args
== 0xf)
5765 /* All $a0-$a3 are args. */
5766 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5767 else if (statics
== 0xf)
5768 /* All $a0-$a3 are statics. */
5769 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5772 /* Count arg registers. */
5782 /* Count static registers. */
5784 while (statics
& 0x8)
5786 statics
= (statics
<< 1) & 0xf;
5792 /* Encode args/statics. */
5793 arg_mask
= (num_args
<< 2) | num_statics
;
5796 /* Encode $s0/$s1. */
5797 if (sregs
& (1 << 0)) /* $s0 */
5799 if (sregs
& (1 << 1)) /* $s1 */
5803 /* Encode $s2-$s8. */
5813 /* Encode frame size. */
5814 if (num_frame_sizes
== 0)
5816 set_insn_error (arg
->argnum
, _("missing frame size"));
5819 if (num_frame_sizes
> 1)
5821 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5824 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5826 set_insn_error (arg
->argnum
, _("invalid frame size"));
5831 /* Finally build the instruction. */
5832 if (mips_opts
.mips16
)
5833 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5835 else if (!mips_opts
.micromips
)
5836 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5841 arg
->insn
->insn_opcode
= opcode
;
5845 /* OP_MDMX_IMM_REG matcher. */
5848 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5849 const struct mips_operand
*operand
)
5851 unsigned int regno
, uval
;
5853 const struct mips_opcode
*opcode
;
5855 /* The mips_opcode records whether this is an octobyte or quadhalf
5856 instruction. Start out with that bit in place. */
5857 opcode
= arg
->insn
->insn_mo
;
5858 uval
= mips_extract_operand (operand
, opcode
->match
);
5859 is_qh
= (uval
!= 0);
5861 if (arg
->token
->type
== OT_REG
)
5863 if ((opcode
->membership
& INSN_5400
)
5864 && strcmp (opcode
->name
, "rzu.ob") == 0)
5866 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5871 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5875 /* Check whether this is a vector register or a broadcast of
5876 a single element. */
5877 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5879 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5881 set_insn_error (arg
->argnum
, _("invalid element selector"));
5884 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5889 /* A full vector. */
5890 if ((opcode
->membership
& INSN_5400
)
5891 && (strcmp (opcode
->name
, "sll.ob") == 0
5892 || strcmp (opcode
->name
, "srl.ob") == 0))
5894 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5900 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5902 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5910 if (!match_const_int (arg
, &sval
))
5912 if (sval
< 0 || sval
> 31)
5914 match_out_of_range (arg
);
5917 uval
|= (sval
& 31);
5919 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5921 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5923 insn_insert_operand (arg
->insn
, operand
, uval
);
5927 /* OP_IMM_INDEX matcher. */
5930 match_imm_index_operand (struct mips_arg_info
*arg
,
5931 const struct mips_operand
*operand
)
5933 unsigned int max_val
;
5935 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5938 max_val
= (1 << operand
->size
) - 1;
5939 if (arg
->token
->u
.index
> max_val
)
5941 match_out_of_range (arg
);
5944 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5949 /* OP_REG_INDEX matcher. */
5952 match_reg_index_operand (struct mips_arg_info
*arg
,
5953 const struct mips_operand
*operand
)
5957 if (arg
->token
->type
!= OT_REG_INDEX
)
5960 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5963 insn_insert_operand (arg
->insn
, operand
, regno
);
5968 /* OP_PC matcher. */
5971 match_pc_operand (struct mips_arg_info
*arg
)
5973 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5981 /* OP_REG28 matcher. */
5984 match_reg28_operand (struct mips_arg_info
*arg
)
5988 if (arg
->token
->type
== OT_REG
5989 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
5998 /* OP_NON_ZERO_REG matcher. */
6001 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
6002 const struct mips_operand
*operand
)
6006 if (!match_reg (arg
, OP_REG_GP
, ®no
))
6011 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
6015 arg
->last_regno
= regno
;
6016 insn_insert_operand (arg
->insn
, operand
, regno
);
6020 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
6021 register that we need to match. */
6024 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
6028 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
6031 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
6032 LENGTH is the length of the value in bytes (4 for float, 8 for double)
6033 and USING_GPRS says whether the destination is a GPR rather than an FPR.
6035 Return the constant in IMM and OFFSET as follows:
6037 - If the constant should be loaded via memory, set IMM to O_absent and
6038 OFFSET to the memory address.
6040 - Otherwise, if the constant should be loaded into two 32-bit registers,
6041 set IMM to the O_constant to load into the high register and OFFSET
6042 to the corresponding value for the low register.
6044 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6046 These constants only appear as the last operand in an instruction,
6047 and every instruction that accepts them in any variant accepts them
6048 in all variants. This means we don't have to worry about backing out
6049 any changes if the instruction does not match. We just match
6050 unconditionally and report an error if the constant is invalid. */
6053 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
6054 expressionS
*offset
, int length
, bool using_gprs
)
6059 const char *newname
;
6060 unsigned char *data
;
6062 /* Where the constant is placed is based on how the MIPS assembler
6065 length == 4 && using_gprs -- immediate value only
6066 length == 8 && using_gprs -- .rdata or immediate value
6067 length == 4 && !using_gprs -- .lit4 or immediate value
6068 length == 8 && !using_gprs -- .lit8 or immediate value
6070 The .lit4 and .lit8 sections are only used if permitted by the
6072 if (arg
->token
->type
!= OT_FLOAT
)
6074 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6078 gas_assert (arg
->token
->u
.flt
.length
== length
);
6079 data
= arg
->token
->u
.flt
.data
;
6082 /* Handle 32-bit constants for which an immediate value is best. */
6085 || g_switch_value
< 4
6086 || (data
[0] == 0 && data
[1] == 0)
6087 || (data
[2] == 0 && data
[3] == 0)))
6089 imm
->X_op
= O_constant
;
6090 if (!target_big_endian
)
6091 imm
->X_add_number
= bfd_getl32 (data
);
6093 imm
->X_add_number
= bfd_getb32 (data
);
6094 offset
->X_op
= O_absent
;
6098 /* Handle 64-bit constants for which an immediate value is best. */
6100 && !mips_disable_float_construction
6101 /* Constants can only be constructed in GPRs and copied to FPRs if the
6102 GPRs are at least as wide as the FPRs or MTHC1 is available.
6103 Unlike most tests for 32-bit floating-point registers this check
6104 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6105 permit 64-bit moves without MXHC1.
6106 Force the constant into memory otherwise. */
6109 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6111 && ((data
[0] == 0 && data
[1] == 0)
6112 || (data
[2] == 0 && data
[3] == 0))
6113 && ((data
[4] == 0 && data
[5] == 0)
6114 || (data
[6] == 0 && data
[7] == 0)))
6116 /* The value is simple enough to load with a couple of instructions.
6117 If using 32-bit registers, set IMM to the high order 32 bits and
6118 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6120 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6122 imm
->X_op
= O_constant
;
6123 offset
->X_op
= O_constant
;
6124 if (!target_big_endian
)
6126 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6127 offset
->X_add_number
= bfd_getl32 (data
);
6131 imm
->X_add_number
= bfd_getb32 (data
);
6132 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6134 if (offset
->X_add_number
== 0)
6135 offset
->X_op
= O_absent
;
6139 imm
->X_op
= O_constant
;
6140 if (!target_big_endian
)
6141 imm
->X_add_number
= bfd_getl64 (data
);
6143 imm
->X_add_number
= bfd_getb64 (data
);
6144 offset
->X_op
= O_absent
;
6149 /* Switch to the right section. */
6151 subseg
= now_subseg
;
6154 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6159 if (using_gprs
|| g_switch_value
< 8)
6160 newname
= RDATA_SECTION_NAME
;
6165 new_seg
= subseg_new (newname
, (subsegT
) 0);
6166 bfd_set_section_flags (new_seg
,
6167 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6168 frag_align (length
== 4 ? 2 : 3, 0, 0);
6169 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6170 record_alignment (new_seg
, 4);
6172 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6174 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6176 /* Set the argument to the current address in the section. */
6177 imm
->X_op
= O_absent
;
6178 offset
->X_op
= O_symbol
;
6179 offset
->X_add_symbol
= symbol_temp_new_now ();
6180 offset
->X_add_number
= 0;
6182 /* Put the floating point number into the section. */
6183 p
= frag_more (length
);
6184 memcpy (p
, data
, length
);
6186 /* Switch back to the original section. */
6187 subseg_set (seg
, subseg
);
6191 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6195 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6196 const struct mips_operand
*operand
,
6201 /* The operand can be an XYZW mask or a single 2-bit channel index
6202 (with X being 0). */
6203 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6205 /* The suffix can be omitted when it is already part of the opcode. */
6206 if (arg
->token
->type
!= OT_CHANNELS
)
6209 uval
= arg
->token
->u
.channels
;
6210 if (operand
->size
== 2)
6212 /* Check that a single bit is set and convert it into a 2-bit index. */
6213 if ((uval
& -uval
) != uval
)
6215 uval
= 4 - ffs (uval
);
6218 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6223 insn_insert_operand (arg
->insn
, operand
, uval
);
6227 /* Try to match a token from ARG against OPERAND. Consume the token
6228 and return true on success, otherwise return false. */
6231 match_operand (struct mips_arg_info
*arg
,
6232 const struct mips_operand
*operand
)
6234 switch (operand
->type
)
6237 return match_int_operand (arg
, operand
);
6240 return match_mapped_int_operand (arg
, operand
);
6243 return match_msb_operand (arg
, operand
);
6246 case OP_OPTIONAL_REG
:
6247 return match_reg_operand (arg
, operand
);
6250 return match_reg_pair_operand (arg
, operand
);
6253 return match_pcrel_operand (arg
);
6256 return match_perf_reg_operand (arg
, operand
);
6258 case OP_ADDIUSP_INT
:
6259 return match_addiusp_operand (arg
, operand
);
6261 case OP_CLO_CLZ_DEST
:
6262 return match_clo_clz_dest_operand (arg
, operand
);
6264 case OP_LWM_SWM_LIST
:
6265 return match_lwm_swm_list_operand (arg
, operand
);
6267 case OP_ENTRY_EXIT_LIST
:
6268 return match_entry_exit_operand (arg
, operand
);
6270 case OP_SAVE_RESTORE_LIST
:
6271 return match_save_restore_list_operand (arg
);
6273 case OP_MDMX_IMM_REG
:
6274 return match_mdmx_imm_reg_operand (arg
, operand
);
6276 case OP_REPEAT_DEST_REG
:
6277 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6279 case OP_REPEAT_PREV_REG
:
6280 return match_tied_reg_operand (arg
, arg
->last_regno
);
6283 return match_pc_operand (arg
);
6286 return match_reg28_operand (arg
);
6289 return match_vu0_suffix_operand (arg
, operand
, false);
6291 case OP_VU0_MATCH_SUFFIX
:
6292 return match_vu0_suffix_operand (arg
, operand
, true);
6295 return match_imm_index_operand (arg
, operand
);
6298 return match_reg_index_operand (arg
, operand
);
6301 return match_same_rs_rt_operand (arg
, operand
);
6304 return match_check_prev_operand (arg
, operand
);
6306 case OP_NON_ZERO_REG
:
6307 return match_non_zero_reg_operand (arg
, operand
);
6312 /* ARG is the state after successfully matching an instruction.
6313 Issue any queued-up warnings. */
6316 check_completed_insn (struct mips_arg_info
*arg
)
6321 as_warn (_("used $at without \".set noat\""));
6323 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6327 /* Return true if modifying general-purpose register REG needs a delay. */
6330 reg_needs_delay (unsigned int reg
)
6332 unsigned long prev_pinfo
;
6334 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6335 if (!mips_opts
.noreorder
6336 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6337 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6338 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6344 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6345 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6346 by VR4120 errata. */
6349 classify_vr4120_insn (const char *name
)
6351 if (strncmp (name
, "macc", 4) == 0)
6352 return FIX_VR4120_MACC
;
6353 if (strncmp (name
, "dmacc", 5) == 0)
6354 return FIX_VR4120_DMACC
;
6355 if (strncmp (name
, "mult", 4) == 0)
6356 return FIX_VR4120_MULT
;
6357 if (strncmp (name
, "dmult", 5) == 0)
6358 return FIX_VR4120_DMULT
;
6359 if (strstr (name
, "div"))
6360 return FIX_VR4120_DIV
;
6361 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6362 return FIX_VR4120_MTHILO
;
6363 return NUM_FIX_VR4120_CLASSES
;
6366 #define INSN_ERET 0x42000018
6367 #define INSN_DERET 0x4200001f
6368 #define INSN_DMULT 0x1c
6369 #define INSN_DMULTU 0x1d
6371 /* Return the number of instructions that must separate INSN1 and INSN2,
6372 where INSN1 is the earlier instruction. Return the worst-case value
6373 for any INSN2 if INSN2 is null. */
6376 insns_between (const struct mips_cl_insn
*insn1
,
6377 const struct mips_cl_insn
*insn2
)
6379 unsigned long pinfo1
, pinfo2
;
6382 /* If INFO2 is null, pessimistically assume that all flags are set for
6383 the second instruction. */
6384 pinfo1
= insn1
->insn_mo
->pinfo
;
6385 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6387 /* For most targets, write-after-read dependencies on the HI and LO
6388 registers must be separated by at least two instructions. */
6389 if (!hilo_interlocks
)
6391 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6393 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6397 /* If we're working around r7000 errata, there must be two instructions
6398 between an mfhi or mflo and any instruction that uses the result. */
6399 if (mips_7000_hilo_fix
6400 && !mips_opts
.micromips
6401 && MF_HILO_INSN (pinfo1
)
6402 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6405 /* If we're working around 24K errata, one instruction is required
6406 if an ERET or DERET is followed by a branch instruction. */
6407 if (mips_fix_24k
&& !mips_opts
.micromips
)
6409 if (insn1
->insn_opcode
== INSN_ERET
6410 || insn1
->insn_opcode
== INSN_DERET
)
6413 || insn2
->insn_opcode
== INSN_ERET
6414 || insn2
->insn_opcode
== INSN_DERET
6415 || delayed_branch_p (insn2
))
6420 /* If we're working around PMC RM7000 errata, there must be three
6421 nops between a dmult and a load instruction. */
6422 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6424 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6425 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6427 if (pinfo2
& INSN_LOAD_MEMORY
)
6432 /* If working around VR4120 errata, check for combinations that need
6433 a single intervening instruction. */
6434 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6436 unsigned int class1
, class2
;
6438 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6439 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6443 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6444 if (vr4120_conflicts
[class1
] & (1 << class2
))
6449 if (!HAVE_CODE_COMPRESSION
)
6451 /* Check for GPR or coprocessor load delays. All such delays
6452 are on the RT register. */
6453 /* Itbl support may require additional care here. */
6454 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6455 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6457 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6461 /* Check for generic coprocessor hazards.
6463 This case is not handled very well. There is no special
6464 knowledge of CP0 handling, and the coprocessors other than
6465 the floating point unit are not distinguished at all. */
6466 /* Itbl support may require additional care here. FIXME!
6467 Need to modify this to include knowledge about
6468 user specified delays! */
6469 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6470 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6472 /* Handle cases where INSN1 writes to a known general coprocessor
6473 register. There must be a one instruction delay before INSN2
6474 if INSN2 reads that register, otherwise no delay is needed. */
6475 mask
= fpr_write_mask (insn1
);
6478 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6483 /* Read-after-write dependencies on the control registers
6484 require a two-instruction gap. */
6485 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6486 && (pinfo2
& INSN_READ_COND_CODE
))
6489 /* We don't know exactly what INSN1 does. If INSN2 is
6490 also a coprocessor instruction, assume there must be
6491 a one instruction gap. */
6492 if (pinfo2
& INSN_COP
)
6497 /* Check for read-after-write dependencies on the coprocessor
6498 control registers in cases where INSN1 does not need a general
6499 coprocessor delay. This means that INSN1 is a floating point
6500 comparison instruction. */
6501 /* Itbl support may require additional care here. */
6502 else if (!cop_interlocks
6503 && (pinfo1
& INSN_WRITE_COND_CODE
)
6504 && (pinfo2
& INSN_READ_COND_CODE
))
6508 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6509 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6511 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6512 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6513 || (insn2
&& delayed_branch_p (insn2
))))
6519 /* Return the number of nops that would be needed to work around the
6520 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6521 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6522 that are contained within the first IGNORE instructions of HIST. */
6525 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6526 const struct mips_cl_insn
*insn
)
6531 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6532 are not affected by the errata. */
6534 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6535 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6536 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6539 /* Search for the first MFLO or MFHI. */
6540 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6541 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6543 /* Extract the destination register. */
6544 mask
= gpr_write_mask (&hist
[i
]);
6546 /* No nops are needed if INSN reads that register. */
6547 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6550 /* ...or if any of the intervening instructions do. */
6551 for (j
= 0; j
< i
; j
++)
6552 if (gpr_read_mask (&hist
[j
]) & mask
)
6556 return MAX_VR4130_NOPS
- i
;
6561 #define BASE_REG_EQ(INSN1, INSN2) \
6562 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6563 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6565 /* Return the minimum alignment for this store instruction. */
6568 fix_24k_align_to (const struct mips_opcode
*mo
)
6570 if (strcmp (mo
->name
, "sh") == 0)
6573 if (strcmp (mo
->name
, "swc1") == 0
6574 || strcmp (mo
->name
, "swc2") == 0
6575 || strcmp (mo
->name
, "sw") == 0
6576 || strcmp (mo
->name
, "sc") == 0
6577 || strcmp (mo
->name
, "s.s") == 0)
6580 if (strcmp (mo
->name
, "sdc1") == 0
6581 || strcmp (mo
->name
, "sdc2") == 0
6582 || strcmp (mo
->name
, "s.d") == 0)
6589 struct fix_24k_store_info
6591 /* Immediate offset, if any, for this store instruction. */
6593 /* Alignment required by this store instruction. */
6595 /* True for register offsets. */
6596 int register_offset
;
6599 /* Comparison function used by qsort. */
6602 fix_24k_sort (const void *a
, const void *b
)
6604 const struct fix_24k_store_info
*pos1
= a
;
6605 const struct fix_24k_store_info
*pos2
= b
;
6607 return (pos1
->off
- pos2
->off
);
6610 /* INSN is a store instruction. Try to record the store information
6611 in STINFO. Return false if the information isn't known. */
6614 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6615 const struct mips_cl_insn
*insn
)
6617 /* The instruction must have a known offset. */
6618 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6621 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6622 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6626 /* Return the number of nops that would be needed to work around the 24k
6627 "lost data on stores during refill" errata if instruction INSN
6628 immediately followed the 2 instructions described by HIST.
6629 Ignore hazards that are contained within the first IGNORE
6630 instructions of HIST.
6632 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6633 for the data cache refills and store data. The following describes
6634 the scenario where the store data could be lost.
6636 * A data cache miss, due to either a load or a store, causing fill
6637 data to be supplied by the memory subsystem
6638 * The first three doublewords of fill data are returned and written
6640 * A sequence of four stores occurs in consecutive cycles around the
6641 final doubleword of the fill:
6645 * Zero, One or more instructions
6648 The four stores A-D must be to different doublewords of the line that
6649 is being filled. The fourth instruction in the sequence above permits
6650 the fill of the final doubleword to be transferred from the FSB into
6651 the cache. In the sequence above, the stores may be either integer
6652 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6653 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6654 different doublewords on the line. If the floating point unit is
6655 running in 1:2 mode, it is not possible to create the sequence above
6656 using only floating point store instructions.
6658 In this case, the cache line being filled is incorrectly marked
6659 invalid, thereby losing the data from any store to the line that
6660 occurs between the original miss and the completion of the five
6661 cycle sequence shown above.
6663 The workarounds are:
6665 * Run the data cache in write-through mode.
6666 * Insert a non-store instruction between
6667 Store A and Store B or Store B and Store C. */
6670 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6671 const struct mips_cl_insn
*insn
)
6673 struct fix_24k_store_info pos
[3];
6674 int align
, i
, base_offset
;
6679 /* If the previous instruction wasn't a store, there's nothing to
6681 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6684 /* If the instructions after the previous one are unknown, we have
6685 to assume the worst. */
6689 /* Check whether we are dealing with three consecutive stores. */
6690 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6691 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6694 /* If we don't know the relationship between the store addresses,
6695 assume the worst. */
6696 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6697 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6700 if (!fix_24k_record_store_info (&pos
[0], insn
)
6701 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6702 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6705 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6707 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6708 X bytes and such that the base register + X is known to be aligned
6711 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6715 align
= pos
[0].align_to
;
6716 base_offset
= pos
[0].off
;
6717 for (i
= 1; i
< 3; i
++)
6718 if (align
< pos
[i
].align_to
)
6720 align
= pos
[i
].align_to
;
6721 base_offset
= pos
[i
].off
;
6723 for (i
= 0; i
< 3; i
++)
6724 pos
[i
].off
-= base_offset
;
6727 pos
[0].off
&= ~align
+ 1;
6728 pos
[1].off
&= ~align
+ 1;
6729 pos
[2].off
&= ~align
+ 1;
6731 /* If any two stores write to the same chunk, they also write to the
6732 same doubleword. The offsets are still sorted at this point. */
6733 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6736 /* A range of at least 9 bytes is needed for the stores to be in
6737 non-overlapping doublewords. */
6738 if (pos
[2].off
- pos
[0].off
<= 8)
6741 if (pos
[2].off
- pos
[1].off
>= 24
6742 || pos
[1].off
- pos
[0].off
>= 24
6743 || pos
[2].off
- pos
[0].off
>= 32)
6749 /* Return the number of nops that would be needed if instruction INSN
6750 immediately followed the MAX_NOPS instructions given by HIST,
6751 where HIST[0] is the most recent instruction. Ignore hazards
6752 between INSN and the first IGNORE instructions in HIST.
6754 If INSN is null, return the worse-case number of nops for any
6758 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6759 const struct mips_cl_insn
*insn
)
6761 int i
, nops
, tmp_nops
;
6764 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6766 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6767 if (tmp_nops
> nops
)
6771 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6773 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6774 if (tmp_nops
> nops
)
6778 if (mips_fix_24k
&& !mips_opts
.micromips
)
6780 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6781 if (tmp_nops
> nops
)
6788 /* The variable arguments provide NUM_INSNS extra instructions that
6789 might be added to HIST. Return the largest number of nops that
6790 would be needed after the extended sequence, ignoring hazards
6791 in the first IGNORE instructions. */
6794 nops_for_sequence (int num_insns
, int ignore
,
6795 const struct mips_cl_insn
*hist
, ...)
6798 struct mips_cl_insn buffer
[MAX_NOPS
];
6799 struct mips_cl_insn
*cursor
;
6802 va_start (args
, hist
);
6803 cursor
= buffer
+ num_insns
;
6804 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6805 while (cursor
> buffer
)
6806 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6808 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6813 /* Like nops_for_insn, but if INSN is a branch, take into account the
6814 worst-case delay for the branch target. */
6817 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6818 const struct mips_cl_insn
*insn
)
6822 nops
= nops_for_insn (ignore
, hist
, insn
);
6823 if (delayed_branch_p (insn
))
6825 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6826 hist
, insn
, get_delay_slot_nop (insn
));
6827 if (tmp_nops
> nops
)
6830 else if (compact_branch_p (insn
))
6832 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6833 if (tmp_nops
> nops
)
6839 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6842 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6844 gas_assert (!HAVE_CODE_COMPRESSION
);
6845 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6846 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6849 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6850 jr target pc &= 'hffff_ffff_cfff_ffff. */
6853 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6855 gas_assert (!HAVE_CODE_COMPRESSION
);
6856 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6857 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6858 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6866 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6867 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6870 ep
.X_op
= O_constant
;
6871 ep
.X_add_number
= 0xcfff0000;
6872 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6873 ep
.X_add_number
= 0xffff;
6874 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6875 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6880 fix_loongson2f (struct mips_cl_insn
* ip
)
6882 if (mips_fix_loongson2f_nop
)
6883 fix_loongson2f_nop (ip
);
6885 if (mips_fix_loongson2f_jump
)
6886 fix_loongson2f_jump (ip
);
6890 has_label_name (const char *arr
[], size_t len
,const char *s
)
6893 for (i
= 0; i
< len
; i
++)
6897 if (streq (arr
[i
], s
))
6903 /* Fix loongson3 llsc errata: Insert sync before ll/lld. */
6906 fix_loongson3_llsc (struct mips_cl_insn
* ip
)
6908 gas_assert (!HAVE_CODE_COMPRESSION
);
6910 /* If is an local label and the insn is not sync,
6911 look forward that whether an branch between ll/sc jump to here
6912 if so, insert a sync. */
6913 if (seg_info (now_seg
)->label_list
6914 && S_IS_LOCAL (seg_info (now_seg
)->label_list
->label
)
6915 && (strcmp (ip
->insn_mo
->name
, "sync") != 0))
6919 const char *label_names
[MAX_LABELS_SAME
];
6920 const char *label_name
;
6922 label_name
= S_GET_NAME (seg_info (now_seg
)->label_list
->label
);
6923 label_names
[0] = label_name
;
6924 struct insn_label_list
*llist
= seg_info (now_seg
)->label_list
;
6925 label_value
= S_GET_VALUE (llist
->label
);
6927 for (i
= 1; i
< MAX_LABELS_SAME
; i
++)
6929 llist
= llist
->next
;
6932 if (S_GET_VALUE (llist
->label
) == label_value
)
6933 label_names
[i
] = S_GET_NAME (llist
->label
);
6937 for (; i
< MAX_LABELS_SAME
; i
++)
6938 label_names
[i
] = NULL
;
6940 unsigned long lookback
= ARRAY_SIZE (history
);
6941 for (i
= 0; i
< lookback
; i
++)
6943 if (streq (history
[i
].insn_mo
->name
, "ll")
6944 || streq (history
[i
].insn_mo
->name
, "lld"))
6947 if (streq (history
[i
].insn_mo
->name
, "sc")
6948 || streq (history
[i
].insn_mo
->name
, "scd"))
6952 for (j
= i
+ 1; j
< lookback
; j
++)
6954 if (streq (history
[i
].insn_mo
->name
, "ll")
6955 || streq (history
[i
].insn_mo
->name
, "lld"))
6958 if (delayed_branch_p (&history
[j
]))
6960 if (has_label_name (label_names
,
6964 add_fixed_insn (&sync_insn
);
6965 insert_into_history (0, 1, &sync_insn
);
6974 /* If we find a sc, we look forward to look for an branch insn,
6975 and see whether it jump back and out of ll/sc. */
6976 else if (streq (ip
->insn_mo
->name
, "sc") || streq (ip
->insn_mo
->name
, "scd"))
6978 unsigned long lookback
= ARRAY_SIZE (history
) - 1;
6981 for (i
= 0; i
< lookback
; i
++)
6983 if (streq (history
[i
].insn_mo
->name
, "ll")
6984 || streq (history
[i
].insn_mo
->name
, "lld"))
6987 if (delayed_branch_p (&history
[i
]))
6991 for (j
= i
+ 1; j
< lookback
; j
++)
6993 if (streq (history
[j
].insn_mo
->name
, "ll")
6994 || streq (history
[i
].insn_mo
->name
, "lld"))
6998 for (; j
< lookback
; j
++)
7000 if (history
[j
].label
[0] != '\0'
7001 && streq (history
[j
].label
, history
[i
].target
)
7002 && strcmp (history
[j
+1].insn_mo
->name
, "sync") != 0)
7004 add_fixed_insn (&sync_insn
);
7005 insert_into_history (++j
, 1, &sync_insn
);
7012 /* Skip if there is a sync before ll/lld. */
7013 if ((strcmp (ip
->insn_mo
->name
, "ll") == 0
7014 || strcmp (ip
->insn_mo
->name
, "lld") == 0)
7015 && (strcmp (history
[0].insn_mo
->name
, "sync") != 0))
7017 add_fixed_insn (&sync_insn
);
7018 insert_into_history (0, 1, &sync_insn
);
7022 /* IP is a branch that has a delay slot, and we need to fill it
7023 automatically. Return true if we can do that by swapping IP
7024 with the previous instruction.
7025 ADDRESS_EXPR is an operand of the instruction to be used with
7029 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7030 bfd_reloc_code_real_type
*reloc_type
)
7032 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
7033 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
7034 unsigned int fpr_read
, prev_fpr_write
;
7036 /* -O2 and above is required for this optimization. */
7037 if (mips_optimize
< 2)
7040 /* If we have seen .set volatile or .set nomove, don't optimize. */
7041 if (mips_opts
.nomove
)
7044 /* We can't swap if the previous instruction's position is fixed. */
7045 if (history
[0].fixed_p
)
7048 /* If the previous previous insn was in a .set noreorder, we can't
7049 swap. Actually, the MIPS assembler will swap in this situation.
7050 However, gcc configured -with-gnu-as will generate code like
7058 in which we can not swap the bne and INSN. If gcc is not configured
7059 -with-gnu-as, it does not output the .set pseudo-ops. */
7060 if (history
[1].noreorder_p
)
7063 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
7064 This means that the previous instruction was a 4-byte one anyhow. */
7065 if (mips_opts
.mips16
&& history
[0].fixp
[0])
7068 /* If the branch is itself the target of a branch, we can not swap.
7069 We cheat on this; all we check for is whether there is a label on
7070 this instruction. If there are any branches to anything other than
7071 a label, users must use .set noreorder. */
7072 if (seg_info (now_seg
)->label_list
)
7075 /* If the previous instruction is in a variant frag other than this
7076 branch's one, we cannot do the swap. This does not apply to
7077 MIPS16 code, which uses variant frags for different purposes. */
7078 if (!mips_opts
.mips16
7080 && history
[0].frag
->fr_type
== rs_machine_dependent
)
7083 /* We do not swap with instructions that cannot architecturally
7084 be placed in a branch delay slot, such as SYNC or ERET. We
7085 also refrain from swapping with a trap instruction, since it
7086 complicates trap handlers to have the trap instruction be in
7088 prev_pinfo
= history
[0].insn_mo
->pinfo
;
7089 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
7092 /* Check for conflicts between the branch and the instructions
7093 before the candidate delay slot. */
7094 if (nops_for_insn (0, history
+ 1, ip
) > 0)
7097 /* Check for conflicts between the swapped sequence and the
7098 target of the branch. */
7099 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
7102 /* If the branch reads a register that the previous
7103 instruction sets, we can not swap. */
7104 gpr_read
= gpr_read_mask (ip
);
7105 prev_gpr_write
= gpr_write_mask (&history
[0]);
7106 if (gpr_read
& prev_gpr_write
)
7109 fpr_read
= fpr_read_mask (ip
);
7110 prev_fpr_write
= fpr_write_mask (&history
[0]);
7111 if (fpr_read
& prev_fpr_write
)
7114 /* If the branch writes a register that the previous
7115 instruction sets, we can not swap. */
7116 gpr_write
= gpr_write_mask (ip
);
7117 if (gpr_write
& prev_gpr_write
)
7120 /* If the branch writes a register that the previous
7121 instruction reads, we can not swap. */
7122 prev_gpr_read
= gpr_read_mask (&history
[0]);
7123 if (gpr_write
& prev_gpr_read
)
7126 /* If one instruction sets a condition code and the
7127 other one uses a condition code, we can not swap. */
7128 pinfo
= ip
->insn_mo
->pinfo
;
7129 if ((pinfo
& INSN_READ_COND_CODE
)
7130 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
7132 if ((pinfo
& INSN_WRITE_COND_CODE
)
7133 && (prev_pinfo
& INSN_READ_COND_CODE
))
7136 /* If the previous instruction uses the PC, we can not swap. */
7137 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7138 if (prev_pinfo2
& INSN2_READ_PC
)
7141 /* If the previous instruction has an incorrect size for a fixed
7142 branch delay slot in microMIPS mode, we cannot swap. */
7143 pinfo2
= ip
->insn_mo
->pinfo2
;
7144 if (mips_opts
.micromips
7145 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
7146 && insn_length (history
) != 2)
7148 if (mips_opts
.micromips
7149 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
7150 && insn_length (history
) != 4)
7153 /* On the R5900 short loops need to be fixed by inserting a NOP in the
7156 The short loop bug under certain conditions causes loops to execute
7157 only once or twice. We must ensure that the assembler never
7158 generates loops that satisfy all of the following conditions:
7160 - a loop consists of less than or equal to six instructions
7161 (including the branch delay slot);
7162 - a loop contains only one conditional branch instruction at the end
7164 - a loop does not contain any other branch or jump instructions;
7165 - a branch delay slot of the loop is not NOP (EE 2.9 or later).
7167 We need to do this because of a hardware bug in the R5900 chip. */
7169 /* Check if instruction has a parameter, ignore "j $31". */
7170 && (address_expr
!= NULL
)
7171 /* Parameter must be 16 bit. */
7172 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
7173 /* Branch to same segment. */
7174 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
7175 /* Branch to same code fragment. */
7176 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
7177 /* Can only calculate branch offset if value is known. */
7178 && symbol_constant_p (address_expr
->X_add_symbol
)
7179 /* Check if branch is really conditional. */
7180 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
7181 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
7182 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
7185 /* Check if loop is shorter than or equal to 6 instructions
7186 including branch and delay slot. */
7187 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
7194 /* When the loop includes branches or jumps,
7195 it is not a short loop. */
7196 for (i
= 0; i
< (distance
/ 4); i
++)
7198 if ((history
[i
].cleared_p
)
7199 || delayed_branch_p (&history
[i
]))
7207 /* Insert nop after branch to fix short loop. */
7216 /* Decide how we should add IP to the instruction stream.
7217 ADDRESS_EXPR is an operand of the instruction to be used with
7220 static enum append_method
7221 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7222 bfd_reloc_code_real_type
*reloc_type
)
7224 /* The relaxed version of a macro sequence must be inherently
7226 if (mips_relax
.sequence
== 2)
7229 /* We must not dabble with instructions in a ".set noreorder" block. */
7230 if (mips_opts
.noreorder
)
7233 /* Otherwise, it's our responsibility to fill branch delay slots. */
7234 if (delayed_branch_p (ip
))
7236 if (!branch_likely_p (ip
)
7237 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7240 if (mips_opts
.mips16
7241 && ISA_SUPPORTS_MIPS16E
7242 && gpr_read_mask (ip
) != 0)
7243 return APPEND_ADD_COMPACT
;
7245 if (mips_opts
.micromips
7246 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7247 || (!forced_insn_length
7248 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7249 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7250 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7251 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7252 return APPEND_ADD_COMPACT
;
7254 return APPEND_ADD_WITH_NOP
;
7260 /* IP is an instruction whose opcode we have just changed, END points
7261 to the end of the opcode table processed. Point IP->insn_mo to the
7262 new opcode's definition. */
7265 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7267 const struct mips_opcode
*mo
;
7269 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7270 if (mo
->pinfo
!= INSN_MACRO
7271 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7279 /* IP is a MIPS16 instruction whose opcode we have just changed.
7280 Point IP->insn_mo to the new opcode's definition. */
7283 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7285 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7288 /* IP is a microMIPS instruction whose opcode we have just changed.
7289 Point IP->insn_mo to the new opcode's definition. */
7292 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7294 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7297 /* For microMIPS macros, we need to generate a local number label
7298 as the target of branches. */
7299 #define MICROMIPS_LABEL_CHAR '\037'
7300 static unsigned long micromips_target_label
;
7301 static char micromips_target_name
[32];
7304 micromips_label_name (void)
7306 char *p
= micromips_target_name
;
7307 char symbol_name_temporary
[24];
7315 l
= micromips_target_label
;
7316 #ifdef LOCAL_LABEL_PREFIX
7317 *p
++ = LOCAL_LABEL_PREFIX
;
7320 *p
++ = MICROMIPS_LABEL_CHAR
;
7323 symbol_name_temporary
[i
++] = l
% 10 + '0';
7328 *p
++ = symbol_name_temporary
[--i
];
7331 return micromips_target_name
;
7335 micromips_label_expr (expressionS
*label_expr
)
7337 label_expr
->X_op
= O_symbol
;
7338 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7339 label_expr
->X_add_number
= 0;
7343 micromips_label_inc (void)
7345 micromips_target_label
++;
7346 *micromips_target_name
= '\0';
7350 micromips_add_label (void)
7354 s
= colon (micromips_label_name ());
7355 micromips_label_inc ();
7356 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7359 /* If assembling microMIPS code, then return the microMIPS reloc
7360 corresponding to the requested one if any. Otherwise return
7361 the reloc unchanged. */
7363 static bfd_reloc_code_real_type
7364 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7366 static const bfd_reloc_code_real_type relocs
[][2] =
7368 /* Keep sorted incrementally by the left-hand key. */
7369 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7370 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7371 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7372 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7373 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7374 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7375 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7376 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7377 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7378 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7379 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7380 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7381 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7382 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7383 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7384 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7385 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7386 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7387 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7388 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7389 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7390 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7391 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7392 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7393 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7394 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7395 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7397 bfd_reloc_code_real_type r
;
7400 if (!mips_opts
.micromips
)
7402 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7408 return relocs
[i
][1];
7413 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7414 Return true on success, storing the resolved value in RESULT. */
7417 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7422 case BFD_RELOC_MIPS_HIGHEST
:
7423 case BFD_RELOC_MICROMIPS_HIGHEST
:
7424 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7427 case BFD_RELOC_MIPS_HIGHER
:
7428 case BFD_RELOC_MICROMIPS_HIGHER
:
7429 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7432 case BFD_RELOC_HI16_S
:
7433 case BFD_RELOC_HI16_S_PCREL
:
7434 case BFD_RELOC_MICROMIPS_HI16_S
:
7435 case BFD_RELOC_MIPS16_HI16_S
:
7436 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7439 case BFD_RELOC_HI16
:
7440 case BFD_RELOC_MICROMIPS_HI16
:
7441 case BFD_RELOC_MIPS16_HI16
:
7442 *result
= (operand
>> 16) & 0xffff;
7445 case BFD_RELOC_LO16
:
7446 case BFD_RELOC_LO16_PCREL
:
7447 case BFD_RELOC_MICROMIPS_LO16
:
7448 case BFD_RELOC_MIPS16_LO16
:
7449 *result
= operand
& 0xffff;
7452 case BFD_RELOC_UNUSED
:
7461 /* Output an instruction. IP is the instruction information.
7462 ADDRESS_EXPR is an operand of the instruction to be used with
7463 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7464 a macro expansion. */
7467 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7468 bfd_reloc_code_real_type
*reloc_type
, bool expansionp
)
7470 unsigned long prev_pinfo2
, pinfo
;
7471 bool relaxed_branch
= false;
7472 enum append_method method
;
7476 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7477 fix_loongson2f (ip
);
7479 ip
->target
[0] = '\0';
7480 if (offset_expr
.X_op
== O_symbol
)
7481 strncpy (ip
->target
, S_GET_NAME (offset_expr
.X_add_symbol
), 15);
7482 ip
->label
[0] = '\0';
7483 if (seg_info (now_seg
)->label_list
)
7484 strncpy (ip
->label
, S_GET_NAME (seg_info (now_seg
)->label_list
->label
), 15);
7485 if (mips_fix_loongson3_llsc
&& !HAVE_CODE_COMPRESSION
)
7486 fix_loongson3_llsc (ip
);
7488 file_ase_mips16
|= mips_opts
.mips16
;
7489 file_ase_micromips
|= mips_opts
.micromips
;
7491 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7492 pinfo
= ip
->insn_mo
->pinfo
;
7494 /* Don't raise alarm about `nods' frags as they'll fill in the right
7495 kind of nop in relaxation if required. */
7496 if (mips_opts
.micromips
7498 && !(history
[0].frag
7499 && history
[0].frag
->fr_type
== rs_machine_dependent
7500 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7501 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7502 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7503 && micromips_insn_length (ip
->insn_mo
) != 2)
7504 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7505 && micromips_insn_length (ip
->insn_mo
) != 4)))
7506 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7507 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7509 if (address_expr
== NULL
)
7511 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7512 && reloc_type
[1] == BFD_RELOC_UNUSED
7513 && reloc_type
[2] == BFD_RELOC_UNUSED
7514 && address_expr
->X_op
== O_constant
)
7516 switch (*reloc_type
)
7518 case BFD_RELOC_MIPS_JMP
:
7522 /* Shift is 2, unusually, for microMIPS JALX. */
7523 shift
= (mips_opts
.micromips
7524 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7525 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7526 as_bad (_("jump to misaligned address (0x%lx)"),
7527 (unsigned long) address_expr
->X_add_number
);
7528 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7534 case BFD_RELOC_MIPS16_JMP
:
7535 if ((address_expr
->X_add_number
& 3) != 0)
7536 as_bad (_("jump to misaligned address (0x%lx)"),
7537 (unsigned long) address_expr
->X_add_number
);
7539 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7540 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7541 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7545 case BFD_RELOC_16_PCREL_S2
:
7549 shift
= mips_opts
.micromips
? 1 : 2;
7550 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7551 as_bad (_("branch to misaligned address (0x%lx)"),
7552 (unsigned long) address_expr
->X_add_number
);
7553 if (!mips_relax_branch
)
7555 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7556 & ~((1 << (shift
+ 16)) - 1))
7557 as_bad (_("branch address range overflow (0x%lx)"),
7558 (unsigned long) address_expr
->X_add_number
);
7559 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7565 case BFD_RELOC_MIPS_21_PCREL_S2
:
7570 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7571 as_bad (_("branch to misaligned address (0x%lx)"),
7572 (unsigned long) address_expr
->X_add_number
);
7573 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7574 & ~((1 << (shift
+ 21)) - 1))
7575 as_bad (_("branch address range overflow (0x%lx)"),
7576 (unsigned long) address_expr
->X_add_number
);
7577 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7582 case BFD_RELOC_MIPS_26_PCREL_S2
:
7587 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7588 as_bad (_("branch to misaligned address (0x%lx)"),
7589 (unsigned long) address_expr
->X_add_number
);
7590 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7591 & ~((1 << (shift
+ 26)) - 1))
7592 as_bad (_("branch address range overflow (0x%lx)"),
7593 (unsigned long) address_expr
->X_add_number
);
7594 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7603 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7606 ip
->insn_opcode
|= value
& 0xffff;
7614 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7616 /* There are a lot of optimizations we could do that we don't.
7617 In particular, we do not, in general, reorder instructions.
7618 If you use gcc with optimization, it will reorder
7619 instructions and generally do much more optimization then we
7620 do here; repeating all that work in the assembler would only
7621 benefit hand written assembly code, and does not seem worth
7623 int nops
= (mips_optimize
== 0
7624 ? nops_for_insn (0, history
, NULL
)
7625 : nops_for_insn_or_target (0, history
, ip
));
7629 unsigned long old_frag_offset
;
7632 old_frag
= frag_now
;
7633 old_frag_offset
= frag_now_fix ();
7635 for (i
= 0; i
< nops
; i
++)
7636 add_fixed_insn (NOP_INSN
);
7637 insert_into_history (0, nops
, NOP_INSN
);
7641 listing_prev_line ();
7642 /* We may be at the start of a variant frag. In case we
7643 are, make sure there is enough space for the frag
7644 after the frags created by listing_prev_line. The
7645 argument to frag_grow here must be at least as large
7646 as the argument to all other calls to frag_grow in
7647 this file. We don't have to worry about being in the
7648 middle of a variant frag, because the variants insert
7649 all needed nop instructions themselves. */
7653 mips_move_text_labels ();
7655 #ifndef NO_ECOFF_DEBUGGING
7656 if (ECOFF_DEBUGGING
)
7657 ecoff_fix_loc (old_frag
, old_frag_offset
);
7661 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7665 /* Work out how many nops in prev_nop_frag are needed by IP,
7666 ignoring hazards generated by the first prev_nop_frag_since
7668 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7669 gas_assert (nops
<= prev_nop_frag_holds
);
7671 /* Enforce NOPS as a minimum. */
7672 if (nops
> prev_nop_frag_required
)
7673 prev_nop_frag_required
= nops
;
7675 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7677 /* Settle for the current number of nops. Update the history
7678 accordingly (for the benefit of any future .set reorder code). */
7679 prev_nop_frag
= NULL
;
7680 insert_into_history (prev_nop_frag_since
,
7681 prev_nop_frag_holds
, NOP_INSN
);
7685 /* Allow this instruction to replace one of the nops that was
7686 tentatively added to prev_nop_frag. */
7687 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7688 prev_nop_frag_holds
--;
7689 prev_nop_frag_since
++;
7693 method
= get_append_method (ip
, address_expr
, reloc_type
);
7694 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7696 dwarf2_emit_insn (0);
7697 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7698 so "move" the instruction address accordingly.
7700 Also, it doesn't seem appropriate for the assembler to reorder .loc
7701 entries. If this instruction is a branch that we are going to swap
7702 with the previous instruction, the two instructions should be
7703 treated as a unit, and the debug information for both instructions
7704 should refer to the start of the branch sequence. Using the
7705 current position is certainly wrong when swapping a 32-bit branch
7706 and a 16-bit delay slot, since the current position would then be
7707 in the middle of a branch. */
7708 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7710 relax32
= (mips_relax_branch
7711 /* Don't try branch relaxation within .set nomacro, or within
7712 .set noat if we use $at for PIC computations. If it turns
7713 out that the branch was out-of-range, we'll get an error. */
7714 && !mips_opts
.warn_about_macros
7715 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7716 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7717 as they have no complementing branches. */
7718 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7720 if (!HAVE_CODE_COMPRESSION
7723 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7724 && delayed_branch_p (ip
))
7726 relaxed_branch
= true;
7727 add_relaxed_insn (ip
, (relaxed_branch_length
7729 uncond_branch_p (ip
) ? -1
7730 : branch_likely_p (ip
) ? 1
7733 (AT
, mips_pic
!= NO_PIC
,
7734 uncond_branch_p (ip
),
7735 branch_likely_p (ip
),
7736 pinfo
& INSN_WRITE_GPR_31
,
7738 address_expr
->X_add_symbol
,
7739 address_expr
->X_add_number
);
7740 *reloc_type
= BFD_RELOC_UNUSED
;
7742 else if (mips_opts
.micromips
7744 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7745 || *reloc_type
> BFD_RELOC_UNUSED
)
7746 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7747 /* Don't try branch relaxation when users specify
7748 16-bit/32-bit instructions. */
7749 && !forced_insn_length
)
7751 bool relax16
= (method
!= APPEND_ADD_COMPACT
7752 && *reloc_type
> BFD_RELOC_UNUSED
);
7753 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7754 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7755 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7756 int nods
= method
== APPEND_ADD_WITH_NOP
;
7757 int al
= pinfo
& INSN_WRITE_GPR_31
;
7758 int length32
= nods
? 8 : 4;
7760 gas_assert (address_expr
!= NULL
);
7761 gas_assert (!mips_relax
.sequence
);
7763 relaxed_branch
= true;
7765 method
= APPEND_ADD
;
7767 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7768 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7769 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7771 uncond
, compact
, al
, nods
,
7773 address_expr
->X_add_symbol
,
7774 address_expr
->X_add_number
);
7775 *reloc_type
= BFD_RELOC_UNUSED
;
7777 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7779 bool require_unextended
;
7780 bool require_extended
;
7784 if (forced_insn_length
!= 0)
7786 require_unextended
= forced_insn_length
== 2;
7787 require_extended
= forced_insn_length
== 4;
7791 require_unextended
= (mips_opts
.noautoextend
7792 && !mips_opcode_32bit_p (ip
->insn_mo
));
7793 require_extended
= 0;
7796 /* We need to set up a variant frag. */
7797 gas_assert (address_expr
!= NULL
);
7798 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7799 symbol created by `make_expr_symbol' may not get a necessary
7800 external relocation produced. */
7801 if (address_expr
->X_op
== O_symbol
)
7803 symbol
= address_expr
->X_add_symbol
;
7804 offset
= address_expr
->X_add_number
;
7808 symbol
= make_expr_symbol (address_expr
);
7809 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7812 add_relaxed_insn (ip
, 12, 0,
7814 (*reloc_type
- BFD_RELOC_UNUSED
,
7815 mips_opts
.ase
& ASE_MIPS16E2
,
7818 mips_opts
.warn_about_macros
,
7819 require_unextended
, require_extended
,
7820 delayed_branch_p (&history
[0]),
7821 history
[0].mips16_absolute_jump_p
),
7824 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7826 if (!delayed_branch_p (ip
))
7827 /* Make sure there is enough room to swap this instruction with
7828 a following jump instruction. */
7830 add_fixed_insn (ip
);
7834 if (mips_opts
.mips16
7835 && mips_opts
.noreorder
7836 && delayed_branch_p (&history
[0]))
7837 as_warn (_("extended instruction in delay slot"));
7839 if (mips_relax
.sequence
)
7841 /* If we've reached the end of this frag, turn it into a variant
7842 frag and record the information for the instructions we've
7844 if (frag_room () < 4)
7845 relax_close_frag ();
7846 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7849 if (mips_relax
.sequence
!= 2)
7851 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7852 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7853 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7854 mips_macro_warning
.insns
[0]++;
7856 if (mips_relax
.sequence
!= 1)
7858 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7859 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7860 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7861 mips_macro_warning
.insns
[1]++;
7864 if (mips_opts
.mips16
)
7867 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7869 add_fixed_insn (ip
);
7872 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7874 bfd_reloc_code_real_type final_type
[3];
7875 reloc_howto_type
*howto0
;
7876 reloc_howto_type
*howto
;
7879 /* Perform any necessary conversion to microMIPS relocations
7880 and find out how many relocations there actually are. */
7881 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7882 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7884 /* In a compound relocation, it is the final (outermost)
7885 operator that determines the relocated field. */
7886 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7891 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7892 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7893 bfd_get_reloc_size (howto
),
7895 howto0
&& howto0
->pc_relative
,
7897 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7898 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7900 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7901 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7902 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7904 /* These relocations can have an addend that won't fit in
7905 4 octets for 64bit assembly. */
7907 && ! howto
->partial_inplace
7908 && (reloc_type
[0] == BFD_RELOC_16
7909 || reloc_type
[0] == BFD_RELOC_32
7910 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7911 || reloc_type
[0] == BFD_RELOC_GPREL16
7912 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7913 || reloc_type
[0] == BFD_RELOC_GPREL32
7914 || reloc_type
[0] == BFD_RELOC_64
7915 || reloc_type
[0] == BFD_RELOC_CTOR
7916 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7917 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7918 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7919 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7920 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7921 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7922 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7923 || hi16_reloc_p (reloc_type
[0])
7924 || lo16_reloc_p (reloc_type
[0])))
7925 ip
->fixp
[0]->fx_no_overflow
= 1;
7927 /* These relocations can have an addend that won't fit in 2 octets. */
7928 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7929 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7930 ip
->fixp
[0]->fx_no_overflow
= 1;
7932 if (mips_relax
.sequence
)
7934 if (mips_relax
.first_fixup
== 0)
7935 mips_relax
.first_fixup
= ip
->fixp
[0];
7937 else if (reloc_needs_lo_p (*reloc_type
))
7939 struct mips_hi_fixup
*hi_fixup
;
7941 /* Reuse the last entry if it already has a matching %lo. */
7942 hi_fixup
= mips_hi_fixup_list
;
7944 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7946 hi_fixup
= XNEW (struct mips_hi_fixup
);
7947 hi_fixup
->next
= mips_hi_fixup_list
;
7948 mips_hi_fixup_list
= hi_fixup
;
7950 hi_fixup
->fixp
= ip
->fixp
[0];
7951 hi_fixup
->seg
= now_seg
;
7954 /* Add fixups for the second and third relocations, if given.
7955 Note that the ABI allows the second relocation to be
7956 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7957 moment we only use RSS_UNDEF, but we could add support
7958 for the others if it ever becomes necessary. */
7959 for (i
= 1; i
< 3; i
++)
7960 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7962 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7963 ip
->fixp
[0]->fx_size
, NULL
, 0,
7964 false, final_type
[i
]);
7966 /* Use fx_tcbit to mark compound relocs. */
7967 ip
->fixp
[0]->fx_tcbit
= 1;
7968 ip
->fixp
[i
]->fx_tcbit
= 1;
7972 /* Update the register mask information. */
7973 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7974 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7979 insert_into_history (0, 1, ip
);
7982 case APPEND_ADD_WITH_NOP
:
7984 struct mips_cl_insn
*nop
;
7986 insert_into_history (0, 1, ip
);
7987 nop
= get_delay_slot_nop (ip
);
7988 add_fixed_insn (nop
);
7989 insert_into_history (0, 1, nop
);
7990 if (mips_relax
.sequence
)
7991 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7995 case APPEND_ADD_COMPACT
:
7996 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7997 if (mips_opts
.mips16
)
7999 ip
->insn_opcode
|= 0x0080;
8000 find_altered_mips16_opcode (ip
);
8002 /* Convert microMIPS instructions. */
8003 else if (mips_opts
.micromips
)
8006 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
8007 ip
->insn_opcode
|= 0x0020;
8009 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
8010 ip
->insn_opcode
= 0x40e00000;
8011 /* beqz16->beqzc, bnez16->bnezc */
8012 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
8014 unsigned long regno
;
8016 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
8017 regno
&= MICROMIPSOP_MASK_MD
;
8018 regno
= micromips_to_32_reg_d_map
[regno
];
8019 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
8020 | (regno
<< MICROMIPSOP_SH_RS
)
8021 | 0x40a00000) ^ 0x00400000;
8023 /* beqz->beqzc, bnez->bnezc */
8024 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
8025 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
8026 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8027 | 0x40a00000) ^ 0x00400000;
8028 /* beq $0->beqzc, bne $0->bnezc */
8029 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
8030 ip
->insn_opcode
= (((ip
->insn_opcode
>>
8031 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
8032 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
8033 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8034 | 0x40a00000) ^ 0x00400000;
8037 find_altered_micromips_opcode (ip
);
8042 insert_into_history (0, 1, ip
);
8047 struct mips_cl_insn delay
= history
[0];
8049 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
8051 /* Add the delay slot instruction to the end of the
8052 current frag and shrink the fixed part of the
8053 original frag. If the branch occupies the tail of
8054 the latter, move it backwards to cover the gap. */
8055 delay
.frag
->fr_fix
-= branch_disp
;
8056 if (delay
.frag
== ip
->frag
)
8057 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
8058 add_fixed_insn (&delay
);
8062 /* If this is not a relaxed branch and we are in the
8063 same frag, then just swap the instructions. */
8064 move_insn (ip
, delay
.frag
, delay
.where
);
8065 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
8069 insert_into_history (0, 1, &delay
);
8074 /* If we have just completed an unconditional branch, clear the history. */
8075 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
8076 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
8080 mips_no_prev_insn ();
8082 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8083 history
[i
].cleared_p
= 1;
8086 /* We need to emit a label at the end of branch-likely macros. */
8087 if (emit_branch_likely_macro
)
8089 emit_branch_likely_macro
= false;
8090 micromips_add_label ();
8093 /* We just output an insn, so the next one doesn't have a label. */
8094 mips_clear_insn_labels ();
8097 /* Forget that there was any previous instruction or label.
8098 When BRANCH is true, the branch history is also flushed. */
8101 mips_no_prev_insn (void)
8103 prev_nop_frag
= NULL
;
8104 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
8105 mips_clear_insn_labels ();
8108 /* This function must be called before we emit something other than
8109 instructions. It is like mips_no_prev_insn except that it inserts
8110 any NOPS that might be needed by previous instructions. */
8113 mips_emit_delays (void)
8115 if (! mips_opts
.noreorder
)
8117 int nops
= nops_for_insn (0, history
, NULL
);
8121 add_fixed_insn (NOP_INSN
);
8122 mips_move_text_labels ();
8125 mips_no_prev_insn ();
8128 /* Start a (possibly nested) noreorder block. */
8131 start_noreorder (void)
8133 if (mips_opts
.noreorder
== 0)
8138 /* None of the instructions before the .set noreorder can be moved. */
8139 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8140 history
[i
].fixed_p
= 1;
8142 /* Insert any nops that might be needed between the .set noreorder
8143 block and the previous instructions. We will later remove any
8144 nops that turn out not to be needed. */
8145 nops
= nops_for_insn (0, history
, NULL
);
8148 if (mips_optimize
!= 0)
8150 /* Record the frag which holds the nop instructions, so
8151 that we can remove them if we don't need them. */
8152 frag_grow (nops
* NOP_INSN_SIZE
);
8153 prev_nop_frag
= frag_now
;
8154 prev_nop_frag_holds
= nops
;
8155 prev_nop_frag_required
= 0;
8156 prev_nop_frag_since
= 0;
8159 for (; nops
> 0; --nops
)
8160 add_fixed_insn (NOP_INSN
);
8162 /* Move on to a new frag, so that it is safe to simply
8163 decrease the size of prev_nop_frag. */
8164 frag_wane (frag_now
);
8166 mips_move_text_labels ();
8168 mips_mark_labels ();
8169 mips_clear_insn_labels ();
8171 mips_opts
.noreorder
++;
8172 mips_any_noreorder
= 1;
8175 /* End a nested noreorder block. */
8178 end_noreorder (void)
8180 mips_opts
.noreorder
--;
8181 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
8183 /* Commit to inserting prev_nop_frag_required nops and go back to
8184 handling nop insertion the .set reorder way. */
8185 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
8187 insert_into_history (prev_nop_frag_since
,
8188 prev_nop_frag_required
, NOP_INSN
);
8189 prev_nop_frag
= NULL
;
8193 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8194 higher bits unset. */
8197 normalize_constant_expr (expressionS
*ex
)
8199 if (ex
->X_op
== O_constant
8200 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8201 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8205 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8206 all higher bits unset. */
8209 normalize_address_expr (expressionS
*ex
)
8211 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
8212 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
8213 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8214 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8218 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8219 Return true if the match was successful.
8221 OPCODE_EXTRA is a value that should be ORed into the opcode
8222 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8223 there are more alternatives after OPCODE and SOFT_MATCH is
8224 as for mips_arg_info. */
8227 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8228 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8229 bool lax_match
, bool complete_p
)
8232 struct mips_arg_info arg
;
8233 const struct mips_operand
*operand
;
8236 imm_expr
.X_op
= O_absent
;
8237 offset_expr
.X_op
= O_absent
;
8238 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8239 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8240 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8242 create_insn (insn
, opcode
);
8243 /* When no opcode suffix is specified, assume ".xyzw". */
8244 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8245 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8247 insn
->insn_opcode
|= opcode_extra
;
8248 memset (&arg
, 0, sizeof (arg
));
8252 arg
.last_regno
= ILLEGAL_REG
;
8253 arg
.dest_regno
= ILLEGAL_REG
;
8254 arg
.lax_match
= lax_match
;
8255 for (args
= opcode
->args
;; ++args
)
8257 if (arg
.token
->type
== OT_END
)
8259 /* Handle unary instructions in which only one operand is given.
8260 The source is then the same as the destination. */
8261 if (arg
.opnum
== 1 && *args
== ',')
8263 operand
= (mips_opts
.micromips
8264 ? decode_micromips_operand (args
+ 1)
8265 : decode_mips_operand (args
+ 1));
8266 if (operand
&& mips_optional_operand_p (operand
))
8274 /* Treat elided base registers as $0. */
8275 if (strcmp (args
, "(b)") == 0)
8283 /* The register suffix is optional. */
8288 /* Fail the match if there were too few operands. */
8292 /* Successful match. */
8295 clear_insn_error ();
8296 if (arg
.dest_regno
== arg
.last_regno
8297 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8301 (0, _("source and destination must be different"));
8302 else if (arg
.last_regno
== 31)
8304 (0, _("a destination register must be supplied"));
8306 else if (arg
.last_regno
== 31
8307 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8308 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8309 set_insn_error (0, _("the source register must not be $31"));
8310 check_completed_insn (&arg
);
8314 /* Fail the match if the line has too many operands. */
8318 /* Handle characters that need to match exactly. */
8319 if (*args
== '(' || *args
== ')' || *args
== ',')
8321 if (match_char (&arg
, *args
))
8328 if (arg
.token
->type
== OT_DOUBLE_CHAR
8329 && arg
.token
->u
.ch
== *args
)
8337 /* Handle special macro operands. Work out the properties of
8346 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8350 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8359 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8363 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8367 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8373 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8375 imm_expr
.X_op
= O_constant
;
8377 normalize_constant_expr (&imm_expr
);
8381 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8383 /* Assume that the offset has been elided and that what
8384 we saw was a base register. The match will fail later
8385 if that assumption turns out to be wrong. */
8386 offset_expr
.X_op
= O_constant
;
8387 offset_expr
.X_add_number
= 0;
8391 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8393 normalize_address_expr (&offset_expr
);
8398 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8404 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8410 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8416 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8422 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8426 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8430 gas_assert (mips_opts
.micromips
);
8436 if (!forced_insn_length
)
8437 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8439 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8441 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8447 operand
= (mips_opts
.micromips
8448 ? decode_micromips_operand (args
)
8449 : decode_mips_operand (args
));
8453 /* Skip prefixes. */
8454 if (*args
== '+' || *args
== 'm' || *args
== '-')
8457 if (mips_optional_operand_p (operand
)
8459 && (arg
.token
[0].type
!= OT_REG
8460 || arg
.token
[1].type
== OT_END
))
8462 /* Assume that the register has been elided and is the
8463 same as the first operand. */
8468 if (!match_operand (&arg
, operand
))
8473 /* Like match_insn, but for MIPS16. */
8476 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8477 struct mips_operand_token
*tokens
)
8480 const struct mips_operand
*operand
;
8481 const struct mips_operand
*ext_operand
;
8483 int required_insn_length
;
8484 struct mips_arg_info arg
;
8487 if (forced_insn_length
)
8488 required_insn_length
= forced_insn_length
;
8489 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8490 required_insn_length
= 2;
8492 required_insn_length
= 0;
8494 create_insn (insn
, opcode
);
8495 imm_expr
.X_op
= O_absent
;
8496 offset_expr
.X_op
= O_absent
;
8497 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8498 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8499 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8502 memset (&arg
, 0, sizeof (arg
));
8506 arg
.last_regno
= ILLEGAL_REG
;
8507 arg
.dest_regno
= ILLEGAL_REG
;
8509 for (args
= opcode
->args
;; ++args
)
8513 if (arg
.token
->type
== OT_END
)
8517 /* Handle unary instructions in which only one operand is given.
8518 The source is then the same as the destination. */
8519 if (arg
.opnum
== 1 && *args
== ',')
8521 operand
= decode_mips16_operand (args
[1], false);
8522 if (operand
&& mips_optional_operand_p (operand
))
8530 /* Fail the match if there were too few operands. */
8534 /* Successful match. Stuff the immediate value in now, if
8536 clear_insn_error ();
8537 if (opcode
->pinfo
== INSN_MACRO
)
8539 gas_assert (relax_char
== 0 || relax_char
== 'p');
8540 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8543 && offset_expr
.X_op
== O_constant
8545 && calculate_reloc (*offset_reloc
,
8546 offset_expr
.X_add_number
,
8549 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8550 required_insn_length
, &insn
->insn_opcode
);
8551 offset_expr
.X_op
= O_absent
;
8552 *offset_reloc
= BFD_RELOC_UNUSED
;
8554 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8556 if (required_insn_length
== 2)
8557 set_insn_error (0, _("invalid unextended operand value"));
8558 else if (!mips_opcode_32bit_p (opcode
))
8560 forced_insn_length
= 4;
8561 insn
->insn_opcode
|= MIPS16_EXTEND
;
8564 else if (relax_char
)
8565 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8567 check_completed_insn (&arg
);
8571 /* Fail the match if the line has too many operands. */
8575 /* Handle characters that need to match exactly. */
8576 if (*args
== '(' || *args
== ')' || *args
== ',')
8578 if (match_char (&arg
, *args
))
8598 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8600 imm_expr
.X_op
= O_constant
;
8602 normalize_constant_expr (&imm_expr
);
8607 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8611 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8615 if (operand
->type
== OP_PCREL
)
8619 ext_operand
= decode_mips16_operand (c
, true);
8620 if (operand
!= ext_operand
)
8622 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8624 offset_expr
.X_op
= O_constant
;
8625 offset_expr
.X_add_number
= 0;
8630 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8633 /* '8' is used for SLTI(U) and has traditionally not
8634 been allowed to take relocation operators. */
8635 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8636 && (ext_operand
->size
!= 16 || c
== '8'))
8638 match_not_constant (&arg
);
8642 if (offset_expr
.X_op
== O_big
)
8644 match_out_of_range (&arg
);
8653 if (mips_optional_operand_p (operand
)
8655 && (arg
.token
[0].type
!= OT_REG
8656 || arg
.token
[1].type
== OT_END
))
8658 /* Assume that the register has been elided and is the
8659 same as the first operand. */
8664 if (!match_operand (&arg
, operand
))
8669 /* Record that the current instruction is invalid for the current ISA. */
8672 match_invalid_for_isa (void)
8675 (0, _("opcode not supported on this processor: %s (%s)"),
8676 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8677 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8680 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8681 Return true if a definite match or failure was found, storing any match
8682 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8683 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8684 tried and failed to match under normal conditions and now want to try a
8685 more relaxed match. */
8688 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8689 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8690 int opcode_extra
, bool lax_match
)
8692 const struct mips_opcode
*opcode
;
8693 const struct mips_opcode
*invalid_delay_slot
;
8694 bool seen_valid_for_isa
, seen_valid_for_size
;
8696 /* Search for a match, ignoring alternatives that don't satisfy the
8697 current ISA or forced_length. */
8698 invalid_delay_slot
= 0;
8699 seen_valid_for_isa
= false;
8700 seen_valid_for_size
= false;
8704 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8705 if (is_opcode_valid (opcode
))
8707 seen_valid_for_isa
= true;
8708 if (is_size_valid (opcode
))
8712 seen_valid_for_size
= true;
8713 delay_slot_ok
= is_delay_slot_valid (opcode
);
8714 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8715 lax_match
, delay_slot_ok
))
8719 if (!invalid_delay_slot
)
8720 invalid_delay_slot
= opcode
;
8729 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8731 /* If the only matches we found had the wrong length for the delay slot,
8732 pick the first such match. We'll issue an appropriate warning later. */
8733 if (invalid_delay_slot
)
8735 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8741 /* Handle the case where we didn't try to match an instruction because
8742 all the alternatives were incompatible with the current ISA. */
8743 if (!seen_valid_for_isa
)
8745 match_invalid_for_isa ();
8749 /* Handle the case where we didn't try to match an instruction because
8750 all the alternatives were of the wrong size. */
8751 if (!seen_valid_for_size
)
8753 if (mips_opts
.insn32
)
8754 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8757 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8758 8 * forced_insn_length
);
8765 /* Like match_insns, but for MIPS16. */
8768 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8769 struct mips_operand_token
*tokens
)
8771 const struct mips_opcode
*opcode
;
8772 bool seen_valid_for_isa
;
8773 bool seen_valid_for_size
;
8775 /* Search for a match, ignoring alternatives that don't satisfy the
8776 current ISA. There are no separate entries for extended forms so
8777 we deal with forced_length later. */
8778 seen_valid_for_isa
= false;
8779 seen_valid_for_size
= false;
8783 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8784 if (is_opcode_valid_16 (opcode
))
8786 seen_valid_for_isa
= true;
8787 if (is_size_valid_16 (opcode
))
8789 seen_valid_for_size
= true;
8790 if (match_mips16_insn (insn
, opcode
, tokens
))
8796 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8797 && strcmp (opcode
->name
, first
->name
) == 0);
8799 /* Handle the case where we didn't try to match an instruction because
8800 all the alternatives were incompatible with the current ISA. */
8801 if (!seen_valid_for_isa
)
8803 match_invalid_for_isa ();
8807 /* Handle the case where we didn't try to match an instruction because
8808 all the alternatives were of the wrong size. */
8809 if (!seen_valid_for_size
)
8811 if (forced_insn_length
== 2)
8813 (0, _("unrecognized unextended version of MIPS16 opcode"));
8816 (0, _("unrecognized extended version of MIPS16 opcode"));
8823 /* Set up global variables for the start of a new macro. */
8828 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8829 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8830 sizeof (mips_macro_warning
.first_insn_sizes
));
8831 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8832 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8833 && delayed_branch_p (&history
[0]));
8835 && history
[0].frag
->fr_type
== rs_machine_dependent
8836 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8837 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8838 mips_macro_warning
.delay_slot_length
= 0;
8840 switch (history
[0].insn_mo
->pinfo2
8841 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8843 case INSN2_BRANCH_DELAY_32BIT
:
8844 mips_macro_warning
.delay_slot_length
= 4;
8846 case INSN2_BRANCH_DELAY_16BIT
:
8847 mips_macro_warning
.delay_slot_length
= 2;
8850 mips_macro_warning
.delay_slot_length
= 0;
8853 mips_macro_warning
.first_frag
= NULL
;
8856 /* Given that a macro is longer than one instruction or of the wrong size,
8857 return the appropriate warning for it. Return null if no warning is
8858 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8859 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8860 and RELAX_NOMACRO. */
8863 macro_warning (relax_substateT subtype
)
8865 if (subtype
& RELAX_DELAY_SLOT
)
8866 return _("macro instruction expanded into multiple instructions"
8867 " in a branch delay slot");
8868 else if (subtype
& RELAX_NOMACRO
)
8869 return _("macro instruction expanded into multiple instructions");
8870 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8871 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8872 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8873 ? _("macro instruction expanded into a wrong size instruction"
8874 " in a 16-bit branch delay slot")
8875 : _("macro instruction expanded into a wrong size instruction"
8876 " in a 32-bit branch delay slot"));
8881 /* Finish up a macro. Emit warnings as appropriate. */
8886 /* Relaxation warning flags. */
8887 relax_substateT subtype
= 0;
8889 /* Check delay slot size requirements. */
8890 if (mips_macro_warning
.delay_slot_length
== 2)
8891 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8892 if (mips_macro_warning
.delay_slot_length
!= 0)
8894 if (mips_macro_warning
.delay_slot_length
8895 != mips_macro_warning
.first_insn_sizes
[0])
8896 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8897 if (mips_macro_warning
.delay_slot_length
8898 != mips_macro_warning
.first_insn_sizes
[1])
8899 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8902 /* Check instruction count requirements. */
8903 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8905 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8906 subtype
|= RELAX_SECOND_LONGER
;
8907 if (mips_opts
.warn_about_macros
)
8908 subtype
|= RELAX_NOMACRO
;
8909 if (mips_macro_warning
.delay_slot_p
)
8910 subtype
|= RELAX_DELAY_SLOT
;
8913 /* If both alternatives fail to fill a delay slot correctly,
8914 emit the warning now. */
8915 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8916 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8921 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8922 | RELAX_DELAY_SLOT_SIZE_FIRST
8923 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8924 msg
= macro_warning (s
);
8926 as_warn ("%s", msg
);
8930 /* If both implementations are longer than 1 instruction, then emit the
8932 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8937 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8938 msg
= macro_warning (s
);
8940 as_warn ("%s", msg
);
8944 /* If any flags still set, then one implementation might need a warning
8945 and the other either will need one of a different kind or none at all.
8946 Pass any remaining flags over to relaxation. */
8947 if (mips_macro_warning
.first_frag
!= NULL
)
8948 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8951 /* Instruction operand formats used in macros that vary between
8952 standard MIPS and microMIPS code. */
8954 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8955 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8956 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8957 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8958 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8959 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8960 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8961 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8963 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8964 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8965 : cop12_fmt[mips_opts.micromips])
8966 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8967 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8968 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8969 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8970 : mem12_fmt[mips_opts.micromips])
8971 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8972 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8973 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8975 /* Read a macro's relocation codes from *ARGS and store them in *R.
8976 The first argument in *ARGS will be either the code for a single
8977 relocation or -1 followed by the three codes that make up a
8978 composite relocation. */
8981 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8985 next
= va_arg (*args
, int);
8987 r
[0] = (bfd_reloc_code_real_type
) next
;
8990 for (i
= 0; i
< 3; i
++)
8991 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8992 /* This function is only used for 16-bit relocation fields.
8993 To make the macro code simpler, treat an unrelocated value
8994 in the same way as BFD_RELOC_LO16. */
8995 if (r
[0] == BFD_RELOC_UNUSED
)
8996 r
[0] = BFD_RELOC_LO16
;
9000 /* Build an instruction created by a macro expansion. This is passed
9001 a pointer to the count of instructions created so far, an
9002 expression, the name of the instruction to build, an operand format
9003 string, and corresponding arguments. */
9006 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
9008 const struct mips_opcode
*mo
= NULL
;
9009 bfd_reloc_code_real_type r
[3];
9010 const struct mips_opcode
*amo
;
9011 const struct mips_operand
*operand
;
9013 struct mips_cl_insn insn
;
9017 va_start (args
, fmt
);
9019 if (mips_opts
.mips16
)
9021 mips16_macro_build (ep
, name
, fmt
, &args
);
9026 r
[0] = BFD_RELOC_UNUSED
;
9027 r
[1] = BFD_RELOC_UNUSED
;
9028 r
[2] = BFD_RELOC_UNUSED
;
9029 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
9030 amo
= (struct mips_opcode
*) str_hash_find (hash
, name
);
9032 gas_assert (strcmp (name
, amo
->name
) == 0);
9036 /* Search until we get a match for NAME. It is assumed here that
9037 macros will never generate MDMX, MIPS-3D, or MT instructions.
9038 We try to match an instruction that fulfills the branch delay
9039 slot instruction length requirement (if any) of the previous
9040 instruction. While doing this we record the first instruction
9041 seen that matches all the other conditions and use it anyway
9042 if the requirement cannot be met; we will issue an appropriate
9043 warning later on. */
9044 if (strcmp (fmt
, amo
->args
) == 0
9045 && amo
->pinfo
!= INSN_MACRO
9046 && is_opcode_valid (amo
)
9047 && is_size_valid (amo
))
9049 if (is_delay_slot_valid (amo
))
9059 gas_assert (amo
->name
);
9061 while (strcmp (name
, amo
->name
) == 0);
9064 create_insn (&insn
, mo
);
9077 macro_read_relocs (&args
, r
);
9078 gas_assert (*r
== BFD_RELOC_GPREL16
9079 || *r
== BFD_RELOC_MIPS_HIGHER
9080 || *r
== BFD_RELOC_HI16_S
9081 || *r
== BFD_RELOC_LO16
9082 || *r
== BFD_RELOC_MIPS_GOT_OFST
9083 || (mips_opts
.micromips
9084 && (*r
== BFD_RELOC_16
9085 || *r
== BFD_RELOC_MIPS_GOT16
9086 || *r
== BFD_RELOC_MIPS_CALL16
9087 || *r
== BFD_RELOC_MIPS_GOT_HI16
9088 || *r
== BFD_RELOC_MIPS_GOT_LO16
9089 || *r
== BFD_RELOC_MIPS_CALL_HI16
9090 || *r
== BFD_RELOC_MIPS_CALL_LO16
9091 || *r
== BFD_RELOC_MIPS_SUB
9092 || *r
== BFD_RELOC_MIPS_GOT_PAGE
9093 || *r
== BFD_RELOC_MIPS_HIGHEST
9094 || *r
== BFD_RELOC_MIPS_GOT_DISP
9095 || *r
== BFD_RELOC_MIPS_TLS_GD
9096 || *r
== BFD_RELOC_MIPS_TLS_LDM
9097 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_HI16
9098 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_LO16
9099 || *r
== BFD_RELOC_MIPS_TLS_GOTTPREL
9100 || *r
== BFD_RELOC_MIPS_TLS_TPREL_HI16
9101 || *r
== BFD_RELOC_MIPS_TLS_TPREL_LO16
)));
9105 macro_read_relocs (&args
, r
);
9109 macro_read_relocs (&args
, r
);
9110 gas_assert (ep
!= NULL
9111 && (ep
->X_op
== O_constant
9112 || (ep
->X_op
== O_symbol
9113 && (*r
== BFD_RELOC_MIPS_HIGHEST
9114 || *r
== BFD_RELOC_HI16_S
9115 || *r
== BFD_RELOC_HI16
9116 || *r
== BFD_RELOC_GPREL16
9117 || *r
== BFD_RELOC_MIPS_GOT_HI16
9118 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
9122 gas_assert (ep
!= NULL
);
9125 * This allows macro() to pass an immediate expression for
9126 * creating short branches without creating a symbol.
9128 * We don't allow branch relaxation for these branches, as
9129 * they should only appear in ".set nomacro" anyway.
9131 if (ep
->X_op
== O_constant
)
9133 /* For microMIPS we always use relocations for branches.
9134 So we should not resolve immediate values. */
9135 gas_assert (!mips_opts
.micromips
);
9137 if ((ep
->X_add_number
& 3) != 0)
9138 as_bad (_("branch to misaligned address (0x%lx)"),
9139 (unsigned long) ep
->X_add_number
);
9140 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
9141 as_bad (_("branch address range overflow (0x%lx)"),
9142 (unsigned long) ep
->X_add_number
);
9143 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
9147 *r
= BFD_RELOC_16_PCREL_S2
;
9151 gas_assert (ep
!= NULL
);
9152 *r
= BFD_RELOC_MIPS_JMP
;
9156 operand
= (mips_opts
.micromips
9157 ? decode_micromips_operand (fmt
)
9158 : decode_mips_operand (fmt
));
9162 uval
= va_arg (args
, int);
9163 if (operand
->type
== OP_CLO_CLZ_DEST
)
9164 uval
|= (uval
<< 5);
9165 insn_insert_operand (&insn
, operand
, uval
);
9167 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
9173 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9175 append_insn (&insn
, ep
, r
, true);
9179 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
9182 struct mips_opcode
*mo
;
9183 struct mips_cl_insn insn
;
9184 const struct mips_operand
*operand
;
9185 bfd_reloc_code_real_type r
[3]
9186 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
9188 mo
= (struct mips_opcode
*) str_hash_find (mips16_op_hash
, name
);
9190 gas_assert (strcmp (name
, mo
->name
) == 0);
9192 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
9195 gas_assert (mo
->name
);
9196 gas_assert (strcmp (name
, mo
->name
) == 0);
9199 create_insn (&insn
, mo
);
9236 gas_assert (ep
!= NULL
);
9238 if (ep
->X_op
!= O_constant
)
9239 *r
= (int) BFD_RELOC_UNUSED
+ c
;
9240 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
9242 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
9244 *r
= BFD_RELOC_UNUSED
;
9250 operand
= decode_mips16_operand (c
, false);
9254 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9259 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9261 append_insn (&insn
, ep
, r
, true);
9265 * Generate a "jalr" instruction with a relocation hint to the called
9266 * function. This occurs in NewABI PIC code.
9269 macro_build_jalr (expressionS
*ep
, int cprestore
)
9271 static const bfd_reloc_code_real_type jalr_relocs
[2]
9272 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9273 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9277 if (MIPS_JALR_HINT_P (ep
))
9282 if (mips_opts
.micromips
)
9284 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9285 ? "jalr" : "jalrs");
9286 if (MIPS_JALR_HINT_P (ep
)
9288 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9289 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9291 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9294 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9295 if (MIPS_JALR_HINT_P (ep
))
9296 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, false, jalr_reloc
);
9300 * Generate a "lui" instruction.
9303 macro_build_lui (expressionS
*ep
, int regnum
)
9305 gas_assert (! mips_opts
.mips16
);
9307 if (ep
->X_op
!= O_constant
)
9309 gas_assert (ep
->X_op
== O_symbol
);
9310 /* _gp_disp is a special case, used from s_cpload.
9311 __gnu_local_gp is used if mips_no_shared. */
9312 gas_assert (mips_pic
== NO_PIC
9314 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9315 || (! mips_in_shared
9316 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9317 "__gnu_local_gp") == 0));
9320 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9323 /* Generate a sequence of instructions to do a load or store from a constant
9324 offset off of a base register (breg) into/from a target register (treg),
9325 using AT if necessary. */
9327 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9328 int treg
, int breg
, int dbl
)
9330 gas_assert (ep
->X_op
== O_constant
);
9332 /* Sign-extending 32-bit constants makes their handling easier. */
9334 normalize_constant_expr (ep
);
9336 /* Right now, this routine can only handle signed 32-bit constants. */
9337 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9338 as_warn (_("operand overflow"));
9340 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9342 /* Signed 16-bit offset will fit in the op. Easy! */
9343 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9347 /* 32-bit offset, need multiple instructions and AT, like:
9348 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9349 addu $tempreg,$tempreg,$breg
9350 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9351 to handle the complete offset. */
9352 macro_build_lui (ep
, AT
);
9353 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9354 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9357 as_bad (_("macro used $at after \".set noat\""));
9362 * Generates code to set the $at register to true (one)
9363 * if reg is less than the immediate expression.
9366 set_at (int reg
, int unsignedp
)
9368 if (imm_expr
.X_add_number
>= -0x8000
9369 && imm_expr
.X_add_number
< 0x8000)
9370 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9371 AT
, reg
, BFD_RELOC_LO16
);
9374 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9375 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9379 /* Count the leading zeroes by performing a binary chop. This is a
9380 bulky bit of source, but performance is a LOT better for the
9381 majority of values than a simple loop to count the bits:
9382 for (lcnt = 0; (lcnt < 32); lcnt++)
9383 if ((v) & (1 << (31 - lcnt)))
9385 However it is not code size friendly, and the gain will drop a bit
9386 on certain cached systems.
9388 #define COUNT_TOP_ZEROES(v) \
9389 (((v) & ~0xffff) == 0 \
9390 ? ((v) & ~0xff) == 0 \
9391 ? ((v) & ~0xf) == 0 \
9392 ? ((v) & ~0x3) == 0 \
9393 ? ((v) & ~0x1) == 0 \
9398 : ((v) & ~0x7) == 0 \
9401 : ((v) & ~0x3f) == 0 \
9402 ? ((v) & ~0x1f) == 0 \
9405 : ((v) & ~0x7f) == 0 \
9408 : ((v) & ~0xfff) == 0 \
9409 ? ((v) & ~0x3ff) == 0 \
9410 ? ((v) & ~0x1ff) == 0 \
9413 : ((v) & ~0x7ff) == 0 \
9416 : ((v) & ~0x3fff) == 0 \
9417 ? ((v) & ~0x1fff) == 0 \
9420 : ((v) & ~0x7fff) == 0 \
9423 : ((v) & ~0xffffff) == 0 \
9424 ? ((v) & ~0xfffff) == 0 \
9425 ? ((v) & ~0x3ffff) == 0 \
9426 ? ((v) & ~0x1ffff) == 0 \
9429 : ((v) & ~0x7ffff) == 0 \
9432 : ((v) & ~0x3fffff) == 0 \
9433 ? ((v) & ~0x1fffff) == 0 \
9436 : ((v) & ~0x7fffff) == 0 \
9439 : ((v) & ~0xfffffff) == 0 \
9440 ? ((v) & ~0x3ffffff) == 0 \
9441 ? ((v) & ~0x1ffffff) == 0 \
9444 : ((v) & ~0x7ffffff) == 0 \
9447 : ((v) & ~0x3fffffff) == 0 \
9448 ? ((v) & ~0x1fffffff) == 0 \
9451 : ((v) & ~0x7fffffff) == 0 \
9456 * This routine generates the least number of instructions necessary to load
9457 * an absolute expression value into a register.
9460 load_register (int reg
, expressionS
*ep
, int dbl
)
9463 expressionS hi32
, lo32
;
9465 if (ep
->X_op
!= O_big
)
9467 gas_assert (ep
->X_op
== O_constant
);
9469 /* Sign-extending 32-bit constants makes their handling easier. */
9471 normalize_constant_expr (ep
);
9473 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9475 /* We can handle 16 bit signed values with an addiu to
9476 $zero. No need to ever use daddiu here, since $zero and
9477 the result are always correct in 32 bit mode. */
9478 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9481 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9483 /* We can handle 16 bit unsigned values with an ori to
9485 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9488 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9490 /* 32 bit values require an lui. */
9491 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9492 if ((ep
->X_add_number
& 0xffff) != 0)
9493 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9498 /* The value is larger than 32 bits. */
9500 if (!dbl
|| GPR_SIZE
== 32)
9504 sprintf_vma (value
, ep
->X_add_number
);
9505 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9506 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9510 if (ep
->X_op
!= O_big
)
9513 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9514 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9515 hi32
.X_add_number
&= 0xffffffff;
9517 lo32
.X_add_number
&= 0xffffffff;
9521 gas_assert (ep
->X_add_number
> 2);
9522 if (ep
->X_add_number
== 3)
9523 generic_bignum
[3] = 0;
9524 else if (ep
->X_add_number
> 4)
9525 as_bad (_("number larger than 64 bits"));
9526 lo32
.X_op
= O_constant
;
9527 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9528 hi32
.X_op
= O_constant
;
9529 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9532 if (hi32
.X_add_number
== 0)
9537 unsigned long hi
, lo
;
9539 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9541 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9543 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9546 if (lo32
.X_add_number
& 0x80000000)
9548 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9549 if (lo32
.X_add_number
& 0xffff)
9550 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9555 /* Check for 16bit shifted constant. We know that hi32 is
9556 non-zero, so start the mask on the first bit of the hi32
9561 unsigned long himask
, lomask
;
9565 himask
= 0xffff >> (32 - shift
);
9566 lomask
= (0xffffU
<< shift
) & 0xffffffff;
9570 himask
= 0xffffU
<< (shift
- 32);
9573 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9574 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9578 tmp
.X_op
= O_constant
;
9580 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9581 | (lo32
.X_add_number
>> shift
));
9583 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9584 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9585 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9586 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9591 while (shift
<= (64 - 16));
9593 /* Find the bit number of the lowest one bit, and store the
9594 shifted value in hi/lo. */
9595 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9596 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9600 while ((lo
& 1) == 0)
9607 lo
|= (hi
& ((2UL << (bit
- 1)) - 1)) << (32 - bit
);
9614 while ((hi
& 1) == 0)
9623 /* Optimize if the shifted value is a (power of 2) - 1. */
9624 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9625 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9627 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9632 /* This instruction will set the register to be all
9634 tmp
.X_op
= O_constant
;
9635 tmp
.X_add_number
= (offsetT
) -1;
9636 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9640 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9641 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9643 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9644 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9649 /* Sign extend hi32 before calling load_register, because we can
9650 generally get better code when we load a sign extended value. */
9651 if ((hi32
.X_add_number
& 0x80000000) != 0)
9652 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9653 load_register (reg
, &hi32
, 0);
9656 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9660 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9668 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9670 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9671 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9677 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9681 mid16
.X_add_number
>>= 16;
9682 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9683 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9686 if ((lo32
.X_add_number
& 0xffff) != 0)
9687 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9691 load_delay_nop (void)
9693 if (!gpr_interlocks
)
9694 macro_build (NULL
, "nop", "");
9697 /* Load an address into a register. */
9700 load_address (int reg
, expressionS
*ep
, int *used_at
)
9702 if (ep
->X_op
!= O_constant
9703 && ep
->X_op
!= O_symbol
)
9705 as_bad (_("expression too complex"));
9706 ep
->X_op
= O_constant
;
9709 if (ep
->X_op
== O_constant
)
9711 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9715 if (mips_pic
== NO_PIC
)
9717 /* If this is a reference to a GP relative symbol, we want
9718 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9720 lui $reg,<sym> (BFD_RELOC_HI16_S)
9721 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9722 If we have an addend, we always use the latter form.
9724 With 64bit address space and a usable $at we want
9725 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9726 lui $at,<sym> (BFD_RELOC_HI16_S)
9727 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9728 daddiu $at,<sym> (BFD_RELOC_LO16)
9732 If $at is already in use, we use a path which is suboptimal
9733 on superscalar processors.
9734 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9735 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9737 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9739 daddiu $reg,<sym> (BFD_RELOC_LO16)
9741 For GP relative symbols in 64bit address space we can use
9742 the same sequence as in 32bit address space. */
9743 if (HAVE_64BIT_SYMBOLS
)
9745 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9746 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9748 relax_start (ep
->X_add_symbol
);
9749 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9750 mips_gp_register
, BFD_RELOC_GPREL16
);
9754 if (*used_at
== 0 && mips_opts
.at
)
9756 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9757 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9758 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9759 BFD_RELOC_MIPS_HIGHER
);
9760 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9761 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9762 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9767 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9768 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9769 BFD_RELOC_MIPS_HIGHER
);
9770 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9771 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9772 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9773 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9776 if (mips_relax
.sequence
)
9781 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9782 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9784 relax_start (ep
->X_add_symbol
);
9785 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9786 mips_gp_register
, BFD_RELOC_GPREL16
);
9789 macro_build_lui (ep
, reg
);
9790 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9791 reg
, reg
, BFD_RELOC_LO16
);
9792 if (mips_relax
.sequence
)
9796 else if (!mips_big_got
)
9800 /* If this is a reference to an external symbol, we want
9801 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9803 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9805 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9806 If there is a constant, it must be added in after.
9808 If we have NewABI, we want
9809 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9810 unless we're referencing a global symbol with a non-zero
9811 offset, in which case cst must be added separately. */
9814 if (ep
->X_add_number
)
9816 ex
.X_add_number
= ep
->X_add_number
;
9817 ep
->X_add_number
= 0;
9818 relax_start (ep
->X_add_symbol
);
9819 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9820 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9821 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9822 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9823 ex
.X_op
= O_constant
;
9824 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9825 reg
, reg
, BFD_RELOC_LO16
);
9826 ep
->X_add_number
= ex
.X_add_number
;
9829 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9830 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9831 if (mips_relax
.sequence
)
9836 ex
.X_add_number
= ep
->X_add_number
;
9837 ep
->X_add_number
= 0;
9838 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9839 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9841 relax_start (ep
->X_add_symbol
);
9843 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9847 if (ex
.X_add_number
!= 0)
9849 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9850 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9851 ex
.X_op
= O_constant
;
9852 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9853 reg
, reg
, BFD_RELOC_LO16
);
9857 else if (mips_big_got
)
9861 /* This is the large GOT case. If this is a reference to an
9862 external symbol, we want
9863 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9865 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9867 Otherwise, for a reference to a local symbol in old ABI, we want
9868 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9870 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9871 If there is a constant, it must be added in after.
9873 In the NewABI, for local symbols, with or without offsets, we want:
9874 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9875 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9879 ex
.X_add_number
= ep
->X_add_number
;
9880 ep
->X_add_number
= 0;
9881 relax_start (ep
->X_add_symbol
);
9882 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9883 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9884 reg
, reg
, mips_gp_register
);
9885 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9886 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9887 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9888 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9889 else if (ex
.X_add_number
)
9891 ex
.X_op
= O_constant
;
9892 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9896 ep
->X_add_number
= ex
.X_add_number
;
9898 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9899 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9900 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9901 BFD_RELOC_MIPS_GOT_OFST
);
9906 ex
.X_add_number
= ep
->X_add_number
;
9907 ep
->X_add_number
= 0;
9908 relax_start (ep
->X_add_symbol
);
9909 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9910 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9911 reg
, reg
, mips_gp_register
);
9912 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9913 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9915 if (reg_needs_delay (mips_gp_register
))
9917 /* We need a nop before loading from $gp. This special
9918 check is required because the lui which starts the main
9919 instruction stream does not refer to $gp, and so will not
9920 insert the nop which may be required. */
9921 macro_build (NULL
, "nop", "");
9923 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9924 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9926 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9930 if (ex
.X_add_number
!= 0)
9932 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9933 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9934 ex
.X_op
= O_constant
;
9935 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9943 if (!mips_opts
.at
&& *used_at
== 1)
9944 as_bad (_("macro used $at after \".set noat\""));
9947 /* Move the contents of register SOURCE into register DEST. */
9950 move_register (int dest
, int source
)
9952 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9953 instruction specifically requires a 32-bit one. */
9954 if (mips_opts
.micromips
9955 && !mips_opts
.insn32
9956 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9957 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9959 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9962 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9963 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9964 The two alternatives are:
9966 Global symbol Local symbol
9967 ------------- ------------
9968 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9970 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9972 load_got_offset emits the first instruction and add_got_offset
9973 emits the second for a 16-bit offset or add_got_offset_hilo emits
9974 a sequence to add a 32-bit offset using a scratch register. */
9977 load_got_offset (int dest
, expressionS
*local
)
9982 global
.X_add_number
= 0;
9984 relax_start (local
->X_add_symbol
);
9985 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9986 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9988 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9989 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9994 add_got_offset (int dest
, expressionS
*local
)
9998 global
.X_op
= O_constant
;
9999 global
.X_op_symbol
= NULL
;
10000 global
.X_add_symbol
= NULL
;
10001 global
.X_add_number
= local
->X_add_number
;
10003 relax_start (local
->X_add_symbol
);
10004 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
10005 dest
, dest
, BFD_RELOC_LO16
);
10007 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
10012 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
10014 expressionS global
;
10015 int hold_mips_optimize
;
10017 global
.X_op
= O_constant
;
10018 global
.X_op_symbol
= NULL
;
10019 global
.X_add_symbol
= NULL
;
10020 global
.X_add_number
= local
->X_add_number
;
10022 relax_start (local
->X_add_symbol
);
10023 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
10025 /* Set mips_optimize around the lui instruction to avoid
10026 inserting an unnecessary nop after the lw. */
10027 hold_mips_optimize
= mips_optimize
;
10029 macro_build_lui (&global
, tmp
);
10030 mips_optimize
= hold_mips_optimize
;
10031 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
10034 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
10037 /* Emit a sequence of instructions to emulate a branch likely operation.
10038 BR is an ordinary branch corresponding to one to be emulated. BRNEG
10039 is its complementing branch with the original condition negated.
10040 CALL is set if the original branch specified the link operation.
10041 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
10043 Code like this is produced in the noreorder mode:
10048 delay slot (executed only if branch taken)
10051 or, if CALL is set:
10056 delay slot (executed only if branch taken)
10059 In the reorder mode the delay slot would be filled with a nop anyway,
10060 so code produced is simply:
10065 This function is used when producing code for the microMIPS ASE that
10066 does not implement branch likely instructions in hardware. */
10069 macro_build_branch_likely (const char *br
, const char *brneg
,
10070 int call
, expressionS
*ep
, const char *fmt
,
10071 unsigned int sreg
, unsigned int treg
)
10073 int noreorder
= mips_opts
.noreorder
;
10076 gas_assert (mips_opts
.micromips
);
10077 start_noreorder ();
10080 micromips_label_expr (&expr1
);
10081 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
10082 macro_build (NULL
, "nop", "");
10083 macro_build (ep
, call
? "bal" : "b", "p");
10085 /* Set to true so that append_insn adds a label. */
10086 emit_branch_likely_macro
= true;
10090 macro_build (ep
, br
, fmt
, sreg
, treg
);
10091 macro_build (NULL
, "nop", "");
10096 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
10097 the condition code tested. EP specifies the branch target. */
10100 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
10102 const int call
= 0;
10127 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
10130 /* Emit a two-argument branch macro specified by TYPE, using SREG as
10131 the register tested. EP specifies the branch target. */
10134 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
10136 const char *brneg
= NULL
;
10146 br
= mips_opts
.micromips
? "bgez" : "bgezl";
10150 gas_assert (mips_opts
.micromips
);
10151 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
10159 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
10166 br
= mips_opts
.micromips
? "blez" : "blezl";
10173 br
= mips_opts
.micromips
? "bltz" : "bltzl";
10177 gas_assert (mips_opts
.micromips
);
10178 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
10185 if (mips_opts
.micromips
&& brneg
)
10186 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
10188 macro_build (ep
, br
, "s,p", sreg
);
10191 /* Emit a three-argument branch macro specified by TYPE, using SREG and
10192 TREG as the registers tested. EP specifies the branch target. */
10195 macro_build_branch_rsrt (int type
, expressionS
*ep
,
10196 unsigned int sreg
, unsigned int treg
)
10198 const char *brneg
= NULL
;
10199 const int call
= 0;
10210 br
= mips_opts
.micromips
? "beq" : "beql";
10219 br
= mips_opts
.micromips
? "bne" : "bnel";
10225 if (mips_opts
.micromips
&& brneg
)
10226 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
10228 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
10231 /* Return the high part that should be loaded in order to make the low
10232 part of VALUE accessible using an offset of OFFBITS bits. */
10235 offset_high_part (offsetT value
, unsigned int offbits
)
10242 bias
= 1 << (offbits
- 1);
10243 low_mask
= bias
* 2 - 1;
10244 return (value
+ bias
) & ~low_mask
;
10247 /* Return true if the value stored in offset_expr and offset_reloc
10248 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10249 amount that the caller wants to add without inducing overflow
10250 and ALIGN is the known alignment of the value in bytes. */
10253 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10257 /* Accept any relocation operator if overflow isn't a concern. */
10258 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10261 /* These relocations are guaranteed not to overflow in correct links. */
10262 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10263 || gprel16_reloc_p (*offset_reloc
))
10266 if (offset_expr
.X_op
== O_constant
10267 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10268 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10275 * This routine implements the seemingly endless macro or synthesized
10276 * instructions and addressing modes in the mips assembly language. Many
10277 * of these macros are simple and are similar to each other. These could
10278 * probably be handled by some kind of table or grammar approach instead of
10279 * this verbose method. Others are not simple macros but are more like
10280 * optimizing code generation.
10281 * One interesting optimization is when several store macros appear
10282 * consecutively that would load AT with the upper half of the same address.
10283 * The ensuing load upper instructions are omitted. This implies some kind
10284 * of global optimization. We currently only optimize within a single macro.
10285 * For many of the load and store macros if the address is specified as a
10286 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10287 * first load register 'at' with zero and use it as the base register. The
10288 * mips assembler simply uses register $zero. Just one tiny optimization
10292 macro (struct mips_cl_insn
*ip
, char *str
)
10294 const struct mips_operand_array
*operands
;
10295 unsigned int breg
, i
;
10296 unsigned int tempreg
;
10299 expressionS label_expr
;
10314 int ll_sc_paired
= 0;
10317 int hold_mips_optimize
;
10318 unsigned int align
;
10319 unsigned int op
[MAX_OPERANDS
];
10321 gas_assert (! mips_opts
.mips16
);
10323 operands
= insn_operands (ip
);
10324 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10325 if (operands
->operand
[i
])
10326 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10330 mask
= ip
->insn_mo
->mask
;
10332 label_expr
.X_op
= O_constant
;
10333 label_expr
.X_op_symbol
= NULL
;
10334 label_expr
.X_add_symbol
= NULL
;
10335 label_expr
.X_add_number
= 0;
10337 expr1
.X_op
= O_constant
;
10338 expr1
.X_op_symbol
= NULL
;
10339 expr1
.X_add_symbol
= NULL
;
10340 expr1
.X_add_number
= 1;
10347 /* Fall through. */
10355 start_noreorder ();
10357 if (mips_opts
.micromips
)
10358 micromips_label_expr (&label_expr
);
10360 label_expr
.X_add_number
= 8;
10361 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10362 if (op
[0] == op
[1])
10363 macro_build (NULL
, "nop", "");
10365 move_register (op
[0], op
[1]);
10366 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10367 if (mips_opts
.micromips
)
10368 micromips_add_label ();
10376 if (ISA_IS_R6 (mips_opts
.isa
))
10388 if (!mips_opts
.micromips
&& !ISA_IS_R6 (mips_opts
.isa
))
10390 if (imm_expr
.X_add_number
>= -0x200
10391 && imm_expr
.X_add_number
< 0x200
10392 && !ISA_IS_R6 (mips_opts
.isa
))
10394 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10395 (int) imm_expr
.X_add_number
);
10404 if (imm_expr
.X_add_number
>= -0x8000
10405 && imm_expr
.X_add_number
< 0x8000)
10407 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10412 load_register (AT
, &imm_expr
, dbl
);
10413 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10432 if (imm_expr
.X_add_number
>= 0
10433 && imm_expr
.X_add_number
< 0x10000)
10435 if (mask
!= M_NOR_I
)
10436 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10439 macro_build (&imm_expr
, "ori", "t,r,i",
10440 op
[0], op
[1], BFD_RELOC_LO16
);
10441 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10447 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10448 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10452 switch (imm_expr
.X_add_number
)
10455 macro_build (NULL
, "nop", "");
10458 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10462 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10463 (int) imm_expr
.X_add_number
);
10466 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10467 (unsigned long) imm_expr
.X_add_number
);
10476 gas_assert (mips_opts
.micromips
);
10477 macro_build_branch_ccl (mask
, &offset_expr
,
10478 EXTRACT_OPERAND (1, BCC
, *ip
));
10485 if (imm_expr
.X_add_number
== 0)
10491 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10493 /* Fall through. */
10496 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10501 /* Fall through. */
10504 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10505 else if (op
[0] == 0)
10506 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10510 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10511 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10512 &offset_expr
, AT
, ZERO
);
10522 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10527 /* Fall through. */
10529 /* Check for > max integer. */
10530 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10533 /* Result is always false. */
10535 macro_build (NULL
, "nop", "");
10537 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10540 ++imm_expr
.X_add_number
;
10541 /* Fall through. */
10544 if (mask
== M_BGEL_I
)
10546 if (imm_expr
.X_add_number
== 0)
10548 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10549 &offset_expr
, op
[0]);
10552 if (imm_expr
.X_add_number
== 1)
10554 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10555 &offset_expr
, op
[0]);
10558 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10561 /* Result is always true. */
10562 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10563 macro_build (&offset_expr
, "b", "p");
10568 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10569 &offset_expr
, AT
, ZERO
);
10574 /* Fall through. */
10578 else if (op
[0] == 0)
10579 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10580 &offset_expr
, ZERO
, op
[1]);
10584 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10585 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10586 &offset_expr
, AT
, ZERO
);
10592 /* Fall through. */
10596 && imm_expr
.X_add_number
== -1))
10598 ++imm_expr
.X_add_number
;
10599 /* Fall through. */
10602 if (mask
== M_BGEUL_I
)
10604 if (imm_expr
.X_add_number
== 0)
10606 else if (imm_expr
.X_add_number
== 1)
10607 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10608 &offset_expr
, op
[0], ZERO
);
10613 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10614 &offset_expr
, AT
, ZERO
);
10620 /* Fall through. */
10623 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10624 else if (op
[0] == 0)
10625 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10629 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10630 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10631 &offset_expr
, AT
, ZERO
);
10637 /* Fall through. */
10640 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10641 &offset_expr
, op
[0], ZERO
);
10642 else if (op
[0] == 0)
10647 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10648 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10649 &offset_expr
, AT
, ZERO
);
10655 /* Fall through. */
10658 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10659 else if (op
[0] == 0)
10660 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10664 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10665 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10666 &offset_expr
, AT
, ZERO
);
10672 /* Fall through. */
10674 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10676 ++imm_expr
.X_add_number
;
10677 /* Fall through. */
10680 if (mask
== M_BLTL_I
)
10682 if (imm_expr
.X_add_number
== 0)
10683 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10684 else if (imm_expr
.X_add_number
== 1)
10685 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10690 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10691 &offset_expr
, AT
, ZERO
);
10697 /* Fall through. */
10700 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10701 &offset_expr
, op
[0], ZERO
);
10702 else if (op
[0] == 0)
10707 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10708 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10709 &offset_expr
, AT
, ZERO
);
10715 /* Fall through. */
10719 && imm_expr
.X_add_number
== -1))
10721 ++imm_expr
.X_add_number
;
10722 /* Fall through. */
10725 if (mask
== M_BLTUL_I
)
10727 if (imm_expr
.X_add_number
== 0)
10729 else if (imm_expr
.X_add_number
== 1)
10730 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10731 &offset_expr
, op
[0], ZERO
);
10736 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10737 &offset_expr
, AT
, ZERO
);
10743 /* Fall through. */
10746 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10747 else if (op
[0] == 0)
10748 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10752 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10753 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10754 &offset_expr
, AT
, ZERO
);
10760 /* Fall through. */
10764 else if (op
[0] == 0)
10765 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10766 &offset_expr
, ZERO
, op
[1]);
10770 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10771 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10772 &offset_expr
, AT
, ZERO
);
10778 /* Fall through. */
10784 /* Fall through. */
10790 as_warn (_("divide by zero"));
10792 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10794 macro_build (NULL
, "break", BRK_FMT
, 7);
10798 start_noreorder ();
10801 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10802 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10806 if (mips_opts
.micromips
)
10807 micromips_label_expr (&label_expr
);
10809 label_expr
.X_add_number
= 8;
10810 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10811 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10812 macro_build (NULL
, "break", BRK_FMT
, 7);
10813 if (mips_opts
.micromips
)
10814 micromips_add_label ();
10816 expr1
.X_add_number
= -1;
10818 load_register (AT
, &expr1
, dbl
);
10819 if (mips_opts
.micromips
)
10820 micromips_label_expr (&label_expr
);
10822 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10823 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10826 expr1
.X_add_number
= 1;
10827 load_register (AT
, &expr1
, dbl
);
10828 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10832 expr1
.X_add_number
= 0x80000000;
10833 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10837 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10838 /* We want to close the noreorder block as soon as possible, so
10839 that later insns are available for delay slot filling. */
10844 if (mips_opts
.micromips
)
10845 micromips_label_expr (&label_expr
);
10847 label_expr
.X_add_number
= 8;
10848 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10849 macro_build (NULL
, "nop", "");
10851 /* We want to close the noreorder block as soon as possible, so
10852 that later insns are available for delay slot filling. */
10855 macro_build (NULL
, "break", BRK_FMT
, 6);
10857 if (mips_opts
.micromips
)
10858 micromips_add_label ();
10859 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10898 if (imm_expr
.X_add_number
== 0)
10900 as_warn (_("divide by zero"));
10902 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10904 macro_build (NULL
, "break", BRK_FMT
, 7);
10907 if (imm_expr
.X_add_number
== 1)
10909 if (strcmp (s2
, "mflo") == 0)
10910 move_register (op
[0], op
[1]);
10912 move_register (op
[0], ZERO
);
10915 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10917 if (strcmp (s2
, "mflo") == 0)
10918 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10920 move_register (op
[0], ZERO
);
10925 load_register (AT
, &imm_expr
, dbl
);
10926 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10927 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10946 start_noreorder ();
10949 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10950 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10951 /* We want to close the noreorder block as soon as possible, so
10952 that later insns are available for delay slot filling. */
10957 if (mips_opts
.micromips
)
10958 micromips_label_expr (&label_expr
);
10960 label_expr
.X_add_number
= 8;
10961 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10962 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10964 /* We want to close the noreorder block as soon as possible, so
10965 that later insns are available for delay slot filling. */
10967 macro_build (NULL
, "break", BRK_FMT
, 7);
10968 if (mips_opts
.micromips
)
10969 micromips_add_label ();
10971 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10976 /* Fall through. */
10982 /* Fall through. */
10985 /* Load the address of a symbol into a register. If breg is not
10986 zero, we then add a base register to it. */
10989 if (dbl
&& GPR_SIZE
== 32)
10990 as_warn (_("dla used to load 32-bit register; recommend using la "
10993 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10994 as_warn (_("la used to load 64-bit address; recommend using dla "
10997 if (small_offset_p (0, align
, 16))
10999 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
11000 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
11004 if (mips_opts
.at
&& (op
[0] == breg
))
11012 if (offset_expr
.X_op
!= O_symbol
11013 && offset_expr
.X_op
!= O_constant
)
11015 as_bad (_("expression too complex"));
11016 offset_expr
.X_op
= O_constant
;
11019 if (offset_expr
.X_op
== O_constant
)
11020 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
11021 else if (mips_pic
== NO_PIC
)
11023 /* If this is a reference to a GP relative symbol, we want
11024 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
11026 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11027 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11028 If we have a constant, we need two instructions anyhow,
11029 so we may as well always use the latter form.
11031 With 64bit address space and a usable $at we want
11032 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11033 lui $at,<sym> (BFD_RELOC_HI16_S)
11034 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11035 daddiu $at,<sym> (BFD_RELOC_LO16)
11037 daddu $tempreg,$tempreg,$at
11039 If $at is already in use, we use a path which is suboptimal
11040 on superscalar processors.
11041 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11042 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11044 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11046 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
11048 For GP relative symbols in 64bit address space we can use
11049 the same sequence as in 32bit address space. */
11050 if (HAVE_64BIT_SYMBOLS
)
11052 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11053 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11055 relax_start (offset_expr
.X_add_symbol
);
11056 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11057 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11061 if (used_at
== 0 && mips_opts
.at
)
11063 macro_build (&offset_expr
, "lui", LUI_FMT
,
11064 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11065 macro_build (&offset_expr
, "lui", LUI_FMT
,
11066 AT
, BFD_RELOC_HI16_S
);
11067 macro_build (&offset_expr
, "daddiu", "t,r,j",
11068 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11069 macro_build (&offset_expr
, "daddiu", "t,r,j",
11070 AT
, AT
, BFD_RELOC_LO16
);
11071 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11072 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11077 macro_build (&offset_expr
, "lui", LUI_FMT
,
11078 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11079 macro_build (&offset_expr
, "daddiu", "t,r,j",
11080 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11081 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11082 macro_build (&offset_expr
, "daddiu", "t,r,j",
11083 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
11084 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11085 macro_build (&offset_expr
, "daddiu", "t,r,j",
11086 tempreg
, tempreg
, BFD_RELOC_LO16
);
11089 if (mips_relax
.sequence
)
11094 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11095 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11097 relax_start (offset_expr
.X_add_symbol
);
11098 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11099 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11102 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11103 as_bad (_("offset too large"));
11104 macro_build_lui (&offset_expr
, tempreg
);
11105 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11106 tempreg
, tempreg
, BFD_RELOC_LO16
);
11107 if (mips_relax
.sequence
)
11111 else if (!mips_big_got
&& !HAVE_NEWABI
)
11113 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11115 /* If this is a reference to an external symbol, and there
11116 is no constant, we want
11117 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11118 or for lca or if tempreg is PIC_CALL_REG
11119 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11120 For a local symbol, we want
11121 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11123 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11125 If we have a small constant, and this is a reference to
11126 an external symbol, we want
11127 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11129 addiu $tempreg,$tempreg,<constant>
11130 For a local symbol, we want the same instruction
11131 sequence, but we output a BFD_RELOC_LO16 reloc on the
11134 If we have a large constant, and this is a reference to
11135 an external symbol, we want
11136 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11137 lui $at,<hiconstant>
11138 addiu $at,$at,<loconstant>
11139 addu $tempreg,$tempreg,$at
11140 For a local symbol, we want the same instruction
11141 sequence, but we output a BFD_RELOC_LO16 reloc on the
11145 if (offset_expr
.X_add_number
== 0)
11147 if (mips_pic
== SVR4_PIC
11149 && (call
|| tempreg
== PIC_CALL_REG
))
11150 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
11152 relax_start (offset_expr
.X_add_symbol
);
11153 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11154 lw_reloc_type
, mips_gp_register
);
11157 /* We're going to put in an addu instruction using
11158 tempreg, so we may as well insert the nop right
11163 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11164 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11166 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11167 tempreg
, tempreg
, BFD_RELOC_LO16
);
11169 /* FIXME: If breg == 0, and the next instruction uses
11170 $tempreg, then if this variant case is used an extra
11171 nop will be generated. */
11173 else if (offset_expr
.X_add_number
>= -0x8000
11174 && offset_expr
.X_add_number
< 0x8000)
11176 load_got_offset (tempreg
, &offset_expr
);
11178 add_got_offset (tempreg
, &offset_expr
);
11182 expr1
.X_add_number
= offset_expr
.X_add_number
;
11183 offset_expr
.X_add_number
=
11184 SEXT_16BIT (offset_expr
.X_add_number
);
11185 load_got_offset (tempreg
, &offset_expr
);
11186 offset_expr
.X_add_number
= expr1
.X_add_number
;
11187 /* If we are going to add in a base register, and the
11188 target register and the base register are the same,
11189 then we are using AT as a temporary register. Since
11190 we want to load the constant into AT, we add our
11191 current AT (from the global offset table) and the
11192 register into the register now, and pretend we were
11193 not using a base register. */
11197 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11202 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
11206 else if (!mips_big_got
&& HAVE_NEWABI
)
11208 int add_breg_early
= 0;
11210 /* If this is a reference to an external, and there is no
11211 constant, or local symbol (*), with or without a
11213 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11214 or for lca or if tempreg is PIC_CALL_REG
11215 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11217 If we have a small constant, and this is a reference to
11218 an external symbol, we want
11219 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11220 addiu $tempreg,$tempreg,<constant>
11222 If we have a large constant, and this is a reference to
11223 an external symbol, we want
11224 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11225 lui $at,<hiconstant>
11226 addiu $at,$at,<loconstant>
11227 addu $tempreg,$tempreg,$at
11229 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11230 local symbols, even though it introduces an additional
11233 if (offset_expr
.X_add_number
)
11235 expr1
.X_add_number
= offset_expr
.X_add_number
;
11236 offset_expr
.X_add_number
= 0;
11238 relax_start (offset_expr
.X_add_symbol
);
11239 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11240 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11242 if (expr1
.X_add_number
>= -0x8000
11243 && expr1
.X_add_number
< 0x8000)
11245 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11246 tempreg
, tempreg
, BFD_RELOC_LO16
);
11248 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11252 /* If we are going to add in a base register, and the
11253 target register and the base register are the same,
11254 then we are using AT as a temporary register. Since
11255 we want to load the constant into AT, we add our
11256 current AT (from the global offset table) and the
11257 register into the register now, and pretend we were
11258 not using a base register. */
11263 gas_assert (tempreg
== AT
);
11264 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11267 add_breg_early
= 1;
11270 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11271 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11277 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11280 offset_expr
.X_add_number
= expr1
.X_add_number
;
11282 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11283 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11284 if (add_breg_early
)
11286 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11287 op
[0], tempreg
, breg
);
11293 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11295 relax_start (offset_expr
.X_add_symbol
);
11296 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11297 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11299 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11300 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11305 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11306 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11309 else if (mips_big_got
&& !HAVE_NEWABI
)
11312 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11313 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11314 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11316 /* This is the large GOT case. If this is a reference to an
11317 external symbol, and there is no constant, we want
11318 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11319 addu $tempreg,$tempreg,$gp
11320 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11321 or for lca or if tempreg is PIC_CALL_REG
11322 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11323 addu $tempreg,$tempreg,$gp
11324 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11325 For a local symbol, we want
11326 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11328 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11330 If we have a small constant, and this is a reference to
11331 an external symbol, we want
11332 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11333 addu $tempreg,$tempreg,$gp
11334 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11336 addiu $tempreg,$tempreg,<constant>
11337 For a local symbol, we want
11338 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11340 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11342 If we have a large constant, and this is a reference to
11343 an external symbol, we want
11344 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11345 addu $tempreg,$tempreg,$gp
11346 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11347 lui $at,<hiconstant>
11348 addiu $at,$at,<loconstant>
11349 addu $tempreg,$tempreg,$at
11350 For a local symbol, we want
11351 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11352 lui $at,<hiconstant>
11353 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11354 addu $tempreg,$tempreg,$at
11357 expr1
.X_add_number
= offset_expr
.X_add_number
;
11358 offset_expr
.X_add_number
= 0;
11359 relax_start (offset_expr
.X_add_symbol
);
11360 gpdelay
= reg_needs_delay (mips_gp_register
);
11361 if (expr1
.X_add_number
== 0 && breg
== 0
11362 && (call
|| tempreg
== PIC_CALL_REG
))
11364 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11365 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11367 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11368 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11369 tempreg
, tempreg
, mips_gp_register
);
11370 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11371 tempreg
, lw_reloc_type
, tempreg
);
11372 if (expr1
.X_add_number
== 0)
11376 /* We're going to put in an addu instruction using
11377 tempreg, so we may as well insert the nop right
11382 else if (expr1
.X_add_number
>= -0x8000
11383 && expr1
.X_add_number
< 0x8000)
11386 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11387 tempreg
, tempreg
, BFD_RELOC_LO16
);
11393 /* If we are going to add in a base register, and the
11394 target register and the base register are the same,
11395 then we are using AT as a temporary register. Since
11396 we want to load the constant into AT, we add our
11397 current AT (from the global offset table) and the
11398 register into the register now, and pretend we were
11399 not using a base register. */
11404 gas_assert (tempreg
== AT
);
11406 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11411 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11412 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11416 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11421 /* This is needed because this instruction uses $gp, but
11422 the first instruction on the main stream does not. */
11423 macro_build (NULL
, "nop", "");
11426 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11427 local_reloc_type
, mips_gp_register
);
11428 if (expr1
.X_add_number
>= -0x8000
11429 && expr1
.X_add_number
< 0x8000)
11432 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11433 tempreg
, tempreg
, BFD_RELOC_LO16
);
11434 /* FIXME: If add_number is 0, and there was no base
11435 register, the external symbol case ended with a load,
11436 so if the symbol turns out to not be external, and
11437 the next instruction uses tempreg, an unnecessary nop
11438 will be inserted. */
11444 /* We must add in the base register now, as in the
11445 external symbol case. */
11446 gas_assert (tempreg
== AT
);
11448 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11451 /* We set breg to 0 because we have arranged to add
11452 it in in both cases. */
11456 macro_build_lui (&expr1
, AT
);
11457 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11458 AT
, AT
, BFD_RELOC_LO16
);
11459 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11460 tempreg
, tempreg
, AT
);
11465 else if (mips_big_got
&& HAVE_NEWABI
)
11467 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11468 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11469 int add_breg_early
= 0;
11471 /* This is the large GOT case. If this is a reference to an
11472 external symbol, and there is no constant, we want
11473 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11474 add $tempreg,$tempreg,$gp
11475 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11476 or for lca or if tempreg is PIC_CALL_REG
11477 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11478 add $tempreg,$tempreg,$gp
11479 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11481 If we have a small constant, and this is a reference to
11482 an external symbol, we want
11483 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11484 add $tempreg,$tempreg,$gp
11485 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11486 addi $tempreg,$tempreg,<constant>
11488 If we have a large constant, and this is a reference to
11489 an external symbol, we want
11490 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11491 addu $tempreg,$tempreg,$gp
11492 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11493 lui $at,<hiconstant>
11494 addi $at,$at,<loconstant>
11495 add $tempreg,$tempreg,$at
11497 If we have NewABI, and we know it's a local symbol, we want
11498 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11499 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11500 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11502 relax_start (offset_expr
.X_add_symbol
);
11504 expr1
.X_add_number
= offset_expr
.X_add_number
;
11505 offset_expr
.X_add_number
= 0;
11507 if (expr1
.X_add_number
== 0 && breg
== 0
11508 && (call
|| tempreg
== PIC_CALL_REG
))
11510 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11511 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11513 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11514 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11515 tempreg
, tempreg
, mips_gp_register
);
11516 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11517 tempreg
, lw_reloc_type
, tempreg
);
11519 if (expr1
.X_add_number
== 0)
11521 else if (expr1
.X_add_number
>= -0x8000
11522 && expr1
.X_add_number
< 0x8000)
11524 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11525 tempreg
, tempreg
, BFD_RELOC_LO16
);
11527 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11531 /* If we are going to add in a base register, and the
11532 target register and the base register are the same,
11533 then we are using AT as a temporary register. Since
11534 we want to load the constant into AT, we add our
11535 current AT (from the global offset table) and the
11536 register into the register now, and pretend we were
11537 not using a base register. */
11542 gas_assert (tempreg
== AT
);
11543 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11546 add_breg_early
= 1;
11549 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11550 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11555 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11558 offset_expr
.X_add_number
= expr1
.X_add_number
;
11559 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11560 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11561 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11562 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11563 if (add_breg_early
)
11565 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11566 op
[0], tempreg
, breg
);
11576 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11580 gas_assert (!mips_opts
.micromips
);
11581 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11585 gas_assert (!mips_opts
.micromips
);
11586 macro_build (NULL
, "c2", "C", 0x02);
11590 gas_assert (!mips_opts
.micromips
);
11591 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11595 gas_assert (!mips_opts
.micromips
);
11596 macro_build (NULL
, "c2", "C", 3);
11600 gas_assert (!mips_opts
.micromips
);
11601 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11605 /* The j instruction may not be used in PIC code, since it
11606 requires an absolute address. We convert it to a b
11608 if (mips_pic
== NO_PIC
)
11609 macro_build (&offset_expr
, "j", "a");
11611 macro_build (&offset_expr
, "b", "p");
11614 /* The jal instructions must be handled as macros because when
11615 generating PIC code they expand to multi-instruction
11616 sequences. Normally they are simple instructions. */
11620 /* Fall through. */
11622 gas_assert (mips_opts
.micromips
);
11623 if (mips_opts
.insn32
)
11625 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11633 /* Fall through. */
11636 if (mips_pic
== NO_PIC
)
11638 s
= jals
? "jalrs" : "jalr";
11639 if (mips_opts
.micromips
11640 && !mips_opts
.insn32
11642 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11643 macro_build (NULL
, s
, "mj", op
[1]);
11645 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11649 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11650 && mips_cprestore_offset
>= 0);
11652 if (op
[1] != PIC_CALL_REG
)
11653 as_warn (_("MIPS PIC call to register other than $25"));
11655 s
= ((mips_opts
.micromips
11656 && !mips_opts
.insn32
11657 && (!mips_opts
.noreorder
|| cprestore
))
11658 ? "jalrs" : "jalr");
11659 if (mips_opts
.micromips
11660 && !mips_opts
.insn32
11662 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11663 macro_build (NULL
, s
, "mj", op
[1]);
11665 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11666 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11668 if (mips_cprestore_offset
< 0)
11669 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11672 if (!mips_frame_reg_valid
)
11674 as_warn (_("no .frame pseudo-op used in PIC code"));
11675 /* Quiet this warning. */
11676 mips_frame_reg_valid
= 1;
11678 if (!mips_cprestore_valid
)
11680 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11681 /* Quiet this warning. */
11682 mips_cprestore_valid
= 1;
11684 if (mips_opts
.noreorder
)
11685 macro_build (NULL
, "nop", "");
11686 expr1
.X_add_number
= mips_cprestore_offset
;
11687 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11690 HAVE_64BIT_ADDRESSES
);
11698 gas_assert (mips_opts
.micromips
);
11699 if (mips_opts
.insn32
)
11701 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11705 /* Fall through. */
11707 if (mips_pic
== NO_PIC
)
11708 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11709 else if (mips_pic
== SVR4_PIC
)
11711 /* If this is a reference to an external symbol, and we are
11712 using a small GOT, we want
11713 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11717 lw $gp,cprestore($sp)
11718 The cprestore value is set using the .cprestore
11719 pseudo-op. If we are using a big GOT, we want
11720 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11722 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11726 lw $gp,cprestore($sp)
11727 If the symbol is not external, we want
11728 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11730 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11733 lw $gp,cprestore($sp)
11735 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11736 sequences above, minus nops, unless the symbol is local,
11737 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11743 relax_start (offset_expr
.X_add_symbol
);
11744 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11745 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11748 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11749 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11755 relax_start (offset_expr
.X_add_symbol
);
11756 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11757 BFD_RELOC_MIPS_CALL_HI16
);
11758 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11759 PIC_CALL_REG
, mips_gp_register
);
11760 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11761 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11764 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11765 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11767 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11768 PIC_CALL_REG
, PIC_CALL_REG
,
11769 BFD_RELOC_MIPS_GOT_OFST
);
11773 macro_build_jalr (&offset_expr
, 0);
11777 relax_start (offset_expr
.X_add_symbol
);
11780 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11781 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11790 gpdelay
= reg_needs_delay (mips_gp_register
);
11791 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11792 BFD_RELOC_MIPS_CALL_HI16
);
11793 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11794 PIC_CALL_REG
, mips_gp_register
);
11795 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11796 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11801 macro_build (NULL
, "nop", "");
11803 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11804 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11807 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11808 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11810 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11812 if (mips_cprestore_offset
< 0)
11813 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11816 if (!mips_frame_reg_valid
)
11818 as_warn (_("no .frame pseudo-op used in PIC code"));
11819 /* Quiet this warning. */
11820 mips_frame_reg_valid
= 1;
11822 if (!mips_cprestore_valid
)
11824 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11825 /* Quiet this warning. */
11826 mips_cprestore_valid
= 1;
11828 if (mips_opts
.noreorder
)
11829 macro_build (NULL
, "nop", "");
11830 expr1
.X_add_number
= mips_cprestore_offset
;
11831 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11834 HAVE_64BIT_ADDRESSES
);
11838 else if (mips_pic
== VXWORKS_PIC
)
11839 as_bad (_("non-PIC jump used in PIC library"));
11946 gas_assert (!mips_opts
.micromips
);
11949 /* Itbl support may require additional care here. */
11955 /* Itbl support may require additional care here. */
11961 offbits
= (mips_opts
.micromips
? 12
11962 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11964 /* Itbl support may require additional care here. */
11968 gas_assert (!mips_opts
.micromips
);
11971 /* Itbl support may require additional care here. */
11977 offbits
= (mips_opts
.micromips
? 12 : 16);
11982 offbits
= (mips_opts
.micromips
? 12 : 16);
11987 /* Itbl support may require additional care here. */
11993 offbits
= (mips_opts
.micromips
? 12
11994 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11996 /* Itbl support may require additional care here. */
12002 /* Itbl support may require additional care here. */
12008 /* Itbl support may require additional care here. */
12014 offbits
= (mips_opts
.micromips
? 12 : 16);
12019 offbits
= (mips_opts
.micromips
? 12 : 16);
12024 offbits
= (mips_opts
.micromips
? 12
12025 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12031 offbits
= (mips_opts
.micromips
? 12
12032 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12038 offbits
= (mips_opts
.micromips
? 12 : 16);
12041 gas_assert (mips_opts
.micromips
);
12048 gas_assert (mips_opts
.micromips
);
12057 s
= ip
->insn_mo
->name
;
12063 gas_assert (mips_opts
.micromips
);
12069 gas_assert (mips_opts
.micromips
);
12076 /* Try to use one the the load registers to compute the base address.
12077 We don't want to use $0 as tempreg. */
12080 if ((op
[0] == ZERO
&& op
[3] == op
[1])
12081 || (op
[1] == ZERO
&& op
[3] == op
[0])
12082 || (op
[0] == ZERO
&& op
[1] == ZERO
))
12084 else if (op
[0] != op
[3] && op
[0] != ZERO
)
12091 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
12094 tempreg
= op
[0] + lp
;
12111 gas_assert (!mips_opts
.micromips
);
12114 /* Itbl support may require additional care here. */
12120 /* Itbl support may require additional care here. */
12126 offbits
= (mips_opts
.micromips
? 12
12127 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12129 /* Itbl support may require additional care here. */
12133 gas_assert (!mips_opts
.micromips
);
12136 /* Itbl support may require additional care here. */
12142 offbits
= (mips_opts
.micromips
? 12 : 16);
12147 offbits
= (mips_opts
.micromips
? 12 : 16);
12152 offbits
= (mips_opts
.micromips
? 12
12153 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12159 offbits
= (mips_opts
.micromips
? 12
12160 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12166 s
= ip
->insn_mo
->name
;
12173 fmt
= (mips_opts
.micromips
? "k,~(b)"
12174 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12176 offbits
= (mips_opts
.micromips
? 12
12177 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12187 fmt
= (mips_opts
.micromips
? "k,~(b)"
12188 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12190 offbits
= (mips_opts
.micromips
? 12
12191 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12203 /* Itbl support may require additional care here. */
12208 offbits
= (mips_opts
.micromips
? 12
12209 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12211 /* Itbl support may require additional care here. */
12217 /* Itbl support may require additional care here. */
12221 gas_assert (!mips_opts
.micromips
);
12224 /* Itbl support may require additional care here. */
12230 offbits
= (mips_opts
.micromips
? 12 : 16);
12235 offbits
= (mips_opts
.micromips
? 12 : 16);
12238 gas_assert (mips_opts
.micromips
);
12244 gas_assert (mips_opts
.micromips
);
12250 gas_assert (mips_opts
.micromips
);
12256 gas_assert (mips_opts
.micromips
);
12264 breg
= ll_sc_paired
? op
[3] : op
[2];
12265 if (small_offset_p (0, align
, 16))
12267 /* The first case exists for M_LD_AB and M_SD_AB, which are
12268 macros for o32 but which should act like normal instructions
12271 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12272 offset_reloc
[1], offset_reloc
[2], breg
);
12273 else if (small_offset_p (0, align
, offbits
))
12278 macro_build (NULL
, s
, fmt
, op
[0], op
[1], breg
);
12280 macro_build (NULL
, s
, fmt
, op
[0], breg
);
12283 macro_build (NULL
, s
, fmt
, op
[0],
12284 (int) offset_expr
.X_add_number
, breg
);
12290 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12291 tempreg
, breg
, -1, offset_reloc
[0],
12292 offset_reloc
[1], offset_reloc
[2]);
12296 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12298 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12301 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12309 if (offset_expr
.X_op
!= O_constant
12310 && offset_expr
.X_op
!= O_symbol
)
12312 as_bad (_("expression too complex"));
12313 offset_expr
.X_op
= O_constant
;
12316 if (HAVE_32BIT_ADDRESSES
12317 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12321 sprintf_vma (value
, offset_expr
.X_add_number
);
12322 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12325 /* A constant expression in PIC code can be handled just as it
12326 is in non PIC code. */
12327 if (offset_expr
.X_op
== O_constant
)
12329 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12330 offbits
== 0 ? 16 : offbits
);
12331 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12333 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12335 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12336 tempreg
, tempreg
, breg
);
12339 if (offset_expr
.X_add_number
!= 0)
12340 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12341 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12343 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12345 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12347 else if (offbits
== 16)
12348 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12350 macro_build (NULL
, s
, fmt
, op
[0],
12351 (int) offset_expr
.X_add_number
, tempreg
);
12353 else if (offbits
!= 16)
12355 /* The offset field is too narrow to be used for a low-part
12356 relocation, so load the whole address into the auxiliary
12358 load_address (tempreg
, &offset_expr
, &used_at
);
12360 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12361 tempreg
, tempreg
, breg
);
12365 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12367 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12370 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12372 else if (mips_pic
== NO_PIC
)
12374 /* If this is a reference to a GP relative symbol, and there
12375 is no base register, we want
12376 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12377 Otherwise, if there is no base register, we want
12378 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12379 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12380 If we have a constant, we need two instructions anyhow,
12381 so we always use the latter form.
12383 If we have a base register, and this is a reference to a
12384 GP relative symbol, we want
12385 addu $tempreg,$breg,$gp
12386 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12388 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12389 addu $tempreg,$tempreg,$breg
12390 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12391 With a constant we always use the latter case.
12393 With 64bit address space and no base register and $at usable,
12395 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12396 lui $at,<sym> (BFD_RELOC_HI16_S)
12397 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12400 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12401 If we have a base register, we want
12402 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12403 lui $at,<sym> (BFD_RELOC_HI16_S)
12404 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12408 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12410 Without $at we can't generate the optimal path for superscalar
12411 processors here since this would require two temporary registers.
12412 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12413 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12415 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12417 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12418 If we have a base register, we want
12419 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12420 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12422 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12424 daddu $tempreg,$tempreg,$breg
12425 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12427 For GP relative symbols in 64bit address space we can use
12428 the same sequence as in 32bit address space. */
12429 if (HAVE_64BIT_SYMBOLS
)
12431 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12432 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12434 relax_start (offset_expr
.X_add_symbol
);
12437 macro_build (&offset_expr
, s
, fmt
, op
[0],
12438 BFD_RELOC_GPREL16
, mips_gp_register
);
12442 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12443 tempreg
, breg
, mips_gp_register
);
12444 macro_build (&offset_expr
, s
, fmt
, op
[0],
12445 BFD_RELOC_GPREL16
, tempreg
);
12450 if (used_at
== 0 && mips_opts
.at
)
12452 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12453 BFD_RELOC_MIPS_HIGHEST
);
12454 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12456 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12457 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12459 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12460 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12461 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12462 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12468 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12469 BFD_RELOC_MIPS_HIGHEST
);
12470 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12471 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12472 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12473 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12474 tempreg
, BFD_RELOC_HI16_S
);
12475 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12477 macro_build (NULL
, "daddu", "d,v,t",
12478 tempreg
, tempreg
, breg
);
12479 macro_build (&offset_expr
, s
, fmt
, op
[0],
12480 BFD_RELOC_LO16
, tempreg
);
12483 if (mips_relax
.sequence
)
12490 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12491 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12493 relax_start (offset_expr
.X_add_symbol
);
12494 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12498 macro_build_lui (&offset_expr
, tempreg
);
12499 macro_build (&offset_expr
, s
, fmt
, op
[0],
12500 BFD_RELOC_LO16
, tempreg
);
12501 if (mips_relax
.sequence
)
12506 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12507 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12509 relax_start (offset_expr
.X_add_symbol
);
12510 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12511 tempreg
, breg
, mips_gp_register
);
12512 macro_build (&offset_expr
, s
, fmt
, op
[0],
12513 BFD_RELOC_GPREL16
, tempreg
);
12516 macro_build_lui (&offset_expr
, tempreg
);
12517 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12518 tempreg
, tempreg
, breg
);
12519 macro_build (&offset_expr
, s
, fmt
, op
[0],
12520 BFD_RELOC_LO16
, tempreg
);
12521 if (mips_relax
.sequence
)
12525 else if (!mips_big_got
)
12527 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12529 /* If this is a reference to an external symbol, we want
12530 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12532 <op> op[0],0($tempreg)
12534 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12536 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12537 <op> op[0],0($tempreg)
12539 For NewABI, we want
12540 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12541 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12543 If there is a base register, we add it to $tempreg before
12544 the <op>. If there is a constant, we stick it in the
12545 <op> instruction. We don't handle constants larger than
12546 16 bits, because we have no way to load the upper 16 bits
12547 (actually, we could handle them for the subset of cases
12548 in which we are not using $at). */
12549 gas_assert (offset_expr
.X_op
== O_symbol
);
12552 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12553 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12555 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12556 tempreg
, tempreg
, breg
);
12557 macro_build (&offset_expr
, s
, fmt
, op
[0],
12558 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12561 expr1
.X_add_number
= offset_expr
.X_add_number
;
12562 offset_expr
.X_add_number
= 0;
12563 if (expr1
.X_add_number
< -0x8000
12564 || expr1
.X_add_number
>= 0x8000)
12565 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12566 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12567 lw_reloc_type
, mips_gp_register
);
12569 relax_start (offset_expr
.X_add_symbol
);
12571 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12572 tempreg
, BFD_RELOC_LO16
);
12575 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12576 tempreg
, tempreg
, breg
);
12577 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12579 else if (mips_big_got
&& !HAVE_NEWABI
)
12583 /* If this is a reference to an external symbol, we want
12584 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12585 addu $tempreg,$tempreg,$gp
12586 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12587 <op> op[0],0($tempreg)
12589 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12591 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12592 <op> op[0],0($tempreg)
12593 If there is a base register, we add it to $tempreg before
12594 the <op>. If there is a constant, we stick it in the
12595 <op> instruction. We don't handle constants larger than
12596 16 bits, because we have no way to load the upper 16 bits
12597 (actually, we could handle them for the subset of cases
12598 in which we are not using $at). */
12599 gas_assert (offset_expr
.X_op
== O_symbol
);
12600 expr1
.X_add_number
= offset_expr
.X_add_number
;
12601 offset_expr
.X_add_number
= 0;
12602 if (expr1
.X_add_number
< -0x8000
12603 || expr1
.X_add_number
>= 0x8000)
12604 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12605 gpdelay
= reg_needs_delay (mips_gp_register
);
12606 relax_start (offset_expr
.X_add_symbol
);
12607 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12608 BFD_RELOC_MIPS_GOT_HI16
);
12609 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12611 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12612 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12615 macro_build (NULL
, "nop", "");
12616 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12617 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12619 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12620 tempreg
, BFD_RELOC_LO16
);
12624 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12625 tempreg
, tempreg
, breg
);
12626 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12628 else if (mips_big_got
&& HAVE_NEWABI
)
12630 /* If this is a reference to an external symbol, we want
12631 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12632 add $tempreg,$tempreg,$gp
12633 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12634 <op> op[0],<ofst>($tempreg)
12635 Otherwise, for local symbols, we want:
12636 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12637 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12638 gas_assert (offset_expr
.X_op
== O_symbol
);
12639 expr1
.X_add_number
= offset_expr
.X_add_number
;
12640 offset_expr
.X_add_number
= 0;
12641 if (expr1
.X_add_number
< -0x8000
12642 || expr1
.X_add_number
>= 0x8000)
12643 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12644 relax_start (offset_expr
.X_add_symbol
);
12645 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12646 BFD_RELOC_MIPS_GOT_HI16
);
12647 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12649 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12650 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12652 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12653 tempreg
, tempreg
, breg
);
12654 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12657 offset_expr
.X_add_number
= expr1
.X_add_number
;
12658 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12659 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12661 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12662 tempreg
, tempreg
, breg
);
12663 macro_build (&offset_expr
, s
, fmt
, op
[0],
12664 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12673 gas_assert (mips_opts
.micromips
);
12674 gas_assert (mips_opts
.insn32
);
12675 start_noreorder ();
12676 macro_build (NULL
, "jr", "s", RA
);
12677 expr1
.X_add_number
= op
[0] << 2;
12678 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12683 gas_assert (mips_opts
.micromips
);
12684 gas_assert (mips_opts
.insn32
);
12685 macro_build (NULL
, "jr", "s", op
[0]);
12686 if (mips_opts
.noreorder
)
12687 macro_build (NULL
, "nop", "");
12692 load_register (op
[0], &imm_expr
, 0);
12696 load_register (op
[0], &imm_expr
, 1);
12700 if (imm_expr
.X_op
== O_constant
)
12703 load_register (AT
, &imm_expr
, 0);
12704 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12709 gas_assert (imm_expr
.X_op
== O_absent
12710 && offset_expr
.X_op
== O_symbol
12711 && strcmp (segment_name (S_GET_SEGMENT
12712 (offset_expr
.X_add_symbol
)),
12714 && offset_expr
.X_add_number
== 0);
12715 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12716 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12721 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12722 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12723 order 32 bits of the value and the low order 32 bits are either
12724 zero or in OFFSET_EXPR. */
12725 if (imm_expr
.X_op
== O_constant
)
12727 if (GPR_SIZE
== 64)
12728 load_register (op
[0], &imm_expr
, 1);
12733 if (target_big_endian
)
12745 load_register (hreg
, &imm_expr
, 0);
12748 if (offset_expr
.X_op
== O_absent
)
12749 move_register (lreg
, 0);
12752 gas_assert (offset_expr
.X_op
== O_constant
);
12753 load_register (lreg
, &offset_expr
, 0);
12759 gas_assert (imm_expr
.X_op
== O_absent
);
12761 /* We know that sym is in the .rdata section. First we get the
12762 upper 16 bits of the address. */
12763 if (mips_pic
== NO_PIC
)
12765 macro_build_lui (&offset_expr
, AT
);
12770 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12771 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12775 /* Now we load the register(s). */
12776 if (GPR_SIZE
== 64)
12779 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12780 BFD_RELOC_LO16
, AT
);
12785 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12786 BFD_RELOC_LO16
, AT
);
12789 /* FIXME: How in the world do we deal with the possible
12791 offset_expr
.X_add_number
+= 4;
12792 macro_build (&offset_expr
, "lw", "t,o(b)",
12793 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12799 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12800 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12801 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12802 the value and the low order 32 bits are either zero or in
12804 if (imm_expr
.X_op
== O_constant
)
12807 if (((FPR_SIZE
== 64 && GPR_SIZE
== 64)
12808 || !ISA_HAS_MXHC1 (mips_opts
.isa
))
12809 && imm_expr
.X_add_number
!= 0)
12813 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12815 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12816 macro_build (NULL
, "dmtc1", "t,S", tempreg
, op
[0]);
12819 if (!ISA_HAS_MXHC1 (mips_opts
.isa
))
12821 if (FPR_SIZE
!= 32)
12822 as_bad (_("Unable to generate `%s' compliant code "
12824 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12826 macro_build (NULL
, "mtc1", "t,G", tempreg
, op
[0] + 1);
12828 if (offset_expr
.X_op
== O_absent
)
12829 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12832 gas_assert (offset_expr
.X_op
== O_constant
);
12833 load_register (AT
, &offset_expr
, 0);
12834 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12836 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12838 if (imm_expr
.X_add_number
!= 0)
12842 load_register (AT
, &imm_expr
, 0);
12844 macro_build (NULL
, "mthc1", "t,G", tempreg
, op
[0]);
12850 gas_assert (imm_expr
.X_op
== O_absent
12851 && offset_expr
.X_op
== O_symbol
12852 && offset_expr
.X_add_number
== 0);
12853 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12854 if (strcmp (s
, ".lit8") == 0)
12856 op
[2] = mips_gp_register
;
12857 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12858 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12859 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12863 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12865 if (mips_pic
!= NO_PIC
)
12866 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12867 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12870 /* FIXME: This won't work for a 64 bit address. */
12871 macro_build_lui (&offset_expr
, AT
);
12875 offset_reloc
[0] = BFD_RELOC_LO16
;
12876 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12877 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12880 /* Fall through. */
12883 /* The MIPS assembler seems to check for X_add_number not
12884 being double aligned and generating:
12887 addiu at,at,%lo(foo+1)
12890 But, the resulting address is the same after relocation so why
12891 generate the extra instruction? */
12892 /* Itbl support may require additional care here. */
12895 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12904 gas_assert (!mips_opts
.micromips
);
12905 /* Itbl support may require additional care here. */
12908 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12928 if (GPR_SIZE
== 64)
12938 if (GPR_SIZE
== 64)
12946 /* Even on a big endian machine $fn comes before $fn+1. We have
12947 to adjust when loading from memory. We set coproc if we must
12948 load $fn+1 first. */
12949 /* Itbl support may require additional care here. */
12950 if (!target_big_endian
)
12954 if (small_offset_p (0, align
, 16))
12957 if (!small_offset_p (4, align
, 16))
12959 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12960 -1, offset_reloc
[0], offset_reloc
[1],
12962 expr1
.X_add_number
= 0;
12966 offset_reloc
[0] = BFD_RELOC_LO16
;
12967 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12968 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12970 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12972 ep
->X_add_number
+= 4;
12973 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12974 offset_reloc
[1], offset_reloc
[2], breg
);
12975 ep
->X_add_number
-= 4;
12976 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12977 offset_reloc
[1], offset_reloc
[2], breg
);
12981 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12982 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12984 ep
->X_add_number
+= 4;
12985 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12986 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12992 if (offset_expr
.X_op
!= O_symbol
12993 && offset_expr
.X_op
!= O_constant
)
12995 as_bad (_("expression too complex"));
12996 offset_expr
.X_op
= O_constant
;
12999 if (HAVE_32BIT_ADDRESSES
13000 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
13004 sprintf_vma (value
, offset_expr
.X_add_number
);
13005 as_bad (_("number (0x%s) larger than 32 bits"), value
);
13008 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
13010 /* If this is a reference to a GP relative symbol, we want
13011 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
13012 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
13013 If we have a base register, we use this
13015 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
13016 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
13017 If this is not a GP relative symbol, we want
13018 lui $at,<sym> (BFD_RELOC_HI16_S)
13019 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13020 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13021 If there is a base register, we add it to $at after the
13022 lui instruction. If there is a constant, we always use
13024 if (offset_expr
.X_op
== O_symbol
13025 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
13026 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
13028 relax_start (offset_expr
.X_add_symbol
);
13031 tempreg
= mips_gp_register
;
13035 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13036 AT
, breg
, mips_gp_register
);
13041 /* Itbl support may require additional care here. */
13042 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13043 BFD_RELOC_GPREL16
, tempreg
);
13044 offset_expr
.X_add_number
+= 4;
13046 /* Set mips_optimize to 2 to avoid inserting an
13048 hold_mips_optimize
= mips_optimize
;
13050 /* Itbl support may require additional care here. */
13051 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13052 BFD_RELOC_GPREL16
, tempreg
);
13053 mips_optimize
= hold_mips_optimize
;
13057 offset_expr
.X_add_number
-= 4;
13060 if (offset_high_part (offset_expr
.X_add_number
, 16)
13061 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
13063 load_address (AT
, &offset_expr
, &used_at
);
13064 offset_expr
.X_op
= O_constant
;
13065 offset_expr
.X_add_number
= 0;
13068 macro_build_lui (&offset_expr
, AT
);
13070 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13071 /* Itbl support may require additional care here. */
13072 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13073 BFD_RELOC_LO16
, AT
);
13074 /* FIXME: How do we handle overflow here? */
13075 offset_expr
.X_add_number
+= 4;
13076 /* Itbl support may require additional care here. */
13077 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13078 BFD_RELOC_LO16
, AT
);
13079 if (mips_relax
.sequence
)
13082 else if (!mips_big_got
)
13084 /* If this is a reference to an external symbol, we want
13085 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13088 <op> op[0]+1,4($at)
13090 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13092 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13093 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13094 If there is a base register we add it to $at before the
13095 lwc1 instructions. If there is a constant we include it
13096 in the lwc1 instructions. */
13098 expr1
.X_add_number
= offset_expr
.X_add_number
;
13099 if (expr1
.X_add_number
< -0x8000
13100 || expr1
.X_add_number
>= 0x8000 - 4)
13101 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13102 load_got_offset (AT
, &offset_expr
);
13105 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13107 /* Set mips_optimize to 2 to avoid inserting an undesired
13109 hold_mips_optimize
= mips_optimize
;
13112 /* Itbl support may require additional care here. */
13113 relax_start (offset_expr
.X_add_symbol
);
13114 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13115 BFD_RELOC_LO16
, AT
);
13116 expr1
.X_add_number
+= 4;
13117 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13118 BFD_RELOC_LO16
, AT
);
13120 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13121 BFD_RELOC_LO16
, AT
);
13122 offset_expr
.X_add_number
+= 4;
13123 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13124 BFD_RELOC_LO16
, AT
);
13127 mips_optimize
= hold_mips_optimize
;
13129 else if (mips_big_got
)
13133 /* If this is a reference to an external symbol, we want
13134 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
13136 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
13139 <op> op[0]+1,4($at)
13141 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13143 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13144 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13145 If there is a base register we add it to $at before the
13146 lwc1 instructions. If there is a constant we include it
13147 in the lwc1 instructions. */
13149 expr1
.X_add_number
= offset_expr
.X_add_number
;
13150 offset_expr
.X_add_number
= 0;
13151 if (expr1
.X_add_number
< -0x8000
13152 || expr1
.X_add_number
>= 0x8000 - 4)
13153 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13154 gpdelay
= reg_needs_delay (mips_gp_register
);
13155 relax_start (offset_expr
.X_add_symbol
);
13156 macro_build (&offset_expr
, "lui", LUI_FMT
,
13157 AT
, BFD_RELOC_MIPS_GOT_HI16
);
13158 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13159 AT
, AT
, mips_gp_register
);
13160 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
13161 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
13164 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13165 /* Itbl support may require additional care here. */
13166 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13167 BFD_RELOC_LO16
, AT
);
13168 expr1
.X_add_number
+= 4;
13170 /* Set mips_optimize to 2 to avoid inserting an undesired
13172 hold_mips_optimize
= mips_optimize
;
13174 /* Itbl support may require additional care here. */
13175 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13176 BFD_RELOC_LO16
, AT
);
13177 mips_optimize
= hold_mips_optimize
;
13178 expr1
.X_add_number
-= 4;
13181 offset_expr
.X_add_number
= expr1
.X_add_number
;
13183 macro_build (NULL
, "nop", "");
13184 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
13185 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
13188 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13189 /* Itbl support may require additional care here. */
13190 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13191 BFD_RELOC_LO16
, AT
);
13192 offset_expr
.X_add_number
+= 4;
13194 /* Set mips_optimize to 2 to avoid inserting an undesired
13196 hold_mips_optimize
= mips_optimize
;
13198 /* Itbl support may require additional care here. */
13199 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13200 BFD_RELOC_LO16
, AT
);
13201 mips_optimize
= hold_mips_optimize
;
13215 gas_assert (!mips_opts
.micromips
);
13220 /* New code added to support COPZ instructions.
13221 This code builds table entries out of the macros in mip_opcodes.
13222 R4000 uses interlocks to handle coproc delays.
13223 Other chips (like the R3000) require nops to be inserted for delays.
13225 FIXME: Currently, we require that the user handle delays.
13226 In order to fill delay slots for non-interlocked chips,
13227 we must have a way to specify delays based on the coprocessor.
13228 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
13229 What are the side-effects of the cop instruction?
13230 What cache support might we have and what are its effects?
13231 Both coprocessor & memory require delays. how long???
13232 What registers are read/set/modified?
13234 If an itbl is provided to interpret cop instructions,
13235 this knowledge can be encoded in the itbl spec. */
13249 gas_assert (!mips_opts
.micromips
);
13250 /* For now we just do C (same as Cz). The parameter will be
13251 stored in insn_opcode by mips_ip. */
13252 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
13256 move_register (op
[0], op
[1]);
13260 gas_assert (mips_opts
.micromips
);
13261 gas_assert (mips_opts
.insn32
);
13262 move_register (micromips_to_32_reg_h_map1
[op
[0]],
13263 micromips_to_32_reg_m_map
[op
[1]]);
13264 move_register (micromips_to_32_reg_h_map2
[op
[0]],
13265 micromips_to_32_reg_n_map
[op
[2]]);
13270 /* Fall through. */
13272 if (mips_opts
.arch
== CPU_R5900
)
13273 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
13277 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
13278 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13284 /* Fall through. */
13286 /* The MIPS assembler some times generates shifts and adds. I'm
13287 not trying to be that fancy. GCC should do this for us
13290 load_register (AT
, &imm_expr
, dbl
);
13291 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
13292 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13297 /* Fall through. */
13304 /* Fall through. */
13307 start_noreorder ();
13310 load_register (AT
, &imm_expr
, dbl
);
13311 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
13312 op
[1], imm
? AT
: op
[2]);
13313 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13314 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
13315 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13317 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13320 if (mips_opts
.micromips
)
13321 micromips_label_expr (&label_expr
);
13323 label_expr
.X_add_number
= 8;
13324 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13325 macro_build (NULL
, "nop", "");
13326 macro_build (NULL
, "break", BRK_FMT
, 6);
13327 if (mips_opts
.micromips
)
13328 micromips_add_label ();
13331 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13336 /* Fall through. */
13343 /* Fall through. */
13346 start_noreorder ();
13349 load_register (AT
, &imm_expr
, dbl
);
13350 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13351 op
[1], imm
? AT
: op
[2]);
13352 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13353 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13355 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13358 if (mips_opts
.micromips
)
13359 micromips_label_expr (&label_expr
);
13361 label_expr
.X_add_number
= 8;
13362 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13363 macro_build (NULL
, "nop", "");
13364 macro_build (NULL
, "break", BRK_FMT
, 6);
13365 if (mips_opts
.micromips
)
13366 micromips_add_label ();
13372 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13374 if (op
[0] == op
[1])
13381 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13382 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13386 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13387 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13388 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13389 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13393 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13395 if (op
[0] == op
[1])
13402 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13403 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13407 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13408 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13409 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13410 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13419 rot
= imm_expr
.X_add_number
& 0x3f;
13420 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13422 rot
= (64 - rot
) & 0x3f;
13424 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13426 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13431 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13434 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13435 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13438 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13439 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13440 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13448 rot
= imm_expr
.X_add_number
& 0x1f;
13449 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13451 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13452 (32 - rot
) & 0x1f);
13457 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13461 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13462 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13463 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13468 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13470 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13474 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13475 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13476 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13477 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13481 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13483 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13487 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13488 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13489 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13490 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13499 rot
= imm_expr
.X_add_number
& 0x3f;
13500 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13503 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13505 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13510 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13513 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13514 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13517 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13518 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13519 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13527 rot
= imm_expr
.X_add_number
& 0x1f;
13528 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13530 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13535 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13539 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13540 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13541 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13547 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13548 else if (op
[2] == 0)
13549 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13552 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13553 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13558 if (imm_expr
.X_add_number
== 0)
13560 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13565 as_warn (_("instruction %s: result is always false"),
13566 ip
->insn_mo
->name
);
13567 move_register (op
[0], 0);
13570 if (CPU_HAS_SEQ (mips_opts
.arch
)
13571 && -512 <= imm_expr
.X_add_number
13572 && imm_expr
.X_add_number
< 512)
13574 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13575 (int) imm_expr
.X_add_number
);
13578 if (imm_expr
.X_add_number
>= 0
13579 && imm_expr
.X_add_number
< 0x10000)
13580 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13581 else if (imm_expr
.X_add_number
> -0x8000
13582 && imm_expr
.X_add_number
< 0)
13584 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13585 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13586 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13588 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13591 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13592 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13597 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13598 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13601 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13604 case M_SGE
: /* X >= Y <==> not (X < Y) */
13610 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13611 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13614 case M_SGE_I
: /* X >= I <==> not (X < I). */
13616 if (imm_expr
.X_add_number
>= -0x8000
13617 && imm_expr
.X_add_number
< 0x8000)
13618 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13619 op
[0], op
[1], BFD_RELOC_LO16
);
13622 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13623 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13627 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13630 case M_SGT
: /* X > Y <==> Y < X. */
13636 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13639 case M_SGT_I
: /* X > I <==> I < X. */
13646 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13647 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13650 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X). */
13656 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13657 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13660 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13667 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13668 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13669 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13673 if (imm_expr
.X_add_number
>= -0x8000
13674 && imm_expr
.X_add_number
< 0x8000)
13676 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13681 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13682 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13686 if (imm_expr
.X_add_number
>= -0x8000
13687 && imm_expr
.X_add_number
< 0x8000)
13689 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13694 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13695 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13700 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13701 else if (op
[2] == 0)
13702 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13705 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13706 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13711 if (imm_expr
.X_add_number
== 0)
13713 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13718 as_warn (_("instruction %s: result is always true"),
13719 ip
->insn_mo
->name
);
13720 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13721 op
[0], 0, BFD_RELOC_LO16
);
13724 if (CPU_HAS_SEQ (mips_opts
.arch
)
13725 && -512 <= imm_expr
.X_add_number
13726 && imm_expr
.X_add_number
< 512)
13728 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13729 (int) imm_expr
.X_add_number
);
13732 if (imm_expr
.X_add_number
>= 0
13733 && imm_expr
.X_add_number
< 0x10000)
13735 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13738 else if (imm_expr
.X_add_number
> -0x8000
13739 && imm_expr
.X_add_number
< 0)
13741 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13742 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13743 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13745 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13748 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13749 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13754 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13755 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13758 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13764 if (ISA_IS_R6 (mips_opts
.isa
))
13776 if (!mips_opts
.micromips
&& !ISA_IS_R6 (mips_opts
.isa
))
13778 if (imm_expr
.X_add_number
> -0x200
13779 && imm_expr
.X_add_number
<= 0x200
13780 && !ISA_IS_R6 (mips_opts
.isa
))
13782 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13783 (int) -imm_expr
.X_add_number
);
13792 if (imm_expr
.X_add_number
> -0x8000
13793 && imm_expr
.X_add_number
<= 0x8000)
13795 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13796 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13801 load_register (AT
, &imm_expr
, dbl
);
13802 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13824 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13825 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13830 gas_assert (!mips_opts
.micromips
);
13831 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13835 * Is the double cfc1 instruction a bug in the mips assembler;
13836 * or is there a reason for it?
13838 start_noreorder ();
13839 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13840 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13841 macro_build (NULL
, "nop", "");
13842 expr1
.X_add_number
= 3;
13843 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13844 expr1
.X_add_number
= 2;
13845 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13846 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13847 macro_build (NULL
, "nop", "");
13848 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13850 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13851 macro_build (NULL
, "nop", "");
13868 offbits
= (mips_opts
.micromips
? 12 : 16);
13874 offbits
= (mips_opts
.micromips
? 12 : 16);
13886 offbits
= (mips_opts
.micromips
? 12 : 16);
13893 offbits
= (mips_opts
.micromips
? 12 : 16);
13899 large_offset
= !small_offset_p (off
, align
, offbits
);
13901 expr1
.X_add_number
= 0;
13906 if (small_offset_p (0, align
, 16))
13907 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13908 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13911 load_address (tempreg
, ep
, &used_at
);
13913 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13914 tempreg
, tempreg
, breg
);
13916 offset_reloc
[0] = BFD_RELOC_LO16
;
13917 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13918 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13923 else if (!ust
&& op
[0] == breg
)
13934 if (!target_big_endian
)
13935 ep
->X_add_number
+= off
;
13937 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13939 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13940 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13942 if (!target_big_endian
)
13943 ep
->X_add_number
-= off
;
13945 ep
->X_add_number
+= off
;
13947 macro_build (NULL
, s2
, "t,~(b)",
13948 tempreg
, (int) ep
->X_add_number
, breg
);
13950 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13951 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13953 /* If necessary, move the result in tempreg to the final destination. */
13954 if (!ust
&& op
[0] != tempreg
)
13956 /* Protect second load's delay slot. */
13958 move_register (op
[0], tempreg
);
13964 if (target_big_endian
== ust
)
13965 ep
->X_add_number
+= off
;
13966 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13967 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13968 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13970 /* For halfword transfers we need a temporary register to shuffle
13971 bytes. Unfortunately for M_USH_A we have none available before
13972 the next store as AT holds the base address. We deal with this
13973 case by clobbering TREG and then restoring it as with ULH. */
13974 tempreg
= ust
== large_offset
? op
[0] : AT
;
13976 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13978 if (target_big_endian
== ust
)
13979 ep
->X_add_number
-= off
;
13981 ep
->X_add_number
+= off
;
13982 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13983 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13985 /* For M_USH_A re-retrieve the LSB. */
13986 if (ust
&& large_offset
)
13988 if (target_big_endian
)
13989 ep
->X_add_number
+= off
;
13991 ep
->X_add_number
-= off
;
13992 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13993 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13995 /* For ULH and M_USH_A OR the LSB in. */
13996 if (!ust
|| large_offset
)
13998 tempreg
= !large_offset
? AT
: op
[0];
13999 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
14000 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
14005 /* FIXME: Check if this is one of the itbl macros, since they
14006 are added dynamically. */
14007 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
14010 if (!mips_opts
.at
&& used_at
)
14011 as_bad (_("macro used $at after \".set noat\""));
14014 /* Implement macros in mips16 mode. */
14017 mips16_macro (struct mips_cl_insn
*ip
)
14019 const struct mips_operand_array
*operands
;
14024 const char *s
, *s2
, *s3
;
14025 unsigned int op
[MAX_OPERANDS
];
14028 mask
= ip
->insn_mo
->mask
;
14030 operands
= insn_operands (ip
);
14031 for (i
= 0; i
< MAX_OPERANDS
; i
++)
14032 if (operands
->operand
[i
])
14033 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
14037 expr1
.X_op
= O_constant
;
14038 expr1
.X_op_symbol
= NULL
;
14039 expr1
.X_add_symbol
= NULL
;
14040 expr1
.X_add_number
= 1;
14051 /* Fall through. */
14057 /* Fall through. */
14061 start_noreorder ();
14062 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
14063 expr1
.X_add_number
= 2;
14064 macro_build (&expr1
, "bnez", "x,p", op
[2]);
14065 macro_build (NULL
, "break", "6", 7);
14067 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
14068 since that causes an overflow. We should do that as well,
14069 but I don't see how to do the comparisons without a temporary
14072 macro_build (NULL
, s
, "x", op
[0]);
14091 start_noreorder ();
14092 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
14093 expr1
.X_add_number
= 2;
14094 macro_build (&expr1
, "bnez", "x,p", op
[2]);
14095 macro_build (NULL
, "break", "6", 7);
14097 macro_build (NULL
, s2
, "x", op
[0]);
14102 /* Fall through. */
14104 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
14105 macro_build (NULL
, "mflo", "x", op
[0]);
14113 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14114 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
14118 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14119 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
14123 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14124 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
14146 goto do_reverse_branch
;
14150 goto do_reverse_branch
;
14162 goto do_reverse_branch
;
14173 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
14174 macro_build (&offset_expr
, s2
, "p");
14201 goto do_addone_branch_i
;
14206 goto do_addone_branch_i
;
14221 goto do_addone_branch_i
;
14227 do_addone_branch_i
:
14228 ++imm_expr
.X_add_number
;
14231 macro_build (&imm_expr
, s
, s3
, op
[0]);
14232 macro_build (&offset_expr
, s2
, "p");
14236 expr1
.X_add_number
= 0;
14237 macro_build (&expr1
, "slti", "x,8", op
[1]);
14238 if (op
[0] != op
[1])
14239 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
14240 expr1
.X_add_number
= 2;
14241 macro_build (&expr1
, "bteqz", "p");
14242 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
14247 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
14248 opcode bits in *OPCODE_EXTRA. */
14250 static struct mips_opcode
*
14251 mips_lookup_insn (htab_t hash
, const char *start
,
14252 ssize_t length
, unsigned int *opcode_extra
)
14254 char *name
, *dot
, *p
;
14255 unsigned int mask
, suffix
;
14257 struct mips_opcode
*insn
;
14259 /* Make a copy of the instruction so that we can fiddle with it. */
14260 name
= xstrndup (start
, length
);
14262 /* Look up the instruction as-is. */
14263 insn
= (struct mips_opcode
*) str_hash_find (hash
, name
);
14267 dot
= strchr (name
, '.');
14270 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14271 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
14272 if (*p
== 0 && mask
!= 0)
14275 insn
= (struct mips_opcode
*) str_hash_find (hash
, name
);
14277 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
14279 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
14285 if (mips_opts
.micromips
)
14287 /* See if there's an instruction size override suffix,
14288 either `16' or `32', at the end of the mnemonic proper,
14289 that defines the operation, i.e. before the first `.'
14290 character if any. Strip it and retry. */
14291 opend
= dot
!= NULL
? dot
- name
: length
;
14292 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
14294 else if (opend
>= 2 && name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
14300 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
14301 insn
= (struct mips_opcode
*) str_hash_find (hash
, name
);
14304 forced_insn_length
= suffix
;
14316 /* Assemble an instruction into its binary format. If the instruction
14317 is a macro, set imm_expr and offset_expr to the values associated
14318 with "I" and "A" operands respectively. Otherwise store the value
14319 of the relocatable field (if any) in offset_expr. In both cases
14320 set offset_reloc to the relocation operators applied to offset_expr. */
14323 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14325 const struct mips_opcode
*first
, *past
;
14329 struct mips_operand_token
*tokens
;
14330 unsigned int opcode_extra
;
14332 if (mips_opts
.micromips
)
14334 hash
= micromips_op_hash
;
14335 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14340 past
= &mips_opcodes
[NUMOPCODES
];
14342 forced_insn_length
= 0;
14345 /* We first try to match an instruction up to a space or to the end. */
14346 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14349 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14352 set_insn_error (0, _("unrecognized opcode"));
14356 if (strcmp (first
->name
, "li.s") == 0)
14358 else if (strcmp (first
->name
, "li.d") == 0)
14362 tokens
= mips_parse_arguments (str
+ end
, format
);
14366 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, false)
14367 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, true))
14368 set_insn_error (0, _("invalid operands"));
14370 obstack_free (&mips_operand_tokens
, tokens
);
14373 /* As for mips_ip, but used when assembling MIPS16 code.
14374 Also set forced_insn_length to the resulting instruction size in
14375 bytes if the user explicitly requested a small or extended instruction. */
14378 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14381 struct mips_opcode
*first
;
14382 struct mips_operand_token
*tokens
;
14385 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14407 else if (*s
== 'e')
14414 else if (*s
++ == ' ')
14416 set_insn_error (0, _("unrecognized opcode"));
14419 forced_insn_length
= l
;
14422 first
= (struct mips_opcode
*) str_hash_find (mips16_op_hash
, str
);
14427 set_insn_error (0, _("unrecognized opcode"));
14431 tokens
= mips_parse_arguments (s
, 0);
14435 if (!match_mips16_insns (insn
, first
, tokens
))
14436 set_insn_error (0, _("invalid operands"));
14438 obstack_free (&mips_operand_tokens
, tokens
);
14441 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14442 NBITS is the number of significant bits in VAL. */
14444 static unsigned long
14445 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14450 val
&= (1U << nbits
) - 1;
14451 if (nbits
== 16 || nbits
== 9)
14453 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14456 else if (nbits
== 15)
14458 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14461 else if (nbits
== 6)
14463 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14466 return (extval
<< 16) | val
;
14469 /* Like decode_mips16_operand, but require the operand to be defined and
14470 require it to be an integer. */
14472 static const struct mips_int_operand
*
14473 mips16_immed_operand (int type
, bool extended_p
)
14475 const struct mips_operand
*operand
;
14477 operand
= decode_mips16_operand (type
, extended_p
);
14478 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14480 return (const struct mips_int_operand
*) operand
;
14483 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14486 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14487 bfd_reloc_code_real_type reloc
, offsetT sval
)
14489 int min_val
, max_val
;
14491 min_val
= mips_int_operand_min (operand
);
14492 max_val
= mips_int_operand_max (operand
);
14493 if (reloc
!= BFD_RELOC_UNUSED
)
14496 sval
= SEXT_16BIT (sval
);
14501 return (sval
>= min_val
14503 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14506 /* Install immediate value VAL into MIPS16 instruction *INSN,
14507 extending it if necessary. The instruction in *INSN may
14508 already be extended.
14510 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14511 if none. In the former case, VAL is a 16-bit number with no
14512 defined signedness.
14514 TYPE is the type of the immediate field. USER_INSN_LENGTH
14515 is the length that the user requested, or 0 if none. */
14518 mips16_immed (const char *file
, unsigned int line
, int type
,
14519 bfd_reloc_code_real_type reloc
, offsetT val
,
14520 unsigned int user_insn_length
, unsigned long *insn
)
14522 const struct mips_int_operand
*operand
;
14523 unsigned int uval
, length
;
14525 operand
= mips16_immed_operand (type
, false);
14526 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14528 /* We need an extended instruction. */
14529 if (user_insn_length
== 2)
14530 as_bad_where (file
, line
, _("invalid unextended operand value"));
14532 *insn
|= MIPS16_EXTEND
;
14534 else if (user_insn_length
== 4)
14536 /* The operand doesn't force an unextended instruction to be extended.
14537 Warn if the user wanted an extended instruction anyway. */
14538 *insn
|= MIPS16_EXTEND
;
14539 as_warn_where (file
, line
,
14540 _("extended operand requested but not required"));
14543 length
= mips16_opcode_length (*insn
);
14546 operand
= mips16_immed_operand (type
, true);
14547 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14548 as_bad_where (file
, line
,
14549 _("operand value out of range for instruction"));
14551 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14552 if (length
== 2 || operand
->root
.lsb
!= 0)
14553 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14555 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14558 struct percent_op_match
14561 bfd_reloc_code_real_type reloc
;
14564 static const struct percent_op_match mips_percent_op
[] =
14566 {"%lo", BFD_RELOC_LO16
},
14567 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14568 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14569 {"%call16", BFD_RELOC_MIPS_CALL16
},
14570 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14571 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14572 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14573 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14574 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14575 {"%got", BFD_RELOC_MIPS_GOT16
},
14576 {"%gp_rel", BFD_RELOC_GPREL16
},
14577 {"%gprel", BFD_RELOC_GPREL16
},
14578 {"%half", BFD_RELOC_16
},
14579 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14580 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14581 {"%neg", BFD_RELOC_MIPS_SUB
},
14582 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14583 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14584 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14585 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14586 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14587 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14588 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14589 {"%hi", BFD_RELOC_HI16_S
},
14590 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14591 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14594 static const struct percent_op_match mips16_percent_op
[] =
14596 {"%lo", BFD_RELOC_MIPS16_LO16
},
14597 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14598 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14599 {"%got", BFD_RELOC_MIPS16_GOT16
},
14600 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14601 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14602 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14603 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14604 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14605 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14606 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14607 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14608 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14612 /* Return true if *STR points to a relocation operator. When returning true,
14613 move *STR over the operator and store its relocation code in *RELOC.
14614 Leave both *STR and *RELOC alone when returning false. */
14617 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14619 const struct percent_op_match
*percent_op
;
14622 if (mips_opts
.mips16
)
14624 percent_op
= mips16_percent_op
;
14625 limit
= ARRAY_SIZE (mips16_percent_op
);
14629 percent_op
= mips_percent_op
;
14630 limit
= ARRAY_SIZE (mips_percent_op
);
14633 for (i
= 0; i
< limit
; i
++)
14634 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14636 int len
= strlen (percent_op
[i
].str
);
14638 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14641 *str
+= strlen (percent_op
[i
].str
);
14642 *reloc
= percent_op
[i
].reloc
;
14644 /* Check whether the output BFD supports this relocation.
14645 If not, issue an error and fall back on something safe. */
14646 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14648 as_bad (_("relocation %s isn't supported by the current ABI"),
14649 percent_op
[i
].str
);
14650 *reloc
= BFD_RELOC_UNUSED
;
14658 /* Parse string STR as a 16-bit relocatable operand. Store the
14659 expression in *EP and the relocations in the array starting
14660 at RELOC. Return the number of relocation operators used.
14662 On exit, EXPR_END points to the first character after the expression. */
14665 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14668 bfd_reloc_code_real_type reversed_reloc
[3];
14669 size_t reloc_index
, i
;
14670 int crux_depth
, str_depth
;
14673 /* Search for the start of the main expression, recoding relocations
14674 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14675 of the main expression and with CRUX_DEPTH containing the number
14676 of open brackets at that point. */
14683 crux_depth
= str_depth
;
14685 /* Skip over whitespace and brackets, keeping count of the number
14687 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14692 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14693 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14695 my_getExpression (ep
, crux
);
14698 /* Match every open bracket. */
14699 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14703 if (crux_depth
> 0)
14704 as_bad (_("unclosed '('"));
14708 for (i
= 0; i
< reloc_index
; i
++)
14709 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14711 return reloc_index
;
14715 my_getExpression (expressionS
*ep
, char *str
)
14719 save_in
= input_line_pointer
;
14720 input_line_pointer
= str
;
14722 expr_end
= input_line_pointer
;
14723 input_line_pointer
= save_in
;
14727 md_atof (int type
, char *litP
, int *sizeP
)
14729 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14733 md_number_to_chars (char *buf
, valueT val
, int n
)
14735 if (target_big_endian
)
14736 number_to_chars_bigendian (buf
, val
, n
);
14738 number_to_chars_littleendian (buf
, val
, n
);
14741 static int support_64bit_objects(void)
14743 const char **list
, **l
;
14746 list
= bfd_target_list ();
14747 for (l
= list
; *l
!= NULL
; l
++)
14748 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14749 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14751 yes
= (*l
!= NULL
);
14756 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14757 NEW_VALUE. Warn if another value was already specified. Note:
14758 we have to defer parsing the -march and -mtune arguments in order
14759 to handle 'from-abi' correctly, since the ABI might be specified
14760 in a later argument. */
14763 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14765 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14766 as_warn (_("a different %s was already specified, is now %s"),
14767 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14770 *string_ptr
= new_value
;
14774 md_parse_option (int c
, const char *arg
)
14778 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14779 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14781 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14782 c
== mips_ases
[i
].option_on
);
14788 case OPTION_CONSTRUCT_FLOATS
:
14789 mips_disable_float_construction
= 0;
14792 case OPTION_NO_CONSTRUCT_FLOATS
:
14793 mips_disable_float_construction
= 1;
14805 target_big_endian
= 1;
14809 target_big_endian
= 0;
14815 else if (arg
[0] == '0')
14817 else if (arg
[0] == '1')
14827 mips_debug
= atoi (arg
);
14831 file_mips_opts
.isa
= ISA_MIPS1
;
14835 file_mips_opts
.isa
= ISA_MIPS2
;
14839 file_mips_opts
.isa
= ISA_MIPS3
;
14843 file_mips_opts
.isa
= ISA_MIPS4
;
14847 file_mips_opts
.isa
= ISA_MIPS5
;
14850 case OPTION_MIPS32
:
14851 file_mips_opts
.isa
= ISA_MIPS32
;
14854 case OPTION_MIPS32R2
:
14855 file_mips_opts
.isa
= ISA_MIPS32R2
;
14858 case OPTION_MIPS32R3
:
14859 file_mips_opts
.isa
= ISA_MIPS32R3
;
14862 case OPTION_MIPS32R5
:
14863 file_mips_opts
.isa
= ISA_MIPS32R5
;
14866 case OPTION_MIPS32R6
:
14867 file_mips_opts
.isa
= ISA_MIPS32R6
;
14870 case OPTION_MIPS64R2
:
14871 file_mips_opts
.isa
= ISA_MIPS64R2
;
14874 case OPTION_MIPS64R3
:
14875 file_mips_opts
.isa
= ISA_MIPS64R3
;
14878 case OPTION_MIPS64R5
:
14879 file_mips_opts
.isa
= ISA_MIPS64R5
;
14882 case OPTION_MIPS64R6
:
14883 file_mips_opts
.isa
= ISA_MIPS64R6
;
14886 case OPTION_MIPS64
:
14887 file_mips_opts
.isa
= ISA_MIPS64
;
14891 mips_set_option_string (&mips_tune_string
, arg
);
14895 mips_set_option_string (&mips_arch_string
, arg
);
14899 mips_set_option_string (&mips_arch_string
, "4650");
14900 mips_set_option_string (&mips_tune_string
, "4650");
14903 case OPTION_NO_M4650
:
14907 mips_set_option_string (&mips_arch_string
, "4010");
14908 mips_set_option_string (&mips_tune_string
, "4010");
14911 case OPTION_NO_M4010
:
14915 mips_set_option_string (&mips_arch_string
, "4100");
14916 mips_set_option_string (&mips_tune_string
, "4100");
14919 case OPTION_NO_M4100
:
14923 mips_set_option_string (&mips_arch_string
, "3900");
14924 mips_set_option_string (&mips_tune_string
, "3900");
14927 case OPTION_NO_M3900
:
14930 case OPTION_MICROMIPS
:
14931 if (file_mips_opts
.mips16
== 1)
14933 as_bad (_("-mmicromips cannot be used with -mips16"));
14936 file_mips_opts
.micromips
= 1;
14937 mips_no_prev_insn ();
14940 case OPTION_NO_MICROMIPS
:
14941 file_mips_opts
.micromips
= 0;
14942 mips_no_prev_insn ();
14945 case OPTION_MIPS16
:
14946 if (file_mips_opts
.micromips
== 1)
14948 as_bad (_("-mips16 cannot be used with -micromips"));
14951 file_mips_opts
.mips16
= 1;
14952 mips_no_prev_insn ();
14955 case OPTION_NO_MIPS16
:
14956 file_mips_opts
.mips16
= 0;
14957 mips_no_prev_insn ();
14960 case OPTION_FIX_24K
:
14964 case OPTION_NO_FIX_24K
:
14968 case OPTION_FIX_RM7000
:
14969 mips_fix_rm7000
= 1;
14972 case OPTION_NO_FIX_RM7000
:
14973 mips_fix_rm7000
= 0;
14976 case OPTION_FIX_LOONGSON3_LLSC
:
14977 mips_fix_loongson3_llsc
= true;
14980 case OPTION_NO_FIX_LOONGSON3_LLSC
:
14981 mips_fix_loongson3_llsc
= false;
14984 case OPTION_FIX_LOONGSON2F_JUMP
:
14985 mips_fix_loongson2f_jump
= true;
14988 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14989 mips_fix_loongson2f_jump
= false;
14992 case OPTION_FIX_LOONGSON2F_NOP
:
14993 mips_fix_loongson2f_nop
= true;
14996 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14997 mips_fix_loongson2f_nop
= false;
15000 case OPTION_FIX_VR4120
:
15001 mips_fix_vr4120
= 1;
15004 case OPTION_NO_FIX_VR4120
:
15005 mips_fix_vr4120
= 0;
15008 case OPTION_FIX_VR4130
:
15009 mips_fix_vr4130
= 1;
15012 case OPTION_NO_FIX_VR4130
:
15013 mips_fix_vr4130
= 0;
15016 case OPTION_FIX_CN63XXP1
:
15017 mips_fix_cn63xxp1
= true;
15020 case OPTION_NO_FIX_CN63XXP1
:
15021 mips_fix_cn63xxp1
= false;
15024 case OPTION_FIX_R5900
:
15025 mips_fix_r5900
= true;
15026 mips_fix_r5900_explicit
= true;
15029 case OPTION_NO_FIX_R5900
:
15030 mips_fix_r5900
= false;
15031 mips_fix_r5900_explicit
= true;
15034 case OPTION_RELAX_BRANCH
:
15035 mips_relax_branch
= 1;
15038 case OPTION_NO_RELAX_BRANCH
:
15039 mips_relax_branch
= 0;
15042 case OPTION_IGNORE_BRANCH_ISA
:
15043 mips_ignore_branch_isa
= true;
15046 case OPTION_NO_IGNORE_BRANCH_ISA
:
15047 mips_ignore_branch_isa
= false;
15050 case OPTION_INSN32
:
15051 file_mips_opts
.insn32
= true;
15054 case OPTION_NO_INSN32
:
15055 file_mips_opts
.insn32
= false;
15058 case OPTION_MSHARED
:
15059 mips_in_shared
= true;
15062 case OPTION_MNO_SHARED
:
15063 mips_in_shared
= false;
15066 case OPTION_MSYM32
:
15067 file_mips_opts
.sym32
= true;
15070 case OPTION_MNO_SYM32
:
15071 file_mips_opts
.sym32
= false;
15074 /* When generating ELF code, we permit -KPIC and -call_shared to
15075 select SVR4_PIC, and -non_shared to select no PIC. This is
15076 intended to be compatible with Irix 5. */
15077 case OPTION_CALL_SHARED
:
15078 mips_pic
= SVR4_PIC
;
15079 mips_abicalls
= true;
15082 case OPTION_CALL_NONPIC
:
15084 mips_abicalls
= true;
15087 case OPTION_NON_SHARED
:
15089 mips_abicalls
= false;
15092 /* The -xgot option tells the assembler to use 32 bit offsets
15093 when accessing the got in SVR4_PIC mode. It is for Irix
15100 g_switch_value
= atoi (arg
);
15104 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15107 mips_abi
= O32_ABI
;
15111 mips_abi
= N32_ABI
;
15115 mips_abi
= N64_ABI
;
15116 if (!support_64bit_objects())
15117 as_fatal (_("no compiled in support for 64 bit object file format"));
15121 file_mips_opts
.gp
= 32;
15125 file_mips_opts
.gp
= 64;
15129 file_mips_opts
.fp
= 32;
15133 file_mips_opts
.fp
= 0;
15137 file_mips_opts
.fp
= 64;
15140 case OPTION_ODD_SPREG
:
15141 file_mips_opts
.oddspreg
= 1;
15144 case OPTION_NO_ODD_SPREG
:
15145 file_mips_opts
.oddspreg
= 0;
15148 case OPTION_SINGLE_FLOAT
:
15149 file_mips_opts
.single_float
= 1;
15152 case OPTION_DOUBLE_FLOAT
:
15153 file_mips_opts
.single_float
= 0;
15156 case OPTION_SOFT_FLOAT
:
15157 file_mips_opts
.soft_float
= 1;
15160 case OPTION_HARD_FLOAT
:
15161 file_mips_opts
.soft_float
= 0;
15165 if (strcmp (arg
, "32") == 0)
15166 mips_abi
= O32_ABI
;
15167 else if (strcmp (arg
, "o64") == 0)
15168 mips_abi
= O64_ABI
;
15169 else if (strcmp (arg
, "n32") == 0)
15170 mips_abi
= N32_ABI
;
15171 else if (strcmp (arg
, "64") == 0)
15173 mips_abi
= N64_ABI
;
15174 if (! support_64bit_objects())
15175 as_fatal (_("no compiled in support for 64 bit object file "
15178 else if (strcmp (arg
, "eabi") == 0)
15179 mips_abi
= EABI_ABI
;
15182 as_fatal (_("invalid abi -mabi=%s"), arg
);
15187 case OPTION_M7000_HILO_FIX
:
15188 mips_7000_hilo_fix
= true;
15191 case OPTION_MNO_7000_HILO_FIX
:
15192 mips_7000_hilo_fix
= false;
15195 case OPTION_MDEBUG
:
15196 mips_flag_mdebug
= true;
15199 case OPTION_NO_MDEBUG
:
15200 mips_flag_mdebug
= false;
15204 mips_flag_pdr
= true;
15207 case OPTION_NO_PDR
:
15208 mips_flag_pdr
= false;
15211 case OPTION_MVXWORKS_PIC
:
15212 mips_pic
= VXWORKS_PIC
;
15216 if (strcmp (arg
, "2008") == 0)
15218 else if (strcmp (arg
, "legacy") == 0)
15222 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
15231 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15236 /* Set up globals to tune for the ISA or processor described by INFO. */
15239 mips_set_tune (const struct mips_cpu_info
*info
)
15242 mips_tune
= info
->cpu
;
15247 mips_after_parse_args (void)
15249 const struct mips_cpu_info
*arch_info
= 0;
15250 const struct mips_cpu_info
*tune_info
= 0;
15252 /* GP relative stuff not working for PE. */
15253 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15255 if (g_switch_seen
&& g_switch_value
!= 0)
15256 as_bad (_("-G not supported in this configuration"));
15257 g_switch_value
= 0;
15260 if (mips_abi
== NO_ABI
)
15261 mips_abi
= MIPS_DEFAULT_ABI
;
15263 /* The following code determines the architecture.
15264 Similar code was added to GCC 3.3 (see override_options() in
15265 config/mips/mips.c). The GAS and GCC code should be kept in sync
15266 as much as possible. */
15268 if (mips_arch_string
!= 0)
15269 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15271 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
15273 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
15274 ISA level specified by -mipsN, while arch_info->isa contains
15275 the -march selection (if any). */
15276 if (arch_info
!= 0)
15278 /* -march takes precedence over -mipsN, since it is more descriptive.
15279 There's no harm in specifying both as long as the ISA levels
15281 if (file_mips_opts
.isa
!= arch_info
->isa
)
15282 as_bad (_("-%s conflicts with the other architecture options,"
15283 " which imply -%s"),
15284 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
15285 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15288 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
15291 if (arch_info
== 0)
15293 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15294 gas_assert (arch_info
);
15297 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15298 as_bad (_("-march=%s is not compatible with the selected ABI"),
15301 file_mips_opts
.arch
= arch_info
->cpu
;
15302 file_mips_opts
.isa
= arch_info
->isa
;
15303 file_mips_opts
.init_ase
= arch_info
->ase
;
15305 /* The EVA Extension has instructions which are only valid when the R6 ISA
15306 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
15308 if (((file_mips_opts
.ase
& ASE_EVA
) != 0) && ISA_IS_R6 (file_mips_opts
.isa
))
15309 file_mips_opts
.ase
|= ASE_EVA_R6
;
15311 /* Set up initial mips_opts state. */
15312 mips_opts
= file_mips_opts
;
15314 /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */
15315 if (!mips_fix_r5900_explicit
)
15316 mips_fix_r5900
= file_mips_opts
.arch
== CPU_R5900
;
15318 /* The register size inference code is now placed in
15319 file_mips_check_options. */
15321 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15323 if (mips_tune_string
!= 0)
15324 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15326 if (tune_info
== 0)
15327 mips_set_tune (arch_info
);
15329 mips_set_tune (tune_info
);
15331 if (mips_flag_mdebug
< 0)
15332 mips_flag_mdebug
= 0;
15336 mips_init_after_args (void)
15338 /* Initialize opcodes. */
15339 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15340 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15344 md_pcrel_from (fixS
*fixP
)
15346 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15348 switch (fixP
->fx_r_type
)
15350 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15351 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15352 /* Return the address of the delay slot. */
15355 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15356 case BFD_RELOC_MICROMIPS_JMP
:
15357 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15358 case BFD_RELOC_16_PCREL_S2
:
15359 case BFD_RELOC_MIPS_21_PCREL_S2
:
15360 case BFD_RELOC_MIPS_26_PCREL_S2
:
15361 case BFD_RELOC_MIPS_JMP
:
15362 /* Return the address of the delay slot. */
15365 case BFD_RELOC_MIPS_18_PCREL_S3
:
15366 /* Return the aligned address of the doubleword containing
15367 the instruction. */
15375 /* This is called before the symbol table is processed. In order to
15376 work with gcc when using mips-tfile, we must keep all local labels.
15377 However, in other cases, we want to discard them. If we were
15378 called with -g, but we didn't see any debugging information, it may
15379 mean that gcc is smuggling debugging information through to
15380 mips-tfile, in which case we must generate all local labels. */
15383 mips_frob_file_before_adjust (void)
15385 #ifndef NO_ECOFF_DEBUGGING
15386 if (ECOFF_DEBUGGING
15388 && ! ecoff_debugging_seen
)
15389 flag_keep_locals
= 1;
15393 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15394 the corresponding LO16 reloc. This is called before md_apply_fix and
15395 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15396 relocation operators.
15398 For our purposes, a %lo() expression matches a %got() or %hi()
15401 (a) it refers to the same symbol; and
15402 (b) the offset applied in the %lo() expression is no lower than
15403 the offset applied in the %got() or %hi().
15405 (b) allows us to cope with code like:
15408 lh $4,%lo(foo+2)($4)
15410 ...which is legal on RELA targets, and has a well-defined behaviour
15411 if the user knows that adding 2 to "foo" will not induce a carry to
15414 When several %lo()s match a particular %got() or %hi(), we use the
15415 following rules to distinguish them:
15417 (1) %lo()s with smaller offsets are a better match than %lo()s with
15420 (2) %lo()s with no matching %got() or %hi() are better than those
15421 that already have a matching %got() or %hi().
15423 (3) later %lo()s are better than earlier %lo()s.
15425 These rules are applied in order.
15427 (1) means, among other things, that %lo()s with identical offsets are
15428 chosen if they exist.
15430 (2) means that we won't associate several high-part relocations with
15431 the same low-part relocation unless there's no alternative. Having
15432 several high parts for the same low part is a GNU extension; this rule
15433 allows careful users to avoid it.
15435 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15436 with the last high-part relocation being at the front of the list.
15437 It therefore makes sense to choose the last matching low-part
15438 relocation, all other things being equal. It's also easier
15439 to code that way. */
15442 mips_frob_file (void)
15444 struct mips_hi_fixup
*l
;
15445 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15447 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15449 segment_info_type
*seginfo
;
15451 fixS
**hi_pos
, **lo_pos
, **pos
;
15453 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15455 /* If a GOT16 relocation turns out to be against a global symbol,
15456 there isn't supposed to be a matching LO. Ignore %gots against
15457 constants; we'll report an error for those later. */
15458 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15459 && !(l
->fixp
->fx_addsy
15460 && pic_need_relax (l
->fixp
->fx_addsy
)))
15463 /* Check quickly whether the next fixup happens to be a matching %lo. */
15464 if (fixup_has_matching_lo_p (l
->fixp
))
15467 seginfo
= seg_info (l
->seg
);
15469 /* Set HI_POS to the position of this relocation in the chain.
15470 Set LO_POS to the position of the chosen low-part relocation.
15471 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15472 relocation that matches an immediately-preceding high-part
15476 matched_lo_p
= false;
15477 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15479 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15481 if (*pos
== l
->fixp
)
15484 if ((*pos
)->fx_r_type
== looking_for_rtype
15485 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15486 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15488 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15490 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15493 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15494 && fixup_has_matching_lo_p (*pos
));
15497 /* If we found a match, remove the high-part relocation from its
15498 current position and insert it before the low-part relocation.
15499 Make the offsets match so that fixup_has_matching_lo_p()
15502 We don't warn about unmatched high-part relocations since some
15503 versions of gcc have been known to emit dead "lui ...%hi(...)"
15505 if (lo_pos
!= NULL
)
15507 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15508 if (l
->fixp
->fx_next
!= *lo_pos
)
15510 *hi_pos
= l
->fixp
->fx_next
;
15511 l
->fixp
->fx_next
= *lo_pos
;
15519 mips_force_relocation (fixS
*fixp
)
15521 if (generic_force_reloc (fixp
))
15524 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15525 so that the linker relaxation can update targets. */
15526 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15527 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15528 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15531 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15532 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15533 microMIPS symbols so that we can do cross-mode branch diagnostics
15534 and BAL to JALX conversion by the linker. */
15535 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15536 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15537 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15539 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15542 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15543 if (ISA_IS_R6 (file_mips_opts
.isa
)
15544 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15545 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15546 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15547 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15548 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15549 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15550 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15556 /* Implement TC_FORCE_RELOCATION_ABS. */
15559 mips_force_relocation_abs (fixS
*fixp
)
15561 if (generic_force_reloc (fixp
))
15564 /* These relocations do not have enough bits in the in-place addend
15565 to hold an arbitrary absolute section's offset. */
15566 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15572 /* Read the instruction associated with RELOC from BUF. */
15574 static unsigned int
15575 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15577 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15578 return read_compressed_insn (buf
, 4);
15580 return read_insn (buf
);
15583 /* Write instruction INSN to BUF, given that it has been relocated
15587 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15588 unsigned long insn
)
15590 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15591 write_compressed_insn (buf
, insn
, 4);
15593 write_insn (buf
, insn
);
15596 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15597 to a symbol in another ISA mode, which cannot be converted to JALX. */
15600 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15602 unsigned long opcode
;
15606 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, true))
15609 other
= S_GET_OTHER (fixP
->fx_addsy
);
15610 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15611 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15612 switch (fixP
->fx_r_type
)
15614 case BFD_RELOC_MIPS_JMP
:
15615 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15616 case BFD_RELOC_MICROMIPS_JMP
:
15617 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15623 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15624 jump to a symbol in the same ISA mode. */
15627 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15629 unsigned long opcode
;
15633 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, true))
15636 other
= S_GET_OTHER (fixP
->fx_addsy
);
15637 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15638 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15639 switch (fixP
->fx_r_type
)
15641 case BFD_RELOC_MIPS_JMP
:
15642 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15643 case BFD_RELOC_MIPS16_JMP
:
15644 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15645 case BFD_RELOC_MICROMIPS_JMP
:
15646 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15652 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15653 to a symbol whose value plus addend is not aligned according to the
15654 ultimate (after linker relaxation) jump instruction's immediate field
15655 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15656 regular MIPS code, to (1 << 2). */
15659 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15661 bool micro_to_mips_p
;
15665 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, true))
15668 other
= S_GET_OTHER (fixP
->fx_addsy
);
15669 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15670 val
+= fixP
->fx_offset
;
15671 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15672 && !ELF_ST_IS_MICROMIPS (other
));
15673 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15674 != ELF_ST_IS_COMPRESSED (other
));
15677 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15678 to a symbol whose annotation indicates another ISA mode. For absolute
15679 symbols check the ISA bit instead.
15681 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15682 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15683 MIPS symbols and associated with BAL instructions as these instructions
15684 may be converted to JALX by the linker. */
15687 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15690 unsigned long opcode
;
15696 if (mips_ignore_branch_isa
)
15699 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, true))
15702 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15703 absolute_p
= bfd_is_abs_section (symsec
);
15705 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15706 other
= S_GET_OTHER (fixP
->fx_addsy
);
15708 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15709 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15710 switch (fixP
->fx_r_type
)
15712 case BFD_RELOC_16_PCREL_S2
:
15713 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15714 && opcode
!= 0x0411);
15715 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15716 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15717 && opcode
!= 0x4060);
15718 case BFD_RELOC_MIPS_21_PCREL_S2
:
15719 case BFD_RELOC_MIPS_26_PCREL_S2
:
15720 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15721 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15722 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15723 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15724 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15725 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15731 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15732 branch instruction pointed to by FIXP is not aligned according to the
15733 branch instruction's immediate field requirement. We need the addend
15734 to preserve the ISA bit and also the sum must not have bit 2 set. We
15735 must explicitly OR in the ISA bit from symbol annotation as the bit
15736 won't be set in the symbol's value then. */
15739 fix_bad_misaligned_branch_p (fixS
*fixP
)
15748 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, true))
15751 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15752 absolute_p
= bfd_is_abs_section (symsec
);
15754 val
= S_GET_VALUE (fixP
->fx_addsy
);
15755 other
= S_GET_OTHER (fixP
->fx_addsy
);
15756 off
= fixP
->fx_offset
;
15758 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15759 val
|= ELF_ST_IS_COMPRESSED (other
);
15761 return (val
& 0x3) != isa_bit
;
15764 /* Calculate the relocation target by masking off ISA mode bit before
15765 combining symbol and addend. */
15768 fix_bad_misaligned_address (fixS
*fixP
)
15773 gas_assert (fixP
!= NULL
&& fixP
->fx_addsy
!= NULL
);
15774 val
= S_GET_VALUE (fixP
->fx_addsy
);
15775 off
= fixP
->fx_offset
;
15776 isa_mode
= (ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixP
->fx_addsy
))
15779 return ((val
& ~isa_mode
) + off
);
15782 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15783 and its calculated value VAL. */
15786 fix_validate_branch (fixS
*fixP
, valueT val
)
15788 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15789 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15790 _("branch to misaligned address (0x%lx)"),
15791 (long) (val
+ md_pcrel_from (fixP
)));
15792 else if (fix_bad_cross_mode_branch_p (fixP
))
15793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15794 _("branch to a symbol in another ISA mode"));
15795 else if (fix_bad_misaligned_branch_p (fixP
))
15796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15797 _("branch to misaligned address (0x%lx)"),
15798 (long) fix_bad_misaligned_address (fixP
));
15799 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15800 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15801 _("cannot encode misaligned addend "
15802 "in the relocatable field (0x%lx)"),
15803 (long) fixP
->fx_offset
);
15806 /* Apply a fixup to the object file. */
15809 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15812 unsigned long insn
;
15813 reloc_howto_type
*howto
;
15815 if (fixP
->fx_pcrel
)
15816 switch (fixP
->fx_r_type
)
15818 case BFD_RELOC_16_PCREL_S2
:
15819 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15820 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15821 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15822 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15823 case BFD_RELOC_32_PCREL
:
15824 case BFD_RELOC_MIPS_21_PCREL_S2
:
15825 case BFD_RELOC_MIPS_26_PCREL_S2
:
15826 case BFD_RELOC_MIPS_18_PCREL_S3
:
15827 case BFD_RELOC_MIPS_19_PCREL_S2
:
15828 case BFD_RELOC_HI16_S_PCREL
:
15829 case BFD_RELOC_LO16_PCREL
:
15833 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15837 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15838 _("PC-relative reference to a different section"));
15842 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15843 that have no MIPS ELF equivalent. */
15844 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15846 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15851 gas_assert (fixP
->fx_size
== 2
15852 || fixP
->fx_size
== 4
15853 || fixP
->fx_r_type
== BFD_RELOC_8
15854 || fixP
->fx_r_type
== BFD_RELOC_16
15855 || fixP
->fx_r_type
== BFD_RELOC_64
15856 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15857 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15858 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15859 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15860 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15861 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15862 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15864 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15866 /* Don't treat parts of a composite relocation as done. There are two
15869 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15870 should nevertheless be emitted if the first part is.
15872 (2) In normal usage, composite relocations are never assembly-time
15873 constants. The easiest way of dealing with the pathological
15874 exceptions is to generate a relocation against STN_UNDEF and
15875 leave everything up to the linker. */
15876 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15879 switch (fixP
->fx_r_type
)
15881 case BFD_RELOC_MIPS_TLS_GD
:
15882 case BFD_RELOC_MIPS_TLS_LDM
:
15883 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15884 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15885 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15886 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15887 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15888 case BFD_RELOC_MIPS_TLS_TPREL32
:
15889 case BFD_RELOC_MIPS_TLS_TPREL64
:
15890 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15891 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15892 case BFD_RELOC_MICROMIPS_TLS_GD
:
15893 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15894 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15895 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15896 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15897 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15898 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15899 case BFD_RELOC_MIPS16_TLS_GD
:
15900 case BFD_RELOC_MIPS16_TLS_LDM
:
15901 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15902 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15903 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15904 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15905 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15906 if (fixP
->fx_addsy
)
15907 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15909 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15910 _("TLS relocation against a constant"));
15913 case BFD_RELOC_MIPS_JMP
:
15914 case BFD_RELOC_MIPS16_JMP
:
15915 case BFD_RELOC_MICROMIPS_JMP
:
15919 gas_assert (!fixP
->fx_done
);
15921 /* Shift is 2, unusually, for microMIPS JALX. */
15922 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15923 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15928 if (fix_bad_cross_mode_jump_p (fixP
))
15929 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15930 _("jump to a symbol in another ISA mode"));
15931 else if (fix_bad_same_mode_jalx_p (fixP
))
15932 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15933 _("JALX to a symbol in the same ISA mode"));
15934 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15935 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15936 _("jump to misaligned address (0x%lx)"),
15937 (long) fix_bad_misaligned_address (fixP
));
15938 else if (HAVE_IN_PLACE_ADDENDS
15939 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15941 _("cannot encode misaligned addend "
15942 "in the relocatable field (0x%lx)"),
15943 (long) fixP
->fx_offset
);
15945 /* Fall through. */
15947 case BFD_RELOC_MIPS_SHIFT5
:
15948 case BFD_RELOC_MIPS_SHIFT6
:
15949 case BFD_RELOC_MIPS_GOT_DISP
:
15950 case BFD_RELOC_MIPS_GOT_PAGE
:
15951 case BFD_RELOC_MIPS_GOT_OFST
:
15952 case BFD_RELOC_MIPS_SUB
:
15953 case BFD_RELOC_MIPS_INSERT_A
:
15954 case BFD_RELOC_MIPS_INSERT_B
:
15955 case BFD_RELOC_MIPS_DELETE
:
15956 case BFD_RELOC_MIPS_HIGHEST
:
15957 case BFD_RELOC_MIPS_HIGHER
:
15958 case BFD_RELOC_MIPS_SCN_DISP
:
15959 case BFD_RELOC_MIPS_REL16
:
15960 case BFD_RELOC_MIPS_RELGOT
:
15961 case BFD_RELOC_MIPS_JALR
:
15962 case BFD_RELOC_HI16
:
15963 case BFD_RELOC_HI16_S
:
15964 case BFD_RELOC_LO16
:
15965 case BFD_RELOC_GPREL16
:
15966 case BFD_RELOC_MIPS_LITERAL
:
15967 case BFD_RELOC_MIPS_CALL16
:
15968 case BFD_RELOC_MIPS_GOT16
:
15969 case BFD_RELOC_GPREL32
:
15970 case BFD_RELOC_MIPS_GOT_HI16
:
15971 case BFD_RELOC_MIPS_GOT_LO16
:
15972 case BFD_RELOC_MIPS_CALL_HI16
:
15973 case BFD_RELOC_MIPS_CALL_LO16
:
15974 case BFD_RELOC_HI16_S_PCREL
:
15975 case BFD_RELOC_LO16_PCREL
:
15976 case BFD_RELOC_MIPS16_GPREL
:
15977 case BFD_RELOC_MIPS16_GOT16
:
15978 case BFD_RELOC_MIPS16_CALL16
:
15979 case BFD_RELOC_MIPS16_HI16
:
15980 case BFD_RELOC_MIPS16_HI16_S
:
15981 case BFD_RELOC_MIPS16_LO16
:
15982 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15983 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15984 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15985 case BFD_RELOC_MICROMIPS_SUB
:
15986 case BFD_RELOC_MICROMIPS_HIGHEST
:
15987 case BFD_RELOC_MICROMIPS_HIGHER
:
15988 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15989 case BFD_RELOC_MICROMIPS_JALR
:
15990 case BFD_RELOC_MICROMIPS_HI16
:
15991 case BFD_RELOC_MICROMIPS_HI16_S
:
15992 case BFD_RELOC_MICROMIPS_LO16
:
15993 case BFD_RELOC_MICROMIPS_GPREL16
:
15994 case BFD_RELOC_MICROMIPS_LITERAL
:
15995 case BFD_RELOC_MICROMIPS_CALL16
:
15996 case BFD_RELOC_MICROMIPS_GOT16
:
15997 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15998 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15999 case BFD_RELOC_MICROMIPS_CALL_HI16
:
16000 case BFD_RELOC_MICROMIPS_CALL_LO16
:
16001 case BFD_RELOC_MIPS_EH
:
16006 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
16008 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
16009 if (mips16_reloc_p (fixP
->fx_r_type
))
16010 insn
|= mips16_immed_extend (value
, 16);
16012 insn
|= (value
& 0xffff);
16013 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
16016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16017 _("unsupported constant in relocation"));
16022 /* This is handled like BFD_RELOC_32, but we output a sign
16023 extended value if we are only 32 bits. */
16026 if (8 <= sizeof (valueT
))
16027 md_number_to_chars (buf
, *valP
, 8);
16032 if ((*valP
& 0x80000000) != 0)
16036 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
16037 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
16042 case BFD_RELOC_RVA
:
16044 case BFD_RELOC_32_PCREL
:
16047 /* If we are deleting this reloc entry, we must fill in the
16048 value now. This can happen if we have a .word which is not
16049 resolved when it appears but is later defined. */
16051 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
16054 case BFD_RELOC_MIPS_21_PCREL_S2
:
16055 fix_validate_branch (fixP
, *valP
);
16056 if (!fixP
->fx_done
)
16059 if (*valP
+ 0x400000 <= 0x7fffff)
16061 insn
= read_insn (buf
);
16062 insn
|= (*valP
>> 2) & 0x1fffff;
16063 write_insn (buf
, insn
);
16066 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16067 _("branch out of range"));
16070 case BFD_RELOC_MIPS_26_PCREL_S2
:
16071 fix_validate_branch (fixP
, *valP
);
16072 if (!fixP
->fx_done
)
16075 if (*valP
+ 0x8000000 <= 0xfffffff)
16077 insn
= read_insn (buf
);
16078 insn
|= (*valP
>> 2) & 0x3ffffff;
16079 write_insn (buf
, insn
);
16082 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16083 _("branch out of range"));
16086 case BFD_RELOC_MIPS_18_PCREL_S3
:
16087 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
16088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16089 _("PC-relative access using misaligned symbol (%lx)"),
16090 (long) S_GET_VALUE (fixP
->fx_addsy
));
16091 if ((fixP
->fx_offset
& 0x7) != 0)
16092 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16093 _("PC-relative access using misaligned offset (%lx)"),
16094 (long) fixP
->fx_offset
);
16095 if (!fixP
->fx_done
)
16098 if (*valP
+ 0x100000 <= 0x1fffff)
16100 insn
= read_insn (buf
);
16101 insn
|= (*valP
>> 3) & 0x3ffff;
16102 write_insn (buf
, insn
);
16105 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16106 _("PC-relative access out of range"));
16109 case BFD_RELOC_MIPS_19_PCREL_S2
:
16110 if ((*valP
& 0x3) != 0)
16111 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16112 _("PC-relative access to misaligned address (%lx)"),
16114 if (!fixP
->fx_done
)
16117 if (*valP
+ 0x100000 <= 0x1fffff)
16119 insn
= read_insn (buf
);
16120 insn
|= (*valP
>> 2) & 0x7ffff;
16121 write_insn (buf
, insn
);
16124 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16125 _("PC-relative access out of range"));
16128 case BFD_RELOC_16_PCREL_S2
:
16129 fix_validate_branch (fixP
, *valP
);
16131 /* We need to save the bits in the instruction since fixup_segment()
16132 might be deleting the relocation entry (i.e., a branch within
16133 the current segment). */
16134 if (! fixP
->fx_done
)
16137 /* Update old instruction data. */
16138 insn
= read_insn (buf
);
16140 if (*valP
+ 0x20000 <= 0x3ffff)
16142 insn
|= (*valP
>> 2) & 0xffff;
16143 write_insn (buf
, insn
);
16145 else if (fixP
->fx_tcbit2
16147 && fixP
->fx_frag
->fr_address
>= text_section
->vma
16148 && (fixP
->fx_frag
->fr_address
16149 < text_section
->vma
+ bfd_section_size (text_section
))
16150 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
16151 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
16152 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
16154 /* The branch offset is too large. If this is an
16155 unconditional branch, and we are not generating PIC code,
16156 we can convert it to an absolute jump instruction. */
16157 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
16158 insn
= 0x0c000000; /* jal */
16160 insn
= 0x08000000; /* j */
16161 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
16163 fixP
->fx_addsy
= section_symbol (text_section
);
16164 *valP
+= md_pcrel_from (fixP
);
16165 write_insn (buf
, insn
);
16169 /* If we got here, we have branch-relaxation disabled,
16170 and there's nothing we can do to fix this instruction
16171 without turning it into a longer sequence. */
16172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16173 _("branch out of range"));
16177 case BFD_RELOC_MIPS16_16_PCREL_S1
:
16178 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
16179 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
16180 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
16181 gas_assert (!fixP
->fx_done
);
16182 if (fix_bad_cross_mode_branch_p (fixP
))
16183 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16184 _("branch to a symbol in another ISA mode"));
16185 else if (fixP
->fx_addsy
16186 && !S_FORCE_RELOC (fixP
->fx_addsy
, true)
16187 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
16188 && (fixP
->fx_offset
& 0x1) != 0)
16189 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16190 _("branch to misaligned address (0x%lx)"),
16191 (long) fix_bad_misaligned_address (fixP
));
16192 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
16193 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16194 _("cannot encode misaligned addend "
16195 "in the relocatable field (0x%lx)"),
16196 (long) fixP
->fx_offset
);
16199 case BFD_RELOC_VTABLE_INHERIT
:
16202 && !S_IS_DEFINED (fixP
->fx_addsy
)
16203 && !S_IS_WEAK (fixP
->fx_addsy
))
16204 S_SET_WEAK (fixP
->fx_addsy
);
16207 case BFD_RELOC_NONE
:
16208 case BFD_RELOC_VTABLE_ENTRY
:
16216 /* Remember value for tc_gen_reloc. */
16217 fixP
->fx_addnumber
= *valP
;
16227 c
= get_symbol_name (&name
);
16228 p
= (symbolS
*) symbol_find_or_make (name
);
16229 (void) restore_line_pointer (c
);
16233 /* Align the current frag to a given power of two. If a particular
16234 fill byte should be used, FILL points to an integer that contains
16235 that byte, otherwise FILL is null.
16237 This function used to have the comment:
16239 The MIPS assembler also automatically adjusts any preceding label.
16241 The implementation therefore applied the adjustment to a maximum of
16242 one label. However, other label adjustments are applied to batches
16243 of labels, and adjusting just one caused problems when new labels
16244 were added for the sake of debugging or unwind information.
16245 We therefore adjust all preceding labels (given as LABELS) instead. */
16248 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16250 mips_emit_delays ();
16251 mips_record_compressed_mode ();
16252 if (fill
== NULL
&& subseg_text_p (now_seg
))
16253 frag_align_code (to
, 0);
16255 frag_align (to
, fill
? *fill
: 0, 0);
16256 record_alignment (now_seg
, to
);
16257 mips_move_labels (labels
, subseg_text_p (now_seg
));
16260 /* Align to a given power of two. .align 0 turns off the automatic
16261 alignment used by the data creating pseudo-ops. */
16264 s_align (int x ATTRIBUTE_UNUSED
)
16266 int temp
, fill_value
, *fill_ptr
;
16267 long max_alignment
= 28;
16269 /* o Note that the assembler pulls down any immediately preceding label
16270 to the aligned address.
16271 o It's not documented but auto alignment is reinstated by
16272 a .align pseudo instruction.
16273 o Note also that after auto alignment is turned off the mips assembler
16274 issues an error on attempt to assemble an improperly aligned data item.
16277 temp
= get_absolute_expression ();
16278 if (temp
> max_alignment
)
16279 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
16282 as_warn (_("alignment negative, 0 assumed"));
16285 if (*input_line_pointer
== ',')
16287 ++input_line_pointer
;
16288 fill_value
= get_absolute_expression ();
16289 fill_ptr
= &fill_value
;
16295 segment_info_type
*si
= seg_info (now_seg
);
16296 struct insn_label_list
*l
= si
->label_list
;
16297 /* Auto alignment should be switched on by next section change. */
16299 mips_align (temp
, fill_ptr
, l
);
16306 demand_empty_rest_of_line ();
16310 s_change_sec (int sec
)
16314 /* The ELF backend needs to know that we are changing sections, so
16315 that .previous works correctly. We could do something like check
16316 for an obj_section_change_hook macro, but that might be confusing
16317 as it would not be appropriate to use it in the section changing
16318 functions in read.c, since obj-elf.c intercepts those. FIXME:
16319 This should be cleaner, somehow. */
16320 obj_elf_section_change_hook ();
16322 mips_emit_delays ();
16333 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16334 demand_empty_rest_of_line ();
16338 seg
= subseg_new (RDATA_SECTION_NAME
,
16339 (subsegT
) get_absolute_expression ());
16340 bfd_set_section_flags (seg
, (SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
16341 | SEC_RELOC
| SEC_DATA
));
16342 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16343 record_alignment (seg
, 4);
16344 demand_empty_rest_of_line ();
16348 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16349 bfd_set_section_flags (seg
, (SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
16350 | SEC_DATA
| SEC_SMALL_DATA
));
16351 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16352 record_alignment (seg
, 4);
16353 demand_empty_rest_of_line ();
16357 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16358 bfd_set_section_flags (seg
, SEC_ALLOC
| SEC_SMALL_DATA
);
16359 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16360 record_alignment (seg
, 4);
16361 demand_empty_rest_of_line ();
16369 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16372 char *section_name
;
16377 int section_entry_size
;
16378 int section_alignment
;
16380 saved_ilp
= input_line_pointer
;
16381 endc
= get_symbol_name (§ion_name
);
16382 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
16384 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
16386 /* Do we have .section Name<,"flags">? */
16387 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16389 /* Just after name is now '\0'. */
16390 (void) restore_line_pointer (endc
);
16391 input_line_pointer
= saved_ilp
;
16392 obj_elf_section (ignore
);
16396 section_name
= xstrdup (section_name
);
16397 c
= restore_line_pointer (endc
);
16399 input_line_pointer
++;
16401 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16403 section_type
= get_absolute_expression ();
16407 if (*input_line_pointer
++ == ',')
16408 section_flag
= get_absolute_expression ();
16412 if (*input_line_pointer
++ == ',')
16413 section_entry_size
= get_absolute_expression ();
16415 section_entry_size
= 0;
16417 if (*input_line_pointer
++ == ',')
16418 section_alignment
= get_absolute_expression ();
16420 section_alignment
= 0;
16422 /* FIXME: really ignore? */
16423 (void) section_alignment
;
16425 /* When using the generic form of .section (as implemented by obj-elf.c),
16426 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16427 traditionally had to fall back on the more common @progbits instead.
16429 There's nothing really harmful in this, since bfd will correct
16430 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16431 means that, for backwards compatibility, the special_section entries
16432 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16434 Even so, we shouldn't force users of the MIPS .section syntax to
16435 incorrectly label the sections as SHT_PROGBITS. The best compromise
16436 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16437 generic type-checking code. */
16438 if (section_type
== SHT_MIPS_DWARF
)
16439 section_type
= SHT_PROGBITS
;
16441 obj_elf_change_section (section_name
, section_type
, section_flag
,
16442 section_entry_size
, 0, 0, 0);
16444 if (now_seg
->name
!= section_name
)
16445 free (section_name
);
16449 mips_enable_auto_align (void)
16455 s_cons (int log_size
)
16457 segment_info_type
*si
= seg_info (now_seg
);
16458 struct insn_label_list
*l
= si
->label_list
;
16460 mips_emit_delays ();
16461 if (log_size
> 0 && auto_align
)
16462 mips_align (log_size
, 0, l
);
16463 cons (1 << log_size
);
16464 mips_clear_insn_labels ();
16468 s_float_cons (int type
)
16470 segment_info_type
*si
= seg_info (now_seg
);
16471 struct insn_label_list
*l
= si
->label_list
;
16473 mips_emit_delays ();
16478 mips_align (3, 0, l
);
16480 mips_align (2, 0, l
);
16484 mips_clear_insn_labels ();
16487 /* Handle .globl. We need to override it because on Irix 5 you are
16490 where foo is an undefined symbol, to mean that foo should be
16491 considered to be the address of a function. */
16494 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16502 c
= get_symbol_name (&name
);
16503 symbolP
= symbol_find_or_make (name
);
16504 S_SET_EXTERNAL (symbolP
);
16506 *input_line_pointer
= c
;
16507 SKIP_WHITESPACE_AFTER_NAME ();
16509 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16510 && (*input_line_pointer
!= ','))
16515 c
= get_symbol_name (&secname
);
16516 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16518 as_bad (_("%s: no such section"), secname
);
16519 (void) restore_line_pointer (c
);
16521 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16522 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
16525 c
= *input_line_pointer
;
16528 input_line_pointer
++;
16529 SKIP_WHITESPACE ();
16530 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16536 demand_empty_rest_of_line ();
16540 /* The Irix 5 and 6 assemblers set the type of any common symbol and
16541 any undefined non-function symbol to STT_OBJECT. We try to be
16542 compatible, since newer Irix 5 and 6 linkers care. */
16545 mips_frob_symbol (symbolS
*symp ATTRIBUTE_UNUSED
)
16547 /* This late in assembly we can set BSF_OBJECT indiscriminately
16548 and let elf.c:swap_out_syms sort out the symbol type. */
16549 flagword
*flags
= &symbol_get_bfdsym (symp
)->flags
;
16550 if ((*flags
& (BSF_GLOBAL
| BSF_WEAK
)) != 0
16551 || !S_IS_DEFINED (symp
))
16552 *flags
|= BSF_OBJECT
;
16557 s_option (int x ATTRIBUTE_UNUSED
)
16562 c
= get_symbol_name (&opt
);
16566 /* FIXME: What does this mean? */
16568 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16572 i
= atoi (opt
+ 3);
16573 if (i
!= 0 && i
!= 2)
16574 as_bad (_(".option pic%d not supported"), i
);
16575 else if (mips_pic
== VXWORKS_PIC
)
16576 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16581 mips_pic
= SVR4_PIC
;
16582 mips_abicalls
= true;
16585 if (mips_pic
== SVR4_PIC
)
16587 if (g_switch_seen
&& g_switch_value
!= 0)
16588 as_warn (_("-G may not be used with SVR4 PIC code"));
16589 g_switch_value
= 0;
16590 bfd_set_gp_size (stdoutput
, 0);
16594 as_warn (_("unrecognized option \"%s\""), opt
);
16596 (void) restore_line_pointer (c
);
16597 demand_empty_rest_of_line ();
16600 /* This structure is used to hold a stack of .set values. */
16602 struct mips_option_stack
16604 struct mips_option_stack
*next
;
16605 struct mips_set_options options
;
16608 static struct mips_option_stack
*mips_opts_stack
;
16610 /* Return status for .set/.module option handling. */
16612 enum code_option_type
16614 /* Unrecognized option. */
16615 OPTION_TYPE_BAD
= -1,
16617 /* Ordinary option. */
16618 OPTION_TYPE_NORMAL
,
16620 /* ISA changing option. */
16624 /* Handle common .set/.module options. Return status indicating option
16627 static enum code_option_type
16628 parse_code_option (char * name
)
16630 bool isa_set
= false;
16631 const struct mips_ase
*ase
;
16633 if (strncmp (name
, "at=", 3) == 0)
16635 char *s
= name
+ 3;
16637 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16638 as_bad (_("unrecognized register name `%s'"), s
);
16640 else if (strcmp (name
, "at") == 0)
16641 mips_opts
.at
= ATREG
;
16642 else if (strcmp (name
, "noat") == 0)
16643 mips_opts
.at
= ZERO
;
16644 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16645 mips_opts
.nomove
= 0;
16646 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16647 mips_opts
.nomove
= 1;
16648 else if (strcmp (name
, "bopt") == 0)
16649 mips_opts
.nobopt
= 0;
16650 else if (strcmp (name
, "nobopt") == 0)
16651 mips_opts
.nobopt
= 1;
16652 else if (strcmp (name
, "gp=32") == 0)
16654 else if (strcmp (name
, "gp=64") == 0)
16656 else if (strcmp (name
, "fp=32") == 0)
16658 else if (strcmp (name
, "fp=xx") == 0)
16660 else if (strcmp (name
, "fp=64") == 0)
16662 else if (strcmp (name
, "softfloat") == 0)
16663 mips_opts
.soft_float
= 1;
16664 else if (strcmp (name
, "hardfloat") == 0)
16665 mips_opts
.soft_float
= 0;
16666 else if (strcmp (name
, "singlefloat") == 0)
16667 mips_opts
.single_float
= 1;
16668 else if (strcmp (name
, "doublefloat") == 0)
16669 mips_opts
.single_float
= 0;
16670 else if (strcmp (name
, "nooddspreg") == 0)
16671 mips_opts
.oddspreg
= 0;
16672 else if (strcmp (name
, "oddspreg") == 0)
16673 mips_opts
.oddspreg
= 1;
16674 else if (strcmp (name
, "mips16") == 0
16675 || strcmp (name
, "MIPS-16") == 0)
16676 mips_opts
.mips16
= 1;
16677 else if (strcmp (name
, "nomips16") == 0
16678 || strcmp (name
, "noMIPS-16") == 0)
16679 mips_opts
.mips16
= 0;
16680 else if (strcmp (name
, "micromips") == 0)
16681 mips_opts
.micromips
= 1;
16682 else if (strcmp (name
, "nomicromips") == 0)
16683 mips_opts
.micromips
= 0;
16684 else if (name
[0] == 'n'
16686 && (ase
= mips_lookup_ase (name
+ 2)))
16687 mips_set_ase (ase
, &mips_opts
, false);
16688 else if ((ase
= mips_lookup_ase (name
)))
16689 mips_set_ase (ase
, &mips_opts
, true);
16690 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16692 /* Permit the user to change the ISA and architecture on the fly.
16693 Needless to say, misuse can cause serious problems. */
16694 if (strncmp (name
, "arch=", 5) == 0)
16696 const struct mips_cpu_info
*p
;
16698 p
= mips_parse_cpu ("internal use", name
+ 5);
16700 as_bad (_("unknown architecture %s"), name
+ 5);
16703 mips_opts
.arch
= p
->cpu
;
16704 mips_opts
.isa
= p
->isa
;
16706 mips_opts
.init_ase
= p
->ase
;
16709 else if (strncmp (name
, "mips", 4) == 0)
16711 const struct mips_cpu_info
*p
;
16713 p
= mips_parse_cpu ("internal use", name
);
16715 as_bad (_("unknown ISA level %s"), name
+ 4);
16718 mips_opts
.arch
= p
->cpu
;
16719 mips_opts
.isa
= p
->isa
;
16721 mips_opts
.init_ase
= p
->ase
;
16725 as_bad (_("unknown ISA or architecture %s"), name
);
16727 else if (strcmp (name
, "autoextend") == 0)
16728 mips_opts
.noautoextend
= 0;
16729 else if (strcmp (name
, "noautoextend") == 0)
16730 mips_opts
.noautoextend
= 1;
16731 else if (strcmp (name
, "insn32") == 0)
16732 mips_opts
.insn32
= true;
16733 else if (strcmp (name
, "noinsn32") == 0)
16734 mips_opts
.insn32
= false;
16735 else if (strcmp (name
, "sym32") == 0)
16736 mips_opts
.sym32
= true;
16737 else if (strcmp (name
, "nosym32") == 0)
16738 mips_opts
.sym32
= false;
16740 return OPTION_TYPE_BAD
;
16742 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16745 /* Handle the .set pseudo-op. */
16748 s_mipsset (int x ATTRIBUTE_UNUSED
)
16750 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16751 char *name
= input_line_pointer
, ch
;
16753 file_mips_check_options ();
16755 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16756 ++input_line_pointer
;
16757 ch
= *input_line_pointer
;
16758 *input_line_pointer
= '\0';
16760 if (strchr (name
, ','))
16762 /* Generic ".set" directive; use the generic handler. */
16763 *input_line_pointer
= ch
;
16764 input_line_pointer
= name
;
16769 if (strcmp (name
, "reorder") == 0)
16771 if (mips_opts
.noreorder
)
16774 else if (strcmp (name
, "noreorder") == 0)
16776 if (!mips_opts
.noreorder
)
16777 start_noreorder ();
16779 else if (strcmp (name
, "macro") == 0)
16780 mips_opts
.warn_about_macros
= 0;
16781 else if (strcmp (name
, "nomacro") == 0)
16783 if (mips_opts
.noreorder
== 0)
16784 as_bad (_("`noreorder' must be set before `nomacro'"));
16785 mips_opts
.warn_about_macros
= 1;
16787 else if (strcmp (name
, "gp=default") == 0)
16788 mips_opts
.gp
= file_mips_opts
.gp
;
16789 else if (strcmp (name
, "fp=default") == 0)
16790 mips_opts
.fp
= file_mips_opts
.fp
;
16791 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16793 mips_opts
.isa
= file_mips_opts
.isa
;
16794 mips_opts
.arch
= file_mips_opts
.arch
;
16795 mips_opts
.init_ase
= file_mips_opts
.init_ase
;
16796 mips_opts
.gp
= file_mips_opts
.gp
;
16797 mips_opts
.fp
= file_mips_opts
.fp
;
16799 else if (strcmp (name
, "push") == 0)
16801 struct mips_option_stack
*s
;
16803 s
= XNEW (struct mips_option_stack
);
16804 s
->next
= mips_opts_stack
;
16805 s
->options
= mips_opts
;
16806 mips_opts_stack
= s
;
16808 else if (strcmp (name
, "pop") == 0)
16810 struct mips_option_stack
*s
;
16812 s
= mips_opts_stack
;
16814 as_bad (_(".set pop with no .set push"));
16817 /* If we're changing the reorder mode we need to handle
16818 delay slots correctly. */
16819 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16820 start_noreorder ();
16821 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16824 mips_opts
= s
->options
;
16825 mips_opts_stack
= s
->next
;
16831 type
= parse_code_option (name
);
16832 if (type
== OPTION_TYPE_BAD
)
16833 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16836 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16837 registers based on what is supported by the arch/cpu. */
16838 if (type
== OPTION_TYPE_ISA
)
16840 switch (mips_opts
.isa
)
16845 /* MIPS I cannot support FPXX. */
16847 /* fall-through. */
16854 if (mips_opts
.fp
!= 0)
16870 if (mips_opts
.fp
!= 0)
16872 if (mips_opts
.arch
== CPU_R5900
)
16879 as_bad (_("unknown ISA level %s"), name
+ 4);
16884 mips_check_options (&mips_opts
, false);
16886 mips_check_isa_supports_ases ();
16887 *input_line_pointer
= ch
;
16888 demand_empty_rest_of_line ();
16891 /* Handle the .module pseudo-op. */
16894 s_module (int ignore ATTRIBUTE_UNUSED
)
16896 char *name
= input_line_pointer
, ch
;
16898 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16899 ++input_line_pointer
;
16900 ch
= *input_line_pointer
;
16901 *input_line_pointer
= '\0';
16903 if (!file_mips_opts_checked
)
16905 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16906 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16908 /* Update module level settings from mips_opts. */
16909 file_mips_opts
= mips_opts
;
16912 as_bad (_(".module is not permitted after generating code"));
16914 *input_line_pointer
= ch
;
16915 demand_empty_rest_of_line ();
16918 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16919 .option pic2. It means to generate SVR4 PIC calls. */
16922 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16924 mips_pic
= SVR4_PIC
;
16925 mips_abicalls
= true;
16927 if (g_switch_seen
&& g_switch_value
!= 0)
16928 as_warn (_("-G may not be used with SVR4 PIC code"));
16929 g_switch_value
= 0;
16931 bfd_set_gp_size (stdoutput
, 0);
16932 demand_empty_rest_of_line ();
16935 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16936 PIC code. It sets the $gp register for the function based on the
16937 function address, which is in the register named in the argument.
16938 This uses a relocation against _gp_disp, which is handled specially
16939 by the linker. The result is:
16940 lui $gp,%hi(_gp_disp)
16941 addiu $gp,$gp,%lo(_gp_disp)
16942 addu $gp,$gp,.cpload argument
16943 The .cpload argument is normally $25 == $t9.
16945 The -mno-shared option changes this to:
16946 lui $gp,%hi(__gnu_local_gp)
16947 addiu $gp,$gp,%lo(__gnu_local_gp)
16948 and the argument is ignored. This saves an instruction, but the
16949 resulting code is not position independent; it uses an absolute
16950 address for __gnu_local_gp. Thus code assembled with -mno-shared
16951 can go into an ordinary executable, but not into a shared library. */
16954 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16960 file_mips_check_options ();
16962 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16963 .cpload is ignored. */
16964 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16970 if (mips_opts
.mips16
)
16972 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16973 ignore_rest_of_line ();
16977 /* .cpload should be in a .set noreorder section. */
16978 if (mips_opts
.noreorder
== 0)
16979 as_warn (_(".cpload not in noreorder section"));
16981 reg
= tc_get_register (0);
16983 /* If we need to produce a 64-bit address, we are better off using
16984 the default instruction sequence. */
16985 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16987 ex
.X_op
= O_symbol
;
16988 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16990 ex
.X_op_symbol
= NULL
;
16991 ex
.X_add_number
= 0;
16993 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16994 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16996 mips_mark_labels ();
16997 mips_assembling_insn
= true;
17000 macro_build_lui (&ex
, mips_gp_register
);
17001 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
17002 mips_gp_register
, BFD_RELOC_LO16
);
17004 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
17005 mips_gp_register
, reg
);
17008 mips_assembling_insn
= false;
17009 demand_empty_rest_of_line ();
17012 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
17013 .cpsetup $reg1, offset|$reg2, label
17015 If offset is given, this results in:
17016 sd $gp, offset($sp)
17017 lui $gp, %hi(%neg(%gp_rel(label)))
17018 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17019 daddu $gp, $gp, $reg1
17021 If $reg2 is given, this results in:
17023 lui $gp, %hi(%neg(%gp_rel(label)))
17024 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17025 daddu $gp, $gp, $reg1
17026 $reg1 is normally $25 == $t9.
17028 The -mno-shared option replaces the last three instructions with
17030 addiu $gp,$gp,%lo(_gp) */
17033 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
17035 expressionS ex_off
;
17036 expressionS ex_sym
;
17039 file_mips_check_options ();
17041 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
17042 We also need NewABI support. */
17043 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17049 if (mips_opts
.mips16
)
17051 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
17052 ignore_rest_of_line ();
17056 reg1
= tc_get_register (0);
17057 SKIP_WHITESPACE ();
17058 if (*input_line_pointer
!= ',')
17060 as_bad (_("missing argument separator ',' for .cpsetup"));
17064 ++input_line_pointer
;
17065 SKIP_WHITESPACE ();
17066 if (*input_line_pointer
== '$')
17068 mips_cpreturn_register
= tc_get_register (0);
17069 mips_cpreturn_offset
= -1;
17073 mips_cpreturn_offset
= get_absolute_expression ();
17074 mips_cpreturn_register
= -1;
17076 SKIP_WHITESPACE ();
17077 if (*input_line_pointer
!= ',')
17079 as_bad (_("missing argument separator ',' for .cpsetup"));
17083 ++input_line_pointer
;
17084 SKIP_WHITESPACE ();
17085 expression (&ex_sym
);
17087 mips_mark_labels ();
17088 mips_assembling_insn
= true;
17091 if (mips_cpreturn_register
== -1)
17093 ex_off
.X_op
= O_constant
;
17094 ex_off
.X_add_symbol
= NULL
;
17095 ex_off
.X_op_symbol
= NULL
;
17096 ex_off
.X_add_number
= mips_cpreturn_offset
;
17098 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
17099 BFD_RELOC_LO16
, SP
);
17102 move_register (mips_cpreturn_register
, mips_gp_register
);
17104 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
17106 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
17107 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
17110 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
17111 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
17112 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
17114 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
17115 mips_gp_register
, reg1
);
17121 ex
.X_op
= O_symbol
;
17122 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
17123 ex
.X_op_symbol
= NULL
;
17124 ex
.X_add_number
= 0;
17126 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
17127 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
17129 macro_build_lui (&ex
, mips_gp_register
);
17130 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
17131 mips_gp_register
, BFD_RELOC_LO16
);
17136 mips_assembling_insn
= false;
17137 demand_empty_rest_of_line ();
17141 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
17143 file_mips_check_options ();
17145 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
17146 .cplocal is ignored. */
17147 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17153 if (mips_opts
.mips16
)
17155 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
17156 ignore_rest_of_line ();
17160 mips_gp_register
= tc_get_register (0);
17161 demand_empty_rest_of_line ();
17164 /* Handle the .cprestore pseudo-op. This stores $gp into a given
17165 offset from $sp. The offset is remembered, and after making a PIC
17166 call $gp is restored from that location. */
17169 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
17173 file_mips_check_options ();
17175 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17176 .cprestore is ignored. */
17177 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
17183 if (mips_opts
.mips16
)
17185 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17186 ignore_rest_of_line ();
17190 mips_cprestore_offset
= get_absolute_expression ();
17191 mips_cprestore_valid
= 1;
17193 ex
.X_op
= O_constant
;
17194 ex
.X_add_symbol
= NULL
;
17195 ex
.X_op_symbol
= NULL
;
17196 ex
.X_add_number
= mips_cprestore_offset
;
17198 mips_mark_labels ();
17199 mips_assembling_insn
= true;
17202 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
17203 SP
, HAVE_64BIT_ADDRESSES
);
17206 mips_assembling_insn
= false;
17207 demand_empty_rest_of_line ();
17210 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17211 was given in the preceding .cpsetup, it results in:
17212 ld $gp, offset($sp)
17214 If a register $reg2 was given there, it results in:
17215 or $gp, $reg2, $0 */
17218 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
17222 file_mips_check_options ();
17224 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17225 We also need NewABI support. */
17226 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17232 if (mips_opts
.mips16
)
17234 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17235 ignore_rest_of_line ();
17239 mips_mark_labels ();
17240 mips_assembling_insn
= true;
17243 if (mips_cpreturn_register
== -1)
17245 ex
.X_op
= O_constant
;
17246 ex
.X_add_symbol
= NULL
;
17247 ex
.X_op_symbol
= NULL
;
17248 ex
.X_add_number
= mips_cpreturn_offset
;
17250 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
17253 move_register (mips_gp_register
, mips_cpreturn_register
);
17257 mips_assembling_insn
= false;
17258 demand_empty_rest_of_line ();
17261 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17262 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17263 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17264 debug information or MIPS16 TLS. */
17267 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
17268 bfd_reloc_code_real_type rtype
)
17275 if (ex
.X_op
!= O_symbol
)
17277 as_bad (_("unsupported use of %s"), dirstr
);
17278 ignore_rest_of_line ();
17281 p
= frag_more (bytes
);
17282 md_number_to_chars (p
, 0, bytes
);
17283 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, false, rtype
);
17284 demand_empty_rest_of_line ();
17285 mips_clear_insn_labels ();
17288 /* Handle .dtprelword. */
17291 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17293 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17296 /* Handle .dtpreldword. */
17299 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17301 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17304 /* Handle .tprelword. */
17307 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17309 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17312 /* Handle .tpreldword. */
17315 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17317 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17320 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17321 code. It sets the offset to use in gp_rel relocations. */
17324 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17326 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17327 We also need NewABI support. */
17328 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17334 mips_gprel_offset
= get_absolute_expression ();
17336 demand_empty_rest_of_line ();
17339 /* Handle the .gpword pseudo-op. This is used when generating PIC
17340 code. It generates a 32 bit GP relative reloc. */
17343 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17345 segment_info_type
*si
;
17346 struct insn_label_list
*l
;
17350 /* When not generating PIC code, this is treated as .word. */
17351 if (mips_pic
!= SVR4_PIC
)
17357 si
= seg_info (now_seg
);
17358 l
= si
->label_list
;
17359 mips_emit_delays ();
17361 mips_align (2, 0, l
);
17364 mips_clear_insn_labels ();
17366 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17368 as_bad (_("unsupported use of .gpword"));
17369 ignore_rest_of_line ();
17373 md_number_to_chars (p
, 0, 4);
17374 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, false,
17375 BFD_RELOC_GPREL32
);
17377 demand_empty_rest_of_line ();
17381 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17383 segment_info_type
*si
;
17384 struct insn_label_list
*l
;
17388 /* When not generating PIC code, this is treated as .dword. */
17389 if (mips_pic
!= SVR4_PIC
)
17395 si
= seg_info (now_seg
);
17396 l
= si
->label_list
;
17397 mips_emit_delays ();
17399 mips_align (3, 0, l
);
17402 mips_clear_insn_labels ();
17404 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17406 as_bad (_("unsupported use of .gpdword"));
17407 ignore_rest_of_line ();
17411 md_number_to_chars (p
, 0, 8);
17412 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, false,
17413 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17415 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17416 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17417 false, BFD_RELOC_64
)->fx_tcbit
= 1;
17419 demand_empty_rest_of_line ();
17422 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17423 tables. It generates a R_MIPS_EH reloc. */
17426 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17431 mips_emit_delays ();
17434 mips_clear_insn_labels ();
17436 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17438 as_bad (_("unsupported use of .ehword"));
17439 ignore_rest_of_line ();
17443 md_number_to_chars (p
, 0, 4);
17444 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, false,
17445 BFD_RELOC_32_PCREL
);
17447 demand_empty_rest_of_line ();
17450 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17451 tables in SVR4 PIC code. */
17454 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17458 file_mips_check_options ();
17460 /* This is ignored when not generating SVR4 PIC code. */
17461 if (mips_pic
!= SVR4_PIC
)
17467 mips_mark_labels ();
17468 mips_assembling_insn
= true;
17470 /* Add $gp to the register named as an argument. */
17472 reg
= tc_get_register (0);
17473 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17476 mips_assembling_insn
= false;
17477 demand_empty_rest_of_line ();
17480 /* Handle the .insn pseudo-op. This marks instruction labels in
17481 mips16/micromips mode. This permits the linker to handle them specially,
17482 such as generating jalx instructions when needed. We also make
17483 them odd for the duration of the assembly, in order to generate the
17484 right sort of code. We will make them even in the adjust_symtab
17485 routine, while leaving them marked. This is convenient for the
17486 debugger and the disassembler. The linker knows to make them odd
17490 s_insn (int ignore ATTRIBUTE_UNUSED
)
17492 file_mips_check_options ();
17493 file_ase_mips16
|= mips_opts
.mips16
;
17494 file_ase_micromips
|= mips_opts
.micromips
;
17496 mips_mark_labels ();
17498 demand_empty_rest_of_line ();
17501 /* Handle the .nan pseudo-op. */
17504 s_nan (int ignore ATTRIBUTE_UNUSED
)
17506 static const char str_legacy
[] = "legacy";
17507 static const char str_2008
[] = "2008";
17510 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17512 if (i
== sizeof (str_2008
) - 1
17513 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17515 else if (i
== sizeof (str_legacy
) - 1
17516 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17518 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17521 as_bad (_("`%s' does not support legacy NaN"),
17522 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17525 as_bad (_("bad .nan directive"));
17527 input_line_pointer
+= i
;
17528 demand_empty_rest_of_line ();
17531 /* Handle a .stab[snd] directive. Ideally these directives would be
17532 implemented in a transparent way, so that removing them would not
17533 have any effect on the generated instructions. However, s_stab
17534 internally changes the section, so in practice we need to decide
17535 now whether the preceding label marks compressed code. We do not
17536 support changing the compression mode of a label after a .stab*
17537 directive, such as in:
17543 so the current mode wins. */
17546 s_mips_stab (int type
)
17548 file_mips_check_options ();
17549 mips_mark_labels ();
17553 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17556 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17563 c
= get_symbol_name (&name
);
17564 symbolP
= symbol_find_or_make (name
);
17565 S_SET_WEAK (symbolP
);
17566 *input_line_pointer
= c
;
17568 SKIP_WHITESPACE_AFTER_NAME ();
17570 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17572 if (S_IS_DEFINED (symbolP
))
17574 as_bad (_("ignoring attempt to redefine symbol %s"),
17575 S_GET_NAME (symbolP
));
17576 ignore_rest_of_line ();
17580 if (*input_line_pointer
== ',')
17582 ++input_line_pointer
;
17583 SKIP_WHITESPACE ();
17587 if (exp
.X_op
!= O_symbol
)
17589 as_bad (_("bad .weakext directive"));
17590 ignore_rest_of_line ();
17593 symbol_set_value_expression (symbolP
, &exp
);
17596 demand_empty_rest_of_line ();
17599 /* Parse a register string into a number. Called from the ECOFF code
17600 to parse .frame. The argument is non-zero if this is the frame
17601 register, so that we can record it in mips_frame_reg. */
17604 tc_get_register (int frame
)
17608 SKIP_WHITESPACE ();
17609 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17613 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17614 mips_frame_reg_valid
= 1;
17615 mips_cprestore_valid
= 0;
17621 md_section_align (asection
*seg
, valueT addr
)
17623 int align
= bfd_section_alignment (seg
);
17625 /* We don't need to align ELF sections to the full alignment.
17626 However, Irix 5 may prefer that we align them at least to a 16
17627 byte boundary. We don't bother to align the sections if we
17628 are targeted for an embedded system. */
17629 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17634 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17637 /* Utility routine, called from above as well. If called while the
17638 input file is still being read, it's only an approximation. (For
17639 example, a symbol may later become defined which appeared to be
17640 undefined earlier.) */
17643 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17648 if (g_switch_value
> 0)
17650 const char *symname
;
17653 /* Find out whether this symbol can be referenced off the $gp
17654 register. It can be if it is smaller than the -G size or if
17655 it is in the .sdata or .sbss section. Certain symbols can
17656 not be referenced off the $gp, although it appears as though
17658 symname
= S_GET_NAME (sym
);
17659 if (symname
!= (const char *) NULL
17660 && (strcmp (symname
, "eprol") == 0
17661 || strcmp (symname
, "etext") == 0
17662 || strcmp (symname
, "_gp") == 0
17663 || strcmp (symname
, "edata") == 0
17664 || strcmp (symname
, "_fbss") == 0
17665 || strcmp (symname
, "_fdata") == 0
17666 || strcmp (symname
, "_ftext") == 0
17667 || strcmp (symname
, "end") == 0
17668 || strcmp (symname
, "_gp_disp") == 0))
17670 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17672 #ifndef NO_ECOFF_DEBUGGING
17673 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17674 && (symbol_get_obj (sym
)->ecoff_extern_size
17675 <= g_switch_value
))
17677 /* We must defer this decision until after the whole
17678 file has been read, since there might be a .extern
17679 after the first use of this symbol. */
17680 || (before_relaxing
17681 #ifndef NO_ECOFF_DEBUGGING
17682 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17684 && S_GET_VALUE (sym
) == 0)
17685 || (S_GET_VALUE (sym
) != 0
17686 && S_GET_VALUE (sym
) <= g_switch_value
)))
17690 const char *segname
;
17692 segname
= segment_name (S_GET_SEGMENT (sym
));
17693 gas_assert (strcmp (segname
, ".lit8") != 0
17694 && strcmp (segname
, ".lit4") != 0);
17695 change
= (strcmp (segname
, ".sdata") != 0
17696 && strcmp (segname
, ".sbss") != 0
17697 && strncmp (segname
, ".sdata.", 7) != 0
17698 && strncmp (segname
, ".sbss.", 6) != 0
17699 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17700 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17705 /* We are not optimizing for the $gp register. */
17710 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17713 pic_need_relax (symbolS
*sym
)
17717 /* Handle the case of a symbol equated to another symbol. */
17718 while (symbol_equated_reloc_p (sym
))
17722 /* It's possible to get a loop here in a badly written program. */
17723 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17729 if (symbol_section_p (sym
))
17732 symsec
= S_GET_SEGMENT (sym
);
17734 /* This must duplicate the test in adjust_reloc_syms. */
17735 return (!bfd_is_und_section (symsec
)
17736 && !bfd_is_abs_section (symsec
)
17737 && !bfd_is_com_section (symsec
)
17738 /* A global or weak symbol is treated as external. */
17739 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17742 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17743 convert a section-relative value VAL to the equivalent PC-relative
17747 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17748 offsetT val
, long stretch
)
17753 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17755 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17757 /* If the relax_marker of the symbol fragment differs from the
17758 relax_marker of this fragment, we have not yet adjusted the
17759 symbol fragment fr_address. We want to add in STRETCH in
17760 order to get a better estimate of the address. This
17761 particularly matters because of the shift bits. */
17762 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17766 /* Adjust stretch for any alignment frag. Note that if have
17767 been expanding the earlier code, the symbol may be
17768 defined in what appears to be an earlier frag. FIXME:
17769 This doesn't handle the fr_subtype field, which specifies
17770 a maximum number of bytes to skip when doing an
17772 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17774 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17777 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17779 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17788 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17790 /* The base address rules are complicated. The base address of
17791 a branch is the following instruction. The base address of a
17792 PC relative load or add is the instruction itself, but if it
17793 is in a delay slot (in which case it can not be extended) use
17794 the address of the instruction whose delay slot it is in. */
17795 if (pcrel_op
->include_isa_bit
)
17799 /* If we are currently assuming that this frag should be
17800 extended, then the current address is two bytes higher. */
17801 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17804 /* Ignore the low bit in the target, since it will be set
17805 for a text label. */
17808 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17810 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17813 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17818 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17819 extended opcode. SEC is the section the frag is in. */
17822 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17824 const struct mips_int_operand
*operand
;
17829 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17831 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17834 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17835 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17836 operand
= mips16_immed_operand (type
, false);
17837 if (S_FORCE_RELOC (fragp
->fr_symbol
, true)
17838 || (operand
->root
.type
== OP_PCREL
17840 : !bfd_is_abs_section (symsec
)))
17843 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17845 if (operand
->root
.type
== OP_PCREL
)
17847 const struct mips_pcrel_operand
*pcrel_op
;
17850 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17853 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17854 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17856 /* If any of the shifted bits are set, we must use an extended
17857 opcode. If the address depends on the size of this
17858 instruction, this can lead to a loop, so we arrange to always
17859 use an extended opcode. */
17860 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17862 fragp
->fr_subtype
=
17863 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17867 /* If we are about to mark a frag as extended because the value
17868 is precisely the next value above maxtiny, then there is a
17869 chance of an infinite loop as in the following code:
17874 In this case when the la is extended, foo is 0x3fc bytes
17875 away, so the la can be shrunk, but then foo is 0x400 away, so
17876 the la must be extended. To avoid this loop, we mark the
17877 frag as extended if it was small, and is about to become
17878 extended with the next value above maxtiny. */
17879 maxtiny
= mips_int_operand_max (operand
);
17880 if (val
== maxtiny
+ (1 << operand
->shift
)
17881 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17883 fragp
->fr_subtype
=
17884 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17889 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17892 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17893 macro expansion. SEC is the section the frag is in. We only
17894 support PC-relative instructions (LA, DLA, LW, LD) here, in
17895 non-PIC code using 32-bit addressing. */
17898 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17900 const struct mips_pcrel_operand
*pcrel_op
;
17901 const struct mips_int_operand
*operand
;
17906 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17908 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17910 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17913 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17919 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17920 if (bfd_is_abs_section (symsec
))
17922 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17924 if (S_FORCE_RELOC (fragp
->fr_symbol
, true) || sec
!= symsec
)
17927 operand
= mips16_immed_operand (type
, true);
17928 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17929 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17930 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17932 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17939 /* Compute the length of a branch sequence, and adjust the
17940 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17941 worst-case length is computed, with UPDATE being used to indicate
17942 whether an unconditional (-1), branch-likely (+1) or regular (0)
17943 branch is to be computed. */
17945 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17951 && S_IS_DEFINED (fragp
->fr_symbol
)
17952 && !S_IS_WEAK (fragp
->fr_symbol
)
17953 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17958 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17960 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17964 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17967 /* If the symbol is not defined or it's in a different segment,
17968 we emit the long sequence. */
17971 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17973 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17974 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17975 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17976 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17977 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17983 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17986 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17988 /* Additional space for PIC loading of target address. */
17990 if (mips_opts
.isa
== ISA_MIPS1
)
17991 /* Additional space for $at-stabilizing nop. */
17995 /* If branch is conditional. */
17996 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
18003 /* Get a FRAG's branch instruction delay slot size, either from the
18004 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
18005 or SHORT_INSN_SIZE otherwise. */
18008 frag_branch_delay_slot_size (fragS
*fragp
, bool al
, int short_insn_size
)
18010 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18013 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
18015 return short_insn_size
;
18018 /* Compute the length of a branch sequence, and adjust the
18019 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
18020 worst-case length is computed, with UPDATE being used to indicate
18021 whether an unconditional (-1), or regular (0) branch is to be
18025 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18027 bool insn32
= true;
18031 int short_insn_size
;
18037 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18038 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18039 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18040 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18042 short_insn_size
= insn32
? 4 : 2;
18045 && S_IS_DEFINED (fragp
->fr_symbol
)
18046 && !S_IS_WEAK (fragp
->fr_symbol
)
18047 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18052 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18053 /* Ignore the low bit in the target, since it will be set
18054 for a text label. */
18055 if ((val
& 1) != 0)
18058 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18062 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
18065 /* If the symbol is not defined or it's in a different segment,
18066 we emit the long sequence. */
18069 if (fragp
&& update
18070 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18071 fragp
->fr_subtype
= (toofar
18072 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
18073 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
18078 bool compact_known
= fragp
!= NULL
;
18079 bool compact
= false;
18084 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18085 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
18088 uncond
= update
< 0;
18090 /* If label is out of range, we turn branch <br>:
18092 <br> label # 4 bytes
18099 # compact && (!PIC || insn32)
18102 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
18103 length
+= short_insn_size
;
18105 /* If assembling PIC code, we further turn:
18111 lw/ld at, %got(label)(gp) # 4 bytes
18112 d/addiu at, %lo(label) # 4 bytes
18113 jr/c at # 2/4 bytes
18116 length
+= 4 + short_insn_size
;
18118 /* Add an extra nop if the jump has no compact form and we need
18119 to fill the delay slot. */
18120 if ((!pic
|| al
) && nods
)
18122 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
18123 : short_insn_size
);
18125 /* If branch <br> is conditional, we prepend negated branch <brneg>:
18127 <brneg> 0f # 4 bytes
18128 nop # 2/4 bytes if !compact
18131 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
18135 /* Add an extra nop to fill the delay slot. */
18136 gas_assert (fragp
);
18137 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
18143 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
18144 bit accordingly. */
18147 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18152 && S_IS_DEFINED (fragp
->fr_symbol
)
18153 && !S_IS_WEAK (fragp
->fr_symbol
)
18154 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18160 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18161 /* Ignore the low bit in the target, since it will be set
18162 for a text label. */
18163 if ((val
& 1) != 0)
18166 /* Assume this is a 2-byte branch. */
18167 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
18169 /* We try to avoid the infinite loop by not adding 2 more bytes for
18174 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18176 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
18177 else if (type
== 'E')
18178 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
18183 /* If the symbol is not defined or it's in a different segment,
18184 we emit a normal 32-bit branch. */
18187 if (fragp
&& update
18188 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18190 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
18191 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
18199 /* Estimate the size of a frag before relaxing. Unless this is the
18200 mips16, we are not really relaxing here, and the final size is
18201 encoded in the subtype information. For the mips16, we have to
18202 decide whether we are using an extended opcode or not. */
18205 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
18209 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18212 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, false);
18214 return fragp
->fr_var
;
18217 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18219 /* We don't want to modify the EXTENDED bit here; it might get us
18220 into infinite loops. We change it only in mips_relax_frag(). */
18221 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18222 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
18224 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
18227 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18231 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18232 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, false);
18233 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18234 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, false);
18235 fragp
->fr_var
= length
;
18240 if (mips_pic
== VXWORKS_PIC
)
18241 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
18243 else if (RELAX_PIC (fragp
->fr_subtype
))
18244 change
= pic_need_relax (fragp
->fr_symbol
);
18246 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
18250 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
18251 return -RELAX_FIRST (fragp
->fr_subtype
);
18254 return -RELAX_SECOND (fragp
->fr_subtype
);
18257 /* This is called to see whether a reloc against a defined symbol
18258 should be converted into a reloc against a section. */
18261 mips_fix_adjustable (fixS
*fixp
)
18263 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18264 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18267 if (fixp
->fx_addsy
== NULL
)
18270 /* Allow relocs used for EH tables. */
18271 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
18274 /* If symbol SYM is in a mergeable section, relocations of the form
18275 SYM + 0 can usually be made section-relative. The mergeable data
18276 is then identified by the section offset rather than by the symbol.
18278 However, if we're generating REL LO16 relocations, the offset is split
18279 between the LO16 and partnering high part relocation. The linker will
18280 need to recalculate the complete offset in order to correctly identify
18283 The linker has traditionally not looked for the partnering high part
18284 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18285 placed anywhere. Rather than break backwards compatibility by changing
18286 this, it seems better not to force the issue, and instead keep the
18287 original symbol. This will work with either linker behavior. */
18288 if ((lo16_reloc_p (fixp
->fx_r_type
)
18289 || reloc_needs_lo_p (fixp
->fx_r_type
))
18290 && HAVE_IN_PLACE_ADDENDS
18291 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
18294 /* There is no place to store an in-place offset for JALR relocations. */
18295 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
18298 /* Likewise an in-range offset of limited PC-relative relocations may
18299 overflow the in-place relocatable field if recalculated against the
18300 start address of the symbol's containing section.
18302 Also, PC relative relocations for MIPS R6 need to be symbol rather than
18303 section relative to allow linker relaxations to be performed later on. */
18304 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
18305 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
18308 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18309 to a floating-point stub. The same is true for non-R_MIPS16_26
18310 relocations against MIPS16 functions; in this case, the stub becomes
18311 the function's canonical address.
18313 Floating-point stubs are stored in unique .mips16.call.* or
18314 .mips16.fn.* sections. If a stub T for function F is in section S,
18315 the first relocation in section S must be against F; this is how the
18316 linker determines the target function. All relocations that might
18317 resolve to T must also be against F. We therefore have the following
18318 restrictions, which are given in an intentionally-redundant way:
18320 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18323 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18324 if that stub might be used.
18326 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18329 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18330 that stub might be used.
18332 There is a further restriction:
18334 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18335 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18336 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18337 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18338 against MIPS16 or microMIPS symbols because we need to keep the
18339 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18340 detection and JAL or BAL to JALX instruction conversion in the
18343 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18344 against a MIPS16 symbol. We deal with (5) by additionally leaving
18345 alone any jump and branch relocations against a microMIPS symbol.
18347 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18348 relocation against some symbol R, no relocation against R may be
18349 reduced. (Note that this deals with (2) as well as (1) because
18350 relocations against global symbols will never be reduced on ELF
18351 targets.) This approach is a little simpler than trying to detect
18352 stub sections, and gives the "all or nothing" per-symbol consistency
18353 that we have for MIPS16 symbols. */
18354 if (fixp
->fx_subsy
== NULL
18355 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18356 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18357 && (jmp_reloc_p (fixp
->fx_r_type
)
18358 || b_reloc_p (fixp
->fx_r_type
)))
18359 || *symbol_get_tc (fixp
->fx_addsy
)))
18365 /* Translate internal representation of relocation info to BFD target
18369 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18371 static arelent
*retval
[4];
18373 bfd_reloc_code_real_type code
;
18375 memset (retval
, 0, sizeof(retval
));
18376 reloc
= retval
[0] = XCNEW (arelent
);
18377 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
18378 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18379 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18381 if (fixp
->fx_pcrel
)
18383 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18384 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18385 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18386 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18387 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18388 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18389 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18390 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18391 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18392 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18393 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18394 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18396 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18397 Relocations want only the symbol offset. */
18398 switch (fixp
->fx_r_type
)
18400 case BFD_RELOC_MIPS_18_PCREL_S3
:
18401 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18404 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18408 else if (HAVE_IN_PLACE_ADDENDS
18409 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18410 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18411 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18413 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18414 addend accordingly. */
18415 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18418 reloc
->addend
= fixp
->fx_addnumber
;
18420 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18421 entry to be used in the relocation's section offset. */
18422 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18424 reloc
->address
= reloc
->addend
;
18428 code
= fixp
->fx_r_type
;
18430 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18431 if (reloc
->howto
== NULL
)
18433 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18434 _("cannot represent %s relocation in this object file"
18436 bfd_get_reloc_code_name (code
));
18443 /* Relax a machine dependent frag. This returns the amount by which
18444 the current size of the frag should change. */
18447 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18449 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18451 offsetT old_var
= fragp
->fr_var
;
18453 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, true);
18455 return fragp
->fr_var
- old_var
;
18458 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18460 offsetT old_var
= fragp
->fr_var
;
18461 offsetT new_var
= 4;
18463 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18464 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, true);
18465 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18466 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, true);
18467 fragp
->fr_var
= new_var
;
18469 return new_var
- old_var
;
18472 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18475 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18477 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18479 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18480 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18482 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18484 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18490 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18492 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18494 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18495 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18496 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18498 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18500 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18508 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18510 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18512 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18513 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18514 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18518 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18519 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18526 /* Convert a machine dependent frag. */
18529 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18531 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18534 unsigned long insn
;
18537 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18538 insn
= read_insn (buf
);
18540 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18542 /* We generate a fixup instead of applying it right now
18543 because, if there are linker relaxations, we're going to
18544 need the relocations. */
18545 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18546 fragp
->fr_symbol
, fragp
->fr_offset
,
18547 true, BFD_RELOC_16_PCREL_S2
);
18548 fixp
->fx_file
= fragp
->fr_file
;
18549 fixp
->fx_line
= fragp
->fr_line
;
18551 buf
= write_insn (buf
, insn
);
18557 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18558 _("relaxed out-of-range branch into a jump"));
18560 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18563 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18565 /* Reverse the branch. */
18566 switch ((insn
>> 28) & 0xf)
18569 if ((insn
& 0xff000000) == 0x47000000
18570 || (insn
& 0xff600000) == 0x45600000)
18572 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18573 reversed by tweaking bit 23. */
18574 insn
^= 0x00800000;
18578 /* bc[0-3][tf]l? instructions can have the condition
18579 reversed by tweaking a single TF bit, and their
18580 opcodes all have 0x4???????. */
18581 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18582 insn
^= 0x00010000;
18587 /* bltz 0x04000000 bgez 0x04010000
18588 bltzal 0x04100000 bgezal 0x04110000 */
18589 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18590 insn
^= 0x00010000;
18594 /* beq 0x10000000 bne 0x14000000
18595 blez 0x18000000 bgtz 0x1c000000 */
18596 insn
^= 0x04000000;
18604 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18606 /* Clear the and-link bit. */
18607 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18609 /* bltzal 0x04100000 bgezal 0x04110000
18610 bltzall 0x04120000 bgezall 0x04130000 */
18611 insn
&= ~0x00100000;
18614 /* Branch over the branch (if the branch was likely) or the
18615 full jump (not likely case). Compute the offset from the
18616 current instruction to branch to. */
18617 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18621 /* How many bytes in instructions we've already emitted? */
18622 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18623 /* How many bytes in instructions from here to the end? */
18624 i
= fragp
->fr_var
- i
;
18626 /* Convert to instruction count. */
18628 /* Branch counts from the next instruction. */
18631 /* Branch over the jump. */
18632 buf
= write_insn (buf
, insn
);
18635 buf
= write_insn (buf
, 0);
18637 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18639 /* beql $0, $0, 2f */
18641 /* Compute the PC offset from the current instruction to
18642 the end of the variable frag. */
18643 /* How many bytes in instructions we've already emitted? */
18644 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18645 /* How many bytes in instructions from here to the end? */
18646 i
= fragp
->fr_var
- i
;
18647 /* Convert to instruction count. */
18649 /* Don't decrement i, because we want to branch over the
18653 buf
= write_insn (buf
, insn
);
18654 buf
= write_insn (buf
, 0);
18658 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18661 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18662 ? 0x0c000000 : 0x08000000);
18664 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18665 fragp
->fr_symbol
, fragp
->fr_offset
,
18666 false, BFD_RELOC_MIPS_JMP
);
18667 fixp
->fx_file
= fragp
->fr_file
;
18668 fixp
->fx_line
= fragp
->fr_line
;
18670 buf
= write_insn (buf
, insn
);
18674 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18676 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18677 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18678 insn
|= at
<< OP_SH_RT
;
18680 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18681 fragp
->fr_symbol
, fragp
->fr_offset
,
18682 false, BFD_RELOC_MIPS_GOT16
);
18683 fixp
->fx_file
= fragp
->fr_file
;
18684 fixp
->fx_line
= fragp
->fr_line
;
18686 buf
= write_insn (buf
, insn
);
18688 if (mips_opts
.isa
== ISA_MIPS1
)
18690 buf
= write_insn (buf
, 0);
18692 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18693 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18694 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18696 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18697 fragp
->fr_symbol
, fragp
->fr_offset
,
18698 false, BFD_RELOC_LO16
);
18699 fixp
->fx_file
= fragp
->fr_file
;
18700 fixp
->fx_line
= fragp
->fr_line
;
18702 buf
= write_insn (buf
, insn
);
18705 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18709 insn
|= at
<< OP_SH_RS
;
18711 buf
= write_insn (buf
, insn
);
18715 fragp
->fr_fix
+= fragp
->fr_var
;
18716 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18720 /* Relax microMIPS branches. */
18721 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18723 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18724 bool compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18725 bool insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18726 bool nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18727 bool pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18728 bool al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18729 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18731 unsigned long insn
;
18734 fragp
->fr_fix
+= fragp
->fr_var
;
18736 /* Handle 16-bit branches that fit or are forced to fit. */
18737 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18739 /* We generate a fixup instead of applying it right now,
18740 because if there is linker relaxation, we're going to
18741 need the relocations. */
18745 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18746 fragp
->fr_symbol
, fragp
->fr_offset
,
18747 true, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18750 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18751 fragp
->fr_symbol
, fragp
->fr_offset
,
18752 true, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18758 fixp
->fx_file
= fragp
->fr_file
;
18759 fixp
->fx_line
= fragp
->fr_line
;
18761 /* These relocations can have an addend that won't fit in
18763 fixp
->fx_no_overflow
= 1;
18768 /* Handle 32-bit branches that fit or are forced to fit. */
18769 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18770 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18772 /* We generate a fixup instead of applying it right now,
18773 because if there is linker relaxation, we're going to
18774 need the relocations. */
18775 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18776 fragp
->fr_symbol
, fragp
->fr_offset
,
18777 true, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18778 fixp
->fx_file
= fragp
->fr_file
;
18779 fixp
->fx_line
= fragp
->fr_line
;
18783 insn
= read_compressed_insn (buf
, 4);
18788 /* Check the short-delay-slot bit. */
18789 if (!al
|| (insn
& 0x02000000) != 0)
18790 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18792 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18795 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18800 /* Relax 16-bit branches to 32-bit branches. */
18803 insn
= read_compressed_insn (buf
, 2);
18805 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18806 insn
= 0x94000000; /* beq */
18807 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18809 unsigned long regno
;
18811 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18812 regno
= micromips_to_32_reg_d_map
[regno
];
18813 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18814 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18819 /* Nothing else to do, just write it out. */
18820 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18821 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18823 buf
= write_compressed_insn (buf
, insn
, 4);
18825 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18826 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18831 insn
= read_compressed_insn (buf
, 4);
18833 /* Relax 32-bit branches to a sequence of instructions. */
18834 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18835 _("relaxed out-of-range branch into a jump"));
18837 /* Set the short-delay-slot bit. */
18838 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18840 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18844 /* Reverse the branch. */
18845 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18846 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18847 insn
^= 0x20000000;
18848 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18849 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18850 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18851 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18852 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18853 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18854 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18855 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18856 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18857 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18858 insn
^= 0x00400000;
18859 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18860 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18861 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18862 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18863 insn
^= 0x00200000;
18864 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18866 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18868 insn
^= 0x00800000;
18874 /* Clear the and-link and short-delay-slot bits. */
18875 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18877 /* bltzal 0x40200000 bgezal 0x40600000 */
18878 /* bltzals 0x42200000 bgezals 0x42600000 */
18879 insn
&= ~0x02200000;
18882 /* Make a label at the end for use with the branch. */
18883 l
= symbol_new (micromips_label_name (), asec
, fragp
, fragp
->fr_fix
);
18884 micromips_label_inc ();
18885 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18888 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, true,
18889 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18890 fixp
->fx_file
= fragp
->fr_file
;
18891 fixp
->fx_line
= fragp
->fr_line
;
18893 /* Branch over the jump. */
18894 buf
= write_compressed_insn (buf
, insn
, 4);
18900 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18902 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18908 unsigned long jal
= (short_ds
|| nods
18909 ? 0x74000000 : 0xf4000000); /* jal/s */
18911 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18912 insn
= al
? jal
: 0xd4000000;
18914 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18915 fragp
->fr_symbol
, fragp
->fr_offset
,
18916 false, BFD_RELOC_MICROMIPS_JMP
);
18917 fixp
->fx_file
= fragp
->fr_file
;
18918 fixp
->fx_line
= fragp
->fr_line
;
18920 buf
= write_compressed_insn (buf
, insn
, 4);
18922 if (compact
|| nods
)
18926 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18928 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18933 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18935 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18936 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18937 insn
|= at
<< MICROMIPSOP_SH_RT
;
18939 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18940 fragp
->fr_symbol
, fragp
->fr_offset
,
18941 false, BFD_RELOC_MICROMIPS_GOT16
);
18942 fixp
->fx_file
= fragp
->fr_file
;
18943 fixp
->fx_line
= fragp
->fr_line
;
18945 buf
= write_compressed_insn (buf
, insn
, 4);
18947 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18948 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18949 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18951 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18952 fragp
->fr_symbol
, fragp
->fr_offset
,
18953 false, BFD_RELOC_MICROMIPS_LO16
);
18954 fixp
->fx_file
= fragp
->fr_file
;
18955 fixp
->fx_line
= fragp
->fr_line
;
18957 buf
= write_compressed_insn (buf
, insn
, 4);
18962 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18963 insn
|= at
<< MICROMIPSOP_SH_RS
;
18965 buf
= write_compressed_insn (buf
, insn
, 4);
18967 if (compact
|| nods
)
18969 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18973 /* jr/jrc/jalr/jalrs $at */
18974 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18975 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18977 insn
= al
? jalr
: jr
;
18978 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18980 buf
= write_compressed_insn (buf
, insn
, 2);
18985 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18987 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18992 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18996 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18999 const struct mips_int_operand
*operand
;
19002 unsigned int user_length
;
19004 unsigned long insn
;
19009 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
19010 operand
= mips16_immed_operand (type
, false);
19012 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
19013 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
19014 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
19016 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
19017 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, true)
19018 || (operand
->root
.type
== OP_PCREL
&& !mac
19020 : !bfd_is_abs_section (symsec
)));
19022 if (operand
->root
.type
== OP_PCREL
&& !mac
)
19024 const struct mips_pcrel_operand
*pcrel_op
;
19026 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
19028 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
19030 if (!mips_ignore_branch_isa
19031 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
19032 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19033 _("branch to a symbol in another ISA mode"));
19034 else if ((fragp
->fr_offset
& 0x1) != 0)
19035 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19036 _("branch to misaligned address (0x%lx)"),
19037 (long) (resolve_symbol_value (fragp
->fr_symbol
)
19038 + (fragp
->fr_offset
& ~1)));
19041 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
19043 /* Make sure the section winds up with the alignment we have
19045 if (operand
->shift
> 0)
19046 record_alignment (asec
, operand
->shift
);
19049 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
19050 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
19053 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19054 _("macro instruction expanded into multiple "
19055 "instructions in a branch delay slot"));
19057 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19058 _("extended instruction in a branch delay slot"));
19060 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
19061 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19062 _("macro instruction expanded into multiple "
19065 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19067 insn
= read_compressed_insn (buf
, 2);
19069 insn
|= MIPS16_EXTEND
;
19071 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
19073 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
19085 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
19086 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
19088 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
19094 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
19096 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19097 fragp
->fr_symbol
, fragp
->fr_offset
,
19098 false, BFD_RELOC_MIPS16_HI16_S
);
19099 fixp
->fx_file
= fragp
->fr_file
;
19100 fixp
->fx_line
= fragp
->fr_line
;
19102 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
19103 fragp
->fr_symbol
, fragp
->fr_offset
,
19104 false, BFD_RELOC_MIPS16_LO16
);
19105 fixp
->fx_file
= fragp
->fr_file
;
19106 fixp
->fx_line
= fragp
->fr_line
;
19111 switch (insn
& 0xf800)
19113 case 0x0800: /* ADDIU */
19114 reg
= (insn
>> 8) & 0x7;
19115 op
= 0xf0004800 | (reg
<< 8);
19117 case 0xb000: /* LW */
19118 reg
= (insn
>> 8) & 0x7;
19119 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
19121 case 0xf800: /* I64 */
19122 reg
= (insn
>> 5) & 0x7;
19123 switch (insn
& 0x0700)
19125 case 0x0400: /* LD */
19126 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
19128 case 0x0600: /* DADDIU */
19129 op
= 0xf000fd00 | (reg
<< 5);
19139 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
19140 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
19141 buf
= write_compressed_insn (buf
, new, 4);
19144 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
19145 buf
= write_compressed_insn (buf
, new, 4);
19147 op
|= mips16_immed_extend (val
, 16);
19148 buf
= write_compressed_insn (buf
, op
, 4);
19150 fragp
->fr_fix
+= e2
? 8 : 12;
19154 unsigned int length
= ext
? 4 : 2;
19158 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
19165 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
19170 if (mac
|| reloc
== BFD_RELOC_NONE
)
19171 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19172 _("unsupported relocation"));
19175 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19176 fragp
->fr_symbol
, fragp
->fr_offset
,
19178 fixp
->fx_file
= fragp
->fr_file
;
19179 fixp
->fx_line
= fragp
->fr_line
;
19182 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19183 _("invalid unextended operand value"));
19186 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
19187 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
19189 gas_assert (mips16_opcode_length (insn
) == length
);
19190 write_compressed_insn (buf
, insn
, length
);
19191 fragp
->fr_fix
+= length
;
19196 relax_substateT subtype
= fragp
->fr_subtype
;
19197 bool second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
19198 bool use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
19199 unsigned int first
, second
;
19202 first
= RELAX_FIRST (subtype
);
19203 second
= RELAX_SECOND (subtype
);
19204 fixp
= (fixS
*) fragp
->fr_opcode
;
19206 /* If the delay slot chosen does not match the size of the instruction,
19207 then emit a warning. */
19208 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
19209 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
19214 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
19215 | RELAX_DELAY_SLOT_SIZE_FIRST
19216 | RELAX_DELAY_SLOT_SIZE_SECOND
);
19217 msg
= macro_warning (s
);
19219 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19223 /* Possibly emit a warning if we've chosen the longer option. */
19224 if (use_second
== second_longer
)
19230 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
19231 msg
= macro_warning (s
);
19233 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19237 /* Go through all the fixups for the first sequence. Disable them
19238 (by marking them as done) if we're going to use the second
19239 sequence instead. */
19241 && fixp
->fx_frag
== fragp
19242 && fixp
->fx_where
+ second
< fragp
->fr_fix
)
19244 if (subtype
& RELAX_USE_SECOND
)
19246 fixp
= fixp
->fx_next
;
19249 /* Go through the fixups for the second sequence. Disable them if
19250 we're going to use the first sequence, otherwise adjust their
19251 addresses to account for the relaxation. */
19252 while (fixp
&& fixp
->fx_frag
== fragp
)
19254 if (subtype
& RELAX_USE_SECOND
)
19255 fixp
->fx_where
-= first
;
19258 fixp
= fixp
->fx_next
;
19261 /* Now modify the frag contents. */
19262 if (subtype
& RELAX_USE_SECOND
)
19266 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
19267 memmove (start
, start
+ first
, second
);
19268 fragp
->fr_fix
-= first
;
19271 fragp
->fr_fix
-= second
;
19275 /* This function is called after the relocs have been generated.
19276 We've been storing mips16 text labels as odd. Here we convert them
19277 back to even for the convenience of the debugger. */
19280 mips_frob_file_after_relocs (void)
19283 unsigned int count
, i
;
19285 syms
= bfd_get_outsymbols (stdoutput
);
19286 count
= bfd_get_symcount (stdoutput
);
19287 for (i
= 0; i
< count
; i
++, syms
++)
19288 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
19289 && ((*syms
)->value
& 1) != 0)
19291 (*syms
)->value
&= ~1;
19292 /* If the symbol has an odd size, it was probably computed
19293 incorrectly, so adjust that as well. */
19294 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
19295 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
19299 /* This function is called whenever a label is defined, including fake
19300 labels instantiated off the dot special symbol. It is used when
19301 handling branch delays; if a branch has a label, we assume we cannot
19302 move it. This also bumps the value of the symbol by 1 in compressed
19306 mips_record_label (symbolS
*sym
)
19308 segment_info_type
*si
= seg_info (now_seg
);
19309 struct insn_label_list
*l
;
19311 if (free_insn_labels
== NULL
)
19312 l
= XNEW (struct insn_label_list
);
19315 l
= free_insn_labels
;
19316 free_insn_labels
= l
->next
;
19320 l
->next
= si
->label_list
;
19321 si
->label_list
= l
;
19324 /* This function is called as tc_frob_label() whenever a label is defined
19325 and adds a DWARF-2 record we only want for true labels. */
19328 mips_define_label (symbolS
*sym
)
19330 mips_record_label (sym
);
19331 dwarf2_emit_label (sym
);
19334 /* This function is called by tc_new_dot_label whenever a new dot symbol
19338 mips_add_dot_label (symbolS
*sym
)
19340 mips_record_label (sym
);
19341 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
19342 mips_compressed_mark_label (sym
);
19345 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19346 static unsigned int
19347 mips_convert_ase_flags (int ase
)
19349 unsigned int ext_ases
= 0;
19352 ext_ases
|= AFL_ASE_DSP
;
19353 if (ase
& ASE_DSPR2
)
19354 ext_ases
|= AFL_ASE_DSPR2
;
19355 if (ase
& ASE_DSPR3
)
19356 ext_ases
|= AFL_ASE_DSPR3
;
19358 ext_ases
|= AFL_ASE_EVA
;
19360 ext_ases
|= AFL_ASE_MCU
;
19361 if (ase
& ASE_MDMX
)
19362 ext_ases
|= AFL_ASE_MDMX
;
19363 if (ase
& ASE_MIPS3D
)
19364 ext_ases
|= AFL_ASE_MIPS3D
;
19366 ext_ases
|= AFL_ASE_MT
;
19367 if (ase
& ASE_SMARTMIPS
)
19368 ext_ases
|= AFL_ASE_SMARTMIPS
;
19369 if (ase
& ASE_VIRT
)
19370 ext_ases
|= AFL_ASE_VIRT
;
19372 ext_ases
|= AFL_ASE_MSA
;
19374 ext_ases
|= AFL_ASE_XPA
;
19375 if (ase
& ASE_MIPS16E2
)
19376 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
19378 ext_ases
|= AFL_ASE_CRC
;
19379 if (ase
& ASE_GINV
)
19380 ext_ases
|= AFL_ASE_GINV
;
19381 if (ase
& ASE_LOONGSON_MMI
)
19382 ext_ases
|= AFL_ASE_LOONGSON_MMI
;
19383 if (ase
& ASE_LOONGSON_CAM
)
19384 ext_ases
|= AFL_ASE_LOONGSON_CAM
;
19385 if (ase
& ASE_LOONGSON_EXT
)
19386 ext_ases
|= AFL_ASE_LOONGSON_EXT
;
19387 if (ase
& ASE_LOONGSON_EXT2
)
19388 ext_ases
|= AFL_ASE_LOONGSON_EXT2
;
19392 /* Some special processing for a MIPS ELF file. */
19395 mips_elf_final_processing (void)
19398 Elf_Internal_ABIFlags_v0 flags
;
19402 switch (file_mips_opts
.isa
)
19405 flags
.isa_level
= 1;
19408 flags
.isa_level
= 2;
19411 flags
.isa_level
= 3;
19414 flags
.isa_level
= 4;
19417 flags
.isa_level
= 5;
19420 flags
.isa_level
= 32;
19424 flags
.isa_level
= 32;
19428 flags
.isa_level
= 32;
19432 flags
.isa_level
= 32;
19436 flags
.isa_level
= 32;
19440 flags
.isa_level
= 64;
19444 flags
.isa_level
= 64;
19448 flags
.isa_level
= 64;
19452 flags
.isa_level
= 64;
19456 flags
.isa_level
= 64;
19461 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19462 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19463 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19464 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19466 flags
.cpr2_size
= AFL_REG_NONE
;
19467 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19468 Tag_GNU_MIPS_ABI_FP
);
19469 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19470 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19471 if (file_ase_mips16
)
19472 flags
.ases
|= AFL_ASE_MIPS16
;
19473 if (file_ase_micromips
)
19474 flags
.ases
|= AFL_ASE_MICROMIPS
;
19476 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19477 || file_mips_opts
.fp
== 64)
19478 && file_mips_opts
.oddspreg
)
19479 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19482 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19483 ((Elf_External_ABIFlags_v0
*)
19486 /* Write out the register information. */
19487 if (mips_abi
!= N64_ABI
)
19491 s
.ri_gprmask
= mips_gprmask
;
19492 s
.ri_cprmask
[0] = mips_cprmask
[0];
19493 s
.ri_cprmask
[1] = mips_cprmask
[1];
19494 s
.ri_cprmask
[2] = mips_cprmask
[2];
19495 s
.ri_cprmask
[3] = mips_cprmask
[3];
19496 /* The gp_value field is set by the MIPS ELF backend. */
19498 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19499 ((Elf32_External_RegInfo
*)
19500 mips_regmask_frag
));
19504 Elf64_Internal_RegInfo s
;
19506 s
.ri_gprmask
= mips_gprmask
;
19508 s
.ri_cprmask
[0] = mips_cprmask
[0];
19509 s
.ri_cprmask
[1] = mips_cprmask
[1];
19510 s
.ri_cprmask
[2] = mips_cprmask
[2];
19511 s
.ri_cprmask
[3] = mips_cprmask
[3];
19512 /* The gp_value field is set by the MIPS ELF backend. */
19514 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19515 ((Elf64_External_RegInfo
*)
19516 mips_regmask_frag
));
19519 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19520 sort of BFD interface for this. */
19521 if (mips_any_noreorder
)
19522 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19523 if (mips_pic
!= NO_PIC
)
19525 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19526 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19529 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19531 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19532 defined at present; this might need to change in future. */
19533 if (file_ase_mips16
)
19534 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19535 if (file_ase_micromips
)
19536 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19537 if (file_mips_opts
.ase
& ASE_MDMX
)
19538 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19540 /* Set the MIPS ELF ABI flags. */
19541 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19542 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19543 else if (mips_abi
== O64_ABI
)
19544 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19545 else if (mips_abi
== EABI_ABI
)
19547 if (file_mips_opts
.gp
== 64)
19548 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19550 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19553 /* Nothing to do for N32_ABI or N64_ABI. */
19555 if (mips_32bitmode
)
19556 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19558 if (mips_nan2008
== 1)
19559 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19561 /* 32 bit code with 64 bit FP registers. */
19562 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19563 Tag_GNU_MIPS_ABI_FP
);
19564 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19565 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19568 typedef struct proc
{
19570 symbolS
*func_end_sym
;
19571 unsigned long reg_mask
;
19572 unsigned long reg_offset
;
19573 unsigned long fpreg_mask
;
19574 unsigned long fpreg_offset
;
19575 unsigned long frame_offset
;
19576 unsigned long frame_reg
;
19577 unsigned long pc_reg
;
19580 static procS cur_proc
;
19581 static procS
*cur_proc_ptr
;
19582 static int numprocs
;
19584 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19585 as "2", and a normal nop as "0". */
19587 #define NOP_OPCODE_MIPS 0
19588 #define NOP_OPCODE_MIPS16 1
19589 #define NOP_OPCODE_MICROMIPS 2
19592 mips_nop_opcode (void)
19594 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19595 return NOP_OPCODE_MICROMIPS
;
19596 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19597 return NOP_OPCODE_MIPS16
;
19599 return NOP_OPCODE_MIPS
;
19602 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19603 32-bit microMIPS NOPs here (if applicable). */
19606 mips_handle_align (fragS
*fragp
)
19610 int bytes
, size
, excess
;
19613 if (fragp
->fr_type
!= rs_align_code
)
19616 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19618 switch (nop_opcode
)
19620 case NOP_OPCODE_MICROMIPS
:
19621 opcode
= micromips_nop32_insn
.insn_opcode
;
19624 case NOP_OPCODE_MIPS16
:
19625 opcode
= mips16_nop_insn
.insn_opcode
;
19628 case NOP_OPCODE_MIPS
:
19630 opcode
= nop_insn
.insn_opcode
;
19635 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19636 excess
= bytes
% size
;
19638 /* Handle the leading part if we're not inserting a whole number of
19639 instructions, and make it the end of the fixed part of the frag.
19640 Try to fit in a short microMIPS NOP if applicable and possible,
19641 and use zeroes otherwise. */
19642 gas_assert (excess
< 4);
19643 fragp
->fr_fix
+= excess
;
19648 /* Fall through. */
19650 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19652 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19656 /* Fall through. */
19659 /* Fall through. */
19664 md_number_to_chars (p
, opcode
, size
);
19665 fragp
->fr_var
= size
;
19674 if (*input_line_pointer
== '-')
19676 ++input_line_pointer
;
19679 if (!ISDIGIT (*input_line_pointer
))
19680 as_bad (_("expected simple number"));
19681 if (input_line_pointer
[0] == '0')
19683 if (input_line_pointer
[1] == 'x')
19685 input_line_pointer
+= 2;
19686 while (ISXDIGIT (*input_line_pointer
))
19689 val
|= hex_value (*input_line_pointer
++);
19691 return negative
? -val
: val
;
19695 ++input_line_pointer
;
19696 while (ISDIGIT (*input_line_pointer
))
19699 val
|= *input_line_pointer
++ - '0';
19701 return negative
? -val
: val
;
19704 if (!ISDIGIT (*input_line_pointer
))
19706 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19707 *input_line_pointer
, *input_line_pointer
);
19708 as_warn (_("invalid number"));
19711 while (ISDIGIT (*input_line_pointer
))
19714 val
+= *input_line_pointer
++ - '0';
19716 return negative
? -val
: val
;
19719 /* The .file directive; just like the usual .file directive, but there
19720 is an initial number which is the ECOFF file index. In the non-ECOFF
19721 case .file implies DWARF-2. */
19724 s_mips_file (int x ATTRIBUTE_UNUSED
)
19726 static int first_file_directive
= 0;
19728 if (ECOFF_DEBUGGING
)
19737 filename
= dwarf2_directive_filename ();
19739 /* Versions of GCC up to 3.1 start files with a ".file"
19740 directive even for stabs output. Make sure that this
19741 ".file" is handled. Note that you need a version of GCC
19742 after 3.1 in order to support DWARF-2 on MIPS. */
19743 if (filename
!= NULL
&& ! first_file_directive
)
19745 (void) new_logical_line (filename
, -1);
19746 s_app_file_string (filename
, 0);
19748 first_file_directive
= 1;
19752 /* The .loc directive, implying DWARF-2. */
19755 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19757 if (!ECOFF_DEBUGGING
)
19758 dwarf2_directive_loc (0);
19761 /* The .end directive. */
19764 s_mips_end (int x ATTRIBUTE_UNUSED
)
19768 /* Following functions need their own .frame and .cprestore directives. */
19769 mips_frame_reg_valid
= 0;
19770 mips_cprestore_valid
= 0;
19772 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19775 demand_empty_rest_of_line ();
19780 if ((bfd_section_flags (now_seg
) & SEC_CODE
) == 0)
19781 as_warn (_(".end not in text section"));
19785 as_warn (_(".end directive without a preceding .ent directive"));
19786 demand_empty_rest_of_line ();
19792 gas_assert (S_GET_NAME (p
));
19793 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19794 as_warn (_(".end symbol does not match .ent symbol"));
19796 if (debug_type
== DEBUG_STABS
)
19797 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19801 as_warn (_(".end directive missing or unknown symbol"));
19803 /* Create an expression to calculate the size of the function. */
19804 if (p
&& cur_proc_ptr
)
19806 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19807 expressionS
*exp
= XNEW (expressionS
);
19810 exp
->X_op
= O_subtract
;
19811 exp
->X_add_symbol
= symbol_temp_new_now ();
19812 exp
->X_op_symbol
= p
;
19813 exp
->X_add_number
= 0;
19815 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19818 #ifdef md_flush_pending_output
19819 md_flush_pending_output ();
19822 /* Generate a .pdr section. */
19823 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19825 segT saved_seg
= now_seg
;
19826 subsegT saved_subseg
= now_subseg
;
19830 gas_assert (pdr_seg
);
19831 subseg_set (pdr_seg
, 0);
19833 /* Write the symbol. */
19834 exp
.X_op
= O_symbol
;
19835 exp
.X_add_symbol
= p
;
19836 exp
.X_add_number
= 0;
19837 emit_expr (&exp
, 4);
19839 fragp
= frag_more (7 * 4);
19841 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19842 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19843 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19844 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19845 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19846 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19847 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19849 subseg_set (saved_seg
, saved_subseg
);
19852 cur_proc_ptr
= NULL
;
19855 /* The .aent and .ent directives. */
19858 s_mips_ent (int aent
)
19862 symbolP
= get_symbol ();
19863 if (*input_line_pointer
== ',')
19864 ++input_line_pointer
;
19865 SKIP_WHITESPACE ();
19866 if (ISDIGIT (*input_line_pointer
)
19867 || *input_line_pointer
== '-')
19870 if ((bfd_section_flags (now_seg
) & SEC_CODE
) == 0)
19871 as_warn (_(".ent or .aent not in text section"));
19873 if (!aent
&& cur_proc_ptr
)
19874 as_warn (_("missing .end"));
19878 /* This function needs its own .frame and .cprestore directives. */
19879 mips_frame_reg_valid
= 0;
19880 mips_cprestore_valid
= 0;
19882 cur_proc_ptr
= &cur_proc
;
19883 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19885 cur_proc_ptr
->func_sym
= symbolP
;
19889 if (debug_type
== DEBUG_STABS
)
19890 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19891 S_GET_NAME (symbolP
));
19894 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19896 demand_empty_rest_of_line ();
19899 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19900 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19901 s_mips_frame is used so that we can set the PDR information correctly.
19902 We can't use the ecoff routines because they make reference to the ecoff
19903 symbol table (in the mdebug section). */
19906 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19908 if (ECOFF_DEBUGGING
)
19914 if (cur_proc_ptr
== (procS
*) NULL
)
19916 as_warn (_(".frame outside of .ent"));
19917 demand_empty_rest_of_line ();
19921 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19923 SKIP_WHITESPACE ();
19924 if (*input_line_pointer
++ != ','
19925 || get_absolute_expression_and_terminator (&val
) != ',')
19927 as_warn (_("bad .frame directive"));
19928 --input_line_pointer
;
19929 demand_empty_rest_of_line ();
19933 cur_proc_ptr
->frame_offset
= val
;
19934 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19936 demand_empty_rest_of_line ();
19940 /* The .fmask and .mask directives. If the mdebug section is present
19941 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19942 embedded targets, s_mips_mask is used so that we can set the PDR
19943 information correctly. We can't use the ecoff routines because they
19944 make reference to the ecoff symbol table (in the mdebug section). */
19947 s_mips_mask (int reg_type
)
19949 if (ECOFF_DEBUGGING
)
19950 s_ignore (reg_type
);
19955 if (cur_proc_ptr
== (procS
*) NULL
)
19957 as_warn (_(".mask/.fmask outside of .ent"));
19958 demand_empty_rest_of_line ();
19962 if (get_absolute_expression_and_terminator (&mask
) != ',')
19964 as_warn (_("bad .mask/.fmask directive"));
19965 --input_line_pointer
;
19966 demand_empty_rest_of_line ();
19970 off
= get_absolute_expression ();
19972 if (reg_type
== 'F')
19974 cur_proc_ptr
->fpreg_mask
= mask
;
19975 cur_proc_ptr
->fpreg_offset
= off
;
19979 cur_proc_ptr
->reg_mask
= mask
;
19980 cur_proc_ptr
->reg_offset
= off
;
19983 demand_empty_rest_of_line ();
19987 /* A table describing all the processors gas knows about. Names are
19988 matched in the order listed.
19990 To ease comparison, please keep this table in the same order as
19991 gcc's mips_cpu_info_table[]. */
19992 static const struct mips_cpu_info mips_cpu_info_table
[] =
19994 /* Entries for generic ISAs. */
19995 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19996 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19997 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19998 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19999 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
20000 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
20001 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20002 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
20003 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
20004 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
20005 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
20006 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
20007 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
20008 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
20009 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
20012 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
20013 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
20014 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
20017 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
20020 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
20021 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
20022 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
20023 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
20024 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
20025 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
20026 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
20027 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
20028 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
20029 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
20030 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
20031 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
20032 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
20033 /* ST Microelectronics Loongson 2E and 2F cores. */
20034 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
20035 { "loongson2f", 0, ASE_LOONGSON_MMI
, ISA_MIPS3
, CPU_LOONGSON_2F
},
20038 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
20039 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
20040 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
20041 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
20042 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
20043 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
20044 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
20045 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
20046 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
20047 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
20048 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
20049 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
20050 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
20051 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
20052 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
20055 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20056 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20057 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20058 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
20060 /* MIPS 32 Release 2 */
20061 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20062 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20063 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20064 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20065 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20066 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20067 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20068 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20069 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
20070 ISA_MIPS32R2
, CPU_MIPS32R2
},
20071 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
20072 ISA_MIPS32R2
, CPU_MIPS32R2
},
20073 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20074 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20075 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20076 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20077 /* Deprecated forms of the above. */
20078 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20079 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20080 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
20081 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20082 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20083 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20084 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20085 /* Deprecated forms of the above. */
20086 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20087 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20088 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
20089 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20090 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20091 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20092 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20093 /* Deprecated forms of the above. */
20094 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20095 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20096 /* 34Kn is a 34kc without DSP. */
20097 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20098 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
20099 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20100 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20101 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20102 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20103 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20104 /* Deprecated forms of the above. */
20105 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20106 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20107 /* 1004K cores are multiprocessor versions of the 34K. */
20108 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20109 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20110 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20111 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20112 /* interaptiv is the new name for 1004kf. */
20113 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20114 { "interaptiv-mr2", 0,
20115 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
20116 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
20117 /* M5100 family. */
20118 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20119 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20120 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
20121 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20124 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
20125 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
20126 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
20127 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
20129 /* Broadcom SB-1 CPU core. */
20130 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
20131 /* Broadcom SB-1A CPU core. */
20132 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
20134 /* MIPS 64 Release 2. */
20135 /* Loongson CPU core. */
20136 /* -march=loongson3a is an alias of -march=gs464 for compatibility. */
20137 { "loongson3a", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20138 ISA_MIPS64R2
, CPU_GS464
},
20139 { "gs464", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20140 ISA_MIPS64R2
, CPU_GS464
},
20141 { "gs464e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20142 | ASE_LOONGSON_EXT2
, ISA_MIPS64R2
, CPU_GS464E
},
20143 { "gs264e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20144 | ASE_LOONGSON_EXT2
| ASE_MSA
| ASE_MSA64
, ISA_MIPS64R2
, CPU_GS264E
},
20146 /* Cavium Networks Octeon CPU core. */
20147 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
20148 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
20149 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
20150 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
20153 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
20156 XLP is mostly like XLR, with the prominent exception that it is
20157 MIPS64R2 rather than MIPS64. */
20158 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
20160 /* MIPS 64 Release 6. */
20161 { "i6400", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20162 { "i6500", 0, ASE_VIRT
| ASE_MSA
| ASE_CRC
| ASE_GINV
,
20163 ISA_MIPS64R6
, CPU_MIPS64R6
},
20164 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20167 { NULL
, 0, 0, 0, 0 }
20171 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
20172 with a final "000" replaced by "k". Ignore case.
20174 Note: this function is shared between GCC and GAS. */
20177 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
20179 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
20180 given
++, canonical
++;
20182 return ((*given
== 0 && *canonical
== 0)
20183 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
20187 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
20188 CPU name. We've traditionally allowed a lot of variation here.
20190 Note: this function is shared between GCC and GAS. */
20193 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
20195 /* First see if the name matches exactly, or with a final "000"
20196 turned into "k". */
20197 if (mips_strict_matching_cpu_name_p (canonical
, given
))
20200 /* If not, try comparing based on numerical designation alone.
20201 See if GIVEN is an unadorned number, or 'r' followed by a number. */
20202 if (TOLOWER (*given
) == 'r')
20204 if (!ISDIGIT (*given
))
20207 /* Skip over some well-known prefixes in the canonical name,
20208 hoping to find a number there too. */
20209 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
20211 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
20213 else if (TOLOWER (canonical
[0]) == 'r')
20216 return mips_strict_matching_cpu_name_p (canonical
, given
);
20220 /* Parse an option that takes the name of a processor as its argument.
20221 OPTION is the name of the option and CPU_STRING is the argument.
20222 Return the corresponding processor enumeration if the CPU_STRING is
20223 recognized, otherwise report an error and return null.
20225 A similar function exists in GCC. */
20227 static const struct mips_cpu_info
*
20228 mips_parse_cpu (const char *option
, const char *cpu_string
)
20230 const struct mips_cpu_info
*p
;
20232 /* 'from-abi' selects the most compatible architecture for the given
20233 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
20234 EABIs, we have to decide whether we're using the 32-bit or 64-bit
20235 version. Look first at the -mgp options, if given, otherwise base
20236 the choice on MIPS_DEFAULT_64BIT.
20238 Treat NO_ABI like the EABIs. One reason to do this is that the
20239 plain 'mips' and 'mips64' configs have 'from-abi' as their default
20240 architecture. This code picks MIPS I for 'mips' and MIPS III for
20241 'mips64', just as we did in the days before 'from-abi'. */
20242 if (strcasecmp (cpu_string
, "from-abi") == 0)
20244 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
20245 return mips_cpu_info_from_isa (ISA_MIPS1
);
20247 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
20248 return mips_cpu_info_from_isa (ISA_MIPS3
);
20250 if (file_mips_opts
.gp
>= 0)
20251 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
20252 ? ISA_MIPS1
: ISA_MIPS3
);
20254 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
20259 /* 'default' has traditionally been a no-op. Probably not very useful. */
20260 if (strcasecmp (cpu_string
, "default") == 0)
20263 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
20264 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
20267 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
20271 /* Return the canonical processor information for ISA (a member of the
20272 ISA_MIPS* enumeration). */
20274 static const struct mips_cpu_info
*
20275 mips_cpu_info_from_isa (int isa
)
20279 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20280 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
20281 && isa
== mips_cpu_info_table
[i
].isa
)
20282 return (&mips_cpu_info_table
[i
]);
20287 static const struct mips_cpu_info
*
20288 mips_cpu_info_from_arch (int arch
)
20292 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20293 if (arch
== mips_cpu_info_table
[i
].cpu
)
20294 return (&mips_cpu_info_table
[i
]);
20300 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
20304 fprintf (stream
, "%24s", "");
20309 fprintf (stream
, ", ");
20313 if (*col_p
+ strlen (string
) > 72)
20315 fprintf (stream
, "\n%24s", "");
20319 fprintf (stream
, "%s", string
);
20320 *col_p
+= strlen (string
);
20326 md_show_usage (FILE *stream
)
20331 fprintf (stream
, _("\
20333 -EB generate big endian output\n\
20334 -EL generate little endian output\n\
20335 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20336 -G NUM allow referencing objects up to NUM bytes\n\
20337 implicitly with the gp register [default 8]\n"));
20338 fprintf (stream
, _("\
20339 -mips1 generate MIPS ISA I instructions\n\
20340 -mips2 generate MIPS ISA II instructions\n\
20341 -mips3 generate MIPS ISA III instructions\n\
20342 -mips4 generate MIPS ISA IV instructions\n\
20343 -mips5 generate MIPS ISA V instructions\n\
20344 -mips32 generate MIPS32 ISA instructions\n\
20345 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20346 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20347 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20348 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20349 -mips64 generate MIPS64 ISA instructions\n\
20350 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20351 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20352 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20353 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20354 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20358 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20359 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
20360 show (stream
, "from-abi", &column
, &first
);
20361 fputc ('\n', stream
);
20363 fprintf (stream
, _("\
20364 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20365 -no-mCPU don't generate code specific to CPU.\n\
20366 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20370 show (stream
, "3900", &column
, &first
);
20371 show (stream
, "4010", &column
, &first
);
20372 show (stream
, "4100", &column
, &first
);
20373 show (stream
, "4650", &column
, &first
);
20374 fputc ('\n', stream
);
20376 fprintf (stream
, _("\
20377 -mips16 generate mips16 instructions\n\
20378 -no-mips16 do not generate mips16 instructions\n"));
20379 fprintf (stream
, _("\
20380 -mmips16e2 generate MIPS16e2 instructions\n\
20381 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20382 fprintf (stream
, _("\
20383 -mmicromips generate microMIPS instructions\n\
20384 -mno-micromips do not generate microMIPS instructions\n"));
20385 fprintf (stream
, _("\
20386 -msmartmips generate smartmips instructions\n\
20387 -mno-smartmips do not generate smartmips instructions\n"));
20388 fprintf (stream
, _("\
20389 -mdsp generate DSP instructions\n\
20390 -mno-dsp do not generate DSP instructions\n"));
20391 fprintf (stream
, _("\
20392 -mdspr2 generate DSP R2 instructions\n\
20393 -mno-dspr2 do not generate DSP R2 instructions\n"));
20394 fprintf (stream
, _("\
20395 -mdspr3 generate DSP R3 instructions\n\
20396 -mno-dspr3 do not generate DSP R3 instructions\n"));
20397 fprintf (stream
, _("\
20398 -mmt generate MT instructions\n\
20399 -mno-mt do not generate MT instructions\n"));
20400 fprintf (stream
, _("\
20401 -mmcu generate MCU instructions\n\
20402 -mno-mcu do not generate MCU instructions\n"));
20403 fprintf (stream
, _("\
20404 -mmsa generate MSA instructions\n\
20405 -mno-msa do not generate MSA instructions\n"));
20406 fprintf (stream
, _("\
20407 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20408 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20409 fprintf (stream
, _("\
20410 -mvirt generate Virtualization instructions\n\
20411 -mno-virt do not generate Virtualization instructions\n"));
20412 fprintf (stream
, _("\
20413 -mcrc generate CRC instructions\n\
20414 -mno-crc do not generate CRC instructions\n"));
20415 fprintf (stream
, _("\
20416 -mginv generate Global INValidate (GINV) instructions\n\
20417 -mno-ginv do not generate Global INValidate instructions\n"));
20418 fprintf (stream
, _("\
20419 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20420 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20421 fprintf (stream
, _("\
20422 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20423 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20424 fprintf (stream
, _("\
20425 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20426 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20427 fprintf (stream
, _("\
20428 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20429 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20430 fprintf (stream
, _("\
20431 -minsn32 only generate 32-bit microMIPS instructions\n\
20432 -mno-insn32 generate all microMIPS instructions\n"));
20433 #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC
20434 fprintf (stream
, _("\
20435 -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\
20436 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n"));
20438 fprintf (stream
, _("\
20439 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20440 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n"));
20442 fprintf (stream
, _("\
20443 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20444 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20445 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20446 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\
20447 -mfix-vr4120 work around certain VR4120 errata\n\
20448 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20449 -mfix-24k insert a nop after ERET and DERET instructions\n\
20450 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20451 -mfix-r5900 work around R5900 short loop errata\n\
20452 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20453 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20454 -msym32 assume all symbols have 32-bit values\n\
20455 -O0 do not remove unneeded NOPs, do not swap branches\n\
20456 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20457 -O2 remove unneeded NOPs and swap branches\n\
20458 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20459 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20460 fprintf (stream
, _("\
20461 -mhard-float allow floating-point instructions\n\
20462 -msoft-float do not allow floating-point instructions\n\
20463 -msingle-float only allow 32-bit floating-point operations\n\
20464 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20465 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20466 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20467 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20468 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20469 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20473 show (stream
, "legacy", &column
, &first
);
20474 show (stream
, "2008", &column
, &first
);
20476 fputc ('\n', stream
);
20478 fprintf (stream
, _("\
20479 -KPIC, -call_shared generate SVR4 position independent code\n\
20480 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20481 -mvxworks-pic generate VxWorks position independent code\n\
20482 -non_shared do not generate code that can operate with DSOs\n\
20483 -xgot assume a 32 bit GOT\n\
20484 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20485 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20486 position dependent (non shared) code\n\
20487 -mabi=ABI create ABI conformant object file for:\n"));
20491 show (stream
, "32", &column
, &first
);
20492 show (stream
, "o64", &column
, &first
);
20493 show (stream
, "n32", &column
, &first
);
20494 show (stream
, "64", &column
, &first
);
20495 show (stream
, "eabi", &column
, &first
);
20497 fputc ('\n', stream
);
20499 fprintf (stream
, _("\
20500 -32 create o32 ABI object file%s\n"),
20501 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20502 fprintf (stream
, _("\
20503 -n32 create n32 ABI object file%s\n"),
20504 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20505 fprintf (stream
, _("\
20506 -64 create 64 ABI object file%s\n"),
20507 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20512 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20514 if (HAVE_64BIT_SYMBOLS
)
20515 return dwarf2_format_64bit_irix
;
20517 return dwarf2_format_32bit
;
20522 mips_dwarf2_addr_size (void)
20524 if (HAVE_64BIT_OBJECTS
)
20530 /* Standard calling conventions leave the CFA at SP on entry. */
20532 mips_cfi_frame_initial_instructions (void)
20534 cfi_add_CFA_def_cfa_register (SP
);
20538 tc_mips_regname_to_dw2regnum (char *regname
)
20540 unsigned int regnum
= -1;
20543 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20549 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20550 Given a symbolic attribute NAME, return the proper integer value.
20551 Returns -1 if the attribute is not known. */
20554 mips_convert_symbolic_attribute (const char *name
)
20556 static const struct
20561 attribute_table
[] =
20563 #define T(tag) {#tag, tag}
20564 T (Tag_GNU_MIPS_ABI_FP
),
20565 T (Tag_GNU_MIPS_ABI_MSA
),
20573 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20574 if (streq (name
, attribute_table
[i
].name
))
20575 return attribute_table
[i
].tag
;
20583 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20585 mips_emit_delays ();
20587 as_warn (_("missing .end at end of assembly"));
20589 /* Just in case no code was emitted, do the consistency check. */
20590 file_mips_check_options ();
20592 /* Set a floating-point ABI if the user did not. */
20593 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20595 /* Perform consistency checks on the floating-point ABI. */
20596 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20597 Tag_GNU_MIPS_ABI_FP
);
20598 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20599 check_fpabi (fpabi
);
20603 /* Soft-float gets precedence over single-float, the two options should
20604 not be used together so this should not matter. */
20605 if (file_mips_opts
.soft_float
== 1)
20606 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20607 /* Single-float gets precedence over all double_float cases. */
20608 else if (file_mips_opts
.single_float
== 1)
20609 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20612 switch (file_mips_opts
.fp
)
20615 if (file_mips_opts
.gp
== 32)
20616 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20619 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20622 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20623 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20624 else if (file_mips_opts
.gp
== 32)
20625 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20627 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20632 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20633 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20637 /* Returns the relocation type required for a particular CFI encoding. */
20639 bfd_reloc_code_real_type
20640 mips_cfi_reloc_for_encoding (int encoding
)
20642 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20643 return BFD_RELOC_32_PCREL
;
20644 else return BFD_RELOC_NONE
;