1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2018 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic
;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got
= 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap
= 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction
;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder
;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix
;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value
= 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen
= 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS
*, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control
*op_hash
= NULL
;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control
*mips16_op_hash
= NULL
;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control
*micromips_op_hash
= NULL
;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars
[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars
[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars
[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS
[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format
{
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error
{
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format
;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error
;
737 static int auto_align
= 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset
= -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset
= -1;
749 static int mips_cpreturn_register
= -1;
750 static int mips_gp_register
= GP
;
751 static int mips_gprel_offset
= 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid
= 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg
= SP
;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid
= 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize
= 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug
= 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history
[1 + MAX_NOPS
];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array
{
797 const struct mips_operand
*operand
[MAX_OPERANDS
];
799 static struct mips_operand_array
*mips_operands
;
800 static struct mips_operand_array
*mips16_operands
;
801 static struct mips_operand_array
*micromips_operands
;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn
;
805 static struct mips_cl_insn mips16_nop_insn
;
806 static struct mips_cl_insn micromips_nop16_insn
;
807 static struct mips_cl_insn micromips_nop32_insn
;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS
*prev_nop_frag
;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds
;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required
;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since
;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup
*next
;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup
*mips_hi_fixup_list
;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS
*prev_reloc_op_frag
;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map
[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1
[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2
[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map
[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump
;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop
;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f
;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120
;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130
;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k
;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000
;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1
;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch
;
947 /* TRUE if checks are suppressed for invalid branches between ISA modes.
948 Needed for broken assembly produced by some GCC versions and some
949 sloppy code out there, where branches to data labels are present. */
950 static bfd_boolean mips_ignore_branch_isa
;
952 /* The expansion of many macros depends on the type of symbol that
953 they refer to. For example, when generating position-dependent code,
954 a macro that refers to a symbol may have two different expansions,
955 one which uses GP-relative addresses and one which uses absolute
956 addresses. When generating SVR4-style PIC, a macro may have
957 different expansions for local and global symbols.
959 We handle these situations by generating both sequences and putting
960 them in variant frags. In position-dependent code, the first sequence
961 will be the GP-relative one and the second sequence will be the
962 absolute one. In SVR4 PIC, the first sequence will be for global
963 symbols and the second will be for local symbols.
965 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
966 SECOND are the lengths of the two sequences in bytes. These fields
967 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
968 the subtype has the following flags:
971 Set if generating PIC code.
974 Set if it has been decided that we should use the second
975 sequence instead of the first.
978 Set in the first variant frag if the macro's second implementation
979 is longer than its first. This refers to the macro as a whole,
980 not an individual relaxation.
983 Set in the first variant frag if the macro appeared in a .set nomacro
984 block and if one alternative requires a warning but the other does not.
987 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
990 RELAX_DELAY_SLOT_16BIT
991 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
994 RELAX_DELAY_SLOT_SIZE_FIRST
995 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
996 the macro is of the wrong size for the branch delay slot.
998 RELAX_DELAY_SLOT_SIZE_SECOND
999 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1000 the macro is of the wrong size for the branch delay slot.
1002 The frag's "opcode" points to the first fixup for relaxable code.
1004 Relaxable macros are generated using a sequence such as:
1006 relax_start (SYMBOL);
1007 ... generate first expansion ...
1009 ... generate second expansion ...
1012 The code and fixups for the unwanted alternative are discarded
1013 by md_convert_frag. */
1014 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1015 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1017 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1018 #define RELAX_SECOND(X) ((X) & 0xff)
1019 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1020 #define RELAX_USE_SECOND 0x20000
1021 #define RELAX_SECOND_LONGER 0x40000
1022 #define RELAX_NOMACRO 0x80000
1023 #define RELAX_DELAY_SLOT 0x100000
1024 #define RELAX_DELAY_SLOT_16BIT 0x200000
1025 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1026 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1028 /* Branch without likely bit. If label is out of range, we turn:
1030 beq reg1, reg2, label
1040 with the following opcode replacements:
1047 bltzal <-> bgezal (with jal label instead of j label)
1049 Even though keeping the delay slot instruction in the delay slot of
1050 the branch would be more efficient, it would be very tricky to do
1051 correctly, because we'd have to introduce a variable frag *after*
1052 the delay slot instruction, and expand that instead. Let's do it
1053 the easy way for now, even if the branch-not-taken case now costs
1054 one additional instruction. Out-of-range branches are not supposed
1055 to be common, anyway.
1057 Branch likely. If label is out of range, we turn:
1059 beql reg1, reg2, label
1060 delay slot (annulled if branch not taken)
1069 delay slot (executed only if branch taken)
1072 It would be possible to generate a shorter sequence by losing the
1073 likely bit, generating something like:
1078 delay slot (executed only if branch taken)
1090 bltzall -> bgezal (with jal label instead of j label)
1091 bgezall -> bltzal (ditto)
1094 but it's not clear that it would actually improve performance. */
1095 #define RELAX_BRANCH_ENCODE(at, pic, \
1096 uncond, likely, link, toofar) \
1097 ((relax_substateT) \
1100 | ((pic) ? 0x20 : 0) \
1101 | ((toofar) ? 0x40 : 0) \
1102 | ((link) ? 0x80 : 0) \
1103 | ((likely) ? 0x100 : 0) \
1104 | ((uncond) ? 0x200 : 0)))
1105 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1106 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1107 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1108 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1109 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1110 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1111 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1113 /* For mips16 code, we use an entirely different form of relaxation.
1114 mips16 supports two versions of most instructions which take
1115 immediate values: a small one which takes some small value, and a
1116 larger one which takes a 16 bit value. Since branches also follow
1117 this pattern, relaxing these values is required.
1119 We can assemble both mips16 and normal MIPS code in a single
1120 object. Therefore, we need to support this type of relaxation at
1121 the same time that we support the relaxation described above. We
1122 use the high bit of the subtype field to distinguish these cases.
1124 The information we store for this type of relaxation is the
1125 argument code found in the opcode file for this relocation, whether
1126 the user explicitly requested a small or extended form, and whether
1127 the relocation is in a jump or jal delay slot. That tells us the
1128 size of the value, and how it should be stored. We also store
1129 whether the fragment is considered to be extended or not. We also
1130 store whether this is known to be a branch to a different section,
1131 whether we have tried to relax this frag yet, and whether we have
1132 ever extended a PC relative fragment because of a shift count. */
1133 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1138 | ((e2) ? 0x100 : 0) \
1139 | ((pic) ? 0x200 : 0) \
1140 | ((sym32) ? 0x400 : 0) \
1141 | ((nomacro) ? 0x800 : 0) \
1142 | ((small) ? 0x1000 : 0) \
1143 | ((ext) ? 0x2000 : 0) \
1144 | ((dslot) ? 0x4000 : 0) \
1145 | ((jal_dslot) ? 0x8000 : 0))
1147 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1148 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1149 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1150 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1151 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1152 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1153 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1154 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1155 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1156 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1158 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1159 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1160 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1161 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1162 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1163 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1164 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1165 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1166 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1168 /* For microMIPS code, we use relaxation similar to one we use for
1169 MIPS16 code. Some instructions that take immediate values support
1170 two encodings: a small one which takes some small value, and a
1171 larger one which takes a 16 bit value. As some branches also follow
1172 this pattern, relaxing these values is required.
1174 We can assemble both microMIPS and normal MIPS code in a single
1175 object. Therefore, we need to support this type of relaxation at
1176 the same time that we support the relaxation described above. We
1177 use one of the high bits of the subtype field to distinguish these
1180 The information we store for this type of relaxation is the argument
1181 code found in the opcode file for this relocation, the register
1182 selected as the assembler temporary, whether in the 32-bit
1183 instruction mode, whether the branch is unconditional, whether it is
1184 compact, whether there is no delay-slot instruction available to fill
1185 in, whether it stores the link address implicitly in $ra, whether
1186 relaxation of out-of-range 32-bit branches to a sequence of
1187 instructions is enabled, and whether the displacement of a branch is
1188 too large to fit as an immediate argument of a 16-bit and a 32-bit
1189 branch, respectively. */
1190 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1191 uncond, compact, link, nods, \
1192 relax32, toofar16, toofar32) \
1195 | (((at) & 0x1f) << 8) \
1196 | ((insn32) ? 0x2000 : 0) \
1197 | ((pic) ? 0x4000 : 0) \
1198 | ((uncond) ? 0x8000 : 0) \
1199 | ((compact) ? 0x10000 : 0) \
1200 | ((link) ? 0x20000 : 0) \
1201 | ((nods) ? 0x40000 : 0) \
1202 | ((relax32) ? 0x80000 : 0) \
1203 | ((toofar16) ? 0x100000 : 0) \
1204 | ((toofar32) ? 0x200000 : 0))
1205 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1206 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1207 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1208 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1209 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1210 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1211 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1212 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1213 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1214 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1216 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1217 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1218 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1219 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1220 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1221 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1223 /* Sign-extend 16-bit value X. */
1224 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1226 /* Is the given value a sign-extended 32-bit value? */
1227 #define IS_SEXT_32BIT_NUM(x) \
1228 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1229 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1231 /* Is the given value a sign-extended 16-bit value? */
1232 #define IS_SEXT_16BIT_NUM(x) \
1233 (((x) &~ (offsetT) 0x7fff) == 0 \
1234 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1236 /* Is the given value a sign-extended 12-bit value? */
1237 #define IS_SEXT_12BIT_NUM(x) \
1238 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1240 /* Is the given value a sign-extended 9-bit value? */
1241 #define IS_SEXT_9BIT_NUM(x) \
1242 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1244 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1245 #define IS_ZEXT_32BIT_NUM(x) \
1246 (((x) &~ (offsetT) 0xffffffff) == 0 \
1247 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1249 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1251 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1252 (((STRUCT) >> (SHIFT)) & (MASK))
1254 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1255 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1257 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1258 : EXTRACT_BITS ((INSN).insn_opcode, \
1259 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1260 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1261 EXTRACT_BITS ((INSN).insn_opcode, \
1262 MIPS16OP_MASK_##FIELD, \
1263 MIPS16OP_SH_##FIELD)
1265 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1266 #define MIPS16_EXTEND (0xf000U << 16)
1268 /* Whether or not we are emitting a branch-likely macro. */
1269 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1271 /* Global variables used when generating relaxable macros. See the
1272 comment above RELAX_ENCODE for more details about how relaxation
1275 /* 0 if we're not emitting a relaxable macro.
1276 1 if we're emitting the first of the two relaxation alternatives.
1277 2 if we're emitting the second alternative. */
1280 /* The first relaxable fixup in the current frag. (In other words,
1281 the first fixup that refers to relaxable code.) */
1284 /* sizes[0] says how many bytes of the first alternative are stored in
1285 the current frag. Likewise sizes[1] for the second alternative. */
1286 unsigned int sizes
[2];
1288 /* The symbol on which the choice of sequence depends. */
1292 /* Global variables used to decide whether a macro needs a warning. */
1294 /* True if the macro is in a branch delay slot. */
1295 bfd_boolean delay_slot_p
;
1297 /* Set to the length in bytes required if the macro is in a delay slot
1298 that requires a specific length of instruction, otherwise zero. */
1299 unsigned int delay_slot_length
;
1301 /* For relaxable macros, sizes[0] is the length of the first alternative
1302 in bytes and sizes[1] is the length of the second alternative.
1303 For non-relaxable macros, both elements give the length of the
1305 unsigned int sizes
[2];
1307 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1308 instruction of the first alternative in bytes and first_insn_sizes[1]
1309 is the length of the first instruction of the second alternative.
1310 For non-relaxable macros, both elements give the length of the first
1311 instruction in bytes.
1313 Set to zero if we haven't yet seen the first instruction. */
1314 unsigned int first_insn_sizes
[2];
1316 /* For relaxable macros, insns[0] is the number of instructions for the
1317 first alternative and insns[1] is the number of instructions for the
1320 For non-relaxable macros, both elements give the number of
1321 instructions for the macro. */
1322 unsigned int insns
[2];
1324 /* The first variant frag for this macro. */
1326 } mips_macro_warning
;
1328 /* Prototypes for static functions. */
1330 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1332 static void append_insn
1333 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1334 bfd_boolean expansionp
);
1335 static void mips_no_prev_insn (void);
1336 static void macro_build (expressionS
*, const char *, const char *, ...);
1337 static void mips16_macro_build
1338 (expressionS
*, const char *, const char *, va_list *);
1339 static void load_register (int, expressionS
*, int);
1340 static void macro_start (void);
1341 static void macro_end (void);
1342 static void macro (struct mips_cl_insn
*ip
, char *str
);
1343 static void mips16_macro (struct mips_cl_insn
* ip
);
1344 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1345 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1346 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1347 static void mips16_immed
1348 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1349 unsigned int, unsigned long *);
1350 static size_t my_getSmallExpression
1351 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1352 static void my_getExpression (expressionS
*, char *);
1353 static void s_align (int);
1354 static void s_change_sec (int);
1355 static void s_change_section (int);
1356 static void s_cons (int);
1357 static void s_float_cons (int);
1358 static void s_mips_globl (int);
1359 static void s_option (int);
1360 static void s_mipsset (int);
1361 static void s_abicalls (int);
1362 static void s_cpload (int);
1363 static void s_cpsetup (int);
1364 static void s_cplocal (int);
1365 static void s_cprestore (int);
1366 static void s_cpreturn (int);
1367 static void s_dtprelword (int);
1368 static void s_dtpreldword (int);
1369 static void s_tprelword (int);
1370 static void s_tpreldword (int);
1371 static void s_gpvalue (int);
1372 static void s_gpword (int);
1373 static void s_gpdword (int);
1374 static void s_ehword (int);
1375 static void s_cpadd (int);
1376 static void s_insn (int);
1377 static void s_nan (int);
1378 static void s_module (int);
1379 static void s_mips_ent (int);
1380 static void s_mips_end (int);
1381 static void s_mips_frame (int);
1382 static void s_mips_mask (int reg_type
);
1383 static void s_mips_stab (int);
1384 static void s_mips_weakext (int);
1385 static void s_mips_file (int);
1386 static void s_mips_loc (int);
1387 static bfd_boolean
pic_need_relax (symbolS
*);
1388 static int relaxed_branch_length (fragS
*, asection
*, int);
1389 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1390 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1391 static void file_mips_check_options (void);
1393 /* Table and functions used to map between CPU/ISA names, and
1394 ISA levels, and CPU numbers. */
1396 struct mips_cpu_info
1398 const char *name
; /* CPU or ISA name. */
1399 int flags
; /* MIPS_CPU_* flags. */
1400 int ase
; /* Set of ASEs implemented by the CPU. */
1401 int isa
; /* ISA level. */
1402 int cpu
; /* CPU number (default CPU if ISA). */
1405 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1407 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1408 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1409 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1411 /* Command-line options. */
1412 const char *md_shortopts
= "O::g::G:";
1416 OPTION_MARCH
= OPTION_MD_BASE
,
1448 OPTION_NO_SMARTMIPS
,
1458 OPTION_NO_MICROMIPS
,
1473 OPTION_M7000_HILO_FIX
,
1474 OPTION_MNO_7000_HILO_FIX
,
1478 OPTION_NO_FIX_RM7000
,
1479 OPTION_FIX_LOONGSON2F_JUMP
,
1480 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1481 OPTION_FIX_LOONGSON2F_NOP
,
1482 OPTION_NO_FIX_LOONGSON2F_NOP
,
1484 OPTION_NO_FIX_VR4120
,
1486 OPTION_NO_FIX_VR4130
,
1487 OPTION_FIX_CN63XXP1
,
1488 OPTION_NO_FIX_CN63XXP1
,
1495 OPTION_CONSTRUCT_FLOATS
,
1496 OPTION_NO_CONSTRUCT_FLOATS
,
1500 OPTION_RELAX_BRANCH
,
1501 OPTION_NO_RELAX_BRANCH
,
1502 OPTION_IGNORE_BRANCH_ISA
,
1503 OPTION_NO_IGNORE_BRANCH_ISA
,
1512 OPTION_SINGLE_FLOAT
,
1513 OPTION_DOUBLE_FLOAT
,
1526 OPTION_MVXWORKS_PIC
,
1529 OPTION_NO_ODD_SPREG
,
1535 struct option md_longopts
[] =
1537 /* Options which specify architecture. */
1538 {"march", required_argument
, NULL
, OPTION_MARCH
},
1539 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1540 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1541 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1542 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1543 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1544 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1545 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1546 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1547 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1548 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1549 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1550 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1551 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1552 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1553 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1554 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1555 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1557 /* Options which specify Application Specific Extensions (ASEs). */
1558 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1559 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1560 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1561 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1562 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1563 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1564 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1565 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1566 {"mmt", no_argument
, NULL
, OPTION_MT
},
1567 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1568 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1569 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1570 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1571 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1572 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1573 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1574 {"meva", no_argument
, NULL
, OPTION_EVA
},
1575 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1576 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1577 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1578 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1579 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1580 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1581 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1582 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1583 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1584 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1585 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1586 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1587 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1588 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1589 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1590 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1591 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1593 /* Old-style architecture options. Don't add more of these. */
1594 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1595 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1596 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1597 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1598 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1599 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1600 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1601 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1603 /* Options which enable bug fixes. */
1604 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1605 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1606 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1607 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1608 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1609 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1610 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1611 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1612 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1613 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1614 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1615 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1616 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1617 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1618 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1619 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1620 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1622 /* Miscellaneous options. */
1623 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1624 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1625 {"break", no_argument
, NULL
, OPTION_BREAK
},
1626 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1627 {"EB", no_argument
, NULL
, OPTION_EB
},
1628 {"EL", no_argument
, NULL
, OPTION_EL
},
1629 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1630 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1631 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1632 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1633 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1634 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1635 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1636 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1637 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1638 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1639 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1640 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1641 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1642 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1643 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1644 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1645 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1646 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1647 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1648 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1649 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1650 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1651 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1653 /* Strictly speaking this next option is ELF specific,
1654 but we allow it for other ports as well in order to
1655 make testing easier. */
1656 {"32", no_argument
, NULL
, OPTION_32
},
1658 /* ELF-specific options. */
1659 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1660 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1661 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1662 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1663 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1664 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1665 {"n32", no_argument
, NULL
, OPTION_N32
},
1666 {"64", no_argument
, NULL
, OPTION_64
},
1667 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1668 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1669 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1670 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1671 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1672 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1674 {NULL
, no_argument
, NULL
, 0}
1676 size_t md_longopts_size
= sizeof (md_longopts
);
1678 /* Information about either an Application Specific Extension or an
1679 optional architecture feature that, for simplicity, we treat in the
1680 same way as an ASE. */
1683 /* The name of the ASE, used in both the command-line and .set options. */
1686 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1687 and 64-bit architectures, the flags here refer to the subset that
1688 is available on both. */
1691 /* The ASE_* flag used for instructions that are available on 64-bit
1692 architectures but that are not included in FLAGS. */
1693 unsigned int flags64
;
1695 /* The command-line options that turn the ASE on and off. */
1699 /* The minimum required architecture revisions for MIPS32, MIPS64,
1700 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1703 int micromips32_rev
;
1704 int micromips64_rev
;
1706 /* The architecture where the ASE was removed or -1 if the extension has not
1711 /* A table of all supported ASEs. */
1712 static const struct mips_ase mips_ases
[] = {
1713 { "dsp", ASE_DSP
, ASE_DSP64
,
1714 OPTION_DSP
, OPTION_NO_DSP
,
1718 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1719 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1723 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1724 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1728 { "eva", ASE_EVA
, 0,
1729 OPTION_EVA
, OPTION_NO_EVA
,
1733 { "mcu", ASE_MCU
, 0,
1734 OPTION_MCU
, OPTION_NO_MCU
,
1738 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1739 { "mdmx", ASE_MDMX
, 0,
1740 OPTION_MDMX
, OPTION_NO_MDMX
,
1744 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1745 { "mips3d", ASE_MIPS3D
, 0,
1746 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1751 OPTION_MT
, OPTION_NO_MT
,
1755 { "smartmips", ASE_SMARTMIPS
, 0,
1756 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1760 { "virt", ASE_VIRT
, ASE_VIRT64
,
1761 OPTION_VIRT
, OPTION_NO_VIRT
,
1765 { "msa", ASE_MSA
, ASE_MSA64
,
1766 OPTION_MSA
, OPTION_NO_MSA
,
1770 { "xpa", ASE_XPA
, 0,
1771 OPTION_XPA
, OPTION_NO_XPA
,
1775 { "mips16e2", ASE_MIPS16E2
, 0,
1776 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1780 { "crc", ASE_CRC
, ASE_CRC64
,
1781 OPTION_CRC
, OPTION_NO_CRC
,
1785 { "ginv", ASE_GINV
, 0,
1786 OPTION_GINV
, OPTION_NO_GINV
,
1791 /* The set of ASEs that require -mfp64. */
1792 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1794 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1795 static const unsigned int mips_ase_groups
[] = {
1796 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
1801 The following pseudo-ops from the Kane and Heinrich MIPS book
1802 should be defined here, but are currently unsupported: .alias,
1803 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1805 The following pseudo-ops from the Kane and Heinrich MIPS book are
1806 specific to the type of debugging information being generated, and
1807 should be defined by the object format: .aent, .begin, .bend,
1808 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1811 The following pseudo-ops from the Kane and Heinrich MIPS book are
1812 not MIPS CPU specific, but are also not specific to the object file
1813 format. This file is probably the best place to define them, but
1814 they are not currently supported: .asm0, .endr, .lab, .struct. */
1816 static const pseudo_typeS mips_pseudo_table
[] =
1818 /* MIPS specific pseudo-ops. */
1819 {"option", s_option
, 0},
1820 {"set", s_mipsset
, 0},
1821 {"rdata", s_change_sec
, 'r'},
1822 {"sdata", s_change_sec
, 's'},
1823 {"livereg", s_ignore
, 0},
1824 {"abicalls", s_abicalls
, 0},
1825 {"cpload", s_cpload
, 0},
1826 {"cpsetup", s_cpsetup
, 0},
1827 {"cplocal", s_cplocal
, 0},
1828 {"cprestore", s_cprestore
, 0},
1829 {"cpreturn", s_cpreturn
, 0},
1830 {"dtprelword", s_dtprelword
, 0},
1831 {"dtpreldword", s_dtpreldword
, 0},
1832 {"tprelword", s_tprelword
, 0},
1833 {"tpreldword", s_tpreldword
, 0},
1834 {"gpvalue", s_gpvalue
, 0},
1835 {"gpword", s_gpword
, 0},
1836 {"gpdword", s_gpdword
, 0},
1837 {"ehword", s_ehword
, 0},
1838 {"cpadd", s_cpadd
, 0},
1839 {"insn", s_insn
, 0},
1841 {"module", s_module
, 0},
1843 /* Relatively generic pseudo-ops that happen to be used on MIPS
1845 {"asciiz", stringer
, 8 + 1},
1846 {"bss", s_change_sec
, 'b'},
1848 {"half", s_cons
, 1},
1849 {"dword", s_cons
, 3},
1850 {"weakext", s_mips_weakext
, 0},
1851 {"origin", s_org
, 0},
1852 {"repeat", s_rept
, 0},
1854 /* For MIPS this is non-standard, but we define it for consistency. */
1855 {"sbss", s_change_sec
, 'B'},
1857 /* These pseudo-ops are defined in read.c, but must be overridden
1858 here for one reason or another. */
1859 {"align", s_align
, 0},
1860 {"byte", s_cons
, 0},
1861 {"data", s_change_sec
, 'd'},
1862 {"double", s_float_cons
, 'd'},
1863 {"float", s_float_cons
, 'f'},
1864 {"globl", s_mips_globl
, 0},
1865 {"global", s_mips_globl
, 0},
1866 {"hword", s_cons
, 1},
1868 {"long", s_cons
, 2},
1869 {"octa", s_cons
, 4},
1870 {"quad", s_cons
, 3},
1871 {"section", s_change_section
, 0},
1872 {"short", s_cons
, 1},
1873 {"single", s_float_cons
, 'f'},
1874 {"stabd", s_mips_stab
, 'd'},
1875 {"stabn", s_mips_stab
, 'n'},
1876 {"stabs", s_mips_stab
, 's'},
1877 {"text", s_change_sec
, 't'},
1878 {"word", s_cons
, 2},
1880 { "extern", ecoff_directive_extern
, 0},
1885 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1887 /* These pseudo-ops should be defined by the object file format.
1888 However, a.out doesn't support them, so we have versions here. */
1889 {"aent", s_mips_ent
, 1},
1890 {"bgnb", s_ignore
, 0},
1891 {"end", s_mips_end
, 0},
1892 {"endb", s_ignore
, 0},
1893 {"ent", s_mips_ent
, 0},
1894 {"file", s_mips_file
, 0},
1895 {"fmask", s_mips_mask
, 'F'},
1896 {"frame", s_mips_frame
, 0},
1897 {"loc", s_mips_loc
, 0},
1898 {"mask", s_mips_mask
, 'R'},
1899 {"verstamp", s_ignore
, 0},
1903 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1904 purpose of the `.dc.a' internal pseudo-op. */
1907 mips_address_bytes (void)
1909 file_mips_check_options ();
1910 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1913 extern void pop_insert (const pseudo_typeS
*);
1916 mips_pop_insert (void)
1918 pop_insert (mips_pseudo_table
);
1919 if (! ECOFF_DEBUGGING
)
1920 pop_insert (mips_nonecoff_pseudo_table
);
1923 /* Symbols labelling the current insn. */
1925 struct insn_label_list
1927 struct insn_label_list
*next
;
1931 static struct insn_label_list
*free_insn_labels
;
1932 #define label_list tc_segment_info_data.labels
1934 static void mips_clear_insn_labels (void);
1935 static void mips_mark_labels (void);
1936 static void mips_compressed_mark_labels (void);
1939 mips_clear_insn_labels (void)
1941 struct insn_label_list
**pl
;
1942 segment_info_type
*si
;
1946 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1949 si
= seg_info (now_seg
);
1950 *pl
= si
->label_list
;
1951 si
->label_list
= NULL
;
1955 /* Mark instruction labels in MIPS16/microMIPS mode. */
1958 mips_mark_labels (void)
1960 if (HAVE_CODE_COMPRESSION
)
1961 mips_compressed_mark_labels ();
1964 static char *expr_end
;
1966 /* An expression in a macro instruction. This is set by mips_ip and
1967 mips16_ip and when populated is always an O_constant. */
1969 static expressionS imm_expr
;
1971 /* The relocatable field in an instruction and the relocs associated
1972 with it. These variables are used for instructions like LUI and
1973 JAL as well as true offsets. They are also used for address
1974 operands in macros. */
1976 static expressionS offset_expr
;
1977 static bfd_reloc_code_real_type offset_reloc
[3]
1978 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1980 /* This is set to the resulting size of the instruction to be produced
1981 by mips16_ip if an explicit extension is used or by mips_ip if an
1982 explicit size is supplied. */
1984 static unsigned int forced_insn_length
;
1986 /* True if we are assembling an instruction. All dot symbols defined during
1987 this time should be treated as code labels. */
1989 static bfd_boolean mips_assembling_insn
;
1991 /* The pdr segment for per procedure frame/regmask info. Not used for
1994 static segT pdr_seg
;
1996 /* The default target format to use. */
1998 #if defined (TE_FreeBSD)
1999 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2000 #elif defined (TE_TMIPS)
2001 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2003 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2007 mips_target_format (void)
2009 switch (OUTPUT_FLAVOR
)
2011 case bfd_target_elf_flavour
:
2013 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2014 return (target_big_endian
2015 ? "elf32-bigmips-vxworks"
2016 : "elf32-littlemips-vxworks");
2018 return (target_big_endian
2019 ? (HAVE_64BIT_OBJECTS
2020 ? ELF_TARGET ("elf64-", "big")
2022 ? ELF_TARGET ("elf32-n", "big")
2023 : ELF_TARGET ("elf32-", "big")))
2024 : (HAVE_64BIT_OBJECTS
2025 ? ELF_TARGET ("elf64-", "little")
2027 ? ELF_TARGET ("elf32-n", "little")
2028 : ELF_TARGET ("elf32-", "little"))));
2035 /* Return the ISA revision that is currently in use, or 0 if we are
2036 generating code for MIPS V or below. */
2041 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2044 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2047 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2050 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2053 /* microMIPS implies revision 2 or above. */
2054 if (mips_opts
.micromips
)
2057 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2063 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2066 mips_ase_mask (unsigned int flags
)
2070 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2071 if (flags
& mips_ase_groups
[i
])
2072 flags
|= mips_ase_groups
[i
];
2076 /* Check whether the current ISA supports ASE. Issue a warning if
2080 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2084 static unsigned int warned_isa
;
2085 static unsigned int warned_fp32
;
2087 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2088 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2090 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2091 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2092 && (warned_isa
& ase
->flags
) != ase
->flags
)
2094 warned_isa
|= ase
->flags
;
2095 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2096 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2098 as_warn (_("the %d-bit %s architecture does not support the"
2099 " `%s' extension"), size
, base
, ase
->name
);
2101 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2102 ase
->name
, base
, size
, min_rev
);
2104 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2105 && (warned_isa
& ase
->flags
) != ase
->flags
)
2107 warned_isa
|= ase
->flags
;
2108 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2109 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2110 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2111 ase
->name
, base
, size
, ase
->rem_rev
);
2114 if ((ase
->flags
& FP64_ASES
)
2115 && mips_opts
.fp
!= 64
2116 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2118 warned_fp32
|= ase
->flags
;
2119 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2123 /* Check all enabled ASEs to see whether they are supported by the
2124 chosen architecture. */
2127 mips_check_isa_supports_ases (void)
2129 unsigned int i
, mask
;
2131 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2133 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2134 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2135 mips_check_isa_supports_ase (&mips_ases
[i
]);
2139 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2140 that were affected. */
2143 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2144 bfd_boolean enabled_p
)
2148 mask
= mips_ase_mask (ase
->flags
);
2151 /* Clear combination ASE flags, which need to be recalculated based on
2152 updated regular ASE settings. */
2153 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
);
2156 opts
->ase
|= ase
->flags
;
2158 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2159 instructions which are only valid when both ASEs are enabled.
2160 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2161 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2163 opts
->ase
|= ASE_XPA_VIRT
;
2164 mask
|= ASE_XPA_VIRT
;
2166 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2168 opts
->ase
|= ASE_MIPS16E2_MT
;
2169 mask
|= ASE_MIPS16E2_MT
;
2175 /* Return the ASE called NAME, or null if none. */
2177 static const struct mips_ase
*
2178 mips_lookup_ase (const char *name
)
2182 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2183 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2184 return &mips_ases
[i
];
2188 /* Return the length of a microMIPS instruction in bytes. If bits of
2189 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2190 otherwise it is a 32-bit instruction. */
2192 static inline unsigned int
2193 micromips_insn_length (const struct mips_opcode
*mo
)
2195 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2198 /* Return the length of MIPS16 instruction OPCODE. */
2200 static inline unsigned int
2201 mips16_opcode_length (unsigned long opcode
)
2203 return (opcode
>> 16) == 0 ? 2 : 4;
2206 /* Return the length of instruction INSN. */
2208 static inline unsigned int
2209 insn_length (const struct mips_cl_insn
*insn
)
2211 if (mips_opts
.micromips
)
2212 return micromips_insn_length (insn
->insn_mo
);
2213 else if (mips_opts
.mips16
)
2214 return mips16_opcode_length (insn
->insn_opcode
);
2219 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2222 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2227 insn
->insn_opcode
= mo
->match
;
2230 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2231 insn
->fixp
[i
] = NULL
;
2232 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2233 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2234 insn
->mips16_absolute_jump_p
= 0;
2235 insn
->complete_p
= 0;
2236 insn
->cleared_p
= 0;
2239 /* Get a list of all the operands in INSN. */
2241 static const struct mips_operand_array
*
2242 insn_operands (const struct mips_cl_insn
*insn
)
2244 if (insn
->insn_mo
>= &mips_opcodes
[0]
2245 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2246 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2248 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2249 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2250 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2252 if (insn
->insn_mo
>= µmips_opcodes
[0]
2253 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2254 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2259 /* Get a description of operand OPNO of INSN. */
2261 static const struct mips_operand
*
2262 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2264 const struct mips_operand_array
*operands
;
2266 operands
= insn_operands (insn
);
2267 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2269 return operands
->operand
[opno
];
2272 /* Install UVAL as the value of OPERAND in INSN. */
2275 insn_insert_operand (struct mips_cl_insn
*insn
,
2276 const struct mips_operand
*operand
, unsigned int uval
)
2278 if (mips_opts
.mips16
2279 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2280 && mips_opcode_32bit_p (insn
->insn_mo
))
2281 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2283 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2286 /* Extract the value of OPERAND from INSN. */
2288 static inline unsigned
2289 insn_extract_operand (const struct mips_cl_insn
*insn
,
2290 const struct mips_operand
*operand
)
2292 return mips_extract_operand (operand
, insn
->insn_opcode
);
2295 /* Record the current MIPS16/microMIPS mode in now_seg. */
2298 mips_record_compressed_mode (void)
2300 segment_info_type
*si
;
2302 si
= seg_info (now_seg
);
2303 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2304 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2305 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2306 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2309 /* Read a standard MIPS instruction from BUF. */
2311 static unsigned long
2312 read_insn (char *buf
)
2314 if (target_big_endian
)
2315 return bfd_getb32 ((bfd_byte
*) buf
);
2317 return bfd_getl32 ((bfd_byte
*) buf
);
2320 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2324 write_insn (char *buf
, unsigned int insn
)
2326 md_number_to_chars (buf
, insn
, 4);
2330 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2331 has length LENGTH. */
2333 static unsigned long
2334 read_compressed_insn (char *buf
, unsigned int length
)
2340 for (i
= 0; i
< length
; i
+= 2)
2343 if (target_big_endian
)
2344 insn
|= bfd_getb16 ((char *) buf
);
2346 insn
|= bfd_getl16 ((char *) buf
);
2352 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2353 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2356 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2360 for (i
= 0; i
< length
; i
+= 2)
2361 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2362 return buf
+ length
;
2365 /* Install INSN at the location specified by its "frag" and "where" fields. */
2368 install_insn (const struct mips_cl_insn
*insn
)
2370 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2371 if (HAVE_CODE_COMPRESSION
)
2372 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2374 write_insn (f
, insn
->insn_opcode
);
2375 mips_record_compressed_mode ();
2378 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2379 and install the opcode in the new location. */
2382 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2387 insn
->where
= where
;
2388 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2389 if (insn
->fixp
[i
] != NULL
)
2391 insn
->fixp
[i
]->fx_frag
= frag
;
2392 insn
->fixp
[i
]->fx_where
= where
;
2394 install_insn (insn
);
2397 /* Add INSN to the end of the output. */
2400 add_fixed_insn (struct mips_cl_insn
*insn
)
2402 char *f
= frag_more (insn_length (insn
));
2403 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2406 /* Start a variant frag and move INSN to the start of the variant part,
2407 marking it as fixed. The other arguments are as for frag_var. */
2410 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2411 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2413 frag_grow (max_chars
);
2414 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2416 frag_var (rs_machine_dependent
, max_chars
, var
,
2417 subtype
, symbol
, offset
, NULL
);
2420 /* Insert N copies of INSN into the history buffer, starting at
2421 position FIRST. Neither FIRST nor N need to be clipped. */
2424 insert_into_history (unsigned int first
, unsigned int n
,
2425 const struct mips_cl_insn
*insn
)
2427 if (mips_relax
.sequence
!= 2)
2431 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2433 history
[i
] = history
[i
- n
];
2439 /* Clear the error in insn_error. */
2442 clear_insn_error (void)
2444 memset (&insn_error
, 0, sizeof (insn_error
));
2447 /* Possibly record error message MSG for the current instruction.
2448 If the error is about a particular argument, ARGNUM is the 1-based
2449 number of that argument, otherwise it is 0. FORMAT is the format
2450 of MSG. Return true if MSG was used, false if the current message
2454 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2459 /* Give priority to errors against specific arguments, and to
2460 the first whole-instruction message. */
2466 /* Keep insn_error if it is against a later argument. */
2467 if (argnum
< insn_error
.min_argnum
)
2470 /* If both errors are against the same argument but are different,
2471 give up on reporting a specific error for this argument.
2472 See the comment about mips_insn_error for details. */
2473 if (argnum
== insn_error
.min_argnum
2475 && strcmp (insn_error
.msg
, msg
) != 0)
2478 insn_error
.min_argnum
+= 1;
2482 insn_error
.min_argnum
= argnum
;
2483 insn_error
.format
= format
;
2484 insn_error
.msg
= msg
;
2488 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2489 as for set_insn_error_format. */
2492 set_insn_error (int argnum
, const char *msg
)
2494 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2497 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2498 as for set_insn_error_format. */
2501 set_insn_error_i (int argnum
, const char *msg
, int i
)
2503 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2507 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2508 are as for set_insn_error_format. */
2511 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2513 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2515 insn_error
.u
.ss
[0] = s1
;
2516 insn_error
.u
.ss
[1] = s2
;
2520 /* Report the error in insn_error, which is against assembly code STR. */
2523 report_insn_error (const char *str
)
2525 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2527 switch (insn_error
.format
)
2534 as_bad (msg
, insn_error
.u
.i
, str
);
2538 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2542 free ((char *) msg
);
2545 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2546 the idea is to make it obvious at a glance that each errata is
2550 init_vr4120_conflicts (void)
2552 #define CONFLICT(FIRST, SECOND) \
2553 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2555 /* Errata 21 - [D]DIV[U] after [D]MACC */
2556 CONFLICT (MACC
, DIV
);
2557 CONFLICT (DMACC
, DIV
);
2559 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2560 CONFLICT (DMULT
, DMULT
);
2561 CONFLICT (DMULT
, DMACC
);
2562 CONFLICT (DMACC
, DMULT
);
2563 CONFLICT (DMACC
, DMACC
);
2565 /* Errata 24 - MT{LO,HI} after [D]MACC */
2566 CONFLICT (MACC
, MTHILO
);
2567 CONFLICT (DMACC
, MTHILO
);
2569 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2570 instruction is executed immediately after a MACC or DMACC
2571 instruction, the result of [either instruction] is incorrect." */
2572 CONFLICT (MACC
, MULT
);
2573 CONFLICT (MACC
, DMULT
);
2574 CONFLICT (DMACC
, MULT
);
2575 CONFLICT (DMACC
, DMULT
);
2577 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2578 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2579 DDIV or DDIVU instruction, the result of the MACC or
2580 DMACC instruction is incorrect.". */
2581 CONFLICT (DMULT
, MACC
);
2582 CONFLICT (DMULT
, DMACC
);
2583 CONFLICT (DIV
, MACC
);
2584 CONFLICT (DIV
, DMACC
);
2594 #define RNUM_MASK 0x00000ff
2595 #define RTYPE_MASK 0x0ffff00
2596 #define RTYPE_NUM 0x0000100
2597 #define RTYPE_FPU 0x0000200
2598 #define RTYPE_FCC 0x0000400
2599 #define RTYPE_VEC 0x0000800
2600 #define RTYPE_GP 0x0001000
2601 #define RTYPE_CP0 0x0002000
2602 #define RTYPE_PC 0x0004000
2603 #define RTYPE_ACC 0x0008000
2604 #define RTYPE_CCC 0x0010000
2605 #define RTYPE_VI 0x0020000
2606 #define RTYPE_VF 0x0040000
2607 #define RTYPE_R5900_I 0x0080000
2608 #define RTYPE_R5900_Q 0x0100000
2609 #define RTYPE_R5900_R 0x0200000
2610 #define RTYPE_R5900_ACC 0x0400000
2611 #define RTYPE_MSA 0x0800000
2612 #define RWARN 0x8000000
2614 #define GENERIC_REGISTER_NUMBERS \
2615 {"$0", RTYPE_NUM | 0}, \
2616 {"$1", RTYPE_NUM | 1}, \
2617 {"$2", RTYPE_NUM | 2}, \
2618 {"$3", RTYPE_NUM | 3}, \
2619 {"$4", RTYPE_NUM | 4}, \
2620 {"$5", RTYPE_NUM | 5}, \
2621 {"$6", RTYPE_NUM | 6}, \
2622 {"$7", RTYPE_NUM | 7}, \
2623 {"$8", RTYPE_NUM | 8}, \
2624 {"$9", RTYPE_NUM | 9}, \
2625 {"$10", RTYPE_NUM | 10}, \
2626 {"$11", RTYPE_NUM | 11}, \
2627 {"$12", RTYPE_NUM | 12}, \
2628 {"$13", RTYPE_NUM | 13}, \
2629 {"$14", RTYPE_NUM | 14}, \
2630 {"$15", RTYPE_NUM | 15}, \
2631 {"$16", RTYPE_NUM | 16}, \
2632 {"$17", RTYPE_NUM | 17}, \
2633 {"$18", RTYPE_NUM | 18}, \
2634 {"$19", RTYPE_NUM | 19}, \
2635 {"$20", RTYPE_NUM | 20}, \
2636 {"$21", RTYPE_NUM | 21}, \
2637 {"$22", RTYPE_NUM | 22}, \
2638 {"$23", RTYPE_NUM | 23}, \
2639 {"$24", RTYPE_NUM | 24}, \
2640 {"$25", RTYPE_NUM | 25}, \
2641 {"$26", RTYPE_NUM | 26}, \
2642 {"$27", RTYPE_NUM | 27}, \
2643 {"$28", RTYPE_NUM | 28}, \
2644 {"$29", RTYPE_NUM | 29}, \
2645 {"$30", RTYPE_NUM | 30}, \
2646 {"$31", RTYPE_NUM | 31}
2648 #define FPU_REGISTER_NAMES \
2649 {"$f0", RTYPE_FPU | 0}, \
2650 {"$f1", RTYPE_FPU | 1}, \
2651 {"$f2", RTYPE_FPU | 2}, \
2652 {"$f3", RTYPE_FPU | 3}, \
2653 {"$f4", RTYPE_FPU | 4}, \
2654 {"$f5", RTYPE_FPU | 5}, \
2655 {"$f6", RTYPE_FPU | 6}, \
2656 {"$f7", RTYPE_FPU | 7}, \
2657 {"$f8", RTYPE_FPU | 8}, \
2658 {"$f9", RTYPE_FPU | 9}, \
2659 {"$f10", RTYPE_FPU | 10}, \
2660 {"$f11", RTYPE_FPU | 11}, \
2661 {"$f12", RTYPE_FPU | 12}, \
2662 {"$f13", RTYPE_FPU | 13}, \
2663 {"$f14", RTYPE_FPU | 14}, \
2664 {"$f15", RTYPE_FPU | 15}, \
2665 {"$f16", RTYPE_FPU | 16}, \
2666 {"$f17", RTYPE_FPU | 17}, \
2667 {"$f18", RTYPE_FPU | 18}, \
2668 {"$f19", RTYPE_FPU | 19}, \
2669 {"$f20", RTYPE_FPU | 20}, \
2670 {"$f21", RTYPE_FPU | 21}, \
2671 {"$f22", RTYPE_FPU | 22}, \
2672 {"$f23", RTYPE_FPU | 23}, \
2673 {"$f24", RTYPE_FPU | 24}, \
2674 {"$f25", RTYPE_FPU | 25}, \
2675 {"$f26", RTYPE_FPU | 26}, \
2676 {"$f27", RTYPE_FPU | 27}, \
2677 {"$f28", RTYPE_FPU | 28}, \
2678 {"$f29", RTYPE_FPU | 29}, \
2679 {"$f30", RTYPE_FPU | 30}, \
2680 {"$f31", RTYPE_FPU | 31}
2682 #define FPU_CONDITION_CODE_NAMES \
2683 {"$fcc0", RTYPE_FCC | 0}, \
2684 {"$fcc1", RTYPE_FCC | 1}, \
2685 {"$fcc2", RTYPE_FCC | 2}, \
2686 {"$fcc3", RTYPE_FCC | 3}, \
2687 {"$fcc4", RTYPE_FCC | 4}, \
2688 {"$fcc5", RTYPE_FCC | 5}, \
2689 {"$fcc6", RTYPE_FCC | 6}, \
2690 {"$fcc7", RTYPE_FCC | 7}
2692 #define COPROC_CONDITION_CODE_NAMES \
2693 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2694 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2695 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2696 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2697 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2698 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2699 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2700 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2702 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2703 {"$a4", RTYPE_GP | 8}, \
2704 {"$a5", RTYPE_GP | 9}, \
2705 {"$a6", RTYPE_GP | 10}, \
2706 {"$a7", RTYPE_GP | 11}, \
2707 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2708 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2709 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2710 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2711 {"$t0", RTYPE_GP | 12}, \
2712 {"$t1", RTYPE_GP | 13}, \
2713 {"$t2", RTYPE_GP | 14}, \
2714 {"$t3", RTYPE_GP | 15}
2716 #define O32_SYMBOLIC_REGISTER_NAMES \
2717 {"$t0", RTYPE_GP | 8}, \
2718 {"$t1", RTYPE_GP | 9}, \
2719 {"$t2", RTYPE_GP | 10}, \
2720 {"$t3", RTYPE_GP | 11}, \
2721 {"$t4", RTYPE_GP | 12}, \
2722 {"$t5", RTYPE_GP | 13}, \
2723 {"$t6", RTYPE_GP | 14}, \
2724 {"$t7", RTYPE_GP | 15}, \
2725 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2726 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2727 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2728 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2730 /* Remaining symbolic register names */
2731 #define SYMBOLIC_REGISTER_NAMES \
2732 {"$zero", RTYPE_GP | 0}, \
2733 {"$at", RTYPE_GP | 1}, \
2734 {"$AT", RTYPE_GP | 1}, \
2735 {"$v0", RTYPE_GP | 2}, \
2736 {"$v1", RTYPE_GP | 3}, \
2737 {"$a0", RTYPE_GP | 4}, \
2738 {"$a1", RTYPE_GP | 5}, \
2739 {"$a2", RTYPE_GP | 6}, \
2740 {"$a3", RTYPE_GP | 7}, \
2741 {"$s0", RTYPE_GP | 16}, \
2742 {"$s1", RTYPE_GP | 17}, \
2743 {"$s2", RTYPE_GP | 18}, \
2744 {"$s3", RTYPE_GP | 19}, \
2745 {"$s4", RTYPE_GP | 20}, \
2746 {"$s5", RTYPE_GP | 21}, \
2747 {"$s6", RTYPE_GP | 22}, \
2748 {"$s7", RTYPE_GP | 23}, \
2749 {"$t8", RTYPE_GP | 24}, \
2750 {"$t9", RTYPE_GP | 25}, \
2751 {"$k0", RTYPE_GP | 26}, \
2752 {"$kt0", RTYPE_GP | 26}, \
2753 {"$k1", RTYPE_GP | 27}, \
2754 {"$kt1", RTYPE_GP | 27}, \
2755 {"$gp", RTYPE_GP | 28}, \
2756 {"$sp", RTYPE_GP | 29}, \
2757 {"$s8", RTYPE_GP | 30}, \
2758 {"$fp", RTYPE_GP | 30}, \
2759 {"$ra", RTYPE_GP | 31}
2761 #define MIPS16_SPECIAL_REGISTER_NAMES \
2762 {"$pc", RTYPE_PC | 0}
2764 #define MDMX_VECTOR_REGISTER_NAMES \
2765 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2766 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2767 {"$v2", RTYPE_VEC | 2}, \
2768 {"$v3", RTYPE_VEC | 3}, \
2769 {"$v4", RTYPE_VEC | 4}, \
2770 {"$v5", RTYPE_VEC | 5}, \
2771 {"$v6", RTYPE_VEC | 6}, \
2772 {"$v7", RTYPE_VEC | 7}, \
2773 {"$v8", RTYPE_VEC | 8}, \
2774 {"$v9", RTYPE_VEC | 9}, \
2775 {"$v10", RTYPE_VEC | 10}, \
2776 {"$v11", RTYPE_VEC | 11}, \
2777 {"$v12", RTYPE_VEC | 12}, \
2778 {"$v13", RTYPE_VEC | 13}, \
2779 {"$v14", RTYPE_VEC | 14}, \
2780 {"$v15", RTYPE_VEC | 15}, \
2781 {"$v16", RTYPE_VEC | 16}, \
2782 {"$v17", RTYPE_VEC | 17}, \
2783 {"$v18", RTYPE_VEC | 18}, \
2784 {"$v19", RTYPE_VEC | 19}, \
2785 {"$v20", RTYPE_VEC | 20}, \
2786 {"$v21", RTYPE_VEC | 21}, \
2787 {"$v22", RTYPE_VEC | 22}, \
2788 {"$v23", RTYPE_VEC | 23}, \
2789 {"$v24", RTYPE_VEC | 24}, \
2790 {"$v25", RTYPE_VEC | 25}, \
2791 {"$v26", RTYPE_VEC | 26}, \
2792 {"$v27", RTYPE_VEC | 27}, \
2793 {"$v28", RTYPE_VEC | 28}, \
2794 {"$v29", RTYPE_VEC | 29}, \
2795 {"$v30", RTYPE_VEC | 30}, \
2796 {"$v31", RTYPE_VEC | 31}
2798 #define R5900_I_NAMES \
2799 {"$I", RTYPE_R5900_I | 0}
2801 #define R5900_Q_NAMES \
2802 {"$Q", RTYPE_R5900_Q | 0}
2804 #define R5900_R_NAMES \
2805 {"$R", RTYPE_R5900_R | 0}
2807 #define R5900_ACC_NAMES \
2808 {"$ACC", RTYPE_R5900_ACC | 0 }
2810 #define MIPS_DSP_ACCUMULATOR_NAMES \
2811 {"$ac0", RTYPE_ACC | 0}, \
2812 {"$ac1", RTYPE_ACC | 1}, \
2813 {"$ac2", RTYPE_ACC | 2}, \
2814 {"$ac3", RTYPE_ACC | 3}
2816 static const struct regname reg_names
[] = {
2817 GENERIC_REGISTER_NUMBERS
,
2819 FPU_CONDITION_CODE_NAMES
,
2820 COPROC_CONDITION_CODE_NAMES
,
2822 /* The $txx registers depends on the abi,
2823 these will be added later into the symbol table from
2824 one of the tables below once mips_abi is set after
2825 parsing of arguments from the command line. */
2826 SYMBOLIC_REGISTER_NAMES
,
2828 MIPS16_SPECIAL_REGISTER_NAMES
,
2829 MDMX_VECTOR_REGISTER_NAMES
,
2834 MIPS_DSP_ACCUMULATOR_NAMES
,
2838 static const struct regname reg_names_o32
[] = {
2839 O32_SYMBOLIC_REGISTER_NAMES
,
2843 static const struct regname reg_names_n32n64
[] = {
2844 N32N64_SYMBOLIC_REGISTER_NAMES
,
2848 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2849 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2850 of these register symbols, return the associated vector register,
2851 otherwise return SYMVAL itself. */
2854 mips_prefer_vec_regno (unsigned int symval
)
2856 if ((symval
& -2) == (RTYPE_GP
| 2))
2857 return RTYPE_VEC
| (symval
& 1);
2861 /* Return true if string [S, E) is a valid register name, storing its
2862 symbol value in *SYMVAL_PTR if so. */
2865 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2870 /* Terminate name. */
2874 /* Look up the name. */
2875 symbol
= symbol_find (s
);
2878 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2881 *symval_ptr
= S_GET_VALUE (symbol
);
2885 /* Return true if the string at *SPTR is a valid register name. Allow it
2886 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2889 When returning true, move *SPTR past the register, store the
2890 register's symbol value in *SYMVAL_PTR and the channel mask in
2891 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2892 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2893 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2896 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2897 unsigned int *channels_ptr
)
2901 unsigned int channels
, symval
, bit
;
2903 /* Find end of name. */
2905 if (is_name_beginner (*e
))
2907 while (is_part_of_name (*e
))
2911 if (!mips_parse_register_1 (s
, e
, &symval
))
2916 /* Eat characters from the end of the string that are valid
2917 channel suffixes. The preceding register must be $ACC or
2918 end with a digit, so there is no ambiguity. */
2921 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2922 if (m
> s
&& m
[-1] == *q
)
2929 || !mips_parse_register_1 (s
, m
, &symval
)
2930 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2935 *symval_ptr
= symval
;
2937 *channels_ptr
= channels
;
2941 /* Check if SPTR points at a valid register specifier according to TYPES.
2942 If so, then return 1, advance S to consume the specifier and store
2943 the register's number in REGNOP, otherwise return 0. */
2946 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2950 if (mips_parse_register (s
, ®no
, NULL
))
2952 if (types
& RTYPE_VEC
)
2953 regno
= mips_prefer_vec_regno (regno
);
2962 as_warn (_("unrecognized register name `%s'"), *s
);
2967 return regno
<= RNUM_MASK
;
2970 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2971 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2974 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2979 for (i
= 0; i
< 4; i
++)
2980 if (*s
== "xyzw"[i
])
2982 *channels
|= 1 << (3 - i
);
2988 /* Token types for parsed operand lists. */
2989 enum mips_operand_token_type
{
2990 /* A plain register, e.g. $f2. */
2993 /* A 4-bit XYZW channel mask. */
2996 /* A constant vector index, e.g. [1]. */
2999 /* A register vector index, e.g. [$2]. */
3002 /* A continuous range of registers, e.g. $s0-$s4. */
3005 /* A (possibly relocated) expression. */
3008 /* A floating-point value. */
3011 /* A single character. This can be '(', ')' or ',', but '(' only appears
3015 /* A doubled character, either "--" or "++". */
3018 /* The end of the operand list. */
3022 /* A parsed operand token. */
3023 struct mips_operand_token
3025 /* The type of token. */
3026 enum mips_operand_token_type type
;
3029 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3032 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3033 unsigned int channels
;
3035 /* The integer value of an OT_INTEGER_INDEX. */
3038 /* The two register symbol values involved in an OT_REG_RANGE. */
3040 unsigned int regno1
;
3041 unsigned int regno2
;
3044 /* The value of an OT_INTEGER. The value is represented as an
3045 expression and the relocation operators that were applied to
3046 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3047 relocation operators were used. */
3050 bfd_reloc_code_real_type relocs
[3];
3053 /* The binary data for an OT_FLOAT constant, and the number of bytes
3056 unsigned char data
[8];
3060 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3065 /* An obstack used to construct lists of mips_operand_tokens. */
3066 static struct obstack mips_operand_tokens
;
3068 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3071 mips_add_token (struct mips_operand_token
*token
,
3072 enum mips_operand_token_type type
)
3075 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3078 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3079 and OT_REG tokens for them if so, and return a pointer to the first
3080 unconsumed character. Return null otherwise. */
3083 mips_parse_base_start (char *s
)
3085 struct mips_operand_token token
;
3086 unsigned int regno
, channels
;
3087 bfd_boolean decrement_p
;
3093 SKIP_SPACE_TABS (s
);
3095 /* Only match "--" as part of a base expression. In other contexts "--X"
3096 is a double negative. */
3097 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3101 SKIP_SPACE_TABS (s
);
3104 /* Allow a channel specifier because that leads to better error messages
3105 than treating something like "$vf0x++" as an expression. */
3106 if (!mips_parse_register (&s
, ®no
, &channels
))
3110 mips_add_token (&token
, OT_CHAR
);
3115 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3118 token
.u
.regno
= regno
;
3119 mips_add_token (&token
, OT_REG
);
3123 token
.u
.channels
= channels
;
3124 mips_add_token (&token
, OT_CHANNELS
);
3127 /* For consistency, only match "++" as part of base expressions too. */
3128 SKIP_SPACE_TABS (s
);
3129 if (s
[0] == '+' && s
[1] == '+')
3133 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3139 /* Parse one or more tokens from S. Return a pointer to the first
3140 unconsumed character on success. Return null if an error was found
3141 and store the error text in insn_error. FLOAT_FORMAT is as for
3142 mips_parse_arguments. */
3145 mips_parse_argument_token (char *s
, char float_format
)
3147 char *end
, *save_in
;
3149 unsigned int regno1
, regno2
, channels
;
3150 struct mips_operand_token token
;
3152 /* First look for "($reg", since we want to treat that as an
3153 OT_CHAR and OT_REG rather than an expression. */
3154 end
= mips_parse_base_start (s
);
3158 /* Handle other characters that end up as OT_CHARs. */
3159 if (*s
== ')' || *s
== ',')
3162 mips_add_token (&token
, OT_CHAR
);
3167 /* Handle tokens that start with a register. */
3168 if (mips_parse_register (&s
, ®no1
, &channels
))
3172 /* A register and a VU0 channel suffix. */
3173 token
.u
.regno
= regno1
;
3174 mips_add_token (&token
, OT_REG
);
3176 token
.u
.channels
= channels
;
3177 mips_add_token (&token
, OT_CHANNELS
);
3181 SKIP_SPACE_TABS (s
);
3184 /* A register range. */
3186 SKIP_SPACE_TABS (s
);
3187 if (!mips_parse_register (&s
, ®no2
, NULL
))
3189 set_insn_error (0, _("invalid register range"));
3193 token
.u
.reg_range
.regno1
= regno1
;
3194 token
.u
.reg_range
.regno2
= regno2
;
3195 mips_add_token (&token
, OT_REG_RANGE
);
3199 /* Add the register itself. */
3200 token
.u
.regno
= regno1
;
3201 mips_add_token (&token
, OT_REG
);
3203 /* Check for a vector index. */
3207 SKIP_SPACE_TABS (s
);
3208 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3209 mips_add_token (&token
, OT_REG_INDEX
);
3212 expressionS element
;
3214 my_getExpression (&element
, s
);
3215 if (element
.X_op
!= O_constant
)
3217 set_insn_error (0, _("vector element must be constant"));
3221 token
.u
.index
= element
.X_add_number
;
3222 mips_add_token (&token
, OT_INTEGER_INDEX
);
3224 SKIP_SPACE_TABS (s
);
3227 set_insn_error (0, _("missing `]'"));
3237 /* First try to treat expressions as floats. */
3238 save_in
= input_line_pointer
;
3239 input_line_pointer
= s
;
3240 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3241 &token
.u
.flt
.length
);
3242 end
= input_line_pointer
;
3243 input_line_pointer
= save_in
;
3246 set_insn_error (0, err
);
3251 mips_add_token (&token
, OT_FLOAT
);
3256 /* Treat everything else as an integer expression. */
3257 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3258 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3259 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3260 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3262 mips_add_token (&token
, OT_INTEGER
);
3266 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3267 if expressions should be treated as 32-bit floating-point constants,
3268 'd' if they should be treated as 64-bit floating-point constants,
3269 or 0 if they should be treated as integer expressions (the usual case).
3271 Return a list of tokens on success, otherwise return 0. The caller
3272 must obstack_free the list after use. */
3274 static struct mips_operand_token
*
3275 mips_parse_arguments (char *s
, char float_format
)
3277 struct mips_operand_token token
;
3279 SKIP_SPACE_TABS (s
);
3282 s
= mips_parse_argument_token (s
, float_format
);
3285 obstack_free (&mips_operand_tokens
,
3286 obstack_finish (&mips_operand_tokens
));
3289 SKIP_SPACE_TABS (s
);
3291 mips_add_token (&token
, OT_END
);
3292 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3295 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3296 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3299 is_opcode_valid (const struct mips_opcode
*mo
)
3301 int isa
= mips_opts
.isa
;
3302 int ase
= mips_opts
.ase
;
3306 if (ISA_HAS_64BIT_REGS (isa
))
3307 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3308 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3309 ase
|= mips_ases
[i
].flags64
;
3311 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3314 /* Check whether the instruction or macro requires single-precision or
3315 double-precision floating-point support. Note that this information is
3316 stored differently in the opcode table for insns and macros. */
3317 if (mo
->pinfo
== INSN_MACRO
)
3319 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3320 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3324 fp_s
= mo
->pinfo
& FP_S
;
3325 fp_d
= mo
->pinfo
& FP_D
;
3328 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3331 if (fp_s
&& mips_opts
.soft_float
)
3337 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3338 selected ISA and architecture. */
3341 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3343 int isa
= mips_opts
.isa
;
3344 int ase
= mips_opts
.ase
;
3347 if (ISA_HAS_64BIT_REGS (isa
))
3348 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3349 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3350 ase
|= mips_ases
[i
].flags64
;
3352 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3355 /* Return TRUE if the size of the microMIPS opcode MO matches one
3356 explicitly requested. Always TRUE in the standard MIPS mode.
3357 Use is_size_valid_16 for MIPS16 opcodes. */
3360 is_size_valid (const struct mips_opcode
*mo
)
3362 if (!mips_opts
.micromips
)
3365 if (mips_opts
.insn32
)
3367 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3369 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3372 if (!forced_insn_length
)
3374 if (mo
->pinfo
== INSN_MACRO
)
3376 return forced_insn_length
== micromips_insn_length (mo
);
3379 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3380 explicitly requested. */
3383 is_size_valid_16 (const struct mips_opcode
*mo
)
3385 if (!forced_insn_length
)
3387 if (mo
->pinfo
== INSN_MACRO
)
3389 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3391 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3396 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3397 of the preceding instruction. Always TRUE in the standard MIPS mode.
3399 We don't accept macros in 16-bit delay slots to avoid a case where
3400 a macro expansion fails because it relies on a preceding 32-bit real
3401 instruction to have matched and does not handle the operands correctly.
3402 The only macros that may expand to 16-bit instructions are JAL that
3403 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3404 and BGT (that likewise cannot be placed in a delay slot) that decay to
3405 a NOP. In all these cases the macros precede any corresponding real
3406 instruction definitions in the opcode table, so they will match in the
3407 second pass where the size of the delay slot is ignored and therefore
3408 produce correct code. */
3411 is_delay_slot_valid (const struct mips_opcode
*mo
)
3413 if (!mips_opts
.micromips
)
3416 if (mo
->pinfo
== INSN_MACRO
)
3417 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3418 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3419 && micromips_insn_length (mo
) != 4)
3421 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3422 && micromips_insn_length (mo
) != 2)
3428 /* For consistency checking, verify that all bits of OPCODE are specified
3429 either by the match/mask part of the instruction definition, or by the
3430 operand list. Also build up a list of operands in OPERANDS.
3432 INSN_BITS says which bits of the instruction are significant.
3433 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3434 provides the mips_operand description of each operand. DECODE_OPERAND
3435 is null for MIPS16 instructions. */
3438 validate_mips_insn (const struct mips_opcode
*opcode
,
3439 unsigned long insn_bits
,
3440 const struct mips_operand
*(*decode_operand
) (const char *),
3441 struct mips_operand_array
*operands
)
3444 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3445 const struct mips_operand
*operand
;
3447 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3448 if ((mask
& opcode
->match
) != opcode
->match
)
3450 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3451 opcode
->name
, opcode
->args
);
3456 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3457 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3458 for (s
= opcode
->args
; *s
; ++s
)
3471 if (!decode_operand
)
3472 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3474 operand
= decode_operand (s
);
3475 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3477 as_bad (_("internal: unknown operand type: %s %s"),
3478 opcode
->name
, opcode
->args
);
3481 gas_assert (opno
< MAX_OPERANDS
);
3482 operands
->operand
[opno
] = operand
;
3483 if (!decode_operand
&& operand
3484 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3485 && mips_opcode_32bit_p (opcode
))
3486 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3487 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3489 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3490 if (operand
->type
== OP_MDMX_IMM_REG
)
3491 /* Bit 5 is the format selector (OB vs QH). The opcode table
3492 has separate entries for each format. */
3493 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3494 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3495 used_bits
&= ~(mask
& 0x700);
3496 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3497 operand field that cannot be fully described with LSB/SIZE. */
3498 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3499 used_bits
&= ~0x6000;
3501 /* Skip prefix characters. */
3502 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3507 doubled
= used_bits
& mask
& insn_bits
;
3510 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3511 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3515 undefined
= ~used_bits
& insn_bits
;
3516 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3518 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3519 undefined
, opcode
->name
, opcode
->args
);
3522 used_bits
&= ~insn_bits
;
3525 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3526 used_bits
, opcode
->name
, opcode
->args
);
3532 /* The MIPS16 version of validate_mips_insn. */
3535 validate_mips16_insn (const struct mips_opcode
*opcode
,
3536 struct mips_operand_array
*operands
)
3538 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3540 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3543 /* The microMIPS version of validate_mips_insn. */
3546 validate_micromips_insn (const struct mips_opcode
*opc
,
3547 struct mips_operand_array
*operands
)
3549 unsigned long insn_bits
;
3550 unsigned long major
;
3551 unsigned int length
;
3553 if (opc
->pinfo
== INSN_MACRO
)
3554 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3557 length
= micromips_insn_length (opc
);
3558 if (length
!= 2 && length
!= 4)
3560 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3561 "%s %s"), length
, opc
->name
, opc
->args
);
3564 major
= opc
->match
>> (10 + 8 * (length
- 2));
3565 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3566 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3568 as_bad (_("internal error: bad microMIPS opcode "
3569 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3573 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3574 insn_bits
= 1 << 4 * length
;
3575 insn_bits
<<= 4 * length
;
3577 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3581 /* This function is called once, at assembler startup time. It should set up
3582 all the tables, etc. that the MD part of the assembler will need. */
3587 const char *retval
= NULL
;
3591 if (mips_pic
!= NO_PIC
)
3593 if (g_switch_seen
&& g_switch_value
!= 0)
3594 as_bad (_("-G may not be used in position-independent code"));
3597 else if (mips_abicalls
)
3599 if (g_switch_seen
&& g_switch_value
!= 0)
3600 as_bad (_("-G may not be used with abicalls"));
3604 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3605 as_warn (_("could not set architecture and machine"));
3607 op_hash
= hash_new ();
3609 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3610 for (i
= 0; i
< NUMOPCODES
;)
3612 const char *name
= mips_opcodes
[i
].name
;
3614 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3617 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3618 mips_opcodes
[i
].name
, retval
);
3619 /* Probably a memory allocation problem? Give up now. */
3620 as_fatal (_("broken assembler, no assembly attempted"));
3624 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3625 decode_mips_operand
, &mips_operands
[i
]))
3627 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3629 create_insn (&nop_insn
, mips_opcodes
+ i
);
3630 if (mips_fix_loongson2f_nop
)
3631 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3632 nop_insn
.fixed_p
= 1;
3636 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3639 mips16_op_hash
= hash_new ();
3640 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3641 bfd_mips16_num_opcodes
);
3644 while (i
< bfd_mips16_num_opcodes
)
3646 const char *name
= mips16_opcodes
[i
].name
;
3648 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3650 as_fatal (_("internal: can't hash `%s': %s"),
3651 mips16_opcodes
[i
].name
, retval
);
3654 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3656 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3658 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3659 mips16_nop_insn
.fixed_p
= 1;
3663 while (i
< bfd_mips16_num_opcodes
3664 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3667 micromips_op_hash
= hash_new ();
3668 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3669 bfd_micromips_num_opcodes
);
3672 while (i
< bfd_micromips_num_opcodes
)
3674 const char *name
= micromips_opcodes
[i
].name
;
3676 retval
= hash_insert (micromips_op_hash
, name
,
3677 (void *) µmips_opcodes
[i
]);
3679 as_fatal (_("internal: can't hash `%s': %s"),
3680 micromips_opcodes
[i
].name
, retval
);
3683 struct mips_cl_insn
*micromips_nop_insn
;
3685 if (!validate_micromips_insn (µmips_opcodes
[i
],
3686 µmips_operands
[i
]))
3689 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3691 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3692 micromips_nop_insn
= µmips_nop16_insn
;
3693 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3694 micromips_nop_insn
= µmips_nop32_insn
;
3698 if (micromips_nop_insn
->insn_mo
== NULL
3699 && strcmp (name
, "nop") == 0)
3701 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3702 micromips_nop_insn
->fixed_p
= 1;
3706 while (++i
< bfd_micromips_num_opcodes
3707 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3711 as_fatal (_("broken assembler, no assembly attempted"));
3713 /* We add all the general register names to the symbol table. This
3714 helps us detect invalid uses of them. */
3715 for (i
= 0; reg_names
[i
].name
; i
++)
3716 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3717 reg_names
[i
].num
, /* & RNUM_MASK, */
3718 &zero_address_frag
));
3720 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3721 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3722 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3723 &zero_address_frag
));
3725 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3726 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3727 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3728 &zero_address_frag
));
3730 for (i
= 0; i
< 32; i
++)
3734 /* R5900 VU0 floating-point register. */
3735 sprintf (regname
, "$vf%d", i
);
3736 symbol_table_insert (symbol_new (regname
, reg_section
,
3737 RTYPE_VF
| i
, &zero_address_frag
));
3739 /* R5900 VU0 integer register. */
3740 sprintf (regname
, "$vi%d", i
);
3741 symbol_table_insert (symbol_new (regname
, reg_section
,
3742 RTYPE_VI
| i
, &zero_address_frag
));
3745 sprintf (regname
, "$w%d", i
);
3746 symbol_table_insert (symbol_new (regname
, reg_section
,
3747 RTYPE_MSA
| i
, &zero_address_frag
));
3750 obstack_init (&mips_operand_tokens
);
3752 mips_no_prev_insn ();
3755 mips_cprmask
[0] = 0;
3756 mips_cprmask
[1] = 0;
3757 mips_cprmask
[2] = 0;
3758 mips_cprmask
[3] = 0;
3760 /* set the default alignment for the text section (2**2) */
3761 record_alignment (text_section
, 2);
3763 bfd_set_gp_size (stdoutput
, g_switch_value
);
3765 /* On a native system other than VxWorks, sections must be aligned
3766 to 16 byte boundaries. When configured for an embedded ELF
3767 target, we don't bother. */
3768 if (strncmp (TARGET_OS
, "elf", 3) != 0
3769 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3771 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3772 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3773 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3776 /* Create a .reginfo section for register masks and a .mdebug
3777 section for debugging information. */
3785 subseg
= now_subseg
;
3787 /* The ABI says this section should be loaded so that the
3788 running program can access it. However, we don't load it
3789 if we are configured for an embedded target */
3790 flags
= SEC_READONLY
| SEC_DATA
;
3791 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3792 flags
|= SEC_ALLOC
| SEC_LOAD
;
3794 if (mips_abi
!= N64_ABI
)
3796 sec
= subseg_new (".reginfo", (subsegT
) 0);
3798 bfd_set_section_flags (stdoutput
, sec
, flags
);
3799 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3801 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3805 /* The 64-bit ABI uses a .MIPS.options section rather than
3806 .reginfo section. */
3807 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3808 bfd_set_section_flags (stdoutput
, sec
, flags
);
3809 bfd_set_section_alignment (stdoutput
, sec
, 3);
3811 /* Set up the option header. */
3813 Elf_Internal_Options opthdr
;
3816 opthdr
.kind
= ODK_REGINFO
;
3817 opthdr
.size
= (sizeof (Elf_External_Options
)
3818 + sizeof (Elf64_External_RegInfo
));
3821 f
= frag_more (sizeof (Elf_External_Options
));
3822 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3823 (Elf_External_Options
*) f
);
3825 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3829 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3830 bfd_set_section_flags (stdoutput
, sec
,
3831 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3832 bfd_set_section_alignment (stdoutput
, sec
, 3);
3833 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3835 if (ECOFF_DEBUGGING
)
3837 sec
= subseg_new (".mdebug", (subsegT
) 0);
3838 (void) bfd_set_section_flags (stdoutput
, sec
,
3839 SEC_HAS_CONTENTS
| SEC_READONLY
);
3840 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3842 else if (mips_flag_pdr
)
3844 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3845 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3846 SEC_READONLY
| SEC_RELOC
3848 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3851 subseg_set (seg
, subseg
);
3854 if (mips_fix_vr4120
)
3855 init_vr4120_conflicts ();
3859 fpabi_incompatible_with (int fpabi
, const char *what
)
3861 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3862 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3866 fpabi_requires (int fpabi
, const char *what
)
3868 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3869 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3872 /* Check -mabi and register sizes against the specified FP ABI. */
3874 check_fpabi (int fpabi
)
3878 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3879 if (file_mips_opts
.soft_float
)
3880 fpabi_incompatible_with (fpabi
, "softfloat");
3881 else if (file_mips_opts
.single_float
)
3882 fpabi_incompatible_with (fpabi
, "singlefloat");
3883 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3884 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3885 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3886 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3889 case Val_GNU_MIPS_ABI_FP_XX
:
3890 if (mips_abi
!= O32_ABI
)
3891 fpabi_requires (fpabi
, "-mabi=32");
3892 else if (file_mips_opts
.soft_float
)
3893 fpabi_incompatible_with (fpabi
, "softfloat");
3894 else if (file_mips_opts
.single_float
)
3895 fpabi_incompatible_with (fpabi
, "singlefloat");
3896 else if (file_mips_opts
.fp
!= 0)
3897 fpabi_requires (fpabi
, "fp=xx");
3900 case Val_GNU_MIPS_ABI_FP_64A
:
3901 case Val_GNU_MIPS_ABI_FP_64
:
3902 if (mips_abi
!= O32_ABI
)
3903 fpabi_requires (fpabi
, "-mabi=32");
3904 else if (file_mips_opts
.soft_float
)
3905 fpabi_incompatible_with (fpabi
, "softfloat");
3906 else if (file_mips_opts
.single_float
)
3907 fpabi_incompatible_with (fpabi
, "singlefloat");
3908 else if (file_mips_opts
.fp
!= 64)
3909 fpabi_requires (fpabi
, "fp=64");
3910 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3911 fpabi_incompatible_with (fpabi
, "nooddspreg");
3912 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3913 fpabi_requires (fpabi
, "nooddspreg");
3916 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3917 if (file_mips_opts
.soft_float
)
3918 fpabi_incompatible_with (fpabi
, "softfloat");
3919 else if (!file_mips_opts
.single_float
)
3920 fpabi_requires (fpabi
, "singlefloat");
3923 case Val_GNU_MIPS_ABI_FP_SOFT
:
3924 if (!file_mips_opts
.soft_float
)
3925 fpabi_requires (fpabi
, "softfloat");
3928 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3929 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3930 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3933 case Val_GNU_MIPS_ABI_FP_NAN2008
:
3934 /* Silently ignore compatibility value. */
3938 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3939 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3944 /* Perform consistency checks on the current options. */
3947 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3949 /* Check the size of integer registers agrees with the ABI and ISA. */
3950 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3951 as_bad (_("`gp=64' used with a 32-bit processor"));
3953 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3954 as_bad (_("`gp=32' used with a 64-bit ABI"));
3956 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3957 as_bad (_("`gp=64' used with a 32-bit ABI"));
3959 /* Check the size of the float registers agrees with the ABI and ISA. */
3963 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
3964 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3965 else if (opts
->single_float
== 1)
3966 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3969 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
3970 as_bad (_("`fp=64' used with a 32-bit fpu"));
3972 && ABI_NEEDS_32BIT_REGS (mips_abi
)
3973 && !ISA_HAS_MXHC1 (opts
->isa
))
3974 as_warn (_("`fp=64' used with a 32-bit ABI"));
3978 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3979 as_warn (_("`fp=32' used with a 64-bit ABI"));
3980 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
3981 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3984 as_bad (_("Unknown size of floating point registers"));
3988 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
3989 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3991 if (opts
->micromips
== 1 && opts
->mips16
== 1)
3992 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3993 else if (ISA_IS_R6 (opts
->isa
)
3994 && (opts
->micromips
== 1
3995 || opts
->mips16
== 1))
3996 as_fatal (_("`%s' cannot be used with `%s'"),
3997 opts
->micromips
? "micromips" : "mips16",
3998 mips_cpu_info_from_isa (opts
->isa
)->name
);
4000 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4001 as_fatal (_("branch relaxation is not supported in `%s'"),
4002 mips_cpu_info_from_isa (opts
->isa
)->name
);
4005 /* Perform consistency checks on the module level options exactly once.
4006 This is a deferred check that happens:
4007 at the first .set directive
4008 or, at the first pseudo op that generates code (inc .dc.a)
4009 or, at the first instruction
4013 file_mips_check_options (void)
4015 const struct mips_cpu_info
*arch_info
= 0;
4017 if (file_mips_opts_checked
)
4020 /* The following code determines the register size.
4021 Similar code was added to GCC 3.3 (see override_options() in
4022 config/mips/mips.c). The GAS and GCC code should be kept in sync
4023 as much as possible. */
4025 if (file_mips_opts
.gp
< 0)
4027 /* Infer the integer register size from the ABI and processor.
4028 Restrict ourselves to 32-bit registers if that's all the
4029 processor has, or if the ABI cannot handle 64-bit registers. */
4030 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4031 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4035 if (file_mips_opts
.fp
< 0)
4037 /* No user specified float register size.
4038 ??? GAS treats single-float processors as though they had 64-bit
4039 float registers (although it complains when double-precision
4040 instructions are used). As things stand, saying they have 32-bit
4041 registers would lead to spurious "register must be even" messages.
4042 So here we assume float registers are never smaller than the
4044 if (file_mips_opts
.gp
== 64)
4045 /* 64-bit integer registers implies 64-bit float registers. */
4046 file_mips_opts
.fp
= 64;
4047 else if ((file_mips_opts
.ase
& FP64_ASES
)
4048 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4049 /* Handle ASEs that require 64-bit float registers, if possible. */
4050 file_mips_opts
.fp
= 64;
4051 else if (ISA_IS_R6 (mips_opts
.isa
))
4052 /* R6 implies 64-bit float registers. */
4053 file_mips_opts
.fp
= 64;
4055 /* 32-bit float registers. */
4056 file_mips_opts
.fp
= 32;
4059 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
4061 /* Disable operations on odd-numbered floating-point registers by default
4062 when using the FPXX ABI. */
4063 if (file_mips_opts
.oddspreg
< 0)
4065 if (file_mips_opts
.fp
== 0)
4066 file_mips_opts
.oddspreg
= 0;
4068 file_mips_opts
.oddspreg
= 1;
4071 /* End of GCC-shared inference code. */
4073 /* This flag is set when we have a 64-bit capable CPU but use only
4074 32-bit wide registers. Note that EABI does not use it. */
4075 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4076 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4077 || mips_abi
== O32_ABI
))
4080 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4081 as_bad (_("trap exception not supported at ISA 1"));
4083 /* If the selected architecture includes support for ASEs, enable
4084 generation of code for them. */
4085 if (file_mips_opts
.mips16
== -1)
4086 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4087 if (file_mips_opts
.micromips
== -1)
4088 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4091 if (mips_nan2008
== -1)
4092 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4093 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4094 as_fatal (_("`%s' does not support legacy NaN"),
4095 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4097 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4098 being selected implicitly. */
4099 if (file_mips_opts
.fp
!= 64)
4100 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4102 /* If the user didn't explicitly select or deselect a particular ASE,
4103 use the default setting for the CPU. */
4104 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
4106 /* Set up the current options. These may change throughout assembly. */
4107 mips_opts
= file_mips_opts
;
4109 mips_check_isa_supports_ases ();
4110 mips_check_options (&file_mips_opts
, TRUE
);
4111 file_mips_opts_checked
= TRUE
;
4113 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4114 as_warn (_("could not set architecture and machine"));
4118 md_assemble (char *str
)
4120 struct mips_cl_insn insn
;
4121 bfd_reloc_code_real_type unused_reloc
[3]
4122 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4124 file_mips_check_options ();
4126 imm_expr
.X_op
= O_absent
;
4127 offset_expr
.X_op
= O_absent
;
4128 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4129 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4130 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4132 mips_mark_labels ();
4133 mips_assembling_insn
= TRUE
;
4134 clear_insn_error ();
4136 if (mips_opts
.mips16
)
4137 mips16_ip (str
, &insn
);
4140 mips_ip (str
, &insn
);
4141 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4142 str
, insn
.insn_opcode
));
4146 report_insn_error (str
);
4147 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4150 if (mips_opts
.mips16
)
4151 mips16_macro (&insn
);
4158 if (offset_expr
.X_op
!= O_absent
)
4159 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4161 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4164 mips_assembling_insn
= FALSE
;
4167 /* Convenience functions for abstracting away the differences between
4168 MIPS16 and non-MIPS16 relocations. */
4170 static inline bfd_boolean
4171 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4175 case BFD_RELOC_MIPS16_JMP
:
4176 case BFD_RELOC_MIPS16_GPREL
:
4177 case BFD_RELOC_MIPS16_GOT16
:
4178 case BFD_RELOC_MIPS16_CALL16
:
4179 case BFD_RELOC_MIPS16_HI16_S
:
4180 case BFD_RELOC_MIPS16_HI16
:
4181 case BFD_RELOC_MIPS16_LO16
:
4182 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4190 static inline bfd_boolean
4191 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4195 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4196 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4197 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4198 case BFD_RELOC_MICROMIPS_GPREL16
:
4199 case BFD_RELOC_MICROMIPS_JMP
:
4200 case BFD_RELOC_MICROMIPS_HI16
:
4201 case BFD_RELOC_MICROMIPS_HI16_S
:
4202 case BFD_RELOC_MICROMIPS_LO16
:
4203 case BFD_RELOC_MICROMIPS_LITERAL
:
4204 case BFD_RELOC_MICROMIPS_GOT16
:
4205 case BFD_RELOC_MICROMIPS_CALL16
:
4206 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4207 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4208 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4209 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4210 case BFD_RELOC_MICROMIPS_SUB
:
4211 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4212 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4213 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4214 case BFD_RELOC_MICROMIPS_HIGHEST
:
4215 case BFD_RELOC_MICROMIPS_HIGHER
:
4216 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4217 case BFD_RELOC_MICROMIPS_JALR
:
4225 static inline bfd_boolean
4226 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4228 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4231 static inline bfd_boolean
4232 b_reloc_p (bfd_reloc_code_real_type reloc
)
4234 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4235 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4236 || reloc
== BFD_RELOC_16_PCREL_S2
4237 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4238 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4239 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4240 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4243 static inline bfd_boolean
4244 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4246 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4247 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4250 static inline bfd_boolean
4251 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4253 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4254 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4257 static inline bfd_boolean
4258 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4260 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4261 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4264 static inline bfd_boolean
4265 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4267 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4270 static inline bfd_boolean
4271 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4273 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4274 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4277 /* Return true if RELOC is a PC-relative relocation that does not have
4278 full address range. */
4280 static inline bfd_boolean
4281 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4285 case BFD_RELOC_16_PCREL_S2
:
4286 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4287 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4288 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4289 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4290 case BFD_RELOC_MIPS_21_PCREL_S2
:
4291 case BFD_RELOC_MIPS_26_PCREL_S2
:
4292 case BFD_RELOC_MIPS_18_PCREL_S3
:
4293 case BFD_RELOC_MIPS_19_PCREL_S2
:
4296 case BFD_RELOC_32_PCREL
:
4297 case BFD_RELOC_HI16_S_PCREL
:
4298 case BFD_RELOC_LO16_PCREL
:
4299 return HAVE_64BIT_ADDRESSES
;
4306 /* Return true if the given relocation might need a matching %lo().
4307 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4308 need a matching %lo() when applied to local symbols. */
4310 static inline bfd_boolean
4311 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4313 return (HAVE_IN_PLACE_ADDENDS
4314 && (hi16_reloc_p (reloc
)
4315 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4316 all GOT16 relocations evaluate to "G". */
4317 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4320 /* Return the type of %lo() reloc needed by RELOC, given that
4321 reloc_needs_lo_p. */
4323 static inline bfd_reloc_code_real_type
4324 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4326 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4327 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4331 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4334 static inline bfd_boolean
4335 fixup_has_matching_lo_p (fixS
*fixp
)
4337 return (fixp
->fx_next
!= NULL
4338 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4339 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4340 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4343 /* Move all labels in LABELS to the current insertion point. TEXT_P
4344 says whether the labels refer to text or data. */
4347 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4349 struct insn_label_list
*l
;
4352 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4354 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4355 symbol_set_frag (l
->label
, frag_now
);
4356 val
= (valueT
) frag_now_fix ();
4357 /* MIPS16/microMIPS text labels are stored as odd. */
4358 if (text_p
&& HAVE_CODE_COMPRESSION
)
4360 S_SET_VALUE (l
->label
, val
);
4364 /* Move all labels in insn_labels to the current insertion point
4365 and treat them as text labels. */
4368 mips_move_text_labels (void)
4370 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4373 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4376 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4378 bfd_boolean linkonce
= FALSE
;
4379 segT symseg
= S_GET_SEGMENT (sym
);
4381 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4383 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4385 /* The GNU toolchain uses an extension for ELF: a section
4386 beginning with the magic string .gnu.linkonce is a
4387 linkonce section. */
4388 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4389 sizeof ".gnu.linkonce" - 1) == 0)
4395 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4396 linker to handle them specially, such as generating jalx instructions
4397 when needed. We also make them odd for the duration of the assembly,
4398 in order to generate the right sort of code. We will make them even
4399 in the adjust_symtab routine, while leaving them marked. This is
4400 convenient for the debugger and the disassembler. The linker knows
4401 to make them odd again. */
4404 mips_compressed_mark_label (symbolS
*label
)
4406 gas_assert (HAVE_CODE_COMPRESSION
);
4408 if (mips_opts
.mips16
)
4409 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4411 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4412 if ((S_GET_VALUE (label
) & 1) == 0
4413 /* Don't adjust the address if the label is global or weak, or
4414 in a link-once section, since we'll be emitting symbol reloc
4415 references to it which will be patched up by the linker, and
4416 the final value of the symbol may or may not be MIPS16/microMIPS. */
4417 && !S_IS_WEAK (label
)
4418 && !S_IS_EXTERNAL (label
)
4419 && !s_is_linkonce (label
, now_seg
))
4420 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4423 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4426 mips_compressed_mark_labels (void)
4428 struct insn_label_list
*l
;
4430 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4431 mips_compressed_mark_label (l
->label
);
4434 /* End the current frag. Make it a variant frag and record the
4438 relax_close_frag (void)
4440 mips_macro_warning
.first_frag
= frag_now
;
4441 frag_var (rs_machine_dependent
, 0, 0,
4442 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4443 mips_pic
!= NO_PIC
),
4444 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4446 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4447 mips_relax
.first_fixup
= 0;
4450 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4451 See the comment above RELAX_ENCODE for more details. */
4454 relax_start (symbolS
*symbol
)
4456 gas_assert (mips_relax
.sequence
== 0);
4457 mips_relax
.sequence
= 1;
4458 mips_relax
.symbol
= symbol
;
4461 /* Start generating the second version of a relaxable sequence.
4462 See the comment above RELAX_ENCODE for more details. */
4467 gas_assert (mips_relax
.sequence
== 1);
4468 mips_relax
.sequence
= 2;
4471 /* End the current relaxable sequence. */
4476 gas_assert (mips_relax
.sequence
== 2);
4477 relax_close_frag ();
4478 mips_relax
.sequence
= 0;
4481 /* Return true if IP is a delayed branch or jump. */
4483 static inline bfd_boolean
4484 delayed_branch_p (const struct mips_cl_insn
*ip
)
4486 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4487 | INSN_COND_BRANCH_DELAY
4488 | INSN_COND_BRANCH_LIKELY
)) != 0;
4491 /* Return true if IP is a compact branch or jump. */
4493 static inline bfd_boolean
4494 compact_branch_p (const struct mips_cl_insn
*ip
)
4496 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4497 | INSN2_COND_BRANCH
)) != 0;
4500 /* Return true if IP is an unconditional branch or jump. */
4502 static inline bfd_boolean
4503 uncond_branch_p (const struct mips_cl_insn
*ip
)
4505 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4506 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4509 /* Return true if IP is a branch-likely instruction. */
4511 static inline bfd_boolean
4512 branch_likely_p (const struct mips_cl_insn
*ip
)
4514 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4517 /* Return the type of nop that should be used to fill the delay slot
4518 of delayed branch IP. */
4520 static struct mips_cl_insn
*
4521 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4523 if (mips_opts
.micromips
4524 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4525 return µmips_nop32_insn
;
4529 /* Return a mask that has bit N set if OPCODE reads the register(s)
4533 insn_read_mask (const struct mips_opcode
*opcode
)
4535 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4538 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4542 insn_write_mask (const struct mips_opcode
*opcode
)
4544 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4547 /* Return a mask of the registers specified by operand OPERAND of INSN.
4548 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4552 operand_reg_mask (const struct mips_cl_insn
*insn
,
4553 const struct mips_operand
*operand
,
4554 unsigned int type_mask
)
4556 unsigned int uval
, vsel
;
4558 switch (operand
->type
)
4565 case OP_ADDIUSP_INT
:
4566 case OP_ENTRY_EXIT_LIST
:
4567 case OP_REPEAT_DEST_REG
:
4568 case OP_REPEAT_PREV_REG
:
4571 case OP_VU0_MATCH_SUFFIX
:
4579 case OP_OPTIONAL_REG
:
4581 const struct mips_reg_operand
*reg_op
;
4583 reg_op
= (const struct mips_reg_operand
*) operand
;
4584 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4586 uval
= insn_extract_operand (insn
, operand
);
4587 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4592 const struct mips_reg_pair_operand
*pair_op
;
4594 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4595 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4597 uval
= insn_extract_operand (insn
, operand
);
4598 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4601 case OP_CLO_CLZ_DEST
:
4602 if (!(type_mask
& (1 << OP_REG_GP
)))
4604 uval
= insn_extract_operand (insn
, operand
);
4605 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4608 if (!(type_mask
& (1 << OP_REG_GP
)))
4610 uval
= insn_extract_operand (insn
, operand
);
4611 gas_assert ((uval
& 31) == (uval
>> 5));
4612 return 1 << (uval
& 31);
4615 case OP_NON_ZERO_REG
:
4616 if (!(type_mask
& (1 << OP_REG_GP
)))
4618 uval
= insn_extract_operand (insn
, operand
);
4619 return 1 << (uval
& 31);
4621 case OP_LWM_SWM_LIST
:
4624 case OP_SAVE_RESTORE_LIST
:
4627 case OP_MDMX_IMM_REG
:
4628 if (!(type_mask
& (1 << OP_REG_VEC
)))
4630 uval
= insn_extract_operand (insn
, operand
);
4632 if ((vsel
& 0x18) == 0x18)
4634 return 1 << (uval
& 31);
4637 if (!(type_mask
& (1 << OP_REG_GP
)))
4639 return 1 << insn_extract_operand (insn
, operand
);
4644 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4645 where bit N of OPNO_MASK is set if operand N should be included.
4646 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4650 insn_reg_mask (const struct mips_cl_insn
*insn
,
4651 unsigned int type_mask
, unsigned int opno_mask
)
4653 unsigned int opno
, reg_mask
;
4657 while (opno_mask
!= 0)
4660 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4667 /* Return the mask of core registers that IP reads. */
4670 gpr_read_mask (const struct mips_cl_insn
*ip
)
4672 unsigned long pinfo
, pinfo2
;
4675 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4676 pinfo
= ip
->insn_mo
->pinfo
;
4677 pinfo2
= ip
->insn_mo
->pinfo2
;
4678 if (pinfo
& INSN_UDI
)
4680 /* UDI instructions have traditionally been assumed to read RS
4682 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4683 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4685 if (pinfo
& INSN_READ_GPR_24
)
4687 if (pinfo2
& INSN2_READ_GPR_16
)
4689 if (pinfo2
& INSN2_READ_SP
)
4691 if (pinfo2
& INSN2_READ_GPR_31
)
4693 /* Don't include register 0. */
4697 /* Return the mask of core registers that IP writes. */
4700 gpr_write_mask (const struct mips_cl_insn
*ip
)
4702 unsigned long pinfo
, pinfo2
;
4705 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4706 pinfo
= ip
->insn_mo
->pinfo
;
4707 pinfo2
= ip
->insn_mo
->pinfo2
;
4708 if (pinfo
& INSN_WRITE_GPR_24
)
4710 if (pinfo
& INSN_WRITE_GPR_31
)
4712 if (pinfo
& INSN_UDI
)
4713 /* UDI instructions have traditionally been assumed to write to RD. */
4714 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4715 if (pinfo2
& INSN2_WRITE_SP
)
4717 /* Don't include register 0. */
4721 /* Return the mask of floating-point registers that IP reads. */
4724 fpr_read_mask (const struct mips_cl_insn
*ip
)
4726 unsigned long pinfo
;
4729 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4730 | (1 << OP_REG_MSA
)),
4731 insn_read_mask (ip
->insn_mo
));
4732 pinfo
= ip
->insn_mo
->pinfo
;
4733 /* Conservatively treat all operands to an FP_D instruction are doubles.
4734 (This is overly pessimistic for things like cvt.d.s.) */
4735 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4740 /* Return the mask of floating-point registers that IP writes. */
4743 fpr_write_mask (const struct mips_cl_insn
*ip
)
4745 unsigned long pinfo
;
4748 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4749 | (1 << OP_REG_MSA
)),
4750 insn_write_mask (ip
->insn_mo
));
4751 pinfo
= ip
->insn_mo
->pinfo
;
4752 /* Conservatively treat all operands to an FP_D instruction are doubles.
4753 (This is overly pessimistic for things like cvt.s.d.) */
4754 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4759 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4760 Check whether that is allowed. */
4763 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4765 const char *s
= insn
->name
;
4766 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4768 && mips_opts
.oddspreg
;
4770 if (insn
->pinfo
== INSN_MACRO
)
4771 /* Let a macro pass, we'll catch it later when it is expanded. */
4774 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4775 otherwise it depends on oddspreg. */
4776 if ((insn
->pinfo
& FP_S
)
4777 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4778 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4779 return FPR_SIZE
== 32 || oddspreg
;
4781 /* Allow odd registers for single-precision ops and double-precision if the
4782 floating-point registers are 64-bit wide. */
4783 switch (insn
->pinfo
& (FP_S
| FP_D
))
4789 return FPR_SIZE
== 64;
4794 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4795 s
= strchr (insn
->name
, '.');
4796 if (s
!= NULL
&& opnum
== 2)
4797 s
= strchr (s
+ 1, '.');
4798 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4801 return FPR_SIZE
== 64;
4804 /* Information about an instruction argument that we're trying to match. */
4805 struct mips_arg_info
4807 /* The instruction so far. */
4808 struct mips_cl_insn
*insn
;
4810 /* The first unconsumed operand token. */
4811 struct mips_operand_token
*token
;
4813 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4816 /* The 1-based argument number, for error reporting. This does not
4817 count elided optional registers, etc.. */
4820 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4821 unsigned int last_regno
;
4823 /* If the first operand was an OP_REG, this is the register that it
4824 specified, otherwise it is ILLEGAL_REG. */
4825 unsigned int dest_regno
;
4827 /* The value of the last OP_INT operand. Only used for OP_MSB,
4828 where it gives the lsb position. */
4829 unsigned int last_op_int
;
4831 /* If true, match routines should assume that no later instruction
4832 alternative matches and should therefore be as accommodating as
4833 possible. Match routines should not report errors if something
4834 is only invalid for !LAX_MATCH. */
4835 bfd_boolean lax_match
;
4837 /* True if a reference to the current AT register was seen. */
4838 bfd_boolean seen_at
;
4841 /* Record that the argument is out of range. */
4844 match_out_of_range (struct mips_arg_info
*arg
)
4846 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4849 /* Record that the argument isn't constant but needs to be. */
4852 match_not_constant (struct mips_arg_info
*arg
)
4854 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4858 /* Try to match an OT_CHAR token for character CH. Consume the token
4859 and return true on success, otherwise return false. */
4862 match_char (struct mips_arg_info
*arg
, char ch
)
4864 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4874 /* Try to get an expression from the next tokens in ARG. Consume the
4875 tokens and return true on success, storing the expression value in
4876 VALUE and relocation types in R. */
4879 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4880 bfd_reloc_code_real_type
*r
)
4882 /* If the next token is a '(' that was parsed as being part of a base
4883 expression, assume we have an elided offset. The later match will fail
4884 if this turns out to be wrong. */
4885 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4887 value
->X_op
= O_constant
;
4888 value
->X_add_number
= 0;
4889 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4893 /* Reject register-based expressions such as "0+$2" and "(($2))".
4894 For plain registers the default error seems more appropriate. */
4895 if (arg
->token
->type
== OT_INTEGER
4896 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4898 set_insn_error (arg
->argnum
, _("register value used as expression"));
4902 if (arg
->token
->type
== OT_INTEGER
)
4904 *value
= arg
->token
->u
.integer
.value
;
4905 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4911 (arg
->argnum
, _("operand %d must be an immediate expression"),
4916 /* Try to get a constant expression from the next tokens in ARG. Consume
4917 the tokens and return true on success, storing the constant value
4921 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4924 bfd_reloc_code_real_type r
[3];
4926 if (!match_expression (arg
, &ex
, r
))
4929 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4930 *value
= ex
.X_add_number
;
4933 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
4934 match_out_of_range (arg
);
4936 match_not_constant (arg
);
4942 /* Return the RTYPE_* flags for a register operand of type TYPE that
4943 appears in instruction OPCODE. */
4946 convert_reg_type (const struct mips_opcode
*opcode
,
4947 enum mips_reg_operand_type type
)
4952 return RTYPE_NUM
| RTYPE_GP
;
4955 /* Allow vector register names for MDMX if the instruction is a 64-bit
4956 FPR load, store or move (including moves to and from GPRs). */
4957 if ((mips_opts
.ase
& ASE_MDMX
)
4958 && (opcode
->pinfo
& FP_D
)
4959 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4960 | INSN_COPROC_MEMORY_DELAY
4963 | INSN_STORE_MEMORY
)))
4964 return RTYPE_FPU
| RTYPE_VEC
;
4968 if (opcode
->pinfo
& (FP_D
| FP_S
))
4969 return RTYPE_CCC
| RTYPE_FCC
;
4973 if (opcode
->membership
& INSN_5400
)
4975 return RTYPE_FPU
| RTYPE_VEC
;
4981 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4982 return RTYPE_NUM
| RTYPE_CP0
;
4989 return RTYPE_NUM
| RTYPE_VI
;
4992 return RTYPE_NUM
| RTYPE_VF
;
4994 case OP_REG_R5900_I
:
4995 return RTYPE_R5900_I
;
4997 case OP_REG_R5900_Q
:
4998 return RTYPE_R5900_Q
;
5000 case OP_REG_R5900_R
:
5001 return RTYPE_R5900_R
;
5003 case OP_REG_R5900_ACC
:
5004 return RTYPE_R5900_ACC
;
5009 case OP_REG_MSA_CTRL
:
5015 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5018 check_regno (struct mips_arg_info
*arg
,
5019 enum mips_reg_operand_type type
, unsigned int regno
)
5021 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5022 arg
->seen_at
= TRUE
;
5024 if (type
== OP_REG_FP
5026 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5028 /* This was a warning prior to introducing O32 FPXX and FP64 support
5029 so maintain a warning for FP32 but raise an error for the new
5032 as_warn (_("float register should be even, was %d"), regno
);
5034 as_bad (_("float register should be even, was %d"), regno
);
5037 if (type
== OP_REG_CCC
)
5042 name
= arg
->insn
->insn_mo
->name
;
5043 length
= strlen (name
);
5044 if ((regno
& 1) != 0
5045 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5046 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5047 as_warn (_("condition code register should be even for %s, was %d"),
5050 if ((regno
& 3) != 0
5051 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5052 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5057 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5058 a register of type TYPE. Return true on success, storing the register
5059 number in *REGNO and warning about any dubious uses. */
5062 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5063 unsigned int symval
, unsigned int *regno
)
5065 if (type
== OP_REG_VEC
)
5066 symval
= mips_prefer_vec_regno (symval
);
5067 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5070 *regno
= symval
& RNUM_MASK
;
5071 check_regno (arg
, type
, *regno
);
5075 /* Try to interpret the next token in ARG as a register of type TYPE.
5076 Consume the token and return true on success, storing the register
5077 number in *REGNO. Return false on failure. */
5080 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5081 unsigned int *regno
)
5083 if (arg
->token
->type
== OT_REG
5084 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5092 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5093 Consume the token and return true on success, storing the register numbers
5094 in *REGNO1 and *REGNO2. Return false on failure. */
5097 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5098 unsigned int *regno1
, unsigned int *regno2
)
5100 if (match_reg (arg
, type
, regno1
))
5105 if (arg
->token
->type
== OT_REG_RANGE
5106 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5107 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5108 && *regno1
<= *regno2
)
5116 /* OP_INT matcher. */
5119 match_int_operand (struct mips_arg_info
*arg
,
5120 const struct mips_operand
*operand_base
)
5122 const struct mips_int_operand
*operand
;
5124 int min_val
, max_val
, factor
;
5127 operand
= (const struct mips_int_operand
*) operand_base
;
5128 factor
= 1 << operand
->shift
;
5129 min_val
= mips_int_operand_min (operand
);
5130 max_val
= mips_int_operand_max (operand
);
5132 if (operand_base
->lsb
== 0
5133 && operand_base
->size
== 16
5134 && operand
->shift
== 0
5135 && operand
->bias
== 0
5136 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5138 /* The operand can be relocated. */
5139 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5142 if (offset_expr
.X_op
== O_big
)
5144 match_out_of_range (arg
);
5148 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5149 /* Relocation operators were used. Accept the argument and
5150 leave the relocation value in offset_expr and offset_relocs
5151 for the caller to process. */
5154 if (offset_expr
.X_op
!= O_constant
)
5156 /* Accept non-constant operands if no later alternative matches,
5157 leaving it for the caller to process. */
5158 if (!arg
->lax_match
)
5160 match_not_constant (arg
);
5163 offset_reloc
[0] = BFD_RELOC_LO16
;
5167 /* Clear the global state; we're going to install the operand
5169 sval
= offset_expr
.X_add_number
;
5170 offset_expr
.X_op
= O_absent
;
5172 /* For compatibility with older assemblers, we accept
5173 0x8000-0xffff as signed 16-bit numbers when only
5174 signed numbers are allowed. */
5177 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5178 if (!arg
->lax_match
&& sval
<= max_val
)
5180 match_out_of_range (arg
);
5187 if (!match_const_int (arg
, &sval
))
5191 arg
->last_op_int
= sval
;
5193 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5195 match_out_of_range (arg
);
5199 uval
= (unsigned int) sval
>> operand
->shift
;
5200 uval
-= operand
->bias
;
5202 /* Handle -mfix-cn63xxp1. */
5204 && mips_fix_cn63xxp1
5205 && !mips_opts
.micromips
5206 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5221 /* The rest must be changed to 28. */
5226 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5230 /* OP_MAPPED_INT matcher. */
5233 match_mapped_int_operand (struct mips_arg_info
*arg
,
5234 const struct mips_operand
*operand_base
)
5236 const struct mips_mapped_int_operand
*operand
;
5237 unsigned int uval
, num_vals
;
5240 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5241 if (!match_const_int (arg
, &sval
))
5244 num_vals
= 1 << operand_base
->size
;
5245 for (uval
= 0; uval
< num_vals
; uval
++)
5246 if (operand
->int_map
[uval
] == sval
)
5248 if (uval
== num_vals
)
5250 match_out_of_range (arg
);
5254 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5258 /* OP_MSB matcher. */
5261 match_msb_operand (struct mips_arg_info
*arg
,
5262 const struct mips_operand
*operand_base
)
5264 const struct mips_msb_operand
*operand
;
5265 int min_val
, max_val
, max_high
;
5266 offsetT size
, sval
, high
;
5268 operand
= (const struct mips_msb_operand
*) operand_base
;
5269 min_val
= operand
->bias
;
5270 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5271 max_high
= operand
->opsize
;
5273 if (!match_const_int (arg
, &size
))
5276 high
= size
+ arg
->last_op_int
;
5277 sval
= operand
->add_lsb
? high
: size
;
5279 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5281 match_out_of_range (arg
);
5284 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5288 /* OP_REG matcher. */
5291 match_reg_operand (struct mips_arg_info
*arg
,
5292 const struct mips_operand
*operand_base
)
5294 const struct mips_reg_operand
*operand
;
5295 unsigned int regno
, uval
, num_vals
;
5297 operand
= (const struct mips_reg_operand
*) operand_base
;
5298 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5301 if (operand
->reg_map
)
5303 num_vals
= 1 << operand
->root
.size
;
5304 for (uval
= 0; uval
< num_vals
; uval
++)
5305 if (operand
->reg_map
[uval
] == regno
)
5307 if (num_vals
== uval
)
5313 arg
->last_regno
= regno
;
5314 if (arg
->opnum
== 1)
5315 arg
->dest_regno
= regno
;
5316 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5320 /* OP_REG_PAIR matcher. */
5323 match_reg_pair_operand (struct mips_arg_info
*arg
,
5324 const struct mips_operand
*operand_base
)
5326 const struct mips_reg_pair_operand
*operand
;
5327 unsigned int regno1
, regno2
, uval
, num_vals
;
5329 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5330 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5331 || !match_char (arg
, ',')
5332 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5335 num_vals
= 1 << operand_base
->size
;
5336 for (uval
= 0; uval
< num_vals
; uval
++)
5337 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5339 if (uval
== num_vals
)
5342 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5346 /* OP_PCREL matcher. The caller chooses the relocation type. */
5349 match_pcrel_operand (struct mips_arg_info
*arg
)
5351 bfd_reloc_code_real_type r
[3];
5353 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5356 /* OP_PERF_REG matcher. */
5359 match_perf_reg_operand (struct mips_arg_info
*arg
,
5360 const struct mips_operand
*operand
)
5364 if (!match_const_int (arg
, &sval
))
5369 || (mips_opts
.arch
== CPU_R5900
5370 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5371 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5373 set_insn_error (arg
->argnum
, _("invalid performance register"));
5377 insn_insert_operand (arg
->insn
, operand
, sval
);
5381 /* OP_ADDIUSP matcher. */
5384 match_addiusp_operand (struct mips_arg_info
*arg
,
5385 const struct mips_operand
*operand
)
5390 if (!match_const_int (arg
, &sval
))
5395 match_out_of_range (arg
);
5400 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5402 match_out_of_range (arg
);
5406 uval
= (unsigned int) sval
;
5407 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5408 insn_insert_operand (arg
->insn
, operand
, uval
);
5412 /* OP_CLO_CLZ_DEST matcher. */
5415 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5416 const struct mips_operand
*operand
)
5420 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5423 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5427 /* OP_CHECK_PREV matcher. */
5430 match_check_prev_operand (struct mips_arg_info
*arg
,
5431 const struct mips_operand
*operand_base
)
5433 const struct mips_check_prev_operand
*operand
;
5436 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5438 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5441 if (!operand
->zero_ok
&& regno
== 0)
5444 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5445 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5446 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5448 arg
->last_regno
= regno
;
5449 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5456 /* OP_SAME_RS_RT matcher. */
5459 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5460 const struct mips_operand
*operand
)
5464 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5469 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5473 arg
->last_regno
= regno
;
5475 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5479 /* OP_LWM_SWM_LIST matcher. */
5482 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5483 const struct mips_operand
*operand
)
5485 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5486 struct mips_arg_info reset
;
5489 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5493 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5498 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5501 while (match_char (arg
, ',')
5502 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5505 if (operand
->size
== 2)
5507 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5513 and any permutations of these. */
5514 if ((reglist
& 0xfff1ffff) != 0x80010000)
5517 sregs
= (reglist
>> 17) & 7;
5522 /* The list must include at least one of ra and s0-sN,
5523 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5524 which are $23 and $30 respectively.) E.g.:
5532 and any permutations of these. */
5533 if ((reglist
& 0x3f00ffff) != 0)
5536 ra
= (reglist
>> 27) & 0x10;
5537 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5540 if ((sregs
& -sregs
) != sregs
)
5543 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5547 /* OP_ENTRY_EXIT_LIST matcher. */
5550 match_entry_exit_operand (struct mips_arg_info
*arg
,
5551 const struct mips_operand
*operand
)
5554 bfd_boolean is_exit
;
5556 /* The format is the same for both ENTRY and EXIT, but the constraints
5558 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5559 mask
= (is_exit
? 7 << 3 : 0);
5562 unsigned int regno1
, regno2
;
5563 bfd_boolean is_freg
;
5565 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5567 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5572 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5575 mask
|= (5 + regno2
) << 3;
5577 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5578 mask
|= (regno2
- 3) << 3;
5579 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5580 mask
|= (regno2
- 15) << 1;
5581 else if (regno1
== RA
&& regno2
== RA
)
5586 while (match_char (arg
, ','));
5588 insn_insert_operand (arg
->insn
, operand
, mask
);
5592 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5593 the argument register mask AMASK, the number of static registers
5594 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5595 respectively, and the frame size FRAME_SIZE. */
5598 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5599 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5600 unsigned int frame_size
)
5602 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5603 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5606 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5607 argument register mask AMASK, the number of static registers saved
5608 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5609 respectively, and the frame size FRAME_SIZE. */
5612 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5613 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5614 unsigned int frame_size
)
5618 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5619 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5620 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5621 | ((frame_size
& 0xf0) << 16));
5625 /* OP_SAVE_RESTORE_LIST matcher. */
5628 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5630 unsigned int opcode
, args
, statics
, sregs
;
5631 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5632 unsigned int arg_mask
, ra
, s0
, s1
;
5635 opcode
= arg
->insn
->insn_opcode
;
5637 num_frame_sizes
= 0;
5646 unsigned int regno1
, regno2
;
5648 if (arg
->token
->type
== OT_INTEGER
)
5650 /* Handle the frame size. */
5651 if (!match_const_int (arg
, &frame_size
))
5653 num_frame_sizes
+= 1;
5657 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5660 while (regno1
<= regno2
)
5662 if (regno1
>= 4 && regno1
<= 7)
5664 if (num_frame_sizes
== 0)
5666 args
|= 1 << (regno1
- 4);
5668 /* statics $a0-$a3 */
5669 statics
|= 1 << (regno1
- 4);
5671 else if (regno1
>= 16 && regno1
<= 23)
5673 sregs
|= 1 << (regno1
- 16);
5674 else if (regno1
== 30)
5677 else if (regno1
== 31)
5678 /* Add $ra to insn. */
5688 while (match_char (arg
, ','));
5690 /* Encode args/statics combination. */
5693 else if (args
== 0xf)
5694 /* All $a0-$a3 are args. */
5695 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5696 else if (statics
== 0xf)
5697 /* All $a0-$a3 are statics. */
5698 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5701 /* Count arg registers. */
5711 /* Count static registers. */
5713 while (statics
& 0x8)
5715 statics
= (statics
<< 1) & 0xf;
5721 /* Encode args/statics. */
5722 arg_mask
= (num_args
<< 2) | num_statics
;
5725 /* Encode $s0/$s1. */
5726 if (sregs
& (1 << 0)) /* $s0 */
5728 if (sregs
& (1 << 1)) /* $s1 */
5732 /* Encode $s2-$s8. */
5742 /* Encode frame size. */
5743 if (num_frame_sizes
== 0)
5745 set_insn_error (arg
->argnum
, _("missing frame size"));
5748 if (num_frame_sizes
> 1)
5750 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5753 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5755 set_insn_error (arg
->argnum
, _("invalid frame size"));
5760 /* Finally build the instruction. */
5761 if (mips_opts
.mips16
)
5762 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5764 else if (!mips_opts
.micromips
)
5765 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5770 arg
->insn
->insn_opcode
= opcode
;
5774 /* OP_MDMX_IMM_REG matcher. */
5777 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5778 const struct mips_operand
*operand
)
5780 unsigned int regno
, uval
;
5782 const struct mips_opcode
*opcode
;
5784 /* The mips_opcode records whether this is an octobyte or quadhalf
5785 instruction. Start out with that bit in place. */
5786 opcode
= arg
->insn
->insn_mo
;
5787 uval
= mips_extract_operand (operand
, opcode
->match
);
5788 is_qh
= (uval
!= 0);
5790 if (arg
->token
->type
== OT_REG
)
5792 if ((opcode
->membership
& INSN_5400
)
5793 && strcmp (opcode
->name
, "rzu.ob") == 0)
5795 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5800 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5804 /* Check whether this is a vector register or a broadcast of
5805 a single element. */
5806 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5808 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5810 set_insn_error (arg
->argnum
, _("invalid element selector"));
5813 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5818 /* A full vector. */
5819 if ((opcode
->membership
& INSN_5400
)
5820 && (strcmp (opcode
->name
, "sll.ob") == 0
5821 || strcmp (opcode
->name
, "srl.ob") == 0))
5823 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5829 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5831 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5839 if (!match_const_int (arg
, &sval
))
5841 if (sval
< 0 || sval
> 31)
5843 match_out_of_range (arg
);
5846 uval
|= (sval
& 31);
5848 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5850 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5852 insn_insert_operand (arg
->insn
, operand
, uval
);
5856 /* OP_IMM_INDEX matcher. */
5859 match_imm_index_operand (struct mips_arg_info
*arg
,
5860 const struct mips_operand
*operand
)
5862 unsigned int max_val
;
5864 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5867 max_val
= (1 << operand
->size
) - 1;
5868 if (arg
->token
->u
.index
> max_val
)
5870 match_out_of_range (arg
);
5873 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5878 /* OP_REG_INDEX matcher. */
5881 match_reg_index_operand (struct mips_arg_info
*arg
,
5882 const struct mips_operand
*operand
)
5886 if (arg
->token
->type
!= OT_REG_INDEX
)
5889 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5892 insn_insert_operand (arg
->insn
, operand
, regno
);
5897 /* OP_PC matcher. */
5900 match_pc_operand (struct mips_arg_info
*arg
)
5902 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5910 /* OP_REG28 matcher. */
5913 match_reg28_operand (struct mips_arg_info
*arg
)
5917 if (arg
->token
->type
== OT_REG
5918 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
5927 /* OP_NON_ZERO_REG matcher. */
5930 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5931 const struct mips_operand
*operand
)
5935 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5941 arg
->last_regno
= regno
;
5942 insn_insert_operand (arg
->insn
, operand
, regno
);
5946 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5947 register that we need to match. */
5950 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5954 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5957 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
5958 LENGTH is the length of the value in bytes (4 for float, 8 for double)
5959 and USING_GPRS says whether the destination is a GPR rather than an FPR.
5961 Return the constant in IMM and OFFSET as follows:
5963 - If the constant should be loaded via memory, set IMM to O_absent and
5964 OFFSET to the memory address.
5966 - Otherwise, if the constant should be loaded into two 32-bit registers,
5967 set IMM to the O_constant to load into the high register and OFFSET
5968 to the corresponding value for the low register.
5970 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5972 These constants only appear as the last operand in an instruction,
5973 and every instruction that accepts them in any variant accepts them
5974 in all variants. This means we don't have to worry about backing out
5975 any changes if the instruction does not match. We just match
5976 unconditionally and report an error if the constant is invalid. */
5979 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5980 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5985 const char *newname
;
5986 unsigned char *data
;
5988 /* Where the constant is placed is based on how the MIPS assembler
5991 length == 4 && using_gprs -- immediate value only
5992 length == 8 && using_gprs -- .rdata or immediate value
5993 length == 4 && !using_gprs -- .lit4 or immediate value
5994 length == 8 && !using_gprs -- .lit8 or immediate value
5996 The .lit4 and .lit8 sections are only used if permitted by the
5998 if (arg
->token
->type
!= OT_FLOAT
)
6000 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6004 gas_assert (arg
->token
->u
.flt
.length
== length
);
6005 data
= arg
->token
->u
.flt
.data
;
6008 /* Handle 32-bit constants for which an immediate value is best. */
6011 || g_switch_value
< 4
6012 || (data
[0] == 0 && data
[1] == 0)
6013 || (data
[2] == 0 && data
[3] == 0)))
6015 imm
->X_op
= O_constant
;
6016 if (!target_big_endian
)
6017 imm
->X_add_number
= bfd_getl32 (data
);
6019 imm
->X_add_number
= bfd_getb32 (data
);
6020 offset
->X_op
= O_absent
;
6024 /* Handle 64-bit constants for which an immediate value is best. */
6026 && !mips_disable_float_construction
6027 /* Constants can only be constructed in GPRs and copied to FPRs if the
6028 GPRs are at least as wide as the FPRs or MTHC1 is available.
6029 Unlike most tests for 32-bit floating-point registers this check
6030 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6031 permit 64-bit moves without MXHC1.
6032 Force the constant into memory otherwise. */
6035 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6037 && ((data
[0] == 0 && data
[1] == 0)
6038 || (data
[2] == 0 && data
[3] == 0))
6039 && ((data
[4] == 0 && data
[5] == 0)
6040 || (data
[6] == 0 && data
[7] == 0)))
6042 /* The value is simple enough to load with a couple of instructions.
6043 If using 32-bit registers, set IMM to the high order 32 bits and
6044 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6046 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6048 imm
->X_op
= O_constant
;
6049 offset
->X_op
= O_constant
;
6050 if (!target_big_endian
)
6052 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6053 offset
->X_add_number
= bfd_getl32 (data
);
6057 imm
->X_add_number
= bfd_getb32 (data
);
6058 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6060 if (offset
->X_add_number
== 0)
6061 offset
->X_op
= O_absent
;
6065 imm
->X_op
= O_constant
;
6066 if (!target_big_endian
)
6067 imm
->X_add_number
= bfd_getl64 (data
);
6069 imm
->X_add_number
= bfd_getb64 (data
);
6070 offset
->X_op
= O_absent
;
6075 /* Switch to the right section. */
6077 subseg
= now_subseg
;
6080 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6085 if (using_gprs
|| g_switch_value
< 8)
6086 newname
= RDATA_SECTION_NAME
;
6091 new_seg
= subseg_new (newname
, (subsegT
) 0);
6092 bfd_set_section_flags (stdoutput
, new_seg
,
6093 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6094 frag_align (length
== 4 ? 2 : 3, 0, 0);
6095 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6096 record_alignment (new_seg
, 4);
6098 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6100 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6102 /* Set the argument to the current address in the section. */
6103 imm
->X_op
= O_absent
;
6104 offset
->X_op
= O_symbol
;
6105 offset
->X_add_symbol
= symbol_temp_new_now ();
6106 offset
->X_add_number
= 0;
6108 /* Put the floating point number into the section. */
6109 p
= frag_more (length
);
6110 memcpy (p
, data
, length
);
6112 /* Switch back to the original section. */
6113 subseg_set (seg
, subseg
);
6117 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6121 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6122 const struct mips_operand
*operand
,
6123 bfd_boolean match_p
)
6127 /* The operand can be an XYZW mask or a single 2-bit channel index
6128 (with X being 0). */
6129 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6131 /* The suffix can be omitted when it is already part of the opcode. */
6132 if (arg
->token
->type
!= OT_CHANNELS
)
6135 uval
= arg
->token
->u
.channels
;
6136 if (operand
->size
== 2)
6138 /* Check that a single bit is set and convert it into a 2-bit index. */
6139 if ((uval
& -uval
) != uval
)
6141 uval
= 4 - ffs (uval
);
6144 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6149 insn_insert_operand (arg
->insn
, operand
, uval
);
6153 /* Try to match a token from ARG against OPERAND. Consume the token
6154 and return true on success, otherwise return false. */
6157 match_operand (struct mips_arg_info
*arg
,
6158 const struct mips_operand
*operand
)
6160 switch (operand
->type
)
6163 return match_int_operand (arg
, operand
);
6166 return match_mapped_int_operand (arg
, operand
);
6169 return match_msb_operand (arg
, operand
);
6172 case OP_OPTIONAL_REG
:
6173 return match_reg_operand (arg
, operand
);
6176 return match_reg_pair_operand (arg
, operand
);
6179 return match_pcrel_operand (arg
);
6182 return match_perf_reg_operand (arg
, operand
);
6184 case OP_ADDIUSP_INT
:
6185 return match_addiusp_operand (arg
, operand
);
6187 case OP_CLO_CLZ_DEST
:
6188 return match_clo_clz_dest_operand (arg
, operand
);
6190 case OP_LWM_SWM_LIST
:
6191 return match_lwm_swm_list_operand (arg
, operand
);
6193 case OP_ENTRY_EXIT_LIST
:
6194 return match_entry_exit_operand (arg
, operand
);
6196 case OP_SAVE_RESTORE_LIST
:
6197 return match_save_restore_list_operand (arg
);
6199 case OP_MDMX_IMM_REG
:
6200 return match_mdmx_imm_reg_operand (arg
, operand
);
6202 case OP_REPEAT_DEST_REG
:
6203 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6205 case OP_REPEAT_PREV_REG
:
6206 return match_tied_reg_operand (arg
, arg
->last_regno
);
6209 return match_pc_operand (arg
);
6212 return match_reg28_operand (arg
);
6215 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6217 case OP_VU0_MATCH_SUFFIX
:
6218 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6221 return match_imm_index_operand (arg
, operand
);
6224 return match_reg_index_operand (arg
, operand
);
6227 return match_same_rs_rt_operand (arg
, operand
);
6230 return match_check_prev_operand (arg
, operand
);
6232 case OP_NON_ZERO_REG
:
6233 return match_non_zero_reg_operand (arg
, operand
);
6238 /* ARG is the state after successfully matching an instruction.
6239 Issue any queued-up warnings. */
6242 check_completed_insn (struct mips_arg_info
*arg
)
6247 as_warn (_("used $at without \".set noat\""));
6249 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6253 /* Return true if modifying general-purpose register REG needs a delay. */
6256 reg_needs_delay (unsigned int reg
)
6258 unsigned long prev_pinfo
;
6260 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6261 if (!mips_opts
.noreorder
6262 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6263 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6264 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6270 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6271 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6272 by VR4120 errata. */
6275 classify_vr4120_insn (const char *name
)
6277 if (strncmp (name
, "macc", 4) == 0)
6278 return FIX_VR4120_MACC
;
6279 if (strncmp (name
, "dmacc", 5) == 0)
6280 return FIX_VR4120_DMACC
;
6281 if (strncmp (name
, "mult", 4) == 0)
6282 return FIX_VR4120_MULT
;
6283 if (strncmp (name
, "dmult", 5) == 0)
6284 return FIX_VR4120_DMULT
;
6285 if (strstr (name
, "div"))
6286 return FIX_VR4120_DIV
;
6287 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6288 return FIX_VR4120_MTHILO
;
6289 return NUM_FIX_VR4120_CLASSES
;
6292 #define INSN_ERET 0x42000018
6293 #define INSN_DERET 0x4200001f
6294 #define INSN_DMULT 0x1c
6295 #define INSN_DMULTU 0x1d
6297 /* Return the number of instructions that must separate INSN1 and INSN2,
6298 where INSN1 is the earlier instruction. Return the worst-case value
6299 for any INSN2 if INSN2 is null. */
6302 insns_between (const struct mips_cl_insn
*insn1
,
6303 const struct mips_cl_insn
*insn2
)
6305 unsigned long pinfo1
, pinfo2
;
6308 /* If INFO2 is null, pessimistically assume that all flags are set for
6309 the second instruction. */
6310 pinfo1
= insn1
->insn_mo
->pinfo
;
6311 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6313 /* For most targets, write-after-read dependencies on the HI and LO
6314 registers must be separated by at least two instructions. */
6315 if (!hilo_interlocks
)
6317 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6319 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6323 /* If we're working around r7000 errata, there must be two instructions
6324 between an mfhi or mflo and any instruction that uses the result. */
6325 if (mips_7000_hilo_fix
6326 && !mips_opts
.micromips
6327 && MF_HILO_INSN (pinfo1
)
6328 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6331 /* If we're working around 24K errata, one instruction is required
6332 if an ERET or DERET is followed by a branch instruction. */
6333 if (mips_fix_24k
&& !mips_opts
.micromips
)
6335 if (insn1
->insn_opcode
== INSN_ERET
6336 || insn1
->insn_opcode
== INSN_DERET
)
6339 || insn2
->insn_opcode
== INSN_ERET
6340 || insn2
->insn_opcode
== INSN_DERET
6341 || delayed_branch_p (insn2
))
6346 /* If we're working around PMC RM7000 errata, there must be three
6347 nops between a dmult and a load instruction. */
6348 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6350 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6351 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6353 if (pinfo2
& INSN_LOAD_MEMORY
)
6358 /* If working around VR4120 errata, check for combinations that need
6359 a single intervening instruction. */
6360 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6362 unsigned int class1
, class2
;
6364 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6365 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6369 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6370 if (vr4120_conflicts
[class1
] & (1 << class2
))
6375 if (!HAVE_CODE_COMPRESSION
)
6377 /* Check for GPR or coprocessor load delays. All such delays
6378 are on the RT register. */
6379 /* Itbl support may require additional care here. */
6380 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6381 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6383 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6387 /* Check for generic coprocessor hazards.
6389 This case is not handled very well. There is no special
6390 knowledge of CP0 handling, and the coprocessors other than
6391 the floating point unit are not distinguished at all. */
6392 /* Itbl support may require additional care here. FIXME!
6393 Need to modify this to include knowledge about
6394 user specified delays! */
6395 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6396 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6398 /* Handle cases where INSN1 writes to a known general coprocessor
6399 register. There must be a one instruction delay before INSN2
6400 if INSN2 reads that register, otherwise no delay is needed. */
6401 mask
= fpr_write_mask (insn1
);
6404 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6409 /* Read-after-write dependencies on the control registers
6410 require a two-instruction gap. */
6411 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6412 && (pinfo2
& INSN_READ_COND_CODE
))
6415 /* We don't know exactly what INSN1 does. If INSN2 is
6416 also a coprocessor instruction, assume there must be
6417 a one instruction gap. */
6418 if (pinfo2
& INSN_COP
)
6423 /* Check for read-after-write dependencies on the coprocessor
6424 control registers in cases where INSN1 does not need a general
6425 coprocessor delay. This means that INSN1 is a floating point
6426 comparison instruction. */
6427 /* Itbl support may require additional care here. */
6428 else if (!cop_interlocks
6429 && (pinfo1
& INSN_WRITE_COND_CODE
)
6430 && (pinfo2
& INSN_READ_COND_CODE
))
6434 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6435 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6437 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6438 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6439 || (insn2
&& delayed_branch_p (insn2
))))
6445 /* Return the number of nops that would be needed to work around the
6446 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6447 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6448 that are contained within the first IGNORE instructions of HIST. */
6451 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6452 const struct mips_cl_insn
*insn
)
6457 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6458 are not affected by the errata. */
6460 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6461 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6462 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6465 /* Search for the first MFLO or MFHI. */
6466 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6467 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6469 /* Extract the destination register. */
6470 mask
= gpr_write_mask (&hist
[i
]);
6472 /* No nops are needed if INSN reads that register. */
6473 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6476 /* ...or if any of the intervening instructions do. */
6477 for (j
= 0; j
< i
; j
++)
6478 if (gpr_read_mask (&hist
[j
]) & mask
)
6482 return MAX_VR4130_NOPS
- i
;
6487 #define BASE_REG_EQ(INSN1, INSN2) \
6488 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6489 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6491 /* Return the minimum alignment for this store instruction. */
6494 fix_24k_align_to (const struct mips_opcode
*mo
)
6496 if (strcmp (mo
->name
, "sh") == 0)
6499 if (strcmp (mo
->name
, "swc1") == 0
6500 || strcmp (mo
->name
, "swc2") == 0
6501 || strcmp (mo
->name
, "sw") == 0
6502 || strcmp (mo
->name
, "sc") == 0
6503 || strcmp (mo
->name
, "s.s") == 0)
6506 if (strcmp (mo
->name
, "sdc1") == 0
6507 || strcmp (mo
->name
, "sdc2") == 0
6508 || strcmp (mo
->name
, "s.d") == 0)
6515 struct fix_24k_store_info
6517 /* Immediate offset, if any, for this store instruction. */
6519 /* Alignment required by this store instruction. */
6521 /* True for register offsets. */
6522 int register_offset
;
6525 /* Comparison function used by qsort. */
6528 fix_24k_sort (const void *a
, const void *b
)
6530 const struct fix_24k_store_info
*pos1
= a
;
6531 const struct fix_24k_store_info
*pos2
= b
;
6533 return (pos1
->off
- pos2
->off
);
6536 /* INSN is a store instruction. Try to record the store information
6537 in STINFO. Return false if the information isn't known. */
6540 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6541 const struct mips_cl_insn
*insn
)
6543 /* The instruction must have a known offset. */
6544 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6547 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6548 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6552 /* Return the number of nops that would be needed to work around the 24k
6553 "lost data on stores during refill" errata if instruction INSN
6554 immediately followed the 2 instructions described by HIST.
6555 Ignore hazards that are contained within the first IGNORE
6556 instructions of HIST.
6558 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6559 for the data cache refills and store data. The following describes
6560 the scenario where the store data could be lost.
6562 * A data cache miss, due to either a load or a store, causing fill
6563 data to be supplied by the memory subsystem
6564 * The first three doublewords of fill data are returned and written
6566 * A sequence of four stores occurs in consecutive cycles around the
6567 final doubleword of the fill:
6571 * Zero, One or more instructions
6574 The four stores A-D must be to different doublewords of the line that
6575 is being filled. The fourth instruction in the sequence above permits
6576 the fill of the final doubleword to be transferred from the FSB into
6577 the cache. In the sequence above, the stores may be either integer
6578 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6579 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6580 different doublewords on the line. If the floating point unit is
6581 running in 1:2 mode, it is not possible to create the sequence above
6582 using only floating point store instructions.
6584 In this case, the cache line being filled is incorrectly marked
6585 invalid, thereby losing the data from any store to the line that
6586 occurs between the original miss and the completion of the five
6587 cycle sequence shown above.
6589 The workarounds are:
6591 * Run the data cache in write-through mode.
6592 * Insert a non-store instruction between
6593 Store A and Store B or Store B and Store C. */
6596 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6597 const struct mips_cl_insn
*insn
)
6599 struct fix_24k_store_info pos
[3];
6600 int align
, i
, base_offset
;
6605 /* If the previous instruction wasn't a store, there's nothing to
6607 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6610 /* If the instructions after the previous one are unknown, we have
6611 to assume the worst. */
6615 /* Check whether we are dealing with three consecutive stores. */
6616 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6617 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6620 /* If we don't know the relationship between the store addresses,
6621 assume the worst. */
6622 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6623 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6626 if (!fix_24k_record_store_info (&pos
[0], insn
)
6627 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6628 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6631 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6633 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6634 X bytes and such that the base register + X is known to be aligned
6637 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6641 align
= pos
[0].align_to
;
6642 base_offset
= pos
[0].off
;
6643 for (i
= 1; i
< 3; i
++)
6644 if (align
< pos
[i
].align_to
)
6646 align
= pos
[i
].align_to
;
6647 base_offset
= pos
[i
].off
;
6649 for (i
= 0; i
< 3; i
++)
6650 pos
[i
].off
-= base_offset
;
6653 pos
[0].off
&= ~align
+ 1;
6654 pos
[1].off
&= ~align
+ 1;
6655 pos
[2].off
&= ~align
+ 1;
6657 /* If any two stores write to the same chunk, they also write to the
6658 same doubleword. The offsets are still sorted at this point. */
6659 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6662 /* A range of at least 9 bytes is needed for the stores to be in
6663 non-overlapping doublewords. */
6664 if (pos
[2].off
- pos
[0].off
<= 8)
6667 if (pos
[2].off
- pos
[1].off
>= 24
6668 || pos
[1].off
- pos
[0].off
>= 24
6669 || pos
[2].off
- pos
[0].off
>= 32)
6675 /* Return the number of nops that would be needed if instruction INSN
6676 immediately followed the MAX_NOPS instructions given by HIST,
6677 where HIST[0] is the most recent instruction. Ignore hazards
6678 between INSN and the first IGNORE instructions in HIST.
6680 If INSN is null, return the worse-case number of nops for any
6684 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6685 const struct mips_cl_insn
*insn
)
6687 int i
, nops
, tmp_nops
;
6690 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6692 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6693 if (tmp_nops
> nops
)
6697 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6699 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6700 if (tmp_nops
> nops
)
6704 if (mips_fix_24k
&& !mips_opts
.micromips
)
6706 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6707 if (tmp_nops
> nops
)
6714 /* The variable arguments provide NUM_INSNS extra instructions that
6715 might be added to HIST. Return the largest number of nops that
6716 would be needed after the extended sequence, ignoring hazards
6717 in the first IGNORE instructions. */
6720 nops_for_sequence (int num_insns
, int ignore
,
6721 const struct mips_cl_insn
*hist
, ...)
6724 struct mips_cl_insn buffer
[MAX_NOPS
];
6725 struct mips_cl_insn
*cursor
;
6728 va_start (args
, hist
);
6729 cursor
= buffer
+ num_insns
;
6730 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6731 while (cursor
> buffer
)
6732 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6734 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6739 /* Like nops_for_insn, but if INSN is a branch, take into account the
6740 worst-case delay for the branch target. */
6743 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6744 const struct mips_cl_insn
*insn
)
6748 nops
= nops_for_insn (ignore
, hist
, insn
);
6749 if (delayed_branch_p (insn
))
6751 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6752 hist
, insn
, get_delay_slot_nop (insn
));
6753 if (tmp_nops
> nops
)
6756 else if (compact_branch_p (insn
))
6758 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6759 if (tmp_nops
> nops
)
6765 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6768 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6770 gas_assert (!HAVE_CODE_COMPRESSION
);
6771 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6772 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6775 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6776 jr target pc &= 'hffff_ffff_cfff_ffff. */
6779 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6781 gas_assert (!HAVE_CODE_COMPRESSION
);
6782 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6783 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6784 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6792 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6793 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6796 ep
.X_op
= O_constant
;
6797 ep
.X_add_number
= 0xcfff0000;
6798 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6799 ep
.X_add_number
= 0xffff;
6800 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6801 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6806 fix_loongson2f (struct mips_cl_insn
* ip
)
6808 if (mips_fix_loongson2f_nop
)
6809 fix_loongson2f_nop (ip
);
6811 if (mips_fix_loongson2f_jump
)
6812 fix_loongson2f_jump (ip
);
6815 /* IP is a branch that has a delay slot, and we need to fill it
6816 automatically. Return true if we can do that by swapping IP
6817 with the previous instruction.
6818 ADDRESS_EXPR is an operand of the instruction to be used with
6822 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6823 bfd_reloc_code_real_type
*reloc_type
)
6825 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6826 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6827 unsigned int fpr_read
, prev_fpr_write
;
6829 /* -O2 and above is required for this optimization. */
6830 if (mips_optimize
< 2)
6833 /* If we have seen .set volatile or .set nomove, don't optimize. */
6834 if (mips_opts
.nomove
)
6837 /* We can't swap if the previous instruction's position is fixed. */
6838 if (history
[0].fixed_p
)
6841 /* If the previous previous insn was in a .set noreorder, we can't
6842 swap. Actually, the MIPS assembler will swap in this situation.
6843 However, gcc configured -with-gnu-as will generate code like
6851 in which we can not swap the bne and INSN. If gcc is not configured
6852 -with-gnu-as, it does not output the .set pseudo-ops. */
6853 if (history
[1].noreorder_p
)
6856 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6857 This means that the previous instruction was a 4-byte one anyhow. */
6858 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6861 /* If the branch is itself the target of a branch, we can not swap.
6862 We cheat on this; all we check for is whether there is a label on
6863 this instruction. If there are any branches to anything other than
6864 a label, users must use .set noreorder. */
6865 if (seg_info (now_seg
)->label_list
)
6868 /* If the previous instruction is in a variant frag other than this
6869 branch's one, we cannot do the swap. This does not apply to
6870 MIPS16 code, which uses variant frags for different purposes. */
6871 if (!mips_opts
.mips16
6873 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6876 /* We do not swap with instructions that cannot architecturally
6877 be placed in a branch delay slot, such as SYNC or ERET. We
6878 also refrain from swapping with a trap instruction, since it
6879 complicates trap handlers to have the trap instruction be in
6881 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6882 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6885 /* Check for conflicts between the branch and the instructions
6886 before the candidate delay slot. */
6887 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6890 /* Check for conflicts between the swapped sequence and the
6891 target of the branch. */
6892 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6895 /* If the branch reads a register that the previous
6896 instruction sets, we can not swap. */
6897 gpr_read
= gpr_read_mask (ip
);
6898 prev_gpr_write
= gpr_write_mask (&history
[0]);
6899 if (gpr_read
& prev_gpr_write
)
6902 fpr_read
= fpr_read_mask (ip
);
6903 prev_fpr_write
= fpr_write_mask (&history
[0]);
6904 if (fpr_read
& prev_fpr_write
)
6907 /* If the branch writes a register that the previous
6908 instruction sets, we can not swap. */
6909 gpr_write
= gpr_write_mask (ip
);
6910 if (gpr_write
& prev_gpr_write
)
6913 /* If the branch writes a register that the previous
6914 instruction reads, we can not swap. */
6915 prev_gpr_read
= gpr_read_mask (&history
[0]);
6916 if (gpr_write
& prev_gpr_read
)
6919 /* If one instruction sets a condition code and the
6920 other one uses a condition code, we can not swap. */
6921 pinfo
= ip
->insn_mo
->pinfo
;
6922 if ((pinfo
& INSN_READ_COND_CODE
)
6923 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6925 if ((pinfo
& INSN_WRITE_COND_CODE
)
6926 && (prev_pinfo
& INSN_READ_COND_CODE
))
6929 /* If the previous instruction uses the PC, we can not swap. */
6930 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6931 if (prev_pinfo2
& INSN2_READ_PC
)
6934 /* If the previous instruction has an incorrect size for a fixed
6935 branch delay slot in microMIPS mode, we cannot swap. */
6936 pinfo2
= ip
->insn_mo
->pinfo2
;
6937 if (mips_opts
.micromips
6938 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6939 && insn_length (history
) != 2)
6941 if (mips_opts
.micromips
6942 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6943 && insn_length (history
) != 4)
6946 /* On R5900 short loops need to be fixed by inserting a nop in
6947 the branch delay slots.
6948 A short loop can be terminated too early. */
6949 if (mips_opts
.arch
== CPU_R5900
6950 /* Check if instruction has a parameter, ignore "j $31". */
6951 && (address_expr
!= NULL
)
6952 /* Parameter must be 16 bit. */
6953 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6954 /* Branch to same segment. */
6955 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
6956 /* Branch to same code fragment. */
6957 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
6958 /* Can only calculate branch offset if value is known. */
6959 && symbol_constant_p (address_expr
->X_add_symbol
)
6960 /* Check if branch is really conditional. */
6961 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6962 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6963 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6966 /* Check if loop is shorter than 6 instructions including
6967 branch and delay slot. */
6968 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
6975 /* When the loop includes branches or jumps,
6976 it is not a short loop. */
6977 for (i
= 0; i
< (distance
/ 4); i
++)
6979 if ((history
[i
].cleared_p
)
6980 || delayed_branch_p (&history
[i
]))
6988 /* Insert nop after branch to fix short loop. */
6997 /* Decide how we should add IP to the instruction stream.
6998 ADDRESS_EXPR is an operand of the instruction to be used with
7001 static enum append_method
7002 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7003 bfd_reloc_code_real_type
*reloc_type
)
7005 /* The relaxed version of a macro sequence must be inherently
7007 if (mips_relax
.sequence
== 2)
7010 /* We must not dabble with instructions in a ".set noreorder" block. */
7011 if (mips_opts
.noreorder
)
7014 /* Otherwise, it's our responsibility to fill branch delay slots. */
7015 if (delayed_branch_p (ip
))
7017 if (!branch_likely_p (ip
)
7018 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7021 if (mips_opts
.mips16
7022 && ISA_SUPPORTS_MIPS16E
7023 && gpr_read_mask (ip
) != 0)
7024 return APPEND_ADD_COMPACT
;
7026 if (mips_opts
.micromips
7027 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7028 || (!forced_insn_length
7029 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7030 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7031 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7032 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7033 return APPEND_ADD_COMPACT
;
7035 return APPEND_ADD_WITH_NOP
;
7041 /* IP is an instruction whose opcode we have just changed, END points
7042 to the end of the opcode table processed. Point IP->insn_mo to the
7043 new opcode's definition. */
7046 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7048 const struct mips_opcode
*mo
;
7050 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7051 if (mo
->pinfo
!= INSN_MACRO
7052 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7060 /* IP is a MIPS16 instruction whose opcode we have just changed.
7061 Point IP->insn_mo to the new opcode's definition. */
7064 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7066 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7069 /* IP is a microMIPS instruction whose opcode we have just changed.
7070 Point IP->insn_mo to the new opcode's definition. */
7073 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7075 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7078 /* For microMIPS macros, we need to generate a local number label
7079 as the target of branches. */
7080 #define MICROMIPS_LABEL_CHAR '\037'
7081 static unsigned long micromips_target_label
;
7082 static char micromips_target_name
[32];
7085 micromips_label_name (void)
7087 char *p
= micromips_target_name
;
7088 char symbol_name_temporary
[24];
7096 l
= micromips_target_label
;
7097 #ifdef LOCAL_LABEL_PREFIX
7098 *p
++ = LOCAL_LABEL_PREFIX
;
7101 *p
++ = MICROMIPS_LABEL_CHAR
;
7104 symbol_name_temporary
[i
++] = l
% 10 + '0';
7109 *p
++ = symbol_name_temporary
[--i
];
7112 return micromips_target_name
;
7116 micromips_label_expr (expressionS
*label_expr
)
7118 label_expr
->X_op
= O_symbol
;
7119 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7120 label_expr
->X_add_number
= 0;
7124 micromips_label_inc (void)
7126 micromips_target_label
++;
7127 *micromips_target_name
= '\0';
7131 micromips_add_label (void)
7135 s
= colon (micromips_label_name ());
7136 micromips_label_inc ();
7137 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7140 /* If assembling microMIPS code, then return the microMIPS reloc
7141 corresponding to the requested one if any. Otherwise return
7142 the reloc unchanged. */
7144 static bfd_reloc_code_real_type
7145 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7147 static const bfd_reloc_code_real_type relocs
[][2] =
7149 /* Keep sorted incrementally by the left-hand key. */
7150 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7151 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7152 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7153 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7154 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7155 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7156 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7157 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7158 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7159 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7160 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7161 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7162 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7163 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7164 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7165 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7166 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7167 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7168 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7169 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7170 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7171 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7172 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7173 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7174 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7175 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7176 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7178 bfd_reloc_code_real_type r
;
7181 if (!mips_opts
.micromips
)
7183 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7189 return relocs
[i
][1];
7194 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7195 Return true on success, storing the resolved value in RESULT. */
7198 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7203 case BFD_RELOC_MIPS_HIGHEST
:
7204 case BFD_RELOC_MICROMIPS_HIGHEST
:
7205 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7208 case BFD_RELOC_MIPS_HIGHER
:
7209 case BFD_RELOC_MICROMIPS_HIGHER
:
7210 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7213 case BFD_RELOC_HI16_S
:
7214 case BFD_RELOC_HI16_S_PCREL
:
7215 case BFD_RELOC_MICROMIPS_HI16_S
:
7216 case BFD_RELOC_MIPS16_HI16_S
:
7217 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7220 case BFD_RELOC_HI16
:
7221 case BFD_RELOC_MICROMIPS_HI16
:
7222 case BFD_RELOC_MIPS16_HI16
:
7223 *result
= (operand
>> 16) & 0xffff;
7226 case BFD_RELOC_LO16
:
7227 case BFD_RELOC_LO16_PCREL
:
7228 case BFD_RELOC_MICROMIPS_LO16
:
7229 case BFD_RELOC_MIPS16_LO16
:
7230 *result
= operand
& 0xffff;
7233 case BFD_RELOC_UNUSED
:
7242 /* Output an instruction. IP is the instruction information.
7243 ADDRESS_EXPR is an operand of the instruction to be used with
7244 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7245 a macro expansion. */
7248 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7249 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7251 unsigned long prev_pinfo2
, pinfo
;
7252 bfd_boolean relaxed_branch
= FALSE
;
7253 enum append_method method
;
7254 bfd_boolean relax32
;
7257 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7258 fix_loongson2f (ip
);
7260 file_ase_mips16
|= mips_opts
.mips16
;
7261 file_ase_micromips
|= mips_opts
.micromips
;
7263 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7264 pinfo
= ip
->insn_mo
->pinfo
;
7266 /* Don't raise alarm about `nods' frags as they'll fill in the right
7267 kind of nop in relaxation if required. */
7268 if (mips_opts
.micromips
7270 && !(history
[0].frag
7271 && history
[0].frag
->fr_type
== rs_machine_dependent
7272 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7273 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7274 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7275 && micromips_insn_length (ip
->insn_mo
) != 2)
7276 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7277 && micromips_insn_length (ip
->insn_mo
) != 4)))
7278 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7279 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7281 if (address_expr
== NULL
)
7283 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7284 && reloc_type
[1] == BFD_RELOC_UNUSED
7285 && reloc_type
[2] == BFD_RELOC_UNUSED
7286 && address_expr
->X_op
== O_constant
)
7288 switch (*reloc_type
)
7290 case BFD_RELOC_MIPS_JMP
:
7294 /* Shift is 2, unusually, for microMIPS JALX. */
7295 shift
= (mips_opts
.micromips
7296 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7297 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7298 as_bad (_("jump to misaligned address (0x%lx)"),
7299 (unsigned long) address_expr
->X_add_number
);
7300 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7306 case BFD_RELOC_MIPS16_JMP
:
7307 if ((address_expr
->X_add_number
& 3) != 0)
7308 as_bad (_("jump to misaligned address (0x%lx)"),
7309 (unsigned long) address_expr
->X_add_number
);
7311 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7312 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7313 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7317 case BFD_RELOC_16_PCREL_S2
:
7321 shift
= mips_opts
.micromips
? 1 : 2;
7322 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7323 as_bad (_("branch to misaligned address (0x%lx)"),
7324 (unsigned long) address_expr
->X_add_number
);
7325 if (!mips_relax_branch
)
7327 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7328 & ~((1 << (shift
+ 16)) - 1))
7329 as_bad (_("branch address range overflow (0x%lx)"),
7330 (unsigned long) address_expr
->X_add_number
);
7331 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7337 case BFD_RELOC_MIPS_21_PCREL_S2
:
7342 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7343 as_bad (_("branch to misaligned address (0x%lx)"),
7344 (unsigned long) address_expr
->X_add_number
);
7345 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7346 & ~((1 << (shift
+ 21)) - 1))
7347 as_bad (_("branch address range overflow (0x%lx)"),
7348 (unsigned long) address_expr
->X_add_number
);
7349 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7354 case BFD_RELOC_MIPS_26_PCREL_S2
:
7359 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7360 as_bad (_("branch to misaligned address (0x%lx)"),
7361 (unsigned long) address_expr
->X_add_number
);
7362 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7363 & ~((1 << (shift
+ 26)) - 1))
7364 as_bad (_("branch address range overflow (0x%lx)"),
7365 (unsigned long) address_expr
->X_add_number
);
7366 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7375 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7378 ip
->insn_opcode
|= value
& 0xffff;
7386 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7388 /* There are a lot of optimizations we could do that we don't.
7389 In particular, we do not, in general, reorder instructions.
7390 If you use gcc with optimization, it will reorder
7391 instructions and generally do much more optimization then we
7392 do here; repeating all that work in the assembler would only
7393 benefit hand written assembly code, and does not seem worth
7395 int nops
= (mips_optimize
== 0
7396 ? nops_for_insn (0, history
, NULL
)
7397 : nops_for_insn_or_target (0, history
, ip
));
7401 unsigned long old_frag_offset
;
7404 old_frag
= frag_now
;
7405 old_frag_offset
= frag_now_fix ();
7407 for (i
= 0; i
< nops
; i
++)
7408 add_fixed_insn (NOP_INSN
);
7409 insert_into_history (0, nops
, NOP_INSN
);
7413 listing_prev_line ();
7414 /* We may be at the start of a variant frag. In case we
7415 are, make sure there is enough space for the frag
7416 after the frags created by listing_prev_line. The
7417 argument to frag_grow here must be at least as large
7418 as the argument to all other calls to frag_grow in
7419 this file. We don't have to worry about being in the
7420 middle of a variant frag, because the variants insert
7421 all needed nop instructions themselves. */
7425 mips_move_text_labels ();
7427 #ifndef NO_ECOFF_DEBUGGING
7428 if (ECOFF_DEBUGGING
)
7429 ecoff_fix_loc (old_frag
, old_frag_offset
);
7433 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7437 /* Work out how many nops in prev_nop_frag are needed by IP,
7438 ignoring hazards generated by the first prev_nop_frag_since
7440 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7441 gas_assert (nops
<= prev_nop_frag_holds
);
7443 /* Enforce NOPS as a minimum. */
7444 if (nops
> prev_nop_frag_required
)
7445 prev_nop_frag_required
= nops
;
7447 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7449 /* Settle for the current number of nops. Update the history
7450 accordingly (for the benefit of any future .set reorder code). */
7451 prev_nop_frag
= NULL
;
7452 insert_into_history (prev_nop_frag_since
,
7453 prev_nop_frag_holds
, NOP_INSN
);
7457 /* Allow this instruction to replace one of the nops that was
7458 tentatively added to prev_nop_frag. */
7459 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7460 prev_nop_frag_holds
--;
7461 prev_nop_frag_since
++;
7465 method
= get_append_method (ip
, address_expr
, reloc_type
);
7466 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7468 dwarf2_emit_insn (0);
7469 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7470 so "move" the instruction address accordingly.
7472 Also, it doesn't seem appropriate for the assembler to reorder .loc
7473 entries. If this instruction is a branch that we are going to swap
7474 with the previous instruction, the two instructions should be
7475 treated as a unit, and the debug information for both instructions
7476 should refer to the start of the branch sequence. Using the
7477 current position is certainly wrong when swapping a 32-bit branch
7478 and a 16-bit delay slot, since the current position would then be
7479 in the middle of a branch. */
7480 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7482 relax32
= (mips_relax_branch
7483 /* Don't try branch relaxation within .set nomacro, or within
7484 .set noat if we use $at for PIC computations. If it turns
7485 out that the branch was out-of-range, we'll get an error. */
7486 && !mips_opts
.warn_about_macros
7487 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7488 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7489 as they have no complementing branches. */
7490 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7492 if (!HAVE_CODE_COMPRESSION
7495 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7496 && delayed_branch_p (ip
))
7498 relaxed_branch
= TRUE
;
7499 add_relaxed_insn (ip
, (relaxed_branch_length
7501 uncond_branch_p (ip
) ? -1
7502 : branch_likely_p (ip
) ? 1
7505 (AT
, mips_pic
!= NO_PIC
,
7506 uncond_branch_p (ip
),
7507 branch_likely_p (ip
),
7508 pinfo
& INSN_WRITE_GPR_31
,
7510 address_expr
->X_add_symbol
,
7511 address_expr
->X_add_number
);
7512 *reloc_type
= BFD_RELOC_UNUSED
;
7514 else if (mips_opts
.micromips
7516 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7517 || *reloc_type
> BFD_RELOC_UNUSED
)
7518 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7519 /* Don't try branch relaxation when users specify
7520 16-bit/32-bit instructions. */
7521 && !forced_insn_length
)
7523 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7524 && *reloc_type
> BFD_RELOC_UNUSED
);
7525 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7526 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7527 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7528 int nods
= method
== APPEND_ADD_WITH_NOP
;
7529 int al
= pinfo
& INSN_WRITE_GPR_31
;
7530 int length32
= nods
? 8 : 4;
7532 gas_assert (address_expr
!= NULL
);
7533 gas_assert (!mips_relax
.sequence
);
7535 relaxed_branch
= TRUE
;
7537 method
= APPEND_ADD
;
7539 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7540 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7541 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7543 uncond
, compact
, al
, nods
,
7545 address_expr
->X_add_symbol
,
7546 address_expr
->X_add_number
);
7547 *reloc_type
= BFD_RELOC_UNUSED
;
7549 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7551 bfd_boolean require_unextended
;
7552 bfd_boolean require_extended
;
7556 if (forced_insn_length
!= 0)
7558 require_unextended
= forced_insn_length
== 2;
7559 require_extended
= forced_insn_length
== 4;
7563 require_unextended
= (mips_opts
.noautoextend
7564 && !mips_opcode_32bit_p (ip
->insn_mo
));
7565 require_extended
= 0;
7568 /* We need to set up a variant frag. */
7569 gas_assert (address_expr
!= NULL
);
7570 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7571 symbol created by `make_expr_symbol' may not get a necessary
7572 external relocation produced. */
7573 if (address_expr
->X_op
== O_symbol
)
7575 symbol
= address_expr
->X_add_symbol
;
7576 offset
= address_expr
->X_add_number
;
7580 symbol
= make_expr_symbol (address_expr
);
7581 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7584 add_relaxed_insn (ip
, 12, 0,
7586 (*reloc_type
- BFD_RELOC_UNUSED
,
7587 mips_opts
.ase
& ASE_MIPS16E2
,
7590 mips_opts
.warn_about_macros
,
7591 require_unextended
, require_extended
,
7592 delayed_branch_p (&history
[0]),
7593 history
[0].mips16_absolute_jump_p
),
7596 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7598 if (!delayed_branch_p (ip
))
7599 /* Make sure there is enough room to swap this instruction with
7600 a following jump instruction. */
7602 add_fixed_insn (ip
);
7606 if (mips_opts
.mips16
7607 && mips_opts
.noreorder
7608 && delayed_branch_p (&history
[0]))
7609 as_warn (_("extended instruction in delay slot"));
7611 if (mips_relax
.sequence
)
7613 /* If we've reached the end of this frag, turn it into a variant
7614 frag and record the information for the instructions we've
7616 if (frag_room () < 4)
7617 relax_close_frag ();
7618 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7621 if (mips_relax
.sequence
!= 2)
7623 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7624 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7625 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7626 mips_macro_warning
.insns
[0]++;
7628 if (mips_relax
.sequence
!= 1)
7630 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7631 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7632 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7633 mips_macro_warning
.insns
[1]++;
7636 if (mips_opts
.mips16
)
7639 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7641 add_fixed_insn (ip
);
7644 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7646 bfd_reloc_code_real_type final_type
[3];
7647 reloc_howto_type
*howto0
;
7648 reloc_howto_type
*howto
;
7651 /* Perform any necessary conversion to microMIPS relocations
7652 and find out how many relocations there actually are. */
7653 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7654 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7656 /* In a compound relocation, it is the final (outermost)
7657 operator that determines the relocated field. */
7658 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7663 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7664 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7665 bfd_get_reloc_size (howto
),
7667 howto0
&& howto0
->pc_relative
,
7669 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7670 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7672 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7673 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7674 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7676 /* These relocations can have an addend that won't fit in
7677 4 octets for 64bit assembly. */
7679 && ! howto
->partial_inplace
7680 && (reloc_type
[0] == BFD_RELOC_16
7681 || reloc_type
[0] == BFD_RELOC_32
7682 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7683 || reloc_type
[0] == BFD_RELOC_GPREL16
7684 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7685 || reloc_type
[0] == BFD_RELOC_GPREL32
7686 || reloc_type
[0] == BFD_RELOC_64
7687 || reloc_type
[0] == BFD_RELOC_CTOR
7688 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7689 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7690 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7691 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7692 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7693 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7694 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7695 || hi16_reloc_p (reloc_type
[0])
7696 || lo16_reloc_p (reloc_type
[0])))
7697 ip
->fixp
[0]->fx_no_overflow
= 1;
7699 /* These relocations can have an addend that won't fit in 2 octets. */
7700 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7701 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7702 ip
->fixp
[0]->fx_no_overflow
= 1;
7704 if (mips_relax
.sequence
)
7706 if (mips_relax
.first_fixup
== 0)
7707 mips_relax
.first_fixup
= ip
->fixp
[0];
7709 else if (reloc_needs_lo_p (*reloc_type
))
7711 struct mips_hi_fixup
*hi_fixup
;
7713 /* Reuse the last entry if it already has a matching %lo. */
7714 hi_fixup
= mips_hi_fixup_list
;
7716 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7718 hi_fixup
= XNEW (struct mips_hi_fixup
);
7719 hi_fixup
->next
= mips_hi_fixup_list
;
7720 mips_hi_fixup_list
= hi_fixup
;
7722 hi_fixup
->fixp
= ip
->fixp
[0];
7723 hi_fixup
->seg
= now_seg
;
7726 /* Add fixups for the second and third relocations, if given.
7727 Note that the ABI allows the second relocation to be
7728 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7729 moment we only use RSS_UNDEF, but we could add support
7730 for the others if it ever becomes necessary. */
7731 for (i
= 1; i
< 3; i
++)
7732 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7734 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7735 ip
->fixp
[0]->fx_size
, NULL
, 0,
7736 FALSE
, final_type
[i
]);
7738 /* Use fx_tcbit to mark compound relocs. */
7739 ip
->fixp
[0]->fx_tcbit
= 1;
7740 ip
->fixp
[i
]->fx_tcbit
= 1;
7744 /* Update the register mask information. */
7745 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7746 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7751 insert_into_history (0, 1, ip
);
7754 case APPEND_ADD_WITH_NOP
:
7756 struct mips_cl_insn
*nop
;
7758 insert_into_history (0, 1, ip
);
7759 nop
= get_delay_slot_nop (ip
);
7760 add_fixed_insn (nop
);
7761 insert_into_history (0, 1, nop
);
7762 if (mips_relax
.sequence
)
7763 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7767 case APPEND_ADD_COMPACT
:
7768 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7769 if (mips_opts
.mips16
)
7771 ip
->insn_opcode
|= 0x0080;
7772 find_altered_mips16_opcode (ip
);
7774 /* Convert microMIPS instructions. */
7775 else if (mips_opts
.micromips
)
7778 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7779 ip
->insn_opcode
|= 0x0020;
7781 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7782 ip
->insn_opcode
= 0x40e00000;
7783 /* beqz16->beqzc, bnez16->bnezc */
7784 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7786 unsigned long regno
;
7788 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7789 regno
&= MICROMIPSOP_MASK_MD
;
7790 regno
= micromips_to_32_reg_d_map
[regno
];
7791 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7792 | (regno
<< MICROMIPSOP_SH_RS
)
7793 | 0x40a00000) ^ 0x00400000;
7795 /* beqz->beqzc, bnez->bnezc */
7796 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7797 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7798 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7799 | 0x40a00000) ^ 0x00400000;
7800 /* beq $0->beqzc, bne $0->bnezc */
7801 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
7802 ip
->insn_opcode
= (((ip
->insn_opcode
>>
7803 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
7804 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
7805 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7806 | 0x40a00000) ^ 0x00400000;
7809 find_altered_micromips_opcode (ip
);
7814 insert_into_history (0, 1, ip
);
7819 struct mips_cl_insn delay
= history
[0];
7821 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7823 /* Add the delay slot instruction to the end of the
7824 current frag and shrink the fixed part of the
7825 original frag. If the branch occupies the tail of
7826 the latter, move it backwards to cover the gap. */
7827 delay
.frag
->fr_fix
-= branch_disp
;
7828 if (delay
.frag
== ip
->frag
)
7829 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7830 add_fixed_insn (&delay
);
7834 /* If this is not a relaxed branch and we are in the
7835 same frag, then just swap the instructions. */
7836 move_insn (ip
, delay
.frag
, delay
.where
);
7837 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7841 insert_into_history (0, 1, &delay
);
7846 /* If we have just completed an unconditional branch, clear the history. */
7847 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7848 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7852 mips_no_prev_insn ();
7854 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7855 history
[i
].cleared_p
= 1;
7858 /* We need to emit a label at the end of branch-likely macros. */
7859 if (emit_branch_likely_macro
)
7861 emit_branch_likely_macro
= FALSE
;
7862 micromips_add_label ();
7865 /* We just output an insn, so the next one doesn't have a label. */
7866 mips_clear_insn_labels ();
7869 /* Forget that there was any previous instruction or label.
7870 When BRANCH is true, the branch history is also flushed. */
7873 mips_no_prev_insn (void)
7875 prev_nop_frag
= NULL
;
7876 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7877 mips_clear_insn_labels ();
7880 /* This function must be called before we emit something other than
7881 instructions. It is like mips_no_prev_insn except that it inserts
7882 any NOPS that might be needed by previous instructions. */
7885 mips_emit_delays (void)
7887 if (! mips_opts
.noreorder
)
7889 int nops
= nops_for_insn (0, history
, NULL
);
7893 add_fixed_insn (NOP_INSN
);
7894 mips_move_text_labels ();
7897 mips_no_prev_insn ();
7900 /* Start a (possibly nested) noreorder block. */
7903 start_noreorder (void)
7905 if (mips_opts
.noreorder
== 0)
7910 /* None of the instructions before the .set noreorder can be moved. */
7911 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7912 history
[i
].fixed_p
= 1;
7914 /* Insert any nops that might be needed between the .set noreorder
7915 block and the previous instructions. We will later remove any
7916 nops that turn out not to be needed. */
7917 nops
= nops_for_insn (0, history
, NULL
);
7920 if (mips_optimize
!= 0)
7922 /* Record the frag which holds the nop instructions, so
7923 that we can remove them if we don't need them. */
7924 frag_grow (nops
* NOP_INSN_SIZE
);
7925 prev_nop_frag
= frag_now
;
7926 prev_nop_frag_holds
= nops
;
7927 prev_nop_frag_required
= 0;
7928 prev_nop_frag_since
= 0;
7931 for (; nops
> 0; --nops
)
7932 add_fixed_insn (NOP_INSN
);
7934 /* Move on to a new frag, so that it is safe to simply
7935 decrease the size of prev_nop_frag. */
7936 frag_wane (frag_now
);
7938 mips_move_text_labels ();
7940 mips_mark_labels ();
7941 mips_clear_insn_labels ();
7943 mips_opts
.noreorder
++;
7944 mips_any_noreorder
= 1;
7947 /* End a nested noreorder block. */
7950 end_noreorder (void)
7952 mips_opts
.noreorder
--;
7953 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7955 /* Commit to inserting prev_nop_frag_required nops and go back to
7956 handling nop insertion the .set reorder way. */
7957 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7959 insert_into_history (prev_nop_frag_since
,
7960 prev_nop_frag_required
, NOP_INSN
);
7961 prev_nop_frag
= NULL
;
7965 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7966 higher bits unset. */
7969 normalize_constant_expr (expressionS
*ex
)
7971 if (ex
->X_op
== O_constant
7972 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7973 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7977 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7978 all higher bits unset. */
7981 normalize_address_expr (expressionS
*ex
)
7983 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7984 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7985 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7986 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7990 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7991 Return true if the match was successful.
7993 OPCODE_EXTRA is a value that should be ORed into the opcode
7994 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7995 there are more alternatives after OPCODE and SOFT_MATCH is
7996 as for mips_arg_info. */
7999 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8000 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8001 bfd_boolean lax_match
, bfd_boolean complete_p
)
8004 struct mips_arg_info arg
;
8005 const struct mips_operand
*operand
;
8008 imm_expr
.X_op
= O_absent
;
8009 offset_expr
.X_op
= O_absent
;
8010 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8011 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8012 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8014 create_insn (insn
, opcode
);
8015 /* When no opcode suffix is specified, assume ".xyzw". */
8016 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8017 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8019 insn
->insn_opcode
|= opcode_extra
;
8020 memset (&arg
, 0, sizeof (arg
));
8024 arg
.last_regno
= ILLEGAL_REG
;
8025 arg
.dest_regno
= ILLEGAL_REG
;
8026 arg
.lax_match
= lax_match
;
8027 for (args
= opcode
->args
;; ++args
)
8029 if (arg
.token
->type
== OT_END
)
8031 /* Handle unary instructions in which only one operand is given.
8032 The source is then the same as the destination. */
8033 if (arg
.opnum
== 1 && *args
== ',')
8035 operand
= (mips_opts
.micromips
8036 ? decode_micromips_operand (args
+ 1)
8037 : decode_mips_operand (args
+ 1));
8038 if (operand
&& mips_optional_operand_p (operand
))
8046 /* Treat elided base registers as $0. */
8047 if (strcmp (args
, "(b)") == 0)
8055 /* The register suffix is optional. */
8060 /* Fail the match if there were too few operands. */
8064 /* Successful match. */
8067 clear_insn_error ();
8068 if (arg
.dest_regno
== arg
.last_regno
8069 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8073 (0, _("source and destination must be different"));
8074 else if (arg
.last_regno
== 31)
8076 (0, _("a destination register must be supplied"));
8078 else if (arg
.last_regno
== 31
8079 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8080 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8081 set_insn_error (0, _("the source register must not be $31"));
8082 check_completed_insn (&arg
);
8086 /* Fail the match if the line has too many operands. */
8090 /* Handle characters that need to match exactly. */
8091 if (*args
== '(' || *args
== ')' || *args
== ',')
8093 if (match_char (&arg
, *args
))
8100 if (arg
.token
->type
== OT_DOUBLE_CHAR
8101 && arg
.token
->u
.ch
== *args
)
8109 /* Handle special macro operands. Work out the properties of
8118 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8122 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8131 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8135 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8139 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8145 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8147 imm_expr
.X_op
= O_constant
;
8149 normalize_constant_expr (&imm_expr
);
8153 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8155 /* Assume that the offset has been elided and that what
8156 we saw was a base register. The match will fail later
8157 if that assumption turns out to be wrong. */
8158 offset_expr
.X_op
= O_constant
;
8159 offset_expr
.X_add_number
= 0;
8163 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8165 normalize_address_expr (&offset_expr
);
8170 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8176 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8182 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8188 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8194 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8198 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8202 gas_assert (mips_opts
.micromips
);
8208 if (!forced_insn_length
)
8209 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8211 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8213 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8219 operand
= (mips_opts
.micromips
8220 ? decode_micromips_operand (args
)
8221 : decode_mips_operand (args
));
8225 /* Skip prefixes. */
8226 if (*args
== '+' || *args
== 'm' || *args
== '-')
8229 if (mips_optional_operand_p (operand
)
8231 && (arg
.token
[0].type
!= OT_REG
8232 || arg
.token
[1].type
== OT_END
))
8234 /* Assume that the register has been elided and is the
8235 same as the first operand. */
8240 if (!match_operand (&arg
, operand
))
8245 /* Like match_insn, but for MIPS16. */
8248 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8249 struct mips_operand_token
*tokens
)
8252 const struct mips_operand
*operand
;
8253 const struct mips_operand
*ext_operand
;
8254 bfd_boolean pcrel
= FALSE
;
8255 int required_insn_length
;
8256 struct mips_arg_info arg
;
8259 if (forced_insn_length
)
8260 required_insn_length
= forced_insn_length
;
8261 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8262 required_insn_length
= 2;
8264 required_insn_length
= 0;
8266 create_insn (insn
, opcode
);
8267 imm_expr
.X_op
= O_absent
;
8268 offset_expr
.X_op
= O_absent
;
8269 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8270 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8271 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8274 memset (&arg
, 0, sizeof (arg
));
8278 arg
.last_regno
= ILLEGAL_REG
;
8279 arg
.dest_regno
= ILLEGAL_REG
;
8281 for (args
= opcode
->args
;; ++args
)
8285 if (arg
.token
->type
== OT_END
)
8289 /* Handle unary instructions in which only one operand is given.
8290 The source is then the same as the destination. */
8291 if (arg
.opnum
== 1 && *args
== ',')
8293 operand
= decode_mips16_operand (args
[1], FALSE
);
8294 if (operand
&& mips_optional_operand_p (operand
))
8302 /* Fail the match if there were too few operands. */
8306 /* Successful match. Stuff the immediate value in now, if
8308 clear_insn_error ();
8309 if (opcode
->pinfo
== INSN_MACRO
)
8311 gas_assert (relax_char
== 0 || relax_char
== 'p');
8312 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8315 && offset_expr
.X_op
== O_constant
8317 && calculate_reloc (*offset_reloc
,
8318 offset_expr
.X_add_number
,
8321 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8322 required_insn_length
, &insn
->insn_opcode
);
8323 offset_expr
.X_op
= O_absent
;
8324 *offset_reloc
= BFD_RELOC_UNUSED
;
8326 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8328 if (required_insn_length
== 2)
8329 set_insn_error (0, _("invalid unextended operand value"));
8330 else if (!mips_opcode_32bit_p (opcode
))
8332 forced_insn_length
= 4;
8333 insn
->insn_opcode
|= MIPS16_EXTEND
;
8336 else if (relax_char
)
8337 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8339 check_completed_insn (&arg
);
8343 /* Fail the match if the line has too many operands. */
8347 /* Handle characters that need to match exactly. */
8348 if (*args
== '(' || *args
== ')' || *args
== ',')
8350 if (match_char (&arg
, *args
))
8370 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8372 imm_expr
.X_op
= O_constant
;
8374 normalize_constant_expr (&imm_expr
);
8379 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8383 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8387 if (operand
->type
== OP_PCREL
)
8391 ext_operand
= decode_mips16_operand (c
, TRUE
);
8392 if (operand
!= ext_operand
)
8394 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8396 offset_expr
.X_op
= O_constant
;
8397 offset_expr
.X_add_number
= 0;
8402 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8405 /* '8' is used for SLTI(U) and has traditionally not
8406 been allowed to take relocation operators. */
8407 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8408 && (ext_operand
->size
!= 16 || c
== '8'))
8410 match_not_constant (&arg
);
8414 if (offset_expr
.X_op
== O_big
)
8416 match_out_of_range (&arg
);
8425 if (mips_optional_operand_p (operand
)
8427 && (arg
.token
[0].type
!= OT_REG
8428 || arg
.token
[1].type
== OT_END
))
8430 /* Assume that the register has been elided and is the
8431 same as the first operand. */
8436 if (!match_operand (&arg
, operand
))
8441 /* Record that the current instruction is invalid for the current ISA. */
8444 match_invalid_for_isa (void)
8447 (0, _("opcode not supported on this processor: %s (%s)"),
8448 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8449 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8452 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8453 Return true if a definite match or failure was found, storing any match
8454 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8455 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8456 tried and failed to match under normal conditions and now want to try a
8457 more relaxed match. */
8460 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8461 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8462 int opcode_extra
, bfd_boolean lax_match
)
8464 const struct mips_opcode
*opcode
;
8465 const struct mips_opcode
*invalid_delay_slot
;
8466 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8468 /* Search for a match, ignoring alternatives that don't satisfy the
8469 current ISA or forced_length. */
8470 invalid_delay_slot
= 0;
8471 seen_valid_for_isa
= FALSE
;
8472 seen_valid_for_size
= FALSE
;
8476 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8477 if (is_opcode_valid (opcode
))
8479 seen_valid_for_isa
= TRUE
;
8480 if (is_size_valid (opcode
))
8482 bfd_boolean delay_slot_ok
;
8484 seen_valid_for_size
= TRUE
;
8485 delay_slot_ok
= is_delay_slot_valid (opcode
);
8486 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8487 lax_match
, delay_slot_ok
))
8491 if (!invalid_delay_slot
)
8492 invalid_delay_slot
= opcode
;
8501 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8503 /* If the only matches we found had the wrong length for the delay slot,
8504 pick the first such match. We'll issue an appropriate warning later. */
8505 if (invalid_delay_slot
)
8507 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8513 /* Handle the case where we didn't try to match an instruction because
8514 all the alternatives were incompatible with the current ISA. */
8515 if (!seen_valid_for_isa
)
8517 match_invalid_for_isa ();
8521 /* Handle the case where we didn't try to match an instruction because
8522 all the alternatives were of the wrong size. */
8523 if (!seen_valid_for_size
)
8525 if (mips_opts
.insn32
)
8526 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8529 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8530 8 * forced_insn_length
);
8537 /* Like match_insns, but for MIPS16. */
8540 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8541 struct mips_operand_token
*tokens
)
8543 const struct mips_opcode
*opcode
;
8544 bfd_boolean seen_valid_for_isa
;
8545 bfd_boolean seen_valid_for_size
;
8547 /* Search for a match, ignoring alternatives that don't satisfy the
8548 current ISA. There are no separate entries for extended forms so
8549 we deal with forced_length later. */
8550 seen_valid_for_isa
= FALSE
;
8551 seen_valid_for_size
= FALSE
;
8555 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8556 if (is_opcode_valid_16 (opcode
))
8558 seen_valid_for_isa
= TRUE
;
8559 if (is_size_valid_16 (opcode
))
8561 seen_valid_for_size
= TRUE
;
8562 if (match_mips16_insn (insn
, opcode
, tokens
))
8568 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8569 && strcmp (opcode
->name
, first
->name
) == 0);
8571 /* Handle the case where we didn't try to match an instruction because
8572 all the alternatives were incompatible with the current ISA. */
8573 if (!seen_valid_for_isa
)
8575 match_invalid_for_isa ();
8579 /* Handle the case where we didn't try to match an instruction because
8580 all the alternatives were of the wrong size. */
8581 if (!seen_valid_for_size
)
8583 if (forced_insn_length
== 2)
8585 (0, _("unrecognized unextended version of MIPS16 opcode"));
8588 (0, _("unrecognized extended version of MIPS16 opcode"));
8595 /* Set up global variables for the start of a new macro. */
8600 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8601 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8602 sizeof (mips_macro_warning
.first_insn_sizes
));
8603 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8604 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8605 && delayed_branch_p (&history
[0]));
8607 && history
[0].frag
->fr_type
== rs_machine_dependent
8608 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8609 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8610 mips_macro_warning
.delay_slot_length
= 0;
8612 switch (history
[0].insn_mo
->pinfo2
8613 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8615 case INSN2_BRANCH_DELAY_32BIT
:
8616 mips_macro_warning
.delay_slot_length
= 4;
8618 case INSN2_BRANCH_DELAY_16BIT
:
8619 mips_macro_warning
.delay_slot_length
= 2;
8622 mips_macro_warning
.delay_slot_length
= 0;
8625 mips_macro_warning
.first_frag
= NULL
;
8628 /* Given that a macro is longer than one instruction or of the wrong size,
8629 return the appropriate warning for it. Return null if no warning is
8630 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8631 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8632 and RELAX_NOMACRO. */
8635 macro_warning (relax_substateT subtype
)
8637 if (subtype
& RELAX_DELAY_SLOT
)
8638 return _("macro instruction expanded into multiple instructions"
8639 " in a branch delay slot");
8640 else if (subtype
& RELAX_NOMACRO
)
8641 return _("macro instruction expanded into multiple instructions");
8642 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8643 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8644 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8645 ? _("macro instruction expanded into a wrong size instruction"
8646 " in a 16-bit branch delay slot")
8647 : _("macro instruction expanded into a wrong size instruction"
8648 " in a 32-bit branch delay slot"));
8653 /* Finish up a macro. Emit warnings as appropriate. */
8658 /* Relaxation warning flags. */
8659 relax_substateT subtype
= 0;
8661 /* Check delay slot size requirements. */
8662 if (mips_macro_warning
.delay_slot_length
== 2)
8663 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8664 if (mips_macro_warning
.delay_slot_length
!= 0)
8666 if (mips_macro_warning
.delay_slot_length
8667 != mips_macro_warning
.first_insn_sizes
[0])
8668 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8669 if (mips_macro_warning
.delay_slot_length
8670 != mips_macro_warning
.first_insn_sizes
[1])
8671 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8674 /* Check instruction count requirements. */
8675 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8677 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8678 subtype
|= RELAX_SECOND_LONGER
;
8679 if (mips_opts
.warn_about_macros
)
8680 subtype
|= RELAX_NOMACRO
;
8681 if (mips_macro_warning
.delay_slot_p
)
8682 subtype
|= RELAX_DELAY_SLOT
;
8685 /* If both alternatives fail to fill a delay slot correctly,
8686 emit the warning now. */
8687 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8688 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8693 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8694 | RELAX_DELAY_SLOT_SIZE_FIRST
8695 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8696 msg
= macro_warning (s
);
8698 as_warn ("%s", msg
);
8702 /* If both implementations are longer than 1 instruction, then emit the
8704 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8709 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8710 msg
= macro_warning (s
);
8712 as_warn ("%s", msg
);
8716 /* If any flags still set, then one implementation might need a warning
8717 and the other either will need one of a different kind or none at all.
8718 Pass any remaining flags over to relaxation. */
8719 if (mips_macro_warning
.first_frag
!= NULL
)
8720 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8723 /* Instruction operand formats used in macros that vary between
8724 standard MIPS and microMIPS code. */
8726 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8727 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8728 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8729 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8730 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8731 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8732 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8733 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8735 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8736 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8737 : cop12_fmt[mips_opts.micromips])
8738 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8739 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8740 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8741 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8742 : mem12_fmt[mips_opts.micromips])
8743 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8744 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8745 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8747 /* Read a macro's relocation codes from *ARGS and store them in *R.
8748 The first argument in *ARGS will be either the code for a single
8749 relocation or -1 followed by the three codes that make up a
8750 composite relocation. */
8753 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8757 next
= va_arg (*args
, int);
8759 r
[0] = (bfd_reloc_code_real_type
) next
;
8762 for (i
= 0; i
< 3; i
++)
8763 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8764 /* This function is only used for 16-bit relocation fields.
8765 To make the macro code simpler, treat an unrelocated value
8766 in the same way as BFD_RELOC_LO16. */
8767 if (r
[0] == BFD_RELOC_UNUSED
)
8768 r
[0] = BFD_RELOC_LO16
;
8772 /* Build an instruction created by a macro expansion. This is passed
8773 a pointer to the count of instructions created so far, an
8774 expression, the name of the instruction to build, an operand format
8775 string, and corresponding arguments. */
8778 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8780 const struct mips_opcode
*mo
= NULL
;
8781 bfd_reloc_code_real_type r
[3];
8782 const struct mips_opcode
*amo
;
8783 const struct mips_operand
*operand
;
8784 struct hash_control
*hash
;
8785 struct mips_cl_insn insn
;
8789 va_start (args
, fmt
);
8791 if (mips_opts
.mips16
)
8793 mips16_macro_build (ep
, name
, fmt
, &args
);
8798 r
[0] = BFD_RELOC_UNUSED
;
8799 r
[1] = BFD_RELOC_UNUSED
;
8800 r
[2] = BFD_RELOC_UNUSED
;
8801 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8802 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8804 gas_assert (strcmp (name
, amo
->name
) == 0);
8808 /* Search until we get a match for NAME. It is assumed here that
8809 macros will never generate MDMX, MIPS-3D, or MT instructions.
8810 We try to match an instruction that fulfills the branch delay
8811 slot instruction length requirement (if any) of the previous
8812 instruction. While doing this we record the first instruction
8813 seen that matches all the other conditions and use it anyway
8814 if the requirement cannot be met; we will issue an appropriate
8815 warning later on. */
8816 if (strcmp (fmt
, amo
->args
) == 0
8817 && amo
->pinfo
!= INSN_MACRO
8818 && is_opcode_valid (amo
)
8819 && is_size_valid (amo
))
8821 if (is_delay_slot_valid (amo
))
8831 gas_assert (amo
->name
);
8833 while (strcmp (name
, amo
->name
) == 0);
8836 create_insn (&insn
, mo
);
8849 macro_read_relocs (&args
, r
);
8850 gas_assert (*r
== BFD_RELOC_GPREL16
8851 || *r
== BFD_RELOC_MIPS_HIGHER
8852 || *r
== BFD_RELOC_HI16_S
8853 || *r
== BFD_RELOC_LO16
8854 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
8858 macro_read_relocs (&args
, r
);
8862 macro_read_relocs (&args
, r
);
8863 gas_assert (ep
!= NULL
8864 && (ep
->X_op
== O_constant
8865 || (ep
->X_op
== O_symbol
8866 && (*r
== BFD_RELOC_MIPS_HIGHEST
8867 || *r
== BFD_RELOC_HI16_S
8868 || *r
== BFD_RELOC_HI16
8869 || *r
== BFD_RELOC_GPREL16
8870 || *r
== BFD_RELOC_MIPS_GOT_HI16
8871 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8875 gas_assert (ep
!= NULL
);
8878 * This allows macro() to pass an immediate expression for
8879 * creating short branches without creating a symbol.
8881 * We don't allow branch relaxation for these branches, as
8882 * they should only appear in ".set nomacro" anyway.
8884 if (ep
->X_op
== O_constant
)
8886 /* For microMIPS we always use relocations for branches.
8887 So we should not resolve immediate values. */
8888 gas_assert (!mips_opts
.micromips
);
8890 if ((ep
->X_add_number
& 3) != 0)
8891 as_bad (_("branch to misaligned address (0x%lx)"),
8892 (unsigned long) ep
->X_add_number
);
8893 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8894 as_bad (_("branch address range overflow (0x%lx)"),
8895 (unsigned long) ep
->X_add_number
);
8896 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8900 *r
= BFD_RELOC_16_PCREL_S2
;
8904 gas_assert (ep
!= NULL
);
8905 *r
= BFD_RELOC_MIPS_JMP
;
8909 operand
= (mips_opts
.micromips
8910 ? decode_micromips_operand (fmt
)
8911 : decode_mips_operand (fmt
));
8915 uval
= va_arg (args
, int);
8916 if (operand
->type
== OP_CLO_CLZ_DEST
)
8917 uval
|= (uval
<< 5);
8918 insn_insert_operand (&insn
, operand
, uval
);
8920 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8926 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8928 append_insn (&insn
, ep
, r
, TRUE
);
8932 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8935 struct mips_opcode
*mo
;
8936 struct mips_cl_insn insn
;
8937 const struct mips_operand
*operand
;
8938 bfd_reloc_code_real_type r
[3]
8939 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8941 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8943 gas_assert (strcmp (name
, mo
->name
) == 0);
8945 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8948 gas_assert (mo
->name
);
8949 gas_assert (strcmp (name
, mo
->name
) == 0);
8952 create_insn (&insn
, mo
);
8989 gas_assert (ep
!= NULL
);
8991 if (ep
->X_op
!= O_constant
)
8992 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8993 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8995 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8997 *r
= BFD_RELOC_UNUSED
;
9003 operand
= decode_mips16_operand (c
, FALSE
);
9007 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9012 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9014 append_insn (&insn
, ep
, r
, TRUE
);
9018 * Generate a "jalr" instruction with a relocation hint to the called
9019 * function. This occurs in NewABI PIC code.
9022 macro_build_jalr (expressionS
*ep
, int cprestore
)
9024 static const bfd_reloc_code_real_type jalr_relocs
[2]
9025 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9026 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9030 if (MIPS_JALR_HINT_P (ep
))
9035 if (mips_opts
.micromips
)
9037 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9038 ? "jalr" : "jalrs");
9039 if (MIPS_JALR_HINT_P (ep
)
9041 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9042 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9044 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9047 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9048 if (MIPS_JALR_HINT_P (ep
))
9049 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
9053 * Generate a "lui" instruction.
9056 macro_build_lui (expressionS
*ep
, int regnum
)
9058 gas_assert (! mips_opts
.mips16
);
9060 if (ep
->X_op
!= O_constant
)
9062 gas_assert (ep
->X_op
== O_symbol
);
9063 /* _gp_disp is a special case, used from s_cpload.
9064 __gnu_local_gp is used if mips_no_shared. */
9065 gas_assert (mips_pic
== NO_PIC
9067 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9068 || (! mips_in_shared
9069 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9070 "__gnu_local_gp") == 0));
9073 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9076 /* Generate a sequence of instructions to do a load or store from a constant
9077 offset off of a base register (breg) into/from a target register (treg),
9078 using AT if necessary. */
9080 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9081 int treg
, int breg
, int dbl
)
9083 gas_assert (ep
->X_op
== O_constant
);
9085 /* Sign-extending 32-bit constants makes their handling easier. */
9087 normalize_constant_expr (ep
);
9089 /* Right now, this routine can only handle signed 32-bit constants. */
9090 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9091 as_warn (_("operand overflow"));
9093 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9095 /* Signed 16-bit offset will fit in the op. Easy! */
9096 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9100 /* 32-bit offset, need multiple instructions and AT, like:
9101 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9102 addu $tempreg,$tempreg,$breg
9103 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9104 to handle the complete offset. */
9105 macro_build_lui (ep
, AT
);
9106 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9107 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9110 as_bad (_("macro used $at after \".set noat\""));
9115 * Generates code to set the $at register to true (one)
9116 * if reg is less than the immediate expression.
9119 set_at (int reg
, int unsignedp
)
9121 if (imm_expr
.X_add_number
>= -0x8000
9122 && imm_expr
.X_add_number
< 0x8000)
9123 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9124 AT
, reg
, BFD_RELOC_LO16
);
9127 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9128 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9132 /* Count the leading zeroes by performing a binary chop. This is a
9133 bulky bit of source, but performance is a LOT better for the
9134 majority of values than a simple loop to count the bits:
9135 for (lcnt = 0; (lcnt < 32); lcnt++)
9136 if ((v) & (1 << (31 - lcnt)))
9138 However it is not code size friendly, and the gain will drop a bit
9139 on certain cached systems.
9141 #define COUNT_TOP_ZEROES(v) \
9142 (((v) & ~0xffff) == 0 \
9143 ? ((v) & ~0xff) == 0 \
9144 ? ((v) & ~0xf) == 0 \
9145 ? ((v) & ~0x3) == 0 \
9146 ? ((v) & ~0x1) == 0 \
9151 : ((v) & ~0x7) == 0 \
9154 : ((v) & ~0x3f) == 0 \
9155 ? ((v) & ~0x1f) == 0 \
9158 : ((v) & ~0x7f) == 0 \
9161 : ((v) & ~0xfff) == 0 \
9162 ? ((v) & ~0x3ff) == 0 \
9163 ? ((v) & ~0x1ff) == 0 \
9166 : ((v) & ~0x7ff) == 0 \
9169 : ((v) & ~0x3fff) == 0 \
9170 ? ((v) & ~0x1fff) == 0 \
9173 : ((v) & ~0x7fff) == 0 \
9176 : ((v) & ~0xffffff) == 0 \
9177 ? ((v) & ~0xfffff) == 0 \
9178 ? ((v) & ~0x3ffff) == 0 \
9179 ? ((v) & ~0x1ffff) == 0 \
9182 : ((v) & ~0x7ffff) == 0 \
9185 : ((v) & ~0x3fffff) == 0 \
9186 ? ((v) & ~0x1fffff) == 0 \
9189 : ((v) & ~0x7fffff) == 0 \
9192 : ((v) & ~0xfffffff) == 0 \
9193 ? ((v) & ~0x3ffffff) == 0 \
9194 ? ((v) & ~0x1ffffff) == 0 \
9197 : ((v) & ~0x7ffffff) == 0 \
9200 : ((v) & ~0x3fffffff) == 0 \
9201 ? ((v) & ~0x1fffffff) == 0 \
9204 : ((v) & ~0x7fffffff) == 0 \
9209 * This routine generates the least number of instructions necessary to load
9210 * an absolute expression value into a register.
9213 load_register (int reg
, expressionS
*ep
, int dbl
)
9216 expressionS hi32
, lo32
;
9218 if (ep
->X_op
!= O_big
)
9220 gas_assert (ep
->X_op
== O_constant
);
9222 /* Sign-extending 32-bit constants makes their handling easier. */
9224 normalize_constant_expr (ep
);
9226 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9228 /* We can handle 16 bit signed values with an addiu to
9229 $zero. No need to ever use daddiu here, since $zero and
9230 the result are always correct in 32 bit mode. */
9231 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9234 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9236 /* We can handle 16 bit unsigned values with an ori to
9238 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9241 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9243 /* 32 bit values require an lui. */
9244 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9245 if ((ep
->X_add_number
& 0xffff) != 0)
9246 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9251 /* The value is larger than 32 bits. */
9253 if (!dbl
|| GPR_SIZE
== 32)
9257 sprintf_vma (value
, ep
->X_add_number
);
9258 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9259 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9263 if (ep
->X_op
!= O_big
)
9266 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9267 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9268 hi32
.X_add_number
&= 0xffffffff;
9270 lo32
.X_add_number
&= 0xffffffff;
9274 gas_assert (ep
->X_add_number
> 2);
9275 if (ep
->X_add_number
== 3)
9276 generic_bignum
[3] = 0;
9277 else if (ep
->X_add_number
> 4)
9278 as_bad (_("number larger than 64 bits"));
9279 lo32
.X_op
= O_constant
;
9280 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9281 hi32
.X_op
= O_constant
;
9282 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9285 if (hi32
.X_add_number
== 0)
9290 unsigned long hi
, lo
;
9292 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9294 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9296 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9299 if (lo32
.X_add_number
& 0x80000000)
9301 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9302 if (lo32
.X_add_number
& 0xffff)
9303 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9308 /* Check for 16bit shifted constant. We know that hi32 is
9309 non-zero, so start the mask on the first bit of the hi32
9314 unsigned long himask
, lomask
;
9318 himask
= 0xffff >> (32 - shift
);
9319 lomask
= (0xffff << shift
) & 0xffffffff;
9323 himask
= 0xffff << (shift
- 32);
9326 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9327 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9331 tmp
.X_op
= O_constant
;
9333 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9334 | (lo32
.X_add_number
>> shift
));
9336 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9337 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9338 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9339 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9344 while (shift
<= (64 - 16));
9346 /* Find the bit number of the lowest one bit, and store the
9347 shifted value in hi/lo. */
9348 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9349 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9353 while ((lo
& 1) == 0)
9358 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9364 while ((hi
& 1) == 0)
9373 /* Optimize if the shifted value is a (power of 2) - 1. */
9374 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9375 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9377 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9382 /* This instruction will set the register to be all
9384 tmp
.X_op
= O_constant
;
9385 tmp
.X_add_number
= (offsetT
) -1;
9386 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9390 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9391 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9393 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9394 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9399 /* Sign extend hi32 before calling load_register, because we can
9400 generally get better code when we load a sign extended value. */
9401 if ((hi32
.X_add_number
& 0x80000000) != 0)
9402 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9403 load_register (reg
, &hi32
, 0);
9406 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9410 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9418 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9420 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9421 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9427 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9431 mid16
.X_add_number
>>= 16;
9432 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9433 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9436 if ((lo32
.X_add_number
& 0xffff) != 0)
9437 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9441 load_delay_nop (void)
9443 if (!gpr_interlocks
)
9444 macro_build (NULL
, "nop", "");
9447 /* Load an address into a register. */
9450 load_address (int reg
, expressionS
*ep
, int *used_at
)
9452 if (ep
->X_op
!= O_constant
9453 && ep
->X_op
!= O_symbol
)
9455 as_bad (_("expression too complex"));
9456 ep
->X_op
= O_constant
;
9459 if (ep
->X_op
== O_constant
)
9461 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9465 if (mips_pic
== NO_PIC
)
9467 /* If this is a reference to a GP relative symbol, we want
9468 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9470 lui $reg,<sym> (BFD_RELOC_HI16_S)
9471 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9472 If we have an addend, we always use the latter form.
9474 With 64bit address space and a usable $at we want
9475 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9476 lui $at,<sym> (BFD_RELOC_HI16_S)
9477 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9478 daddiu $at,<sym> (BFD_RELOC_LO16)
9482 If $at is already in use, we use a path which is suboptimal
9483 on superscalar processors.
9484 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9485 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9487 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9489 daddiu $reg,<sym> (BFD_RELOC_LO16)
9491 For GP relative symbols in 64bit address space we can use
9492 the same sequence as in 32bit address space. */
9493 if (HAVE_64BIT_SYMBOLS
)
9495 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9496 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9498 relax_start (ep
->X_add_symbol
);
9499 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9500 mips_gp_register
, BFD_RELOC_GPREL16
);
9504 if (*used_at
== 0 && mips_opts
.at
)
9506 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9507 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9508 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9509 BFD_RELOC_MIPS_HIGHER
);
9510 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9511 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9512 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9517 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9518 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9519 BFD_RELOC_MIPS_HIGHER
);
9520 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9521 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9522 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9523 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9526 if (mips_relax
.sequence
)
9531 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9532 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9534 relax_start (ep
->X_add_symbol
);
9535 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9536 mips_gp_register
, BFD_RELOC_GPREL16
);
9539 macro_build_lui (ep
, reg
);
9540 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9541 reg
, reg
, BFD_RELOC_LO16
);
9542 if (mips_relax
.sequence
)
9546 else if (!mips_big_got
)
9550 /* If this is a reference to an external symbol, we want
9551 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9553 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9555 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9556 If there is a constant, it must be added in after.
9558 If we have NewABI, we want
9559 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9560 unless we're referencing a global symbol with a non-zero
9561 offset, in which case cst must be added separately. */
9564 if (ep
->X_add_number
)
9566 ex
.X_add_number
= ep
->X_add_number
;
9567 ep
->X_add_number
= 0;
9568 relax_start (ep
->X_add_symbol
);
9569 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9570 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9571 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9572 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9573 ex
.X_op
= O_constant
;
9574 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9575 reg
, reg
, BFD_RELOC_LO16
);
9576 ep
->X_add_number
= ex
.X_add_number
;
9579 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9580 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9581 if (mips_relax
.sequence
)
9586 ex
.X_add_number
= ep
->X_add_number
;
9587 ep
->X_add_number
= 0;
9588 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9589 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9591 relax_start (ep
->X_add_symbol
);
9593 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9597 if (ex
.X_add_number
!= 0)
9599 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9600 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9601 ex
.X_op
= O_constant
;
9602 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9603 reg
, reg
, BFD_RELOC_LO16
);
9607 else if (mips_big_got
)
9611 /* This is the large GOT case. If this is a reference to an
9612 external symbol, we want
9613 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9615 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9617 Otherwise, for a reference to a local symbol in old ABI, we want
9618 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9620 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9621 If there is a constant, it must be added in after.
9623 In the NewABI, for local symbols, with or without offsets, we want:
9624 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9625 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9629 ex
.X_add_number
= ep
->X_add_number
;
9630 ep
->X_add_number
= 0;
9631 relax_start (ep
->X_add_symbol
);
9632 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9633 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9634 reg
, reg
, mips_gp_register
);
9635 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9636 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9637 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9638 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9639 else if (ex
.X_add_number
)
9641 ex
.X_op
= O_constant
;
9642 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9646 ep
->X_add_number
= ex
.X_add_number
;
9648 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9649 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9650 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9651 BFD_RELOC_MIPS_GOT_OFST
);
9656 ex
.X_add_number
= ep
->X_add_number
;
9657 ep
->X_add_number
= 0;
9658 relax_start (ep
->X_add_symbol
);
9659 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9660 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9661 reg
, reg
, mips_gp_register
);
9662 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9663 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9665 if (reg_needs_delay (mips_gp_register
))
9667 /* We need a nop before loading from $gp. This special
9668 check is required because the lui which starts the main
9669 instruction stream does not refer to $gp, and so will not
9670 insert the nop which may be required. */
9671 macro_build (NULL
, "nop", "");
9673 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9674 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9676 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9680 if (ex
.X_add_number
!= 0)
9682 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9683 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9684 ex
.X_op
= O_constant
;
9685 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9693 if (!mips_opts
.at
&& *used_at
== 1)
9694 as_bad (_("macro used $at after \".set noat\""));
9697 /* Move the contents of register SOURCE into register DEST. */
9700 move_register (int dest
, int source
)
9702 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9703 instruction specifically requires a 32-bit one. */
9704 if (mips_opts
.micromips
9705 && !mips_opts
.insn32
9706 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9707 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9709 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9712 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9713 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9714 The two alternatives are:
9716 Global symbol Local symbol
9717 ------------- ------------
9718 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9720 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9722 load_got_offset emits the first instruction and add_got_offset
9723 emits the second for a 16-bit offset or add_got_offset_hilo emits
9724 a sequence to add a 32-bit offset using a scratch register. */
9727 load_got_offset (int dest
, expressionS
*local
)
9732 global
.X_add_number
= 0;
9734 relax_start (local
->X_add_symbol
);
9735 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9736 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9738 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9739 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9744 add_got_offset (int dest
, expressionS
*local
)
9748 global
.X_op
= O_constant
;
9749 global
.X_op_symbol
= NULL
;
9750 global
.X_add_symbol
= NULL
;
9751 global
.X_add_number
= local
->X_add_number
;
9753 relax_start (local
->X_add_symbol
);
9754 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9755 dest
, dest
, BFD_RELOC_LO16
);
9757 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9762 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9765 int hold_mips_optimize
;
9767 global
.X_op
= O_constant
;
9768 global
.X_op_symbol
= NULL
;
9769 global
.X_add_symbol
= NULL
;
9770 global
.X_add_number
= local
->X_add_number
;
9772 relax_start (local
->X_add_symbol
);
9773 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9775 /* Set mips_optimize around the lui instruction to avoid
9776 inserting an unnecessary nop after the lw. */
9777 hold_mips_optimize
= mips_optimize
;
9779 macro_build_lui (&global
, tmp
);
9780 mips_optimize
= hold_mips_optimize
;
9781 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9784 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9787 /* Emit a sequence of instructions to emulate a branch likely operation.
9788 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9789 is its complementing branch with the original condition negated.
9790 CALL is set if the original branch specified the link operation.
9791 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9793 Code like this is produced in the noreorder mode:
9798 delay slot (executed only if branch taken)
9806 delay slot (executed only if branch taken)
9809 In the reorder mode the delay slot would be filled with a nop anyway,
9810 so code produced is simply:
9815 This function is used when producing code for the microMIPS ASE that
9816 does not implement branch likely instructions in hardware. */
9819 macro_build_branch_likely (const char *br
, const char *brneg
,
9820 int call
, expressionS
*ep
, const char *fmt
,
9821 unsigned int sreg
, unsigned int treg
)
9823 int noreorder
= mips_opts
.noreorder
;
9826 gas_assert (mips_opts
.micromips
);
9830 micromips_label_expr (&expr1
);
9831 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9832 macro_build (NULL
, "nop", "");
9833 macro_build (ep
, call
? "bal" : "b", "p");
9835 /* Set to true so that append_insn adds a label. */
9836 emit_branch_likely_macro
= TRUE
;
9840 macro_build (ep
, br
, fmt
, sreg
, treg
);
9841 macro_build (NULL
, "nop", "");
9846 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9847 the condition code tested. EP specifies the branch target. */
9850 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9877 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9880 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9881 the register tested. EP specifies the branch target. */
9884 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9886 const char *brneg
= NULL
;
9896 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9900 gas_assert (mips_opts
.micromips
);
9901 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9909 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9916 br
= mips_opts
.micromips
? "blez" : "blezl";
9923 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9927 gas_assert (mips_opts
.micromips
);
9928 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9935 if (mips_opts
.micromips
&& brneg
)
9936 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9938 macro_build (ep
, br
, "s,p", sreg
);
9941 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9942 TREG as the registers tested. EP specifies the branch target. */
9945 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9946 unsigned int sreg
, unsigned int treg
)
9948 const char *brneg
= NULL
;
9960 br
= mips_opts
.micromips
? "beq" : "beql";
9969 br
= mips_opts
.micromips
? "bne" : "bnel";
9975 if (mips_opts
.micromips
&& brneg
)
9976 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9978 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9981 /* Return the high part that should be loaded in order to make the low
9982 part of VALUE accessible using an offset of OFFBITS bits. */
9985 offset_high_part (offsetT value
, unsigned int offbits
)
9992 bias
= 1 << (offbits
- 1);
9993 low_mask
= bias
* 2 - 1;
9994 return (value
+ bias
) & ~low_mask
;
9997 /* Return true if the value stored in offset_expr and offset_reloc
9998 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9999 amount that the caller wants to add without inducing overflow
10000 and ALIGN is the known alignment of the value in bytes. */
10003 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10007 /* Accept any relocation operator if overflow isn't a concern. */
10008 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10011 /* These relocations are guaranteed not to overflow in correct links. */
10012 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10013 || gprel16_reloc_p (*offset_reloc
))
10016 if (offset_expr
.X_op
== O_constant
10017 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10018 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10025 * This routine implements the seemingly endless macro or synthesized
10026 * instructions and addressing modes in the mips assembly language. Many
10027 * of these macros are simple and are similar to each other. These could
10028 * probably be handled by some kind of table or grammar approach instead of
10029 * this verbose method. Others are not simple macros but are more like
10030 * optimizing code generation.
10031 * One interesting optimization is when several store macros appear
10032 * consecutively that would load AT with the upper half of the same address.
10033 * The ensuing load upper instructions are omitted. This implies some kind
10034 * of global optimization. We currently only optimize within a single macro.
10035 * For many of the load and store macros if the address is specified as a
10036 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10037 * first load register 'at' with zero and use it as the base register. The
10038 * mips assembler simply uses register $zero. Just one tiny optimization
10042 macro (struct mips_cl_insn
*ip
, char *str
)
10044 const struct mips_operand_array
*operands
;
10045 unsigned int breg
, i
;
10046 unsigned int tempreg
;
10049 expressionS label_expr
;
10064 bfd_boolean large_offset
;
10066 int hold_mips_optimize
;
10067 unsigned int align
;
10068 unsigned int op
[MAX_OPERANDS
];
10070 gas_assert (! mips_opts
.mips16
);
10072 operands
= insn_operands (ip
);
10073 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10074 if (operands
->operand
[i
])
10075 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10079 mask
= ip
->insn_mo
->mask
;
10081 label_expr
.X_op
= O_constant
;
10082 label_expr
.X_op_symbol
= NULL
;
10083 label_expr
.X_add_symbol
= NULL
;
10084 label_expr
.X_add_number
= 0;
10086 expr1
.X_op
= O_constant
;
10087 expr1
.X_op_symbol
= NULL
;
10088 expr1
.X_add_symbol
= NULL
;
10089 expr1
.X_add_number
= 1;
10096 /* Fall through. */
10104 start_noreorder ();
10106 if (mips_opts
.micromips
)
10107 micromips_label_expr (&label_expr
);
10109 label_expr
.X_add_number
= 8;
10110 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10111 if (op
[0] == op
[1])
10112 macro_build (NULL
, "nop", "");
10114 move_register (op
[0], op
[1]);
10115 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10116 if (mips_opts
.micromips
)
10117 micromips_add_label ();
10134 if (!mips_opts
.micromips
)
10136 if (imm_expr
.X_add_number
>= -0x200
10137 && imm_expr
.X_add_number
< 0x200)
10139 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10140 (int) imm_expr
.X_add_number
);
10149 if (imm_expr
.X_add_number
>= -0x8000
10150 && imm_expr
.X_add_number
< 0x8000)
10152 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10157 load_register (AT
, &imm_expr
, dbl
);
10158 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10177 if (imm_expr
.X_add_number
>= 0
10178 && imm_expr
.X_add_number
< 0x10000)
10180 if (mask
!= M_NOR_I
)
10181 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10184 macro_build (&imm_expr
, "ori", "t,r,i",
10185 op
[0], op
[1], BFD_RELOC_LO16
);
10186 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10192 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10193 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10197 switch (imm_expr
.X_add_number
)
10200 macro_build (NULL
, "nop", "");
10203 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10207 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10208 (int) imm_expr
.X_add_number
);
10211 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10212 (unsigned long) imm_expr
.X_add_number
);
10221 gas_assert (mips_opts
.micromips
);
10222 macro_build_branch_ccl (mask
, &offset_expr
,
10223 EXTRACT_OPERAND (1, BCC
, *ip
));
10230 if (imm_expr
.X_add_number
== 0)
10236 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10238 /* Fall through. */
10241 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10246 /* Fall through. */
10249 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10250 else if (op
[0] == 0)
10251 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10255 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10256 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10257 &offset_expr
, AT
, ZERO
);
10267 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10272 /* Fall through. */
10274 /* Check for > max integer. */
10275 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10278 /* Result is always false. */
10280 macro_build (NULL
, "nop", "");
10282 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10285 ++imm_expr
.X_add_number
;
10289 if (mask
== M_BGEL_I
)
10291 if (imm_expr
.X_add_number
== 0)
10293 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10294 &offset_expr
, op
[0]);
10297 if (imm_expr
.X_add_number
== 1)
10299 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10300 &offset_expr
, op
[0]);
10303 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10306 /* result is always true */
10307 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10308 macro_build (&offset_expr
, "b", "p");
10313 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10314 &offset_expr
, AT
, ZERO
);
10319 /* Fall through. */
10323 else if (op
[0] == 0)
10324 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10325 &offset_expr
, ZERO
, op
[1]);
10329 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10330 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10331 &offset_expr
, AT
, ZERO
);
10337 /* Fall through. */
10341 && imm_expr
.X_add_number
== -1))
10343 ++imm_expr
.X_add_number
;
10347 if (mask
== M_BGEUL_I
)
10349 if (imm_expr
.X_add_number
== 0)
10351 else if (imm_expr
.X_add_number
== 1)
10352 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10353 &offset_expr
, op
[0], ZERO
);
10358 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10359 &offset_expr
, AT
, ZERO
);
10365 /* Fall through. */
10368 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10369 else if (op
[0] == 0)
10370 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10374 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10375 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10376 &offset_expr
, AT
, ZERO
);
10382 /* Fall through. */
10385 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10386 &offset_expr
, op
[0], ZERO
);
10387 else if (op
[0] == 0)
10392 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10393 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10394 &offset_expr
, AT
, ZERO
);
10400 /* Fall through. */
10403 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10404 else if (op
[0] == 0)
10405 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10409 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10410 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10411 &offset_expr
, AT
, ZERO
);
10417 /* Fall through. */
10419 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10421 ++imm_expr
.X_add_number
;
10425 if (mask
== M_BLTL_I
)
10427 if (imm_expr
.X_add_number
== 0)
10428 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10429 else if (imm_expr
.X_add_number
== 1)
10430 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10435 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10436 &offset_expr
, AT
, ZERO
);
10442 /* Fall through. */
10445 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10446 &offset_expr
, op
[0], ZERO
);
10447 else if (op
[0] == 0)
10452 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10453 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10454 &offset_expr
, AT
, ZERO
);
10460 /* Fall through. */
10464 && imm_expr
.X_add_number
== -1))
10466 ++imm_expr
.X_add_number
;
10470 if (mask
== M_BLTUL_I
)
10472 if (imm_expr
.X_add_number
== 0)
10474 else if (imm_expr
.X_add_number
== 1)
10475 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10476 &offset_expr
, op
[0], ZERO
);
10481 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10482 &offset_expr
, AT
, ZERO
);
10488 /* Fall through. */
10491 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10492 else if (op
[0] == 0)
10493 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10497 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10498 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10499 &offset_expr
, AT
, ZERO
);
10505 /* Fall through. */
10509 else if (op
[0] == 0)
10510 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10511 &offset_expr
, ZERO
, op
[1]);
10515 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10516 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10517 &offset_expr
, AT
, ZERO
);
10523 /* Fall through. */
10529 /* Fall through. */
10535 as_warn (_("divide by zero"));
10537 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10539 macro_build (NULL
, "break", BRK_FMT
, 7);
10543 start_noreorder ();
10546 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10547 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10551 if (mips_opts
.micromips
)
10552 micromips_label_expr (&label_expr
);
10554 label_expr
.X_add_number
= 8;
10555 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10556 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10557 macro_build (NULL
, "break", BRK_FMT
, 7);
10558 if (mips_opts
.micromips
)
10559 micromips_add_label ();
10561 expr1
.X_add_number
= -1;
10563 load_register (AT
, &expr1
, dbl
);
10564 if (mips_opts
.micromips
)
10565 micromips_label_expr (&label_expr
);
10567 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10568 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10571 expr1
.X_add_number
= 1;
10572 load_register (AT
, &expr1
, dbl
);
10573 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10577 expr1
.X_add_number
= 0x80000000;
10578 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10582 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10583 /* We want to close the noreorder block as soon as possible, so
10584 that later insns are available for delay slot filling. */
10589 if (mips_opts
.micromips
)
10590 micromips_label_expr (&label_expr
);
10592 label_expr
.X_add_number
= 8;
10593 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10594 macro_build (NULL
, "nop", "");
10596 /* We want to close the noreorder block as soon as possible, so
10597 that later insns are available for delay slot filling. */
10600 macro_build (NULL
, "break", BRK_FMT
, 6);
10602 if (mips_opts
.micromips
)
10603 micromips_add_label ();
10604 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10643 if (imm_expr
.X_add_number
== 0)
10645 as_warn (_("divide by zero"));
10647 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10649 macro_build (NULL
, "break", BRK_FMT
, 7);
10652 if (imm_expr
.X_add_number
== 1)
10654 if (strcmp (s2
, "mflo") == 0)
10655 move_register (op
[0], op
[1]);
10657 move_register (op
[0], ZERO
);
10660 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10662 if (strcmp (s2
, "mflo") == 0)
10663 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10665 move_register (op
[0], ZERO
);
10670 load_register (AT
, &imm_expr
, dbl
);
10671 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10672 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10691 start_noreorder ();
10694 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10695 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10696 /* We want to close the noreorder block as soon as possible, so
10697 that later insns are available for delay slot filling. */
10702 if (mips_opts
.micromips
)
10703 micromips_label_expr (&label_expr
);
10705 label_expr
.X_add_number
= 8;
10706 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10707 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10709 /* We want to close the noreorder block as soon as possible, so
10710 that later insns are available for delay slot filling. */
10712 macro_build (NULL
, "break", BRK_FMT
, 7);
10713 if (mips_opts
.micromips
)
10714 micromips_add_label ();
10716 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10721 /* Fall through. */
10727 /* Fall through. */
10730 /* Load the address of a symbol into a register. If breg is not
10731 zero, we then add a base register to it. */
10734 if (dbl
&& GPR_SIZE
== 32)
10735 as_warn (_("dla used to load 32-bit register; recommend using la "
10738 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10739 as_warn (_("la used to load 64-bit address; recommend using dla "
10742 if (small_offset_p (0, align
, 16))
10744 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10745 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10749 if (mips_opts
.at
&& (op
[0] == breg
))
10757 if (offset_expr
.X_op
!= O_symbol
10758 && offset_expr
.X_op
!= O_constant
)
10760 as_bad (_("expression too complex"));
10761 offset_expr
.X_op
= O_constant
;
10764 if (offset_expr
.X_op
== O_constant
)
10765 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10766 else if (mips_pic
== NO_PIC
)
10768 /* If this is a reference to a GP relative symbol, we want
10769 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10771 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10772 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10773 If we have a constant, we need two instructions anyhow,
10774 so we may as well always use the latter form.
10776 With 64bit address space and a usable $at we want
10777 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10778 lui $at,<sym> (BFD_RELOC_HI16_S)
10779 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10780 daddiu $at,<sym> (BFD_RELOC_LO16)
10782 daddu $tempreg,$tempreg,$at
10784 If $at is already in use, we use a path which is suboptimal
10785 on superscalar processors.
10786 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10787 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10789 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10791 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10793 For GP relative symbols in 64bit address space we can use
10794 the same sequence as in 32bit address space. */
10795 if (HAVE_64BIT_SYMBOLS
)
10797 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10798 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10800 relax_start (offset_expr
.X_add_symbol
);
10801 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10802 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10806 if (used_at
== 0 && mips_opts
.at
)
10808 macro_build (&offset_expr
, "lui", LUI_FMT
,
10809 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10810 macro_build (&offset_expr
, "lui", LUI_FMT
,
10811 AT
, BFD_RELOC_HI16_S
);
10812 macro_build (&offset_expr
, "daddiu", "t,r,j",
10813 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10814 macro_build (&offset_expr
, "daddiu", "t,r,j",
10815 AT
, AT
, BFD_RELOC_LO16
);
10816 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10817 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10822 macro_build (&offset_expr
, "lui", LUI_FMT
,
10823 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10824 macro_build (&offset_expr
, "daddiu", "t,r,j",
10825 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10826 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10827 macro_build (&offset_expr
, "daddiu", "t,r,j",
10828 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10829 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10830 macro_build (&offset_expr
, "daddiu", "t,r,j",
10831 tempreg
, tempreg
, BFD_RELOC_LO16
);
10834 if (mips_relax
.sequence
)
10839 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10840 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10842 relax_start (offset_expr
.X_add_symbol
);
10843 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10844 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10847 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10848 as_bad (_("offset too large"));
10849 macro_build_lui (&offset_expr
, tempreg
);
10850 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10851 tempreg
, tempreg
, BFD_RELOC_LO16
);
10852 if (mips_relax
.sequence
)
10856 else if (!mips_big_got
&& !HAVE_NEWABI
)
10858 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10860 /* If this is a reference to an external symbol, and there
10861 is no constant, we want
10862 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10863 or for lca or if tempreg is PIC_CALL_REG
10864 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10865 For a local symbol, we want
10866 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10868 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10870 If we have a small constant, and this is a reference to
10871 an external symbol, we want
10872 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10874 addiu $tempreg,$tempreg,<constant>
10875 For a local symbol, we want the same instruction
10876 sequence, but we output a BFD_RELOC_LO16 reloc on the
10879 If we have a large constant, and this is a reference to
10880 an external symbol, we want
10881 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10882 lui $at,<hiconstant>
10883 addiu $at,$at,<loconstant>
10884 addu $tempreg,$tempreg,$at
10885 For a local symbol, we want the same instruction
10886 sequence, but we output a BFD_RELOC_LO16 reloc on the
10890 if (offset_expr
.X_add_number
== 0)
10892 if (mips_pic
== SVR4_PIC
10894 && (call
|| tempreg
== PIC_CALL_REG
))
10895 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10897 relax_start (offset_expr
.X_add_symbol
);
10898 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10899 lw_reloc_type
, mips_gp_register
);
10902 /* We're going to put in an addu instruction using
10903 tempreg, so we may as well insert the nop right
10908 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10909 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10911 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10912 tempreg
, tempreg
, BFD_RELOC_LO16
);
10914 /* FIXME: If breg == 0, and the next instruction uses
10915 $tempreg, then if this variant case is used an extra
10916 nop will be generated. */
10918 else if (offset_expr
.X_add_number
>= -0x8000
10919 && offset_expr
.X_add_number
< 0x8000)
10921 load_got_offset (tempreg
, &offset_expr
);
10923 add_got_offset (tempreg
, &offset_expr
);
10927 expr1
.X_add_number
= offset_expr
.X_add_number
;
10928 offset_expr
.X_add_number
=
10929 SEXT_16BIT (offset_expr
.X_add_number
);
10930 load_got_offset (tempreg
, &offset_expr
);
10931 offset_expr
.X_add_number
= expr1
.X_add_number
;
10932 /* If we are going to add in a base register, and the
10933 target register and the base register are the same,
10934 then we are using AT as a temporary register. Since
10935 we want to load the constant into AT, we add our
10936 current AT (from the global offset table) and the
10937 register into the register now, and pretend we were
10938 not using a base register. */
10942 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10947 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10951 else if (!mips_big_got
&& HAVE_NEWABI
)
10953 int add_breg_early
= 0;
10955 /* If this is a reference to an external, and there is no
10956 constant, or local symbol (*), with or without a
10958 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10959 or for lca or if tempreg is PIC_CALL_REG
10960 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10962 If we have a small constant, and this is a reference to
10963 an external symbol, we want
10964 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10965 addiu $tempreg,$tempreg,<constant>
10967 If we have a large constant, and this is a reference to
10968 an external symbol, we want
10969 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10970 lui $at,<hiconstant>
10971 addiu $at,$at,<loconstant>
10972 addu $tempreg,$tempreg,$at
10974 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10975 local symbols, even though it introduces an additional
10978 if (offset_expr
.X_add_number
)
10980 expr1
.X_add_number
= offset_expr
.X_add_number
;
10981 offset_expr
.X_add_number
= 0;
10983 relax_start (offset_expr
.X_add_symbol
);
10984 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10985 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10987 if (expr1
.X_add_number
>= -0x8000
10988 && expr1
.X_add_number
< 0x8000)
10990 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10991 tempreg
, tempreg
, BFD_RELOC_LO16
);
10993 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10997 /* If we are going to add in a base register, and the
10998 target register and the base register are the same,
10999 then we are using AT as a temporary register. Since
11000 we want to load the constant into AT, we add our
11001 current AT (from the global offset table) and the
11002 register into the register now, and pretend we were
11003 not using a base register. */
11008 gas_assert (tempreg
== AT
);
11009 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11012 add_breg_early
= 1;
11015 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11016 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11022 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11025 offset_expr
.X_add_number
= expr1
.X_add_number
;
11027 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11028 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11029 if (add_breg_early
)
11031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11032 op
[0], tempreg
, breg
);
11038 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11040 relax_start (offset_expr
.X_add_symbol
);
11041 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11042 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11044 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11045 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11050 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11051 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11054 else if (mips_big_got
&& !HAVE_NEWABI
)
11057 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11058 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11059 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11061 /* This is the large GOT case. If this is a reference to an
11062 external symbol, and there is no constant, we want
11063 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11064 addu $tempreg,$tempreg,$gp
11065 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11066 or for lca or if tempreg is PIC_CALL_REG
11067 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11068 addu $tempreg,$tempreg,$gp
11069 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11070 For a local symbol, we want
11071 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11073 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11075 If we have a small constant, and this is a reference to
11076 an external symbol, we want
11077 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11078 addu $tempreg,$tempreg,$gp
11079 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11081 addiu $tempreg,$tempreg,<constant>
11082 For a local symbol, we want
11083 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11085 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11087 If we have a large constant, and this is a reference to
11088 an external symbol, we want
11089 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11090 addu $tempreg,$tempreg,$gp
11091 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11092 lui $at,<hiconstant>
11093 addiu $at,$at,<loconstant>
11094 addu $tempreg,$tempreg,$at
11095 For a local symbol, we want
11096 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11097 lui $at,<hiconstant>
11098 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11099 addu $tempreg,$tempreg,$at
11102 expr1
.X_add_number
= offset_expr
.X_add_number
;
11103 offset_expr
.X_add_number
= 0;
11104 relax_start (offset_expr
.X_add_symbol
);
11105 gpdelay
= reg_needs_delay (mips_gp_register
);
11106 if (expr1
.X_add_number
== 0 && breg
== 0
11107 && (call
|| tempreg
== PIC_CALL_REG
))
11109 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11110 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11112 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11113 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11114 tempreg
, tempreg
, mips_gp_register
);
11115 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11116 tempreg
, lw_reloc_type
, tempreg
);
11117 if (expr1
.X_add_number
== 0)
11121 /* We're going to put in an addu instruction using
11122 tempreg, so we may as well insert the nop right
11127 else if (expr1
.X_add_number
>= -0x8000
11128 && expr1
.X_add_number
< 0x8000)
11131 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11132 tempreg
, tempreg
, BFD_RELOC_LO16
);
11138 /* If we are going to add in a base register, and the
11139 target register and the base register are the same,
11140 then we are using AT as a temporary register. Since
11141 we want to load the constant into AT, we add our
11142 current AT (from the global offset table) and the
11143 register into the register now, and pretend we were
11144 not using a base register. */
11149 gas_assert (tempreg
== AT
);
11151 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11156 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11157 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11161 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11166 /* This is needed because this instruction uses $gp, but
11167 the first instruction on the main stream does not. */
11168 macro_build (NULL
, "nop", "");
11171 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11172 local_reloc_type
, mips_gp_register
);
11173 if (expr1
.X_add_number
>= -0x8000
11174 && expr1
.X_add_number
< 0x8000)
11177 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11178 tempreg
, tempreg
, BFD_RELOC_LO16
);
11179 /* FIXME: If add_number is 0, and there was no base
11180 register, the external symbol case ended with a load,
11181 so if the symbol turns out to not be external, and
11182 the next instruction uses tempreg, an unnecessary nop
11183 will be inserted. */
11189 /* We must add in the base register now, as in the
11190 external symbol case. */
11191 gas_assert (tempreg
== AT
);
11193 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11196 /* We set breg to 0 because we have arranged to add
11197 it in in both cases. */
11201 macro_build_lui (&expr1
, AT
);
11202 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11203 AT
, AT
, BFD_RELOC_LO16
);
11204 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11205 tempreg
, tempreg
, AT
);
11210 else if (mips_big_got
&& HAVE_NEWABI
)
11212 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11213 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11214 int add_breg_early
= 0;
11216 /* This is the large GOT case. If this is a reference to an
11217 external symbol, and there is no constant, we want
11218 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11219 add $tempreg,$tempreg,$gp
11220 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11221 or for lca or if tempreg is PIC_CALL_REG
11222 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11223 add $tempreg,$tempreg,$gp
11224 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11226 If we have a small constant, and this is a reference to
11227 an external symbol, we want
11228 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11229 add $tempreg,$tempreg,$gp
11230 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11231 addi $tempreg,$tempreg,<constant>
11233 If we have a large constant, and this is a reference to
11234 an external symbol, we want
11235 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11236 addu $tempreg,$tempreg,$gp
11237 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11238 lui $at,<hiconstant>
11239 addi $at,$at,<loconstant>
11240 add $tempreg,$tempreg,$at
11242 If we have NewABI, and we know it's a local symbol, we want
11243 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11244 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11245 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11247 relax_start (offset_expr
.X_add_symbol
);
11249 expr1
.X_add_number
= offset_expr
.X_add_number
;
11250 offset_expr
.X_add_number
= 0;
11252 if (expr1
.X_add_number
== 0 && breg
== 0
11253 && (call
|| tempreg
== PIC_CALL_REG
))
11255 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11256 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11258 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11259 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11260 tempreg
, tempreg
, mips_gp_register
);
11261 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11262 tempreg
, lw_reloc_type
, tempreg
);
11264 if (expr1
.X_add_number
== 0)
11266 else if (expr1
.X_add_number
>= -0x8000
11267 && expr1
.X_add_number
< 0x8000)
11269 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11270 tempreg
, tempreg
, BFD_RELOC_LO16
);
11272 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11276 /* If we are going to add in a base register, and the
11277 target register and the base register are the same,
11278 then we are using AT as a temporary register. Since
11279 we want to load the constant into AT, we add our
11280 current AT (from the global offset table) and the
11281 register into the register now, and pretend we were
11282 not using a base register. */
11287 gas_assert (tempreg
== AT
);
11288 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11291 add_breg_early
= 1;
11294 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11295 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11300 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11303 offset_expr
.X_add_number
= expr1
.X_add_number
;
11304 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11305 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11306 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11307 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11308 if (add_breg_early
)
11310 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11311 op
[0], tempreg
, breg
);
11321 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11325 gas_assert (!mips_opts
.micromips
);
11326 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11330 gas_assert (!mips_opts
.micromips
);
11331 macro_build (NULL
, "c2", "C", 0x02);
11335 gas_assert (!mips_opts
.micromips
);
11336 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11340 gas_assert (!mips_opts
.micromips
);
11341 macro_build (NULL
, "c2", "C", 3);
11345 gas_assert (!mips_opts
.micromips
);
11346 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11350 /* The j instruction may not be used in PIC code, since it
11351 requires an absolute address. We convert it to a b
11353 if (mips_pic
== NO_PIC
)
11354 macro_build (&offset_expr
, "j", "a");
11356 macro_build (&offset_expr
, "b", "p");
11359 /* The jal instructions must be handled as macros because when
11360 generating PIC code they expand to multi-instruction
11361 sequences. Normally they are simple instructions. */
11365 /* Fall through. */
11367 gas_assert (mips_opts
.micromips
);
11368 if (mips_opts
.insn32
)
11370 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11378 /* Fall through. */
11381 if (mips_pic
== NO_PIC
)
11383 s
= jals
? "jalrs" : "jalr";
11384 if (mips_opts
.micromips
11385 && !mips_opts
.insn32
11387 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11388 macro_build (NULL
, s
, "mj", op
[1]);
11390 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11394 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11395 && mips_cprestore_offset
>= 0);
11397 if (op
[1] != PIC_CALL_REG
)
11398 as_warn (_("MIPS PIC call to register other than $25"));
11400 s
= ((mips_opts
.micromips
11401 && !mips_opts
.insn32
11402 && (!mips_opts
.noreorder
|| cprestore
))
11403 ? "jalrs" : "jalr");
11404 if (mips_opts
.micromips
11405 && !mips_opts
.insn32
11407 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11408 macro_build (NULL
, s
, "mj", op
[1]);
11410 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11411 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11413 if (mips_cprestore_offset
< 0)
11414 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11417 if (!mips_frame_reg_valid
)
11419 as_warn (_("no .frame pseudo-op used in PIC code"));
11420 /* Quiet this warning. */
11421 mips_frame_reg_valid
= 1;
11423 if (!mips_cprestore_valid
)
11425 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11426 /* Quiet this warning. */
11427 mips_cprestore_valid
= 1;
11429 if (mips_opts
.noreorder
)
11430 macro_build (NULL
, "nop", "");
11431 expr1
.X_add_number
= mips_cprestore_offset
;
11432 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11435 HAVE_64BIT_ADDRESSES
);
11443 gas_assert (mips_opts
.micromips
);
11444 if (mips_opts
.insn32
)
11446 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11450 /* Fall through. */
11452 if (mips_pic
== NO_PIC
)
11453 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11454 else if (mips_pic
== SVR4_PIC
)
11456 /* If this is a reference to an external symbol, and we are
11457 using a small GOT, we want
11458 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11462 lw $gp,cprestore($sp)
11463 The cprestore value is set using the .cprestore
11464 pseudo-op. If we are using a big GOT, we want
11465 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11467 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11471 lw $gp,cprestore($sp)
11472 If the symbol is not external, we want
11473 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11475 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11478 lw $gp,cprestore($sp)
11480 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11481 sequences above, minus nops, unless the symbol is local,
11482 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11488 relax_start (offset_expr
.X_add_symbol
);
11489 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11490 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11493 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11494 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11500 relax_start (offset_expr
.X_add_symbol
);
11501 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11502 BFD_RELOC_MIPS_CALL_HI16
);
11503 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11504 PIC_CALL_REG
, mips_gp_register
);
11505 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11506 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11509 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11510 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11512 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11513 PIC_CALL_REG
, PIC_CALL_REG
,
11514 BFD_RELOC_MIPS_GOT_OFST
);
11518 macro_build_jalr (&offset_expr
, 0);
11522 relax_start (offset_expr
.X_add_symbol
);
11525 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11526 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11535 gpdelay
= reg_needs_delay (mips_gp_register
);
11536 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11537 BFD_RELOC_MIPS_CALL_HI16
);
11538 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11539 PIC_CALL_REG
, mips_gp_register
);
11540 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11541 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11546 macro_build (NULL
, "nop", "");
11548 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11549 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11552 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11553 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11555 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11557 if (mips_cprestore_offset
< 0)
11558 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11561 if (!mips_frame_reg_valid
)
11563 as_warn (_("no .frame pseudo-op used in PIC code"));
11564 /* Quiet this warning. */
11565 mips_frame_reg_valid
= 1;
11567 if (!mips_cprestore_valid
)
11569 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11570 /* Quiet this warning. */
11571 mips_cprestore_valid
= 1;
11573 if (mips_opts
.noreorder
)
11574 macro_build (NULL
, "nop", "");
11575 expr1
.X_add_number
= mips_cprestore_offset
;
11576 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11579 HAVE_64BIT_ADDRESSES
);
11583 else if (mips_pic
== VXWORKS_PIC
)
11584 as_bad (_("non-PIC jump used in PIC library"));
11691 gas_assert (!mips_opts
.micromips
);
11694 /* Itbl support may require additional care here. */
11700 /* Itbl support may require additional care here. */
11706 offbits
= (mips_opts
.micromips
? 12
11707 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11709 /* Itbl support may require additional care here. */
11713 gas_assert (!mips_opts
.micromips
);
11716 /* Itbl support may require additional care here. */
11722 offbits
= (mips_opts
.micromips
? 12 : 16);
11727 offbits
= (mips_opts
.micromips
? 12 : 16);
11732 /* Itbl support may require additional care here. */
11738 offbits
= (mips_opts
.micromips
? 12
11739 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11741 /* Itbl support may require additional care here. */
11747 /* Itbl support may require additional care here. */
11753 /* Itbl support may require additional care here. */
11759 offbits
= (mips_opts
.micromips
? 12 : 16);
11764 offbits
= (mips_opts
.micromips
? 12 : 16);
11769 offbits
= (mips_opts
.micromips
? 12
11770 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11776 offbits
= (mips_opts
.micromips
? 12
11777 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11783 offbits
= (mips_opts
.micromips
? 12 : 16);
11786 gas_assert (mips_opts
.micromips
);
11793 gas_assert (mips_opts
.micromips
);
11800 gas_assert (mips_opts
.micromips
);
11806 gas_assert (mips_opts
.micromips
);
11813 /* We don't want to use $0 as tempreg. */
11814 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11817 tempreg
= op
[0] + lp
;
11833 gas_assert (!mips_opts
.micromips
);
11836 /* Itbl support may require additional care here. */
11842 /* Itbl support may require additional care here. */
11848 offbits
= (mips_opts
.micromips
? 12
11849 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11851 /* Itbl support may require additional care here. */
11855 gas_assert (!mips_opts
.micromips
);
11858 /* Itbl support may require additional care here. */
11864 offbits
= (mips_opts
.micromips
? 12 : 16);
11869 offbits
= (mips_opts
.micromips
? 12 : 16);
11874 offbits
= (mips_opts
.micromips
? 12
11875 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11881 offbits
= (mips_opts
.micromips
? 12
11882 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11887 fmt
= (mips_opts
.micromips
? "k,~(b)"
11888 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11890 offbits
= (mips_opts
.micromips
? 12
11891 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11901 fmt
= (mips_opts
.micromips
? "k,~(b)"
11902 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11904 offbits
= (mips_opts
.micromips
? 12
11905 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11917 /* Itbl support may require additional care here. */
11922 offbits
= (mips_opts
.micromips
? 12
11923 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11925 /* Itbl support may require additional care here. */
11931 /* Itbl support may require additional care here. */
11935 gas_assert (!mips_opts
.micromips
);
11938 /* Itbl support may require additional care here. */
11944 offbits
= (mips_opts
.micromips
? 12 : 16);
11949 offbits
= (mips_opts
.micromips
? 12 : 16);
11952 gas_assert (mips_opts
.micromips
);
11958 gas_assert (mips_opts
.micromips
);
11964 gas_assert (mips_opts
.micromips
);
11970 gas_assert (mips_opts
.micromips
);
11979 if (small_offset_p (0, align
, 16))
11981 /* The first case exists for M_LD_AB and M_SD_AB, which are
11982 macros for o32 but which should act like normal instructions
11985 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11986 offset_reloc
[1], offset_reloc
[2], breg
);
11987 else if (small_offset_p (0, align
, offbits
))
11990 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11992 macro_build (NULL
, s
, fmt
, op
[0],
11993 (int) offset_expr
.X_add_number
, breg
);
11999 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12000 tempreg
, breg
, -1, offset_reloc
[0],
12001 offset_reloc
[1], offset_reloc
[2]);
12003 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12005 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12013 if (offset_expr
.X_op
!= O_constant
12014 && offset_expr
.X_op
!= O_symbol
)
12016 as_bad (_("expression too complex"));
12017 offset_expr
.X_op
= O_constant
;
12020 if (HAVE_32BIT_ADDRESSES
12021 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12025 sprintf_vma (value
, offset_expr
.X_add_number
);
12026 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12029 /* A constant expression in PIC code can be handled just as it
12030 is in non PIC code. */
12031 if (offset_expr
.X_op
== O_constant
)
12033 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12034 offbits
== 0 ? 16 : offbits
);
12035 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12037 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12039 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12040 tempreg
, tempreg
, breg
);
12043 if (offset_expr
.X_add_number
!= 0)
12044 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12045 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12046 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12048 else if (offbits
== 16)
12049 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12051 macro_build (NULL
, s
, fmt
, op
[0],
12052 (int) offset_expr
.X_add_number
, tempreg
);
12054 else if (offbits
!= 16)
12056 /* The offset field is too narrow to be used for a low-part
12057 relocation, so load the whole address into the auxiliary
12059 load_address (tempreg
, &offset_expr
, &used_at
);
12061 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12062 tempreg
, tempreg
, breg
);
12064 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12066 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12068 else if (mips_pic
== NO_PIC
)
12070 /* If this is a reference to a GP relative symbol, and there
12071 is no base register, we want
12072 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12073 Otherwise, if there is no base register, we want
12074 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12075 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12076 If we have a constant, we need two instructions anyhow,
12077 so we always use the latter form.
12079 If we have a base register, and this is a reference to a
12080 GP relative symbol, we want
12081 addu $tempreg,$breg,$gp
12082 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12084 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12085 addu $tempreg,$tempreg,$breg
12086 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12087 With a constant we always use the latter case.
12089 With 64bit address space and no base register and $at usable,
12091 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12092 lui $at,<sym> (BFD_RELOC_HI16_S)
12093 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12096 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12097 If we have a base register, we want
12098 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12099 lui $at,<sym> (BFD_RELOC_HI16_S)
12100 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12104 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12106 Without $at we can't generate the optimal path for superscalar
12107 processors here since this would require two temporary registers.
12108 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12109 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12111 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12113 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12114 If we have a base register, we want
12115 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12116 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12118 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12120 daddu $tempreg,$tempreg,$breg
12121 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12123 For GP relative symbols in 64bit address space we can use
12124 the same sequence as in 32bit address space. */
12125 if (HAVE_64BIT_SYMBOLS
)
12127 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12128 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12130 relax_start (offset_expr
.X_add_symbol
);
12133 macro_build (&offset_expr
, s
, fmt
, op
[0],
12134 BFD_RELOC_GPREL16
, mips_gp_register
);
12138 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12139 tempreg
, breg
, mips_gp_register
);
12140 macro_build (&offset_expr
, s
, fmt
, op
[0],
12141 BFD_RELOC_GPREL16
, tempreg
);
12146 if (used_at
== 0 && mips_opts
.at
)
12148 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12149 BFD_RELOC_MIPS_HIGHEST
);
12150 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12152 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12153 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12155 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12156 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12157 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12158 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12164 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12165 BFD_RELOC_MIPS_HIGHEST
);
12166 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12167 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12168 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12169 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12170 tempreg
, BFD_RELOC_HI16_S
);
12171 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12173 macro_build (NULL
, "daddu", "d,v,t",
12174 tempreg
, tempreg
, breg
);
12175 macro_build (&offset_expr
, s
, fmt
, op
[0],
12176 BFD_RELOC_LO16
, tempreg
);
12179 if (mips_relax
.sequence
)
12186 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12187 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12189 relax_start (offset_expr
.X_add_symbol
);
12190 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12194 macro_build_lui (&offset_expr
, tempreg
);
12195 macro_build (&offset_expr
, s
, fmt
, op
[0],
12196 BFD_RELOC_LO16
, tempreg
);
12197 if (mips_relax
.sequence
)
12202 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12203 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12205 relax_start (offset_expr
.X_add_symbol
);
12206 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12207 tempreg
, breg
, mips_gp_register
);
12208 macro_build (&offset_expr
, s
, fmt
, op
[0],
12209 BFD_RELOC_GPREL16
, tempreg
);
12212 macro_build_lui (&offset_expr
, tempreg
);
12213 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12214 tempreg
, tempreg
, breg
);
12215 macro_build (&offset_expr
, s
, fmt
, op
[0],
12216 BFD_RELOC_LO16
, tempreg
);
12217 if (mips_relax
.sequence
)
12221 else if (!mips_big_got
)
12223 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12225 /* If this is a reference to an external symbol, we want
12226 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12228 <op> op[0],0($tempreg)
12230 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12232 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12233 <op> op[0],0($tempreg)
12235 For NewABI, we want
12236 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12237 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12239 If there is a base register, we add it to $tempreg before
12240 the <op>. If there is a constant, we stick it in the
12241 <op> instruction. We don't handle constants larger than
12242 16 bits, because we have no way to load the upper 16 bits
12243 (actually, we could handle them for the subset of cases
12244 in which we are not using $at). */
12245 gas_assert (offset_expr
.X_op
== O_symbol
);
12248 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12249 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12251 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12252 tempreg
, tempreg
, breg
);
12253 macro_build (&offset_expr
, s
, fmt
, op
[0],
12254 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12257 expr1
.X_add_number
= offset_expr
.X_add_number
;
12258 offset_expr
.X_add_number
= 0;
12259 if (expr1
.X_add_number
< -0x8000
12260 || expr1
.X_add_number
>= 0x8000)
12261 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12262 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12263 lw_reloc_type
, mips_gp_register
);
12265 relax_start (offset_expr
.X_add_symbol
);
12267 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12268 tempreg
, BFD_RELOC_LO16
);
12271 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12272 tempreg
, tempreg
, breg
);
12273 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12275 else if (mips_big_got
&& !HAVE_NEWABI
)
12279 /* If this is a reference to an external symbol, we want
12280 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12281 addu $tempreg,$tempreg,$gp
12282 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12283 <op> op[0],0($tempreg)
12285 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12287 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12288 <op> op[0],0($tempreg)
12289 If there is a base register, we add it to $tempreg before
12290 the <op>. If there is a constant, we stick it in the
12291 <op> instruction. We don't handle constants larger than
12292 16 bits, because we have no way to load the upper 16 bits
12293 (actually, we could handle them for the subset of cases
12294 in which we are not using $at). */
12295 gas_assert (offset_expr
.X_op
== O_symbol
);
12296 expr1
.X_add_number
= offset_expr
.X_add_number
;
12297 offset_expr
.X_add_number
= 0;
12298 if (expr1
.X_add_number
< -0x8000
12299 || expr1
.X_add_number
>= 0x8000)
12300 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12301 gpdelay
= reg_needs_delay (mips_gp_register
);
12302 relax_start (offset_expr
.X_add_symbol
);
12303 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12304 BFD_RELOC_MIPS_GOT_HI16
);
12305 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12307 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12308 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12311 macro_build (NULL
, "nop", "");
12312 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12313 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12315 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12316 tempreg
, BFD_RELOC_LO16
);
12320 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12321 tempreg
, tempreg
, breg
);
12322 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12324 else if (mips_big_got
&& HAVE_NEWABI
)
12326 /* If this is a reference to an external symbol, we want
12327 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12328 add $tempreg,$tempreg,$gp
12329 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12330 <op> op[0],<ofst>($tempreg)
12331 Otherwise, for local symbols, we want:
12332 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12333 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12334 gas_assert (offset_expr
.X_op
== O_symbol
);
12335 expr1
.X_add_number
= offset_expr
.X_add_number
;
12336 offset_expr
.X_add_number
= 0;
12337 if (expr1
.X_add_number
< -0x8000
12338 || expr1
.X_add_number
>= 0x8000)
12339 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12340 relax_start (offset_expr
.X_add_symbol
);
12341 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12342 BFD_RELOC_MIPS_GOT_HI16
);
12343 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12345 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12346 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12348 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12349 tempreg
, tempreg
, breg
);
12350 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12353 offset_expr
.X_add_number
= expr1
.X_add_number
;
12354 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12355 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12357 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12358 tempreg
, tempreg
, breg
);
12359 macro_build (&offset_expr
, s
, fmt
, op
[0],
12360 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12369 gas_assert (mips_opts
.micromips
);
12370 gas_assert (mips_opts
.insn32
);
12371 start_noreorder ();
12372 macro_build (NULL
, "jr", "s", RA
);
12373 expr1
.X_add_number
= op
[0] << 2;
12374 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12379 gas_assert (mips_opts
.micromips
);
12380 gas_assert (mips_opts
.insn32
);
12381 macro_build (NULL
, "jr", "s", op
[0]);
12382 if (mips_opts
.noreorder
)
12383 macro_build (NULL
, "nop", "");
12388 load_register (op
[0], &imm_expr
, 0);
12392 load_register (op
[0], &imm_expr
, 1);
12396 if (imm_expr
.X_op
== O_constant
)
12399 load_register (AT
, &imm_expr
, 0);
12400 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12405 gas_assert (imm_expr
.X_op
== O_absent
12406 && offset_expr
.X_op
== O_symbol
12407 && strcmp (segment_name (S_GET_SEGMENT
12408 (offset_expr
.X_add_symbol
)),
12410 && offset_expr
.X_add_number
== 0);
12411 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12412 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12417 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12418 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12419 order 32 bits of the value and the low order 32 bits are either
12420 zero or in OFFSET_EXPR. */
12421 if (imm_expr
.X_op
== O_constant
)
12423 if (GPR_SIZE
== 64)
12424 load_register (op
[0], &imm_expr
, 1);
12429 if (target_big_endian
)
12441 load_register (hreg
, &imm_expr
, 0);
12444 if (offset_expr
.X_op
== O_absent
)
12445 move_register (lreg
, 0);
12448 gas_assert (offset_expr
.X_op
== O_constant
);
12449 load_register (lreg
, &offset_expr
, 0);
12455 gas_assert (imm_expr
.X_op
== O_absent
);
12457 /* We know that sym is in the .rdata section. First we get the
12458 upper 16 bits of the address. */
12459 if (mips_pic
== NO_PIC
)
12461 macro_build_lui (&offset_expr
, AT
);
12466 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12467 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12471 /* Now we load the register(s). */
12472 if (GPR_SIZE
== 64)
12475 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12476 BFD_RELOC_LO16
, AT
);
12481 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12482 BFD_RELOC_LO16
, AT
);
12485 /* FIXME: How in the world do we deal with the possible
12487 offset_expr
.X_add_number
+= 4;
12488 macro_build (&offset_expr
, "lw", "t,o(b)",
12489 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12495 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12496 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12497 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12498 the value and the low order 32 bits are either zero or in
12500 if (imm_expr
.X_op
== O_constant
)
12503 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12504 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12505 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12508 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12509 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12510 else if (FPR_SIZE
!= 32)
12511 as_bad (_("Unable to generate `%s' compliant code "
12513 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12515 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12516 if (offset_expr
.X_op
== O_absent
)
12517 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12520 gas_assert (offset_expr
.X_op
== O_constant
);
12521 load_register (AT
, &offset_expr
, 0);
12522 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12528 gas_assert (imm_expr
.X_op
== O_absent
12529 && offset_expr
.X_op
== O_symbol
12530 && offset_expr
.X_add_number
== 0);
12531 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12532 if (strcmp (s
, ".lit8") == 0)
12534 op
[2] = mips_gp_register
;
12535 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12536 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12537 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12541 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12543 if (mips_pic
!= NO_PIC
)
12544 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12545 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12548 /* FIXME: This won't work for a 64 bit address. */
12549 macro_build_lui (&offset_expr
, AT
);
12553 offset_reloc
[0] = BFD_RELOC_LO16
;
12554 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12555 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12562 * The MIPS assembler seems to check for X_add_number not
12563 * being double aligned and generating:
12564 * lui at,%hi(foo+1)
12566 * addiu at,at,%lo(foo+1)
12569 * But, the resulting address is the same after relocation so why
12570 * generate the extra instruction?
12572 /* Itbl support may require additional care here. */
12575 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12584 gas_assert (!mips_opts
.micromips
);
12585 /* Itbl support may require additional care here. */
12588 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12608 if (GPR_SIZE
== 64)
12618 if (GPR_SIZE
== 64)
12626 /* Even on a big endian machine $fn comes before $fn+1. We have
12627 to adjust when loading from memory. We set coproc if we must
12628 load $fn+1 first. */
12629 /* Itbl support may require additional care here. */
12630 if (!target_big_endian
)
12634 if (small_offset_p (0, align
, 16))
12637 if (!small_offset_p (4, align
, 16))
12639 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12640 -1, offset_reloc
[0], offset_reloc
[1],
12642 expr1
.X_add_number
= 0;
12646 offset_reloc
[0] = BFD_RELOC_LO16
;
12647 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12648 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12650 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12652 ep
->X_add_number
+= 4;
12653 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12654 offset_reloc
[1], offset_reloc
[2], breg
);
12655 ep
->X_add_number
-= 4;
12656 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12657 offset_reloc
[1], offset_reloc
[2], breg
);
12661 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12662 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12664 ep
->X_add_number
+= 4;
12665 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12666 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12672 if (offset_expr
.X_op
!= O_symbol
12673 && offset_expr
.X_op
!= O_constant
)
12675 as_bad (_("expression too complex"));
12676 offset_expr
.X_op
= O_constant
;
12679 if (HAVE_32BIT_ADDRESSES
12680 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12684 sprintf_vma (value
, offset_expr
.X_add_number
);
12685 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12688 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12690 /* If this is a reference to a GP relative symbol, we want
12691 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12692 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12693 If we have a base register, we use this
12695 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12696 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12697 If this is not a GP relative symbol, we want
12698 lui $at,<sym> (BFD_RELOC_HI16_S)
12699 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12700 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12701 If there is a base register, we add it to $at after the
12702 lui instruction. If there is a constant, we always use
12704 if (offset_expr
.X_op
== O_symbol
12705 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12706 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12708 relax_start (offset_expr
.X_add_symbol
);
12711 tempreg
= mips_gp_register
;
12715 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12716 AT
, breg
, mips_gp_register
);
12721 /* Itbl support may require additional care here. */
12722 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12723 BFD_RELOC_GPREL16
, tempreg
);
12724 offset_expr
.X_add_number
+= 4;
12726 /* Set mips_optimize to 2 to avoid inserting an
12728 hold_mips_optimize
= mips_optimize
;
12730 /* Itbl support may require additional care here. */
12731 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12732 BFD_RELOC_GPREL16
, tempreg
);
12733 mips_optimize
= hold_mips_optimize
;
12737 offset_expr
.X_add_number
-= 4;
12740 if (offset_high_part (offset_expr
.X_add_number
, 16)
12741 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12743 load_address (AT
, &offset_expr
, &used_at
);
12744 offset_expr
.X_op
= O_constant
;
12745 offset_expr
.X_add_number
= 0;
12748 macro_build_lui (&offset_expr
, AT
);
12750 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12751 /* Itbl support may require additional care here. */
12752 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12753 BFD_RELOC_LO16
, AT
);
12754 /* FIXME: How do we handle overflow here? */
12755 offset_expr
.X_add_number
+= 4;
12756 /* Itbl support may require additional care here. */
12757 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12758 BFD_RELOC_LO16
, AT
);
12759 if (mips_relax
.sequence
)
12762 else if (!mips_big_got
)
12764 /* If this is a reference to an external symbol, we want
12765 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12768 <op> op[0]+1,4($at)
12770 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12772 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12773 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12774 If there is a base register we add it to $at before the
12775 lwc1 instructions. If there is a constant we include it
12776 in the lwc1 instructions. */
12778 expr1
.X_add_number
= offset_expr
.X_add_number
;
12779 if (expr1
.X_add_number
< -0x8000
12780 || expr1
.X_add_number
>= 0x8000 - 4)
12781 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12782 load_got_offset (AT
, &offset_expr
);
12785 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12787 /* Set mips_optimize to 2 to avoid inserting an undesired
12789 hold_mips_optimize
= mips_optimize
;
12792 /* Itbl support may require additional care here. */
12793 relax_start (offset_expr
.X_add_symbol
);
12794 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12795 BFD_RELOC_LO16
, AT
);
12796 expr1
.X_add_number
+= 4;
12797 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12798 BFD_RELOC_LO16
, AT
);
12800 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12801 BFD_RELOC_LO16
, AT
);
12802 offset_expr
.X_add_number
+= 4;
12803 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12804 BFD_RELOC_LO16
, AT
);
12807 mips_optimize
= hold_mips_optimize
;
12809 else if (mips_big_got
)
12813 /* If this is a reference to an external symbol, we want
12814 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12816 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12819 <op> op[0]+1,4($at)
12821 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12823 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12824 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12825 If there is a base register we add it to $at before the
12826 lwc1 instructions. If there is a constant we include it
12827 in the lwc1 instructions. */
12829 expr1
.X_add_number
= offset_expr
.X_add_number
;
12830 offset_expr
.X_add_number
= 0;
12831 if (expr1
.X_add_number
< -0x8000
12832 || expr1
.X_add_number
>= 0x8000 - 4)
12833 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12834 gpdelay
= reg_needs_delay (mips_gp_register
);
12835 relax_start (offset_expr
.X_add_symbol
);
12836 macro_build (&offset_expr
, "lui", LUI_FMT
,
12837 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12838 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12839 AT
, AT
, mips_gp_register
);
12840 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12841 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12844 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12845 /* Itbl support may require additional care here. */
12846 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12847 BFD_RELOC_LO16
, AT
);
12848 expr1
.X_add_number
+= 4;
12850 /* Set mips_optimize to 2 to avoid inserting an undesired
12852 hold_mips_optimize
= mips_optimize
;
12854 /* Itbl support may require additional care here. */
12855 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12856 BFD_RELOC_LO16
, AT
);
12857 mips_optimize
= hold_mips_optimize
;
12858 expr1
.X_add_number
-= 4;
12861 offset_expr
.X_add_number
= expr1
.X_add_number
;
12863 macro_build (NULL
, "nop", "");
12864 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12865 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12868 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12869 /* Itbl support may require additional care here. */
12870 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12871 BFD_RELOC_LO16
, AT
);
12872 offset_expr
.X_add_number
+= 4;
12874 /* Set mips_optimize to 2 to avoid inserting an undesired
12876 hold_mips_optimize
= mips_optimize
;
12878 /* Itbl support may require additional care here. */
12879 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12880 BFD_RELOC_LO16
, AT
);
12881 mips_optimize
= hold_mips_optimize
;
12895 gas_assert (!mips_opts
.micromips
);
12900 /* New code added to support COPZ instructions.
12901 This code builds table entries out of the macros in mip_opcodes.
12902 R4000 uses interlocks to handle coproc delays.
12903 Other chips (like the R3000) require nops to be inserted for delays.
12905 FIXME: Currently, we require that the user handle delays.
12906 In order to fill delay slots for non-interlocked chips,
12907 we must have a way to specify delays based on the coprocessor.
12908 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12909 What are the side-effects of the cop instruction?
12910 What cache support might we have and what are its effects?
12911 Both coprocessor & memory require delays. how long???
12912 What registers are read/set/modified?
12914 If an itbl is provided to interpret cop instructions,
12915 this knowledge can be encoded in the itbl spec. */
12929 gas_assert (!mips_opts
.micromips
);
12930 /* For now we just do C (same as Cz). The parameter will be
12931 stored in insn_opcode by mips_ip. */
12932 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
12936 move_register (op
[0], op
[1]);
12940 gas_assert (mips_opts
.micromips
);
12941 gas_assert (mips_opts
.insn32
);
12942 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12943 micromips_to_32_reg_m_map
[op
[1]]);
12944 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12945 micromips_to_32_reg_n_map
[op
[2]]);
12950 /* Fall through. */
12952 if (mips_opts
.arch
== CPU_R5900
)
12953 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12957 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12958 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12964 /* Fall through. */
12966 /* The MIPS assembler some times generates shifts and adds. I'm
12967 not trying to be that fancy. GCC should do this for us
12970 load_register (AT
, &imm_expr
, dbl
);
12971 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12972 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12977 /* Fall through. */
12984 /* Fall through. */
12987 start_noreorder ();
12990 load_register (AT
, &imm_expr
, dbl
);
12991 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12992 op
[1], imm
? AT
: op
[2]);
12993 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12994 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12995 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12997 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13000 if (mips_opts
.micromips
)
13001 micromips_label_expr (&label_expr
);
13003 label_expr
.X_add_number
= 8;
13004 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13005 macro_build (NULL
, "nop", "");
13006 macro_build (NULL
, "break", BRK_FMT
, 6);
13007 if (mips_opts
.micromips
)
13008 micromips_add_label ();
13011 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13016 /* Fall through. */
13023 /* Fall through. */
13026 start_noreorder ();
13029 load_register (AT
, &imm_expr
, dbl
);
13030 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13031 op
[1], imm
? AT
: op
[2]);
13032 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13033 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13035 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13038 if (mips_opts
.micromips
)
13039 micromips_label_expr (&label_expr
);
13041 label_expr
.X_add_number
= 8;
13042 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13043 macro_build (NULL
, "nop", "");
13044 macro_build (NULL
, "break", BRK_FMT
, 6);
13045 if (mips_opts
.micromips
)
13046 micromips_add_label ();
13052 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13054 if (op
[0] == op
[1])
13061 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13062 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13066 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13067 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13068 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13069 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13073 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13075 if (op
[0] == op
[1])
13082 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13083 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13087 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13088 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13089 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13090 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13099 rot
= imm_expr
.X_add_number
& 0x3f;
13100 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13102 rot
= (64 - rot
) & 0x3f;
13104 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13106 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13111 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13114 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13115 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13118 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13119 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13120 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13128 rot
= imm_expr
.X_add_number
& 0x1f;
13129 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13131 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13132 (32 - rot
) & 0x1f);
13137 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13141 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13142 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13143 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13148 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13150 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13154 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13155 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13156 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13157 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13161 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13163 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13167 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13168 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13169 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13170 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13179 rot
= imm_expr
.X_add_number
& 0x3f;
13180 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13183 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13185 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13190 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13193 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13194 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13197 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13198 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13199 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13207 rot
= imm_expr
.X_add_number
& 0x1f;
13208 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13210 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13215 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13219 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13220 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13221 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13227 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13228 else if (op
[2] == 0)
13229 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13232 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13233 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13238 if (imm_expr
.X_add_number
== 0)
13240 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13245 as_warn (_("instruction %s: result is always false"),
13246 ip
->insn_mo
->name
);
13247 move_register (op
[0], 0);
13250 if (CPU_HAS_SEQ (mips_opts
.arch
)
13251 && -512 <= imm_expr
.X_add_number
13252 && imm_expr
.X_add_number
< 512)
13254 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13255 (int) imm_expr
.X_add_number
);
13258 if (imm_expr
.X_add_number
>= 0
13259 && imm_expr
.X_add_number
< 0x10000)
13260 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13261 else if (imm_expr
.X_add_number
> -0x8000
13262 && imm_expr
.X_add_number
< 0)
13264 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13265 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13266 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13268 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13271 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13272 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13277 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13278 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13281 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13284 case M_SGE
: /* X >= Y <==> not (X < Y) */
13290 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13291 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13294 case M_SGE_I
: /* X >= I <==> not (X < I) */
13296 if (imm_expr
.X_add_number
>= -0x8000
13297 && imm_expr
.X_add_number
< 0x8000)
13298 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13299 op
[0], op
[1], BFD_RELOC_LO16
);
13302 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13303 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13307 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13310 case M_SGT
: /* X > Y <==> Y < X */
13316 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13319 case M_SGT_I
: /* X > I <==> I < X */
13326 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13327 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13330 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
13336 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13337 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13340 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13347 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13348 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13349 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13353 if (imm_expr
.X_add_number
>= -0x8000
13354 && imm_expr
.X_add_number
< 0x8000)
13356 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13361 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13362 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13366 if (imm_expr
.X_add_number
>= -0x8000
13367 && imm_expr
.X_add_number
< 0x8000)
13369 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13374 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13375 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13380 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13381 else if (op
[2] == 0)
13382 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13385 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13386 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13391 if (imm_expr
.X_add_number
== 0)
13393 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13398 as_warn (_("instruction %s: result is always true"),
13399 ip
->insn_mo
->name
);
13400 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13401 op
[0], 0, BFD_RELOC_LO16
);
13404 if (CPU_HAS_SEQ (mips_opts
.arch
)
13405 && -512 <= imm_expr
.X_add_number
13406 && imm_expr
.X_add_number
< 512)
13408 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13409 (int) imm_expr
.X_add_number
);
13412 if (imm_expr
.X_add_number
>= 0
13413 && imm_expr
.X_add_number
< 0x10000)
13415 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13418 else if (imm_expr
.X_add_number
> -0x8000
13419 && imm_expr
.X_add_number
< 0)
13421 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13422 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13423 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13425 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13428 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13429 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13434 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13435 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13438 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13453 if (!mips_opts
.micromips
)
13455 if (imm_expr
.X_add_number
> -0x200
13456 && imm_expr
.X_add_number
<= 0x200)
13458 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13459 (int) -imm_expr
.X_add_number
);
13468 if (imm_expr
.X_add_number
> -0x8000
13469 && imm_expr
.X_add_number
<= 0x8000)
13471 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13472 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13477 load_register (AT
, &imm_expr
, dbl
);
13478 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13500 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13501 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13506 gas_assert (!mips_opts
.micromips
);
13507 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13511 * Is the double cfc1 instruction a bug in the mips assembler;
13512 * or is there a reason for it?
13514 start_noreorder ();
13515 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13516 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13517 macro_build (NULL
, "nop", "");
13518 expr1
.X_add_number
= 3;
13519 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13520 expr1
.X_add_number
= 2;
13521 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13522 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13523 macro_build (NULL
, "nop", "");
13524 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13526 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13527 macro_build (NULL
, "nop", "");
13544 offbits
= (mips_opts
.micromips
? 12 : 16);
13550 offbits
= (mips_opts
.micromips
? 12 : 16);
13562 offbits
= (mips_opts
.micromips
? 12 : 16);
13569 offbits
= (mips_opts
.micromips
? 12 : 16);
13575 large_offset
= !small_offset_p (off
, align
, offbits
);
13577 expr1
.X_add_number
= 0;
13582 if (small_offset_p (0, align
, 16))
13583 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13584 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13587 load_address (tempreg
, ep
, &used_at
);
13589 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13590 tempreg
, tempreg
, breg
);
13592 offset_reloc
[0] = BFD_RELOC_LO16
;
13593 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13594 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13599 else if (!ust
&& op
[0] == breg
)
13610 if (!target_big_endian
)
13611 ep
->X_add_number
+= off
;
13613 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13615 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13616 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13618 if (!target_big_endian
)
13619 ep
->X_add_number
-= off
;
13621 ep
->X_add_number
+= off
;
13623 macro_build (NULL
, s2
, "t,~(b)",
13624 tempreg
, (int) ep
->X_add_number
, breg
);
13626 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13627 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13629 /* If necessary, move the result in tempreg to the final destination. */
13630 if (!ust
&& op
[0] != tempreg
)
13632 /* Protect second load's delay slot. */
13634 move_register (op
[0], tempreg
);
13640 if (target_big_endian
== ust
)
13641 ep
->X_add_number
+= off
;
13642 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13643 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13644 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13646 /* For halfword transfers we need a temporary register to shuffle
13647 bytes. Unfortunately for M_USH_A we have none available before
13648 the next store as AT holds the base address. We deal with this
13649 case by clobbering TREG and then restoring it as with ULH. */
13650 tempreg
= ust
== large_offset
? op
[0] : AT
;
13652 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13654 if (target_big_endian
== ust
)
13655 ep
->X_add_number
-= off
;
13657 ep
->X_add_number
+= off
;
13658 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13659 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13661 /* For M_USH_A re-retrieve the LSB. */
13662 if (ust
&& large_offset
)
13664 if (target_big_endian
)
13665 ep
->X_add_number
+= off
;
13667 ep
->X_add_number
-= off
;
13668 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13669 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13671 /* For ULH and M_USH_A OR the LSB in. */
13672 if (!ust
|| large_offset
)
13674 tempreg
= !large_offset
? AT
: op
[0];
13675 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13676 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13681 /* FIXME: Check if this is one of the itbl macros, since they
13682 are added dynamically. */
13683 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13686 if (!mips_opts
.at
&& used_at
)
13687 as_bad (_("macro used $at after \".set noat\""));
13690 /* Implement macros in mips16 mode. */
13693 mips16_macro (struct mips_cl_insn
*ip
)
13695 const struct mips_operand_array
*operands
;
13700 const char *s
, *s2
, *s3
;
13701 unsigned int op
[MAX_OPERANDS
];
13704 mask
= ip
->insn_mo
->mask
;
13706 operands
= insn_operands (ip
);
13707 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13708 if (operands
->operand
[i
])
13709 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13713 expr1
.X_op
= O_constant
;
13714 expr1
.X_op_symbol
= NULL
;
13715 expr1
.X_add_symbol
= NULL
;
13716 expr1
.X_add_number
= 1;
13727 /* Fall through. */
13733 /* Fall through. */
13737 start_noreorder ();
13738 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
13739 expr1
.X_add_number
= 2;
13740 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13741 macro_build (NULL
, "break", "6", 7);
13743 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13744 since that causes an overflow. We should do that as well,
13745 but I don't see how to do the comparisons without a temporary
13748 macro_build (NULL
, s
, "x", op
[0]);
13767 start_noreorder ();
13768 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
13769 expr1
.X_add_number
= 2;
13770 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13771 macro_build (NULL
, "break", "6", 7);
13773 macro_build (NULL
, s2
, "x", op
[0]);
13778 /* Fall through. */
13780 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13781 macro_build (NULL
, "mflo", "x", op
[0]);
13789 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13790 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
13794 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13795 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13799 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13800 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13822 goto do_reverse_branch
;
13826 goto do_reverse_branch
;
13838 goto do_reverse_branch
;
13849 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13850 macro_build (&offset_expr
, s2
, "p");
13877 goto do_addone_branch_i
;
13882 goto do_addone_branch_i
;
13897 goto do_addone_branch_i
;
13903 do_addone_branch_i
:
13904 ++imm_expr
.X_add_number
;
13907 macro_build (&imm_expr
, s
, s3
, op
[0]);
13908 macro_build (&offset_expr
, s2
, "p");
13912 expr1
.X_add_number
= 0;
13913 macro_build (&expr1
, "slti", "x,8", op
[1]);
13914 if (op
[0] != op
[1])
13915 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13916 expr1
.X_add_number
= 2;
13917 macro_build (&expr1
, "bteqz", "p");
13918 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13923 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13924 opcode bits in *OPCODE_EXTRA. */
13926 static struct mips_opcode
*
13927 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13928 ssize_t length
, unsigned int *opcode_extra
)
13930 char *name
, *dot
, *p
;
13931 unsigned int mask
, suffix
;
13933 struct mips_opcode
*insn
;
13935 /* Make a copy of the instruction so that we can fiddle with it. */
13936 name
= xstrndup (start
, length
);
13938 /* Look up the instruction as-is. */
13939 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13943 dot
= strchr (name
, '.');
13946 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13947 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13948 if (*p
== 0 && mask
!= 0)
13951 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13953 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13955 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13961 if (mips_opts
.micromips
)
13963 /* See if there's an instruction size override suffix,
13964 either `16' or `32', at the end of the mnemonic proper,
13965 that defines the operation, i.e. before the first `.'
13966 character if any. Strip it and retry. */
13967 opend
= dot
!= NULL
? dot
- name
: length
;
13968 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13970 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13976 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13977 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13980 forced_insn_length
= suffix
;
13992 /* Assemble an instruction into its binary format. If the instruction
13993 is a macro, set imm_expr and offset_expr to the values associated
13994 with "I" and "A" operands respectively. Otherwise store the value
13995 of the relocatable field (if any) in offset_expr. In both cases
13996 set offset_reloc to the relocation operators applied to offset_expr. */
13999 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14001 const struct mips_opcode
*first
, *past
;
14002 struct hash_control
*hash
;
14005 struct mips_operand_token
*tokens
;
14006 unsigned int opcode_extra
;
14008 if (mips_opts
.micromips
)
14010 hash
= micromips_op_hash
;
14011 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14016 past
= &mips_opcodes
[NUMOPCODES
];
14018 forced_insn_length
= 0;
14021 /* We first try to match an instruction up to a space or to the end. */
14022 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14025 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14028 set_insn_error (0, _("unrecognized opcode"));
14032 if (strcmp (first
->name
, "li.s") == 0)
14034 else if (strcmp (first
->name
, "li.d") == 0)
14038 tokens
= mips_parse_arguments (str
+ end
, format
);
14042 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
14043 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
14044 set_insn_error (0, _("invalid operands"));
14046 obstack_free (&mips_operand_tokens
, tokens
);
14049 /* As for mips_ip, but used when assembling MIPS16 code.
14050 Also set forced_insn_length to the resulting instruction size in
14051 bytes if the user explicitly requested a small or extended instruction. */
14054 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14057 struct mips_opcode
*first
;
14058 struct mips_operand_token
*tokens
;
14061 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14083 else if (*s
== 'e')
14090 else if (*s
++ == ' ')
14092 set_insn_error (0, _("unrecognized opcode"));
14095 forced_insn_length
= l
;
14098 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
14103 set_insn_error (0, _("unrecognized opcode"));
14107 tokens
= mips_parse_arguments (s
, 0);
14111 if (!match_mips16_insns (insn
, first
, tokens
))
14112 set_insn_error (0, _("invalid operands"));
14114 obstack_free (&mips_operand_tokens
, tokens
);
14117 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14118 NBITS is the number of significant bits in VAL. */
14120 static unsigned long
14121 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14126 val
&= (1U << nbits
) - 1;
14127 if (nbits
== 16 || nbits
== 9)
14129 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14132 else if (nbits
== 15)
14134 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14137 else if (nbits
== 6)
14139 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14142 return (extval
<< 16) | val
;
14145 /* Like decode_mips16_operand, but require the operand to be defined and
14146 require it to be an integer. */
14148 static const struct mips_int_operand
*
14149 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14151 const struct mips_operand
*operand
;
14153 operand
= decode_mips16_operand (type
, extended_p
);
14154 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14156 return (const struct mips_int_operand
*) operand
;
14159 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14162 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14163 bfd_reloc_code_real_type reloc
, offsetT sval
)
14165 int min_val
, max_val
;
14167 min_val
= mips_int_operand_min (operand
);
14168 max_val
= mips_int_operand_max (operand
);
14169 if (reloc
!= BFD_RELOC_UNUSED
)
14172 sval
= SEXT_16BIT (sval
);
14177 return (sval
>= min_val
14179 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14182 /* Install immediate value VAL into MIPS16 instruction *INSN,
14183 extending it if necessary. The instruction in *INSN may
14184 already be extended.
14186 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14187 if none. In the former case, VAL is a 16-bit number with no
14188 defined signedness.
14190 TYPE is the type of the immediate field. USER_INSN_LENGTH
14191 is the length that the user requested, or 0 if none. */
14194 mips16_immed (const char *file
, unsigned int line
, int type
,
14195 bfd_reloc_code_real_type reloc
, offsetT val
,
14196 unsigned int user_insn_length
, unsigned long *insn
)
14198 const struct mips_int_operand
*operand
;
14199 unsigned int uval
, length
;
14201 operand
= mips16_immed_operand (type
, FALSE
);
14202 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14204 /* We need an extended instruction. */
14205 if (user_insn_length
== 2)
14206 as_bad_where (file
, line
, _("invalid unextended operand value"));
14208 *insn
|= MIPS16_EXTEND
;
14210 else if (user_insn_length
== 4)
14212 /* The operand doesn't force an unextended instruction to be extended.
14213 Warn if the user wanted an extended instruction anyway. */
14214 *insn
|= MIPS16_EXTEND
;
14215 as_warn_where (file
, line
,
14216 _("extended operand requested but not required"));
14219 length
= mips16_opcode_length (*insn
);
14222 operand
= mips16_immed_operand (type
, TRUE
);
14223 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14224 as_bad_where (file
, line
,
14225 _("operand value out of range for instruction"));
14227 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14228 if (length
== 2 || operand
->root
.lsb
!= 0)
14229 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14231 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14234 struct percent_op_match
14237 bfd_reloc_code_real_type reloc
;
14240 static const struct percent_op_match mips_percent_op
[] =
14242 {"%lo", BFD_RELOC_LO16
},
14243 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14244 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14245 {"%call16", BFD_RELOC_MIPS_CALL16
},
14246 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14247 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14248 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14249 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14250 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14251 {"%got", BFD_RELOC_MIPS_GOT16
},
14252 {"%gp_rel", BFD_RELOC_GPREL16
},
14253 {"%gprel", BFD_RELOC_GPREL16
},
14254 {"%half", BFD_RELOC_16
},
14255 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14256 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14257 {"%neg", BFD_RELOC_MIPS_SUB
},
14258 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14259 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14260 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14261 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14262 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14263 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14264 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14265 {"%hi", BFD_RELOC_HI16_S
},
14266 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14267 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14270 static const struct percent_op_match mips16_percent_op
[] =
14272 {"%lo", BFD_RELOC_MIPS16_LO16
},
14273 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14274 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14275 {"%got", BFD_RELOC_MIPS16_GOT16
},
14276 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14277 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14278 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14279 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14280 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14281 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14282 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14283 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14284 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14288 /* Return true if *STR points to a relocation operator. When returning true,
14289 move *STR over the operator and store its relocation code in *RELOC.
14290 Leave both *STR and *RELOC alone when returning false. */
14293 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14295 const struct percent_op_match
*percent_op
;
14298 if (mips_opts
.mips16
)
14300 percent_op
= mips16_percent_op
;
14301 limit
= ARRAY_SIZE (mips16_percent_op
);
14305 percent_op
= mips_percent_op
;
14306 limit
= ARRAY_SIZE (mips_percent_op
);
14309 for (i
= 0; i
< limit
; i
++)
14310 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14312 int len
= strlen (percent_op
[i
].str
);
14314 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14317 *str
+= strlen (percent_op
[i
].str
);
14318 *reloc
= percent_op
[i
].reloc
;
14320 /* Check whether the output BFD supports this relocation.
14321 If not, issue an error and fall back on something safe. */
14322 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14324 as_bad (_("relocation %s isn't supported by the current ABI"),
14325 percent_op
[i
].str
);
14326 *reloc
= BFD_RELOC_UNUSED
;
14334 /* Parse string STR as a 16-bit relocatable operand. Store the
14335 expression in *EP and the relocations in the array starting
14336 at RELOC. Return the number of relocation operators used.
14338 On exit, EXPR_END points to the first character after the expression. */
14341 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14344 bfd_reloc_code_real_type reversed_reloc
[3];
14345 size_t reloc_index
, i
;
14346 int crux_depth
, str_depth
;
14349 /* Search for the start of the main expression, recoding relocations
14350 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14351 of the main expression and with CRUX_DEPTH containing the number
14352 of open brackets at that point. */
14359 crux_depth
= str_depth
;
14361 /* Skip over whitespace and brackets, keeping count of the number
14363 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14368 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14369 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14371 my_getExpression (ep
, crux
);
14374 /* Match every open bracket. */
14375 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14379 if (crux_depth
> 0)
14380 as_bad (_("unclosed '('"));
14384 if (reloc_index
!= 0)
14386 prev_reloc_op_frag
= frag_now
;
14387 for (i
= 0; i
< reloc_index
; i
++)
14388 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14391 return reloc_index
;
14395 my_getExpression (expressionS
*ep
, char *str
)
14399 save_in
= input_line_pointer
;
14400 input_line_pointer
= str
;
14402 expr_end
= input_line_pointer
;
14403 input_line_pointer
= save_in
;
14407 md_atof (int type
, char *litP
, int *sizeP
)
14409 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14413 md_number_to_chars (char *buf
, valueT val
, int n
)
14415 if (target_big_endian
)
14416 number_to_chars_bigendian (buf
, val
, n
);
14418 number_to_chars_littleendian (buf
, val
, n
);
14421 static int support_64bit_objects(void)
14423 const char **list
, **l
;
14426 list
= bfd_target_list ();
14427 for (l
= list
; *l
!= NULL
; l
++)
14428 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14429 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14431 yes
= (*l
!= NULL
);
14436 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14437 NEW_VALUE. Warn if another value was already specified. Note:
14438 we have to defer parsing the -march and -mtune arguments in order
14439 to handle 'from-abi' correctly, since the ABI might be specified
14440 in a later argument. */
14443 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14445 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14446 as_warn (_("a different %s was already specified, is now %s"),
14447 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14450 *string_ptr
= new_value
;
14454 md_parse_option (int c
, const char *arg
)
14458 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14459 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14461 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14462 c
== mips_ases
[i
].option_on
);
14468 case OPTION_CONSTRUCT_FLOATS
:
14469 mips_disable_float_construction
= 0;
14472 case OPTION_NO_CONSTRUCT_FLOATS
:
14473 mips_disable_float_construction
= 1;
14485 target_big_endian
= 1;
14489 target_big_endian
= 0;
14495 else if (arg
[0] == '0')
14497 else if (arg
[0] == '1')
14507 mips_debug
= atoi (arg
);
14511 file_mips_opts
.isa
= ISA_MIPS1
;
14515 file_mips_opts
.isa
= ISA_MIPS2
;
14519 file_mips_opts
.isa
= ISA_MIPS3
;
14523 file_mips_opts
.isa
= ISA_MIPS4
;
14527 file_mips_opts
.isa
= ISA_MIPS5
;
14530 case OPTION_MIPS32
:
14531 file_mips_opts
.isa
= ISA_MIPS32
;
14534 case OPTION_MIPS32R2
:
14535 file_mips_opts
.isa
= ISA_MIPS32R2
;
14538 case OPTION_MIPS32R3
:
14539 file_mips_opts
.isa
= ISA_MIPS32R3
;
14542 case OPTION_MIPS32R5
:
14543 file_mips_opts
.isa
= ISA_MIPS32R5
;
14546 case OPTION_MIPS32R6
:
14547 file_mips_opts
.isa
= ISA_MIPS32R6
;
14550 case OPTION_MIPS64R2
:
14551 file_mips_opts
.isa
= ISA_MIPS64R2
;
14554 case OPTION_MIPS64R3
:
14555 file_mips_opts
.isa
= ISA_MIPS64R3
;
14558 case OPTION_MIPS64R5
:
14559 file_mips_opts
.isa
= ISA_MIPS64R5
;
14562 case OPTION_MIPS64R6
:
14563 file_mips_opts
.isa
= ISA_MIPS64R6
;
14566 case OPTION_MIPS64
:
14567 file_mips_opts
.isa
= ISA_MIPS64
;
14571 mips_set_option_string (&mips_tune_string
, arg
);
14575 mips_set_option_string (&mips_arch_string
, arg
);
14579 mips_set_option_string (&mips_arch_string
, "4650");
14580 mips_set_option_string (&mips_tune_string
, "4650");
14583 case OPTION_NO_M4650
:
14587 mips_set_option_string (&mips_arch_string
, "4010");
14588 mips_set_option_string (&mips_tune_string
, "4010");
14591 case OPTION_NO_M4010
:
14595 mips_set_option_string (&mips_arch_string
, "4100");
14596 mips_set_option_string (&mips_tune_string
, "4100");
14599 case OPTION_NO_M4100
:
14603 mips_set_option_string (&mips_arch_string
, "3900");
14604 mips_set_option_string (&mips_tune_string
, "3900");
14607 case OPTION_NO_M3900
:
14610 case OPTION_MICROMIPS
:
14611 if (file_mips_opts
.mips16
== 1)
14613 as_bad (_("-mmicromips cannot be used with -mips16"));
14616 file_mips_opts
.micromips
= 1;
14617 mips_no_prev_insn ();
14620 case OPTION_NO_MICROMIPS
:
14621 file_mips_opts
.micromips
= 0;
14622 mips_no_prev_insn ();
14625 case OPTION_MIPS16
:
14626 if (file_mips_opts
.micromips
== 1)
14628 as_bad (_("-mips16 cannot be used with -micromips"));
14631 file_mips_opts
.mips16
= 1;
14632 mips_no_prev_insn ();
14635 case OPTION_NO_MIPS16
:
14636 file_mips_opts
.mips16
= 0;
14637 mips_no_prev_insn ();
14640 case OPTION_FIX_24K
:
14644 case OPTION_NO_FIX_24K
:
14648 case OPTION_FIX_RM7000
:
14649 mips_fix_rm7000
= 1;
14652 case OPTION_NO_FIX_RM7000
:
14653 mips_fix_rm7000
= 0;
14656 case OPTION_FIX_LOONGSON2F_JUMP
:
14657 mips_fix_loongson2f_jump
= TRUE
;
14660 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14661 mips_fix_loongson2f_jump
= FALSE
;
14664 case OPTION_FIX_LOONGSON2F_NOP
:
14665 mips_fix_loongson2f_nop
= TRUE
;
14668 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14669 mips_fix_loongson2f_nop
= FALSE
;
14672 case OPTION_FIX_VR4120
:
14673 mips_fix_vr4120
= 1;
14676 case OPTION_NO_FIX_VR4120
:
14677 mips_fix_vr4120
= 0;
14680 case OPTION_FIX_VR4130
:
14681 mips_fix_vr4130
= 1;
14684 case OPTION_NO_FIX_VR4130
:
14685 mips_fix_vr4130
= 0;
14688 case OPTION_FIX_CN63XXP1
:
14689 mips_fix_cn63xxp1
= TRUE
;
14692 case OPTION_NO_FIX_CN63XXP1
:
14693 mips_fix_cn63xxp1
= FALSE
;
14696 case OPTION_RELAX_BRANCH
:
14697 mips_relax_branch
= 1;
14700 case OPTION_NO_RELAX_BRANCH
:
14701 mips_relax_branch
= 0;
14704 case OPTION_IGNORE_BRANCH_ISA
:
14705 mips_ignore_branch_isa
= TRUE
;
14708 case OPTION_NO_IGNORE_BRANCH_ISA
:
14709 mips_ignore_branch_isa
= FALSE
;
14712 case OPTION_INSN32
:
14713 file_mips_opts
.insn32
= TRUE
;
14716 case OPTION_NO_INSN32
:
14717 file_mips_opts
.insn32
= FALSE
;
14720 case OPTION_MSHARED
:
14721 mips_in_shared
= TRUE
;
14724 case OPTION_MNO_SHARED
:
14725 mips_in_shared
= FALSE
;
14728 case OPTION_MSYM32
:
14729 file_mips_opts
.sym32
= TRUE
;
14732 case OPTION_MNO_SYM32
:
14733 file_mips_opts
.sym32
= FALSE
;
14736 /* When generating ELF code, we permit -KPIC and -call_shared to
14737 select SVR4_PIC, and -non_shared to select no PIC. This is
14738 intended to be compatible with Irix 5. */
14739 case OPTION_CALL_SHARED
:
14740 mips_pic
= SVR4_PIC
;
14741 mips_abicalls
= TRUE
;
14744 case OPTION_CALL_NONPIC
:
14746 mips_abicalls
= TRUE
;
14749 case OPTION_NON_SHARED
:
14751 mips_abicalls
= FALSE
;
14754 /* The -xgot option tells the assembler to use 32 bit offsets
14755 when accessing the got in SVR4_PIC mode. It is for Irix
14762 g_switch_value
= atoi (arg
);
14766 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14769 mips_abi
= O32_ABI
;
14773 mips_abi
= N32_ABI
;
14777 mips_abi
= N64_ABI
;
14778 if (!support_64bit_objects())
14779 as_fatal (_("no compiled in support for 64 bit object file format"));
14783 file_mips_opts
.gp
= 32;
14787 file_mips_opts
.gp
= 64;
14791 file_mips_opts
.fp
= 32;
14795 file_mips_opts
.fp
= 0;
14799 file_mips_opts
.fp
= 64;
14802 case OPTION_ODD_SPREG
:
14803 file_mips_opts
.oddspreg
= 1;
14806 case OPTION_NO_ODD_SPREG
:
14807 file_mips_opts
.oddspreg
= 0;
14810 case OPTION_SINGLE_FLOAT
:
14811 file_mips_opts
.single_float
= 1;
14814 case OPTION_DOUBLE_FLOAT
:
14815 file_mips_opts
.single_float
= 0;
14818 case OPTION_SOFT_FLOAT
:
14819 file_mips_opts
.soft_float
= 1;
14822 case OPTION_HARD_FLOAT
:
14823 file_mips_opts
.soft_float
= 0;
14827 if (strcmp (arg
, "32") == 0)
14828 mips_abi
= O32_ABI
;
14829 else if (strcmp (arg
, "o64") == 0)
14830 mips_abi
= O64_ABI
;
14831 else if (strcmp (arg
, "n32") == 0)
14832 mips_abi
= N32_ABI
;
14833 else if (strcmp (arg
, "64") == 0)
14835 mips_abi
= N64_ABI
;
14836 if (! support_64bit_objects())
14837 as_fatal (_("no compiled in support for 64 bit object file "
14840 else if (strcmp (arg
, "eabi") == 0)
14841 mips_abi
= EABI_ABI
;
14844 as_fatal (_("invalid abi -mabi=%s"), arg
);
14849 case OPTION_M7000_HILO_FIX
:
14850 mips_7000_hilo_fix
= TRUE
;
14853 case OPTION_MNO_7000_HILO_FIX
:
14854 mips_7000_hilo_fix
= FALSE
;
14857 case OPTION_MDEBUG
:
14858 mips_flag_mdebug
= TRUE
;
14861 case OPTION_NO_MDEBUG
:
14862 mips_flag_mdebug
= FALSE
;
14866 mips_flag_pdr
= TRUE
;
14869 case OPTION_NO_PDR
:
14870 mips_flag_pdr
= FALSE
;
14873 case OPTION_MVXWORKS_PIC
:
14874 mips_pic
= VXWORKS_PIC
;
14878 if (strcmp (arg
, "2008") == 0)
14880 else if (strcmp (arg
, "legacy") == 0)
14884 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14893 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14898 /* Set up globals to tune for the ISA or processor described by INFO. */
14901 mips_set_tune (const struct mips_cpu_info
*info
)
14904 mips_tune
= info
->cpu
;
14909 mips_after_parse_args (void)
14911 const struct mips_cpu_info
*arch_info
= 0;
14912 const struct mips_cpu_info
*tune_info
= 0;
14914 /* GP relative stuff not working for PE */
14915 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14917 if (g_switch_seen
&& g_switch_value
!= 0)
14918 as_bad (_("-G not supported in this configuration"));
14919 g_switch_value
= 0;
14922 if (mips_abi
== NO_ABI
)
14923 mips_abi
= MIPS_DEFAULT_ABI
;
14925 /* The following code determines the architecture.
14926 Similar code was added to GCC 3.3 (see override_options() in
14927 config/mips/mips.c). The GAS and GCC code should be kept in sync
14928 as much as possible. */
14930 if (mips_arch_string
!= 0)
14931 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14933 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
14935 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14936 ISA level specified by -mipsN, while arch_info->isa contains
14937 the -march selection (if any). */
14938 if (arch_info
!= 0)
14940 /* -march takes precedence over -mipsN, since it is more descriptive.
14941 There's no harm in specifying both as long as the ISA levels
14943 if (file_mips_opts
.isa
!= arch_info
->isa
)
14944 as_bad (_("-%s conflicts with the other architecture options,"
14945 " which imply -%s"),
14946 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
14947 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14950 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
14953 if (arch_info
== 0)
14955 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14956 gas_assert (arch_info
);
14959 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14960 as_bad (_("-march=%s is not compatible with the selected ABI"),
14963 file_mips_opts
.arch
= arch_info
->cpu
;
14964 file_mips_opts
.isa
= arch_info
->isa
;
14966 /* Set up initial mips_opts state. */
14967 mips_opts
= file_mips_opts
;
14969 /* The register size inference code is now placed in
14970 file_mips_check_options. */
14972 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14974 if (mips_tune_string
!= 0)
14975 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
14977 if (tune_info
== 0)
14978 mips_set_tune (arch_info
);
14980 mips_set_tune (tune_info
);
14982 if (mips_flag_mdebug
< 0)
14983 mips_flag_mdebug
= 0;
14987 mips_init_after_args (void)
14989 /* initialize opcodes */
14990 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14991 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14995 md_pcrel_from (fixS
*fixP
)
14997 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14998 switch (fixP
->fx_r_type
)
15000 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15001 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15002 /* Return the address of the delay slot. */
15005 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15006 case BFD_RELOC_MICROMIPS_JMP
:
15007 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15008 case BFD_RELOC_16_PCREL_S2
:
15009 case BFD_RELOC_MIPS_21_PCREL_S2
:
15010 case BFD_RELOC_MIPS_26_PCREL_S2
:
15011 case BFD_RELOC_MIPS_JMP
:
15012 /* Return the address of the delay slot. */
15015 case BFD_RELOC_MIPS_18_PCREL_S3
:
15016 /* Return the aligned address of the doubleword containing
15017 the instruction. */
15025 /* This is called before the symbol table is processed. In order to
15026 work with gcc when using mips-tfile, we must keep all local labels.
15027 However, in other cases, we want to discard them. If we were
15028 called with -g, but we didn't see any debugging information, it may
15029 mean that gcc is smuggling debugging information through to
15030 mips-tfile, in which case we must generate all local labels. */
15033 mips_frob_file_before_adjust (void)
15035 #ifndef NO_ECOFF_DEBUGGING
15036 if (ECOFF_DEBUGGING
15038 && ! ecoff_debugging_seen
)
15039 flag_keep_locals
= 1;
15043 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15044 the corresponding LO16 reloc. This is called before md_apply_fix and
15045 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15046 relocation operators.
15048 For our purposes, a %lo() expression matches a %got() or %hi()
15051 (a) it refers to the same symbol; and
15052 (b) the offset applied in the %lo() expression is no lower than
15053 the offset applied in the %got() or %hi().
15055 (b) allows us to cope with code like:
15058 lh $4,%lo(foo+2)($4)
15060 ...which is legal on RELA targets, and has a well-defined behaviour
15061 if the user knows that adding 2 to "foo" will not induce a carry to
15064 When several %lo()s match a particular %got() or %hi(), we use the
15065 following rules to distinguish them:
15067 (1) %lo()s with smaller offsets are a better match than %lo()s with
15070 (2) %lo()s with no matching %got() or %hi() are better than those
15071 that already have a matching %got() or %hi().
15073 (3) later %lo()s are better than earlier %lo()s.
15075 These rules are applied in order.
15077 (1) means, among other things, that %lo()s with identical offsets are
15078 chosen if they exist.
15080 (2) means that we won't associate several high-part relocations with
15081 the same low-part relocation unless there's no alternative. Having
15082 several high parts for the same low part is a GNU extension; this rule
15083 allows careful users to avoid it.
15085 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15086 with the last high-part relocation being at the front of the list.
15087 It therefore makes sense to choose the last matching low-part
15088 relocation, all other things being equal. It's also easier
15089 to code that way. */
15092 mips_frob_file (void)
15094 struct mips_hi_fixup
*l
;
15095 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15097 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15099 segment_info_type
*seginfo
;
15100 bfd_boolean matched_lo_p
;
15101 fixS
**hi_pos
, **lo_pos
, **pos
;
15103 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15105 /* If a GOT16 relocation turns out to be against a global symbol,
15106 there isn't supposed to be a matching LO. Ignore %gots against
15107 constants; we'll report an error for those later. */
15108 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15109 && !(l
->fixp
->fx_addsy
15110 && pic_need_relax (l
->fixp
->fx_addsy
)))
15113 /* Check quickly whether the next fixup happens to be a matching %lo. */
15114 if (fixup_has_matching_lo_p (l
->fixp
))
15117 seginfo
= seg_info (l
->seg
);
15119 /* Set HI_POS to the position of this relocation in the chain.
15120 Set LO_POS to the position of the chosen low-part relocation.
15121 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15122 relocation that matches an immediately-preceding high-part
15126 matched_lo_p
= FALSE
;
15127 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15129 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15131 if (*pos
== l
->fixp
)
15134 if ((*pos
)->fx_r_type
== looking_for_rtype
15135 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15136 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15138 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15140 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15143 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15144 && fixup_has_matching_lo_p (*pos
));
15147 /* If we found a match, remove the high-part relocation from its
15148 current position and insert it before the low-part relocation.
15149 Make the offsets match so that fixup_has_matching_lo_p()
15152 We don't warn about unmatched high-part relocations since some
15153 versions of gcc have been known to emit dead "lui ...%hi(...)"
15155 if (lo_pos
!= NULL
)
15157 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15158 if (l
->fixp
->fx_next
!= *lo_pos
)
15160 *hi_pos
= l
->fixp
->fx_next
;
15161 l
->fixp
->fx_next
= *lo_pos
;
15169 mips_force_relocation (fixS
*fixp
)
15171 if (generic_force_reloc (fixp
))
15174 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15175 so that the linker relaxation can update targets. */
15176 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15177 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15178 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15181 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15182 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15183 microMIPS symbols so that we can do cross-mode branch diagnostics
15184 and BAL to JALX conversion by the linker. */
15185 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15186 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15187 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15189 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15192 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15193 if (ISA_IS_R6 (file_mips_opts
.isa
)
15194 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15195 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15196 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15197 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15198 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15199 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15200 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15206 /* Implement TC_FORCE_RELOCATION_ABS. */
15209 mips_force_relocation_abs (fixS
*fixp
)
15211 if (generic_force_reloc (fixp
))
15214 /* These relocations do not have enough bits in the in-place addend
15215 to hold an arbitrary absolute section's offset. */
15216 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15222 /* Read the instruction associated with RELOC from BUF. */
15224 static unsigned int
15225 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15227 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15228 return read_compressed_insn (buf
, 4);
15230 return read_insn (buf
);
15233 /* Write instruction INSN to BUF, given that it has been relocated
15237 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15238 unsigned long insn
)
15240 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15241 write_compressed_insn (buf
, insn
, 4);
15243 write_insn (buf
, insn
);
15246 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15247 to a symbol in another ISA mode, which cannot be converted to JALX. */
15250 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15252 unsigned long opcode
;
15256 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15259 other
= S_GET_OTHER (fixP
->fx_addsy
);
15260 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15261 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15262 switch (fixP
->fx_r_type
)
15264 case BFD_RELOC_MIPS_JMP
:
15265 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15266 case BFD_RELOC_MICROMIPS_JMP
:
15267 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15273 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15274 jump to a symbol in the same ISA mode. */
15277 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15279 unsigned long opcode
;
15283 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15286 other
= S_GET_OTHER (fixP
->fx_addsy
);
15287 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15288 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15289 switch (fixP
->fx_r_type
)
15291 case BFD_RELOC_MIPS_JMP
:
15292 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15293 case BFD_RELOC_MIPS16_JMP
:
15294 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15295 case BFD_RELOC_MICROMIPS_JMP
:
15296 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15302 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15303 to a symbol whose value plus addend is not aligned according to the
15304 ultimate (after linker relaxation) jump instruction's immediate field
15305 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15306 regular MIPS code, to (1 << 2). */
15309 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15311 bfd_boolean micro_to_mips_p
;
15315 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15318 other
= S_GET_OTHER (fixP
->fx_addsy
);
15319 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15320 val
+= fixP
->fx_offset
;
15321 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15322 && !ELF_ST_IS_MICROMIPS (other
));
15323 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15324 != ELF_ST_IS_COMPRESSED (other
));
15327 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15328 to a symbol whose annotation indicates another ISA mode. For absolute
15329 symbols check the ISA bit instead.
15331 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15332 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15333 MIPS symbols and associated with BAL instructions as these instructions
15334 may be converted to JALX by the linker. */
15337 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15339 bfd_boolean absolute_p
;
15340 unsigned long opcode
;
15346 if (mips_ignore_branch_isa
)
15349 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15352 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15353 absolute_p
= bfd_is_abs_section (symsec
);
15355 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15356 other
= S_GET_OTHER (fixP
->fx_addsy
);
15358 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15359 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15360 switch (fixP
->fx_r_type
)
15362 case BFD_RELOC_16_PCREL_S2
:
15363 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15364 && opcode
!= 0x0411);
15365 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15366 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15367 && opcode
!= 0x4060);
15368 case BFD_RELOC_MIPS_21_PCREL_S2
:
15369 case BFD_RELOC_MIPS_26_PCREL_S2
:
15370 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15371 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15372 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15373 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15374 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15375 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15381 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15382 branch instruction pointed to by FIXP is not aligned according to the
15383 branch instruction's immediate field requirement. We need the addend
15384 to preserve the ISA bit and also the sum must not have bit 2 set. We
15385 must explicitly OR in the ISA bit from symbol annotation as the bit
15386 won't be set in the symbol's value then. */
15389 fix_bad_misaligned_branch_p (fixS
*fixP
)
15391 bfd_boolean absolute_p
;
15398 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15401 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15402 absolute_p
= bfd_is_abs_section (symsec
);
15404 val
= S_GET_VALUE (fixP
->fx_addsy
);
15405 other
= S_GET_OTHER (fixP
->fx_addsy
);
15406 off
= fixP
->fx_offset
;
15408 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15409 val
|= ELF_ST_IS_COMPRESSED (other
);
15411 return (val
& 0x3) != isa_bit
;
15414 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15415 and its calculated value VAL. */
15418 fix_validate_branch (fixS
*fixP
, valueT val
)
15420 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15421 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15422 _("branch to misaligned address (0x%lx)"),
15423 (long) (val
+ md_pcrel_from (fixP
)));
15424 else if (fix_bad_cross_mode_branch_p (fixP
))
15425 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15426 _("branch to a symbol in another ISA mode"));
15427 else if (fix_bad_misaligned_branch_p (fixP
))
15428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15429 _("branch to misaligned address (0x%lx)"),
15430 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15431 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15432 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15433 _("cannot encode misaligned addend "
15434 "in the relocatable field (0x%lx)"),
15435 (long) fixP
->fx_offset
);
15438 /* Apply a fixup to the object file. */
15441 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15444 unsigned long insn
;
15445 reloc_howto_type
*howto
;
15447 if (fixP
->fx_pcrel
)
15448 switch (fixP
->fx_r_type
)
15450 case BFD_RELOC_16_PCREL_S2
:
15451 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15452 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15453 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15454 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15455 case BFD_RELOC_32_PCREL
:
15456 case BFD_RELOC_MIPS_21_PCREL_S2
:
15457 case BFD_RELOC_MIPS_26_PCREL_S2
:
15458 case BFD_RELOC_MIPS_18_PCREL_S3
:
15459 case BFD_RELOC_MIPS_19_PCREL_S2
:
15460 case BFD_RELOC_HI16_S_PCREL
:
15461 case BFD_RELOC_LO16_PCREL
:
15465 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15469 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15470 _("PC-relative reference to a different section"));
15474 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15475 that have no MIPS ELF equivalent. */
15476 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15478 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15483 gas_assert (fixP
->fx_size
== 2
15484 || fixP
->fx_size
== 4
15485 || fixP
->fx_r_type
== BFD_RELOC_8
15486 || fixP
->fx_r_type
== BFD_RELOC_16
15487 || fixP
->fx_r_type
== BFD_RELOC_64
15488 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15489 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15490 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15491 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15492 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15493 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15494 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15496 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15498 /* Don't treat parts of a composite relocation as done. There are two
15501 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15502 should nevertheless be emitted if the first part is.
15504 (2) In normal usage, composite relocations are never assembly-time
15505 constants. The easiest way of dealing with the pathological
15506 exceptions is to generate a relocation against STN_UNDEF and
15507 leave everything up to the linker. */
15508 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15511 switch (fixP
->fx_r_type
)
15513 case BFD_RELOC_MIPS_TLS_GD
:
15514 case BFD_RELOC_MIPS_TLS_LDM
:
15515 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15516 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15517 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15518 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15519 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15520 case BFD_RELOC_MIPS_TLS_TPREL32
:
15521 case BFD_RELOC_MIPS_TLS_TPREL64
:
15522 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15523 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15524 case BFD_RELOC_MICROMIPS_TLS_GD
:
15525 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15526 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15527 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15528 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15529 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15530 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15531 case BFD_RELOC_MIPS16_TLS_GD
:
15532 case BFD_RELOC_MIPS16_TLS_LDM
:
15533 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15534 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15535 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15536 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15537 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15538 if (fixP
->fx_addsy
)
15539 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15541 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15542 _("TLS relocation against a constant"));
15545 case BFD_RELOC_MIPS_JMP
:
15546 case BFD_RELOC_MIPS16_JMP
:
15547 case BFD_RELOC_MICROMIPS_JMP
:
15551 gas_assert (!fixP
->fx_done
);
15553 /* Shift is 2, unusually, for microMIPS JALX. */
15554 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15555 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15560 if (fix_bad_cross_mode_jump_p (fixP
))
15561 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15562 _("jump to a symbol in another ISA mode"));
15563 else if (fix_bad_same_mode_jalx_p (fixP
))
15564 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15565 _("JALX to a symbol in the same ISA mode"));
15566 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15567 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15568 _("jump to misaligned address (0x%lx)"),
15569 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15570 + fixP
->fx_offset
));
15571 else if (HAVE_IN_PLACE_ADDENDS
15572 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15573 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15574 _("cannot encode misaligned addend "
15575 "in the relocatable field (0x%lx)"),
15576 (long) fixP
->fx_offset
);
15578 /* Fall through. */
15580 case BFD_RELOC_MIPS_SHIFT5
:
15581 case BFD_RELOC_MIPS_SHIFT6
:
15582 case BFD_RELOC_MIPS_GOT_DISP
:
15583 case BFD_RELOC_MIPS_GOT_PAGE
:
15584 case BFD_RELOC_MIPS_GOT_OFST
:
15585 case BFD_RELOC_MIPS_SUB
:
15586 case BFD_RELOC_MIPS_INSERT_A
:
15587 case BFD_RELOC_MIPS_INSERT_B
:
15588 case BFD_RELOC_MIPS_DELETE
:
15589 case BFD_RELOC_MIPS_HIGHEST
:
15590 case BFD_RELOC_MIPS_HIGHER
:
15591 case BFD_RELOC_MIPS_SCN_DISP
:
15592 case BFD_RELOC_MIPS_REL16
:
15593 case BFD_RELOC_MIPS_RELGOT
:
15594 case BFD_RELOC_MIPS_JALR
:
15595 case BFD_RELOC_HI16
:
15596 case BFD_RELOC_HI16_S
:
15597 case BFD_RELOC_LO16
:
15598 case BFD_RELOC_GPREL16
:
15599 case BFD_RELOC_MIPS_LITERAL
:
15600 case BFD_RELOC_MIPS_CALL16
:
15601 case BFD_RELOC_MIPS_GOT16
:
15602 case BFD_RELOC_GPREL32
:
15603 case BFD_RELOC_MIPS_GOT_HI16
:
15604 case BFD_RELOC_MIPS_GOT_LO16
:
15605 case BFD_RELOC_MIPS_CALL_HI16
:
15606 case BFD_RELOC_MIPS_CALL_LO16
:
15607 case BFD_RELOC_HI16_S_PCREL
:
15608 case BFD_RELOC_LO16_PCREL
:
15609 case BFD_RELOC_MIPS16_GPREL
:
15610 case BFD_RELOC_MIPS16_GOT16
:
15611 case BFD_RELOC_MIPS16_CALL16
:
15612 case BFD_RELOC_MIPS16_HI16
:
15613 case BFD_RELOC_MIPS16_HI16_S
:
15614 case BFD_RELOC_MIPS16_LO16
:
15615 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15616 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15617 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15618 case BFD_RELOC_MICROMIPS_SUB
:
15619 case BFD_RELOC_MICROMIPS_HIGHEST
:
15620 case BFD_RELOC_MICROMIPS_HIGHER
:
15621 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15622 case BFD_RELOC_MICROMIPS_JALR
:
15623 case BFD_RELOC_MICROMIPS_HI16
:
15624 case BFD_RELOC_MICROMIPS_HI16_S
:
15625 case BFD_RELOC_MICROMIPS_LO16
:
15626 case BFD_RELOC_MICROMIPS_GPREL16
:
15627 case BFD_RELOC_MICROMIPS_LITERAL
:
15628 case BFD_RELOC_MICROMIPS_CALL16
:
15629 case BFD_RELOC_MICROMIPS_GOT16
:
15630 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15631 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15632 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15633 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15634 case BFD_RELOC_MIPS_EH
:
15639 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15641 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15642 if (mips16_reloc_p (fixP
->fx_r_type
))
15643 insn
|= mips16_immed_extend (value
, 16);
15645 insn
|= (value
& 0xffff);
15646 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15649 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15650 _("unsupported constant in relocation"));
15655 /* This is handled like BFD_RELOC_32, but we output a sign
15656 extended value if we are only 32 bits. */
15659 if (8 <= sizeof (valueT
))
15660 md_number_to_chars (buf
, *valP
, 8);
15665 if ((*valP
& 0x80000000) != 0)
15669 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15670 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15675 case BFD_RELOC_RVA
:
15677 case BFD_RELOC_32_PCREL
:
15680 /* If we are deleting this reloc entry, we must fill in the
15681 value now. This can happen if we have a .word which is not
15682 resolved when it appears but is later defined. */
15684 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15687 case BFD_RELOC_MIPS_21_PCREL_S2
:
15688 fix_validate_branch (fixP
, *valP
);
15689 if (!fixP
->fx_done
)
15692 if (*valP
+ 0x400000 <= 0x7fffff)
15694 insn
= read_insn (buf
);
15695 insn
|= (*valP
>> 2) & 0x1fffff;
15696 write_insn (buf
, insn
);
15699 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15700 _("branch out of range"));
15703 case BFD_RELOC_MIPS_26_PCREL_S2
:
15704 fix_validate_branch (fixP
, *valP
);
15705 if (!fixP
->fx_done
)
15708 if (*valP
+ 0x8000000 <= 0xfffffff)
15710 insn
= read_insn (buf
);
15711 insn
|= (*valP
>> 2) & 0x3ffffff;
15712 write_insn (buf
, insn
);
15715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15716 _("branch out of range"));
15719 case BFD_RELOC_MIPS_18_PCREL_S3
:
15720 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15721 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15722 _("PC-relative access using misaligned symbol (%lx)"),
15723 (long) S_GET_VALUE (fixP
->fx_addsy
));
15724 if ((fixP
->fx_offset
& 0x7) != 0)
15725 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15726 _("PC-relative access using misaligned offset (%lx)"),
15727 (long) fixP
->fx_offset
);
15728 if (!fixP
->fx_done
)
15731 if (*valP
+ 0x100000 <= 0x1fffff)
15733 insn
= read_insn (buf
);
15734 insn
|= (*valP
>> 3) & 0x3ffff;
15735 write_insn (buf
, insn
);
15738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15739 _("PC-relative access out of range"));
15742 case BFD_RELOC_MIPS_19_PCREL_S2
:
15743 if ((*valP
& 0x3) != 0)
15744 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15745 _("PC-relative access to misaligned address (%lx)"),
15747 if (!fixP
->fx_done
)
15750 if (*valP
+ 0x100000 <= 0x1fffff)
15752 insn
= read_insn (buf
);
15753 insn
|= (*valP
>> 2) & 0x7ffff;
15754 write_insn (buf
, insn
);
15757 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15758 _("PC-relative access out of range"));
15761 case BFD_RELOC_16_PCREL_S2
:
15762 fix_validate_branch (fixP
, *valP
);
15764 /* We need to save the bits in the instruction since fixup_segment()
15765 might be deleting the relocation entry (i.e., a branch within
15766 the current segment). */
15767 if (! fixP
->fx_done
)
15770 /* Update old instruction data. */
15771 insn
= read_insn (buf
);
15773 if (*valP
+ 0x20000 <= 0x3ffff)
15775 insn
|= (*valP
>> 2) & 0xffff;
15776 write_insn (buf
, insn
);
15778 else if (fixP
->fx_tcbit2
15780 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15781 && (fixP
->fx_frag
->fr_address
15782 < text_section
->vma
+ bfd_get_section_size (text_section
))
15783 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15784 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15785 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15787 /* The branch offset is too large. If this is an
15788 unconditional branch, and we are not generating PIC code,
15789 we can convert it to an absolute jump instruction. */
15790 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15791 insn
= 0x0c000000; /* jal */
15793 insn
= 0x08000000; /* j */
15794 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15796 fixP
->fx_addsy
= section_symbol (text_section
);
15797 *valP
+= md_pcrel_from (fixP
);
15798 write_insn (buf
, insn
);
15802 /* If we got here, we have branch-relaxation disabled,
15803 and there's nothing we can do to fix this instruction
15804 without turning it into a longer sequence. */
15805 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15806 _("branch out of range"));
15810 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15811 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15812 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15813 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15814 gas_assert (!fixP
->fx_done
);
15815 if (fix_bad_cross_mode_branch_p (fixP
))
15816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15817 _("branch to a symbol in another ISA mode"));
15818 else if (fixP
->fx_addsy
15819 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
15820 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
15821 && (fixP
->fx_offset
& 0x1) != 0)
15822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15823 _("branch to misaligned address (0x%lx)"),
15824 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15825 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
15826 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15827 _("cannot encode misaligned addend "
15828 "in the relocatable field (0x%lx)"),
15829 (long) fixP
->fx_offset
);
15832 case BFD_RELOC_VTABLE_INHERIT
:
15835 && !S_IS_DEFINED (fixP
->fx_addsy
)
15836 && !S_IS_WEAK (fixP
->fx_addsy
))
15837 S_SET_WEAK (fixP
->fx_addsy
);
15840 case BFD_RELOC_NONE
:
15841 case BFD_RELOC_VTABLE_ENTRY
:
15849 /* Remember value for tc_gen_reloc. */
15850 fixP
->fx_addnumber
= *valP
;
15860 c
= get_symbol_name (&name
);
15861 p
= (symbolS
*) symbol_find_or_make (name
);
15862 (void) restore_line_pointer (c
);
15866 /* Align the current frag to a given power of two. If a particular
15867 fill byte should be used, FILL points to an integer that contains
15868 that byte, otherwise FILL is null.
15870 This function used to have the comment:
15872 The MIPS assembler also automatically adjusts any preceding label.
15874 The implementation therefore applied the adjustment to a maximum of
15875 one label. However, other label adjustments are applied to batches
15876 of labels, and adjusting just one caused problems when new labels
15877 were added for the sake of debugging or unwind information.
15878 We therefore adjust all preceding labels (given as LABELS) instead. */
15881 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15883 mips_emit_delays ();
15884 mips_record_compressed_mode ();
15885 if (fill
== NULL
&& subseg_text_p (now_seg
))
15886 frag_align_code (to
, 0);
15888 frag_align (to
, fill
? *fill
: 0, 0);
15889 record_alignment (now_seg
, to
);
15890 mips_move_labels (labels
, FALSE
);
15893 /* Align to a given power of two. .align 0 turns off the automatic
15894 alignment used by the data creating pseudo-ops. */
15897 s_align (int x ATTRIBUTE_UNUSED
)
15899 int temp
, fill_value
, *fill_ptr
;
15900 long max_alignment
= 28;
15902 /* o Note that the assembler pulls down any immediately preceding label
15903 to the aligned address.
15904 o It's not documented but auto alignment is reinstated by
15905 a .align pseudo instruction.
15906 o Note also that after auto alignment is turned off the mips assembler
15907 issues an error on attempt to assemble an improperly aligned data item.
15910 temp
= get_absolute_expression ();
15911 if (temp
> max_alignment
)
15912 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15915 as_warn (_("alignment negative, 0 assumed"));
15918 if (*input_line_pointer
== ',')
15920 ++input_line_pointer
;
15921 fill_value
= get_absolute_expression ();
15922 fill_ptr
= &fill_value
;
15928 segment_info_type
*si
= seg_info (now_seg
);
15929 struct insn_label_list
*l
= si
->label_list
;
15930 /* Auto alignment should be switched on by next section change. */
15932 mips_align (temp
, fill_ptr
, l
);
15939 demand_empty_rest_of_line ();
15943 s_change_sec (int sec
)
15947 /* The ELF backend needs to know that we are changing sections, so
15948 that .previous works correctly. We could do something like check
15949 for an obj_section_change_hook macro, but that might be confusing
15950 as it would not be appropriate to use it in the section changing
15951 functions in read.c, since obj-elf.c intercepts those. FIXME:
15952 This should be cleaner, somehow. */
15953 obj_elf_section_change_hook ();
15955 mips_emit_delays ();
15966 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15967 demand_empty_rest_of_line ();
15971 seg
= subseg_new (RDATA_SECTION_NAME
,
15972 (subsegT
) get_absolute_expression ());
15973 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15974 | SEC_READONLY
| SEC_RELOC
15976 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15977 record_alignment (seg
, 4);
15978 demand_empty_rest_of_line ();
15982 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15983 bfd_set_section_flags (stdoutput
, seg
,
15984 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15985 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15986 record_alignment (seg
, 4);
15987 demand_empty_rest_of_line ();
15991 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15992 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15993 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15994 record_alignment (seg
, 4);
15995 demand_empty_rest_of_line ();
16003 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16006 char *section_name
;
16011 int section_entry_size
;
16012 int section_alignment
;
16014 saved_ilp
= input_line_pointer
;
16015 endc
= get_symbol_name (§ion_name
);
16016 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
16018 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
16020 /* Do we have .section Name<,"flags">? */
16021 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16023 /* Just after name is now '\0'. */
16024 (void) restore_line_pointer (endc
);
16025 input_line_pointer
= saved_ilp
;
16026 obj_elf_section (ignore
);
16030 section_name
= xstrdup (section_name
);
16031 c
= restore_line_pointer (endc
);
16033 input_line_pointer
++;
16035 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16037 section_type
= get_absolute_expression ();
16041 if (*input_line_pointer
++ == ',')
16042 section_flag
= get_absolute_expression ();
16046 if (*input_line_pointer
++ == ',')
16047 section_entry_size
= get_absolute_expression ();
16049 section_entry_size
= 0;
16051 if (*input_line_pointer
++ == ',')
16052 section_alignment
= get_absolute_expression ();
16054 section_alignment
= 0;
16056 /* FIXME: really ignore? */
16057 (void) section_alignment
;
16059 /* When using the generic form of .section (as implemented by obj-elf.c),
16060 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16061 traditionally had to fall back on the more common @progbits instead.
16063 There's nothing really harmful in this, since bfd will correct
16064 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16065 means that, for backwards compatibility, the special_section entries
16066 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16068 Even so, we shouldn't force users of the MIPS .section syntax to
16069 incorrectly label the sections as SHT_PROGBITS. The best compromise
16070 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16071 generic type-checking code. */
16072 if (section_type
== SHT_MIPS_DWARF
)
16073 section_type
= SHT_PROGBITS
;
16075 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
16076 section_entry_size
, 0, 0, 0);
16078 if (now_seg
->name
!= section_name
)
16079 free (section_name
);
16083 mips_enable_auto_align (void)
16089 s_cons (int log_size
)
16091 segment_info_type
*si
= seg_info (now_seg
);
16092 struct insn_label_list
*l
= si
->label_list
;
16094 mips_emit_delays ();
16095 if (log_size
> 0 && auto_align
)
16096 mips_align (log_size
, 0, l
);
16097 cons (1 << log_size
);
16098 mips_clear_insn_labels ();
16102 s_float_cons (int type
)
16104 segment_info_type
*si
= seg_info (now_seg
);
16105 struct insn_label_list
*l
= si
->label_list
;
16107 mips_emit_delays ();
16112 mips_align (3, 0, l
);
16114 mips_align (2, 0, l
);
16118 mips_clear_insn_labels ();
16121 /* Handle .globl. We need to override it because on Irix 5 you are
16124 where foo is an undefined symbol, to mean that foo should be
16125 considered to be the address of a function. */
16128 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16137 c
= get_symbol_name (&name
);
16138 symbolP
= symbol_find_or_make (name
);
16139 S_SET_EXTERNAL (symbolP
);
16141 *input_line_pointer
= c
;
16142 SKIP_WHITESPACE_AFTER_NAME ();
16144 /* On Irix 5, every global symbol that is not explicitly labelled as
16145 being a function is apparently labelled as being an object. */
16148 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16149 && (*input_line_pointer
!= ','))
16154 c
= get_symbol_name (&secname
);
16155 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16157 as_bad (_("%s: no such section"), secname
);
16158 (void) restore_line_pointer (c
);
16160 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16161 flag
= BSF_FUNCTION
;
16164 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16166 c
= *input_line_pointer
;
16169 input_line_pointer
++;
16170 SKIP_WHITESPACE ();
16171 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16177 demand_empty_rest_of_line ();
16181 s_option (int x ATTRIBUTE_UNUSED
)
16186 c
= get_symbol_name (&opt
);
16190 /* FIXME: What does this mean? */
16192 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16196 i
= atoi (opt
+ 3);
16197 if (i
!= 0 && i
!= 2)
16198 as_bad (_(".option pic%d not supported"), i
);
16199 else if (mips_pic
== VXWORKS_PIC
)
16200 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16205 mips_pic
= SVR4_PIC
;
16206 mips_abicalls
= TRUE
;
16209 if (mips_pic
== SVR4_PIC
)
16211 if (g_switch_seen
&& g_switch_value
!= 0)
16212 as_warn (_("-G may not be used with SVR4 PIC code"));
16213 g_switch_value
= 0;
16214 bfd_set_gp_size (stdoutput
, 0);
16218 as_warn (_("unrecognized option \"%s\""), opt
);
16220 (void) restore_line_pointer (c
);
16221 demand_empty_rest_of_line ();
16224 /* This structure is used to hold a stack of .set values. */
16226 struct mips_option_stack
16228 struct mips_option_stack
*next
;
16229 struct mips_set_options options
;
16232 static struct mips_option_stack
*mips_opts_stack
;
16234 /* Return status for .set/.module option handling. */
16236 enum code_option_type
16238 /* Unrecognized option. */
16239 OPTION_TYPE_BAD
= -1,
16241 /* Ordinary option. */
16242 OPTION_TYPE_NORMAL
,
16244 /* ISA changing option. */
16248 /* Handle common .set/.module options. Return status indicating option
16251 static enum code_option_type
16252 parse_code_option (char * name
)
16254 bfd_boolean isa_set
= FALSE
;
16255 const struct mips_ase
*ase
;
16257 if (strncmp (name
, "at=", 3) == 0)
16259 char *s
= name
+ 3;
16261 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16262 as_bad (_("unrecognized register name `%s'"), s
);
16264 else if (strcmp (name
, "at") == 0)
16265 mips_opts
.at
= ATREG
;
16266 else if (strcmp (name
, "noat") == 0)
16267 mips_opts
.at
= ZERO
;
16268 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16269 mips_opts
.nomove
= 0;
16270 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16271 mips_opts
.nomove
= 1;
16272 else if (strcmp (name
, "bopt") == 0)
16273 mips_opts
.nobopt
= 0;
16274 else if (strcmp (name
, "nobopt") == 0)
16275 mips_opts
.nobopt
= 1;
16276 else if (strcmp (name
, "gp=32") == 0)
16278 else if (strcmp (name
, "gp=64") == 0)
16280 else if (strcmp (name
, "fp=32") == 0)
16282 else if (strcmp (name
, "fp=xx") == 0)
16284 else if (strcmp (name
, "fp=64") == 0)
16286 else if (strcmp (name
, "softfloat") == 0)
16287 mips_opts
.soft_float
= 1;
16288 else if (strcmp (name
, "hardfloat") == 0)
16289 mips_opts
.soft_float
= 0;
16290 else if (strcmp (name
, "singlefloat") == 0)
16291 mips_opts
.single_float
= 1;
16292 else if (strcmp (name
, "doublefloat") == 0)
16293 mips_opts
.single_float
= 0;
16294 else if (strcmp (name
, "nooddspreg") == 0)
16295 mips_opts
.oddspreg
= 0;
16296 else if (strcmp (name
, "oddspreg") == 0)
16297 mips_opts
.oddspreg
= 1;
16298 else if (strcmp (name
, "mips16") == 0
16299 || strcmp (name
, "MIPS-16") == 0)
16300 mips_opts
.mips16
= 1;
16301 else if (strcmp (name
, "nomips16") == 0
16302 || strcmp (name
, "noMIPS-16") == 0)
16303 mips_opts
.mips16
= 0;
16304 else if (strcmp (name
, "micromips") == 0)
16305 mips_opts
.micromips
= 1;
16306 else if (strcmp (name
, "nomicromips") == 0)
16307 mips_opts
.micromips
= 0;
16308 else if (name
[0] == 'n'
16310 && (ase
= mips_lookup_ase (name
+ 2)))
16311 mips_set_ase (ase
, &mips_opts
, FALSE
);
16312 else if ((ase
= mips_lookup_ase (name
)))
16313 mips_set_ase (ase
, &mips_opts
, TRUE
);
16314 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16316 /* Permit the user to change the ISA and architecture on the fly.
16317 Needless to say, misuse can cause serious problems. */
16318 if (strncmp (name
, "arch=", 5) == 0)
16320 const struct mips_cpu_info
*p
;
16322 p
= mips_parse_cpu ("internal use", name
+ 5);
16324 as_bad (_("unknown architecture %s"), name
+ 5);
16327 mips_opts
.arch
= p
->cpu
;
16328 mips_opts
.isa
= p
->isa
;
16332 else if (strncmp (name
, "mips", 4) == 0)
16334 const struct mips_cpu_info
*p
;
16336 p
= mips_parse_cpu ("internal use", name
);
16338 as_bad (_("unknown ISA level %s"), name
+ 4);
16341 mips_opts
.arch
= p
->cpu
;
16342 mips_opts
.isa
= p
->isa
;
16347 as_bad (_("unknown ISA or architecture %s"), name
);
16349 else if (strcmp (name
, "autoextend") == 0)
16350 mips_opts
.noautoextend
= 0;
16351 else if (strcmp (name
, "noautoextend") == 0)
16352 mips_opts
.noautoextend
= 1;
16353 else if (strcmp (name
, "insn32") == 0)
16354 mips_opts
.insn32
= TRUE
;
16355 else if (strcmp (name
, "noinsn32") == 0)
16356 mips_opts
.insn32
= FALSE
;
16357 else if (strcmp (name
, "sym32") == 0)
16358 mips_opts
.sym32
= TRUE
;
16359 else if (strcmp (name
, "nosym32") == 0)
16360 mips_opts
.sym32
= FALSE
;
16362 return OPTION_TYPE_BAD
;
16364 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16367 /* Handle the .set pseudo-op. */
16370 s_mipsset (int x ATTRIBUTE_UNUSED
)
16372 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16373 char *name
= input_line_pointer
, ch
;
16375 file_mips_check_options ();
16377 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16378 ++input_line_pointer
;
16379 ch
= *input_line_pointer
;
16380 *input_line_pointer
= '\0';
16382 if (strchr (name
, ','))
16384 /* Generic ".set" directive; use the generic handler. */
16385 *input_line_pointer
= ch
;
16386 input_line_pointer
= name
;
16391 if (strcmp (name
, "reorder") == 0)
16393 if (mips_opts
.noreorder
)
16396 else if (strcmp (name
, "noreorder") == 0)
16398 if (!mips_opts
.noreorder
)
16399 start_noreorder ();
16401 else if (strcmp (name
, "macro") == 0)
16402 mips_opts
.warn_about_macros
= 0;
16403 else if (strcmp (name
, "nomacro") == 0)
16405 if (mips_opts
.noreorder
== 0)
16406 as_bad (_("`noreorder' must be set before `nomacro'"));
16407 mips_opts
.warn_about_macros
= 1;
16409 else if (strcmp (name
, "gp=default") == 0)
16410 mips_opts
.gp
= file_mips_opts
.gp
;
16411 else if (strcmp (name
, "fp=default") == 0)
16412 mips_opts
.fp
= file_mips_opts
.fp
;
16413 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16415 mips_opts
.isa
= file_mips_opts
.isa
;
16416 mips_opts
.arch
= file_mips_opts
.arch
;
16417 mips_opts
.gp
= file_mips_opts
.gp
;
16418 mips_opts
.fp
= file_mips_opts
.fp
;
16420 else if (strcmp (name
, "push") == 0)
16422 struct mips_option_stack
*s
;
16424 s
= XNEW (struct mips_option_stack
);
16425 s
->next
= mips_opts_stack
;
16426 s
->options
= mips_opts
;
16427 mips_opts_stack
= s
;
16429 else if (strcmp (name
, "pop") == 0)
16431 struct mips_option_stack
*s
;
16433 s
= mips_opts_stack
;
16435 as_bad (_(".set pop with no .set push"));
16438 /* If we're changing the reorder mode we need to handle
16439 delay slots correctly. */
16440 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16441 start_noreorder ();
16442 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16445 mips_opts
= s
->options
;
16446 mips_opts_stack
= s
->next
;
16452 type
= parse_code_option (name
);
16453 if (type
== OPTION_TYPE_BAD
)
16454 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16457 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16458 registers based on what is supported by the arch/cpu. */
16459 if (type
== OPTION_TYPE_ISA
)
16461 switch (mips_opts
.isa
)
16466 /* MIPS I cannot support FPXX. */
16468 /* fall-through. */
16475 if (mips_opts
.fp
!= 0)
16491 if (mips_opts
.fp
!= 0)
16493 if (mips_opts
.arch
== CPU_R5900
)
16500 as_bad (_("unknown ISA level %s"), name
+ 4);
16505 mips_check_options (&mips_opts
, FALSE
);
16507 mips_check_isa_supports_ases ();
16508 *input_line_pointer
= ch
;
16509 demand_empty_rest_of_line ();
16512 /* Handle the .module pseudo-op. */
16515 s_module (int ignore ATTRIBUTE_UNUSED
)
16517 char *name
= input_line_pointer
, ch
;
16519 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16520 ++input_line_pointer
;
16521 ch
= *input_line_pointer
;
16522 *input_line_pointer
= '\0';
16524 if (!file_mips_opts_checked
)
16526 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16527 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16529 /* Update module level settings from mips_opts. */
16530 file_mips_opts
= mips_opts
;
16533 as_bad (_(".module is not permitted after generating code"));
16535 *input_line_pointer
= ch
;
16536 demand_empty_rest_of_line ();
16539 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16540 .option pic2. It means to generate SVR4 PIC calls. */
16543 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16545 mips_pic
= SVR4_PIC
;
16546 mips_abicalls
= TRUE
;
16548 if (g_switch_seen
&& g_switch_value
!= 0)
16549 as_warn (_("-G may not be used with SVR4 PIC code"));
16550 g_switch_value
= 0;
16552 bfd_set_gp_size (stdoutput
, 0);
16553 demand_empty_rest_of_line ();
16556 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16557 PIC code. It sets the $gp register for the function based on the
16558 function address, which is in the register named in the argument.
16559 This uses a relocation against _gp_disp, which is handled specially
16560 by the linker. The result is:
16561 lui $gp,%hi(_gp_disp)
16562 addiu $gp,$gp,%lo(_gp_disp)
16563 addu $gp,$gp,.cpload argument
16564 The .cpload argument is normally $25 == $t9.
16566 The -mno-shared option changes this to:
16567 lui $gp,%hi(__gnu_local_gp)
16568 addiu $gp,$gp,%lo(__gnu_local_gp)
16569 and the argument is ignored. This saves an instruction, but the
16570 resulting code is not position independent; it uses an absolute
16571 address for __gnu_local_gp. Thus code assembled with -mno-shared
16572 can go into an ordinary executable, but not into a shared library. */
16575 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16581 file_mips_check_options ();
16583 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16584 .cpload is ignored. */
16585 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16591 if (mips_opts
.mips16
)
16593 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16594 ignore_rest_of_line ();
16598 /* .cpload should be in a .set noreorder section. */
16599 if (mips_opts
.noreorder
== 0)
16600 as_warn (_(".cpload not in noreorder section"));
16602 reg
= tc_get_register (0);
16604 /* If we need to produce a 64-bit address, we are better off using
16605 the default instruction sequence. */
16606 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16608 ex
.X_op
= O_symbol
;
16609 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16611 ex
.X_op_symbol
= NULL
;
16612 ex
.X_add_number
= 0;
16614 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16615 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16617 mips_mark_labels ();
16618 mips_assembling_insn
= TRUE
;
16621 macro_build_lui (&ex
, mips_gp_register
);
16622 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16623 mips_gp_register
, BFD_RELOC_LO16
);
16625 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16626 mips_gp_register
, reg
);
16629 mips_assembling_insn
= FALSE
;
16630 demand_empty_rest_of_line ();
16633 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16634 .cpsetup $reg1, offset|$reg2, label
16636 If offset is given, this results in:
16637 sd $gp, offset($sp)
16638 lui $gp, %hi(%neg(%gp_rel(label)))
16639 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16640 daddu $gp, $gp, $reg1
16642 If $reg2 is given, this results in:
16644 lui $gp, %hi(%neg(%gp_rel(label)))
16645 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16646 daddu $gp, $gp, $reg1
16647 $reg1 is normally $25 == $t9.
16649 The -mno-shared option replaces the last three instructions with
16651 addiu $gp,$gp,%lo(_gp) */
16654 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16656 expressionS ex_off
;
16657 expressionS ex_sym
;
16660 file_mips_check_options ();
16662 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16663 We also need NewABI support. */
16664 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16670 if (mips_opts
.mips16
)
16672 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16673 ignore_rest_of_line ();
16677 reg1
= tc_get_register (0);
16678 SKIP_WHITESPACE ();
16679 if (*input_line_pointer
!= ',')
16681 as_bad (_("missing argument separator ',' for .cpsetup"));
16685 ++input_line_pointer
;
16686 SKIP_WHITESPACE ();
16687 if (*input_line_pointer
== '$')
16689 mips_cpreturn_register
= tc_get_register (0);
16690 mips_cpreturn_offset
= -1;
16694 mips_cpreturn_offset
= get_absolute_expression ();
16695 mips_cpreturn_register
= -1;
16697 SKIP_WHITESPACE ();
16698 if (*input_line_pointer
!= ',')
16700 as_bad (_("missing argument separator ',' for .cpsetup"));
16704 ++input_line_pointer
;
16705 SKIP_WHITESPACE ();
16706 expression (&ex_sym
);
16708 mips_mark_labels ();
16709 mips_assembling_insn
= TRUE
;
16712 if (mips_cpreturn_register
== -1)
16714 ex_off
.X_op
= O_constant
;
16715 ex_off
.X_add_symbol
= NULL
;
16716 ex_off
.X_op_symbol
= NULL
;
16717 ex_off
.X_add_number
= mips_cpreturn_offset
;
16719 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16720 BFD_RELOC_LO16
, SP
);
16723 move_register (mips_cpreturn_register
, mips_gp_register
);
16725 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16727 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16728 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16731 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16732 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16733 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16735 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16736 mips_gp_register
, reg1
);
16742 ex
.X_op
= O_symbol
;
16743 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16744 ex
.X_op_symbol
= NULL
;
16745 ex
.X_add_number
= 0;
16747 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16748 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16750 macro_build_lui (&ex
, mips_gp_register
);
16751 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16752 mips_gp_register
, BFD_RELOC_LO16
);
16757 mips_assembling_insn
= FALSE
;
16758 demand_empty_rest_of_line ();
16762 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16764 file_mips_check_options ();
16766 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16767 .cplocal is ignored. */
16768 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16774 if (mips_opts
.mips16
)
16776 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16777 ignore_rest_of_line ();
16781 mips_gp_register
= tc_get_register (0);
16782 demand_empty_rest_of_line ();
16785 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16786 offset from $sp. The offset is remembered, and after making a PIC
16787 call $gp is restored from that location. */
16790 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16794 file_mips_check_options ();
16796 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16797 .cprestore is ignored. */
16798 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16804 if (mips_opts
.mips16
)
16806 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16807 ignore_rest_of_line ();
16811 mips_cprestore_offset
= get_absolute_expression ();
16812 mips_cprestore_valid
= 1;
16814 ex
.X_op
= O_constant
;
16815 ex
.X_add_symbol
= NULL
;
16816 ex
.X_op_symbol
= NULL
;
16817 ex
.X_add_number
= mips_cprestore_offset
;
16819 mips_mark_labels ();
16820 mips_assembling_insn
= TRUE
;
16823 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16824 SP
, HAVE_64BIT_ADDRESSES
);
16827 mips_assembling_insn
= FALSE
;
16828 demand_empty_rest_of_line ();
16831 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16832 was given in the preceding .cpsetup, it results in:
16833 ld $gp, offset($sp)
16835 If a register $reg2 was given there, it results in:
16836 or $gp, $reg2, $0 */
16839 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16843 file_mips_check_options ();
16845 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16846 We also need NewABI support. */
16847 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16853 if (mips_opts
.mips16
)
16855 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16856 ignore_rest_of_line ();
16860 mips_mark_labels ();
16861 mips_assembling_insn
= TRUE
;
16864 if (mips_cpreturn_register
== -1)
16866 ex
.X_op
= O_constant
;
16867 ex
.X_add_symbol
= NULL
;
16868 ex
.X_op_symbol
= NULL
;
16869 ex
.X_add_number
= mips_cpreturn_offset
;
16871 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16874 move_register (mips_gp_register
, mips_cpreturn_register
);
16878 mips_assembling_insn
= FALSE
;
16879 demand_empty_rest_of_line ();
16882 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16883 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16884 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16885 debug information or MIPS16 TLS. */
16888 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16889 bfd_reloc_code_real_type rtype
)
16896 if (ex
.X_op
!= O_symbol
)
16898 as_bad (_("unsupported use of %s"), dirstr
);
16899 ignore_rest_of_line ();
16902 p
= frag_more (bytes
);
16903 md_number_to_chars (p
, 0, bytes
);
16904 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16905 demand_empty_rest_of_line ();
16906 mips_clear_insn_labels ();
16909 /* Handle .dtprelword. */
16912 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16914 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16917 /* Handle .dtpreldword. */
16920 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16922 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16925 /* Handle .tprelword. */
16928 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16930 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16933 /* Handle .tpreldword. */
16936 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16938 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16941 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16942 code. It sets the offset to use in gp_rel relocations. */
16945 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16947 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16948 We also need NewABI support. */
16949 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16955 mips_gprel_offset
= get_absolute_expression ();
16957 demand_empty_rest_of_line ();
16960 /* Handle the .gpword pseudo-op. This is used when generating PIC
16961 code. It generates a 32 bit GP relative reloc. */
16964 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16966 segment_info_type
*si
;
16967 struct insn_label_list
*l
;
16971 /* When not generating PIC code, this is treated as .word. */
16972 if (mips_pic
!= SVR4_PIC
)
16978 si
= seg_info (now_seg
);
16979 l
= si
->label_list
;
16980 mips_emit_delays ();
16982 mips_align (2, 0, l
);
16985 mips_clear_insn_labels ();
16987 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16989 as_bad (_("unsupported use of .gpword"));
16990 ignore_rest_of_line ();
16994 md_number_to_chars (p
, 0, 4);
16995 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16996 BFD_RELOC_GPREL32
);
16998 demand_empty_rest_of_line ();
17002 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17004 segment_info_type
*si
;
17005 struct insn_label_list
*l
;
17009 /* When not generating PIC code, this is treated as .dword. */
17010 if (mips_pic
!= SVR4_PIC
)
17016 si
= seg_info (now_seg
);
17017 l
= si
->label_list
;
17018 mips_emit_delays ();
17020 mips_align (3, 0, l
);
17023 mips_clear_insn_labels ();
17025 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17027 as_bad (_("unsupported use of .gpdword"));
17028 ignore_rest_of_line ();
17032 md_number_to_chars (p
, 0, 8);
17033 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17034 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17036 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17037 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17038 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17040 demand_empty_rest_of_line ();
17043 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17044 tables. It generates a R_MIPS_EH reloc. */
17047 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17052 mips_emit_delays ();
17055 mips_clear_insn_labels ();
17057 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17059 as_bad (_("unsupported use of .ehword"));
17060 ignore_rest_of_line ();
17064 md_number_to_chars (p
, 0, 4);
17065 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17066 BFD_RELOC_32_PCREL
);
17068 demand_empty_rest_of_line ();
17071 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17072 tables in SVR4 PIC code. */
17075 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17079 file_mips_check_options ();
17081 /* This is ignored when not generating SVR4 PIC code. */
17082 if (mips_pic
!= SVR4_PIC
)
17088 mips_mark_labels ();
17089 mips_assembling_insn
= TRUE
;
17091 /* Add $gp to the register named as an argument. */
17093 reg
= tc_get_register (0);
17094 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17097 mips_assembling_insn
= FALSE
;
17098 demand_empty_rest_of_line ();
17101 /* Handle the .insn pseudo-op. This marks instruction labels in
17102 mips16/micromips mode. This permits the linker to handle them specially,
17103 such as generating jalx instructions when needed. We also make
17104 them odd for the duration of the assembly, in order to generate the
17105 right sort of code. We will make them even in the adjust_symtab
17106 routine, while leaving them marked. This is convenient for the
17107 debugger and the disassembler. The linker knows to make them odd
17111 s_insn (int ignore ATTRIBUTE_UNUSED
)
17113 file_mips_check_options ();
17114 file_ase_mips16
|= mips_opts
.mips16
;
17115 file_ase_micromips
|= mips_opts
.micromips
;
17117 mips_mark_labels ();
17119 demand_empty_rest_of_line ();
17122 /* Handle the .nan pseudo-op. */
17125 s_nan (int ignore ATTRIBUTE_UNUSED
)
17127 static const char str_legacy
[] = "legacy";
17128 static const char str_2008
[] = "2008";
17131 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17133 if (i
== sizeof (str_2008
) - 1
17134 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17136 else if (i
== sizeof (str_legacy
) - 1
17137 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17139 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17142 as_bad (_("`%s' does not support legacy NaN"),
17143 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17146 as_bad (_("bad .nan directive"));
17148 input_line_pointer
+= i
;
17149 demand_empty_rest_of_line ();
17152 /* Handle a .stab[snd] directive. Ideally these directives would be
17153 implemented in a transparent way, so that removing them would not
17154 have any effect on the generated instructions. However, s_stab
17155 internally changes the section, so in practice we need to decide
17156 now whether the preceding label marks compressed code. We do not
17157 support changing the compression mode of a label after a .stab*
17158 directive, such as in:
17164 so the current mode wins. */
17167 s_mips_stab (int type
)
17169 file_mips_check_options ();
17170 mips_mark_labels ();
17174 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17177 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17184 c
= get_symbol_name (&name
);
17185 symbolP
= symbol_find_or_make (name
);
17186 S_SET_WEAK (symbolP
);
17187 *input_line_pointer
= c
;
17189 SKIP_WHITESPACE_AFTER_NAME ();
17191 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17193 if (S_IS_DEFINED (symbolP
))
17195 as_bad (_("ignoring attempt to redefine symbol %s"),
17196 S_GET_NAME (symbolP
));
17197 ignore_rest_of_line ();
17201 if (*input_line_pointer
== ',')
17203 ++input_line_pointer
;
17204 SKIP_WHITESPACE ();
17208 if (exp
.X_op
!= O_symbol
)
17210 as_bad (_("bad .weakext directive"));
17211 ignore_rest_of_line ();
17214 symbol_set_value_expression (symbolP
, &exp
);
17217 demand_empty_rest_of_line ();
17220 /* Parse a register string into a number. Called from the ECOFF code
17221 to parse .frame. The argument is non-zero if this is the frame
17222 register, so that we can record it in mips_frame_reg. */
17225 tc_get_register (int frame
)
17229 SKIP_WHITESPACE ();
17230 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17234 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17235 mips_frame_reg_valid
= 1;
17236 mips_cprestore_valid
= 0;
17242 md_section_align (asection
*seg
, valueT addr
)
17244 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17246 /* We don't need to align ELF sections to the full alignment.
17247 However, Irix 5 may prefer that we align them at least to a 16
17248 byte boundary. We don't bother to align the sections if we
17249 are targeted for an embedded system. */
17250 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17255 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17258 /* Utility routine, called from above as well. If called while the
17259 input file is still being read, it's only an approximation. (For
17260 example, a symbol may later become defined which appeared to be
17261 undefined earlier.) */
17264 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17269 if (g_switch_value
> 0)
17271 const char *symname
;
17274 /* Find out whether this symbol can be referenced off the $gp
17275 register. It can be if it is smaller than the -G size or if
17276 it is in the .sdata or .sbss section. Certain symbols can
17277 not be referenced off the $gp, although it appears as though
17279 symname
= S_GET_NAME (sym
);
17280 if (symname
!= (const char *) NULL
17281 && (strcmp (symname
, "eprol") == 0
17282 || strcmp (symname
, "etext") == 0
17283 || strcmp (symname
, "_gp") == 0
17284 || strcmp (symname
, "edata") == 0
17285 || strcmp (symname
, "_fbss") == 0
17286 || strcmp (symname
, "_fdata") == 0
17287 || strcmp (symname
, "_ftext") == 0
17288 || strcmp (symname
, "end") == 0
17289 || strcmp (symname
, "_gp_disp") == 0))
17291 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17293 #ifndef NO_ECOFF_DEBUGGING
17294 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17295 && (symbol_get_obj (sym
)->ecoff_extern_size
17296 <= g_switch_value
))
17298 /* We must defer this decision until after the whole
17299 file has been read, since there might be a .extern
17300 after the first use of this symbol. */
17301 || (before_relaxing
17302 #ifndef NO_ECOFF_DEBUGGING
17303 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17305 && S_GET_VALUE (sym
) == 0)
17306 || (S_GET_VALUE (sym
) != 0
17307 && S_GET_VALUE (sym
) <= g_switch_value
)))
17311 const char *segname
;
17313 segname
= segment_name (S_GET_SEGMENT (sym
));
17314 gas_assert (strcmp (segname
, ".lit8") != 0
17315 && strcmp (segname
, ".lit4") != 0);
17316 change
= (strcmp (segname
, ".sdata") != 0
17317 && strcmp (segname
, ".sbss") != 0
17318 && strncmp (segname
, ".sdata.", 7) != 0
17319 && strncmp (segname
, ".sbss.", 6) != 0
17320 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17321 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17326 /* We are not optimizing for the $gp register. */
17331 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17334 pic_need_relax (symbolS
*sym
)
17338 /* Handle the case of a symbol equated to another symbol. */
17339 while (symbol_equated_reloc_p (sym
))
17343 /* It's possible to get a loop here in a badly written program. */
17344 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17350 if (symbol_section_p (sym
))
17353 symsec
= S_GET_SEGMENT (sym
);
17355 /* This must duplicate the test in adjust_reloc_syms. */
17356 return (!bfd_is_und_section (symsec
)
17357 && !bfd_is_abs_section (symsec
)
17358 && !bfd_is_com_section (symsec
)
17359 /* A global or weak symbol is treated as external. */
17360 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17363 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17364 convert a section-relative value VAL to the equivalent PC-relative
17368 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17369 offsetT val
, long stretch
)
17374 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17376 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17378 /* If the relax_marker of the symbol fragment differs from the
17379 relax_marker of this fragment, we have not yet adjusted the
17380 symbol fragment fr_address. We want to add in STRETCH in
17381 order to get a better estimate of the address. This
17382 particularly matters because of the shift bits. */
17383 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17387 /* Adjust stretch for any alignment frag. Note that if have
17388 been expanding the earlier code, the symbol may be
17389 defined in what appears to be an earlier frag. FIXME:
17390 This doesn't handle the fr_subtype field, which specifies
17391 a maximum number of bytes to skip when doing an
17393 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17395 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17398 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17400 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17409 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17411 /* The base address rules are complicated. The base address of
17412 a branch is the following instruction. The base address of a
17413 PC relative load or add is the instruction itself, but if it
17414 is in a delay slot (in which case it can not be extended) use
17415 the address of the instruction whose delay slot it is in. */
17416 if (pcrel_op
->include_isa_bit
)
17420 /* If we are currently assuming that this frag should be
17421 extended, then the current address is two bytes higher. */
17422 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17425 /* Ignore the low bit in the target, since it will be set
17426 for a text label. */
17429 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17431 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17434 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17439 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17440 extended opcode. SEC is the section the frag is in. */
17443 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17445 const struct mips_int_operand
*operand
;
17450 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17452 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17455 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17456 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17457 operand
= mips16_immed_operand (type
, FALSE
);
17458 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17459 || (operand
->root
.type
== OP_PCREL
17461 : !bfd_is_abs_section (symsec
)))
17464 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17466 if (operand
->root
.type
== OP_PCREL
)
17468 const struct mips_pcrel_operand
*pcrel_op
;
17471 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17474 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17475 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17477 /* If any of the shifted bits are set, we must use an extended
17478 opcode. If the address depends on the size of this
17479 instruction, this can lead to a loop, so we arrange to always
17480 use an extended opcode. */
17481 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17483 fragp
->fr_subtype
=
17484 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17488 /* If we are about to mark a frag as extended because the value
17489 is precisely the next value above maxtiny, then there is a
17490 chance of an infinite loop as in the following code:
17495 In this case when the la is extended, foo is 0x3fc bytes
17496 away, so the la can be shrunk, but then foo is 0x400 away, so
17497 the la must be extended. To avoid this loop, we mark the
17498 frag as extended if it was small, and is about to become
17499 extended with the next value above maxtiny. */
17500 maxtiny
= mips_int_operand_max (operand
);
17501 if (val
== maxtiny
+ (1 << operand
->shift
)
17502 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17504 fragp
->fr_subtype
=
17505 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17510 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17513 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17514 macro expansion. SEC is the section the frag is in. We only
17515 support PC-relative instructions (LA, DLA, LW, LD) here, in
17516 non-PIC code using 32-bit addressing. */
17519 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17521 const struct mips_pcrel_operand
*pcrel_op
;
17522 const struct mips_int_operand
*operand
;
17527 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17529 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17531 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17534 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17540 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17541 if (bfd_is_abs_section (symsec
))
17543 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17545 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17548 operand
= mips16_immed_operand (type
, TRUE
);
17549 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17550 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17551 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17553 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17560 /* Compute the length of a branch sequence, and adjust the
17561 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17562 worst-case length is computed, with UPDATE being used to indicate
17563 whether an unconditional (-1), branch-likely (+1) or regular (0)
17564 branch is to be computed. */
17566 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17568 bfd_boolean toofar
;
17572 && S_IS_DEFINED (fragp
->fr_symbol
)
17573 && !S_IS_WEAK (fragp
->fr_symbol
)
17574 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17579 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17581 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17585 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17588 /* If the symbol is not defined or it's in a different segment,
17589 we emit the long sequence. */
17592 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17594 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17595 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17596 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17597 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17598 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17604 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17607 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17609 /* Additional space for PIC loading of target address. */
17611 if (mips_opts
.isa
== ISA_MIPS1
)
17612 /* Additional space for $at-stabilizing nop. */
17616 /* If branch is conditional. */
17617 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17624 /* Get a FRAG's branch instruction delay slot size, either from the
17625 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17626 or SHORT_INSN_SIZE otherwise. */
17629 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17631 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17634 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17636 return short_insn_size
;
17639 /* Compute the length of a branch sequence, and adjust the
17640 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17641 worst-case length is computed, with UPDATE being used to indicate
17642 whether an unconditional (-1), or regular (0) branch is to be
17646 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17648 bfd_boolean insn32
= TRUE
;
17649 bfd_boolean nods
= TRUE
;
17650 bfd_boolean pic
= TRUE
;
17651 bfd_boolean al
= TRUE
;
17652 int short_insn_size
;
17653 bfd_boolean toofar
;
17658 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17659 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17660 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
17661 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17663 short_insn_size
= insn32
? 4 : 2;
17666 && S_IS_DEFINED (fragp
->fr_symbol
)
17667 && !S_IS_WEAK (fragp
->fr_symbol
)
17668 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17673 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17674 /* Ignore the low bit in the target, since it will be set
17675 for a text label. */
17676 if ((val
& 1) != 0)
17679 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17683 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17686 /* If the symbol is not defined or it's in a different segment,
17687 we emit the long sequence. */
17690 if (fragp
&& update
17691 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17692 fragp
->fr_subtype
= (toofar
17693 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17694 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17699 bfd_boolean compact_known
= fragp
!= NULL
;
17700 bfd_boolean compact
= FALSE
;
17701 bfd_boolean uncond
;
17705 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17706 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17709 uncond
= update
< 0;
17711 /* If label is out of range, we turn branch <br>:
17713 <br> label # 4 bytes
17720 # compact && (!PIC || insn32)
17723 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
17724 length
+= short_insn_size
;
17726 /* If assembling PIC code, we further turn:
17732 lw/ld at, %got(label)(gp) # 4 bytes
17733 d/addiu at, %lo(label) # 4 bytes
17734 jr/c at # 2/4 bytes
17737 length
+= 4 + short_insn_size
;
17739 /* Add an extra nop if the jump has no compact form and we need
17740 to fill the delay slot. */
17741 if ((!pic
|| al
) && nods
)
17743 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17744 : short_insn_size
);
17746 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17748 <brneg> 0f # 4 bytes
17749 nop # 2/4 bytes if !compact
17752 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17756 /* Add an extra nop to fill the delay slot. */
17757 gas_assert (fragp
);
17758 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
17764 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17765 bit accordingly. */
17768 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17770 bfd_boolean toofar
;
17773 && S_IS_DEFINED (fragp
->fr_symbol
)
17774 && !S_IS_WEAK (fragp
->fr_symbol
)
17775 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17781 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17782 /* Ignore the low bit in the target, since it will be set
17783 for a text label. */
17784 if ((val
& 1) != 0)
17787 /* Assume this is a 2-byte branch. */
17788 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17790 /* We try to avoid the infinite loop by not adding 2 more bytes for
17795 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17797 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17798 else if (type
== 'E')
17799 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17804 /* If the symbol is not defined or it's in a different segment,
17805 we emit a normal 32-bit branch. */
17808 if (fragp
&& update
17809 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17811 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17812 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17820 /* Estimate the size of a frag before relaxing. Unless this is the
17821 mips16, we are not really relaxing here, and the final size is
17822 encoded in the subtype information. For the mips16, we have to
17823 decide whether we are using an extended opcode or not. */
17826 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17830 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17833 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17835 return fragp
->fr_var
;
17838 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17840 /* We don't want to modify the EXTENDED bit here; it might get us
17841 into infinite loops. We change it only in mips_relax_frag(). */
17842 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17843 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
17845 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
17848 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17852 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17853 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17854 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17855 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17856 fragp
->fr_var
= length
;
17861 if (mips_pic
== VXWORKS_PIC
)
17862 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17864 else if (RELAX_PIC (fragp
->fr_subtype
))
17865 change
= pic_need_relax (fragp
->fr_symbol
);
17867 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17871 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17872 return -RELAX_FIRST (fragp
->fr_subtype
);
17875 return -RELAX_SECOND (fragp
->fr_subtype
);
17878 /* This is called to see whether a reloc against a defined symbol
17879 should be converted into a reloc against a section. */
17882 mips_fix_adjustable (fixS
*fixp
)
17884 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17885 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17888 if (fixp
->fx_addsy
== NULL
)
17891 /* Allow relocs used for EH tables. */
17892 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17895 /* If symbol SYM is in a mergeable section, relocations of the form
17896 SYM + 0 can usually be made section-relative. The mergeable data
17897 is then identified by the section offset rather than by the symbol.
17899 However, if we're generating REL LO16 relocations, the offset is split
17900 between the LO16 and partnering high part relocation. The linker will
17901 need to recalculate the complete offset in order to correctly identify
17904 The linker has traditionally not looked for the partnering high part
17905 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17906 placed anywhere. Rather than break backwards compatibility by changing
17907 this, it seems better not to force the issue, and instead keep the
17908 original symbol. This will work with either linker behavior. */
17909 if ((lo16_reloc_p (fixp
->fx_r_type
)
17910 || reloc_needs_lo_p (fixp
->fx_r_type
))
17911 && HAVE_IN_PLACE_ADDENDS
17912 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17915 /* There is no place to store an in-place offset for JALR relocations. */
17916 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
17919 /* Likewise an in-range offset of limited PC-relative relocations may
17920 overflow the in-place relocatable field if recalculated against the
17921 start address of the symbol's containing section.
17923 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17924 section relative to allow linker relaxations to be performed later on. */
17925 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17926 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
17929 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17930 to a floating-point stub. The same is true for non-R_MIPS16_26
17931 relocations against MIPS16 functions; in this case, the stub becomes
17932 the function's canonical address.
17934 Floating-point stubs are stored in unique .mips16.call.* or
17935 .mips16.fn.* sections. If a stub T for function F is in section S,
17936 the first relocation in section S must be against F; this is how the
17937 linker determines the target function. All relocations that might
17938 resolve to T must also be against F. We therefore have the following
17939 restrictions, which are given in an intentionally-redundant way:
17941 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17944 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17945 if that stub might be used.
17947 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17950 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17951 that stub might be used.
17953 There is a further restriction:
17955 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17956 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17957 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17958 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17959 against MIPS16 or microMIPS symbols because we need to keep the
17960 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17961 detection and JAL or BAL to JALX instruction conversion in the
17964 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17965 against a MIPS16 symbol. We deal with (5) by additionally leaving
17966 alone any jump and branch relocations against a microMIPS symbol.
17968 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17969 relocation against some symbol R, no relocation against R may be
17970 reduced. (Note that this deals with (2) as well as (1) because
17971 relocations against global symbols will never be reduced on ELF
17972 targets.) This approach is a little simpler than trying to detect
17973 stub sections, and gives the "all or nothing" per-symbol consistency
17974 that we have for MIPS16 symbols. */
17975 if (fixp
->fx_subsy
== NULL
17976 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17977 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17978 && (jmp_reloc_p (fixp
->fx_r_type
)
17979 || b_reloc_p (fixp
->fx_r_type
)))
17980 || *symbol_get_tc (fixp
->fx_addsy
)))
17986 /* Translate internal representation of relocation info to BFD target
17990 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17992 static arelent
*retval
[4];
17994 bfd_reloc_code_real_type code
;
17996 memset (retval
, 0, sizeof(retval
));
17997 reloc
= retval
[0] = XCNEW (arelent
);
17998 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
17999 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18000 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18002 if (fixp
->fx_pcrel
)
18004 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18005 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18006 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18007 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18008 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18009 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18010 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18011 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18012 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18013 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18014 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18015 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18017 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18018 Relocations want only the symbol offset. */
18019 switch (fixp
->fx_r_type
)
18021 case BFD_RELOC_MIPS_18_PCREL_S3
:
18022 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18025 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18029 else if (HAVE_IN_PLACE_ADDENDS
18030 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18031 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18032 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18034 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18035 addend accordingly. */
18036 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18039 reloc
->addend
= fixp
->fx_addnumber
;
18041 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18042 entry to be used in the relocation's section offset. */
18043 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18045 reloc
->address
= reloc
->addend
;
18049 code
= fixp
->fx_r_type
;
18051 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18052 if (reloc
->howto
== NULL
)
18054 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18055 _("cannot represent %s relocation in this object file"
18057 bfd_get_reloc_code_name (code
));
18064 /* Relax a machine dependent frag. This returns the amount by which
18065 the current size of the frag should change. */
18068 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18070 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18072 offsetT old_var
= fragp
->fr_var
;
18074 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18076 return fragp
->fr_var
- old_var
;
18079 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18081 offsetT old_var
= fragp
->fr_var
;
18082 offsetT new_var
= 4;
18084 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18085 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18086 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18087 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18088 fragp
->fr_var
= new_var
;
18090 return new_var
- old_var
;
18093 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18096 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18098 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18100 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18101 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18103 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18105 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18111 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18113 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18115 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18116 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18117 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18119 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18121 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18129 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18131 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18133 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18134 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18135 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18139 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18140 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18147 /* Convert a machine dependent frag. */
18150 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18152 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18155 unsigned long insn
;
18158 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18159 insn
= read_insn (buf
);
18161 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18163 /* We generate a fixup instead of applying it right now
18164 because, if there are linker relaxations, we're going to
18165 need the relocations. */
18166 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18167 fragp
->fr_symbol
, fragp
->fr_offset
,
18168 TRUE
, BFD_RELOC_16_PCREL_S2
);
18169 fixp
->fx_file
= fragp
->fr_file
;
18170 fixp
->fx_line
= fragp
->fr_line
;
18172 buf
= write_insn (buf
, insn
);
18178 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18179 _("relaxed out-of-range branch into a jump"));
18181 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18184 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18186 /* Reverse the branch. */
18187 switch ((insn
>> 28) & 0xf)
18190 if ((insn
& 0xff000000) == 0x47000000
18191 || (insn
& 0xff600000) == 0x45600000)
18193 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18194 reversed by tweaking bit 23. */
18195 insn
^= 0x00800000;
18199 /* bc[0-3][tf]l? instructions can have the condition
18200 reversed by tweaking a single TF bit, and their
18201 opcodes all have 0x4???????. */
18202 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18203 insn
^= 0x00010000;
18208 /* bltz 0x04000000 bgez 0x04010000
18209 bltzal 0x04100000 bgezal 0x04110000 */
18210 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18211 insn
^= 0x00010000;
18215 /* beq 0x10000000 bne 0x14000000
18216 blez 0x18000000 bgtz 0x1c000000 */
18217 insn
^= 0x04000000;
18225 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18227 /* Clear the and-link bit. */
18228 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18230 /* bltzal 0x04100000 bgezal 0x04110000
18231 bltzall 0x04120000 bgezall 0x04130000 */
18232 insn
&= ~0x00100000;
18235 /* Branch over the branch (if the branch was likely) or the
18236 full jump (not likely case). Compute the offset from the
18237 current instruction to branch to. */
18238 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18242 /* How many bytes in instructions we've already emitted? */
18243 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18244 /* How many bytes in instructions from here to the end? */
18245 i
= fragp
->fr_var
- i
;
18247 /* Convert to instruction count. */
18249 /* Branch counts from the next instruction. */
18252 /* Branch over the jump. */
18253 buf
= write_insn (buf
, insn
);
18256 buf
= write_insn (buf
, 0);
18258 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18260 /* beql $0, $0, 2f */
18262 /* Compute the PC offset from the current instruction to
18263 the end of the variable frag. */
18264 /* How many bytes in instructions we've already emitted? */
18265 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18266 /* How many bytes in instructions from here to the end? */
18267 i
= fragp
->fr_var
- i
;
18268 /* Convert to instruction count. */
18270 /* Don't decrement i, because we want to branch over the
18274 buf
= write_insn (buf
, insn
);
18275 buf
= write_insn (buf
, 0);
18279 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18282 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18283 ? 0x0c000000 : 0x08000000);
18285 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18286 fragp
->fr_symbol
, fragp
->fr_offset
,
18287 FALSE
, BFD_RELOC_MIPS_JMP
);
18288 fixp
->fx_file
= fragp
->fr_file
;
18289 fixp
->fx_line
= fragp
->fr_line
;
18291 buf
= write_insn (buf
, insn
);
18295 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18297 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18298 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18299 insn
|= at
<< OP_SH_RT
;
18301 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18302 fragp
->fr_symbol
, fragp
->fr_offset
,
18303 FALSE
, BFD_RELOC_MIPS_GOT16
);
18304 fixp
->fx_file
= fragp
->fr_file
;
18305 fixp
->fx_line
= fragp
->fr_line
;
18307 buf
= write_insn (buf
, insn
);
18309 if (mips_opts
.isa
== ISA_MIPS1
)
18311 buf
= write_insn (buf
, 0);
18313 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18314 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18315 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18317 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18318 fragp
->fr_symbol
, fragp
->fr_offset
,
18319 FALSE
, BFD_RELOC_LO16
);
18320 fixp
->fx_file
= fragp
->fr_file
;
18321 fixp
->fx_line
= fragp
->fr_line
;
18323 buf
= write_insn (buf
, insn
);
18326 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18330 insn
|= at
<< OP_SH_RS
;
18332 buf
= write_insn (buf
, insn
);
18336 fragp
->fr_fix
+= fragp
->fr_var
;
18337 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18341 /* Relax microMIPS branches. */
18342 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18344 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18345 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18346 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18347 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18348 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18349 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18350 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18351 bfd_boolean short_ds
;
18352 unsigned long insn
;
18355 fragp
->fr_fix
+= fragp
->fr_var
;
18357 /* Handle 16-bit branches that fit or are forced to fit. */
18358 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18360 /* We generate a fixup instead of applying it right now,
18361 because if there is linker relaxation, we're going to
18362 need the relocations. */
18366 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18367 fragp
->fr_symbol
, fragp
->fr_offset
,
18368 TRUE
, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18371 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18372 fragp
->fr_symbol
, fragp
->fr_offset
,
18373 TRUE
, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18379 fixp
->fx_file
= fragp
->fr_file
;
18380 fixp
->fx_line
= fragp
->fr_line
;
18382 /* These relocations can have an addend that won't fit in
18384 fixp
->fx_no_overflow
= 1;
18389 /* Handle 32-bit branches that fit or are forced to fit. */
18390 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18391 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18393 /* We generate a fixup instead of applying it right now,
18394 because if there is linker relaxation, we're going to
18395 need the relocations. */
18396 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18397 fragp
->fr_symbol
, fragp
->fr_offset
,
18398 TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18399 fixp
->fx_file
= fragp
->fr_file
;
18400 fixp
->fx_line
= fragp
->fr_line
;
18404 insn
= read_compressed_insn (buf
, 4);
18409 /* Check the short-delay-slot bit. */
18410 if (!al
|| (insn
& 0x02000000) != 0)
18411 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18413 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18416 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18421 /* Relax 16-bit branches to 32-bit branches. */
18424 insn
= read_compressed_insn (buf
, 2);
18426 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18427 insn
= 0x94000000; /* beq */
18428 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18430 unsigned long regno
;
18432 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18433 regno
= micromips_to_32_reg_d_map
[regno
];
18434 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18435 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18440 /* Nothing else to do, just write it out. */
18441 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18442 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18444 buf
= write_compressed_insn (buf
, insn
, 4);
18446 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18447 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18452 insn
= read_compressed_insn (buf
, 4);
18454 /* Relax 32-bit branches to a sequence of instructions. */
18455 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18456 _("relaxed out-of-range branch into a jump"));
18458 /* Set the short-delay-slot bit. */
18459 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18461 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18465 /* Reverse the branch. */
18466 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18467 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18468 insn
^= 0x20000000;
18469 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18470 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18471 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18472 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18473 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18474 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18475 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18476 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18477 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18478 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18479 insn
^= 0x00400000;
18480 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18481 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18482 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18483 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18484 insn
^= 0x00200000;
18485 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18487 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18489 insn
^= 0x00800000;
18495 /* Clear the and-link and short-delay-slot bits. */
18496 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18498 /* bltzal 0x40200000 bgezal 0x40600000 */
18499 /* bltzals 0x42200000 bgezals 0x42600000 */
18500 insn
&= ~0x02200000;
18503 /* Make a label at the end for use with the branch. */
18504 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18505 micromips_label_inc ();
18506 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18509 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18510 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18511 fixp
->fx_file
= fragp
->fr_file
;
18512 fixp
->fx_line
= fragp
->fr_line
;
18514 /* Branch over the jump. */
18515 buf
= write_compressed_insn (buf
, insn
, 4);
18521 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18523 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18529 unsigned long jal
= (short_ds
|| nods
18530 ? 0x74000000 : 0xf4000000); /* jal/s */
18532 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18533 insn
= al
? jal
: 0xd4000000;
18535 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18536 fragp
->fr_symbol
, fragp
->fr_offset
,
18537 FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18538 fixp
->fx_file
= fragp
->fr_file
;
18539 fixp
->fx_line
= fragp
->fr_line
;
18541 buf
= write_compressed_insn (buf
, insn
, 4);
18543 if (compact
|| nods
)
18547 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18549 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18554 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18556 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18557 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18558 insn
|= at
<< MICROMIPSOP_SH_RT
;
18560 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18561 fragp
->fr_symbol
, fragp
->fr_offset
,
18562 FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18563 fixp
->fx_file
= fragp
->fr_file
;
18564 fixp
->fx_line
= fragp
->fr_line
;
18566 buf
= write_compressed_insn (buf
, insn
, 4);
18568 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18569 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18570 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18572 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18573 fragp
->fr_symbol
, fragp
->fr_offset
,
18574 FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18575 fixp
->fx_file
= fragp
->fr_file
;
18576 fixp
->fx_line
= fragp
->fr_line
;
18578 buf
= write_compressed_insn (buf
, insn
, 4);
18583 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18584 insn
|= at
<< MICROMIPSOP_SH_RS
;
18586 buf
= write_compressed_insn (buf
, insn
, 4);
18588 if (compact
|| nods
)
18590 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18594 /* jr/jrc/jalr/jalrs $at */
18595 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18596 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18598 insn
= al
? jalr
: jr
;
18599 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18601 buf
= write_compressed_insn (buf
, insn
, 2);
18606 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18608 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18613 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18617 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18620 const struct mips_int_operand
*operand
;
18623 unsigned int user_length
;
18624 bfd_boolean need_reloc
;
18625 unsigned long insn
;
18630 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18631 operand
= mips16_immed_operand (type
, FALSE
);
18633 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18634 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18635 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18637 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18638 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18639 || (operand
->root
.type
== OP_PCREL
&& !mac
18641 : !bfd_is_abs_section (symsec
)));
18643 if (operand
->root
.type
== OP_PCREL
&& !mac
)
18645 const struct mips_pcrel_operand
*pcrel_op
;
18647 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18649 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18651 if (!mips_ignore_branch_isa
18652 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18653 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18654 _("branch to a symbol in another ISA mode"));
18655 else if ((fragp
->fr_offset
& 0x1) != 0)
18656 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18657 _("branch to misaligned address (0x%lx)"),
18661 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
18663 /* Make sure the section winds up with the alignment we have
18665 if (operand
->shift
> 0)
18666 record_alignment (asec
, operand
->shift
);
18669 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18670 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18673 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18674 _("macro instruction expanded into multiple "
18675 "instructions in a branch delay slot"));
18677 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18678 _("extended instruction in a branch delay slot"));
18680 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
18681 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18682 _("macro instruction expanded into multiple "
18685 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18687 insn
= read_compressed_insn (buf
, 2);
18689 insn
|= MIPS16_EXTEND
;
18691 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18693 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18705 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
18706 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
18708 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
18714 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
18716 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18717 fragp
->fr_symbol
, fragp
->fr_offset
,
18718 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
18719 fixp
->fx_file
= fragp
->fr_file
;
18720 fixp
->fx_line
= fragp
->fr_line
;
18722 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
18723 fragp
->fr_symbol
, fragp
->fr_offset
,
18724 FALSE
, BFD_RELOC_MIPS16_LO16
);
18725 fixp
->fx_file
= fragp
->fr_file
;
18726 fixp
->fx_line
= fragp
->fr_line
;
18731 switch (insn
& 0xf800)
18733 case 0x0800: /* ADDIU */
18734 reg
= (insn
>> 8) & 0x7;
18735 op
= 0xf0004800 | (reg
<< 8);
18737 case 0xb000: /* LW */
18738 reg
= (insn
>> 8) & 0x7;
18739 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
18741 case 0xf800: /* I64 */
18742 reg
= (insn
>> 5) & 0x7;
18743 switch (insn
& 0x0700)
18745 case 0x0400: /* LD */
18746 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
18748 case 0x0600: /* DADDIU */
18749 op
= 0xf000fd00 | (reg
<< 5);
18759 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
18760 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
18761 buf
= write_compressed_insn (buf
, new, 4);
18764 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
18765 buf
= write_compressed_insn (buf
, new, 4);
18767 op
|= mips16_immed_extend (val
, 16);
18768 buf
= write_compressed_insn (buf
, op
, 4);
18770 fragp
->fr_fix
+= e2
? 8 : 12;
18774 unsigned int length
= ext
? 4 : 2;
18778 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
18785 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
18790 if (mac
|| reloc
== BFD_RELOC_NONE
)
18791 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18792 _("unsupported relocation"));
18795 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18796 fragp
->fr_symbol
, fragp
->fr_offset
,
18798 fixp
->fx_file
= fragp
->fr_file
;
18799 fixp
->fx_line
= fragp
->fr_line
;
18802 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18803 _("invalid unextended operand value"));
18806 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18807 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18809 gas_assert (mips16_opcode_length (insn
) == length
);
18810 write_compressed_insn (buf
, insn
, length
);
18811 fragp
->fr_fix
+= length
;
18816 relax_substateT subtype
= fragp
->fr_subtype
;
18817 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18818 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18822 first
= RELAX_FIRST (subtype
);
18823 second
= RELAX_SECOND (subtype
);
18824 fixp
= (fixS
*) fragp
->fr_opcode
;
18826 /* If the delay slot chosen does not match the size of the instruction,
18827 then emit a warning. */
18828 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18829 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18834 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18835 | RELAX_DELAY_SLOT_SIZE_FIRST
18836 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18837 msg
= macro_warning (s
);
18839 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18843 /* Possibly emit a warning if we've chosen the longer option. */
18844 if (use_second
== second_longer
)
18850 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18851 msg
= macro_warning (s
);
18853 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18857 /* Go through all the fixups for the first sequence. Disable them
18858 (by marking them as done) if we're going to use the second
18859 sequence instead. */
18861 && fixp
->fx_frag
== fragp
18862 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18864 if (subtype
& RELAX_USE_SECOND
)
18866 fixp
= fixp
->fx_next
;
18869 /* Go through the fixups for the second sequence. Disable them if
18870 we're going to use the first sequence, otherwise adjust their
18871 addresses to account for the relaxation. */
18872 while (fixp
&& fixp
->fx_frag
== fragp
)
18874 if (subtype
& RELAX_USE_SECOND
)
18875 fixp
->fx_where
-= first
;
18878 fixp
= fixp
->fx_next
;
18881 /* Now modify the frag contents. */
18882 if (subtype
& RELAX_USE_SECOND
)
18886 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18887 memmove (start
, start
+ first
, second
);
18888 fragp
->fr_fix
-= first
;
18891 fragp
->fr_fix
-= second
;
18895 /* This function is called after the relocs have been generated.
18896 We've been storing mips16 text labels as odd. Here we convert them
18897 back to even for the convenience of the debugger. */
18900 mips_frob_file_after_relocs (void)
18903 unsigned int count
, i
;
18905 syms
= bfd_get_outsymbols (stdoutput
);
18906 count
= bfd_get_symcount (stdoutput
);
18907 for (i
= 0; i
< count
; i
++, syms
++)
18908 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18909 && ((*syms
)->value
& 1) != 0)
18911 (*syms
)->value
&= ~1;
18912 /* If the symbol has an odd size, it was probably computed
18913 incorrectly, so adjust that as well. */
18914 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18915 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18919 /* This function is called whenever a label is defined, including fake
18920 labels instantiated off the dot special symbol. It is used when
18921 handling branch delays; if a branch has a label, we assume we cannot
18922 move it. This also bumps the value of the symbol by 1 in compressed
18926 mips_record_label (symbolS
*sym
)
18928 segment_info_type
*si
= seg_info (now_seg
);
18929 struct insn_label_list
*l
;
18931 if (free_insn_labels
== NULL
)
18932 l
= XNEW (struct insn_label_list
);
18935 l
= free_insn_labels
;
18936 free_insn_labels
= l
->next
;
18940 l
->next
= si
->label_list
;
18941 si
->label_list
= l
;
18944 /* This function is called as tc_frob_label() whenever a label is defined
18945 and adds a DWARF-2 record we only want for true labels. */
18948 mips_define_label (symbolS
*sym
)
18950 mips_record_label (sym
);
18951 dwarf2_emit_label (sym
);
18954 /* This function is called by tc_new_dot_label whenever a new dot symbol
18958 mips_add_dot_label (symbolS
*sym
)
18960 mips_record_label (sym
);
18961 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18962 mips_compressed_mark_label (sym
);
18965 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18966 static unsigned int
18967 mips_convert_ase_flags (int ase
)
18969 unsigned int ext_ases
= 0;
18972 ext_ases
|= AFL_ASE_DSP
;
18973 if (ase
& ASE_DSPR2
)
18974 ext_ases
|= AFL_ASE_DSPR2
;
18975 if (ase
& ASE_DSPR3
)
18976 ext_ases
|= AFL_ASE_DSPR3
;
18978 ext_ases
|= AFL_ASE_EVA
;
18980 ext_ases
|= AFL_ASE_MCU
;
18981 if (ase
& ASE_MDMX
)
18982 ext_ases
|= AFL_ASE_MDMX
;
18983 if (ase
& ASE_MIPS3D
)
18984 ext_ases
|= AFL_ASE_MIPS3D
;
18986 ext_ases
|= AFL_ASE_MT
;
18987 if (ase
& ASE_SMARTMIPS
)
18988 ext_ases
|= AFL_ASE_SMARTMIPS
;
18989 if (ase
& ASE_VIRT
)
18990 ext_ases
|= AFL_ASE_VIRT
;
18992 ext_ases
|= AFL_ASE_MSA
;
18994 ext_ases
|= AFL_ASE_XPA
;
18995 if (ase
& ASE_MIPS16E2
)
18996 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
18998 ext_ases
|= AFL_ASE_CRC
;
18999 if (ase
& ASE_GINV
)
19000 ext_ases
|= AFL_ASE_GINV
;
19004 /* Some special processing for a MIPS ELF file. */
19007 mips_elf_final_processing (void)
19010 Elf_Internal_ABIFlags_v0 flags
;
19014 switch (file_mips_opts
.isa
)
19017 flags
.isa_level
= 1;
19020 flags
.isa_level
= 2;
19023 flags
.isa_level
= 3;
19026 flags
.isa_level
= 4;
19029 flags
.isa_level
= 5;
19032 flags
.isa_level
= 32;
19036 flags
.isa_level
= 32;
19040 flags
.isa_level
= 32;
19044 flags
.isa_level
= 32;
19048 flags
.isa_level
= 32;
19052 flags
.isa_level
= 64;
19056 flags
.isa_level
= 64;
19060 flags
.isa_level
= 64;
19064 flags
.isa_level
= 64;
19068 flags
.isa_level
= 64;
19073 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19074 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19075 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19076 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19078 flags
.cpr2_size
= AFL_REG_NONE
;
19079 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19080 Tag_GNU_MIPS_ABI_FP
);
19081 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19082 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19083 if (file_ase_mips16
)
19084 flags
.ases
|= AFL_ASE_MIPS16
;
19085 if (file_ase_micromips
)
19086 flags
.ases
|= AFL_ASE_MICROMIPS
;
19088 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19089 || file_mips_opts
.fp
== 64)
19090 && file_mips_opts
.oddspreg
)
19091 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19094 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19095 ((Elf_External_ABIFlags_v0
*)
19098 /* Write out the register information. */
19099 if (mips_abi
!= N64_ABI
)
19103 s
.ri_gprmask
= mips_gprmask
;
19104 s
.ri_cprmask
[0] = mips_cprmask
[0];
19105 s
.ri_cprmask
[1] = mips_cprmask
[1];
19106 s
.ri_cprmask
[2] = mips_cprmask
[2];
19107 s
.ri_cprmask
[3] = mips_cprmask
[3];
19108 /* The gp_value field is set by the MIPS ELF backend. */
19110 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19111 ((Elf32_External_RegInfo
*)
19112 mips_regmask_frag
));
19116 Elf64_Internal_RegInfo s
;
19118 s
.ri_gprmask
= mips_gprmask
;
19120 s
.ri_cprmask
[0] = mips_cprmask
[0];
19121 s
.ri_cprmask
[1] = mips_cprmask
[1];
19122 s
.ri_cprmask
[2] = mips_cprmask
[2];
19123 s
.ri_cprmask
[3] = mips_cprmask
[3];
19124 /* The gp_value field is set by the MIPS ELF backend. */
19126 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19127 ((Elf64_External_RegInfo
*)
19128 mips_regmask_frag
));
19131 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19132 sort of BFD interface for this. */
19133 if (mips_any_noreorder
)
19134 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19135 if (mips_pic
!= NO_PIC
)
19137 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19138 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19141 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19143 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19144 defined at present; this might need to change in future. */
19145 if (file_ase_mips16
)
19146 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19147 if (file_ase_micromips
)
19148 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19149 if (file_mips_opts
.ase
& ASE_MDMX
)
19150 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19152 /* Set the MIPS ELF ABI flags. */
19153 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19154 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19155 else if (mips_abi
== O64_ABI
)
19156 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19157 else if (mips_abi
== EABI_ABI
)
19159 if (file_mips_opts
.gp
== 64)
19160 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19162 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19165 /* Nothing to do for N32_ABI or N64_ABI. */
19167 if (mips_32bitmode
)
19168 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19170 if (mips_nan2008
== 1)
19171 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19173 /* 32 bit code with 64 bit FP registers. */
19174 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19175 Tag_GNU_MIPS_ABI_FP
);
19176 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19177 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19180 typedef struct proc
{
19182 symbolS
*func_end_sym
;
19183 unsigned long reg_mask
;
19184 unsigned long reg_offset
;
19185 unsigned long fpreg_mask
;
19186 unsigned long fpreg_offset
;
19187 unsigned long frame_offset
;
19188 unsigned long frame_reg
;
19189 unsigned long pc_reg
;
19192 static procS cur_proc
;
19193 static procS
*cur_proc_ptr
;
19194 static int numprocs
;
19196 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19197 as "2", and a normal nop as "0". */
19199 #define NOP_OPCODE_MIPS 0
19200 #define NOP_OPCODE_MIPS16 1
19201 #define NOP_OPCODE_MICROMIPS 2
19204 mips_nop_opcode (void)
19206 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19207 return NOP_OPCODE_MICROMIPS
;
19208 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19209 return NOP_OPCODE_MIPS16
;
19211 return NOP_OPCODE_MIPS
;
19214 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19215 32-bit microMIPS NOPs here (if applicable). */
19218 mips_handle_align (fragS
*fragp
)
19222 int bytes
, size
, excess
;
19225 if (fragp
->fr_type
!= rs_align_code
)
19228 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19230 switch (nop_opcode
)
19232 case NOP_OPCODE_MICROMIPS
:
19233 opcode
= micromips_nop32_insn
.insn_opcode
;
19236 case NOP_OPCODE_MIPS16
:
19237 opcode
= mips16_nop_insn
.insn_opcode
;
19240 case NOP_OPCODE_MIPS
:
19242 opcode
= nop_insn
.insn_opcode
;
19247 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19248 excess
= bytes
% size
;
19250 /* Handle the leading part if we're not inserting a whole number of
19251 instructions, and make it the end of the fixed part of the frag.
19252 Try to fit in a short microMIPS NOP if applicable and possible,
19253 and use zeroes otherwise. */
19254 gas_assert (excess
< 4);
19255 fragp
->fr_fix
+= excess
;
19260 /* Fall through. */
19262 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19264 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19268 /* Fall through. */
19271 /* Fall through. */
19276 md_number_to_chars (p
, opcode
, size
);
19277 fragp
->fr_var
= size
;
19286 if (*input_line_pointer
== '-')
19288 ++input_line_pointer
;
19291 if (!ISDIGIT (*input_line_pointer
))
19292 as_bad (_("expected simple number"));
19293 if (input_line_pointer
[0] == '0')
19295 if (input_line_pointer
[1] == 'x')
19297 input_line_pointer
+= 2;
19298 while (ISXDIGIT (*input_line_pointer
))
19301 val
|= hex_value (*input_line_pointer
++);
19303 return negative
? -val
: val
;
19307 ++input_line_pointer
;
19308 while (ISDIGIT (*input_line_pointer
))
19311 val
|= *input_line_pointer
++ - '0';
19313 return negative
? -val
: val
;
19316 if (!ISDIGIT (*input_line_pointer
))
19318 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19319 *input_line_pointer
, *input_line_pointer
);
19320 as_warn (_("invalid number"));
19323 while (ISDIGIT (*input_line_pointer
))
19326 val
+= *input_line_pointer
++ - '0';
19328 return negative
? -val
: val
;
19331 /* The .file directive; just like the usual .file directive, but there
19332 is an initial number which is the ECOFF file index. In the non-ECOFF
19333 case .file implies DWARF-2. */
19336 s_mips_file (int x ATTRIBUTE_UNUSED
)
19338 static int first_file_directive
= 0;
19340 if (ECOFF_DEBUGGING
)
19349 filename
= dwarf2_directive_filename ();
19351 /* Versions of GCC up to 3.1 start files with a ".file"
19352 directive even for stabs output. Make sure that this
19353 ".file" is handled. Note that you need a version of GCC
19354 after 3.1 in order to support DWARF-2 on MIPS. */
19355 if (filename
!= NULL
&& ! first_file_directive
)
19357 (void) new_logical_line (filename
, -1);
19358 s_app_file_string (filename
, 0);
19360 first_file_directive
= 1;
19364 /* The .loc directive, implying DWARF-2. */
19367 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19369 if (!ECOFF_DEBUGGING
)
19370 dwarf2_directive_loc (0);
19373 /* The .end directive. */
19376 s_mips_end (int x ATTRIBUTE_UNUSED
)
19380 /* Following functions need their own .frame and .cprestore directives. */
19381 mips_frame_reg_valid
= 0;
19382 mips_cprestore_valid
= 0;
19384 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19387 demand_empty_rest_of_line ();
19392 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19393 as_warn (_(".end not in text section"));
19397 as_warn (_(".end directive without a preceding .ent directive"));
19398 demand_empty_rest_of_line ();
19404 gas_assert (S_GET_NAME (p
));
19405 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19406 as_warn (_(".end symbol does not match .ent symbol"));
19408 if (debug_type
== DEBUG_STABS
)
19409 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19413 as_warn (_(".end directive missing or unknown symbol"));
19415 /* Create an expression to calculate the size of the function. */
19416 if (p
&& cur_proc_ptr
)
19418 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19419 expressionS
*exp
= XNEW (expressionS
);
19422 exp
->X_op
= O_subtract
;
19423 exp
->X_add_symbol
= symbol_temp_new_now ();
19424 exp
->X_op_symbol
= p
;
19425 exp
->X_add_number
= 0;
19427 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19430 #ifdef md_flush_pending_output
19431 md_flush_pending_output ();
19434 /* Generate a .pdr section. */
19435 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19437 segT saved_seg
= now_seg
;
19438 subsegT saved_subseg
= now_subseg
;
19442 gas_assert (pdr_seg
);
19443 subseg_set (pdr_seg
, 0);
19445 /* Write the symbol. */
19446 exp
.X_op
= O_symbol
;
19447 exp
.X_add_symbol
= p
;
19448 exp
.X_add_number
= 0;
19449 emit_expr (&exp
, 4);
19451 fragp
= frag_more (7 * 4);
19453 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19454 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19455 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19456 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19457 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19458 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19459 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19461 subseg_set (saved_seg
, saved_subseg
);
19464 cur_proc_ptr
= NULL
;
19467 /* The .aent and .ent directives. */
19470 s_mips_ent (int aent
)
19474 symbolP
= get_symbol ();
19475 if (*input_line_pointer
== ',')
19476 ++input_line_pointer
;
19477 SKIP_WHITESPACE ();
19478 if (ISDIGIT (*input_line_pointer
)
19479 || *input_line_pointer
== '-')
19482 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19483 as_warn (_(".ent or .aent not in text section"));
19485 if (!aent
&& cur_proc_ptr
)
19486 as_warn (_("missing .end"));
19490 /* This function needs its own .frame and .cprestore directives. */
19491 mips_frame_reg_valid
= 0;
19492 mips_cprestore_valid
= 0;
19494 cur_proc_ptr
= &cur_proc
;
19495 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19497 cur_proc_ptr
->func_sym
= symbolP
;
19501 if (debug_type
== DEBUG_STABS
)
19502 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19503 S_GET_NAME (symbolP
));
19506 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19508 demand_empty_rest_of_line ();
19511 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19512 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19513 s_mips_frame is used so that we can set the PDR information correctly.
19514 We can't use the ecoff routines because they make reference to the ecoff
19515 symbol table (in the mdebug section). */
19518 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19520 if (ECOFF_DEBUGGING
)
19526 if (cur_proc_ptr
== (procS
*) NULL
)
19528 as_warn (_(".frame outside of .ent"));
19529 demand_empty_rest_of_line ();
19533 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19535 SKIP_WHITESPACE ();
19536 if (*input_line_pointer
++ != ','
19537 || get_absolute_expression_and_terminator (&val
) != ',')
19539 as_warn (_("bad .frame directive"));
19540 --input_line_pointer
;
19541 demand_empty_rest_of_line ();
19545 cur_proc_ptr
->frame_offset
= val
;
19546 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19548 demand_empty_rest_of_line ();
19552 /* The .fmask and .mask directives. If the mdebug section is present
19553 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19554 embedded targets, s_mips_mask is used so that we can set the PDR
19555 information correctly. We can't use the ecoff routines because they
19556 make reference to the ecoff symbol table (in the mdebug section). */
19559 s_mips_mask (int reg_type
)
19561 if (ECOFF_DEBUGGING
)
19562 s_ignore (reg_type
);
19567 if (cur_proc_ptr
== (procS
*) NULL
)
19569 as_warn (_(".mask/.fmask outside of .ent"));
19570 demand_empty_rest_of_line ();
19574 if (get_absolute_expression_and_terminator (&mask
) != ',')
19576 as_warn (_("bad .mask/.fmask directive"));
19577 --input_line_pointer
;
19578 demand_empty_rest_of_line ();
19582 off
= get_absolute_expression ();
19584 if (reg_type
== 'F')
19586 cur_proc_ptr
->fpreg_mask
= mask
;
19587 cur_proc_ptr
->fpreg_offset
= off
;
19591 cur_proc_ptr
->reg_mask
= mask
;
19592 cur_proc_ptr
->reg_offset
= off
;
19595 demand_empty_rest_of_line ();
19599 /* A table describing all the processors gas knows about. Names are
19600 matched in the order listed.
19602 To ease comparison, please keep this table in the same order as
19603 gcc's mips_cpu_info_table[]. */
19604 static const struct mips_cpu_info mips_cpu_info_table
[] =
19606 /* Entries for generic ISAs */
19607 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19608 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19609 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19610 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19611 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19612 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19613 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19614 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19615 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19616 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19617 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19618 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19619 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19620 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19621 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19624 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19625 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19626 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19629 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19632 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19633 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19634 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19635 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19636 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19637 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19638 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19639 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19640 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19641 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19642 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19643 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19644 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19645 /* ST Microelectronics Loongson 2E and 2F cores */
19646 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19647 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19650 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19651 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19652 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19653 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19654 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19655 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19656 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19657 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19658 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19659 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19660 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19661 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19662 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19663 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19664 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19667 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19668 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19669 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19670 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19672 /* MIPS 32 Release 2 */
19673 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19674 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19675 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19676 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19677 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19678 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19679 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19680 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19681 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19682 ISA_MIPS32R2
, CPU_MIPS32R2
},
19683 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19684 ISA_MIPS32R2
, CPU_MIPS32R2
},
19685 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19686 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19687 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19688 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19689 /* Deprecated forms of the above. */
19690 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19691 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19692 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19693 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19694 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19695 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19696 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19697 /* Deprecated forms of the above. */
19698 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19699 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19700 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19701 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19702 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19703 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19704 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19705 /* Deprecated forms of the above. */
19706 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19707 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19708 /* 34Kn is a 34kc without DSP. */
19709 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19710 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19711 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19712 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19713 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19714 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19715 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19716 /* Deprecated forms of the above. */
19717 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19718 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19719 /* 1004K cores are multiprocessor versions of the 34K. */
19720 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19721 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19722 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19723 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19724 /* interaptiv is the new name for 1004kf */
19725 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19726 { "interaptiv-mr2", 0,
19727 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
19728 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
19730 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19731 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19732 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19733 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19736 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19737 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19738 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19739 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19741 /* Broadcom SB-1 CPU core */
19742 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19743 /* Broadcom SB-1A CPU core */
19744 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19746 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
19748 /* MIPS 64 Release 2 */
19750 /* Cavium Networks Octeon CPU core */
19751 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19752 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19753 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19754 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
19757 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19760 XLP is mostly like XLR, with the prominent exception that it is
19761 MIPS64R2 rather than MIPS64. */
19762 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19764 /* MIPS 64 Release 6 */
19765 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19766 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19769 { NULL
, 0, 0, 0, 0 }
19773 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19774 with a final "000" replaced by "k". Ignore case.
19776 Note: this function is shared between GCC and GAS. */
19779 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19781 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19782 given
++, canonical
++;
19784 return ((*given
== 0 && *canonical
== 0)
19785 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19789 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19790 CPU name. We've traditionally allowed a lot of variation here.
19792 Note: this function is shared between GCC and GAS. */
19795 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19797 /* First see if the name matches exactly, or with a final "000"
19798 turned into "k". */
19799 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19802 /* If not, try comparing based on numerical designation alone.
19803 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19804 if (TOLOWER (*given
) == 'r')
19806 if (!ISDIGIT (*given
))
19809 /* Skip over some well-known prefixes in the canonical name,
19810 hoping to find a number there too. */
19811 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19813 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19815 else if (TOLOWER (canonical
[0]) == 'r')
19818 return mips_strict_matching_cpu_name_p (canonical
, given
);
19822 /* Parse an option that takes the name of a processor as its argument.
19823 OPTION is the name of the option and CPU_STRING is the argument.
19824 Return the corresponding processor enumeration if the CPU_STRING is
19825 recognized, otherwise report an error and return null.
19827 A similar function exists in GCC. */
19829 static const struct mips_cpu_info
*
19830 mips_parse_cpu (const char *option
, const char *cpu_string
)
19832 const struct mips_cpu_info
*p
;
19834 /* 'from-abi' selects the most compatible architecture for the given
19835 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19836 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19837 version. Look first at the -mgp options, if given, otherwise base
19838 the choice on MIPS_DEFAULT_64BIT.
19840 Treat NO_ABI like the EABIs. One reason to do this is that the
19841 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19842 architecture. This code picks MIPS I for 'mips' and MIPS III for
19843 'mips64', just as we did in the days before 'from-abi'. */
19844 if (strcasecmp (cpu_string
, "from-abi") == 0)
19846 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19847 return mips_cpu_info_from_isa (ISA_MIPS1
);
19849 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19850 return mips_cpu_info_from_isa (ISA_MIPS3
);
19852 if (file_mips_opts
.gp
>= 0)
19853 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
19854 ? ISA_MIPS1
: ISA_MIPS3
);
19856 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19861 /* 'default' has traditionally been a no-op. Probably not very useful. */
19862 if (strcasecmp (cpu_string
, "default") == 0)
19865 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19866 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19869 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
19873 /* Return the canonical processor information for ISA (a member of the
19874 ISA_MIPS* enumeration). */
19876 static const struct mips_cpu_info
*
19877 mips_cpu_info_from_isa (int isa
)
19881 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19882 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19883 && isa
== mips_cpu_info_table
[i
].isa
)
19884 return (&mips_cpu_info_table
[i
]);
19889 static const struct mips_cpu_info
*
19890 mips_cpu_info_from_arch (int arch
)
19894 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19895 if (arch
== mips_cpu_info_table
[i
].cpu
)
19896 return (&mips_cpu_info_table
[i
]);
19902 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19906 fprintf (stream
, "%24s", "");
19911 fprintf (stream
, ", ");
19915 if (*col_p
+ strlen (string
) > 72)
19917 fprintf (stream
, "\n%24s", "");
19921 fprintf (stream
, "%s", string
);
19922 *col_p
+= strlen (string
);
19928 md_show_usage (FILE *stream
)
19933 fprintf (stream
, _("\
19935 -EB generate big endian output\n\
19936 -EL generate little endian output\n\
19937 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19938 -G NUM allow referencing objects up to NUM bytes\n\
19939 implicitly with the gp register [default 8]\n"));
19940 fprintf (stream
, _("\
19941 -mips1 generate MIPS ISA I instructions\n\
19942 -mips2 generate MIPS ISA II instructions\n\
19943 -mips3 generate MIPS ISA III instructions\n\
19944 -mips4 generate MIPS ISA IV instructions\n\
19945 -mips5 generate MIPS ISA V instructions\n\
19946 -mips32 generate MIPS32 ISA instructions\n\
19947 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19948 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19949 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19950 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19951 -mips64 generate MIPS64 ISA instructions\n\
19952 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19953 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19954 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19955 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19956 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19960 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19961 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19962 show (stream
, "from-abi", &column
, &first
);
19963 fputc ('\n', stream
);
19965 fprintf (stream
, _("\
19966 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19967 -no-mCPU don't generate code specific to CPU.\n\
19968 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19972 show (stream
, "3900", &column
, &first
);
19973 show (stream
, "4010", &column
, &first
);
19974 show (stream
, "4100", &column
, &first
);
19975 show (stream
, "4650", &column
, &first
);
19976 fputc ('\n', stream
);
19978 fprintf (stream
, _("\
19979 -mips16 generate mips16 instructions\n\
19980 -no-mips16 do not generate mips16 instructions\n"));
19981 fprintf (stream
, _("\
19982 -mmips16e2 generate MIPS16e2 instructions\n\
19983 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
19984 fprintf (stream
, _("\
19985 -mmicromips generate microMIPS instructions\n\
19986 -mno-micromips do not generate microMIPS instructions\n"));
19987 fprintf (stream
, _("\
19988 -msmartmips generate smartmips instructions\n\
19989 -mno-smartmips do not generate smartmips instructions\n"));
19990 fprintf (stream
, _("\
19991 -mdsp generate DSP instructions\n\
19992 -mno-dsp do not generate DSP instructions\n"));
19993 fprintf (stream
, _("\
19994 -mdspr2 generate DSP R2 instructions\n\
19995 -mno-dspr2 do not generate DSP R2 instructions\n"));
19996 fprintf (stream
, _("\
19997 -mdspr3 generate DSP R3 instructions\n\
19998 -mno-dspr3 do not generate DSP R3 instructions\n"));
19999 fprintf (stream
, _("\
20000 -mmt generate MT instructions\n\
20001 -mno-mt do not generate MT instructions\n"));
20002 fprintf (stream
, _("\
20003 -mmcu generate MCU instructions\n\
20004 -mno-mcu do not generate MCU instructions\n"));
20005 fprintf (stream
, _("\
20006 -mmsa generate MSA instructions\n\
20007 -mno-msa do not generate MSA instructions\n"));
20008 fprintf (stream
, _("\
20009 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20010 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20011 fprintf (stream
, _("\
20012 -mvirt generate Virtualization instructions\n\
20013 -mno-virt do not generate Virtualization instructions\n"));
20014 fprintf (stream
, _("\
20015 -mcrc generate CRC instructions\n\
20016 -mno-crc do not generate CRC instructions\n"));
20017 fprintf (stream
, _("\
20018 -mginv generate Global INValidate (GINV) instructions\n\
20019 -mno-ginv do not generate Global INValidate instructions\n"));
20020 fprintf (stream
, _("\
20021 -minsn32 only generate 32-bit microMIPS instructions\n\
20022 -mno-insn32 generate all microMIPS instructions\n"));
20023 fprintf (stream
, _("\
20024 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20025 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20026 -mfix-vr4120 work around certain VR4120 errata\n\
20027 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20028 -mfix-24k insert a nop after ERET and DERET instructions\n\
20029 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20030 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20031 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20032 -msym32 assume all symbols have 32-bit values\n\
20033 -O0 do not remove unneeded NOPs, do not swap branches\n\
20034 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20035 -O2 remove unneeded NOPs and swap branches\n\
20036 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20037 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20038 fprintf (stream
, _("\
20039 -mhard-float allow floating-point instructions\n\
20040 -msoft-float do not allow floating-point instructions\n\
20041 -msingle-float only allow 32-bit floating-point operations\n\
20042 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20043 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20044 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20045 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20046 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20047 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20051 show (stream
, "legacy", &column
, &first
);
20052 show (stream
, "2008", &column
, &first
);
20054 fputc ('\n', stream
);
20056 fprintf (stream
, _("\
20057 -KPIC, -call_shared generate SVR4 position independent code\n\
20058 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20059 -mvxworks-pic generate VxWorks position independent code\n\
20060 -non_shared do not generate code that can operate with DSOs\n\
20061 -xgot assume a 32 bit GOT\n\
20062 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20063 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20064 position dependent (non shared) code\n\
20065 -mabi=ABI create ABI conformant object file for:\n"));
20069 show (stream
, "32", &column
, &first
);
20070 show (stream
, "o64", &column
, &first
);
20071 show (stream
, "n32", &column
, &first
);
20072 show (stream
, "64", &column
, &first
);
20073 show (stream
, "eabi", &column
, &first
);
20075 fputc ('\n', stream
);
20077 fprintf (stream
, _("\
20078 -32 create o32 ABI object file%s\n"),
20079 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20080 fprintf (stream
, _("\
20081 -n32 create n32 ABI object file%s\n"),
20082 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20083 fprintf (stream
, _("\
20084 -64 create 64 ABI object file%s\n"),
20085 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20090 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20092 if (HAVE_64BIT_SYMBOLS
)
20093 return dwarf2_format_64bit_irix
;
20095 return dwarf2_format_32bit
;
20100 mips_dwarf2_addr_size (void)
20102 if (HAVE_64BIT_OBJECTS
)
20108 /* Standard calling conventions leave the CFA at SP on entry. */
20110 mips_cfi_frame_initial_instructions (void)
20112 cfi_add_CFA_def_cfa_register (SP
);
20116 tc_mips_regname_to_dw2regnum (char *regname
)
20118 unsigned int regnum
= -1;
20121 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20127 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20128 Given a symbolic attribute NAME, return the proper integer value.
20129 Returns -1 if the attribute is not known. */
20132 mips_convert_symbolic_attribute (const char *name
)
20134 static const struct
20139 attribute_table
[] =
20141 #define T(tag) {#tag, tag}
20142 T (Tag_GNU_MIPS_ABI_FP
),
20143 T (Tag_GNU_MIPS_ABI_MSA
),
20151 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20152 if (streq (name
, attribute_table
[i
].name
))
20153 return attribute_table
[i
].tag
;
20161 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20163 mips_emit_delays ();
20165 as_warn (_("missing .end at end of assembly"));
20167 /* Just in case no code was emitted, do the consistency check. */
20168 file_mips_check_options ();
20170 /* Set a floating-point ABI if the user did not. */
20171 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20173 /* Perform consistency checks on the floating-point ABI. */
20174 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20175 Tag_GNU_MIPS_ABI_FP
);
20176 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20177 check_fpabi (fpabi
);
20181 /* Soft-float gets precedence over single-float, the two options should
20182 not be used together so this should not matter. */
20183 if (file_mips_opts
.soft_float
== 1)
20184 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20185 /* Single-float gets precedence over all double_float cases. */
20186 else if (file_mips_opts
.single_float
== 1)
20187 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20190 switch (file_mips_opts
.fp
)
20193 if (file_mips_opts
.gp
== 32)
20194 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20197 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20200 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20201 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20202 else if (file_mips_opts
.gp
== 32)
20203 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20205 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20210 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20211 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20215 /* Returns the relocation type required for a particular CFI encoding. */
20217 bfd_reloc_code_real_type
20218 mips_cfi_reloc_for_encoding (int encoding
)
20220 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20221 return BFD_RELOC_32_PCREL
;
20222 else return BFD_RELOC_NONE
;