1 /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
25 #include "dw2gencfi.h"
26 #include "opcode/ppc.h"
30 #include "elf/ppc64.h"
31 #include "dwarf2dbg.h"
35 #include "coff/xcoff.h"
39 /* This is the assembler for the PowerPC or POWER (RS/6000) chips. */
41 /* Tell the main code what the endianness is. */
42 extern int target_big_endian
;
44 /* Whether or not, we've set target_big_endian. */
45 static int set_target_endian
= 0;
47 /* Whether to use user friendly register names. */
48 #ifndef TARGET_REG_NAMES_P
49 #define TARGET_REG_NAMES_P FALSE
52 /* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST,
55 /* #lo(value) denotes the least significant 16 bits of the indicated. */
56 #define PPC_LO(v) ((v) & 0xffff)
58 /* #hi(value) denotes bits 16 through 31 of the indicated value. */
59 #define PPC_HI(v) (((v) >> 16) & 0xffff)
61 /* #ha(value) denotes the high adjusted value: bits 16 through 31 of
62 the indicated value, compensating for #lo() being treated as a
64 #define PPC_HA(v) PPC_HI ((v) + 0x8000)
66 /* #higher(value) denotes bits 32 through 47 of the indicated value. */
67 #define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff)
69 /* #highera(value) denotes bits 32 through 47 of the indicated value,
70 compensating for #lo() being treated as a signed number. */
71 #define PPC_HIGHERA(v) PPC_HIGHER ((v) + 0x8000)
73 /* #highest(value) denotes bits 48 through 63 of the indicated value. */
74 #define PPC_HIGHEST(v) (((v) >> 24 >> 24) & 0xffff)
76 /* #highesta(value) denotes bits 48 through 63 of the indicated value,
77 compensating for #lo being treated as a signed number. */
78 #define PPC_HIGHESTA(v) PPC_HIGHEST ((v) + 0x8000)
80 #define SEX16(val) (((val) ^ 0x8000) - 0x8000)
82 /* For the time being on ppc64, don't report overflow on @h and @ha
83 applied to constants. */
84 #define REPORT_OVERFLOW_HI 0
86 static bfd_boolean reg_names_p
= TARGET_REG_NAMES_P
;
88 static void ppc_macro (char *, const struct powerpc_macro
*);
89 static void ppc_byte (int);
91 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
92 static void ppc_tc (int);
93 static void ppc_machine (int);
97 static void ppc_comm (int);
98 static void ppc_bb (int);
99 static void ppc_bc (int);
100 static void ppc_bf (int);
101 static void ppc_biei (int);
102 static void ppc_bs (int);
103 static void ppc_eb (int);
104 static void ppc_ec (int);
105 static void ppc_ef (int);
106 static void ppc_es (int);
107 static void ppc_csect (int);
108 static void ppc_dwsect (int);
109 static void ppc_change_csect (symbolS
*, offsetT
);
110 static void ppc_function (int);
111 static void ppc_extern (int);
112 static void ppc_lglobl (int);
113 static void ppc_ref (int);
114 static void ppc_section (int);
115 static void ppc_named_section (int);
116 static void ppc_stabx (int);
117 static void ppc_rename (int);
118 static void ppc_toc (int);
119 static void ppc_xcoff_cons (int);
120 static void ppc_vbyte (int);
124 static void ppc_elf_rdata (int);
125 static void ppc_elf_lcomm (int);
126 static void ppc_elf_localentry (int);
127 static void ppc_elf_abiversion (int);
128 static void ppc_elf_gnu_attribute (int);
131 /* Generic assembler global variables which must be defined by all
135 /* This string holds the chars that always start a comment. If the
136 pre-processor is disabled, these aren't very useful. The macro
137 tc_comment_chars points to this. We use this, rather than the
138 usual comment_chars, so that we can switch for Solaris conventions. */
139 static const char ppc_solaris_comment_chars
[] = "#!";
140 static const char ppc_eabi_comment_chars
[] = "#";
142 #ifdef TARGET_SOLARIS_COMMENT
143 const char *ppc_comment_chars
= ppc_solaris_comment_chars
;
145 const char *ppc_comment_chars
= ppc_eabi_comment_chars
;
148 const char comment_chars
[] = "#";
151 /* Characters which start a comment at the beginning of a line. */
152 const char line_comment_chars
[] = "#";
154 /* Characters which may be used to separate multiple commands on a
156 const char line_separator_chars
[] = ";";
158 /* Characters which are used to indicate an exponent in a floating
160 const char EXP_CHARS
[] = "eE";
162 /* Characters which mean that a number is a floating point constant,
164 const char FLT_CHARS
[] = "dD";
166 /* Anything that can start an operand needs to be mentioned here,
167 to stop the input scrubber eating whitespace. */
168 const char ppc_symbol_chars
[] = "%[";
170 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
171 int ppc_cie_data_alignment
;
173 /* The dwarf2 minimum instruction length. */
174 int ppc_dwarf2_line_min_insn_length
;
176 /* More than this number of nops in an alignment op gets a branch
178 unsigned long nop_limit
= 4;
180 /* The type of processor we are assembling for. This is one or more
181 of the PPC_OPCODE flags defined in opcode/ppc.h. */
182 ppc_cpu_t ppc_cpu
= 0;
183 ppc_cpu_t sticky
= 0;
185 /* Value for ELF e_flags EF_PPC64_ABI. */
186 unsigned int ppc_abiversion
= 0;
189 /* Flags set on encountering toc relocs. */
191 has_large_toc_reloc
= 1,
192 has_small_toc_reloc
= 2
196 /* Warn on emitting data to code sections. */
202 /* The target specific pseudo-ops which we support. */
204 const pseudo_typeS md_pseudo_table
[] =
206 /* Pseudo-ops which must be overridden. */
207 { "byte", ppc_byte
, 0 },
210 /* Pseudo-ops specific to the RS/6000 XCOFF format. Some of these
211 legitimately belong in the obj-*.c file. However, XCOFF is based
212 on COFF, and is only implemented for the RS/6000. We just use
213 obj-coff.c, and add what we need here. */
214 { "comm", ppc_comm
, 0 },
215 { "lcomm", ppc_comm
, 1 },
219 { "bi", ppc_biei
, 0 },
221 { "csect", ppc_csect
, 0 },
222 { "dwsect", ppc_dwsect
, 0 },
223 { "data", ppc_section
, 'd' },
227 { "ei", ppc_biei
, 1 },
229 { "extern", ppc_extern
, 0 },
230 { "function", ppc_function
, 0 },
231 { "lglobl", ppc_lglobl
, 0 },
232 { "ref", ppc_ref
, 0 },
233 { "rename", ppc_rename
, 0 },
234 { "section", ppc_named_section
, 0 },
235 { "stabx", ppc_stabx
, 0 },
236 { "text", ppc_section
, 't' },
237 { "toc", ppc_toc
, 0 },
238 { "long", ppc_xcoff_cons
, 2 },
239 { "llong", ppc_xcoff_cons
, 3 },
240 { "word", ppc_xcoff_cons
, 1 },
241 { "short", ppc_xcoff_cons
, 1 },
242 { "vbyte", ppc_vbyte
, 0 },
246 { "llong", cons
, 8 },
247 { "rdata", ppc_elf_rdata
, 0 },
248 { "rodata", ppc_elf_rdata
, 0 },
249 { "lcomm", ppc_elf_lcomm
, 0 },
250 { "localentry", ppc_elf_localentry
, 0 },
251 { "abiversion", ppc_elf_abiversion
, 0 },
252 { "gnu_attribute", ppc_elf_gnu_attribute
, 0},
255 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
257 { "machine", ppc_machine
, 0 },
264 /* Predefined register names if -mregnames (or default for Windows NT).
265 In general, there are lots of them, in an attempt to be compatible
266 with a number of other Windows NT assemblers. */
268 /* Structure to hold information about predefined registers. */
272 unsigned short value
;
273 unsigned short flags
;
276 /* List of registers that are pre-defined:
278 Each general register has predefined names of the form:
279 1. r<reg_num> which has the value <reg_num>.
280 2. r.<reg_num> which has the value <reg_num>.
282 Each floating point register has predefined names of the form:
283 1. f<reg_num> which has the value <reg_num>.
284 2. f.<reg_num> which has the value <reg_num>.
286 Each vector unit register has predefined names of the form:
287 1. v<reg_num> which has the value <reg_num>.
288 2. v.<reg_num> which has the value <reg_num>.
290 Each condition register has predefined names of the form:
291 1. cr<reg_num> which has the value <reg_num>.
292 2. cr.<reg_num> which has the value <reg_num>.
294 There are individual registers as well:
295 sp or r.sp has the value 1
296 rtoc or r.toc has the value 2
301 dsisr has the value 18
303 sdr1 has the value 25
304 srr0 has the value 26
305 srr1 has the value 27
307 The table is sorted. Suitable for searching by a binary search. */
309 static const struct pd_reg pre_defined_registers
[] =
311 /* VSX accumulators. */
312 { "a0", 0, PPC_OPERAND_ACC
},
313 { "a1", 1, PPC_OPERAND_ACC
},
314 { "a2", 2, PPC_OPERAND_ACC
},
315 { "a3", 3, PPC_OPERAND_ACC
},
316 { "a4", 4, PPC_OPERAND_ACC
},
317 { "a5", 5, PPC_OPERAND_ACC
},
318 { "a6", 6, PPC_OPERAND_ACC
},
319 { "a7", 7, PPC_OPERAND_ACC
},
321 /* Condition Registers */
322 { "cr.0", 0, PPC_OPERAND_CR_REG
},
323 { "cr.1", 1, PPC_OPERAND_CR_REG
},
324 { "cr.2", 2, PPC_OPERAND_CR_REG
},
325 { "cr.3", 3, PPC_OPERAND_CR_REG
},
326 { "cr.4", 4, PPC_OPERAND_CR_REG
},
327 { "cr.5", 5, PPC_OPERAND_CR_REG
},
328 { "cr.6", 6, PPC_OPERAND_CR_REG
},
329 { "cr.7", 7, PPC_OPERAND_CR_REG
},
331 { "cr0", 0, PPC_OPERAND_CR_REG
},
332 { "cr1", 1, PPC_OPERAND_CR_REG
},
333 { "cr2", 2, PPC_OPERAND_CR_REG
},
334 { "cr3", 3, PPC_OPERAND_CR_REG
},
335 { "cr4", 4, PPC_OPERAND_CR_REG
},
336 { "cr5", 5, PPC_OPERAND_CR_REG
},
337 { "cr6", 6, PPC_OPERAND_CR_REG
},
338 { "cr7", 7, PPC_OPERAND_CR_REG
},
340 { "ctr", 9, PPC_OPERAND_SPR
},
341 { "dar", 19, PPC_OPERAND_SPR
},
342 { "dec", 22, PPC_OPERAND_SPR
},
343 { "dsisr", 18, PPC_OPERAND_SPR
},
345 /* Floating point registers */
346 { "f.0", 0, PPC_OPERAND_FPR
},
347 { "f.1", 1, PPC_OPERAND_FPR
},
348 { "f.10", 10, PPC_OPERAND_FPR
},
349 { "f.11", 11, PPC_OPERAND_FPR
},
350 { "f.12", 12, PPC_OPERAND_FPR
},
351 { "f.13", 13, PPC_OPERAND_FPR
},
352 { "f.14", 14, PPC_OPERAND_FPR
},
353 { "f.15", 15, PPC_OPERAND_FPR
},
354 { "f.16", 16, PPC_OPERAND_FPR
},
355 { "f.17", 17, PPC_OPERAND_FPR
},
356 { "f.18", 18, PPC_OPERAND_FPR
},
357 { "f.19", 19, PPC_OPERAND_FPR
},
358 { "f.2", 2, PPC_OPERAND_FPR
},
359 { "f.20", 20, PPC_OPERAND_FPR
},
360 { "f.21", 21, PPC_OPERAND_FPR
},
361 { "f.22", 22, PPC_OPERAND_FPR
},
362 { "f.23", 23, PPC_OPERAND_FPR
},
363 { "f.24", 24, PPC_OPERAND_FPR
},
364 { "f.25", 25, PPC_OPERAND_FPR
},
365 { "f.26", 26, PPC_OPERAND_FPR
},
366 { "f.27", 27, PPC_OPERAND_FPR
},
367 { "f.28", 28, PPC_OPERAND_FPR
},
368 { "f.29", 29, PPC_OPERAND_FPR
},
369 { "f.3", 3, PPC_OPERAND_FPR
},
370 { "f.30", 30, PPC_OPERAND_FPR
},
371 { "f.31", 31, PPC_OPERAND_FPR
},
372 { "f.32", 32, PPC_OPERAND_VSR
},
373 { "f.33", 33, PPC_OPERAND_VSR
},
374 { "f.34", 34, PPC_OPERAND_VSR
},
375 { "f.35", 35, PPC_OPERAND_VSR
},
376 { "f.36", 36, PPC_OPERAND_VSR
},
377 { "f.37", 37, PPC_OPERAND_VSR
},
378 { "f.38", 38, PPC_OPERAND_VSR
},
379 { "f.39", 39, PPC_OPERAND_VSR
},
380 { "f.4", 4, PPC_OPERAND_FPR
},
381 { "f.40", 40, PPC_OPERAND_VSR
},
382 { "f.41", 41, PPC_OPERAND_VSR
},
383 { "f.42", 42, PPC_OPERAND_VSR
},
384 { "f.43", 43, PPC_OPERAND_VSR
},
385 { "f.44", 44, PPC_OPERAND_VSR
},
386 { "f.45", 45, PPC_OPERAND_VSR
},
387 { "f.46", 46, PPC_OPERAND_VSR
},
388 { "f.47", 47, PPC_OPERAND_VSR
},
389 { "f.48", 48, PPC_OPERAND_VSR
},
390 { "f.49", 49, PPC_OPERAND_VSR
},
391 { "f.5", 5, PPC_OPERAND_FPR
},
392 { "f.50", 50, PPC_OPERAND_VSR
},
393 { "f.51", 51, PPC_OPERAND_VSR
},
394 { "f.52", 52, PPC_OPERAND_VSR
},
395 { "f.53", 53, PPC_OPERAND_VSR
},
396 { "f.54", 54, PPC_OPERAND_VSR
},
397 { "f.55", 55, PPC_OPERAND_VSR
},
398 { "f.56", 56, PPC_OPERAND_VSR
},
399 { "f.57", 57, PPC_OPERAND_VSR
},
400 { "f.58", 58, PPC_OPERAND_VSR
},
401 { "f.59", 59, PPC_OPERAND_VSR
},
402 { "f.6", 6, PPC_OPERAND_FPR
},
403 { "f.60", 60, PPC_OPERAND_VSR
},
404 { "f.61", 61, PPC_OPERAND_VSR
},
405 { "f.62", 62, PPC_OPERAND_VSR
},
406 { "f.63", 63, PPC_OPERAND_VSR
},
407 { "f.7", 7, PPC_OPERAND_FPR
},
408 { "f.8", 8, PPC_OPERAND_FPR
},
409 { "f.9", 9, PPC_OPERAND_FPR
},
411 { "f0", 0, PPC_OPERAND_FPR
},
412 { "f1", 1, PPC_OPERAND_FPR
},
413 { "f10", 10, PPC_OPERAND_FPR
},
414 { "f11", 11, PPC_OPERAND_FPR
},
415 { "f12", 12, PPC_OPERAND_FPR
},
416 { "f13", 13, PPC_OPERAND_FPR
},
417 { "f14", 14, PPC_OPERAND_FPR
},
418 { "f15", 15, PPC_OPERAND_FPR
},
419 { "f16", 16, PPC_OPERAND_FPR
},
420 { "f17", 17, PPC_OPERAND_FPR
},
421 { "f18", 18, PPC_OPERAND_FPR
},
422 { "f19", 19, PPC_OPERAND_FPR
},
423 { "f2", 2, PPC_OPERAND_FPR
},
424 { "f20", 20, PPC_OPERAND_FPR
},
425 { "f21", 21, PPC_OPERAND_FPR
},
426 { "f22", 22, PPC_OPERAND_FPR
},
427 { "f23", 23, PPC_OPERAND_FPR
},
428 { "f24", 24, PPC_OPERAND_FPR
},
429 { "f25", 25, PPC_OPERAND_FPR
},
430 { "f26", 26, PPC_OPERAND_FPR
},
431 { "f27", 27, PPC_OPERAND_FPR
},
432 { "f28", 28, PPC_OPERAND_FPR
},
433 { "f29", 29, PPC_OPERAND_FPR
},
434 { "f3", 3, PPC_OPERAND_FPR
},
435 { "f30", 30, PPC_OPERAND_FPR
},
436 { "f31", 31, PPC_OPERAND_FPR
},
437 { "f32", 32, PPC_OPERAND_VSR
},
438 { "f33", 33, PPC_OPERAND_VSR
},
439 { "f34", 34, PPC_OPERAND_VSR
},
440 { "f35", 35, PPC_OPERAND_VSR
},
441 { "f36", 36, PPC_OPERAND_VSR
},
442 { "f37", 37, PPC_OPERAND_VSR
},
443 { "f38", 38, PPC_OPERAND_VSR
},
444 { "f39", 39, PPC_OPERAND_VSR
},
445 { "f4", 4, PPC_OPERAND_FPR
},
446 { "f40", 40, PPC_OPERAND_VSR
},
447 { "f41", 41, PPC_OPERAND_VSR
},
448 { "f42", 42, PPC_OPERAND_VSR
},
449 { "f43", 43, PPC_OPERAND_VSR
},
450 { "f44", 44, PPC_OPERAND_VSR
},
451 { "f45", 45, PPC_OPERAND_VSR
},
452 { "f46", 46, PPC_OPERAND_VSR
},
453 { "f47", 47, PPC_OPERAND_VSR
},
454 { "f48", 48, PPC_OPERAND_VSR
},
455 { "f49", 49, PPC_OPERAND_VSR
},
456 { "f5", 5, PPC_OPERAND_FPR
},
457 { "f50", 50, PPC_OPERAND_VSR
},
458 { "f51", 51, PPC_OPERAND_VSR
},
459 { "f52", 52, PPC_OPERAND_VSR
},
460 { "f53", 53, PPC_OPERAND_VSR
},
461 { "f54", 54, PPC_OPERAND_VSR
},
462 { "f55", 55, PPC_OPERAND_VSR
},
463 { "f56", 56, PPC_OPERAND_VSR
},
464 { "f57", 57, PPC_OPERAND_VSR
},
465 { "f58", 58, PPC_OPERAND_VSR
},
466 { "f59", 59, PPC_OPERAND_VSR
},
467 { "f6", 6, PPC_OPERAND_FPR
},
468 { "f60", 60, PPC_OPERAND_VSR
},
469 { "f61", 61, PPC_OPERAND_VSR
},
470 { "f62", 62, PPC_OPERAND_VSR
},
471 { "f63", 63, PPC_OPERAND_VSR
},
472 { "f7", 7, PPC_OPERAND_FPR
},
473 { "f8", 8, PPC_OPERAND_FPR
},
474 { "f9", 9, PPC_OPERAND_FPR
},
476 /* Quantization registers used with pair single instructions. */
477 { "gqr.0", 0, PPC_OPERAND_GQR
},
478 { "gqr.1", 1, PPC_OPERAND_GQR
},
479 { "gqr.2", 2, PPC_OPERAND_GQR
},
480 { "gqr.3", 3, PPC_OPERAND_GQR
},
481 { "gqr.4", 4, PPC_OPERAND_GQR
},
482 { "gqr.5", 5, PPC_OPERAND_GQR
},
483 { "gqr.6", 6, PPC_OPERAND_GQR
},
484 { "gqr.7", 7, PPC_OPERAND_GQR
},
485 { "gqr0", 0, PPC_OPERAND_GQR
},
486 { "gqr1", 1, PPC_OPERAND_GQR
},
487 { "gqr2", 2, PPC_OPERAND_GQR
},
488 { "gqr3", 3, PPC_OPERAND_GQR
},
489 { "gqr4", 4, PPC_OPERAND_GQR
},
490 { "gqr5", 5, PPC_OPERAND_GQR
},
491 { "gqr6", 6, PPC_OPERAND_GQR
},
492 { "gqr7", 7, PPC_OPERAND_GQR
},
494 { "lr", 8, PPC_OPERAND_SPR
},
496 /* General Purpose Registers */
497 { "r.0", 0, PPC_OPERAND_GPR
},
498 { "r.1", 1, PPC_OPERAND_GPR
},
499 { "r.10", 10, PPC_OPERAND_GPR
},
500 { "r.11", 11, PPC_OPERAND_GPR
},
501 { "r.12", 12, PPC_OPERAND_GPR
},
502 { "r.13", 13, PPC_OPERAND_GPR
},
503 { "r.14", 14, PPC_OPERAND_GPR
},
504 { "r.15", 15, PPC_OPERAND_GPR
},
505 { "r.16", 16, PPC_OPERAND_GPR
},
506 { "r.17", 17, PPC_OPERAND_GPR
},
507 { "r.18", 18, PPC_OPERAND_GPR
},
508 { "r.19", 19, PPC_OPERAND_GPR
},
509 { "r.2", 2, PPC_OPERAND_GPR
},
510 { "r.20", 20, PPC_OPERAND_GPR
},
511 { "r.21", 21, PPC_OPERAND_GPR
},
512 { "r.22", 22, PPC_OPERAND_GPR
},
513 { "r.23", 23, PPC_OPERAND_GPR
},
514 { "r.24", 24, PPC_OPERAND_GPR
},
515 { "r.25", 25, PPC_OPERAND_GPR
},
516 { "r.26", 26, PPC_OPERAND_GPR
},
517 { "r.27", 27, PPC_OPERAND_GPR
},
518 { "r.28", 28, PPC_OPERAND_GPR
},
519 { "r.29", 29, PPC_OPERAND_GPR
},
520 { "r.3", 3, PPC_OPERAND_GPR
},
521 { "r.30", 30, PPC_OPERAND_GPR
},
522 { "r.31", 31, PPC_OPERAND_GPR
},
523 { "r.4", 4, PPC_OPERAND_GPR
},
524 { "r.5", 5, PPC_OPERAND_GPR
},
525 { "r.6", 6, PPC_OPERAND_GPR
},
526 { "r.7", 7, PPC_OPERAND_GPR
},
527 { "r.8", 8, PPC_OPERAND_GPR
},
528 { "r.9", 9, PPC_OPERAND_GPR
},
530 { "r.sp", 1, PPC_OPERAND_GPR
},
532 { "r.toc", 2, PPC_OPERAND_GPR
},
534 { "r0", 0, PPC_OPERAND_GPR
},
535 { "r1", 1, PPC_OPERAND_GPR
},
536 { "r10", 10, PPC_OPERAND_GPR
},
537 { "r11", 11, PPC_OPERAND_GPR
},
538 { "r12", 12, PPC_OPERAND_GPR
},
539 { "r13", 13, PPC_OPERAND_GPR
},
540 { "r14", 14, PPC_OPERAND_GPR
},
541 { "r15", 15, PPC_OPERAND_GPR
},
542 { "r16", 16, PPC_OPERAND_GPR
},
543 { "r17", 17, PPC_OPERAND_GPR
},
544 { "r18", 18, PPC_OPERAND_GPR
},
545 { "r19", 19, PPC_OPERAND_GPR
},
546 { "r2", 2, PPC_OPERAND_GPR
},
547 { "r20", 20, PPC_OPERAND_GPR
},
548 { "r21", 21, PPC_OPERAND_GPR
},
549 { "r22", 22, PPC_OPERAND_GPR
},
550 { "r23", 23, PPC_OPERAND_GPR
},
551 { "r24", 24, PPC_OPERAND_GPR
},
552 { "r25", 25, PPC_OPERAND_GPR
},
553 { "r26", 26, PPC_OPERAND_GPR
},
554 { "r27", 27, PPC_OPERAND_GPR
},
555 { "r28", 28, PPC_OPERAND_GPR
},
556 { "r29", 29, PPC_OPERAND_GPR
},
557 { "r3", 3, PPC_OPERAND_GPR
},
558 { "r30", 30, PPC_OPERAND_GPR
},
559 { "r31", 31, PPC_OPERAND_GPR
},
560 { "r4", 4, PPC_OPERAND_GPR
},
561 { "r5", 5, PPC_OPERAND_GPR
},
562 { "r6", 6, PPC_OPERAND_GPR
},
563 { "r7", 7, PPC_OPERAND_GPR
},
564 { "r8", 8, PPC_OPERAND_GPR
},
565 { "r9", 9, PPC_OPERAND_GPR
},
567 { "rtoc", 2, PPC_OPERAND_GPR
},
569 { "sdr1", 25, PPC_OPERAND_SPR
},
571 { "sp", 1, PPC_OPERAND_GPR
},
573 { "srr0", 26, PPC_OPERAND_SPR
},
574 { "srr1", 27, PPC_OPERAND_SPR
},
576 /* Vector (Altivec/VMX) registers */
577 { "v.0", 0, PPC_OPERAND_VR
},
578 { "v.1", 1, PPC_OPERAND_VR
},
579 { "v.10", 10, PPC_OPERAND_VR
},
580 { "v.11", 11, PPC_OPERAND_VR
},
581 { "v.12", 12, PPC_OPERAND_VR
},
582 { "v.13", 13, PPC_OPERAND_VR
},
583 { "v.14", 14, PPC_OPERAND_VR
},
584 { "v.15", 15, PPC_OPERAND_VR
},
585 { "v.16", 16, PPC_OPERAND_VR
},
586 { "v.17", 17, PPC_OPERAND_VR
},
587 { "v.18", 18, PPC_OPERAND_VR
},
588 { "v.19", 19, PPC_OPERAND_VR
},
589 { "v.2", 2, PPC_OPERAND_VR
},
590 { "v.20", 20, PPC_OPERAND_VR
},
591 { "v.21", 21, PPC_OPERAND_VR
},
592 { "v.22", 22, PPC_OPERAND_VR
},
593 { "v.23", 23, PPC_OPERAND_VR
},
594 { "v.24", 24, PPC_OPERAND_VR
},
595 { "v.25", 25, PPC_OPERAND_VR
},
596 { "v.26", 26, PPC_OPERAND_VR
},
597 { "v.27", 27, PPC_OPERAND_VR
},
598 { "v.28", 28, PPC_OPERAND_VR
},
599 { "v.29", 29, PPC_OPERAND_VR
},
600 { "v.3", 3, PPC_OPERAND_VR
},
601 { "v.30", 30, PPC_OPERAND_VR
},
602 { "v.31", 31, PPC_OPERAND_VR
},
603 { "v.4", 4, PPC_OPERAND_VR
},
604 { "v.5", 5, PPC_OPERAND_VR
},
605 { "v.6", 6, PPC_OPERAND_VR
},
606 { "v.7", 7, PPC_OPERAND_VR
},
607 { "v.8", 8, PPC_OPERAND_VR
},
608 { "v.9", 9, PPC_OPERAND_VR
},
610 { "v0", 0, PPC_OPERAND_VR
},
611 { "v1", 1, PPC_OPERAND_VR
},
612 { "v10", 10, PPC_OPERAND_VR
},
613 { "v11", 11, PPC_OPERAND_VR
},
614 { "v12", 12, PPC_OPERAND_VR
},
615 { "v13", 13, PPC_OPERAND_VR
},
616 { "v14", 14, PPC_OPERAND_VR
},
617 { "v15", 15, PPC_OPERAND_VR
},
618 { "v16", 16, PPC_OPERAND_VR
},
619 { "v17", 17, PPC_OPERAND_VR
},
620 { "v18", 18, PPC_OPERAND_VR
},
621 { "v19", 19, PPC_OPERAND_VR
},
622 { "v2", 2, PPC_OPERAND_VR
},
623 { "v20", 20, PPC_OPERAND_VR
},
624 { "v21", 21, PPC_OPERAND_VR
},
625 { "v22", 22, PPC_OPERAND_VR
},
626 { "v23", 23, PPC_OPERAND_VR
},
627 { "v24", 24, PPC_OPERAND_VR
},
628 { "v25", 25, PPC_OPERAND_VR
},
629 { "v26", 26, PPC_OPERAND_VR
},
630 { "v27", 27, PPC_OPERAND_VR
},
631 { "v28", 28, PPC_OPERAND_VR
},
632 { "v29", 29, PPC_OPERAND_VR
},
633 { "v3", 3, PPC_OPERAND_VR
},
634 { "v30", 30, PPC_OPERAND_VR
},
635 { "v31", 31, PPC_OPERAND_VR
},
636 { "v4", 4, PPC_OPERAND_VR
},
637 { "v5", 5, PPC_OPERAND_VR
},
638 { "v6", 6, PPC_OPERAND_VR
},
639 { "v7", 7, PPC_OPERAND_VR
},
640 { "v8", 8, PPC_OPERAND_VR
},
641 { "v9", 9, PPC_OPERAND_VR
},
643 /* Vector Scalar (VSX) registers (ISA 2.06). */
644 { "vs.0", 0, PPC_OPERAND_VSR
},
645 { "vs.1", 1, PPC_OPERAND_VSR
},
646 { "vs.10", 10, PPC_OPERAND_VSR
},
647 { "vs.11", 11, PPC_OPERAND_VSR
},
648 { "vs.12", 12, PPC_OPERAND_VSR
},
649 { "vs.13", 13, PPC_OPERAND_VSR
},
650 { "vs.14", 14, PPC_OPERAND_VSR
},
651 { "vs.15", 15, PPC_OPERAND_VSR
},
652 { "vs.16", 16, PPC_OPERAND_VSR
},
653 { "vs.17", 17, PPC_OPERAND_VSR
},
654 { "vs.18", 18, PPC_OPERAND_VSR
},
655 { "vs.19", 19, PPC_OPERAND_VSR
},
656 { "vs.2", 2, PPC_OPERAND_VSR
},
657 { "vs.20", 20, PPC_OPERAND_VSR
},
658 { "vs.21", 21, PPC_OPERAND_VSR
},
659 { "vs.22", 22, PPC_OPERAND_VSR
},
660 { "vs.23", 23, PPC_OPERAND_VSR
},
661 { "vs.24", 24, PPC_OPERAND_VSR
},
662 { "vs.25", 25, PPC_OPERAND_VSR
},
663 { "vs.26", 26, PPC_OPERAND_VSR
},
664 { "vs.27", 27, PPC_OPERAND_VSR
},
665 { "vs.28", 28, PPC_OPERAND_VSR
},
666 { "vs.29", 29, PPC_OPERAND_VSR
},
667 { "vs.3", 3, PPC_OPERAND_VSR
},
668 { "vs.30", 30, PPC_OPERAND_VSR
},
669 { "vs.31", 31, PPC_OPERAND_VSR
},
670 { "vs.32", 32, PPC_OPERAND_VSR
},
671 { "vs.33", 33, PPC_OPERAND_VSR
},
672 { "vs.34", 34, PPC_OPERAND_VSR
},
673 { "vs.35", 35, PPC_OPERAND_VSR
},
674 { "vs.36", 36, PPC_OPERAND_VSR
},
675 { "vs.37", 37, PPC_OPERAND_VSR
},
676 { "vs.38", 38, PPC_OPERAND_VSR
},
677 { "vs.39", 39, PPC_OPERAND_VSR
},
678 { "vs.4", 4, PPC_OPERAND_VSR
},
679 { "vs.40", 40, PPC_OPERAND_VSR
},
680 { "vs.41", 41, PPC_OPERAND_VSR
},
681 { "vs.42", 42, PPC_OPERAND_VSR
},
682 { "vs.43", 43, PPC_OPERAND_VSR
},
683 { "vs.44", 44, PPC_OPERAND_VSR
},
684 { "vs.45", 45, PPC_OPERAND_VSR
},
685 { "vs.46", 46, PPC_OPERAND_VSR
},
686 { "vs.47", 47, PPC_OPERAND_VSR
},
687 { "vs.48", 48, PPC_OPERAND_VSR
},
688 { "vs.49", 49, PPC_OPERAND_VSR
},
689 { "vs.5", 5, PPC_OPERAND_VSR
},
690 { "vs.50", 50, PPC_OPERAND_VSR
},
691 { "vs.51", 51, PPC_OPERAND_VSR
},
692 { "vs.52", 52, PPC_OPERAND_VSR
},
693 { "vs.53", 53, PPC_OPERAND_VSR
},
694 { "vs.54", 54, PPC_OPERAND_VSR
},
695 { "vs.55", 55, PPC_OPERAND_VSR
},
696 { "vs.56", 56, PPC_OPERAND_VSR
},
697 { "vs.57", 57, PPC_OPERAND_VSR
},
698 { "vs.58", 58, PPC_OPERAND_VSR
},
699 { "vs.59", 59, PPC_OPERAND_VSR
},
700 { "vs.6", 6, PPC_OPERAND_VSR
},
701 { "vs.60", 60, PPC_OPERAND_VSR
},
702 { "vs.61", 61, PPC_OPERAND_VSR
},
703 { "vs.62", 62, PPC_OPERAND_VSR
},
704 { "vs.63", 63, PPC_OPERAND_VSR
},
705 { "vs.7", 7, PPC_OPERAND_VSR
},
706 { "vs.8", 8, PPC_OPERAND_VSR
},
707 { "vs.9", 9, PPC_OPERAND_VSR
},
709 { "vs0", 0, PPC_OPERAND_VSR
},
710 { "vs1", 1, PPC_OPERAND_VSR
},
711 { "vs10", 10, PPC_OPERAND_VSR
},
712 { "vs11", 11, PPC_OPERAND_VSR
},
713 { "vs12", 12, PPC_OPERAND_VSR
},
714 { "vs13", 13, PPC_OPERAND_VSR
},
715 { "vs14", 14, PPC_OPERAND_VSR
},
716 { "vs15", 15, PPC_OPERAND_VSR
},
717 { "vs16", 16, PPC_OPERAND_VSR
},
718 { "vs17", 17, PPC_OPERAND_VSR
},
719 { "vs18", 18, PPC_OPERAND_VSR
},
720 { "vs19", 19, PPC_OPERAND_VSR
},
721 { "vs2", 2, PPC_OPERAND_VSR
},
722 { "vs20", 20, PPC_OPERAND_VSR
},
723 { "vs21", 21, PPC_OPERAND_VSR
},
724 { "vs22", 22, PPC_OPERAND_VSR
},
725 { "vs23", 23, PPC_OPERAND_VSR
},
726 { "vs24", 24, PPC_OPERAND_VSR
},
727 { "vs25", 25, PPC_OPERAND_VSR
},
728 { "vs26", 26, PPC_OPERAND_VSR
},
729 { "vs27", 27, PPC_OPERAND_VSR
},
730 { "vs28", 28, PPC_OPERAND_VSR
},
731 { "vs29", 29, PPC_OPERAND_VSR
},
732 { "vs3", 3, PPC_OPERAND_VSR
},
733 { "vs30", 30, PPC_OPERAND_VSR
},
734 { "vs31", 31, PPC_OPERAND_VSR
},
735 { "vs32", 32, PPC_OPERAND_VSR
},
736 { "vs33", 33, PPC_OPERAND_VSR
},
737 { "vs34", 34, PPC_OPERAND_VSR
},
738 { "vs35", 35, PPC_OPERAND_VSR
},
739 { "vs36", 36, PPC_OPERAND_VSR
},
740 { "vs37", 37, PPC_OPERAND_VSR
},
741 { "vs38", 38, PPC_OPERAND_VSR
},
742 { "vs39", 39, PPC_OPERAND_VSR
},
743 { "vs4", 4, PPC_OPERAND_VSR
},
744 { "vs40", 40, PPC_OPERAND_VSR
},
745 { "vs41", 41, PPC_OPERAND_VSR
},
746 { "vs42", 42, PPC_OPERAND_VSR
},
747 { "vs43", 43, PPC_OPERAND_VSR
},
748 { "vs44", 44, PPC_OPERAND_VSR
},
749 { "vs45", 45, PPC_OPERAND_VSR
},
750 { "vs46", 46, PPC_OPERAND_VSR
},
751 { "vs47", 47, PPC_OPERAND_VSR
},
752 { "vs48", 48, PPC_OPERAND_VSR
},
753 { "vs49", 49, PPC_OPERAND_VSR
},
754 { "vs5", 5, PPC_OPERAND_VSR
},
755 { "vs50", 50, PPC_OPERAND_VSR
},
756 { "vs51", 51, PPC_OPERAND_VSR
},
757 { "vs52", 52, PPC_OPERAND_VSR
},
758 { "vs53", 53, PPC_OPERAND_VSR
},
759 { "vs54", 54, PPC_OPERAND_VSR
},
760 { "vs55", 55, PPC_OPERAND_VSR
},
761 { "vs56", 56, PPC_OPERAND_VSR
},
762 { "vs57", 57, PPC_OPERAND_VSR
},
763 { "vs58", 58, PPC_OPERAND_VSR
},
764 { "vs59", 59, PPC_OPERAND_VSR
},
765 { "vs6", 6, PPC_OPERAND_VSR
},
766 { "vs60", 60, PPC_OPERAND_VSR
},
767 { "vs61", 61, PPC_OPERAND_VSR
},
768 { "vs62", 62, PPC_OPERAND_VSR
},
769 { "vs63", 63, PPC_OPERAND_VSR
},
770 { "vs7", 7, PPC_OPERAND_VSR
},
771 { "vs8", 8, PPC_OPERAND_VSR
},
772 { "vs9", 9, PPC_OPERAND_VSR
},
774 { "xer", 1, PPC_OPERAND_SPR
}
777 #define REG_NAME_CNT (sizeof (pre_defined_registers) / sizeof (struct pd_reg))
779 /* Given NAME, find the register number associated with that name, return
780 the integer value associated with the given name or -1 on failure. */
782 static const struct pd_reg
*
783 reg_name_search (const struct pd_reg
*regs
, int regcount
, const char *name
)
785 int middle
, low
, high
;
793 middle
= (low
+ high
) / 2;
794 cmp
= strcasecmp (name
, regs
[middle
].name
);
800 return ®s
[middle
];
808 * Summary of register_name.
810 * in: Input_line_pointer points to 1st char of operand.
812 * out: A expressionS.
813 * The operand may have been a register: in this case, X_op == O_register,
814 * X_add_number is set to the register number, and truth is returned.
815 * Input_line_pointer->(next non-blank) char after operand, or is in its
820 register_name (expressionS
*expressionP
)
822 const struct pd_reg
*reg
;
827 /* Find the spelling of the operand. */
828 start
= name
= input_line_pointer
;
829 if (name
[0] == '%' && ISALPHA (name
[1]))
830 name
= ++input_line_pointer
;
832 else if (!reg_names_p
|| !ISALPHA (name
[0]))
835 c
= get_symbol_name (&name
);
836 reg
= reg_name_search (pre_defined_registers
, REG_NAME_CNT
, name
);
838 /* Put back the delimiting char. */
839 *input_line_pointer
= c
;
841 /* Look to see if it's in the register table. */
844 expressionP
->X_op
= O_register
;
845 expressionP
->X_add_number
= reg
->value
;
846 expressionP
->X_md
= reg
->flags
;
848 /* Make the rest nice. */
849 expressionP
->X_add_symbol
= NULL
;
850 expressionP
->X_op_symbol
= NULL
;
854 /* Reset the line as if we had not done anything. */
855 input_line_pointer
= start
;
859 /* This function is called for each symbol seen in an expression. It
860 handles the special parsing which PowerPC assemblers are supposed
861 to use for condition codes. */
863 /* Whether to do the special parsing. */
864 static bfd_boolean cr_operand
;
866 /* Names to recognize in a condition code. This table is sorted. */
867 static const struct pd_reg cr_names
[] =
869 { "cr0", 0, PPC_OPERAND_CR_REG
},
870 { "cr1", 1, PPC_OPERAND_CR_REG
},
871 { "cr2", 2, PPC_OPERAND_CR_REG
},
872 { "cr3", 3, PPC_OPERAND_CR_REG
},
873 { "cr4", 4, PPC_OPERAND_CR_REG
},
874 { "cr5", 5, PPC_OPERAND_CR_REG
},
875 { "cr6", 6, PPC_OPERAND_CR_REG
},
876 { "cr7", 7, PPC_OPERAND_CR_REG
},
877 { "eq", 2, PPC_OPERAND_CR_BIT
},
878 { "gt", 1, PPC_OPERAND_CR_BIT
},
879 { "lt", 0, PPC_OPERAND_CR_BIT
},
880 { "so", 3, PPC_OPERAND_CR_BIT
},
881 { "un", 3, PPC_OPERAND_CR_BIT
}
884 /* Parsing function. This returns non-zero if it recognized an
888 ppc_parse_name (const char *name
, expressionS
*exp
)
890 const struct pd_reg
*reg
;
897 reg
= reg_name_search (cr_names
, sizeof cr_names
/ sizeof cr_names
[0],
902 exp
->X_op
= O_register
;
903 exp
->X_add_number
= reg
->value
;
904 exp
->X_md
= reg
->flags
;
909 /* Propagate X_md and check register expressions. This is to support
910 condition codes like 4*cr5+eq. */
913 ppc_optimize_expr (expressionS
*left
, operatorT op
, expressionS
*right
)
915 /* Accept 4*cr<n> and cr<n>*4. */
917 && ((right
->X_op
== O_register
918 && right
->X_md
== PPC_OPERAND_CR_REG
919 && left
->X_op
== O_constant
920 && left
->X_add_number
== 4)
921 || (left
->X_op
== O_register
922 && left
->X_md
== PPC_OPERAND_CR_REG
923 && right
->X_op
== O_constant
924 && right
->X_add_number
== 4)))
926 left
->X_op
= O_register
;
927 left
->X_md
= PPC_OPERAND_CR_REG
| PPC_OPERAND_CR_BIT
;
928 left
->X_add_number
*= right
->X_add_number
;
932 /* Accept the above plus <cr bit>, and <cr bit> plus the above. */
933 if (right
->X_op
== O_register
934 && left
->X_op
== O_register
936 && ((right
->X_md
== PPC_OPERAND_CR_BIT
937 && left
->X_md
== (PPC_OPERAND_CR_REG
| PPC_OPERAND_CR_BIT
))
938 || (right
->X_md
== (PPC_OPERAND_CR_REG
| PPC_OPERAND_CR_BIT
)
939 && left
->X_md
== PPC_OPERAND_CR_BIT
)))
941 left
->X_md
= PPC_OPERAND_CR_BIT
;
942 right
->X_op
= O_constant
;
946 /* Accept reg +/- constant. */
947 if (left
->X_op
== O_register
948 && !((op
== O_add
|| op
== O_subtract
) && right
->X_op
== O_constant
))
949 as_warn (_("invalid register expression"));
951 /* Accept constant + reg. */
952 if (right
->X_op
== O_register
)
954 if (op
== O_add
&& left
->X_op
== O_constant
)
955 left
->X_md
= right
->X_md
;
957 as_warn (_("invalid register expression"));
963 /* Local variables. */
965 /* Whether to target xcoff64/elf64. */
966 static unsigned int ppc_obj64
= BFD_DEFAULT_TARGET_SIZE
== 64;
968 /* Opcode hash table. */
969 static struct hash_control
*ppc_hash
;
971 /* Macro hash table. */
972 static struct hash_control
*ppc_macro_hash
;
975 /* What type of shared library support to use. */
976 static enum { SHLIB_NONE
, SHLIB_PIC
, SHLIB_MRELOCATABLE
} shlib
= SHLIB_NONE
;
978 /* Flags to set in the elf header. */
979 static flagword ppc_flags
= 0;
981 /* Whether this is Solaris or not. */
982 #ifdef TARGET_SOLARIS_COMMENT
983 #define SOLARIS_P TRUE
985 #define SOLARIS_P FALSE
988 static bfd_boolean msolaris
= SOLARIS_P
;
993 /* The RS/6000 assembler uses the .csect pseudo-op to generate code
994 using a bunch of different sections. These assembler sections,
995 however, are all encompassed within the .text or .data sections of
996 the final output file. We handle this by using different
997 subsegments within these main segments. */
999 /* Next subsegment to allocate within the .text segment. */
1000 static subsegT ppc_text_subsegment
= 2;
1002 /* Linked list of csects in the text section. */
1003 static symbolS
*ppc_text_csects
;
1005 /* Next subsegment to allocate within the .data segment. */
1006 static subsegT ppc_data_subsegment
= 2;
1008 /* Linked list of csects in the data section. */
1009 static symbolS
*ppc_data_csects
;
1011 /* The current csect. */
1012 static symbolS
*ppc_current_csect
;
1014 /* The RS/6000 assembler uses a TOC which holds addresses of functions
1015 and variables. Symbols are put in the TOC with the .tc pseudo-op.
1016 A special relocation is used when accessing TOC entries. We handle
1017 the TOC as a subsegment within the .data segment. We set it up if
1018 we see a .toc pseudo-op, and save the csect symbol here. */
1019 static symbolS
*ppc_toc_csect
;
1021 /* The first frag in the TOC subsegment. */
1022 static fragS
*ppc_toc_frag
;
1024 /* The first frag in the first subsegment after the TOC in the .data
1025 segment. NULL if there are no subsegments after the TOC. */
1026 static fragS
*ppc_after_toc_frag
;
1028 /* The current static block. */
1029 static symbolS
*ppc_current_block
;
1031 /* The COFF debugging section; set by md_begin. This is not the
1032 .debug section, but is instead the secret BFD section which will
1033 cause BFD to set the section number of a symbol to N_DEBUG. */
1034 static asection
*ppc_coff_debug_section
;
1036 /* Structure to set the length field of the dwarf sections. */
1037 struct dw_subsection
{
1038 /* Subsections are simply linked. */
1039 struct dw_subsection
*link
;
1041 /* The subsection number. */
1044 /* Expression to compute the length of the section. */
1045 expressionS end_exp
;
1048 static struct dw_section
{
1049 /* Corresponding section. */
1052 /* Simply linked list of subsections with a label. */
1053 struct dw_subsection
*list_subseg
;
1055 /* The anonymous subsection. */
1056 struct dw_subsection
*anon_subseg
;
1057 } dw_sections
[XCOFF_DWSECT_NBR_NAMES
];
1058 #endif /* OBJ_XCOFF */
1061 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE" */
1062 unsigned long *ppc_apuinfo_list
;
1063 unsigned int ppc_apuinfo_num
;
1064 unsigned int ppc_apuinfo_num_alloc
;
1065 #endif /* OBJ_ELF */
1068 const char *const md_shortopts
= "b:l:usm:K:VQ:";
1070 const char *const md_shortopts
= "um:";
1072 #define OPTION_NOPS (OPTION_MD_BASE + 0)
1073 const struct option md_longopts
[] = {
1074 {"nops", required_argument
, NULL
, OPTION_NOPS
},
1075 {"ppc476-workaround", no_argument
, &warn_476
, 1},
1076 {"no-ppc476-workaround", no_argument
, &warn_476
, 0},
1077 {NULL
, no_argument
, NULL
, 0}
1079 const size_t md_longopts_size
= sizeof (md_longopts
);
1082 md_parse_option (int c
, const char *arg
)
1089 /* -u means that any undefined symbols should be treated as
1090 external, which is the default for gas anyhow. */
1095 /* Solaris as takes -le (presumably for little endian). For completeness
1096 sake, recognize -be also. */
1097 if (strcmp (arg
, "e") == 0)
1099 target_big_endian
= 0;
1100 set_target_endian
= 1;
1101 if (ppc_cpu
& PPC_OPCODE_VLE
)
1102 as_bad (_("the use of -mvle requires big endian."));
1110 if (strcmp (arg
, "e") == 0)
1112 target_big_endian
= 1;
1113 set_target_endian
= 1;
1121 /* Recognize -K PIC. */
1122 if (strcmp (arg
, "PIC") == 0 || strcmp (arg
, "pic") == 0)
1125 ppc_flags
|= EF_PPC_RELOCATABLE_LIB
;
1133 /* a64 and a32 determine whether to use XCOFF64 or XCOFF32. */
1135 if (strcmp (arg
, "64") == 0)
1139 if (ppc_cpu
& PPC_OPCODE_VLE
)
1140 as_bad (_("the use of -mvle requires -a32."));
1142 as_fatal (_("%s unsupported"), "-a64");
1145 else if (strcmp (arg
, "32") == 0)
1152 new_cpu
= ppc_parse_cpu (ppc_cpu
, &sticky
, arg
);
1153 /* "raw" is only valid for the disassembler. */
1154 if (new_cpu
!= 0 && (new_cpu
& PPC_OPCODE_RAW
) == 0)
1157 if (strcmp (arg
, "vle") == 0)
1159 if (set_target_endian
&& target_big_endian
== 0)
1160 as_bad (_("the use of -mvle requires big endian."));
1162 as_bad (_("the use of -mvle requires -a32."));
1166 else if (strcmp (arg
, "no-vle") == 0)
1168 sticky
&= ~PPC_OPCODE_VLE
;
1170 new_cpu
= ppc_parse_cpu (ppc_cpu
, &sticky
, "booke");
1171 new_cpu
&= ~PPC_OPCODE_VLE
;
1176 else if (strcmp (arg
, "regnames") == 0)
1179 else if (strcmp (arg
, "no-regnames") == 0)
1180 reg_names_p
= FALSE
;
1183 /* -mrelocatable/-mrelocatable-lib -- warn about initializations
1184 that require relocation. */
1185 else if (strcmp (arg
, "relocatable") == 0)
1187 shlib
= SHLIB_MRELOCATABLE
;
1188 ppc_flags
|= EF_PPC_RELOCATABLE
;
1191 else if (strcmp (arg
, "relocatable-lib") == 0)
1193 shlib
= SHLIB_MRELOCATABLE
;
1194 ppc_flags
|= EF_PPC_RELOCATABLE_LIB
;
1197 /* -memb, set embedded bit. */
1198 else if (strcmp (arg
, "emb") == 0)
1199 ppc_flags
|= EF_PPC_EMB
;
1201 /* -mlittle/-mbig set the endianness. */
1202 else if (strcmp (arg
, "little") == 0
1203 || strcmp (arg
, "little-endian") == 0)
1205 target_big_endian
= 0;
1206 set_target_endian
= 1;
1207 if (ppc_cpu
& PPC_OPCODE_VLE
)
1208 as_bad (_("the use of -mvle requires big endian."));
1211 else if (strcmp (arg
, "big") == 0 || strcmp (arg
, "big-endian") == 0)
1213 target_big_endian
= 1;
1214 set_target_endian
= 1;
1217 else if (strcmp (arg
, "solaris") == 0)
1220 ppc_comment_chars
= ppc_solaris_comment_chars
;
1223 else if (strcmp (arg
, "no-solaris") == 0)
1226 ppc_comment_chars
= ppc_eabi_comment_chars
;
1228 else if (strcmp (arg
, "spe2") == 0)
1230 ppc_cpu
|= PPC_OPCODE_SPE2
;
1235 as_bad (_("invalid switch -m%s"), arg
);
1241 /* -V: SVR4 argument to print version ID. */
1243 print_version_id ();
1246 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
1247 should be emitted or not. FIXME: Not implemented. */
1251 /* Solaris takes -s to specify that .stabs go in a .stabs section,
1252 rather than .stabs.excl, which is ignored by the linker.
1253 FIXME: Not implemented. */
1264 nop_limit
= strtoul (optarg
, &end
, 0);
1266 as_bad (_("--nops needs a numeric argument"));
1281 is_ppc64_target (const bfd_target
*targ
, void *data ATTRIBUTE_UNUSED
)
1283 switch (targ
->flavour
)
1286 case bfd_target_elf_flavour
:
1287 return strncmp (targ
->name
, "elf64-powerpc", 13) == 0;
1290 case bfd_target_xcoff_flavour
:
1291 return (strcmp (targ
->name
, "aixcoff64-rs6000") == 0
1292 || strcmp (targ
->name
, "aix5coff64-rs6000") == 0);
1300 md_show_usage (FILE *stream
)
1302 fprintf (stream
, _("\
1303 PowerPC options:\n"));
1304 fprintf (stream
, _("\
1305 -a32 generate ELF32/XCOFF32\n"));
1306 if (bfd_iterate_over_targets (is_ppc64_target
, NULL
))
1307 fprintf (stream
, _("\
1308 -a64 generate ELF64/XCOFF64\n"));
1309 fprintf (stream
, _("\
1311 fprintf (stream
, _("\
1312 -mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n"));
1313 fprintf (stream
, _("\
1314 -mpwr generate code for POWER (RIOS1)\n"));
1315 fprintf (stream
, _("\
1316 -m601 generate code for PowerPC 601\n"));
1317 fprintf (stream
, _("\
1318 -mppc, -mppc32, -m603, -m604\n\
1319 generate code for PowerPC 603/604\n"));
1320 fprintf (stream
, _("\
1321 -m403 generate code for PowerPC 403\n"));
1322 fprintf (stream
, _("\
1323 -m405 generate code for PowerPC 405\n"));
1324 fprintf (stream
, _("\
1325 -m440 generate code for PowerPC 440\n"));
1326 fprintf (stream
, _("\
1327 -m464 generate code for PowerPC 464\n"));
1328 fprintf (stream
, _("\
1329 -m476 generate code for PowerPC 476\n"));
1330 fprintf (stream
, _("\
1331 -m7400, -m7410, -m7450, -m7455\n\
1332 generate code for PowerPC 7400/7410/7450/7455\n"));
1333 fprintf (stream
, _("\
1334 -m750cl, -mgekko, -mbroadway\n\
1335 generate code for PowerPC 750cl/Gekko/Broadway\n"));
1336 fprintf (stream
, _("\
1337 -m821, -m850, -m860 generate code for PowerPC 821/850/860\n"));
1338 fprintf (stream
, _("\
1339 -mppc64, -m620 generate code for PowerPC 620/625/630\n"));
1340 fprintf (stream
, _("\
1341 -mppc64bridge generate code for PowerPC 64, including bridge insns\n"));
1342 fprintf (stream
, _("\
1343 -mbooke generate code for 32-bit PowerPC BookE\n"));
1344 fprintf (stream
, _("\
1345 -ma2 generate code for A2 architecture\n"));
1346 fprintf (stream
, _("\
1347 -mpower4, -mpwr4 generate code for Power4 architecture\n"));
1348 fprintf (stream
, _("\
1349 -mpower5, -mpwr5, -mpwr5x\n\
1350 generate code for Power5 architecture\n"));
1351 fprintf (stream
, _("\
1352 -mpower6, -mpwr6 generate code for Power6 architecture\n"));
1353 fprintf (stream
, _("\
1354 -mpower7, -mpwr7 generate code for Power7 architecture\n"));
1355 fprintf (stream
, _("\
1356 -mpower8, -mpwr8 generate code for Power8 architecture\n"));
1357 fprintf (stream
, _("\
1358 -mpower9, -mpwr9 generate code for Power9 architecture\n"));
1359 fprintf (stream
, _("\
1360 -mpower10, -mpwr10 generate code for Power10 architecture\n"));
1361 fprintf (stream
, _("\
1362 -mcell generate code for Cell Broadband Engine architecture\n"));
1363 fprintf (stream
, _("\
1364 -mcom generate code for Power/PowerPC common instructions\n"));
1365 fprintf (stream
, _("\
1366 -many generate code for any architecture (PWR/PWRX/PPC)\n"));
1367 fprintf (stream
, _("\
1368 -maltivec generate code for AltiVec\n"));
1369 fprintf (stream
, _("\
1370 -mvsx generate code for Vector-Scalar (VSX) instructions\n"));
1371 fprintf (stream
, _("\
1372 -me300 generate code for PowerPC e300 family\n"));
1373 fprintf (stream
, _("\
1374 -me500, -me500x2 generate code for Motorola e500 core complex\n"));
1375 fprintf (stream
, _("\
1376 -me500mc, generate code for Freescale e500mc core complex\n"));
1377 fprintf (stream
, _("\
1378 -me500mc64, generate code for Freescale e500mc64 core complex\n"));
1379 fprintf (stream
, _("\
1380 -me5500, generate code for Freescale e5500 core complex\n"));
1381 fprintf (stream
, _("\
1382 -me6500, generate code for Freescale e6500 core complex\n"));
1383 fprintf (stream
, _("\
1384 -mspe generate code for Motorola SPE instructions\n"));
1385 fprintf (stream
, _("\
1386 -mspe2 generate code for Freescale SPE2 instructions\n"));
1387 fprintf (stream
, _("\
1388 -mvle generate code for Freescale VLE instructions\n"));
1389 fprintf (stream
, _("\
1390 -mtitan generate code for AppliedMicro Titan core complex\n"));
1391 fprintf (stream
, _("\
1392 -mregnames Allow symbolic names for registers\n"));
1393 fprintf (stream
, _("\
1394 -mno-regnames Do not allow symbolic names for registers\n"));
1396 fprintf (stream
, _("\
1397 -mrelocatable support for GCC's -mrelocatble option\n"));
1398 fprintf (stream
, _("\
1399 -mrelocatable-lib support for GCC's -mrelocatble-lib option\n"));
1400 fprintf (stream
, _("\
1401 -memb set PPC_EMB bit in ELF flags\n"));
1402 fprintf (stream
, _("\
1403 -mlittle, -mlittle-endian, -le\n\
1404 generate code for a little endian machine\n"));
1405 fprintf (stream
, _("\
1406 -mbig, -mbig-endian, -be\n\
1407 generate code for a big endian machine\n"));
1408 fprintf (stream
, _("\
1409 -msolaris generate code for Solaris\n"));
1410 fprintf (stream
, _("\
1411 -mno-solaris do not generate code for Solaris\n"));
1412 fprintf (stream
, _("\
1413 -K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags\n"));
1414 fprintf (stream
, _("\
1415 -V print assembler version number\n"));
1416 fprintf (stream
, _("\
1417 -Qy, -Qn ignored\n"));
1419 fprintf (stream
, _("\
1420 -nops=count when aligning, more than COUNT nops uses a branch\n"));
1421 fprintf (stream
, _("\
1422 -ppc476-workaround warn if emitting data to code sections\n"));
1425 /* Set ppc_cpu if it is not already set. */
1430 const char *default_os
= TARGET_OS
;
1431 const char *default_cpu
= TARGET_CPU
;
1433 if ((ppc_cpu
& ~(ppc_cpu_t
) PPC_OPCODE_ANY
) == 0)
1436 if (target_big_endian
)
1437 ppc_cpu
|= PPC_OPCODE_PPC
| PPC_OPCODE_64
;
1439 /* The minimum supported cpu for 64-bit little-endian is power8. */
1440 ppc_cpu
|= ppc_parse_cpu (ppc_cpu
, &sticky
, "power8");
1441 else if (strncmp (default_os
, "aix", 3) == 0
1442 && default_os
[3] >= '4' && default_os
[3] <= '9')
1443 ppc_cpu
|= PPC_OPCODE_COMMON
;
1444 else if (strncmp (default_os
, "aix3", 4) == 0)
1445 ppc_cpu
|= PPC_OPCODE_POWER
;
1446 else if (strcmp (default_cpu
, "rs6000") == 0)
1447 ppc_cpu
|= PPC_OPCODE_POWER
;
1448 else if (strncmp (default_cpu
, "powerpc", 7) == 0)
1449 ppc_cpu
|= PPC_OPCODE_PPC
;
1451 as_fatal (_("unknown default cpu = %s, os = %s"),
1452 default_cpu
, default_os
);
1456 /* Figure out the BFD architecture to use. This function and ppc_mach
1457 are called well before md_begin, when the output file is opened. */
1459 enum bfd_architecture
1462 const char *default_cpu
= TARGET_CPU
;
1465 if ((ppc_cpu
& PPC_OPCODE_PPC
) != 0)
1466 return bfd_arch_powerpc
;
1467 if ((ppc_cpu
& PPC_OPCODE_VLE
) != 0)
1468 return bfd_arch_powerpc
;
1469 if ((ppc_cpu
& PPC_OPCODE_POWER
) != 0)
1470 return bfd_arch_rs6000
;
1471 if ((ppc_cpu
& (PPC_OPCODE_COMMON
| PPC_OPCODE_ANY
)) != 0)
1473 if (strcmp (default_cpu
, "rs6000") == 0)
1474 return bfd_arch_rs6000
;
1475 else if (strncmp (default_cpu
, "powerpc", 7) == 0)
1476 return bfd_arch_powerpc
;
1479 as_fatal (_("neither Power nor PowerPC opcodes were selected."));
1480 return bfd_arch_unknown
;
1487 return bfd_mach_ppc64
;
1488 else if (ppc_arch () == bfd_arch_rs6000
)
1489 return bfd_mach_rs6k
;
1490 else if (ppc_cpu
& PPC_OPCODE_TITAN
)
1491 return bfd_mach_ppc_titan
;
1492 else if (ppc_cpu
& PPC_OPCODE_VLE
)
1493 return bfd_mach_ppc_vle
;
1495 return bfd_mach_ppc
;
1499 ppc_target_format (void)
1503 return "xcoff-powermac";
1506 return (ppc_obj64
? "aix5coff64-rs6000" : "aixcoff-rs6000");
1508 return (ppc_obj64
? "aixcoff64-rs6000" : "aixcoff-rs6000");
1514 return (ppc_obj64
? "elf64-powerpc-freebsd" : "elf32-powerpc-freebsd");
1515 # elif defined (TE_VXWORKS)
1516 return "elf32-powerpc-vxworks";
1518 return (target_big_endian
1519 ? (ppc_obj64
? "elf64-powerpc" : "elf32-powerpc")
1520 : (ppc_obj64
? "elf64-powerpcle" : "elf32-powerpcle"));
1525 /* Validate one entry in powerpc_opcodes[] or vle_opcodes[].
1526 Return TRUE if there's a problem, otherwise FALSE. */
1529 insn_validate (const struct powerpc_opcode
*op
)
1531 const unsigned char *o
;
1532 uint64_t omask
= op
->mask
;
1534 /* The mask had better not trim off opcode bits. */
1535 if ((op
->opcode
& omask
) != op
->opcode
)
1537 as_bad (_("mask trims opcode bits for %s"), op
->name
);
1541 /* The operands must not overlap the opcode or each other. */
1542 for (o
= op
->operands
; *o
; ++o
)
1544 bfd_boolean optional
= FALSE
;
1545 if (*o
>= num_powerpc_operands
)
1547 as_bad (_("operand index error for %s"), op
->name
);
1553 const struct powerpc_operand
*operand
= &powerpc_operands
[*o
];
1554 if (operand
->shift
== (int) PPC_OPSHIFT_INV
)
1561 if ((operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
1563 else if ((operand
->flags
& PPC_OPERAND_PLUS1
) != 0)
1565 mask
= (*operand
->insert
) (0, val
, ppc_cpu
, &errmsg
);
1567 else if (operand
->shift
>= 0)
1568 mask
= operand
->bitm
<< operand
->shift
;
1570 mask
= operand
->bitm
>> -operand
->shift
;
1573 as_bad (_("operand %d overlap in %s"),
1574 (int) (o
- op
->operands
), op
->name
);
1578 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0)
1582 as_bad (_("non-optional operand %d follows optional operand in %s"),
1583 (int) (o
- op
->operands
), op
->name
);
1591 /* Insert opcodes and macros into hash tables. Called at startup and
1592 for .machine pseudo. */
1595 ppc_setup_opcodes (void)
1597 const struct powerpc_opcode
*op
;
1598 const struct powerpc_opcode
*op_end
;
1599 const struct powerpc_macro
*macro
;
1600 const struct powerpc_macro
*macro_end
;
1601 bfd_boolean bad_insn
= FALSE
;
1603 if (ppc_hash
!= NULL
)
1604 hash_die (ppc_hash
);
1605 if (ppc_macro_hash
!= NULL
)
1606 hash_die (ppc_macro_hash
);
1608 /* Insert the opcodes into a hash table. */
1609 ppc_hash
= hash_new ();
1611 if (ENABLE_CHECKING
)
1615 /* An index into powerpc_operands is stored in struct fix
1616 fx_pcrel_adjust which is 8 bits wide. */
1617 gas_assert (num_powerpc_operands
< 256);
1619 /* Check operand masks. Code here and in the disassembler assumes
1620 all the 1's in the mask are contiguous. */
1621 for (i
= 0; i
< num_powerpc_operands
; ++i
)
1623 uint64_t mask
= powerpc_operands
[i
].bitm
;
1627 right_bit
= mask
& -mask
;
1629 right_bit
= mask
& -mask
;
1630 if (mask
!= right_bit
)
1632 as_bad (_("powerpc_operands[%d].bitm invalid"), i
);
1635 for (j
= i
+ 1; j
< num_powerpc_operands
; ++j
)
1636 if (memcmp (&powerpc_operands
[i
], &powerpc_operands
[j
],
1637 sizeof (powerpc_operands
[0])) == 0)
1639 as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"),
1646 op_end
= powerpc_opcodes
+ powerpc_num_opcodes
;
1647 for (op
= powerpc_opcodes
; op
< op_end
; op
++)
1649 if (ENABLE_CHECKING
)
1651 unsigned int new_opcode
= PPC_OP (op
[0].opcode
);
1653 #ifdef PRINT_OPCODE_TABLE
1654 printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
1655 op
->name
, (unsigned int) (op
- powerpc_opcodes
),
1656 new_opcode
, (unsigned long long) op
->opcode
,
1657 (unsigned long long) op
->mask
, (unsigned long long) op
->flags
);
1660 /* The major opcodes had better be sorted. Code in the disassembler
1661 assumes the insns are sorted according to major opcode. */
1662 if (op
!= powerpc_opcodes
1663 && new_opcode
< PPC_OP (op
[-1].opcode
))
1665 as_bad (_("major opcode is not sorted for %s"), op
->name
);
1669 if ((op
->flags
& PPC_OPCODE_VLE
) != 0)
1671 as_bad (_("%s is enabled by vle flag"), op
->name
);
1674 if (PPC_OP (op
->opcode
) != 4
1675 && PPC_OP (op
->opcode
) != 31
1676 && (op
->deprecated
& PPC_OPCODE_VLE
) == 0)
1678 as_bad (_("%s not disabled by vle flag"), op
->name
);
1681 bad_insn
|= insn_validate (op
);
1684 if ((ppc_cpu
& op
->flags
) != 0
1685 && !(ppc_cpu
& op
->deprecated
))
1689 retval
= hash_insert (ppc_hash
, op
->name
, (void *) op
);
1692 as_bad (_("duplicate instruction %s"),
1699 if ((ppc_cpu
& PPC_OPCODE_ANY
) != 0)
1700 for (op
= powerpc_opcodes
; op
< op_end
; op
++)
1701 hash_insert (ppc_hash
, op
->name
, (void *) op
);
1703 op_end
= prefix_opcodes
+ prefix_num_opcodes
;
1704 for (op
= prefix_opcodes
; op
< op_end
; op
++)
1706 if (ENABLE_CHECKING
)
1708 unsigned int new_opcode
= PPC_PREFIX_SEG (op
[0].opcode
);
1710 #ifdef PRINT_OPCODE_TABLE
1711 printf ("%-14s\t#%04u\tmajor op/2: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
1712 op
->name
, (unsigned int) (op
- prefix_opcodes
),
1713 new_opcode
, (unsigned long long) op
->opcode
,
1714 (unsigned long long) op
->mask
, (unsigned long long) op
->flags
);
1717 /* The major opcodes had better be sorted. Code in the disassembler
1718 assumes the insns are sorted according to major opcode. */
1719 if (op
!= prefix_opcodes
1720 && new_opcode
< PPC_PREFIX_SEG (op
[-1].opcode
))
1722 as_bad (_("major opcode is not sorted for %s"), op
->name
);
1725 bad_insn
|= insn_validate (op
);
1728 if ((ppc_cpu
& op
->flags
) != 0
1729 && !(ppc_cpu
& op
->deprecated
))
1733 retval
= hash_insert (ppc_hash
, op
->name
, (void *) op
);
1736 as_bad (_("duplicate instruction %s"),
1743 if ((ppc_cpu
& PPC_OPCODE_ANY
) != 0)
1744 for (op
= prefix_opcodes
; op
< op_end
; op
++)
1745 hash_insert (ppc_hash
, op
->name
, (void *) op
);
1747 op_end
= vle_opcodes
+ vle_num_opcodes
;
1748 for (op
= vle_opcodes
; op
< op_end
; op
++)
1750 if (ENABLE_CHECKING
)
1752 unsigned new_seg
= VLE_OP_TO_SEG (VLE_OP (op
[0].opcode
, op
[0].mask
));
1754 #ifdef PRINT_OPCODE_TABLE
1755 printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
1756 op
->name
, (unsigned int) (op
- vle_opcodes
),
1757 (unsigned int) new_seg
, (unsigned long long) op
->opcode
,
1758 (unsigned long long) op
->mask
, (unsigned long long) op
->flags
);
1761 /* The major opcodes had better be sorted. Code in the disassembler
1762 assumes the insns are sorted according to major opcode. */
1763 if (op
!= vle_opcodes
1764 && new_seg
< VLE_OP_TO_SEG (VLE_OP (op
[-1].opcode
, op
[-1].mask
)))
1766 as_bad (_("major opcode is not sorted for %s"), op
->name
);
1770 bad_insn
|= insn_validate (op
);
1773 if ((ppc_cpu
& op
->flags
) != 0
1774 && !(ppc_cpu
& op
->deprecated
))
1778 retval
= hash_insert (ppc_hash
, op
->name
, (void *) op
);
1781 as_bad (_("duplicate instruction %s"),
1788 /* SPE2 instructions */
1789 if ((ppc_cpu
& PPC_OPCODE_SPE2
) == PPC_OPCODE_SPE2
)
1791 op_end
= spe2_opcodes
+ spe2_num_opcodes
;
1792 for (op
= spe2_opcodes
; op
< op_end
; op
++)
1794 if (ENABLE_CHECKING
)
1796 if (op
!= spe2_opcodes
)
1798 unsigned old_seg
, new_seg
;
1800 old_seg
= VLE_OP (op
[-1].opcode
, op
[-1].mask
);
1801 old_seg
= VLE_OP_TO_SEG (old_seg
);
1802 new_seg
= VLE_OP (op
[0].opcode
, op
[0].mask
);
1803 new_seg
= VLE_OP_TO_SEG (new_seg
);
1805 /* The major opcodes had better be sorted. Code in the
1806 disassembler assumes the insns are sorted according to
1808 if (new_seg
< old_seg
)
1810 as_bad (_("major opcode is not sorted for %s"), op
->name
);
1815 bad_insn
|= insn_validate (op
);
1818 if ((ppc_cpu
& op
->flags
) != 0 && !(ppc_cpu
& op
->deprecated
))
1822 retval
= hash_insert (ppc_hash
, op
->name
, (void *) op
);
1825 as_bad (_("duplicate instruction %s"),
1832 for (op
= spe2_opcodes
; op
< op_end
; op
++)
1833 hash_insert (ppc_hash
, op
->name
, (void *) op
);
1836 /* Insert the macros into a hash table. */
1837 ppc_macro_hash
= hash_new ();
1839 macro_end
= powerpc_macros
+ powerpc_num_macros
;
1840 for (macro
= powerpc_macros
; macro
< macro_end
; macro
++)
1842 if ((macro
->flags
& ppc_cpu
) != 0 || (ppc_cpu
& PPC_OPCODE_ANY
) != 0)
1846 retval
= hash_insert (ppc_macro_hash
, macro
->name
, (void *) macro
);
1847 if (retval
!= (const char *) NULL
)
1849 as_bad (_("duplicate macro %s"), macro
->name
);
1859 /* This function is called when the assembler starts up. It is called
1860 after the options have been parsed and the output file has been
1868 ppc_cie_data_alignment
= ppc_obj64
? -8 : -4;
1869 ppc_dwarf2_line_min_insn_length
= (ppc_cpu
& PPC_OPCODE_VLE
) ? 2 : 4;
1872 /* Set the ELF flags if desired. */
1873 if (ppc_flags
&& !msolaris
)
1874 bfd_set_private_flags (stdoutput
, ppc_flags
);
1877 ppc_setup_opcodes ();
1879 /* Tell the main code what the endianness is if it is not overridden
1881 if (!set_target_endian
)
1883 set_target_endian
= 1;
1884 target_big_endian
= PPC_BIG_ENDIAN
;
1888 ppc_coff_debug_section
= coff_section_from_bfd_index (stdoutput
, N_DEBUG
);
1890 /* Create dummy symbols to serve as initial csects. This forces the
1891 text csects to precede the data csects. These symbols will not
1893 ppc_text_csects
= symbol_make ("dummy\001");
1894 symbol_get_tc (ppc_text_csects
)->within
= ppc_text_csects
;
1895 ppc_data_csects
= symbol_make ("dummy\001");
1896 symbol_get_tc (ppc_data_csects
)->within
= ppc_data_csects
;
1904 if (ppc_apuinfo_list
== NULL
)
1907 /* Ok, so write the section info out. We have this layout:
1911 0 8 length of "APUinfo\0"
1912 4 (n*4) number of APU's (4 bytes each)
1915 20 APU#1 first APU's info
1916 24 APU#2 second APU's info
1921 asection
*seg
= now_seg
;
1922 subsegT subseg
= now_subseg
;
1923 asection
*apuinfo_secp
= (asection
*) NULL
;
1926 /* Create the .PPC.EMB.apuinfo section. */
1927 apuinfo_secp
= subseg_new (APUINFO_SECTION_NAME
, 0);
1928 bfd_set_section_flags (apuinfo_secp
, SEC_HAS_CONTENTS
| SEC_READONLY
);
1931 md_number_to_chars (p
, (valueT
) 8, 4);
1934 md_number_to_chars (p
, (valueT
) ppc_apuinfo_num
* 4, 4);
1937 md_number_to_chars (p
, (valueT
) 2, 4);
1940 strcpy (p
, APUINFO_LABEL
);
1942 for (i
= 0; i
< ppc_apuinfo_num
; i
++)
1945 md_number_to_chars (p
, (valueT
) ppc_apuinfo_list
[i
], 4);
1948 frag_align (2, 0, 0);
1950 /* We probably can't restore the current segment, for there likely
1953 subseg_set (seg
, subseg
);
1958 /* Insert an operand value into an instruction. */
1961 ppc_insert_operand (uint64_t insn
,
1962 const struct powerpc_operand
*operand
,
1968 int64_t min
, max
, right
;
1970 max
= operand
->bitm
;
1974 if ((operand
->flags
& PPC_OPERAND_SIGNOPT
) != 0)
1976 /* Extend the allowed range for addis to [-32768, 65535].
1977 Similarly for cmpli and some VLE high part insns. For 64-bit
1978 it would be good to disable this for signed fields since the
1979 value is sign extended into the high 32 bits of the register.
1980 If the value is, say, an address, then we might care about
1981 the high bits. However, gcc as of 2014-06 uses unsigned
1982 values when loading the high part of 64-bit constants using
1984 min
= ~(max
>> 1) & -right
;
1986 else if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
1988 max
= (max
>> 1) & -right
;
1989 min
= ~max
& -right
;
1992 if ((operand
->flags
& PPC_OPERAND_PLUS1
) != 0)
1995 if ((operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
2004 /* Some people write constants with the sign extension done by
2005 hand but only up to 32 bits. This shouldn't really be valid,
2006 but, to permit this code to assemble on a 64-bit host, we
2007 sign extend the 32-bit value to 64 bits if so doing makes the
2008 value valid. We only do this for operands that are 32-bits or
2011 && (operand
->bitm
& ~0xffffffffULL
) == 0
2012 && (val
- (1LL << 32)) >= min
2013 && (val
- (1LL << 32)) <= max
2014 && ((val
- (1LL << 32)) & (right
- 1)) == 0)
2015 val
= val
- (1LL << 32);
2017 /* Similarly, people write expressions like ~(1<<15), and expect
2018 this to be OK for a 32-bit unsigned value. */
2020 && (operand
->bitm
& ~0xffffffffULL
) == 0
2021 && (val
+ (1LL << 32)) >= min
2022 && (val
+ (1LL << 32)) <= max
2023 && ((val
+ (1LL << 32)) & (right
- 1)) == 0)
2024 val
= val
+ (1LL << 32);
2028 || (val
& (right
- 1)) != 0)
2029 as_bad_value_out_of_range (_("operand"), val
, min
, max
, file
, line
);
2032 if (operand
->insert
)
2037 insn
= (*operand
->insert
) (insn
, val
, cpu
, &errmsg
);
2038 if (errmsg
!= (const char *) NULL
)
2039 as_bad_where (file
, line
, "%s", errmsg
);
2041 else if (operand
->shift
>= 0)
2042 insn
|= (val
& operand
->bitm
) << operand
->shift
;
2044 insn
|= (val
& operand
->bitm
) >> -operand
->shift
;
2051 /* Parse @got, etc. and return the desired relocation. */
2052 static bfd_reloc_code_real_type
2053 ppc_elf_suffix (char **str_p
, expressionS
*exp_p
)
2057 unsigned int length
: 8;
2058 unsigned int valid32
: 1;
2059 unsigned int valid64
: 1;
2068 const struct map_bfd
*ptr
;
2070 #define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc }
2071 #define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc }
2072 #define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc }
2074 static const struct map_bfd mapping
[] = {
2075 MAP ("l", BFD_RELOC_LO16
),
2076 MAP ("h", BFD_RELOC_HI16
),
2077 MAP ("ha", BFD_RELOC_HI16_S
),
2078 MAP ("brtaken", BFD_RELOC_PPC_B16_BRTAKEN
),
2079 MAP ("brntaken", BFD_RELOC_PPC_B16_BRNTAKEN
),
2080 MAP ("got", BFD_RELOC_16_GOTOFF
),
2081 MAP ("got@l", BFD_RELOC_LO16_GOTOFF
),
2082 MAP ("got@h", BFD_RELOC_HI16_GOTOFF
),
2083 MAP ("got@ha", BFD_RELOC_HI16_S_GOTOFF
),
2084 MAP ("plt@l", BFD_RELOC_LO16_PLTOFF
),
2085 MAP ("plt@h", BFD_RELOC_HI16_PLTOFF
),
2086 MAP ("plt@ha", BFD_RELOC_HI16_S_PLTOFF
),
2087 MAP ("copy", BFD_RELOC_PPC_COPY
),
2088 MAP ("globdat", BFD_RELOC_PPC_GLOB_DAT
),
2089 MAP ("sectoff", BFD_RELOC_16_BASEREL
),
2090 MAP ("sectoff@l", BFD_RELOC_LO16_BASEREL
),
2091 MAP ("sectoff@h", BFD_RELOC_HI16_BASEREL
),
2092 MAP ("sectoff@ha", BFD_RELOC_HI16_S_BASEREL
),
2093 MAP ("tls", BFD_RELOC_PPC_TLS
),
2094 MAP ("dtpmod", BFD_RELOC_PPC_DTPMOD
),
2095 MAP ("dtprel", BFD_RELOC_PPC_DTPREL
),
2096 MAP ("dtprel@l", BFD_RELOC_PPC_DTPREL16_LO
),
2097 MAP ("dtprel@h", BFD_RELOC_PPC_DTPREL16_HI
),
2098 MAP ("dtprel@ha", BFD_RELOC_PPC_DTPREL16_HA
),
2099 MAP ("tprel", BFD_RELOC_PPC_TPREL
),
2100 MAP ("tprel@l", BFD_RELOC_PPC_TPREL16_LO
),
2101 MAP ("tprel@h", BFD_RELOC_PPC_TPREL16_HI
),
2102 MAP ("tprel@ha", BFD_RELOC_PPC_TPREL16_HA
),
2103 MAP ("got@tlsgd", BFD_RELOC_PPC_GOT_TLSGD16
),
2104 MAP ("got@tlsgd@l", BFD_RELOC_PPC_GOT_TLSGD16_LO
),
2105 MAP ("got@tlsgd@h", BFD_RELOC_PPC_GOT_TLSGD16_HI
),
2106 MAP ("got@tlsgd@ha", BFD_RELOC_PPC_GOT_TLSGD16_HA
),
2107 MAP ("got@tlsld", BFD_RELOC_PPC_GOT_TLSLD16
),
2108 MAP ("got@tlsld@l", BFD_RELOC_PPC_GOT_TLSLD16_LO
),
2109 MAP ("got@tlsld@h", BFD_RELOC_PPC_GOT_TLSLD16_HI
),
2110 MAP ("got@tlsld@ha", BFD_RELOC_PPC_GOT_TLSLD16_HA
),
2111 MAP ("got@dtprel", BFD_RELOC_PPC_GOT_DTPREL16
),
2112 MAP ("got@dtprel@l", BFD_RELOC_PPC_GOT_DTPREL16_LO
),
2113 MAP ("got@dtprel@h", BFD_RELOC_PPC_GOT_DTPREL16_HI
),
2114 MAP ("got@dtprel@ha", BFD_RELOC_PPC_GOT_DTPREL16_HA
),
2115 MAP ("got@tprel", BFD_RELOC_PPC_GOT_TPREL16
),
2116 MAP ("got@tprel@l", BFD_RELOC_PPC_GOT_TPREL16_LO
),
2117 MAP ("got@tprel@h", BFD_RELOC_PPC_GOT_TPREL16_HI
),
2118 MAP ("got@tprel@ha", BFD_RELOC_PPC_GOT_TPREL16_HA
),
2119 MAP32 ("fixup", BFD_RELOC_CTOR
),
2120 MAP32 ("plt", BFD_RELOC_24_PLT_PCREL
),
2121 MAP32 ("pltrel24", BFD_RELOC_24_PLT_PCREL
),
2122 MAP32 ("local24pc", BFD_RELOC_PPC_LOCAL24PC
),
2123 MAP32 ("local", BFD_RELOC_PPC_LOCAL24PC
),
2124 MAP32 ("pltrel", BFD_RELOC_32_PLT_PCREL
),
2125 MAP32 ("sdarel", BFD_RELOC_GPREL16
),
2126 MAP32 ("sdarel@l", BFD_RELOC_PPC_VLE_SDAREL_LO16A
),
2127 MAP32 ("sdarel@h", BFD_RELOC_PPC_VLE_SDAREL_HI16A
),
2128 MAP32 ("sdarel@ha", BFD_RELOC_PPC_VLE_SDAREL_HA16A
),
2129 MAP32 ("naddr", BFD_RELOC_PPC_EMB_NADDR32
),
2130 MAP32 ("naddr16", BFD_RELOC_PPC_EMB_NADDR16
),
2131 MAP32 ("naddr@l", BFD_RELOC_PPC_EMB_NADDR16_LO
),
2132 MAP32 ("naddr@h", BFD_RELOC_PPC_EMB_NADDR16_HI
),
2133 MAP32 ("naddr@ha", BFD_RELOC_PPC_EMB_NADDR16_HA
),
2134 MAP32 ("sdai16", BFD_RELOC_PPC_EMB_SDAI16
),
2135 MAP32 ("sda2rel", BFD_RELOC_PPC_EMB_SDA2REL
),
2136 MAP32 ("sda2i16", BFD_RELOC_PPC_EMB_SDA2I16
),
2137 MAP32 ("sda21", BFD_RELOC_PPC_EMB_SDA21
),
2138 MAP32 ("sda21@l", BFD_RELOC_PPC_VLE_SDA21_LO
),
2139 MAP32 ("mrkref", BFD_RELOC_PPC_EMB_MRKREF
),
2140 MAP32 ("relsect", BFD_RELOC_PPC_EMB_RELSEC16
),
2141 MAP32 ("relsect@l", BFD_RELOC_PPC_EMB_RELST_LO
),
2142 MAP32 ("relsect@h", BFD_RELOC_PPC_EMB_RELST_HI
),
2143 MAP32 ("relsect@ha", BFD_RELOC_PPC_EMB_RELST_HA
),
2144 MAP32 ("bitfld", BFD_RELOC_PPC_EMB_BIT_FLD
),
2145 MAP32 ("relsda", BFD_RELOC_PPC_EMB_RELSDA
),
2146 MAP32 ("xgot", BFD_RELOC_PPC_TOC16
),
2147 MAP64 ("high", BFD_RELOC_PPC64_ADDR16_HIGH
),
2148 MAP64 ("higha", BFD_RELOC_PPC64_ADDR16_HIGHA
),
2149 MAP64 ("higher", BFD_RELOC_PPC64_HIGHER
),
2150 MAP64 ("highera", BFD_RELOC_PPC64_HIGHER_S
),
2151 MAP64 ("highest", BFD_RELOC_PPC64_HIGHEST
),
2152 MAP64 ("highesta", BFD_RELOC_PPC64_HIGHEST_S
),
2153 MAP64 ("tocbase", BFD_RELOC_PPC64_TOC
),
2154 MAP64 ("toc", BFD_RELOC_PPC_TOC16
),
2155 MAP64 ("toc@l", BFD_RELOC_PPC64_TOC16_LO
),
2156 MAP64 ("toc@h", BFD_RELOC_PPC64_TOC16_HI
),
2157 MAP64 ("toc@ha", BFD_RELOC_PPC64_TOC16_HA
),
2158 MAP64 ("dtprel@high", BFD_RELOC_PPC64_DTPREL16_HIGH
),
2159 MAP64 ("dtprel@higha", BFD_RELOC_PPC64_DTPREL16_HIGHA
),
2160 MAP64 ("dtprel@higher", BFD_RELOC_PPC64_DTPREL16_HIGHER
),
2161 MAP64 ("dtprel@highera", BFD_RELOC_PPC64_DTPREL16_HIGHERA
),
2162 MAP64 ("dtprel@highest", BFD_RELOC_PPC64_DTPREL16_HIGHEST
),
2163 MAP64 ("dtprel@highesta", BFD_RELOC_PPC64_DTPREL16_HIGHESTA
),
2164 MAP64 ("localentry", BFD_RELOC_PPC64_ADDR64_LOCAL
),
2165 MAP64 ("tprel@high", BFD_RELOC_PPC64_TPREL16_HIGH
),
2166 MAP64 ("tprel@higha", BFD_RELOC_PPC64_TPREL16_HIGHA
),
2167 MAP64 ("tprel@higher", BFD_RELOC_PPC64_TPREL16_HIGHER
),
2168 MAP64 ("tprel@highera", BFD_RELOC_PPC64_TPREL16_HIGHERA
),
2169 MAP64 ("tprel@highest", BFD_RELOC_PPC64_TPREL16_HIGHEST
),
2170 MAP64 ("tprel@highesta", BFD_RELOC_PPC64_TPREL16_HIGHESTA
),
2171 MAP64 ("notoc", BFD_RELOC_PPC64_REL24_NOTOC
),
2172 MAP64 ("pcrel", BFD_RELOC_PPC64_PCREL34
),
2173 MAP64 ("got@pcrel", BFD_RELOC_PPC64_GOT_PCREL34
),
2174 MAP64 ("plt@pcrel", BFD_RELOC_PPC64_PLT_PCREL34
),
2175 MAP64 ("tls@pcrel", BFD_RELOC_PPC64_TLS_PCREL
),
2176 MAP64 ("got@tlsgd@pcrel", BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
),
2177 MAP64 ("got@tlsld@pcrel", BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
),
2178 MAP64 ("got@tprel@pcrel", BFD_RELOC_PPC64_GOT_TPREL_PCREL34
),
2179 MAP64 ("got@dtprel@pcrel", BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
),
2180 MAP64 ("higher34", BFD_RELOC_PPC64_ADDR16_HIGHER34
),
2181 MAP64 ("highera34", BFD_RELOC_PPC64_ADDR16_HIGHERA34
),
2182 MAP64 ("highest34", BFD_RELOC_PPC64_ADDR16_HIGHEST34
),
2183 MAP64 ("highesta34", BFD_RELOC_PPC64_ADDR16_HIGHESTA34
),
2184 { (char *) 0, 0, 0, 0, BFD_RELOC_NONE
}
2188 return BFD_RELOC_NONE
;
2190 for (ch
= *str
, str2
= ident
;
2191 (str2
< ident
+ sizeof (ident
) - 1
2192 && (ISALNUM (ch
) || ch
== '@'));
2195 *str2
++ = TOLOWER (ch
);
2202 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
2203 if (ch
== ptr
->string
[0]
2204 && len
== ptr
->length
2205 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0
2206 && (ppc_obj64
? ptr
->valid64
: ptr
->valid32
))
2208 int reloc
= ptr
->reloc
;
2210 if (!ppc_obj64
&& exp_p
->X_add_number
!= 0)
2214 case BFD_RELOC_16_GOTOFF
:
2215 case BFD_RELOC_LO16_GOTOFF
:
2216 case BFD_RELOC_HI16_GOTOFF
:
2217 case BFD_RELOC_HI16_S_GOTOFF
:
2218 as_warn (_("symbol+offset@%s means symbol@%s+offset"),
2219 ptr
->string
, ptr
->string
);
2222 case BFD_RELOC_PPC_GOT_TLSGD16
:
2223 case BFD_RELOC_PPC_GOT_TLSGD16_LO
:
2224 case BFD_RELOC_PPC_GOT_TLSGD16_HI
:
2225 case BFD_RELOC_PPC_GOT_TLSGD16_HA
:
2226 case BFD_RELOC_PPC_GOT_TLSLD16
:
2227 case BFD_RELOC_PPC_GOT_TLSLD16_LO
:
2228 case BFD_RELOC_PPC_GOT_TLSLD16_HI
:
2229 case BFD_RELOC_PPC_GOT_TLSLD16_HA
:
2230 case BFD_RELOC_PPC_GOT_DTPREL16
:
2231 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
2232 case BFD_RELOC_PPC_GOT_DTPREL16_HI
:
2233 case BFD_RELOC_PPC_GOT_DTPREL16_HA
:
2234 case BFD_RELOC_PPC_GOT_TPREL16
:
2235 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
2236 case BFD_RELOC_PPC_GOT_TPREL16_HI
:
2237 case BFD_RELOC_PPC_GOT_TPREL16_HA
:
2238 as_bad (_("symbol+offset@%s not supported"), ptr
->string
);
2243 /* Now check for identifier@suffix+constant. */
2244 if (*str
== '-' || *str
== '+')
2246 char *orig_line
= input_line_pointer
;
2247 expressionS new_exp
;
2249 input_line_pointer
= str
;
2250 expression (&new_exp
);
2251 if (new_exp
.X_op
== O_constant
)
2253 exp_p
->X_add_number
+= new_exp
.X_add_number
;
2254 str
= input_line_pointer
;
2257 if (&input_line_pointer
!= str_p
)
2258 input_line_pointer
= orig_line
;
2262 if (reloc
== (int) BFD_RELOC_PPC64_TOC
2263 && exp_p
->X_op
== O_symbol
2264 && strcmp (S_GET_NAME (exp_p
->X_add_symbol
), ".TOC.") == 0)
2266 /* Change the symbol so that the dummy .TOC. symbol can be
2267 omitted from the object file. */
2268 exp_p
->X_add_symbol
= &abs_symbol
;
2271 return (bfd_reloc_code_real_type
) reloc
;
2274 return BFD_RELOC_NONE
;
2277 /* Support @got, etc. on constants emitted via .short, .int etc. */
2279 bfd_reloc_code_real_type
2280 ppc_elf_parse_cons (expressionS
*exp
, unsigned int nbytes
)
2283 if (nbytes
>= 2 && *input_line_pointer
== '@')
2284 return ppc_elf_suffix (&input_line_pointer
, exp
);
2285 return BFD_RELOC_NONE
;
2288 /* Warn when emitting data to code sections, unless we are emitting
2289 a relocation that ld --ppc476-workaround uses to recognise data
2290 *and* there was an unconditional branch prior to the data. */
2293 ppc_elf_cons_fix_check (expressionS
*exp ATTRIBUTE_UNUSED
,
2294 unsigned int nbytes
, fixS
*fix
)
2297 && (now_seg
->flags
& SEC_CODE
) != 0
2300 || !(fix
->fx_r_type
== BFD_RELOC_32
2301 || fix
->fx_r_type
== BFD_RELOC_CTOR
2302 || fix
->fx_r_type
== BFD_RELOC_32_PCREL
)
2303 || !(last_seg
== now_seg
&& last_subseg
== now_subseg
)
2304 || !((last_insn
& (0x3f << 26)) == (18u << 26)
2305 || ((last_insn
& (0x3f << 26)) == (16u << 26)
2306 && (last_insn
& (0x14 << 21)) == (0x14 << 21))
2307 || ((last_insn
& (0x3f << 26)) == (19u << 26)
2308 && (last_insn
& (0x3ff << 1)) == (16u << 1)
2309 && (last_insn
& (0x14 << 21)) == (0x14 << 21)))))
2311 /* Flag that we've warned. */
2315 as_warn (_("data in executable section"));
2319 /* Solaris pseduo op to change to the .rodata section. */
2321 ppc_elf_rdata (int xxx
)
2323 char *save_line
= input_line_pointer
;
2324 static char section
[] = ".rodata\n";
2326 /* Just pretend this is .section .rodata */
2327 input_line_pointer
= section
;
2328 obj_elf_section (xxx
);
2330 input_line_pointer
= save_line
;
2333 /* Pseudo op to make file scope bss items. */
2335 ppc_elf_lcomm (int xxx ATTRIBUTE_UNUSED
)
2348 c
= get_symbol_name (&name
);
2350 /* Just after name is now '\0'. */
2351 p
= input_line_pointer
;
2353 SKIP_WHITESPACE_AFTER_NAME ();
2354 if (*input_line_pointer
!= ',')
2356 as_bad (_("expected comma after symbol-name: rest of line ignored."));
2357 ignore_rest_of_line ();
2361 input_line_pointer
++; /* skip ',' */
2362 if ((size
= get_absolute_expression ()) < 0)
2364 as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) size
);
2365 ignore_rest_of_line ();
2369 /* The third argument to .lcomm is the alignment. */
2370 if (*input_line_pointer
!= ',')
2374 ++input_line_pointer
;
2375 align
= get_absolute_expression ();
2378 as_warn (_("ignoring bad alignment"));
2384 symbolP
= symbol_find_or_make (name
);
2387 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
2389 as_bad (_("ignoring attempt to re-define symbol `%s'."),
2390 S_GET_NAME (symbolP
));
2391 ignore_rest_of_line ();
2395 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
2397 as_bad (_("length of .lcomm \"%s\" is already %ld. Not changed to %ld."),
2398 S_GET_NAME (symbolP
),
2399 (long) S_GET_VALUE (symbolP
),
2402 ignore_rest_of_line ();
2408 old_subsec
= now_subseg
;
2411 /* Convert to a power of 2 alignment. */
2412 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++align2
);
2415 as_bad (_("common alignment not a power of 2"));
2416 ignore_rest_of_line ();
2423 record_alignment (bss_section
, align2
);
2424 subseg_set (bss_section
, 1);
2426 frag_align (align2
, 0, 0);
2427 if (S_GET_SEGMENT (symbolP
) == bss_section
)
2428 symbol_get_frag (symbolP
)->fr_symbol
= 0;
2429 symbol_set_frag (symbolP
, frag_now
);
2430 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
2433 S_SET_SIZE (symbolP
, size
);
2434 S_SET_SEGMENT (symbolP
, bss_section
);
2435 subseg_set (old_sec
, old_subsec
);
2436 demand_empty_rest_of_line ();
2439 /* Pseudo op to set symbol local entry point. */
2441 ppc_elf_localentry (int ignore ATTRIBUTE_UNUSED
)
2444 char c
= get_symbol_name (&name
);
2449 elf_symbol_type
*elfsym
;
2451 p
= input_line_pointer
;
2453 SKIP_WHITESPACE_AFTER_NAME ();
2454 if (*input_line_pointer
!= ',')
2457 as_bad (_("expected comma after name `%s' in .localentry directive"),
2460 ignore_rest_of_line ();
2463 input_line_pointer
++;
2465 if (exp
.X_op
== O_absent
)
2467 as_bad (_("missing expression in .localentry directive"));
2468 exp
.X_op
= O_constant
;
2469 exp
.X_add_number
= 0;
2472 sym
= symbol_find_or_make (name
);
2475 if (resolve_expression (&exp
)
2476 && exp
.X_op
== O_constant
)
2478 unsigned int encoded
, ok
;
2481 if (exp
.X_add_number
== 1 || exp
.X_add_number
== 7)
2482 encoded
= exp
.X_add_number
<< STO_PPC64_LOCAL_BIT
;
2485 encoded
= PPC64_SET_LOCAL_ENTRY_OFFSET (exp
.X_add_number
);
2486 if (exp
.X_add_number
!= (offsetT
) PPC64_LOCAL_ENTRY_OFFSET (encoded
))
2488 as_bad (_(".localentry expression for `%s' "
2489 "is not a valid power of 2"), S_GET_NAME (sym
));
2495 bfdsym
= symbol_get_bfdsym (sym
);
2496 elfsym
= elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
2497 gas_assert (elfsym
);
2498 elfsym
->internal_elf_sym
.st_other
&= ~STO_PPC64_LOCAL_MASK
;
2499 elfsym
->internal_elf_sym
.st_other
|= encoded
;
2500 if (ppc_abiversion
== 0)
2505 as_bad (_(".localentry expression for `%s' "
2506 "does not evaluate to a constant"), S_GET_NAME (sym
));
2508 demand_empty_rest_of_line ();
2511 /* Pseudo op to set ABI version. */
2513 ppc_elf_abiversion (int ignore ATTRIBUTE_UNUSED
)
2518 if (exp
.X_op
== O_absent
)
2520 as_bad (_("missing expression in .abiversion directive"));
2521 exp
.X_op
= O_constant
;
2522 exp
.X_add_number
= 0;
2525 if (resolve_expression (&exp
)
2526 && exp
.X_op
== O_constant
)
2527 ppc_abiversion
= exp
.X_add_number
;
2529 as_bad (_(".abiversion expression does not evaluate to a constant"));
2530 demand_empty_rest_of_line ();
2533 /* Parse a .gnu_attribute directive. */
2535 ppc_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED
)
2537 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_GNU
);
2539 /* Check validity of defined powerpc tags. */
2540 if (tag
== Tag_GNU_Power_ABI_FP
2541 || tag
== Tag_GNU_Power_ABI_Vector
2542 || tag
== Tag_GNU_Power_ABI_Struct_Return
)
2546 val
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, tag
);
2548 if ((tag
== Tag_GNU_Power_ABI_FP
&& val
> 15)
2549 || (tag
== Tag_GNU_Power_ABI_Vector
&& val
> 3)
2550 || (tag
== Tag_GNU_Power_ABI_Struct_Return
&& val
> 2))
2551 as_warn (_("unknown .gnu_attribute value"));
2555 /* Set ABI version in output file. */
2559 if (ppc_obj64
&& ppc_abiversion
!= 0)
2561 elf_elfheader (stdoutput
)->e_flags
&= ~EF_PPC64_ABI
;
2562 elf_elfheader (stdoutput
)->e_flags
|= ppc_abiversion
& EF_PPC64_ABI
;
2564 /* Any selection of opcodes based on ppc_cpu after gas has finished
2565 parsing the file is invalid. md_apply_fix and ppc_handle_align
2566 must select opcodes based on the machine in force at the point
2567 where the fixup or alignment frag was created, not the machine in
2568 force at the end of file. */
2572 /* Validate any relocations emitted for -mrelocatable, possibly adding
2573 fixups for word relocations in writable segments, so we can adjust
2576 ppc_elf_validate_fix (fixS
*fixp
, segT seg
)
2578 if (fixp
->fx_done
|| fixp
->fx_pcrel
)
2587 case SHLIB_MRELOCATABLE
:
2588 if (fixp
->fx_r_type
!= BFD_RELOC_16_GOTOFF
2589 && fixp
->fx_r_type
!= BFD_RELOC_HI16_GOTOFF
2590 && fixp
->fx_r_type
!= BFD_RELOC_LO16_GOTOFF
2591 && fixp
->fx_r_type
!= BFD_RELOC_HI16_S_GOTOFF
2592 && fixp
->fx_r_type
!= BFD_RELOC_16_BASEREL
2593 && fixp
->fx_r_type
!= BFD_RELOC_LO16_BASEREL
2594 && fixp
->fx_r_type
!= BFD_RELOC_HI16_BASEREL
2595 && fixp
->fx_r_type
!= BFD_RELOC_HI16_S_BASEREL
2596 && (seg
->flags
& SEC_LOAD
) != 0
2597 && strcmp (segment_name (seg
), ".got2") != 0
2598 && strcmp (segment_name (seg
), ".dtors") != 0
2599 && strcmp (segment_name (seg
), ".ctors") != 0
2600 && strcmp (segment_name (seg
), ".fixup") != 0
2601 && strcmp (segment_name (seg
), ".gcc_except_table") != 0
2602 && strcmp (segment_name (seg
), ".eh_frame") != 0
2603 && strcmp (segment_name (seg
), ".ex_shared") != 0)
2605 if ((seg
->flags
& (SEC_READONLY
| SEC_CODE
)) != 0
2606 || fixp
->fx_r_type
!= BFD_RELOC_CTOR
)
2608 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2609 _("relocation cannot be done when using -mrelocatable"));
2616 /* Prevent elf_frob_file_before_adjust removing a weak undefined
2617 function descriptor sym if the corresponding code sym is used. */
2620 ppc_frob_file_before_adjust (void)
2628 for (symp
= symbol_rootP
; symp
; symp
= symbol_next (symp
))
2634 name
= S_GET_NAME (symp
);
2638 if (! S_IS_WEAK (symp
)
2639 || S_IS_DEFINED (symp
))
2642 dotname
= concat (".", name
, (char *) NULL
);
2643 dotsym
= symbol_find_noref (dotname
, 1);
2645 if (dotsym
!= NULL
&& (symbol_used_p (dotsym
)
2646 || symbol_used_in_reloc_p (dotsym
)))
2647 symbol_mark_used (symp
);
2651 toc
= bfd_get_section_by_name (stdoutput
, ".toc");
2653 && toc_reloc_types
!= has_large_toc_reloc
2654 && bfd_section_size (toc
) > 0x10000)
2655 as_warn (_("TOC section size exceeds 64k"));
2658 /* .TOC. used in an opd entry as .TOC.@tocbase doesn't need to be
2659 emitted. Other uses of .TOC. will cause the symbol to be marked
2660 with BSF_KEEP in md_apply_fix. */
2663 ppc_elf_adjust_symtab (void)
2668 symp
= symbol_find (".TOC.");
2671 asymbol
*bsym
= symbol_get_bfdsym (symp
);
2672 if ((bsym
->flags
& BSF_KEEP
) == 0)
2673 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2677 #endif /* OBJ_ELF */
2679 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
2680 /* See whether a symbol is in the TOC section. */
2683 ppc_is_toc_sym (symbolS
*sym
)
2686 return (symbol_get_tc (sym
)->symbol_class
== XMC_TC
2687 || symbol_get_tc (sym
)->symbol_class
== XMC_TC0
);
2690 const char *sname
= segment_name (S_GET_SEGMENT (sym
));
2692 return strcmp (sname
, ".toc") == 0;
2694 return strcmp (sname
, ".got") == 0;
2697 #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */
2701 #define APUID(a,v) ((((a) & 0xffff) << 16) | ((v) & 0xffff))
2703 ppc_apuinfo_section_add (unsigned int apu
, unsigned int version
)
2707 /* Check we don't already exist. */
2708 for (i
= 0; i
< ppc_apuinfo_num
; i
++)
2709 if (ppc_apuinfo_list
[i
] == APUID (apu
, version
))
2712 if (ppc_apuinfo_num
== ppc_apuinfo_num_alloc
)
2714 if (ppc_apuinfo_num_alloc
== 0)
2716 ppc_apuinfo_num_alloc
= 4;
2717 ppc_apuinfo_list
= XNEWVEC (unsigned long, ppc_apuinfo_num_alloc
);
2721 ppc_apuinfo_num_alloc
+= 4;
2722 ppc_apuinfo_list
= XRESIZEVEC (unsigned long, ppc_apuinfo_list
,
2723 ppc_apuinfo_num_alloc
);
2726 ppc_apuinfo_list
[ppc_apuinfo_num
++] = APUID (apu
, version
);
2731 /* Various frobbings of labels and their addresses. */
2733 /* Symbols labelling the current insn. */
2734 struct insn_label_list
2736 struct insn_label_list
*next
;
2740 static struct insn_label_list
*insn_labels
;
2741 static struct insn_label_list
*free_insn_labels
;
2744 ppc_record_label (symbolS
*sym
)
2746 struct insn_label_list
*l
;
2748 if (free_insn_labels
== NULL
)
2749 l
= XNEW (struct insn_label_list
);
2752 l
= free_insn_labels
;
2753 free_insn_labels
= l
->next
;
2757 l
->next
= insn_labels
;
2762 ppc_clear_labels (void)
2764 while (insn_labels
!= NULL
)
2766 struct insn_label_list
*l
= insn_labels
;
2767 insn_labels
= l
->next
;
2768 l
->next
= free_insn_labels
;
2769 free_insn_labels
= l
;
2774 ppc_start_line_hook (void)
2776 ppc_clear_labels ();
2780 ppc_new_dot_label (symbolS
*sym
)
2782 ppc_record_label (sym
);
2784 /* Anchor this label to the current csect for relocations. */
2785 symbol_get_tc (sym
)->within
= ppc_current_csect
;
2790 ppc_frob_label (symbolS
*sym
)
2792 ppc_record_label (sym
);
2795 /* Set the class of a label based on where it is defined. This handles
2796 symbols without suffixes. Also, move the symbol so that it follows
2797 the csect symbol. */
2798 if (ppc_current_csect
!= (symbolS
*) NULL
)
2800 if (symbol_get_tc (sym
)->symbol_class
== -1)
2801 symbol_get_tc (sym
)->symbol_class
= symbol_get_tc (ppc_current_csect
)->symbol_class
;
2803 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
2804 symbol_append (sym
, symbol_get_tc (ppc_current_csect
)->within
,
2805 &symbol_rootP
, &symbol_lastP
);
2806 symbol_get_tc (ppc_current_csect
)->within
= sym
;
2807 symbol_get_tc (sym
)->within
= ppc_current_csect
;
2812 dwarf2_emit_label (sym
);
2816 /* We need to keep a list of fixups. We can't simply generate them as
2817 we go, because that would require us to first create the frag, and
2818 that would screw up references to ``.''. */
2824 bfd_reloc_code_real_type reloc
;
2827 #define MAX_INSN_FIXUPS (5)
2829 /* Return the field size operated on by RELOC, and whether it is
2830 pc-relative in PC_RELATIVE. */
2833 fixup_size (bfd_reloc_code_real_type reloc
, bfd_boolean
*pc_relative
)
2835 unsigned int size
= 0;
2836 bfd_boolean pcrel
= FALSE
;
2840 /* This switch statement must handle all BFD_RELOC values
2841 possible in instruction fixups. As is, it handles all
2842 BFD_RELOC values used in bfd/elf64-ppc.c, bfd/elf32-ppc.c,
2843 bfd/coff-rs6000.c and bfd/coff64-rs6000.c.
2844 Overkill since data and marker relocs need not be handled
2845 here, but this way we can be sure a needed fixup reloc isn't
2846 accidentally omitted. */
2847 case BFD_RELOC_PPC_EMB_MRKREF
:
2848 case BFD_RELOC_VTABLE_ENTRY
:
2849 case BFD_RELOC_VTABLE_INHERIT
:
2857 case BFD_RELOC_16_BASEREL
:
2858 case BFD_RELOC_16_GOTOFF
:
2859 case BFD_RELOC_GPREL16
:
2860 case BFD_RELOC_HI16
:
2861 case BFD_RELOC_HI16_BASEREL
:
2862 case BFD_RELOC_HI16_GOTOFF
:
2863 case BFD_RELOC_HI16_PLTOFF
:
2864 case BFD_RELOC_HI16_S
:
2865 case BFD_RELOC_HI16_S_BASEREL
:
2866 case BFD_RELOC_HI16_S_GOTOFF
:
2867 case BFD_RELOC_HI16_S_PLTOFF
:
2868 case BFD_RELOC_LO16
:
2869 case BFD_RELOC_LO16_BASEREL
:
2870 case BFD_RELOC_LO16_GOTOFF
:
2871 case BFD_RELOC_LO16_PLTOFF
:
2872 case BFD_RELOC_PPC64_ADDR16_DS
:
2873 case BFD_RELOC_PPC64_ADDR16_HIGH
:
2874 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
2875 case BFD_RELOC_PPC64_ADDR16_HIGHER34
:
2876 case BFD_RELOC_PPC64_ADDR16_HIGHERA34
:
2877 case BFD_RELOC_PPC64_ADDR16_HIGHEST34
:
2878 case BFD_RELOC_PPC64_ADDR16_HIGHESTA34
:
2879 case BFD_RELOC_PPC64_ADDR16_LO_DS
:
2880 case BFD_RELOC_PPC64_DTPREL16_DS
:
2881 case BFD_RELOC_PPC64_DTPREL16_HIGH
:
2882 case BFD_RELOC_PPC64_DTPREL16_HIGHA
:
2883 case BFD_RELOC_PPC64_DTPREL16_HIGHER
:
2884 case BFD_RELOC_PPC64_DTPREL16_HIGHERA
:
2885 case BFD_RELOC_PPC64_DTPREL16_HIGHEST
:
2886 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA
:
2887 case BFD_RELOC_PPC64_DTPREL16_LO_DS
:
2888 case BFD_RELOC_PPC64_GOT16_DS
:
2889 case BFD_RELOC_PPC64_GOT16_LO_DS
:
2890 case BFD_RELOC_PPC64_HIGHER
:
2891 case BFD_RELOC_PPC64_HIGHER_S
:
2892 case BFD_RELOC_PPC64_HIGHEST
:
2893 case BFD_RELOC_PPC64_HIGHEST_S
:
2894 case BFD_RELOC_PPC64_PLT16_LO_DS
:
2895 case BFD_RELOC_PPC64_PLTGOT16
:
2896 case BFD_RELOC_PPC64_PLTGOT16_DS
:
2897 case BFD_RELOC_PPC64_PLTGOT16_HA
:
2898 case BFD_RELOC_PPC64_PLTGOT16_HI
:
2899 case BFD_RELOC_PPC64_PLTGOT16_LO
:
2900 case BFD_RELOC_PPC64_PLTGOT16_LO_DS
:
2901 case BFD_RELOC_PPC64_SECTOFF_DS
:
2902 case BFD_RELOC_PPC64_SECTOFF_LO_DS
:
2903 case BFD_RELOC_PPC64_TOC16_DS
:
2904 case BFD_RELOC_PPC64_TOC16_HA
:
2905 case BFD_RELOC_PPC64_TOC16_HI
:
2906 case BFD_RELOC_PPC64_TOC16_LO
:
2907 case BFD_RELOC_PPC64_TOC16_LO_DS
:
2908 case BFD_RELOC_PPC64_TPREL16_DS
:
2909 case BFD_RELOC_PPC64_TPREL16_HIGH
:
2910 case BFD_RELOC_PPC64_TPREL16_HIGHA
:
2911 case BFD_RELOC_PPC64_TPREL16_HIGHER
:
2912 case BFD_RELOC_PPC64_TPREL16_HIGHERA
:
2913 case BFD_RELOC_PPC64_TPREL16_HIGHEST
:
2914 case BFD_RELOC_PPC64_TPREL16_HIGHESTA
:
2915 case BFD_RELOC_PPC64_TPREL16_LO_DS
:
2917 case BFD_RELOC_PPC_BA16
:
2919 case BFD_RELOC_PPC_DTPREL16
:
2920 case BFD_RELOC_PPC_DTPREL16_HA
:
2921 case BFD_RELOC_PPC_DTPREL16_HI
:
2922 case BFD_RELOC_PPC_DTPREL16_LO
:
2923 case BFD_RELOC_PPC_EMB_NADDR16
:
2924 case BFD_RELOC_PPC_EMB_NADDR16_HA
:
2925 case BFD_RELOC_PPC_EMB_NADDR16_HI
:
2926 case BFD_RELOC_PPC_EMB_NADDR16_LO
:
2927 case BFD_RELOC_PPC_EMB_RELSDA
:
2928 case BFD_RELOC_PPC_EMB_RELSEC16
:
2929 case BFD_RELOC_PPC_EMB_RELST_LO
:
2930 case BFD_RELOC_PPC_EMB_RELST_HI
:
2931 case BFD_RELOC_PPC_EMB_RELST_HA
:
2932 case BFD_RELOC_PPC_EMB_SDA2I16
:
2933 case BFD_RELOC_PPC_EMB_SDA2REL
:
2934 case BFD_RELOC_PPC_EMB_SDAI16
:
2935 case BFD_RELOC_PPC_GOT_DTPREL16
:
2936 case BFD_RELOC_PPC_GOT_DTPREL16_HA
:
2937 case BFD_RELOC_PPC_GOT_DTPREL16_HI
:
2938 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
2939 case BFD_RELOC_PPC_GOT_TLSGD16
:
2940 case BFD_RELOC_PPC_GOT_TLSGD16_HA
:
2941 case BFD_RELOC_PPC_GOT_TLSGD16_HI
:
2942 case BFD_RELOC_PPC_GOT_TLSGD16_LO
:
2943 case BFD_RELOC_PPC_GOT_TLSLD16
:
2944 case BFD_RELOC_PPC_GOT_TLSLD16_HA
:
2945 case BFD_RELOC_PPC_GOT_TLSLD16_HI
:
2946 case BFD_RELOC_PPC_GOT_TLSLD16_LO
:
2947 case BFD_RELOC_PPC_GOT_TPREL16
:
2948 case BFD_RELOC_PPC_GOT_TPREL16_HA
:
2949 case BFD_RELOC_PPC_GOT_TPREL16_HI
:
2950 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
2951 case BFD_RELOC_PPC_TOC16
:
2952 case BFD_RELOC_PPC_TPREL16
:
2953 case BFD_RELOC_PPC_TPREL16_HA
:
2954 case BFD_RELOC_PPC_TPREL16_HI
:
2955 case BFD_RELOC_PPC_TPREL16_LO
:
2959 case BFD_RELOC_16_PCREL
:
2960 case BFD_RELOC_HI16_PCREL
:
2961 case BFD_RELOC_HI16_S_PCREL
:
2962 case BFD_RELOC_LO16_PCREL
:
2963 case BFD_RELOC_PPC64_REL16_HIGH
:
2964 case BFD_RELOC_PPC64_REL16_HIGHA
:
2965 case BFD_RELOC_PPC64_REL16_HIGHER
:
2966 case BFD_RELOC_PPC64_REL16_HIGHER34
:
2967 case BFD_RELOC_PPC64_REL16_HIGHERA
:
2968 case BFD_RELOC_PPC64_REL16_HIGHERA34
:
2969 case BFD_RELOC_PPC64_REL16_HIGHEST
:
2970 case BFD_RELOC_PPC64_REL16_HIGHEST34
:
2971 case BFD_RELOC_PPC64_REL16_HIGHESTA
:
2972 case BFD_RELOC_PPC64_REL16_HIGHESTA34
:
2974 case BFD_RELOC_PPC_B16
:
2976 case BFD_RELOC_PPC_VLE_REL8
:
2982 case BFD_RELOC_32_PLTOFF
:
2984 case BFD_RELOC_CTOR
:
2986 case BFD_RELOC_PPC64_ENTRY
:
2987 case BFD_RELOC_PPC_16DX_HA
:
2989 case BFD_RELOC_PPC_BA16
:
2991 case BFD_RELOC_PPC_BA16_BRNTAKEN
:
2992 case BFD_RELOC_PPC_BA16_BRTAKEN
:
2993 case BFD_RELOC_PPC_BA26
:
2994 case BFD_RELOC_PPC_EMB_BIT_FLD
:
2995 case BFD_RELOC_PPC_EMB_NADDR32
:
2996 case BFD_RELOC_PPC_EMB_SDA21
:
2997 case BFD_RELOC_PPC_TLS
:
2998 case BFD_RELOC_PPC_TLSGD
:
2999 case BFD_RELOC_PPC_TLSLD
:
3000 case BFD_RELOC_PPC_VLE_HA16A
:
3001 case BFD_RELOC_PPC_VLE_HA16D
:
3002 case BFD_RELOC_PPC_VLE_HI16A
:
3003 case BFD_RELOC_PPC_VLE_HI16D
:
3004 case BFD_RELOC_PPC_VLE_LO16A
:
3005 case BFD_RELOC_PPC_VLE_LO16D
:
3006 case BFD_RELOC_PPC_VLE_SDA21
:
3007 case BFD_RELOC_PPC_VLE_SDA21_LO
:
3008 case BFD_RELOC_PPC_VLE_SDAREL_HA16A
:
3009 case BFD_RELOC_PPC_VLE_SDAREL_HA16D
:
3010 case BFD_RELOC_PPC_VLE_SDAREL_HI16A
:
3011 case BFD_RELOC_PPC_VLE_SDAREL_HI16D
:
3012 case BFD_RELOC_PPC_VLE_SDAREL_LO16A
:
3013 case BFD_RELOC_PPC_VLE_SDAREL_LO16D
:
3014 case BFD_RELOC_PPC64_TLS_PCREL
:
3019 case BFD_RELOC_24_PLT_PCREL
:
3020 case BFD_RELOC_32_PCREL
:
3021 case BFD_RELOC_32_PLT_PCREL
:
3022 case BFD_RELOC_PPC64_REL24_NOTOC
:
3024 case BFD_RELOC_PPC_B16
:
3026 case BFD_RELOC_PPC_B16_BRNTAKEN
:
3027 case BFD_RELOC_PPC_B16_BRTAKEN
:
3028 case BFD_RELOC_PPC_B26
:
3029 case BFD_RELOC_PPC_LOCAL24PC
:
3030 case BFD_RELOC_PPC_REL16DX_HA
:
3031 case BFD_RELOC_PPC_VLE_REL15
:
3032 case BFD_RELOC_PPC_VLE_REL24
:
3038 case BFD_RELOC_CTOR
:
3040 case BFD_RELOC_PPC_COPY
:
3041 case BFD_RELOC_PPC_DTPMOD
:
3042 case BFD_RELOC_PPC_DTPREL
:
3043 case BFD_RELOC_PPC_GLOB_DAT
:
3044 case BFD_RELOC_PPC_TPREL
:
3045 size
= ppc_obj64
? 8 : 4;
3049 case BFD_RELOC_64_PLTOFF
:
3050 case BFD_RELOC_PPC64_ADDR64_LOCAL
:
3051 case BFD_RELOC_PPC64_D28
:
3052 case BFD_RELOC_PPC64_D34
:
3053 case BFD_RELOC_PPC64_D34_LO
:
3054 case BFD_RELOC_PPC64_D34_HI30
:
3055 case BFD_RELOC_PPC64_D34_HA30
:
3056 case BFD_RELOC_PPC64_TPREL34
:
3057 case BFD_RELOC_PPC64_DTPREL34
:
3058 case BFD_RELOC_PPC64_TOC
:
3062 case BFD_RELOC_64_PCREL
:
3063 case BFD_RELOC_64_PLT_PCREL
:
3064 case BFD_RELOC_PPC64_GOT_PCREL34
:
3065 case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
:
3066 case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
:
3067 case BFD_RELOC_PPC64_GOT_TPREL_PCREL34
:
3068 case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
:
3069 case BFD_RELOC_PPC64_PCREL28
:
3070 case BFD_RELOC_PPC64_PCREL34
:
3071 case BFD_RELOC_PPC64_PLT_PCREL34
:
3080 if (ENABLE_CHECKING
)
3082 reloc_howto_type
*reloc_howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
3083 if (reloc_howto
!= NULL
3084 && (size
!= bfd_get_reloc_size (reloc_howto
)
3085 || pcrel
!= reloc_howto
->pc_relative
))
3087 as_bad (_("%s howto doesn't match size/pcrel in gas"),
3092 *pc_relative
= pcrel
;
3097 /* If we have parsed a call to __tls_get_addr, parse an argument like
3098 (gd0@tlsgd). *STR is the leading parenthesis on entry. If an arg
3099 is successfully parsed, *STR is updated past the trailing
3100 parenthesis and trailing white space, and *TLS_FIX contains the
3101 reloc and arg expression. */
3104 parse_tls_arg (char **str
, const expressionS
*exp
, struct ppc_fixup
*tls_fix
)
3106 const char *sym_name
= S_GET_NAME (exp
->X_add_symbol
);
3107 if (sym_name
[0] == '.')
3110 tls_fix
->reloc
= BFD_RELOC_NONE
;
3111 if (strncasecmp (sym_name
, "__tls_get_addr", 14) == 0
3112 && (sym_name
[14] == 0
3113 || strcasecmp (sym_name
+ 14, "_desc") == 0
3114 || strcasecmp (sym_name
+ 14, "_opt") == 0))
3116 char *hold
= input_line_pointer
;
3117 input_line_pointer
= *str
+ 1;
3118 expression (&tls_fix
->exp
);
3119 if (tls_fix
->exp
.X_op
== O_symbol
)
3121 if (strncasecmp (input_line_pointer
, "@tlsgd)", 7) == 0)
3122 tls_fix
->reloc
= BFD_RELOC_PPC_TLSGD
;
3123 else if (strncasecmp (input_line_pointer
, "@tlsld)", 7) == 0)
3124 tls_fix
->reloc
= BFD_RELOC_PPC_TLSLD
;
3125 if (tls_fix
->reloc
!= BFD_RELOC_NONE
)
3127 input_line_pointer
+= 7;
3129 *str
= input_line_pointer
;
3132 input_line_pointer
= hold
;
3134 return tls_fix
->reloc
!= BFD_RELOC_NONE
;
3138 /* This routine is called for each instruction to be assembled. */
3141 md_assemble (char *str
)
3144 const struct powerpc_opcode
*opcode
;
3146 const unsigned char *opindex_ptr
;
3149 struct ppc_fixup fixups
[MAX_INSN_FIXUPS
];
3154 unsigned int insn_length
;
3156 /* Get the opcode. */
3157 for (s
= str
; *s
!= '\0' && ! ISSPACE (*s
); s
++)
3162 /* Look up the opcode in the hash table. */
3163 opcode
= (const struct powerpc_opcode
*) hash_find (ppc_hash
, str
);
3164 if (opcode
== (const struct powerpc_opcode
*) NULL
)
3166 const struct powerpc_macro
*macro
;
3168 macro
= (const struct powerpc_macro
*) hash_find (ppc_macro_hash
, str
);
3169 if (macro
== (const struct powerpc_macro
*) NULL
)
3170 as_bad (_("unrecognized opcode: `%s'"), str
);
3172 ppc_macro (s
, macro
);
3174 ppc_clear_labels ();
3178 insn
= opcode
->opcode
;
3179 if (!target_big_endian
3180 && ((insn
& ~(1 << 26)) == 46u << 26
3181 || (insn
& ~(0xc0 << 1)) == (31u << 26 | 533 << 1)))
3183 /* lmw, stmw, lswi, lswx, stswi, stswx */
3184 as_bad (_("`%s' invalid when little-endian"), str
);
3185 ppc_clear_labels ();
3190 while (ISSPACE (*str
))
3193 /* PowerPC operands are just expressions. The only real issue is
3194 that a few operand types are optional. If an instruction has
3195 multiple optional operands and one is omitted, then all optional
3196 operands past the first omitted one must also be omitted. */
3197 int num_optional_operands
= 0;
3198 int num_optional_provided
= 0;
3200 /* Gather the operands. */
3204 for (opindex_ptr
= opcode
->operands
; *opindex_ptr
!= 0; opindex_ptr
++)
3206 const struct powerpc_operand
*operand
;
3212 if (next_opindex
== 0)
3213 operand
= &powerpc_operands
[*opindex_ptr
];
3216 operand
= &powerpc_operands
[next_opindex
];
3221 /* If this is an optional operand, and we are skipping it, just
3222 insert the default value, usually a zero. */
3223 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0
3224 && !((operand
->flags
& PPC_OPERAND_OPTIONAL32
) != 0 && ppc_obj64
))
3226 if (num_optional_operands
== 0)
3228 const unsigned char *optr
;
3234 for (optr
= opindex_ptr
; *optr
!= 0; optr
++)
3236 const struct powerpc_operand
*op
;
3237 op
= &powerpc_operands
[*optr
];
3241 if ((op
->flags
& PPC_OPERAND_OPTIONAL
) != 0
3242 && !((op
->flags
& PPC_OPERAND_OPTIONAL32
) != 0
3244 ++num_optional_operands
;
3246 if (s
!= NULL
&& *s
!= '\0')
3250 /* Look for the start of the next operand. */
3251 if ((op
->flags
& PPC_OPERAND_PARENS
) != 0)
3252 s
= strpbrk (s
, "(,");
3254 s
= strchr (s
, ',');
3260 omitted
= total
- provided
;
3261 num_optional_provided
= num_optional_operands
- omitted
;
3263 if (--num_optional_provided
< 0)
3265 int64_t val
= ppc_optional_operand_value (operand
, insn
, ppc_cpu
,
3266 num_optional_provided
);
3267 if (operand
->insert
)
3269 insn
= (*operand
->insert
) (insn
, val
, ppc_cpu
, &errmsg
);
3270 if (errmsg
!= (const char *) NULL
)
3271 as_bad ("%s", errmsg
);
3273 else if (operand
->shift
>= 0)
3274 insn
|= (val
& operand
->bitm
) << operand
->shift
;
3276 insn
|= (val
& operand
->bitm
) >> -operand
->shift
;
3278 if ((operand
->flags
& PPC_OPERAND_NEXT
) != 0)
3279 next_opindex
= *opindex_ptr
+ 1;
3284 /* Gather the operand. */
3285 hold
= input_line_pointer
;
3286 input_line_pointer
= str
;
3289 && (((operand
->flags
& PPC_OPERAND_CR_BIT
) != 0)
3290 || ((operand
->flags
& PPC_OPERAND_CR_REG
) != 0)))
3291 || !register_name (&ex
))
3293 char save_lex
= lex_type
['%'];
3295 if (((operand
->flags
& PPC_OPERAND_CR_REG
) != 0)
3296 || (operand
->flags
& PPC_OPERAND_CR_BIT
) != 0)
3299 lex_type
['%'] |= LEX_BEGIN_NAME
;
3303 lex_type
['%'] = save_lex
;
3306 str
= input_line_pointer
;
3307 input_line_pointer
= hold
;
3309 if (ex
.X_op
== O_illegal
)
3310 as_bad (_("illegal operand"));
3311 else if (ex
.X_op
== O_absent
)
3312 as_bad (_("missing operand"));
3313 else if (ex
.X_op
== O_register
)
3317 & (PPC_OPERAND_GPR
| PPC_OPERAND_FPR
| PPC_OPERAND_VR
3318 | PPC_OPERAND_VSR
| PPC_OPERAND_CR_BIT
| PPC_OPERAND_CR_REG
3319 | PPC_OPERAND_SPR
| PPC_OPERAND_GQR
| PPC_OPERAND_ACC
)) != 0
3320 && !((ex
.X_md
& PPC_OPERAND_GPR
) != 0
3321 && ex
.X_add_number
!= 0
3322 && (operand
->flags
& PPC_OPERAND_GPR_0
) != 0))
3323 as_warn (_("invalid register expression"));
3324 insn
= ppc_insert_operand (insn
, operand
, ex
.X_add_number
,
3325 ppc_cpu
, (char *) NULL
, 0);
3327 else if (ex
.X_op
== O_constant
)
3330 /* Allow @HA, @L, @H on constants. */
3331 bfd_reloc_code_real_type reloc
;
3332 char *orig_str
= str
;
3334 if ((reloc
= ppc_elf_suffix (&str
, &ex
)) != BFD_RELOC_NONE
)
3341 case BFD_RELOC_LO16
:
3342 ex
.X_add_number
&= 0xffff;
3343 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3344 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3347 case BFD_RELOC_HI16
:
3348 if (REPORT_OVERFLOW_HI
&& ppc_obj64
)
3350 /* PowerPC64 @h is tested for overflow. */
3351 ex
.X_add_number
= (addressT
) ex
.X_add_number
>> 16;
3352 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3354 addressT sign
= (((addressT
) -1 >> 16) + 1) >> 1;
3356 = ((addressT
) ex
.X_add_number
^ sign
) - sign
;
3362 case BFD_RELOC_PPC64_ADDR16_HIGH
:
3363 ex
.X_add_number
= PPC_HI (ex
.X_add_number
);
3364 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3365 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3368 case BFD_RELOC_HI16_S
:
3369 if (REPORT_OVERFLOW_HI
&& ppc_obj64
)
3371 /* PowerPC64 @ha is tested for overflow. */
3373 = ((addressT
) ex
.X_add_number
+ 0x8000) >> 16;
3374 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3376 addressT sign
= (((addressT
) -1 >> 16) + 1) >> 1;
3378 = ((addressT
) ex
.X_add_number
^ sign
) - sign
;
3384 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
3385 ex
.X_add_number
= PPC_HA (ex
.X_add_number
);
3386 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3387 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3390 case BFD_RELOC_PPC64_HIGHER
:
3391 ex
.X_add_number
= PPC_HIGHER (ex
.X_add_number
);
3392 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3393 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3396 case BFD_RELOC_PPC64_HIGHER_S
:
3397 ex
.X_add_number
= PPC_HIGHERA (ex
.X_add_number
);
3398 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3399 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3402 case BFD_RELOC_PPC64_HIGHEST
:
3403 ex
.X_add_number
= PPC_HIGHEST (ex
.X_add_number
);
3404 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3405 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3408 case BFD_RELOC_PPC64_HIGHEST_S
:
3409 ex
.X_add_number
= PPC_HIGHESTA (ex
.X_add_number
);
3410 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3411 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3414 #endif /* OBJ_ELF */
3415 insn
= ppc_insert_operand (insn
, operand
, ex
.X_add_number
,
3416 ppc_cpu
, (char *) NULL
, 0);
3420 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
3422 /* Look for a __tls_get_addr arg using the insane old syntax. */
3423 if (ex
.X_op
== O_symbol
&& *str
== '(' && fc
< MAX_INSN_FIXUPS
3424 && parse_tls_arg (&str
, &ex
, &fixups
[fc
]))
3426 fixups
[fc
].opindex
= *opindex_ptr
;
3430 if ((reloc
= ppc_elf_suffix (&str
, &ex
)) != BFD_RELOC_NONE
)
3432 /* If VLE-mode convert LO/HI/HA relocations. */
3433 if (opcode
->flags
& PPC_OPCODE_VLE
)
3435 uint64_t tmp_insn
= insn
& opcode
->mask
;
3437 int use_a_reloc
= (tmp_insn
== E_OR2I_INSN
3438 || tmp_insn
== E_AND2I_DOT_INSN
3439 || tmp_insn
== E_OR2IS_INSN
3440 || tmp_insn
== E_LI_INSN
3441 || tmp_insn
== E_LIS_INSN
3442 || tmp_insn
== E_AND2IS_DOT_INSN
);
3445 int use_d_reloc
= (tmp_insn
== E_ADD2I_DOT_INSN
3446 || tmp_insn
== E_ADD2IS_INSN
3447 || tmp_insn
== E_CMP16I_INSN
3448 || tmp_insn
== E_MULL2I_INSN
3449 || tmp_insn
== E_CMPL16I_INSN
3450 || tmp_insn
== E_CMPH16I_INSN
3451 || tmp_insn
== E_CMPHL16I_INSN
);
3458 case BFD_RELOC_PPC_EMB_SDA21
:
3459 reloc
= BFD_RELOC_PPC_VLE_SDA21
;
3462 case BFD_RELOC_LO16
:
3464 reloc
= BFD_RELOC_PPC_VLE_LO16D
;
3465 else if (use_a_reloc
)
3466 reloc
= BFD_RELOC_PPC_VLE_LO16A
;
3469 case BFD_RELOC_HI16
:
3471 reloc
= BFD_RELOC_PPC_VLE_HI16D
;
3472 else if (use_a_reloc
)
3473 reloc
= BFD_RELOC_PPC_VLE_HI16A
;
3476 case BFD_RELOC_HI16_S
:
3478 reloc
= BFD_RELOC_PPC_VLE_HA16D
;
3479 else if (use_a_reloc
)
3480 reloc
= BFD_RELOC_PPC_VLE_HA16A
;
3483 case BFD_RELOC_PPC_VLE_SDAREL_LO16A
:
3485 reloc
= BFD_RELOC_PPC_VLE_SDAREL_LO16D
;
3488 case BFD_RELOC_PPC_VLE_SDAREL_HI16A
:
3490 reloc
= BFD_RELOC_PPC_VLE_SDAREL_HI16D
;
3493 case BFD_RELOC_PPC_VLE_SDAREL_HA16A
:
3495 reloc
= BFD_RELOC_PPC_VLE_SDAREL_HA16D
;
3500 /* TLS and other tweaks. */
3506 case BFD_RELOC_PPC_TLS
:
3507 case BFD_RELOC_PPC64_TLS_PCREL
:
3508 if (!_bfd_elf_ppc_at_tls_transform (opcode
->opcode
, 0))
3509 as_bad (_("@tls may not be used with \"%s\" operands"),
3511 else if (operand
->shift
!= 11)
3512 as_bad (_("@tls may only be used in last operand"));
3514 insn
= ppc_insert_operand (insn
, operand
,
3516 ppc_cpu
, (char *) NULL
, 0);
3519 /* We'll only use the 32 (or 64) bit form of these relocations
3520 in constants. Instructions get the 16 or 34 bit form. */
3521 case BFD_RELOC_PPC_DTPREL
:
3522 if (operand
->bitm
== 0x3ffffffffULL
)
3523 reloc
= BFD_RELOC_PPC64_DTPREL34
;
3525 reloc
= BFD_RELOC_PPC_DTPREL16
;
3528 case BFD_RELOC_PPC_TPREL
:
3529 if (operand
->bitm
== 0x3ffffffffULL
)
3530 reloc
= BFD_RELOC_PPC64_TPREL34
;
3532 reloc
= BFD_RELOC_PPC_TPREL16
;
3535 case BFD_RELOC_PPC64_PCREL34
:
3536 if (operand
->bitm
== 0xfffffffULL
)
3538 reloc
= BFD_RELOC_PPC64_PCREL28
;
3542 case BFD_RELOC_PPC64_GOT_PCREL34
:
3543 case BFD_RELOC_PPC64_PLT_PCREL34
:
3544 case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
:
3545 case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
:
3546 case BFD_RELOC_PPC64_GOT_TPREL_PCREL34
:
3547 case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
:
3548 if (operand
->bitm
!= 0x3ffffffffULL
3549 || (operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
3550 as_warn (_("%s unsupported on this instruction"), "@pcrel");
3553 case BFD_RELOC_LO16
:
3554 if (operand
->bitm
== 0x3ffffffffULL
3555 && (operand
->flags
& PPC_OPERAND_NEGATIVE
) == 0)
3556 reloc
= BFD_RELOC_PPC64_D34_LO
;
3557 else if ((operand
->bitm
| 0xf) != 0xffff
3558 || operand
->shift
!= 0
3559 || (operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
3560 as_warn (_("%s unsupported on this instruction"), "@l");
3563 case BFD_RELOC_HI16
:
3564 if (operand
->bitm
== 0x3ffffffffULL
3565 && (operand
->flags
& PPC_OPERAND_NEGATIVE
) == 0)
3566 reloc
= BFD_RELOC_PPC64_D34_HI30
;
3567 else if (operand
->bitm
!= 0xffff
3568 || operand
->shift
!= 0
3569 || (operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
3570 as_warn (_("%s unsupported on this instruction"), "@h");
3573 case BFD_RELOC_HI16_S
:
3574 if (operand
->bitm
== 0x3ffffffffULL
3575 && (operand
->flags
& PPC_OPERAND_NEGATIVE
) == 0)
3576 reloc
= BFD_RELOC_PPC64_D34_HA30
;
3577 else if (operand
->bitm
== 0xffff
3578 && operand
->shift
== (int) PPC_OPSHIFT_INV
3579 && opcode
->opcode
== (19 << 26) + (2 << 1))
3581 reloc
= BFD_RELOC_PPC_16DX_HA
;
3582 else if (operand
->bitm
!= 0xffff
3583 || operand
->shift
!= 0
3584 || (operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
3585 as_warn (_("%s unsupported on this instruction"), "@ha");
3588 #endif /* OBJ_ELF */
3590 if (reloc
!= BFD_RELOC_NONE
)
3592 /* Determine a BFD reloc value based on the operand information.
3593 We are only prepared to turn a few of the operands into
3595 else if ((operand
->flags
& (PPC_OPERAND_RELATIVE
3596 | PPC_OPERAND_ABSOLUTE
)) != 0
3597 && operand
->bitm
== 0x3fffffc
3598 && operand
->shift
== 0)
3599 reloc
= BFD_RELOC_PPC_B26
;
3600 else if ((operand
->flags
& (PPC_OPERAND_RELATIVE
3601 | PPC_OPERAND_ABSOLUTE
)) != 0
3602 && operand
->bitm
== 0xfffc
3603 && operand
->shift
== 0)
3604 reloc
= BFD_RELOC_PPC_B16
;
3605 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0
3606 && operand
->bitm
== 0x1fe
3607 && operand
->shift
== -1)
3608 reloc
= BFD_RELOC_PPC_VLE_REL8
;
3609 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0
3610 && operand
->bitm
== 0xfffe
3611 && operand
->shift
== 0)
3612 reloc
= BFD_RELOC_PPC_VLE_REL15
;
3613 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0
3614 && operand
->bitm
== 0x1fffffe
3615 && operand
->shift
== 0)
3616 reloc
= BFD_RELOC_PPC_VLE_REL24
;
3617 else if ((operand
->flags
& PPC_OPERAND_NEGATIVE
) == 0
3618 && (operand
->bitm
& 0xfff0) == 0xfff0
3619 && operand
->shift
== 0)
3621 reloc
= BFD_RELOC_16
;
3622 #if defined OBJ_XCOFF || defined OBJ_ELF
3623 /* Note: the symbol may be not yet defined. */
3624 if ((operand
->flags
& PPC_OPERAND_PARENS
) != 0
3625 && ppc_is_toc_sym (ex
.X_add_symbol
))
3627 reloc
= BFD_RELOC_PPC_TOC16
;
3629 as_warn (_("assuming %s on symbol"),
3630 ppc_obj64
? "@toc" : "@xgot");
3635 else if (operand
->bitm
== 0x3ffffffffULL
)
3636 reloc
= BFD_RELOC_PPC64_D34
;
3637 else if (operand
->bitm
== 0xfffffffULL
)
3638 reloc
= BFD_RELOC_PPC64_D28
;
3640 /* For the absolute forms of branches, convert the PC
3641 relative form back into the absolute. */
3642 if ((operand
->flags
& PPC_OPERAND_ABSOLUTE
) != 0)
3646 case BFD_RELOC_PPC_B26
:
3647 reloc
= BFD_RELOC_PPC_BA26
;
3649 case BFD_RELOC_PPC_B16
:
3650 reloc
= BFD_RELOC_PPC_BA16
;
3653 case BFD_RELOC_PPC_B16_BRTAKEN
:
3654 reloc
= BFD_RELOC_PPC_BA16_BRTAKEN
;
3656 case BFD_RELOC_PPC_B16_BRNTAKEN
:
3657 reloc
= BFD_RELOC_PPC_BA16_BRNTAKEN
;
3668 case BFD_RELOC_PPC_TOC16
:
3669 toc_reloc_types
|= has_small_toc_reloc
;
3671 case BFD_RELOC_PPC64_TOC16_LO
:
3672 case BFD_RELOC_PPC64_TOC16_HI
:
3673 case BFD_RELOC_PPC64_TOC16_HA
:
3674 toc_reloc_types
|= has_large_toc_reloc
;
3681 && (operand
->flags
& (PPC_OPERAND_DS
| PPC_OPERAND_DQ
)) != 0)
3686 reloc
= BFD_RELOC_PPC64_ADDR16_DS
;
3689 case BFD_RELOC_LO16
:
3690 reloc
= BFD_RELOC_PPC64_ADDR16_LO_DS
;
3693 case BFD_RELOC_16_GOTOFF
:
3694 reloc
= BFD_RELOC_PPC64_GOT16_DS
;
3697 case BFD_RELOC_LO16_GOTOFF
:
3698 reloc
= BFD_RELOC_PPC64_GOT16_LO_DS
;
3701 case BFD_RELOC_LO16_PLTOFF
:
3702 reloc
= BFD_RELOC_PPC64_PLT16_LO_DS
;
3705 case BFD_RELOC_16_BASEREL
:
3706 reloc
= BFD_RELOC_PPC64_SECTOFF_DS
;
3709 case BFD_RELOC_LO16_BASEREL
:
3710 reloc
= BFD_RELOC_PPC64_SECTOFF_LO_DS
;
3713 case BFD_RELOC_PPC_TOC16
:
3714 reloc
= BFD_RELOC_PPC64_TOC16_DS
;
3717 case BFD_RELOC_PPC64_TOC16_LO
:
3718 reloc
= BFD_RELOC_PPC64_TOC16_LO_DS
;
3721 case BFD_RELOC_PPC64_PLTGOT16
:
3722 reloc
= BFD_RELOC_PPC64_PLTGOT16_DS
;
3725 case BFD_RELOC_PPC64_PLTGOT16_LO
:
3726 reloc
= BFD_RELOC_PPC64_PLTGOT16_LO_DS
;
3729 case BFD_RELOC_PPC_DTPREL16
:
3730 reloc
= BFD_RELOC_PPC64_DTPREL16_DS
;
3733 case BFD_RELOC_PPC_DTPREL16_LO
:
3734 reloc
= BFD_RELOC_PPC64_DTPREL16_LO_DS
;
3737 case BFD_RELOC_PPC_TPREL16
:
3738 reloc
= BFD_RELOC_PPC64_TPREL16_DS
;
3741 case BFD_RELOC_PPC_TPREL16_LO
:
3742 reloc
= BFD_RELOC_PPC64_TPREL16_LO_DS
;
3745 case BFD_RELOC_PPC_GOT_DTPREL16
:
3746 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
3747 case BFD_RELOC_PPC_GOT_TPREL16
:
3748 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
3752 as_bad (_("unsupported relocation for DS offset field"));
3757 /* Look for a __tls_get_addr arg after any __tls_get_addr
3758 modifiers like @plt. This fixup must be emitted before
3759 the usual call fixup. */
3760 if (ex
.X_op
== O_symbol
&& *str
== '(' && fc
< MAX_INSN_FIXUPS
3761 && parse_tls_arg (&str
, &ex
, &fixups
[fc
]))
3763 fixups
[fc
].opindex
= *opindex_ptr
;
3768 /* We need to generate a fixup for this expression. */
3769 if (fc
>= MAX_INSN_FIXUPS
)
3770 as_fatal (_("too many fixups"));
3771 fixups
[fc
].exp
= ex
;
3772 fixups
[fc
].opindex
= *opindex_ptr
;
3773 fixups
[fc
].reloc
= reloc
;
3781 /* If expecting more operands, then we want to see "),". */
3782 if (*str
== endc
&& opindex_ptr
[1] != 0)
3786 while (ISSPACE (*str
));
3790 else if ((operand
->flags
& PPC_OPERAND_PARENS
) != 0)
3795 /* The call to expression should have advanced str past any
3803 else if (*str
!= '\0')
3805 as_bad (_("syntax error; found `%c', expected `%c'"), *str
, endc
);
3808 else if (endc
== ')')
3810 as_bad (_("syntax error; end of line, expected `%c'"), endc
);
3815 while (ISSPACE (*str
))
3819 as_bad (_("junk at end of line: `%s'"), str
);
3822 /* Do we need/want an APUinfo section? */
3823 if ((ppc_cpu
& (PPC_OPCODE_E500
| PPC_OPCODE_E500MC
| PPC_OPCODE_VLE
)) != 0
3826 /* These are all version "1". */
3827 if (opcode
->flags
& PPC_OPCODE_SPE
)
3828 ppc_apuinfo_section_add (PPC_APUINFO_SPE
, 1);
3829 if (opcode
->flags
& PPC_OPCODE_ISEL
)
3830 ppc_apuinfo_section_add (PPC_APUINFO_ISEL
, 1);
3831 if (opcode
->flags
& PPC_OPCODE_EFS
)
3832 ppc_apuinfo_section_add (PPC_APUINFO_EFS
, 1);
3833 if (opcode
->flags
& PPC_OPCODE_BRLOCK
)
3834 ppc_apuinfo_section_add (PPC_APUINFO_BRLOCK
, 1);
3835 if (opcode
->flags
& PPC_OPCODE_PMR
)
3836 ppc_apuinfo_section_add (PPC_APUINFO_PMR
, 1);
3837 if (opcode
->flags
& PPC_OPCODE_CACHELCK
)
3838 ppc_apuinfo_section_add (PPC_APUINFO_CACHELCK
, 1);
3839 if (opcode
->flags
& PPC_OPCODE_RFMCI
)
3840 ppc_apuinfo_section_add (PPC_APUINFO_RFMCI
, 1);
3841 /* Only set the VLE flag if the instruction has been pulled via
3842 the VLE instruction set. This way the flag is guaranteed to
3843 be set for VLE-only instructions or for VLE-only processors,
3844 however it'll remain clear for dual-mode instructions on
3845 dual-mode and, more importantly, standard-mode processors. */
3846 if ((ppc_cpu
& opcode
->flags
) == PPC_OPCODE_VLE
)
3848 ppc_apuinfo_section_add (PPC_APUINFO_VLE
, 1);
3849 if (elf_section_data (now_seg
) != NULL
)
3850 elf_section_data (now_seg
)->this_hdr
.sh_flags
|= SHF_PPC_VLE
;
3855 /* Write out the instruction. */
3858 if ((ppc_cpu
& PPC_OPCODE_VLE
) != 0)
3859 /* All instructions can start on a 2 byte boundary for VLE. */
3862 if (frag_now
->insn_addr
!= addr_mask
)
3864 /* Don't emit instructions to a frag started for data, or for a
3865 CPU differing in VLE mode. Data is allowed to be misaligned,
3866 and it's possible to start a new frag in the middle of
3868 frag_wane (frag_now
);
3872 /* Check that insns within the frag are aligned. ppc_frag_check
3873 will ensure that the frag start address is aligned. */
3874 if ((frag_now_fix () & addr_mask
) != 0)
3875 as_bad (_("instruction address is not a multiple of %d"), addr_mask
+ 1);
3877 /* Differentiate between two, four, and eight byte insns. */
3879 if ((ppc_cpu
& PPC_OPCODE_VLE
) != 0 && PPC_OP_SE_VLE (insn
))
3881 else if ((opcode
->flags
& PPC_OPCODE_POWER10
) != 0
3882 && PPC_PREFIX_P (insn
))
3884 struct insn_label_list
*l
;
3888 /* 8-byte prefix instructions are not allowed to cross 64-byte
3890 frag_align_code (6, 4);
3891 record_alignment (now_seg
, 6);
3893 /* Update "dot" in any expressions used by this instruction, and
3894 a label attached to the instruction. By "attached" we mean
3895 on the same source line as the instruction and without any
3896 intervening semicolons. */
3897 dot_value
= frag_now_fix ();
3898 dot_frag
= frag_now
;
3899 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
3901 symbol_set_frag (l
->label
, dot_frag
);
3902 S_SET_VALUE (l
->label
, dot_value
);
3906 ppc_clear_labels ();
3908 f
= frag_more (insn_length
);
3909 frag_now
->insn_addr
= addr_mask
;
3911 /* The prefix part of an 8-byte instruction always occupies the lower
3912 addressed word in a doubleword, regardless of endianness. */
3913 if (!target_big_endian
&& insn_length
== 8)
3915 md_number_to_chars (f
, PPC_GET_PREFIX (insn
), 4);
3916 md_number_to_chars (f
+ 4, PPC_GET_SUFFIX (insn
), 4);
3919 md_number_to_chars (f
, insn
, insn_length
);
3923 last_subseg
= now_subseg
;
3926 dwarf2_emit_insn (insn_length
);
3929 /* Create any fixups. */
3930 for (i
= 0; i
< fc
; i
++)
3933 if (fixups
[i
].reloc
!= BFD_RELOC_NONE
)
3936 unsigned int size
= fixup_size (fixups
[i
].reloc
, &pcrel
);
3937 int offset
= target_big_endian
? (insn_length
- size
) : 0;
3939 fixP
= fix_new_exp (frag_now
,
3940 f
- frag_now
->fr_literal
+ offset
,
3948 const struct powerpc_operand
*operand
;
3950 operand
= &powerpc_operands
[fixups
[i
].opindex
];
3951 fixP
= fix_new_exp (frag_now
,
3952 f
- frag_now
->fr_literal
,
3955 (operand
->flags
& PPC_OPERAND_RELATIVE
) != 0,
3958 fixP
->fx_pcrel_adjust
= fixups
[i
].opindex
;
3962 /* Handle a macro. Gather all the operands, transform them as
3963 described by the macro, and call md_assemble recursively. All the
3964 operands are separated by commas; we don't accept parentheses
3965 around operands here. */
3968 ppc_macro (char *str
, const struct powerpc_macro
*macro
)
3979 /* Gather the users operands into the operands array. */
3984 if (count
>= sizeof operands
/ sizeof operands
[0])
3986 operands
[count
++] = s
;
3987 s
= strchr (s
, ',');
3988 if (s
== (char *) NULL
)
3993 if (count
!= macro
->operands
)
3995 as_bad (_("wrong number of operands"));
3999 /* Work out how large the string must be (the size is unbounded
4000 because it includes user input). */
4002 format
= macro
->format
;
4003 while (*format
!= '\0')
4012 arg
= strtol (format
+ 1, &send
, 10);
4013 know (send
!= format
&& arg
< count
);
4014 len
+= strlen (operands
[arg
]);
4019 /* Put the string together. */
4020 complete
= s
= XNEWVEC (char, len
+ 1);
4021 format
= macro
->format
;
4022 while (*format
!= '\0')
4028 arg
= strtol (format
+ 1, &send
, 10);
4029 strcpy (s
, operands
[arg
]);
4036 /* Assemble the constructed instruction. */
4037 md_assemble (complete
);
4042 /* For ELF, add support for SHT_ORDERED. */
4045 ppc_section_type (char *str
, size_t len
)
4047 if (len
== 7 && strncmp (str
, "ordered", 7) == 0)
4054 ppc_section_flags (flagword flags
, bfd_vma attr ATTRIBUTE_UNUSED
, int type
)
4056 if (type
== SHT_ORDERED
)
4057 flags
|= SEC_ALLOC
| SEC_LOAD
| SEC_SORT_ENTRIES
;
4063 ppc_elf_section_letter (int letter
, const char **ptrmsg
)
4068 *ptrmsg
= _("bad .section directive: want a,e,v,w,x,M,S,G,T in string");
4071 #endif /* OBJ_ELF */
4074 /* Pseudo-op handling. */
4076 /* The .byte pseudo-op. This is similar to the normal .byte
4077 pseudo-op, but it can also take a single ASCII string. */
4080 ppc_byte (int ignore ATTRIBUTE_UNUSED
)
4084 if (*input_line_pointer
!= '\"')
4090 /* Gather characters. A real double quote is doubled. Unusual
4091 characters are not permitted. */
4092 ++input_line_pointer
;
4097 c
= *input_line_pointer
++;
4101 if (*input_line_pointer
!= '\"')
4103 ++input_line_pointer
;
4106 FRAG_APPEND_1_CHAR (c
);
4110 if (warn_476
&& count
!= 0 && (now_seg
->flags
& SEC_CODE
) != 0)
4111 as_warn (_("data in executable section"));
4112 demand_empty_rest_of_line ();
4117 /* XCOFF specific pseudo-op handling. */
4119 /* This is set if we are creating a .stabx symbol, since we don't want
4120 to handle symbol suffixes for such symbols. */
4121 static bfd_boolean ppc_stab_symbol
;
4123 /* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common
4124 symbols in the .bss segment as though they were local common
4125 symbols, and uses a different smclas. The native Aix 4.3.3 assembler
4126 aligns .comm and .lcomm to 4 bytes. */
4129 ppc_comm (int lcomm
)
4131 asection
*current_seg
= now_seg
;
4132 subsegT current_subseg
= now_subseg
;
4138 symbolS
*lcomm_sym
= NULL
;
4142 endc
= get_symbol_name (&name
);
4143 end_name
= input_line_pointer
;
4144 (void) restore_line_pointer (endc
);
4146 if (*input_line_pointer
!= ',')
4148 as_bad (_("missing size"));
4149 ignore_rest_of_line ();
4152 ++input_line_pointer
;
4154 size
= get_absolute_expression ();
4157 as_bad (_("negative size"));
4158 ignore_rest_of_line ();
4164 /* The third argument to .comm is the alignment. */
4165 if (*input_line_pointer
!= ',')
4169 ++input_line_pointer
;
4170 align
= get_absolute_expression ();
4173 as_warn (_("ignoring bad alignment"));
4183 /* The third argument to .lcomm appears to be the real local
4184 common symbol to create. References to the symbol named in
4185 the first argument are turned into references to the third
4187 if (*input_line_pointer
!= ',')
4189 as_bad (_("missing real symbol name"));
4190 ignore_rest_of_line ();
4193 ++input_line_pointer
;
4195 lcomm_endc
= get_symbol_name (&lcomm_name
);
4197 lcomm_sym
= symbol_find_or_make (lcomm_name
);
4199 (void) restore_line_pointer (lcomm_endc
);
4201 /* The fourth argument to .lcomm is the alignment. */
4202 if (*input_line_pointer
!= ',')
4211 ++input_line_pointer
;
4212 align
= get_absolute_expression ();
4215 as_warn (_("ignoring bad alignment"));
4222 sym
= symbol_find_or_make (name
);
4225 if (S_IS_DEFINED (sym
)
4226 || S_GET_VALUE (sym
) != 0)
4228 as_bad (_("attempt to redefine symbol"));
4229 ignore_rest_of_line ();
4233 record_alignment (bss_section
, align
);
4236 || ! S_IS_DEFINED (lcomm_sym
))
4245 S_SET_EXTERNAL (sym
);
4249 symbol_get_tc (lcomm_sym
)->output
= 1;
4250 def_sym
= lcomm_sym
;
4254 subseg_set (bss_section
, 1);
4255 frag_align (align
, 0, 0);
4257 symbol_set_frag (def_sym
, frag_now
);
4258 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, def_sym
,
4259 def_size
, (char *) NULL
);
4261 S_SET_SEGMENT (def_sym
, bss_section
);
4262 symbol_get_tc (def_sym
)->align
= align
;
4266 /* Align the size of lcomm_sym. */
4267 symbol_get_frag (lcomm_sym
)->fr_offset
=
4268 ((symbol_get_frag (lcomm_sym
)->fr_offset
+ (1 << align
) - 1)
4269 &~ ((1 << align
) - 1));
4270 if (align
> symbol_get_tc (lcomm_sym
)->align
)
4271 symbol_get_tc (lcomm_sym
)->align
= align
;
4276 /* Make sym an offset from lcomm_sym. */
4277 S_SET_SEGMENT (sym
, bss_section
);
4278 symbol_set_frag (sym
, symbol_get_frag (lcomm_sym
));
4279 S_SET_VALUE (sym
, symbol_get_frag (lcomm_sym
)->fr_offset
);
4280 symbol_get_frag (lcomm_sym
)->fr_offset
+= size
;
4283 subseg_set (current_seg
, current_subseg
);
4285 demand_empty_rest_of_line ();
4288 /* The .csect pseudo-op. This switches us into a different
4289 subsegment. The first argument is a symbol whose value is the
4290 start of the .csect. In COFF, csect symbols get special aux
4291 entries defined by the x_csect field of union internal_auxent. The
4292 optional second argument is the alignment (the default is 2). */
4295 ppc_csect (int ignore ATTRIBUTE_UNUSED
)
4302 endc
= get_symbol_name (&name
);
4304 sym
= symbol_find_or_make (name
);
4306 (void) restore_line_pointer (endc
);
4308 if (S_GET_NAME (sym
)[0] == '\0')
4310 /* An unnamed csect is assumed to be [PR]. */
4311 symbol_get_tc (sym
)->symbol_class
= XMC_PR
;
4315 if (*input_line_pointer
== ',')
4317 ++input_line_pointer
;
4318 align
= get_absolute_expression ();
4321 ppc_change_csect (sym
, align
);
4323 demand_empty_rest_of_line ();
4326 /* Change to a different csect. */
4329 ppc_change_csect (symbolS
*sym
, offsetT align
)
4331 if (S_IS_DEFINED (sym
))
4332 subseg_set (S_GET_SEGMENT (sym
), symbol_get_tc (sym
)->subseg
);
4342 /* This is a new csect. We need to look at the symbol class to
4343 figure out whether it should go in the text section or the
4347 switch (symbol_get_tc (sym
)->symbol_class
)
4357 S_SET_SEGMENT (sym
, text_section
);
4358 symbol_get_tc (sym
)->subseg
= ppc_text_subsegment
;
4359 ++ppc_text_subsegment
;
4360 list_ptr
= &ppc_text_csects
;
4370 if (ppc_toc_csect
!= NULL
4371 && (symbol_get_tc (ppc_toc_csect
)->subseg
+ 1
4372 == ppc_data_subsegment
))
4374 S_SET_SEGMENT (sym
, data_section
);
4375 symbol_get_tc (sym
)->subseg
= ppc_data_subsegment
;
4376 ++ppc_data_subsegment
;
4377 list_ptr
= &ppc_data_csects
;
4383 /* We set the obstack chunk size to a small value before
4384 changing subsegments, so that we don't use a lot of memory
4385 space for what may be a small section. */
4386 hold_chunksize
= chunksize
;
4389 sec
= subseg_new (segment_name (S_GET_SEGMENT (sym
)),
4390 symbol_get_tc (sym
)->subseg
);
4392 chunksize
= hold_chunksize
;
4395 ppc_after_toc_frag
= frag_now
;
4397 record_alignment (sec
, align
);
4399 frag_align_code (align
, 0);
4401 frag_align (align
, 0, 0);
4403 symbol_set_frag (sym
, frag_now
);
4404 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
4406 symbol_get_tc (sym
)->align
= align
;
4407 symbol_get_tc (sym
)->output
= 1;
4408 symbol_get_tc (sym
)->within
= sym
;
4410 for (list
= *list_ptr
;
4411 symbol_get_tc (list
)->next
!= (symbolS
*) NULL
;
4412 list
= symbol_get_tc (list
)->next
)
4414 symbol_get_tc (list
)->next
= sym
;
4416 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4417 symbol_append (sym
, symbol_get_tc (list
)->within
, &symbol_rootP
,
4421 ppc_current_csect
= sym
;
4425 ppc_change_debug_section (unsigned int idx
, subsegT subseg
)
4429 const struct xcoff_dwsect_name
*dw
= &xcoff_dwsect_names
[idx
];
4431 sec
= subseg_new (dw
->name
, subseg
);
4432 oldflags
= bfd_section_flags (sec
);
4433 if (oldflags
== SEC_NO_FLAGS
)
4435 /* Just created section. */
4436 gas_assert (dw_sections
[idx
].sect
== NULL
);
4438 bfd_set_section_flags (sec
, SEC_DEBUGGING
);
4439 bfd_set_section_alignment (sec
, 0);
4440 dw_sections
[idx
].sect
= sec
;
4443 /* Not anymore in a csect. */
4444 ppc_current_csect
= NULL
;
4447 /* The .dwsect pseudo-op. Defines a DWARF section. Syntax is:
4448 .dwsect flag [, opt-label ]
4452 ppc_dwsect (int ignore ATTRIBUTE_UNUSED
)
4456 const struct xcoff_dwsect_name
*dw
;
4457 struct dw_subsection
*subseg
;
4458 struct dw_section
*dws
;
4462 flag
= get_absolute_expression ();
4464 for (i
= 0; i
< XCOFF_DWSECT_NBR_NAMES
; i
++)
4465 if (xcoff_dwsect_names
[i
].flag
== flag
)
4467 dw
= &xcoff_dwsect_names
[i
];
4471 /* Parse opt-label. */
4472 if (*input_line_pointer
== ',')
4477 ++input_line_pointer
;
4479 c
= get_symbol_name (&label
);
4480 opt_label
= symbol_find_or_make (label
);
4481 (void) restore_line_pointer (c
);
4486 demand_empty_rest_of_line ();
4488 /* Return now in case of unknown subsection. */
4491 as_bad (_("no known dwarf XCOFF section for flag 0x%08x\n"),
4496 /* Find the subsection. */
4497 dws
= &dw_sections
[i
];
4499 if (opt_label
!= NULL
&& S_IS_DEFINED (opt_label
))
4501 /* Sanity check (note that in theory S_GET_SEGMENT mustn't be null). */
4502 if (dws
->sect
== NULL
|| S_GET_SEGMENT (opt_label
) != dws
->sect
)
4504 as_bad (_("label %s was not defined in this dwarf section"),
4505 S_GET_NAME (opt_label
));
4506 subseg
= dws
->anon_subseg
;
4510 subseg
= symbol_get_tc (opt_label
)->u
.dw
;
4515 /* Switch to the subsection. */
4516 ppc_change_debug_section (i
, subseg
->subseg
);
4520 /* Create a new dw subsection. */
4521 subseg
= XNEW (struct dw_subsection
);
4523 if (opt_label
== NULL
)
4525 /* The anonymous one. */
4527 subseg
->link
= NULL
;
4528 dws
->anon_subseg
= subseg
;
4533 if (dws
->list_subseg
!= NULL
)
4534 subseg
->subseg
= dws
->list_subseg
->subseg
+ 1;
4538 subseg
->link
= dws
->list_subseg
;
4539 dws
->list_subseg
= subseg
;
4540 symbol_get_tc (opt_label
)->u
.dw
= subseg
;
4543 ppc_change_debug_section (i
, subseg
->subseg
);
4547 /* Add the length field. */
4548 expressionS
*exp
= &subseg
->end_exp
;
4551 if (opt_label
!= NULL
)
4552 symbol_set_value_now (opt_label
);
4554 /* Add the length field. Note that according to the AIX assembler
4555 manual, the size of the length field is 4 for powerpc32 but
4556 12 for powerpc64. */
4559 /* Write the 64bit marker. */
4560 md_number_to_chars (frag_more (4), -1, 4);
4563 exp
->X_op
= O_subtract
;
4564 exp
->X_op_symbol
= symbol_temp_new_now ();
4565 exp
->X_add_symbol
= symbol_temp_make ();
4567 sz
= ppc_obj64
? 8 : 4;
4568 exp
->X_add_number
= -sz
;
4569 emit_expr (exp
, sz
);
4574 /* This function handles the .text and .data pseudo-ops. These
4575 pseudo-ops aren't really used by XCOFF; we implement them for the
4576 convenience of people who aren't used to XCOFF. */
4579 ppc_section (int type
)
4586 else if (type
== 'd')
4591 sym
= symbol_find_or_make (name
);
4593 ppc_change_csect (sym
, 2);
4595 demand_empty_rest_of_line ();
4598 /* This function handles the .section pseudo-op. This is mostly to
4599 give an error, since XCOFF only supports .text, .data and .bss, but
4600 we do permit the user to name the text or data section. */
4603 ppc_named_section (int ignore ATTRIBUTE_UNUSED
)
4606 const char *real_name
;
4610 c
= get_symbol_name (&user_name
);
4612 if (strcmp (user_name
, ".text") == 0)
4613 real_name
= ".text[PR]";
4614 else if (strcmp (user_name
, ".data") == 0)
4615 real_name
= ".data[RW]";
4618 as_bad (_("the XCOFF file format does not support arbitrary sections"));
4619 (void) restore_line_pointer (c
);
4620 ignore_rest_of_line ();
4624 (void) restore_line_pointer (c
);
4626 sym
= symbol_find_or_make (real_name
);
4628 ppc_change_csect (sym
, 2);
4630 demand_empty_rest_of_line ();
4633 /* The .extern pseudo-op. We create an undefined symbol. */
4636 ppc_extern (int ignore ATTRIBUTE_UNUSED
)
4641 endc
= get_symbol_name (&name
);
4643 (void) symbol_find_or_make (name
);
4645 (void) restore_line_pointer (endc
);
4647 demand_empty_rest_of_line ();
4650 /* The .lglobl pseudo-op. Keep the symbol in the symbol table. */
4653 ppc_lglobl (int ignore ATTRIBUTE_UNUSED
)
4659 endc
= get_symbol_name (&name
);
4661 sym
= symbol_find_or_make (name
);
4663 (void) restore_line_pointer (endc
);
4665 symbol_get_tc (sym
)->output
= 1;
4667 demand_empty_rest_of_line ();
4670 /* The .ref pseudo-op. It takes a list of symbol names and inserts R_REF
4671 relocations at the beginning of the current csect.
4673 (In principle, there's no reason why the relocations _have_ to be at
4674 the beginning. Anywhere in the csect would do. However, inserting
4675 at the beginning is what the native assembler does, and it helps to
4676 deal with cases where the .ref statements follow the section contents.)
4678 ??? .refs don't work for empty .csects. However, the native assembler
4679 doesn't report an error in this case, and neither yet do we. */
4682 ppc_ref (int ignore ATTRIBUTE_UNUSED
)
4687 if (ppc_current_csect
== NULL
)
4689 as_bad (_(".ref outside .csect"));
4690 ignore_rest_of_line ();
4696 c
= get_symbol_name (&name
);
4698 fix_at_start (symbol_get_frag (ppc_current_csect
), 0,
4699 symbol_find_or_make (name
), 0, FALSE
, BFD_RELOC_NONE
);
4701 *input_line_pointer
= c
;
4702 SKIP_WHITESPACE_AFTER_NAME ();
4703 c
= *input_line_pointer
;
4706 input_line_pointer
++;
4708 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
4710 as_bad (_("missing symbol name"));
4711 ignore_rest_of_line ();
4718 demand_empty_rest_of_line ();
4721 /* The .rename pseudo-op. The RS/6000 assembler can rename symbols,
4722 although I don't know why it bothers. */
4725 ppc_rename (int ignore ATTRIBUTE_UNUSED
)
4732 endc
= get_symbol_name (&name
);
4734 sym
= symbol_find_or_make (name
);
4736 (void) restore_line_pointer (endc
);
4738 if (*input_line_pointer
!= ',')
4740 as_bad (_("missing rename string"));
4741 ignore_rest_of_line ();
4744 ++input_line_pointer
;
4746 symbol_get_tc (sym
)->real_name
= demand_copy_C_string (&len
);
4748 demand_empty_rest_of_line ();
4751 /* The .stabx pseudo-op. This is similar to a normal .stabs
4752 pseudo-op, but slightly different. A sample is
4753 .stabx "main:F-1",.main,142,0
4754 The first argument is the symbol name to create. The second is the
4755 value, and the third is the storage class. The fourth seems to be
4756 always zero, and I am assuming it is the type. */
4759 ppc_stabx (int ignore ATTRIBUTE_UNUSED
)
4766 name
= demand_copy_C_string (&len
);
4768 if (*input_line_pointer
!= ',')
4770 as_bad (_("missing value"));
4773 ++input_line_pointer
;
4775 ppc_stab_symbol
= TRUE
;
4776 sym
= symbol_make (name
);
4777 ppc_stab_symbol
= FALSE
;
4779 symbol_get_tc (sym
)->real_name
= name
;
4781 (void) expression (&exp
);
4788 as_bad (_("illegal .stabx expression; zero assumed"));
4789 exp
.X_add_number
= 0;
4792 S_SET_VALUE (sym
, (valueT
) exp
.X_add_number
);
4793 symbol_set_frag (sym
, &zero_address_frag
);
4797 if (S_GET_SEGMENT (exp
.X_add_symbol
) == undefined_section
)
4798 symbol_set_value_expression (sym
, &exp
);
4802 exp
.X_add_number
+ S_GET_VALUE (exp
.X_add_symbol
));
4803 symbol_set_frag (sym
, symbol_get_frag (exp
.X_add_symbol
));
4808 /* The value is some complex expression. This will probably
4809 fail at some later point, but this is probably the right
4810 thing to do here. */
4811 symbol_set_value_expression (sym
, &exp
);
4815 S_SET_SEGMENT (sym
, ppc_coff_debug_section
);
4816 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
4818 if (*input_line_pointer
!= ',')
4820 as_bad (_("missing class"));
4823 ++input_line_pointer
;
4825 S_SET_STORAGE_CLASS (sym
, get_absolute_expression ());
4827 if (*input_line_pointer
!= ',')
4829 as_bad (_("missing type"));
4832 ++input_line_pointer
;
4834 S_SET_DATA_TYPE (sym
, get_absolute_expression ());
4836 symbol_get_tc (sym
)->output
= 1;
4838 if (S_GET_STORAGE_CLASS (sym
) == C_STSYM
)
4843 .stabx "z",arrays_,133,0
4846 .comm arrays_,13768,3
4848 resolve_symbol_value will copy the exp's "within" into sym's when the
4849 offset is 0. Since this seems to be corner case problem,
4850 only do the correction for storage class C_STSYM. A better solution
4851 would be to have the tc field updated in ppc_symbol_new_hook. */
4853 if (exp
.X_op
== O_symbol
)
4855 if (ppc_current_block
== NULL
)
4856 as_bad (_(".stabx of storage class stsym must be within .bs/.es"));
4858 symbol_get_tc (sym
)->within
= ppc_current_block
;
4859 symbol_get_tc (exp
.X_add_symbol
)->within
= ppc_current_block
;
4863 if (exp
.X_op
!= O_symbol
4864 || ! S_IS_EXTERNAL (exp
.X_add_symbol
)
4865 || S_GET_SEGMENT (exp
.X_add_symbol
) != bss_section
)
4866 ppc_frob_label (sym
);
4869 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4870 symbol_append (sym
, exp
.X_add_symbol
, &symbol_rootP
, &symbol_lastP
);
4871 if (symbol_get_tc (ppc_current_csect
)->within
== exp
.X_add_symbol
)
4872 symbol_get_tc (ppc_current_csect
)->within
= sym
;
4875 demand_empty_rest_of_line ();
4878 /* The .function pseudo-op. This takes several arguments. The first
4879 argument seems to be the external name of the symbol. The second
4880 argument seems to be the label for the start of the function. gcc
4881 uses the same name for both. I have no idea what the third and
4882 fourth arguments are meant to be. The optional fifth argument is
4883 an expression for the size of the function. In COFF this symbol
4884 gets an aux entry like that used for a csect. */
4887 ppc_function (int ignore ATTRIBUTE_UNUSED
)
4895 endc
= get_symbol_name (&name
);
4897 /* Ignore any [PR] suffix. */
4898 name
= ppc_canonicalize_symbol_name (name
);
4899 s
= strchr (name
, '[');
4900 if (s
!= (char *) NULL
4901 && strcmp (s
+ 1, "PR]") == 0)
4904 ext_sym
= symbol_find_or_make (name
);
4906 (void) restore_line_pointer (endc
);
4908 if (*input_line_pointer
!= ',')
4910 as_bad (_("missing symbol name"));
4911 ignore_rest_of_line ();
4914 ++input_line_pointer
;
4916 endc
= get_symbol_name (&name
);
4918 lab_sym
= symbol_find_or_make (name
);
4920 (void) restore_line_pointer (endc
);
4922 if (ext_sym
!= lab_sym
)
4926 exp
.X_op
= O_symbol
;
4927 exp
.X_add_symbol
= lab_sym
;
4928 exp
.X_op_symbol
= NULL
;
4929 exp
.X_add_number
= 0;
4931 symbol_set_value_expression (ext_sym
, &exp
);
4934 if (symbol_get_tc (ext_sym
)->symbol_class
== -1)
4935 symbol_get_tc (ext_sym
)->symbol_class
= XMC_PR
;
4936 symbol_get_tc (ext_sym
)->output
= 1;
4938 if (*input_line_pointer
== ',')
4942 /* Ignore the third argument. */
4943 ++input_line_pointer
;
4945 if (*input_line_pointer
== ',')
4947 /* Ignore the fourth argument. */
4948 ++input_line_pointer
;
4950 if (*input_line_pointer
== ',')
4952 /* The fifth argument is the function size. */
4953 ++input_line_pointer
;
4954 symbol_get_tc (ext_sym
)->u
.size
= symbol_new
4955 ("L0\001", absolute_section
,(valueT
) 0, &zero_address_frag
);
4956 pseudo_set (symbol_get_tc (ext_sym
)->u
.size
);
4961 S_SET_DATA_TYPE (ext_sym
, DT_FCN
<< N_BTSHFT
);
4962 SF_SET_FUNCTION (ext_sym
);
4963 SF_SET_PROCESS (ext_sym
);
4964 coff_add_linesym (ext_sym
);
4966 demand_empty_rest_of_line ();
4969 /* The .bf pseudo-op. This is just like a COFF C_FCN symbol named
4970 ".bf". If the pseudo op .bi was seen before .bf, patch the .bi sym
4971 with the correct line number */
4973 static symbolS
*saved_bi_sym
= 0;
4976 ppc_bf (int ignore ATTRIBUTE_UNUSED
)
4980 sym
= symbol_make (".bf");
4981 S_SET_SEGMENT (sym
, text_section
);
4982 symbol_set_frag (sym
, frag_now
);
4983 S_SET_VALUE (sym
, frag_now_fix ());
4984 S_SET_STORAGE_CLASS (sym
, C_FCN
);
4986 coff_line_base
= get_absolute_expression ();
4988 S_SET_NUMBER_AUXILIARY (sym
, 1);
4989 SA_SET_SYM_LNNO (sym
, coff_line_base
);
4991 /* Line number for bi. */
4994 S_SET_VALUE (saved_bi_sym
, coff_n_line_nos
);
4999 symbol_get_tc (sym
)->output
= 1;
5001 ppc_frob_label (sym
);
5003 demand_empty_rest_of_line ();
5006 /* The .ef pseudo-op. This is just like a COFF C_FCN symbol named
5007 ".ef", except that the line number is absolute, not relative to the
5008 most recent ".bf" symbol. */
5011 ppc_ef (int ignore ATTRIBUTE_UNUSED
)
5015 sym
= symbol_make (".ef");
5016 S_SET_SEGMENT (sym
, text_section
);
5017 symbol_set_frag (sym
, frag_now
);
5018 S_SET_VALUE (sym
, frag_now_fix ());
5019 S_SET_STORAGE_CLASS (sym
, C_FCN
);
5020 S_SET_NUMBER_AUXILIARY (sym
, 1);
5021 SA_SET_SYM_LNNO (sym
, get_absolute_expression ());
5022 symbol_get_tc (sym
)->output
= 1;
5024 ppc_frob_label (sym
);
5026 demand_empty_rest_of_line ();
5029 /* The .bi and .ei pseudo-ops. These take a string argument and
5030 generates a C_BINCL or C_EINCL symbol, which goes at the start of
5031 the symbol list. The value of .bi will be know when the next .bf
5037 static symbolS
*last_biei
;
5044 name
= demand_copy_C_string (&len
);
5046 /* The value of these symbols is actually file offset. Here we set
5047 the value to the index into the line number entries. In
5048 ppc_frob_symbols we set the fix_line field, which will cause BFD
5049 to do the right thing. */
5051 sym
= symbol_make (name
);
5052 /* obj-coff.c currently only handles line numbers correctly in the
5054 S_SET_SEGMENT (sym
, text_section
);
5055 S_SET_VALUE (sym
, coff_n_line_nos
);
5056 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5058 S_SET_STORAGE_CLASS (sym
, ei
? C_EINCL
: C_BINCL
);
5059 symbol_get_tc (sym
)->output
= 1;
5067 for (look
= last_biei
? last_biei
: symbol_rootP
;
5068 (look
!= (symbolS
*) NULL
5069 && (S_GET_STORAGE_CLASS (look
) == C_FILE
5070 || S_GET_STORAGE_CLASS (look
) == C_BINCL
5071 || S_GET_STORAGE_CLASS (look
) == C_EINCL
));
5072 look
= symbol_next (look
))
5074 if (look
!= (symbolS
*) NULL
)
5076 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
5077 symbol_insert (sym
, look
, &symbol_rootP
, &symbol_lastP
);
5081 demand_empty_rest_of_line ();
5084 /* The .bs pseudo-op. This generates a C_BSTAT symbol named ".bs".
5085 There is one argument, which is a csect symbol. The value of the
5086 .bs symbol is the index of this csect symbol. */
5089 ppc_bs (int ignore ATTRIBUTE_UNUSED
)
5096 if (ppc_current_block
!= NULL
)
5097 as_bad (_("nested .bs blocks"));
5099 endc
= get_symbol_name (&name
);
5101 csect
= symbol_find_or_make (name
);
5103 (void) restore_line_pointer (endc
);
5105 sym
= symbol_make (".bs");
5106 S_SET_SEGMENT (sym
, now_seg
);
5107 S_SET_STORAGE_CLASS (sym
, C_BSTAT
);
5108 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5109 symbol_get_tc (sym
)->output
= 1;
5111 symbol_get_tc (sym
)->within
= csect
;
5113 ppc_frob_label (sym
);
5115 ppc_current_block
= sym
;
5117 demand_empty_rest_of_line ();
5120 /* The .es pseudo-op. Generate a C_ESTART symbol named .es. */
5123 ppc_es (int ignore ATTRIBUTE_UNUSED
)
5127 if (ppc_current_block
== NULL
)
5128 as_bad (_(".es without preceding .bs"));
5130 sym
= symbol_make (".es");
5131 S_SET_SEGMENT (sym
, now_seg
);
5132 S_SET_STORAGE_CLASS (sym
, C_ESTAT
);
5133 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5134 symbol_get_tc (sym
)->output
= 1;
5136 ppc_frob_label (sym
);
5138 ppc_current_block
= NULL
;
5140 demand_empty_rest_of_line ();
5143 /* The .bb pseudo-op. Generate a C_BLOCK symbol named .bb, with a
5147 ppc_bb (int ignore ATTRIBUTE_UNUSED
)
5151 sym
= symbol_make (".bb");
5152 S_SET_SEGMENT (sym
, text_section
);
5153 symbol_set_frag (sym
, frag_now
);
5154 S_SET_VALUE (sym
, frag_now_fix ());
5155 S_SET_STORAGE_CLASS (sym
, C_BLOCK
);
5157 S_SET_NUMBER_AUXILIARY (sym
, 1);
5158 SA_SET_SYM_LNNO (sym
, get_absolute_expression ());
5160 symbol_get_tc (sym
)->output
= 1;
5162 SF_SET_PROCESS (sym
);
5164 ppc_frob_label (sym
);
5166 demand_empty_rest_of_line ();
5169 /* The .eb pseudo-op. Generate a C_BLOCK symbol named .eb, with a
5173 ppc_eb (int ignore ATTRIBUTE_UNUSED
)
5177 sym
= symbol_make (".eb");
5178 S_SET_SEGMENT (sym
, text_section
);
5179 symbol_set_frag (sym
, frag_now
);
5180 S_SET_VALUE (sym
, frag_now_fix ());
5181 S_SET_STORAGE_CLASS (sym
, C_BLOCK
);
5182 S_SET_NUMBER_AUXILIARY (sym
, 1);
5183 SA_SET_SYM_LNNO (sym
, get_absolute_expression ());
5184 symbol_get_tc (sym
)->output
= 1;
5186 SF_SET_PROCESS (sym
);
5188 ppc_frob_label (sym
);
5190 demand_empty_rest_of_line ();
5193 /* The .bc pseudo-op. This just creates a C_BCOMM symbol with a
5197 ppc_bc (int ignore ATTRIBUTE_UNUSED
)
5203 name
= demand_copy_C_string (&len
);
5204 sym
= symbol_make (name
);
5205 S_SET_SEGMENT (sym
, ppc_coff_debug_section
);
5206 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5207 S_SET_STORAGE_CLASS (sym
, C_BCOMM
);
5208 S_SET_VALUE (sym
, 0);
5209 symbol_get_tc (sym
)->output
= 1;
5211 ppc_frob_label (sym
);
5213 demand_empty_rest_of_line ();
5216 /* The .ec pseudo-op. This just creates a C_ECOMM symbol. */
5219 ppc_ec (int ignore ATTRIBUTE_UNUSED
)
5223 sym
= symbol_make (".ec");
5224 S_SET_SEGMENT (sym
, ppc_coff_debug_section
);
5225 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5226 S_SET_STORAGE_CLASS (sym
, C_ECOMM
);
5227 S_SET_VALUE (sym
, 0);
5228 symbol_get_tc (sym
)->output
= 1;
5230 ppc_frob_label (sym
);
5232 demand_empty_rest_of_line ();
5235 /* The .toc pseudo-op. Switch to the .toc subsegment. */
5238 ppc_toc (int ignore ATTRIBUTE_UNUSED
)
5240 if (ppc_toc_csect
!= (symbolS
*) NULL
)
5241 subseg_set (data_section
, symbol_get_tc (ppc_toc_csect
)->subseg
);
5248 subseg
= ppc_data_subsegment
;
5249 ++ppc_data_subsegment
;
5251 subseg_new (segment_name (data_section
), subseg
);
5252 ppc_toc_frag
= frag_now
;
5254 sym
= symbol_find_or_make ("TOC[TC0]");
5255 symbol_set_frag (sym
, frag_now
);
5256 S_SET_SEGMENT (sym
, data_section
);
5257 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5258 symbol_get_tc (sym
)->subseg
= subseg
;
5259 symbol_get_tc (sym
)->output
= 1;
5260 symbol_get_tc (sym
)->within
= sym
;
5262 ppc_toc_csect
= sym
;
5264 for (list
= ppc_data_csects
;
5265 symbol_get_tc (list
)->next
!= (symbolS
*) NULL
;
5266 list
= symbol_get_tc (list
)->next
)
5268 symbol_get_tc (list
)->next
= sym
;
5270 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
5271 symbol_append (sym
, symbol_get_tc (list
)->within
, &symbol_rootP
,
5275 ppc_current_csect
= ppc_toc_csect
;
5277 demand_empty_rest_of_line ();
5280 /* The AIX assembler automatically aligns the operands of a .long or
5281 .short pseudo-op, and we want to be compatible. */
5284 ppc_xcoff_cons (int log_size
)
5286 frag_align (log_size
, 0, 0);
5287 record_alignment (now_seg
, log_size
);
5288 cons (1 << log_size
);
5292 ppc_vbyte (int dummy ATTRIBUTE_UNUSED
)
5297 (void) expression (&exp
);
5299 if (exp
.X_op
!= O_constant
)
5301 as_bad (_("non-constant byte count"));
5305 byte_count
= exp
.X_add_number
;
5307 if (*input_line_pointer
!= ',')
5309 as_bad (_("missing value"));
5313 ++input_line_pointer
;
5318 ppc_xcoff_end (void)
5322 for (i
= 0; i
< XCOFF_DWSECT_NBR_NAMES
; i
++)
5324 struct dw_section
*dws
= &dw_sections
[i
];
5325 struct dw_subsection
*dwss
;
5327 if (dws
->anon_subseg
)
5329 dwss
= dws
->anon_subseg
;
5330 dwss
->link
= dws
->list_subseg
;
5333 dwss
= dws
->list_subseg
;
5335 for (; dwss
!= NULL
; dwss
= dwss
->link
)
5336 if (dwss
->end_exp
.X_add_symbol
!= NULL
)
5338 subseg_set (dws
->sect
, dwss
->subseg
);
5339 symbol_set_value_now (dwss
->end_exp
.X_add_symbol
);
5345 #endif /* OBJ_XCOFF */
5346 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
5348 /* The .tc pseudo-op. This is used when generating either XCOFF or
5349 ELF. This takes two or more arguments.
5351 When generating XCOFF output, the first argument is the name to
5352 give to this location in the toc; this will be a symbol with class
5353 TC. The rest of the arguments are N-byte values to actually put at
5354 this location in the TOC; often there is just one more argument, a
5355 relocatable symbol reference. The size of the value to store
5356 depends on target word size. A 32-bit target uses 4-byte values, a
5357 64-bit target uses 8-byte values.
5359 When not generating XCOFF output, the arguments are the same, but
5360 the first argument is simply ignored. */
5363 ppc_tc (int ignore ATTRIBUTE_UNUSED
)
5367 /* Define the TOC symbol name. */
5373 if (ppc_toc_csect
== (symbolS
*) NULL
5374 || ppc_toc_csect
!= ppc_current_csect
)
5376 as_bad (_(".tc not in .toc section"));
5377 ignore_rest_of_line ();
5381 endc
= get_symbol_name (&name
);
5383 sym
= symbol_find_or_make (name
);
5385 (void) restore_line_pointer (endc
);
5387 if (S_IS_DEFINED (sym
))
5391 label
= symbol_get_tc (ppc_current_csect
)->within
;
5392 if (symbol_get_tc (label
)->symbol_class
!= XMC_TC0
)
5394 as_bad (_(".tc with no label"));
5395 ignore_rest_of_line ();
5399 S_SET_SEGMENT (label
, S_GET_SEGMENT (sym
));
5400 symbol_set_frag (label
, symbol_get_frag (sym
));
5401 S_SET_VALUE (label
, S_GET_VALUE (sym
));
5403 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5404 ++input_line_pointer
;
5409 S_SET_SEGMENT (sym
, now_seg
);
5410 symbol_set_frag (sym
, frag_now
);
5411 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5412 symbol_get_tc (sym
)->symbol_class
= XMC_TC
;
5413 symbol_get_tc (sym
)->output
= 1;
5415 ppc_frob_label (sym
);
5418 #endif /* OBJ_XCOFF */
5422 /* Skip the TOC symbol name. */
5423 while (is_part_of_name (*input_line_pointer
)
5424 || *input_line_pointer
== ' '
5425 || *input_line_pointer
== '['
5426 || *input_line_pointer
== ']'
5427 || *input_line_pointer
== '{'
5428 || *input_line_pointer
== '}')
5429 ++input_line_pointer
;
5431 /* Align to a four/eight byte boundary. */
5432 align
= ppc_obj64
? 3 : 2;
5433 frag_align (align
, 0, 0);
5434 record_alignment (now_seg
, align
);
5435 #endif /* OBJ_ELF */
5437 if (*input_line_pointer
!= ',')
5438 demand_empty_rest_of_line ();
5441 ++input_line_pointer
;
5442 cons (ppc_obj64
? 8 : 4);
5446 /* Pseudo-op .machine. */
5449 ppc_machine (int ignore ATTRIBUTE_UNUSED
)
5453 #define MAX_HISTORY 100
5454 static ppc_cpu_t
*cpu_history
;
5455 static int curr_hist
;
5459 c
= get_symbol_name (&cpu_string
);
5460 cpu_string
= xstrdup (cpu_string
);
5461 (void) restore_line_pointer (c
);
5463 if (cpu_string
!= NULL
)
5465 ppc_cpu_t old_cpu
= ppc_cpu
;
5469 for (p
= cpu_string
; *p
!= 0; p
++)
5472 if (strcmp (cpu_string
, "push") == 0)
5474 if (cpu_history
== NULL
)
5475 cpu_history
= XNEWVEC (ppc_cpu_t
, MAX_HISTORY
);
5477 if (curr_hist
>= MAX_HISTORY
)
5478 as_bad (_(".machine stack overflow"));
5480 cpu_history
[curr_hist
++] = ppc_cpu
;
5482 else if (strcmp (cpu_string
, "pop") == 0)
5485 as_bad (_(".machine stack underflow"));
5487 ppc_cpu
= cpu_history
[--curr_hist
];
5489 else if ((new_cpu
= ppc_parse_cpu (ppc_cpu
, &sticky
, cpu_string
)) != 0)
5492 as_bad (_("invalid machine `%s'"), cpu_string
);
5494 if (ppc_cpu
!= old_cpu
)
5495 ppc_setup_opcodes ();
5498 demand_empty_rest_of_line ();
5500 #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */
5504 /* XCOFF specific symbol and file handling. */
5506 /* Canonicalize the symbol name. We use the to force the suffix, if
5507 any, to use square brackets, and to be in upper case. */
5510 ppc_canonicalize_symbol_name (char *name
)
5514 if (ppc_stab_symbol
)
5517 for (s
= name
; *s
!= '\0' && *s
!= '{' && *s
!= '['; s
++)
5531 for (s
++; *s
!= '\0' && *s
!= brac
; s
++)
5534 if (*s
== '\0' || s
[1] != '\0')
5535 as_bad (_("bad symbol suffix"));
5543 /* Set the class of a symbol based on the suffix, if any. This is
5544 called whenever a new symbol is created. */
5547 ppc_symbol_new_hook (symbolS
*sym
)
5549 struct ppc_tc_sy
*tc
;
5552 tc
= symbol_get_tc (sym
);
5555 tc
->symbol_class
= -1;
5556 tc
->real_name
= NULL
;
5563 if (ppc_stab_symbol
)
5566 s
= strchr (S_GET_NAME (sym
), '[');
5567 if (s
== (const char *) NULL
)
5569 /* There is no suffix. */
5578 if (strcmp (s
, "BS]") == 0)
5579 tc
->symbol_class
= XMC_BS
;
5582 if (strcmp (s
, "DB]") == 0)
5583 tc
->symbol_class
= XMC_DB
;
5584 else if (strcmp (s
, "DS]") == 0)
5585 tc
->symbol_class
= XMC_DS
;
5588 if (strcmp (s
, "GL]") == 0)
5589 tc
->symbol_class
= XMC_GL
;
5592 if (strcmp (s
, "PR]") == 0)
5593 tc
->symbol_class
= XMC_PR
;
5596 if (strcmp (s
, "RO]") == 0)
5597 tc
->symbol_class
= XMC_RO
;
5598 else if (strcmp (s
, "RW]") == 0)
5599 tc
->symbol_class
= XMC_RW
;
5602 if (strcmp (s
, "SV]") == 0)
5603 tc
->symbol_class
= XMC_SV
;
5606 if (strcmp (s
, "TC]") == 0)
5607 tc
->symbol_class
= XMC_TC
;
5608 else if (strcmp (s
, "TI]") == 0)
5609 tc
->symbol_class
= XMC_TI
;
5610 else if (strcmp (s
, "TB]") == 0)
5611 tc
->symbol_class
= XMC_TB
;
5612 else if (strcmp (s
, "TC0]") == 0 || strcmp (s
, "T0]") == 0)
5613 tc
->symbol_class
= XMC_TC0
;
5616 if (strcmp (s
, "UA]") == 0)
5617 tc
->symbol_class
= XMC_UA
;
5618 else if (strcmp (s
, "UC]") == 0)
5619 tc
->symbol_class
= XMC_UC
;
5622 if (strcmp (s
, "XO]") == 0)
5623 tc
->symbol_class
= XMC_XO
;
5627 if (tc
->symbol_class
== -1)
5628 as_bad (_("unrecognized symbol suffix"));
5631 /* This variable is set by ppc_frob_symbol if any absolute symbols are
5632 seen. It tells ppc_adjust_symtab whether it needs to look through
5635 static bfd_boolean ppc_saw_abs
;
5637 /* Change the name of a symbol just before writing it out. Set the
5638 real name if the .rename pseudo-op was used. Otherwise, remove any
5639 class suffix. Return 1 if the symbol should not be included in the
5643 ppc_frob_symbol (symbolS
*sym
)
5645 static symbolS
*ppc_last_function
;
5646 static symbolS
*set_end
;
5648 /* Discard symbols that should not be included in the output symbol
5650 if (! symbol_used_in_reloc_p (sym
)
5651 && ((symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
) != 0
5652 || (! (S_IS_EXTERNAL (sym
) || S_IS_WEAK (sym
))
5653 && ! symbol_get_tc (sym
)->output
5654 && S_GET_STORAGE_CLASS (sym
) != C_FILE
)))
5657 /* This one will disappear anyway. Don't make a csect sym for it. */
5658 if (sym
== abs_section_sym
)
5661 if (symbol_get_tc (sym
)->real_name
!= (char *) NULL
)
5662 S_SET_NAME (sym
, symbol_get_tc (sym
)->real_name
);
5668 name
= S_GET_NAME (sym
);
5669 s
= strchr (name
, '[');
5670 if (s
!= (char *) NULL
)
5676 snew
= xstrndup (name
, len
);
5678 S_SET_NAME (sym
, snew
);
5682 if (set_end
!= (symbolS
*) NULL
)
5684 SA_SET_SYM_ENDNDX (set_end
, sym
);
5688 if (SF_GET_FUNCTION (sym
))
5690 if (ppc_last_function
!= (symbolS
*) NULL
)
5691 as_bad (_("two .function pseudo-ops with no intervening .ef"));
5692 ppc_last_function
= sym
;
5693 if (symbol_get_tc (sym
)->u
.size
!= (symbolS
*) NULL
)
5695 resolve_symbol_value (symbol_get_tc (sym
)->u
.size
);
5696 SA_SET_SYM_FSIZE (sym
,
5697 (long) S_GET_VALUE (symbol_get_tc (sym
)->u
.size
));
5700 else if (S_GET_STORAGE_CLASS (sym
) == C_FCN
5701 && strcmp (S_GET_NAME (sym
), ".ef") == 0)
5703 if (ppc_last_function
== (symbolS
*) NULL
)
5704 as_bad (_(".ef with no preceding .function"));
5707 set_end
= ppc_last_function
;
5708 ppc_last_function
= NULL
;
5710 /* We don't have a C_EFCN symbol, but we need to force the
5711 COFF backend to believe that it has seen one. */
5712 coff_last_function
= NULL
;
5716 if (! (S_IS_EXTERNAL (sym
) || S_IS_WEAK (sym
))
5717 && (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
) == 0
5718 && S_GET_STORAGE_CLASS (sym
) != C_FILE
5719 && S_GET_STORAGE_CLASS (sym
) != C_FCN
5720 && S_GET_STORAGE_CLASS (sym
) != C_BLOCK
5721 && S_GET_STORAGE_CLASS (sym
) != C_BSTAT
5722 && S_GET_STORAGE_CLASS (sym
) != C_ESTAT
5723 && S_GET_STORAGE_CLASS (sym
) != C_BINCL
5724 && S_GET_STORAGE_CLASS (sym
) != C_EINCL
5725 && S_GET_SEGMENT (sym
) != ppc_coff_debug_section
)
5726 S_SET_STORAGE_CLASS (sym
, C_HIDEXT
);
5728 if (S_GET_STORAGE_CLASS (sym
) == C_EXT
5729 || S_GET_STORAGE_CLASS (sym
) == C_AIX_WEAKEXT
5730 || S_GET_STORAGE_CLASS (sym
) == C_HIDEXT
)
5733 union internal_auxent
*a
;
5735 /* Create a csect aux. */
5736 i
= S_GET_NUMBER_AUXILIARY (sym
);
5737 S_SET_NUMBER_AUXILIARY (sym
, i
+ 1);
5738 a
= &coffsymbol (symbol_get_bfdsym (sym
))->native
[i
+ 1].u
.auxent
;
5739 if (symbol_get_tc (sym
)->symbol_class
== XMC_TC0
)
5741 /* This is the TOC table. */
5742 know (strcmp (S_GET_NAME (sym
), "TOC") == 0);
5743 a
->x_csect
.x_scnlen
.l
= 0;
5744 a
->x_csect
.x_smtyp
= (2 << 3) | XTY_SD
;
5746 else if (symbol_get_tc (sym
)->subseg
!= 0)
5748 /* This is a csect symbol. x_scnlen is the size of the
5750 if (symbol_get_tc (sym
)->next
== (symbolS
*) NULL
)
5751 a
->x_csect
.x_scnlen
.l
= (bfd_section_size (S_GET_SEGMENT (sym
))
5752 - S_GET_VALUE (sym
));
5755 resolve_symbol_value (symbol_get_tc (sym
)->next
);
5756 a
->x_csect
.x_scnlen
.l
= (S_GET_VALUE (symbol_get_tc (sym
)->next
)
5757 - S_GET_VALUE (sym
));
5759 a
->x_csect
.x_smtyp
= (symbol_get_tc (sym
)->align
<< 3) | XTY_SD
;
5761 else if (S_GET_SEGMENT (sym
) == bss_section
)
5763 /* This is a common symbol. */
5764 a
->x_csect
.x_scnlen
.l
= symbol_get_frag (sym
)->fr_offset
;
5765 a
->x_csect
.x_smtyp
= (symbol_get_tc (sym
)->align
<< 3) | XTY_CM
;
5766 if (S_IS_EXTERNAL (sym
))
5767 symbol_get_tc (sym
)->symbol_class
= XMC_RW
;
5769 symbol_get_tc (sym
)->symbol_class
= XMC_BS
;
5771 else if (S_GET_SEGMENT (sym
) == absolute_section
)
5773 /* This is an absolute symbol. The csect will be created by
5774 ppc_adjust_symtab. */
5776 a
->x_csect
.x_smtyp
= XTY_LD
;
5777 if (symbol_get_tc (sym
)->symbol_class
== -1)
5778 symbol_get_tc (sym
)->symbol_class
= XMC_XO
;
5780 else if (! S_IS_DEFINED (sym
))
5782 /* This is an external symbol. */
5783 a
->x_csect
.x_scnlen
.l
= 0;
5784 a
->x_csect
.x_smtyp
= XTY_ER
;
5786 else if (symbol_get_tc (sym
)->symbol_class
== XMC_TC
)
5790 /* This is a TOC definition. x_scnlen is the size of the
5792 next
= symbol_next (sym
);
5793 while (symbol_get_tc (next
)->symbol_class
== XMC_TC0
)
5794 next
= symbol_next (next
);
5795 if (next
== (symbolS
*) NULL
5796 || symbol_get_tc (next
)->symbol_class
!= XMC_TC
)
5798 if (ppc_after_toc_frag
== (fragS
*) NULL
)
5799 a
->x_csect
.x_scnlen
.l
= (bfd_section_size (data_section
)
5800 - S_GET_VALUE (sym
));
5802 a
->x_csect
.x_scnlen
.l
= (ppc_after_toc_frag
->fr_address
5803 - S_GET_VALUE (sym
));
5807 resolve_symbol_value (next
);
5808 a
->x_csect
.x_scnlen
.l
= (S_GET_VALUE (next
)
5809 - S_GET_VALUE (sym
));
5811 a
->x_csect
.x_smtyp
= (2 << 3) | XTY_SD
;
5817 /* This is a normal symbol definition. x_scnlen is the
5818 symbol index of the containing csect. */
5819 if (S_GET_SEGMENT (sym
) == text_section
)
5820 csect
= ppc_text_csects
;
5821 else if (S_GET_SEGMENT (sym
) == data_section
)
5822 csect
= ppc_data_csects
;
5826 /* Skip the initial dummy symbol. */
5827 csect
= symbol_get_tc (csect
)->next
;
5829 if (csect
== (symbolS
*) NULL
)
5831 as_warn (_("warning: symbol %s has no csect"), S_GET_NAME (sym
));
5832 a
->x_csect
.x_scnlen
.l
= 0;
5836 while (symbol_get_tc (csect
)->next
!= (symbolS
*) NULL
)
5838 resolve_symbol_value (symbol_get_tc (csect
)->next
);
5839 if (S_GET_VALUE (symbol_get_tc (csect
)->next
)
5840 > S_GET_VALUE (sym
))
5842 csect
= symbol_get_tc (csect
)->next
;
5845 a
->x_csect
.x_scnlen
.p
=
5846 coffsymbol (symbol_get_bfdsym (csect
))->native
;
5847 coffsymbol (symbol_get_bfdsym (sym
))->native
[i
+ 1].fix_scnlen
=
5850 a
->x_csect
.x_smtyp
= XTY_LD
;
5853 a
->x_csect
.x_parmhash
= 0;
5854 a
->x_csect
.x_snhash
= 0;
5855 if (symbol_get_tc (sym
)->symbol_class
== -1)
5856 a
->x_csect
.x_smclas
= XMC_PR
;
5858 a
->x_csect
.x_smclas
= symbol_get_tc (sym
)->symbol_class
;
5859 a
->x_csect
.x_stab
= 0;
5860 a
->x_csect
.x_snstab
= 0;
5862 /* Don't let the COFF backend resort these symbols. */
5863 symbol_get_bfdsym (sym
)->flags
|= BSF_NOT_AT_END
;
5865 else if (S_GET_STORAGE_CLASS (sym
) == C_BSTAT
)
5867 /* We want the value to be the symbol index of the referenced
5868 csect symbol. BFD will do that for us if we set the right
5870 asymbol
*bsym
= symbol_get_bfdsym (symbol_get_tc (sym
)->within
);
5871 combined_entry_type
*c
= coffsymbol (bsym
)->native
;
5873 S_SET_VALUE (sym
, (valueT
) (size_t) c
);
5874 coffsymbol (symbol_get_bfdsym (sym
))->native
->fix_value
= 1;
5876 else if (S_GET_STORAGE_CLASS (sym
) == C_STSYM
)
5881 block
= symbol_get_tc (sym
)->within
;
5884 /* The value is the offset from the enclosing csect. */
5887 csect
= symbol_get_tc (block
)->within
;
5888 resolve_symbol_value (csect
);
5889 base
= S_GET_VALUE (csect
);
5894 S_SET_VALUE (sym
, S_GET_VALUE (sym
) - base
);
5896 else if (S_GET_STORAGE_CLASS (sym
) == C_BINCL
5897 || S_GET_STORAGE_CLASS (sym
) == C_EINCL
)
5899 /* We want the value to be a file offset into the line numbers.
5900 BFD will do that for us if we set the right flags. We have
5901 already set the value correctly. */
5902 coffsymbol (symbol_get_bfdsym (sym
))->native
->fix_line
= 1;
5908 /* Adjust the symbol table. This creates csect symbols for all
5909 absolute symbols. */
5912 ppc_adjust_symtab (void)
5919 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
5923 union internal_auxent
*a
;
5925 if (S_GET_SEGMENT (sym
) != absolute_section
)
5928 csect
= symbol_create (".abs[XO]", absolute_section
,
5929 S_GET_VALUE (sym
), &zero_address_frag
);
5930 symbol_get_bfdsym (csect
)->value
= S_GET_VALUE (sym
);
5931 S_SET_STORAGE_CLASS (csect
, C_HIDEXT
);
5932 i
= S_GET_NUMBER_AUXILIARY (csect
);
5933 S_SET_NUMBER_AUXILIARY (csect
, i
+ 1);
5934 a
= &coffsymbol (symbol_get_bfdsym (csect
))->native
[i
+ 1].u
.auxent
;
5935 a
->x_csect
.x_scnlen
.l
= 0;
5936 a
->x_csect
.x_smtyp
= XTY_SD
;
5937 a
->x_csect
.x_parmhash
= 0;
5938 a
->x_csect
.x_snhash
= 0;
5939 a
->x_csect
.x_smclas
= XMC_XO
;
5940 a
->x_csect
.x_stab
= 0;
5941 a
->x_csect
.x_snstab
= 0;
5943 symbol_insert (csect
, sym
, &symbol_rootP
, &symbol_lastP
);
5945 i
= S_GET_NUMBER_AUXILIARY (sym
);
5946 a
= &coffsymbol (symbol_get_bfdsym (sym
))->native
[i
].u
.auxent
;
5947 a
->x_csect
.x_scnlen
.p
= coffsymbol (symbol_get_bfdsym (csect
))->native
;
5948 coffsymbol (symbol_get_bfdsym (sym
))->native
[i
].fix_scnlen
= 1;
5951 ppc_saw_abs
= FALSE
;
5954 /* Set the VMA for a section. This is called on all the sections in
5958 ppc_frob_section (asection
*sec
)
5960 static bfd_vma vma
= 0;
5962 /* Dwarf sections start at 0. */
5963 if (bfd_section_flags (sec
) & SEC_DEBUGGING
)
5966 vma
= md_section_align (sec
, vma
);
5967 bfd_set_section_vma (sec
, vma
);
5968 vma
+= bfd_section_size (sec
);
5971 #endif /* OBJ_XCOFF */
5974 md_atof (int type
, char *litp
, int *sizep
)
5976 return ieee_md_atof (type
, litp
, sizep
, target_big_endian
);
5979 /* Write a value out to the object file, using the appropriate
5983 md_number_to_chars (char *buf
, valueT val
, int n
)
5985 if (target_big_endian
)
5986 number_to_chars_bigendian (buf
, val
, n
);
5988 number_to_chars_littleendian (buf
, val
, n
);
5991 /* Align a section (I don't know why this is machine dependent). */
5994 md_section_align (asection
*seg ATTRIBUTE_UNUSED
, valueT addr
)
5999 int align
= bfd_section_alignment (seg
);
6001 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
6005 /* We don't have any form of relaxing. */
6008 md_estimate_size_before_relax (fragS
*fragp ATTRIBUTE_UNUSED
,
6009 asection
*seg ATTRIBUTE_UNUSED
)
6015 /* Convert a machine dependent frag. We never generate these. */
6018 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
6019 asection
*sec ATTRIBUTE_UNUSED
,
6020 fragS
*fragp ATTRIBUTE_UNUSED
)
6025 /* We have no need to default values of symbols. */
6028 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6033 /* Functions concerning relocs. */
6035 /* The location from which a PC relative jump should be calculated,
6036 given a PC relative reloc. */
6039 md_pcrel_from_section (fixS
*fixp
, segT sec ATTRIBUTE_UNUSED
)
6041 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6046 /* This is called to see whether a fixup should be adjusted to use a
6047 section symbol. We take the opportunity to change a fixup against
6048 a symbol in the TOC subsegment into a reloc against the
6049 corresponding .tc symbol. */
6052 ppc_fix_adjustable (fixS
*fix
)
6054 valueT val
= resolve_symbol_value (fix
->fx_addsy
);
6055 segT symseg
= S_GET_SEGMENT (fix
->fx_addsy
);
6056 TC_SYMFIELD_TYPE
*tc
;
6058 if (symseg
== absolute_section
)
6061 /* Always adjust symbols in debugging sections. */
6062 if (bfd_section_flags (symseg
) & SEC_DEBUGGING
)
6065 if (ppc_toc_csect
!= (symbolS
*) NULL
6066 && fix
->fx_addsy
!= ppc_toc_csect
6067 && symseg
== data_section
6068 && val
>= ppc_toc_frag
->fr_address
6069 && (ppc_after_toc_frag
== (fragS
*) NULL
6070 || val
< ppc_after_toc_frag
->fr_address
))
6074 for (sy
= symbol_next (ppc_toc_csect
);
6075 sy
!= (symbolS
*) NULL
;
6076 sy
= symbol_next (sy
))
6078 TC_SYMFIELD_TYPE
*sy_tc
= symbol_get_tc (sy
);
6080 if (sy_tc
->symbol_class
== XMC_TC0
)
6082 if (sy_tc
->symbol_class
!= XMC_TC
)
6084 if (val
== resolve_symbol_value (sy
))
6087 fix
->fx_addnumber
= val
- ppc_toc_frag
->fr_address
;
6092 as_bad_where (fix
->fx_file
, fix
->fx_line
,
6093 _("symbol in .toc does not match any .tc"));
6096 /* Possibly adjust the reloc to be against the csect. */
6097 tc
= symbol_get_tc (fix
->fx_addsy
);
6099 && tc
->symbol_class
!= XMC_TC0
6100 && tc
->symbol_class
!= XMC_TC
6101 && symseg
!= bss_section
6102 /* Don't adjust if this is a reloc in the toc section. */
6103 && (symseg
!= data_section
6104 || ppc_toc_csect
== NULL
6105 || val
< ppc_toc_frag
->fr_address
6106 || (ppc_after_toc_frag
!= NULL
6107 && val
>= ppc_after_toc_frag
->fr_address
)))
6109 symbolS
*csect
= tc
->within
;
6111 /* If the symbol was not declared by a label (eg: a section symbol),
6112 use the section instead of the csect. This doesn't happen in
6113 normal AIX assembly code. */
6115 csect
= seg_info (symseg
)->sym
;
6117 fix
->fx_offset
+= val
- symbol_get_frag (csect
)->fr_address
;
6118 fix
->fx_addsy
= csect
;
6123 /* Adjust a reloc against a .lcomm symbol to be against the base
6125 if (symseg
== bss_section
6126 && ! S_IS_EXTERNAL (fix
->fx_addsy
))
6128 symbolS
*sy
= symbol_get_frag (fix
->fx_addsy
)->fr_symbol
;
6130 fix
->fx_offset
+= val
- resolve_symbol_value (sy
);
6137 /* A reloc from one csect to another must be kept. The assembler
6138 will, of course, keep relocs between sections, and it will keep
6139 absolute relocs, but we need to force it to keep PC relative relocs
6140 between two csects in the same section. */
6143 ppc_force_relocation (fixS
*fix
)
6145 /* At this point fix->fx_addsy should already have been converted to
6146 a csect symbol. If the csect does not include the fragment, then
6147 we need to force the relocation. */
6149 && fix
->fx_addsy
!= NULL
6150 && symbol_get_tc (fix
->fx_addsy
)->subseg
!= 0
6151 && ((symbol_get_frag (fix
->fx_addsy
)->fr_address
6152 > fix
->fx_frag
->fr_address
)
6153 || (symbol_get_tc (fix
->fx_addsy
)->next
!= NULL
6154 && (symbol_get_frag (symbol_get_tc (fix
->fx_addsy
)->next
)->fr_address
6155 <= fix
->fx_frag
->fr_address
))))
6158 return generic_force_reloc (fix
);
6160 #endif /* OBJ_XCOFF */
6163 /* If this function returns non-zero, it guarantees that a relocation
6164 will be emitted for a fixup. */
6167 ppc_force_relocation (fixS
*fix
)
6169 /* Branch prediction relocations must force a relocation, as must
6170 the vtable description relocs. */
6171 switch (fix
->fx_r_type
)
6173 case BFD_RELOC_PPC_B16_BRTAKEN
:
6174 case BFD_RELOC_PPC_B16_BRNTAKEN
:
6175 case BFD_RELOC_PPC_BA16_BRTAKEN
:
6176 case BFD_RELOC_PPC_BA16_BRNTAKEN
:
6177 case BFD_RELOC_24_PLT_PCREL
:
6178 case BFD_RELOC_PPC64_TOC
:
6180 case BFD_RELOC_PPC_B26
:
6181 case BFD_RELOC_PPC_BA26
:
6182 case BFD_RELOC_PPC_B16
:
6183 case BFD_RELOC_PPC_BA16
:
6184 case BFD_RELOC_PPC64_REL24_NOTOC
:
6185 /* All branch fixups targeting a localentry symbol must
6186 force a relocation. */
6189 asymbol
*bfdsym
= symbol_get_bfdsym (fix
->fx_addsy
);
6190 elf_symbol_type
*elfsym
6191 = elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
6192 gas_assert (elfsym
);
6193 if ((STO_PPC64_LOCAL_MASK
& elfsym
->internal_elf_sym
.st_other
) != 0)
6201 if (fix
->fx_r_type
>= BFD_RELOC_PPC_TLS
6202 && fix
->fx_r_type
<= BFD_RELOC_PPC64_TLS_PCREL
)
6205 return generic_force_reloc (fix
);
6209 ppc_fix_adjustable (fixS
*fix
)
6211 switch (fix
->fx_r_type
)
6213 /* All branch fixups targeting a localentry symbol must
6214 continue using the symbol. */
6215 case BFD_RELOC_PPC_B26
:
6216 case BFD_RELOC_PPC_BA26
:
6217 case BFD_RELOC_PPC_B16
:
6218 case BFD_RELOC_PPC_BA16
:
6219 case BFD_RELOC_PPC_B16_BRTAKEN
:
6220 case BFD_RELOC_PPC_B16_BRNTAKEN
:
6221 case BFD_RELOC_PPC_BA16_BRTAKEN
:
6222 case BFD_RELOC_PPC_BA16_BRNTAKEN
:
6223 case BFD_RELOC_PPC64_REL24_NOTOC
:
6226 asymbol
*bfdsym
= symbol_get_bfdsym (fix
->fx_addsy
);
6227 elf_symbol_type
*elfsym
6228 = elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
6229 gas_assert (elfsym
);
6230 if ((STO_PPC64_LOCAL_MASK
& elfsym
->internal_elf_sym
.st_other
) != 0)
6238 return (fix
->fx_r_type
!= BFD_RELOC_16_GOTOFF
6239 && fix
->fx_r_type
!= BFD_RELOC_LO16_GOTOFF
6240 && fix
->fx_r_type
!= BFD_RELOC_HI16_GOTOFF
6241 && fix
->fx_r_type
!= BFD_RELOC_HI16_S_GOTOFF
6242 && fix
->fx_r_type
!= BFD_RELOC_PPC64_GOT16_DS
6243 && fix
->fx_r_type
!= BFD_RELOC_PPC64_GOT16_LO_DS
6244 && fix
->fx_r_type
!= BFD_RELOC_PPC64_GOT_PCREL34
6245 && fix
->fx_r_type
!= BFD_RELOC_24_PLT_PCREL
6246 && fix
->fx_r_type
!= BFD_RELOC_32_PLTOFF
6247 && fix
->fx_r_type
!= BFD_RELOC_32_PLT_PCREL
6248 && fix
->fx_r_type
!= BFD_RELOC_LO16_PLTOFF
6249 && fix
->fx_r_type
!= BFD_RELOC_HI16_PLTOFF
6250 && fix
->fx_r_type
!= BFD_RELOC_HI16_S_PLTOFF
6251 && fix
->fx_r_type
!= BFD_RELOC_64_PLTOFF
6252 && fix
->fx_r_type
!= BFD_RELOC_64_PLT_PCREL
6253 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLT16_LO_DS
6254 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLT_PCREL34
6255 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16
6256 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_LO
6257 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_HI
6258 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_HA
6259 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_DS
6260 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_LO_DS
6261 && fix
->fx_r_type
!= BFD_RELOC_GPREL16
6262 && fix
->fx_r_type
!= BFD_RELOC_PPC_VLE_SDAREL_LO16A
6263 && fix
->fx_r_type
!= BFD_RELOC_PPC_VLE_SDAREL_HI16A
6264 && fix
->fx_r_type
!= BFD_RELOC_PPC_VLE_SDAREL_HA16A
6265 && fix
->fx_r_type
!= BFD_RELOC_VTABLE_INHERIT
6266 && fix
->fx_r_type
!= BFD_RELOC_VTABLE_ENTRY
6267 && !(fix
->fx_r_type
>= BFD_RELOC_PPC_TLS
6268 && fix
->fx_r_type
<= BFD_RELOC_PPC64_TLS_PCREL
));
6273 ppc_frag_check (struct frag
*fragP
)
6275 if ((fragP
->fr_address
& fragP
->insn_addr
) != 0)
6276 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
6277 _("instruction address is not a multiple of %d"),
6278 fragP
->insn_addr
+ 1);
6281 /* rs_align_code frag handling. */
6283 enum ppc_nop_encoding_for_rs_align_code
6292 ppc_nop_select (void)
6294 if ((ppc_cpu
& PPC_OPCODE_VLE
) != 0)
6296 if ((ppc_cpu
& (PPC_OPCODE_POWER9
| PPC_OPCODE_E500MC
)) == 0)
6298 if ((ppc_cpu
& PPC_OPCODE_POWER7
) != 0)
6299 return PPC_NOP_GROUP_P7
;
6300 if ((ppc_cpu
& PPC_OPCODE_POWER6
) != 0)
6301 return PPC_NOP_GROUP_P6
;
6303 return PPC_NOP_VANILLA
;
6307 ppc_handle_align (struct frag
*fragP
)
6309 valueT count
= (fragP
->fr_next
->fr_address
6310 - (fragP
->fr_address
+ fragP
->fr_fix
));
6311 char *dest
= fragP
->fr_literal
+ fragP
->fr_fix
;
6312 enum ppc_nop_encoding_for_rs_align_code nop_select
= *dest
& 0xff;
6314 /* Pad with zeros if not inserting a whole number of instructions.
6315 We could pad with zeros up to an instruction boundary then follow
6316 with nops but odd counts indicate data in an executable section
6317 so padding with zeros is most appropriate. */
6319 || (nop_select
== PPC_NOP_VLE
? (count
& 1) != 0 : (count
& 3) != 0))
6325 if (nop_select
== PPC_NOP_VLE
)
6329 md_number_to_chars (dest
, 0x4400, 2);
6335 if (count
> 4 * nop_limit
&& count
< 0x2000000)
6339 /* Make a branch, then follow with nops. Insert another
6340 frag to handle the nops. */
6341 md_number_to_chars (dest
, 0x48000000 + count
, 4);
6346 rest
= xmalloc (SIZEOF_STRUCT_FRAG
+ 4);
6347 memcpy (rest
, fragP
, SIZEOF_STRUCT_FRAG
);
6348 fragP
->fr_next
= rest
;
6350 rest
->fr_address
+= rest
->fr_fix
+ 4;
6352 /* If we leave the next frag as rs_align_code we'll come here
6353 again, resulting in a bunch of branches rather than a
6354 branch followed by nops. */
6355 rest
->fr_type
= rs_align
;
6356 dest
= rest
->fr_literal
;
6359 md_number_to_chars (dest
, 0x60000000, 4);
6361 if (nop_select
>= PPC_NOP_GROUP_P6
)
6363 /* For power6, power7, and power8, we want the last nop to
6364 be a group terminating one. Do this by inserting an
6365 rs_fill frag immediately after this one, with its address
6366 set to the last nop location. This will automatically
6367 reduce the number of nops in the current frag by one. */
6370 struct frag
*group_nop
= xmalloc (SIZEOF_STRUCT_FRAG
+ 4);
6372 memcpy (group_nop
, fragP
, SIZEOF_STRUCT_FRAG
);
6373 group_nop
->fr_address
= group_nop
->fr_next
->fr_address
- 4;
6374 group_nop
->fr_fix
= 0;
6375 group_nop
->fr_offset
= 1;
6376 group_nop
->fr_type
= rs_fill
;
6377 fragP
->fr_next
= group_nop
;
6378 dest
= group_nop
->fr_literal
;
6381 if (nop_select
== PPC_NOP_GROUP_P6
)
6382 /* power6 group terminating nop: "ori 1,1,0". */
6383 md_number_to_chars (dest
, 0x60210000, 4);
6385 /* power7/power8 group terminating nop: "ori 2,2,0". */
6386 md_number_to_chars (dest
, 0x60420000, 4);
6391 /* Apply a fixup to the object code. This is called for all the
6392 fixups we generated by the calls to fix_new_exp, above. */
6395 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
6397 valueT value
= * valP
;
6399 const struct powerpc_operand
*operand
;
6402 if (fixP
->fx_addsy
!= NULL
)
6404 /* Hack around bfd_install_relocation brain damage. */
6406 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6408 if (fixP
->fx_addsy
== abs_section_sym
)
6414 /* FIXME FIXME FIXME: The value we are passed in *valP includes
6415 the symbol values. If we are doing this relocation the code in
6416 write.c is going to call bfd_install_relocation, which is also
6417 going to use the symbol value. That means that if the reloc is
6418 fully resolved we want to use *valP since bfd_install_relocation is
6420 However, if the reloc is not fully resolved we do not want to
6421 use *valP, and must use fx_offset instead. If the relocation
6422 is PC-relative, we then need to re-apply md_pcrel_from_section
6423 to this new relocation value. */
6424 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
6429 value
= fixP
->fx_offset
;
6431 value
-= md_pcrel_from_section (fixP
, seg
);
6435 /* We are only able to convert some relocs to pc-relative. */
6438 switch (fixP
->fx_r_type
)
6441 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
6445 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
6449 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
6452 case BFD_RELOC_LO16
:
6453 fixP
->fx_r_type
= BFD_RELOC_LO16_PCREL
;
6456 case BFD_RELOC_HI16
:
6457 fixP
->fx_r_type
= BFD_RELOC_HI16_PCREL
;
6460 case BFD_RELOC_HI16_S
:
6461 fixP
->fx_r_type
= BFD_RELOC_HI16_S_PCREL
;
6464 case BFD_RELOC_PPC64_ADDR16_HIGH
:
6465 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGH
;
6468 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
6469 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHA
;
6472 case BFD_RELOC_PPC64_HIGHER
:
6473 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHER
;
6476 case BFD_RELOC_PPC64_HIGHER_S
:
6477 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHERA
;
6480 case BFD_RELOC_PPC64_HIGHEST
:
6481 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHEST
;
6484 case BFD_RELOC_PPC64_HIGHEST_S
:
6485 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHESTA
;
6488 case BFD_RELOC_PPC64_ADDR16_HIGHER34
:
6489 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHER34
;
6492 case BFD_RELOC_PPC64_ADDR16_HIGHERA34
:
6493 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHERA34
;
6496 case BFD_RELOC_PPC64_ADDR16_HIGHEST34
:
6497 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHEST34
;
6500 case BFD_RELOC_PPC64_ADDR16_HIGHESTA34
:
6501 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHESTA34
;
6504 case BFD_RELOC_PPC_16DX_HA
:
6505 fixP
->fx_r_type
= BFD_RELOC_PPC_REL16DX_HA
;
6508 case BFD_RELOC_PPC64_D34
:
6509 fixP
->fx_r_type
= BFD_RELOC_PPC64_PCREL34
;
6512 case BFD_RELOC_PPC64_D28
:
6513 fixP
->fx_r_type
= BFD_RELOC_PPC64_PCREL28
;
6520 else if (!fixP
->fx_done
6521 && fixP
->fx_r_type
== BFD_RELOC_PPC_16DX_HA
)
6523 /* addpcis is relative to next insn address. */
6525 fixP
->fx_r_type
= BFD_RELOC_PPC_REL16DX_HA
;
6530 if (fixP
->fx_pcrel_adjust
!= 0)
6532 /* This is a fixup on an instruction. */
6533 int opindex
= fixP
->fx_pcrel_adjust
& 0xff;
6535 operand
= &powerpc_operands
[opindex
];
6537 /* An instruction like `lwz 9,sym(30)' when `sym' is not a TOC symbol
6538 does not generate a reloc. It uses the offset of `sym' within its
6539 csect. Other usages, such as `.long sym', generate relocs. This
6540 is the documented behaviour of non-TOC symbols. */
6541 if ((operand
->flags
& PPC_OPERAND_PARENS
) != 0
6542 && (operand
->bitm
& 0xfff0) == 0xfff0
6543 && operand
->shift
== 0
6544 && (operand
->insert
== NULL
|| ppc_obj64
)
6545 && fixP
->fx_addsy
!= NULL
6546 && symbol_get_tc (fixP
->fx_addsy
)->subseg
!= 0
6547 && symbol_get_tc (fixP
->fx_addsy
)->symbol_class
!= XMC_TC
6548 && symbol_get_tc (fixP
->fx_addsy
)->symbol_class
!= XMC_TC0
6549 && S_GET_SEGMENT (fixP
->fx_addsy
) != bss_section
)
6551 value
= fixP
->fx_offset
;
6555 /* During parsing of instructions, a TOC16 reloc is generated for
6556 instructions such as 'lwz RT,SYM(RB)' if SYM is a symbol defined
6557 in the toc. But at parse time, SYM may be not yet defined, so
6558 check again here. */
6559 if (fixP
->fx_r_type
== BFD_RELOC_16
6560 && fixP
->fx_addsy
!= NULL
6561 && ppc_is_toc_sym (fixP
->fx_addsy
))
6562 fixP
->fx_r_type
= BFD_RELOC_PPC_TOC16
;
6566 /* Calculate value to be stored in field. */
6568 switch (fixP
->fx_r_type
)
6571 case BFD_RELOC_PPC64_ADDR16_LO_DS
:
6572 case BFD_RELOC_PPC_VLE_LO16A
:
6573 case BFD_RELOC_PPC_VLE_LO16D
:
6575 case BFD_RELOC_LO16
:
6576 case BFD_RELOC_LO16_PCREL
:
6577 fieldval
= value
& 0xffff;
6579 if (operand
!= NULL
&& (operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
6580 fieldval
= SEX16 (fieldval
);
6581 fixP
->fx_no_overflow
= 1;
6584 case BFD_RELOC_HI16
:
6585 case BFD_RELOC_HI16_PCREL
:
6587 if (REPORT_OVERFLOW_HI
&& ppc_obj64
)
6589 fieldval
= value
>> 16;
6590 if (operand
!= NULL
&& (operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
6592 valueT sign
= (((valueT
) -1 >> 16) + 1) >> 1;
6593 fieldval
= ((valueT
) fieldval
^ sign
) - sign
;
6599 case BFD_RELOC_PPC_VLE_HI16A
:
6600 case BFD_RELOC_PPC_VLE_HI16D
:
6601 case BFD_RELOC_PPC64_ADDR16_HIGH
:
6603 fieldval
= PPC_HI (value
);
6604 goto sign_extend_16
;
6606 case BFD_RELOC_HI16_S
:
6607 case BFD_RELOC_HI16_S_PCREL
:
6608 case BFD_RELOC_PPC_16DX_HA
:
6609 case BFD_RELOC_PPC_REL16DX_HA
:
6611 if (REPORT_OVERFLOW_HI
&& ppc_obj64
)
6613 fieldval
= (value
+ 0x8000) >> 16;
6614 if (operand
!= NULL
&& (operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
6616 valueT sign
= (((valueT
) -1 >> 16) + 1) >> 1;
6617 fieldval
= ((valueT
) fieldval
^ sign
) - sign
;
6623 case BFD_RELOC_PPC_VLE_HA16A
:
6624 case BFD_RELOC_PPC_VLE_HA16D
:
6625 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
6627 fieldval
= PPC_HA (value
);
6628 goto sign_extend_16
;
6631 case BFD_RELOC_PPC64_HIGHER
:
6632 fieldval
= PPC_HIGHER (value
);
6633 goto sign_extend_16
;
6635 case BFD_RELOC_PPC64_HIGHER_S
:
6636 fieldval
= PPC_HIGHERA (value
);
6637 goto sign_extend_16
;
6639 case BFD_RELOC_PPC64_HIGHEST
:
6640 fieldval
= PPC_HIGHEST (value
);
6641 goto sign_extend_16
;
6643 case BFD_RELOC_PPC64_HIGHEST_S
:
6644 fieldval
= PPC_HIGHESTA (value
);
6645 goto sign_extend_16
;
6652 if (operand
!= NULL
)
6654 /* Handle relocs in an insn. */
6655 switch (fixP
->fx_r_type
)
6658 /* The following relocs can't be calculated by the assembler.
6659 Leave the field zero. */
6660 case BFD_RELOC_PPC_TPREL16
:
6661 case BFD_RELOC_PPC_TPREL16_LO
:
6662 case BFD_RELOC_PPC_TPREL16_HI
:
6663 case BFD_RELOC_PPC_TPREL16_HA
:
6664 case BFD_RELOC_PPC_DTPREL16
:
6665 case BFD_RELOC_PPC_DTPREL16_LO
:
6666 case BFD_RELOC_PPC_DTPREL16_HI
:
6667 case BFD_RELOC_PPC_DTPREL16_HA
:
6668 case BFD_RELOC_PPC_GOT_TLSGD16
:
6669 case BFD_RELOC_PPC_GOT_TLSGD16_LO
:
6670 case BFD_RELOC_PPC_GOT_TLSGD16_HI
:
6671 case BFD_RELOC_PPC_GOT_TLSGD16_HA
:
6672 case BFD_RELOC_PPC_GOT_TLSLD16
:
6673 case BFD_RELOC_PPC_GOT_TLSLD16_LO
:
6674 case BFD_RELOC_PPC_GOT_TLSLD16_HI
:
6675 case BFD_RELOC_PPC_GOT_TLSLD16_HA
:
6676 case BFD_RELOC_PPC_GOT_TPREL16
:
6677 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
6678 case BFD_RELOC_PPC_GOT_TPREL16_HI
:
6679 case BFD_RELOC_PPC_GOT_TPREL16_HA
:
6680 case BFD_RELOC_PPC_GOT_DTPREL16
:
6681 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
6682 case BFD_RELOC_PPC_GOT_DTPREL16_HI
:
6683 case BFD_RELOC_PPC_GOT_DTPREL16_HA
:
6684 case BFD_RELOC_PPC64_TPREL16_DS
:
6685 case BFD_RELOC_PPC64_TPREL16_LO_DS
:
6686 case BFD_RELOC_PPC64_TPREL16_HIGH
:
6687 case BFD_RELOC_PPC64_TPREL16_HIGHA
:
6688 case BFD_RELOC_PPC64_TPREL16_HIGHER
:
6689 case BFD_RELOC_PPC64_TPREL16_HIGHERA
:
6690 case BFD_RELOC_PPC64_TPREL16_HIGHEST
:
6691 case BFD_RELOC_PPC64_TPREL16_HIGHESTA
:
6692 case BFD_RELOC_PPC64_DTPREL16_HIGH
:
6693 case BFD_RELOC_PPC64_DTPREL16_HIGHA
:
6694 case BFD_RELOC_PPC64_DTPREL16_DS
:
6695 case BFD_RELOC_PPC64_DTPREL16_LO_DS
:
6696 case BFD_RELOC_PPC64_DTPREL16_HIGHER
:
6697 case BFD_RELOC_PPC64_DTPREL16_HIGHERA
:
6698 case BFD_RELOC_PPC64_DTPREL16_HIGHEST
:
6699 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA
:
6700 case BFD_RELOC_PPC64_TPREL34
:
6701 case BFD_RELOC_PPC64_DTPREL34
:
6702 case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
:
6703 case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
:
6704 case BFD_RELOC_PPC64_GOT_TPREL_PCREL34
:
6705 case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
:
6706 gas_assert (fixP
->fx_addsy
!= NULL
);
6707 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6711 /* These also should leave the field zero for the same
6712 reason. Note that older versions of gas wrote values
6713 here. If we want to go back to the old behaviour, then
6714 all _LO and _LO_DS cases will need to be treated like
6715 BFD_RELOC_LO16_PCREL above. Similarly for _HI etc. */
6716 case BFD_RELOC_16_GOTOFF
:
6717 case BFD_RELOC_LO16_GOTOFF
:
6718 case BFD_RELOC_HI16_GOTOFF
:
6719 case BFD_RELOC_HI16_S_GOTOFF
:
6720 case BFD_RELOC_LO16_PLTOFF
:
6721 case BFD_RELOC_HI16_PLTOFF
:
6722 case BFD_RELOC_HI16_S_PLTOFF
:
6723 case BFD_RELOC_GPREL16
:
6724 case BFD_RELOC_16_BASEREL
:
6725 case BFD_RELOC_LO16_BASEREL
:
6726 case BFD_RELOC_HI16_BASEREL
:
6727 case BFD_RELOC_HI16_S_BASEREL
:
6728 case BFD_RELOC_PPC_TOC16
:
6729 case BFD_RELOC_PPC64_TOC16_LO
:
6730 case BFD_RELOC_PPC64_TOC16_HI
:
6731 case BFD_RELOC_PPC64_TOC16_HA
:
6732 case BFD_RELOC_PPC64_PLTGOT16
:
6733 case BFD_RELOC_PPC64_PLTGOT16_LO
:
6734 case BFD_RELOC_PPC64_PLTGOT16_HI
:
6735 case BFD_RELOC_PPC64_PLTGOT16_HA
:
6736 case BFD_RELOC_PPC64_GOT16_DS
:
6737 case BFD_RELOC_PPC64_GOT16_LO_DS
:
6738 case BFD_RELOC_PPC64_PLT16_LO_DS
:
6739 case BFD_RELOC_PPC64_SECTOFF_DS
:
6740 case BFD_RELOC_PPC64_SECTOFF_LO_DS
:
6741 case BFD_RELOC_PPC64_TOC16_DS
:
6742 case BFD_RELOC_PPC64_TOC16_LO_DS
:
6743 case BFD_RELOC_PPC64_PLTGOT16_DS
:
6744 case BFD_RELOC_PPC64_PLTGOT16_LO_DS
:
6745 case BFD_RELOC_PPC_EMB_NADDR16
:
6746 case BFD_RELOC_PPC_EMB_NADDR16_LO
:
6747 case BFD_RELOC_PPC_EMB_NADDR16_HI
:
6748 case BFD_RELOC_PPC_EMB_NADDR16_HA
:
6749 case BFD_RELOC_PPC_EMB_SDAI16
:
6750 case BFD_RELOC_PPC_EMB_SDA2I16
:
6751 case BFD_RELOC_PPC_EMB_SDA2REL
:
6752 case BFD_RELOC_PPC_EMB_SDA21
:
6753 case BFD_RELOC_PPC_EMB_MRKREF
:
6754 case BFD_RELOC_PPC_EMB_RELSEC16
:
6755 case BFD_RELOC_PPC_EMB_RELST_LO
:
6756 case BFD_RELOC_PPC_EMB_RELST_HI
:
6757 case BFD_RELOC_PPC_EMB_RELST_HA
:
6758 case BFD_RELOC_PPC_EMB_BIT_FLD
:
6759 case BFD_RELOC_PPC_EMB_RELSDA
:
6760 case BFD_RELOC_PPC_VLE_SDA21
:
6761 case BFD_RELOC_PPC_VLE_SDA21_LO
:
6762 case BFD_RELOC_PPC_VLE_SDAREL_LO16A
:
6763 case BFD_RELOC_PPC_VLE_SDAREL_LO16D
:
6764 case BFD_RELOC_PPC_VLE_SDAREL_HI16A
:
6765 case BFD_RELOC_PPC_VLE_SDAREL_HI16D
:
6766 case BFD_RELOC_PPC_VLE_SDAREL_HA16A
:
6767 case BFD_RELOC_PPC_VLE_SDAREL_HA16D
:
6768 case BFD_RELOC_PPC64_GOT_PCREL34
:
6769 case BFD_RELOC_PPC64_PLT_PCREL34
:
6770 gas_assert (fixP
->fx_addsy
!= NULL
);
6773 case BFD_RELOC_PPC_TLS
:
6774 case BFD_RELOC_PPC_TLSGD
:
6775 case BFD_RELOC_PPC_TLSLD
:
6776 case BFD_RELOC_PPC64_TLS_PCREL
:
6782 case BFD_RELOC_PPC_B16
:
6783 /* Adjust the offset to the instruction boundary. */
6788 case BFD_RELOC_VTABLE_INHERIT
:
6789 case BFD_RELOC_VTABLE_ENTRY
:
6790 case BFD_RELOC_PPC_DTPMOD
:
6791 case BFD_RELOC_PPC_TPREL
:
6792 case BFD_RELOC_PPC_DTPREL
:
6793 case BFD_RELOC_PPC_COPY
:
6794 case BFD_RELOC_PPC_GLOB_DAT
:
6795 case BFD_RELOC_32_PLT_PCREL
:
6796 case BFD_RELOC_PPC_EMB_NADDR32
:
6797 case BFD_RELOC_PPC64_TOC
:
6798 case BFD_RELOC_CTOR
:
6800 case BFD_RELOC_32_PCREL
:
6803 case BFD_RELOC_64_PCREL
:
6804 case BFD_RELOC_PPC64_ADDR64_LOCAL
:
6805 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6806 _("%s unsupported as instruction fixup"),
6807 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6816 /* powerpc uses RELA style relocs, so if emitting a reloc the field
6817 contents can stay at zero. */
6818 #define APPLY_RELOC fixP->fx_done
6820 #define APPLY_RELOC 1
6822 /* We need to call the insert function even when fieldval is
6823 zero if the insert function would translate that zero to a
6824 bit pattern other than all zeros. */
6825 if ((fieldval
!= 0 && APPLY_RELOC
) || operand
->insert
!= NULL
)
6828 unsigned char *where
;
6830 /* Fetch the instruction, insert the fully resolved operand
6831 value, and stuff the instruction back again. */
6832 where
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6833 if (target_big_endian
)
6835 if (fixP
->fx_size
< 4)
6836 insn
= bfd_getb16 (where
);
6839 insn
= bfd_getb32 (where
);
6840 if (fixP
->fx_size
> 4)
6841 insn
= insn
<< 32 | bfd_getb32 (where
+ 4);
6846 if (fixP
->fx_size
< 4)
6847 insn
= bfd_getl16 (where
);
6850 insn
= bfd_getl32 (where
);
6851 if (fixP
->fx_size
> 4)
6852 insn
= insn
<< 32 | bfd_getl32 (where
+ 4);
6855 insn
= ppc_insert_operand (insn
, operand
, fieldval
,
6856 fixP
->tc_fix_data
.ppc_cpu
,
6857 fixP
->fx_file
, fixP
->fx_line
);
6858 if (target_big_endian
)
6860 if (fixP
->fx_size
< 4)
6861 bfd_putb16 (insn
, where
);
6864 if (fixP
->fx_size
> 4)
6866 bfd_putb32 (insn
, where
+ 4);
6869 bfd_putb32 (insn
, where
);
6874 if (fixP
->fx_size
< 4)
6875 bfd_putl16 (insn
, where
);
6878 if (fixP
->fx_size
> 4)
6880 bfd_putl32 (insn
, where
+ 4);
6883 bfd_putl32 (insn
, where
);
6889 /* Nothing else to do here. */
6892 gas_assert (fixP
->fx_addsy
!= NULL
);
6893 if (fixP
->fx_r_type
== BFD_RELOC_NONE
)
6898 /* Use expr_symbol_where to see if this is an expression
6900 if (expr_symbol_where (fixP
->fx_addsy
, &sfile
, &sline
))
6901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6902 _("unresolved expression that must be resolved"));
6904 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6905 _("unsupported relocation against %s"),
6906 S_GET_NAME (fixP
->fx_addsy
));
6913 /* Handle relocs in data. */
6914 switch (fixP
->fx_r_type
)
6916 case BFD_RELOC_VTABLE_INHERIT
:
6918 && !S_IS_DEFINED (fixP
->fx_addsy
)
6919 && !S_IS_WEAK (fixP
->fx_addsy
))
6920 S_SET_WEAK (fixP
->fx_addsy
);
6923 case BFD_RELOC_VTABLE_ENTRY
:
6928 /* These can appear with @l etc. in data. */
6929 case BFD_RELOC_LO16
:
6930 case BFD_RELOC_LO16_PCREL
:
6931 case BFD_RELOC_HI16
:
6932 case BFD_RELOC_HI16_PCREL
:
6933 case BFD_RELOC_HI16_S
:
6934 case BFD_RELOC_HI16_S_PCREL
:
6935 case BFD_RELOC_PPC64_HIGHER
:
6936 case BFD_RELOC_PPC64_HIGHER_S
:
6937 case BFD_RELOC_PPC64_HIGHEST
:
6938 case BFD_RELOC_PPC64_HIGHEST_S
:
6939 case BFD_RELOC_PPC64_ADDR16_HIGH
:
6940 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
6941 case BFD_RELOC_PPC64_ADDR64_LOCAL
:
6944 case BFD_RELOC_PPC_DTPMOD
:
6945 case BFD_RELOC_PPC_TPREL
:
6946 case BFD_RELOC_PPC_DTPREL
:
6947 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6950 /* Just punt all of these to the linker. */
6951 case BFD_RELOC_PPC_B16_BRTAKEN
:
6952 case BFD_RELOC_PPC_B16_BRNTAKEN
:
6953 case BFD_RELOC_16_GOTOFF
:
6954 case BFD_RELOC_LO16_GOTOFF
:
6955 case BFD_RELOC_HI16_GOTOFF
:
6956 case BFD_RELOC_HI16_S_GOTOFF
:
6957 case BFD_RELOC_LO16_PLTOFF
:
6958 case BFD_RELOC_HI16_PLTOFF
:
6959 case BFD_RELOC_HI16_S_PLTOFF
:
6960 case BFD_RELOC_PPC_COPY
:
6961 case BFD_RELOC_PPC_GLOB_DAT
:
6962 case BFD_RELOC_16_BASEREL
:
6963 case BFD_RELOC_LO16_BASEREL
:
6964 case BFD_RELOC_HI16_BASEREL
:
6965 case BFD_RELOC_HI16_S_BASEREL
:
6966 case BFD_RELOC_PPC_TLS
:
6967 case BFD_RELOC_PPC_DTPREL16_LO
:
6968 case BFD_RELOC_PPC_DTPREL16_HI
:
6969 case BFD_RELOC_PPC_DTPREL16_HA
:
6970 case BFD_RELOC_PPC_TPREL16_LO
:
6971 case BFD_RELOC_PPC_TPREL16_HI
:
6972 case BFD_RELOC_PPC_TPREL16_HA
:
6973 case BFD_RELOC_PPC_GOT_TLSGD16
:
6974 case BFD_RELOC_PPC_GOT_TLSGD16_LO
:
6975 case BFD_RELOC_PPC_GOT_TLSGD16_HI
:
6976 case BFD_RELOC_PPC_GOT_TLSGD16_HA
:
6977 case BFD_RELOC_PPC_GOT_TLSLD16
:
6978 case BFD_RELOC_PPC_GOT_TLSLD16_LO
:
6979 case BFD_RELOC_PPC_GOT_TLSLD16_HI
:
6980 case BFD_RELOC_PPC_GOT_TLSLD16_HA
:
6981 case BFD_RELOC_PPC_GOT_DTPREL16
:
6982 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
6983 case BFD_RELOC_PPC_GOT_DTPREL16_HI
:
6984 case BFD_RELOC_PPC_GOT_DTPREL16_HA
:
6985 case BFD_RELOC_PPC_GOT_TPREL16
:
6986 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
6987 case BFD_RELOC_PPC_GOT_TPREL16_HI
:
6988 case BFD_RELOC_PPC_GOT_TPREL16_HA
:
6989 case BFD_RELOC_24_PLT_PCREL
:
6990 case BFD_RELOC_PPC_LOCAL24PC
:
6991 case BFD_RELOC_32_PLT_PCREL
:
6992 case BFD_RELOC_GPREL16
:
6993 case BFD_RELOC_PPC_VLE_SDAREL_LO16A
:
6994 case BFD_RELOC_PPC_VLE_SDAREL_HI16A
:
6995 case BFD_RELOC_PPC_VLE_SDAREL_HA16A
:
6996 case BFD_RELOC_PPC_EMB_NADDR32
:
6997 case BFD_RELOC_PPC_EMB_NADDR16
:
6998 case BFD_RELOC_PPC_EMB_NADDR16_LO
:
6999 case BFD_RELOC_PPC_EMB_NADDR16_HI
:
7000 case BFD_RELOC_PPC_EMB_NADDR16_HA
:
7001 case BFD_RELOC_PPC_EMB_SDAI16
:
7002 case BFD_RELOC_PPC_EMB_SDA2REL
:
7003 case BFD_RELOC_PPC_EMB_SDA2I16
:
7004 case BFD_RELOC_PPC_EMB_SDA21
:
7005 case BFD_RELOC_PPC_VLE_SDA21_LO
:
7006 case BFD_RELOC_PPC_EMB_MRKREF
:
7007 case BFD_RELOC_PPC_EMB_RELSEC16
:
7008 case BFD_RELOC_PPC_EMB_RELST_LO
:
7009 case BFD_RELOC_PPC_EMB_RELST_HI
:
7010 case BFD_RELOC_PPC_EMB_RELST_HA
:
7011 case BFD_RELOC_PPC_EMB_BIT_FLD
:
7012 case BFD_RELOC_PPC_EMB_RELSDA
:
7013 case BFD_RELOC_PPC64_TOC
:
7014 case BFD_RELOC_PPC_TOC16
:
7015 case BFD_RELOC_PPC64_TOC16_LO
:
7016 case BFD_RELOC_PPC64_TOC16_HI
:
7017 case BFD_RELOC_PPC64_TOC16_HA
:
7018 case BFD_RELOC_PPC64_DTPREL16_HIGH
:
7019 case BFD_RELOC_PPC64_DTPREL16_HIGHA
:
7020 case BFD_RELOC_PPC64_DTPREL16_HIGHER
:
7021 case BFD_RELOC_PPC64_DTPREL16_HIGHERA
:
7022 case BFD_RELOC_PPC64_DTPREL16_HIGHEST
:
7023 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA
:
7024 case BFD_RELOC_PPC64_TPREL16_HIGH
:
7025 case BFD_RELOC_PPC64_TPREL16_HIGHA
:
7026 case BFD_RELOC_PPC64_TPREL16_HIGHER
:
7027 case BFD_RELOC_PPC64_TPREL16_HIGHERA
:
7028 case BFD_RELOC_PPC64_TPREL16_HIGHEST
:
7029 case BFD_RELOC_PPC64_TPREL16_HIGHESTA
:
7030 case BFD_RELOC_PPC64_TLS_PCREL
:
7036 case BFD_RELOC_NONE
:
7038 case BFD_RELOC_CTOR
:
7040 case BFD_RELOC_32_PCREL
:
7043 case BFD_RELOC_64_PCREL
:
7045 case BFD_RELOC_16_PCREL
:
7051 _("Gas failure, reloc value %d\n"), fixP
->fx_r_type
);
7056 if (fixP
->fx_size
&& APPLY_RELOC
)
7057 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
7058 fieldval
, fixP
->fx_size
);
7060 && (seg
->flags
& SEC_CODE
) != 0
7061 && fixP
->fx_size
== 4
7064 && (fixP
->fx_r_type
== BFD_RELOC_32
7065 || fixP
->fx_r_type
== BFD_RELOC_CTOR
7066 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
))
7067 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
7068 _("data in executable section"));
7072 ppc_elf_validate_fix (fixP
, seg
);
7073 fixP
->fx_addnumber
= value
;
7075 /* PowerPC uses RELA relocs, ie. the reloc addend is stored separately
7076 from the section contents. If we are going to be emitting a reloc
7077 then the section contents are immaterial, so don't warn if they
7078 happen to overflow. Leave such warnings to ld. */
7081 fixP
->fx_no_overflow
= 1;
7083 /* Arrange to emit .TOC. as a normal symbol if used in anything
7084 but .TOC.@tocbase. */
7086 && fixP
->fx_r_type
!= BFD_RELOC_PPC64_TOC
7087 && fixP
->fx_addsy
!= NULL
7088 && strcmp (S_GET_NAME (fixP
->fx_addsy
), ".TOC.") == 0)
7089 symbol_get_bfdsym (fixP
->fx_addsy
)->flags
|= BSF_KEEP
;
7092 if (fixP
->fx_r_type
!= BFD_RELOC_PPC_TOC16
)
7093 fixP
->fx_addnumber
= 0;
7096 /* We want to use the offset within the toc, not the actual VMA
7098 fixP
->fx_addnumber
= (- bfd_section_vma (S_GET_SEGMENT (fixP
->fx_addsy
))
7099 - S_GET_VALUE (ppc_toc_csect
));
7100 /* Set *valP to avoid errors. */
7106 /* Generate a reloc for a fixup. */
7109 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
, fixS
*fixp
)
7113 reloc
= XNEW (arelent
);
7115 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7116 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7117 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7118 /* BFD_RELOC_PPC64_TLS_PCREL generates R_PPC64_TLS with an odd r_offset. */
7119 if (fixp
->fx_r_type
== BFD_RELOC_PPC64_TLS_PCREL
)
7121 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
7122 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
7124 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7125 _("reloc %d not supported by object file format"),
7126 (int) fixp
->fx_r_type
);
7129 reloc
->addend
= fixp
->fx_addnumber
;
7135 ppc_cfi_frame_initial_instructions (void)
7137 cfi_add_CFA_def_cfa (1, 0);
7141 tc_ppc_regname_to_dw2regnum (char *regname
)
7143 unsigned int regnum
= -1;
7147 static struct { const char *name
; int dw2regnum
; } regnames
[] =
7149 { "sp", 1 }, { "r.sp", 1 }, { "rtoc", 2 }, { "r.toc", 2 },
7150 { "mq", 64 }, { "lr", 65 }, { "ctr", 66 }, { "ap", 67 },
7151 { "cr", 70 }, { "xer", 76 }, { "vrsave", 109 }, { "vscr", 110 },
7152 { "spe_acc", 111 }, { "spefscr", 112 }
7155 for (i
= 0; i
< ARRAY_SIZE (regnames
); ++i
)
7156 if (strcmp (regnames
[i
].name
, regname
) == 0)
7157 return regnames
[i
].dw2regnum
;
7159 if (regname
[0] == 'r' || regname
[0] == 'f' || regname
[0] == 'v')
7161 p
= regname
+ 1 + (regname
[1] == '.');
7162 regnum
= strtoul (p
, &q
, 10);
7163 if (p
== q
|| *q
|| regnum
>= 32)
7165 if (regname
[0] == 'f')
7167 else if (regname
[0] == 'v')
7170 else if (regname
[0] == 'c' && regname
[1] == 'r')
7172 p
= regname
+ 2 + (regname
[2] == '.');
7173 if (p
[0] < '0' || p
[0] > '7' || p
[1])
7175 regnum
= p
[0] - '0' + 68;