1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 /* Let riscv_after_parse_args set the default value according to xlen. */
67 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
68 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
71 /* Need to sync the version with RISC-V compiler. */
72 #ifndef DEFAULT_RISCV_ISA_SPEC
73 #define DEFAULT_RISCV_ISA_SPEC "2.2"
76 #ifndef DEFAULT_RISCV_PRIV_SPEC
77 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
80 static const char default_arch
[] = DEFAULT_ARCH
;
81 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
82 static enum riscv_isa_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
83 static enum riscv_priv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
85 static unsigned xlen
= 0; /* The width of an x-register. */
86 static unsigned abi_xlen
= 0; /* The width of a pointer in the ABI. */
87 static bfd_boolean rve_abi
= FALSE
;
90 FLOAT_ABI_DEFAULT
= -1,
96 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
98 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
99 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
101 static unsigned elf_flags
= 0;
103 /* Set the default_isa_spec. Return 0 if the spec isn't supported.
104 Otherwise, return 1. */
107 riscv_set_default_isa_spec (const char *s
)
109 enum riscv_isa_spec_class
class;
110 if (!riscv_get_isa_spec_class (s
, &class))
112 as_bad ("unknown default ISA spec `%s' set by "
113 "-misa-spec or --with-isa-spec", s
);
117 default_isa_spec
= class;
121 /* Set the default_priv_spec. Find the privileged elf attributes when
122 the input string is NULL. Return 0 if the spec isn't supported.
123 Otherwise, return 1. */
126 riscv_set_default_priv_spec (const char *s
)
128 enum riscv_priv_spec_class
class;
129 unsigned major
, minor
, revision
;
132 if (riscv_get_priv_spec_class (s
, &class))
134 default_priv_spec
= class;
140 as_bad (_("unknown default privileged spec `%s' set by "
141 "-mpriv-spec or --with-priv-spec"), s
);
145 /* Set the default_priv_spec by the privileged elf attributes. */
146 attr
= elf_known_obj_attributes_proc (stdoutput
);
147 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
148 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
149 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
150 if (riscv_get_priv_spec_class_from_numbers (major
,
155 /* 0.0.0 is meaningless. */
156 if (class == PRIV_SPEC_CLASS_NONE
)
159 default_priv_spec
= class;
163 /* Still can not find the privileged spec class. */
164 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
165 "privileged elf attributes"), major
, minor
, revision
);
169 /* This is the set of options which the .option pseudo-op may modify. */
170 struct riscv_set_options
172 int pic
; /* Generate position-independent code. */
173 int rvc
; /* Generate RVC code. */
174 int rve
; /* Generate RVE code. */
175 int relax
; /* Emit relocs the linker is allowed to relax. */
176 int arch_attr
; /* Emit architecture and privileged elf attributes. */
177 int csr_check
; /* Enable the CSR checking. */
180 static struct riscv_set_options riscv_opts
=
186 DEFAULT_RISCV_ATTR
, /* arch_attr */
191 riscv_set_rvc (bfd_boolean rvc_value
)
194 elf_flags
|= EF_RISCV_RVC
;
196 riscv_opts
.rvc
= rvc_value
;
200 riscv_set_rve (bfd_boolean rve_value
)
202 riscv_opts
.rve
= rve_value
;
205 static riscv_subset_list_t riscv_subsets
;
208 riscv_subset_supports (const char *feature
)
210 struct riscv_subset_t
*subset
;
212 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
215 return riscv_lookup_subset (&riscv_subsets
, feature
, &subset
);
219 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
223 case INSN_CLASS_I
: return riscv_subset_supports ("i");
224 case INSN_CLASS_C
: return riscv_subset_supports ("c");
225 case INSN_CLASS_A
: return riscv_subset_supports ("a");
226 case INSN_CLASS_M
: return riscv_subset_supports ("m");
227 case INSN_CLASS_F
: return riscv_subset_supports ("f");
228 case INSN_CLASS_D
: return riscv_subset_supports ("d");
229 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
231 case INSN_CLASS_F_AND_C
:
232 return (riscv_subset_supports ("f")
233 && riscv_subset_supports ("c"));
234 case INSN_CLASS_D_AND_C
:
235 return (riscv_subset_supports ("d")
236 && riscv_subset_supports ("c"));
238 case INSN_CLASS_ZICSR
:
239 return riscv_subset_supports ("zicsr");
240 case INSN_CLASS_ZIFENCEI
:
241 return riscv_subset_supports ("zifencei");
242 case INSN_CLASS_ZIHINTPAUSE
:
243 return riscv_subset_supports ("zihintpause");
246 return riscv_subset_supports ("zba");
248 return riscv_subset_supports ("zbb");
250 return riscv_subset_supports ("zbc");
251 case INSN_CLASS_ZBA_OR_ZBB
:
252 return (riscv_subset_supports ("zba")
253 || riscv_subset_supports ("zbb"));
256 as_fatal ("internal: unreachable");
261 /* Handle of the extension with version hash table. */
262 static htab_t ext_version_hash
= NULL
;
265 init_ext_version_hash (const struct riscv_ext_version
*table
)
268 htab_t hash
= str_htab_create ();
270 while (table
[i
].name
)
272 const char *name
= table
[i
].name
;
273 if (str_hash_insert (hash
, name
, &table
[i
], 0) != NULL
)
274 as_fatal (_("internal: duplicate %s"), name
);
278 && strcmp (table
[i
].name
, name
) == 0)
286 riscv_get_default_ext_version (const char *name
,
290 struct riscv_ext_version
*ext
;
292 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
295 ext
= (struct riscv_ext_version
*) str_hash_find (ext_version_hash
, name
);
298 && strcmp (ext
->name
, name
) == 0)
300 if (ext
->isa_spec_class
== ISA_SPEC_CLASS_DRAFT
301 || ext
->isa_spec_class
== default_isa_spec
)
303 *major_version
= ext
->major_version
;
304 *minor_version
= ext
->minor_version
;
311 /* Set which ISA and extensions are available. */
314 riscv_set_arch (const char *s
)
316 riscv_parse_subset_t rps
;
317 rps
.subset_list
= &riscv_subsets
;
318 rps
.error_handler
= as_bad
;
320 rps
.get_default_version
= riscv_get_default_ext_version
;
325 riscv_release_subset_list (&riscv_subsets
);
326 riscv_parse_subset (&rps
, s
);
329 /* Indicate -mabi option is explictly set. */
330 static bfd_boolean explicit_mabi
= FALSE
;
333 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
336 float_abi
= new_float_abi
;
340 /* If the -mabi option isn't set, then set the abi according to the
341 ISA string. Otherwise, check if there is any conflict. */
344 riscv_set_abi_by_arch (void)
348 if (riscv_subset_supports ("q"))
349 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, FALSE
);
350 else if (riscv_subset_supports ("d"))
351 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, FALSE
);
353 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, FALSE
);
357 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
359 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
360 else if (abi_xlen
< xlen
)
361 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
364 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
365 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
366 elf_flags
|= float_abi
<< 1;
369 elf_flags
|= EF_RISCV_RVE
;
372 /* Handle of the OPCODE hash table. */
373 static htab_t op_hash
= NULL
;
375 /* Handle of the type of .insn hash table. */
376 static htab_t insn_type_hash
= NULL
;
378 /* This array holds the chars that always start a comment. If the
379 pre-processor is disabled, these aren't very useful. */
380 const char comment_chars
[] = "#";
382 /* This array holds the chars that only start a comment at the beginning of
383 a line. If the line seems to have the form '# 123 filename'
384 .line and .file directives will appear in the pre-processed output
386 Note that input_file.c hand checks for '#' at the beginning of the
387 first line of the input file. This is because the compiler outputs
388 #NO_APP at the beginning of its output.
390 Also note that C style comments are always supported. */
391 const char line_comment_chars
[] = "#";
393 /* This array holds machine specific line separator characters. */
394 const char line_separator_chars
[] = ";";
396 /* Chars that can be used to separate mant from exp in floating point nums. */
397 const char EXP_CHARS
[] = "eE";
399 /* Chars that mean this number is a floating point constant.
400 As in 0f12.456 or 0d1.2345e12. */
401 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
403 /* Indicate we are already assemble any instructions or not. */
404 static bfd_boolean start_assemble
= FALSE
;
406 /* Indicate ELF attributes are explicitly set. */
407 static bfd_boolean explicit_attr
= FALSE
;
409 /* Indicate CSR or priv instructions are explicitly used. */
410 static bfd_boolean explicit_priv_attr
= FALSE
;
412 /* Macros for encoding relaxation state for RVC branches and far jumps. */
413 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
416 | ((uncond) ? 1 : 0) \
419 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
420 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
421 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
422 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
424 /* Is the given value a sign-extended 32-bit value? */
425 #define IS_SEXT_32BIT_NUM(x) \
426 (((x) &~ (offsetT) 0x7fffffff) == 0 \
427 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
429 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
430 #define IS_ZEXT_32BIT_NUM(x) \
431 (((x) &~ (offsetT) 0xffffffff) == 0 \
432 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
434 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
435 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
436 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
437 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
439 /* Determine if an instruction matches an opcode. */
440 #define OPCODE_MATCHES(OPCODE, OP) \
441 (((OPCODE) & MASK_##OP) == MATCH_##OP)
443 static char *expr_end
;
445 /* The default target format to use. */
448 riscv_target_format (void)
450 if (target_big_endian
)
451 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
453 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
456 /* Return the length of instruction INSN. */
458 static inline unsigned int
459 insn_length (const struct riscv_cl_insn
*insn
)
461 return riscv_insn_length (insn
->insn_opcode
);
464 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
467 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
470 insn
->insn_opcode
= mo
->match
;
476 /* Install INSN at the location specified by its "frag" and "where" fields. */
479 install_insn (const struct riscv_cl_insn
*insn
)
481 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
482 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
485 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
486 and install the opcode in the new location. */
489 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
493 if (insn
->fixp
!= NULL
)
495 insn
->fixp
->fx_frag
= frag
;
496 insn
->fixp
->fx_where
= where
;
501 /* Add INSN to the end of the output. */
504 add_fixed_insn (struct riscv_cl_insn
*insn
)
506 char *f
= frag_more (insn_length (insn
));
507 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
511 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
512 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
514 frag_grow (max_chars
);
515 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
516 frag_var (rs_machine_dependent
, max_chars
, var
,
517 subtype
, symbol
, offset
, NULL
);
520 /* Compute the length of a branch sequence, and adjust the stored length
521 accordingly. If FRAGP is NULL, the worst-case length is returned. */
524 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
526 int jump
, rvc
, length
= 8;
531 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
532 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
533 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
535 /* Assume jumps are in range; the linker will catch any that aren't. */
536 length
= jump
? 4 : 8;
538 if (fragp
->fr_symbol
!= NULL
539 && S_IS_DEFINED (fragp
->fr_symbol
)
540 && !S_IS_WEAK (fragp
->fr_symbol
)
541 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
543 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
544 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
545 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
547 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
549 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
551 else if (!jump
&& rvc
)
556 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
561 /* Information about an opcode name, mnemonics and its value. */
568 /* List for all supported opcode name. */
569 static const struct opcode_name_t opcode_name_list
[] =
614 /* Hash table for lookup opcode name. */
615 static htab_t opcode_names_hash
= NULL
;
617 /* Initialization for hash table of opcode name. */
620 init_opcode_names_hash (void)
622 const struct opcode_name_t
*opcode
;
624 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
625 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
626 as_fatal (_("internal: duplicate %s"), opcode
->name
);
629 /* Find `s` is a valid opcode name or not, return the opcode name info
632 static const struct opcode_name_t
*
633 opcode_name_lookup (char **s
)
637 struct opcode_name_t
*o
;
639 /* Find end of name. */
641 if (is_name_beginner (*e
))
643 while (is_part_of_name (*e
))
646 /* Terminate name. */
650 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
652 /* Advance to next token if one was recognized. */
671 static htab_t reg_names_hash
= NULL
;
672 static htab_t csr_extra_hash
= NULL
;
674 #define ENCODE_REG_HASH(cls, n) \
675 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
676 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
677 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
680 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
682 void *hash
= ENCODE_REG_HASH (class, n
);
683 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
684 as_fatal (_("internal: duplicate %s"), name
);
688 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
692 for (i
= 0; i
< n
; i
++)
693 hash_reg_name (class, names
[i
], i
);
696 /* Init hash table csr_extra_hash to handle CSR. */
699 riscv_init_csr_hash (const char *name
,
701 enum riscv_csr_class
class,
702 enum riscv_priv_spec_class define_version
,
703 enum riscv_priv_spec_class abort_version
)
705 struct riscv_csr_extra
*entry
, *pre_entry
;
706 bfd_boolean need_enrty
= TRUE
;
709 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
710 while (need_enrty
&& entry
!= NULL
)
712 if (entry
->csr_class
== class
713 && entry
->address
== address
714 && entry
->define_version
== define_version
715 && entry
->abort_version
== abort_version
)
725 entry
= XNEW (struct riscv_csr_extra
);
726 entry
->csr_class
= class;
727 entry
->address
= address
;
728 entry
->define_version
= define_version
;
729 entry
->abort_version
= abort_version
;
732 if (pre_entry
== NULL
)
733 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
735 pre_entry
->next
= entry
;
738 /* Return the CSR address after checking the ISA dependency and
739 the privileged spec version.
741 There are one warning and two errors for CSR,
743 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
744 or the privileged spec, report warning only if -mcsr-check is set.
745 Unknown CSR: the CSR has never been defined, report error.
746 Improper CSR: the CSR number over the range (> 0xfff), report error. */
749 riscv_csr_address (const char *csr_name
,
750 struct riscv_csr_extra
*entry
)
752 struct riscv_csr_extra
*saved_entry
= entry
;
753 enum riscv_csr_class csr_class
= entry
->csr_class
;
754 bfd_boolean need_check_version
= TRUE
;
755 bfd_boolean result
= TRUE
;
760 result
= riscv_subset_supports ("i");
763 result
= (xlen
== 32 && riscv_subset_supports ("i"));
766 result
= riscv_subset_supports ("f");
767 need_check_version
= FALSE
;
769 case CSR_CLASS_DEBUG
:
770 need_check_version
= FALSE
;
773 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
776 if (riscv_opts
.csr_check
&& !result
)
777 as_warn (_("invalid CSR `%s' for the current ISA"), csr_name
);
779 while (entry
!= NULL
)
781 if (!need_check_version
782 || (default_priv_spec
>= entry
->define_version
783 && default_priv_spec
< entry
->abort_version
))
785 /* Find the CSR according to the specific version. */
786 return entry
->address
;
791 /* Can not find the CSR address from the chosen privileged version,
792 so use the newly defined value. */
793 if (riscv_opts
.csr_check
)
795 const char *priv_name
= riscv_get_priv_spec_name (default_priv_spec
);
797 if (priv_name
!= NULL
)
798 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
799 csr_name
, priv_name
);
802 return saved_entry
->address
;
805 /* Return -1 if the CSR has never been defined. Otherwise, return
809 reg_csr_lookup_internal (const char *s
)
811 struct riscv_csr_extra
*r
=
812 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
817 return riscv_csr_address (s
, r
);
821 reg_lookup_internal (const char *s
, enum reg_class
class)
825 if (class == RCLASS_CSR
)
826 return reg_csr_lookup_internal (s
);
828 r
= str_hash_find (reg_names_hash
, s
);
829 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
832 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
835 return DECODE_REG_NUM (r
);
839 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
845 /* Find end of name. */
847 if (is_name_beginner (*e
))
849 while (is_part_of_name (*e
))
852 /* Terminate name. */
856 /* Look for the register. Advance to next token if one was recognized. */
857 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
867 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
869 const char *p
= strchr (*s
, ',');
870 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
875 for (i
= 0; i
< size
; i
++)
876 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
886 /* For consistency checking, verify that all bits are specified either
887 by the match/mask part of the instruction definition, or by the
888 operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
891 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
893 const char *p
= opc
->args
;
895 insn_t used_bits
= opc
->mask
;
897 insn_t required_bits
;
900 insn_width
= 8 * riscv_insn_length (opc
->match
);
902 insn_width
= 8 * length
;
904 required_bits
= ~0ULL >> (64 - insn_width
);
906 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
908 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
909 opc
->name
, opc
->args
);
913 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
920 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
921 case 'c': break; /* RS1, constrained to equal sp. */
922 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
923 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
924 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
925 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
926 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
927 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
928 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
929 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
930 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
931 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
932 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
933 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
934 case 'w': break; /* RS1S, constrained to equal RD. */
935 case 'x': break; /* RS2S, constrained to equal RD. */
936 case 'z': break; /* RS2S, constrained to be x0. */
937 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
938 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
939 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
940 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
941 case 'U': break; /* RS1, constrained to equal RD. */
942 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
943 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
944 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
945 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
946 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
947 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
948 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
949 case 'F': /* RVC funct for .insn directive. */
952 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
953 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
954 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
955 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
957 as_bad (_("internal: bad RISC-V opcode "
958 "(unknown operand type `CF%c'): %s %s"),
959 c
, opc
->name
, opc
->args
);
964 as_bad (_("internal: bad RISC-V opcode "
965 "(unknown operand type `C%c'): %s %s"),
966 c
, opc
->name
, opc
->args
);
973 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
974 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
976 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
977 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
978 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
980 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
981 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
982 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
);
984 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
985 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
986 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
987 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
988 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
989 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
990 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
991 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
993 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
994 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
995 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
996 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
997 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1003 case 'F': /* Funct for .insn directive. */
1006 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1007 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1008 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1010 as_bad (_("internal: bad RISC-V opcode "
1011 "(unknown operand type `F%c'): %s %s"),
1012 c
, opc
->name
, opc
->args
);
1016 case 'O': /* Opcode for .insn directive. */
1019 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1020 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1022 as_bad (_("internal: bad RISC-V opcode "
1023 "(unknown operand type `F%c'): %s %s"),
1024 c
, opc
->name
, opc
->args
);
1029 as_bad (_("internal: bad RISC-V opcode "
1030 "(unknown operand type `%c'): %s %s"),
1031 c
, opc
->name
, opc
->args
);
1035 if (used_bits
!= required_bits
)
1037 as_bad (_("internal: bad RISC-V opcode "
1038 "(bits 0x%lx undefined): %s %s"),
1039 ~(unsigned long)(used_bits
& required_bits
),
1040 opc
->name
, opc
->args
);
1046 struct percent_op_match
1049 bfd_reloc_code_real_type reloc
;
1052 /* Common hash table initialization function for instruction and .insn
1056 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1057 bfd_boolean insn_directive_p
)
1061 htab_t hash
= str_htab_create ();
1062 while (opcodes
[i
].name
)
1064 const char *name
= opcodes
[i
].name
;
1065 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1066 as_fatal (_("internal: duplicate %s"), name
);
1070 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1072 if (insn_directive_p
)
1073 length
= ((name
[0] == 'c') ? 2 : 4);
1075 length
= 0; /* Let assembler determine the length. */
1076 if (!validate_riscv_insn (&opcodes
[i
], length
))
1077 as_fatal (_("internal: broken assembler. "
1078 "No assembly attempted"));
1081 gas_assert (!insn_directive_p
);
1084 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1090 /* This function is called once, at assembler startup time. It should set up
1091 all the tables, etc. that the MD part of the assembler will need. */
1096 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1098 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1099 as_warn (_("could not set architecture and machine"));
1101 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1102 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1104 reg_names_hash
= str_htab_create ();
1105 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1106 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1107 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1108 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1109 /* Add "fp" as an alias for "s0". */
1110 hash_reg_name (RCLASS_GPR
, "fp", 8);
1112 /* Create and insert CSR hash tables. */
1113 csr_extra_hash
= str_htab_create ();
1114 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1115 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1116 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1117 DECLARE_CSR(name, num, class, define_version, abort_version);
1118 #include "opcode/riscv-opc.h"
1121 opcode_names_hash
= str_htab_create ();
1122 init_opcode_names_hash ();
1124 /* Set the default alignment for the text section. */
1125 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1129 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1136 case BFD_RELOC_RISCV_HI20
:
1137 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1139 case BFD_RELOC_RISCV_LO12_S
:
1140 return ENCODE_STYPE_IMM (value
);
1142 case BFD_RELOC_RISCV_LO12_I
:
1143 return ENCODE_ITYPE_IMM (value
);
1150 /* Output an instruction. IP is the instruction information.
1151 ADDRESS_EXPR is an operand of the instruction to be used with
1155 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1156 bfd_reloc_code_real_type reloc_type
)
1158 dwarf2_emit_insn (0);
1160 if (reloc_type
!= BFD_RELOC_UNUSED
)
1162 reloc_howto_type
*howto
;
1164 gas_assert (address_expr
);
1165 if (reloc_type
== BFD_RELOC_12_PCREL
1166 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1168 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1169 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1170 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1172 if (now_seg
== absolute_section
)
1174 as_bad (_("relaxable branches not supported in absolute section"));
1178 add_relaxed_insn (ip
, worst_case
, best_case
,
1179 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1180 address_expr
->X_add_symbol
,
1181 address_expr
->X_add_number
);
1186 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1188 as_bad (_("internal: usupported RISC-V relocation number %d"),
1191 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1192 bfd_get_reloc_size (howto
),
1193 address_expr
, FALSE
, reloc_type
);
1195 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1199 add_fixed_insn (ip
);
1202 /* We need to start a new frag after any instruction that can be
1203 optimized away or compressed by the linker during relaxation, to prevent
1204 the assembler from computing static offsets across such an instruction.
1205 This is necessary to get correct EH info. */
1206 if (reloc_type
== BFD_RELOC_RISCV_HI20
1207 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1208 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1209 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1211 frag_wane (frag_now
);
1216 /* Build an instruction created by a macro expansion. This is passed
1217 a pointer to the count of instructions created so far, an expression,
1218 the name of the instruction to build, an operand format string, and
1219 corresponding arguments. */
1222 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1224 const struct riscv_opcode
*mo
;
1225 struct riscv_cl_insn insn
;
1226 bfd_reloc_code_real_type r
;
1229 va_start (args
, fmt
);
1231 r
= BFD_RELOC_UNUSED
;
1232 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1235 /* Find a non-RVC variant of the instruction. append_insn will compress
1237 while (riscv_insn_length (mo
->match
) < 4)
1239 gas_assert (strcmp (name
, mo
->name
) == 0);
1241 create_insn (&insn
, mo
);
1247 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1251 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1255 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1261 gas_assert (ep
!= NULL
);
1262 r
= va_arg (args
, int);
1270 as_fatal (_("internal: invalid macro"));
1275 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1277 append_insn (&insn
, ep
, r
);
1280 /* Build an instruction created by a macro expansion. Like md_assemble but
1281 accept a printf-style format string and arguments. */
1284 md_assemblef (const char *format
, ...)
1290 va_start (ap
, format
);
1292 r
= vasprintf (&buf
, format
, ap
);
1295 as_fatal (_("internal: vasprintf failed"));
1303 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1307 normalize_constant_expr (expressionS
*ex
)
1311 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1312 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1313 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1317 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1318 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1321 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1322 bfd_boolean maybe_csr
)
1324 if (ex
->X_op
== O_big
)
1325 as_bad (_("unsupported large constant"));
1326 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1327 as_bad (_("unknown CSR `%s'"),
1328 S_GET_NAME (ex
->X_add_symbol
));
1329 else if (ex
->X_op
!= O_constant
)
1330 as_bad (_("instruction %s requires absolute expression"),
1332 normalize_constant_expr (ex
);
1336 make_internal_label (void)
1338 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1342 /* Load an entry from the GOT. */
1345 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1346 const char *lo_insn
, const char *lo_pattern
,
1347 bfd_reloc_code_real_type hi_reloc
,
1348 bfd_reloc_code_real_type lo_reloc
)
1351 ep2
.X_op
= O_symbol
;
1352 ep2
.X_add_symbol
= make_internal_label ();
1353 ep2
.X_add_number
= 0;
1355 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1356 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1360 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1361 bfd_reloc_code_real_type hi_reloc
,
1362 bfd_reloc_code_real_type lo_reloc
)
1364 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1368 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1369 bfd_reloc_code_real_type hi_reloc
,
1370 bfd_reloc_code_real_type lo_reloc
)
1372 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1375 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1378 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1379 bfd_reloc_code_real_type reloc
)
1381 /* Ensure the jalr is emitted to the same frag as the auipc. */
1383 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1384 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1385 /* See comment at end of append_insn. */
1386 frag_wane (frag_now
);
1390 /* Load an integer constant into a register. */
1393 load_const (int reg
, expressionS
*ep
)
1395 int shift
= RISCV_IMM_BITS
;
1396 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1397 expressionS upper
= *ep
, lower
= *ep
;
1398 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1399 upper
.X_add_number
-= lower
.X_add_number
;
1401 if (ep
->X_op
!= O_constant
)
1403 as_bad (_("unsupported large constant"));
1407 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1409 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1410 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1413 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1414 load_const (reg
, &upper
);
1416 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1417 if (lower
.X_add_number
!= 0)
1418 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1419 lower
.X_add_number
);
1423 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1426 if (upper
.X_add_number
!= 0)
1428 /* Discard low part and zero-extend upper immediate. */
1429 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1431 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1435 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1436 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1437 lower
.X_add_number
);
1441 /* Zero extend and sign extend byte/half-word/word. */
1444 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bfd_boolean sign
)
1448 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1449 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1453 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1454 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1458 /* Expand RISC-V assembly macros into one or more instructions. */
1461 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1462 bfd_reloc_code_real_type
*imm_reloc
)
1464 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1465 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1466 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1467 int mask
= ip
->insn_mo
->mask
;
1472 load_const (rd
, imm_expr
);
1477 /* Load the address of a symbol into a register. */
1478 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1479 as_bad (_("offset too large"));
1481 if (imm_expr
->X_op
== O_constant
)
1482 load_const (rd
, imm_expr
);
1483 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol. */
1484 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1485 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1486 else /* Local PIC symbol, or any non-PIC symbol. */
1487 pcrel_load (rd
, rd
, imm_expr
, "addi",
1488 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1492 pcrel_load (rd
, rd
, imm_expr
, "addi",
1493 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1497 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1498 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1502 pcrel_load (rd
, rd
, imm_expr
, "lb",
1503 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1507 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1508 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1512 pcrel_load (rd
, rd
, imm_expr
, "lh",
1513 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1517 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1518 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1522 pcrel_load (rd
, rd
, imm_expr
, "lw",
1523 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1527 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1528 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1532 pcrel_load (rd
, rd
, imm_expr
, "ld",
1533 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1537 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1538 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1542 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1543 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1547 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1548 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1552 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1553 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1557 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1558 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1562 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1563 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1567 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1568 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1572 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1573 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1577 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1581 riscv_ext (rd
, rs1
, xlen
- 16, FALSE
);
1585 riscv_ext (rd
, rs1
, xlen
- 32, FALSE
);
1589 riscv_ext (rd
, rs1
, xlen
- 8, TRUE
);
1593 riscv_ext (rd
, rs1
, xlen
- 16, TRUE
);
1597 as_bad (_("internal: macro %s not implemented"), ip
->insn_mo
->name
);
1602 static const struct percent_op_match percent_op_utype
[] =
1604 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1605 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1606 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1607 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1608 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1609 {"%hi", BFD_RELOC_RISCV_HI20
},
1613 static const struct percent_op_match percent_op_itype
[] =
1615 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1616 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1617 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1621 static const struct percent_op_match percent_op_stype
[] =
1623 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1624 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1625 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1629 static const struct percent_op_match percent_op_rtype
[] =
1631 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1635 static const struct percent_op_match percent_op_null
[] =
1640 /* Return true if *STR points to a relocation operator. When returning true,
1641 move *STR over the operator and store its relocation code in *RELOC.
1642 Leave both *STR and *RELOC alone when returning false. */
1645 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1646 const struct percent_op_match
*percent_op
)
1648 for ( ; percent_op
->str
; percent_op
++)
1649 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1651 int len
= strlen (percent_op
->str
);
1653 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1656 *str
+= strlen (percent_op
->str
);
1657 *reloc
= percent_op
->reloc
;
1659 /* Check whether the output BFD supports this relocation.
1660 If not, issue an error and fall back on something safe. */
1661 if (*reloc
!= BFD_RELOC_UNUSED
1662 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1664 as_bad ("internal: relocation %s isn't supported by the "
1665 "current ABI", percent_op
->str
);
1666 *reloc
= BFD_RELOC_UNUSED
;
1674 my_getExpression (expressionS
*ep
, char *str
)
1678 save_in
= input_line_pointer
;
1679 input_line_pointer
= str
;
1681 expr_end
= input_line_pointer
;
1682 input_line_pointer
= save_in
;
1685 /* Parse string STR as a 16-bit relocatable operand. Store the
1686 expression in *EP and the relocation, if any, in RELOC.
1687 Return the number of relocation operators used (0 or 1).
1689 On exit, EXPR_END points to the first character after the expression. */
1692 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1693 char *str
, const struct percent_op_match
*percent_op
)
1696 unsigned crux_depth
, str_depth
, regno
;
1699 /* First, check for integer registers. No callers can accept a reg, but
1700 we need to avoid accidentally creating a useless undefined symbol below,
1701 if this is an instruction pattern that can't match. A glibc build fails
1702 if this is removed. */
1703 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1705 ep
->X_op
= O_register
;
1706 ep
->X_add_number
= regno
;
1711 /* Search for the start of the main expression.
1713 End the loop with CRUX pointing to the start of the main expression and
1714 with CRUX_DEPTH containing the number of open brackets at that point. */
1721 crux_depth
= str_depth
;
1723 /* Skip over whitespace and brackets, keeping count of the number
1725 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1731 && parse_relocation (&str
, reloc
, percent_op
));
1733 my_getExpression (ep
, crux
);
1736 /* Match every open bracket. */
1737 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1742 as_bad ("unclosed '('");
1749 /* Parse opcode name, could be an mnemonics or number. */
1752 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1753 char *str
, const struct percent_op_match
*percent_op
)
1755 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1759 ep
->X_op
= O_constant
;
1760 ep
->X_add_number
= o
->val
;
1764 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1767 /* Detect and handle implicitly zero load-store offsets. For example,
1768 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1769 an implicit offset was detected. */
1772 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1774 /* Check whether there is only a single bracketed expression left.
1775 If so, it must be the base register and the constant must be zero. */
1776 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1778 ep
->X_op
= O_constant
;
1779 ep
->X_add_number
= 0;
1786 /* All RISC-V CSR instructions belong to one of these classes. */
1795 /* Return which CSR instruction is checking. */
1797 static enum csr_insn_type
1798 riscv_csr_insn_type (insn_t insn
)
1800 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1801 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1803 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1804 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1806 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1807 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1810 return INSN_NOT_CSR
;
1813 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1814 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1815 CSR address is 0x3. */
1818 riscv_csr_read_only_check (insn_t insn
)
1820 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1821 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1822 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1823 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1826 && (((csr_insn
== INSN_CSRRS
1827 || csr_insn
== INSN_CSRRC
)
1829 || csr_insn
== INSN_CSRRW
))
1835 /* Return True if it is a privileged instruction. Otherwise, return FALSE.
1837 uret is actually a N-ext instruction. So it is better to regard it as
1838 an user instruction rather than the priv instruction.
1840 hret is used to return from traps in H-mode. H-mode is removed since
1841 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1842 Therefore, hret should be controlled by the hypervisor spec rather than
1843 priv spec in the future.
1845 dret is defined in the debug spec, so it should be checked in the future,
1849 riscv_is_priv_insn (insn_t insn
)
1851 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
1852 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
1853 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
1854 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
1855 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1856 check it here to keep the compatible. */
1857 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
1860 /* This routine assembles an instruction into its binary format. As a
1861 side effect, it sets the global variable imm_reloc to the type of
1862 relocation to do if one of the operands is an address expression. */
1865 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1866 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
1871 struct riscv_opcode
*insn
;
1876 const struct percent_op_match
*p
;
1877 const char *error
= "unrecognized opcode";
1878 /* Indicate we are assembling instruction with CSR. */
1879 bfd_boolean insn_with_csr
= FALSE
;
1881 /* Parse the name of the instruction. Terminate the string if whitespace
1882 is found so that str_hash_find only sees the name part of the string. */
1883 for (s
= str
; *s
!= '\0'; ++s
)
1891 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
1894 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1896 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1899 if (!riscv_multi_subset_supports (insn
->insn_class
))
1902 create_insn (ip
, insn
);
1905 imm_expr
->X_op
= O_absent
;
1906 *imm_reloc
= BFD_RELOC_UNUSED
;
1907 p
= percent_op_itype
;
1909 for (args
= insn
->args
;; ++args
)
1911 s
+= strspn (s
, " \t");
1914 case '\0': /* End of args. */
1915 if (insn
->pinfo
!= INSN_MACRO
)
1917 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1920 /* For .insn, insn->match and insn->mask are 0. */
1921 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1927 if (riscv_is_priv_insn (ip
->insn_opcode
))
1928 explicit_priv_attr
= TRUE
;
1930 /* Check if we write a read-only CSR by the CSR
1933 && riscv_opts
.csr_check
1934 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1936 /* Restore the character in advance, since we want to
1937 report the detailed warning message here. */
1939 *(argsStart
- 1) = save_c
;
1940 as_warn (_("read-only CSR is written `%s'"), str
);
1941 insn_with_csr
= FALSE
;
1946 /* Successful assembly. */
1948 insn_with_csr
= FALSE
;
1954 case 's': /* RS1 x8-x15. */
1955 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1956 || !(regno
>= 8 && regno
<= 15))
1958 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1960 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1961 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1962 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1965 case 't': /* RS2 x8-x15. */
1966 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1967 || !(regno
>= 8 && regno
<= 15))
1969 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1971 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1972 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1973 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1976 case 'U': /* RS1, constrained to equal RD. */
1977 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1978 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1982 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1984 INSERT_OPERAND (CRS2
, *ip
, regno
);
1986 case 'c': /* RS1, constrained to equal sp. */
1987 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1991 case 'z': /* RS2, constrained to equal x0. */
1992 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1997 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1998 || imm_expr
->X_op
!= O_constant
1999 || imm_expr
->X_add_number
<= 0
2000 || imm_expr
->X_add_number
>= 64)
2002 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2005 imm_expr
->X_op
= O_absent
;
2008 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2009 || imm_expr
->X_op
!= O_constant
2010 || imm_expr
->X_add_number
<= 0
2011 || imm_expr
->X_add_number
>= 32
2012 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2014 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2017 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2018 || imm_expr
->X_op
!= O_constant
2019 || imm_expr
->X_add_number
< 0
2020 || imm_expr
->X_add_number
>= 256
2021 || !VALID_RVC_UIMM8 ((valueT
) imm_expr
->X_add_number
))
2023 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
2026 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2027 || imm_expr
->X_op
!= O_constant
2028 || imm_expr
->X_add_number
== 0
2029 || !VALID_RVC_SIMM3 ((valueT
) imm_expr
->X_add_number
))
2031 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
2034 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2035 || imm_expr
->X_op
!= O_constant
2036 || imm_expr
->X_add_number
== 0
2037 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2039 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2042 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2044 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2045 || imm_expr
->X_op
!= O_constant
2046 || !VALID_RVC_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2048 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
2051 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2053 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2054 || imm_expr
->X_op
!= O_constant
2055 || !VALID_RVC_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2057 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
2060 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2062 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2063 || imm_expr
->X_op
!= O_constant
2064 || !VALID_RVC_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2067 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
2070 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2072 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2073 || imm_expr
->X_op
!= O_constant
2074 || !VALID_RVC_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2077 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
2080 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2081 || imm_expr
->X_op
!= O_constant
2082 /* C.addiw, c.li, and c.andi allow zero immediate.
2083 C.addi allows zero immediate as hint. Otherwise this
2085 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2087 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2090 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2091 || imm_expr
->X_op
!= O_constant
2092 || imm_expr
->X_add_number
== 0
2093 || !VALID_RVC_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2096 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2099 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2100 || imm_expr
->X_op
!= O_constant
2101 || imm_expr
->X_add_number
== 0
2102 || !VALID_RVC_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2105 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
2108 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2110 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2111 || imm_expr
->X_op
!= O_constant
2112 || !VALID_RVC_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2115 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
2118 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2120 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2121 || imm_expr
->X_op
!= O_constant
2122 || !VALID_RVC_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2125 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
2128 p
= percent_op_utype
;
2129 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2132 if (imm_expr
->X_op
!= O_constant
2133 || imm_expr
->X_add_number
<= 0
2134 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2135 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2136 && (imm_expr
->X_add_number
<
2137 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2139 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2142 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2143 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2144 || ((int32_t)imm_expr
->X_add_number
2145 != imm_expr
->X_add_number
))
2147 imm_expr
->X_add_number
=
2148 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2154 case 'S': /* Floating-point RS1 x8-x15. */
2155 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2156 || !(regno
>= 8 && regno
<= 15))
2158 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2160 case 'D': /* Floating-point RS2 x8-x15. */
2161 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2162 || !(regno
>= 8 && regno
<= 15))
2164 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2166 case 'T': /* Floating-point RS2. */
2167 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2169 INSERT_OPERAND (CRS2
, *ip
, regno
);
2175 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2176 || imm_expr
->X_op
!= O_constant
2177 || imm_expr
->X_add_number
< 0
2178 || imm_expr
->X_add_number
>= 64)
2180 as_bad (_("bad value for compressed funct6 "
2181 "field, value must be 0...64"));
2184 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2185 imm_expr
->X_op
= O_absent
;
2190 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2191 || imm_expr
->X_op
!= O_constant
2192 || imm_expr
->X_add_number
< 0
2193 || imm_expr
->X_add_number
>= 16)
2195 as_bad (_("bad value for compressed funct4 "
2196 "field, value must be 0...15"));
2199 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2200 imm_expr
->X_op
= O_absent
;
2205 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2206 || imm_expr
->X_op
!= O_constant
2207 || imm_expr
->X_add_number
< 0
2208 || imm_expr
->X_add_number
>= 8)
2210 as_bad (_("bad value for compressed funct3 "
2211 "field, value must be 0...7"));
2214 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2215 imm_expr
->X_op
= O_absent
;
2220 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2221 || imm_expr
->X_op
!= O_constant
2222 || imm_expr
->X_add_number
< 0
2223 || imm_expr
->X_add_number
>= 4)
2225 as_bad (_("bad value for compressed funct2 "
2226 "field, value must be 0...3"));
2229 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2230 imm_expr
->X_op
= O_absent
;
2235 as_bad (_("internal: unknown compressed funct "
2236 "field specifier `CF%c'"), *args
);
2241 as_bad (_("internal: unknown compressed field "
2242 "specifier `C%c'"), *args
);
2261 case '<': /* Shift amount, 0 - 31. */
2262 my_getExpression (imm_expr
, s
);
2263 check_absolute_expr (ip
, imm_expr
, FALSE
);
2264 if ((unsigned long) imm_expr
->X_add_number
> 31)
2265 as_bad (_("improper shift amount (%lu)"),
2266 (unsigned long) imm_expr
->X_add_number
);
2267 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2268 imm_expr
->X_op
= O_absent
;
2272 case '>': /* Shift amount, 0 - (XLEN-1). */
2273 my_getExpression (imm_expr
, s
);
2274 check_absolute_expr (ip
, imm_expr
, FALSE
);
2275 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2276 as_bad (_("improper shift amount (%lu)"),
2277 (unsigned long) imm_expr
->X_add_number
);
2278 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2279 imm_expr
->X_op
= O_absent
;
2283 case 'Z': /* CSRRxI immediate. */
2284 my_getExpression (imm_expr
, s
);
2285 check_absolute_expr (ip
, imm_expr
, FALSE
);
2286 if ((unsigned long) imm_expr
->X_add_number
> 31)
2287 as_bad (_("improper CSRxI immediate (%lu)"),
2288 (unsigned long) imm_expr
->X_add_number
);
2289 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2290 imm_expr
->X_op
= O_absent
;
2294 case 'E': /* Control register. */
2295 insn_with_csr
= TRUE
;
2296 explicit_priv_attr
= TRUE
;
2297 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2298 INSERT_OPERAND (CSR
, *ip
, regno
);
2301 my_getExpression (imm_expr
, s
);
2302 check_absolute_expr (ip
, imm_expr
, TRUE
);
2303 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2304 as_bad (_("improper CSR address (%lu)"),
2305 (unsigned long) imm_expr
->X_add_number
);
2306 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2307 imm_expr
->X_op
= O_absent
;
2312 case 'm': /* Rounding mode. */
2313 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2315 INSERT_OPERAND (RM
, *ip
, regno
);
2321 case 'Q': /* Fence predecessor/successor. */
2322 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2326 INSERT_OPERAND (PRED
, *ip
, regno
);
2328 INSERT_OPERAND (SUCC
, *ip
, regno
);
2333 case 'd': /* Destination register. */
2334 case 's': /* Source register. */
2335 case 't': /* Target register. */
2337 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2343 /* Now that we have assembled one operand, we use the args
2344 string to figure out where it goes in the instruction. */
2348 INSERT_OPERAND (RS1
, *ip
, regno
);
2351 INSERT_OPERAND (RD
, *ip
, regno
);
2354 INSERT_OPERAND (RS2
, *ip
, regno
);
2357 INSERT_OPERAND (RS3
, *ip
, regno
);
2364 case 'D': /* Floating point RD. */
2365 case 'S': /* Floating point RS1. */
2366 case 'T': /* Floating point RS2. */
2367 case 'U': /* Floating point RS1 and RS2. */
2368 case 'R': /* Floating point RS3. */
2369 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2377 INSERT_OPERAND (RD
, *ip
, regno
);
2380 INSERT_OPERAND (RS1
, *ip
, regno
);
2383 INSERT_OPERAND (RS1
, *ip
, regno
);
2386 INSERT_OPERAND (RS2
, *ip
, regno
);
2389 INSERT_OPERAND (RS3
, *ip
, regno
);
2397 my_getExpression (imm_expr
, s
);
2398 if (imm_expr
->X_op
!= O_big
2399 && imm_expr
->X_op
!= O_constant
)
2401 normalize_constant_expr (imm_expr
);
2406 my_getExpression (imm_expr
, s
);
2407 normalize_constant_expr (imm_expr
);
2408 /* The 'A' format specifier must be a symbol. */
2409 if (imm_expr
->X_op
!= O_symbol
)
2411 *imm_reloc
= BFD_RELOC_32
;
2416 my_getExpression (imm_expr
, s
);
2417 normalize_constant_expr (imm_expr
);
2418 /* The 'B' format specifier must be a symbol or a constant. */
2419 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2421 if (imm_expr
->X_op
== O_symbol
)
2422 *imm_reloc
= BFD_RELOC_32
;
2426 case 'j': /* Sign-extended immediate. */
2427 p
= percent_op_itype
;
2428 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2430 case 'q': /* Store displacement. */
2431 p
= percent_op_stype
;
2432 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2434 case 'o': /* Load displacement. */
2435 p
= percent_op_itype
;
2436 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2439 /* This is used for TLS, where the fourth operand is
2440 %tprel_add, to get a relocation applied to an add
2441 instruction, for relaxation to use. */
2442 p
= percent_op_rtype
;
2444 case '0': /* AMO displacement, which must be zero. */
2445 p
= percent_op_null
;
2447 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2450 /* If this value won't fit into a 16 bit offset, then go
2451 find a macro that will generate the 32 bit offset
2453 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2455 normalize_constant_expr (imm_expr
);
2456 if (imm_expr
->X_op
!= O_constant
2457 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2459 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2460 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2466 case 'p': /* PC-relative offset. */
2468 *imm_reloc
= BFD_RELOC_12_PCREL
;
2469 my_getExpression (imm_expr
, s
);
2473 case 'u': /* Upper 20 bits. */
2474 p
= percent_op_utype
;
2475 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2477 if (imm_expr
->X_op
!= O_constant
)
2480 if (imm_expr
->X_add_number
< 0
2481 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2482 as_bad (_("lui expression not in range 0..1048575"));
2484 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2485 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2490 case 'a': /* 20-bit PC-relative offset. */
2492 my_getExpression (imm_expr
, s
);
2494 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2498 my_getExpression (imm_expr
, s
);
2500 if (strcmp (s
, "@plt") == 0)
2502 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2506 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2513 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2514 || imm_expr
->X_op
!= O_constant
2515 || imm_expr
->X_add_number
< 0
2516 || imm_expr
->X_add_number
>= 128
2517 || (imm_expr
->X_add_number
& 0x3) != 3)
2519 as_bad (_("bad value for opcode field, "
2520 "value must be 0...127 and "
2521 "lower 2 bits must be 0x3"));
2524 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2525 imm_expr
->X_op
= O_absent
;
2530 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2531 || imm_expr
->X_op
!= O_constant
2532 || imm_expr
->X_add_number
< 0
2533 || imm_expr
->X_add_number
>= 3)
2535 as_bad (_("bad value for opcode field, "
2536 "value must be 0...2"));
2539 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2540 imm_expr
->X_op
= O_absent
;
2545 as_bad (_("internal: unknown opcode field "
2546 "specifier `O%c'"), *args
);
2554 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2555 || imm_expr
->X_op
!= O_constant
2556 || imm_expr
->X_add_number
< 0
2557 || imm_expr
->X_add_number
>= 128)
2559 as_bad (_("bad value for funct7 field, "
2560 "value must be 0...127"));
2563 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2564 imm_expr
->X_op
= O_absent
;
2569 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2570 || imm_expr
->X_op
!= O_constant
2571 || imm_expr
->X_add_number
< 0
2572 || imm_expr
->X_add_number
>= 8)
2574 as_bad (_("bad value for funct3 field, "
2575 "value must be 0...7"));
2578 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2579 imm_expr
->X_op
= O_absent
;
2584 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2585 || imm_expr
->X_op
!= O_constant
2586 || imm_expr
->X_add_number
< 0
2587 || imm_expr
->X_add_number
>= 4)
2589 as_bad (_("bad value for funct2 field, "
2590 "value must be 0...3"));
2593 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2594 imm_expr
->X_op
= O_absent
;
2599 as_bad (_("internal: unknown funct field "
2600 "specifier `F%c'\n"), *args
);
2605 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2606 || imm_expr
->X_op
!= O_constant
2607 || imm_expr
->X_add_number
!= 0)
2610 imm_expr
->X_op
= O_absent
;
2614 as_fatal (_("internal: unknown argument type `%c'"), *args
);
2619 error
= _("illegal operands");
2620 insn_with_csr
= FALSE
;
2624 /* Restore the character we might have clobbered above. */
2626 *(argsStart
- 1) = save_c
;
2632 md_assemble (char *str
)
2634 struct riscv_cl_insn insn
;
2635 expressionS imm_expr
;
2636 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2638 /* The architecture and privileged elf attributes should be set
2639 before assembling. */
2640 if (!start_assemble
)
2642 start_assemble
= TRUE
;
2644 riscv_set_abi_by_arch ();
2645 if (!riscv_set_default_priv_spec (NULL
))
2649 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2653 as_bad ("%s `%s'", error
, str
);
2657 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2658 macro (&insn
, &imm_expr
, &imm_reloc
);
2660 append_insn (&insn
, &imm_expr
, imm_reloc
);
2664 md_atof (int type
, char *litP
, int *sizeP
)
2666 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2670 md_number_to_chars (char *buf
, valueT val
, int n
)
2672 if (target_big_endian
)
2673 number_to_chars_bigendian (buf
, val
, n
);
2675 number_to_chars_littleendian (buf
, val
, n
);
2678 const char *md_shortopts
= "O::g::G:";
2682 OPTION_MARCH
= OPTION_MD_BASE
,
2689 OPTION_NO_ARCH_ATTR
,
2691 OPTION_NO_CSR_CHECK
,
2695 OPTION_LITTLE_ENDIAN
,
2699 struct option md_longopts
[] =
2701 {"march", required_argument
, NULL
, OPTION_MARCH
},
2702 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2703 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2704 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2705 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2706 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2707 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2708 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2709 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2710 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2711 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2712 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2713 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2714 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
2715 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
2717 {NULL
, no_argument
, NULL
, 0}
2719 size_t md_longopts_size
= sizeof (md_longopts
);
2722 md_parse_option (int c
, const char *arg
)
2727 default_arch_with_ext
= arg
;
2731 riscv_opts
.pic
= FALSE
;
2735 riscv_opts
.pic
= TRUE
;
2739 if (strcmp (arg
, "ilp32") == 0)
2740 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2741 else if (strcmp (arg
, "ilp32e") == 0)
2742 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2743 else if (strcmp (arg
, "ilp32f") == 0)
2744 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2745 else if (strcmp (arg
, "ilp32d") == 0)
2746 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2747 else if (strcmp (arg
, "ilp32q") == 0)
2748 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2749 else if (strcmp (arg
, "lp64") == 0)
2750 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2751 else if (strcmp (arg
, "lp64f") == 0)
2752 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2753 else if (strcmp (arg
, "lp64d") == 0)
2754 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2755 else if (strcmp (arg
, "lp64q") == 0)
2756 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2759 explicit_mabi
= TRUE
;
2763 riscv_opts
.relax
= TRUE
;
2766 case OPTION_NO_RELAX
:
2767 riscv_opts
.relax
= FALSE
;
2770 case OPTION_ARCH_ATTR
:
2771 riscv_opts
.arch_attr
= TRUE
;
2774 case OPTION_NO_ARCH_ATTR
:
2775 riscv_opts
.arch_attr
= FALSE
;
2778 case OPTION_CSR_CHECK
:
2779 riscv_opts
.csr_check
= TRUE
;
2782 case OPTION_NO_CSR_CHECK
:
2783 riscv_opts
.csr_check
= FALSE
;
2786 case OPTION_MISA_SPEC
:
2787 return riscv_set_default_isa_spec (arg
);
2789 case OPTION_MPRIV_SPEC
:
2790 return riscv_set_default_priv_spec (arg
);
2792 case OPTION_BIG_ENDIAN
:
2793 target_big_endian
= 1;
2796 case OPTION_LITTLE_ENDIAN
:
2797 target_big_endian
= 0;
2808 riscv_after_parse_args (void)
2810 /* The --with-arch is optional for now, so we still need to set the xlen
2811 according to the default_arch, which is set by the --target. */
2814 if (strcmp (default_arch
, "riscv32") == 0)
2816 else if (strcmp (default_arch
, "riscv64") == 0)
2819 as_bad ("unknown default architecture `%s'", default_arch
);
2821 if (default_arch_with_ext
== NULL
)
2822 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2824 /* Initialize the hash table for extensions with default version. */
2825 ext_version_hash
= init_ext_version_hash (riscv_ext_version_table
);
2827 /* Set default specs. */
2828 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2829 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2830 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2831 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2833 riscv_set_arch (default_arch_with_ext
);
2835 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2836 riscv_set_rvc (FALSE
);
2837 if (riscv_subset_supports ("c"))
2838 riscv_set_rvc (TRUE
);
2840 /* Enable RVE if specified by the -march option. */
2841 riscv_set_rve (FALSE
);
2842 if (riscv_subset_supports ("e"))
2843 riscv_set_rve (TRUE
);
2845 /* If the CIE to be produced has not been overridden on the command line,
2846 then produce version 3 by default. This allows us to use the full
2847 range of registers in a .cfi_return_column directive. */
2848 if (flag_dwarf_cie_version
== -1)
2849 flag_dwarf_cie_version
= 3;
2853 md_pcrel_from (fixS
*fixP
)
2855 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2858 /* Apply a fixup to the object file. */
2861 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2863 unsigned int subtype
;
2864 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2865 bfd_boolean relaxable
= FALSE
;
2869 /* Remember value for tc_gen_reloc. */
2870 fixP
->fx_addnumber
= *valP
;
2872 switch (fixP
->fx_r_type
)
2874 case BFD_RELOC_RISCV_HI20
:
2875 case BFD_RELOC_RISCV_LO12_I
:
2876 case BFD_RELOC_RISCV_LO12_S
:
2877 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2878 | bfd_getl32 (buf
), buf
);
2879 if (fixP
->fx_addsy
== NULL
)
2880 fixP
->fx_done
= TRUE
;
2884 case BFD_RELOC_RISCV_GOT_HI20
:
2885 case BFD_RELOC_RISCV_ADD8
:
2886 case BFD_RELOC_RISCV_ADD16
:
2887 case BFD_RELOC_RISCV_ADD32
:
2888 case BFD_RELOC_RISCV_ADD64
:
2889 case BFD_RELOC_RISCV_SUB6
:
2890 case BFD_RELOC_RISCV_SUB8
:
2891 case BFD_RELOC_RISCV_SUB16
:
2892 case BFD_RELOC_RISCV_SUB32
:
2893 case BFD_RELOC_RISCV_SUB64
:
2894 case BFD_RELOC_RISCV_RELAX
:
2897 case BFD_RELOC_RISCV_TPREL_HI20
:
2898 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2899 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2900 case BFD_RELOC_RISCV_TPREL_ADD
:
2904 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2905 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2906 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2907 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2908 if (fixP
->fx_addsy
!= NULL
)
2909 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2911 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2912 _("TLS relocation against a constant"));
2916 /* Use pc-relative relocation for FDE initial location.
2917 The symbol address in .eh_frame may be adjusted in
2918 _bfd_elf_discard_section_eh_frame, and the content of
2919 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2920 Therefore, we cannot insert a relocation whose addend symbol is
2921 in .eh_frame. Othrewise, the value may be adjusted twice. */
2922 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2923 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2924 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2925 && S_GET_VALUE (fixP
->fx_subsy
)
2926 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2928 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2929 fixP
->fx_subsy
= NULL
;
2936 case BFD_RELOC_RISCV_CFA
:
2937 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2939 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2940 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2941 fixP
->fx_next
->fx_subsy
= NULL
;
2942 fixP
->fx_next
->fx_offset
= 0;
2943 fixP
->fx_subsy
= NULL
;
2945 switch (fixP
->fx_r_type
)
2948 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2949 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2953 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2954 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2958 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2959 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2963 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2964 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2967 case BFD_RELOC_RISCV_CFA
:
2968 /* Load the byte to get the subtype. */
2969 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2970 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2973 case DW_CFA_advance_loc1
:
2974 fixP
->fx_where
= loc
+ 1;
2975 fixP
->fx_next
->fx_where
= loc
+ 1;
2976 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2977 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2980 case DW_CFA_advance_loc2
:
2982 fixP
->fx_next
->fx_size
= 2;
2983 fixP
->fx_where
= loc
+ 1;
2984 fixP
->fx_next
->fx_where
= loc
+ 1;
2985 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2986 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2989 case DW_CFA_advance_loc4
:
2991 fixP
->fx_next
->fx_size
= 4;
2992 fixP
->fx_where
= loc
;
2993 fixP
->fx_next
->fx_where
= loc
;
2994 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2995 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2999 if (subtype
< 0x80 && (subtype
& 0x40))
3001 /* DW_CFA_advance_loc */
3002 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
3003 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
3004 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
3005 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
3008 as_fatal (_("internal: bad CFA value #%d"), subtype
);
3014 /* This case is unreachable. */
3021 /* If we are deleting this reloc entry, we must fill in the
3022 value now. This can happen if we have a .word which is not
3023 resolved when it appears but is later defined. */
3024 if (fixP
->fx_addsy
== NULL
)
3026 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
3027 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3032 case BFD_RELOC_RISCV_JMP
:
3035 /* Fill in a tentative value to improve objdump readability. */
3036 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3037 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3038 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
3042 case BFD_RELOC_12_PCREL
:
3045 /* Fill in a tentative value to improve objdump readability. */
3046 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3047 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3048 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
3052 case BFD_RELOC_RISCV_RVC_BRANCH
:
3055 /* Fill in a tentative value to improve objdump readability. */
3056 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3057 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3058 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
3062 case BFD_RELOC_RISCV_RVC_JUMP
:
3065 /* Fill in a tentative value to improve objdump readability. */
3066 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3067 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3068 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
3072 case BFD_RELOC_RISCV_CALL
:
3073 case BFD_RELOC_RISCV_CALL_PLT
:
3077 case BFD_RELOC_RISCV_PCREL_HI20
:
3078 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3079 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3080 relaxable
= riscv_opts
.relax
;
3083 case BFD_RELOC_RISCV_ALIGN
:
3087 /* We ignore generic BFD relocations we don't know about. */
3088 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3089 as_fatal (_("internal: bad relocation #%d"), fixP
->fx_r_type
);
3092 if (fixP
->fx_subsy
!= NULL
)
3093 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3094 _("unsupported symbol subtraction"));
3096 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3097 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3099 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3100 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3101 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3102 fixP
->fx_next
->fx_size
= 0;
3106 /* Because the value of .cfi_remember_state may changed after relaxation,
3107 we insert a fix to relocate it again in link-time. */
3110 riscv_pre_output_hook (void)
3112 const frchainS
*frch
;
3115 /* Save the current segment info. */
3117 subsegT subseg
= now_subseg
;
3119 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3120 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3124 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3126 if (frag
->fr_type
== rs_cfa
)
3129 expressionS
*symval
;
3131 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3132 exp
.X_op
= O_subtract
;
3133 exp
.X_add_symbol
= symval
->X_add_symbol
;
3134 exp
.X_add_number
= 0;
3135 exp
.X_op_symbol
= symval
->X_op_symbol
;
3137 /* We must set the segment before creating a frag after all
3138 frag chains have been chained together. */
3139 subseg_set (s
, frch
->frch_subseg
);
3141 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3142 BFD_RELOC_RISCV_CFA
);
3147 /* Restore the original segment info. */
3148 subseg_set (seg
, subseg
);
3151 /* This structure is used to hold a stack of .option values. */
3152 struct riscv_option_stack
3154 struct riscv_option_stack
*next
;
3155 struct riscv_set_options options
;
3158 static struct riscv_option_stack
*riscv_opts_stack
;
3160 /* Handle the .option pseudo-op. */
3163 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3165 char *name
= input_line_pointer
, ch
;
3167 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3168 ++input_line_pointer
;
3169 ch
= *input_line_pointer
;
3170 *input_line_pointer
= '\0';
3172 if (strcmp (name
, "rvc") == 0)
3173 riscv_set_rvc (TRUE
);
3174 else if (strcmp (name
, "norvc") == 0)
3175 riscv_set_rvc (FALSE
);
3176 else if (strcmp (name
, "pic") == 0)
3177 riscv_opts
.pic
= TRUE
;
3178 else if (strcmp (name
, "nopic") == 0)
3179 riscv_opts
.pic
= FALSE
;
3180 else if (strcmp (name
, "relax") == 0)
3181 riscv_opts
.relax
= TRUE
;
3182 else if (strcmp (name
, "norelax") == 0)
3183 riscv_opts
.relax
= FALSE
;
3184 else if (strcmp (name
, "csr-check") == 0)
3185 riscv_opts
.csr_check
= TRUE
;
3186 else if (strcmp (name
, "no-csr-check") == 0)
3187 riscv_opts
.csr_check
= FALSE
;
3188 else if (strcmp (name
, "push") == 0)
3190 struct riscv_option_stack
*s
;
3192 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3193 s
->next
= riscv_opts_stack
;
3194 s
->options
= riscv_opts
;
3195 riscv_opts_stack
= s
;
3197 else if (strcmp (name
, "pop") == 0)
3199 struct riscv_option_stack
*s
;
3201 s
= riscv_opts_stack
;
3203 as_bad (_(".option pop with no .option push"));
3206 riscv_opts
= s
->options
;
3207 riscv_opts_stack
= s
->next
;
3213 as_warn (_("unrecognized .option directive: %s\n"), name
);
3215 *input_line_pointer
= ch
;
3216 demand_empty_rest_of_line ();
3219 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3220 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3221 use in DWARF debug information. */
3224 s_dtprel (int bytes
)
3231 if (ex
.X_op
!= O_symbol
)
3233 as_bad (_("unsupported use of %s"), (bytes
== 8
3236 ignore_rest_of_line ();
3239 p
= frag_more (bytes
);
3240 md_number_to_chars (p
, 0, bytes
);
3241 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3243 ? BFD_RELOC_RISCV_TLS_DTPREL64
3244 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3246 demand_empty_rest_of_line ();
3249 /* Handle the .bss pseudo-op. */
3252 s_bss (int ignore ATTRIBUTE_UNUSED
)
3254 subseg_set (bss_section
, 0);
3255 demand_empty_rest_of_line ();
3259 riscv_make_nops (char *buf
, bfd_vma bytes
)
3263 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3264 means we are not within a valid instruction sequence. It is thus safe
3265 to use a zero byte, even though that is not a valid instruction. */
3269 /* Use at most one 2-byte NOP. */
3270 if ((bytes
- i
) % 4 == 2)
3272 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
3276 /* Fill the remainder with 4-byte NOPs. */
3277 for ( ; i
< bytes
; i
+= 4)
3278 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
3281 /* Called from md_do_align. Used to create an alignment frag in a
3282 code section by emitting a worst-case NOP sequence that the linker
3283 will later relax to the correct number of NOPs. We can't compute
3284 the correct alignment now because of other linker relaxations. */
3287 riscv_frag_align_code (int n
)
3289 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3290 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3291 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3295 /* If we are moving to a smaller alignment than the instruction size, then no
3296 alignment is required. */
3297 if (bytes
<= insn_alignment
)
3300 /* When not relaxing, riscv_handle_align handles code alignment. */
3301 if (!riscv_opts
.relax
)
3304 nops
= frag_more (worst_case_bytes
);
3306 ex
.X_op
= O_constant
;
3307 ex
.X_add_number
= worst_case_bytes
;
3309 riscv_make_nops (nops
, worst_case_bytes
);
3311 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3312 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3317 /* Implement HANDLE_ALIGN. */
3320 riscv_handle_align (fragS
*fragP
)
3322 switch (fragP
->fr_type
)
3325 /* When relaxing, riscv_frag_align_code handles code alignment. */
3326 if (!riscv_opts
.relax
)
3328 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3329 - fragP
->fr_address
- fragP
->fr_fix
);
3330 /* We have 4 byte uncompressed nops. */
3331 bfd_signed_vma size
= 4;
3332 bfd_signed_vma excess
= bytes
% size
;
3333 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3338 /* Insert zeros or compressed nops to get 4 byte alignment. */
3341 riscv_make_nops (p
, excess
);
3342 fragP
->fr_fix
+= excess
;
3346 /* Insert variable number of 4 byte uncompressed nops. */
3347 riscv_make_nops (p
, size
);
3348 fragP
->fr_var
= size
;
3358 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3360 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3363 /* Translate internal representation of relocation info to BFD target
3367 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3369 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3371 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3372 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3373 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3374 reloc
->addend
= fixp
->fx_addnumber
;
3376 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3377 if (reloc
->howto
== NULL
)
3379 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3380 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3382 /* We don't have R_RISCV_8/16, but for this special case,
3383 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3387 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3388 _("cannot represent %s relocation in object file"),
3389 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3397 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3399 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3401 offsetT old_var
= fragp
->fr_var
;
3402 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3403 return fragp
->fr_var
- old_var
;
3409 /* Expand far branches to multi-instruction sequences. */
3412 md_convert_frag_branch (fragS
*fragp
)
3420 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3422 exp
.X_op
= O_symbol
;
3423 exp
.X_add_symbol
= fragp
->fr_symbol
;
3424 exp
.X_add_number
= fragp
->fr_offset
;
3426 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3428 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3430 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3434 /* Expand the RVC branch into a RISC-V one. */
3435 insn
= bfd_getl16 (buf
);
3436 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3437 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3439 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3440 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3441 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3442 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3443 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3444 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3447 bfd_putl32 (insn
, buf
);
3451 /* Invert the branch condition. Branch over the jump. */
3452 insn
= bfd_getl16 (buf
);
3453 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3454 insn
|= ENCODE_RVC_B_IMM (6);
3455 bfd_putl16 (insn
, buf
);
3460 /* Just keep the RVC branch. */
3461 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3462 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3463 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3464 2, &exp
, FALSE
, reloc
);
3473 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3476 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3478 /* Invert the branch condition. Branch over the jump. */
3479 insn
= bfd_getl32 (buf
);
3480 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3481 insn
|= ENCODE_SBTYPE_IMM (8);
3482 bfd_putl32 (insn
, buf
);
3486 /* Jump to the target. */
3487 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3488 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3489 bfd_putl32 (MATCH_JAL
, buf
);
3494 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3495 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3496 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3497 4, &exp
, FALSE
, reloc
);
3506 fixp
->fx_file
= fragp
->fr_file
;
3507 fixp
->fx_line
= fragp
->fr_line
;
3509 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3510 + fragp
->fr_fix
+ fragp
->fr_var
);
3512 fragp
->fr_fix
+= fragp
->fr_var
;
3515 /* Relax a machine dependent frag. This returns the amount by which
3516 the current size of the frag should change. */
3519 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3522 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3523 md_convert_frag_branch (fragp
);
3527 md_show_usage (FILE *stream
)
3529 fprintf (stream
, _("\
3531 -fpic generate position-independent code\n\
3532 -fno-pic don't generate position-independent code (default)\n\
3533 -march=ISA set the RISC-V architecture\n\
3534 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3535 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3536 -mabi=ABI set the RISC-V ABI\n\
3537 -mrelax enable relax (default)\n\
3538 -mno-relax disable relax\n\
3539 -march-attr generate RISC-V arch attribute\n\
3540 -mno-arch-attr don't generate RISC-V arch attribute\n\
3544 /* Standard calling conventions leave the CFA at SP on entry. */
3547 riscv_cfi_frame_initial_instructions (void)
3549 cfi_add_CFA_def_cfa_register (X_SP
);
3553 tc_riscv_regname_to_dw2regnum (char *regname
)
3557 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3560 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3563 /* CSRs are numbered 4096 -> 8191. */
3564 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3567 as_bad (_("unknown register `%s'"), regname
);
3572 riscv_elf_final_processing (void)
3574 riscv_set_abi_by_arch ();
3575 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3578 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3579 since these directives break relaxation when used with symbol deltas. */
3582 s_riscv_leb128 (int sign
)
3585 char *save_in
= input_line_pointer
;
3588 if (exp
.X_op
!= O_constant
)
3589 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3590 demand_empty_rest_of_line ();
3592 input_line_pointer
= save_in
;
3593 return s_leb128 (sign
);
3596 /* Parse the .insn directive. */
3599 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3601 char *str
= input_line_pointer
;
3602 struct riscv_cl_insn insn
;
3603 expressionS imm_expr
;
3604 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3607 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3608 ++input_line_pointer
;
3610 save_c
= *input_line_pointer
;
3611 *input_line_pointer
= '\0';
3613 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3614 &imm_reloc
, insn_type_hash
);
3618 as_bad ("%s `%s'", error
, str
);
3622 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3623 append_insn (&insn
, &imm_expr
, imm_reloc
);
3626 *input_line_pointer
= save_c
;
3627 demand_empty_rest_of_line ();
3630 /* Update architecture and privileged elf attributes. If we don't set
3631 them, then try to output the default ones. */
3634 riscv_write_out_attrs (void)
3636 const char *arch_str
, *priv_str
, *p
;
3637 /* versions[0]: major version.
3638 versions[1]: minor version.
3639 versions[2]: revision version. */
3640 unsigned versions
[3] = {0}, number
= 0;
3643 /* Re-write architecture elf attribute. */
3644 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3645 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3646 xfree ((void *) arch_str
);
3648 /* For the file without any instruction, we don't set the default_priv_spec
3649 according to the privileged elf attributes since the md_assemble isn't
3652 && !riscv_set_default_priv_spec (NULL
))
3655 /* If we already have set privileged elf attributes, then no need to do
3656 anything. Otherwise, don't generate or update them when no CSR and
3657 privileged instructions are used. */
3658 if (!explicit_priv_attr
)
3661 priv_str
= riscv_get_priv_spec_name (default_priv_spec
);
3663 for (i
= 0; *p
; ++p
)
3665 if (*p
== '.' && i
< 3)
3667 versions
[i
++] = number
;
3670 else if (ISDIGIT (*p
))
3671 number
= (number
* 10) + (*p
- '0');
3674 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str
);
3678 versions
[i
] = number
;
3680 /* Re-write privileged elf attributes. */
3681 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3682 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3683 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3686 /* Add the default contents for the .riscv.attributes section. */
3689 riscv_set_public_attributes (void)
3691 if (riscv_opts
.arch_attr
|| explicit_attr
)
3692 riscv_write_out_attrs ();
3695 /* Called after all assembly has been done. */
3700 riscv_set_public_attributes ();
3703 /* Given a symbolic attribute NAME, return the proper integer value.
3704 Returns -1 if the attribute is not known. */
3707 riscv_convert_symbolic_attribute (const char *name
)
3716 /* When you modify this table you should
3717 also modify the list in doc/c-riscv.texi. */
3718 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3722 T(priv_spec_revision
),
3723 T(unaligned_access
),
3732 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3733 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3734 return attribute_table
[i
].tag
;
3739 /* Parse a .attribute directive. */
3742 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3744 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3746 obj_attribute
*attr
;
3748 explicit_attr
= TRUE
;
3751 case Tag_RISCV_arch
:
3753 attr
= elf_known_obj_attributes_proc (stdoutput
);
3754 if (!start_assemble
)
3755 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3757 as_fatal (_("architecture elf attributes must set before "
3758 "any instructions"));
3760 if (old_xlen
!= xlen
)
3762 /* We must re-init bfd again if xlen is changed. */
3763 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3764 bfd_find_target (riscv_target_format (), stdoutput
);
3766 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3767 as_warn (_("could not set architecture and machine"));
3771 case Tag_RISCV_priv_spec
:
3772 case Tag_RISCV_priv_spec_minor
:
3773 case Tag_RISCV_priv_spec_revision
:
3775 as_fatal (_("privileged elf attributes must set before "
3776 "any instructions"));
3784 /* RISC-V pseudo-ops table. */
3785 static const pseudo_typeS riscv_pseudo_table
[] =
3787 {"option", s_riscv_option
, 0},
3791 {"dtprelword", s_dtprel
, 4},
3792 {"dtpreldword", s_dtprel
, 8},
3794 {"uleb128", s_riscv_leb128
, 0},
3795 {"sleb128", s_riscv_leb128
, 1},
3796 {"insn", s_riscv_insn
, 0},
3797 {"attribute", s_riscv_attribute
, 0},
3803 riscv_pop_insert (void)
3805 extern void pop_insert (const pseudo_typeS
*);
3807 pop_insert (riscv_pseudo_table
);