1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/cpu-riscv.h"
33 #include "bfd/elfxx-riscv.h"
34 #include "elf/riscv.h"
35 #include "opcode/riscv.h"
39 /* Information about an instruction, including its format, operands
43 /* The opcode's entry in riscv_opcodes. */
44 const struct riscv_opcode
*insn_mo
;
46 /* The encoded instruction bits. */
49 /* The frag that contains the instruction. */
52 /* The offset into FRAG of the first instruction byte. */
55 /* The relocs associated with the instruction, if any. */
59 /* All RISC-V CSR belong to one of these classes. */
65 CSR_CLASS_I_32
, /* rv32 only */
66 CSR_CLASS_F
, /* f-ext only */
67 CSR_CLASS_DEBUG
/* debug CSR */
70 /* This structure holds all restricted conditions for a CSR. */
71 struct riscv_csr_extra
73 /* Class to which this CSR belongs. Used to decide whether or
74 not this CSR is legal in the current -march context. */
75 enum riscv_csr_class csr_class
;
77 /* CSR may have differnet numbers in the previous priv spec. */
80 /* Record the CSR is defined/valid in which versions. */
81 enum riscv_spec_class define_version
;
83 /* Record the CSR is aborted/invalid from which versions. If it isn't
84 aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
85 enum riscv_spec_class abort_version
;
87 /* The CSR may have more than one setting. */
88 struct riscv_csr_extra
*next
;
91 /* All standard/Z* extensions defined in all supported ISA spec. */
92 struct riscv_ext_version
95 enum riscv_spec_class isa_spec_class
;
100 static const struct riscv_ext_version ext_version_table
[] =
102 {"e", ISA_SPEC_CLASS_20191213
, 1, 9},
103 {"e", ISA_SPEC_CLASS_20190608
, 1, 9},
104 {"e", ISA_SPEC_CLASS_2P2
, 1, 9},
106 {"i", ISA_SPEC_CLASS_20191213
, 2, 1},
107 {"i", ISA_SPEC_CLASS_20190608
, 2, 1},
108 {"i", ISA_SPEC_CLASS_2P2
, 2, 0},
110 {"m", ISA_SPEC_CLASS_20191213
, 2, 0},
111 {"m", ISA_SPEC_CLASS_20190608
, 2, 0},
112 {"m", ISA_SPEC_CLASS_2P2
, 2, 0},
114 {"a", ISA_SPEC_CLASS_20191213
, 2, 1},
115 {"a", ISA_SPEC_CLASS_20190608
, 2, 0},
116 {"a", ISA_SPEC_CLASS_2P2
, 2, 0},
118 {"f", ISA_SPEC_CLASS_20191213
, 2, 2},
119 {"f", ISA_SPEC_CLASS_20190608
, 2, 2},
120 {"f", ISA_SPEC_CLASS_2P2
, 2, 0},
122 {"d", ISA_SPEC_CLASS_20191213
, 2, 2},
123 {"d", ISA_SPEC_CLASS_20190608
, 2, 2},
124 {"d", ISA_SPEC_CLASS_2P2
, 2, 0},
126 {"q", ISA_SPEC_CLASS_20191213
, 2, 2},
127 {"q", ISA_SPEC_CLASS_20190608
, 2, 2},
128 {"q", ISA_SPEC_CLASS_2P2
, 2, 0},
130 {"c", ISA_SPEC_CLASS_20191213
, 2, 0},
131 {"c", ISA_SPEC_CLASS_20190608
, 2, 0},
132 {"c", ISA_SPEC_CLASS_2P2
, 2, 0},
134 {"zicsr", ISA_SPEC_CLASS_20191213
, 2, 0},
135 {"zicsr", ISA_SPEC_CLASS_20190608
, 2, 0},
137 {"zifencei", ISA_SPEC_CLASS_20191213
, 2, 0},
138 {"zifencei", ISA_SPEC_CLASS_20190608
, 2, 0},
140 {"zihintpause", ISA_SPEC_CLASS_DRAFT
, 1, 0},
142 /* Terminate the list. */
147 #define DEFAULT_ARCH "riscv64"
150 #ifndef DEFAULT_RISCV_ATTR
151 #define DEFAULT_RISCV_ATTR 0
154 /* Let riscv_after_parse_args set the default value according to xlen. */
155 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
156 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
159 /* Need to sync the version with RISC-V compiler. */
160 #ifndef DEFAULT_RISCV_ISA_SPEC
161 #define DEFAULT_RISCV_ISA_SPEC "2.2"
164 #ifndef DEFAULT_RISCV_PRIV_SPEC
165 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
168 static const char default_arch
[] = DEFAULT_ARCH
;
169 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
170 static enum riscv_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
171 static enum riscv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
173 static unsigned xlen
= 0; /* The width of an x-register. */
174 static unsigned abi_xlen
= 0; /* The width of a pointer in the ABI. */
175 static bfd_boolean rve_abi
= FALSE
;
178 FLOAT_ABI_DEFAULT
= -1,
184 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
186 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
187 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
189 static unsigned elf_flags
= 0;
191 /* Set the default_isa_spec. Return 0 if the spec isn't supported.
192 Otherwise, return 1. */
195 riscv_set_default_isa_spec (const char *s
)
197 enum riscv_spec_class
class = ISA_SPEC_CLASS_NONE
;
198 RISCV_GET_ISA_SPEC_CLASS (s
, class);
199 if (class == ISA_SPEC_CLASS_NONE
)
201 as_bad ("unknown default ISA spec `%s' set by "
202 "-misa-spec or --with-isa-spec", s
);
206 default_isa_spec
= class;
210 /* Set the default_priv_spec. Find the privileged elf attributes when
211 the input string is NULL. Return 0 if the spec isn't supported.
212 Otherwise, return 1. */
215 riscv_set_default_priv_spec (const char *s
)
217 enum riscv_spec_class
class = PRIV_SPEC_CLASS_NONE
;
218 unsigned major
, minor
, revision
;
221 RISCV_GET_PRIV_SPEC_CLASS (s
, class);
222 if (class != PRIV_SPEC_CLASS_NONE
)
224 default_priv_spec
= class;
230 as_bad (_("unknown default privileged spec `%s' set by "
231 "-mpriv-spec or --with-priv-spec"), s
);
235 /* Set the default_priv_spec by the privileged elf attributes. */
236 attr
= elf_known_obj_attributes_proc (stdoutput
);
237 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
238 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
239 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
240 /* Version 0.0.0 is the default value and meningless. */
241 if (major
== 0 && minor
== 0 && revision
== 0)
244 riscv_get_priv_spec_class_from_numbers (major
, minor
, revision
, &class);
245 if (class != PRIV_SPEC_CLASS_NONE
)
247 default_priv_spec
= class;
251 /* Still can not find the privileged spec class. */
252 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
253 "privileged elf attributes"), major
, minor
, revision
);
257 /* This is the set of options which the .option pseudo-op may modify. */
258 struct riscv_set_options
260 int pic
; /* Generate position-independent code. */
261 int rvc
; /* Generate RVC code. */
262 int rve
; /* Generate RVE code. */
263 int relax
; /* Emit relocs the linker is allowed to relax. */
264 int arch_attr
; /* Emit architecture and privileged elf attributes. */
265 int csr_check
; /* Enable the CSR checking. */
268 static struct riscv_set_options riscv_opts
=
274 DEFAULT_RISCV_ATTR
, /* arch_attr */
279 riscv_set_rvc (bfd_boolean rvc_value
)
282 elf_flags
|= EF_RISCV_RVC
;
284 riscv_opts
.rvc
= rvc_value
;
288 riscv_set_rve (bfd_boolean rve_value
)
290 riscv_opts
.rve
= rve_value
;
293 static riscv_subset_list_t riscv_subsets
;
296 riscv_subset_supports (const char *feature
)
298 struct riscv_subset_t
*subset
;
300 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
303 return riscv_lookup_subset (&riscv_subsets
, feature
, &subset
);
307 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
311 case INSN_CLASS_I
: return riscv_subset_supports ("i");
312 case INSN_CLASS_C
: return riscv_subset_supports ("c");
313 case INSN_CLASS_A
: return riscv_subset_supports ("a");
314 case INSN_CLASS_M
: return riscv_subset_supports ("m");
315 case INSN_CLASS_F
: return riscv_subset_supports ("f");
316 case INSN_CLASS_D
: return riscv_subset_supports ("d");
317 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
319 case INSN_CLASS_F_AND_C
:
320 return (riscv_subset_supports ("f")
321 && riscv_subset_supports ("c"));
322 case INSN_CLASS_D_AND_C
:
323 return (riscv_subset_supports ("d")
324 && riscv_subset_supports ("c"));
326 case INSN_CLASS_ZICSR
:
327 return riscv_subset_supports ("zicsr");
328 case INSN_CLASS_ZIFENCEI
:
329 return riscv_subset_supports ("zifencei");
330 case INSN_CLASS_ZIHINTPAUSE
:
331 return riscv_subset_supports ("zihintpause");
334 as_fatal ("internal: unreachable");
339 /* Handle of the extension with version hash table. */
340 static htab_t ext_version_hash
= NULL
;
343 init_ext_version_hash (void)
345 const struct riscv_ext_version
*table
= ext_version_table
;
346 htab_t hash
= str_htab_create ();
349 while (table
[i
].name
)
351 const char *name
= table
[i
].name
;
352 if (str_hash_insert (hash
, name
, &table
[i
], 0) != NULL
)
353 as_fatal (_("internal: duplicate %s"), name
);
357 && strcmp (table
[i
].name
, name
) == 0)
365 riscv_get_default_ext_version (const char *name
,
369 struct riscv_ext_version
*ext
;
371 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
374 ext
= (struct riscv_ext_version
*) str_hash_find (ext_version_hash
, name
);
377 && strcmp (ext
->name
, name
) == 0)
379 if (ext
->isa_spec_class
== ISA_SPEC_CLASS_DRAFT
380 || ext
->isa_spec_class
== default_isa_spec
)
382 *major_version
= ext
->major_version
;
383 *minor_version
= ext
->minor_version
;
390 /* Set which ISA and extensions are available. */
393 riscv_set_arch (const char *s
)
395 riscv_parse_subset_t rps
;
396 rps
.subset_list
= &riscv_subsets
;
397 rps
.error_handler
= as_bad
;
399 rps
.get_default_version
= riscv_get_default_ext_version
;
404 riscv_release_subset_list (&riscv_subsets
);
405 riscv_parse_subset (&rps
, s
);
408 /* Indicate -mabi option is explictly set. */
409 static bfd_boolean explicit_mabi
= FALSE
;
412 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
415 float_abi
= new_float_abi
;
419 /* If the -mabi option isn't set, then set the abi according to the
420 ISA string. Otherwise, check if there is any conflict. */
423 riscv_set_abi_by_arch (void)
427 if (riscv_subset_supports ("q"))
428 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, FALSE
);
429 else if (riscv_subset_supports ("d"))
430 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, FALSE
);
432 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, FALSE
);
436 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
438 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
439 else if (abi_xlen
< xlen
)
440 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
443 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
444 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
445 elf_flags
|= float_abi
<< 1;
448 elf_flags
|= EF_RISCV_RVE
;
451 /* Handle of the OPCODE hash table. */
452 static htab_t op_hash
= NULL
;
454 /* Handle of the type of .insn hash table. */
455 static htab_t insn_type_hash
= NULL
;
457 /* This array holds the chars that always start a comment. If the
458 pre-processor is disabled, these aren't very useful. */
459 const char comment_chars
[] = "#";
461 /* This array holds the chars that only start a comment at the beginning of
462 a line. If the line seems to have the form '# 123 filename'
463 .line and .file directives will appear in the pre-processed output
465 Note that input_file.c hand checks for '#' at the beginning of the
466 first line of the input file. This is because the compiler outputs
467 #NO_APP at the beginning of its output.
469 Also note that C style comments are always supported. */
470 const char line_comment_chars
[] = "#";
472 /* This array holds machine specific line separator characters. */
473 const char line_separator_chars
[] = ";";
475 /* Chars that can be used to separate mant from exp in floating point nums. */
476 const char EXP_CHARS
[] = "eE";
478 /* Chars that mean this number is a floating point constant.
479 As in 0f12.456 or 0d1.2345e12. */
480 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
482 /* Indicate we are already assemble any instructions or not. */
483 static bfd_boolean start_assemble
= FALSE
;
485 /* Indicate ELF attributes are explicitly set. */
486 static bfd_boolean explicit_attr
= FALSE
;
488 /* Indicate CSR or priv instructions are explicitly used. */
489 static bfd_boolean explicit_priv_attr
= FALSE
;
491 /* Macros for encoding relaxation state for RVC branches and far jumps. */
492 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
495 | ((uncond) ? 1 : 0) \
498 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
499 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
500 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
501 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
503 /* Is the given value a sign-extended 32-bit value? */
504 #define IS_SEXT_32BIT_NUM(x) \
505 (((x) &~ (offsetT) 0x7fffffff) == 0 \
506 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
508 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
509 #define IS_ZEXT_32BIT_NUM(x) \
510 (((x) &~ (offsetT) 0xffffffff) == 0 \
511 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
513 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
514 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
515 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
516 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
518 /* Determine if an instruction matches an opcode. */
519 #define OPCODE_MATCHES(OPCODE, OP) \
520 (((OPCODE) & MASK_##OP) == MATCH_##OP)
522 static char *expr_end
;
524 /* The default target format to use. */
527 riscv_target_format (void)
529 if (target_big_endian
)
530 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
532 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
535 /* Return the length of instruction INSN. */
537 static inline unsigned int
538 insn_length (const struct riscv_cl_insn
*insn
)
540 return riscv_insn_length (insn
->insn_opcode
);
543 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
546 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
549 insn
->insn_opcode
= mo
->match
;
555 /* Install INSN at the location specified by its "frag" and "where" fields. */
558 install_insn (const struct riscv_cl_insn
*insn
)
560 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
561 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
564 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
565 and install the opcode in the new location. */
568 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
572 if (insn
->fixp
!= NULL
)
574 insn
->fixp
->fx_frag
= frag
;
575 insn
->fixp
->fx_where
= where
;
580 /* Add INSN to the end of the output. */
583 add_fixed_insn (struct riscv_cl_insn
*insn
)
585 char *f
= frag_more (insn_length (insn
));
586 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
590 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
591 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
593 frag_grow (max_chars
);
594 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
595 frag_var (rs_machine_dependent
, max_chars
, var
,
596 subtype
, symbol
, offset
, NULL
);
599 /* Compute the length of a branch sequence, and adjust the stored length
600 accordingly. If FRAGP is NULL, the worst-case length is returned. */
603 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
605 int jump
, rvc
, length
= 8;
610 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
611 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
612 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
614 /* Assume jumps are in range; the linker will catch any that aren't. */
615 length
= jump
? 4 : 8;
617 if (fragp
->fr_symbol
!= NULL
618 && S_IS_DEFINED (fragp
->fr_symbol
)
619 && !S_IS_WEAK (fragp
->fr_symbol
)
620 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
622 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
623 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
624 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
626 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
628 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
630 else if (!jump
&& rvc
)
635 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
640 /* Information about an opcode name, mnemonics and its value. */
647 /* List for all supported opcode name. */
648 static const struct opcode_name_t opcode_name_list
[] =
693 /* Hash table for lookup opcode name. */
694 static htab_t opcode_names_hash
= NULL
;
696 /* Initialization for hash table of opcode name. */
699 init_opcode_names_hash (void)
701 const struct opcode_name_t
*opcode
;
703 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
704 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
705 as_fatal (_("internal: duplicate %s"), opcode
->name
);
708 /* Find `s` is a valid opcode name or not, return the opcode name info
711 static const struct opcode_name_t
*
712 opcode_name_lookup (char **s
)
716 struct opcode_name_t
*o
;
718 /* Find end of name. */
720 if (is_name_beginner (*e
))
722 while (is_part_of_name (*e
))
725 /* Terminate name. */
729 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
731 /* Advance to next token if one was recognized. */
750 static htab_t reg_names_hash
= NULL
;
751 static htab_t csr_extra_hash
= NULL
;
753 #define ENCODE_REG_HASH(cls, n) \
754 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
755 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
756 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
759 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
761 void *hash
= ENCODE_REG_HASH (class, n
);
762 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
763 as_fatal (_("internal: duplicate %s"), name
);
767 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
771 for (i
= 0; i
< n
; i
++)
772 hash_reg_name (class, names
[i
], i
);
775 /* Init hash table csr_extra_hash to handle CSR. */
778 riscv_init_csr_hash (const char *name
,
780 enum riscv_csr_class
class,
781 enum riscv_spec_class define_version
,
782 enum riscv_spec_class abort_version
)
784 struct riscv_csr_extra
*entry
, *pre_entry
;
785 bfd_boolean need_enrty
= TRUE
;
788 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
789 while (need_enrty
&& entry
!= NULL
)
791 if (entry
->csr_class
== class
792 && entry
->address
== address
793 && entry
->define_version
== define_version
794 && entry
->abort_version
== abort_version
)
804 entry
= XNEW (struct riscv_csr_extra
);
805 entry
->csr_class
= class;
806 entry
->address
= address
;
807 entry
->define_version
= define_version
;
808 entry
->abort_version
= abort_version
;
811 if (pre_entry
== NULL
)
812 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
814 pre_entry
->next
= entry
;
817 /* Return the CSR address after checking the ISA dependency and
818 the privileged spec version.
820 There are one warning and two errors for CSR,
822 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
823 or the privileged spec, report warning only if -mcsr-check is set.
824 Unknown CSR: the CSR has never been defined, report error.
825 Improper CSR: the CSR number over the range (> 0xfff), report error. */
828 riscv_csr_address (const char *csr_name
,
829 struct riscv_csr_extra
*entry
)
831 struct riscv_csr_extra
*saved_entry
= entry
;
832 enum riscv_csr_class csr_class
= entry
->csr_class
;
833 bfd_boolean need_check_version
= TRUE
;
834 bfd_boolean result
= TRUE
;
839 result
= riscv_subset_supports ("i");
842 result
= (xlen
== 32 && riscv_subset_supports ("i"));
845 result
= riscv_subset_supports ("f");
846 need_check_version
= FALSE
;
848 case CSR_CLASS_DEBUG
:
849 need_check_version
= FALSE
;
852 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
855 if (riscv_opts
.csr_check
&& !result
)
856 as_warn (_("invalid CSR `%s' for the current ISA"), csr_name
);
858 while (entry
!= NULL
)
860 if (!need_check_version
861 || (default_priv_spec
>= entry
->define_version
862 && default_priv_spec
< entry
->abort_version
))
864 /* Find the CSR according to the specific version. */
865 return entry
->address
;
870 /* Can not find the CSR address from the chosen privileged version,
871 so use the newly defined value. */
872 if (riscv_opts
.csr_check
)
874 const char *priv_name
= NULL
;
875 RISCV_GET_PRIV_SPEC_NAME (priv_name
, default_priv_spec
);
876 if (priv_name
!= NULL
)
877 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
878 csr_name
, priv_name
);
881 return saved_entry
->address
;
884 /* Return -1 if the CSR has never been defined. Otherwise, return
888 reg_csr_lookup_internal (const char *s
)
890 struct riscv_csr_extra
*r
=
891 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
896 return riscv_csr_address (s
, r
);
900 reg_lookup_internal (const char *s
, enum reg_class
class)
904 if (class == RCLASS_CSR
)
905 return reg_csr_lookup_internal (s
);
907 r
= str_hash_find (reg_names_hash
, s
);
908 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
911 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
914 return DECODE_REG_NUM (r
);
918 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
924 /* Find end of name. */
926 if (is_name_beginner (*e
))
928 while (is_part_of_name (*e
))
931 /* Terminate name. */
935 /* Look for the register. Advance to next token if one was recognized. */
936 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
946 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
948 const char *p
= strchr (*s
, ',');
949 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
954 for (i
= 0; i
< size
; i
++)
955 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
965 /* For consistency checking, verify that all bits are specified either
966 by the match/mask part of the instruction definition, or by the
967 operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
970 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
972 const char *p
= opc
->args
;
974 insn_t used_bits
= opc
->mask
;
976 insn_t required_bits
;
979 insn_width
= 8 * riscv_insn_length (opc
->match
);
981 insn_width
= 8 * length
;
983 required_bits
= ~0ULL >> (64 - insn_width
);
985 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
987 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
988 opc
->name
, opc
->args
);
992 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
999 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
1000 case 'c': break; /* RS1, constrained to equal sp. */
1001 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
1002 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
1003 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
1004 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
1005 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
1006 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
1007 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
1008 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
1009 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
1010 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
1011 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
1012 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
1013 case 'w': break; /* RS1S, constrained to equal RD. */
1014 case 'x': break; /* RS2S, constrained to equal RD. */
1015 case 'z': break; /* RS2S, constrained to be x0. */
1016 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
1017 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
1018 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
1019 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
1020 case 'U': break; /* RS1, constrained to equal RD. */
1021 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
1022 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
1023 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
1024 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
1025 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
1026 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
1027 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
1028 case 'F': /* RVC funct for .insn directive. */
1031 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
1032 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
1033 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
1034 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
1036 as_bad (_("internal: bad RISC-V opcode "
1037 "(unknown operand type `CF%c'): %s %s"),
1038 c
, opc
->name
, opc
->args
);
1043 as_bad (_("internal: bad RISC-V opcode "
1044 "(unknown operand type `C%c'): %s %s"),
1045 c
, opc
->name
, opc
->args
);
1052 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
1053 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
1055 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
1056 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1057 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
1059 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
1060 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1061 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
);
1063 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
1064 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
1065 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
1066 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1067 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
1068 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
1069 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
1070 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
1072 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
1073 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
1074 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
1075 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1076 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1082 case 'F': /* Funct for .insn directive. */
1085 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1086 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1087 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1089 as_bad (_("internal: bad RISC-V opcode "
1090 "(unknown operand type `F%c'): %s %s"),
1091 c
, opc
->name
, opc
->args
);
1095 case 'O': /* Opcode for .insn directive. */
1098 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1099 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1101 as_bad (_("internal: bad RISC-V opcode "
1102 "(unknown operand type `F%c'): %s %s"),
1103 c
, opc
->name
, opc
->args
);
1108 as_bad (_("internal: bad RISC-V opcode "
1109 "(unknown operand type `%c'): %s %s"),
1110 c
, opc
->name
, opc
->args
);
1114 if (used_bits
!= required_bits
)
1116 as_bad (_("internal: bad RISC-V opcode "
1117 "(bits 0x%lx undefined): %s %s"),
1118 ~(unsigned long)(used_bits
& required_bits
),
1119 opc
->name
, opc
->args
);
1125 struct percent_op_match
1128 bfd_reloc_code_real_type reloc
;
1131 /* Common hash table initialization function for instruction and .insn
1135 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1136 bfd_boolean insn_directive_p
)
1140 htab_t hash
= str_htab_create ();
1141 while (opcodes
[i
].name
)
1143 const char *name
= opcodes
[i
].name
;
1144 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1145 as_fatal (_("internal: duplicate %s"), name
);
1149 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1151 if (insn_directive_p
)
1152 length
= ((name
[0] == 'c') ? 2 : 4);
1154 length
= 0; /* Let assembler determine the length. */
1155 if (!validate_riscv_insn (&opcodes
[i
], length
))
1156 as_fatal (_("internal: broken assembler. "
1157 "No assembly attempted"));
1160 gas_assert (!insn_directive_p
);
1163 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1169 /* This function is called once, at assembler startup time. It should set up
1170 all the tables, etc. that the MD part of the assembler will need. */
1175 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1177 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1178 as_warn (_("could not set architecture and machine"));
1180 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1181 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1183 reg_names_hash
= str_htab_create ();
1184 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1185 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1186 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1187 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1188 /* Add "fp" as an alias for "s0". */
1189 hash_reg_name (RCLASS_GPR
, "fp", 8);
1191 /* Create and insert CSR hash tables. */
1192 csr_extra_hash
= str_htab_create ();
1193 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1194 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1195 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1196 DECLARE_CSR(name, num, class, define_version, abort_version);
1197 #include "opcode/riscv-opc.h"
1200 opcode_names_hash
= str_htab_create ();
1201 init_opcode_names_hash ();
1203 /* Set the default alignment for the text section. */
1204 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1208 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1215 case BFD_RELOC_RISCV_HI20
:
1216 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1218 case BFD_RELOC_RISCV_LO12_S
:
1219 return ENCODE_STYPE_IMM (value
);
1221 case BFD_RELOC_RISCV_LO12_I
:
1222 return ENCODE_ITYPE_IMM (value
);
1229 /* Output an instruction. IP is the instruction information.
1230 ADDRESS_EXPR is an operand of the instruction to be used with
1234 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1235 bfd_reloc_code_real_type reloc_type
)
1237 dwarf2_emit_insn (0);
1239 if (reloc_type
!= BFD_RELOC_UNUSED
)
1241 reloc_howto_type
*howto
;
1243 gas_assert (address_expr
);
1244 if (reloc_type
== BFD_RELOC_12_PCREL
1245 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1247 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1248 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1249 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1251 if (now_seg
== absolute_section
)
1253 as_bad (_("relaxable branches not supported in absolute section"));
1257 add_relaxed_insn (ip
, worst_case
, best_case
,
1258 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1259 address_expr
->X_add_symbol
,
1260 address_expr
->X_add_number
);
1265 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1267 as_bad (_("internal: usupported RISC-V relocation number %d"),
1270 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1271 bfd_get_reloc_size (howto
),
1272 address_expr
, FALSE
, reloc_type
);
1274 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1278 add_fixed_insn (ip
);
1281 /* We need to start a new frag after any instruction that can be
1282 optimized away or compressed by the linker during relaxation, to prevent
1283 the assembler from computing static offsets across such an instruction.
1284 This is necessary to get correct EH info. */
1285 if (reloc_type
== BFD_RELOC_RISCV_HI20
1286 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1287 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1288 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1290 frag_wane (frag_now
);
1295 /* Build an instruction created by a macro expansion. This is passed
1296 a pointer to the count of instructions created so far, an expression,
1297 the name of the instruction to build, an operand format string, and
1298 corresponding arguments. */
1301 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1303 const struct riscv_opcode
*mo
;
1304 struct riscv_cl_insn insn
;
1305 bfd_reloc_code_real_type r
;
1308 va_start (args
, fmt
);
1310 r
= BFD_RELOC_UNUSED
;
1311 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1314 /* Find a non-RVC variant of the instruction. append_insn will compress
1316 while (riscv_insn_length (mo
->match
) < 4)
1318 gas_assert (strcmp (name
, mo
->name
) == 0);
1320 create_insn (&insn
, mo
);
1326 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1330 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1334 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1340 gas_assert (ep
!= NULL
);
1341 r
= va_arg (args
, int);
1349 as_fatal (_("internal: invalid macro"));
1354 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1356 append_insn (&insn
, ep
, r
);
1359 /* Build an instruction created by a macro expansion. Like md_assemble but
1360 accept a printf-style format string and arguments. */
1363 md_assemblef (const char *format
, ...)
1369 va_start (ap
, format
);
1371 r
= vasprintf (&buf
, format
, ap
);
1374 as_fatal (_("internal: vasprintf failed"));
1382 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1386 normalize_constant_expr (expressionS
*ex
)
1390 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1391 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1392 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1396 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1397 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1400 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1401 bfd_boolean maybe_csr
)
1403 if (ex
->X_op
== O_big
)
1404 as_bad (_("unsupported large constant"));
1405 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1406 as_bad (_("unknown CSR `%s'"),
1407 S_GET_NAME (ex
->X_add_symbol
));
1408 else if (ex
->X_op
!= O_constant
)
1409 as_bad (_("instruction %s requires absolute expression"),
1411 normalize_constant_expr (ex
);
1415 make_internal_label (void)
1417 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1421 /* Load an entry from the GOT. */
1424 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1425 const char *lo_insn
, const char *lo_pattern
,
1426 bfd_reloc_code_real_type hi_reloc
,
1427 bfd_reloc_code_real_type lo_reloc
)
1430 ep2
.X_op
= O_symbol
;
1431 ep2
.X_add_symbol
= make_internal_label ();
1432 ep2
.X_add_number
= 0;
1434 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1435 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1439 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1440 bfd_reloc_code_real_type hi_reloc
,
1441 bfd_reloc_code_real_type lo_reloc
)
1443 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1447 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1448 bfd_reloc_code_real_type hi_reloc
,
1449 bfd_reloc_code_real_type lo_reloc
)
1451 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1454 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1457 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1458 bfd_reloc_code_real_type reloc
)
1460 /* Ensure the jalr is emitted to the same frag as the auipc. */
1462 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1463 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1464 /* See comment at end of append_insn. */
1465 frag_wane (frag_now
);
1469 /* Load an integer constant into a register. */
1472 load_const (int reg
, expressionS
*ep
)
1474 int shift
= RISCV_IMM_BITS
;
1475 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1476 expressionS upper
= *ep
, lower
= *ep
;
1477 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1478 upper
.X_add_number
-= lower
.X_add_number
;
1480 if (ep
->X_op
!= O_constant
)
1482 as_bad (_("unsupported large constant"));
1486 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1488 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1489 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1492 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1493 load_const (reg
, &upper
);
1495 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1496 if (lower
.X_add_number
!= 0)
1497 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1498 lower
.X_add_number
);
1502 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1505 if (upper
.X_add_number
!= 0)
1507 /* Discard low part and zero-extend upper immediate. */
1508 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1510 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1514 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1515 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1516 lower
.X_add_number
);
1520 /* Zero extend and sign extend byte/half-word/word. */
1523 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bfd_boolean sign
)
1527 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1528 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1532 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1533 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1537 /* Expand RISC-V assembly macros into one or more instructions. */
1540 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1541 bfd_reloc_code_real_type
*imm_reloc
)
1543 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1544 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1545 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1546 int mask
= ip
->insn_mo
->mask
;
1551 load_const (rd
, imm_expr
);
1556 /* Load the address of a symbol into a register. */
1557 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1558 as_bad (_("offset too large"));
1560 if (imm_expr
->X_op
== O_constant
)
1561 load_const (rd
, imm_expr
);
1562 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol. */
1563 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1564 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1565 else /* Local PIC symbol, or any non-PIC symbol. */
1566 pcrel_load (rd
, rd
, imm_expr
, "addi",
1567 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1571 pcrel_load (rd
, rd
, imm_expr
, "addi",
1572 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1576 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1577 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1581 pcrel_load (rd
, rd
, imm_expr
, "lb",
1582 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1586 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1587 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1591 pcrel_load (rd
, rd
, imm_expr
, "lh",
1592 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1596 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1597 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1601 pcrel_load (rd
, rd
, imm_expr
, "lw",
1602 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1606 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1607 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1611 pcrel_load (rd
, rd
, imm_expr
, "ld",
1612 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1616 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1617 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1621 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1622 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1626 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1627 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1631 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1632 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1636 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1637 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1641 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1642 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1646 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1647 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1651 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1652 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1656 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1660 riscv_ext (rd
, rs1
, xlen
- 16, FALSE
);
1664 riscv_ext (rd
, rs1
, xlen
- 32, FALSE
);
1668 riscv_ext (rd
, rs1
, xlen
- 8, TRUE
);
1672 riscv_ext (rd
, rs1
, xlen
- 16, TRUE
);
1676 as_bad (_("internal: macro %s not implemented"), ip
->insn_mo
->name
);
1681 static const struct percent_op_match percent_op_utype
[] =
1683 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1684 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1685 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1686 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1687 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1688 {"%hi", BFD_RELOC_RISCV_HI20
},
1692 static const struct percent_op_match percent_op_itype
[] =
1694 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1695 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1696 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1700 static const struct percent_op_match percent_op_stype
[] =
1702 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1703 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1704 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1708 static const struct percent_op_match percent_op_rtype
[] =
1710 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1714 static const struct percent_op_match percent_op_null
[] =
1719 /* Return true if *STR points to a relocation operator. When returning true,
1720 move *STR over the operator and store its relocation code in *RELOC.
1721 Leave both *STR and *RELOC alone when returning false. */
1724 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1725 const struct percent_op_match
*percent_op
)
1727 for ( ; percent_op
->str
; percent_op
++)
1728 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1730 int len
= strlen (percent_op
->str
);
1732 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1735 *str
+= strlen (percent_op
->str
);
1736 *reloc
= percent_op
->reloc
;
1738 /* Check whether the output BFD supports this relocation.
1739 If not, issue an error and fall back on something safe. */
1740 if (*reloc
!= BFD_RELOC_UNUSED
1741 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1743 as_bad ("internal: relocation %s isn't supported by the "
1744 "current ABI", percent_op
->str
);
1745 *reloc
= BFD_RELOC_UNUSED
;
1753 my_getExpression (expressionS
*ep
, char *str
)
1757 save_in
= input_line_pointer
;
1758 input_line_pointer
= str
;
1760 expr_end
= input_line_pointer
;
1761 input_line_pointer
= save_in
;
1764 /* Parse string STR as a 16-bit relocatable operand. Store the
1765 expression in *EP and the relocation, if any, in RELOC.
1766 Return the number of relocation operators used (0 or 1).
1768 On exit, EXPR_END points to the first character after the expression. */
1771 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1772 char *str
, const struct percent_op_match
*percent_op
)
1775 unsigned crux_depth
, str_depth
, regno
;
1778 /* First, check for integer registers. No callers can accept a reg, but
1779 we need to avoid accidentally creating a useless undefined symbol below,
1780 if this is an instruction pattern that can't match. A glibc build fails
1781 if this is removed. */
1782 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1784 ep
->X_op
= O_register
;
1785 ep
->X_add_number
= regno
;
1790 /* Search for the start of the main expression.
1792 End the loop with CRUX pointing to the start of the main expression and
1793 with CRUX_DEPTH containing the number of open brackets at that point. */
1800 crux_depth
= str_depth
;
1802 /* Skip over whitespace and brackets, keeping count of the number
1804 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1810 && parse_relocation (&str
, reloc
, percent_op
));
1812 my_getExpression (ep
, crux
);
1815 /* Match every open bracket. */
1816 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1821 as_bad ("unclosed '('");
1828 /* Parse opcode name, could be an mnemonics or number. */
1831 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1832 char *str
, const struct percent_op_match
*percent_op
)
1834 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1838 ep
->X_op
= O_constant
;
1839 ep
->X_add_number
= o
->val
;
1843 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1846 /* Detect and handle implicitly zero load-store offsets. For example,
1847 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1848 an implicit offset was detected. */
1851 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1853 /* Check whether there is only a single bracketed expression left.
1854 If so, it must be the base register and the constant must be zero. */
1855 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1857 ep
->X_op
= O_constant
;
1858 ep
->X_add_number
= 0;
1865 /* All RISC-V CSR instructions belong to one of these classes. */
1874 /* Return which CSR instruction is checking. */
1876 static enum csr_insn_type
1877 riscv_csr_insn_type (insn_t insn
)
1879 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1880 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1882 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1883 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1885 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1886 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1889 return INSN_NOT_CSR
;
1892 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1893 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1894 CSR address is 0x3. */
1897 riscv_csr_read_only_check (insn_t insn
)
1899 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1900 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1901 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1902 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1905 && (((csr_insn
== INSN_CSRRS
1906 || csr_insn
== INSN_CSRRC
)
1908 || csr_insn
== INSN_CSRRW
))
1914 /* Return True if it is a privileged instruction. Otherwise, return FALSE.
1916 uret is actually a N-ext instruction. So it is better to regard it as
1917 an user instruction rather than the priv instruction.
1919 hret is used to return from traps in H-mode. H-mode is removed since
1920 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1921 Therefore, hret should be controlled by the hypervisor spec rather than
1922 priv spec in the future.
1924 dret is defined in the debug spec, so it should be checked in the future,
1928 riscv_is_priv_insn (insn_t insn
)
1930 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
1931 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
1932 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
1933 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
1934 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1935 check it here to keep the compatible. */
1936 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
1939 /* This routine assembles an instruction into its binary format. As a
1940 side effect, it sets the global variable imm_reloc to the type of
1941 relocation to do if one of the operands is an address expression. */
1944 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1945 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
1950 struct riscv_opcode
*insn
;
1955 const struct percent_op_match
*p
;
1956 const char *error
= "unrecognized opcode";
1957 /* Indicate we are assembling instruction with CSR. */
1958 bfd_boolean insn_with_csr
= FALSE
;
1960 /* Parse the name of the instruction. Terminate the string if whitespace
1961 is found so that str_hash_find only sees the name part of the string. */
1962 for (s
= str
; *s
!= '\0'; ++s
)
1970 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
1973 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1975 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1978 if (!riscv_multi_subset_supports (insn
->insn_class
))
1981 create_insn (ip
, insn
);
1984 imm_expr
->X_op
= O_absent
;
1985 *imm_reloc
= BFD_RELOC_UNUSED
;
1986 p
= percent_op_itype
;
1988 for (args
= insn
->args
;; ++args
)
1990 s
+= strspn (s
, " \t");
1993 case '\0': /* End of args. */
1994 if (insn
->pinfo
!= INSN_MACRO
)
1996 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1999 /* For .insn, insn->match and insn->mask are 0. */
2000 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
2006 if (riscv_is_priv_insn (ip
->insn_opcode
))
2007 explicit_priv_attr
= TRUE
;
2009 /* Check if we write a read-only CSR by the CSR
2012 && riscv_opts
.csr_check
2013 && !riscv_csr_read_only_check (ip
->insn_opcode
))
2015 /* Restore the character in advance, since we want to
2016 report the detailed warning message here. */
2018 *(argsStart
- 1) = save_c
;
2019 as_warn (_("read-only CSR is written `%s'"), str
);
2020 insn_with_csr
= FALSE
;
2025 /* Successful assembly. */
2027 insn_with_csr
= FALSE
;
2033 case 's': /* RS1 x8-x15. */
2034 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2035 || !(regno
>= 8 && regno
<= 15))
2037 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2039 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2040 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2041 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
2044 case 't': /* RS2 x8-x15. */
2045 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2046 || !(regno
>= 8 && regno
<= 15))
2048 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2050 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2051 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2052 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
2055 case 'U': /* RS1, constrained to equal RD. */
2056 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2057 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
2061 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
2063 INSERT_OPERAND (CRS2
, *ip
, regno
);
2065 case 'c': /* RS1, constrained to equal sp. */
2066 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2070 case 'z': /* RS2, constrained to equal x0. */
2071 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2076 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2077 || imm_expr
->X_op
!= O_constant
2078 || imm_expr
->X_add_number
<= 0
2079 || imm_expr
->X_add_number
>= 64)
2081 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2084 imm_expr
->X_op
= O_absent
;
2087 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2088 || imm_expr
->X_op
!= O_constant
2089 || imm_expr
->X_add_number
<= 0
2090 || imm_expr
->X_add_number
>= 32
2091 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2093 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2096 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2097 || imm_expr
->X_op
!= O_constant
2098 || imm_expr
->X_add_number
< 0
2099 || imm_expr
->X_add_number
>= 256
2100 || !VALID_RVC_UIMM8 ((valueT
) imm_expr
->X_add_number
))
2102 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
2105 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2106 || imm_expr
->X_op
!= O_constant
2107 || imm_expr
->X_add_number
== 0
2108 || !VALID_RVC_SIMM3 ((valueT
) imm_expr
->X_add_number
))
2110 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
2113 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2114 || imm_expr
->X_op
!= O_constant
2115 || imm_expr
->X_add_number
== 0
2116 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2118 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2121 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2123 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2124 || imm_expr
->X_op
!= O_constant
2125 || !VALID_RVC_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2127 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
2130 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2132 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2133 || imm_expr
->X_op
!= O_constant
2134 || !VALID_RVC_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2136 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
2139 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2141 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2142 || imm_expr
->X_op
!= O_constant
2143 || !VALID_RVC_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2146 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
2149 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2151 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2152 || imm_expr
->X_op
!= O_constant
2153 || !VALID_RVC_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2156 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
2159 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2160 || imm_expr
->X_op
!= O_constant
2161 /* C.addiw, c.li, and c.andi allow zero immediate.
2162 C.addi allows zero immediate as hint. Otherwise this
2164 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2166 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2169 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2170 || imm_expr
->X_op
!= O_constant
2171 || imm_expr
->X_add_number
== 0
2172 || !VALID_RVC_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2175 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2178 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2179 || imm_expr
->X_op
!= O_constant
2180 || imm_expr
->X_add_number
== 0
2181 || !VALID_RVC_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2184 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
2187 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2189 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2190 || imm_expr
->X_op
!= O_constant
2191 || !VALID_RVC_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2194 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
2197 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2199 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2200 || imm_expr
->X_op
!= O_constant
2201 || !VALID_RVC_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2204 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
2207 p
= percent_op_utype
;
2208 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2211 if (imm_expr
->X_op
!= O_constant
2212 || imm_expr
->X_add_number
<= 0
2213 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2214 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2215 && (imm_expr
->X_add_number
<
2216 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2218 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2221 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2222 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2223 || ((int32_t)imm_expr
->X_add_number
2224 != imm_expr
->X_add_number
))
2226 imm_expr
->X_add_number
=
2227 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2233 case 'S': /* Floating-point RS1 x8-x15. */
2234 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2235 || !(regno
>= 8 && regno
<= 15))
2237 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2239 case 'D': /* Floating-point RS2 x8-x15. */
2240 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2241 || !(regno
>= 8 && regno
<= 15))
2243 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2245 case 'T': /* Floating-point RS2. */
2246 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2248 INSERT_OPERAND (CRS2
, *ip
, regno
);
2254 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2255 || imm_expr
->X_op
!= O_constant
2256 || imm_expr
->X_add_number
< 0
2257 || imm_expr
->X_add_number
>= 64)
2259 as_bad (_("bad value for compressed funct6 "
2260 "field, value must be 0...64"));
2263 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2264 imm_expr
->X_op
= O_absent
;
2269 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2270 || imm_expr
->X_op
!= O_constant
2271 || imm_expr
->X_add_number
< 0
2272 || imm_expr
->X_add_number
>= 16)
2274 as_bad (_("bad value for compressed funct4 "
2275 "field, value must be 0...15"));
2278 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2279 imm_expr
->X_op
= O_absent
;
2284 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2285 || imm_expr
->X_op
!= O_constant
2286 || imm_expr
->X_add_number
< 0
2287 || imm_expr
->X_add_number
>= 8)
2289 as_bad (_("bad value for compressed funct3 "
2290 "field, value must be 0...7"));
2293 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2294 imm_expr
->X_op
= O_absent
;
2299 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2300 || imm_expr
->X_op
!= O_constant
2301 || imm_expr
->X_add_number
< 0
2302 || imm_expr
->X_add_number
>= 4)
2304 as_bad (_("bad value for compressed funct2 "
2305 "field, value must be 0...3"));
2308 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2309 imm_expr
->X_op
= O_absent
;
2314 as_bad (_("internal: unknown compressed funct "
2315 "field specifier `CF%c'"), *args
);
2320 as_bad (_("internal: unknown compressed field "
2321 "specifier `C%c'"), *args
);
2340 case '<': /* Shift amount, 0 - 31. */
2341 my_getExpression (imm_expr
, s
);
2342 check_absolute_expr (ip
, imm_expr
, FALSE
);
2343 if ((unsigned long) imm_expr
->X_add_number
> 31)
2344 as_bad (_("improper shift amount (%lu)"),
2345 (unsigned long) imm_expr
->X_add_number
);
2346 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2347 imm_expr
->X_op
= O_absent
;
2351 case '>': /* Shift amount, 0 - (XLEN-1). */
2352 my_getExpression (imm_expr
, s
);
2353 check_absolute_expr (ip
, imm_expr
, FALSE
);
2354 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2355 as_bad (_("improper shift amount (%lu)"),
2356 (unsigned long) imm_expr
->X_add_number
);
2357 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2358 imm_expr
->X_op
= O_absent
;
2362 case 'Z': /* CSRRxI immediate. */
2363 my_getExpression (imm_expr
, s
);
2364 check_absolute_expr (ip
, imm_expr
, FALSE
);
2365 if ((unsigned long) imm_expr
->X_add_number
> 31)
2366 as_bad (_("improper CSRxI immediate (%lu)"),
2367 (unsigned long) imm_expr
->X_add_number
);
2368 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2369 imm_expr
->X_op
= O_absent
;
2373 case 'E': /* Control register. */
2374 insn_with_csr
= TRUE
;
2375 explicit_priv_attr
= TRUE
;
2376 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2377 INSERT_OPERAND (CSR
, *ip
, regno
);
2380 my_getExpression (imm_expr
, s
);
2381 check_absolute_expr (ip
, imm_expr
, TRUE
);
2382 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2383 as_bad (_("improper CSR address (%lu)"),
2384 (unsigned long) imm_expr
->X_add_number
);
2385 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2386 imm_expr
->X_op
= O_absent
;
2391 case 'm': /* Rounding mode. */
2392 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2394 INSERT_OPERAND (RM
, *ip
, regno
);
2400 case 'Q': /* Fence predecessor/successor. */
2401 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2405 INSERT_OPERAND (PRED
, *ip
, regno
);
2407 INSERT_OPERAND (SUCC
, *ip
, regno
);
2412 case 'd': /* Destination register. */
2413 case 's': /* Source register. */
2414 case 't': /* Target register. */
2416 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2422 /* Now that we have assembled one operand, we use the args
2423 string to figure out where it goes in the instruction. */
2427 INSERT_OPERAND (RS1
, *ip
, regno
);
2430 INSERT_OPERAND (RD
, *ip
, regno
);
2433 INSERT_OPERAND (RS2
, *ip
, regno
);
2436 INSERT_OPERAND (RS3
, *ip
, regno
);
2443 case 'D': /* Floating point RD. */
2444 case 'S': /* Floating point RS1. */
2445 case 'T': /* Floating point RS2. */
2446 case 'U': /* Floating point RS1 and RS2. */
2447 case 'R': /* Floating point RS3. */
2448 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2456 INSERT_OPERAND (RD
, *ip
, regno
);
2459 INSERT_OPERAND (RS1
, *ip
, regno
);
2462 INSERT_OPERAND (RS1
, *ip
, regno
);
2465 INSERT_OPERAND (RS2
, *ip
, regno
);
2468 INSERT_OPERAND (RS3
, *ip
, regno
);
2476 my_getExpression (imm_expr
, s
);
2477 if (imm_expr
->X_op
!= O_big
2478 && imm_expr
->X_op
!= O_constant
)
2480 normalize_constant_expr (imm_expr
);
2485 my_getExpression (imm_expr
, s
);
2486 normalize_constant_expr (imm_expr
);
2487 /* The 'A' format specifier must be a symbol. */
2488 if (imm_expr
->X_op
!= O_symbol
)
2490 *imm_reloc
= BFD_RELOC_32
;
2495 my_getExpression (imm_expr
, s
);
2496 normalize_constant_expr (imm_expr
);
2497 /* The 'B' format specifier must be a symbol or a constant. */
2498 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2500 if (imm_expr
->X_op
== O_symbol
)
2501 *imm_reloc
= BFD_RELOC_32
;
2505 case 'j': /* Sign-extended immediate. */
2506 p
= percent_op_itype
;
2507 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2509 case 'q': /* Store displacement. */
2510 p
= percent_op_stype
;
2511 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2513 case 'o': /* Load displacement. */
2514 p
= percent_op_itype
;
2515 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2518 /* This is used for TLS, where the fourth operand is
2519 %tprel_add, to get a relocation applied to an add
2520 instruction, for relaxation to use. */
2521 p
= percent_op_rtype
;
2523 case '0': /* AMO displacement, which must be zero. */
2524 p
= percent_op_null
;
2526 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2529 /* If this value won't fit into a 16 bit offset, then go
2530 find a macro that will generate the 32 bit offset
2532 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2534 normalize_constant_expr (imm_expr
);
2535 if (imm_expr
->X_op
!= O_constant
2536 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2538 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2539 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2545 case 'p': /* PC-relative offset. */
2547 *imm_reloc
= BFD_RELOC_12_PCREL
;
2548 my_getExpression (imm_expr
, s
);
2552 case 'u': /* Upper 20 bits. */
2553 p
= percent_op_utype
;
2554 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2556 if (imm_expr
->X_op
!= O_constant
)
2559 if (imm_expr
->X_add_number
< 0
2560 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2561 as_bad (_("lui expression not in range 0..1048575"));
2563 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2564 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2569 case 'a': /* 20-bit PC-relative offset. */
2571 my_getExpression (imm_expr
, s
);
2573 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2577 my_getExpression (imm_expr
, s
);
2579 if (strcmp (s
, "@plt") == 0)
2581 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2585 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2592 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2593 || imm_expr
->X_op
!= O_constant
2594 || imm_expr
->X_add_number
< 0
2595 || imm_expr
->X_add_number
>= 128
2596 || (imm_expr
->X_add_number
& 0x3) != 3)
2598 as_bad (_("bad value for opcode field, "
2599 "value must be 0...127 and "
2600 "lower 2 bits must be 0x3"));
2603 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2604 imm_expr
->X_op
= O_absent
;
2609 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2610 || imm_expr
->X_op
!= O_constant
2611 || imm_expr
->X_add_number
< 0
2612 || imm_expr
->X_add_number
>= 3)
2614 as_bad (_("bad value for opcode field, "
2615 "value must be 0...2"));
2618 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2619 imm_expr
->X_op
= O_absent
;
2624 as_bad (_("internal: unknown opcode field "
2625 "specifier `O%c'"), *args
);
2633 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2634 || imm_expr
->X_op
!= O_constant
2635 || imm_expr
->X_add_number
< 0
2636 || imm_expr
->X_add_number
>= 128)
2638 as_bad (_("bad value for funct7 field, "
2639 "value must be 0...127"));
2642 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2643 imm_expr
->X_op
= O_absent
;
2648 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2649 || imm_expr
->X_op
!= O_constant
2650 || imm_expr
->X_add_number
< 0
2651 || imm_expr
->X_add_number
>= 8)
2653 as_bad (_("bad value for funct3 field, "
2654 "value must be 0...7"));
2657 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2658 imm_expr
->X_op
= O_absent
;
2663 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2664 || imm_expr
->X_op
!= O_constant
2665 || imm_expr
->X_add_number
< 0
2666 || imm_expr
->X_add_number
>= 4)
2668 as_bad (_("bad value for funct2 field, "
2669 "value must be 0...3"));
2672 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2673 imm_expr
->X_op
= O_absent
;
2678 as_bad (_("internal: unknown funct field "
2679 "specifier `F%c'\n"), *args
);
2684 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2685 || imm_expr
->X_op
!= O_constant
2686 || imm_expr
->X_add_number
!= 0)
2689 imm_expr
->X_op
= O_absent
;
2693 as_fatal (_("internal: unknown argument type `%c'"), *args
);
2698 error
= _("illegal operands");
2699 insn_with_csr
= FALSE
;
2703 /* Restore the character we might have clobbered above. */
2705 *(argsStart
- 1) = save_c
;
2711 md_assemble (char *str
)
2713 struct riscv_cl_insn insn
;
2714 expressionS imm_expr
;
2715 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2717 /* The architecture and privileged elf attributes should be set
2718 before assembling. */
2719 if (!start_assemble
)
2721 start_assemble
= TRUE
;
2723 riscv_set_abi_by_arch ();
2724 if (!riscv_set_default_priv_spec (NULL
))
2728 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2732 as_bad ("%s `%s'", error
, str
);
2736 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2737 macro (&insn
, &imm_expr
, &imm_reloc
);
2739 append_insn (&insn
, &imm_expr
, imm_reloc
);
2743 md_atof (int type
, char *litP
, int *sizeP
)
2745 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2749 md_number_to_chars (char *buf
, valueT val
, int n
)
2751 if (target_big_endian
)
2752 number_to_chars_bigendian (buf
, val
, n
);
2754 number_to_chars_littleendian (buf
, val
, n
);
2757 const char *md_shortopts
= "O::g::G:";
2761 OPTION_MARCH
= OPTION_MD_BASE
,
2768 OPTION_NO_ARCH_ATTR
,
2770 OPTION_NO_CSR_CHECK
,
2774 OPTION_LITTLE_ENDIAN
,
2778 struct option md_longopts
[] =
2780 {"march", required_argument
, NULL
, OPTION_MARCH
},
2781 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2782 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2783 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2784 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2785 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2786 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2787 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2788 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2789 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2790 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2791 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2792 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2793 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
2794 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
2796 {NULL
, no_argument
, NULL
, 0}
2798 size_t md_longopts_size
= sizeof (md_longopts
);
2801 md_parse_option (int c
, const char *arg
)
2806 default_arch_with_ext
= arg
;
2810 riscv_opts
.pic
= FALSE
;
2814 riscv_opts
.pic
= TRUE
;
2818 if (strcmp (arg
, "ilp32") == 0)
2819 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2820 else if (strcmp (arg
, "ilp32e") == 0)
2821 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2822 else if (strcmp (arg
, "ilp32f") == 0)
2823 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2824 else if (strcmp (arg
, "ilp32d") == 0)
2825 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2826 else if (strcmp (arg
, "ilp32q") == 0)
2827 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2828 else if (strcmp (arg
, "lp64") == 0)
2829 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2830 else if (strcmp (arg
, "lp64f") == 0)
2831 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2832 else if (strcmp (arg
, "lp64d") == 0)
2833 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2834 else if (strcmp (arg
, "lp64q") == 0)
2835 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2838 explicit_mabi
= TRUE
;
2842 riscv_opts
.relax
= TRUE
;
2845 case OPTION_NO_RELAX
:
2846 riscv_opts
.relax
= FALSE
;
2849 case OPTION_ARCH_ATTR
:
2850 riscv_opts
.arch_attr
= TRUE
;
2853 case OPTION_NO_ARCH_ATTR
:
2854 riscv_opts
.arch_attr
= FALSE
;
2857 case OPTION_CSR_CHECK
:
2858 riscv_opts
.csr_check
= TRUE
;
2861 case OPTION_NO_CSR_CHECK
:
2862 riscv_opts
.csr_check
= FALSE
;
2865 case OPTION_MISA_SPEC
:
2866 return riscv_set_default_isa_spec (arg
);
2868 case OPTION_MPRIV_SPEC
:
2869 return riscv_set_default_priv_spec (arg
);
2871 case OPTION_BIG_ENDIAN
:
2872 target_big_endian
= 1;
2875 case OPTION_LITTLE_ENDIAN
:
2876 target_big_endian
= 0;
2887 riscv_after_parse_args (void)
2889 /* The --with-arch is optional for now, so we still need to set the xlen
2890 according to the default_arch, which is set by the --target. */
2893 if (strcmp (default_arch
, "riscv32") == 0)
2895 else if (strcmp (default_arch
, "riscv64") == 0)
2898 as_bad ("unknown default architecture `%s'", default_arch
);
2900 if (default_arch_with_ext
== NULL
)
2901 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2903 /* Initialize the hash table for extensions with default version. */
2904 ext_version_hash
= init_ext_version_hash ();
2906 /* Set default specs. */
2907 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2908 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2909 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2910 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2912 riscv_set_arch (default_arch_with_ext
);
2914 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2915 riscv_set_rvc (FALSE
);
2916 if (riscv_subset_supports ("c"))
2917 riscv_set_rvc (TRUE
);
2919 /* Enable RVE if specified by the -march option. */
2920 riscv_set_rve (FALSE
);
2921 if (riscv_subset_supports ("e"))
2922 riscv_set_rve (TRUE
);
2924 /* If the CIE to be produced has not been overridden on the command line,
2925 then produce version 3 by default. This allows us to use the full
2926 range of registers in a .cfi_return_column directive. */
2927 if (flag_dwarf_cie_version
== -1)
2928 flag_dwarf_cie_version
= 3;
2932 md_pcrel_from (fixS
*fixP
)
2934 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2937 /* Apply a fixup to the object file. */
2940 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2942 unsigned int subtype
;
2943 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2944 bfd_boolean relaxable
= FALSE
;
2948 /* Remember value for tc_gen_reloc. */
2949 fixP
->fx_addnumber
= *valP
;
2951 switch (fixP
->fx_r_type
)
2953 case BFD_RELOC_RISCV_HI20
:
2954 case BFD_RELOC_RISCV_LO12_I
:
2955 case BFD_RELOC_RISCV_LO12_S
:
2956 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2957 | bfd_getl32 (buf
), buf
);
2958 if (fixP
->fx_addsy
== NULL
)
2959 fixP
->fx_done
= TRUE
;
2963 case BFD_RELOC_RISCV_GOT_HI20
:
2964 case BFD_RELOC_RISCV_ADD8
:
2965 case BFD_RELOC_RISCV_ADD16
:
2966 case BFD_RELOC_RISCV_ADD32
:
2967 case BFD_RELOC_RISCV_ADD64
:
2968 case BFD_RELOC_RISCV_SUB6
:
2969 case BFD_RELOC_RISCV_SUB8
:
2970 case BFD_RELOC_RISCV_SUB16
:
2971 case BFD_RELOC_RISCV_SUB32
:
2972 case BFD_RELOC_RISCV_SUB64
:
2973 case BFD_RELOC_RISCV_RELAX
:
2976 case BFD_RELOC_RISCV_TPREL_HI20
:
2977 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2978 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2979 case BFD_RELOC_RISCV_TPREL_ADD
:
2983 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2984 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2985 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2986 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2987 if (fixP
->fx_addsy
!= NULL
)
2988 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2990 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2991 _("TLS relocation against a constant"));
2995 /* Use pc-relative relocation for FDE initial location.
2996 The symbol address in .eh_frame may be adjusted in
2997 _bfd_elf_discard_section_eh_frame, and the content of
2998 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2999 Therefore, we cannot insert a relocation whose addend symbol is
3000 in .eh_frame. Othrewise, the value may be adjusted twice. */
3001 if (fixP
->fx_addsy
&& fixP
->fx_subsy
3002 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
3003 && strcmp (sub_segment
->name
, ".eh_frame") == 0
3004 && S_GET_VALUE (fixP
->fx_subsy
)
3005 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
3007 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
3008 fixP
->fx_subsy
= NULL
;
3015 case BFD_RELOC_RISCV_CFA
:
3016 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
3018 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3019 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
3020 fixP
->fx_next
->fx_subsy
= NULL
;
3021 fixP
->fx_next
->fx_offset
= 0;
3022 fixP
->fx_subsy
= NULL
;
3024 switch (fixP
->fx_r_type
)
3027 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
3028 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
3032 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
3033 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3037 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
3038 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3042 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
3043 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3046 case BFD_RELOC_RISCV_CFA
:
3047 /* Load the byte to get the subtype. */
3048 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
3049 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
3052 case DW_CFA_advance_loc1
:
3053 fixP
->fx_where
= loc
+ 1;
3054 fixP
->fx_next
->fx_where
= loc
+ 1;
3055 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
3056 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3059 case DW_CFA_advance_loc2
:
3061 fixP
->fx_next
->fx_size
= 2;
3062 fixP
->fx_where
= loc
+ 1;
3063 fixP
->fx_next
->fx_where
= loc
+ 1;
3064 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
3065 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3068 case DW_CFA_advance_loc4
:
3070 fixP
->fx_next
->fx_size
= 4;
3071 fixP
->fx_where
= loc
;
3072 fixP
->fx_next
->fx_where
= loc
;
3073 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
3074 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3078 if (subtype
< 0x80 && (subtype
& 0x40))
3080 /* DW_CFA_advance_loc */
3081 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
3082 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
3083 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
3084 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
3087 as_fatal (_("internal: bad CFA value #%d"), subtype
);
3093 /* This case is unreachable. */
3100 /* If we are deleting this reloc entry, we must fill in the
3101 value now. This can happen if we have a .word which is not
3102 resolved when it appears but is later defined. */
3103 if (fixP
->fx_addsy
== NULL
)
3105 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
3106 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3111 case BFD_RELOC_RISCV_JMP
:
3114 /* Fill in a tentative value to improve objdump readability. */
3115 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3116 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3117 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
3121 case BFD_RELOC_12_PCREL
:
3124 /* Fill in a tentative value to improve objdump readability. */
3125 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3126 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3127 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
3131 case BFD_RELOC_RISCV_RVC_BRANCH
:
3134 /* Fill in a tentative value to improve objdump readability. */
3135 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3136 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3137 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
3141 case BFD_RELOC_RISCV_RVC_JUMP
:
3144 /* Fill in a tentative value to improve objdump readability. */
3145 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3146 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3147 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
3151 case BFD_RELOC_RISCV_CALL
:
3152 case BFD_RELOC_RISCV_CALL_PLT
:
3156 case BFD_RELOC_RISCV_PCREL_HI20
:
3157 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3158 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3159 relaxable
= riscv_opts
.relax
;
3162 case BFD_RELOC_RISCV_ALIGN
:
3166 /* We ignore generic BFD relocations we don't know about. */
3167 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3168 as_fatal (_("internal: bad relocation #%d"), fixP
->fx_r_type
);
3171 if (fixP
->fx_subsy
!= NULL
)
3172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3173 _("unsupported symbol subtraction"));
3175 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3176 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3178 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3179 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3180 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3181 fixP
->fx_next
->fx_size
= 0;
3185 /* Because the value of .cfi_remember_state may changed after relaxation,
3186 we insert a fix to relocate it again in link-time. */
3189 riscv_pre_output_hook (void)
3191 const frchainS
*frch
;
3194 /* Save the current segment info. */
3196 subsegT subseg
= now_subseg
;
3198 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3199 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3203 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3205 if (frag
->fr_type
== rs_cfa
)
3208 expressionS
*symval
;
3210 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3211 exp
.X_op
= O_subtract
;
3212 exp
.X_add_symbol
= symval
->X_add_symbol
;
3213 exp
.X_add_number
= 0;
3214 exp
.X_op_symbol
= symval
->X_op_symbol
;
3216 /* We must set the segment before creating a frag after all
3217 frag chains have been chained together. */
3218 subseg_set (s
, frch
->frch_subseg
);
3220 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3221 BFD_RELOC_RISCV_CFA
);
3226 /* Restore the original segment info. */
3227 subseg_set (seg
, subseg
);
3230 /* This structure is used to hold a stack of .option values. */
3231 struct riscv_option_stack
3233 struct riscv_option_stack
*next
;
3234 struct riscv_set_options options
;
3237 static struct riscv_option_stack
*riscv_opts_stack
;
3239 /* Handle the .option pseudo-op. */
3242 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3244 char *name
= input_line_pointer
, ch
;
3246 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3247 ++input_line_pointer
;
3248 ch
= *input_line_pointer
;
3249 *input_line_pointer
= '\0';
3251 if (strcmp (name
, "rvc") == 0)
3252 riscv_set_rvc (TRUE
);
3253 else if (strcmp (name
, "norvc") == 0)
3254 riscv_set_rvc (FALSE
);
3255 else if (strcmp (name
, "pic") == 0)
3256 riscv_opts
.pic
= TRUE
;
3257 else if (strcmp (name
, "nopic") == 0)
3258 riscv_opts
.pic
= FALSE
;
3259 else if (strcmp (name
, "relax") == 0)
3260 riscv_opts
.relax
= TRUE
;
3261 else if (strcmp (name
, "norelax") == 0)
3262 riscv_opts
.relax
= FALSE
;
3263 else if (strcmp (name
, "csr-check") == 0)
3264 riscv_opts
.csr_check
= TRUE
;
3265 else if (strcmp (name
, "no-csr-check") == 0)
3266 riscv_opts
.csr_check
= FALSE
;
3267 else if (strcmp (name
, "push") == 0)
3269 struct riscv_option_stack
*s
;
3271 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3272 s
->next
= riscv_opts_stack
;
3273 s
->options
= riscv_opts
;
3274 riscv_opts_stack
= s
;
3276 else if (strcmp (name
, "pop") == 0)
3278 struct riscv_option_stack
*s
;
3280 s
= riscv_opts_stack
;
3282 as_bad (_(".option pop with no .option push"));
3285 riscv_opts
= s
->options
;
3286 riscv_opts_stack
= s
->next
;
3292 as_warn (_("unrecognized .option directive: %s\n"), name
);
3294 *input_line_pointer
= ch
;
3295 demand_empty_rest_of_line ();
3298 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3299 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3300 use in DWARF debug information. */
3303 s_dtprel (int bytes
)
3310 if (ex
.X_op
!= O_symbol
)
3312 as_bad (_("unsupported use of %s"), (bytes
== 8
3315 ignore_rest_of_line ();
3318 p
= frag_more (bytes
);
3319 md_number_to_chars (p
, 0, bytes
);
3320 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3322 ? BFD_RELOC_RISCV_TLS_DTPREL64
3323 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3325 demand_empty_rest_of_line ();
3328 /* Handle the .bss pseudo-op. */
3331 s_bss (int ignore ATTRIBUTE_UNUSED
)
3333 subseg_set (bss_section
, 0);
3334 demand_empty_rest_of_line ();
3338 riscv_make_nops (char *buf
, bfd_vma bytes
)
3342 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3343 means we are not within a valid instruction sequence. It is thus safe
3344 to use a zero byte, even though that is not a valid instruction. */
3348 /* Use at most one 2-byte NOP. */
3349 if ((bytes
- i
) % 4 == 2)
3351 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
3355 /* Fill the remainder with 4-byte NOPs. */
3356 for ( ; i
< bytes
; i
+= 4)
3357 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
3360 /* Called from md_do_align. Used to create an alignment frag in a
3361 code section by emitting a worst-case NOP sequence that the linker
3362 will later relax to the correct number of NOPs. We can't compute
3363 the correct alignment now because of other linker relaxations. */
3366 riscv_frag_align_code (int n
)
3368 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3369 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3370 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3374 /* If we are moving to a smaller alignment than the instruction size, then no
3375 alignment is required. */
3376 if (bytes
<= insn_alignment
)
3379 /* When not relaxing, riscv_handle_align handles code alignment. */
3380 if (!riscv_opts
.relax
)
3383 nops
= frag_more (worst_case_bytes
);
3385 ex
.X_op
= O_constant
;
3386 ex
.X_add_number
= worst_case_bytes
;
3388 riscv_make_nops (nops
, worst_case_bytes
);
3390 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3391 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3396 /* Implement HANDLE_ALIGN. */
3399 riscv_handle_align (fragS
*fragP
)
3401 switch (fragP
->fr_type
)
3404 /* When relaxing, riscv_frag_align_code handles code alignment. */
3405 if (!riscv_opts
.relax
)
3407 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3408 - fragP
->fr_address
- fragP
->fr_fix
);
3409 /* We have 4 byte uncompressed nops. */
3410 bfd_signed_vma size
= 4;
3411 bfd_signed_vma excess
= bytes
% size
;
3412 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3417 /* Insert zeros or compressed nops to get 4 byte alignment. */
3420 riscv_make_nops (p
, excess
);
3421 fragP
->fr_fix
+= excess
;
3425 /* Insert variable number of 4 byte uncompressed nops. */
3426 riscv_make_nops (p
, size
);
3427 fragP
->fr_var
= size
;
3437 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3439 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3442 /* Translate internal representation of relocation info to BFD target
3446 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3448 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3450 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3451 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3452 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3453 reloc
->addend
= fixp
->fx_addnumber
;
3455 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3456 if (reloc
->howto
== NULL
)
3458 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3459 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3461 /* We don't have R_RISCV_8/16, but for this special case,
3462 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3466 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3467 _("cannot represent %s relocation in object file"),
3468 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3476 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3478 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3480 offsetT old_var
= fragp
->fr_var
;
3481 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3482 return fragp
->fr_var
- old_var
;
3488 /* Expand far branches to multi-instruction sequences. */
3491 md_convert_frag_branch (fragS
*fragp
)
3499 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3501 exp
.X_op
= O_symbol
;
3502 exp
.X_add_symbol
= fragp
->fr_symbol
;
3503 exp
.X_add_number
= fragp
->fr_offset
;
3505 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3507 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3509 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3513 /* Expand the RVC branch into a RISC-V one. */
3514 insn
= bfd_getl16 (buf
);
3515 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3516 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3518 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3519 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3520 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3521 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3522 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3523 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3526 bfd_putl32 (insn
, buf
);
3530 /* Invert the branch condition. Branch over the jump. */
3531 insn
= bfd_getl16 (buf
);
3532 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3533 insn
|= ENCODE_RVC_B_IMM (6);
3534 bfd_putl16 (insn
, buf
);
3539 /* Just keep the RVC branch. */
3540 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3541 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3542 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3543 2, &exp
, FALSE
, reloc
);
3552 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3555 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3557 /* Invert the branch condition. Branch over the jump. */
3558 insn
= bfd_getl32 (buf
);
3559 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3560 insn
|= ENCODE_SBTYPE_IMM (8);
3561 bfd_putl32 (insn
, buf
);
3565 /* Jump to the target. */
3566 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3567 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3568 bfd_putl32 (MATCH_JAL
, buf
);
3573 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3574 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3575 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3576 4, &exp
, FALSE
, reloc
);
3585 fixp
->fx_file
= fragp
->fr_file
;
3586 fixp
->fx_line
= fragp
->fr_line
;
3588 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3589 + fragp
->fr_fix
+ fragp
->fr_var
);
3591 fragp
->fr_fix
+= fragp
->fr_var
;
3594 /* Relax a machine dependent frag. This returns the amount by which
3595 the current size of the frag should change. */
3598 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3601 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3602 md_convert_frag_branch (fragp
);
3606 md_show_usage (FILE *stream
)
3608 fprintf (stream
, _("\
3610 -fpic generate position-independent code\n\
3611 -fno-pic don't generate position-independent code (default)\n\
3612 -march=ISA set the RISC-V architecture\n\
3613 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3614 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3615 -mabi=ABI set the RISC-V ABI\n\
3616 -mrelax enable relax (default)\n\
3617 -mno-relax disable relax\n\
3618 -march-attr generate RISC-V arch attribute\n\
3619 -mno-arch-attr don't generate RISC-V arch attribute\n\
3623 /* Standard calling conventions leave the CFA at SP on entry. */
3626 riscv_cfi_frame_initial_instructions (void)
3628 cfi_add_CFA_def_cfa_register (X_SP
);
3632 tc_riscv_regname_to_dw2regnum (char *regname
)
3636 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3639 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3642 /* CSRs are numbered 4096 -> 8191. */
3643 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3646 as_bad (_("unknown register `%s'"), regname
);
3651 riscv_elf_final_processing (void)
3653 riscv_set_abi_by_arch ();
3654 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3657 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3658 since these directives break relaxation when used with symbol deltas. */
3661 s_riscv_leb128 (int sign
)
3664 char *save_in
= input_line_pointer
;
3667 if (exp
.X_op
!= O_constant
)
3668 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3669 demand_empty_rest_of_line ();
3671 input_line_pointer
= save_in
;
3672 return s_leb128 (sign
);
3675 /* Parse the .insn directive. */
3678 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3680 char *str
= input_line_pointer
;
3681 struct riscv_cl_insn insn
;
3682 expressionS imm_expr
;
3683 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3686 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3687 ++input_line_pointer
;
3689 save_c
= *input_line_pointer
;
3690 *input_line_pointer
= '\0';
3692 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3693 &imm_reloc
, insn_type_hash
);
3697 as_bad ("%s `%s'", error
, str
);
3701 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3702 append_insn (&insn
, &imm_expr
, imm_reloc
);
3705 *input_line_pointer
= save_c
;
3706 demand_empty_rest_of_line ();
3709 /* Update architecture and privileged elf attributes. If we don't set
3710 them, then try to output the default ones. */
3713 riscv_write_out_attrs (void)
3715 const char *arch_str
, *priv_str
, *p
;
3716 /* versions[0]: major version.
3717 versions[1]: minor version.
3718 versions[2]: revision version. */
3719 unsigned versions
[3] = {0}, number
= 0;
3722 /* Re-write architecture elf attribute. */
3723 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3724 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3725 xfree ((void *) arch_str
);
3727 /* For the file without any instruction, we don't set the default_priv_spec
3728 according to the privileged elf attributes since the md_assemble isn't
3731 && !riscv_set_default_priv_spec (NULL
))
3734 /* If we already have set privileged elf attributes, then no need to do
3735 anything. Otherwise, don't generate or update them when no CSR and
3736 privileged instructions are used. */
3737 if (!explicit_priv_attr
)
3740 RISCV_GET_PRIV_SPEC_NAME (priv_str
, default_priv_spec
);
3742 for (i
= 0; *p
; ++p
)
3744 if (*p
== '.' && i
< 3)
3746 versions
[i
++] = number
;
3749 else if (ISDIGIT (*p
))
3750 number
= (number
* 10) + (*p
- '0');
3753 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str
);
3757 versions
[i
] = number
;
3759 /* Re-write privileged elf attributes. */
3760 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3761 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3762 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3765 /* Add the default contents for the .riscv.attributes section. */
3768 riscv_set_public_attributes (void)
3770 if (riscv_opts
.arch_attr
|| explicit_attr
)
3771 riscv_write_out_attrs ();
3774 /* Called after all assembly has been done. */
3779 riscv_set_public_attributes ();
3782 /* Given a symbolic attribute NAME, return the proper integer value.
3783 Returns -1 if the attribute is not known. */
3786 riscv_convert_symbolic_attribute (const char *name
)
3795 /* When you modify this table you should
3796 also modify the list in doc/c-riscv.texi. */
3797 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3801 T(priv_spec_revision
),
3802 T(unaligned_access
),
3811 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3812 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3813 return attribute_table
[i
].tag
;
3818 /* Parse a .attribute directive. */
3821 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3823 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3825 obj_attribute
*attr
;
3827 explicit_attr
= TRUE
;
3830 case Tag_RISCV_arch
:
3832 attr
= elf_known_obj_attributes_proc (stdoutput
);
3833 if (!start_assemble
)
3834 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3836 as_fatal (_("architecture elf attributes must set before "
3837 "any instructions"));
3839 if (old_xlen
!= xlen
)
3841 /* We must re-init bfd again if xlen is changed. */
3842 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3843 bfd_find_target (riscv_target_format (), stdoutput
);
3845 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3846 as_warn (_("could not set architecture and machine"));
3850 case Tag_RISCV_priv_spec
:
3851 case Tag_RISCV_priv_spec_minor
:
3852 case Tag_RISCV_priv_spec_revision
:
3854 as_fatal (_("privileged elf attributes must set before "
3855 "any instructions"));
3863 /* RISC-V pseudo-ops table. */
3864 static const pseudo_typeS riscv_pseudo_table
[] =
3866 {"option", s_riscv_option
, 0},
3870 {"dtprelword", s_dtprel
, 4},
3871 {"dtpreldword", s_dtprel
, 8},
3873 {"uleb128", s_riscv_leb128
, 0},
3874 {"sleb128", s_riscv_leb128
, 1},
3875 {"insn", s_riscv_insn
, 0},
3876 {"attribute", s_riscv_attribute
, 0},
3882 riscv_pop_insert (void)
3884 extern void pop_insert (const pseudo_typeS
*);
3886 pop_insert (riscv_pseudo_table
);