1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2023 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits
46 (first bits enough to extract instruction length on a long opcode). */
49 /* The long encoded instruction bits ([0] is non-zero on a long opcode). */
50 char insn_long_opcode
[RISCV_MAX_INSN_LEN
];
52 /* The frag that contains the instruction. */
55 /* The offset into FRAG of the first instruction byte. */
58 /* The relocs associated with the instruction, if any. */
62 /* All RISC-V CSR belong to one of these classes. */
68 CSR_CLASS_I_32
, /* rv32 only */
69 CSR_CLASS_F
, /* f-ext only */
70 CSR_CLASS_ZKR
, /* zkr only */
71 CSR_CLASS_V
, /* rvv only */
72 CSR_CLASS_DEBUG
, /* debug CSR */
73 CSR_CLASS_H
, /* hypervisor */
74 CSR_CLASS_H_32
, /* hypervisor, rv32 only */
75 CSR_CLASS_SMAIA
, /* Smaia */
76 CSR_CLASS_SMAIA_32
, /* Smaia, rv32 only */
77 CSR_CLASS_SMSTATEEN
, /* Smstateen only */
78 CSR_CLASS_SMSTATEEN_32
, /* Smstateen RV32 only */
79 CSR_CLASS_SSAIA
, /* Ssaia */
80 CSR_CLASS_SSAIA_AND_H
, /* Ssaia with H */
81 CSR_CLASS_SSAIA_32
, /* Ssaia, rv32 only */
82 CSR_CLASS_SSAIA_AND_H_32
, /* Ssaia with H, rv32 only */
83 CSR_CLASS_SSSTATEEN
, /* S[ms]stateen only */
84 CSR_CLASS_SSSTATEEN_AND_H
, /* S[ms]stateen only (with H) */
85 CSR_CLASS_SSSTATEEN_AND_H_32
, /* S[ms]stateen RV32 only (with H) */
86 CSR_CLASS_SSCOFPMF
, /* Sscofpmf only */
87 CSR_CLASS_SSCOFPMF_32
, /* Sscofpmf RV32 only */
88 CSR_CLASS_SSTC
, /* Sstc only */
89 CSR_CLASS_SSTC_AND_H
, /* Sstc only (with H) */
90 CSR_CLASS_SSTC_32
, /* Sstc RV32 only */
91 CSR_CLASS_SSTC_AND_H_32
, /* Sstc RV32 only (with H) */
94 /* This structure holds all restricted conditions for a CSR. */
95 struct riscv_csr_extra
97 /* Class to which this CSR belongs. Used to decide whether or
98 not this CSR is legal in the current -march context. */
99 enum riscv_csr_class csr_class
;
101 /* CSR may have differnet numbers in the previous priv spec. */
104 /* Record the CSR is defined/valid in which versions. */
105 enum riscv_spec_class define_version
;
107 /* Record the CSR is aborted/invalid from which versions. If it isn't
108 aborted in the current version, then it should be PRIV_SPEC_CLASS_DRAFT. */
109 enum riscv_spec_class abort_version
;
111 /* The CSR may have more than one setting. */
112 struct riscv_csr_extra
*next
;
115 /* This structure contains information about errors that occur within the
117 struct riscv_ip_error
119 /* General error message */
122 /* Statement that caused the error */
125 /* Missing extension that needs to be enabled */
126 const char* missing_ext
;
130 #define DEFAULT_ARCH "riscv64"
133 #ifndef DEFAULT_RISCV_ATTR
134 #define DEFAULT_RISCV_ATTR 0
137 /* Let riscv_after_parse_args set the default value according to xlen. */
138 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
139 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
142 /* Need to sync the version with RISC-V compiler. */
143 #ifndef DEFAULT_RISCV_ISA_SPEC
144 #define DEFAULT_RISCV_ISA_SPEC "20191213"
147 #ifndef DEFAULT_RISCV_PRIV_SPEC
148 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
151 static const char default_arch
[] = DEFAULT_ARCH
;
152 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
153 static enum riscv_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
154 static enum riscv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
156 static unsigned xlen
= 0; /* The width of an x-register. */
157 static unsigned abi_xlen
= 0; /* The width of a pointer in the ABI. */
158 static bool rve_abi
= false;
161 FLOAT_ABI_DEFAULT
= -1,
167 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
169 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
170 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
172 static unsigned elf_flags
= 0;
174 static bool probing_insn_operands
;
176 /* Set the default_isa_spec. Return 0 if the spec isn't supported.
177 Otherwise, return 1. */
180 riscv_set_default_isa_spec (const char *s
)
182 enum riscv_spec_class
class = ISA_SPEC_CLASS_NONE
;
183 RISCV_GET_ISA_SPEC_CLASS (s
, class);
184 if (class == ISA_SPEC_CLASS_NONE
)
186 as_bad ("unknown default ISA spec `%s' set by "
187 "-misa-spec or --with-isa-spec", s
);
191 default_isa_spec
= class;
195 /* Set the default_priv_spec. Find the privileged elf attributes when
196 the input string is NULL. Return 0 if the spec isn't supported.
197 Otherwise, return 1. */
200 riscv_set_default_priv_spec (const char *s
)
202 enum riscv_spec_class
class = PRIV_SPEC_CLASS_NONE
;
203 unsigned major
, minor
, revision
;
206 RISCV_GET_PRIV_SPEC_CLASS (s
, class);
207 if (class != PRIV_SPEC_CLASS_NONE
)
209 default_priv_spec
= class;
215 as_bad (_("unknown default privileged spec `%s' set by "
216 "-mpriv-spec or --with-priv-spec"), s
);
220 /* Set the default_priv_spec by the privileged elf attributes. */
221 attr
= elf_known_obj_attributes_proc (stdoutput
);
222 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
223 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
224 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
225 /* Version 0.0.0 is the default value and meningless. */
226 if (major
== 0 && minor
== 0 && revision
== 0)
229 riscv_get_priv_spec_class_from_numbers (major
, minor
, revision
, &class);
230 if (class != PRIV_SPEC_CLASS_NONE
)
232 default_priv_spec
= class;
236 /* Still can not find the privileged spec class. */
237 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
238 "privileged elf attributes"), major
, minor
, revision
);
242 /* This is the set of options which the .option pseudo-op may modify. */
243 struct riscv_set_options
245 int pic
; /* Generate position-independent code. */
246 int rvc
; /* Generate RVC code. */
247 int relax
; /* Emit relocs the linker is allowed to relax. */
248 int arch_attr
; /* Emit architecture and privileged elf attributes. */
249 int csr_check
; /* Enable the CSR checking. */
252 static struct riscv_set_options riscv_opts
=
257 DEFAULT_RISCV_ATTR
, /* arch_attr */
261 /* Enable or disable the rvc flags for riscv_opts. Turn on the rvc flag
262 for elf_flags once we have enabled c extension. */
265 riscv_set_rvc (bool rvc_value
)
268 elf_flags
|= EF_RISCV_RVC
;
270 riscv_opts
.rvc
= rvc_value
;
273 /* Turn on the tso flag for elf_flags once we have enabled ztso extension. */
278 elf_flags
|= EF_RISCV_TSO
;
281 /* The linked list hanging off of .subsets_list records all enabled extensions,
282 which are parsed from the architecture string. The architecture string can
283 be set by the -march option, the elf architecture attributes, and the
284 --with-arch configure option. */
285 static riscv_parse_subset_t riscv_rps_as
=
287 NULL
, /* subset_list, we will set it later once
288 riscv_opts_stack is created or updated. */
289 as_bad
, /* error_handler. */
291 &default_isa_spec
, /* isa_spec. */
292 true, /* check_unknown_prefixed_ext. */
295 /* Update the architecture string in the subset_list. */
298 riscv_reset_subsets_list_arch_str (void)
300 riscv_subset_list_t
*subsets
= riscv_rps_as
.subset_list
;
301 if (subsets
->arch_str
!= NULL
)
302 free ((void *) subsets
->arch_str
);
303 subsets
->arch_str
= riscv_arch_str (xlen
, subsets
);
306 /* This structure is used to hold a stack of .option values. */
307 struct riscv_option_stack
309 struct riscv_option_stack
*next
;
310 struct riscv_set_options options
;
311 riscv_subset_list_t
*subset_list
;
314 static struct riscv_option_stack
*riscv_opts_stack
= NULL
;
316 /* Set which ISA and extensions are available. */
319 riscv_set_arch (const char *s
)
321 if (s
!= NULL
&& strcmp (s
, "") == 0)
323 as_bad (_("the architecture string of -march and elf architecture "
324 "attributes cannot be empty"));
328 if (riscv_rps_as
.subset_list
== NULL
)
330 riscv_rps_as
.subset_list
= XNEW (riscv_subset_list_t
);
331 riscv_rps_as
.subset_list
->head
= NULL
;
332 riscv_rps_as
.subset_list
->tail
= NULL
;
333 riscv_rps_as
.subset_list
->arch_str
= NULL
;
335 riscv_release_subset_list (riscv_rps_as
.subset_list
);
336 riscv_parse_subset (&riscv_rps_as
, s
);
337 riscv_reset_subsets_list_arch_str ();
339 riscv_set_rvc (false);
340 if (riscv_subset_supports (&riscv_rps_as
, "c"))
341 riscv_set_rvc (true);
343 if (riscv_subset_supports (&riscv_rps_as
, "ztso"))
347 /* Indicate -mabi option is explictly set. */
348 static bool explicit_mabi
= false;
350 /* Set the abi information. */
353 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bool rve
)
356 float_abi
= new_float_abi
;
360 /* If the -mabi option isn't set, then set the abi according to the
361 ISA string. Otherwise, check if there is any conflict. */
364 riscv_set_abi_by_arch (void)
368 if (riscv_subset_supports (&riscv_rps_as
, "q"))
369 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, false);
370 else if (riscv_subset_supports (&riscv_rps_as
, "d"))
371 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, false);
372 else if (riscv_subset_supports (&riscv_rps_as
, "e"))
373 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, true);
375 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, false);
379 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
381 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
382 else if (abi_xlen
< xlen
)
383 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
385 if (riscv_subset_supports (&riscv_rps_as
, "e") && !rve_abi
)
386 as_bad ("only the ilp32e ABI is supported for e extension");
388 if (float_abi
== FLOAT_ABI_SINGLE
389 && !riscv_subset_supports (&riscv_rps_as
, "f"))
390 as_bad ("ilp32f/lp64f ABI can't be used when f extension "
392 else if (float_abi
== FLOAT_ABI_DOUBLE
393 && !riscv_subset_supports (&riscv_rps_as
, "d"))
394 as_bad ("ilp32d/lp64d ABI can't be used when d extension "
396 else if (float_abi
== FLOAT_ABI_QUAD
397 && !riscv_subset_supports (&riscv_rps_as
, "q"))
398 as_bad ("ilp32q/lp64q ABI can't be used when q extension "
402 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
403 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
404 elf_flags
|= float_abi
<< 1;
407 elf_flags
|= EF_RISCV_RVE
;
410 /* Handle of the OPCODE hash table. */
411 static htab_t op_hash
= NULL
;
413 /* Handle of the type of .insn hash table. */
414 static htab_t insn_type_hash
= NULL
;
416 /* This array holds the chars that always start a comment. If the
417 pre-processor is disabled, these aren't very useful. */
418 const char comment_chars
[] = "#";
420 /* This array holds the chars that only start a comment at the beginning of
421 a line. If the line seems to have the form '# 123 filename'
422 .line and .file directives will appear in the pre-processed output
424 Note that input_file.c hand checks for '#' at the beginning of the
425 first line of the input file. This is because the compiler outputs
426 #NO_APP at the beginning of its output.
428 Also note that C style comments are always supported. */
429 const char line_comment_chars
[] = "#";
431 /* This array holds machine specific line separator characters. */
432 const char line_separator_chars
[] = ";";
434 /* Chars that can be used to separate mant from exp in floating point nums. */
435 const char EXP_CHARS
[] = "eE";
437 /* Chars that mean this number is a floating point constant.
438 As in 0f12.456 or 0d1.2345e12. */
439 const char FLT_CHARS
[] = "rRsSfFdDxXpPhH";
441 /* Indicate we are already assemble any instructions or not. */
442 static bool start_assemble
= false;
444 /* Indicate ELF attributes are explicitly set. */
445 static bool explicit_attr
= false;
447 /* Indicate CSR or priv instructions are explicitly used. */
448 static bool explicit_priv_attr
= false;
450 static char *expr_parse_end
;
452 /* Macros for encoding relaxation state for RVC branches and far jumps. */
453 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
456 | ((uncond) ? 1 : 0) \
459 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
460 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
461 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
462 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
464 /* Is the given value a sign-extended 32-bit value? */
465 #define IS_SEXT_32BIT_NUM(x) \
466 (((x) &~ (offsetT) 0x7fffffff) == 0 \
467 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
469 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
470 #define IS_ZEXT_32BIT_NUM(x) \
471 (((x) &~ (offsetT) 0xffffffff) == 0 \
472 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
474 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
475 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
476 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
477 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
479 #define INSERT_IMM(n, s, INSN, VALUE) \
480 INSERT_BITS ((INSN).insn_opcode, VALUE, (1ULL<<n) - 1, s)
482 /* Determine if an instruction matches an opcode. */
483 #define OPCODE_MATCHES(OPCODE, OP) \
484 (((OPCODE) & MASK_##OP) == MATCH_##OP)
486 /* Create a new mapping symbol for the transition to STATE. */
489 make_mapping_symbol (enum riscv_seg_mstate state
,
492 const char *arch_str
,
493 bool odd_data_padding
)
503 if (arch_str
!= NULL
)
505 size_t size
= strlen (arch_str
) + 3; /* "$x" + '\0' */
506 buff
= xmalloc (size
);
507 snprintf (buff
, size
, "$x%s", arch_str
);
517 symbolS
*symbol
= symbol_new (name
, now_seg
, frag
, value
);
518 symbol_get_bfdsym (symbol
)->flags
|= (BSF_NO_FLAGS
| BSF_LOCAL
);
519 if (arch_str
!= NULL
)
521 /* Store current $x+arch into tc_segment_info. */
522 seg_info (now_seg
)->tc_segment_info_data
.arch_map_symbol
= symbol
;
523 xfree ((void *) buff
);
526 /* If .fill or other data filling directive generates zero sized data,
527 then mapping symbol for the following code will have the same value.
529 Please see gas/testsuite/gas/riscv/mapping.s: .text.zero.fill.first
530 and .text.zero.fill.last. */
531 symbolS
*first
= frag
->tc_frag_data
.first_map_symbol
;
532 symbolS
*last
= frag
->tc_frag_data
.last_map_symbol
;
533 symbolS
*removed
= NULL
;
538 know (S_GET_VALUE (first
) == S_GET_VALUE (symbol
)
540 /* Remove the old one. */
543 frag
->tc_frag_data
.first_map_symbol
= symbol
;
545 else if (last
!= NULL
)
547 /* The mapping symbols should be added in offset order. */
548 know (S_GET_VALUE (last
) <= S_GET_VALUE (symbol
));
549 /* Remove the old one. */
550 if (S_GET_VALUE (last
) == S_GET_VALUE (symbol
))
553 frag
->tc_frag_data
.last_map_symbol
= symbol
;
558 if (odd_data_padding
)
560 /* If the removed mapping symbol is $x+arch, then add it back to
562 const char *str
= strncmp (S_GET_NAME (removed
), "$xrv", 4) == 0
563 ? S_GET_NAME (removed
) + 2 : NULL
;
564 make_mapping_symbol (MAP_INSN
, frag
->fr_fix
+ 1, frag
, str
,
565 false/* odd_data_padding */);
567 symbol_remove (removed
, &symbol_rootP
, &symbol_lastP
);
570 /* Set the mapping state for frag_now. */
573 riscv_mapping_state (enum riscv_seg_mstate to_state
,
577 enum riscv_seg_mstate from_state
=
578 seg_info (now_seg
)->tc_segment_info_data
.map_state
;
579 bool reset_seg_arch_str
= false;
581 if (!SEG_NORMAL (now_seg
)
582 /* For now we only add the mapping symbols to text sections.
583 Therefore, the dis-assembler only show the actual contents
584 distribution for text. Other sections will be shown as
585 data without the details. */
586 || !subseg_text_p (now_seg
))
589 /* The mapping symbol should be emitted if not in the right
591 symbolS
*seg_arch_symbol
=
592 seg_info (now_seg
)->tc_segment_info_data
.arch_map_symbol
;
593 if (to_state
== MAP_INSN
&& seg_arch_symbol
== 0)
595 /* Always add $x+arch at the first instruction of section. */
596 reset_seg_arch_str
= true;
598 else if (seg_arch_symbol
!= 0
599 && to_state
== MAP_INSN
601 && strcmp (riscv_rps_as
.subset_list
->arch_str
,
602 S_GET_NAME (seg_arch_symbol
) + 2) != 0)
604 reset_seg_arch_str
= true;
606 else if (from_state
== to_state
)
609 valueT value
= (valueT
) (frag_now_fix () - max_chars
);
610 seg_info (now_seg
)->tc_segment_info_data
.map_state
= to_state
;
611 const char *arch_str
= reset_seg_arch_str
612 ? riscv_rps_as
.subset_list
->arch_str
: NULL
;
613 make_mapping_symbol (to_state
, value
, frag_now
, arch_str
,
614 false/* odd_data_padding */);
617 /* Add the odd bytes of paddings for riscv_handle_align. */
620 riscv_add_odd_padding_symbol (fragS
*frag
)
622 /* If there was already a mapping symbol, it should be
623 removed in the make_mapping_symbol.
625 Please see gas/testsuite/gas/riscv/mapping.s: .text.odd.align.*. */
626 make_mapping_symbol (MAP_DATA
, frag
->fr_fix
, frag
,
627 NULL
/* arch_str */, true/* odd_data_padding */);
630 /* Remove any excess mapping symbols generated for alignment frags in
631 SEC. We may have created a mapping symbol before a zero byte
632 alignment; remove it if there's a mapping symbol after the
636 riscv_check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
,
638 void *dummy ATTRIBUTE_UNUSED
)
640 segment_info_type
*seginfo
= seg_info (sec
);
643 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
646 for (fragp
= seginfo
->frchainP
->frch_root
;
648 fragp
= fragp
->fr_next
)
650 symbolS
*last
= fragp
->tc_frag_data
.last_map_symbol
;
651 fragS
*next
= fragp
->fr_next
;
653 if (last
== NULL
|| next
== NULL
)
656 /* Check the last mapping symbol if it is at the boundary of
658 if (S_GET_VALUE (last
) < next
->fr_address
)
660 know (S_GET_VALUE (last
) == next
->fr_address
);
664 symbolS
*next_first
= next
->tc_frag_data
.first_map_symbol
;
665 if (next_first
!= NULL
)
667 /* The last mapping symbol overlaps with another one
668 which at the start of the next frag.
670 Please see the gas/testsuite/gas/riscv/mapping.s:
671 .text.zero.fill.align.A and .text.zero.fill.align.B. */
672 know (S_GET_VALUE (last
) == S_GET_VALUE (next_first
));
673 symbolS
*removed
= last
;
674 if (strncmp (S_GET_NAME (last
), "$xrv", 4) == 0
675 && strcmp (S_GET_NAME (next_first
), "$x") == 0)
676 removed
= next_first
;
677 symbol_remove (removed
, &symbol_rootP
, &symbol_lastP
);
681 if (next
->fr_next
== NULL
)
683 /* The last mapping symbol is at the end of the section.
685 Please see the gas/testsuite/gas/riscv/mapping.s:
686 .text.last.section. */
687 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
688 symbol_remove (last
, &symbol_rootP
, &symbol_lastP
);
692 /* Since we may have empty frags without any mapping symbols,
693 keep looking until the non-empty frag. */
694 if (next
->fr_address
!= next
->fr_next
->fr_address
)
697 next
= next
->fr_next
;
699 while (next
!= NULL
);
703 /* The default target format to use. */
706 riscv_target_format (void)
708 if (target_big_endian
)
709 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
711 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
714 /* Return the length of instruction INSN. */
716 static inline unsigned int
717 insn_length (const struct riscv_cl_insn
*insn
)
719 return riscv_insn_length (insn
->insn_opcode
);
722 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
725 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
728 insn
->insn_opcode
= mo
->match
;
729 insn
->insn_long_opcode
[0] = 0;
735 /* Install INSN at the location specified by its "frag" and "where" fields. */
738 install_insn (const struct riscv_cl_insn
*insn
)
740 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
741 if (insn
->insn_long_opcode
[0] != 0)
742 memcpy (f
, insn
->insn_long_opcode
, insn_length (insn
));
744 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
747 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
748 and install the opcode in the new location. */
751 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
755 if (insn
->fixp
!= NULL
)
757 insn
->fixp
->fx_frag
= frag
;
758 insn
->fixp
->fx_where
= where
;
763 /* Add INSN to the end of the output. */
766 add_fixed_insn (struct riscv_cl_insn
*insn
)
768 char *f
= frag_more (insn_length (insn
));
769 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
773 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
774 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
776 frag_grow (max_chars
);
777 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
778 frag_var (rs_machine_dependent
, max_chars
, var
,
779 subtype
, symbol
, offset
, NULL
);
782 /* Compute the length of a branch sequence, and adjust the stored length
783 accordingly. If FRAGP is NULL, the worst-case length is returned. */
786 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
788 int jump
, rvc
, length
= 8;
793 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
794 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
795 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
797 /* Assume jumps are in range; the linker will catch any that aren't. */
798 length
= jump
? 4 : 8;
800 if (fragp
->fr_symbol
!= NULL
801 && S_IS_DEFINED (fragp
->fr_symbol
)
802 && !S_IS_WEAK (fragp
->fr_symbol
)
803 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
805 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
806 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
807 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
809 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
811 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
813 else if (!jump
&& rvc
)
818 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
823 /* Information about an opcode name, mnemonics and its value. */
830 /* List for all supported opcode name. */
831 static const struct opcode_name_t opcode_name_list
[] =
876 /* Hash table for lookup opcode name. */
877 static htab_t opcode_names_hash
= NULL
;
879 /* Initialization for hash table of opcode name. */
882 init_opcode_names_hash (void)
884 const struct opcode_name_t
*opcode
;
886 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
887 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
888 as_fatal (_("internal: duplicate %s"), opcode
->name
);
891 /* Find `s` is a valid opcode name or not, return the opcode name info
894 static const struct opcode_name_t
*
895 opcode_name_lookup (char **s
)
899 struct opcode_name_t
*o
;
901 /* Find end of name. */
903 if (is_name_beginner (*e
))
905 while (is_part_of_name (*e
))
908 /* Terminate name. */
912 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
914 /* Advance to next token if one was recognized. */
924 /* All RISC-V registers belong to one of these classes. */
936 static htab_t reg_names_hash
= NULL
;
937 static htab_t csr_extra_hash
= NULL
;
939 #define ENCODE_REG_HASH(cls, n) \
940 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
941 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
942 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
945 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
947 void *hash
= ENCODE_REG_HASH (class, n
);
948 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
949 as_fatal (_("internal: duplicate %s"), name
);
953 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
957 for (i
= 0; i
< n
; i
++)
958 hash_reg_name (class, names
[i
], i
);
961 /* Init hash table csr_extra_hash to handle CSR. */
964 riscv_init_csr_hash (const char *name
,
966 enum riscv_csr_class
class,
967 enum riscv_spec_class define_version
,
968 enum riscv_spec_class abort_version
)
970 struct riscv_csr_extra
*entry
, *pre_entry
;
971 bool need_enrty
= true;
974 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
975 while (need_enrty
&& entry
!= NULL
)
977 if (entry
->csr_class
== class
978 && entry
->address
== address
979 && entry
->define_version
== define_version
980 && entry
->abort_version
== abort_version
)
990 entry
= notes_alloc (sizeof (*entry
));
991 entry
->csr_class
= class;
992 entry
->address
= address
;
993 entry
->define_version
= define_version
;
994 entry
->abort_version
= abort_version
;
997 if (pre_entry
== NULL
)
998 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
1000 pre_entry
->next
= entry
;
1003 /* Return the CSR address after checking the ISA dependency and
1004 the privileged spec version.
1006 There are one warning and two errors for CSR,
1008 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
1009 or the privileged spec, report warning only if -mcsr-check is set.
1010 Unknown CSR: the CSR has never been defined, report error.
1011 Improper CSR: the CSR number over the range (> 0xfff), report error. */
1014 riscv_csr_address (const char *csr_name
,
1015 struct riscv_csr_extra
*entry
)
1017 struct riscv_csr_extra
*saved_entry
= entry
;
1018 enum riscv_csr_class csr_class
= entry
->csr_class
;
1019 bool need_check_version
= false;
1020 bool is_rv32_only
= false;
1021 bool is_h_required
= false;
1022 const char* extension
= NULL
;
1026 case CSR_CLASS_I_32
:
1027 is_rv32_only
= true;
1030 need_check_version
= true;
1033 case CSR_CLASS_H_32
:
1034 is_rv32_only
= true;
1046 extension
= "zve32x";
1048 case CSR_CLASS_SMAIA_32
:
1049 is_rv32_only
= true;
1051 case CSR_CLASS_SMAIA
:
1052 extension
= "smaia";
1054 case CSR_CLASS_SMSTATEEN_32
:
1055 is_rv32_only
= true;
1057 case CSR_CLASS_SMSTATEEN
:
1058 extension
= "smstateen";
1060 case CSR_CLASS_SSAIA
:
1061 case CSR_CLASS_SSAIA_AND_H
:
1062 case CSR_CLASS_SSAIA_32
:
1063 case CSR_CLASS_SSAIA_AND_H_32
:
1064 is_rv32_only
= (csr_class
== CSR_CLASS_SSAIA_32
1065 || csr_class
== CSR_CLASS_SSAIA_AND_H_32
);
1066 is_h_required
= (csr_class
== CSR_CLASS_SSAIA_AND_H
1067 || csr_class
== CSR_CLASS_SSAIA_AND_H_32
);
1068 extension
= "ssaia";
1070 case CSR_CLASS_SSSTATEEN_AND_H_32
:
1071 is_rv32_only
= true;
1073 case CSR_CLASS_SSSTATEEN_AND_H
:
1074 is_h_required
= true;
1076 case CSR_CLASS_SSSTATEEN
:
1077 extension
= "ssstateen";
1079 case CSR_CLASS_SSCOFPMF_32
:
1080 is_rv32_only
= true;
1082 case CSR_CLASS_SSCOFPMF
:
1083 extension
= "sscofpmf";
1085 case CSR_CLASS_SSTC
:
1086 case CSR_CLASS_SSTC_AND_H
:
1087 case CSR_CLASS_SSTC_32
:
1088 case CSR_CLASS_SSTC_AND_H_32
:
1089 is_rv32_only
= (csr_class
== CSR_CLASS_SSTC_32
1090 || csr_class
== CSR_CLASS_SSTC_AND_H_32
);
1091 is_h_required
= (csr_class
== CSR_CLASS_SSTC_AND_H
1092 || csr_class
== CSR_CLASS_SSTC_AND_H_32
);
1095 case CSR_CLASS_DEBUG
:
1098 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
1101 if (riscv_opts
.csr_check
)
1103 if (is_rv32_only
&& xlen
!= 32)
1104 as_warn (_("invalid CSR `%s', needs rv32i extension"), csr_name
);
1105 if (is_h_required
&& !riscv_subset_supports (&riscv_rps_as
, "h"))
1106 as_warn (_("invalid CSR `%s', needs `h' extension"), csr_name
);
1108 if (extension
!= NULL
1109 && !riscv_subset_supports (&riscv_rps_as
, extension
))
1110 as_warn (_("invalid CSR `%s', needs `%s' extension"),
1111 csr_name
, extension
);
1114 while (entry
!= NULL
)
1116 if (!need_check_version
1117 || (default_priv_spec
>= entry
->define_version
1118 && default_priv_spec
< entry
->abort_version
))
1120 /* Find the CSR according to the specific version. */
1121 return entry
->address
;
1123 entry
= entry
->next
;
1126 /* Can not find the CSR address from the chosen privileged version,
1127 so use the newly defined value. */
1128 if (riscv_opts
.csr_check
)
1130 const char *priv_name
= NULL
;
1131 RISCV_GET_PRIV_SPEC_NAME (priv_name
, default_priv_spec
);
1132 if (priv_name
!= NULL
)
1133 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
1134 csr_name
, priv_name
);
1137 return saved_entry
->address
;
1140 /* Return -1 if the CSR has never been defined. Otherwise, return
1144 reg_csr_lookup_internal (const char *s
)
1146 struct riscv_csr_extra
*r
=
1147 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
1152 return riscv_csr_address (s
, r
);
1156 reg_lookup_internal (const char *s
, enum reg_class
class)
1160 if (class == RCLASS_CSR
)
1161 return reg_csr_lookup_internal (s
);
1163 r
= str_hash_find (reg_names_hash
, s
);
1164 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
1167 if (riscv_subset_supports (&riscv_rps_as
, "e")
1168 && class == RCLASS_GPR
1169 && DECODE_REG_NUM (r
) > 15)
1172 return DECODE_REG_NUM (r
);
1176 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
1182 /* Find end of name. */
1184 if (is_name_beginner (*e
))
1186 while (is_part_of_name (*e
))
1189 /* Terminate name. */
1193 /* Look for the register. Advance to next token if one was recognized. */
1194 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
1204 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
1206 const char *p
= strchr (*s
, ',');
1207 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
1212 for (i
= 0; i
< size
; i
++)
1213 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0
1214 && array
[i
][len
] == '\0')
1224 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
1225 #define USE_IMM(n, s) \
1226 (used_bits |= ((insn_t)((1ull<<n)-1) << (s)))
1228 /* For consistency checking, verify that all bits are specified either
1229 by the match/mask part of the instruction definition, or by the
1230 operand list. The `length` could be the actual instruction length or
1231 0 for auto-detection. */
1234 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
1236 const char *oparg
, *opargStart
;
1237 insn_t used_bits
= opc
->mask
;
1239 insn_t required_bits
;
1242 length
= riscv_insn_length (opc
->match
);
1243 /* We don't support instructions longer than 64-bits yet. */
1246 insn_width
= 8 * length
;
1248 required_bits
= ((insn_t
)~0ULL) >> (64 - insn_width
);
1250 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
1252 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
1253 opc
->name
, opc
->args
);
1257 for (oparg
= opc
->args
; *oparg
; ++oparg
)
1265 case 'U': break; /* CRS1, constrained to equal RD. */
1266 case 'c': break; /* CRS1, constrained to equal sp. */
1267 case 'T': /* CRS2, floating point. */
1268 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
1269 case 'S': /* CRS1S, floating point. */
1270 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
1271 case 'w': break; /* CRS1S, constrained to equal RD. */
1272 case 'D': /* CRS2S, floating point. */
1273 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
1274 case 'x': break; /* CRS2S, constrained to equal RD. */
1275 case 'z': break; /* CRS2S, constrained to be x0. */
1276 case '>': /* CITYPE immediate, compressed shift. */
1277 case 'u': /* CITYPE immediate, compressed lui. */
1278 case 'v': /* CITYPE immediate, li to compressed lui. */
1279 case 'o': /* CITYPE immediate, allow zero. */
1280 case 'j': used_bits
|= ENCODE_CITYPE_IMM (-1U); break;
1281 case 'L': used_bits
|= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
1282 case 'm': used_bits
|= ENCODE_CITYPE_LWSP_IMM (-1U); break;
1283 case 'n': used_bits
|= ENCODE_CITYPE_LDSP_IMM (-1U); break;
1284 case '6': used_bits
|= ENCODE_CSSTYPE_IMM (-1U); break;
1285 case 'M': used_bits
|= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
1286 case 'N': used_bits
|= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
1287 case '8': used_bits
|= ENCODE_CIWTYPE_IMM (-1U); break;
1288 case 'K': used_bits
|= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
1289 /* CLTYPE and CSTYPE have the same immediate encoding. */
1290 case '5': used_bits
|= ENCODE_CLTYPE_IMM (-1U); break;
1291 case 'k': used_bits
|= ENCODE_CLTYPE_LW_IMM (-1U); break;
1292 case 'l': used_bits
|= ENCODE_CLTYPE_LD_IMM (-1U); break;
1293 case 'p': used_bits
|= ENCODE_CBTYPE_IMM (-1U); break;
1294 case 'a': used_bits
|= ENCODE_CJTYPE_IMM (-1U); break;
1295 case 'F': /* Compressed funct for .insn directive. */
1298 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
1299 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
1300 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
1301 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
1303 goto unknown_validate_operand
;
1307 goto unknown_validate_operand
;
1309 break; /* end RVC */
1314 case 'f': USE_BITS (OP_MASK_VD
, OP_SH_VD
); break;
1315 case 'e': USE_BITS (OP_MASK_VWD
, OP_SH_VWD
); break;
1316 case 's': USE_BITS (OP_MASK_VS1
, OP_SH_VS1
); break;
1317 case 't': USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1318 case 'u': USE_BITS (OP_MASK_VS1
, OP_SH_VS1
);
1319 USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1320 case 'v': USE_BITS (OP_MASK_VD
, OP_SH_VD
);
1321 USE_BITS (OP_MASK_VS1
, OP_SH_VS1
);
1322 USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1324 case 'b': used_bits
|= ENCODE_RVV_VB_IMM (-1U); break;
1325 case 'c': used_bits
|= ENCODE_RVV_VC_IMM (-1U); break;
1328 case 'k': USE_BITS (OP_MASK_VIMM
, OP_SH_VIMM
); break;
1329 case 'm': USE_BITS (OP_MASK_VMASK
, OP_SH_VMASK
); break;
1330 case 'M': break; /* Macro operand, must be a mask register. */
1331 case 'T': break; /* Macro operand, must be a vector register. */
1333 goto unknown_validate_operand
;
1335 break; /* end RVV */
1339 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
1340 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
1341 case 'A': break; /* Macro operand, must be symbol. */
1342 case 'B': break; /* Macro operand, must be symbol or constant. */
1343 case 'c': break; /* Macro operand, must be symbol or constant. */
1344 case 'I': break; /* Macro operand, must be constant. */
1345 case 'D': /* RD, floating point. */
1346 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
1347 case 'y': USE_BITS (OP_MASK_BS
, OP_SH_BS
); break;
1348 case 'Y': USE_BITS (OP_MASK_RNUM
, OP_SH_RNUM
); break;
1349 case 'Z': /* RS1, CSR number. */
1350 case 'S': /* RS1, floating point. */
1351 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1352 case 'U': /* RS1 and RS2 are the same, floating point. */
1353 USE_BITS (OP_MASK_RS1
, OP_SH_RS1
);
1355 case 'T': /* RS2, floating point. */
1356 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
1357 case 'R': /* RS3, floating point. */
1358 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
1359 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
1360 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
1361 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
1362 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
1363 case 'o': /* ITYPE immediate, load displacement. */
1364 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
1365 case 'a': used_bits
|= ENCODE_JTYPE_IMM (-1U); break;
1366 case 'p': used_bits
|= ENCODE_BTYPE_IMM (-1U); break;
1367 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1368 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1369 case 'z': break; /* Zero immediate. */
1370 case '[': break; /* Unused operand. */
1371 case ']': break; /* Unused operand. */
1372 case '0': break; /* AMO displacement, must to zero. */
1373 case '1': break; /* Relaxation operand. */
1374 case 'F': /* Funct for .insn directive. */
1377 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1378 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1379 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1381 goto unknown_validate_operand
;
1384 case 'O': /* Opcode for .insn directive. */
1387 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1388 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1390 goto unknown_validate_operand
;
1393 case 'W': /* Various operands. */
1399 case 'f': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1401 goto unknown_validate_operand
;
1405 goto unknown_validate_operand
;
1408 case 'X': /* Integer immediate. */
1415 case 'l': /* Literal. */
1416 oparg
+= strcspn(oparg
, ",") - 1;
1418 case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
1420 case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */
1423 n
= strtol (oparg
+ 1, (char **)&oparg
, 10);
1425 goto unknown_validate_operand
;
1426 s
= strtol (oparg
+ 1, (char **)&oparg
, 10);
1432 goto unknown_validate_operand
;
1437 unknown_validate_operand
:
1438 as_bad (_("internal: bad RISC-V opcode "
1439 "(unknown operand type `%s'): %s %s"),
1440 opargStart
, opc
->name
, opc
->args
);
1445 if (used_bits
!= required_bits
)
1447 as_bad (_("internal: bad RISC-V opcode "
1448 "(bits %#llx undefined or invalid): %s %s"),
1449 (unsigned long long)(used_bits
^ required_bits
),
1450 opc
->name
, opc
->args
);
1458 struct percent_op_match
1461 bfd_reloc_code_real_type reloc
;
1464 /* Common hash table initialization function for instruction and .insn
1468 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1469 bool insn_directive_p
)
1473 htab_t hash
= str_htab_create ();
1474 while (opcodes
[i
].name
)
1476 const char *name
= opcodes
[i
].name
;
1477 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1478 as_fatal (_("internal: duplicate %s"), name
);
1482 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1484 if (insn_directive_p
)
1485 length
= ((name
[0] == 'c') ? 2 : 4);
1487 length
= 0; /* Let assembler determine the length. */
1488 if (!validate_riscv_insn (&opcodes
[i
], length
))
1489 as_fatal (_("internal: broken assembler. "
1490 "No assembly attempted"));
1493 gas_assert (!insn_directive_p
);
1496 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1502 /* This function is called once, at assembler startup time. It should set up
1503 all the tables, etc. that the MD part of the assembler will need. */
1508 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1510 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1511 as_warn (_("could not set architecture and machine"));
1513 op_hash
= init_opcode_hash (riscv_opcodes
, false);
1514 insn_type_hash
= init_opcode_hash (riscv_insn_types
, true);
1516 reg_names_hash
= str_htab_create ();
1517 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1518 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1519 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1520 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1521 hash_reg_names (RCLASS_VECR
, riscv_vecr_names_numeric
, NVECR
);
1522 hash_reg_names (RCLASS_VECM
, riscv_vecm_names_numeric
, NVECM
);
1523 /* Add "fp" as an alias for "s0". */
1524 hash_reg_name (RCLASS_GPR
, "fp", 8);
1526 /* Create and insert CSR hash tables. */
1527 csr_extra_hash
= str_htab_create ();
1528 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1529 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1530 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1531 DECLARE_CSR(name, num, class, define_version, abort_version);
1532 #include "opcode/riscv-opc.h"
1535 opcode_names_hash
= str_htab_create ();
1536 init_opcode_names_hash ();
1538 /* Set the default alignment for the text section. */
1539 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1543 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1550 case BFD_RELOC_RISCV_HI20
:
1551 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1553 case BFD_RELOC_RISCV_LO12_S
:
1554 return ENCODE_STYPE_IMM (value
);
1556 case BFD_RELOC_RISCV_LO12_I
:
1557 return ENCODE_ITYPE_IMM (value
);
1564 /* Output an instruction. IP is the instruction information.
1565 ADDRESS_EXPR is an operand of the instruction to be used with
1569 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1570 bfd_reloc_code_real_type reloc_type
)
1572 dwarf2_emit_insn (0);
1574 if (reloc_type
!= BFD_RELOC_UNUSED
)
1576 reloc_howto_type
*howto
;
1578 gas_assert (address_expr
);
1579 if (reloc_type
== BFD_RELOC_12_PCREL
1580 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1582 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1583 int best_case
= insn_length (ip
);
1584 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1586 if (now_seg
== absolute_section
)
1588 as_bad (_("relaxable branches not supported in absolute section"));
1592 add_relaxed_insn (ip
, worst_case
, best_case
,
1593 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1594 address_expr
->X_add_symbol
,
1595 address_expr
->X_add_number
);
1600 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1602 as_bad (_("internal: unsupported RISC-V relocation number %d"),
1605 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1606 bfd_get_reloc_size (howto
),
1607 address_expr
, false, reloc_type
);
1609 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1613 add_fixed_insn (ip
);
1615 /* We need to start a new frag after any instruction that can be
1616 optimized away or compressed by the linker during relaxation, to prevent
1617 the assembler from computing static offsets across such an instruction.
1618 This is necessary to get correct EH info. */
1619 if (reloc_type
== BFD_RELOC_RISCV_HI20
1620 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1621 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1622 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1624 frag_wane (frag_now
);
1629 /* Build an instruction created by a macro expansion. This is passed
1630 a pointer to the count of instructions created so far, an expression,
1631 the name of the instruction to build, an operand format string, and
1632 corresponding arguments. */
1635 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1637 const struct riscv_opcode
*mo
;
1638 struct riscv_cl_insn insn
;
1639 bfd_reloc_code_real_type r
;
1641 const char *fmtStart
;
1643 va_start (args
, fmt
);
1645 r
= BFD_RELOC_UNUSED
;
1646 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1649 /* Find a non-RVC variant of the instruction. append_insn will compress
1651 while (riscv_insn_length (mo
->match
) < 4)
1653 gas_assert (strcmp (name
, mo
->name
) == 0);
1655 create_insn (&insn
, mo
);
1665 INSERT_OPERAND (VD
, insn
, va_arg (args
, int));
1668 INSERT_OPERAND (VS1
, insn
, va_arg (args
, int));
1671 INSERT_OPERAND (VS2
, insn
, va_arg (args
, int));
1675 int reg
= va_arg (args
, int);
1678 INSERT_OPERAND (VMASK
, insn
, 1);
1683 INSERT_OPERAND (VMASK
, insn
, 0);
1687 goto unknown_macro_argument
;
1690 goto unknown_macro_argument
;
1695 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1698 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1701 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1707 gas_assert (ep
!= NULL
);
1708 r
= va_arg (args
, int);
1716 unknown_macro_argument
:
1717 as_fatal (_("internal: invalid macro argument `%s'"), fmtStart
);
1722 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1724 append_insn (&insn
, ep
, r
);
1727 /* Build an instruction created by a macro expansion. Like md_assemble but
1728 accept a printf-style format string and arguments. */
1731 md_assemblef (const char *format
, ...)
1737 va_start (ap
, format
);
1739 r
= vasprintf (&buf
, format
, ap
);
1742 as_fatal (_("internal: vasprintf failed"));
1750 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1754 normalize_constant_expr (expressionS
*ex
)
1758 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1759 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1760 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1764 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1765 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1768 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1771 if (ex
->X_op
== O_big
)
1772 as_bad (_("unsupported large constant"));
1773 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1774 as_bad (_("unknown CSR `%s'"),
1775 S_GET_NAME (ex
->X_add_symbol
));
1776 else if (ex
->X_op
!= O_constant
)
1777 as_bad (_("instruction %s requires absolute expression"),
1779 normalize_constant_expr (ex
);
1783 make_internal_label (void)
1785 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1789 /* Load an entry from the GOT. */
1792 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1793 const char *lo_insn
, const char *lo_pattern
,
1794 bfd_reloc_code_real_type hi_reloc
,
1795 bfd_reloc_code_real_type lo_reloc
)
1798 ep2
.X_op
= O_symbol
;
1799 ep2
.X_add_symbol
= make_internal_label ();
1800 ep2
.X_add_number
= 0;
1802 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1803 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1807 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1808 bfd_reloc_code_real_type hi_reloc
,
1809 bfd_reloc_code_real_type lo_reloc
)
1811 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1815 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1816 bfd_reloc_code_real_type hi_reloc
,
1817 bfd_reloc_code_real_type lo_reloc
)
1819 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1822 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1825 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1826 bfd_reloc_code_real_type reloc
)
1828 /* Ensure the jalr is emitted to the same frag as the auipc. */
1830 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1831 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1832 /* See comment at end of append_insn. */
1833 frag_wane (frag_now
);
1837 /* Load an integer constant into a register. */
1840 load_const (int reg
, expressionS
*ep
)
1842 int shift
= RISCV_IMM_BITS
;
1843 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1844 expressionS upper
= *ep
, lower
= *ep
;
1845 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1846 upper
.X_add_number
-= lower
.X_add_number
;
1848 if (ep
->X_op
!= O_constant
)
1850 as_bad (_("unsupported large constant"));
1854 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1856 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1857 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1860 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1861 load_const (reg
, &upper
);
1863 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1864 if (lower
.X_add_number
!= 0)
1865 md_assemblef ("addi x%d, x%d, %" PRId64
, reg
, reg
,
1866 (int64_t) lower
.X_add_number
);
1870 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1873 if (upper
.X_add_number
!= 0)
1875 /* Discard low part and zero-extend upper immediate. */
1876 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1878 md_assemblef ("lui x%d, 0x%" PRIx64
, reg
, (uint64_t) upper_imm
);
1882 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1883 md_assemblef ("%s x%d, x%d, %" PRId64
, ADD32_INSN
, reg
, hi_reg
,
1884 (int64_t) lower
.X_add_number
);
1888 /* Zero extend and sign extend byte/half-word/word. */
1891 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bool sign
)
1895 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1896 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1900 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1901 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1905 /* Expand RISC-V Vector macros into one or more instructions. */
1908 vector_macro (struct riscv_cl_insn
*ip
)
1910 int vd
= (ip
->insn_opcode
>> OP_SH_VD
) & OP_MASK_VD
;
1911 int vs1
= (ip
->insn_opcode
>> OP_SH_VS1
) & OP_MASK_VS1
;
1912 int vs2
= (ip
->insn_opcode
>> OP_SH_VS2
) & OP_MASK_VS2
;
1913 int vm
= (ip
->insn_opcode
>> OP_SH_VMASK
) & OP_MASK_VMASK
;
1914 int vtemp
= (ip
->insn_opcode
>> OP_SH_VFUNCT6
) & OP_MASK_VFUNCT6
;
1915 int mask
= ip
->insn_mo
->mask
;
1923 macro_build (NULL
, "vmslt.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, -1);
1924 macro_build (NULL
, "vmnand.mm", "Vd,Vt,Vs", vd
, vd
, vd
);
1929 /* Masked. Have vtemp to avoid overlap constraints. */
1932 macro_build (NULL
, "vmslt.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1933 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vm
, vtemp
);
1937 /* Preserve the value of vd if not updating by vm. */
1938 macro_build (NULL
, "vmslt.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1939 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vtemp
, vm
, vtemp
);
1940 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1941 macro_build (NULL
, "vmor.mm", "Vd,Vt,Vs", vd
, vtemp
, vd
);
1946 /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
1947 macro_build (NULL
, "vmslt.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, vm
);
1948 macro_build (NULL
, "vmxor.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1951 as_bad (_("must provide temp if destination overlaps mask"));
1958 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, -1);
1959 macro_build (NULL
, "vmnand.mm", "Vd,Vt,Vs", vd
, vd
, vd
);
1964 /* Masked. Have vtemp to avoid overlap constraints. */
1967 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1968 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vm
, vtemp
);
1972 /* Preserve the value of vd if not updating by vm. */
1973 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1974 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vtemp
, vm
, vtemp
);
1975 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1976 macro_build (NULL
, "vmor.mm", "Vd,Vt,Vs", vd
, vtemp
, vd
);
1981 /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
1982 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, vm
);
1983 macro_build (NULL
, "vmxor.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1986 as_bad (_("must provide temp if destination overlaps mask"));
1994 /* Expand RISC-V assembly macros into one or more instructions. */
1997 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1998 bfd_reloc_code_real_type
*imm_reloc
)
2000 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
2001 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
2002 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
2003 int mask
= ip
->insn_mo
->mask
;
2008 load_const (rd
, imm_expr
);
2013 /* Load the address of a symbol into a register. */
2014 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
2015 as_bad (_("offset too large"));
2017 if (imm_expr
->X_op
== O_constant
)
2018 load_const (rd
, imm_expr
);
2019 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol. */
2020 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
2021 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2022 else /* Local PIC symbol, or any non-PIC symbol. */
2023 pcrel_load (rd
, rd
, imm_expr
, "addi",
2024 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2028 pcrel_load (rd
, rd
, imm_expr
, "addi",
2029 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2033 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
2034 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2038 pcrel_load (rd
, rd
, imm_expr
, "lb",
2039 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2043 pcrel_load (rd
, rd
, imm_expr
, "lbu",
2044 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2048 pcrel_load (rd
, rd
, imm_expr
, "lh",
2049 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2053 pcrel_load (rd
, rd
, imm_expr
, "lhu",
2054 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2058 pcrel_load (rd
, rd
, imm_expr
, "lw",
2059 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2063 pcrel_load (rd
, rd
, imm_expr
, "lwu",
2064 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2068 pcrel_load (rd
, rd
, imm_expr
, "ld",
2069 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2073 pcrel_load (rd
, rs1
, imm_expr
, "flw",
2074 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2078 pcrel_load (rd
, rs1
, imm_expr
, "fld",
2079 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2083 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
2084 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2088 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
2089 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2093 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
2094 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2098 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
2099 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2103 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
2104 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2108 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
2109 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2113 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
2117 riscv_ext (rd
, rs1
, xlen
- 16, false);
2121 riscv_ext (rd
, rs1
, xlen
- 32, false);
2125 riscv_ext (rd
, rs1
, xlen
- 8, true);
2129 riscv_ext (rd
, rs1
, xlen
- 16, true);
2138 pcrel_load (rd
, rs1
, imm_expr
, "flh",
2139 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
2142 pcrel_store (rs2
, rs1
, imm_expr
, "fsh",
2143 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
2147 as_bad (_("internal: macro %s not implemented"), ip
->insn_mo
->name
);
2152 static const struct percent_op_match percent_op_utype
[] =
2154 {"tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
2155 {"pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
2156 {"got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
2157 {"tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
2158 {"tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
2159 {"hi", BFD_RELOC_RISCV_HI20
},
2163 static const struct percent_op_match percent_op_itype
[] =
2165 {"lo", BFD_RELOC_RISCV_LO12_I
},
2166 {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
2167 {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
2171 static const struct percent_op_match percent_op_stype
[] =
2173 {"lo", BFD_RELOC_RISCV_LO12_S
},
2174 {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
2175 {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
2179 static const struct percent_op_match percent_op_rtype
[] =
2181 {"tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
2185 static const struct percent_op_match percent_op_null
[] =
2190 /* Return true if *STR points to a relocation operator. When returning true,
2191 move *STR over the operator and store its relocation code in *RELOC.
2192 Leave both *STR and *RELOC alone when returning false. */
2195 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
2196 const struct percent_op_match
*percent_op
)
2198 for ( ; percent_op
->str
; percent_op
++)
2199 if (strncasecmp (*str
+ 1, percent_op
->str
, strlen (percent_op
->str
)) == 0)
2201 size_t len
= 1 + strlen (percent_op
->str
);
2203 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
2207 *reloc
= percent_op
->reloc
;
2209 /* Check whether the output BFD supports this relocation.
2210 If not, issue an error and fall back on something safe. */
2211 if (*reloc
!= BFD_RELOC_UNUSED
2212 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
2214 as_bad ("internal: relocation %s isn't supported by the "
2215 "current ABI", percent_op
->str
);
2216 *reloc
= BFD_RELOC_UNUSED
;
2224 my_getExpression (expressionS
*ep
, char *str
)
2228 save_in
= input_line_pointer
;
2229 input_line_pointer
= str
;
2231 expr_parse_end
= input_line_pointer
;
2232 input_line_pointer
= save_in
;
2235 /* Parse string STR as a 16-bit relocatable operand. Store the
2236 expression in *EP and the relocation, if any, in RELOC.
2237 Return the number of relocation operators used (0 or 1).
2239 On exit, EXPR_PARSE_END points to the first character after the
2243 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
2244 char *str
, const struct percent_op_match
*percent_op
)
2247 unsigned crux_depth
, str_depth
;
2248 bool orig_probing
= probing_insn_operands
;
2251 /* Search for the start of the main expression.
2253 End the loop with CRUX pointing to the start of the main expression and
2254 with CRUX_DEPTH containing the number of open brackets at that point. */
2261 crux_depth
= str_depth
;
2263 /* Skip over whitespace and brackets, keeping count of the number
2265 while (*str
== ' ' || *str
== '\t' || *str
== '(')
2271 && parse_relocation (&str
, reloc
, percent_op
));
2275 /* expression() will choke on anything looking like an (unrecognized)
2276 relocation specifier. Don't even call it, avoiding multiple (and
2277 perhaps redundant) error messages; our caller will issue one. */
2278 ep
->X_op
= O_illegal
;
2282 /* Anything inside parentheses or subject to a relocation operator cannot
2283 be a register and hence can be treated the same as operands to
2284 directives (other than .insn). */
2285 if (str_depth
|| reloc_index
)
2286 probing_insn_operands
= false;
2288 my_getExpression (ep
, crux
);
2289 str
= expr_parse_end
;
2291 probing_insn_operands
= orig_probing
;
2293 /* Match every open bracket. */
2294 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
2299 as_bad ("unclosed '('");
2301 expr_parse_end
= str
;
2306 /* Parse opcode name, could be an mnemonics or number. */
2309 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
2312 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
2316 ep
->X_op
= O_constant
;
2317 ep
->X_add_number
= o
->val
;
2321 return my_getSmallExpression (ep
, reloc
, str
, percent_op_null
);
2324 /* Parse string STR as a vsetvli operand. Store the expression in *EP.
2325 On exit, EXPR_PARSE_END points to the first character after the
2329 my_getVsetvliExpression (expressionS
*ep
, char *str
)
2331 unsigned int vsew_value
= 0, vlmul_value
= 0;
2332 unsigned int vta_value
= 0, vma_value
= 0;
2333 bfd_boolean vsew_found
= FALSE
, vlmul_found
= FALSE
;
2334 bfd_boolean vta_found
= FALSE
, vma_found
= FALSE
;
2336 if (arg_lookup (&str
, riscv_vsew
, ARRAY_SIZE (riscv_vsew
), &vsew_value
))
2341 as_bad (_("multiple vsew constants"));
2344 if (arg_lookup (&str
, riscv_vlmul
, ARRAY_SIZE (riscv_vlmul
), &vlmul_value
))
2349 as_bad (_("multiple vlmul constants"));
2352 if (arg_lookup (&str
, riscv_vta
, ARRAY_SIZE (riscv_vta
), &vta_value
))
2357 as_bad (_("multiple vta constants"));
2360 if (arg_lookup (&str
, riscv_vma
, ARRAY_SIZE (riscv_vma
), &vma_value
))
2365 as_bad (_("multiple vma constants"));
2369 if (vsew_found
|| vlmul_found
|| vta_found
|| vma_found
)
2371 ep
->X_op
= O_constant
;
2372 ep
->X_add_number
= (vlmul_value
<< OP_SH_VLMUL
)
2373 | (vsew_value
<< OP_SH_VSEW
)
2374 | (vta_value
<< OP_SH_VTA
)
2375 | (vma_value
<< OP_SH_VMA
);
2376 expr_parse_end
= str
;
2380 my_getExpression (ep
, str
);
2381 str
= expr_parse_end
;
2385 /* Detect and handle implicitly zero load-store offsets. For example,
2386 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return true if such
2387 an implicit offset was detected. */
2390 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
2392 /* Check whether there is only a single bracketed expression left.
2393 If so, it must be the base register and the constant must be zero. */
2394 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
2396 ep
->X_op
= O_constant
;
2397 ep
->X_add_number
= 0;
2404 /* All RISC-V CSR instructions belong to one of these classes. */
2413 /* Return which CSR instruction is checking. */
2415 static enum csr_insn_type
2416 riscv_csr_insn_type (insn_t insn
)
2418 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
2419 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
2421 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
2422 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
2424 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
2425 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
2428 return INSN_NOT_CSR
;
2431 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
2432 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
2433 CSR address is 0x3. */
2436 riscv_csr_read_only_check (insn_t insn
)
2438 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
2439 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
2440 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
2441 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
2444 && (((csr_insn
== INSN_CSRRS
2445 || csr_insn
== INSN_CSRRC
)
2447 || csr_insn
== INSN_CSRRW
))
2453 /* Return true if it is a privileged instruction. Otherwise, return false.
2455 uret is actually a N-ext instruction. So it is better to regard it as
2456 an user instruction rather than the priv instruction.
2458 hret is used to return from traps in H-mode. H-mode is removed since
2459 the v1.10 priv spec, but probably be added in the new hypervisor spec.
2460 Therefore, hret should be controlled by the hypervisor spec rather than
2461 priv spec in the future.
2463 dret is defined in the debug spec, so it should be checked in the future,
2467 riscv_is_priv_insn (insn_t insn
)
2469 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
2470 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
2471 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
2472 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
2473 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
2474 check it here to keep the compatible. */
2475 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
2478 static symbolS
*deferred_sym_rootP
;
2479 static symbolS
*deferred_sym_lastP
;
2480 /* Since symbols can't easily be freed, try to recycle ones which weren't
2482 static symbolS
*orphan_sym_rootP
;
2483 static symbolS
*orphan_sym_lastP
;
2485 /* This routine assembles an instruction into its binary format. As a
2486 side effect, it sets the global variable imm_reloc to the type of
2487 relocation to do if one of the operands is an address expression. */
2489 static struct riscv_ip_error
2490 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
2491 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
2493 /* The operand string defined in the riscv_opcodes. */
2494 const char *oparg
, *opargStart
;
2495 /* The parsed operands from assembly. */
2496 char *asarg
, *asargStart
;
2498 struct riscv_opcode
*insn
;
2500 const struct percent_op_match
*p
;
2501 struct riscv_ip_error error
;
2502 error
.msg
= "unrecognized opcode";
2503 error
.statement
= str
;
2504 error
.missing_ext
= NULL
;
2505 /* Indicate we are assembling instruction with CSR. */
2506 bool insn_with_csr
= false;
2508 /* Parse the name of the instruction. Terminate the string if whitespace
2509 is found so that str_hash_find only sees the name part of the string. */
2510 for (asarg
= str
; *asarg
!= '\0'; ++asarg
)
2511 if (ISSPACE (*asarg
))
2518 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
2520 probing_insn_operands
= true;
2523 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
2525 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
2528 if (!riscv_multi_subset_supports (&riscv_rps_as
, insn
->insn_class
))
2530 error
.missing_ext
= riscv_multi_subset_supports_ext (&riscv_rps_as
,
2535 /* Reset error message of the previous round. */
2536 error
.msg
= _("illegal operands");
2537 error
.missing_ext
= NULL
;
2539 /* Purge deferred symbols from the previous round, if any. */
2540 while (deferred_sym_rootP
)
2542 symbolS
*sym
= deferred_sym_rootP
;
2544 symbol_remove (sym
, &deferred_sym_rootP
, &deferred_sym_lastP
);
2545 symbol_append (sym
, orphan_sym_lastP
, &orphan_sym_rootP
,
2549 create_insn (ip
, insn
);
2551 imm_expr
->X_op
= O_absent
;
2552 *imm_reloc
= BFD_RELOC_UNUSED
;
2553 p
= percent_op_null
;
2555 for (oparg
= insn
->args
;; ++oparg
)
2558 asarg
+= strspn (asarg
, " \t");
2561 case '\0': /* End of args. */
2562 if (insn
->pinfo
!= INSN_MACRO
)
2564 if (!insn
->match_func (insn
, ip
->insn_opcode
))
2567 /* For .insn, insn->match and insn->mask are 0. */
2568 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
2574 if (riscv_is_priv_insn (ip
->insn_opcode
))
2575 explicit_priv_attr
= true;
2577 /* Check if we write a read-only CSR by the CSR
2580 && riscv_opts
.csr_check
2581 && !riscv_csr_read_only_check (ip
->insn_opcode
))
2583 /* Restore the character in advance, since we want to
2584 report the detailed warning message here. */
2586 *(asargStart
- 1) = save_c
;
2587 as_warn (_("read-only CSR is written `%s'"), str
);
2588 insn_with_csr
= false;
2591 /* The (segmant) load and store with EEW 64 cannot be used
2592 when zve32x is enabled. */
2593 if (ip
->insn_mo
->pinfo
& INSN_V_EEW64
2594 && riscv_subset_supports (&riscv_rps_as
, "zve32x")
2595 && !riscv_subset_supports (&riscv_rps_as
, "zve64x"))
2597 error
.msg
= _("illegal opcode for zve32x");
2604 /* Successful assembly. */
2606 insn_with_csr
= false;
2608 /* Commit deferred symbols, if any. */
2609 while (deferred_sym_rootP
)
2611 symbolS
*sym
= deferred_sym_rootP
;
2613 symbol_remove (sym
, &deferred_sym_rootP
,
2614 &deferred_sym_lastP
);
2615 symbol_append (sym
, symbol_lastP
, &symbol_rootP
,
2617 symbol_table_insert (sym
);
2624 case 's': /* RS1 x8-x15. */
2625 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2626 || !(regno
>= 8 && regno
<= 15))
2628 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2630 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2631 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2632 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
2635 case 't': /* RS2 x8-x15. */
2636 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2637 || !(regno
>= 8 && regno
<= 15))
2639 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2641 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2642 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2643 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
2646 case 'U': /* RS1, constrained to equal RD. */
2647 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2648 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
2652 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
))
2654 INSERT_OPERAND (CRS2
, *ip
, regno
);
2656 case 'c': /* RS1, constrained to equal sp. */
2657 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2661 case 'z': /* RS2, constrained to equal x0. */
2662 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2666 case '>': /* Shift amount, 0 - (XLEN-1). */
2667 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2668 || imm_expr
->X_op
!= O_constant
2669 || (unsigned long) imm_expr
->X_add_number
>= xlen
)
2671 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2673 asarg
= expr_parse_end
;
2674 imm_expr
->X_op
= O_absent
;
2677 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2678 || imm_expr
->X_op
!= O_constant
2679 || imm_expr
->X_add_number
< 0
2680 || imm_expr
->X_add_number
>= 32
2681 || !VALID_CLTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2683 ip
->insn_opcode
|= ENCODE_CLTYPE_IMM (imm_expr
->X_add_number
);
2686 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2687 || imm_expr
->X_op
!= O_constant
2688 || imm_expr
->X_add_number
< 0
2689 || imm_expr
->X_add_number
>= 64
2690 || !VALID_CSSTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2692 ip
->insn_opcode
|= ENCODE_CSSTYPE_IMM (imm_expr
->X_add_number
);
2695 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2696 || imm_expr
->X_op
!= O_constant
2697 || imm_expr
->X_add_number
< 0
2698 || imm_expr
->X_add_number
>= 256
2699 || !VALID_CIWTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2701 ip
->insn_opcode
|= ENCODE_CIWTYPE_IMM (imm_expr
->X_add_number
);
2704 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2705 || imm_expr
->X_op
!= O_constant
2706 || imm_expr
->X_add_number
== 0
2707 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2709 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2712 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2714 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2715 || imm_expr
->X_op
!= O_constant
2716 || !VALID_CLTYPE_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2718 ip
->insn_opcode
|= ENCODE_CLTYPE_LW_IMM (imm_expr
->X_add_number
);
2721 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2723 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2724 || imm_expr
->X_op
!= O_constant
2725 || !VALID_CLTYPE_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2727 ip
->insn_opcode
|= ENCODE_CLTYPE_LD_IMM (imm_expr
->X_add_number
);
2730 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2732 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2733 || imm_expr
->X_op
!= O_constant
2734 || !VALID_CITYPE_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2737 ENCODE_CITYPE_LWSP_IMM (imm_expr
->X_add_number
);
2740 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2742 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2743 || imm_expr
->X_op
!= O_constant
2744 || !VALID_CITYPE_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2747 ENCODE_CITYPE_LDSP_IMM (imm_expr
->X_add_number
);
2750 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2751 || imm_expr
->X_op
!= O_constant
2752 /* C.addiw, c.li, and c.andi allow zero immediate.
2753 C.addi allows zero immediate as hint. Otherwise this
2755 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2757 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2760 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2761 || imm_expr
->X_op
!= O_constant
2762 || imm_expr
->X_add_number
== 0
2763 || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2766 ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2769 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2770 || imm_expr
->X_op
!= O_constant
2771 || !VALID_CITYPE_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2774 ENCODE_CITYPE_ADDI16SP_IMM (imm_expr
->X_add_number
);
2777 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2779 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2780 || imm_expr
->X_op
!= O_constant
2781 || !VALID_CSSTYPE_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2784 ENCODE_CSSTYPE_SWSP_IMM (imm_expr
->X_add_number
);
2787 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2789 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2790 || imm_expr
->X_op
!= O_constant
2791 || !VALID_CSSTYPE_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2794 ENCODE_CSSTYPE_SDSP_IMM (imm_expr
->X_add_number
);
2797 p
= percent_op_utype
;
2798 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
2801 if (imm_expr
->X_op
!= O_constant
2802 || imm_expr
->X_add_number
<= 0
2803 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2804 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2805 && (imm_expr
->X_add_number
<
2806 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2808 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2811 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2812 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2813 || ((int32_t)imm_expr
->X_add_number
2814 != imm_expr
->X_add_number
))
2816 imm_expr
->X_add_number
=
2817 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2823 case 'S': /* Floating-point RS1 x8-x15. */
2824 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
)
2825 || !(regno
>= 8 && regno
<= 15))
2827 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2829 case 'D': /* Floating-point RS2 x8-x15. */
2830 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
)
2831 || !(regno
>= 8 && regno
<= 15))
2833 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2835 case 'T': /* Floating-point RS2. */
2836 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
))
2838 INSERT_OPERAND (CRS2
, *ip
, regno
);
2844 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2845 || imm_expr
->X_op
!= O_constant
2846 || imm_expr
->X_add_number
< 0
2847 || imm_expr
->X_add_number
>= 64)
2849 as_bad (_("bad value for compressed funct6 "
2850 "field, value must be 0...63"));
2853 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2854 imm_expr
->X_op
= O_absent
;
2855 asarg
= expr_parse_end
;
2859 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2860 || imm_expr
->X_op
!= O_constant
2861 || imm_expr
->X_add_number
< 0
2862 || imm_expr
->X_add_number
>= 16)
2864 as_bad (_("bad value for compressed funct4 "
2865 "field, value must be 0...15"));
2868 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2869 imm_expr
->X_op
= O_absent
;
2870 asarg
= expr_parse_end
;
2874 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2875 || imm_expr
->X_op
!= O_constant
2876 || imm_expr
->X_add_number
< 0
2877 || imm_expr
->X_add_number
>= 8)
2879 as_bad (_("bad value for compressed funct3 "
2880 "field, value must be 0...7"));
2883 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2884 imm_expr
->X_op
= O_absent
;
2885 asarg
= expr_parse_end
;
2889 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2890 || imm_expr
->X_op
!= O_constant
2891 || imm_expr
->X_add_number
< 0
2892 || imm_expr
->X_add_number
>= 4)
2894 as_bad (_("bad value for compressed funct2 "
2895 "field, value must be 0...3"));
2898 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2899 imm_expr
->X_op
= O_absent
;
2900 asarg
= expr_parse_end
;
2904 goto unknown_riscv_ip_operand
;
2909 goto unknown_riscv_ip_operand
;
2911 break; /* end RVC */
2917 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2919 INSERT_OPERAND (VD
, *ip
, regno
);
2922 case 'e': /* AMO VD */
2923 if (reg_lookup (&asarg
, RCLASS_GPR
, ®no
) && regno
== 0)
2924 INSERT_OPERAND (VWD
, *ip
, 0);
2925 else if (reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2927 INSERT_OPERAND (VWD
, *ip
, 1);
2928 INSERT_OPERAND (VD
, *ip
, regno
);
2934 case 'f': /* AMO VS3 */
2935 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2937 if (!EXTRACT_OPERAND (VWD
, ip
->insn_opcode
))
2938 INSERT_OPERAND (VD
, *ip
, regno
);
2941 /* VS3 must match VD. */
2942 if (EXTRACT_OPERAND (VD
, ip
->insn_opcode
) != regno
)
2948 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2950 INSERT_OPERAND (VS1
, *ip
, regno
);
2954 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2956 INSERT_OPERAND (VS2
, *ip
, regno
);
2959 case 'u': /* VS1 == VS2 */
2960 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2962 INSERT_OPERAND (VS1
, *ip
, regno
);
2963 INSERT_OPERAND (VS2
, *ip
, regno
);
2966 case 'v': /* VD == VS1 == VS2 */
2967 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2969 INSERT_OPERAND (VD
, *ip
, regno
);
2970 INSERT_OPERAND (VS1
, *ip
, regno
);
2971 INSERT_OPERAND (VS2
, *ip
, regno
);
2974 /* The `V0` is carry-in register for v[m]adc and v[m]sbc,
2975 and is used to choose vs1/rs1/frs1/imm or vs2 for
2976 v[f]merge. It use the same encoding as the vector mask
2979 if (reg_lookup (&asarg
, RCLASS_VECR
, ®no
) && regno
== 0)
2983 case 'b': /* vtypei for vsetivli */
2984 my_getVsetvliExpression (imm_expr
, asarg
);
2985 check_absolute_expr (ip
, imm_expr
, FALSE
);
2986 if (!VALID_RVV_VB_IMM (imm_expr
->X_add_number
))
2987 as_bad (_("bad value for vsetivli immediate field, "
2988 "value must be 0..1023"));
2990 |= ENCODE_RVV_VB_IMM (imm_expr
->X_add_number
);
2991 imm_expr
->X_op
= O_absent
;
2992 asarg
= expr_parse_end
;
2995 case 'c': /* vtypei for vsetvli */
2996 my_getVsetvliExpression (imm_expr
, asarg
);
2997 check_absolute_expr (ip
, imm_expr
, FALSE
);
2998 if (!VALID_RVV_VC_IMM (imm_expr
->X_add_number
))
2999 as_bad (_("bad value for vsetvli immediate field, "
3000 "value must be 0..2047"));
3002 |= ENCODE_RVV_VC_IMM (imm_expr
->X_add_number
);
3003 imm_expr
->X_op
= O_absent
;
3004 asarg
= expr_parse_end
;
3007 case 'i': /* vector arith signed immediate */
3008 my_getExpression (imm_expr
, asarg
);
3009 check_absolute_expr (ip
, imm_expr
, FALSE
);
3010 if (imm_expr
->X_add_number
> 15
3011 || imm_expr
->X_add_number
< -16)
3012 as_bad (_("bad value for vector immediate field, "
3013 "value must be -16...15"));
3014 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
);
3015 imm_expr
->X_op
= O_absent
;
3016 asarg
= expr_parse_end
;
3019 case 'j': /* vector arith unsigned immediate */
3020 my_getExpression (imm_expr
, asarg
);
3021 check_absolute_expr (ip
, imm_expr
, FALSE
);
3022 if (imm_expr
->X_add_number
< 0
3023 || imm_expr
->X_add_number
>= 32)
3024 as_bad (_("bad value for vector immediate field, "
3025 "value must be 0...31"));
3026 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
);
3027 imm_expr
->X_op
= O_absent
;
3028 asarg
= expr_parse_end
;
3031 case 'k': /* vector arith signed immediate, minus 1 */
3032 my_getExpression (imm_expr
, asarg
);
3033 check_absolute_expr (ip
, imm_expr
, FALSE
);
3034 if (imm_expr
->X_add_number
> 16
3035 || imm_expr
->X_add_number
< -15)
3036 as_bad (_("bad value for vector immediate field, "
3037 "value must be -15...16"));
3038 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
- 1);
3039 imm_expr
->X_op
= O_absent
;
3040 asarg
= expr_parse_end
;
3043 case 'm': /* optional vector mask */
3046 INSERT_OPERAND (VMASK
, *ip
, 1);
3049 else if (*asarg
== ',' && asarg
++
3050 && reg_lookup (&asarg
, RCLASS_VECM
, ®no
)
3053 INSERT_OPERAND (VMASK
, *ip
, 0);
3058 case 'M': /* required vector mask */
3059 if (reg_lookup (&asarg
, RCLASS_VECM
, ®no
) && regno
== 0)
3061 INSERT_OPERAND (VMASK
, *ip
, 0);
3066 case 'T': /* vector macro temporary register */
3067 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
) || regno
== 0)
3069 /* Store it in the FUNCT6 field as we don't have anyplace
3070 else to store it. */
3071 INSERT_OPERAND (VFUNCT6
, *ip
, regno
);
3075 goto unknown_riscv_ip_operand
;
3077 break; /* end RVV */
3080 if (*asarg
++ == *oparg
)
3089 if (*asarg
++ == *oparg
)
3093 case '<': /* Shift amount, 0 - 31. */
3094 my_getExpression (imm_expr
, asarg
);
3095 check_absolute_expr (ip
, imm_expr
, false);
3096 if ((unsigned long) imm_expr
->X_add_number
> 31)
3097 as_bad (_("improper shift amount (%"PRIu64
")"),
3098 imm_expr
->X_add_number
);
3099 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
3100 imm_expr
->X_op
= O_absent
;
3101 asarg
= expr_parse_end
;
3104 case '>': /* Shift amount, 0 - (XLEN-1). */
3105 my_getExpression (imm_expr
, asarg
);
3106 check_absolute_expr (ip
, imm_expr
, false);
3107 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
3108 as_bad (_("improper shift amount (%"PRIu64
")"),
3109 imm_expr
->X_add_number
);
3110 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
3111 imm_expr
->X_op
= O_absent
;
3112 asarg
= expr_parse_end
;
3115 case 'Z': /* CSRRxI immediate. */
3116 my_getExpression (imm_expr
, asarg
);
3117 check_absolute_expr (ip
, imm_expr
, false);
3118 if ((unsigned long) imm_expr
->X_add_number
> 31)
3119 as_bad (_("improper CSRxI immediate (%"PRIu64
")"),
3120 imm_expr
->X_add_number
);
3121 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
3122 imm_expr
->X_op
= O_absent
;
3123 asarg
= expr_parse_end
;
3126 case 'E': /* Control register. */
3127 insn_with_csr
= true;
3128 explicit_priv_attr
= true;
3129 if (reg_lookup (&asarg
, RCLASS_CSR
, ®no
))
3130 INSERT_OPERAND (CSR
, *ip
, regno
);
3133 my_getExpression (imm_expr
, asarg
);
3134 check_absolute_expr (ip
, imm_expr
, true);
3135 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
3136 as_bad (_("improper CSR address (%"PRIu64
")"),
3137 imm_expr
->X_add_number
);
3138 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
3139 imm_expr
->X_op
= O_absent
;
3140 asarg
= expr_parse_end
;
3144 case 'm': /* Rounding mode. */
3145 if (arg_lookup (&asarg
, riscv_rm
,
3146 ARRAY_SIZE (riscv_rm
), ®no
))
3148 INSERT_OPERAND (RM
, *ip
, regno
);
3154 case 'Q': /* Fence predecessor/successor. */
3155 if (arg_lookup (&asarg
, riscv_pred_succ
,
3156 ARRAY_SIZE (riscv_pred_succ
), ®no
))
3159 INSERT_OPERAND (PRED
, *ip
, regno
);
3161 INSERT_OPERAND (SUCC
, *ip
, regno
);
3166 case 'd': /* Destination register. */
3167 case 's': /* Source register. */
3168 case 't': /* Target register. */
3170 if (reg_lookup (&asarg
, RCLASS_GPR
, ®no
))
3176 /* Now that we have assembled one operand, we use the args
3177 string to figure out where it goes in the instruction. */
3181 INSERT_OPERAND (RS1
, *ip
, regno
);
3184 INSERT_OPERAND (RD
, *ip
, regno
);
3187 INSERT_OPERAND (RS2
, *ip
, regno
);
3190 INSERT_OPERAND (RS3
, *ip
, regno
);
3197 case 'D': /* Floating point RD. */
3198 case 'S': /* Floating point RS1. */
3199 case 'T': /* Floating point RS2. */
3200 case 'U': /* Floating point RS1 and RS2. */
3201 case 'R': /* Floating point RS3. */
3202 if (reg_lookup (&asarg
,
3203 (riscv_subset_supports (&riscv_rps_as
, "zfinx")
3204 ? RCLASS_GPR
: RCLASS_FPR
), ®no
))
3212 INSERT_OPERAND (RD
, *ip
, regno
);
3215 INSERT_OPERAND (RS1
, *ip
, regno
);
3218 INSERT_OPERAND (RS1
, *ip
, regno
);
3221 INSERT_OPERAND (RS2
, *ip
, regno
);
3224 INSERT_OPERAND (RS3
, *ip
, regno
);
3232 my_getExpression (imm_expr
, asarg
);
3233 if (imm_expr
->X_op
!= O_big
3234 && imm_expr
->X_op
!= O_constant
)
3236 normalize_constant_expr (imm_expr
);
3237 asarg
= expr_parse_end
;
3241 my_getExpression (imm_expr
, asarg
);
3242 normalize_constant_expr (imm_expr
);
3243 /* The 'A' format specifier must be a symbol. */
3244 if (imm_expr
->X_op
!= O_symbol
)
3246 *imm_reloc
= BFD_RELOC_32
;
3247 asarg
= expr_parse_end
;
3251 my_getExpression (imm_expr
, asarg
);
3252 normalize_constant_expr (imm_expr
);
3253 /* The 'B' format specifier must be a symbol or a constant. */
3254 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
3256 if (imm_expr
->X_op
== O_symbol
)
3257 *imm_reloc
= BFD_RELOC_32
;
3258 asarg
= expr_parse_end
;
3261 case 'j': /* Sign-extended immediate. */
3262 p
= percent_op_itype
;
3263 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
3265 case 'q': /* Store displacement. */
3266 p
= percent_op_stype
;
3267 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
3269 case 'o': /* Load displacement. */
3270 p
= percent_op_itype
;
3271 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
3274 /* This is used for TLS, where the fourth operand is
3275 %tprel_add, to get a relocation applied to an add
3276 instruction, for relaxation to use. */
3277 p
= percent_op_rtype
;
3279 case '0': /* AMO displacement, which must be zero. */
3281 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
3284 /* If this value won't fit into a 16 bit offset, then go
3285 find a macro that will generate the 32 bit offset
3287 if (!my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
3289 normalize_constant_expr (imm_expr
);
3290 if (imm_expr
->X_op
!= O_constant
3291 || (*oparg
== '0' && imm_expr
->X_add_number
!= 0)
3293 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
3294 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
3297 asarg
= expr_parse_end
;
3300 case 'p': /* PC-relative offset. */
3302 *imm_reloc
= BFD_RELOC_12_PCREL
;
3303 my_getExpression (imm_expr
, asarg
);
3304 asarg
= expr_parse_end
;
3307 case 'u': /* Upper 20 bits. */
3308 p
= percent_op_utype
;
3309 if (!my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
3311 if (imm_expr
->X_op
!= O_constant
)
3314 if (imm_expr
->X_add_number
< 0
3315 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
3316 as_bad (_("lui expression not in range 0..1048575"));
3318 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
3319 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
3321 asarg
= expr_parse_end
;
3324 case 'a': /* 20-bit PC-relative offset. */
3326 my_getExpression (imm_expr
, asarg
);
3327 asarg
= expr_parse_end
;
3328 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
3332 my_getExpression (imm_expr
, asarg
);
3333 asarg
= expr_parse_end
;
3334 if (strcmp (asarg
, "@plt") == 0)
3336 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
3343 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, asarg
)
3344 || imm_expr
->X_op
!= O_constant
3345 || imm_expr
->X_add_number
< 0
3346 || imm_expr
->X_add_number
>= 128
3347 || (imm_expr
->X_add_number
& 0x3) != 3)
3349 as_bad (_("bad value for opcode field, "
3350 "value must be 0...127 and "
3351 "lower 2 bits must be 0x3"));
3354 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
3355 imm_expr
->X_op
= O_absent
;
3356 asarg
= expr_parse_end
;
3360 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, asarg
)
3361 || imm_expr
->X_op
!= O_constant
3362 || imm_expr
->X_add_number
< 0
3363 || imm_expr
->X_add_number
>= 3)
3365 as_bad (_("bad value for opcode field, "
3366 "value must be 0...2"));
3369 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
3370 imm_expr
->X_op
= O_absent
;
3371 asarg
= expr_parse_end
;
3375 goto unknown_riscv_ip_operand
;
3383 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3384 || imm_expr
->X_op
!= O_constant
3385 || imm_expr
->X_add_number
< 0
3386 || imm_expr
->X_add_number
>= 128)
3388 as_bad (_("bad value for funct7 field, "
3389 "value must be 0...127"));
3392 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
3393 imm_expr
->X_op
= O_absent
;
3394 asarg
= expr_parse_end
;
3398 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3399 || imm_expr
->X_op
!= O_constant
3400 || imm_expr
->X_add_number
< 0
3401 || imm_expr
->X_add_number
>= 8)
3403 as_bad (_("bad value for funct3 field, "
3404 "value must be 0...7"));
3407 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
3408 imm_expr
->X_op
= O_absent
;
3409 asarg
= expr_parse_end
;
3413 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3414 || imm_expr
->X_op
!= O_constant
3415 || imm_expr
->X_add_number
< 0
3416 || imm_expr
->X_add_number
>= 4)
3418 as_bad (_("bad value for funct2 field, "
3419 "value must be 0...3"));
3422 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
3423 imm_expr
->X_op
= O_absent
;
3424 asarg
= expr_parse_end
;
3428 goto unknown_riscv_ip_operand
;
3432 case 'y': /* bs immediate */
3433 my_getExpression (imm_expr
, asarg
);
3434 check_absolute_expr (ip
, imm_expr
, FALSE
);
3435 if ((unsigned long)imm_expr
->X_add_number
> 3)
3436 as_bad(_("Improper bs immediate (%lu)"),
3437 (unsigned long)imm_expr
->X_add_number
);
3438 INSERT_OPERAND(BS
, *ip
, imm_expr
->X_add_number
);
3439 imm_expr
->X_op
= O_absent
;
3440 asarg
= expr_parse_end
;
3443 case 'Y': /* rnum immediate */
3444 my_getExpression (imm_expr
, asarg
);
3445 check_absolute_expr (ip
, imm_expr
, FALSE
);
3446 if ((unsigned long)imm_expr
->X_add_number
> 10)
3447 as_bad(_("Improper rnum immediate (%lu)"),
3448 (unsigned long)imm_expr
->X_add_number
);
3449 INSERT_OPERAND(RNUM
, *ip
, imm_expr
->X_add_number
);
3450 imm_expr
->X_op
= O_absent
;
3451 asarg
= expr_parse_end
;
3455 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3456 || imm_expr
->X_op
!= O_constant
3457 || imm_expr
->X_add_number
!= 0)
3459 asarg
= expr_parse_end
;
3460 imm_expr
->X_op
= O_absent
;
3463 case 'W': /* Various operands. */
3470 /* Prefetch offset for 'Zicbop' extension.
3471 pseudo S-type but lower 5-bits zero. */
3472 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
3474 my_getExpression (imm_expr
, asarg
);
3475 check_absolute_expr (ip
, imm_expr
, false);
3476 if (((unsigned) (imm_expr
->X_add_number
) & 0x1fU
)
3477 || imm_expr
->X_add_number
>= RISCV_IMM_REACH
/ 2
3478 || imm_expr
->X_add_number
< -RISCV_IMM_REACH
/ 2)
3479 as_bad (_ ("improper prefetch offset (%ld)"),
3480 (long) imm_expr
->X_add_number
);
3481 ip
->insn_opcode
|= ENCODE_STYPE_IMM (
3482 (unsigned) (imm_expr
->X_add_number
) & ~0x1fU
);
3483 imm_expr
->X_op
= O_absent
;
3484 asarg
= expr_parse_end
;
3487 goto unknown_riscv_ip_operand
;
3491 goto unknown_riscv_ip_operand
;
3495 case 'X': /* Integer immediate. */
3503 case 'l': /* Literal. */
3504 n
= strcspn (++oparg
, ",");
3505 if (strncmp (oparg
, asarg
, n
))
3506 as_bad (_("unexpected literal (%s)"), asarg
);
3510 case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
3513 case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */
3517 n
= strtol (oparg
+ 1, (char **)&oparg
, 10);
3519 goto unknown_riscv_ip_operand
;
3520 s
= strtol (oparg
+ 1, (char **)&oparg
, 10);
3523 my_getExpression (imm_expr
, asarg
);
3524 check_absolute_expr (ip
, imm_expr
, false);
3527 if (!VALIDATE_U_IMM (imm_expr
->X_add_number
, n
))
3528 as_bad (_("improper immediate value (%"PRIu64
")"),
3529 imm_expr
->X_add_number
);
3533 if (!VALIDATE_S_IMM (imm_expr
->X_add_number
, n
))
3534 as_bad (_("improper immediate value (%"PRIi64
")"),
3535 imm_expr
->X_add_number
);
3537 INSERT_IMM (n
, s
, *ip
, imm_expr
->X_add_number
);
3538 imm_expr
->X_op
= O_absent
;
3539 asarg
= expr_parse_end
;
3542 goto unknown_riscv_ip_operand
;
3548 unknown_riscv_ip_operand
:
3549 as_fatal (_("internal: unknown argument type `%s'"),
3555 insn_with_csr
= false;
3559 /* Restore the character we might have clobbered above. */
3561 *(asargStart
- 1) = save_c
;
3563 probing_insn_operands
= false;
3568 /* Similar to riscv_ip, but assembles an instruction according to the
3569 hardcode values of .insn directive. */
3572 riscv_ip_hardcode (char *str
,
3573 struct riscv_cl_insn
*ip
,
3574 expressionS
*imm_expr
,
3577 struct riscv_opcode
*insn
;
3578 insn_t values
[2] = {0, 0};
3579 unsigned int num
= 0;
3581 input_line_pointer
= str
;
3584 expression (imm_expr
);
3585 switch (imm_expr
->X_op
)
3588 values
[num
++] = (insn_t
) imm_expr
->X_add_number
;
3591 /* Extract lower 32-bits of a big number.
3592 Assume that generic_bignum_to_int32 work on such number. */
3593 values
[num
++] = (insn_t
) generic_bignum_to_int32 ();
3596 /* The first value isn't constant, so it should be
3597 .insn <type> <operands>. We have been parsed it
3601 return _("values must be constant");
3604 while (*input_line_pointer
++ == ',' && num
< 2 && imm_expr
->X_op
!= O_big
);
3606 input_line_pointer
--;
3607 if (*input_line_pointer
!= '\0')
3608 return _("unrecognized values");
3610 insn
= XNEW (struct riscv_opcode
);
3611 insn
->match
= values
[num
- 1];
3612 create_insn (ip
, insn
);
3613 unsigned int bytes
= riscv_insn_length (insn
->match
);
3615 if (num
== 2 && values
[0] != bytes
)
3616 return _("value conflicts with instruction length");
3618 if (imm_expr
->X_op
== O_big
)
3620 unsigned int llen
= 0;
3621 for (LITTLENUM_TYPE lval
= generic_bignum
[imm_expr
->X_add_number
- 1];
3623 lval
>>= BITS_PER_CHAR
;
3624 unsigned int repr_bytes
3625 = (imm_expr
->X_add_number
- 1) * CHARS_PER_LITTLENUM
+ llen
;
3626 if (bytes
< repr_bytes
)
3627 return _("value conflicts with instruction length");
3628 for (num
= 0; num
< imm_expr
->X_add_number
- 1; ++num
)
3629 number_to_chars_littleendian (
3630 ip
->insn_long_opcode
+ num
* CHARS_PER_LITTLENUM
,
3631 generic_bignum
[num
],
3632 CHARS_PER_LITTLENUM
);
3634 number_to_chars_littleendian (
3635 ip
->insn_long_opcode
+ num
* CHARS_PER_LITTLENUM
,
3636 generic_bignum
[num
],
3638 memset(ip
->insn_long_opcode
+ repr_bytes
, 0, bytes
- repr_bytes
);
3642 if (bytes
< sizeof(values
[0]) && values
[num
- 1] >> (8 * bytes
) != 0)
3643 return _("value conflicts with instruction length");
3649 md_assemble (char *str
)
3651 struct riscv_cl_insn insn
;
3652 expressionS imm_expr
;
3653 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3655 /* The architecture and privileged elf attributes should be set
3656 before assembling. */
3657 if (!start_assemble
)
3659 start_assemble
= true;
3661 riscv_set_abi_by_arch ();
3662 if (!riscv_set_default_priv_spec (NULL
))
3666 riscv_mapping_state (MAP_INSN
, 0, false/* fr_align_code */);
3668 const struct riscv_ip_error error
= riscv_ip (str
, &insn
, &imm_expr
,
3669 &imm_reloc
, op_hash
);
3673 if (error
.missing_ext
)
3674 as_bad ("%s `%s', extension `%s' required", error
.msg
,
3675 error
.statement
, error
.missing_ext
);
3677 as_bad ("%s `%s'", error
.msg
, error
.statement
);
3681 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3682 macro (&insn
, &imm_expr
, &imm_reloc
);
3684 append_insn (&insn
, &imm_expr
, imm_reloc
);
3688 md_atof (int type
, char *litP
, int *sizeP
)
3690 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
3694 md_number_to_chars (char *buf
, valueT val
, int n
)
3696 if (target_big_endian
)
3697 number_to_chars_bigendian (buf
, val
, n
);
3699 number_to_chars_littleendian (buf
, val
, n
);
3702 const char *md_shortopts
= "O::g::G:";
3706 OPTION_MARCH
= OPTION_MD_BASE
,
3713 OPTION_NO_ARCH_ATTR
,
3715 OPTION_NO_CSR_CHECK
,
3719 OPTION_LITTLE_ENDIAN
,
3723 struct option md_longopts
[] =
3725 {"march", required_argument
, NULL
, OPTION_MARCH
},
3726 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
3727 {"fpic", no_argument
, NULL
, OPTION_PIC
},
3728 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
3729 {"mabi", required_argument
, NULL
, OPTION_MABI
},
3730 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
3731 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
3732 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
3733 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
3734 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
3735 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
3736 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
3737 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
3738 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
3739 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
3741 {NULL
, no_argument
, NULL
, 0}
3743 size_t md_longopts_size
= sizeof (md_longopts
);
3746 md_parse_option (int c
, const char *arg
)
3751 default_arch_with_ext
= arg
;
3755 riscv_opts
.pic
= false;
3759 riscv_opts
.pic
= true;
3763 if (strcmp (arg
, "ilp32") == 0)
3764 riscv_set_abi (32, FLOAT_ABI_SOFT
, false);
3765 else if (strcmp (arg
, "ilp32e") == 0)
3766 riscv_set_abi (32, FLOAT_ABI_SOFT
, true);
3767 else if (strcmp (arg
, "ilp32f") == 0)
3768 riscv_set_abi (32, FLOAT_ABI_SINGLE
, false);
3769 else if (strcmp (arg
, "ilp32d") == 0)
3770 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, false);
3771 else if (strcmp (arg
, "ilp32q") == 0)
3772 riscv_set_abi (32, FLOAT_ABI_QUAD
, false);
3773 else if (strcmp (arg
, "lp64") == 0)
3774 riscv_set_abi (64, FLOAT_ABI_SOFT
, false);
3775 else if (strcmp (arg
, "lp64f") == 0)
3776 riscv_set_abi (64, FLOAT_ABI_SINGLE
, false);
3777 else if (strcmp (arg
, "lp64d") == 0)
3778 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, false);
3779 else if (strcmp (arg
, "lp64q") == 0)
3780 riscv_set_abi (64, FLOAT_ABI_QUAD
, false);
3783 explicit_mabi
= true;
3787 riscv_opts
.relax
= true;
3790 case OPTION_NO_RELAX
:
3791 riscv_opts
.relax
= false;
3794 case OPTION_ARCH_ATTR
:
3795 riscv_opts
.arch_attr
= true;
3798 case OPTION_NO_ARCH_ATTR
:
3799 riscv_opts
.arch_attr
= false;
3802 case OPTION_CSR_CHECK
:
3803 riscv_opts
.csr_check
= true;
3806 case OPTION_NO_CSR_CHECK
:
3807 riscv_opts
.csr_check
= false;
3810 case OPTION_MISA_SPEC
:
3811 return riscv_set_default_isa_spec (arg
);
3813 case OPTION_MPRIV_SPEC
:
3814 return riscv_set_default_priv_spec (arg
);
3816 case OPTION_BIG_ENDIAN
:
3817 target_big_endian
= 1;
3820 case OPTION_LITTLE_ENDIAN
:
3821 target_big_endian
= 0;
3832 riscv_after_parse_args (void)
3834 /* The --with-arch is optional for now, so we still need to set the xlen
3835 according to the default_arch, which is set by the --target. */
3838 if (strcmp (default_arch
, "riscv32") == 0)
3840 else if (strcmp (default_arch
, "riscv64") == 0)
3843 as_bad ("unknown default architecture `%s'", default_arch
);
3846 /* Set default specs. */
3847 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
3848 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
3849 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
3850 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
3852 riscv_set_arch (default_arch_with_ext
);
3854 /* If the CIE to be produced has not been overridden on the command line,
3855 then produce version 3 by default. This allows us to use the full
3856 range of registers in a .cfi_return_column directive. */
3857 if (flag_dwarf_cie_version
== -1)
3858 flag_dwarf_cie_version
= 3;
3861 bool riscv_parse_name (const char *name
, struct expressionS
*ep
,
3862 enum expr_mode mode
)
3867 if (!probing_insn_operands
)
3870 gas_assert (mode
== expr_normal
);
3872 regno
= reg_lookup_internal (name
, RCLASS_GPR
);
3873 if (regno
== (unsigned int)-1)
3876 if (symbol_find (name
) != NULL
)
3879 /* Create a symbol without adding it to the symbol table yet.
3880 Insertion will happen only once we commit to using the insn
3881 we're probing operands for. */
3882 for (sym
= deferred_sym_rootP
; sym
; sym
= symbol_next (sym
))
3883 if (strcmp (name
, S_GET_NAME (sym
)) == 0)
3887 for (sym
= orphan_sym_rootP
; sym
; sym
= symbol_next (sym
))
3888 if (strcmp (name
, S_GET_NAME (sym
)) == 0)
3890 symbol_remove (sym
, &orphan_sym_rootP
, &orphan_sym_lastP
);
3894 sym
= symbol_create (name
, undefined_section
,
3895 &zero_address_frag
, 0);
3897 symbol_append (sym
, deferred_sym_lastP
, &deferred_sym_rootP
,
3898 &deferred_sym_lastP
);
3901 ep
->X_op
= O_symbol
;
3902 ep
->X_add_symbol
= sym
;
3903 ep
->X_add_number
= 0;
3909 md_pcrel_from (fixS
*fixP
)
3911 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3914 /* Apply a fixup to the object file. */
3917 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
3919 unsigned int subtype
;
3920 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
3921 bool relaxable
= false;
3925 /* Remember value for tc_gen_reloc. */
3926 fixP
->fx_addnumber
= *valP
;
3928 switch (fixP
->fx_r_type
)
3930 case BFD_RELOC_RISCV_HI20
:
3931 case BFD_RELOC_RISCV_LO12_I
:
3932 case BFD_RELOC_RISCV_LO12_S
:
3933 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
3934 | bfd_getl32 (buf
), buf
);
3935 if (fixP
->fx_addsy
== NULL
)
3936 fixP
->fx_done
= true;
3940 case BFD_RELOC_RISCV_GOT_HI20
:
3941 case BFD_RELOC_RISCV_ADD8
:
3942 case BFD_RELOC_RISCV_ADD16
:
3943 case BFD_RELOC_RISCV_ADD32
:
3944 case BFD_RELOC_RISCV_ADD64
:
3945 case BFD_RELOC_RISCV_SUB6
:
3946 case BFD_RELOC_RISCV_SUB8
:
3947 case BFD_RELOC_RISCV_SUB16
:
3948 case BFD_RELOC_RISCV_SUB32
:
3949 case BFD_RELOC_RISCV_SUB64
:
3950 case BFD_RELOC_RISCV_RELAX
:
3953 case BFD_RELOC_RISCV_TPREL_HI20
:
3954 case BFD_RELOC_RISCV_TPREL_LO12_I
:
3955 case BFD_RELOC_RISCV_TPREL_LO12_S
:
3956 case BFD_RELOC_RISCV_TPREL_ADD
:
3960 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
3961 case BFD_RELOC_RISCV_TLS_GD_HI20
:
3962 case BFD_RELOC_RISCV_TLS_DTPREL32
:
3963 case BFD_RELOC_RISCV_TLS_DTPREL64
:
3964 if (fixP
->fx_addsy
!= NULL
)
3965 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3967 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3968 _("TLS relocation against a constant"));
3972 /* Use pc-relative relocation for FDE initial location.
3973 The symbol address in .eh_frame may be adjusted in
3974 _bfd_elf_discard_section_eh_frame, and the content of
3975 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
3976 Therefore, we cannot insert a relocation whose addend symbol is
3977 in .eh_frame. Othrewise, the value may be adjusted twice. */
3978 if (fixP
->fx_addsy
&& fixP
->fx_subsy
3979 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
3980 && strcmp (sub_segment
->name
, ".eh_frame") == 0
3981 && S_GET_VALUE (fixP
->fx_subsy
)
3982 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
3984 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
3985 fixP
->fx_subsy
= NULL
;
3992 case BFD_RELOC_RISCV_CFA
:
3993 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
3995 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3996 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
3997 fixP
->fx_next
->fx_subsy
= NULL
;
3998 fixP
->fx_next
->fx_offset
= 0;
3999 fixP
->fx_subsy
= NULL
;
4001 switch (fixP
->fx_r_type
)
4004 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
4005 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
4009 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
4010 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
4014 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
4015 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
4019 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
4020 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
4023 case BFD_RELOC_RISCV_CFA
:
4024 /* Load the byte to get the subtype. */
4025 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
4026 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
4029 case DW_CFA_advance_loc1
:
4030 fixP
->fx_where
= loc
+ 1;
4031 fixP
->fx_next
->fx_where
= loc
+ 1;
4032 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
4033 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
4036 case DW_CFA_advance_loc2
:
4038 fixP
->fx_next
->fx_size
= 2;
4039 fixP
->fx_where
= loc
+ 1;
4040 fixP
->fx_next
->fx_where
= loc
+ 1;
4041 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
4042 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
4045 case DW_CFA_advance_loc4
:
4047 fixP
->fx_next
->fx_size
= 4;
4048 fixP
->fx_where
= loc
;
4049 fixP
->fx_next
->fx_where
= loc
;
4050 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
4051 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
4055 if (subtype
< 0x80 && (subtype
& 0x40))
4057 /* DW_CFA_advance_loc */
4058 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
4059 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
4060 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
4061 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
4064 as_fatal (_("internal: bad CFA value #%d"), subtype
);
4070 /* This case is unreachable. */
4077 /* If we are deleting this reloc entry, we must fill in the
4078 value now. This can happen if we have a .word which is not
4079 resolved when it appears but is later defined. */
4080 if (fixP
->fx_addsy
== NULL
)
4082 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
4083 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
4088 case BFD_RELOC_RISCV_JMP
:
4091 /* Fill in a tentative value to improve objdump readability. */
4092 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
4093 bfd_vma delta
= target
- md_pcrel_from (fixP
);
4094 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_JTYPE_IMM (delta
), buf
);
4098 case BFD_RELOC_12_PCREL
:
4101 /* Fill in a tentative value to improve objdump readability. */
4102 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
4103 bfd_vma delta
= target
- md_pcrel_from (fixP
);
4104 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_BTYPE_IMM (delta
), buf
);
4108 case BFD_RELOC_RISCV_RVC_BRANCH
:
4111 /* Fill in a tentative value to improve objdump readability. */
4112 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
4113 bfd_vma delta
= target
- md_pcrel_from (fixP
);
4114 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CBTYPE_IMM (delta
), buf
);
4118 case BFD_RELOC_RISCV_RVC_JUMP
:
4121 /* Fill in a tentative value to improve objdump readability. */
4122 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
4123 bfd_vma delta
= target
- md_pcrel_from (fixP
);
4124 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CJTYPE_IMM (delta
), buf
);
4128 case BFD_RELOC_RISCV_CALL
:
4129 case BFD_RELOC_RISCV_CALL_PLT
:
4133 case BFD_RELOC_RISCV_PCREL_HI20
:
4134 case BFD_RELOC_RISCV_PCREL_LO12_S
:
4135 case BFD_RELOC_RISCV_PCREL_LO12_I
:
4136 relaxable
= riscv_opts
.relax
;
4139 case BFD_RELOC_RISCV_ALIGN
:
4143 /* We ignore generic BFD relocations we don't know about. */
4144 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
4145 as_fatal (_("internal: bad relocation #%d"), fixP
->fx_r_type
);
4148 if (fixP
->fx_subsy
!= NULL
)
4149 as_bad_subtract (fixP
);
4151 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
4152 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
4154 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
4155 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
4156 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
4157 fixP
->fx_next
->fx_size
= 0;
4161 /* Because the value of .cfi_remember_state may changed after relaxation,
4162 we insert a fix to relocate it again in link-time. */
4165 riscv_pre_output_hook (void)
4167 const frchainS
*frch
;
4170 /* Save the current segment info. */
4172 subsegT subseg
= now_subseg
;
4174 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
4175 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
4179 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
4181 if (frag
->fr_type
== rs_cfa
)
4184 expressionS
*symval
;
4186 symval
= symbol_get_value_expression (frag
->fr_symbol
);
4187 exp
.X_op
= O_subtract
;
4188 exp
.X_add_symbol
= symval
->X_add_symbol
;
4189 exp
.X_add_number
= 0;
4190 exp
.X_op_symbol
= symval
->X_op_symbol
;
4192 /* We must set the segment before creating a frag after all
4193 frag chains have been chained together. */
4194 subseg_set (s
, frch
->frch_subseg
);
4196 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
4197 BFD_RELOC_RISCV_CFA
);
4202 /* Restore the original segment info. */
4203 subseg_set (seg
, subseg
);
4206 /* Handle the .option pseudo-op. */
4209 s_riscv_option (int x ATTRIBUTE_UNUSED
)
4211 char *name
= input_line_pointer
, ch
;
4213 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4214 ++input_line_pointer
;
4215 ch
= *input_line_pointer
;
4216 *input_line_pointer
= '\0';
4218 if (strcmp (name
, "rvc") == 0)
4220 riscv_update_subset (&riscv_rps_as
, "+c");
4221 riscv_reset_subsets_list_arch_str ();
4222 riscv_set_rvc (true);
4224 else if (strcmp (name
, "norvc") == 0)
4226 riscv_update_subset (&riscv_rps_as
, "-c");
4227 riscv_reset_subsets_list_arch_str ();
4228 riscv_set_rvc (false);
4230 else if (strcmp (name
, "pic") == 0)
4231 riscv_opts
.pic
= true;
4232 else if (strcmp (name
, "nopic") == 0)
4233 riscv_opts
.pic
= false;
4234 else if (strcmp (name
, "relax") == 0)
4235 riscv_opts
.relax
= true;
4236 else if (strcmp (name
, "norelax") == 0)
4237 riscv_opts
.relax
= false;
4238 else if (strcmp (name
, "csr-check") == 0)
4239 riscv_opts
.csr_check
= true;
4240 else if (strcmp (name
, "no-csr-check") == 0)
4241 riscv_opts
.csr_check
= false;
4242 else if (strncmp (name
, "arch,", 5) == 0)
4245 if (ISSPACE (*name
) && *name
!= '\0')
4247 riscv_update_subset (&riscv_rps_as
, name
);
4248 riscv_reset_subsets_list_arch_str ();
4250 riscv_set_rvc (false);
4251 if (riscv_subset_supports (&riscv_rps_as
, "c"))
4252 riscv_set_rvc (true);
4254 if (riscv_subset_supports (&riscv_rps_as
, "ztso"))
4257 else if (strcmp (name
, "push") == 0)
4259 struct riscv_option_stack
*s
;
4261 s
= XNEW (struct riscv_option_stack
);
4262 s
->next
= riscv_opts_stack
;
4263 s
->options
= riscv_opts
;
4264 s
->subset_list
= riscv_rps_as
.subset_list
;
4265 riscv_opts_stack
= s
;
4266 riscv_rps_as
.subset_list
= riscv_copy_subset_list (s
->subset_list
);
4268 else if (strcmp (name
, "pop") == 0)
4270 struct riscv_option_stack
*s
;
4272 s
= riscv_opts_stack
;
4274 as_bad (_(".option pop with no .option push"));
4277 riscv_subset_list_t
*release_subsets
= riscv_rps_as
.subset_list
;
4278 riscv_opts_stack
= s
->next
;
4279 riscv_opts
= s
->options
;
4280 riscv_rps_as
.subset_list
= s
->subset_list
;
4281 riscv_release_subset_list (release_subsets
);
4287 as_warn (_("unrecognized .option directive: %s"), name
);
4289 *input_line_pointer
= ch
;
4290 demand_empty_rest_of_line ();
4293 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
4294 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
4295 use in DWARF debug information. */
4298 s_dtprel (int bytes
)
4305 if (ex
.X_op
!= O_symbol
)
4307 as_bad (_("unsupported use of %s"), (bytes
== 8
4310 ignore_rest_of_line ();
4313 p
= frag_more (bytes
);
4314 md_number_to_chars (p
, 0, bytes
);
4315 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, false,
4317 ? BFD_RELOC_RISCV_TLS_DTPREL64
4318 : BFD_RELOC_RISCV_TLS_DTPREL32
));
4320 demand_empty_rest_of_line ();
4323 /* Handle the .bss pseudo-op. */
4326 s_bss (int ignore ATTRIBUTE_UNUSED
)
4328 subseg_set (bss_section
, 0);
4329 demand_empty_rest_of_line ();
4333 riscv_make_nops (char *buf
, bfd_vma bytes
)
4337 /* RISC-V instructions cannot begin or end on odd addresses, so this case
4338 means we are not within a valid instruction sequence. It is thus safe
4339 to use a zero byte, even though that is not a valid instruction. */
4343 /* Use at most one 2-byte NOP. */
4344 if ((bytes
- i
) % 4 == 2)
4346 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
4350 /* Fill the remainder with 4-byte NOPs. */
4351 for ( ; i
< bytes
; i
+= 4)
4352 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
4355 /* Called from md_do_align. Used to create an alignment frag in a
4356 code section by emitting a worst-case NOP sequence that the linker
4357 will later relax to the correct number of NOPs. We can't compute
4358 the correct alignment now because of other linker relaxations. */
4361 riscv_frag_align_code (int n
)
4363 bfd_vma bytes
= (bfd_vma
) 1 << n
;
4364 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
4365 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
4369 /* If we are moving to a smaller alignment than the instruction size, then no
4370 alignment is required. */
4371 if (bytes
<= insn_alignment
)
4374 /* When not relaxing, riscv_handle_align handles code alignment. */
4375 if (!riscv_opts
.relax
)
4378 /* Maybe we should use frag_var to create a new rs_align_code fragment,
4379 rather than just use frag_more to handle an alignment here? So that we
4380 don't need to call riscv_mapping_state again later, and then only need
4381 to check frag->fr_type to see if it is frag_align_code. */
4382 nops
= frag_more (worst_case_bytes
);
4384 ex
.X_op
= O_constant
;
4385 ex
.X_add_number
= worst_case_bytes
;
4387 riscv_make_nops (nops
, worst_case_bytes
);
4389 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
4390 &ex
, false, BFD_RELOC_RISCV_ALIGN
);
4392 riscv_mapping_state (MAP_INSN
, worst_case_bytes
, true/* fr_align_code */);
4394 /* We need to start a new frag after the alignment which may be removed by
4395 the linker, to prevent the assembler from computing static offsets.
4396 This is necessary to get correct EH info. */
4397 frag_wane (frag_now
);
4403 /* Implement HANDLE_ALIGN. */
4406 riscv_handle_align (fragS
*fragP
)
4408 switch (fragP
->fr_type
)
4411 /* When relaxing, riscv_frag_align_code handles code alignment. */
4412 if (!riscv_opts
.relax
)
4414 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
4415 - fragP
->fr_address
- fragP
->fr_fix
);
4416 /* We have 4 byte uncompressed nops. */
4417 bfd_signed_vma size
= 4;
4418 bfd_signed_vma excess
= bytes
% size
;
4419 bfd_boolean odd_padding
= (excess
% 2 == 1);
4420 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
4425 /* Insert zeros or compressed nops to get 4 byte alignment. */
4429 riscv_add_odd_padding_symbol (fragP
);
4430 riscv_make_nops (p
, excess
);
4431 fragP
->fr_fix
+= excess
;
4435 /* The frag will be changed to `rs_fill` later. The function
4436 `write_contents` will try to fill the remaining spaces
4437 according to the patterns we give. In this case, we give
4438 a 4 byte uncompressed nop as the pattern, and set the size
4439 of the pattern into `fr_var`. The nop will be output to the
4440 file `fr_offset` times. However, `fr_offset` could be zero
4441 if we don't need to pad the boundary finally. */
4442 riscv_make_nops (p
, size
);
4443 fragP
->fr_var
= size
;
4452 /* This usually called from frag_var. */
4455 riscv_init_frag (fragS
* fragP
, int max_chars
)
4457 /* Do not add mapping symbol to debug sections. */
4458 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
4461 switch (fragP
->fr_type
)
4466 riscv_mapping_state (MAP_DATA
, max_chars
, false/* fr_align_code */);
4469 riscv_mapping_state (MAP_INSN
, max_chars
, true/* fr_align_code */);
4477 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
4479 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, false));
4482 /* Translate internal representation of relocation info to BFD target
4486 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
4488 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
4490 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4491 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4492 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4493 reloc
->addend
= fixp
->fx_addnumber
;
4495 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
4496 if (reloc
->howto
== NULL
)
4498 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
4499 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
4501 /* We don't have R_RISCV_8/16, but for this special case,
4502 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
4506 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4507 _("cannot represent %s relocation in object file"),
4508 bfd_get_reloc_code_name (fixp
->fx_r_type
));
4516 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
4518 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
4520 offsetT old_var
= fragp
->fr_var
;
4521 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, true);
4522 return fragp
->fr_var
- old_var
;
4528 /* Expand far branches to multi-instruction sequences. */
4531 md_convert_frag_branch (fragS
*fragp
)
4539 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
4541 exp
.X_op
= O_symbol
;
4542 exp
.X_add_symbol
= fragp
->fr_symbol
;
4543 exp
.X_add_number
= fragp
->fr_offset
;
4545 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
4547 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
4549 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
4553 /* Expand the RVC branch into a RISC-V one. */
4554 insn
= bfd_getl16 (buf
);
4555 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
4556 if ((insn
& MASK_C_J
) == MATCH_C_J
)
4558 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
4559 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
4560 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
4561 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
4562 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
4563 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
4566 bfd_putl32 (insn
, buf
);
4570 /* Invert the branch condition. Branch over the jump. */
4571 insn
= bfd_getl16 (buf
);
4572 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
4573 insn
|= ENCODE_CBTYPE_IMM (6);
4574 bfd_putl16 (insn
, buf
);
4579 /* Just keep the RVC branch. */
4580 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
4581 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
4582 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4583 2, &exp
, false, reloc
);
4592 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
4595 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
4597 /* Invert the branch condition. Branch over the jump. */
4598 insn
= bfd_getl32 (buf
);
4599 insn
^= MATCH_BEQ
^ MATCH_BNE
;
4600 insn
|= ENCODE_BTYPE_IMM (8);
4601 bfd_putl32 (insn
, buf
);
4605 /* Jump to the target. */
4606 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4607 4, &exp
, false, BFD_RELOC_RISCV_JMP
);
4608 bfd_putl32 (MATCH_JAL
, buf
);
4613 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
4614 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
4615 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4616 4, &exp
, false, reloc
);
4625 fixp
->fx_file
= fragp
->fr_file
;
4626 fixp
->fx_line
= fragp
->fr_line
;
4628 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
4629 + fragp
->fr_fix
+ fragp
->fr_var
);
4631 fragp
->fr_fix
+= fragp
->fr_var
;
4634 /* Relax a machine dependent frag. This returns the amount by which
4635 the current size of the frag should change. */
4638 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
4641 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
4642 md_convert_frag_branch (fragp
);
4646 md_show_usage (FILE *stream
)
4648 fprintf (stream
, _("\
4650 -fpic or -fPIC generate position-independent code\n\
4651 -fno-pic don't generate position-independent code (default)\n\
4652 -march=ISA set the RISC-V architecture\n\
4653 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
4654 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11, 1.12)\n\
4655 -mabi=ABI set the RISC-V ABI\n\
4656 -mrelax enable relax (default)\n\
4657 -mno-relax disable relax\n\
4658 -march-attr generate RISC-V arch attribute\n\
4659 -mno-arch-attr don't generate RISC-V arch attribute\n\
4660 -mcsr-check enable the csr ISA and privilege spec version checks\n\
4661 -mno-csr-check disable the csr ISA and privilege spec version checks (default)\n\
4662 -mbig-endian assemble for big-endian\n\
4663 -mlittle-endian assemble for little-endian\n\
4667 /* Standard calling conventions leave the CFA at SP on entry. */
4670 riscv_cfi_frame_initial_instructions (void)
4672 cfi_add_CFA_def_cfa_register (X_SP
);
4676 tc_riscv_regname_to_dw2regnum (char *regname
)
4680 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
4683 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
4686 if ((reg
= reg_lookup_internal (regname
, RCLASS_VECR
)) >= 0)
4689 /* CSRs are numbered 4096 -> 8191. */
4690 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
4693 as_bad (_("unknown register `%s'"), regname
);
4698 riscv_elf_final_processing (void)
4700 riscv_set_abi_by_arch ();
4701 riscv_release_subset_list (riscv_rps_as
.subset_list
);
4702 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
4705 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
4706 since these directives break relaxation when used with symbol deltas. */
4709 s_riscv_leb128 (int sign
)
4712 char *save_in
= input_line_pointer
;
4715 if (exp
.X_op
!= O_constant
)
4716 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
4717 demand_empty_rest_of_line ();
4719 input_line_pointer
= save_in
;
4720 return s_leb128 (sign
);
4723 /* Parse the .insn directive. There are three formats,
4724 Format 1: .insn <type> <operand1>, <operand2>, ...
4725 Format 2: .insn <length>, <value>
4726 Format 3: .insn <value>. */
4729 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
4731 char *str
= input_line_pointer
;
4732 struct riscv_cl_insn insn
;
4733 expressionS imm_expr
;
4734 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
4737 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4738 ++input_line_pointer
;
4740 save_c
= *input_line_pointer
;
4741 *input_line_pointer
= '\0';
4743 riscv_mapping_state (MAP_INSN
, 0, false/* fr_align_code */);
4745 struct riscv_ip_error error
= riscv_ip (str
, &insn
, &imm_expr
,
4746 &imm_reloc
, insn_type_hash
);
4749 char *save_in
= input_line_pointer
;
4750 error
.msg
= riscv_ip_hardcode (str
, &insn
, &imm_expr
, error
.msg
);
4751 input_line_pointer
= save_in
;
4756 if (error
.missing_ext
)
4757 as_bad ("%s `%s', extension `%s' required", error
.msg
, error
.statement
,
4760 as_bad ("%s `%s'", error
.msg
, error
.statement
);
4764 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
4765 append_insn (&insn
, &imm_expr
, imm_reloc
);
4768 *input_line_pointer
= save_c
;
4769 demand_empty_rest_of_line ();
4772 /* Update architecture and privileged elf attributes. If we don't set
4773 them, then try to output the default ones. */
4776 riscv_write_out_attrs (void)
4778 const char *arch_str
, *priv_str
, *p
;
4779 /* versions[0]: major version.
4780 versions[1]: minor version.
4781 versions[2]: revision version. */
4782 unsigned versions
[3] = {0}, number
= 0;
4785 /* Re-write architecture elf attribute. */
4786 arch_str
= riscv_rps_as
.subset_list
->arch_str
;
4787 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
4789 /* For the file without any instruction, we don't set the default_priv_spec
4790 according to the privileged elf attributes since the md_assemble isn't
4793 && !riscv_set_default_priv_spec (NULL
))
4796 /* If we already have set privileged elf attributes, then no need to do
4797 anything. Otherwise, don't generate or update them when no CSR and
4798 privileged instructions are used. */
4799 if (!explicit_priv_attr
)
4802 RISCV_GET_PRIV_SPEC_NAME (priv_str
, default_priv_spec
);
4804 for (i
= 0; *p
; ++p
)
4806 if (*p
== '.' && i
< 3)
4808 versions
[i
++] = number
;
4811 else if (ISDIGIT (*p
))
4812 number
= (number
* 10) + (*p
- '0');
4815 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str
);
4819 versions
[i
] = number
;
4821 /* Re-write privileged elf attributes. */
4822 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
4823 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
4824 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
4827 /* Add the default contents for the .riscv.attributes section. */
4830 riscv_set_public_attributes (void)
4832 if (riscv_opts
.arch_attr
|| explicit_attr
)
4833 riscv_write_out_attrs ();
4836 /* Called after all assembly has been done. */
4839 riscv_md_finish (void)
4841 riscv_set_public_attributes ();
4844 /* Adjust the symbol table. */
4847 riscv_adjust_symtab (void)
4849 bfd_map_over_sections (stdoutput
, riscv_check_mapping_symbols
, (char *) 0);
4850 elf_adjust_symtab ();
4853 /* Given a symbolic attribute NAME, return the proper integer value.
4854 Returns -1 if the attribute is not known. */
4857 riscv_convert_symbolic_attribute (const char *name
)
4866 /* When you modify this table you should
4867 also modify the list in doc/c-riscv.texi. */
4868 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
4872 T(priv_spec_revision
),
4873 T(unaligned_access
),
4882 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
4883 if (strcmp (name
, attribute_table
[i
].name
) == 0)
4884 return attribute_table
[i
].tag
;
4889 /* Parse a .attribute directive. */
4892 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
4894 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4896 obj_attribute
*attr
;
4898 explicit_attr
= true;
4901 case Tag_RISCV_arch
:
4903 attr
= elf_known_obj_attributes_proc (stdoutput
);
4904 if (!start_assemble
)
4905 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
4907 as_fatal (_("architecture elf attributes must set before "
4908 "any instructions"));
4910 if (old_xlen
!= xlen
)
4912 /* We must re-init bfd again if xlen is changed. */
4913 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
4914 bfd_find_target (riscv_target_format (), stdoutput
);
4916 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
4917 as_warn (_("could not set architecture and machine"));
4921 case Tag_RISCV_priv_spec
:
4922 case Tag_RISCV_priv_spec_minor
:
4923 case Tag_RISCV_priv_spec_revision
:
4925 as_fatal (_("privileged elf attributes must set before "
4926 "any instructions"));
4934 /* Mark symbol that it follows a variant CC convention. */
4937 s_variant_cc (int ignored ATTRIBUTE_UNUSED
)
4943 elf_symbol_type
*elfsym
;
4945 c
= get_symbol_name (&name
);
4947 as_bad (_("missing symbol name for .variant_cc directive"));
4948 sym
= symbol_find_or_make (name
);
4949 restore_line_pointer (c
);
4950 demand_empty_rest_of_line ();
4952 bfdsym
= symbol_get_bfdsym (sym
);
4953 elfsym
= elf_symbol_from (bfdsym
);
4954 gas_assert (elfsym
);
4955 elfsym
->internal_elf_sym
.st_other
|= STO_RISCV_VARIANT_CC
;
4958 /* Same as elf_copy_symbol_attributes, but without copying st_other.
4959 This is needed so RISC-V specific st_other values can be independently
4960 specified for an IFUNC resolver (that is called by the dynamic linker)
4961 and the symbol it resolves (aliased to the resolver). In particular,
4962 if a function symbol has special st_other value set via directives,
4963 then attaching an IFUNC resolver to that symbol should not override
4964 the st_other setting. Requiring the directive on the IFUNC resolver
4965 symbol would be unexpected and problematic in C code, where the two
4966 symbols appear as two independent function declarations. */
4969 riscv_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
4971 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
4972 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
4973 /* If size is unset, copy size from src. Because we don't track whether
4974 .size has been used, we can't differentiate .size dest, 0 from the case
4975 where dest's size is unset. */
4976 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
4980 destelf
->size
= XNEW (expressionS
);
4981 *destelf
->size
= *srcelf
->size
;
4983 S_SET_SIZE (dest
, S_GET_SIZE (src
));
4987 /* RISC-V pseudo-ops table. */
4988 static const pseudo_typeS riscv_pseudo_table
[] =
4990 {"option", s_riscv_option
, 0},
4994 {"dtprelword", s_dtprel
, 4},
4995 {"dtpreldword", s_dtprel
, 8},
4997 {"uleb128", s_riscv_leb128
, 0},
4998 {"sleb128", s_riscv_leb128
, 1},
4999 {"insn", s_riscv_insn
, 0},
5000 {"attribute", s_riscv_attribute
, 0},
5001 {"variant_cc", s_variant_cc
, 0},
5002 {"float16", float_cons
, 'h'},
5008 riscv_pop_insert (void)
5010 extern void pop_insert (const pseudo_typeS
*);
5012 pop_insert (riscv_pseudo_table
);