1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 static const char default_arch
[] = DEFAULT_ARCH
;
64 static unsigned xlen
= 0; /* width of an x-register */
65 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
66 static bfd_boolean rve_abi
= FALSE
;
68 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
69 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
71 static unsigned elf_flags
= 0;
73 /* This is the set of options which the .option pseudo-op may modify. */
75 struct riscv_set_options
77 int pic
; /* Generate position-independent code. */
78 int rvc
; /* Generate RVC code. */
79 int rve
; /* Generate RVE code. */
80 int relax
; /* Emit relocs the linker is allowed to relax. */
83 static struct riscv_set_options riscv_opts
=
92 riscv_set_rvc (bfd_boolean rvc_value
)
95 elf_flags
|= EF_RISCV_RVC
;
97 riscv_opts
.rvc
= rvc_value
;
101 riscv_set_rve (bfd_boolean rve_value
)
103 riscv_opts
.rve
= rve_value
;
106 static riscv_subset_list_t riscv_subsets
;
109 riscv_subset_supports (const char *feature
)
111 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
114 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
118 riscv_multi_subset_supports (const char *features
[])
121 bfd_boolean supported
= TRUE
;
123 for (;features
[i
]; ++i
)
124 supported
= supported
&& riscv_subset_supports (features
[i
]);
129 /* Set which ISA and extensions are available. */
132 riscv_set_arch (const char *s
)
134 riscv_parse_subset_t rps
;
135 rps
.subset_list
= &riscv_subsets
;
136 rps
.error_handler
= as_fatal
;
139 riscv_release_subset_list (&riscv_subsets
);
140 riscv_parse_subset (&rps
, s
);
143 /* Handle of the OPCODE hash table. */
144 static struct hash_control
*op_hash
= NULL
;
146 /* Handle of the type of .insn hash table. */
147 static struct hash_control
*insn_type_hash
= NULL
;
149 /* This array holds the chars that always start a comment. If the
150 pre-processor is disabled, these aren't very useful */
151 const char comment_chars
[] = "#";
153 /* This array holds the chars that only start a comment at the beginning of
154 a line. If the line seems to have the form '# 123 filename'
155 .line and .file directives will appear in the pre-processed output */
156 /* Note that input_file.c hand checks for '#' at the beginning of the
157 first line of the input file. This is because the compiler outputs
158 #NO_APP at the beginning of its output. */
159 /* Also note that C style comments are always supported. */
160 const char line_comment_chars
[] = "#";
162 /* This array holds machine specific line separator characters. */
163 const char line_separator_chars
[] = ";";
165 /* Chars that can be used to separate mant from exp in floating point nums */
166 const char EXP_CHARS
[] = "eE";
168 /* Chars that mean this number is a floating point constant */
171 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
173 /* Macros for encoding relaxation state for RVC branches and far jumps. */
174 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
177 | ((uncond) ? 1 : 0) \
180 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
181 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
182 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
183 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
185 /* Is the given value a sign-extended 32-bit value? */
186 #define IS_SEXT_32BIT_NUM(x) \
187 (((x) &~ (offsetT) 0x7fffffff) == 0 \
188 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
190 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
191 #define IS_ZEXT_32BIT_NUM(x) \
192 (((x) &~ (offsetT) 0xffffffff) == 0 \
193 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
195 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
196 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
197 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
198 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
200 /* Determine if an instruction matches an opcode. */
201 #define OPCODE_MATCHES(OPCODE, OP) \
202 (((OPCODE) & MASK_##OP) == MATCH_##OP)
204 static char *expr_end
;
206 /* The default target format to use. */
209 riscv_target_format (void)
211 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
214 /* Return the length of instruction INSN. */
216 static inline unsigned int
217 insn_length (const struct riscv_cl_insn
*insn
)
219 return riscv_insn_length (insn
->insn_opcode
);
222 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
225 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
228 insn
->insn_opcode
= mo
->match
;
234 /* Install INSN at the location specified by its "frag" and "where" fields. */
237 install_insn (const struct riscv_cl_insn
*insn
)
239 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
240 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
243 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
244 and install the opcode in the new location. */
247 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
251 if (insn
->fixp
!= NULL
)
253 insn
->fixp
->fx_frag
= frag
;
254 insn
->fixp
->fx_where
= where
;
259 /* Add INSN to the end of the output. */
262 add_fixed_insn (struct riscv_cl_insn
*insn
)
264 char *f
= frag_more (insn_length (insn
));
265 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
269 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
270 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
272 frag_grow (max_chars
);
273 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
274 frag_var (rs_machine_dependent
, max_chars
, var
,
275 subtype
, symbol
, offset
, NULL
);
278 /* Compute the length of a branch sequence, and adjust the stored length
279 accordingly. If FRAGP is NULL, the worst-case length is returned. */
282 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
284 int jump
, rvc
, length
= 8;
289 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
290 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
291 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
293 /* Assume jumps are in range; the linker will catch any that aren't. */
294 length
= jump
? 4 : 8;
296 if (fragp
->fr_symbol
!= NULL
297 && S_IS_DEFINED (fragp
->fr_symbol
)
298 && !S_IS_WEAK (fragp
->fr_symbol
)
299 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
301 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
302 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
303 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
305 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
307 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
309 else if (!jump
&& rvc
)
314 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
319 /* Information about an opcode name, mnemonics and its value. */
326 /* List for all supported opcode name. */
327 static const struct opcode_name_t opcode_name_list
[] =
372 /* Hash table for lookup opcode name. */
373 static struct hash_control
*opcode_names_hash
= NULL
;
375 /* Initialization for hash table of opcode name. */
377 init_opcode_names_hash (void)
380 const struct opcode_name_t
*opcode
;
382 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
384 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
387 as_fatal (_("internal error: can't hash `%s': %s"),
388 opcode
->name
, retval
);
392 /* Find `s` is a valid opcode name or not,
393 return the opcode name info if found. */
394 static const struct opcode_name_t
*
395 opcode_name_lookup (char **s
)
399 struct opcode_name_t
*o
;
401 /* Find end of name. */
403 if (is_name_beginner (*e
))
405 while (is_part_of_name (*e
))
408 /* Terminate name. */
412 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
414 /* Advance to next token if one was recognized. */
438 static struct hash_control
*reg_names_hash
= NULL
;
440 #define ENCODE_REG_HASH(cls, n) \
441 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
442 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
443 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
446 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
448 void *hash
= ENCODE_REG_HASH (class, n
);
449 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
452 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
456 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
460 for (i
= 0; i
< n
; i
++)
461 hash_reg_name (class, names
[i
], i
);
465 reg_lookup_internal (const char *s
, enum reg_class
class)
467 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
469 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
472 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
475 return DECODE_REG_NUM (r
);
479 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
485 /* Find end of name. */
487 if (is_name_beginner (*e
))
489 while (is_part_of_name (*e
))
492 /* Terminate name. */
496 /* Look for the register. Advance to next token if one was recognized. */
497 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
507 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
509 const char *p
= strchr (*s
, ',');
510 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
515 for (i
= 0; i
< size
; i
++)
516 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
526 /* For consistency checking, verify that all bits are specified either
527 by the match/mask part of the instruction definition, or by the
530 `length` could be 0, 4 or 8, 0 for auto detection. */
532 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
534 const char *p
= opc
->args
;
536 insn_t used_bits
= opc
->mask
;
538 insn_t required_bits
;
541 insn_width
= 8 * riscv_insn_length (opc
->match
);
543 insn_width
= 8 * length
;
545 required_bits
= ~0ULL >> (64 - insn_width
);
547 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
549 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
550 opc
->name
, opc
->args
);
554 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
561 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
562 case 'c': break; /* RS1, constrained to equal sp */
563 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
564 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
565 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
566 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
567 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
568 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
569 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
570 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
571 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
572 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
573 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
574 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
575 case 'w': break; /* RS1S, constrained to equal RD */
576 case 'x': break; /* RS2S, constrained to equal RD */
577 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
578 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
579 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
580 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
581 case 'U': break; /* RS1, constrained to equal RD */
582 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
583 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
584 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
585 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
586 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
587 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
588 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
589 case 'F': /* funct */
592 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
593 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
594 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
595 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
597 as_bad (_("internal: bad RISC-V opcode"
598 " (unknown operand type `CF%c'): %s %s"),
599 c
, opc
->name
, opc
->args
);
604 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
605 c
, opc
->name
, opc
->args
);
612 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
613 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
615 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
616 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
617 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
619 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
620 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
621 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
622 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
623 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
624 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
625 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
626 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
627 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
628 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
629 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
631 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
632 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
633 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
634 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
635 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
641 case 'F': /* funct */
644 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
645 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
646 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
648 as_bad (_("internal: bad RISC-V opcode"
649 " (unknown operand type `F%c'): %s %s"),
650 c
, opc
->name
, opc
->args
);
654 case 'O': /* opcode */
657 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
658 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
660 as_bad (_("internal: bad RISC-V opcode"
661 " (unknown operand type `F%c'): %s %s"),
662 c
, opc
->name
, opc
->args
);
667 as_bad (_("internal: bad RISC-V opcode "
668 "(unknown operand type `%c'): %s %s"),
669 c
, opc
->name
, opc
->args
);
673 if (used_bits
!= required_bits
)
675 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
676 ~(unsigned long)(used_bits
& required_bits
),
677 opc
->name
, opc
->args
);
683 struct percent_op_match
686 bfd_reloc_code_real_type reloc
;
689 /* Common hash table initialization function for
690 instruction and .insn directive. */
691 static struct hash_control
*
692 init_opcode_hash (const struct riscv_opcode
*opcodes
,
693 bfd_boolean insn_directive_p
)
697 struct hash_control
*hash
= hash_new ();
698 while (opcodes
[i
].name
)
700 const char *name
= opcodes
[i
].name
;
701 const char *hash_error
=
702 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
706 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
707 opcodes
[i
].name
, hash_error
);
708 /* Probably a memory allocation problem? Give up now. */
709 as_fatal (_("Broken assembler. No assembly attempted."));
714 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
716 if (insn_directive_p
)
717 length
= ((name
[0] == 'c') ? 2 : 4);
719 length
= 0; /* Let assembler determine the length. */
720 if (!validate_riscv_insn (&opcodes
[i
], length
))
721 as_fatal (_("Broken assembler. No assembly attempted."));
724 gas_assert (!insn_directive_p
);
727 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
733 /* This function is called once, at assembler startup time. It should set up
734 all the tables, etc. that the MD part of the assembler will need. */
739 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
741 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
742 as_warn (_("Could not set architecture and machine"));
744 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
745 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
747 reg_names_hash
= hash_new ();
748 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
749 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
750 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
751 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
753 /* Add "fp" as an alias for "s0". */
754 hash_reg_name (RCLASS_GPR
, "fp", 8);
756 opcode_names_hash
= hash_new ();
757 init_opcode_names_hash ();
759 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
760 #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
761 #include "opcode/riscv-opc.h"
764 /* Set the default alignment for the text section. */
765 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
769 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
776 case BFD_RELOC_RISCV_HI20
:
777 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
779 case BFD_RELOC_RISCV_LO12_S
:
780 return ENCODE_STYPE_IMM (value
);
782 case BFD_RELOC_RISCV_LO12_I
:
783 return ENCODE_ITYPE_IMM (value
);
790 /* Output an instruction. IP is the instruction information.
791 ADDRESS_EXPR is an operand of the instruction to be used with
795 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
796 bfd_reloc_code_real_type reloc_type
)
798 dwarf2_emit_insn (0);
800 if (reloc_type
!= BFD_RELOC_UNUSED
)
802 reloc_howto_type
*howto
;
804 gas_assert (address_expr
);
805 if (reloc_type
== BFD_RELOC_12_PCREL
806 || reloc_type
== BFD_RELOC_RISCV_JMP
)
808 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
809 int best_case
= riscv_insn_length (ip
->insn_opcode
);
810 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
811 add_relaxed_insn (ip
, worst_case
, best_case
,
812 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
813 address_expr
->X_add_symbol
,
814 address_expr
->X_add_number
);
819 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
821 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
823 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
824 bfd_get_reloc_size (howto
),
825 address_expr
, FALSE
, reloc_type
);
827 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
834 /* We need to start a new frag after any instruction that can be
835 optimized away or compressed by the linker during relaxation, to prevent
836 the assembler from computing static offsets across such an instruction.
837 This is necessary to get correct EH info. */
838 if (reloc_type
== BFD_RELOC_RISCV_CALL
839 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
840 || reloc_type
== BFD_RELOC_RISCV_HI20
841 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
842 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
843 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
845 frag_wane (frag_now
);
850 /* Build an instruction created by a macro expansion. This is passed
851 a pointer to the count of instructions created so far, an
852 expression, the name of the instruction to build, an operand format
853 string, and corresponding arguments. */
856 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
858 const struct riscv_opcode
*mo
;
859 struct riscv_cl_insn insn
;
860 bfd_reloc_code_real_type r
;
863 va_start (args
, fmt
);
865 r
= BFD_RELOC_UNUSED
;
866 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
869 /* Find a non-RVC variant of the instruction. append_insn will compress
871 while (riscv_insn_length (mo
->match
) < 4)
873 gas_assert (strcmp (name
, mo
->name
) == 0);
875 create_insn (&insn
, mo
);
881 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
885 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
889 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
893 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
899 gas_assert (ep
!= NULL
);
900 r
= va_arg (args
, int);
908 as_fatal (_("internal error: invalid macro"));
913 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
915 append_insn (&insn
, ep
, r
);
918 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
921 normalize_constant_expr (expressionS
*ex
)
925 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
926 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
927 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
931 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
932 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
935 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
936 bfd_boolean maybe_csr
)
938 if (ex
->X_op
== O_big
)
939 as_bad (_("unsupported large constant"));
940 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
941 as_bad (_("unknown CSR `%s'"),
942 S_GET_NAME (ex
->X_add_symbol
));
943 else if (ex
->X_op
!= O_constant
)
944 as_bad (_("Instruction %s requires absolute expression"),
946 normalize_constant_expr (ex
);
950 make_internal_label (void)
952 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
953 (valueT
) frag_now_fix (), frag_now
);
956 /* Load an entry from the GOT. */
958 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
959 const char *lo_insn
, const char *lo_pattern
,
960 bfd_reloc_code_real_type hi_reloc
,
961 bfd_reloc_code_real_type lo_reloc
)
965 ep2
.X_add_symbol
= make_internal_label ();
966 ep2
.X_add_number
= 0;
968 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
969 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
973 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
974 bfd_reloc_code_real_type hi_reloc
,
975 bfd_reloc_code_real_type lo_reloc
)
977 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
981 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
982 bfd_reloc_code_real_type hi_reloc
,
983 bfd_reloc_code_real_type lo_reloc
)
985 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
988 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
990 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
991 bfd_reloc_code_real_type reloc
)
993 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
994 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
997 /* Load an integer constant into a register. */
1000 load_const (int reg
, expressionS
*ep
)
1002 int shift
= RISCV_IMM_BITS
;
1003 expressionS upper
= *ep
, lower
= *ep
;
1004 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
1005 upper
.X_add_number
-= lower
.X_add_number
;
1007 if (ep
->X_op
!= O_constant
)
1009 as_bad (_("unsupported large constant"));
1013 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1015 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1016 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1019 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1020 load_const (reg
, &upper
);
1022 macro_build (NULL
, "slli", "d,s,>", reg
, reg
, shift
);
1023 if (lower
.X_add_number
!= 0)
1024 macro_build (&lower
, "addi", "d,s,j", reg
, reg
, BFD_RELOC_RISCV_LO12_I
);
1028 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1031 if (upper
.X_add_number
!= 0)
1033 macro_build (ep
, "lui", "d,u", reg
, BFD_RELOC_RISCV_HI20
);
1037 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1038 macro_build (ep
, ADD32_INSN
, "d,s,j", reg
, hi_reg
,
1039 BFD_RELOC_RISCV_LO12_I
);
1043 /* Expand RISC-V assembly macros into one or more instructions. */
1045 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1046 bfd_reloc_code_real_type
*imm_reloc
)
1048 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1049 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1050 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1051 int mask
= ip
->insn_mo
->mask
;
1056 load_const (rd
, imm_expr
);
1061 /* Load the address of a symbol into a register. */
1062 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1063 as_bad (_("offset too large"));
1065 if (imm_expr
->X_op
== O_constant
)
1066 load_const (rd
, imm_expr
);
1067 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1068 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1069 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1070 else /* Local PIC symbol, or any non-PIC symbol */
1071 pcrel_load (rd
, rd
, imm_expr
, "addi",
1072 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1076 pcrel_load (rd
, rd
, imm_expr
, "addi",
1077 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1081 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1082 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1086 pcrel_load (rd
, rd
, imm_expr
, "lb",
1087 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1091 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1092 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1096 pcrel_load (rd
, rd
, imm_expr
, "lh",
1097 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1101 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1102 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1106 pcrel_load (rd
, rd
, imm_expr
, "lw",
1107 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1111 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1112 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1116 pcrel_load (rd
, rd
, imm_expr
, "ld",
1117 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1121 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1122 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1126 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1127 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1131 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1132 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1136 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1137 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1141 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1142 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1146 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1147 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1151 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1152 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1156 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1157 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1161 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1165 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1170 static const struct percent_op_match percent_op_utype
[] =
1172 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1173 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1174 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1175 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1176 {"%hi", BFD_RELOC_RISCV_HI20
},
1180 static const struct percent_op_match percent_op_itype
[] =
1182 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1183 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1184 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1188 static const struct percent_op_match percent_op_stype
[] =
1190 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1191 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1192 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1196 static const struct percent_op_match percent_op_rtype
[] =
1198 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1202 static const struct percent_op_match percent_op_null
[] =
1207 /* Return true if *STR points to a relocation operator. When returning true,
1208 move *STR over the operator and store its relocation code in *RELOC.
1209 Leave both *STR and *RELOC alone when returning false. */
1212 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1213 const struct percent_op_match
*percent_op
)
1215 for ( ; percent_op
->str
; percent_op
++)
1216 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1218 int len
= strlen (percent_op
->str
);
1220 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1223 *str
+= strlen (percent_op
->str
);
1224 *reloc
= percent_op
->reloc
;
1226 /* Check whether the output BFD supports this relocation.
1227 If not, issue an error and fall back on something safe. */
1228 if (*reloc
!= BFD_RELOC_UNUSED
1229 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1231 as_bad ("relocation %s isn't supported by the current ABI",
1233 *reloc
= BFD_RELOC_UNUSED
;
1241 my_getExpression (expressionS
*ep
, char *str
)
1245 save_in
= input_line_pointer
;
1246 input_line_pointer
= str
;
1248 expr_end
= input_line_pointer
;
1249 input_line_pointer
= save_in
;
1252 /* Parse string STR as a 16-bit relocatable operand. Store the
1253 expression in *EP and the relocation, if any, in RELOC.
1254 Return the number of relocation operators used (0 or 1).
1256 On exit, EXPR_END points to the first character after the expression. */
1259 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1260 char *str
, const struct percent_op_match
*percent_op
)
1263 unsigned crux_depth
, str_depth
, regno
;
1266 /* First, check for integer registers. No callers can accept a reg, but
1267 we need to avoid accidentally creating a useless undefined symbol below,
1268 if this is an instruction pattern that can't match. A glibc build fails
1269 if this is removed. */
1270 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1272 ep
->X_op
= O_register
;
1273 ep
->X_add_number
= regno
;
1278 /* Search for the start of the main expression.
1279 End the loop with CRUX pointing to the start
1280 of the main expression and with CRUX_DEPTH containing the number
1281 of open brackets at that point. */
1288 crux_depth
= str_depth
;
1290 /* Skip over whitespace and brackets, keeping count of the number
1292 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1298 && parse_relocation (&str
, reloc
, percent_op
));
1300 my_getExpression (ep
, crux
);
1303 /* Match every open bracket. */
1304 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1309 as_bad ("unclosed '('");
1316 /* Parse opcode name, could be an mnemonics or number. */
1318 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1319 char *str
, const struct percent_op_match
*percent_op
)
1321 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1325 ep
->X_op
= O_constant
;
1326 ep
->X_add_number
= o
->val
;
1330 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1333 /* Detect and handle implicitly zero load-store offsets. For example,
1334 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1335 an implicit offset was detected. */
1338 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1340 /* Check whether there is only a single bracketed expression left.
1341 If so, it must be the base register and the constant must be zero. */
1342 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1344 ep
->X_op
= O_constant
;
1345 ep
->X_add_number
= 0;
1352 /* This routine assembles an instruction into its binary format. As a
1353 side effect, it sets the global variable imm_reloc to the type of
1354 relocation to do if one of the operands is an address expression. */
1357 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1358 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1363 struct riscv_opcode
*insn
;
1368 const struct percent_op_match
*p
;
1369 const char *error
= "unrecognized opcode";
1371 /* Parse the name of the instruction. Terminate the string if whitespace
1372 is found so that hash_find only sees the name part of the string. */
1373 for (s
= str
; *s
!= '\0'; ++s
)
1381 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1384 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1386 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1389 if (!riscv_multi_subset_supports (insn
->subset
))
1392 create_insn (ip
, insn
);
1395 imm_expr
->X_op
= O_absent
;
1396 *imm_reloc
= BFD_RELOC_UNUSED
;
1397 p
= percent_op_itype
;
1399 for (args
= insn
->args
;; ++args
)
1401 s
+= strspn (s
, " \t");
1404 case '\0': /* End of args. */
1405 if (insn
->pinfo
!= INSN_MACRO
)
1407 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1410 /* For .insn, insn->match and insn->mask are 0. */
1411 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1419 /* Successful assembly. */
1426 case 's': /* RS1 x8-x15 */
1427 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1428 || !(regno
>= 8 && regno
<= 15))
1430 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1432 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1433 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1434 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1437 case 't': /* RS2 x8-x15 */
1438 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1439 || !(regno
>= 8 && regno
<= 15))
1441 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1443 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1444 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1445 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1448 case 'U': /* RS1, constrained to equal RD. */
1449 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1450 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1454 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1456 INSERT_OPERAND (CRS2
, *ip
, regno
);
1458 case 'c': /* RS1, constrained to equal sp. */
1459 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1464 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1465 || imm_expr
->X_op
!= O_constant
1466 || imm_expr
->X_add_number
<= 0
1467 || imm_expr
->X_add_number
>= 64)
1469 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1472 imm_expr
->X_op
= O_absent
;
1475 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1476 || imm_expr
->X_op
!= O_constant
1477 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1478 || imm_expr
->X_add_number
<= 0
1479 || imm_expr
->X_add_number
>= 32)
1481 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1484 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1485 || imm_expr
->X_op
!= O_constant
1486 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1487 || imm_expr
->X_add_number
< 0
1488 || imm_expr
->X_add_number
>= 256)
1490 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1493 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1494 || imm_expr
->X_op
!= O_constant
1495 || imm_expr
->X_add_number
== 0
1496 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1498 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1501 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1502 || imm_expr
->X_op
!= O_constant
1503 || imm_expr
->X_add_number
== 0
1504 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1506 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1509 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1511 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1512 || imm_expr
->X_op
!= O_constant
1513 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1515 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1518 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1520 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1521 || imm_expr
->X_op
!= O_constant
1522 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1524 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1527 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1529 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1530 || imm_expr
->X_op
!= O_constant
1531 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1534 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1537 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1539 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1540 || imm_expr
->X_op
!= O_constant
1541 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1544 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1547 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1548 || imm_expr
->X_op
!= O_constant
1549 /* C.addiw, c.li, and c.andi allow zero immediate.
1550 C.addi allows zero immediate as hint. Otherwise this
1552 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1554 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1557 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1558 || imm_expr
->X_op
!= O_constant
1559 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1560 || imm_expr
->X_add_number
== 0)
1563 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1566 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1567 || imm_expr
->X_op
!= O_constant
1568 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1569 || imm_expr
->X_add_number
== 0)
1572 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1575 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1577 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1578 || imm_expr
->X_op
!= O_constant
1579 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1582 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1585 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1587 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1588 || imm_expr
->X_op
!= O_constant
1589 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1592 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1595 p
= percent_op_utype
;
1596 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1599 if (imm_expr
->X_op
!= O_constant
1600 || imm_expr
->X_add_number
<= 0
1601 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1602 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1603 && (imm_expr
->X_add_number
<
1604 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1606 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1609 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1610 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1611 || ((int32_t)imm_expr
->X_add_number
1612 != imm_expr
->X_add_number
))
1614 imm_expr
->X_add_number
=
1615 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1621 case 'S': /* Floating-point RS1 x8-x15. */
1622 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1623 || !(regno
>= 8 && regno
<= 15))
1625 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1627 case 'D': /* Floating-point RS2 x8-x15. */
1628 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1629 || !(regno
>= 8 && regno
<= 15))
1631 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1633 case 'T': /* Floating-point RS2. */
1634 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1636 INSERT_OPERAND (CRS2
, *ip
, regno
);
1642 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1643 || imm_expr
->X_op
!= O_constant
1644 || imm_expr
->X_add_number
< 0
1645 || imm_expr
->X_add_number
>= 64)
1647 as_bad (_("bad value for funct6 field, "
1648 "value must be 0...64"));
1652 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
1653 imm_expr
->X_op
= O_absent
;
1657 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1658 || imm_expr
->X_op
!= O_constant
1659 || imm_expr
->X_add_number
< 0
1660 || imm_expr
->X_add_number
>= 16)
1662 as_bad (_("bad value for funct4 field, "
1663 "value must be 0...15"));
1667 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
1668 imm_expr
->X_op
= O_absent
;
1672 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1673 || imm_expr
->X_op
!= O_constant
1674 || imm_expr
->X_add_number
< 0
1675 || imm_expr
->X_add_number
>= 8)
1677 as_bad (_("bad value for funct3 field, "
1678 "value must be 0...7"));
1681 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
1682 imm_expr
->X_op
= O_absent
;
1686 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1687 || imm_expr
->X_op
!= O_constant
1688 || imm_expr
->X_add_number
< 0
1689 || imm_expr
->X_add_number
>= 4)
1691 as_bad (_("bad value for funct2 field, "
1692 "value must be 0...3"));
1695 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
1696 imm_expr
->X_op
= O_absent
;
1700 as_bad (_("bad compressed FUNCT field"
1701 " specifier 'CF%c'\n"),
1707 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1726 case '<': /* Shift amount, 0 - 31. */
1727 my_getExpression (imm_expr
, s
);
1728 check_absolute_expr (ip
, imm_expr
, FALSE
);
1729 if ((unsigned long) imm_expr
->X_add_number
> 31)
1730 as_bad (_("Improper shift amount (%lu)"),
1731 (unsigned long) imm_expr
->X_add_number
);
1732 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1733 imm_expr
->X_op
= O_absent
;
1737 case '>': /* Shift amount, 0 - (XLEN-1). */
1738 my_getExpression (imm_expr
, s
);
1739 check_absolute_expr (ip
, imm_expr
, FALSE
);
1740 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1741 as_bad (_("Improper shift amount (%lu)"),
1742 (unsigned long) imm_expr
->X_add_number
);
1743 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1744 imm_expr
->X_op
= O_absent
;
1748 case 'Z': /* CSRRxI immediate. */
1749 my_getExpression (imm_expr
, s
);
1750 check_absolute_expr (ip
, imm_expr
, FALSE
);
1751 if ((unsigned long) imm_expr
->X_add_number
> 31)
1752 as_bad (_("Improper CSRxI immediate (%lu)"),
1753 (unsigned long) imm_expr
->X_add_number
);
1754 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1755 imm_expr
->X_op
= O_absent
;
1759 case 'E': /* Control register. */
1760 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1761 INSERT_OPERAND (CSR
, *ip
, regno
);
1764 my_getExpression (imm_expr
, s
);
1765 check_absolute_expr (ip
, imm_expr
, TRUE
);
1766 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1767 as_bad (_("Improper CSR address (%lu)"),
1768 (unsigned long) imm_expr
->X_add_number
);
1769 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1770 imm_expr
->X_op
= O_absent
;
1775 case 'm': /* Rounding mode. */
1776 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1778 INSERT_OPERAND (RM
, *ip
, regno
);
1784 case 'Q': /* Fence predecessor/successor. */
1785 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1789 INSERT_OPERAND (PRED
, *ip
, regno
);
1791 INSERT_OPERAND (SUCC
, *ip
, regno
);
1796 case 'd': /* Destination register. */
1797 case 's': /* Source register. */
1798 case 't': /* Target register. */
1799 case 'r': /* rs3. */
1800 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1806 /* Now that we have assembled one operand, we use the args
1807 string to figure out where it goes in the instruction. */
1811 INSERT_OPERAND (RS1
, *ip
, regno
);
1814 INSERT_OPERAND (RD
, *ip
, regno
);
1817 INSERT_OPERAND (RS2
, *ip
, regno
);
1820 INSERT_OPERAND (RS3
, *ip
, regno
);
1827 case 'D': /* Floating point rd. */
1828 case 'S': /* Floating point rs1. */
1829 case 'T': /* Floating point rs2. */
1830 case 'U': /* Floating point rs1 and rs2. */
1831 case 'R': /* Floating point rs3. */
1832 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1840 INSERT_OPERAND (RD
, *ip
, regno
);
1843 INSERT_OPERAND (RS1
, *ip
, regno
);
1846 INSERT_OPERAND (RS1
, *ip
, regno
);
1849 INSERT_OPERAND (RS2
, *ip
, regno
);
1852 INSERT_OPERAND (RS3
, *ip
, regno
);
1861 my_getExpression (imm_expr
, s
);
1862 if (imm_expr
->X_op
!= O_big
1863 && imm_expr
->X_op
!= O_constant
)
1865 normalize_constant_expr (imm_expr
);
1870 my_getExpression (imm_expr
, s
);
1871 normalize_constant_expr (imm_expr
);
1872 /* The 'A' format specifier must be a symbol. */
1873 if (imm_expr
->X_op
!= O_symbol
)
1875 *imm_reloc
= BFD_RELOC_32
;
1880 my_getExpression (imm_expr
, s
);
1881 normalize_constant_expr (imm_expr
);
1882 /* The 'B' format specifier must be a symbol or a constant. */
1883 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
1885 if (imm_expr
->X_op
== O_symbol
)
1886 *imm_reloc
= BFD_RELOC_32
;
1890 case 'j': /* Sign-extended immediate. */
1891 p
= percent_op_itype
;
1892 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1894 case 'q': /* Store displacement. */
1895 p
= percent_op_stype
;
1896 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
1898 case 'o': /* Load displacement. */
1899 p
= percent_op_itype
;
1900 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1902 case '1': /* 4-operand add, must be %tprel_add. */
1903 p
= percent_op_rtype
;
1905 case '0': /* AMO "displacement," which must be zero. */
1906 p
= percent_op_null
;
1908 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1911 /* If this value won't fit into a 16 bit offset, then go
1912 find a macro that will generate the 32 bit offset
1914 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1916 normalize_constant_expr (imm_expr
);
1917 if (imm_expr
->X_op
!= O_constant
1918 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
1920 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
1921 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
1928 case 'p': /* PC-relative offset. */
1930 *imm_reloc
= BFD_RELOC_12_PCREL
;
1931 my_getExpression (imm_expr
, s
);
1935 case 'u': /* Upper 20 bits. */
1936 p
= percent_op_utype
;
1937 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1938 && imm_expr
->X_op
== O_constant
)
1940 if (imm_expr
->X_add_number
< 0
1941 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
1942 as_bad (_("lui expression not in range 0..1048575"));
1944 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
1945 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
1947 /* The 'u' format specifier must be a symbol or a constant. */
1948 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
1953 case 'a': /* 20-bit PC-relative offset. */
1955 my_getExpression (imm_expr
, s
);
1957 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
1961 my_getExpression (imm_expr
, s
);
1963 if (strcmp (s
, "@plt") == 0)
1965 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
1969 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
1975 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
1976 || imm_expr
->X_op
!= O_constant
1977 || imm_expr
->X_add_number
< 0
1978 || imm_expr
->X_add_number
>= 128
1979 || (imm_expr
->X_add_number
& 0x3) != 3)
1981 as_bad (_("bad value for opcode field, "
1982 "value must be 0...127 and "
1983 "lower 2 bits must be 0x3"));
1987 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
1988 imm_expr
->X_op
= O_absent
;
1992 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
1993 || imm_expr
->X_op
!= O_constant
1994 || imm_expr
->X_add_number
< 0
1995 || imm_expr
->X_add_number
>= 3)
1997 as_bad (_("bad value for opcode field, "
1998 "value must be 0...2"));
2002 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2003 imm_expr
->X_op
= O_absent
;
2007 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2015 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2016 || imm_expr
->X_op
!= O_constant
2017 || imm_expr
->X_add_number
< 0
2018 || imm_expr
->X_add_number
>= 128)
2020 as_bad (_("bad value for funct7 field, "
2021 "value must be 0...127"));
2025 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2026 imm_expr
->X_op
= O_absent
;
2030 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2031 || imm_expr
->X_op
!= O_constant
2032 || imm_expr
->X_add_number
< 0
2033 || imm_expr
->X_add_number
>= 8)
2035 as_bad (_("bad value for funct3 field, "
2036 "value must be 0...7"));
2040 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2041 imm_expr
->X_op
= O_absent
;
2045 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2046 || imm_expr
->X_op
!= O_constant
2047 || imm_expr
->X_add_number
< 0
2048 || imm_expr
->X_add_number
>= 4)
2050 as_bad (_("bad value for funct2 field, "
2051 "value must be 0...3"));
2055 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2056 imm_expr
->X_op
= O_absent
;
2061 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2066 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2067 || imm_expr
->X_op
!= O_constant
2068 || imm_expr
->X_add_number
!= 0)
2071 imm_expr
->X_op
= O_absent
;
2075 as_fatal (_("internal error: bad argument type %c"), *args
);
2080 error
= _("illegal operands");
2084 /* Restore the character we might have clobbered above. */
2086 *(argsStart
- 1) = save_c
;
2092 md_assemble (char *str
)
2094 struct riscv_cl_insn insn
;
2095 expressionS imm_expr
;
2096 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2098 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2102 as_bad ("%s `%s'", error
, str
);
2106 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2107 macro (&insn
, &imm_expr
, &imm_reloc
);
2109 append_insn (&insn
, &imm_expr
, imm_reloc
);
2113 md_atof (int type
, char *litP
, int *sizeP
)
2115 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2119 md_number_to_chars (char *buf
, valueT val
, int n
)
2121 number_to_chars_littleendian (buf
, val
, n
);
2124 const char *md_shortopts
= "O::g::G:";
2128 OPTION_MARCH
= OPTION_MD_BASE
,
2137 struct option md_longopts
[] =
2139 {"march", required_argument
, NULL
, OPTION_MARCH
},
2140 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2141 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2142 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2143 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2144 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2145 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2147 {NULL
, no_argument
, NULL
, 0}
2149 size_t md_longopts_size
= sizeof (md_longopts
);
2152 FLOAT_ABI_DEFAULT
= -1,
2158 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2161 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2163 abi_xlen
= new_xlen
;
2164 float_abi
= new_float_abi
;
2169 md_parse_option (int c
, const char *arg
)
2174 riscv_set_arch (arg
);
2178 riscv_opts
.pic
= FALSE
;
2182 riscv_opts
.pic
= TRUE
;
2186 if (strcmp (arg
, "ilp32") == 0)
2187 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2188 else if (strcmp (arg
, "ilp32e") == 0)
2189 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2190 else if (strcmp (arg
, "ilp32f") == 0)
2191 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2192 else if (strcmp (arg
, "ilp32d") == 0)
2193 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2194 else if (strcmp (arg
, "ilp32q") == 0)
2195 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2196 else if (strcmp (arg
, "lp64") == 0)
2197 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2198 else if (strcmp (arg
, "lp64f") == 0)
2199 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2200 else if (strcmp (arg
, "lp64d") == 0)
2201 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2202 else if (strcmp (arg
, "lp64q") == 0)
2203 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2209 riscv_opts
.relax
= TRUE
;
2212 case OPTION_NO_RELAX
:
2213 riscv_opts
.relax
= FALSE
;
2224 riscv_after_parse_args (void)
2228 if (strcmp (default_arch
, "riscv32") == 0)
2230 else if (strcmp (default_arch
, "riscv64") == 0)
2233 as_bad ("unknown default architecture `%s'", default_arch
);
2236 if (riscv_subsets
.head
== NULL
)
2237 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
2239 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2240 riscv_set_rvc (FALSE
);
2241 if (riscv_subset_supports ("c"))
2242 riscv_set_rvc (TRUE
);
2244 /* Enable RVE if specified by the -march option. */
2245 riscv_set_rve (FALSE
);
2246 if (riscv_subset_supports ("e"))
2247 riscv_set_rve (TRUE
);
2249 /* Infer ABI from ISA if not specified on command line. */
2252 else if (abi_xlen
> xlen
)
2253 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2254 else if (abi_xlen
< xlen
)
2255 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2257 if (float_abi
== FLOAT_ABI_DEFAULT
)
2259 riscv_subset_t
*subset
;
2261 /* Assume soft-float unless D extension is present. */
2262 float_abi
= FLOAT_ABI_SOFT
;
2264 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2266 if (strcasecmp (subset
->name
, "D") == 0)
2267 float_abi
= FLOAT_ABI_DOUBLE
;
2268 if (strcasecmp (subset
->name
, "Q") == 0)
2269 float_abi
= FLOAT_ABI_QUAD
;
2274 elf_flags
|= EF_RISCV_RVE
;
2276 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2277 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2281 md_pcrel_from (fixS
*fixP
)
2283 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2286 /* Apply a fixup to the object file. */
2289 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2291 unsigned int subtype
;
2292 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2293 bfd_boolean relaxable
= FALSE
;
2297 /* Remember value for tc_gen_reloc. */
2298 fixP
->fx_addnumber
= *valP
;
2300 switch (fixP
->fx_r_type
)
2302 case BFD_RELOC_RISCV_HI20
:
2303 case BFD_RELOC_RISCV_LO12_I
:
2304 case BFD_RELOC_RISCV_LO12_S
:
2305 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2306 | bfd_getl32 (buf
), buf
);
2307 if (fixP
->fx_addsy
== NULL
)
2308 fixP
->fx_done
= TRUE
;
2312 case BFD_RELOC_RISCV_GOT_HI20
:
2313 case BFD_RELOC_RISCV_ADD8
:
2314 case BFD_RELOC_RISCV_ADD16
:
2315 case BFD_RELOC_RISCV_ADD32
:
2316 case BFD_RELOC_RISCV_ADD64
:
2317 case BFD_RELOC_RISCV_SUB6
:
2318 case BFD_RELOC_RISCV_SUB8
:
2319 case BFD_RELOC_RISCV_SUB16
:
2320 case BFD_RELOC_RISCV_SUB32
:
2321 case BFD_RELOC_RISCV_SUB64
:
2322 case BFD_RELOC_RISCV_RELAX
:
2325 case BFD_RELOC_RISCV_TPREL_HI20
:
2326 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2327 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2328 case BFD_RELOC_RISCV_TPREL_ADD
:
2332 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2333 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2334 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2335 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2336 if (fixP
->fx_addsy
!= NULL
)
2337 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2339 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2340 _("TLS relocation against a constant"));
2344 /* Use pc-relative relocation for FDE initial location.
2345 The symbol address in .eh_frame may be adjusted in
2346 _bfd_elf_discard_section_eh_frame, and the content of
2347 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2348 Therefore, we cannot insert a relocation whose addend symbol is
2349 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2350 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2351 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2352 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2353 && S_GET_VALUE (fixP
->fx_subsy
)
2354 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2356 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2357 fixP
->fx_subsy
= NULL
;
2364 case BFD_RELOC_RISCV_CFA
:
2365 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2367 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2368 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2369 fixP
->fx_next
->fx_subsy
= NULL
;
2370 fixP
->fx_next
->fx_offset
= 0;
2371 fixP
->fx_subsy
= NULL
;
2373 switch (fixP
->fx_r_type
)
2376 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2377 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2381 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2382 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2386 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2387 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2391 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2392 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2395 case BFD_RELOC_RISCV_CFA
:
2396 /* Load the byte to get the subtype. */
2397 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2398 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2401 case DW_CFA_advance_loc1
:
2402 fixP
->fx_where
= loc
+ 1;
2403 fixP
->fx_next
->fx_where
= loc
+ 1;
2404 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2405 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2408 case DW_CFA_advance_loc2
:
2410 fixP
->fx_next
->fx_size
= 2;
2411 fixP
->fx_where
= loc
+ 1;
2412 fixP
->fx_next
->fx_where
= loc
+ 1;
2413 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2414 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2417 case DW_CFA_advance_loc4
:
2419 fixP
->fx_next
->fx_size
= 4;
2420 fixP
->fx_where
= loc
;
2421 fixP
->fx_next
->fx_where
= loc
;
2422 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2423 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2427 if (subtype
< 0x80 && (subtype
& 0x40))
2429 /* DW_CFA_advance_loc */
2430 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2431 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2432 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2433 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2436 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2442 /* This case is unreachable. */
2449 /* If we are deleting this reloc entry, we must fill in the
2450 value now. This can happen if we have a .word which is not
2451 resolved when it appears but is later defined. */
2452 if (fixP
->fx_addsy
== NULL
)
2454 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2455 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2460 case BFD_RELOC_RISCV_JMP
:
2463 /* Fill in a tentative value to improve objdump readability. */
2464 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2465 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2466 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2470 case BFD_RELOC_12_PCREL
:
2473 /* Fill in a tentative value to improve objdump readability. */
2474 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2475 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2476 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2480 case BFD_RELOC_RISCV_RVC_BRANCH
:
2483 /* Fill in a tentative value to improve objdump readability. */
2484 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2485 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2486 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2490 case BFD_RELOC_RISCV_RVC_JUMP
:
2493 /* Fill in a tentative value to improve objdump readability. */
2494 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2495 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2496 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2500 case BFD_RELOC_RISCV_CALL
:
2501 case BFD_RELOC_RISCV_CALL_PLT
:
2505 case BFD_RELOC_RISCV_PCREL_HI20
:
2506 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2507 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2508 relaxable
= riscv_opts
.relax
;
2511 case BFD_RELOC_RISCV_ALIGN
:
2515 /* We ignore generic BFD relocations we don't know about. */
2516 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2517 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2520 if (fixP
->fx_subsy
!= NULL
)
2521 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2522 _("unsupported symbol subtraction"));
2524 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2525 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2527 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2528 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2529 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2533 /* Because the value of .cfi_remember_state may changed after relaxation,
2534 we insert a fix to relocate it again in link-time. */
2537 riscv_pre_output_hook (void)
2539 const frchainS
*frch
;
2542 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2543 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2547 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2549 if (frag
->fr_type
== rs_cfa
)
2552 expressionS
*symval
;
2554 symval
= symbol_get_value_expression (frag
->fr_symbol
);
2555 exp
.X_op
= O_subtract
;
2556 exp
.X_add_symbol
= symval
->X_add_symbol
;
2557 exp
.X_add_number
= 0;
2558 exp
.X_op_symbol
= symval
->X_op_symbol
;
2560 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2561 BFD_RELOC_RISCV_CFA
);
2568 /* This structure is used to hold a stack of .option values. */
2570 struct riscv_option_stack
2572 struct riscv_option_stack
*next
;
2573 struct riscv_set_options options
;
2576 static struct riscv_option_stack
*riscv_opts_stack
;
2578 /* Handle the .option pseudo-op. */
2581 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2583 char *name
= input_line_pointer
, ch
;
2585 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2586 ++input_line_pointer
;
2587 ch
= *input_line_pointer
;
2588 *input_line_pointer
= '\0';
2590 if (strcmp (name
, "rvc") == 0)
2591 riscv_set_rvc (TRUE
);
2592 else if (strcmp (name
, "norvc") == 0)
2593 riscv_set_rvc (FALSE
);
2594 else if (strcmp (name
, "pic") == 0)
2595 riscv_opts
.pic
= TRUE
;
2596 else if (strcmp (name
, "nopic") == 0)
2597 riscv_opts
.pic
= FALSE
;
2598 else if (strcmp (name
, "relax") == 0)
2599 riscv_opts
.relax
= TRUE
;
2600 else if (strcmp (name
, "norelax") == 0)
2601 riscv_opts
.relax
= FALSE
;
2602 else if (strcmp (name
, "push") == 0)
2604 struct riscv_option_stack
*s
;
2606 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2607 s
->next
= riscv_opts_stack
;
2608 s
->options
= riscv_opts
;
2609 riscv_opts_stack
= s
;
2611 else if (strcmp (name
, "pop") == 0)
2613 struct riscv_option_stack
*s
;
2615 s
= riscv_opts_stack
;
2617 as_bad (_(".option pop with no .option push"));
2620 riscv_opts
= s
->options
;
2621 riscv_opts_stack
= s
->next
;
2627 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2629 *input_line_pointer
= ch
;
2630 demand_empty_rest_of_line ();
2633 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2634 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2635 use in DWARF debug information. */
2638 s_dtprel (int bytes
)
2645 if (ex
.X_op
!= O_symbol
)
2647 as_bad (_("Unsupported use of %s"), (bytes
== 8
2650 ignore_rest_of_line ();
2653 p
= frag_more (bytes
);
2654 md_number_to_chars (p
, 0, bytes
);
2655 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2657 ? BFD_RELOC_RISCV_TLS_DTPREL64
2658 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2660 demand_empty_rest_of_line ();
2663 /* Handle the .bss pseudo-op. */
2666 s_bss (int ignore ATTRIBUTE_UNUSED
)
2668 subseg_set (bss_section
, 0);
2669 demand_empty_rest_of_line ();
2673 riscv_make_nops (char *buf
, bfd_vma bytes
)
2677 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2678 means we are not within a valid instruction sequence. It is thus safe
2679 to use a zero byte, even though that is not a valid instruction. */
2683 /* Use at most one 2-byte NOP. */
2684 if ((bytes
- i
) % 4 == 2)
2686 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2690 /* Fill the remainder with 4-byte NOPs. */
2691 for ( ; i
< bytes
; i
+= 4)
2692 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2695 /* Called from md_do_align. Used to create an alignment frag in a
2696 code section by emitting a worst-case NOP sequence that the linker
2697 will later relax to the correct number of NOPs. We can't compute
2698 the correct alignment now because of other linker relaxations. */
2701 riscv_frag_align_code (int n
)
2703 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2704 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
2705 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
2709 /* If we are moving to a smaller alignment than the instruction size, then no
2710 alignment is required. */
2711 if (bytes
<= insn_alignment
)
2714 /* When not relaxing, riscv_handle_align handles code alignment. */
2715 if (!riscv_opts
.relax
)
2718 nops
= frag_more (worst_case_bytes
);
2720 ex
.X_op
= O_constant
;
2721 ex
.X_add_number
= worst_case_bytes
;
2723 riscv_make_nops (nops
, worst_case_bytes
);
2725 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2726 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2731 /* Implement HANDLE_ALIGN. */
2734 riscv_handle_align (fragS
*fragP
)
2736 switch (fragP
->fr_type
)
2739 /* When relaxing, riscv_frag_align_code handles code alignment. */
2740 if (!riscv_opts
.relax
)
2742 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
2743 - fragP
->fr_address
- fragP
->fr_fix
);
2744 /* We have 4 byte uncompressed nops. */
2745 bfd_signed_vma size
= 4;
2746 bfd_signed_vma excess
= bytes
% size
;
2747 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2752 /* Insert zeros or compressed nops to get 4 byte alignment. */
2755 riscv_make_nops (p
, excess
);
2756 fragP
->fr_fix
+= excess
;
2760 /* Insert variable number of 4 byte uncompressed nops. */
2761 riscv_make_nops (p
, size
);
2762 fragP
->fr_var
= size
;
2772 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2774 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2777 /* Translate internal representation of relocation info to BFD target
2781 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2783 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2785 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2786 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2787 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2788 reloc
->addend
= fixp
->fx_addnumber
;
2790 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2791 if (reloc
->howto
== NULL
)
2793 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2794 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2796 /* We don't have R_RISCV_8/16, but for this special case,
2797 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2801 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2802 _("cannot represent %s relocation in object file"),
2803 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2811 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2813 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2815 offsetT old_var
= fragp
->fr_var
;
2816 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2817 return fragp
->fr_var
- old_var
;
2823 /* Expand far branches to multi-instruction sequences. */
2826 md_convert_frag_branch (fragS
*fragp
)
2834 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2836 exp
.X_op
= O_symbol
;
2837 exp
.X_add_symbol
= fragp
->fr_symbol
;
2838 exp
.X_add_number
= fragp
->fr_offset
;
2840 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2842 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2844 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2848 /* Expand the RVC branch into a RISC-V one. */
2849 insn
= bfd_getl16 (buf
);
2850 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2851 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2853 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2854 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2855 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2856 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2857 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2858 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2861 bfd_putl32 (insn
, buf
);
2865 /* Invert the branch condition. Branch over the jump. */
2866 insn
= bfd_getl16 (buf
);
2867 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2868 insn
|= ENCODE_RVC_B_IMM (6);
2869 bfd_putl16 (insn
, buf
);
2874 /* Just keep the RVC branch. */
2875 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2876 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2877 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2878 2, &exp
, FALSE
, reloc
);
2887 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2890 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2892 /* Invert the branch condition. Branch over the jump. */
2893 insn
= bfd_getl32 (buf
);
2894 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2895 insn
|= ENCODE_SBTYPE_IMM (8);
2896 md_number_to_chars ((char *) buf
, insn
, 4);
2900 /* Jump to the target. */
2901 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2902 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
2903 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
2908 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2909 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
2910 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2911 4, &exp
, FALSE
, reloc
);
2920 fixp
->fx_file
= fragp
->fr_file
;
2921 fixp
->fx_line
= fragp
->fr_line
;
2923 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
2924 + fragp
->fr_fix
+ fragp
->fr_var
);
2926 fragp
->fr_fix
+= fragp
->fr_var
;
2929 /* Relax a machine dependent frag. This returns the amount by which
2930 the current size of the frag should change. */
2933 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
2936 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
2937 md_convert_frag_branch (fragp
);
2941 md_show_usage (FILE *stream
)
2943 fprintf (stream
, _("\
2945 -fpic generate position-independent code\n\
2946 -fno-pic don't generate position-independent code (default)\n\
2947 -march=ISA set the RISC-V architecture\n\
2948 -mabi=ABI set the RISC-V ABI\n\
2949 -mrelax enable relax (default)\n\
2950 -mno-relax disable relax\n\
2954 /* Standard calling conventions leave the CFA at SP on entry. */
2956 riscv_cfi_frame_initial_instructions (void)
2958 cfi_add_CFA_def_cfa_register (X_SP
);
2962 tc_riscv_regname_to_dw2regnum (char *regname
)
2966 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
2969 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
2972 as_bad (_("unknown register `%s'"), regname
);
2977 riscv_elf_final_processing (void)
2979 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
2982 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
2983 since these directives break relaxation when used with symbol deltas. */
2986 s_riscv_leb128 (int sign
)
2989 char *save_in
= input_line_pointer
;
2992 if (exp
.X_op
!= O_constant
)
2993 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
2994 demand_empty_rest_of_line ();
2996 input_line_pointer
= save_in
;
2997 return s_leb128 (sign
);
3000 /* Parse the .insn directive. */
3003 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3005 char *str
= input_line_pointer
;
3006 struct riscv_cl_insn insn
;
3007 expressionS imm_expr
;
3008 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3011 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3012 ++input_line_pointer
;
3014 save_c
= *input_line_pointer
;
3015 *input_line_pointer
= '\0';
3017 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3018 &imm_reloc
, insn_type_hash
);
3022 as_bad ("%s `%s'", error
, str
);
3026 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3027 append_insn (&insn
, &imm_expr
, imm_reloc
);
3030 *input_line_pointer
= save_c
;
3031 demand_empty_rest_of_line ();
3034 /* Pseudo-op table. */
3036 static const pseudo_typeS riscv_pseudo_table
[] =
3038 /* RISC-V-specific pseudo-ops. */
3039 {"option", s_riscv_option
, 0},
3043 {"dtprelword", s_dtprel
, 4},
3044 {"dtpreldword", s_dtprel
, 8},
3046 {"uleb128", s_riscv_leb128
, 0},
3047 {"sleb128", s_riscv_leb128
, 1},
3048 {"insn", s_riscv_insn
, 0},
3054 riscv_pop_insert (void)
3056 extern void pop_insert (const pseudo_typeS
*);
3058 pop_insert (riscv_pseudo_table
);