1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2022 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
58 /* All RISC-V CSR belong to one of these classes. */
64 CSR_CLASS_I_32
, /* rv32 only */
65 CSR_CLASS_F
, /* f-ext only */
66 CSR_CLASS_ZKR
, /* zkr only */
67 CSR_CLASS_V
, /* rvv only */
68 CSR_CLASS_DEBUG
, /* debug CSR */
69 CSR_CLASS_H
, /* hypervisor */
70 CSR_CLASS_H_32
, /* hypervisor, rv32 only */
71 CSR_CLASS_SMSTATEEN
, /* Smstateen only */
72 CSR_CLASS_SMSTATEEN_AND_H
, /* Smstateen only (with H) */
73 CSR_CLASS_SMSTATEEN_32
, /* Smstateen RV32 only */
74 CSR_CLASS_SMSTATEEN_AND_H_32
, /* Smstateen RV32 only (with H) */
75 CSR_CLASS_SSCOFPMF
, /* Sscofpmf only */
76 CSR_CLASS_SSCOFPMF_32
, /* Sscofpmf RV32 only */
77 CSR_CLASS_SSTC
, /* Sstc only */
78 CSR_CLASS_SSTC_AND_H
, /* Sstc only (with H) */
79 CSR_CLASS_SSTC_32
, /* Sstc RV32 only */
80 CSR_CLASS_SSTC_AND_H_32
, /* Sstc RV32 only (with H) */
83 /* This structure holds all restricted conditions for a CSR. */
84 struct riscv_csr_extra
86 /* Class to which this CSR belongs. Used to decide whether or
87 not this CSR is legal in the current -march context. */
88 enum riscv_csr_class csr_class
;
90 /* CSR may have differnet numbers in the previous priv spec. */
93 /* Record the CSR is defined/valid in which versions. */
94 enum riscv_spec_class define_version
;
96 /* Record the CSR is aborted/invalid from which versions. If it isn't
97 aborted in the current version, then it should be PRIV_SPEC_CLASS_DRAFT. */
98 enum riscv_spec_class abort_version
;
100 /* The CSR may have more than one setting. */
101 struct riscv_csr_extra
*next
;
104 /* This structure contains information about errors that occur within the
106 struct riscv_ip_error
108 /* General error message */
111 /* Statement that caused the error */
114 /* Missing extension that needs to be enabled */
115 const char* missing_ext
;
119 #define DEFAULT_ARCH "riscv64"
122 #ifndef DEFAULT_RISCV_ATTR
123 #define DEFAULT_RISCV_ATTR 0
126 /* Let riscv_after_parse_args set the default value according to xlen. */
127 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
128 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
131 /* Need to sync the version with RISC-V compiler. */
132 #ifndef DEFAULT_RISCV_ISA_SPEC
133 #define DEFAULT_RISCV_ISA_SPEC "20191213"
136 #ifndef DEFAULT_RISCV_PRIV_SPEC
137 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
140 static const char default_arch
[] = DEFAULT_ARCH
;
141 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
142 static enum riscv_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
143 static enum riscv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
145 static unsigned xlen
= 0; /* The width of an x-register. */
146 static unsigned abi_xlen
= 0; /* The width of a pointer in the ABI. */
147 static bool rve_abi
= false;
150 FLOAT_ABI_DEFAULT
= -1,
156 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
158 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
159 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
161 static unsigned elf_flags
= 0;
163 /* Set the default_isa_spec. Return 0 if the spec isn't supported.
164 Otherwise, return 1. */
167 riscv_set_default_isa_spec (const char *s
)
169 enum riscv_spec_class
class = ISA_SPEC_CLASS_NONE
;
170 RISCV_GET_ISA_SPEC_CLASS (s
, class);
171 if (class == ISA_SPEC_CLASS_NONE
)
173 as_bad ("unknown default ISA spec `%s' set by "
174 "-misa-spec or --with-isa-spec", s
);
178 default_isa_spec
= class;
182 /* Set the default_priv_spec. Find the privileged elf attributes when
183 the input string is NULL. Return 0 if the spec isn't supported.
184 Otherwise, return 1. */
187 riscv_set_default_priv_spec (const char *s
)
189 enum riscv_spec_class
class = PRIV_SPEC_CLASS_NONE
;
190 unsigned major
, minor
, revision
;
193 RISCV_GET_PRIV_SPEC_CLASS (s
, class);
194 if (class != PRIV_SPEC_CLASS_NONE
)
196 default_priv_spec
= class;
202 as_bad (_("unknown default privileged spec `%s' set by "
203 "-mpriv-spec or --with-priv-spec"), s
);
207 /* Set the default_priv_spec by the privileged elf attributes. */
208 attr
= elf_known_obj_attributes_proc (stdoutput
);
209 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
210 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
211 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
212 /* Version 0.0.0 is the default value and meningless. */
213 if (major
== 0 && minor
== 0 && revision
== 0)
216 riscv_get_priv_spec_class_from_numbers (major
, minor
, revision
, &class);
217 if (class != PRIV_SPEC_CLASS_NONE
)
219 default_priv_spec
= class;
223 /* Still can not find the privileged spec class. */
224 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
225 "privileged elf attributes"), major
, minor
, revision
);
229 /* This is the set of options which the .option pseudo-op may modify. */
230 struct riscv_set_options
232 int pic
; /* Generate position-independent code. */
233 int rvc
; /* Generate RVC code. */
234 int relax
; /* Emit relocs the linker is allowed to relax. */
235 int arch_attr
; /* Emit architecture and privileged elf attributes. */
236 int csr_check
; /* Enable the CSR checking. */
239 static struct riscv_set_options riscv_opts
=
244 DEFAULT_RISCV_ATTR
, /* arch_attr */
248 /* Enable or disable the rvc flags for riscv_opts. Turn on the rvc flag
249 for elf_flags once we have enabled c extension. */
252 riscv_set_rvc (bool rvc_value
)
255 elf_flags
|= EF_RISCV_RVC
;
257 riscv_opts
.rvc
= rvc_value
;
260 /* This linked list records all enabled extensions, which are parsed from
261 the architecture string. The architecture string can be set by the
262 -march option, the elf architecture attributes, and the --with-arch
264 static riscv_subset_list_t
*riscv_subsets
= NULL
;
265 static riscv_parse_subset_t riscv_rps_as
=
267 NULL
, /* subset_list, we will set it later once
268 riscv_opts_stack is created or updated. */
269 as_bad
, /* error_handler. */
271 &default_isa_spec
, /* isa_spec. */
272 true, /* check_unknown_prefixed_ext. */
275 /* This structure is used to hold a stack of .option values. */
276 struct riscv_option_stack
278 struct riscv_option_stack
*next
;
279 struct riscv_set_options options
;
280 riscv_subset_list_t
*subset_list
;
283 static struct riscv_option_stack
*riscv_opts_stack
= NULL
;
285 /* Set which ISA and extensions are available. */
288 riscv_set_arch (const char *s
)
290 if (s
!= NULL
&& strcmp (s
, "") == 0)
292 as_bad (_("the architecture string of -march and elf architecture "
293 "attributes cannot be empty"));
297 if (riscv_subsets
== NULL
)
299 riscv_subsets
= XNEW (riscv_subset_list_t
);
300 riscv_subsets
->head
= NULL
;
301 riscv_subsets
->tail
= NULL
;
302 riscv_rps_as
.subset_list
= riscv_subsets
;
304 riscv_release_subset_list (riscv_subsets
);
305 riscv_parse_subset (&riscv_rps_as
, s
);
307 riscv_set_rvc (false);
308 if (riscv_subset_supports (&riscv_rps_as
, "c"))
309 riscv_set_rvc (true);
312 /* Indicate -mabi option is explictly set. */
313 static bool explicit_mabi
= false;
315 /* Set the abi information. */
318 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bool rve
)
321 float_abi
= new_float_abi
;
325 /* If the -mabi option isn't set, then set the abi according to the
326 ISA string. Otherwise, check if there is any conflict. */
329 riscv_set_abi_by_arch (void)
333 if (riscv_subset_supports (&riscv_rps_as
, "q"))
334 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, false);
335 else if (riscv_subset_supports (&riscv_rps_as
, "d"))
336 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, false);
337 else if (riscv_subset_supports (&riscv_rps_as
, "e"))
338 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, true);
340 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, false);
344 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
346 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
347 else if (abi_xlen
< xlen
)
348 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
350 if (riscv_subset_supports (&riscv_rps_as
, "e") && !rve_abi
)
351 as_bad ("only the ilp32e ABI is supported for e extension");
353 if (float_abi
== FLOAT_ABI_SINGLE
354 && !riscv_subset_supports (&riscv_rps_as
, "f"))
355 as_bad ("ilp32f/lp64f ABI can't be used when f extension "
357 else if (float_abi
== FLOAT_ABI_DOUBLE
358 && !riscv_subset_supports (&riscv_rps_as
, "d"))
359 as_bad ("ilp32d/lp64d ABI can't be used when d extension "
361 else if (float_abi
== FLOAT_ABI_QUAD
362 && !riscv_subset_supports (&riscv_rps_as
, "q"))
363 as_bad ("ilp32q/lp64q ABI can't be used when q extension "
367 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
368 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
369 elf_flags
|= float_abi
<< 1;
372 elf_flags
|= EF_RISCV_RVE
;
375 /* Handle of the OPCODE hash table. */
376 static htab_t op_hash
= NULL
;
378 /* Handle of the type of .insn hash table. */
379 static htab_t insn_type_hash
= NULL
;
381 /* This array holds the chars that always start a comment. If the
382 pre-processor is disabled, these aren't very useful. */
383 const char comment_chars
[] = "#";
385 /* This array holds the chars that only start a comment at the beginning of
386 a line. If the line seems to have the form '# 123 filename'
387 .line and .file directives will appear in the pre-processed output
389 Note that input_file.c hand checks for '#' at the beginning of the
390 first line of the input file. This is because the compiler outputs
391 #NO_APP at the beginning of its output.
393 Also note that C style comments are always supported. */
394 const char line_comment_chars
[] = "#";
396 /* This array holds machine specific line separator characters. */
397 const char line_separator_chars
[] = ";";
399 /* Chars that can be used to separate mant from exp in floating point nums. */
400 const char EXP_CHARS
[] = "eE";
402 /* Chars that mean this number is a floating point constant.
403 As in 0f12.456 or 0d1.2345e12. */
404 const char FLT_CHARS
[] = "rRsSfFdDxXpPhH";
406 /* Indicate we are already assemble any instructions or not. */
407 static bool start_assemble
= false;
409 /* Indicate ELF attributes are explicitly set. */
410 static bool explicit_attr
= false;
412 /* Indicate CSR or priv instructions are explicitly used. */
413 static bool explicit_priv_attr
= false;
415 static char *expr_end
;
417 /* Macros for encoding relaxation state for RVC branches and far jumps. */
418 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
421 | ((uncond) ? 1 : 0) \
424 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
425 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
426 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
427 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
429 /* Is the given value a sign-extended 32-bit value? */
430 #define IS_SEXT_32BIT_NUM(x) \
431 (((x) &~ (offsetT) 0x7fffffff) == 0 \
432 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
434 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
435 #define IS_ZEXT_32BIT_NUM(x) \
436 (((x) &~ (offsetT) 0xffffffff) == 0 \
437 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
439 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
440 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
441 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
442 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
444 /* Determine if an instruction matches an opcode. */
445 #define OPCODE_MATCHES(OPCODE, OP) \
446 (((OPCODE) & MASK_##OP) == MATCH_##OP)
448 /* Create a new mapping symbol for the transition to STATE. */
451 make_mapping_symbol (enum riscv_seg_mstate state
,
468 symbolS
*symbol
= symbol_new (name
, now_seg
, frag
, value
);
469 symbol_get_bfdsym (symbol
)->flags
|= (BSF_NO_FLAGS
| BSF_LOCAL
);
471 /* If .fill or other data filling directive generates zero sized data,
472 or we are adding odd alignemnts, then the mapping symbol for the
473 following code will have the same value. */
476 if (frag
->tc_frag_data
.first_map_symbol
!= NULL
)
478 know (S_GET_VALUE (frag
->tc_frag_data
.first_map_symbol
)
479 == S_GET_VALUE (symbol
));
480 /* Remove the old one. */
481 symbol_remove (frag
->tc_frag_data
.first_map_symbol
,
482 &symbol_rootP
, &symbol_lastP
);
484 frag
->tc_frag_data
.first_map_symbol
= symbol
;
486 if (frag
->tc_frag_data
.last_map_symbol
!= NULL
)
488 /* The mapping symbols should be added in offset order. */
489 know (S_GET_VALUE (frag
->tc_frag_data
.last_map_symbol
)
490 <= S_GET_VALUE (symbol
));
491 /* Remove the old one. */
492 if (S_GET_VALUE (frag
->tc_frag_data
.last_map_symbol
)
493 == S_GET_VALUE (symbol
))
494 symbol_remove (frag
->tc_frag_data
.last_map_symbol
,
495 &symbol_rootP
, &symbol_lastP
);
497 frag
->tc_frag_data
.last_map_symbol
= symbol
;
500 /* Set the mapping state for frag_now. */
503 riscv_mapping_state (enum riscv_seg_mstate to_state
,
506 enum riscv_seg_mstate from_state
=
507 seg_info (now_seg
)->tc_segment_info_data
.map_state
;
509 if (!SEG_NORMAL (now_seg
)
510 /* For now I only add the mapping symbols to text sections.
511 Therefore, the dis-assembler only show the actual contents
512 distribution for text. Other sections will be shown as
513 data without the details. */
514 || !subseg_text_p (now_seg
))
517 /* The mapping symbol should be emitted if not in the right
519 if (from_state
== to_state
)
522 valueT value
= (valueT
) (frag_now_fix () - max_chars
);
523 seg_info (now_seg
)->tc_segment_info_data
.map_state
= to_state
;
524 make_mapping_symbol (to_state
, value
, frag_now
);
527 /* Add the odd bytes of paddings for riscv_handle_align. */
530 riscv_add_odd_padding_symbol (fragS
*frag
)
532 /* If there was already a mapping symbol, it should be
533 removed in the make_mapping_symbol. */
534 make_mapping_symbol (MAP_DATA
, frag
->fr_fix
, frag
);
535 make_mapping_symbol (MAP_INSN
, frag
->fr_fix
+ 1, frag
);
538 /* Remove any excess mapping symbols generated for alignment frags in
539 SEC. We may have created a mapping symbol before a zero byte
540 alignment; remove it if there's a mapping symbol after the
544 riscv_check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
,
546 void *dummy ATTRIBUTE_UNUSED
)
548 segment_info_type
*seginfo
= seg_info (sec
);
551 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
554 for (fragp
= seginfo
->frchainP
->frch_root
;
556 fragp
= fragp
->fr_next
)
558 symbolS
*last
= fragp
->tc_frag_data
.last_map_symbol
;
559 fragS
*next
= fragp
->fr_next
;
561 if (last
== NULL
|| next
== NULL
)
564 /* Check the last mapping symbol if it is at the boundary of
566 if (S_GET_VALUE (last
) < next
->fr_address
)
568 know (S_GET_VALUE (last
) == next
->fr_address
);
572 if (next
->tc_frag_data
.first_map_symbol
!= NULL
)
574 /* The last mapping symbol overlaps with another one
575 which at the start of the next frag. */
576 symbol_remove (last
, &symbol_rootP
, &symbol_lastP
);
580 if (next
->fr_next
== NULL
)
582 /* The last mapping symbol is at the end of the section. */
583 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
584 symbol_remove (last
, &symbol_rootP
, &symbol_lastP
);
588 /* Since we may have empty frags without any mapping symbols,
589 keep looking until the non-empty frag. */
590 if (next
->fr_address
!= next
->fr_next
->fr_address
)
593 next
= next
->fr_next
;
595 while (next
!= NULL
);
599 /* The default target format to use. */
602 riscv_target_format (void)
604 if (target_big_endian
)
605 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
607 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
610 /* Return the length of instruction INSN. */
612 static inline unsigned int
613 insn_length (const struct riscv_cl_insn
*insn
)
615 return riscv_insn_length (insn
->insn_opcode
);
618 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
621 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
624 insn
->insn_opcode
= mo
->match
;
630 /* Install INSN at the location specified by its "frag" and "where" fields. */
633 install_insn (const struct riscv_cl_insn
*insn
)
635 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
636 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
639 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
640 and install the opcode in the new location. */
643 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
647 if (insn
->fixp
!= NULL
)
649 insn
->fixp
->fx_frag
= frag
;
650 insn
->fixp
->fx_where
= where
;
655 /* Add INSN to the end of the output. */
658 add_fixed_insn (struct riscv_cl_insn
*insn
)
660 char *f
= frag_more (insn_length (insn
));
661 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
665 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
666 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
668 frag_grow (max_chars
);
669 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
670 frag_var (rs_machine_dependent
, max_chars
, var
,
671 subtype
, symbol
, offset
, NULL
);
674 /* Compute the length of a branch sequence, and adjust the stored length
675 accordingly. If FRAGP is NULL, the worst-case length is returned. */
678 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
680 int jump
, rvc
, length
= 8;
685 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
686 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
687 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
689 /* Assume jumps are in range; the linker will catch any that aren't. */
690 length
= jump
? 4 : 8;
692 if (fragp
->fr_symbol
!= NULL
693 && S_IS_DEFINED (fragp
->fr_symbol
)
694 && !S_IS_WEAK (fragp
->fr_symbol
)
695 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
697 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
698 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
699 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
701 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
703 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
705 else if (!jump
&& rvc
)
710 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
715 /* Information about an opcode name, mnemonics and its value. */
722 /* List for all supported opcode name. */
723 static const struct opcode_name_t opcode_name_list
[] =
768 /* Hash table for lookup opcode name. */
769 static htab_t opcode_names_hash
= NULL
;
771 /* Initialization for hash table of opcode name. */
774 init_opcode_names_hash (void)
776 const struct opcode_name_t
*opcode
;
778 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
779 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
780 as_fatal (_("internal: duplicate %s"), opcode
->name
);
783 /* Find `s` is a valid opcode name or not, return the opcode name info
786 static const struct opcode_name_t
*
787 opcode_name_lookup (char **s
)
791 struct opcode_name_t
*o
;
793 /* Find end of name. */
795 if (is_name_beginner (*e
))
797 while (is_part_of_name (*e
))
800 /* Terminate name. */
804 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
806 /* Advance to next token if one was recognized. */
816 /* All RISC-V registers belong to one of these classes. */
828 static htab_t reg_names_hash
= NULL
;
829 static htab_t csr_extra_hash
= NULL
;
831 #define ENCODE_REG_HASH(cls, n) \
832 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
833 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
834 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
837 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
839 void *hash
= ENCODE_REG_HASH (class, n
);
840 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
841 as_fatal (_("internal: duplicate %s"), name
);
845 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
849 for (i
= 0; i
< n
; i
++)
850 hash_reg_name (class, names
[i
], i
);
853 /* Init hash table csr_extra_hash to handle CSR. */
856 riscv_init_csr_hash (const char *name
,
858 enum riscv_csr_class
class,
859 enum riscv_spec_class define_version
,
860 enum riscv_spec_class abort_version
)
862 struct riscv_csr_extra
*entry
, *pre_entry
;
863 bool need_enrty
= true;
866 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
867 while (need_enrty
&& entry
!= NULL
)
869 if (entry
->csr_class
== class
870 && entry
->address
== address
871 && entry
->define_version
== define_version
872 && entry
->abort_version
== abort_version
)
882 entry
= notes_alloc (sizeof (*entry
));
883 entry
->csr_class
= class;
884 entry
->address
= address
;
885 entry
->define_version
= define_version
;
886 entry
->abort_version
= abort_version
;
889 if (pre_entry
== NULL
)
890 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
892 pre_entry
->next
= entry
;
895 /* Return the CSR address after checking the ISA dependency and
896 the privileged spec version.
898 There are one warning and two errors for CSR,
900 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
901 or the privileged spec, report warning only if -mcsr-check is set.
902 Unknown CSR: the CSR has never been defined, report error.
903 Improper CSR: the CSR number over the range (> 0xfff), report error. */
906 riscv_csr_address (const char *csr_name
,
907 struct riscv_csr_extra
*entry
)
909 struct riscv_csr_extra
*saved_entry
= entry
;
910 enum riscv_csr_class csr_class
= entry
->csr_class
;
911 bool need_check_version
= false;
912 bool is_rv32_only
= false;
913 bool is_h_required
= false;
914 const char* extension
= NULL
;
922 need_check_version
= true;
940 case CSR_CLASS_SMSTATEEN
:
941 case CSR_CLASS_SMSTATEEN_AND_H
:
942 case CSR_CLASS_SMSTATEEN_32
:
943 case CSR_CLASS_SMSTATEEN_AND_H_32
:
944 is_rv32_only
= (csr_class
== CSR_CLASS_SMSTATEEN_32
945 || csr_class
== CSR_CLASS_SMSTATEEN_AND_H_32
);
946 is_h_required
= (csr_class
== CSR_CLASS_SMSTATEEN_AND_H
947 || csr_class
== CSR_CLASS_SMSTATEEN_AND_H_32
);
948 extension
= "smstateen";
950 case CSR_CLASS_SSCOFPMF_32
:
953 case CSR_CLASS_SSCOFPMF
:
954 extension
= "sscofpmf";
957 case CSR_CLASS_SSTC_AND_H
:
958 case CSR_CLASS_SSTC_32
:
959 case CSR_CLASS_SSTC_AND_H_32
:
960 is_rv32_only
= (csr_class
== CSR_CLASS_SSTC_32
961 || csr_class
== CSR_CLASS_SSTC_AND_H_32
);
962 is_h_required
= (csr_class
== CSR_CLASS_SSTC_AND_H
963 || csr_class
== CSR_CLASS_SSTC_AND_H_32
);
966 case CSR_CLASS_DEBUG
:
969 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
972 if (riscv_opts
.csr_check
)
974 if (is_rv32_only
&& xlen
!= 32)
975 as_warn (_("invalid CSR `%s', needs rv32i extension"), csr_name
);
976 if (is_h_required
&& !riscv_subset_supports (&riscv_rps_as
, "h"))
977 as_warn (_("invalid CSR `%s', needs `h' extension"), csr_name
);
979 if (extension
!= NULL
980 && !riscv_subset_supports (&riscv_rps_as
, extension
))
981 as_warn (_("invalid CSR `%s', needs `%s' extension"),
982 csr_name
, extension
);
985 while (entry
!= NULL
)
987 if (!need_check_version
988 || (default_priv_spec
>= entry
->define_version
989 && default_priv_spec
< entry
->abort_version
))
991 /* Find the CSR according to the specific version. */
992 return entry
->address
;
997 /* Can not find the CSR address from the chosen privileged version,
998 so use the newly defined value. */
999 if (riscv_opts
.csr_check
)
1001 const char *priv_name
= NULL
;
1002 RISCV_GET_PRIV_SPEC_NAME (priv_name
, default_priv_spec
);
1003 if (priv_name
!= NULL
)
1004 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
1005 csr_name
, priv_name
);
1008 return saved_entry
->address
;
1011 /* Return -1 if the CSR has never been defined. Otherwise, return
1015 reg_csr_lookup_internal (const char *s
)
1017 struct riscv_csr_extra
*r
=
1018 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
1023 return riscv_csr_address (s
, r
);
1027 reg_lookup_internal (const char *s
, enum reg_class
class)
1031 if (class == RCLASS_CSR
)
1032 return reg_csr_lookup_internal (s
);
1034 r
= str_hash_find (reg_names_hash
, s
);
1035 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
1038 if (riscv_subset_supports (&riscv_rps_as
, "e")
1039 && class == RCLASS_GPR
1040 && DECODE_REG_NUM (r
) > 15)
1043 return DECODE_REG_NUM (r
);
1047 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
1053 /* Find end of name. */
1055 if (is_name_beginner (*e
))
1057 while (is_part_of_name (*e
))
1060 /* Terminate name. */
1064 /* Look for the register. Advance to next token if one was recognized. */
1065 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
1075 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
1077 const char *p
= strchr (*s
, ',');
1078 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
1083 for (i
= 0; i
< size
; i
++)
1084 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
1094 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
1096 /* For consistency checking, verify that all bits are specified either
1097 by the match/mask part of the instruction definition, or by the
1098 operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
1101 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
1103 const char *oparg
, *opargStart
;
1104 insn_t used_bits
= opc
->mask
;
1106 insn_t required_bits
;
1109 insn_width
= 8 * riscv_insn_length (opc
->match
);
1111 insn_width
= 8 * length
;
1113 required_bits
= ~0ULL >> (64 - insn_width
);
1115 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
1117 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
1118 opc
->name
, opc
->args
);
1122 for (oparg
= opc
->args
; *oparg
; ++oparg
)
1130 case 'U': break; /* CRS1, constrained to equal RD. */
1131 case 'c': break; /* CRS1, constrained to equal sp. */
1132 case 'T': /* CRS2, floating point. */
1133 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
1134 case 'S': /* CRS1S, floating point. */
1135 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
1136 case 'w': break; /* CRS1S, constrained to equal RD. */
1137 case 'D': /* CRS2S, floating point. */
1138 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
1139 case 'x': break; /* CRS2S, constrained to equal RD. */
1140 case 'z': break; /* CRS2S, constrained to be x0. */
1141 case '>': /* CITYPE immediate, compressed shift. */
1142 case 'u': /* CITYPE immediate, compressed lui. */
1143 case 'v': /* CITYPE immediate, li to compressed lui. */
1144 case 'o': /* CITYPE immediate, allow zero. */
1145 case 'j': used_bits
|= ENCODE_CITYPE_IMM (-1U); break;
1146 case 'L': used_bits
|= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
1147 case 'm': used_bits
|= ENCODE_CITYPE_LWSP_IMM (-1U); break;
1148 case 'n': used_bits
|= ENCODE_CITYPE_LDSP_IMM (-1U); break;
1149 case '6': used_bits
|= ENCODE_CSSTYPE_IMM (-1U); break;
1150 case 'M': used_bits
|= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
1151 case 'N': used_bits
|= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
1152 case '8': used_bits
|= ENCODE_CIWTYPE_IMM (-1U); break;
1153 case 'K': used_bits
|= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
1154 /* CLTYPE and CSTYPE have the same immediate encoding. */
1155 case '5': used_bits
|= ENCODE_CLTYPE_IMM (-1U); break;
1156 case 'k': used_bits
|= ENCODE_CLTYPE_LW_IMM (-1U); break;
1157 case 'l': used_bits
|= ENCODE_CLTYPE_LD_IMM (-1U); break;
1158 case 'p': used_bits
|= ENCODE_CBTYPE_IMM (-1U); break;
1159 case 'a': used_bits
|= ENCODE_CJTYPE_IMM (-1U); break;
1160 case 'F': /* Compressed funct for .insn directive. */
1163 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
1164 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
1165 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
1166 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
1168 goto unknown_validate_operand
;
1172 goto unknown_validate_operand
;
1174 break; /* end RVC */
1179 case 'f': USE_BITS (OP_MASK_VD
, OP_SH_VD
); break;
1180 case 'e': USE_BITS (OP_MASK_VWD
, OP_SH_VWD
); break;
1181 case 's': USE_BITS (OP_MASK_VS1
, OP_SH_VS1
); break;
1182 case 't': USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1183 case 'u': USE_BITS (OP_MASK_VS1
, OP_SH_VS1
);
1184 USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1185 case 'v': USE_BITS (OP_MASK_VD
, OP_SH_VD
);
1186 USE_BITS (OP_MASK_VS1
, OP_SH_VS1
);
1187 USE_BITS (OP_MASK_VS2
, OP_SH_VS2
); break;
1189 case 'b': used_bits
|= ENCODE_RVV_VB_IMM (-1U); break;
1190 case 'c': used_bits
|= ENCODE_RVV_VC_IMM (-1U); break;
1193 case 'k': USE_BITS (OP_MASK_VIMM
, OP_SH_VIMM
); break;
1194 case 'm': USE_BITS (OP_MASK_VMASK
, OP_SH_VMASK
); break;
1196 goto unknown_validate_operand
;
1198 break; /* end RVV */
1202 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
1203 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
1204 case 'A': break; /* Macro operand, must be symbol. */
1205 case 'B': break; /* Macro operand, must be symbol or constant. */
1206 case 'I': break; /* Macro operand, must be constant. */
1207 case 'D': /* RD, floating point. */
1208 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
1209 case 'y': USE_BITS (OP_MASK_BS
, OP_SH_BS
); break;
1210 case 'Y': USE_BITS (OP_MASK_RNUM
, OP_SH_RNUM
); break;
1211 case 'Z': /* RS1, CSR number. */
1212 case 'S': /* RS1, floating point. */
1213 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1214 case 'U': /* RS1 and RS2 are the same, floating point. */
1215 USE_BITS (OP_MASK_RS1
, OP_SH_RS1
);
1217 case 'T': /* RS2, floating point. */
1218 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
1219 case 'R': /* RS3, floating point. */
1220 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
1221 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
1222 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
1223 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
1224 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
1225 case 'o': /* ITYPE immediate, load displacement. */
1226 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
1227 case 'a': used_bits
|= ENCODE_JTYPE_IMM (-1U); break;
1228 case 'p': used_bits
|= ENCODE_BTYPE_IMM (-1U); break;
1229 case 'f': /* Fall through. */
1230 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1231 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1232 case 'z': break; /* Zero immediate. */
1233 case '[': break; /* Unused operand. */
1234 case ']': break; /* Unused operand. */
1235 case '0': break; /* AMO displacement, must to zero. */
1236 case '1': break; /* Relaxation operand. */
1237 case 'F': /* Funct for .insn directive. */
1240 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1241 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1242 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1244 goto unknown_validate_operand
;
1247 case 'O': /* Opcode for .insn directive. */
1250 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1251 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1253 goto unknown_validate_operand
;
1257 unknown_validate_operand
:
1258 as_bad (_("internal: bad RISC-V opcode "
1259 "(unknown operand type `%s'): %s %s"),
1260 opargStart
, opc
->name
, opc
->args
);
1265 if (used_bits
!= required_bits
)
1267 as_bad (_("internal: bad RISC-V opcode "
1268 "(bits 0x%lx undefined): %s %s"),
1269 ~(unsigned long)(used_bits
& required_bits
),
1270 opc
->name
, opc
->args
);
1278 struct percent_op_match
1281 bfd_reloc_code_real_type reloc
;
1284 /* Common hash table initialization function for instruction and .insn
1288 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1289 bool insn_directive_p
)
1293 htab_t hash
= str_htab_create ();
1294 while (opcodes
[i
].name
)
1296 const char *name
= opcodes
[i
].name
;
1297 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1298 as_fatal (_("internal: duplicate %s"), name
);
1302 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1304 if (insn_directive_p
)
1305 length
= ((name
[0] == 'c') ? 2 : 4);
1307 length
= 0; /* Let assembler determine the length. */
1308 if (!validate_riscv_insn (&opcodes
[i
], length
))
1309 as_fatal (_("internal: broken assembler. "
1310 "No assembly attempted"));
1313 gas_assert (!insn_directive_p
);
1316 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1322 /* This function is called once, at assembler startup time. It should set up
1323 all the tables, etc. that the MD part of the assembler will need. */
1328 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1330 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1331 as_warn (_("could not set architecture and machine"));
1333 op_hash
= init_opcode_hash (riscv_opcodes
, false);
1334 insn_type_hash
= init_opcode_hash (riscv_insn_types
, true);
1336 reg_names_hash
= str_htab_create ();
1337 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1338 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1339 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1340 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1341 hash_reg_names (RCLASS_VECR
, riscv_vecr_names_numeric
, NVECR
);
1342 hash_reg_names (RCLASS_VECM
, riscv_vecm_names_numeric
, NVECM
);
1343 /* Add "fp" as an alias for "s0". */
1344 hash_reg_name (RCLASS_GPR
, "fp", 8);
1346 /* Create and insert CSR hash tables. */
1347 csr_extra_hash
= str_htab_create ();
1348 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1349 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1350 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1351 DECLARE_CSR(name, num, class, define_version, abort_version);
1352 #include "opcode/riscv-opc.h"
1355 opcode_names_hash
= str_htab_create ();
1356 init_opcode_names_hash ();
1358 /* Set the default alignment for the text section. */
1359 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1363 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1370 case BFD_RELOC_RISCV_HI20
:
1371 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1373 case BFD_RELOC_RISCV_LO12_S
:
1374 return ENCODE_STYPE_IMM (value
);
1376 case BFD_RELOC_RISCV_LO12_I
:
1377 return ENCODE_ITYPE_IMM (value
);
1384 /* Output an instruction. IP is the instruction information.
1385 ADDRESS_EXPR is an operand of the instruction to be used with
1389 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1390 bfd_reloc_code_real_type reloc_type
)
1392 dwarf2_emit_insn (0);
1394 if (reloc_type
!= BFD_RELOC_UNUSED
)
1396 reloc_howto_type
*howto
;
1398 gas_assert (address_expr
);
1399 if (reloc_type
== BFD_RELOC_12_PCREL
1400 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1402 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1403 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1404 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1406 if (now_seg
== absolute_section
)
1408 as_bad (_("relaxable branches not supported in absolute section"));
1412 add_relaxed_insn (ip
, worst_case
, best_case
,
1413 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1414 address_expr
->X_add_symbol
,
1415 address_expr
->X_add_number
);
1420 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1422 as_bad (_("internal: unsupported RISC-V relocation number %d"),
1425 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1426 bfd_get_reloc_size (howto
),
1427 address_expr
, false, reloc_type
);
1429 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1433 add_fixed_insn (ip
);
1436 /* We need to start a new frag after any instruction that can be
1437 optimized away or compressed by the linker during relaxation, to prevent
1438 the assembler from computing static offsets across such an instruction.
1439 This is necessary to get correct EH info. */
1440 if (reloc_type
== BFD_RELOC_RISCV_HI20
1441 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1442 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1443 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1445 frag_wane (frag_now
);
1450 /* Build an instruction created by a macro expansion. This is passed
1451 a pointer to the count of instructions created so far, an expression,
1452 the name of the instruction to build, an operand format string, and
1453 corresponding arguments. */
1456 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1458 const struct riscv_opcode
*mo
;
1459 struct riscv_cl_insn insn
;
1460 bfd_reloc_code_real_type r
;
1462 const char *fmtStart
;
1464 va_start (args
, fmt
);
1466 r
= BFD_RELOC_UNUSED
;
1467 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1470 /* Find a non-RVC variant of the instruction. append_insn will compress
1472 while (riscv_insn_length (mo
->match
) < 4)
1474 gas_assert (strcmp (name
, mo
->name
) == 0);
1476 create_insn (&insn
, mo
);
1486 INSERT_OPERAND (VD
, insn
, va_arg (args
, int));
1489 INSERT_OPERAND (VS1
, insn
, va_arg (args
, int));
1492 INSERT_OPERAND (VS2
, insn
, va_arg (args
, int));
1496 int reg
= va_arg (args
, int);
1499 INSERT_OPERAND (VMASK
, insn
, 1);
1504 INSERT_OPERAND (VMASK
, insn
, 0);
1508 goto unknown_macro_argument
;
1511 goto unknown_macro_argument
;
1516 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1519 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1522 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1528 gas_assert (ep
!= NULL
);
1529 r
= va_arg (args
, int);
1537 unknown_macro_argument
:
1538 as_fatal (_("internal: invalid macro argument `%s'"), fmtStart
);
1543 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1545 append_insn (&insn
, ep
, r
);
1548 /* Build an instruction created by a macro expansion. Like md_assemble but
1549 accept a printf-style format string and arguments. */
1552 md_assemblef (const char *format
, ...)
1558 va_start (ap
, format
);
1560 r
= vasprintf (&buf
, format
, ap
);
1563 as_fatal (_("internal: vasprintf failed"));
1571 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1575 normalize_constant_expr (expressionS
*ex
)
1579 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1580 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1581 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1585 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1586 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1589 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1592 if (ex
->X_op
== O_big
)
1593 as_bad (_("unsupported large constant"));
1594 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1595 as_bad (_("unknown CSR `%s'"),
1596 S_GET_NAME (ex
->X_add_symbol
));
1597 else if (ex
->X_op
!= O_constant
)
1598 as_bad (_("instruction %s requires absolute expression"),
1600 normalize_constant_expr (ex
);
1604 make_internal_label (void)
1606 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1610 /* Load an entry from the GOT. */
1613 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1614 const char *lo_insn
, const char *lo_pattern
,
1615 bfd_reloc_code_real_type hi_reloc
,
1616 bfd_reloc_code_real_type lo_reloc
)
1619 ep2
.X_op
= O_symbol
;
1620 ep2
.X_add_symbol
= make_internal_label ();
1621 ep2
.X_add_number
= 0;
1623 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1624 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1628 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1629 bfd_reloc_code_real_type hi_reloc
,
1630 bfd_reloc_code_real_type lo_reloc
)
1632 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1636 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1637 bfd_reloc_code_real_type hi_reloc
,
1638 bfd_reloc_code_real_type lo_reloc
)
1640 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1643 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1646 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1647 bfd_reloc_code_real_type reloc
)
1649 /* Ensure the jalr is emitted to the same frag as the auipc. */
1651 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1652 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1653 /* See comment at end of append_insn. */
1654 frag_wane (frag_now
);
1658 /* Load an integer constant into a register. */
1661 load_const (int reg
, expressionS
*ep
)
1663 int shift
= RISCV_IMM_BITS
;
1664 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1665 expressionS upper
= *ep
, lower
= *ep
;
1666 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1667 upper
.X_add_number
-= lower
.X_add_number
;
1669 if (ep
->X_op
!= O_constant
)
1671 as_bad (_("unsupported large constant"));
1675 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1677 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1678 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1681 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1682 load_const (reg
, &upper
);
1684 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1685 if (lower
.X_add_number
!= 0)
1686 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1687 lower
.X_add_number
);
1691 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1694 if (upper
.X_add_number
!= 0)
1696 /* Discard low part and zero-extend upper immediate. */
1697 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1699 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1703 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1704 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1705 lower
.X_add_number
);
1709 /* Zero extend and sign extend byte/half-word/word. */
1712 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bool sign
)
1716 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1717 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1721 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1722 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1726 /* Expand RISC-V Vector macros into one or more instructions. */
1729 vector_macro (struct riscv_cl_insn
*ip
)
1731 int vd
= (ip
->insn_opcode
>> OP_SH_VD
) & OP_MASK_VD
;
1732 int vs1
= (ip
->insn_opcode
>> OP_SH_VS1
) & OP_MASK_VS1
;
1733 int vs2
= (ip
->insn_opcode
>> OP_SH_VS2
) & OP_MASK_VS2
;
1734 int vm
= (ip
->insn_opcode
>> OP_SH_VMASK
) & OP_MASK_VMASK
;
1735 int vtemp
= (ip
->insn_opcode
>> OP_SH_VFUNCT6
) & OP_MASK_VFUNCT6
;
1736 int mask
= ip
->insn_mo
->mask
;
1744 macro_build (NULL
, "vmslt.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, -1);
1745 macro_build (NULL
, "vmnand.mm", "Vd,Vt,Vs", vd
, vd
, vd
);
1750 /* Masked. Have vtemp to avoid overlap constraints. */
1753 macro_build (NULL
, "vmslt.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1754 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vm
, vtemp
);
1758 /* Preserve the value of vd if not updating by vm. */
1759 macro_build (NULL
, "vmslt.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1760 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vtemp
, vm
, vtemp
);
1761 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1762 macro_build (NULL
, "vmor.mm", "Vd,Vt,Vs", vd
, vtemp
, vd
);
1767 /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
1768 macro_build (NULL
, "vmslt.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, vm
);
1769 macro_build (NULL
, "vmxor.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1772 as_bad (_("must provide temp if destination overlaps mask"));
1779 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, -1);
1780 macro_build (NULL
, "vmnand.mm", "Vd,Vt,Vs", vd
, vd
, vd
);
1785 /* Masked. Have vtemp to avoid overlap constraints. */
1788 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1789 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vm
, vtemp
);
1793 /* Preserve the value of vd if not updating by vm. */
1794 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,s", vtemp
, vs2
, vs1
);
1795 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vtemp
, vm
, vtemp
);
1796 macro_build (NULL
, "vmandnot.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1797 macro_build (NULL
, "vmor.mm", "Vd,Vt,Vs", vd
, vtemp
, vd
);
1802 /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
1803 macro_build (NULL
, "vmsltu.vx", "Vd,Vt,sVm", vd
, vs2
, vs1
, vm
);
1804 macro_build (NULL
, "vmxor.mm", "Vd,Vt,Vs", vd
, vd
, vm
);
1807 as_bad (_("must provide temp if destination overlaps mask"));
1815 /* Expand RISC-V assembly macros into one or more instructions. */
1818 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1819 bfd_reloc_code_real_type
*imm_reloc
)
1821 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1822 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1823 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1824 int mask
= ip
->insn_mo
->mask
;
1829 load_const (rd
, imm_expr
);
1834 /* Load the address of a symbol into a register. */
1835 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1836 as_bad (_("offset too large"));
1838 if (imm_expr
->X_op
== O_constant
)
1839 load_const (rd
, imm_expr
);
1840 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol. */
1841 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1842 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1843 else /* Local PIC symbol, or any non-PIC symbol. */
1844 pcrel_load (rd
, rd
, imm_expr
, "addi",
1845 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1849 pcrel_load (rd
, rd
, imm_expr
, "addi",
1850 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1854 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1855 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1859 pcrel_load (rd
, rd
, imm_expr
, "lb",
1860 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1864 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1865 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1869 pcrel_load (rd
, rd
, imm_expr
, "lh",
1870 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1874 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1875 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1879 pcrel_load (rd
, rd
, imm_expr
, "lw",
1880 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1884 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1885 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1889 pcrel_load (rd
, rd
, imm_expr
, "ld",
1890 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1894 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1895 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1899 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1900 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1904 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1905 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1909 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1910 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1914 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1915 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1919 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1920 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1924 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1925 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1929 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1930 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1934 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1938 riscv_ext (rd
, rs1
, xlen
- 16, false);
1942 riscv_ext (rd
, rs1
, xlen
- 32, false);
1946 riscv_ext (rd
, rs1
, xlen
- 8, true);
1950 riscv_ext (rd
, rs1
, xlen
- 16, true);
1959 pcrel_load (rd
, rs1
, imm_expr
, "flh",
1960 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1963 pcrel_store (rs2
, rs1
, imm_expr
, "fsh",
1964 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1968 as_bad (_("internal: macro %s not implemented"), ip
->insn_mo
->name
);
1973 static const struct percent_op_match percent_op_utype
[] =
1975 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1976 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1977 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1978 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1979 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1980 {"%hi", BFD_RELOC_RISCV_HI20
},
1984 static const struct percent_op_match percent_op_itype
[] =
1986 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1987 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1988 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1992 static const struct percent_op_match percent_op_stype
[] =
1994 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1995 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1996 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
2000 static const struct percent_op_match percent_op_rtype
[] =
2002 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
2006 static const struct percent_op_match percent_op_null
[] =
2011 /* Return true if *STR points to a relocation operator. When returning true,
2012 move *STR over the operator and store its relocation code in *RELOC.
2013 Leave both *STR and *RELOC alone when returning false. */
2016 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
2017 const struct percent_op_match
*percent_op
)
2019 for ( ; percent_op
->str
; percent_op
++)
2020 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
2022 int len
= strlen (percent_op
->str
);
2024 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
2027 *str
+= strlen (percent_op
->str
);
2028 *reloc
= percent_op
->reloc
;
2030 /* Check whether the output BFD supports this relocation.
2031 If not, issue an error and fall back on something safe. */
2032 if (*reloc
!= BFD_RELOC_UNUSED
2033 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
2035 as_bad ("internal: relocation %s isn't supported by the "
2036 "current ABI", percent_op
->str
);
2037 *reloc
= BFD_RELOC_UNUSED
;
2045 my_getExpression (expressionS
*ep
, char *str
)
2049 save_in
= input_line_pointer
;
2050 input_line_pointer
= str
;
2052 expr_end
= input_line_pointer
;
2053 input_line_pointer
= save_in
;
2056 /* Parse string STR as a 16-bit relocatable operand. Store the
2057 expression in *EP and the relocation, if any, in RELOC.
2058 Return the number of relocation operators used (0 or 1).
2060 On exit, EXPR_END points to the first character after the expression. */
2063 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
2064 char *str
, const struct percent_op_match
*percent_op
)
2067 unsigned crux_depth
, str_depth
, regno
;
2070 /* First, check for integer registers. No callers can accept a reg, but
2071 we need to avoid accidentally creating a useless undefined symbol below,
2072 if this is an instruction pattern that can't match. A glibc build fails
2073 if this is removed. */
2074 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
2076 ep
->X_op
= O_register
;
2077 ep
->X_add_number
= regno
;
2082 /* Search for the start of the main expression.
2084 End the loop with CRUX pointing to the start of the main expression and
2085 with CRUX_DEPTH containing the number of open brackets at that point. */
2092 crux_depth
= str_depth
;
2094 /* Skip over whitespace and brackets, keeping count of the number
2096 while (*str
== ' ' || *str
== '\t' || *str
== '(')
2102 && parse_relocation (&str
, reloc
, percent_op
));
2104 my_getExpression (ep
, crux
);
2107 /* Match every open bracket. */
2108 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
2113 as_bad ("unclosed '('");
2120 /* Parse opcode name, could be an mnemonics or number. */
2123 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
2124 char *str
, const struct percent_op_match
*percent_op
)
2126 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
2130 ep
->X_op
= O_constant
;
2131 ep
->X_add_number
= o
->val
;
2135 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
2138 /* Parse string STR as a vsetvli operand. Store the expression in *EP.
2139 On exit, EXPR_END points to the first character after the expression. */
2142 my_getVsetvliExpression (expressionS
*ep
, char *str
)
2144 unsigned int vsew_value
= 0, vlmul_value
= 0;
2145 unsigned int vta_value
= 0, vma_value
= 0;
2146 bfd_boolean vsew_found
= FALSE
, vlmul_found
= FALSE
;
2147 bfd_boolean vta_found
= FALSE
, vma_found
= FALSE
;
2149 if (arg_lookup (&str
, riscv_vsew
, ARRAY_SIZE (riscv_vsew
), &vsew_value
))
2154 as_bad (_("multiple vsew constants"));
2157 if (arg_lookup (&str
, riscv_vlmul
, ARRAY_SIZE (riscv_vlmul
), &vlmul_value
))
2162 as_bad (_("multiple vlmul constants"));
2165 if (arg_lookup (&str
, riscv_vta
, ARRAY_SIZE (riscv_vta
), &vta_value
))
2170 as_bad (_("multiple vta constants"));
2173 if (arg_lookup (&str
, riscv_vma
, ARRAY_SIZE (riscv_vma
), &vma_value
))
2178 as_bad (_("multiple vma constants"));
2182 if (vsew_found
|| vlmul_found
|| vta_found
|| vma_found
)
2184 ep
->X_op
= O_constant
;
2185 ep
->X_add_number
= (vlmul_value
<< OP_SH_VLMUL
)
2186 | (vsew_value
<< OP_SH_VSEW
)
2187 | (vta_value
<< OP_SH_VTA
)
2188 | (vma_value
<< OP_SH_VMA
);
2193 my_getExpression (ep
, str
);
2198 /* Detect and handle implicitly zero load-store offsets. For example,
2199 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return true if such
2200 an implicit offset was detected. */
2203 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
2205 /* Check whether there is only a single bracketed expression left.
2206 If so, it must be the base register and the constant must be zero. */
2207 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
2209 ep
->X_op
= O_constant
;
2210 ep
->X_add_number
= 0;
2217 /* All RISC-V CSR instructions belong to one of these classes. */
2226 /* Return which CSR instruction is checking. */
2228 static enum csr_insn_type
2229 riscv_csr_insn_type (insn_t insn
)
2231 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
2232 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
2234 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
2235 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
2237 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
2238 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
2241 return INSN_NOT_CSR
;
2244 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
2245 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
2246 CSR address is 0x3. */
2249 riscv_csr_read_only_check (insn_t insn
)
2251 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
2252 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
2253 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
2254 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
2257 && (((csr_insn
== INSN_CSRRS
2258 || csr_insn
== INSN_CSRRC
)
2260 || csr_insn
== INSN_CSRRW
))
2266 /* Return true if it is a privileged instruction. Otherwise, return false.
2268 uret is actually a N-ext instruction. So it is better to regard it as
2269 an user instruction rather than the priv instruction.
2271 hret is used to return from traps in H-mode. H-mode is removed since
2272 the v1.10 priv spec, but probably be added in the new hypervisor spec.
2273 Therefore, hret should be controlled by the hypervisor spec rather than
2274 priv spec in the future.
2276 dret is defined in the debug spec, so it should be checked in the future,
2280 riscv_is_priv_insn (insn_t insn
)
2282 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
2283 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
2284 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
2285 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
2286 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
2287 check it here to keep the compatible. */
2288 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
2291 /* This routine assembles an instruction into its binary format. As a
2292 side effect, it sets the global variable imm_reloc to the type of
2293 relocation to do if one of the operands is an address expression. */
2295 static struct riscv_ip_error
2296 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
2297 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
2299 /* The operand string defined in the riscv_opcodes. */
2300 const char *oparg
, *opargStart
;
2301 /* The parsed operands from assembly. */
2302 char *asarg
, *asargStart
;
2304 struct riscv_opcode
*insn
;
2307 const struct percent_op_match
*p
;
2308 struct riscv_ip_error error
;
2309 error
.msg
= "unrecognized opcode";
2310 error
.statement
= str
;
2311 error
.missing_ext
= NULL
;
2312 /* Indicate we are assembling instruction with CSR. */
2313 bool insn_with_csr
= false;
2315 /* Parse the name of the instruction. Terminate the string if whitespace
2316 is found so that str_hash_find only sees the name part of the string. */
2317 for (asarg
= str
; *asarg
!= '\0'; ++asarg
)
2318 if (ISSPACE (*asarg
))
2325 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
2328 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
2330 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
2333 if (!riscv_multi_subset_supports (&riscv_rps_as
, insn
->insn_class
))
2335 error
.missing_ext
= riscv_multi_subset_supports_ext (&riscv_rps_as
,
2340 /* Reset error message of the previous round. */
2341 error
.msg
= _("illegal operands");
2342 error
.missing_ext
= NULL
;
2343 create_insn (ip
, insn
);
2346 imm_expr
->X_op
= O_absent
;
2347 *imm_reloc
= BFD_RELOC_UNUSED
;
2348 p
= percent_op_itype
;
2350 for (oparg
= insn
->args
;; ++oparg
)
2353 asarg
+= strspn (asarg
, " \t");
2356 case '\0': /* End of args. */
2357 if (insn
->pinfo
!= INSN_MACRO
)
2359 if (!insn
->match_func (insn
, ip
->insn_opcode
))
2362 /* For .insn, insn->match and insn->mask are 0. */
2363 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
2369 if (riscv_is_priv_insn (ip
->insn_opcode
))
2370 explicit_priv_attr
= true;
2372 /* Check if we write a read-only CSR by the CSR
2375 && riscv_opts
.csr_check
2376 && !riscv_csr_read_only_check (ip
->insn_opcode
))
2378 /* Restore the character in advance, since we want to
2379 report the detailed warning message here. */
2381 *(asargStart
- 1) = save_c
;
2382 as_warn (_("read-only CSR is written `%s'"), str
);
2383 insn_with_csr
= false;
2386 /* The (segmant) load and store with EEW 64 cannot be used
2387 when zve32x is enabled. */
2388 if (ip
->insn_mo
->pinfo
& INSN_V_EEW64
2389 && riscv_subset_supports (&riscv_rps_as
, "zve32x")
2390 && !riscv_subset_supports (&riscv_rps_as
, "zve64x"))
2392 error
.msg
= _("illegal opcode for zve32x");
2398 /* Successful assembly. */
2400 insn_with_csr
= false;
2406 case 's': /* RS1 x8-x15. */
2407 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2408 || !(regno
>= 8 && regno
<= 15))
2410 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2412 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2413 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2414 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
2417 case 't': /* RS2 x8-x15. */
2418 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2419 || !(regno
>= 8 && regno
<= 15))
2421 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2423 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2424 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2425 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
2428 case 'U': /* RS1, constrained to equal RD. */
2429 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2430 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
2434 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
))
2436 INSERT_OPERAND (CRS2
, *ip
, regno
);
2438 case 'c': /* RS1, constrained to equal sp. */
2439 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2443 case 'z': /* RS2, constrained to equal x0. */
2444 if (!reg_lookup (&asarg
, RCLASS_GPR
, ®no
)
2448 case '>': /* Shift amount, 0 - (XLEN-1). */
2449 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2450 || imm_expr
->X_op
!= O_constant
2451 || (unsigned long) imm_expr
->X_add_number
>= xlen
)
2453 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2456 imm_expr
->X_op
= O_absent
;
2459 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2460 || imm_expr
->X_op
!= O_constant
2461 || imm_expr
->X_add_number
< 0
2462 || imm_expr
->X_add_number
>= 32
2463 || !VALID_CLTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2465 ip
->insn_opcode
|= ENCODE_CLTYPE_IMM (imm_expr
->X_add_number
);
2468 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2469 || imm_expr
->X_op
!= O_constant
2470 || imm_expr
->X_add_number
< 0
2471 || imm_expr
->X_add_number
>= 64
2472 || !VALID_CSSTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2474 ip
->insn_opcode
|= ENCODE_CSSTYPE_IMM (imm_expr
->X_add_number
);
2477 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2478 || imm_expr
->X_op
!= O_constant
2479 || imm_expr
->X_add_number
< 0
2480 || imm_expr
->X_add_number
>= 256
2481 || !VALID_CIWTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2483 ip
->insn_opcode
|= ENCODE_CIWTYPE_IMM (imm_expr
->X_add_number
);
2486 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2487 || imm_expr
->X_op
!= O_constant
2488 || imm_expr
->X_add_number
== 0
2489 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2491 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2494 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2496 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2497 || imm_expr
->X_op
!= O_constant
2498 || !VALID_CLTYPE_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2500 ip
->insn_opcode
|= ENCODE_CLTYPE_LW_IMM (imm_expr
->X_add_number
);
2503 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2505 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2506 || imm_expr
->X_op
!= O_constant
2507 || !VALID_CLTYPE_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2509 ip
->insn_opcode
|= ENCODE_CLTYPE_LD_IMM (imm_expr
->X_add_number
);
2512 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2514 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2515 || imm_expr
->X_op
!= O_constant
2516 || !VALID_CITYPE_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2519 ENCODE_CITYPE_LWSP_IMM (imm_expr
->X_add_number
);
2522 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2524 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2525 || imm_expr
->X_op
!= O_constant
2526 || !VALID_CITYPE_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2529 ENCODE_CITYPE_LDSP_IMM (imm_expr
->X_add_number
);
2532 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2533 || imm_expr
->X_op
!= O_constant
2534 /* C.addiw, c.li, and c.andi allow zero immediate.
2535 C.addi allows zero immediate as hint. Otherwise this
2537 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2539 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2542 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2543 || imm_expr
->X_op
!= O_constant
2544 || imm_expr
->X_add_number
== 0
2545 || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2548 ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2551 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2552 || imm_expr
->X_op
!= O_constant
2553 || !VALID_CITYPE_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2556 ENCODE_CITYPE_ADDI16SP_IMM (imm_expr
->X_add_number
);
2559 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2561 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2562 || imm_expr
->X_op
!= O_constant
2563 || !VALID_CSSTYPE_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2566 ENCODE_CSSTYPE_SWSP_IMM (imm_expr
->X_add_number
);
2569 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
2571 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2572 || imm_expr
->X_op
!= O_constant
2573 || !VALID_CSSTYPE_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2576 ENCODE_CSSTYPE_SDSP_IMM (imm_expr
->X_add_number
);
2579 p
= percent_op_utype
;
2580 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
2583 if (imm_expr
->X_op
!= O_constant
2584 || imm_expr
->X_add_number
<= 0
2585 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2586 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2587 && (imm_expr
->X_add_number
<
2588 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2590 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2593 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2594 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2595 || ((int32_t)imm_expr
->X_add_number
2596 != imm_expr
->X_add_number
))
2598 imm_expr
->X_add_number
=
2599 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2605 case 'S': /* Floating-point RS1 x8-x15. */
2606 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
)
2607 || !(regno
>= 8 && regno
<= 15))
2609 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2611 case 'D': /* Floating-point RS2 x8-x15. */
2612 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
)
2613 || !(regno
>= 8 && regno
<= 15))
2615 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2617 case 'T': /* Floating-point RS2. */
2618 if (!reg_lookup (&asarg
, RCLASS_FPR
, ®no
))
2620 INSERT_OPERAND (CRS2
, *ip
, regno
);
2626 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2627 || imm_expr
->X_op
!= O_constant
2628 || imm_expr
->X_add_number
< 0
2629 || imm_expr
->X_add_number
>= 64)
2631 as_bad (_("bad value for compressed funct6 "
2632 "field, value must be 0...63"));
2635 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2636 imm_expr
->X_op
= O_absent
;
2641 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2642 || imm_expr
->X_op
!= O_constant
2643 || imm_expr
->X_add_number
< 0
2644 || imm_expr
->X_add_number
>= 16)
2646 as_bad (_("bad value for compressed funct4 "
2647 "field, value must be 0...15"));
2650 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2651 imm_expr
->X_op
= O_absent
;
2656 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2657 || imm_expr
->X_op
!= O_constant
2658 || imm_expr
->X_add_number
< 0
2659 || imm_expr
->X_add_number
>= 8)
2661 as_bad (_("bad value for compressed funct3 "
2662 "field, value must be 0...7"));
2665 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2666 imm_expr
->X_op
= O_absent
;
2671 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
2672 || imm_expr
->X_op
!= O_constant
2673 || imm_expr
->X_add_number
< 0
2674 || imm_expr
->X_add_number
>= 4)
2676 as_bad (_("bad value for compressed funct2 "
2677 "field, value must be 0...3"));
2680 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2681 imm_expr
->X_op
= O_absent
;
2686 goto unknown_riscv_ip_operand
;
2691 goto unknown_riscv_ip_operand
;
2693 break; /* end RVC */
2699 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2701 INSERT_OPERAND (VD
, *ip
, regno
);
2704 case 'e': /* AMO VD */
2705 if (reg_lookup (&asarg
, RCLASS_GPR
, ®no
) && regno
== 0)
2706 INSERT_OPERAND (VWD
, *ip
, 0);
2707 else if (reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2709 INSERT_OPERAND (VWD
, *ip
, 1);
2710 INSERT_OPERAND (VD
, *ip
, regno
);
2716 case 'f': /* AMO VS3 */
2717 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2719 if (!EXTRACT_OPERAND (VWD
, ip
->insn_opcode
))
2720 INSERT_OPERAND (VD
, *ip
, regno
);
2723 /* VS3 must match VD. */
2724 if (EXTRACT_OPERAND (VD
, ip
->insn_opcode
) != regno
)
2730 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2732 INSERT_OPERAND (VS1
, *ip
, regno
);
2736 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2738 INSERT_OPERAND (VS2
, *ip
, regno
);
2741 case 'u': /* VS1 == VS2 */
2742 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2744 INSERT_OPERAND (VS1
, *ip
, regno
);
2745 INSERT_OPERAND (VS2
, *ip
, regno
);
2748 case 'v': /* VD == VS1 == VS2 */
2749 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
))
2751 INSERT_OPERAND (VD
, *ip
, regno
);
2752 INSERT_OPERAND (VS1
, *ip
, regno
);
2753 INSERT_OPERAND (VS2
, *ip
, regno
);
2756 /* The `V0` is carry-in register for v[m]adc and v[m]sbc,
2757 and is used to choose vs1/rs1/frs1/imm or vs2 for
2758 v[f]merge. It use the same encoding as the vector mask
2761 if (reg_lookup (&asarg
, RCLASS_VECR
, ®no
) && regno
== 0)
2765 case 'b': /* vtypei for vsetivli */
2766 my_getVsetvliExpression (imm_expr
, asarg
);
2767 check_absolute_expr (ip
, imm_expr
, FALSE
);
2768 if (!VALID_RVV_VB_IMM (imm_expr
->X_add_number
))
2769 as_bad (_("bad value for vsetivli immediate field, "
2770 "value must be 0..1023"));
2772 |= ENCODE_RVV_VB_IMM (imm_expr
->X_add_number
);
2773 imm_expr
->X_op
= O_absent
;
2777 case 'c': /* vtypei for vsetvli */
2778 my_getVsetvliExpression (imm_expr
, asarg
);
2779 check_absolute_expr (ip
, imm_expr
, FALSE
);
2780 if (!VALID_RVV_VC_IMM (imm_expr
->X_add_number
))
2781 as_bad (_("bad value for vsetvli immediate field, "
2782 "value must be 0..2047"));
2784 |= ENCODE_RVV_VC_IMM (imm_expr
->X_add_number
);
2785 imm_expr
->X_op
= O_absent
;
2789 case 'i': /* vector arith signed immediate */
2790 my_getExpression (imm_expr
, asarg
);
2791 check_absolute_expr (ip
, imm_expr
, FALSE
);
2792 if (imm_expr
->X_add_number
> 15
2793 || imm_expr
->X_add_number
< -16)
2794 as_bad (_("bad value for vector immediate field, "
2795 "value must be -16...15"));
2796 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
);
2797 imm_expr
->X_op
= O_absent
;
2801 case 'j': /* vector arith unsigned immediate */
2802 my_getExpression (imm_expr
, asarg
);
2803 check_absolute_expr (ip
, imm_expr
, FALSE
);
2804 if (imm_expr
->X_add_number
< 0
2805 || imm_expr
->X_add_number
>= 32)
2806 as_bad (_("bad value for vector immediate field, "
2807 "value must be 0...31"));
2808 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
);
2809 imm_expr
->X_op
= O_absent
;
2813 case 'k': /* vector arith signed immediate, minus 1 */
2814 my_getExpression (imm_expr
, asarg
);
2815 check_absolute_expr (ip
, imm_expr
, FALSE
);
2816 if (imm_expr
->X_add_number
> 16
2817 || imm_expr
->X_add_number
< -15)
2818 as_bad (_("bad value for vector immediate field, "
2819 "value must be -15...16"));
2820 INSERT_OPERAND (VIMM
, *ip
, imm_expr
->X_add_number
- 1);
2821 imm_expr
->X_op
= O_absent
;
2825 case 'm': /* optional vector mask */
2828 INSERT_OPERAND (VMASK
, *ip
, 1);
2831 else if (*asarg
== ',' && asarg
++
2832 && reg_lookup (&asarg
, RCLASS_VECM
, ®no
)
2835 INSERT_OPERAND (VMASK
, *ip
, 0);
2840 case 'M': /* required vector mask */
2841 if (reg_lookup (&asarg
, RCLASS_VECM
, ®no
) && regno
== 0)
2843 INSERT_OPERAND (VMASK
, *ip
, 0);
2848 case 'T': /* vector macro temporary register */
2849 if (!reg_lookup (&asarg
, RCLASS_VECR
, ®no
) || regno
== 0)
2851 /* Store it in the FUNCT6 field as we don't have anyplace
2852 else to store it. */
2853 INSERT_OPERAND (VFUNCT6
, *ip
, regno
);
2857 goto unknown_riscv_ip_operand
;
2859 break; /* end RVV */
2863 if (*asarg
++ == *oparg
)
2872 if (*asarg
++ == *oparg
)
2876 case '<': /* Shift amount, 0 - 31. */
2877 my_getExpression (imm_expr
, asarg
);
2878 check_absolute_expr (ip
, imm_expr
, false);
2879 if ((unsigned long) imm_expr
->X_add_number
> 31)
2880 as_bad (_("improper shift amount (%lu)"),
2881 (unsigned long) imm_expr
->X_add_number
);
2882 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2883 imm_expr
->X_op
= O_absent
;
2887 case '>': /* Shift amount, 0 - (XLEN-1). */
2888 my_getExpression (imm_expr
, asarg
);
2889 check_absolute_expr (ip
, imm_expr
, false);
2890 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2891 as_bad (_("improper shift amount (%lu)"),
2892 (unsigned long) imm_expr
->X_add_number
);
2893 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2894 imm_expr
->X_op
= O_absent
;
2898 case 'Z': /* CSRRxI immediate. */
2899 my_getExpression (imm_expr
, asarg
);
2900 check_absolute_expr (ip
, imm_expr
, false);
2901 if ((unsigned long) imm_expr
->X_add_number
> 31)
2902 as_bad (_("improper CSRxI immediate (%lu)"),
2903 (unsigned long) imm_expr
->X_add_number
);
2904 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2905 imm_expr
->X_op
= O_absent
;
2909 case 'E': /* Control register. */
2910 insn_with_csr
= true;
2911 explicit_priv_attr
= true;
2912 if (reg_lookup (&asarg
, RCLASS_CSR
, ®no
))
2913 INSERT_OPERAND (CSR
, *ip
, regno
);
2916 my_getExpression (imm_expr
, asarg
);
2917 check_absolute_expr (ip
, imm_expr
, true);
2918 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2919 as_bad (_("improper CSR address (%lu)"),
2920 (unsigned long) imm_expr
->X_add_number
);
2921 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2922 imm_expr
->X_op
= O_absent
;
2927 case 'm': /* Rounding mode. */
2928 if (arg_lookup (&asarg
, riscv_rm
,
2929 ARRAY_SIZE (riscv_rm
), ®no
))
2931 INSERT_OPERAND (RM
, *ip
, regno
);
2937 case 'Q': /* Fence predecessor/successor. */
2938 if (arg_lookup (&asarg
, riscv_pred_succ
,
2939 ARRAY_SIZE (riscv_pred_succ
), ®no
))
2942 INSERT_OPERAND (PRED
, *ip
, regno
);
2944 INSERT_OPERAND (SUCC
, *ip
, regno
);
2949 case 'd': /* Destination register. */
2950 case 's': /* Source register. */
2951 case 't': /* Target register. */
2953 if (reg_lookup (&asarg
, RCLASS_GPR
, ®no
))
2959 /* Now that we have assembled one operand, we use the args
2960 string to figure out where it goes in the instruction. */
2964 INSERT_OPERAND (RS1
, *ip
, regno
);
2967 INSERT_OPERAND (RD
, *ip
, regno
);
2970 INSERT_OPERAND (RS2
, *ip
, regno
);
2973 INSERT_OPERAND (RS3
, *ip
, regno
);
2980 case 'D': /* Floating point RD. */
2981 case 'S': /* Floating point RS1. */
2982 case 'T': /* Floating point RS2. */
2983 case 'U': /* Floating point RS1 and RS2. */
2984 case 'R': /* Floating point RS3. */
2985 if (reg_lookup (&asarg
,
2986 (riscv_subset_supports (&riscv_rps_as
, "zfinx")
2987 ? RCLASS_GPR
: RCLASS_FPR
), ®no
))
2995 INSERT_OPERAND (RD
, *ip
, regno
);
2998 INSERT_OPERAND (RS1
, *ip
, regno
);
3001 INSERT_OPERAND (RS1
, *ip
, regno
);
3004 INSERT_OPERAND (RS2
, *ip
, regno
);
3007 INSERT_OPERAND (RS3
, *ip
, regno
);
3015 my_getExpression (imm_expr
, asarg
);
3016 if (imm_expr
->X_op
!= O_big
3017 && imm_expr
->X_op
!= O_constant
)
3019 normalize_constant_expr (imm_expr
);
3024 my_getExpression (imm_expr
, asarg
);
3025 normalize_constant_expr (imm_expr
);
3026 /* The 'A' format specifier must be a symbol. */
3027 if (imm_expr
->X_op
!= O_symbol
)
3029 *imm_reloc
= BFD_RELOC_32
;
3034 my_getExpression (imm_expr
, asarg
);
3035 normalize_constant_expr (imm_expr
);
3036 /* The 'B' format specifier must be a symbol or a constant. */
3037 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
3039 if (imm_expr
->X_op
== O_symbol
)
3040 *imm_reloc
= BFD_RELOC_32
;
3044 case 'j': /* Sign-extended immediate. */
3045 p
= percent_op_itype
;
3046 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
3048 case 'q': /* Store displacement. */
3049 p
= percent_op_stype
;
3050 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
3052 case 'o': /* Load displacement. */
3053 p
= percent_op_itype
;
3054 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
3057 /* This is used for TLS, where the fourth operand is
3058 %tprel_add, to get a relocation applied to an add
3059 instruction, for relaxation to use. */
3060 p
= percent_op_rtype
;
3062 case '0': /* AMO displacement, which must be zero. */
3063 p
= percent_op_null
;
3065 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
3068 /* If this value won't fit into a 16 bit offset, then go
3069 find a macro that will generate the 32 bit offset
3071 if (!my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
3073 normalize_constant_expr (imm_expr
);
3074 if (imm_expr
->X_op
!= O_constant
3075 || (*oparg
== '0' && imm_expr
->X_add_number
!= 0)
3077 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
3078 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
3084 case 'p': /* PC-relative offset. */
3086 *imm_reloc
= BFD_RELOC_12_PCREL
;
3087 my_getExpression (imm_expr
, asarg
);
3091 case 'u': /* Upper 20 bits. */
3092 p
= percent_op_utype
;
3093 if (!my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
))
3095 if (imm_expr
->X_op
!= O_constant
)
3098 if (imm_expr
->X_add_number
< 0
3099 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
3100 as_bad (_("lui expression not in range 0..1048575"));
3102 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
3103 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
3108 case 'a': /* 20-bit PC-relative offset. */
3110 my_getExpression (imm_expr
, asarg
);
3112 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
3116 my_getExpression (imm_expr
, asarg
);
3118 if (strcmp (asarg
, "@plt") == 0)
3120 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
3124 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
3131 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, asarg
, p
)
3132 || imm_expr
->X_op
!= O_constant
3133 || imm_expr
->X_add_number
< 0
3134 || imm_expr
->X_add_number
>= 128
3135 || (imm_expr
->X_add_number
& 0x3) != 3)
3137 as_bad (_("bad value for opcode field, "
3138 "value must be 0...127 and "
3139 "lower 2 bits must be 0x3"));
3142 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
3143 imm_expr
->X_op
= O_absent
;
3148 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, asarg
, p
)
3149 || imm_expr
->X_op
!= O_constant
3150 || imm_expr
->X_add_number
< 0
3151 || imm_expr
->X_add_number
>= 3)
3153 as_bad (_("bad value for opcode field, "
3154 "value must be 0...2"));
3157 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
3158 imm_expr
->X_op
= O_absent
;
3163 goto unknown_riscv_ip_operand
;
3171 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3172 || imm_expr
->X_op
!= O_constant
3173 || imm_expr
->X_add_number
< 0
3174 || imm_expr
->X_add_number
>= 128)
3176 as_bad (_("bad value for funct7 field, "
3177 "value must be 0...127"));
3180 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
3181 imm_expr
->X_op
= O_absent
;
3186 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3187 || imm_expr
->X_op
!= O_constant
3188 || imm_expr
->X_add_number
< 0
3189 || imm_expr
->X_add_number
>= 8)
3191 as_bad (_("bad value for funct3 field, "
3192 "value must be 0...7"));
3195 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
3196 imm_expr
->X_op
= O_absent
;
3201 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3202 || imm_expr
->X_op
!= O_constant
3203 || imm_expr
->X_add_number
< 0
3204 || imm_expr
->X_add_number
>= 4)
3206 as_bad (_("bad value for funct2 field, "
3207 "value must be 0...3"));
3210 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
3211 imm_expr
->X_op
= O_absent
;
3216 goto unknown_riscv_ip_operand
;
3220 case 'y': /* bs immediate */
3221 my_getExpression (imm_expr
, asarg
);
3222 check_absolute_expr (ip
, imm_expr
, FALSE
);
3223 if ((unsigned long)imm_expr
->X_add_number
> 3)
3224 as_bad(_("Improper bs immediate (%lu)"),
3225 (unsigned long)imm_expr
->X_add_number
);
3226 INSERT_OPERAND(BS
, *ip
, imm_expr
->X_add_number
);
3227 imm_expr
->X_op
= O_absent
;
3231 case 'Y': /* rnum immediate */
3232 my_getExpression (imm_expr
, asarg
);
3233 check_absolute_expr (ip
, imm_expr
, FALSE
);
3234 if ((unsigned long)imm_expr
->X_add_number
> 10)
3235 as_bad(_("Improper rnum immediate (%lu)"),
3236 (unsigned long)imm_expr
->X_add_number
);
3237 INSERT_OPERAND(RNUM
, *ip
, imm_expr
->X_add_number
);
3238 imm_expr
->X_op
= O_absent
;
3243 if (my_getSmallExpression (imm_expr
, imm_reloc
, asarg
, p
)
3244 || imm_expr
->X_op
!= O_constant
3245 || imm_expr
->X_add_number
!= 0)
3248 imm_expr
->X_op
= O_absent
;
3251 case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */
3252 if (riscv_handle_implicit_zero_offset (imm_expr
, asarg
))
3254 my_getExpression (imm_expr
, asarg
);
3255 check_absolute_expr (ip
, imm_expr
, false);
3256 if (((unsigned) (imm_expr
->X_add_number
) & 0x1fU
)
3257 || imm_expr
->X_add_number
>= (signed) RISCV_IMM_REACH
/ 2
3258 || imm_expr
->X_add_number
< -(signed) RISCV_IMM_REACH
/ 2)
3259 as_bad (_("improper prefetch offset (%ld)"),
3260 (long) imm_expr
->X_add_number
);
3262 ENCODE_STYPE_IMM ((unsigned) (imm_expr
->X_add_number
) &
3264 imm_expr
->X_op
= O_absent
;
3269 unknown_riscv_ip_operand
:
3270 as_fatal (_("internal: unknown argument type `%s'"),
3276 insn_with_csr
= false;
3280 /* Restore the character we might have clobbered above. */
3282 *(asargStart
- 1) = save_c
;
3287 /* Similar to riscv_ip, but assembles an instruction according to the
3288 hardcode values of .insn directive. */
3291 riscv_ip_hardcode (char *str
,
3292 struct riscv_cl_insn
*ip
,
3293 expressionS
*imm_expr
,
3296 struct riscv_opcode
*insn
;
3297 insn_t values
[2] = {0, 0};
3298 unsigned int num
= 0;
3300 input_line_pointer
= str
;
3303 expression (imm_expr
);
3304 if (imm_expr
->X_op
!= O_constant
)
3306 /* The first value isn't constant, so it should be
3307 .insn <type> <operands>. We have been parsed it
3311 return _("values must be constant");
3313 values
[num
++] = (insn_t
) imm_expr
->X_add_number
;
3315 while (*input_line_pointer
++ == ',' && num
< 2);
3317 input_line_pointer
--;
3318 if (*input_line_pointer
!= '\0')
3319 return _("unrecognized values");
3321 insn
= XNEW (struct riscv_opcode
);
3322 insn
->match
= values
[num
- 1];
3323 create_insn (ip
, insn
);
3324 unsigned int bytes
= riscv_insn_length (insn
->match
);
3325 if ((bytes
< sizeof(values
[0]) && values
[num
- 1] >> (8 * bytes
) != 0)
3326 || (num
== 2 && values
[0] != bytes
))
3327 return _("value conflicts with instruction length");
3333 md_assemble (char *str
)
3335 struct riscv_cl_insn insn
;
3336 expressionS imm_expr
;
3337 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3339 /* The architecture and privileged elf attributes should be set
3340 before assembling. */
3341 if (!start_assemble
)
3343 start_assemble
= true;
3345 riscv_set_abi_by_arch ();
3346 if (!riscv_set_default_priv_spec (NULL
))
3350 riscv_mapping_state (MAP_INSN
, 0);
3352 const struct riscv_ip_error error
= riscv_ip (str
, &insn
, &imm_expr
,
3353 &imm_reloc
, op_hash
);
3357 if (error
.missing_ext
)
3358 as_bad ("%s `%s', extension `%s' required", error
.msg
,
3359 error
.statement
, error
.missing_ext
);
3361 as_bad ("%s `%s'", error
.msg
, error
.statement
);
3365 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3366 macro (&insn
, &imm_expr
, &imm_reloc
);
3368 append_insn (&insn
, &imm_expr
, imm_reloc
);
3372 md_atof (int type
, char *litP
, int *sizeP
)
3374 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
3378 md_number_to_chars (char *buf
, valueT val
, int n
)
3380 if (target_big_endian
)
3381 number_to_chars_bigendian (buf
, val
, n
);
3383 number_to_chars_littleendian (buf
, val
, n
);
3386 const char *md_shortopts
= "O::g::G:";
3390 OPTION_MARCH
= OPTION_MD_BASE
,
3397 OPTION_NO_ARCH_ATTR
,
3399 OPTION_NO_CSR_CHECK
,
3403 OPTION_LITTLE_ENDIAN
,
3407 struct option md_longopts
[] =
3409 {"march", required_argument
, NULL
, OPTION_MARCH
},
3410 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
3411 {"fpic", no_argument
, NULL
, OPTION_PIC
},
3412 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
3413 {"mabi", required_argument
, NULL
, OPTION_MABI
},
3414 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
3415 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
3416 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
3417 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
3418 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
3419 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
3420 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
3421 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
3422 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
3423 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
3425 {NULL
, no_argument
, NULL
, 0}
3427 size_t md_longopts_size
= sizeof (md_longopts
);
3430 md_parse_option (int c
, const char *arg
)
3435 default_arch_with_ext
= arg
;
3439 riscv_opts
.pic
= false;
3443 riscv_opts
.pic
= true;
3447 if (strcmp (arg
, "ilp32") == 0)
3448 riscv_set_abi (32, FLOAT_ABI_SOFT
, false);
3449 else if (strcmp (arg
, "ilp32e") == 0)
3450 riscv_set_abi (32, FLOAT_ABI_SOFT
, true);
3451 else if (strcmp (arg
, "ilp32f") == 0)
3452 riscv_set_abi (32, FLOAT_ABI_SINGLE
, false);
3453 else if (strcmp (arg
, "ilp32d") == 0)
3454 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, false);
3455 else if (strcmp (arg
, "ilp32q") == 0)
3456 riscv_set_abi (32, FLOAT_ABI_QUAD
, false);
3457 else if (strcmp (arg
, "lp64") == 0)
3458 riscv_set_abi (64, FLOAT_ABI_SOFT
, false);
3459 else if (strcmp (arg
, "lp64f") == 0)
3460 riscv_set_abi (64, FLOAT_ABI_SINGLE
, false);
3461 else if (strcmp (arg
, "lp64d") == 0)
3462 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, false);
3463 else if (strcmp (arg
, "lp64q") == 0)
3464 riscv_set_abi (64, FLOAT_ABI_QUAD
, false);
3467 explicit_mabi
= true;
3471 riscv_opts
.relax
= true;
3474 case OPTION_NO_RELAX
:
3475 riscv_opts
.relax
= false;
3478 case OPTION_ARCH_ATTR
:
3479 riscv_opts
.arch_attr
= true;
3482 case OPTION_NO_ARCH_ATTR
:
3483 riscv_opts
.arch_attr
= false;
3486 case OPTION_CSR_CHECK
:
3487 riscv_opts
.csr_check
= true;
3490 case OPTION_NO_CSR_CHECK
:
3491 riscv_opts
.csr_check
= false;
3494 case OPTION_MISA_SPEC
:
3495 return riscv_set_default_isa_spec (arg
);
3497 case OPTION_MPRIV_SPEC
:
3498 return riscv_set_default_priv_spec (arg
);
3500 case OPTION_BIG_ENDIAN
:
3501 target_big_endian
= 1;
3504 case OPTION_LITTLE_ENDIAN
:
3505 target_big_endian
= 0;
3516 riscv_after_parse_args (void)
3518 /* The --with-arch is optional for now, so we still need to set the xlen
3519 according to the default_arch, which is set by the --target. */
3522 if (strcmp (default_arch
, "riscv32") == 0)
3524 else if (strcmp (default_arch
, "riscv64") == 0)
3527 as_bad ("unknown default architecture `%s'", default_arch
);
3530 /* Set default specs. */
3531 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
3532 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
3533 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
3534 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
3536 riscv_set_arch (default_arch_with_ext
);
3538 /* If the CIE to be produced has not been overridden on the command line,
3539 then produce version 3 by default. This allows us to use the full
3540 range of registers in a .cfi_return_column directive. */
3541 if (flag_dwarf_cie_version
== -1)
3542 flag_dwarf_cie_version
= 3;
3546 md_pcrel_from (fixS
*fixP
)
3548 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3551 /* Apply a fixup to the object file. */
3554 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
3556 unsigned int subtype
;
3557 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
3558 bool relaxable
= false;
3562 /* Remember value for tc_gen_reloc. */
3563 fixP
->fx_addnumber
= *valP
;
3565 switch (fixP
->fx_r_type
)
3567 case BFD_RELOC_RISCV_HI20
:
3568 case BFD_RELOC_RISCV_LO12_I
:
3569 case BFD_RELOC_RISCV_LO12_S
:
3570 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
3571 | bfd_getl32 (buf
), buf
);
3572 if (fixP
->fx_addsy
== NULL
)
3573 fixP
->fx_done
= true;
3577 case BFD_RELOC_RISCV_GOT_HI20
:
3578 case BFD_RELOC_RISCV_ADD8
:
3579 case BFD_RELOC_RISCV_ADD16
:
3580 case BFD_RELOC_RISCV_ADD32
:
3581 case BFD_RELOC_RISCV_ADD64
:
3582 case BFD_RELOC_RISCV_SUB6
:
3583 case BFD_RELOC_RISCV_SUB8
:
3584 case BFD_RELOC_RISCV_SUB16
:
3585 case BFD_RELOC_RISCV_SUB32
:
3586 case BFD_RELOC_RISCV_SUB64
:
3587 case BFD_RELOC_RISCV_RELAX
:
3590 case BFD_RELOC_RISCV_TPREL_HI20
:
3591 case BFD_RELOC_RISCV_TPREL_LO12_I
:
3592 case BFD_RELOC_RISCV_TPREL_LO12_S
:
3593 case BFD_RELOC_RISCV_TPREL_ADD
:
3597 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
3598 case BFD_RELOC_RISCV_TLS_GD_HI20
:
3599 case BFD_RELOC_RISCV_TLS_DTPREL32
:
3600 case BFD_RELOC_RISCV_TLS_DTPREL64
:
3601 if (fixP
->fx_addsy
!= NULL
)
3602 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3604 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3605 _("TLS relocation against a constant"));
3609 /* Use pc-relative relocation for FDE initial location.
3610 The symbol address in .eh_frame may be adjusted in
3611 _bfd_elf_discard_section_eh_frame, and the content of
3612 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
3613 Therefore, we cannot insert a relocation whose addend symbol is
3614 in .eh_frame. Othrewise, the value may be adjusted twice. */
3615 if (fixP
->fx_addsy
&& fixP
->fx_subsy
3616 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
3617 && strcmp (sub_segment
->name
, ".eh_frame") == 0
3618 && S_GET_VALUE (fixP
->fx_subsy
)
3619 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
3621 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
3622 fixP
->fx_subsy
= NULL
;
3629 case BFD_RELOC_RISCV_CFA
:
3630 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
3632 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3633 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
3634 fixP
->fx_next
->fx_subsy
= NULL
;
3635 fixP
->fx_next
->fx_offset
= 0;
3636 fixP
->fx_subsy
= NULL
;
3638 switch (fixP
->fx_r_type
)
3641 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
3642 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
3646 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
3647 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3651 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
3652 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3656 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
3657 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3660 case BFD_RELOC_RISCV_CFA
:
3661 /* Load the byte to get the subtype. */
3662 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
3663 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
3666 case DW_CFA_advance_loc1
:
3667 fixP
->fx_where
= loc
+ 1;
3668 fixP
->fx_next
->fx_where
= loc
+ 1;
3669 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
3670 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3673 case DW_CFA_advance_loc2
:
3675 fixP
->fx_next
->fx_size
= 2;
3676 fixP
->fx_where
= loc
+ 1;
3677 fixP
->fx_next
->fx_where
= loc
+ 1;
3678 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
3679 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3682 case DW_CFA_advance_loc4
:
3684 fixP
->fx_next
->fx_size
= 4;
3685 fixP
->fx_where
= loc
;
3686 fixP
->fx_next
->fx_where
= loc
;
3687 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
3688 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3692 if (subtype
< 0x80 && (subtype
& 0x40))
3694 /* DW_CFA_advance_loc */
3695 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
3696 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
3697 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
3698 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
3701 as_fatal (_("internal: bad CFA value #%d"), subtype
);
3707 /* This case is unreachable. */
3714 /* If we are deleting this reloc entry, we must fill in the
3715 value now. This can happen if we have a .word which is not
3716 resolved when it appears but is later defined. */
3717 if (fixP
->fx_addsy
== NULL
)
3719 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
3720 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3725 case BFD_RELOC_RISCV_JMP
:
3728 /* Fill in a tentative value to improve objdump readability. */
3729 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3730 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3731 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_JTYPE_IMM (delta
), buf
);
3735 case BFD_RELOC_12_PCREL
:
3738 /* Fill in a tentative value to improve objdump readability. */
3739 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3740 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3741 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_BTYPE_IMM (delta
), buf
);
3745 case BFD_RELOC_RISCV_RVC_BRANCH
:
3748 /* Fill in a tentative value to improve objdump readability. */
3749 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3750 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3751 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CBTYPE_IMM (delta
), buf
);
3755 case BFD_RELOC_RISCV_RVC_JUMP
:
3758 /* Fill in a tentative value to improve objdump readability. */
3759 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3760 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3761 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CJTYPE_IMM (delta
), buf
);
3765 case BFD_RELOC_RISCV_CALL
:
3766 case BFD_RELOC_RISCV_CALL_PLT
:
3770 case BFD_RELOC_RISCV_PCREL_HI20
:
3771 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3772 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3773 relaxable
= riscv_opts
.relax
;
3776 case BFD_RELOC_RISCV_ALIGN
:
3780 /* We ignore generic BFD relocations we don't know about. */
3781 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3782 as_fatal (_("internal: bad relocation #%d"), fixP
->fx_r_type
);
3785 if (fixP
->fx_subsy
!= NULL
)
3786 as_bad_subtract (fixP
);
3788 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3789 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3791 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3792 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3793 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3794 fixP
->fx_next
->fx_size
= 0;
3798 /* Because the value of .cfi_remember_state may changed after relaxation,
3799 we insert a fix to relocate it again in link-time. */
3802 riscv_pre_output_hook (void)
3804 const frchainS
*frch
;
3807 /* Save the current segment info. */
3809 subsegT subseg
= now_subseg
;
3811 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3812 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3816 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3818 if (frag
->fr_type
== rs_cfa
)
3821 expressionS
*symval
;
3823 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3824 exp
.X_op
= O_subtract
;
3825 exp
.X_add_symbol
= symval
->X_add_symbol
;
3826 exp
.X_add_number
= 0;
3827 exp
.X_op_symbol
= symval
->X_op_symbol
;
3829 /* We must set the segment before creating a frag after all
3830 frag chains have been chained together. */
3831 subseg_set (s
, frch
->frch_subseg
);
3833 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3834 BFD_RELOC_RISCV_CFA
);
3839 /* Restore the original segment info. */
3840 subseg_set (seg
, subseg
);
3843 /* Handle the .option pseudo-op. */
3846 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3848 char *name
= input_line_pointer
, ch
;
3850 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3851 ++input_line_pointer
;
3852 ch
= *input_line_pointer
;
3853 *input_line_pointer
= '\0';
3855 if (strcmp (name
, "rvc") == 0)
3857 riscv_update_subset (&riscv_rps_as
, "+c");
3858 riscv_set_rvc (true);
3860 else if (strcmp (name
, "norvc") == 0)
3862 riscv_update_subset (&riscv_rps_as
, "-c");
3863 riscv_set_rvc (false);
3865 else if (strcmp (name
, "pic") == 0)
3866 riscv_opts
.pic
= true;
3867 else if (strcmp (name
, "nopic") == 0)
3868 riscv_opts
.pic
= false;
3869 else if (strcmp (name
, "relax") == 0)
3870 riscv_opts
.relax
= true;
3871 else if (strcmp (name
, "norelax") == 0)
3872 riscv_opts
.relax
= false;
3873 else if (strcmp (name
, "csr-check") == 0)
3874 riscv_opts
.csr_check
= true;
3875 else if (strcmp (name
, "no-csr-check") == 0)
3876 riscv_opts
.csr_check
= false;
3877 else if (strncmp (name
, "arch,", 5) == 0)
3880 if (ISSPACE (*name
) && *name
!= '\0')
3882 riscv_update_subset (&riscv_rps_as
, name
);
3884 riscv_set_rvc (false);
3885 if (riscv_subset_supports (&riscv_rps_as
, "c"))
3886 riscv_set_rvc (true);
3888 else if (strcmp (name
, "push") == 0)
3890 struct riscv_option_stack
*s
;
3892 s
= XNEW (struct riscv_option_stack
);
3893 s
->next
= riscv_opts_stack
;
3894 s
->options
= riscv_opts
;
3895 s
->subset_list
= riscv_subsets
;
3896 riscv_opts_stack
= s
;
3897 riscv_subsets
= riscv_copy_subset_list (s
->subset_list
);
3898 riscv_rps_as
.subset_list
= riscv_subsets
;
3900 else if (strcmp (name
, "pop") == 0)
3902 struct riscv_option_stack
*s
;
3904 s
= riscv_opts_stack
;
3906 as_bad (_(".option pop with no .option push"));
3909 riscv_subset_list_t
*release_subsets
= riscv_subsets
;
3910 riscv_opts_stack
= s
->next
;
3911 riscv_opts
= s
->options
;
3912 riscv_subsets
= s
->subset_list
;
3913 riscv_rps_as
.subset_list
= riscv_subsets
;
3914 riscv_release_subset_list (release_subsets
);
3920 as_warn (_("unrecognized .option directive: %s\n"), name
);
3922 *input_line_pointer
= ch
;
3923 demand_empty_rest_of_line ();
3926 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3927 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3928 use in DWARF debug information. */
3931 s_dtprel (int bytes
)
3938 if (ex
.X_op
!= O_symbol
)
3940 as_bad (_("unsupported use of %s"), (bytes
== 8
3943 ignore_rest_of_line ();
3946 p
= frag_more (bytes
);
3947 md_number_to_chars (p
, 0, bytes
);
3948 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, false,
3950 ? BFD_RELOC_RISCV_TLS_DTPREL64
3951 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3953 demand_empty_rest_of_line ();
3956 /* Handle the .bss pseudo-op. */
3959 s_bss (int ignore ATTRIBUTE_UNUSED
)
3961 subseg_set (bss_section
, 0);
3962 demand_empty_rest_of_line ();
3966 riscv_make_nops (char *buf
, bfd_vma bytes
)
3970 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3971 means we are not within a valid instruction sequence. It is thus safe
3972 to use a zero byte, even though that is not a valid instruction. */
3976 /* Use at most one 2-byte NOP. */
3977 if ((bytes
- i
) % 4 == 2)
3979 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
3983 /* Fill the remainder with 4-byte NOPs. */
3984 for ( ; i
< bytes
; i
+= 4)
3985 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
3988 /* Called from md_do_align. Used to create an alignment frag in a
3989 code section by emitting a worst-case NOP sequence that the linker
3990 will later relax to the correct number of NOPs. We can't compute
3991 the correct alignment now because of other linker relaxations. */
3994 riscv_frag_align_code (int n
)
3996 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3997 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3998 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
4002 /* If we are moving to a smaller alignment than the instruction size, then no
4003 alignment is required. */
4004 if (bytes
<= insn_alignment
)
4007 /* When not relaxing, riscv_handle_align handles code alignment. */
4008 if (!riscv_opts
.relax
)
4011 nops
= frag_more (worst_case_bytes
);
4013 ex
.X_op
= O_constant
;
4014 ex
.X_add_number
= worst_case_bytes
;
4016 riscv_make_nops (nops
, worst_case_bytes
);
4018 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
4019 &ex
, false, BFD_RELOC_RISCV_ALIGN
);
4021 riscv_mapping_state (MAP_INSN
, worst_case_bytes
);
4023 /* We need to start a new frag after the alignment which may be removed by
4024 the linker, to prevent the assembler from computing static offsets.
4025 This is necessary to get correct EH info. */
4026 frag_wane (frag_now
);
4032 /* Implement HANDLE_ALIGN. */
4035 riscv_handle_align (fragS
*fragP
)
4037 switch (fragP
->fr_type
)
4040 /* When relaxing, riscv_frag_align_code handles code alignment. */
4041 if (!riscv_opts
.relax
)
4043 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
4044 - fragP
->fr_address
- fragP
->fr_fix
);
4045 /* We have 4 byte uncompressed nops. */
4046 bfd_signed_vma size
= 4;
4047 bfd_signed_vma excess
= bytes
% size
;
4048 bfd_boolean odd_padding
= (excess
% 2 == 1);
4049 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
4054 /* Insert zeros or compressed nops to get 4 byte alignment. */
4058 riscv_add_odd_padding_symbol (fragP
);
4059 riscv_make_nops (p
, excess
);
4060 fragP
->fr_fix
+= excess
;
4064 /* The frag will be changed to `rs_fill` later. The function
4065 `write_contents` will try to fill the remaining spaces
4066 according to the patterns we give. In this case, we give
4067 a 4 byte uncompressed nop as the pattern, and set the size
4068 of the pattern into `fr_var`. The nop will be output to the
4069 file `fr_offset` times. However, `fr_offset` could be zero
4070 if we don't need to pad the boundary finally. */
4071 riscv_make_nops (p
, size
);
4072 fragP
->fr_var
= size
;
4081 /* This usually called from frag_var. */
4084 riscv_init_frag (fragS
* fragP
, int max_chars
)
4086 /* Do not add mapping symbol to debug sections. */
4087 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
4090 switch (fragP
->fr_type
)
4095 riscv_mapping_state (MAP_DATA
, max_chars
);
4098 riscv_mapping_state (MAP_INSN
, max_chars
);
4106 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
4108 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, false));
4111 /* Translate internal representation of relocation info to BFD target
4115 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
4117 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
4119 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4120 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4121 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4122 reloc
->addend
= fixp
->fx_addnumber
;
4124 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
4125 if (reloc
->howto
== NULL
)
4127 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
4128 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
4130 /* We don't have R_RISCV_8/16, but for this special case,
4131 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
4135 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4136 _("cannot represent %s relocation in object file"),
4137 bfd_get_reloc_code_name (fixp
->fx_r_type
));
4145 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
4147 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
4149 offsetT old_var
= fragp
->fr_var
;
4150 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, true);
4151 return fragp
->fr_var
- old_var
;
4157 /* Expand far branches to multi-instruction sequences. */
4160 md_convert_frag_branch (fragS
*fragp
)
4168 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
4170 exp
.X_op
= O_symbol
;
4171 exp
.X_add_symbol
= fragp
->fr_symbol
;
4172 exp
.X_add_number
= fragp
->fr_offset
;
4174 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
4176 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
4178 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
4182 /* Expand the RVC branch into a RISC-V one. */
4183 insn
= bfd_getl16 (buf
);
4184 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
4185 if ((insn
& MASK_C_J
) == MATCH_C_J
)
4187 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
4188 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
4189 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
4190 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
4191 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
4192 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
4195 bfd_putl32 (insn
, buf
);
4199 /* Invert the branch condition. Branch over the jump. */
4200 insn
= bfd_getl16 (buf
);
4201 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
4202 insn
|= ENCODE_CBTYPE_IMM (6);
4203 bfd_putl16 (insn
, buf
);
4208 /* Just keep the RVC branch. */
4209 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
4210 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
4211 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4212 2, &exp
, false, reloc
);
4221 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
4224 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
4226 /* Invert the branch condition. Branch over the jump. */
4227 insn
= bfd_getl32 (buf
);
4228 insn
^= MATCH_BEQ
^ MATCH_BNE
;
4229 insn
|= ENCODE_BTYPE_IMM (8);
4230 bfd_putl32 (insn
, buf
);
4234 /* Jump to the target. */
4235 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4236 4, &exp
, false, BFD_RELOC_RISCV_JMP
);
4237 bfd_putl32 (MATCH_JAL
, buf
);
4242 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
4243 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
4244 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
4245 4, &exp
, false, reloc
);
4254 fixp
->fx_file
= fragp
->fr_file
;
4255 fixp
->fx_line
= fragp
->fr_line
;
4257 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
4258 + fragp
->fr_fix
+ fragp
->fr_var
);
4260 fragp
->fr_fix
+= fragp
->fr_var
;
4263 /* Relax a machine dependent frag. This returns the amount by which
4264 the current size of the frag should change. */
4267 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
4270 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
4271 md_convert_frag_branch (fragp
);
4275 md_show_usage (FILE *stream
)
4277 fprintf (stream
, _("\
4279 -fpic or -fPIC generate position-independent code\n\
4280 -fno-pic don't generate position-independent code (default)\n\
4281 -march=ISA set the RISC-V architecture\n\
4282 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
4283 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11, 1.12)\n\
4284 -mabi=ABI set the RISC-V ABI\n\
4285 -mrelax enable relax (default)\n\
4286 -mno-relax disable relax\n\
4287 -march-attr generate RISC-V arch attribute\n\
4288 -mno-arch-attr don't generate RISC-V arch attribute\n\
4289 -mcsr-check enable the csr ISA and privilege spec version checks\n\
4290 -mno-csr-check disable the csr ISA and privilege spec version checks (default)\n\
4291 -mbig-endian assemble for big-endian\n\
4292 -mlittle-endian assemble for little-endian\n\
4296 /* Standard calling conventions leave the CFA at SP on entry. */
4299 riscv_cfi_frame_initial_instructions (void)
4301 cfi_add_CFA_def_cfa_register (X_SP
);
4305 tc_riscv_regname_to_dw2regnum (char *regname
)
4309 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
4312 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
4315 /* CSRs are numbered 4096 -> 8191. */
4316 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
4319 as_bad (_("unknown register `%s'"), regname
);
4324 riscv_elf_final_processing (void)
4326 riscv_set_abi_by_arch ();
4327 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
4330 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
4331 since these directives break relaxation when used with symbol deltas. */
4334 s_riscv_leb128 (int sign
)
4337 char *save_in
= input_line_pointer
;
4340 if (exp
.X_op
!= O_constant
)
4341 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
4342 demand_empty_rest_of_line ();
4344 input_line_pointer
= save_in
;
4345 return s_leb128 (sign
);
4348 /* Parse the .insn directive. There are three formats,
4349 Format 1: .insn <type> <operand1>, <operand2>, ...
4350 Format 2: .insn <length>, <value>
4351 Format 3: .insn <value>. */
4354 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
4356 char *str
= input_line_pointer
;
4357 struct riscv_cl_insn insn
;
4358 expressionS imm_expr
;
4359 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
4362 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4363 ++input_line_pointer
;
4365 save_c
= *input_line_pointer
;
4366 *input_line_pointer
= '\0';
4368 riscv_mapping_state (MAP_INSN
, 0);
4370 struct riscv_ip_error error
= riscv_ip (str
, &insn
, &imm_expr
,
4371 &imm_reloc
, insn_type_hash
);
4374 char *save_in
= input_line_pointer
;
4375 error
.msg
= riscv_ip_hardcode (str
, &insn
, &imm_expr
, error
.msg
);
4376 input_line_pointer
= save_in
;
4381 if (error
.missing_ext
)
4382 as_bad ("%s `%s', extension `%s' required", error
.msg
, error
.statement
,
4385 as_bad ("%s `%s'", error
.msg
, error
.statement
);
4389 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
4390 append_insn (&insn
, &imm_expr
, imm_reloc
);
4393 *input_line_pointer
= save_c
;
4394 demand_empty_rest_of_line ();
4397 /* Update architecture and privileged elf attributes. If we don't set
4398 them, then try to output the default ones. */
4401 riscv_write_out_attrs (void)
4403 const char *arch_str
, *priv_str
, *p
;
4404 /* versions[0]: major version.
4405 versions[1]: minor version.
4406 versions[2]: revision version. */
4407 unsigned versions
[3] = {0}, number
= 0;
4410 /* Re-write architecture elf attribute. */
4411 arch_str
= riscv_arch_str (xlen
, riscv_subsets
);
4412 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
4413 xfree ((void *) arch_str
);
4415 /* For the file without any instruction, we don't set the default_priv_spec
4416 according to the privileged elf attributes since the md_assemble isn't
4419 && !riscv_set_default_priv_spec (NULL
))
4422 /* If we already have set privileged elf attributes, then no need to do
4423 anything. Otherwise, don't generate or update them when no CSR and
4424 privileged instructions are used. */
4425 if (!explicit_priv_attr
)
4428 RISCV_GET_PRIV_SPEC_NAME (priv_str
, default_priv_spec
);
4430 for (i
= 0; *p
; ++p
)
4432 if (*p
== '.' && i
< 3)
4434 versions
[i
++] = number
;
4437 else if (ISDIGIT (*p
))
4438 number
= (number
* 10) + (*p
- '0');
4441 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str
);
4445 versions
[i
] = number
;
4447 /* Re-write privileged elf attributes. */
4448 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
4449 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
4450 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
4453 /* Add the default contents for the .riscv.attributes section. */
4456 riscv_set_public_attributes (void)
4458 if (riscv_opts
.arch_attr
|| explicit_attr
)
4459 riscv_write_out_attrs ();
4462 /* Called after all assembly has been done. */
4465 riscv_md_finish (void)
4467 riscv_set_public_attributes ();
4470 /* Adjust the symbol table. */
4473 riscv_adjust_symtab (void)
4475 bfd_map_over_sections (stdoutput
, riscv_check_mapping_symbols
, (char *) 0);
4476 elf_adjust_symtab ();
4479 /* Given a symbolic attribute NAME, return the proper integer value.
4480 Returns -1 if the attribute is not known. */
4483 riscv_convert_symbolic_attribute (const char *name
)
4492 /* When you modify this table you should
4493 also modify the list in doc/c-riscv.texi. */
4494 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
4498 T(priv_spec_revision
),
4499 T(unaligned_access
),
4508 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
4509 if (strcmp (name
, attribute_table
[i
].name
) == 0)
4510 return attribute_table
[i
].tag
;
4515 /* Parse a .attribute directive. */
4518 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
4520 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4522 obj_attribute
*attr
;
4524 explicit_attr
= true;
4527 case Tag_RISCV_arch
:
4529 attr
= elf_known_obj_attributes_proc (stdoutput
);
4530 if (!start_assemble
)
4531 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
4533 as_fatal (_("architecture elf attributes must set before "
4534 "any instructions"));
4536 if (old_xlen
!= xlen
)
4538 /* We must re-init bfd again if xlen is changed. */
4539 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
4540 bfd_find_target (riscv_target_format (), stdoutput
);
4542 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
4543 as_warn (_("could not set architecture and machine"));
4547 case Tag_RISCV_priv_spec
:
4548 case Tag_RISCV_priv_spec_minor
:
4549 case Tag_RISCV_priv_spec_revision
:
4551 as_fatal (_("privileged elf attributes must set before "
4552 "any instructions"));
4560 /* Mark symbol that it follows a variant CC convention. */
4563 s_variant_cc (int ignored ATTRIBUTE_UNUSED
)
4569 elf_symbol_type
*elfsym
;
4571 c
= get_symbol_name (&name
);
4573 as_bad (_("missing symbol name for .variant_cc directive"));
4574 sym
= symbol_find_or_make (name
);
4575 restore_line_pointer (c
);
4576 demand_empty_rest_of_line ();
4578 bfdsym
= symbol_get_bfdsym (sym
);
4579 elfsym
= elf_symbol_from (bfdsym
);
4580 gas_assert (elfsym
);
4581 elfsym
->internal_elf_sym
.st_other
|= STO_RISCV_VARIANT_CC
;
4584 /* Same as elf_copy_symbol_attributes, but without copying st_other.
4585 This is needed so RISC-V specific st_other values can be independently
4586 specified for an IFUNC resolver (that is called by the dynamic linker)
4587 and the symbol it resolves (aliased to the resolver). In particular,
4588 if a function symbol has special st_other value set via directives,
4589 then attaching an IFUNC resolver to that symbol should not override
4590 the st_other setting. Requiring the directive on the IFUNC resolver
4591 symbol would be unexpected and problematic in C code, where the two
4592 symbols appear as two independent function declarations. */
4595 riscv_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
4597 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
4598 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
4599 /* If size is unset, copy size from src. Because we don't track whether
4600 .size has been used, we can't differentiate .size dest, 0 from the case
4601 where dest's size is unset. */
4602 if (!destelf
->size
&& S_GET_SIZE (dest
) == 0)
4606 destelf
->size
= XNEW (expressionS
);
4607 *destelf
->size
= *srcelf
->size
;
4609 S_SET_SIZE (dest
, S_GET_SIZE (src
));
4613 /* RISC-V pseudo-ops table. */
4614 static const pseudo_typeS riscv_pseudo_table
[] =
4616 {"option", s_riscv_option
, 0},
4620 {"dtprelword", s_dtprel
, 4},
4621 {"dtpreldword", s_dtprel
, 8},
4623 {"uleb128", s_riscv_leb128
, 0},
4624 {"sleb128", s_riscv_leb128
, 1},
4625 {"insn", s_riscv_insn
, 0},
4626 {"attribute", s_riscv_attribute
, 0},
4627 {"variant_cc", s_variant_cc
, 0},
4628 {"float16", float_cons
, 'h'},
4634 riscv_pop_insert (void)
4636 extern void pop_insert (const pseudo_typeS
*);
4638 pop_insert (riscv_pseudo_table
);