1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/cpu-riscv.h"
33 #include "bfd/elfxx-riscv.h"
34 #include "elf/riscv.h"
35 #include "opcode/riscv.h"
39 /* Information about an instruction, including its format, operands
43 /* The opcode's entry in riscv_opcodes. */
44 const struct riscv_opcode
*insn_mo
;
46 /* The encoded instruction bits. */
49 /* The frag that contains the instruction. */
52 /* The offset into FRAG of the first instruction byte. */
55 /* The relocs associated with the instruction, if any. */
59 /* All RISC-V CSR belong to one of these classes. */
65 CSR_CLASS_I_32
, /* rv32 only */
66 CSR_CLASS_F
, /* f-ext only */
67 CSR_CLASS_DEBUG
/* debug CSR */
70 /* This structure holds all restricted conditions for a CSR. */
71 struct riscv_csr_extra
73 /* Class to which this CSR belongs. Used to decide whether or
74 not this CSR is legal in the current -march context. */
75 enum riscv_csr_class csr_class
;
77 /* CSR may have differnet numbers in the previous priv spec. */
80 /* Record the CSR is defined/valid in which versions. */
81 enum riscv_spec_class define_version
;
83 /* Record the CSR is aborted/invalid from which versions. If it isn't
84 aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
85 enum riscv_spec_class abort_version
;
87 /* The CSR may have more than one setting. */
88 struct riscv_csr_extra
*next
;
91 /* All standard/Z* extensions defined in all supported ISA spec. */
92 struct riscv_ext_version
95 enum riscv_spec_class isa_spec_class
;
100 static const struct riscv_ext_version ext_version_table
[] =
102 {"e", ISA_SPEC_CLASS_20191213
, 1, 9},
103 {"e", ISA_SPEC_CLASS_20190608
, 1, 9},
104 {"e", ISA_SPEC_CLASS_2P2
, 1, 9},
106 {"i", ISA_SPEC_CLASS_20191213
, 2, 1},
107 {"i", ISA_SPEC_CLASS_20190608
, 2, 1},
108 {"i", ISA_SPEC_CLASS_2P2
, 2, 0},
110 {"m", ISA_SPEC_CLASS_20191213
, 2, 0},
111 {"m", ISA_SPEC_CLASS_20190608
, 2, 0},
112 {"m", ISA_SPEC_CLASS_2P2
, 2, 0},
114 {"a", ISA_SPEC_CLASS_20191213
, 2, 1},
115 {"a", ISA_SPEC_CLASS_20190608
, 2, 0},
116 {"a", ISA_SPEC_CLASS_2P2
, 2, 0},
118 {"f", ISA_SPEC_CLASS_20191213
, 2, 2},
119 {"f", ISA_SPEC_CLASS_20190608
, 2, 2},
120 {"f", ISA_SPEC_CLASS_2P2
, 2, 0},
122 {"d", ISA_SPEC_CLASS_20191213
, 2, 2},
123 {"d", ISA_SPEC_CLASS_20190608
, 2, 2},
124 {"d", ISA_SPEC_CLASS_2P2
, 2, 0},
126 {"q", ISA_SPEC_CLASS_20191213
, 2, 2},
127 {"q", ISA_SPEC_CLASS_20190608
, 2, 2},
128 {"q", ISA_SPEC_CLASS_2P2
, 2, 0},
130 {"c", ISA_SPEC_CLASS_20191213
, 2, 0},
131 {"c", ISA_SPEC_CLASS_20190608
, 2, 0},
132 {"c", ISA_SPEC_CLASS_2P2
, 2, 0},
134 {"zicsr", ISA_SPEC_CLASS_20191213
, 2, 0},
135 {"zicsr", ISA_SPEC_CLASS_20190608
, 2, 0},
137 {"zifencei", ISA_SPEC_CLASS_20191213
, 2, 0},
138 {"zifencei", ISA_SPEC_CLASS_20190608
, 2, 0},
140 {"zihintpause", ISA_SPEC_CLASS_DRAFT
, 1, 0},
142 {"zbb", ISA_SPEC_CLASS_DRAFT
, 0, 93},
143 {"zba", ISA_SPEC_CLASS_DRAFT
, 0, 93},
144 {"zbc", ISA_SPEC_CLASS_DRAFT
, 0, 93},
146 /* Terminate the list. */
151 #define DEFAULT_ARCH "riscv64"
154 #ifndef DEFAULT_RISCV_ATTR
155 #define DEFAULT_RISCV_ATTR 0
158 /* Let riscv_after_parse_args set the default value according to xlen. */
159 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
160 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
163 /* Need to sync the version with RISC-V compiler. */
164 #ifndef DEFAULT_RISCV_ISA_SPEC
165 #define DEFAULT_RISCV_ISA_SPEC "2.2"
168 #ifndef DEFAULT_RISCV_PRIV_SPEC
169 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
172 static const char default_arch
[] = DEFAULT_ARCH
;
173 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
174 static enum riscv_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
175 static enum riscv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
177 static unsigned xlen
= 0; /* The width of an x-register. */
178 static unsigned abi_xlen
= 0; /* The width of a pointer in the ABI. */
179 static bool rve_abi
= false;
182 FLOAT_ABI_DEFAULT
= -1,
188 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
190 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
191 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
193 static unsigned elf_flags
= 0;
195 /* Set the default_isa_spec. Return 0 if the spec isn't supported.
196 Otherwise, return 1. */
199 riscv_set_default_isa_spec (const char *s
)
201 enum riscv_spec_class
class = ISA_SPEC_CLASS_NONE
;
202 RISCV_GET_ISA_SPEC_CLASS (s
, class);
203 if (class == ISA_SPEC_CLASS_NONE
)
205 as_bad ("unknown default ISA spec `%s' set by "
206 "-misa-spec or --with-isa-spec", s
);
210 default_isa_spec
= class;
214 /* Set the default_priv_spec. Find the privileged elf attributes when
215 the input string is NULL. Return 0 if the spec isn't supported.
216 Otherwise, return 1. */
219 riscv_set_default_priv_spec (const char *s
)
221 enum riscv_spec_class
class = PRIV_SPEC_CLASS_NONE
;
222 unsigned major
, minor
, revision
;
225 RISCV_GET_PRIV_SPEC_CLASS (s
, class);
226 if (class != PRIV_SPEC_CLASS_NONE
)
228 default_priv_spec
= class;
234 as_bad (_("unknown default privileged spec `%s' set by "
235 "-mpriv-spec or --with-priv-spec"), s
);
239 /* Set the default_priv_spec by the privileged elf attributes. */
240 attr
= elf_known_obj_attributes_proc (stdoutput
);
241 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
242 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
243 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
244 /* Version 0.0.0 is the default value and meningless. */
245 if (major
== 0 && minor
== 0 && revision
== 0)
248 riscv_get_priv_spec_class_from_numbers (major
, minor
, revision
, &class);
249 if (class != PRIV_SPEC_CLASS_NONE
)
251 default_priv_spec
= class;
255 /* Still can not find the privileged spec class. */
256 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
257 "privileged elf attributes"), major
, minor
, revision
);
261 /* This is the set of options which the .option pseudo-op may modify. */
262 struct riscv_set_options
264 int pic
; /* Generate position-independent code. */
265 int rvc
; /* Generate RVC code. */
266 int rve
; /* Generate RVE code. */
267 int relax
; /* Emit relocs the linker is allowed to relax. */
268 int arch_attr
; /* Emit architecture and privileged elf attributes. */
269 int csr_check
; /* Enable the CSR checking. */
272 static struct riscv_set_options riscv_opts
=
278 DEFAULT_RISCV_ATTR
, /* arch_attr */
283 riscv_set_rvc (bool rvc_value
)
286 elf_flags
|= EF_RISCV_RVC
;
288 riscv_opts
.rvc
= rvc_value
;
292 riscv_set_rve (bool rve_value
)
294 riscv_opts
.rve
= rve_value
;
297 static riscv_subset_list_t riscv_subsets
;
300 riscv_subset_supports (const char *feature
)
302 struct riscv_subset_t
*subset
;
304 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
307 return riscv_lookup_subset (&riscv_subsets
, feature
, &subset
);
311 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
315 case INSN_CLASS_I
: return riscv_subset_supports ("i");
316 case INSN_CLASS_C
: return riscv_subset_supports ("c");
317 case INSN_CLASS_A
: return riscv_subset_supports ("a");
318 case INSN_CLASS_M
: return riscv_subset_supports ("m");
319 case INSN_CLASS_F
: return riscv_subset_supports ("f");
320 case INSN_CLASS_D
: return riscv_subset_supports ("d");
321 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
323 case INSN_CLASS_F_AND_C
:
324 return (riscv_subset_supports ("f")
325 && riscv_subset_supports ("c"));
326 case INSN_CLASS_D_AND_C
:
327 return (riscv_subset_supports ("d")
328 && riscv_subset_supports ("c"));
330 case INSN_CLASS_ZICSR
:
331 return riscv_subset_supports ("zicsr");
332 case INSN_CLASS_ZIFENCEI
:
333 return riscv_subset_supports ("zifencei");
334 case INSN_CLASS_ZIHINTPAUSE
:
335 return riscv_subset_supports ("zihintpause");
338 return riscv_subset_supports ("zbb");
341 return riscv_subset_supports ("zba");
344 return riscv_subset_supports ("zbc");
347 as_fatal ("internal: unreachable");
352 /* Handle of the extension with version hash table. */
353 static htab_t ext_version_hash
= NULL
;
356 init_ext_version_hash (void)
358 const struct riscv_ext_version
*table
= ext_version_table
;
359 htab_t hash
= str_htab_create ();
362 while (table
[i
].name
)
364 const char *name
= table
[i
].name
;
365 if (str_hash_insert (hash
, name
, &table
[i
], 0) != NULL
)
366 as_fatal (_("internal: duplicate %s"), name
);
370 && strcmp (table
[i
].name
, name
) == 0)
378 riscv_get_default_ext_version (const char *name
,
382 struct riscv_ext_version
*ext
;
384 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
387 ext
= (struct riscv_ext_version
*) str_hash_find (ext_version_hash
, name
);
390 && strcmp (ext
->name
, name
) == 0)
392 if (ext
->isa_spec_class
== ISA_SPEC_CLASS_DRAFT
393 || ext
->isa_spec_class
== default_isa_spec
)
395 *major_version
= ext
->major_version
;
396 *minor_version
= ext
->minor_version
;
403 /* Set which ISA and extensions are available. */
406 riscv_set_arch (const char *s
)
408 riscv_parse_subset_t rps
;
409 rps
.subset_list
= &riscv_subsets
;
410 rps
.error_handler
= as_bad
;
412 rps
.get_default_version
= riscv_get_default_ext_version
;
413 rps
.check_unknown_prefixed_ext
= true;
418 riscv_release_subset_list (&riscv_subsets
);
419 riscv_parse_subset (&rps
, s
);
422 /* Indicate -mabi option is explictly set. */
423 static bool explicit_mabi
= false;
426 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bool rve
)
429 float_abi
= new_float_abi
;
433 /* If the -mabi option isn't set, then set the abi according to the
434 ISA string. Otherwise, check if there is any conflict. */
437 riscv_set_abi_by_arch (void)
441 if (riscv_subset_supports ("q"))
442 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, false);
443 else if (riscv_subset_supports ("d"))
444 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, false);
445 else if (riscv_subset_supports ("e"))
446 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, true);
448 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, false);
452 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
454 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
455 else if (abi_xlen
< xlen
)
456 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
458 if (riscv_subset_supports ("e") && !rve_abi
)
459 as_bad ("only the ilp32e ABI is supported for e extension");
461 if (float_abi
== FLOAT_ABI_SINGLE
462 && !riscv_subset_supports ("f"))
463 as_bad ("ilp32f/lp64f ABI can't be used when f extension "
465 else if (float_abi
== FLOAT_ABI_DOUBLE
466 && !riscv_subset_supports ("d"))
467 as_bad ("ilp32d/lp64d ABI can't be used when d extension "
469 else if (float_abi
== FLOAT_ABI_QUAD
470 && !riscv_subset_supports ("q"))
471 as_bad ("ilp32q/lp64q ABI can't be used when q extension "
475 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
476 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
477 elf_flags
|= float_abi
<< 1;
480 elf_flags
|= EF_RISCV_RVE
;
483 /* Handle of the OPCODE hash table. */
484 static htab_t op_hash
= NULL
;
486 /* Handle of the type of .insn hash table. */
487 static htab_t insn_type_hash
= NULL
;
489 /* This array holds the chars that always start a comment. If the
490 pre-processor is disabled, these aren't very useful. */
491 const char comment_chars
[] = "#";
493 /* This array holds the chars that only start a comment at the beginning of
494 a line. If the line seems to have the form '# 123 filename'
495 .line and .file directives will appear in the pre-processed output
497 Note that input_file.c hand checks for '#' at the beginning of the
498 first line of the input file. This is because the compiler outputs
499 #NO_APP at the beginning of its output.
501 Also note that C style comments are always supported. */
502 const char line_comment_chars
[] = "#";
504 /* This array holds machine specific line separator characters. */
505 const char line_separator_chars
[] = ";";
507 /* Chars that can be used to separate mant from exp in floating point nums. */
508 const char EXP_CHARS
[] = "eE";
510 /* Chars that mean this number is a floating point constant.
511 As in 0f12.456 or 0d1.2345e12. */
512 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
514 /* Indicate we are already assemble any instructions or not. */
515 static bool start_assemble
= false;
517 /* Indicate ELF attributes are explicitly set. */
518 static bool explicit_attr
= false;
520 /* Indicate CSR or priv instructions are explicitly used. */
521 static bool explicit_priv_attr
= false;
523 /* Macros for encoding relaxation state for RVC branches and far jumps. */
524 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
527 | ((uncond) ? 1 : 0) \
530 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
531 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
532 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
533 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
535 /* Is the given value a sign-extended 32-bit value? */
536 #define IS_SEXT_32BIT_NUM(x) \
537 (((x) &~ (offsetT) 0x7fffffff) == 0 \
538 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
540 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
541 #define IS_ZEXT_32BIT_NUM(x) \
542 (((x) &~ (offsetT) 0xffffffff) == 0 \
543 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
545 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
546 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
547 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
548 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
550 /* Determine if an instruction matches an opcode. */
551 #define OPCODE_MATCHES(OPCODE, OP) \
552 (((OPCODE) & MASK_##OP) == MATCH_##OP)
554 static char *expr_end
;
556 /* The default target format to use. */
559 riscv_target_format (void)
561 if (target_big_endian
)
562 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
564 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
567 /* Return the length of instruction INSN. */
569 static inline unsigned int
570 insn_length (const struct riscv_cl_insn
*insn
)
572 return riscv_insn_length (insn
->insn_opcode
);
575 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
578 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
581 insn
->insn_opcode
= mo
->match
;
587 /* Install INSN at the location specified by its "frag" and "where" fields. */
590 install_insn (const struct riscv_cl_insn
*insn
)
592 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
593 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
596 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
597 and install the opcode in the new location. */
600 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
604 if (insn
->fixp
!= NULL
)
606 insn
->fixp
->fx_frag
= frag
;
607 insn
->fixp
->fx_where
= where
;
612 /* Add INSN to the end of the output. */
615 add_fixed_insn (struct riscv_cl_insn
*insn
)
617 char *f
= frag_more (insn_length (insn
));
618 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
622 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
623 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
625 frag_grow (max_chars
);
626 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
627 frag_var (rs_machine_dependent
, max_chars
, var
,
628 subtype
, symbol
, offset
, NULL
);
631 /* Compute the length of a branch sequence, and adjust the stored length
632 accordingly. If FRAGP is NULL, the worst-case length is returned. */
635 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
637 int jump
, rvc
, length
= 8;
642 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
643 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
644 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
646 /* Assume jumps are in range; the linker will catch any that aren't. */
647 length
= jump
? 4 : 8;
649 if (fragp
->fr_symbol
!= NULL
650 && S_IS_DEFINED (fragp
->fr_symbol
)
651 && !S_IS_WEAK (fragp
->fr_symbol
)
652 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
654 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
655 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
656 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
658 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
660 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
662 else if (!jump
&& rvc
)
667 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
672 /* Information about an opcode name, mnemonics and its value. */
679 /* List for all supported opcode name. */
680 static const struct opcode_name_t opcode_name_list
[] =
725 /* Hash table for lookup opcode name. */
726 static htab_t opcode_names_hash
= NULL
;
728 /* Initialization for hash table of opcode name. */
731 init_opcode_names_hash (void)
733 const struct opcode_name_t
*opcode
;
735 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
736 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
737 as_fatal (_("internal: duplicate %s"), opcode
->name
);
740 /* Find `s` is a valid opcode name or not, return the opcode name info
743 static const struct opcode_name_t
*
744 opcode_name_lookup (char **s
)
748 struct opcode_name_t
*o
;
750 /* Find end of name. */
752 if (is_name_beginner (*e
))
754 while (is_part_of_name (*e
))
757 /* Terminate name. */
761 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
763 /* Advance to next token if one was recognized. */
782 static htab_t reg_names_hash
= NULL
;
783 static htab_t csr_extra_hash
= NULL
;
785 #define ENCODE_REG_HASH(cls, n) \
786 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
787 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
788 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
791 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
793 void *hash
= ENCODE_REG_HASH (class, n
);
794 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
795 as_fatal (_("internal: duplicate %s"), name
);
799 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
803 for (i
= 0; i
< n
; i
++)
804 hash_reg_name (class, names
[i
], i
);
807 /* Init hash table csr_extra_hash to handle CSR. */
810 riscv_init_csr_hash (const char *name
,
812 enum riscv_csr_class
class,
813 enum riscv_spec_class define_version
,
814 enum riscv_spec_class abort_version
)
816 struct riscv_csr_extra
*entry
, *pre_entry
;
817 bool need_enrty
= true;
820 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
821 while (need_enrty
&& entry
!= NULL
)
823 if (entry
->csr_class
== class
824 && entry
->address
== address
825 && entry
->define_version
== define_version
826 && entry
->abort_version
== abort_version
)
836 entry
= XNEW (struct riscv_csr_extra
);
837 entry
->csr_class
= class;
838 entry
->address
= address
;
839 entry
->define_version
= define_version
;
840 entry
->abort_version
= abort_version
;
843 if (pre_entry
== NULL
)
844 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
846 pre_entry
->next
= entry
;
849 /* Return the CSR address after checking the ISA dependency and
850 the privileged spec version.
852 There are one warning and two errors for CSR,
854 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
855 or the privileged spec, report warning only if -mcsr-check is set.
856 Unknown CSR: the CSR has never been defined, report error.
857 Improper CSR: the CSR number over the range (> 0xfff), report error. */
860 riscv_csr_address (const char *csr_name
,
861 struct riscv_csr_extra
*entry
)
863 struct riscv_csr_extra
*saved_entry
= entry
;
864 enum riscv_csr_class csr_class
= entry
->csr_class
;
865 bool need_check_version
= true;
871 result
= riscv_subset_supports ("i");
874 result
= (xlen
== 32 && riscv_subset_supports ("i"));
877 result
= riscv_subset_supports ("f");
878 need_check_version
= false;
880 case CSR_CLASS_DEBUG
:
881 need_check_version
= false;
884 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
887 if (riscv_opts
.csr_check
&& !result
)
888 as_warn (_("invalid CSR `%s' for the current ISA"), csr_name
);
890 while (entry
!= NULL
)
892 if (!need_check_version
893 || (default_priv_spec
>= entry
->define_version
894 && default_priv_spec
< entry
->abort_version
))
896 /* Find the CSR according to the specific version. */
897 return entry
->address
;
902 /* Can not find the CSR address from the chosen privileged version,
903 so use the newly defined value. */
904 if (riscv_opts
.csr_check
)
906 const char *priv_name
= NULL
;
907 RISCV_GET_PRIV_SPEC_NAME (priv_name
, default_priv_spec
);
908 if (priv_name
!= NULL
)
909 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
910 csr_name
, priv_name
);
913 return saved_entry
->address
;
916 /* Return -1 if the CSR has never been defined. Otherwise, return
920 reg_csr_lookup_internal (const char *s
)
922 struct riscv_csr_extra
*r
=
923 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
928 return riscv_csr_address (s
, r
);
932 reg_lookup_internal (const char *s
, enum reg_class
class)
936 if (class == RCLASS_CSR
)
937 return reg_csr_lookup_internal (s
);
939 r
= str_hash_find (reg_names_hash
, s
);
940 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
943 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
946 return DECODE_REG_NUM (r
);
950 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
956 /* Find end of name. */
958 if (is_name_beginner (*e
))
960 while (is_part_of_name (*e
))
963 /* Terminate name. */
967 /* Look for the register. Advance to next token if one was recognized. */
968 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
978 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
980 const char *p
= strchr (*s
, ',');
981 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
986 for (i
= 0; i
< size
; i
++)
987 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
997 /* For consistency checking, verify that all bits are specified either
998 by the match/mask part of the instruction definition, or by the
999 operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
1002 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
1004 const char *p
= opc
->args
;
1006 insn_t used_bits
= opc
->mask
;
1008 insn_t required_bits
;
1011 insn_width
= 8 * riscv_insn_length (opc
->match
);
1013 insn_width
= 8 * length
;
1015 required_bits
= ~0ULL >> (64 - insn_width
);
1017 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
1019 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
1020 opc
->name
, opc
->args
);
1024 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
1031 case 'U': break; /* CRS1, constrained to equal RD. */
1032 case 'c': break; /* CRS1, constrained to equal sp. */
1033 case 'T': /* CRS2, floating point. */
1034 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
1035 case 'S': /* CRS1S, floating point. */
1036 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
1037 case 'w': break; /* CRS1S, constrained to equal RD. */
1038 case 'D': /* CRS2S, floating point. */
1039 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
1040 case 'x': break; /* CRS2S, constrained to equal RD. */
1041 case 'z': break; /* CRS2S, constrained to be x0. */
1042 case '>': /* CITYPE immediate, compressed shift. */
1043 case 'u': /* CITYPE immediate, compressed lui. */
1044 case 'v': /* CITYPE immediate, li to compressed lui. */
1045 case 'o': /* CITYPE immediate, allow zero. */
1046 case 'j': used_bits
|= ENCODE_CITYPE_IMM (-1U); break;
1047 case 'L': used_bits
|= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
1048 case 'm': used_bits
|= ENCODE_CITYPE_LWSP_IMM (-1U); break;
1049 case 'n': used_bits
|= ENCODE_CITYPE_LDSP_IMM (-1U); break;
1050 case '6': used_bits
|= ENCODE_CSSTYPE_IMM (-1U); break;
1051 case 'M': used_bits
|= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
1052 case 'N': used_bits
|= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
1053 case '8': used_bits
|= ENCODE_CIWTYPE_IMM (-1U); break;
1054 case 'K': used_bits
|= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
1055 /* CLTYPE and CSTYPE have the same immediate encoding. */
1056 case '5': used_bits
|= ENCODE_CLTYPE_IMM (-1U); break;
1057 case 'k': used_bits
|= ENCODE_CLTYPE_LW_IMM (-1U); break;
1058 case 'l': used_bits
|= ENCODE_CLTYPE_LD_IMM (-1U); break;
1059 case 'p': used_bits
|= ENCODE_CBTYPE_IMM (-1U); break;
1060 case 'a': used_bits
|= ENCODE_CJTYPE_IMM (-1U); break;
1061 case 'F': /* Compressed funct for .insn directive. */
1064 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
1065 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
1066 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
1067 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
1069 as_bad (_("internal: bad RISC-V opcode "
1070 "(unknown operand type `CF%c'): %s %s"),
1071 c
, opc
->name
, opc
->args
);
1076 as_bad (_("internal: bad RISC-V opcode "
1077 "(unknown operand type `C%c'): %s %s"),
1078 c
, opc
->name
, opc
->args
);
1085 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
1086 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
1087 case 'A': break; /* Macro operand, must be symbol. */
1088 case 'B': break; /* Macro operand, must be symbol or constant. */
1089 case 'I': break; /* Macro operand, must be constant. */
1090 case 'D': /* RD, floating point. */
1091 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
1092 case 'Z': /* RS1, CSR number. */
1093 case 'S': /* RS1, floating point. */
1094 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1095 case 'U': /* RS1 and RS2 are the same, floating point. */
1096 USE_BITS (OP_MASK_RS1
, OP_SH_RS1
);
1098 case 'T': /* RS2, floating point. */
1099 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
1100 case 'R': /* RS3, floating point. */
1101 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
1102 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
1103 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
1104 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
1105 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
1106 case 'o': /* ITYPE immediate, load displacement. */
1107 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
1108 case 'a': used_bits
|= ENCODE_JTYPE_IMM (-1U); break;
1109 case 'p': used_bits
|= ENCODE_BTYPE_IMM (-1U); break;
1110 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1111 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1112 case 'z': break; /* Zero immediate. */
1113 case '[': break; /* Unused operand. */
1114 case ']': break; /* Unused operand. */
1115 case '0': break; /* AMO displacement, must to zero. */
1116 case '1': break; /* Relaxation operand. */
1117 case 'F': /* Funct for .insn directive. */
1120 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1121 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1122 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1124 as_bad (_("internal: bad RISC-V opcode "
1125 "(unknown operand type `F%c'): %s %s"),
1126 c
, opc
->name
, opc
->args
);
1130 case 'O': /* Opcode for .insn directive. */
1133 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1134 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1136 as_bad (_("internal: bad RISC-V opcode "
1137 "(unknown operand type `F%c'): %s %s"),
1138 c
, opc
->name
, opc
->args
);
1143 as_bad (_("internal: bad RISC-V opcode "
1144 "(unknown operand type `%c'): %s %s"),
1145 c
, opc
->name
, opc
->args
);
1149 if (used_bits
!= required_bits
)
1151 as_bad (_("internal: bad RISC-V opcode "
1152 "(bits 0x%lx undefined): %s %s"),
1153 ~(unsigned long)(used_bits
& required_bits
),
1154 opc
->name
, opc
->args
);
1160 struct percent_op_match
1163 bfd_reloc_code_real_type reloc
;
1166 /* Common hash table initialization function for instruction and .insn
1170 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1171 bool insn_directive_p
)
1175 htab_t hash
= str_htab_create ();
1176 while (opcodes
[i
].name
)
1178 const char *name
= opcodes
[i
].name
;
1179 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1180 as_fatal (_("internal: duplicate %s"), name
);
1184 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1186 if (insn_directive_p
)
1187 length
= ((name
[0] == 'c') ? 2 : 4);
1189 length
= 0; /* Let assembler determine the length. */
1190 if (!validate_riscv_insn (&opcodes
[i
], length
))
1191 as_fatal (_("internal: broken assembler. "
1192 "No assembly attempted"));
1195 gas_assert (!insn_directive_p
);
1198 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1204 /* This function is called once, at assembler startup time. It should set up
1205 all the tables, etc. that the MD part of the assembler will need. */
1210 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1212 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1213 as_warn (_("could not set architecture and machine"));
1215 op_hash
= init_opcode_hash (riscv_opcodes
, false);
1216 insn_type_hash
= init_opcode_hash (riscv_insn_types
, true);
1218 reg_names_hash
= str_htab_create ();
1219 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1220 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1221 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1222 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1223 /* Add "fp" as an alias for "s0". */
1224 hash_reg_name (RCLASS_GPR
, "fp", 8);
1226 /* Create and insert CSR hash tables. */
1227 csr_extra_hash
= str_htab_create ();
1228 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1229 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1230 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1231 DECLARE_CSR(name, num, class, define_version, abort_version);
1232 #include "opcode/riscv-opc.h"
1235 opcode_names_hash
= str_htab_create ();
1236 init_opcode_names_hash ();
1238 /* Set the default alignment for the text section. */
1239 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1243 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1250 case BFD_RELOC_RISCV_HI20
:
1251 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1253 case BFD_RELOC_RISCV_LO12_S
:
1254 return ENCODE_STYPE_IMM (value
);
1256 case BFD_RELOC_RISCV_LO12_I
:
1257 return ENCODE_ITYPE_IMM (value
);
1264 /* Output an instruction. IP is the instruction information.
1265 ADDRESS_EXPR is an operand of the instruction to be used with
1269 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1270 bfd_reloc_code_real_type reloc_type
)
1272 dwarf2_emit_insn (0);
1274 if (reloc_type
!= BFD_RELOC_UNUSED
)
1276 reloc_howto_type
*howto
;
1278 gas_assert (address_expr
);
1279 if (reloc_type
== BFD_RELOC_12_PCREL
1280 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1282 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1283 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1284 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1286 if (now_seg
== absolute_section
)
1288 as_bad (_("relaxable branches not supported in absolute section"));
1292 add_relaxed_insn (ip
, worst_case
, best_case
,
1293 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1294 address_expr
->X_add_symbol
,
1295 address_expr
->X_add_number
);
1300 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1302 as_bad (_("internal: usupported RISC-V relocation number %d"),
1305 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1306 bfd_get_reloc_size (howto
),
1307 address_expr
, false, reloc_type
);
1309 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1313 add_fixed_insn (ip
);
1316 /* We need to start a new frag after any instruction that can be
1317 optimized away or compressed by the linker during relaxation, to prevent
1318 the assembler from computing static offsets across such an instruction.
1319 This is necessary to get correct EH info. */
1320 if (reloc_type
== BFD_RELOC_RISCV_HI20
1321 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1322 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1323 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1325 frag_wane (frag_now
);
1330 /* Build an instruction created by a macro expansion. This is passed
1331 a pointer to the count of instructions created so far, an expression,
1332 the name of the instruction to build, an operand format string, and
1333 corresponding arguments. */
1336 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1338 const struct riscv_opcode
*mo
;
1339 struct riscv_cl_insn insn
;
1340 bfd_reloc_code_real_type r
;
1343 va_start (args
, fmt
);
1345 r
= BFD_RELOC_UNUSED
;
1346 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1349 /* Find a non-RVC variant of the instruction. append_insn will compress
1351 while (riscv_insn_length (mo
->match
) < 4)
1353 gas_assert (strcmp (name
, mo
->name
) == 0);
1355 create_insn (&insn
, mo
);
1361 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1365 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1369 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1375 gas_assert (ep
!= NULL
);
1376 r
= va_arg (args
, int);
1384 as_fatal (_("internal: invalid macro"));
1389 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1391 append_insn (&insn
, ep
, r
);
1394 /* Build an instruction created by a macro expansion. Like md_assemble but
1395 accept a printf-style format string and arguments. */
1398 md_assemblef (const char *format
, ...)
1404 va_start (ap
, format
);
1406 r
= vasprintf (&buf
, format
, ap
);
1409 as_fatal (_("internal: vasprintf failed"));
1417 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1421 normalize_constant_expr (expressionS
*ex
)
1425 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1426 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1427 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1431 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1432 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1435 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1438 if (ex
->X_op
== O_big
)
1439 as_bad (_("unsupported large constant"));
1440 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1441 as_bad (_("unknown CSR `%s'"),
1442 S_GET_NAME (ex
->X_add_symbol
));
1443 else if (ex
->X_op
!= O_constant
)
1444 as_bad (_("instruction %s requires absolute expression"),
1446 normalize_constant_expr (ex
);
1450 make_internal_label (void)
1452 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1456 /* Load an entry from the GOT. */
1459 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1460 const char *lo_insn
, const char *lo_pattern
,
1461 bfd_reloc_code_real_type hi_reloc
,
1462 bfd_reloc_code_real_type lo_reloc
)
1465 ep2
.X_op
= O_symbol
;
1466 ep2
.X_add_symbol
= make_internal_label ();
1467 ep2
.X_add_number
= 0;
1469 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1470 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1474 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1475 bfd_reloc_code_real_type hi_reloc
,
1476 bfd_reloc_code_real_type lo_reloc
)
1478 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1482 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1483 bfd_reloc_code_real_type hi_reloc
,
1484 bfd_reloc_code_real_type lo_reloc
)
1486 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1489 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1492 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1493 bfd_reloc_code_real_type reloc
)
1495 /* Ensure the jalr is emitted to the same frag as the auipc. */
1497 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1498 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1499 /* See comment at end of append_insn. */
1500 frag_wane (frag_now
);
1504 /* Load an integer constant into a register. */
1507 load_const (int reg
, expressionS
*ep
)
1509 int shift
= RISCV_IMM_BITS
;
1510 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1511 expressionS upper
= *ep
, lower
= *ep
;
1512 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1513 upper
.X_add_number
-= lower
.X_add_number
;
1515 if (ep
->X_op
!= O_constant
)
1517 as_bad (_("unsupported large constant"));
1521 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1523 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1524 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1527 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1528 load_const (reg
, &upper
);
1530 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1531 if (lower
.X_add_number
!= 0)
1532 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1533 lower
.X_add_number
);
1537 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1540 if (upper
.X_add_number
!= 0)
1542 /* Discard low part and zero-extend upper immediate. */
1543 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1545 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1549 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1550 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1551 lower
.X_add_number
);
1555 /* Zero extend and sign extend byte/half-word/word. */
1558 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bool sign
)
1562 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1563 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1567 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1568 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1572 /* Expand RISC-V assembly macros into one or more instructions. */
1575 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1576 bfd_reloc_code_real_type
*imm_reloc
)
1578 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1579 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1580 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1581 int mask
= ip
->insn_mo
->mask
;
1586 load_const (rd
, imm_expr
);
1591 /* Load the address of a symbol into a register. */
1592 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1593 as_bad (_("offset too large"));
1595 if (imm_expr
->X_op
== O_constant
)
1596 load_const (rd
, imm_expr
);
1597 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol. */
1598 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1599 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1600 else /* Local PIC symbol, or any non-PIC symbol. */
1601 pcrel_load (rd
, rd
, imm_expr
, "addi",
1602 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1606 pcrel_load (rd
, rd
, imm_expr
, "addi",
1607 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1611 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1612 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1616 pcrel_load (rd
, rd
, imm_expr
, "lb",
1617 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1621 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1622 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1626 pcrel_load (rd
, rd
, imm_expr
, "lh",
1627 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1631 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1632 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1636 pcrel_load (rd
, rd
, imm_expr
, "lw",
1637 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1641 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1642 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1646 pcrel_load (rd
, rd
, imm_expr
, "ld",
1647 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1651 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1652 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1656 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1657 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1661 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1662 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1666 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1667 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1671 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1672 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1676 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1677 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1681 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1682 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1686 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1687 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1691 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1695 riscv_ext (rd
, rs1
, xlen
- 16, false);
1699 riscv_ext (rd
, rs1
, xlen
- 32, false);
1703 riscv_ext (rd
, rs1
, xlen
- 8, true);
1707 riscv_ext (rd
, rs1
, xlen
- 16, true);
1711 as_bad (_("internal: macro %s not implemented"), ip
->insn_mo
->name
);
1716 static const struct percent_op_match percent_op_utype
[] =
1718 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1719 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1720 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1721 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1722 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1723 {"%hi", BFD_RELOC_RISCV_HI20
},
1727 static const struct percent_op_match percent_op_itype
[] =
1729 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1730 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1731 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1735 static const struct percent_op_match percent_op_stype
[] =
1737 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1738 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1739 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1743 static const struct percent_op_match percent_op_rtype
[] =
1745 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1749 static const struct percent_op_match percent_op_null
[] =
1754 /* Return true if *STR points to a relocation operator. When returning true,
1755 move *STR over the operator and store its relocation code in *RELOC.
1756 Leave both *STR and *RELOC alone when returning false. */
1759 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1760 const struct percent_op_match
*percent_op
)
1762 for ( ; percent_op
->str
; percent_op
++)
1763 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1765 int len
= strlen (percent_op
->str
);
1767 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1770 *str
+= strlen (percent_op
->str
);
1771 *reloc
= percent_op
->reloc
;
1773 /* Check whether the output BFD supports this relocation.
1774 If not, issue an error and fall back on something safe. */
1775 if (*reloc
!= BFD_RELOC_UNUSED
1776 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1778 as_bad ("internal: relocation %s isn't supported by the "
1779 "current ABI", percent_op
->str
);
1780 *reloc
= BFD_RELOC_UNUSED
;
1788 my_getExpression (expressionS
*ep
, char *str
)
1792 save_in
= input_line_pointer
;
1793 input_line_pointer
= str
;
1795 expr_end
= input_line_pointer
;
1796 input_line_pointer
= save_in
;
1799 /* Parse string STR as a 16-bit relocatable operand. Store the
1800 expression in *EP and the relocation, if any, in RELOC.
1801 Return the number of relocation operators used (0 or 1).
1803 On exit, EXPR_END points to the first character after the expression. */
1806 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1807 char *str
, const struct percent_op_match
*percent_op
)
1810 unsigned crux_depth
, str_depth
, regno
;
1813 /* First, check for integer registers. No callers can accept a reg, but
1814 we need to avoid accidentally creating a useless undefined symbol below,
1815 if this is an instruction pattern that can't match. A glibc build fails
1816 if this is removed. */
1817 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1819 ep
->X_op
= O_register
;
1820 ep
->X_add_number
= regno
;
1825 /* Search for the start of the main expression.
1827 End the loop with CRUX pointing to the start of the main expression and
1828 with CRUX_DEPTH containing the number of open brackets at that point. */
1835 crux_depth
= str_depth
;
1837 /* Skip over whitespace and brackets, keeping count of the number
1839 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1845 && parse_relocation (&str
, reloc
, percent_op
));
1847 my_getExpression (ep
, crux
);
1850 /* Match every open bracket. */
1851 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1856 as_bad ("unclosed '('");
1863 /* Parse opcode name, could be an mnemonics or number. */
1866 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1867 char *str
, const struct percent_op_match
*percent_op
)
1869 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1873 ep
->X_op
= O_constant
;
1874 ep
->X_add_number
= o
->val
;
1878 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1881 /* Detect and handle implicitly zero load-store offsets. For example,
1882 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1883 an implicit offset was detected. */
1886 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1888 /* Check whether there is only a single bracketed expression left.
1889 If so, it must be the base register and the constant must be zero. */
1890 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1892 ep
->X_op
= O_constant
;
1893 ep
->X_add_number
= 0;
1900 /* All RISC-V CSR instructions belong to one of these classes. */
1909 /* Return which CSR instruction is checking. */
1911 static enum csr_insn_type
1912 riscv_csr_insn_type (insn_t insn
)
1914 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1915 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1917 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1918 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1920 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1921 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1924 return INSN_NOT_CSR
;
1927 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1928 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1929 CSR address is 0x3. */
1932 riscv_csr_read_only_check (insn_t insn
)
1934 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1935 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1936 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1937 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1940 && (((csr_insn
== INSN_CSRRS
1941 || csr_insn
== INSN_CSRRC
)
1943 || csr_insn
== INSN_CSRRW
))
1949 /* Return True if it is a privileged instruction. Otherwise, return FALSE.
1951 uret is actually a N-ext instruction. So it is better to regard it as
1952 an user instruction rather than the priv instruction.
1954 hret is used to return from traps in H-mode. H-mode is removed since
1955 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1956 Therefore, hret should be controlled by the hypervisor spec rather than
1957 priv spec in the future.
1959 dret is defined in the debug spec, so it should be checked in the future,
1963 riscv_is_priv_insn (insn_t insn
)
1965 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
1966 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
1967 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
1968 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
1969 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1970 check it here to keep the compatible. */
1971 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
1974 /* This routine assembles an instruction into its binary format. As a
1975 side effect, it sets the global variable imm_reloc to the type of
1976 relocation to do if one of the operands is an address expression. */
1979 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1980 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
1985 struct riscv_opcode
*insn
;
1990 const struct percent_op_match
*p
;
1991 const char *error
= "unrecognized opcode";
1992 /* Indicate we are assembling instruction with CSR. */
1993 bool insn_with_csr
= false;
1995 /* Parse the name of the instruction. Terminate the string if whitespace
1996 is found so that str_hash_find only sees the name part of the string. */
1997 for (s
= str
; *s
!= '\0'; ++s
)
2005 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
2008 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
2010 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
2013 if (!riscv_multi_subset_supports (insn
->insn_class
))
2016 create_insn (ip
, insn
);
2019 imm_expr
->X_op
= O_absent
;
2020 *imm_reloc
= BFD_RELOC_UNUSED
;
2021 p
= percent_op_itype
;
2023 for (args
= insn
->args
;; ++args
)
2025 s
+= strspn (s
, " \t");
2028 case '\0': /* End of args. */
2029 if (insn
->pinfo
!= INSN_MACRO
)
2031 if (!insn
->match_func (insn
, ip
->insn_opcode
))
2034 /* For .insn, insn->match and insn->mask are 0. */
2035 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
2041 if (riscv_is_priv_insn (ip
->insn_opcode
))
2042 explicit_priv_attr
= true;
2044 /* Check if we write a read-only CSR by the CSR
2047 && riscv_opts
.csr_check
2048 && !riscv_csr_read_only_check (ip
->insn_opcode
))
2050 /* Restore the character in advance, since we want to
2051 report the detailed warning message here. */
2053 *(argsStart
- 1) = save_c
;
2054 as_warn (_("read-only CSR is written `%s'"), str
);
2055 insn_with_csr
= false;
2060 /* Successful assembly. */
2062 insn_with_csr
= false;
2068 case 's': /* RS1 x8-x15. */
2069 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2070 || !(regno
>= 8 && regno
<= 15))
2072 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2074 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2075 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2076 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
2079 case 't': /* RS2 x8-x15. */
2080 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2081 || !(regno
>= 8 && regno
<= 15))
2083 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2085 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2086 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2087 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
2090 case 'U': /* RS1, constrained to equal RD. */
2091 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2092 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
2096 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
2098 INSERT_OPERAND (CRS2
, *ip
, regno
);
2100 case 'c': /* RS1, constrained to equal sp. */
2101 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2105 case 'z': /* RS2, constrained to equal x0. */
2106 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2110 case '>': /* Shift amount, 0 - (XLEN-1). */
2111 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2112 || imm_expr
->X_op
!= O_constant
2113 || (unsigned long) imm_expr
->X_add_number
>= xlen
)
2115 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2118 imm_expr
->X_op
= O_absent
;
2121 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2122 || imm_expr
->X_op
!= O_constant
2123 || imm_expr
->X_add_number
< 0
2124 || imm_expr
->X_add_number
>= 32
2125 || !VALID_CLTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2127 ip
->insn_opcode
|= ENCODE_CLTYPE_IMM (imm_expr
->X_add_number
);
2130 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2131 || imm_expr
->X_op
!= O_constant
2132 || imm_expr
->X_add_number
< 0
2133 || imm_expr
->X_add_number
>= 64
2134 || !VALID_CSSTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2136 ip
->insn_opcode
|= ENCODE_CSSTYPE_IMM (imm_expr
->X_add_number
);
2139 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2140 || imm_expr
->X_op
!= O_constant
2141 || imm_expr
->X_add_number
< 0
2142 || imm_expr
->X_add_number
>= 256
2143 || !VALID_CIWTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2145 ip
->insn_opcode
|= ENCODE_CIWTYPE_IMM (imm_expr
->X_add_number
);
2148 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2149 || imm_expr
->X_op
!= O_constant
2150 || imm_expr
->X_add_number
== 0
2151 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2153 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2156 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2158 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2159 || imm_expr
->X_op
!= O_constant
2160 || !VALID_CLTYPE_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2162 ip
->insn_opcode
|= ENCODE_CLTYPE_LW_IMM (imm_expr
->X_add_number
);
2165 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2167 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2168 || imm_expr
->X_op
!= O_constant
2169 || !VALID_CLTYPE_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2171 ip
->insn_opcode
|= ENCODE_CLTYPE_LD_IMM (imm_expr
->X_add_number
);
2174 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2176 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2177 || imm_expr
->X_op
!= O_constant
2178 || !VALID_CITYPE_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2181 ENCODE_CITYPE_LWSP_IMM (imm_expr
->X_add_number
);
2184 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2186 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2187 || imm_expr
->X_op
!= O_constant
2188 || !VALID_CITYPE_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2191 ENCODE_CITYPE_LDSP_IMM (imm_expr
->X_add_number
);
2194 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2195 || imm_expr
->X_op
!= O_constant
2196 /* C.addiw, c.li, and c.andi allow zero immediate.
2197 C.addi allows zero immediate as hint. Otherwise this
2199 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2201 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2204 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2205 || imm_expr
->X_op
!= O_constant
2206 || imm_expr
->X_add_number
== 0
2207 || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2210 ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2213 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2214 || imm_expr
->X_op
!= O_constant
2215 || !VALID_CITYPE_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2218 ENCODE_CITYPE_ADDI16SP_IMM (imm_expr
->X_add_number
);
2221 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2223 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2224 || imm_expr
->X_op
!= O_constant
2225 || !VALID_CSSTYPE_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2228 ENCODE_CSSTYPE_SWSP_IMM (imm_expr
->X_add_number
);
2231 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2233 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2234 || imm_expr
->X_op
!= O_constant
2235 || !VALID_CSSTYPE_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2238 ENCODE_CSSTYPE_SDSP_IMM (imm_expr
->X_add_number
);
2241 p
= percent_op_utype
;
2242 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2245 if (imm_expr
->X_op
!= O_constant
2246 || imm_expr
->X_add_number
<= 0
2247 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2248 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2249 && (imm_expr
->X_add_number
<
2250 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2252 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2255 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2256 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2257 || ((int32_t)imm_expr
->X_add_number
2258 != imm_expr
->X_add_number
))
2260 imm_expr
->X_add_number
=
2261 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2267 case 'S': /* Floating-point RS1 x8-x15. */
2268 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2269 || !(regno
>= 8 && regno
<= 15))
2271 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2273 case 'D': /* Floating-point RS2 x8-x15. */
2274 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2275 || !(regno
>= 8 && regno
<= 15))
2277 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2279 case 'T': /* Floating-point RS2. */
2280 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2282 INSERT_OPERAND (CRS2
, *ip
, regno
);
2288 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2289 || imm_expr
->X_op
!= O_constant
2290 || imm_expr
->X_add_number
< 0
2291 || imm_expr
->X_add_number
>= 64)
2293 as_bad (_("bad value for compressed funct6 "
2294 "field, value must be 0...64"));
2297 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2298 imm_expr
->X_op
= O_absent
;
2303 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2304 || imm_expr
->X_op
!= O_constant
2305 || imm_expr
->X_add_number
< 0
2306 || imm_expr
->X_add_number
>= 16)
2308 as_bad (_("bad value for compressed funct4 "
2309 "field, value must be 0...15"));
2312 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2313 imm_expr
->X_op
= O_absent
;
2318 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2319 || imm_expr
->X_op
!= O_constant
2320 || imm_expr
->X_add_number
< 0
2321 || imm_expr
->X_add_number
>= 8)
2323 as_bad (_("bad value for compressed funct3 "
2324 "field, value must be 0...7"));
2327 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2328 imm_expr
->X_op
= O_absent
;
2333 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2334 || imm_expr
->X_op
!= O_constant
2335 || imm_expr
->X_add_number
< 0
2336 || imm_expr
->X_add_number
>= 4)
2338 as_bad (_("bad value for compressed funct2 "
2339 "field, value must be 0...3"));
2342 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2343 imm_expr
->X_op
= O_absent
;
2348 as_bad (_("internal: unknown compressed funct "
2349 "field specifier `CF%c'"), *args
);
2354 as_bad (_("internal: unknown compressed field "
2355 "specifier `C%c'"), *args
);
2374 case '<': /* Shift amount, 0 - 31. */
2375 my_getExpression (imm_expr
, s
);
2376 check_absolute_expr (ip
, imm_expr
, false);
2377 if ((unsigned long) imm_expr
->X_add_number
> 31)
2378 as_bad (_("improper shift amount (%lu)"),
2379 (unsigned long) imm_expr
->X_add_number
);
2380 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2381 imm_expr
->X_op
= O_absent
;
2385 case '>': /* Shift amount, 0 - (XLEN-1). */
2386 my_getExpression (imm_expr
, s
);
2387 check_absolute_expr (ip
, imm_expr
, false);
2388 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2389 as_bad (_("improper shift amount (%lu)"),
2390 (unsigned long) imm_expr
->X_add_number
);
2391 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2392 imm_expr
->X_op
= O_absent
;
2396 case 'Z': /* CSRRxI immediate. */
2397 my_getExpression (imm_expr
, s
);
2398 check_absolute_expr (ip
, imm_expr
, false);
2399 if ((unsigned long) imm_expr
->X_add_number
> 31)
2400 as_bad (_("improper CSRxI immediate (%lu)"),
2401 (unsigned long) imm_expr
->X_add_number
);
2402 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2403 imm_expr
->X_op
= O_absent
;
2407 case 'E': /* Control register. */
2408 insn_with_csr
= true;
2409 explicit_priv_attr
= true;
2410 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2411 INSERT_OPERAND (CSR
, *ip
, regno
);
2414 my_getExpression (imm_expr
, s
);
2415 check_absolute_expr (ip
, imm_expr
, true);
2416 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2417 as_bad (_("improper CSR address (%lu)"),
2418 (unsigned long) imm_expr
->X_add_number
);
2419 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2420 imm_expr
->X_op
= O_absent
;
2425 case 'm': /* Rounding mode. */
2426 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2428 INSERT_OPERAND (RM
, *ip
, regno
);
2434 case 'Q': /* Fence predecessor/successor. */
2435 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2439 INSERT_OPERAND (PRED
, *ip
, regno
);
2441 INSERT_OPERAND (SUCC
, *ip
, regno
);
2446 case 'd': /* Destination register. */
2447 case 's': /* Source register. */
2448 case 't': /* Target register. */
2450 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2456 /* Now that we have assembled one operand, we use the args
2457 string to figure out where it goes in the instruction. */
2461 INSERT_OPERAND (RS1
, *ip
, regno
);
2464 INSERT_OPERAND (RD
, *ip
, regno
);
2467 INSERT_OPERAND (RS2
, *ip
, regno
);
2470 INSERT_OPERAND (RS3
, *ip
, regno
);
2477 case 'D': /* Floating point RD. */
2478 case 'S': /* Floating point RS1. */
2479 case 'T': /* Floating point RS2. */
2480 case 'U': /* Floating point RS1 and RS2. */
2481 case 'R': /* Floating point RS3. */
2482 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2490 INSERT_OPERAND (RD
, *ip
, regno
);
2493 INSERT_OPERAND (RS1
, *ip
, regno
);
2496 INSERT_OPERAND (RS1
, *ip
, regno
);
2499 INSERT_OPERAND (RS2
, *ip
, regno
);
2502 INSERT_OPERAND (RS3
, *ip
, regno
);
2510 my_getExpression (imm_expr
, s
);
2511 if (imm_expr
->X_op
!= O_big
2512 && imm_expr
->X_op
!= O_constant
)
2514 normalize_constant_expr (imm_expr
);
2519 my_getExpression (imm_expr
, s
);
2520 normalize_constant_expr (imm_expr
);
2521 /* The 'A' format specifier must be a symbol. */
2522 if (imm_expr
->X_op
!= O_symbol
)
2524 *imm_reloc
= BFD_RELOC_32
;
2529 my_getExpression (imm_expr
, s
);
2530 normalize_constant_expr (imm_expr
);
2531 /* The 'B' format specifier must be a symbol or a constant. */
2532 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2534 if (imm_expr
->X_op
== O_symbol
)
2535 *imm_reloc
= BFD_RELOC_32
;
2539 case 'j': /* Sign-extended immediate. */
2540 p
= percent_op_itype
;
2541 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2543 case 'q': /* Store displacement. */
2544 p
= percent_op_stype
;
2545 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2547 case 'o': /* Load displacement. */
2548 p
= percent_op_itype
;
2549 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2552 /* This is used for TLS, where the fourth operand is
2553 %tprel_add, to get a relocation applied to an add
2554 instruction, for relaxation to use. */
2555 p
= percent_op_rtype
;
2557 case '0': /* AMO displacement, which must be zero. */
2558 p
= percent_op_null
;
2560 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2563 /* If this value won't fit into a 16 bit offset, then go
2564 find a macro that will generate the 32 bit offset
2566 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2568 normalize_constant_expr (imm_expr
);
2569 if (imm_expr
->X_op
!= O_constant
2570 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2572 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2573 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2579 case 'p': /* PC-relative offset. */
2581 *imm_reloc
= BFD_RELOC_12_PCREL
;
2582 my_getExpression (imm_expr
, s
);
2586 case 'u': /* Upper 20 bits. */
2587 p
= percent_op_utype
;
2588 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2590 if (imm_expr
->X_op
!= O_constant
)
2593 if (imm_expr
->X_add_number
< 0
2594 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2595 as_bad (_("lui expression not in range 0..1048575"));
2597 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2598 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2603 case 'a': /* 20-bit PC-relative offset. */
2605 my_getExpression (imm_expr
, s
);
2607 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2611 my_getExpression (imm_expr
, s
);
2613 if (strcmp (s
, "@plt") == 0)
2615 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2619 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2626 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2627 || imm_expr
->X_op
!= O_constant
2628 || imm_expr
->X_add_number
< 0
2629 || imm_expr
->X_add_number
>= 128
2630 || (imm_expr
->X_add_number
& 0x3) != 3)
2632 as_bad (_("bad value for opcode field, "
2633 "value must be 0...127 and "
2634 "lower 2 bits must be 0x3"));
2637 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2638 imm_expr
->X_op
= O_absent
;
2643 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2644 || imm_expr
->X_op
!= O_constant
2645 || imm_expr
->X_add_number
< 0
2646 || imm_expr
->X_add_number
>= 3)
2648 as_bad (_("bad value for opcode field, "
2649 "value must be 0...2"));
2652 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2653 imm_expr
->X_op
= O_absent
;
2658 as_bad (_("internal: unknown opcode field "
2659 "specifier `O%c'"), *args
);
2667 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2668 || imm_expr
->X_op
!= O_constant
2669 || imm_expr
->X_add_number
< 0
2670 || imm_expr
->X_add_number
>= 128)
2672 as_bad (_("bad value for funct7 field, "
2673 "value must be 0...127"));
2676 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2677 imm_expr
->X_op
= O_absent
;
2682 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2683 || imm_expr
->X_op
!= O_constant
2684 || imm_expr
->X_add_number
< 0
2685 || imm_expr
->X_add_number
>= 8)
2687 as_bad (_("bad value for funct3 field, "
2688 "value must be 0...7"));
2691 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2692 imm_expr
->X_op
= O_absent
;
2697 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2698 || imm_expr
->X_op
!= O_constant
2699 || imm_expr
->X_add_number
< 0
2700 || imm_expr
->X_add_number
>= 4)
2702 as_bad (_("bad value for funct2 field, "
2703 "value must be 0...3"));
2706 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2707 imm_expr
->X_op
= O_absent
;
2712 as_bad (_("internal: unknown funct field "
2713 "specifier `F%c'\n"), *args
);
2718 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2719 || imm_expr
->X_op
!= O_constant
2720 || imm_expr
->X_add_number
!= 0)
2723 imm_expr
->X_op
= O_absent
;
2727 as_fatal (_("internal: unknown argument type `%c'"), *args
);
2732 error
= _("illegal operands");
2733 insn_with_csr
= false;
2737 /* Restore the character we might have clobbered above. */
2739 *(argsStart
- 1) = save_c
;
2745 md_assemble (char *str
)
2747 struct riscv_cl_insn insn
;
2748 expressionS imm_expr
;
2749 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2751 /* The architecture and privileged elf attributes should be set
2752 before assembling. */
2753 if (!start_assemble
)
2755 start_assemble
= true;
2757 riscv_set_abi_by_arch ();
2758 if (!riscv_set_default_priv_spec (NULL
))
2762 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2766 as_bad ("%s `%s'", error
, str
);
2770 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2771 macro (&insn
, &imm_expr
, &imm_reloc
);
2773 append_insn (&insn
, &imm_expr
, imm_reloc
);
2777 md_atof (int type
, char *litP
, int *sizeP
)
2779 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2783 md_number_to_chars (char *buf
, valueT val
, int n
)
2785 if (target_big_endian
)
2786 number_to_chars_bigendian (buf
, val
, n
);
2788 number_to_chars_littleendian (buf
, val
, n
);
2791 const char *md_shortopts
= "O::g::G:";
2795 OPTION_MARCH
= OPTION_MD_BASE
,
2802 OPTION_NO_ARCH_ATTR
,
2804 OPTION_NO_CSR_CHECK
,
2808 OPTION_LITTLE_ENDIAN
,
2812 struct option md_longopts
[] =
2814 {"march", required_argument
, NULL
, OPTION_MARCH
},
2815 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2816 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2817 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2818 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2819 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2820 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2821 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2822 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2823 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2824 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2825 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2826 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2827 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
2828 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
2830 {NULL
, no_argument
, NULL
, 0}
2832 size_t md_longopts_size
= sizeof (md_longopts
);
2835 md_parse_option (int c
, const char *arg
)
2840 default_arch_with_ext
= arg
;
2844 riscv_opts
.pic
= false;
2848 riscv_opts
.pic
= true;
2852 if (strcmp (arg
, "ilp32") == 0)
2853 riscv_set_abi (32, FLOAT_ABI_SOFT
, false);
2854 else if (strcmp (arg
, "ilp32e") == 0)
2855 riscv_set_abi (32, FLOAT_ABI_SOFT
, true);
2856 else if (strcmp (arg
, "ilp32f") == 0)
2857 riscv_set_abi (32, FLOAT_ABI_SINGLE
, false);
2858 else if (strcmp (arg
, "ilp32d") == 0)
2859 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, false);
2860 else if (strcmp (arg
, "ilp32q") == 0)
2861 riscv_set_abi (32, FLOAT_ABI_QUAD
, false);
2862 else if (strcmp (arg
, "lp64") == 0)
2863 riscv_set_abi (64, FLOAT_ABI_SOFT
, false);
2864 else if (strcmp (arg
, "lp64f") == 0)
2865 riscv_set_abi (64, FLOAT_ABI_SINGLE
, false);
2866 else if (strcmp (arg
, "lp64d") == 0)
2867 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, false);
2868 else if (strcmp (arg
, "lp64q") == 0)
2869 riscv_set_abi (64, FLOAT_ABI_QUAD
, false);
2872 explicit_mabi
= true;
2876 riscv_opts
.relax
= true;
2879 case OPTION_NO_RELAX
:
2880 riscv_opts
.relax
= false;
2883 case OPTION_ARCH_ATTR
:
2884 riscv_opts
.arch_attr
= true;
2887 case OPTION_NO_ARCH_ATTR
:
2888 riscv_opts
.arch_attr
= false;
2891 case OPTION_CSR_CHECK
:
2892 riscv_opts
.csr_check
= true;
2895 case OPTION_NO_CSR_CHECK
:
2896 riscv_opts
.csr_check
= false;
2899 case OPTION_MISA_SPEC
:
2900 return riscv_set_default_isa_spec (arg
);
2902 case OPTION_MPRIV_SPEC
:
2903 return riscv_set_default_priv_spec (arg
);
2905 case OPTION_BIG_ENDIAN
:
2906 target_big_endian
= 1;
2909 case OPTION_LITTLE_ENDIAN
:
2910 target_big_endian
= 0;
2921 riscv_after_parse_args (void)
2923 /* The --with-arch is optional for now, so we still need to set the xlen
2924 according to the default_arch, which is set by the --target. */
2927 if (strcmp (default_arch
, "riscv32") == 0)
2929 else if (strcmp (default_arch
, "riscv64") == 0)
2932 as_bad ("unknown default architecture `%s'", default_arch
);
2934 if (default_arch_with_ext
== NULL
)
2935 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2937 /* Initialize the hash table for extensions with default version. */
2938 ext_version_hash
= init_ext_version_hash ();
2940 /* Set default specs. */
2941 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2942 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2943 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2944 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2946 riscv_set_arch (default_arch_with_ext
);
2948 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2949 riscv_set_rvc (false);
2950 if (riscv_subset_supports ("c"))
2951 riscv_set_rvc (true);
2953 /* Enable RVE if specified by the -march option. */
2954 riscv_set_rve (false);
2955 if (riscv_subset_supports ("e"))
2956 riscv_set_rve (true);
2958 /* If the CIE to be produced has not been overridden on the command line,
2959 then produce version 3 by default. This allows us to use the full
2960 range of registers in a .cfi_return_column directive. */
2961 if (flag_dwarf_cie_version
== -1)
2962 flag_dwarf_cie_version
= 3;
2966 md_pcrel_from (fixS
*fixP
)
2968 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2971 /* Apply a fixup to the object file. */
2974 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2976 unsigned int subtype
;
2977 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2978 bool relaxable
= false;
2982 /* Remember value for tc_gen_reloc. */
2983 fixP
->fx_addnumber
= *valP
;
2985 switch (fixP
->fx_r_type
)
2987 case BFD_RELOC_RISCV_HI20
:
2988 case BFD_RELOC_RISCV_LO12_I
:
2989 case BFD_RELOC_RISCV_LO12_S
:
2990 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2991 | bfd_getl32 (buf
), buf
);
2992 if (fixP
->fx_addsy
== NULL
)
2993 fixP
->fx_done
= true;
2997 case BFD_RELOC_RISCV_GOT_HI20
:
2998 case BFD_RELOC_RISCV_ADD8
:
2999 case BFD_RELOC_RISCV_ADD16
:
3000 case BFD_RELOC_RISCV_ADD32
:
3001 case BFD_RELOC_RISCV_ADD64
:
3002 case BFD_RELOC_RISCV_SUB6
:
3003 case BFD_RELOC_RISCV_SUB8
:
3004 case BFD_RELOC_RISCV_SUB16
:
3005 case BFD_RELOC_RISCV_SUB32
:
3006 case BFD_RELOC_RISCV_SUB64
:
3007 case BFD_RELOC_RISCV_RELAX
:
3010 case BFD_RELOC_RISCV_TPREL_HI20
:
3011 case BFD_RELOC_RISCV_TPREL_LO12_I
:
3012 case BFD_RELOC_RISCV_TPREL_LO12_S
:
3013 case BFD_RELOC_RISCV_TPREL_ADD
:
3017 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
3018 case BFD_RELOC_RISCV_TLS_GD_HI20
:
3019 case BFD_RELOC_RISCV_TLS_DTPREL32
:
3020 case BFD_RELOC_RISCV_TLS_DTPREL64
:
3021 if (fixP
->fx_addsy
!= NULL
)
3022 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3024 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3025 _("TLS relocation against a constant"));
3029 /* Use pc-relative relocation for FDE initial location.
3030 The symbol address in .eh_frame may be adjusted in
3031 _bfd_elf_discard_section_eh_frame, and the content of
3032 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
3033 Therefore, we cannot insert a relocation whose addend symbol is
3034 in .eh_frame. Othrewise, the value may be adjusted twice. */
3035 if (fixP
->fx_addsy
&& fixP
->fx_subsy
3036 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
3037 && strcmp (sub_segment
->name
, ".eh_frame") == 0
3038 && S_GET_VALUE (fixP
->fx_subsy
)
3039 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
3041 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
3042 fixP
->fx_subsy
= NULL
;
3049 case BFD_RELOC_RISCV_CFA
:
3050 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
3052 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3053 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
3054 fixP
->fx_next
->fx_subsy
= NULL
;
3055 fixP
->fx_next
->fx_offset
= 0;
3056 fixP
->fx_subsy
= NULL
;
3058 switch (fixP
->fx_r_type
)
3061 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
3062 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
3066 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
3067 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3071 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
3072 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3076 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
3077 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3080 case BFD_RELOC_RISCV_CFA
:
3081 /* Load the byte to get the subtype. */
3082 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
3083 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
3086 case DW_CFA_advance_loc1
:
3087 fixP
->fx_where
= loc
+ 1;
3088 fixP
->fx_next
->fx_where
= loc
+ 1;
3089 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
3090 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3093 case DW_CFA_advance_loc2
:
3095 fixP
->fx_next
->fx_size
= 2;
3096 fixP
->fx_where
= loc
+ 1;
3097 fixP
->fx_next
->fx_where
= loc
+ 1;
3098 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
3099 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3102 case DW_CFA_advance_loc4
:
3104 fixP
->fx_next
->fx_size
= 4;
3105 fixP
->fx_where
= loc
;
3106 fixP
->fx_next
->fx_where
= loc
;
3107 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
3108 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3112 if (subtype
< 0x80 && (subtype
& 0x40))
3114 /* DW_CFA_advance_loc */
3115 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
3116 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
3117 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
3118 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
3121 as_fatal (_("internal: bad CFA value #%d"), subtype
);
3127 /* This case is unreachable. */
3134 /* If we are deleting this reloc entry, we must fill in the
3135 value now. This can happen if we have a .word which is not
3136 resolved when it appears but is later defined. */
3137 if (fixP
->fx_addsy
== NULL
)
3139 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
3140 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3145 case BFD_RELOC_RISCV_JMP
:
3148 /* Fill in a tentative value to improve objdump readability. */
3149 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3150 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3151 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_JTYPE_IMM (delta
), buf
);
3155 case BFD_RELOC_12_PCREL
:
3158 /* Fill in a tentative value to improve objdump readability. */
3159 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3160 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3161 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_BTYPE_IMM (delta
), buf
);
3165 case BFD_RELOC_RISCV_RVC_BRANCH
:
3168 /* Fill in a tentative value to improve objdump readability. */
3169 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3170 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3171 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CBTYPE_IMM (delta
), buf
);
3175 case BFD_RELOC_RISCV_RVC_JUMP
:
3178 /* Fill in a tentative value to improve objdump readability. */
3179 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3180 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3181 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CJTYPE_IMM (delta
), buf
);
3185 case BFD_RELOC_RISCV_CALL
:
3186 case BFD_RELOC_RISCV_CALL_PLT
:
3190 case BFD_RELOC_RISCV_PCREL_HI20
:
3191 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3192 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3193 relaxable
= riscv_opts
.relax
;
3196 case BFD_RELOC_RISCV_ALIGN
:
3200 /* We ignore generic BFD relocations we don't know about. */
3201 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3202 as_fatal (_("internal: bad relocation #%d"), fixP
->fx_r_type
);
3205 if (fixP
->fx_subsy
!= NULL
)
3206 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3207 _("unsupported symbol subtraction"));
3209 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3210 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3212 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3213 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3214 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3215 fixP
->fx_next
->fx_size
= 0;
3219 /* Because the value of .cfi_remember_state may changed after relaxation,
3220 we insert a fix to relocate it again in link-time. */
3223 riscv_pre_output_hook (void)
3225 const frchainS
*frch
;
3228 /* Save the current segment info. */
3230 subsegT subseg
= now_subseg
;
3232 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3233 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3237 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3239 if (frag
->fr_type
== rs_cfa
)
3242 expressionS
*symval
;
3244 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3245 exp
.X_op
= O_subtract
;
3246 exp
.X_add_symbol
= symval
->X_add_symbol
;
3247 exp
.X_add_number
= 0;
3248 exp
.X_op_symbol
= symval
->X_op_symbol
;
3250 /* We must set the segment before creating a frag after all
3251 frag chains have been chained together. */
3252 subseg_set (s
, frch
->frch_subseg
);
3254 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3255 BFD_RELOC_RISCV_CFA
);
3260 /* Restore the original segment info. */
3261 subseg_set (seg
, subseg
);
3264 /* This structure is used to hold a stack of .option values. */
3265 struct riscv_option_stack
3267 struct riscv_option_stack
*next
;
3268 struct riscv_set_options options
;
3271 static struct riscv_option_stack
*riscv_opts_stack
;
3273 /* Handle the .option pseudo-op. */
3276 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3278 char *name
= input_line_pointer
, ch
;
3280 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3281 ++input_line_pointer
;
3282 ch
= *input_line_pointer
;
3283 *input_line_pointer
= '\0';
3285 if (strcmp (name
, "rvc") == 0)
3286 riscv_set_rvc (true);
3287 else if (strcmp (name
, "norvc") == 0)
3288 riscv_set_rvc (false);
3289 else if (strcmp (name
, "pic") == 0)
3290 riscv_opts
.pic
= true;
3291 else if (strcmp (name
, "nopic") == 0)
3292 riscv_opts
.pic
= false;
3293 else if (strcmp (name
, "relax") == 0)
3294 riscv_opts
.relax
= true;
3295 else if (strcmp (name
, "norelax") == 0)
3296 riscv_opts
.relax
= false;
3297 else if (strcmp (name
, "csr-check") == 0)
3298 riscv_opts
.csr_check
= true;
3299 else if (strcmp (name
, "no-csr-check") == 0)
3300 riscv_opts
.csr_check
= false;
3301 else if (strcmp (name
, "push") == 0)
3303 struct riscv_option_stack
*s
;
3305 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3306 s
->next
= riscv_opts_stack
;
3307 s
->options
= riscv_opts
;
3308 riscv_opts_stack
= s
;
3310 else if (strcmp (name
, "pop") == 0)
3312 struct riscv_option_stack
*s
;
3314 s
= riscv_opts_stack
;
3316 as_bad (_(".option pop with no .option push"));
3319 riscv_opts
= s
->options
;
3320 riscv_opts_stack
= s
->next
;
3326 as_warn (_("unrecognized .option directive: %s\n"), name
);
3328 *input_line_pointer
= ch
;
3329 demand_empty_rest_of_line ();
3332 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3333 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3334 use in DWARF debug information. */
3337 s_dtprel (int bytes
)
3344 if (ex
.X_op
!= O_symbol
)
3346 as_bad (_("unsupported use of %s"), (bytes
== 8
3349 ignore_rest_of_line ();
3352 p
= frag_more (bytes
);
3353 md_number_to_chars (p
, 0, bytes
);
3354 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, false,
3356 ? BFD_RELOC_RISCV_TLS_DTPREL64
3357 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3359 demand_empty_rest_of_line ();
3362 /* Handle the .bss pseudo-op. */
3365 s_bss (int ignore ATTRIBUTE_UNUSED
)
3367 subseg_set (bss_section
, 0);
3368 demand_empty_rest_of_line ();
3372 riscv_make_nops (char *buf
, bfd_vma bytes
)
3376 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3377 means we are not within a valid instruction sequence. It is thus safe
3378 to use a zero byte, even though that is not a valid instruction. */
3382 /* Use at most one 2-byte NOP. */
3383 if ((bytes
- i
) % 4 == 2)
3385 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
3389 /* Fill the remainder with 4-byte NOPs. */
3390 for ( ; i
< bytes
; i
+= 4)
3391 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
3394 /* Called from md_do_align. Used to create an alignment frag in a
3395 code section by emitting a worst-case NOP sequence that the linker
3396 will later relax to the correct number of NOPs. We can't compute
3397 the correct alignment now because of other linker relaxations. */
3400 riscv_frag_align_code (int n
)
3402 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3403 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3404 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3408 /* If we are moving to a smaller alignment than the instruction size, then no
3409 alignment is required. */
3410 if (bytes
<= insn_alignment
)
3413 /* When not relaxing, riscv_handle_align handles code alignment. */
3414 if (!riscv_opts
.relax
)
3417 nops
= frag_more (worst_case_bytes
);
3419 ex
.X_op
= O_constant
;
3420 ex
.X_add_number
= worst_case_bytes
;
3422 riscv_make_nops (nops
, worst_case_bytes
);
3424 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3425 &ex
, false, BFD_RELOC_RISCV_ALIGN
);
3430 /* Implement HANDLE_ALIGN. */
3433 riscv_handle_align (fragS
*fragP
)
3435 switch (fragP
->fr_type
)
3438 /* When relaxing, riscv_frag_align_code handles code alignment. */
3439 if (!riscv_opts
.relax
)
3441 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3442 - fragP
->fr_address
- fragP
->fr_fix
);
3443 /* We have 4 byte uncompressed nops. */
3444 bfd_signed_vma size
= 4;
3445 bfd_signed_vma excess
= bytes
% size
;
3446 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3451 /* Insert zeros or compressed nops to get 4 byte alignment. */
3454 riscv_make_nops (p
, excess
);
3455 fragP
->fr_fix
+= excess
;
3459 /* Insert variable number of 4 byte uncompressed nops. */
3460 riscv_make_nops (p
, size
);
3461 fragP
->fr_var
= size
;
3471 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3473 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, false));
3476 /* Translate internal representation of relocation info to BFD target
3480 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3482 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3484 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3485 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3486 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3487 reloc
->addend
= fixp
->fx_addnumber
;
3489 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3490 if (reloc
->howto
== NULL
)
3492 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3493 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3495 /* We don't have R_RISCV_8/16, but for this special case,
3496 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3500 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3501 _("cannot represent %s relocation in object file"),
3502 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3510 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3512 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3514 offsetT old_var
= fragp
->fr_var
;
3515 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, true);
3516 return fragp
->fr_var
- old_var
;
3522 /* Expand far branches to multi-instruction sequences. */
3525 md_convert_frag_branch (fragS
*fragp
)
3533 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3535 exp
.X_op
= O_symbol
;
3536 exp
.X_add_symbol
= fragp
->fr_symbol
;
3537 exp
.X_add_number
= fragp
->fr_offset
;
3539 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3541 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3543 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3547 /* Expand the RVC branch into a RISC-V one. */
3548 insn
= bfd_getl16 (buf
);
3549 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3550 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3552 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3553 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3554 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3555 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3556 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3557 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3560 bfd_putl32 (insn
, buf
);
3564 /* Invert the branch condition. Branch over the jump. */
3565 insn
= bfd_getl16 (buf
);
3566 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3567 insn
|= ENCODE_CBTYPE_IMM (6);
3568 bfd_putl16 (insn
, buf
);
3573 /* Just keep the RVC branch. */
3574 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3575 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3576 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3577 2, &exp
, false, reloc
);
3586 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3589 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3591 /* Invert the branch condition. Branch over the jump. */
3592 insn
= bfd_getl32 (buf
);
3593 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3594 insn
|= ENCODE_BTYPE_IMM (8);
3595 bfd_putl32 (insn
, buf
);
3599 /* Jump to the target. */
3600 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3601 4, &exp
, false, BFD_RELOC_RISCV_JMP
);
3602 bfd_putl32 (MATCH_JAL
, buf
);
3607 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3608 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3609 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3610 4, &exp
, false, reloc
);
3619 fixp
->fx_file
= fragp
->fr_file
;
3620 fixp
->fx_line
= fragp
->fr_line
;
3622 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3623 + fragp
->fr_fix
+ fragp
->fr_var
);
3625 fragp
->fr_fix
+= fragp
->fr_var
;
3628 /* Relax a machine dependent frag. This returns the amount by which
3629 the current size of the frag should change. */
3632 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3635 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3636 md_convert_frag_branch (fragp
);
3640 md_show_usage (FILE *stream
)
3642 fprintf (stream
, _("\
3644 -fpic generate position-independent code\n\
3645 -fno-pic don't generate position-independent code (default)\n\
3646 -march=ISA set the RISC-V architecture\n\
3647 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3648 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3649 -mabi=ABI set the RISC-V ABI\n\
3650 -mrelax enable relax (default)\n\
3651 -mno-relax disable relax\n\
3652 -march-attr generate RISC-V arch attribute\n\
3653 -mno-arch-attr don't generate RISC-V arch attribute\n\
3657 /* Standard calling conventions leave the CFA at SP on entry. */
3660 riscv_cfi_frame_initial_instructions (void)
3662 cfi_add_CFA_def_cfa_register (X_SP
);
3666 tc_riscv_regname_to_dw2regnum (char *regname
)
3670 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3673 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3676 /* CSRs are numbered 4096 -> 8191. */
3677 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3680 as_bad (_("unknown register `%s'"), regname
);
3685 riscv_elf_final_processing (void)
3687 riscv_set_abi_by_arch ();
3688 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3691 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3692 since these directives break relaxation when used with symbol deltas. */
3695 s_riscv_leb128 (int sign
)
3698 char *save_in
= input_line_pointer
;
3701 if (exp
.X_op
!= O_constant
)
3702 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3703 demand_empty_rest_of_line ();
3705 input_line_pointer
= save_in
;
3706 return s_leb128 (sign
);
3709 /* Parse the .insn directive. */
3712 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3714 char *str
= input_line_pointer
;
3715 struct riscv_cl_insn insn
;
3716 expressionS imm_expr
;
3717 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3720 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3721 ++input_line_pointer
;
3723 save_c
= *input_line_pointer
;
3724 *input_line_pointer
= '\0';
3726 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3727 &imm_reloc
, insn_type_hash
);
3731 as_bad ("%s `%s'", error
, str
);
3735 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3736 append_insn (&insn
, &imm_expr
, imm_reloc
);
3739 *input_line_pointer
= save_c
;
3740 demand_empty_rest_of_line ();
3743 /* Update architecture and privileged elf attributes. If we don't set
3744 them, then try to output the default ones. */
3747 riscv_write_out_attrs (void)
3749 const char *arch_str
, *priv_str
, *p
;
3750 /* versions[0]: major version.
3751 versions[1]: minor version.
3752 versions[2]: revision version. */
3753 unsigned versions
[3] = {0}, number
= 0;
3756 /* Re-write architecture elf attribute. */
3757 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3758 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3759 xfree ((void *) arch_str
);
3761 /* For the file without any instruction, we don't set the default_priv_spec
3762 according to the privileged elf attributes since the md_assemble isn't
3765 && !riscv_set_default_priv_spec (NULL
))
3768 /* If we already have set privileged elf attributes, then no need to do
3769 anything. Otherwise, don't generate or update them when no CSR and
3770 privileged instructions are used. */
3771 if (!explicit_priv_attr
)
3774 RISCV_GET_PRIV_SPEC_NAME (priv_str
, default_priv_spec
);
3776 for (i
= 0; *p
; ++p
)
3778 if (*p
== '.' && i
< 3)
3780 versions
[i
++] = number
;
3783 else if (ISDIGIT (*p
))
3784 number
= (number
* 10) + (*p
- '0');
3787 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str
);
3791 versions
[i
] = number
;
3793 /* Re-write privileged elf attributes. */
3794 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3795 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3796 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3799 /* Add the default contents for the .riscv.attributes section. */
3802 riscv_set_public_attributes (void)
3804 if (riscv_opts
.arch_attr
|| explicit_attr
)
3805 riscv_write_out_attrs ();
3808 /* Called after all assembly has been done. */
3813 riscv_set_public_attributes ();
3816 /* Given a symbolic attribute NAME, return the proper integer value.
3817 Returns -1 if the attribute is not known. */
3820 riscv_convert_symbolic_attribute (const char *name
)
3829 /* When you modify this table you should
3830 also modify the list in doc/c-riscv.texi. */
3831 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3835 T(priv_spec_revision
),
3836 T(unaligned_access
),
3845 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3846 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3847 return attribute_table
[i
].tag
;
3852 /* Parse a .attribute directive. */
3855 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3857 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3859 obj_attribute
*attr
;
3861 explicit_attr
= true;
3864 case Tag_RISCV_arch
:
3866 attr
= elf_known_obj_attributes_proc (stdoutput
);
3867 if (!start_assemble
)
3868 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3870 as_fatal (_("architecture elf attributes must set before "
3871 "any instructions"));
3873 if (old_xlen
!= xlen
)
3875 /* We must re-init bfd again if xlen is changed. */
3876 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3877 bfd_find_target (riscv_target_format (), stdoutput
);
3879 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3880 as_warn (_("could not set architecture and machine"));
3884 case Tag_RISCV_priv_spec
:
3885 case Tag_RISCV_priv_spec_minor
:
3886 case Tag_RISCV_priv_spec_revision
:
3888 as_fatal (_("privileged elf attributes must set before "
3889 "any instructions"));
3897 /* RISC-V pseudo-ops table. */
3898 static const pseudo_typeS riscv_pseudo_table
[] =
3900 {"option", s_riscv_option
, 0},
3904 {"dtprelword", s_dtprel
, 4},
3905 {"dtpreldword", s_dtprel
, 8},
3907 {"uleb128", s_riscv_leb128
, 0},
3908 {"sleb128", s_riscv_leb128
, 1},
3909 {"insn", s_riscv_insn
, 0},
3910 {"attribute", s_riscv_attribute
, 0},
3916 riscv_pop_insert (void)
3918 extern void pop_insert (const pseudo_typeS
*);
3920 pop_insert (riscv_pseudo_table
);